diff --git a/doc/.~lock.parts_list.ods# b/doc/.~lock.parts_list.ods# index a971fb88..45483854 100644 --- a/doc/.~lock.parts_list.ods# +++ b/doc/.~lock.parts_list.ods# @@ -1 +1 @@ -,penguin,penguin-pc,16.03.2020 15:16,file:///home/penguin/.config/libreoffice/4; \ No newline at end of file +,penguin,penguin-pc,19.03.2020 17:46,file:///home/penguin/.config/libreoffice/4; \ No newline at end of file diff --git a/doc/parts_list.ods b/doc/parts_list.ods index 3f3877f4..571cfcf0 100644 Binary files a/doc/parts_list.ods and b/doc/parts_list.ods differ diff --git a/electrical/same54_dev_board/_autosave-BRAIN.sch b/electrical/same54_dev_board/_autosave-BRAIN.sch new file mode 100644 index 00000000..3c64584f --- /dev/null +++ b/electrical/same54_dev_board/_autosave-BRAIN.sch @@ -0,0 +1,60 @@ +EESchema Schematic File Version 4 +EELAYER 30 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 4 4 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L p_ATSAME54P20A-AU:p_ATSAME54P20A-AU U? +U 1 1 5E82A2F6 +P 1500 2150 +F 0 "U?" H 1583 3315 50 0000 C CNN +F 1 "p_ATSAME54P20A-AU" H 1583 3224 50 0000 C CNN +F 2 "" H 300 3400 50 0001 C CNN +F 3 "" H 300 3400 50 0001 C CNN + 1 1500 2150 + 1 0 0 -1 +$EndComp +$Comp +L p_ATSAME54P20A-AU:p_ATSAME54P20A-AU U? +U 2 1 5E82C3BA +P 3450 2550 +F 0 "U?" H 3558 3615 50 0000 C CNN +F 1 "p_ATSAME54P20A-AU" H 3558 3524 50 0000 C CNN +F 2 "" H 2250 3800 50 0001 C CNN +F 3 "" H 2250 3800 50 0001 C CNN + 2 3450 2550 + 1 0 0 -1 +$EndComp +$Comp +L p_ATSAME54P20A-AU:p_ATSAME54P20A-AU U? +U 3 1 5E82DE73 +P 5950 2300 +F 0 "U?" H 6058 3315 50 0000 C CNN +F 1 "p_ATSAME54P20A-AU" H 6058 3224 50 0000 C CNN +F 2 "" H 4750 3550 50 0001 C CNN +F 3 "" H 4750 3550 50 0001 C CNN + 3 5950 2300 + 1 0 0 -1 +$EndComp +$Comp +L p_ATSAME54P20A-AU:p_ATSAME54P20A-AU U? +U 4 1 5E8352A8 +P 7450 2000 +F 0 "U?" H 7558 3065 50 0000 C CNN +F 1 "p_ATSAME54P20A-AU" H 7558 2974 50 0000 C CNN +F 2 "" H 6250 3250 50 0001 C CNN +F 3 "" H 6250 3250 50 0001 C CNN + 4 7450 2000 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/electrical/same54_dev_board/_autosave-Power.sch b/electrical/same54_dev_board/_autosave-Power.sch index 0bcf2e8f..95b6b9ee 100644 --- a/electrical/same54_dev_board/_autosave-Power.sch +++ b/electrical/same54_dev_board/_autosave-Power.sch @@ -3,7 +3,7 @@ EELAYER 30 0 EELAYER END $Descr A4 11693 8268 encoding utf-8 -Sheet 2 2 +Sheet 2 4 Title "" Date "" Rev "" @@ -15,13 +15,13 @@ Comment4 "" $EndDescr $Comp L p_ATSAME54P20A-AU:p_ATSAME54P20A-AU U? -U 5 1 5E7A11E1 -P 2750 2300 -F 0 "U?" H 2750 3215 50 0000 C CNN -F 1 "p_ATSAME54P20A-AU" H 2750 3124 50 0000 C CNN -F 2 "" H 1550 3550 50 0001 C CNN -F 3 "" H 1550 3550 50 0001 C CNN - 5 2750 2300 +U 5 1 5E84F3B3 +P 4800 3300 +F 0 "U?" H 4800 4215 50 0000 C CNN +F 1 "p_ATSAME54P20A-AU" H 4800 4124 50 0000 C CNN +F 2 "" H 3600 4550 50 0001 C CNN +F 3 "" H 3600 4550 50 0001 C CNN + 5 4800 3300 1 0 0 -1 $EndComp $EndSCHEMATC diff --git a/electrical/same54_dev_board/_autosave-SCREEN_INTF.sch b/electrical/same54_dev_board/_autosave-SCREEN_INTF.sch new file mode 100644 index 00000000..c77bab05 --- /dev/null +++ b/electrical/same54_dev_board/_autosave-SCREEN_INTF.sch @@ -0,0 +1,360 @@ +EESchema Schematic File Version 4 +EELAYER 30 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 5 5 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L Conn_02x20_LCD_INTF:Conn_02x20_Odd_Even_LCD_INTF J? +U 1 1 5E858ED6 +P 4500 2350 +F 0 "J?" H 4500 3475 50 0000 C CNN +F 1 "Conn_02x20_Odd_Even_LCD_INTF" H 4500 3384 50 0000 C CNN +F 2 "" H 4100 2350 50 0001 C CNN +F 3 "file:///home/penguin/Downloads/SSD1963_v1.6.pdf" H 4100 2350 50 0001 C CNN + 1 4500 2350 + 1 0 0 -1 +$EndComp +Text GLabel 900 650 0 50 Input ~ 0 +g_3v3 +Text GLabel 850 850 0 50 Input ~ 0 +g_5v +Wire Wire Line + 900 650 1150 650 +Text Label 1150 650 0 50 ~ 0 +3v3 +Wire Wire Line + 850 850 1150 850 +Text Label 1150 850 0 50 ~ 0 +5v +Wire Wire Line + 2500 1750 2550 1750 +Text Label 2800 1200 0 50 ~ 0 +3v3 +$Comp +L Device:R_Small R? +U 1 1 5E889CF7 +P 850 1950 +F 0 "R?" V 654 1950 50 0000 C CNN +F 1 "39k" V 745 1950 50 0000 C CNN +F 2 "" H 850 1950 50 0001 C CNN +F 3 "~" H 850 1950 50 0001 C CNN + 1 850 1950 + 0 1 1 0 +$EndComp +Wire Wire Line + 1100 1950 950 1950 +Wire Wire Line + 750 1950 750 2150 +$Comp +L power:GND #PWR? +U 1 1 5E88D5B3 +P 750 2150 +F 0 "#PWR?" H 750 1900 50 0001 C CNN +F 1 "GND" H 755 1977 50 0000 C CNN +F 2 "" H 750 2150 50 0001 C CNN +F 3 "" H 750 2150 50 0001 C CNN + 1 750 2150 + 1 0 0 -1 +$EndComp +Entry Wire Line + 900 2350 1000 2450 +Wire Wire Line + 1000 2450 1100 2450 +Wire Wire Line + 2500 3950 2500 4050 +$Comp +L power:GND #PWR? +U 1 1 5E89C68E +P 2500 4100 +F 0 "#PWR?" H 2500 3850 50 0001 C CNN +F 1 "GND" H 2505 3927 50 0000 C CNN +F 2 "" H 2500 4100 50 0001 C CNN +F 3 "" H 2500 4100 50 0001 C CNN + 1 2500 4100 + 1 0 0 -1 +$EndComp +Entry Wire Line + 900 2450 1000 2550 +Entry Wire Line + 900 2550 1000 2650 +Entry Wire Line + 900 2650 1000 2750 +Entry Wire Line + 900 2750 1000 2850 +Entry Wire Line + 900 2850 1000 2950 +Entry Wire Line + 900 2950 1000 3050 +Entry Wire Line + 900 3050 1000 3150 +Entry Wire Line + 900 3150 1000 3250 +Entry Wire Line + 900 3250 1000 3350 +Entry Wire Line + 900 3350 1000 3450 +Entry Wire Line + 900 3450 1000 3550 +Entry Wire Line + 900 3550 1000 3650 +Entry Wire Line + 900 3650 1000 3750 +Entry Wire Line + 2800 2350 2700 2450 +Entry Wire Line + 2800 2450 2700 2550 +Entry Wire Line + 2800 2550 2700 2650 +Entry Wire Line + 2800 2650 2700 2750 +Entry Wire Line + 2800 2750 2700 2850 +Entry Wire Line + 2800 2850 2700 2950 +Entry Wire Line + 2800 2950 2700 3050 +Entry Wire Line + 2800 3050 2700 3150 +Entry Wire Line + 2800 3150 2700 3250 +Entry Wire Line + 2800 3250 2700 3350 +Wire Wire Line + 1000 2550 1100 2550 +Wire Wire Line + 1000 2650 1100 2650 +Wire Wire Line + 1000 2750 1100 2750 +Wire Wire Line + 1000 2850 1100 2850 +Wire Wire Line + 1000 2950 1100 2950 +Wire Wire Line + 1000 3050 1100 3050 +Wire Wire Line + 1000 3150 1100 3150 +Wire Wire Line + 1000 3250 1100 3250 +Wire Wire Line + 1000 3350 1100 3350 +Wire Wire Line + 1000 3450 1100 3450 +Wire Wire Line + 1000 3550 1100 3550 +Wire Wire Line + 1000 3650 1100 3650 +Wire Wire Line + 1000 3750 1100 3750 +Text Label 1000 2450 0 50 ~ 0 +D0 +Text Label 1000 2550 0 50 ~ 0 +D1 +Text Label 1000 2650 0 50 ~ 0 +D2 +Text Label 1000 2750 0 50 ~ 0 +D3 +Text Label 1000 2850 0 50 ~ 0 +D4 +Text Label 1000 2950 0 50 ~ 0 +D5 +Text Label 1000 3050 0 50 ~ 0 +D6 +Text Label 1000 3150 0 50 ~ 0 +D7 +Text Label 1000 3250 0 50 ~ 0 +D8 +Text Label 1000 3350 0 50 ~ 0 +D9 +Text Label 1000 3450 0 50 ~ 0 +D10 +Text Label 1000 3550 0 50 ~ 0 +D11 +Text Label 1000 3650 0 50 ~ 0 +D12 +Text Label 1000 3750 0 50 ~ 0 +D13 +Text Label 2500 2450 0 50 ~ 0 +D14 +Text Label 2500 2550 0 50 ~ 0 +D15 +Text Label 2500 2650 0 50 ~ 0 +D16 +Text Label 2500 2750 0 50 ~ 0 +D17 +Text Label 2500 2850 0 50 ~ 0 +D18 +Text Label 2500 2950 0 50 ~ 0 +D19 +Text Label 2500 3050 0 50 ~ 0 +D20 +Text Label 2500 3150 0 50 ~ 0 +D21 +Text Label 2500 3250 0 50 ~ 0 +D22 +Text Label 2500 3350 0 50 ~ 0 +D23 +Text Notes 5600 1300 0 50 ~ 0 +LCD INTF -- LCD Interface Section\n - D[0-23] represent data pins on the 8080 (parallel) bus\n - The MAX7301 is an IO expander acting as the data bus middleman\n between the brain and the ssd1963\n - The lcd control pins will still be controlled directly from the brain to alleviate timing issues and \n because its just going to be easier to debug\n - The MAX7301 is going to be run at something around 20MHz so we should be ok with timing +Wire Notes Line + 5550 800 9600 800 +Wire Notes Line + 9600 800 9600 2250 +Wire Notes Line + 9600 2250 5550 2250 +Wire Notes Line + 5550 2250 5550 800 +Entry Wire Line + 3650 1950 3750 2050 +Entry Wire Line + 3650 2050 3750 2150 +Entry Wire Line + 3650 2150 3750 2250 +Entry Wire Line + 3650 2250 3750 2350 +Entry Wire Line + 3650 2350 3750 2450 +Entry Wire Line + 3650 2450 3750 2550 +Entry Wire Line + 3650 2550 3750 2650 +Entry Wire Line + 3650 2650 3750 2750 +Entry Wire Line + 3650 2750 3750 2850 +Entry Wire Line + 3650 2850 3750 2950 +Entry Wire Line + 3650 2950 3750 3050 +Entry Wire Line + 3650 3050 3750 3150 +Wire Bus Line + 3650 3900 5500 3900 +Wire Bus Line + 5500 3900 5500 1450 +Wire Wire Line + 3750 2050 3900 2050 +Wire Wire Line + 3750 2150 3900 2150 +Wire Wire Line + 3750 2250 3900 2250 +Wire Wire Line + 3750 2350 3900 2350 +Wire Wire Line + 3750 2450 3900 2450 +Wire Wire Line + 3750 2550 3900 2550 +Wire Wire Line + 3750 2650 3900 2650 +Wire Wire Line + 3750 2750 3900 2750 +Wire Wire Line + 3750 2850 3900 2850 +Wire Wire Line + 3750 2950 3900 2950 +Wire Wire Line + 3750 3050 3900 3050 +Wire Wire Line + 3750 3150 3900 3150 +Wire Wire Line + 2500 2450 2700 2450 +Wire Wire Line + 2500 2550 2700 2550 +Wire Wire Line + 2500 2650 2700 2650 +Wire Wire Line + 2500 2750 2700 2750 +Wire Wire Line + 2500 2850 2700 2850 +Wire Wire Line + 2500 2950 2700 2950 +Wire Wire Line + 2500 3050 2700 3050 +Wire Wire Line + 2500 3150 2700 3150 +Wire Wire Line + 2500 3250 2700 3250 +Wire Wire Line + 2500 3350 2700 3350 +Wire Bus Line + 900 4500 2800 4500 +NoConn ~ 2500 3450 +NoConn ~ 2500 3550 +NoConn ~ 2500 3650 +NoConn ~ 2500 3750 +Wire Bus Line + 3250 1800 3650 1800 +Entry Bus Bus + 3150 1900 3250 1800 +Wire Bus Line + 3150 1900 3150 2300 +Wire Bus Line + 3150 2300 2800 2300 +Text Notes 2100 1100 0 50 ~ 0 +this looks atrocious but idk how to make busses vertical ,,, +$Comp +L MAX7301AAX_:MAX7301AAX+ U? +U 1 1 5E86D6D7 +P 1800 2950 +F 0 "U?" H 1800 4420 50 0000 C CNN +F 1 "MAX7301AAX+" H 1800 4329 50 0000 C CNN +F 2 "SOP80P1030X264-36N" H 1800 2950 50 0001 L BNN +F 3 "https://datasheets.maximintegrated.com/en/ds/MAX7301.pdf" H 1800 2950 50 0001 L BNN +F 4 "None" H 1800 2950 50 0001 L BNN "Field4" +F 5 "Interface IC - I/O extensions Maxim Integrated MAX7301AAX+ SPI 26 MHz SSOP 36" H 1800 2950 50 0001 L BNN "Field5" +F 6 "SSOP-36 Maxim" H 1800 2950 50 0001 L BNN "Field6" +F 7 "Unavailable" H 1800 2950 50 0001 L BNN "Field7" +F 8 "MAX7301AAX+" H 1800 2950 50 0001 L BNN "Field8" + 1 1800 2950 + 1 0 0 -1 +$EndComp +Connection ~ 2500 4050 +Wire Wire Line + 2500 4050 2500 4100 +$Comp +L Device:C_Small C? +U 1 1 5E988E9B +P 2800 1450 +F 0 "C?" H 2892 1496 50 0000 L CNN +F 1 "C_Small" H 2892 1405 50 0000 L CNN +F 2 "" H 2800 1450 50 0001 C CNN +F 3 "~" H 2800 1450 50 0001 C CNN + 1 2800 1450 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2800 1200 2800 1350 +Wire Wire Line + 2800 1350 2550 1350 +Connection ~ 2800 1350 +Wire Wire Line + 2800 1550 2800 1650 +$Comp +L power:GND #PWR? +U 1 1 5E98EDCE +P 2800 1650 +F 0 "#PWR?" H 2800 1400 50 0001 C CNN +F 1 "GND" H 2805 1477 50 0000 C CNN +F 2 "" H 2800 1650 50 0001 C CNN +F 3 "" H 2800 1650 50 0001 C CNN + 1 2800 1650 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2550 1350 2550 1750 +Wire Bus Line + 2800 2300 2800 4500 +Wire Bus Line + 900 2350 900 4500 +Wire Bus Line + 3650 1800 3650 3900 +$EndSCHEMATC diff --git a/electrical/same54_dev_board/_autosave-USB_INTF.sch b/electrical/same54_dev_board/_autosave-USB_INTF.sch new file mode 100644 index 00000000..cbaf7a16 --- /dev/null +++ b/electrical/same54_dev_board/_autosave-USB_INTF.sch @@ -0,0 +1,47 @@ +EESchema Schematic File Version 4 +EELAYER 30 0 +EELAYER END +$Descr A4 11693 8268 +encoding utf-8 +Sheet 3 4 +Title "" +Date "" +Rev "" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Comp +L dk_Interface-Controllers:FT232RQ-REEL U? +U 1 1 5E84744C +P 2600 1100 +F 0 "U?" H 2400 1403 60 0000 C CNN +F 1 "FT232RQ-REEL" H 2400 1297 60 0000 C CNN +F 2 "digikey-footprints:QFN-32-1EP_5x5mm" H 2800 1300 60 0001 L CNN +F 3 "https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232R.pdf" H 2800 1400 60 0001 L CNN +F 4 "768-1008-1-ND" H 2800 1500 60 0001 L CNN "Digi-Key_PN" +F 5 "FT232RQ-REEL" H 2800 1600 60 0001 L CNN "MPN" +F 6 "Integrated Circuits (ICs)" H 2800 1700 60 0001 L CNN "Category" +F 7 "Interface - Controllers" H 2800 1800 60 0001 L CNN "Family" +F 8 "https://www.ftdichip.com/Support/Documents/DataSheets/ICs/DS_FT232R.pdf" H 2800 1900 60 0001 L CNN "DK_Datasheet_Link" +F 9 "/product-detail/en/ftdi-future-technology-devices-international-ltd/FT232RQ-REEL/768-1008-1-ND/1836403" H 2800 2000 60 0001 L CNN "DK_Detail_Page" +F 10 "IC USB FS SERIAL UART 32-QFN" H 2800 2100 60 0001 L CNN "Description" +F 11 "FTDI, Future Technology Devices International Ltd" H 2800 2200 60 0001 L CNN "Manufacturer" +F 12 "Active" H 2800 2300 60 0001 L CNN "Status" + 1 2600 1100 + 1 0 0 -1 +$EndComp +$Comp +L Connector:USB_B_Micro J? +U 1 1 5E8480AD +P 1300 1400 +F 0 "J?" H 1357 1867 50 0000 C CNN +F 1 "USB_B_Micro" H 1357 1776 50 0000 C CNN +F 2 "" H 1450 1350 50 0001 C CNN +F 3 "~" H 1450 1350 50 0001 C CNN + 1 1300 1400 + 1 0 0 -1 +$EndComp +$EndSCHEMATC diff --git a/electrical/same54_dev_board/_autosave-same54_dev_board.sch b/electrical/same54_dev_board/_autosave-same54_dev_board.sch new file mode 100644 index 00000000..8e2615a0 --- /dev/null +++ b/electrical/same54_dev_board/_autosave-same54_dev_board.sch @@ -0,0 +1,128 @@ +EESchema Schematic File Version 4 +EELAYER 30 0 +EELAYER END +$Descr A 11000 8500 +encoding utf-8 +Sheet 1 5 +Title "Project Oracle" +Date "2020-03-16" +Rev "v0.1" +Comp "" +Comment1 "" +Comment2 "" +Comment3 "" +Comment4 "" +$EndDescr +$Sheet +S 5300 850 3000 2000 +U 5E7872D3 +F0 "s_Power" 50 +F1 "Power.sch" 50 +$EndSheet +$Sheet +S 700 2450 3750 2550 +U 5E7C0F59 +F0 "s_USB_INTF.sch" 50 +F1 "USB_INTF.sch" 50 +$EndSheet +$Sheet +S 750 800 1750 1300 +U 5E805E4F +F0 "s_BRAIN" 50 +F1 "BRAIN.sch" 50 +$EndSheet +Text Notes 800 1000 0 50 ~ 0 +Brain -- ATSAME54P20A will controll peripherals, including an IO extender which,\n will handler the control of the screen (mikroe board with SSD1963) +Text GLabel 900 6250 0 50 Input ~ 0 +g_3v3 +Text GLabel 1800 6250 0 50 Input ~ 0 +g_5v +$Sheet +S 5250 3550 3100 2000 +U 5E8589A7 +F0 "g_SCREEN_INTF" 50 +F1 "SCREEN_INTF.sch" 50 +$EndSheet +Wire Wire Line + 900 6250 950 6250 +$Comp +L power:+3V3 #PWR? +U 1 1 5E97BC15 +P 1200 6250 +F 0 "#PWR?" H 1200 6100 50 0001 C CNN +F 1 "+3V3" H 1215 6423 50 0000 C CNN +F 2 "" H 1200 6250 50 0001 C CNN +F 3 "" H 1200 6250 50 0001 C CNN + 1 1200 6250 + 1 0 0 -1 +$EndComp +$Comp +L power:+5V #PWR? +U 1 1 5E97C21D +P 2150 6250 +F 0 "#PWR?" H 2150 6100 50 0001 C CNN +F 1 "+5V" H 2165 6423 50 0000 C CNN +F 2 "" H 2150 6250 50 0001 C CNN +F 3 "" H 2150 6250 50 0001 C CNN + 1 2150 6250 + 1 0 0 -1 +$EndComp +$Comp +L power:PWR_FLAG #FLG? +U 1 1 5E97C674 +P 950 5850 +F 0 "#FLG?" H 950 5925 50 0001 C CNN +F 1 "PWR_FLAG" H 950 6023 50 0000 C CNN +F 2 "" H 950 5850 50 0001 C CNN +F 3 "~" H 950 5850 50 0001 C CNN + 1 950 5850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 950 6250 950 5850 +Connection ~ 950 6250 +Wire Wire Line + 950 6250 1200 6250 +$Comp +L power:GND #PWR? +U 1 1 5E97DBEE +P 2600 6250 +F 0 "#PWR?" H 2600 6000 50 0001 C CNN +F 1 "GND" H 2605 6077 50 0000 C CNN +F 2 "" H 2600 6250 50 0001 C CNN +F 3 "" H 2600 6250 50 0001 C CNN + 1 2600 6250 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1800 6250 1900 6250 +$Comp +L power:PWR_FLAG #FLG? +U 1 1 5E97F87F +P 1900 5850 +F 0 "#FLG?" H 1900 5925 50 0001 C CNN +F 1 "PWR_FLAG" H 1900 6023 50 0000 C CNN +F 2 "" H 1900 5850 50 0001 C CNN +F 3 "~" H 1900 5850 50 0001 C CNN + 1 1900 5850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 1900 6250 1900 5850 +Connection ~ 1900 6250 +Wire Wire Line + 1900 6250 2150 6250 +$Comp +L power:PWR_FLAG #FLG? +U 1 1 5E980A5B +P 2600 5850 +F 0 "#FLG?" H 2600 5925 50 0001 C CNN +F 1 "PWR_FLAG" H 2600 6023 50 0000 C CNN +F 2 "" H 2600 5850 50 0001 C CNN +F 3 "~" H 2600 5850 50 0001 C CNN + 1 2600 5850 + 1 0 0 -1 +$EndComp +Wire Wire Line + 2600 6250 2600 5850 +$EndSCHEMATC diff --git a/electrical/same54_dev_board/fp-info-cache b/electrical/same54_dev_board/fp-info-cache index a3235f93..f2b3535e 100644 --- a/electrical/same54_dev_board/fp-info-cache +++ b/electrical/same54_dev_board/fp-info-cache @@ -1,4 +1,4 @@ -17823362727053047 +17824947138230346 Battery BatteryHolder_Bulgin_BX0036_1xC Bulgin Battery Holder, BX0036, Battery Type C (https://www.bulgin.com/products/pub/media/bulgin/data/Battery_holders.pdf) @@ -78756,3 +78756,10 @@ test106 0 0 0 +proj_modules +SOP80P1030X264-36N + + +0 +36 +36 diff --git a/electrical/same54_dev_board/libraries/MAX7301AAX_.dcm b/electrical/same54_dev_board/libraries/MAX7301AAX_.dcm new file mode 100644 index 00000000..5f3ed79b --- /dev/null +++ b/electrical/same54_dev_board/libraries/MAX7301AAX_.dcm @@ -0,0 +1,3 @@ +EESchema-DOCLIB Version 2.0 +# +#End Doc Library diff --git a/electrical/same54_dev_board/libraries/MAX7301AAX_.lib b/electrical/same54_dev_board/libraries/MAX7301AAX_.lib index b168697a..7889ab1d 100644 --- a/electrical/same54_dev_board/libraries/MAX7301AAX_.lib +++ b/electrical/same54_dev_board/libraries/MAX7301AAX_.lib @@ -1,7 +1,5 @@ -EESchema-LIBRARY Version 2.3 +EESchema-LIBRARY Version 2.4 #encoding utf-8 -#(c) SnapEDA 2016 (snapeda.com) -#This work is licensed under a Creative Commons Attribution-ShareAlike 4.0 International License (CC BY-SA) with Design Exception 1.0 # # MAX7301AAX+ # @@ -16,47 +14,47 @@ F6 "SSOP-36 Maxim" 0 0 50 H I L BNN F7 "Unavailable" 0 0 50 H I L BNN F8 "MAX7301AAX+" 0 0 50 H I L BNN DRAW +P 2 0 0 16 -500 -1300 -500 1300 N P 2 0 0 16 -500 1300 500 1300 N -P 2 0 0 16 500 1300 500 -1300 N P 2 0 0 16 500 -1300 -500 -1300 N -P 2 0 0 16 -500 -1300 -500 1300 N -X CS 35 700 1000 200 L 40 40 0 0 I -X DIN 34 700 800 200 L 40 40 0 0 I -X ISET 1 -700 1000 200 R 40 40 0 0 I +P 2 0 0 16 500 1300 500 -1300 N +X ISET 1 -700 1000 200 R 40 40 0 0 I +X P9 10 -700 0 200 R 40 40 0 0 B +X P10 11 -700 -100 200 R 40 40 0 0 B +X P11 12 -700 -200 200 R 40 40 0 0 B +X P12 13 -700 -300 200 R 40 40 0 0 B +X P13 14 -700 -400 200 R 40 40 0 0 B +X P14 15 -700 -500 200 R 40 40 0 0 B +X P15 16 -700 -600 200 R 40 40 0 0 B +X P16 17 -700 -700 200 R 40 40 0 0 B +X P17 18 -700 -800 200 R 40 40 0 0 B +X P18 19 700 500 200 L 40 40 0 0 B +X GND 2 700 -1100 200 L 40 40 0 0 W +X P19 20 700 400 200 L 40 40 0 0 B +X P20 21 700 300 200 L 40 40 0 0 B +X P21 22 700 200 200 L 40 40 0 0 B +X P22 23 700 100 200 L 40 40 0 0 B +X P23 24 700 0 200 L 40 40 0 0 B +X P24 25 700 -100 200 L 40 40 0 0 B +X P25 26 700 -200 200 L 40 40 0 0 B +X P26 27 700 -300 200 L 40 40 0 0 B +X P27 28 700 -400 200 L 40 40 0 0 B +X P28 29 700 -500 200 L 40 40 0 0 B +X GND 3 700 -1000 200 L 40 40 0 0 W +X P29 30 700 -600 200 L 40 40 0 0 B +X P30 31 700 -700 200 L 40 40 0 0 B +X P31 32 700 -800 200 L 40 40 0 0 B X SCLK 33 700 900 200 L 40 40 0 0 I C -X P4 5 -700 500 200 R 40 40 0 0 B -X P5 6 -700 400 200 R 40 40 0 0 B -X P6 7 -700 300 200 R 40 40 0 0 B -X P7 8 -700 200 200 R 40 40 0 0 B -X P8 9 -700 100 200 R 40 40 0 0 B -X P9 10 -700 0 200 R 40 40 0 0 B -X P10 11 -700 -100 200 R 40 40 0 0 B -X P11 12 -700 -200 200 R 40 40 0 0 B -X P12 13 -700 -300 200 R 40 40 0 0 B -X P13 14 -700 -400 200 R 40 40 0 0 B -X P14 15 -700 -500 200 R 40 40 0 0 B -X P15 16 -700 -600 200 R 40 40 0 0 B -X P16 17 -700 -700 200 R 40 40 0 0 B -X P17 18 -700 -800 200 R 40 40 0 0 B -X V+ 36 700 1200 200 L 40 40 0 0 W -X DOUT 4 700 700 200 L 40 40 0 0 O -X P18 19 700 500 200 L 40 40 0 0 B -X P19 20 700 400 200 L 40 40 0 0 B -X P20 21 700 300 200 L 40 40 0 0 B -X P21 22 700 200 200 L 40 40 0 0 B -X P22 23 700 100 200 L 40 40 0 0 B -X P23 24 700 0 200 L 40 40 0 0 B -X P24 25 700 -100 200 L 40 40 0 0 B -X P25 26 700 -200 200 L 40 40 0 0 B -X P26 27 700 -300 200 L 40 40 0 0 B -X P27 28 700 -400 200 L 40 40 0 0 B -X P28 29 700 -500 200 L 40 40 0 0 B -X P29 30 700 -600 200 L 40 40 0 0 B -X P30 31 700 -700 200 L 40 40 0 0 B -X P31 32 700 -800 200 L 40 40 0 0 B -X GND 2 700 -1000 200 L 40 40 0 0 W -X GND 3 700 -1000 200 L 40 40 0 0 W +X DIN 34 700 800 200 L 40 40 0 0 I +X CS 35 700 1000 200 L 40 40 0 0 I +X V+ 36 700 1200 200 L 40 40 0 0 W +X DOUT 4 700 700 200 L 40 40 0 0 O +X P4 5 -700 500 200 R 40 40 0 0 B +X P5 6 -700 400 200 R 40 40 0 0 B +X P6 7 -700 300 200 R 40 40 0 0 B +X P7 8 -700 200 200 R 40 40 0 0 B +X P8 9 -700 100 200 R 40 40 0 0 B ENDDRAW ENDDEF # -# End Library \ No newline at end of file +#End Library diff --git a/electrical/same54_dev_board/same54_dev_board-cache.lib b/electrical/same54_dev_board/same54_dev_board-cache.lib index 1c1c69fa..cd059420 100644 --- a/electrical/same54_dev_board/same54_dev_board-cache.lib +++ b/electrical/same54_dev_board/same54_dev_board-cache.lib @@ -96,6 +96,62 @@ X ~TFT_CS 9 -600 500 150 R 50 50 1 1 P ENDDRAW ENDDEF # +# MAX7301AAX__MAX7301AAX+ +# +DEF MAX7301AAX__MAX7301AAX+ U 0 40 Y Y 1 L N +F0 "U" -500 1339 50 H V L BNN +F1 "MAX7301AAX__MAX7301AAX+" -500 -1457 50 H V L BNN +F2 "SOP80P1030X264-36N" 0 0 50 H I L BNN +F3 "Maxim Integrated" 0 0 50 H I L BNN +F4 "None" 0 0 50 H I L BNN +F5 "Interface IC - I/O extensions Maxim Integrated MAX7301AAX+ SPI 26 MHz SSOP 36" 0 0 50 H I L BNN +F6 "SSOP-36 Maxim" 0 0 50 H I L BNN +F7 "Unavailable" 0 0 50 H I L BNN +F8 "MAX7301AAX+" 0 0 50 H I L BNN +DRAW +P 2 0 0 16 -500 -1300 -500 1300 N +P 2 0 0 16 -500 1300 500 1300 N +P 2 0 0 16 500 -1300 -500 -1300 N +P 2 0 0 16 500 1300 500 -1300 N +X ISET 1 -700 1000 200 R 40 40 0 0 I +X P9 10 -700 0 200 R 40 40 0 0 B +X P10 11 -700 -100 200 R 40 40 0 0 B +X P11 12 -700 -200 200 R 40 40 0 0 B +X P12 13 -700 -300 200 R 40 40 0 0 B +X P13 14 -700 -400 200 R 40 40 0 0 B +X P14 15 -700 -500 200 R 40 40 0 0 B +X P15 16 -700 -600 200 R 40 40 0 0 B +X P16 17 -700 -700 200 R 40 40 0 0 B +X P17 18 -700 -800 200 R 40 40 0 0 B +X P18 19 700 500 200 L 40 40 0 0 B +X GND 2 700 -1000 200 L 40 40 0 0 W +X P19 20 700 400 200 L 40 40 0 0 B +X P20 21 700 300 200 L 40 40 0 0 B +X P21 22 700 200 200 L 40 40 0 0 B +X P22 23 700 100 200 L 40 40 0 0 B +X P23 24 700 0 200 L 40 40 0 0 B +X P24 25 700 -100 200 L 40 40 0 0 B +X P25 26 700 -200 200 L 40 40 0 0 B +X P26 27 700 -300 200 L 40 40 0 0 B +X P27 28 700 -400 200 L 40 40 0 0 B +X P28 29 700 -500 200 L 40 40 0 0 B +X GND 3 700 -1000 200 L 40 40 0 0 W +X P29 30 700 -600 200 L 40 40 0 0 B +X P30 31 700 -700 200 L 40 40 0 0 B +X P31 32 700 -800 200 L 40 40 0 0 B +X SCLK 33 700 900 200 L 40 40 0 0 I C +X DIN 34 700 800 200 L 40 40 0 0 I +X CS 35 700 1000 200 L 40 40 0 0 I +X V+ 36 700 1200 200 L 40 40 0 0 W +X DOUT 4 700 700 200 L 40 40 0 0 O +X P4 5 -700 500 200 R 40 40 0 0 B +X P5 6 -700 400 200 R 40 40 0 0 B +X P6 7 -700 300 200 R 40 40 0 0 B +X P7 8 -700 200 200 R 40 40 0 0 B +X P8 9 -700 100 200 R 40 40 0 0 B +ENDDRAW +ENDDEF +# # dk_Interface-Controllers_FT232RQ-REEL # DEF dk_Interface-Controllers_FT232RQ-REEL U 0 40 Y Y 1 F N diff --git a/electrical/same54_dev_board/same54_dev_board.sch b/electrical/same54_dev_board/same54_dev_board.sch index eca4da90..8ec71930 100644 --- a/electrical/same54_dev_board/same54_dev_board.sch +++ b/electrical/same54_dev_board/same54_dev_board.sch @@ -99,4 +99,20 @@ F 3 "~" H 7500 4200 50 0001 C CNN 1 7900 4200 1 0 0 -1 $EndComp +$Comp +L MAX7301AAX_:MAX7301AAX+ U? +U 1 1 5E8C31CA +P 7000 7450 +F 0 "U?" H 7000 8920 50 0000 C CNN +F 1 "MAX7301AAX+" H 7000 8829 50 0000 C CNN +F 2 "SOP80P1030X264-36N" H 7000 7450 50 0001 L BNN +F 3 "Maxim Integrated" H 7000 7450 50 0001 L BNN +F 4 "None" H 7000 7450 50 0001 L BNN "Field4" +F 5 "Interface IC - I/O extensions Maxim Integrated MAX7301AAX+ SPI 26 MHz SSOP 36" H 7000 7450 50 0001 L BNN "Field5" +F 6 "SSOP-36 Maxim" H 7000 7450 50 0001 L BNN "Field6" +F 7 "Unavailable" H 7000 7450 50 0001 L BNN "Field7" +F 8 "MAX7301AAX+" H 7000 7450 50 0001 L BNN "Field8" + 1 7000 7450 + 1 0 0 -1 +$EndComp $EndSCHEMATC diff --git a/electrical/same54_dev_board/same54_dev_board.sch-bak b/electrical/same54_dev_board/same54_dev_board.sch-bak index 934703b2..eca4da90 100644 --- a/electrical/same54_dev_board/same54_dev_board.sch-bak +++ b/electrical/same54_dev_board/same54_dev_board.sch-bak @@ -89,14 +89,14 @@ F 3 "" H 4400 4950 50 0001 C CNN 1 0 0 -1 $EndComp $Comp -L Connector_Generic:Conn_02x20_Odd_Even J? -U 1 1 5E801746 -P 8150 4100 -F 0 "J?" H 8200 5217 50 0000 C CNN -F 1 "Conn_02x20_LCD_INTF" H 8200 5126 50 0000 C CNN -F 2 "" H 8150 4100 50 0001 C CNN -F 3 "~" H 8150 4100 50 0001 C CNN - 1 8150 4100 +L Conn_02x20_LCD_INTF:Conn_02x20_Odd_Even_LCD_INTF J? +U 1 1 5E896181 +P 7900 4200 +F 0 "J?" H 7900 5325 50 0000 C CNN +F 1 "Conn_02x20_Odd_Even_LCD_INTF" H 7900 5234 50 0000 C CNN +F 2 "" H 7500 4200 50 0001 C CNN +F 3 "~" H 7500 4200 50 0001 C CNN + 1 7900 4200 1 0 0 -1 $EndComp $EndSCHEMATC diff --git a/software/README.md b/software/README.md new file mode 100644 index 00000000..daef2c46 --- /dev/null +++ b/software/README.md @@ -0,0 +1,17 @@ +# Software Readme + + + +## Goals + - Fish Tank Controller that will monitor and send updates via wifi (or ethernet idk yet???) + +## To Do + - PCB + - Decide on core reqs (ex: do i want wifi or NOT) + - map pins + - create bare software for pin mappings + - fix asf4 vomit <<>> + +## Info + + diff --git a/software/conf/project_oracle.atstart b/software/conf/project_oracle.atstart new file mode 100644 index 00000000..1db4532a --- /dev/null +++ b/software/conf/project_oracle.atstart @@ -0,0 +1,1261 @@ +format_version: '2' +name: My Project +versions: + api: '1.0' + backend: 1.7.301 + commit: 1e07622763d149970fd8808a8f12ff3b1e84e0d7 + content: unknown + content_pack_name: unknown + format: '2' + frontend: 1.7.301 + packs_version_avr8: 1.0.1408 + packs_version_qtouch: unknown + packs_version_sam: 1.0.1373 + version_backend: 1.7.301 + version_frontend: '' +board: + identifier: CustomBoard + device: SAME54P20A-AF +details: null +application: null +middlewares: {} +drivers: + CMCC: + user_label: CMCC + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::CMCC::driver_config_definition::CMCC::HAL:HPL:CMCC + functionality: System + api: HAL:HPL:CMCC + configuration: + cache_size: 4 KB + cmcc_advanced_configuration: false + cmcc_clock_gating_disable: false + cmcc_data_cache_disable: false + cmcc_enable: false + cmcc_inst_cache_disable: false + optional_signals: [] + variant: null + clocks: + domain_group: null + DMAC: + user_label: DMAC + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC + functionality: System + api: HAL:HPL:DMAC + configuration: + dmac_beatsize_0: 8-bit bus transfer + dmac_beatsize_1: 8-bit bus transfer + dmac_beatsize_10: 8-bit bus transfer + dmac_beatsize_11: 8-bit bus transfer + dmac_beatsize_12: 8-bit bus transfer + dmac_beatsize_13: 8-bit bus transfer + dmac_beatsize_14: 8-bit bus transfer + dmac_beatsize_15: 8-bit bus transfer + dmac_beatsize_16: 8-bit bus transfer + dmac_beatsize_17: 8-bit bus transfer + dmac_beatsize_18: 8-bit bus transfer + dmac_beatsize_19: 8-bit bus transfer + dmac_beatsize_2: 8-bit bus transfer + dmac_beatsize_20: 8-bit bus transfer + dmac_beatsize_21: 8-bit bus transfer + dmac_beatsize_22: 8-bit bus transfer + dmac_beatsize_23: 8-bit bus transfer + dmac_beatsize_24: 8-bit bus transfer + dmac_beatsize_25: 8-bit bus transfer + dmac_beatsize_26: 8-bit bus transfer + dmac_beatsize_27: 8-bit bus transfer + dmac_beatsize_28: 8-bit bus transfer + dmac_beatsize_29: 8-bit bus transfer + dmac_beatsize_3: 8-bit bus transfer + dmac_beatsize_30: 8-bit bus transfer + dmac_beatsize_31: 8-bit bus transfer + dmac_beatsize_4: 8-bit bus transfer + dmac_beatsize_5: 8-bit bus transfer + dmac_beatsize_6: 8-bit bus transfer + dmac_beatsize_7: 8-bit bus transfer + dmac_beatsize_8: 8-bit bus transfer + dmac_beatsize_9: 8-bit bus transfer + dmac_blockact_0: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_1: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_10: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_11: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_12: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_13: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_14: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_15: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_16: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_17: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_18: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_19: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_2: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_20: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_21: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_22: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_23: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_24: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_25: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_26: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_27: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_28: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_29: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_3: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_30: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_31: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_4: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_5: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_6: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_7: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_8: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_9: Channel will be disabled if it is the last block transfer in + the transaction + dmac_channel_0_settings: false + dmac_channel_10_settings: false + dmac_channel_11_settings: false + dmac_channel_12_settings: false + dmac_channel_13_settings: false + dmac_channel_14_settings: false + dmac_channel_15_settings: false + dmac_channel_16_settings: false + dmac_channel_17_settings: false + dmac_channel_18_settings: false + dmac_channel_19_settings: false + dmac_channel_1_settings: false + dmac_channel_20_settings: false + dmac_channel_21_settings: false + dmac_channel_22_settings: false + dmac_channel_23_settings: false + dmac_channel_24_settings: false + dmac_channel_25_settings: false + dmac_channel_26_settings: false + dmac_channel_27_settings: false + dmac_channel_28_settings: false + dmac_channel_29_settings: false + dmac_channel_2_settings: false + dmac_channel_30_settings: false + dmac_channel_31_settings: false + dmac_channel_3_settings: false + dmac_channel_4_settings: false + dmac_channel_5_settings: false + dmac_channel_6_settings: false + dmac_channel_7_settings: false + dmac_channel_8_settings: false + dmac_channel_9_settings: false + dmac_dbgrun: false + dmac_dstinc_0: false + dmac_dstinc_1: false + dmac_dstinc_10: false + dmac_dstinc_11: false + dmac_dstinc_12: false + dmac_dstinc_13: false + dmac_dstinc_14: false + dmac_dstinc_15: false + dmac_dstinc_16: false + dmac_dstinc_17: false + dmac_dstinc_18: false + dmac_dstinc_19: false + dmac_dstinc_2: false + dmac_dstinc_20: false + dmac_dstinc_21: false + dmac_dstinc_22: false + dmac_dstinc_23: false + dmac_dstinc_24: false + dmac_dstinc_25: false + dmac_dstinc_26: false + dmac_dstinc_27: false + dmac_dstinc_28: false + dmac_dstinc_29: false + dmac_dstinc_3: false + dmac_dstinc_30: false + dmac_dstinc_31: false + dmac_dstinc_4: false + dmac_dstinc_5: false + dmac_dstinc_6: false + dmac_dstinc_7: false + dmac_dstinc_8: false + dmac_dstinc_9: false + dmac_enable: false + dmac_evact_0: No action + dmac_evact_1: No action + dmac_evact_10: No action + dmac_evact_11: No action + dmac_evact_12: No action + dmac_evact_13: No action + dmac_evact_14: No action + dmac_evact_15: No action + dmac_evact_16: No action + dmac_evact_17: No action + dmac_evact_18: No action + dmac_evact_19: No action + dmac_evact_2: No action + dmac_evact_20: No action + dmac_evact_21: No action + dmac_evact_22: No action + dmac_evact_23: No action + dmac_evact_24: No action + dmac_evact_25: No action + dmac_evact_26: No action + dmac_evact_27: No action + dmac_evact_28: No action + dmac_evact_29: No action + dmac_evact_3: No action + dmac_evact_30: No action + dmac_evact_31: No action + dmac_evact_4: No action + dmac_evact_5: No action + dmac_evact_6: No action + dmac_evact_7: No action + dmac_evact_8: No action + dmac_evact_9: No action + dmac_evie_0: false + dmac_evie_1: false + dmac_evie_10: false + dmac_evie_11: false + dmac_evie_12: false + dmac_evie_13: false + dmac_evie_14: false + dmac_evie_15: false + dmac_evie_16: false + dmac_evie_17: false + dmac_evie_18: false + dmac_evie_19: false + dmac_evie_2: false + dmac_evie_20: false + dmac_evie_21: false + dmac_evie_22: false + dmac_evie_23: false + dmac_evie_24: false + dmac_evie_25: false + dmac_evie_26: false + dmac_evie_27: false + dmac_evie_28: false + dmac_evie_29: false + dmac_evie_3: false + dmac_evie_30: false + dmac_evie_31: false + dmac_evie_4: false + dmac_evie_5: false + dmac_evie_6: false + dmac_evie_7: false + dmac_evie_8: false + dmac_evie_9: false + dmac_evoe_0: false + dmac_evoe_1: false + dmac_evoe_10: false + dmac_evoe_11: false + dmac_evoe_12: false + dmac_evoe_13: false + dmac_evoe_14: false + dmac_evoe_15: false + dmac_evoe_16: false + dmac_evoe_17: false + dmac_evoe_18: false + dmac_evoe_19: false + dmac_evoe_2: false + dmac_evoe_20: false + dmac_evoe_21: false + dmac_evoe_22: false + dmac_evoe_23: false + dmac_evoe_24: false + dmac_evoe_25: false + dmac_evoe_26: false + dmac_evoe_27: false + dmac_evoe_28: false + dmac_evoe_29: false + dmac_evoe_3: false + dmac_evoe_30: false + dmac_evoe_31: false + dmac_evoe_4: false + dmac_evoe_5: false + dmac_evoe_6: false + dmac_evoe_7: false + dmac_evoe_8: false + dmac_evoe_9: false + dmac_evosel_0: Event generation disabled + dmac_evosel_1: Event generation disabled + dmac_evosel_10: Event generation disabled + dmac_evosel_11: Event generation disabled + dmac_evosel_12: Event generation disabled + dmac_evosel_13: Event generation disabled + dmac_evosel_14: Event generation disabled + dmac_evosel_15: Event generation disabled + dmac_evosel_16: Event generation disabled + dmac_evosel_17: Event generation disabled + dmac_evosel_18: Event generation disabled + dmac_evosel_19: Event generation disabled + dmac_evosel_2: Event generation disabled + dmac_evosel_20: Event generation disabled + dmac_evosel_21: Event generation disabled + dmac_evosel_22: Event generation disabled + dmac_evosel_23: Event generation disabled + dmac_evosel_24: Event generation disabled + dmac_evosel_25: Event generation disabled + dmac_evosel_26: Event generation disabled + dmac_evosel_27: Event generation disabled + dmac_evosel_28: Event generation disabled + dmac_evosel_29: Event generation disabled + dmac_evosel_3: Event generation disabled + dmac_evosel_30: Event generation disabled + dmac_evosel_31: Event generation disabled + dmac_evosel_4: Event generation disabled + dmac_evosel_5: Event generation disabled + dmac_evosel_6: Event generation disabled + dmac_evosel_7: Event generation disabled + dmac_evosel_8: Event generation disabled + dmac_evosel_9: Event generation disabled + dmac_lvl_0: Channel priority 0 + dmac_lvl_1: Channel priority 0 + dmac_lvl_10: Channel priority 0 + dmac_lvl_11: Channel priority 0 + dmac_lvl_12: Channel priority 0 + dmac_lvl_13: Channel priority 0 + dmac_lvl_14: Channel priority 0 + dmac_lvl_15: Channel priority 0 + dmac_lvl_16: Channel priority 0 + dmac_lvl_17: Channel priority 0 + dmac_lvl_18: Channel priority 0 + dmac_lvl_19: Channel priority 0 + dmac_lvl_2: Channel priority 0 + dmac_lvl_20: Channel priority 0 + dmac_lvl_21: Channel priority 0 + dmac_lvl_22: Channel priority 0 + dmac_lvl_23: Channel priority 0 + dmac_lvl_24: Channel priority 0 + dmac_lvl_25: Channel priority 0 + dmac_lvl_26: Channel priority 0 + dmac_lvl_27: Channel priority 0 + dmac_lvl_28: Channel priority 0 + dmac_lvl_29: Channel priority 0 + dmac_lvl_3: Channel priority 0 + dmac_lvl_30: Channel priority 0 + dmac_lvl_31: Channel priority 0 + dmac_lvl_4: Channel priority 0 + dmac_lvl_5: Channel priority 0 + dmac_lvl_6: Channel priority 0 + dmac_lvl_7: Channel priority 0 + dmac_lvl_8: Channel priority 0 + dmac_lvl_9: Channel priority 0 + dmac_lvlen0: true + dmac_lvlen1: true + dmac_lvlen2: true + dmac_lvlen3: true + dmac_lvlpri0: 0 + dmac_lvlpri1: 0 + dmac_lvlpri2: 0 + dmac_lvlpri3: 0 + dmac_rrlvlen0: Static arbitration scheme for channel with priority 0 + dmac_rrlvlen1: Static arbitration scheme for channel with priority 1 + dmac_rrlvlen2: Static arbitration scheme for channel with priority 2 + dmac_rrlvlen3: Static arbitration scheme for channel with priority 3 + dmac_runstdby_0: false + dmac_runstdby_1: false + dmac_runstdby_10: false + dmac_runstdby_11: false + dmac_runstdby_12: false + dmac_runstdby_13: false + dmac_runstdby_14: false + dmac_runstdby_15: false + dmac_runstdby_16: false + dmac_runstdby_17: false + dmac_runstdby_18: false + dmac_runstdby_19: false + dmac_runstdby_2: false + dmac_runstdby_20: false + dmac_runstdby_21: false + dmac_runstdby_22: false + dmac_runstdby_23: false + dmac_runstdby_24: false + dmac_runstdby_25: false + dmac_runstdby_26: false + dmac_runstdby_27: false + dmac_runstdby_28: false + dmac_runstdby_29: false + dmac_runstdby_3: false + dmac_runstdby_30: false + dmac_runstdby_31: false + dmac_runstdby_4: false + dmac_runstdby_5: false + dmac_runstdby_6: false + dmac_runstdby_7: false + dmac_runstdby_8: false + dmac_runstdby_9: false + dmac_srcinc_0: false + dmac_srcinc_1: false + dmac_srcinc_10: false + dmac_srcinc_11: false + dmac_srcinc_12: false + dmac_srcinc_13: false + dmac_srcinc_14: false + dmac_srcinc_15: false + dmac_srcinc_16: false + dmac_srcinc_17: false + dmac_srcinc_18: false + dmac_srcinc_19: false + dmac_srcinc_2: false + dmac_srcinc_20: false + dmac_srcinc_21: false + dmac_srcinc_22: false + dmac_srcinc_23: false + dmac_srcinc_24: false + dmac_srcinc_25: false + dmac_srcinc_26: false + dmac_srcinc_27: false + dmac_srcinc_28: false + dmac_srcinc_29: false + dmac_srcinc_3: false + dmac_srcinc_30: false + dmac_srcinc_31: false + dmac_srcinc_4: false + dmac_srcinc_5: false + dmac_srcinc_6: false + dmac_srcinc_7: false + dmac_srcinc_8: false + dmac_srcinc_9: false + dmac_stepsel_0: Step size settings apply to the destination address + dmac_stepsel_1: Step size settings apply to the destination address + dmac_stepsel_10: Step size settings apply to the destination address + dmac_stepsel_11: Step size settings apply to the destination address + dmac_stepsel_12: Step size settings apply to the destination address + dmac_stepsel_13: Step size settings apply to the destination address + dmac_stepsel_14: Step size settings apply to the destination address + dmac_stepsel_15: Step size settings apply to the destination address + dmac_stepsel_16: Step size settings apply to the destination address + dmac_stepsel_17: Step size settings apply to the destination address + dmac_stepsel_18: Step size settings apply to the destination address + dmac_stepsel_19: Step size settings apply to the destination address + dmac_stepsel_2: Step size settings apply to the destination address + dmac_stepsel_20: Step size settings apply to the destination address + dmac_stepsel_21: Step size settings apply to the destination address + dmac_stepsel_22: Step size settings apply to the destination address + dmac_stepsel_23: Step size settings apply to the destination address + dmac_stepsel_24: Step size settings apply to the destination address + dmac_stepsel_25: Step size settings apply to the destination address + dmac_stepsel_26: Step size settings apply to the destination address + dmac_stepsel_27: Step size settings apply to the destination address + dmac_stepsel_28: Step size settings apply to the destination address + dmac_stepsel_29: Step size settings apply to the destination address + dmac_stepsel_3: Step size settings apply to the destination address + dmac_stepsel_30: Step size settings apply to the destination address + dmac_stepsel_31: Step size settings apply to the destination address + dmac_stepsel_4: Step size settings apply to the destination address + dmac_stepsel_5: Step size settings apply to the destination address + dmac_stepsel_6: Step size settings apply to the destination address + dmac_stepsel_7: Step size settings apply to the destination address + dmac_stepsel_8: Step size settings apply to the destination address + dmac_stepsel_9: Step size settings apply to the destination address + dmac_stepsize_0: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_1: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_10: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_11: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_12: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_13: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_14: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_15: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_16: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_17: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_18: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_19: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_2: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_20: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_21: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_22: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_23: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_24: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_25: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_26: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_27: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_28: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_29: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_3: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_30: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_31: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_4: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_5: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_6: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_trifsrc_0: Only software/event triggers + dmac_trifsrc_1: Only software/event triggers + dmac_trifsrc_10: Only software/event triggers + dmac_trifsrc_11: Only software/event triggers + dmac_trifsrc_12: Only software/event triggers + dmac_trifsrc_13: Only software/event triggers + dmac_trifsrc_14: Only software/event triggers + dmac_trifsrc_15: Only software/event triggers + dmac_trifsrc_16: Only software/event triggers + dmac_trifsrc_17: Only software/event triggers + dmac_trifsrc_18: Only software/event triggers + dmac_trifsrc_19: Only software/event triggers + dmac_trifsrc_2: Only software/event triggers + dmac_trifsrc_20: Only software/event triggers + dmac_trifsrc_21: Only software/event triggers + dmac_trifsrc_22: Only software/event triggers + dmac_trifsrc_23: Only software/event triggers + dmac_trifsrc_24: Only software/event triggers + dmac_trifsrc_25: Only software/event triggers + dmac_trifsrc_26: Only software/event triggers + dmac_trifsrc_27: Only software/event triggers + dmac_trifsrc_28: Only software/event triggers + dmac_trifsrc_29: Only software/event triggers + dmac_trifsrc_3: Only software/event triggers + dmac_trifsrc_30: Only software/event triggers + dmac_trifsrc_31: Only software/event triggers + dmac_trifsrc_4: Only software/event triggers + dmac_trifsrc_5: Only software/event triggers + dmac_trifsrc_6: Only software/event triggers + dmac_trifsrc_7: Only software/event triggers + dmac_trifsrc_8: Only software/event triggers + dmac_trifsrc_9: Only software/event triggers + dmac_trigact_0: One trigger required for each block transfer + dmac_trigact_1: One trigger required for each block transfer + dmac_trigact_10: One trigger required for each block transfer + dmac_trigact_11: One trigger required for each block transfer + dmac_trigact_12: One trigger required for each block transfer + dmac_trigact_13: One trigger required for each block transfer + dmac_trigact_14: One trigger required for each block transfer + dmac_trigact_15: One trigger required for each block transfer + dmac_trigact_16: One trigger required for each block transfer + dmac_trigact_17: One trigger required for each block transfer + dmac_trigact_18: One trigger required for each block transfer + dmac_trigact_19: One trigger required for each block transfer + dmac_trigact_2: One trigger required for each block transfer + dmac_trigact_20: One trigger required for each block transfer + dmac_trigact_21: One trigger required for each block transfer + dmac_trigact_22: One trigger required for each block transfer + dmac_trigact_23: One trigger required for each block transfer + dmac_trigact_24: One trigger required for each block transfer + dmac_trigact_25: One trigger required for each block transfer + dmac_trigact_26: One trigger required for each block transfer + dmac_trigact_27: One trigger required for each block transfer + dmac_trigact_28: One trigger required for each block transfer + dmac_trigact_29: One trigger required for each block transfer + dmac_trigact_3: One trigger required for each block transfer + dmac_trigact_30: One trigger required for each block transfer + dmac_trigact_31: One trigger required for each block transfer + dmac_trigact_4: One trigger required for each block transfer + dmac_trigact_5: One trigger required for each block transfer + dmac_trigact_6: One trigger required for each block transfer + dmac_trigact_7: One trigger required for each block transfer + dmac_trigact_8: One trigger required for each block transfer + dmac_trigact_9: One trigger required for each block transfer + optional_signals: [] + variant: null + clocks: + domain_group: null + EXTERNAL_IRQ_0: + user_label: EXTERNAL_IRQ_0 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::EIC::driver_config_definition::Default::HAL:Driver:Ext.IRQ + functionality: External_IRQ + api: HAL:Driver:Ext_IRQ + configuration: + eic_arch_asynch0: false + eic_arch_asynch1: false + eic_arch_asynch10: false + eic_arch_asynch11: false + eic_arch_asynch12: false + eic_arch_asynch13: false + eic_arch_asynch14: false + eic_arch_asynch15: false + eic_arch_asynch2: false + eic_arch_asynch3: false + eic_arch_asynch4: false + eic_arch_asynch5: false + eic_arch_asynch6: false + eic_arch_asynch7: false + eic_arch_asynch8: false + eic_arch_asynch9: false + eic_arch_cksel: Clocked by GCLK + eic_arch_debounce_enable0: false + eic_arch_debounce_enable1: false + eic_arch_debounce_enable10: false + eic_arch_debounce_enable11: false + eic_arch_debounce_enable12: false + eic_arch_debounce_enable13: false + eic_arch_debounce_enable14: false + eic_arch_debounce_enable15: false + eic_arch_debounce_enable2: false + eic_arch_debounce_enable3: false + eic_arch_debounce_enable4: false + eic_arch_debounce_enable5: false + eic_arch_debounce_enable6: false + eic_arch_debounce_enable7: false + eic_arch_debounce_enable8: false + eic_arch_debounce_enable9: false + eic_arch_enable_irq_setting0: false + eic_arch_enable_irq_setting1: false + eic_arch_enable_irq_setting10: false + eic_arch_enable_irq_setting11: false + eic_arch_enable_irq_setting12: false + eic_arch_enable_irq_setting13: false + eic_arch_enable_irq_setting14: false + eic_arch_enable_irq_setting15: false + eic_arch_enable_irq_setting2: false + eic_arch_enable_irq_setting3: false + eic_arch_enable_irq_setting4: false + eic_arch_enable_irq_setting5: false + eic_arch_enable_irq_setting6: false + eic_arch_enable_irq_setting7: false + eic_arch_enable_irq_setting8: false + eic_arch_enable_irq_setting9: false + eic_arch_extinteo0: false + eic_arch_extinteo1: false + eic_arch_extinteo10: false + eic_arch_extinteo11: false + eic_arch_extinteo12: false + eic_arch_extinteo13: false + eic_arch_extinteo14: false + eic_arch_extinteo15: false + eic_arch_extinteo2: false + eic_arch_extinteo3: false + eic_arch_extinteo4: false + eic_arch_extinteo5: false + eic_arch_extinteo6: false + eic_arch_extinteo7: false + eic_arch_extinteo8: false + eic_arch_extinteo9: false + eic_arch_filten0: false + eic_arch_filten1: false + eic_arch_filten10: false + eic_arch_filten11: false + eic_arch_filten12: false + eic_arch_filten13: false + eic_arch_filten14: false + eic_arch_filten15: false + eic_arch_filten2: false + eic_arch_filten3: false + eic_arch_filten4: false + eic_arch_filten5: false + eic_arch_filten6: false + eic_arch_filten7: false + eic_arch_filten8: false + eic_arch_filten9: false + eic_arch_nmi_ctrl: false + eic_arch_nmiasynch: false + eic_arch_nmifilten: false + eic_arch_nmisense: No detection + eic_arch_prescaler0: Divided by 2 + eic_arch_prescaler1: Divided by 2 + eic_arch_sense0: No detection + eic_arch_sense1: No detection + eic_arch_sense10: No detection + eic_arch_sense11: No detection + eic_arch_sense12: No detection + eic_arch_sense13: No detection + eic_arch_sense14: No detection + eic_arch_sense15: No detection + eic_arch_sense2: No detection + eic_arch_sense3: No detection + eic_arch_sense4: No detection + eic_arch_sense5: No detection + eic_arch_sense6: No detection + eic_arch_sense7: No detection + eic_arch_sense8: No detection + eic_arch_sense9: No detection + eic_arch_states0: '3' + eic_arch_states1: '3' + eic_arch_tickon: The sampling rate is EIC clock + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: EIC + input: Generic clock generator 0 + external: false + external_frequency: 0 + configuration: + eic_gclk_selection: Generic clock generator 0 + GCLK: + user_label: GCLK + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK + functionality: System + api: HAL:HPL:GCLK + configuration: + enable_gclk_gen_0: true + enable_gclk_gen_0__externalclock: 1000000 + enable_gclk_gen_1: false + enable_gclk_gen_10: false + enable_gclk_gen_10__externalclock: 1000000 + enable_gclk_gen_11: false + enable_gclk_gen_11__externalclock: 1000000 + enable_gclk_gen_1__externalclock: 1000000 + enable_gclk_gen_2: false + enable_gclk_gen_2__externalclock: 1000000 + enable_gclk_gen_3: true + enable_gclk_gen_3__externalclock: 1000000 + enable_gclk_gen_4: false + enable_gclk_gen_4__externalclock: 1000000 + enable_gclk_gen_5: false + enable_gclk_gen_5__externalclock: 1000000 + enable_gclk_gen_6: false + enable_gclk_gen_6__externalclock: 1000000 + enable_gclk_gen_7: false + enable_gclk_gen_7__externalclock: 1000000 + enable_gclk_gen_8: false + enable_gclk_gen_8__externalclock: 1000000 + enable_gclk_gen_9: false + enable_gclk_gen_9__externalclock: 1000000 + gclk_arch_gen_0_enable: true + gclk_arch_gen_0_idc: false + gclk_arch_gen_0_oe: false + gclk_arch_gen_0_oov: false + gclk_arch_gen_0_runstdby: false + gclk_arch_gen_10_enable: false + gclk_arch_gen_10_idc: false + gclk_arch_gen_10_oe: false + gclk_arch_gen_10_oov: false + gclk_arch_gen_10_runstdby: false + gclk_arch_gen_11_enable: false + gclk_arch_gen_11_idc: false + gclk_arch_gen_11_oe: false + gclk_arch_gen_11_oov: false + gclk_arch_gen_11_runstdby: false + gclk_arch_gen_1_enable: false + gclk_arch_gen_1_idc: false + gclk_arch_gen_1_oe: false + gclk_arch_gen_1_oov: false + gclk_arch_gen_1_runstdby: false + gclk_arch_gen_2_enable: false + gclk_arch_gen_2_idc: false + gclk_arch_gen_2_oe: false + gclk_arch_gen_2_oov: false + gclk_arch_gen_2_runstdby: false + gclk_arch_gen_3_enable: true + gclk_arch_gen_3_idc: false + gclk_arch_gen_3_oe: false + gclk_arch_gen_3_oov: false + gclk_arch_gen_3_runstdby: false + gclk_arch_gen_4_enable: false + gclk_arch_gen_4_idc: false + gclk_arch_gen_4_oe: false + gclk_arch_gen_4_oov: false + gclk_arch_gen_4_runstdby: false + gclk_arch_gen_5_enable: false + gclk_arch_gen_5_idc: false + gclk_arch_gen_5_oe: false + gclk_arch_gen_5_oov: false + gclk_arch_gen_5_runstdby: false + gclk_arch_gen_6_enable: false + gclk_arch_gen_6_idc: false + gclk_arch_gen_6_oe: false + gclk_arch_gen_6_oov: false + gclk_arch_gen_6_runstdby: false + gclk_arch_gen_7_enable: false + gclk_arch_gen_7_idc: false + gclk_arch_gen_7_oe: false + gclk_arch_gen_7_oov: false + gclk_arch_gen_7_runstdby: false + gclk_arch_gen_8_enable: false + gclk_arch_gen_8_idc: false + gclk_arch_gen_8_oe: false + gclk_arch_gen_8_oov: false + gclk_arch_gen_8_runstdby: false + gclk_arch_gen_9_enable: false + gclk_arch_gen_9_idc: false + gclk_arch_gen_9_oe: false + gclk_arch_gen_9_oov: false + gclk_arch_gen_9_runstdby: false + gclk_gen_0_div: 1 + gclk_gen_0_div_sel: false + gclk_gen_0_oscillator: Digital Phase Locked Loop (DPLL0) + gclk_gen_10_div: 1 + gclk_gen_10_div_sel: false + gclk_gen_10_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_11_div: 1 + gclk_gen_11_div_sel: false + gclk_gen_11_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_1_div: 1 + gclk_gen_1_div_sel: false + gclk_gen_1_oscillator: Digital Frequency Locked Loop (DFLL48M) + gclk_gen_2_div: 1 + gclk_gen_2_div_sel: true + gclk_gen_2_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_3_div: 1 + gclk_gen_3_div_sel: false + gclk_gen_3_oscillator: 32kHz External Crystal Oscillator (XOSC32K) + gclk_gen_4_div: 1 + gclk_gen_4_div_sel: false + gclk_gen_4_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_5_div: 1 + gclk_gen_5_div_sel: false + gclk_gen_5_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_6_div: 1 + gclk_gen_6_div_sel: false + gclk_gen_6_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_7_div: 1 + gclk_gen_7_div_sel: false + gclk_gen_7_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_8_div: 1 + gclk_gen_8_div_sel: false + gclk_gen_8_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_9_div: 1 + gclk_gen_9_div_sel: false + gclk_gen_9_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + optional_signals: [] + variant: null + clocks: + domain_group: null + MCLK: + user_label: MCLK + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK + functionality: System + api: HAL:HPL:MCLK + configuration: + cpu_clock_source: Generic clock generator 0 + cpu_div: '1' + enable_cpu_clock: true + mclk_arch_bupdiv: Divide by 8 + mclk_arch_hsdiv: Divide by 1 + mclk_arch_lpdiv: Divide by 4 + nvm_wait_states: '5' + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: CPU + input: CPU + external: false + external_frequency: 0 + configuration: {} + OSC32KCTRL: + user_label: OSC32KCTRL + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL + functionality: System + api: HAL:HPL:OSC32KCTRL + configuration: + enable_osculp32k: true + enable_rtc_source: false + enable_xosc32k: true + osculp32k_calib: 0 + osculp32k_calib_enable: false + rtc_1khz_selection: false + rtc_source_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) + xosc32k_arch_cfden: false + xosc32k_arch_cfdeo: false + xosc32k_arch_cgm: Standard mode + xosc32k_arch_en1k: false + xosc32k_arch_en32k: true + xosc32k_arch_enable: true + xosc32k_arch_ondemand: true + xosc32k_arch_runstdby: false + xosc32k_arch_startup: 1000092us + xosc32k_arch_swben: false + xosc32k_arch_xtalen: true + optional_signals: [] + variant: null + clocks: + domain_group: null + OSCCTRL: + user_label: OSCCTRL + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL + functionality: System + api: HAL:HPL:OSCCTRL + configuration: + dfll_arch_bplckc: false + dfll_arch_calibration: false + dfll_arch_ccdis: false + dfll_arch_coarse: 31 + dfll_arch_cstep: 1 + dfll_arch_enable: false + dfll_arch_fine: 128 + dfll_arch_fstep: 1 + dfll_arch_llaw: false + dfll_arch_ondemand: false + dfll_arch_qldis: false + dfll_arch_runstdby: false + dfll_arch_stable: false + dfll_arch_usbcrm: false + dfll_arch_waitlock: true + dfll_mode: Open Loop Mode + dfll_mul: 0 + dfll_ref_clock: Generic clock generator 3 + enable_dfll: false + enable_fdpll0: true + enable_fdpll1: false + enable_xosc0: false + enable_xosc1: false + fdpll0_arch_dcoen: false + fdpll0_arch_enable: true + fdpll0_arch_filter: 0 + fdpll0_arch_lbypass: true + fdpll0_arch_ltime: No time-out, automatic lock + fdpll0_arch_ondemand: false + fdpll0_arch_refclk: XOSC32K clock reference + fdpll0_arch_runstdby: false + fdpll0_arch_wuf: false + fdpll0_clock_dcofilter: 0 + fdpll0_clock_div: 0 + fdpll0_ldr: 3661 + fdpll0_ldrfrac: 1 + fdpll0_ref_clock: 32kHz External Crystal Oscillator (XOSC32K) + fdpll1_arch_dcoen: false + fdpll1_arch_enable: false + fdpll1_arch_filter: 0 + fdpll1_arch_lbypass: false + fdpll1_arch_ltime: No time-out, automatic lock + fdpll1_arch_ondemand: false + fdpll1_arch_refclk: XOSC32K clock reference + fdpll1_arch_runstdby: false + fdpll1_arch_wuf: false + fdpll1_clock_dcofilter: 0 + fdpll1_clock_div: 0 + fdpll1_ldr: 1463 + fdpll1_ldrfrac: 13 + fdpll1_ref_clock: 32kHz External Crystal Oscillator (XOSC32K) + xosc0_arch_cfden: false + xosc0_arch_enable: false + xosc0_arch_enalc: false + xosc0_arch_lowbufgain: false + xosc0_arch_ondemand: false + xosc0_arch_runstdby: false + xosc0_arch_startup: 31us + xosc0_arch_swben: false + xosc0_arch_xtalen: false + xosc0_frequency: 12000000 + xosc1_arch_cfden: false + xosc1_arch_enable: false + xosc1_arch_enalc: false + xosc1_arch_lowbufgain: false + xosc1_arch_ondemand: false + xosc1_arch_runstdby: false + xosc1_arch_startup: 31us + xosc1_arch_swben: false + xosc1_arch_xtalen: true + xosc1_frequency: 12000000 + optional_signals: [] + variant: null + clocks: + domain_group: null + PORT: + user_label: PORT + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::PORT::driver_config_definition::PORT::HAL:HPL:PORT + functionality: System + api: HAL:HPL:PORT + configuration: + enable_port_input_event_0: false + enable_port_input_event_1: false + enable_port_input_event_2: false + enable_port_input_event_3: false + porta_event_action_0: Output register of pin will be set to level of event + porta_event_action_1: Output register of pin will be set to level of event + porta_event_action_2: Output register of pin will be set to level of event + porta_event_action_3: Output register of pin will be set to level of event + porta_event_pin_identifier_0: 0 + porta_event_pin_identifier_1: 0 + porta_event_pin_identifier_2: 0 + porta_event_pin_identifier_3: 0 + porta_input_event_enable_0: false + porta_input_event_enable_1: false + porta_input_event_enable_2: false + porta_input_event_enable_3: false + portb_event_action_0: Output register of pin will be set to level of event + portb_event_action_1: Output register of pin will be set to level of event + portb_event_action_2: Output register of pin will be set to level of event + portb_event_action_3: Output register of pin will be set to level of event + portb_event_pin_identifier_0: 0 + portb_event_pin_identifier_1: 0 + portb_event_pin_identifier_2: 0 + portb_event_pin_identifier_3: 0 + portb_input_event_enable_0: false + portb_input_event_enable_1: false + portb_input_event_enable_2: false + portb_input_event_enable_3: false + portc_event_action_0: Output register of pin will be set to level of event + portc_event_action_1: Output register of pin will be set to level of event + portc_event_action_2: Output register of pin will be set to level of event + portc_event_action_3: Output register of pin will be set to level of event + portc_event_pin_identifier_0: 0 + portc_event_pin_identifier_1: 0 + portc_event_pin_identifier_2: 0 + portc_event_pin_identifier_3: 0 + portc_input_event_enable_0: false + portc_input_event_enable_1: false + portc_input_event_enable_2: false + portc_input_event_enable_3: false + portd_event_action_0: Output register of pin will be set to level of event + portd_event_action_1: Output register of pin will be set to level of event + portd_event_action_2: Output register of pin will be set to level of event + portd_event_action_3: Output register of pin will be set to level of event + portd_event_pin_identifier_0: 0 + portd_event_pin_identifier_1: 0 + portd_event_pin_identifier_2: 0 + portd_event_pin_identifier_3: 0 + portd_input_event_enable_0: false + portd_input_event_enable_1: false + portd_input_event_enable_2: false + portd_input_event_enable_3: false + optional_signals: [] + variant: null + clocks: + domain_group: null + QUAD_SPI_0: + user_label: QUAD_SPI_0 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::QSPI::driver_config_definition::QSPI.Master::HAL:Driver:QSPI.Sync + functionality: Quad_SPI + api: HAL:Driver:QSPI_Sync + configuration: + qspi_advanced: false + qspi_baud_rate: 375000 + qspi_cpha: Data is changed on the leading edge of SPCK and captured on the following + edge of SPCK. + qspi_cpol: The inactive state value of SPCK is logic level zero. + qspi_dlybs: 0 + qspi_dlycs: 0 + optional_signals: [] + variant: null + clocks: + domain_group: null + RAMECC: + user_label: RAMECC + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::RAMECC::driver_config_definition::RAMECC::HAL:HPL:RAMECC + functionality: System + api: HAL:HPL:RAMECC + configuration: {} + optional_signals: [] + variant: null + clocks: + domain_group: null + TIMER_0: + user_label: TIMER_0 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::RTC::driver_config_definition::Timer::HAL:Driver:Timer + functionality: Timer + api: HAL:Driver:Timer + configuration: + rtc_arch_comp_val: 32 + rtc_arch_init_reset: true + rtc_arch_prescaler: OFF(Peripheral clock divided by 1) + rtc_cmpeo0: false + rtc_cmpeo1: false + rtc_event_control: false + rtc_ovfeo: false + rtc_pereo0: false + rtc_pereo1: false + rtc_pereo2: false + rtc_pereo3: false + rtc_pereo4: false + rtc_pereo5: false + rtc_pereo6: false + rtc_pereo7: false + rtc_tamper_active_layer_frequency_prescalar: DIV2 CLK_RTC_OUT is CLK_RTC /2 + rtc_tamper_debounce_frequency_prescalar: DIV2 CLK_RTC_DEB is CLK_RTC /2 + rtc_tamper_input_action_0: OFF(Disabled) + rtc_tamper_input_action_1: OFF(Disabled) + rtc_tamper_input_action_2: OFF(Disabled) + rtc_tamper_input_action_3: OFF(Disabled) + rtc_tamper_input_action_4: OFF(Disabled) + rtc_tampereo: false + rtc_tampevei: false + tamper_debounce_enable_0: false + tamper_debounce_enable_1: false + tamper_debounce_enable_2: false + tamper_debounce_enable_3: false + tamper_debounce_enable_4: false + tamper_input_0_settings: false + tamper_input_1_settings: false + tamper_input_2_settings: false + tamper_input_3_settings: false + tamper_input_4_settings: false + tamper_level_0: false + tamper_level_1: false + tamper_level_2: false + tamper_level_3: false + tamper_level_4: false + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: RTC + input: RTC source + external: false + external_frequency: 0 + configuration: + rtc_clk_selection: RTC source + USART_0: + user_label: USART_0 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::SERCOM0::driver_config_definition::UART::HAL:Driver:USART.Sync + functionality: USART + api: HAL:Driver:USART_Sync + configuration: + usart_advanced: false + usart_arch_clock_mode: USART with internal clock + usart_arch_cloden: false + usart_arch_dbgstop: Keep running + usart_arch_dord: LSB is transmitted first + usart_arch_enc: No encoding + usart_arch_fractional: 0 + usart_arch_ibon: false + usart_arch_lin_slave_enable: Disable + usart_arch_runstdby: false + usart_arch_sampa: 7-8-9 (3-4-5 8-bit over-sampling) + usart_arch_sampr: 16x arithmetic + usart_arch_sfde: false + usart_baud_rate: 9600 + usart_character_size: 8 bits + usart_parity: No parity + usart_rx_enable: true + usart_stop_bit: One stop bit + usart_tx_enable: true + optional_signals: [] + variant: + specification: TXPO=0, RXPO=1, CMODE=0 + required_signals: + - name: SERCOM0/PAD/0 + pad: PA04 + label: TX + - name: SERCOM0/PAD/1 + pad: PA05 + label: RX + clocks: + domain_group: + nodes: + - name: Core + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Slow + input: Generic clock generator 3 + external: false + external_frequency: 0 + configuration: + core_gclk_selection: Generic clock generator 0 + slow_gclk_selection: Generic clock generator 3 + I2C_0: + user_label: I2C_0 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::SERCOM1::driver_config_definition::I2C.Master.Standard~2FFast-mode::HAL:Driver:I2C.Master.Sync + functionality: I2C + api: HAL:Driver:I2C_Master_Sync + configuration: + i2c_master_advanced: false + i2c_master_arch_dbgstop: Keep running + i2c_master_arch_inactout: Disabled + i2c_master_arch_lowtout: false + i2c_master_arch_mexttoen: false + i2c_master_arch_runstdby: false + i2c_master_arch_sdahold: 300-600ns hold time + i2c_master_arch_sexttoen: false + i2c_master_arch_trise: 215 + i2c_master_baud_rate: 100000 + optional_signals: [] + variant: + specification: SDA=0, SCL=1 + required_signals: + - name: SERCOM1/PAD/0 + pad: PA16 + label: SDA + - name: SERCOM1/PAD/1 + pad: PA17 + label: SCL + clocks: + domain_group: + nodes: + - name: Core + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Slow + input: Generic clock generator 3 + external: false + external_frequency: 0 + configuration: + core_gclk_selection: Generic clock generator 0 + slow_gclk_selection: Generic clock generator 3 + DELAY_0: + user_label: DELAY_0 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::SysTick::driver_config_definition::Delay::HAL:Driver:Delay + functionality: Delay + api: HAL:Driver:Delay + configuration: + systick_arch_tickint: false + optional_signals: [] + variant: null + clocks: + domain_group: null + TIMER_1: + user_label: TIMER_1 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::TC0::driver_config_definition::Timer::HAL:Driver:Timer + functionality: Timer + api: HAL:Driver:Timer + configuration: + tc_arch_dbgrun: false + tc_arch_evact: Event action disabled + tc_arch_mceo0: false + tc_arch_mceo1: false + tc_arch_ondemand: false + tc_arch_ovfeo: false + tc_arch_presync: Reload or reset counter on next GCLK + tc_arch_runstdby: false + tc_arch_tcei: false + tc_arch_tcinv: false + timer_advanced_configuration: false + timer_event_control: false + timer_prescaler: Divide by 8 + timer_tick: 1000 + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: TC + input: Generic clock generator 0 + external: false + external_frequency: 0 + configuration: + tc_gclk_selection: Generic clock generator 0 +pads: + PA04: + name: PA04 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::pad::PA04 + mode: Peripheral IO + user_label: PA04 + configuration: null + PA05: + name: PA05 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::pad::PA05 + mode: Peripheral IO + user_label: PA05 + configuration: null + PA16: + name: PA16 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::pad::PA16 + mode: I2C + user_label: PA16 + configuration: null + PA17: + name: PA17 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54P20A-AF::pad::PA17 + mode: I2C + user_label: PA17 + configuration: null +toolchain_options: []