diff --git a/software/firmware/Makefile.backup b/software/firmware/Makefile.backup new file mode 100644 index 00000000..b633a617 --- /dev/null +++ b/software/firmware/Makefile.backup @@ -0,0 +1,662 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +GDB=arm-none-eabi-gdb +ifdef SystemRoot + SHELL = cmd.exe + MK_DIR = mkdir +else + ifeq ($(shell uname), Linux) + MK_DIR = mkdir -p + endif + + ifeq ($(shell uname | cut -d _ -f 1), CYGWIN) + MK_DIR = mkdir -p + endif + + ifeq ($(shell uname | cut -d _ -f 1), MINGW32) + MK_DIR = mkdir -p + endif + + ifeq ($(shell uname | cut -d _ -f 1), MINGW64) + MK_DIR = mkdir -p + endif + + ifeq ($(shell uname | cut -d _ -f 1), DARWIN) + MK_DIR = mkdir -p + endif +endif + +print-% : ; @echo $* = $($*) +# List the subdirectories for creating object files +SUB_DIRS += \ + \ +hpl/pm \ +hpl/tc \ +hpl/osc32kctrl \ +hpl/ramecc \ +hpl/dmac \ +hal/src \ +gcc \ +hpl/mclk \ +hpl/eic \ +hpl/sercom \ +hpl/gclk \ +hpl/oscctrl \ +hal/utils/src \ +gcc/gcc \ +hpl/core \ +hpl/cmcc \ +shared/drivers \ +shared/devices \ +shared/devices/display \ +shared/thirdparty/lvgl/porting \ +shared/thirdparty/lvgl/src/lv_core \ +shared/thirdparty/lvgl/src/lv_draw \ +shared/thirdparty/lvgl/src/lv_font \ +shared/thirdparty/lvgl/src/lv_gpu \ +shared/thirdparty/lvgl/src/lv_hal \ +shared/thirdparty/lvgl/src/lv_misc \ +shared/thirdparty/lvgl/src/lv_themes \ +shared/thirdparty/lvgl/src/lv_widgets \ +shared/thirdparty/lvgl/tests \ +shared/thirdparty/lvgl/tests/lv_test_core \ +shared/thirdparty/lvgl/tests/lv_test_objx + +# List the object files +OBJS += \ +hal/src/hal_io.o \ +hpl/eic/hpl_eic.o \ +hpl/core/hpl_core_m4.o \ +hal/utils/src/utils_syscalls.o \ +hal/src/hal_timer.o \ +gcc/system_same54.o \ +hal/src/hal_i2c_m_sync.o \ +hal/src/hal_delay.o \ +hpl/pm/hpl_pm.o \ +hpl/core/hpl_init.o \ +hpl/ramecc/hpl_ramecc.o \ +hal/utils/src/utils_list.o \ +hal/utils/src/utils_assert.o \ +hpl/dmac/hpl_dmac.o \ +hpl/oscctrl/hpl_oscctrl.o \ +hpl/mclk/hpl_mclk.o \ +hpl/sercom/hpl_sercom.o \ +hpl/gclk/hpl_gclk.o \ +hal/src/hal_init.o \ +gcc/gcc/startup_same54.o \ +main.o \ +oracle.o \ +hpl/osc32kctrl/hpl_osc32kctrl.o \ +driver_init.o \ +hal/src/hal_usart_async.o \ +hal/src/hal_ext_irq.o \ +hal/utils/src/utils_ringbuffer.o \ +hal/src/hal_gpio.o \ +hal/utils/src/utils_event.o \ +hal/src/hal_sleep.o \ +hal/src/hal_cache.o \ +hpl/cmcc/hpl_cmcc.o \ +atmel_start.o \ +hpl/tc/hpl_tc.o \ +hal/src/hal_atomic.o \ +shared/drivers/p_gpio.o \ +shared/drivers/p_i2c.o \ +shared/drivers/p_tcc.o \ +shared/drivers/p_usart.o \ +shared/devices/p_screen.o \ +shared/devices/display/p_ssd1963.o \ +shared/thirdparty/lvgl/porting/lv_port_disp_template.o \ +shared/thirdparty/lvgl/porting/lv_port_fs_template.o \ +shared/thirdparty/lvgl/porting/lv_port_indev_template.o \ +shared/thirdparty/lvgl/src/lv_core/lv_debug.o \ +shared/thirdparty/lvgl/src/lv_core/lv_disp.o \ +shared/thirdparty/lvgl/src/lv_core/lv_group.o \ +shared/thirdparty/lvgl/src/lv_core/lv_indev.o \ +shared/thirdparty/lvgl/src/lv_core/lv_obj.o \ +shared/thirdparty/lvgl/src/lv_core/lv_refr.o \ +shared/thirdparty/lvgl/src/lv_core/lv_style.o \ +shared/thirdparty/lvgl/src/lv_draw/lv_draw_arc.o \ +shared/thirdparty/lvgl/src/lv_draw/lv_draw_blend.o \ +shared/thirdparty/lvgl/src/lv_draw/lv_draw_img.o \ +shared/thirdparty/lvgl/src/lv_draw/lv_draw_label.o \ +shared/thirdparty/lvgl/src/lv_draw/lv_draw_line.o \ +shared/thirdparty/lvgl/src/lv_draw/lv_draw_mask.o \ +shared/thirdparty/lvgl/src/lv_draw/lv_draw_rect.o \ +shared/thirdparty/lvgl/src/lv_draw/lv_draw_triangle.o \ +shared/thirdparty/lvgl/src/lv_draw/lv_img_buf.o \ +shared/thirdparty/lvgl/src/lv_draw/lv_img_cache.o \ +shared/thirdparty/lvgl/src/lv_draw/lv_img_decoder.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_dejavu_16_persian_hebrew.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_fmt_txt.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_12.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_12_subpx.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_14.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_16.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_18.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_20.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_22.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_24.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_26.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_28.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_28_compressed.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_30.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_32.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_34.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_36.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_38.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_40.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_42.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_44.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_46.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_48.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_simsun_16_cjk.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_unscii_8.o \ +shared/thirdparty/lvgl/src/lv_gpu/lv_gpu_stm32_dma2d.o \ +shared/thirdparty/lvgl/src/lv_hal/lv_hal_disp.o \ +shared/thirdparty/lvgl/src/lv_hal/lv_hal_indev.o \ +shared/thirdparty/lvgl/src/lv_hal/lv_hal_tick.o \ +shared/thirdparty/lvgl/src/lv_misc/lv_anim.o \ +shared/thirdparty/lvgl/src/lv_misc/lv_area.o \ +shared/thirdparty/lvgl/src/lv_misc/lv_async.o \ +shared/thirdparty/lvgl/src/lv_misc/lv_bidi.o \ +shared/thirdparty/lvgl/src/lv_misc/lv_color.o \ +shared/thirdparty/lvgl/src/lv_misc/lv_fs.o \ +shared/thirdparty/lvgl/src/lv_misc/lv_gc.o \ +shared/thirdparty/lvgl/src/lv_misc/lv_ll.o \ +shared/thirdparty/lvgl/src/lv_misc/lv_log.o \ +shared/thirdparty/lvgl/src/lv_misc/lv_math.o \ +shared/thirdparty/lvgl/src/lv_misc/lv_mem.o \ +shared/thirdparty/lvgl/src/lv_misc/lv_printf.o \ +shared/thirdparty/lvgl/src/lv_misc/lv_task.o \ +shared/thirdparty/lvgl/src/lv_misc/lv_templ.o \ +shared/thirdparty/lvgl/src/lv_misc/lv_txt.o \ +shared/thirdparty/lvgl/src/lv_misc/lv_txt_ap.o \ +shared/thirdparty/lvgl/src/lv_misc/lv_utils.o \ +shared/thirdparty/lvgl/src/lv_themes/lv_theme.o \ +shared/thirdparty/lvgl/src/lv_themes/lv_theme_empty.o \ +shared/thirdparty/lvgl/src/lv_themes/lv_theme_material.o \ +shared/thirdparty/lvgl/src/lv_themes/lv_theme_mono.o \ +shared/thirdparty/lvgl/src/lv_themes/lv_theme_template.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_arc.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_bar.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_btn.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_btnmatrix.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_calendar.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_canvas.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_chart.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_checkbox.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_cont.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_cpicker.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_dropdown.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_gauge.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_img.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_imgbtn.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_keyboard.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_label.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_led.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_line.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_linemeter.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_list.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_msgbox.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_objmask.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_objx_templ.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_page.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_roller.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_slider.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_spinbox.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_spinner.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_switch.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_table.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_tabview.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_textarea.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_tileview.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_win.o \ +shared/thirdparty/lvgl/tests/lv_test_assert.o \ +shared/thirdparty/lvgl/tests/lv_test_core/lv_test_core.o \ +shared/thirdparty/lvgl/tests/lv_test_core/lv_test_obj.o \ +shared/thirdparty/lvgl/tests/lv_test_core/lv_test_style.o \ +shared/thirdparty/lvgl/tests/lv_test_main.o \ +shared/thirdparty/lvgl/tests/lv_test_objx/lv_test_cont.o + +OBJS_AS_ARGS += \ +"hal/src/hal_io.o" \ +"hpl/eic/hpl_eic.o" \ +"hpl/core/hpl_core_m4.o" \ +"hal/utils/src/utils_syscalls.o" \ +"hal/src/hal_timer.o" \ +"gcc/system_same54.o" \ +"hal/src/hal_i2c_m_sync.o" \ +"hal/src/hal_delay.o" \ +"hpl/pm/hpl_pm.o" \ +"hpl/core/hpl_init.o" \ +"hpl/ramecc/hpl_ramecc.o" \ +"hal/utils/src/utils_list.o" \ +"hal/utils/src/utils_assert.o" \ +"hpl/dmac/hpl_dmac.o" \ +"hpl/oscctrl/hpl_oscctrl.o" \ +"hpl/mclk/hpl_mclk.o" \ +"hpl/sercom/hpl_sercom.o" \ +"hpl/gclk/hpl_gclk.o" \ +"hal/src/hal_init.o" \ +"gcc/gcc/startup_same54.o" \ +"main.o" \ +"oracle.o" \ +"hpl/osc32kctrl/hpl_osc32kctrl.o" \ +"driver_init.o" \ +"hal/src/hal_usart_async.o" \ +"hal/src/hal_ext_irq.o" \ +"hal/utils/src/utils_ringbuffer.o" \ +"hal/src/hal_gpio.o" \ +"hal/utils/src/utils_event.o" \ +"hal/src/hal_sleep.o" \ +"hal/src/hal_cache.o" \ +"hpl/cmcc/hpl_cmcc.o" \ +"atmel_start.o" \ +"hpl/tc/hpl_tc.o" \ +"hal/src/hal_atomic.o" \ +"shared/drivers/p_gpio.o" \ +"shared/drivers/p_i2c.o" \ +"shared/drivers/p_tcc.o" \ +"shared/drivers/p_usart.o" \ +"shared/devices/p_screen.o" \ +"shared/devices/display/p_ssd1963.o" \ +"shared/thirdparty/lvgl/porting/lv_port_disp_template.o" \ +"shared/thirdparty/lvgl/porting/lv_port_fs_template.o" \ +"shared/thirdparty/lvgl/porting/lv_port_indev_template.o" \ +"shared/thirdparty/lvgl/src/lv_core/lv_debug.o" \ +"shared/thirdparty/lvgl/src/lv_core/lv_disp.o" \ +"shared/thirdparty/lvgl/src/lv_core/lv_group.o" \ +"shared/thirdparty/lvgl/src/lv_core/lv_indev.o" \ +"shared/thirdparty/lvgl/src/lv_core/lv_obj.o" \ +"shared/thirdparty/lvgl/src/lv_core/lv_refr.o" \ +"shared/thirdparty/lvgl/src/lv_core/lv_style.o" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_draw_arc.o" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_draw_blend.o" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_draw_img.o" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_draw_label.o" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_draw_line.o" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_draw_mask.o" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_draw_rect.o" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_draw_triangle.o" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_img_buf.o" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_img_cache.o" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_img_decoder.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_dejavu_16_persian_hebrew.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_fmt_txt.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_12.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_12_subpx.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_14.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_16.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_18.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_20.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_22.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_24.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_26.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_28.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_28_compressed.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_30.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_32.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_34.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_36.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_38.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_40.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_42.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_44.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_46.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_48.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_simsun_16_cjk.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_unscii_8.o" \ +"shared/thirdparty/lvgl/src/lv_gpu/lv_gpu_stm32_dma2d.o" \ +"shared/thirdparty/lvgl/src/lv_hal/lv_hal_disp.o" \ +"shared/thirdparty/lvgl/src/lv_hal/lv_hal_indev.o" \ +"shared/thirdparty/lvgl/src/lv_hal/lv_hal_tick.o" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_anim.o" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_area.o" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_async.o" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_bidi.o" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_color.o" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_fs.o" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_gc.o" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_ll.o" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_log.o" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_math.o" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_mem.o" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_printf.o" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_task.o" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_templ.o" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_txt.o" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_txt_ap.o" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_utils.o" \ +"shared/thirdparty/lvgl/src/lv_themes/lv_theme.o" \ +"shared/thirdparty/lvgl/src/lv_themes/lv_theme_empty.o" \ +"shared/thirdparty/lvgl/src/lv_themes/lv_theme_material.o" \ +"shared/thirdparty/lvgl/src/lv_themes/lv_theme_mono.o" \ +"shared/thirdparty/lvgl/src/lv_themes/lv_theme_template.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_arc.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_bar.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_btn.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_btnmatrix.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_calendar.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_canvas.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_chart.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_checkbox.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_cont.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_cpicker.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_dropdown.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_gauge.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_img.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_imgbtn.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_keyboard.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_label.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_led.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_line.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_linemeter.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_list.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_msgbox.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_objmask.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_objx_templ.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_page.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_roller.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_slider.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_spinbox.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_spinner.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_switch.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_table.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_tabview.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_textarea.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_tileview.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_win.o" \ +"shared/thirdparty/lvgl/tests/lv_test_assert.o" \ +"shared/thirdparty/lvgl/tests/lv_test_core/lv_test_core.o" \ +"shared/thirdparty/lvgl/tests/lv_test_core/lv_test_obj.o" \ +"shared/thirdparty/lvgl/tests/lv_test_core/lv_test_style.o" \ +"shared/thirdparty/lvgl/tests/lv_test_main.o" \ +"shared/thirdparty/lvgl/tests/lv_test_objx/lv_test_cont.o" + +# List the directories containing header files +DIR_INCLUDES += \ +-I"../" \ +-I"../config" \ +-I"../hal/include" \ +-I"../hal/utils/include" \ +-I"../hpl/cmcc" \ +-I"../hpl/core" \ +-I"../hpl/dmac" \ +-I"../hpl/eic" \ +-I"../hpl/gclk" \ +-I"../hpl/mclk" \ +-I"../hpl/osc32kctrl" \ +-I"../hpl/oscctrl" \ +-I"../hpl/pm" \ +-I"../hpl/port" \ +-I"../hpl/ramecc" \ +-I"../hpl/sercom" \ +-I"../hpl/tc" \ +-I"../hri" \ +-I"../CMSIS/Core/Include" \ +-I"../include" \ +-I"../shared/thirdparty" \ +-I"../shared/thirdparty/lvgl" \ +-I"../shared/drivers" \ +-I"../shared/devices" \ +-I"../shared/devices/display" + +# List the dependency files +DEPS := $(OBJS:%.o=%.d) + +DEPS_AS_ARGS += \ +"hal/utils/src/utils_event.d" \ +"hal/src/hal_io.d" \ +"hpl/ramecc/hpl_ramecc.d" \ +"hpl/core/hpl_core_m4.d" \ +"hpl/eic/hpl_eic.d" \ +"hal/utils/src/utils_syscalls.d" \ +"hal/src/hal_i2c_m_sync.d" \ +"hal/src/hal_timer.d" \ +"hal/utils/src/utils_list.d" \ +"hpl/cmcc/hpl_cmcc.d" \ +"hpl/dmac/hpl_dmac.d" \ +"hal/utils/src/utils_assert.d" \ +"hal/src/hal_delay.d" \ +"hpl/core/hpl_init.d" \ +"hpl/pm/hpl_pm.d" \ +"hpl/gclk/hpl_gclk.d" \ +"hpl/sercom/hpl_sercom.d" \ +"gcc/gcc/startup_same54.d" \ +"hal/src/hal_init.d" \ +"hpl/mclk/hpl_mclk.d" \ +"driver_init.d" \ +"hal/src/hal_usart_async.d" \ +"hpl/osc32kctrl/hpl_osc32kctrl.d" \ +"main.d" \ +"hal/src/hal_cache.d" \ +"hal/src/hal_sleep.d" \ +"hal/utils/src/utils_ringbuffer.d" \ +"hal/src/hal_ext_irq.d" \ +"hal/src/hal_gpio.d" \ +"hal/src/hal_atomic.d" \ +"hpl/tc/hpl_tc.d" \ +"hpl/oscctrl/hpl_oscctrl.d" \ +"gcc/system_same54.d" \ +"atmel_start.d" \ +"shared/drivers/p_gpio.d" \ +"shared/drivers/p_i2c.d" \ +"shared/drivers/p_tcc.d" \ +"shared/drivers/p_usart.d" \ +"shared/devices/p_screen.d" \ +"shared/devices/display/p_ssd1963.d" \ +"shared/thirdparty/lvgl/porting/lv_port_disp_template.d" \ +"shared/thirdparty/lvgl/porting/lv_port_fs_template.d" \ +"shared/thirdparty/lvgl/porting/lv_port_indev_template.d" \ +"shared/thirdparty/lvgl/src/lv_core/lv_debug.d" \ +"shared/thirdparty/lvgl/src/lv_core/lv_disp.d" \ +"shared/thirdparty/lvgl/src/lv_core/lv_group.d" \ +"shared/thirdparty/lvgl/src/lv_core/lv_indev.d" \ +"shared/thirdparty/lvgl/src/lv_core/lv_obj.d" \ +"shared/thirdparty/lvgl/src/lv_core/lv_refr.d" \ +"shared/thirdparty/lvgl/src/lv_core/lv_style.d" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_draw_arc.d" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_draw_blend.d" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_draw_img.d" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_draw_label.d" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_draw_line.d" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_draw_mask.d" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_draw_rect.d" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_draw_triangle.d" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_img_buf.d" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_img_cache.d" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_img_decoder.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_dejavu_16_persian_hebrew.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_fmt_txt.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_12.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_12_subpx.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_14.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_16.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_18.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_20.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_22.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_24.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_26.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_28.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_28_compressed.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_30.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_32.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_34.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_36.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_38.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_40.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_42.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_44.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_46.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_48.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_simsun_16_cjk.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_unscii_8.d" \ +"shared/thirdparty/lvgl/src/lv_gpu/lv_gpu_stm32_dma2d.d" \ +"shared/thirdparty/lvgl/src/lv_hal/lv_hal_disp.d" \ +"shared/thirdparty/lvgl/src/lv_hal/lv_hal_indev.d" \ +"shared/thirdparty/lvgl/src/lv_hal/lv_hal_tick.d" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_anim.d" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_area.d" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_async.d" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_bidi.d" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_color.d" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_fs.d" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_gc.d" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_ll.d" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_log.d" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_math.d" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_mem.d" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_printf.d" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_task.d" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_templ.d" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_txt.d" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_txt_ap.d" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_utils.d" \ +"shared/thirdparty/lvgl/src/lv_themes/lv_theme.d" \ +"shared/thirdparty/lvgl/src/lv_themes/lv_theme_empty.d" \ +"shared/thirdparty/lvgl/src/lv_themes/lv_theme_material.d" \ +"shared/thirdparty/lvgl/src/lv_themes/lv_theme_mono.d" \ +"shared/thirdparty/lvgl/src/lv_themes/lv_theme_template.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_arc.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_bar.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_btn.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_btnmatrix.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_calendar.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_canvas.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_chart.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_checkbox.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_cont.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_cpicker.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_dropdown.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_gauge.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_img.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_imgbtn.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_keyboard.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_label.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_led.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_line.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_linemeter.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_list.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_msgbox.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_objmask.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_objx_templ.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_page.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_roller.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_slider.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_spinbox.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_spinner.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_switch.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_table.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_tabview.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_textarea.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_tileview.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_win.d" \ +"shared/thirdparty/lvgl/tests/lv_test_assert.d" \ +"shared/thirdparty/lvgl/tests/lv_test_core/lv_test_core.d" \ +"shared/thirdparty/lvgl/tests/lv_test_core/lv_test_obj.d" \ +"shared/thirdparty/lvgl/tests/lv_test_core/lv_test_style.d" \ +"shared/thirdparty/lvgl/tests/lv_test_main.d" \ +"shared/thirdparty/lvgl/tests/lv_test_objx/lv_test_cont.d" + +OUTPUT_FILE_NAME :=AtmelStart +QUOTE := " +OUTPUT_FILE_PATH +=$(OUTPUT_FILE_NAME).elf +OUTPUT_FILE_PATH_AS_ARGS +=$(OUTPUT_FILE_NAME).elf + +vpath %.c ../ +vpath %.s ../ +vpath %.S ../ + +# All Target +all: $(SUB_DIRS) $(OUTPUT_FILE_PATH) + +# Linker target + +$(OUTPUT_FILE_PATH): $(OBJS) + @echo Building target: $@ + @echo Invoking: ARM/GNU Linker + $(QUOTE)arm-none-eabi-gcc$(QUOTE) -o $(OUTPUT_FILE_NAME).elf $(OBJS_AS_ARGS) -Wl,--start-group -lm -Wl,--end-group -mthumb \ +-Wl,-Map="$(OUTPUT_FILE_NAME).map" --specs=nano.specs -Wl,--gc-sections -mcpu=cortex-m4 \ + \ +-T"../gcc/gcc/same54n19a_flash.ld" \ +-L"../gcc/gcc" + @echo Finished building target: $@ + + "arm-none-eabi-objcopy" -O binary "$(OUTPUT_FILE_NAME).elf" "$(OUTPUT_FILE_NAME).bin" + "arm-none-eabi-objcopy" -O ihex -R .eeprom -R .fuse -R .lock -R .signature \ + "$(OUTPUT_FILE_NAME).elf" "$(OUTPUT_FILE_NAME).hex" + "arm-none-eabi-objcopy" -j .eeprom --set-section-flags=.eeprom=alloc,load --change-section-lma \ + .eeprom=0 --no-change-warnings -O binary "$(OUTPUT_FILE_NAME).elf" \ + "$(OUTPUT_FILE_NAME).eep" || exit 0 + "arm-none-eabi-objdump" -h -S "$(OUTPUT_FILE_NAME).elf" > "$(OUTPUT_FILE_NAME).lss" + "arm-none-eabi-size" "$(OUTPUT_FILE_NAME).elf" + + + +# Compiler targets + + + + +%.o: %.c + @echo Building file: $< + @echo ARM/GNU C Compiler + $(QUOTE)arm-none-eabi-gcc$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \ +-D__SAME54N19A__ -mcpu=cortex-m4 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 \ +$(DIR_INCLUDES) \ +-MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + +%.o: %.s + @echo Building file: $< + @echo ARM/GNU Assembler + $(QUOTE)arm-none-eabi-as$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \ +-D__SAME54N19A__ -mcpu=cortex-m4 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 \ +$(DIR_INCLUDES) \ +-MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + +%.o: %.S + @echo Building file: $< + @echo ARM/GNU Preprocessing Assembler + $(QUOTE)arm-none-eabi-gcc$(QUOTE) -x c -mthumb -DDEBUG -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \ +-D__SAME54N19A__ -mcpu=cortex-m4 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 \ +$(DIR_INCLUDES) \ +-MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + +# Detect changes in the dependent files and recompile the respective object files. +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(DEPS)),) +-include $(DEPS) +endif +endif + +$(SUB_DIRS): + $(MK_DIR) "$@" + +clean: + rm -f $(OBJS_AS_ARGS) + rm -f $(OUTPUT_FILE_PATH) + rm -f $(DEPS) + rm -f $(DEPS_AS_ARGS) + rm -f $(OUTPUT_FILE_NAME).a $(OUTPUT_FILE_NAME).hex $(OUTPUT_FILE_NAME).bin \ + $(OUTPUT_FILE_NAME).lss $(OUTPUT_FILE_NAME).eep $(OUTPUT_FILE_NAME).map \ + $(OUTPUT_FILE_NAME).srec + +push:\ +all + @echo $(QUOTE)$(QUOTE) + @echo $(QUOTE)Uploading $(OUTPUT_FILE_NAME).elf...$(QUOTE) + @$(GDB) $(OUTPUT_FILE_NAME).elf -x $(QUOTE)../scripts/push.gdb$(QUOTE) >/dev/null + @echo $(QUOTE)$(QUOTE)$(OUTPUT_FILE_NAME).elf $(QUOTE) uploaded!$(QUOTE) + @$(QUOTE)$(SIZE)$(QUOTE) $(QUOTE)$(OUTPUT_FILE_NAME).elf$(QUOTE) + +debug:\ +all + @$(GDB) $(OUTPUT_FILE_NAME).elf -x $(QUOTE)../scripts/debug.gdb$(QUOTE) diff --git a/software/firmware/oracle_e54_edition/build/.gdb_history b/software/firmware/oracle_e54_edition/build/.gdb_history index 3ec4ce19..b9c1011f 100644 --- a/software/firmware/oracle_e54_edition/build/.gdb_history +++ b/software/firmware/oracle_e54_edition/build/.gdb_history @@ -35,3 +35,33 @@ mon s att 1 q q +tar ext /dev/ttyBmpGdb +load +monitor load +load +r +file oracle-e54.elf +load +q +tar ext /dev/ttyBmpGdb +mon s +mon s +mon s +mon s +mon s +att 1 +att 1 +mon s +mon s +mon s +mon s +mon s +mon s +mon s +mon s +tar ext /dev/ttyBmpGdb +mon s +mon s +mon s +mon s +mon s diff --git a/software/firmware/oracle_e54_edition_pre_port/e54_gfx_learning/e54_gfx_learning/Debug/.gdb_history b/software/firmware/oracle_e54_edition_pre_port/e54_gfx_learning/e54_gfx_learning/Debug/.gdb_history new file mode 100644 index 00000000..7e984f49 --- /dev/null +++ b/software/firmware/oracle_e54_edition_pre_port/e54_gfx_learning/e54_gfx_learning/Debug/.gdb_history @@ -0,0 +1,49 @@ +q +load +q +b main +r +s +c +q +b main] +b main +r +s +n +n +n +n +n +n +c +q +b main +r +s +n +s +n +n +n +n +n +n +n +n +r +s +n +n +n +n +n +n +s +s +s +c +q +q +qq +q diff --git a/software/firmware/oracle_e54_edition_pre_port/e54_gfx_learning/e54_gfx_learning/Debug/gdb.txt b/software/firmware/oracle_e54_edition_pre_port/e54_gfx_learning/e54_gfx_learning/Debug/gdb.txt new file mode 100644 index 00000000..e04fd10a --- /dev/null +++ b/software/firmware/oracle_e54_edition_pre_port/e54_gfx_learning/e54_gfx_learning/Debug/gdb.txt @@ -0,0 +1,2321 @@ +0x00000000 in exception_table () +### Assembly ######################################################################################################## + 0x00000000 ? ldmia r0!, {} + 0x00000002 ? movs r0, #1 + 0x00000004 ? asrs r1, r6, #32 + 0x00000006 ? movs r0, r0 + 0x00000008 ? asrs r5, r5, #32 + 0x0000000a ? movs r0, r0 + 0x0000000c ? asrs r5, r5, #32 + 0x0000000e ? movs r0, r0 + 0x00000010 ? asrs r5, r5, #32 + 0x00000012 ? movs r0, r0 +### Breakpoints ##################################################################################################### +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x0002180b r5 0x00011065 r10 0xfffdfdff pc 0x00000000 primask 0x00 + r1 0x00000001 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x01000000 basepri 0x00 + r2 0x20008e4c r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x20008570 r8 0x2000c67c sp 0x2001c800 msp 0x2001c800 control 0x00 + r4 0x0002180b r9 0x00011fb1 lr 0xffffffff psp 0xfdff677c +### Source ########################################################################################################## +### Stack ########################################################################################################### +[0] from 0x00000000 in exception_table +### Threads ######################################################################################################### +[1] id 0 from 0x00000000 in exception_table +### Variables ####################################################################################################### +##################################################################################################################### +target halted due to debug-request, current mode: Thread +xPSR: 0x01000000 pc: 0x00001030 msp: 0x2001c800 +Loading section .text, size 0x29a28 lma 0x0 +Loading section .ARM.exidx, size 0x8 lma 0x29a28 +Loading section .relocate, size 0x74 lma 0x29a30 +Start address 0x00000000, load size 170660 +Transfer rate: 46 KB/sec, 13127 bytes/write. +Breakpoint 1 at 0x2252: file .././main.c, line 6. +Note: automatically using hardware breakpoints for read-only addresses. +Starting program: /storage/Shared/Projects/Embedded-Graphics-Learning/software/firmware/oracle_e54_edition_pre_port/e54_gfx_learning/e54_gfx_learning/Debug/e54_gfx_learning.elf +### Output/messages ################################################################################################# + +Breakpoint 1, main () at .././main.c:6 +warning: Source file is more recent than executable. +6 oracle_init(); +### Assembly ######################################################################################################## +~ +~ +~ +~ + 0x00002250 main+0 push {r3, lr} +!0x00002252 main+2 ldr r3, [pc, #8] ; (0x225c ) + 0x00002254 main+4 blx r3 + 0x00002256 main+6 ldr r4, [pc, #8] ; (0x2260 ) + 0x00002258 main+8 blx r4 + 0x0000225a main+10 b.n 0x2258 +### Breakpoints ##################################################################################################### +[1] break at 0x00002252 in .././main.c:6 for main hit 1 time +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x00029a30 r5 0x00011065 r10 0xfffdfdff pc 0x00002252 primask 0x00 + r1 0x00000000 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x61000000 basepri 0x00 + r2 0x00f00000 r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x00002251 r8 0x2000c67c sp 0x2001c7f0 msp 0x2001c7f0 control 0x00 + r4 0x0002180b r9 0x00011fb1 lr 0x000010a1 psp 0xfdff677c +### Source ########################################################################################################## +~ +~ +~ +~ +~ + 1 #include "oracle.h" + 2 + 3 + 4 int main(void) + 5 { +! 6 oracle_init(); + 7 + 8 for(;;) + 9 { + 10 oracle_service(); + 11 } + 12 } +~ +~ +~ +### Stack ########################################################################################################### +[0] from 0x00002252 in main+2 at .././main.c:6 +### Threads ######################################################################################################### +[1] id 0 from 0x00002252 in main+2 at .././main.c:6 +### Variables ####################################################################################################### +##################################################################################################################### +### Output/messages ################################################################################################# +oracle_init () at .././oracle.c:20 +warning: Source file is more recent than executable. +20 init_mcu(); +### Assembly ######################################################################################################## +~ +~ +~ +~ + 0x00002264 oracle_init+0 push {r3, lr} + 0x00002266 oracle_init+2 ldr r3, [pc, #24] ; (0x2280 ) + 0x00002268 oracle_init+4 blx r3 + 0x0000226a oracle_init+6 ldr r3, [pc, #24] ; (0x2284 ) + 0x0000226c oracle_init+8 blx r3 + 0x0000226e oracle_init+10 ldr r3, [pc, #24] ; (0x2288 ) +### Breakpoints ##################################################################################################### +[1] break at 0x00002252 in .././main.c:6 for main hit 1 time +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x00029a30 r5 0x00011065 r10 0xfffdfdff pc 0x00002266 primask 0x00 + r1 0x00000000 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x61000000 basepri 0x00 + r2 0x00f00000 r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x00002265 r8 0x2000c67c sp 0x2001c7e8 msp 0x2001c7e8 control 0x00 + r4 0x0002180b r9 0x00011fb1 lr 0x00002257 psp 0xfdff677c +### Source ########################################################################################################## + 10 #include "p_i2c.h" + 11 #include "p_tcc.h" + 12 #include "lvgl/lvgl.h" + 13 #include "p_ssd1963.h" + 14 #include "p_screen.h" + 15 + 16 + 17 void oracle_init(void) + 18 { + 19 // init mcu + 20 init_mcu(); + 21 // uart init + 22 p_usart_init(); + 23 // i2c init + 24 p_i2c_init(); + 25 // gpio init + 26 p_gpio_init(); + 27 // time init + 28 p_tcc_init(); + 29 +### Stack ########################################################################################################### +[0] from 0x00002266 in oracle_init+2 at .././oracle.c:20 +[1] from 0x00002256 in main+6 at .././main.c:6 +### Threads ######################################################################################################### +[1] id 0 from 0x00002266 in oracle_init+2 at .././oracle.c:20 +### Variables ####################################################################################################### +##################################################################################################################### +Continuing. +### Output/messages ################################################################################################# + +Program received signal SIGINT, Interrupt. +lv_task_handler () at ../thirdparty/lvgl/src/lv_misc/lv_task.c:78 +warning: Source file is more recent than executable. +78 if(already_running) return 1; +### Assembly ######################################################################################################## +~ +~ +~ +~ + 0x000137c0 lv_task_handler+0 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 0x000137c4 lv_task_handler+4 ldr r3, [pc, #352] ; (0x13928 ) + 0x000137c6 lv_task_handler+6 ldrb r3, [r3, #4] + 0x000137c8 lv_task_handler+8 cmp r3, #0 + 0x000137ca lv_task_handler+10 bne.w 0x13920 + 0x000137ce lv_task_handler+14 ldr r3, [pc, #344] ; (0x13928 ) +### Breakpoints ##################################################################################################### +[1] break at 0x00002252 in .././main.c:6 for main hit 1 time +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0xffffffff r5 0x00011065 r10 0xfffdfdff pc 0x000137c4 primask 0x00 + r1 0x20008590 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x41000000 basepri 0x00 + r2 0x00000000 r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x000137c1 r8 0x2000c67c sp 0x2001c7c0 msp 0x2001c7c0 control 0x00 + r4 0x00002299 r9 0x00011fb1 lr 0x00001027 psp 0xfdff677c +### Source ########################################################################################################## + 68 * @return the time after which it must be called again + 69 */ + 70 LV_ATTRIBUTE_TASK_HANDLER uint32_t lv_task_handler(void) + 71 { + 72 + 73 + 74 LV_LOG_TRACE("lv_task_handler started"); + 75 + 76 /*Avoid concurrent running of the task handler*/ + 77 static bool already_running = false; + 78 if(already_running) return 1; + 79 already_running = true; + 80 + 81 static uint32_t idle_period_start = 0; + 82 static uint32_t handler_start = 0; + 83 static uint32_t busy_time = 0; + 84 static uint32_t time_till_next; + 85 + 86 if(lv_task_run == false) { + 87 already_running = false; /*Release mutex*/ +### Stack ########################################################################################################### +[0] from 0x000137c4 in lv_task_handler+4 at ../thirdparty/lvgl/src/lv_misc/lv_task.c:78 +[1] from 0x00001026 in p_screen_service+6 at ../devices/p_screen.c:43 +[2] from 0x0000229e in oracle_service+6 at .././oracle.c:35 +[3] from 0x0000225a in main+10 at .././main.c:10 +### Threads ######################################################################################################### +[1] id 0 from 0x000137c4 in lv_task_handler+4 at ../thirdparty/lvgl/src/lv_misc/lv_task.c:78 +### Variables ####################################################################################################### +loc already_running = false, idle_period_start = 66000, handler_start = 66088, busy_time = 31, time_till_next = 4294967295, task_interrupter = , next = , end_flag = , idle_period_time = +##################################################################################################################### +Quit +Detaching from program: /storage/Shared/Projects/Embedded-Graphics-Learning/software/firmware/oracle_e54_edition_pre_port/e54_gfx_learning/e54_gfx_learning/Debug/e54_gfx_learning.elf, Remote target +[Inferior 1 (Remote target) detached] +lv_task_handler () at ../thirdparty/lvgl/src/lv_misc/lv_task.c:78 +warning: Source file is more recent than executable. +78 if(already_running) return 1; +### Assembly ######################################################################################################## +~ +~ +~ +~ + 0x000137c0 lv_task_handler+0 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 0x000137c4 lv_task_handler+4 ldr r3, [pc, #352] ; (0x13928 ) + 0x000137c6 lv_task_handler+6 ldrb r3, [r3, #4] + 0x000137c8 lv_task_handler+8 cmp r3, #0 + 0x000137ca lv_task_handler+10 bne.w 0x13920 + 0x000137ce lv_task_handler+14 ldr r3, [pc, #344] ; (0x13928 ) +### Breakpoints ##################################################################################################### +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0xffffffff r5 0x00011065 r10 0xfffdfdff pc 0x000137c4 primask 0x00 + r1 0x20008590 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x41000000 basepri 0x00 + r2 0x00000000 r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x000137c1 r8 0x2000c67c sp 0x2001c7c0 msp 0x2001c7c0 control 0x00 + r4 0x00002299 r9 0x00011fb1 lr 0x00001027 psp 0xfdff677c +### Source ########################################################################################################## + 68 * @return the time after which it must be called again + 69 */ + 70 LV_ATTRIBUTE_TASK_HANDLER uint32_t lv_task_handler(void) + 71 { + 72 + 73 + 74 LV_LOG_TRACE("lv_task_handler started"); + 75 + 76 /*Avoid concurrent running of the task handler*/ + 77 static bool already_running = false; + 78 if(already_running) return 1; + 79 already_running = true; + 80 + 81 static uint32_t idle_period_start = 0; + 82 static uint32_t handler_start = 0; + 83 static uint32_t busy_time = 0; + 84 static uint32_t time_till_next; + 85 + 86 if(lv_task_run == false) { + 87 already_running = false; /*Release mutex*/ +### Stack ########################################################################################################### +[0] from 0x000137c4 in lv_task_handler+4 at ../thirdparty/lvgl/src/lv_misc/lv_task.c:78 +[1] from 0x00001026 in p_screen_service+6 at ../devices/p_screen.c:43 +[2] from 0x0000229e in oracle_service+6 at .././oracle.c:35 +[3] from 0x0000225a in main+10 at .././main.c:10 +### Threads ######################################################################################################### +[1] id 0 from 0x000137c4 in lv_task_handler+4 at ../thirdparty/lvgl/src/lv_misc/lv_task.c:78 +### Variables ####################################################################################################### +loc already_running = false, idle_period_start = 66000, handler_start = 66088, busy_time = 31, time_till_next = 4294967295, task_interrupter = , next = , end_flag = , idle_period_time = +##################################################################################################################### +target halted due to debug-request, current mode: Thread +xPSR: 0x01000000 pc: 0x00001030 msp: 0x2001c800 +Loading section .text, size 0x29a28 lma 0x0 +Loading section .ARM.exidx, size 0x8 lma 0x29a28 +Loading section .relocate, size 0x74 lma 0x29a30 +Start address 0x00000000, load size 170660 +Transfer rate: 46 KB/sec, 13127 bytes/write. +Function "main]" not defined. +Quit +Breakpoint 1 at 0x2252: file .././main.c, line 6. +Note: automatically using hardware breakpoints for read-only addresses. +Starting program: /storage/Shared/Projects/Embedded-Graphics-Learning/software/firmware/oracle_e54_edition_pre_port/e54_gfx_learning/e54_gfx_learning/Debug/e54_gfx_learning.elf +### Output/messages ################################################################################################# + +Breakpoint 1, main () at .././main.c:6 +warning: Source file is more recent than executable. +6 oracle_init(); +### Assembly ######################################################################################################## +~ +~ +~ +~ + 0x00002250 main+0 push {r3, lr} +!0x00002252 main+2 ldr r3, [pc, #8] ; (0x225c ) + 0x00002254 main+4 blx r3 + 0x00002256 main+6 ldr r4, [pc, #8] ; (0x2260 ) + 0x00002258 main+8 blx r4 + 0x0000225a main+10 b.n 0x2258 +### Breakpoints ##################################################################################################### +[1] break at 0x00002252 in .././main.c:6 for main hit 1 time +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x00029a30 r5 0x00011065 r10 0xfffdfdff pc 0x00002252 primask 0x00 + r1 0x00000000 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x61000000 basepri 0x00 + r2 0x00f00000 r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x00002251 r8 0x2000c67c sp 0x2001c7f0 msp 0x2001c7f0 control 0x00 + r4 0x00002299 r9 0x00011fb1 lr 0x000010a1 psp 0xfdff677c +### Source ########################################################################################################## +~ +~ +~ +~ +~ + 1 #include "oracle.h" + 2 + 3 + 4 int main(void) + 5 { +! 6 oracle_init(); + 7 + 8 for(;;) + 9 { + 10 oracle_service(); + 11 } + 12 } +~ +~ +~ +### Stack ########################################################################################################### +[0] from 0x00002252 in main+2 at .././main.c:6 +### Threads ######################################################################################################### +[1] id 0 from 0x00002252 in main+2 at .././main.c:6 +### Variables ####################################################################################################### +##################################################################################################################### +### Output/messages ################################################################################################# +oracle_init () at .././oracle.c:20 +warning: Source file is more recent than executable. +20 init_mcu(); +### Assembly ######################################################################################################## +~ +~ +~ +~ + 0x00002264 oracle_init+0 push {r3, lr} + 0x00002266 oracle_init+2 ldr r3, [pc, #24] ; (0x2280 ) + 0x00002268 oracle_init+4 blx r3 + 0x0000226a oracle_init+6 ldr r3, [pc, #24] ; (0x2284 ) + 0x0000226c oracle_init+8 blx r3 + 0x0000226e oracle_init+10 ldr r3, [pc, #24] ; (0x2288 ) +### Breakpoints ##################################################################################################### +[1] break at 0x00002252 in .././main.c:6 for main hit 1 time +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x00029a30 r5 0x00011065 r10 0xfffdfdff pc 0x00002266 primask 0x00 + r1 0x00000000 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x61000000 basepri 0x00 + r2 0x00f00000 r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x00002265 r8 0x2000c67c sp 0x2001c7e8 msp 0x2001c7e8 control 0x00 + r4 0x00002299 r9 0x00011fb1 lr 0x00002257 psp 0xfdff677c +### Source ########################################################################################################## + 10 #include "p_i2c.h" + 11 #include "p_tcc.h" + 12 #include "lvgl/lvgl.h" + 13 #include "p_ssd1963.h" + 14 #include "p_screen.h" + 15 + 16 + 17 void oracle_init(void) + 18 { + 19 // init mcu + 20 init_mcu(); + 21 // uart init + 22 p_usart_init(); + 23 // i2c init + 24 p_i2c_init(); + 25 // gpio init + 26 p_gpio_init(); + 27 // time init + 28 p_tcc_init(); + 29 +### Stack ########################################################################################################### +[0] from 0x00002266 in oracle_init+2 at .././oracle.c:20 +[1] from 0x00002256 in main+6 at .././main.c:6 +### Threads ######################################################################################################### +[1] id 0 from 0x00002266 in oracle_init+2 at .././oracle.c:20 +### Variables ####################################################################################################### +##################################################################################################################### +### Output/messages ################################################################################################# +22 p_usart_init(); +### Assembly ######################################################################################################## +~ +~ + 0x00002264 oracle_init+0 push {r3, lr} + 0x00002266 oracle_init+2 ldr r3, [pc, #24] ; (0x2280 ) + 0x00002268 oracle_init+4 blx r3 + 0x0000226a oracle_init+6 ldr r3, [pc, #24] ; (0x2284 ) + 0x0000226c oracle_init+8 blx r3 + 0x0000226e oracle_init+10 ldr r3, [pc, #24] ; (0x2288 ) + 0x00002270 oracle_init+12 blx r3 + 0x00002272 oracle_init+14 ldr r3, [pc, #24] ; (0x228c ) +### Breakpoints ##################################################################################################### +[1] break at 0x00002252 in .././main.c:6 for main hit 1 time +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x00000fff r5 0x00011065 r10 0xfffdfdff pc 0x0000226a primask 0x00 + r1 0x40001c00 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x61000000 basepri 0x00 + r2 0x00003ffd r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x00001c39 r8 0x2000c67c sp 0x2001c7e8 msp 0x2001c7e8 control 0x00 + r4 0x00002299 r9 0x00011fb1 lr 0x00001c5f psp 0xfdff677c +### Source ########################################################################################################## + 12 #include "lvgl/lvgl.h" + 13 #include "p_ssd1963.h" + 14 #include "p_screen.h" + 15 + 16 + 17 void oracle_init(void) + 18 { + 19 // init mcu + 20 init_mcu(); + 21 // uart init + 22 p_usart_init(); + 23 // i2c init + 24 p_i2c_init(); + 25 // gpio init + 26 p_gpio_init(); + 27 // time init + 28 p_tcc_init(); + 29 + 30 p_screen_init(); + 31 } +### Stack ########################################################################################################### +[0] from 0x0000226a in oracle_init+6 at .././oracle.c:22 +[1] from 0x00002256 in main+6 at .././main.c:6 +### Threads ######################################################################################################### +[1] id 0 from 0x0000226a in oracle_init+6 at .././oracle.c:22 +### Variables ####################################################################################################### +##################################################################################################################### +### Output/messages ################################################################################################# +24 p_i2c_init(); +### Assembly ######################################################################################################## + 0x00002264 oracle_init+0 push {r3, lr} + 0x00002266 oracle_init+2 ldr r3, [pc, #24] ; (0x2280 ) + 0x00002268 oracle_init+4 blx r3 + 0x0000226a oracle_init+6 ldr r3, [pc, #24] ; (0x2284 ) + 0x0000226c oracle_init+8 blx r3 + 0x0000226e oracle_init+10 ldr r3, [pc, #24] ; (0x2288 ) + 0x00002270 oracle_init+12 blx r3 + 0x00002272 oracle_init+14 ldr r3, [pc, #24] ; (0x228c ) + 0x00002274 oracle_init+16 blx r3 + 0x00002276 oracle_init+18 ldr r3, [pc, #24] ; (0x2290 ) +### Breakpoints ##################################################################################################### +[1] break at 0x00002252 in .././main.c:6 for main hit 1 time +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x0000000c r5 0x00011065 r10 0xfffdfdff pc 0x0000226e primask 0x00 + r1 0x00023ae0 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x21000000 basepri 0x00 + r2 0x00000001 r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x41012000 r8 0x2000c67c sp 0x2001c7e8 msp 0x2001c7e8 control 0x00 + r4 0x00002299 r9 0x00011fb1 lr 0x0000188d psp 0xfdff677c +### Source ########################################################################################################## + 14 #include "p_screen.h" + 15 + 16 + 17 void oracle_init(void) + 18 { + 19 // init mcu + 20 init_mcu(); + 21 // uart init + 22 p_usart_init(); + 23 // i2c init + 24 p_i2c_init(); + 25 // gpio init + 26 p_gpio_init(); + 27 // time init + 28 p_tcc_init(); + 29 + 30 p_screen_init(); + 31 } + 32 + 33 void oracle_service(void) +### Stack ########################################################################################################### +[0] from 0x0000226e in oracle_init+10 at .././oracle.c:24 +[1] from 0x00002256 in main+6 at .././main.c:6 +### Threads ######################################################################################################### +[1] id 0 from 0x0000226e in oracle_init+10 at .././oracle.c:24 +### Variables ####################################################################################################### +##################################################################################################################### +### Output/messages ################################################################################################# +26 p_gpio_init(); +### Assembly ######################################################################################################## + 0x00002268 oracle_init+4 blx r3 + 0x0000226a oracle_init+6 ldr r3, [pc, #24] ; (0x2284 ) + 0x0000226c oracle_init+8 blx r3 + 0x0000226e oracle_init+10 ldr r3, [pc, #24] ; (0x2288 ) + 0x00002270 oracle_init+12 blx r3 + 0x00002272 oracle_init+14 ldr r3, [pc, #24] ; (0x228c ) + 0x00002274 oracle_init+16 blx r3 + 0x00002276 oracle_init+18 ldr r3, [pc, #24] ; (0x2290 ) + 0x00002278 oracle_init+20 blx r3 + 0x0000227a oracle_init+22 ldr r3, [pc, #24] ; (0x2294 ) +### Breakpoints ##################################################################################################### +[1] break at 0x00002252 in .././main.c:6 for main hit 1 time +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x0000000c r5 0x00011065 r10 0xfffdfdff pc 0x00002272 primask 0x00 + r1 0x00023ae0 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x21000000 basepri 0x00 + r2 0x00000001 r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x00001425 r8 0x2000c67c sp 0x2001c7e8 msp 0x2001c7e8 control 0x00 + r4 0x00002299 r9 0x00011fb1 lr 0x00002273 psp 0xfdff677c +### Source ########################################################################################################## + 16 + 17 void oracle_init(void) + 18 { + 19 // init mcu + 20 init_mcu(); + 21 // uart init + 22 p_usart_init(); + 23 // i2c init + 24 p_i2c_init(); + 25 // gpio init + 26 p_gpio_init(); + 27 // time init + 28 p_tcc_init(); + 29 + 30 p_screen_init(); + 31 } + 32 + 33 void oracle_service(void) + 34 { + 35 p_screen_service(); +### Stack ########################################################################################################### +[0] from 0x00002272 in oracle_init+14 at .././oracle.c:26 +[1] from 0x00002256 in main+6 at .././main.c:6 +### Threads ######################################################################################################### +[1] id 0 from 0x00002272 in oracle_init+14 at .././oracle.c:26 +### Variables ####################################################################################################### +##################################################################################################################### +### Output/messages ################################################################################################# +28 p_tcc_init(); +### Assembly ######################################################################################################## + 0x0000226c oracle_init+8 blx r3 + 0x0000226e oracle_init+10 ldr r3, [pc, #24] ; (0x2288 ) + 0x00002270 oracle_init+12 blx r3 + 0x00002272 oracle_init+14 ldr r3, [pc, #24] ; (0x228c ) + 0x00002274 oracle_init+16 blx r3 + 0x00002276 oracle_init+18 ldr r3, [pc, #24] ; (0x2290 ) + 0x00002278 oracle_init+20 blx r3 + 0x0000227a oracle_init+22 ldr r3, [pc, #24] ; (0x2294 ) + 0x0000227c oracle_init+24 blx r3 + 0x0000227e oracle_init+26 pop {r3, pc} +### Breakpoints ##################################################################################################### +[1] break at 0x00002252 in .././main.c:6 for main hit 1 time +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x00000080 r5 0x00011065 r10 0xfffdfdff pc 0x00002276 primask 0x00 + r1 0x00000006 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x01000000 basepri 0x00 + r2 0x00000006 r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x41008000 r8 0x2000c67c sp 0x2001c7e8 msp 0x2001c7e8 control 0x00 + r4 0x00002299 r9 0x00011fb1 lr 0x0000130f psp 0xfdff677c +### Source ########################################################################################################## + 18 { + 19 // init mcu + 20 init_mcu(); + 21 // uart init + 22 p_usart_init(); + 23 // i2c init + 24 p_i2c_init(); + 25 // gpio init + 26 p_gpio_init(); + 27 // time init + 28 p_tcc_init(); + 29 + 30 p_screen_init(); + 31 } + 32 + 33 void oracle_service(void) + 34 { + 35 p_screen_service(); + 36 } +~ +### Stack ########################################################################################################### +[0] from 0x00002276 in oracle_init+18 at .././oracle.c:28 +[1] from 0x00002256 in main+6 at .././main.c:6 +### Threads ######################################################################################################### +[1] id 0 from 0x00002276 in oracle_init+18 at .././oracle.c:28 +### Variables ####################################################################################################### +##################################################################################################################### +### Output/messages ################################################################################################# +30 p_screen_init(); +### Assembly ######################################################################################################## + 0x00002270 oracle_init+12 blx r3 + 0x00002272 oracle_init+14 ldr r3, [pc, #24] ; (0x228c ) + 0x00002274 oracle_init+16 blx r3 + 0x00002276 oracle_init+18 ldr r3, [pc, #24] ; (0x2290 ) + 0x00002278 oracle_init+20 blx r3 + 0x0000227a oracle_init+22 ldr r3, [pc, #24] ; (0x2294 ) + 0x0000227c oracle_init+24 blx r3 + 0x0000227e oracle_init+26 pop {r3, pc} + 0x00002280 oracle_init+28 adds r1, r7, #0 + 0x00002282 oracle_init+30 movs r0, r0 +### Breakpoints ##################################################################################################### +[1] break at 0x00002252 in .././main.c:6 for main hit 1 time +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x00000000 r5 0x00011065 r10 0xfffdfdff pc 0x0000227a primask 0x00 + r1 0x00023ac8 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x41000000 basepri 0x00 + r2 0x40003800 r7 0x20008590 r12 0x2000c614 fpscr 0x00000000 faultmask 0x00 + r3 0x00000000 r8 0x2000c67c sp 0x2001c7e8 msp 0x2001c7e8 control 0x00 + r4 0x00002299 r9 0x00011fb1 lr 0x00001745 psp 0xfdff677c +### Source ########################################################################################################## + 20 init_mcu(); + 21 // uart init + 22 p_usart_init(); + 23 // i2c init + 24 p_i2c_init(); + 25 // gpio init + 26 p_gpio_init(); + 27 // time init + 28 p_tcc_init(); + 29 + 30 p_screen_init(); + 31 } + 32 + 33 void oracle_service(void) + 34 { + 35 p_screen_service(); + 36 } +~ +~ +~ +### Stack ########################################################################################################### +[0] from 0x0000227a in oracle_init+22 at .././oracle.c:30 +[1] from 0x00002256 in main+6 at .././main.c:6 +### Threads ######################################################################################################### +[1] id 0 from 0x0000227a in oracle_init+22 at .././oracle.c:30 +### Variables ####################################################################################################### +##################################################################################################################### +### Output/messages ################################################################################################# +main () at .././main.c:10 +10 oracle_service(); +### Assembly ######################################################################################################## +~ +~ + 0x00002250 main+0 push {r3, lr} +!0x00002252 main+2 ldr r3, [pc, #8] ; (0x225c ) + 0x00002254 main+4 blx r3 + 0x00002256 main+6 ldr r4, [pc, #8] ; (0x2260 ) + 0x00002258 main+8 blx r4 + 0x0000225a main+10 b.n 0x2258 + 0x0000225c main+12 movs r2, #101 ; 0x65 + 0x0000225e main+14 movs r0, r0 +### Breakpoints ##################################################################################################### +[1] break at 0x00002252 in .././main.c:6 for main hit 1 time +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x00000001 r5 0x00011065 r10 0xfffdfdff pc 0x00002256 primask 0x00 + r1 0x20008fe8 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x81000000 basepri 0x00 + r2 0x00000000 r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x00002265 r8 0x2000c67c sp 0x2001c7f0 msp 0x2001c7f0 control 0x00 + r4 0x00002299 r9 0x00011fb1 lr 0x00005eb5 psp 0xfdff677c +### Source ########################################################################################################## +~ + 1 #include "oracle.h" + 2 + 3 + 4 int main(void) + 5 { +! 6 oracle_init(); + 7 + 8 for(;;) + 9 { + 10 oracle_service(); + 11 } + 12 } +~ +~ +~ +~ +~ +~ +~ +### Stack ########################################################################################################### +[0] from 0x00002256 in main+6 at .././main.c:10 +### Threads ######################################################################################################### +[1] id 0 from 0x00002256 in main+6 at .././main.c:10 +### Variables ####################################################################################################### +##################################################################################################################### +Continuing. +### Output/messages ################################################################################################# + +Program received signal SIGINT, Interrupt. +0x0001104e in lv_tick_get () at ../thirdparty/lvgl/src/lv_hal/lv_hal_tick.c:61 +warning: Source file is more recent than executable. +61 tick_irq_flag = 1; +### Assembly ######################################################################################################## +~ +~ +~ +~ + 0x0001104c lv_tick_get+0 ldr r3, [pc, #16] ; (0x11060 ) + 0x0001104e lv_tick_get+2 mov.w r1, #1 + 0x00011052 lv_tick_get+6 strb r1, [r3, #0] + 0x00011054 lv_tick_get+8 ldrb r2, [r3, #0] + 0x00011056 lv_tick_get+10 cmp r2, #0 + 0x00011058 lv_tick_get+12 beq.n 0x11052 +### Breakpoints ##################################################################################################### +[1] break at 0x00002252 in .././main.c:6 for main hit 1 time +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x0000a604 r5 0x00011065 r10 0xfffdfdff pc 0x0001104e primask 0x00 + r1 0x00000001 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x61000000 basepri 0x00 + r2 0x00000001 r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x20008570 r8 0x2000c67c sp 0x2001c7b8 msp 0x2001c7b8 control 0x00 + r4 0x0000a604 r9 0x00011fb1 lr 0x0001106d psp 0xfdff677c +### Source ########################################################################################################## + 51 + 52 /** + 53 * Get the elapsed milliseconds since start up + 54 * @return the elapsed milliseconds + 55 */ + 56 uint32_t lv_tick_get(void) + 57 { + 58 #if LV_TICK_CUSTOM == 0 + 59 uint32_t result; + 60 do { + 61 tick_irq_flag = 1; + 62 result = sys_time; + 63 } while(!tick_irq_flag); /*'lv_tick_inc()' clears this flag which can be in an interrupt. + 64 Continue until make a non interrupted cycle */ + 65 + 66 return result; + 67 #else + 68 return LV_TICK_CUSTOM_SYS_TIME_EXPR; + 69 #endif + 70 } +### Stack ########################################################################################################### +[0] from 0x0001104e in lv_tick_get+2 at ../thirdparty/lvgl/src/lv_hal/lv_hal_tick.c:61 +[1] from 0x0001106c in lv_tick_elaps+8 at ../thirdparty/lvgl/src/lv_hal/lv_hal_tick.c:79 +[2] from 0x0001386a in lv_task_handler+170 at ../thirdparty/lvgl/src/lv_misc/lv_task.c:169 +[3] from 0x00001026 in p_screen_service+6 at ../devices/p_screen.c:43 +[4] from 0x0000229e in oracle_service+6 at .././oracle.c:35 +[5] from 0x0000225a in main+10 at .././main.c:10 +### Threads ######################################################################################################### +[1] id 0 from 0x0001104e in lv_tick_get+2 at ../thirdparty/lvgl/src/lv_hal/lv_hal_tick.c:61 +### Variables ####################################################################################################### +loc result = 42559 +##################################################################################################################### +Detaching from program: /storage/Shared/Projects/Embedded-Graphics-Learning/software/firmware/oracle_e54_edition_pre_port/e54_gfx_learning/e54_gfx_learning/Debug/e54_gfx_learning.elf, Remote target +[Inferior 1 (Remote target) detached] +0x0001104e in lv_tick_get () at ../thirdparty/lvgl/src/lv_hal/lv_hal_tick.c:61 +warning: Source file is more recent than executable. +61 tick_irq_flag = 1; +### Assembly ######################################################################################################## +~ +~ +~ +~ + 0x0001104c lv_tick_get+0 ldr r3, [pc, #16] ; (0x11060 ) + 0x0001104e lv_tick_get+2 mov.w r1, #1 + 0x00011052 lv_tick_get+6 strb r1, [r3, #0] + 0x00011054 lv_tick_get+8 ldrb r2, [r3, #0] + 0x00011056 lv_tick_get+10 cmp r2, #0 + 0x00011058 lv_tick_get+12 beq.n 0x11052 +### Breakpoints ##################################################################################################### +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x0000a604 r5 0x00011065 r10 0xfffdfdff pc 0x0001104e primask 0x00 + r1 0x00000001 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x61000000 basepri 0x00 + r2 0x00000001 r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x20008570 r8 0x2000c67c sp 0x2001c7b8 msp 0x2001c7b8 control 0x00 + r4 0x0000a604 r9 0x00011fb1 lr 0x0001106d psp 0xfdff677c +### Source ########################################################################################################## + 51 + 52 /** + 53 * Get the elapsed milliseconds since start up + 54 * @return the elapsed milliseconds + 55 */ + 56 uint32_t lv_tick_get(void) + 57 { + 58 #if LV_TICK_CUSTOM == 0 + 59 uint32_t result; + 60 do { + 61 tick_irq_flag = 1; + 62 result = sys_time; + 63 } while(!tick_irq_flag); /*'lv_tick_inc()' clears this flag which can be in an interrupt. + 64 Continue until make a non interrupted cycle */ + 65 + 66 return result; + 67 #else + 68 return LV_TICK_CUSTOM_SYS_TIME_EXPR; + 69 #endif + 70 } +### Stack ########################################################################################################### +[0] from 0x0001104e in lv_tick_get+2 at ../thirdparty/lvgl/src/lv_hal/lv_hal_tick.c:61 +[1] from 0x0001106c in lv_tick_elaps+8 at ../thirdparty/lvgl/src/lv_hal/lv_hal_tick.c:79 +[2] from 0x0001386a in lv_task_handler+170 at ../thirdparty/lvgl/src/lv_misc/lv_task.c:169 +[3] from 0x00001026 in p_screen_service+6 at ../devices/p_screen.c:43 +[4] from 0x0000229e in oracle_service+6 at .././oracle.c:35 +[5] from 0x0000225a in main+10 at .././main.c:10 +### Threads ######################################################################################################### +[1] id 0 from 0x0001104e in lv_tick_get+2 at ../thirdparty/lvgl/src/lv_hal/lv_hal_tick.c:61 +### Variables ####################################################################################################### +loc result = 42559 +##################################################################################################################### +Loading section .text, size 0x29a28 lma 0x0 +Loading section .ARM.exidx, size 0x8 lma 0x29a28 +Loading section .relocate, size 0x74 lma 0x29a30 +Start address 0x00000000, load size 170660 +Transfer rate: 46 KB/sec, 13127 bytes/write. +A debugging session is active. + + Inferior 1 [Remote target] will be detached. + +Quit anyway? (y or n) [answered Y; input not from terminal] +[Inferior 1 (Remote target) detached] +lv_task_handler () at ../thirdparty/lvgl/src/lv_misc/lv_task.c:71 +warning: Source file is more recent than executable. +71 { +### Assembly ######################################################################################################## +~ +~ +~ +~ +~ + 0x000137c0 lv_task_handler+0 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 0x000137c4 lv_task_handler+4 ldr r3, [pc, #352] ; (0x13928 ) + 0x000137c6 lv_task_handler+6 ldrb r3, [r3, #4] + 0x000137c8 lv_task_handler+8 cmp r3, #0 + 0x000137ca lv_task_handler+10 bne.w 0x13920 +### Breakpoints ##################################################################################################### +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0xffffffff r5 0x00011065 r10 0xfffdfdff pc 0x000137c0 primask 0x00 + r1 0x20008590 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x41000000 basepri 0x00 + r2 0x00000000 r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x000137c1 r8 0x2000c67c sp 0x2001c7e0 msp 0x2001c7e0 control 0x00 + r4 0x00002299 r9 0x00011fb1 lr 0x00001027 psp 0xfdff677c +### Source ########################################################################################################## + 61 task_list_changed = false; + 62 /*Initially enable the lv_task handling*/ + 63 lv_task_enable(true); + 64 } + 65 + 66 /** + 67 * Call it periodically to handle lv_tasks. + 68 * @return the time after which it must be called again + 69 */ + 70 LV_ATTRIBUTE_TASK_HANDLER uint32_t lv_task_handler(void) + 71 { + 72 + 73 + 74 LV_LOG_TRACE("lv_task_handler started"); + 75 + 76 /*Avoid concurrent running of the task handler*/ + 77 static bool already_running = false; + 78 if(already_running) return 1; + 79 already_running = true; + 80 +### Stack ########################################################################################################### +[0] from 0x000137c0 in lv_task_handler+0 at ../thirdparty/lvgl/src/lv_misc/lv_task.c:71 +[1] from 0x00001026 in p_screen_service+6 at ../devices/p_screen.c:43 +[2] from 0x0000229e in oracle_service+6 at .././oracle.c:35 +[3] from 0x0000225a in main+10 at .././main.c:10 +### Threads ######################################################################################################### +[1] id 0 from 0x000137c0 in lv_task_handler+0 at ../thirdparty/lvgl/src/lv_misc/lv_task.c:71 +### Variables ####################################################################################################### +loc already_running = false, idle_period_start = 111000, handler_start = 111482, busy_time = 169, time_till_next = 4294967295, task_interrupter = , next = , end_flag = , idle_period_time = +##################################################################################################################### +target halted due to debug-request, current mode: Thread +xPSR: 0x01000000 pc: 0x00001030 msp: 0x2001c800 +Loading section .text, size 0x29a28 lma 0x0 +Loading section .ARM.exidx, size 0x8 lma 0x29a28 +Loading section .relocate, size 0x74 lma 0x29a30 +Start address 0x00000000, load size 170660 +Transfer rate: 46 KB/sec, 13127 bytes/write. +Breakpoint 1 at 0x2252: file .././main.c, line 6. +Note: automatically using hardware breakpoints for read-only addresses. +Starting program: /storage/Shared/Projects/Embedded-Graphics-Learning/software/firmware/oracle_e54_edition_pre_port/e54_gfx_learning/e54_gfx_learning/Debug/e54_gfx_learning.elf +### Output/messages ################################################################################################# + +Breakpoint 1, main () at .././main.c:6 +warning: Source file is more recent than executable. +6 oracle_init(); +### Assembly ######################################################################################################## +~ +~ +~ +~ + 0x00002250 main+0 push {r3, lr} +!0x00002252 main+2 ldr r3, [pc, #8] ; (0x225c ) + 0x00002254 main+4 blx r3 + 0x00002256 main+6 ldr r4, [pc, #8] ; (0x2260 ) + 0x00002258 main+8 blx r4 + 0x0000225a main+10 b.n 0x2258 +### Breakpoints ##################################################################################################### +[1] break at 0x00002252 in .././main.c:6 for main hit 1 time +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x00029a30 r5 0x00011065 r10 0xfffdfdff pc 0x00002252 primask 0x00 + r1 0x00000000 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x61000000 basepri 0x00 + r2 0x00f00000 r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x00002251 r8 0x2000c67c sp 0x2001c7f0 msp 0x2001c7f0 control 0x00 + r4 0x00002299 r9 0x00011fb1 lr 0x000010a1 psp 0xfdff677c +### Source ########################################################################################################## +~ +~ +~ +~ +~ + 1 #include "oracle.h" + 2 + 3 + 4 int main(void) + 5 { +! 6 oracle_init(); + 7 + 8 for(;;) + 9 { + 10 oracle_service(); + 11 } + 12 } +~ +~ +~ +### Stack ########################################################################################################### +[0] from 0x00002252 in main+2 at .././main.c:6 +### Threads ######################################################################################################### +[1] id 0 from 0x00002252 in main+2 at .././main.c:6 +### Variables ####################################################################################################### +##################################################################################################################### +### Output/messages ################################################################################################# +oracle_init () at .././oracle.c:20 +warning: Source file is more recent than executable. +20 init_mcu(); +### Assembly ######################################################################################################## +~ +~ +~ +~ + 0x00002264 oracle_init+0 push {r3, lr} + 0x00002266 oracle_init+2 ldr r3, [pc, #24] ; (0x2280 ) + 0x00002268 oracle_init+4 blx r3 + 0x0000226a oracle_init+6 ldr r3, [pc, #24] ; (0x2284 ) + 0x0000226c oracle_init+8 blx r3 + 0x0000226e oracle_init+10 ldr r3, [pc, #24] ; (0x2288 ) +### Breakpoints ##################################################################################################### +[1] break at 0x00002252 in .././main.c:6 for main hit 1 time +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x00029a30 r5 0x00011065 r10 0xfffdfdff pc 0x00002266 primask 0x00 + r1 0x00000000 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x61000000 basepri 0x00 + r2 0x00f00000 r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x00002265 r8 0x2000c67c sp 0x2001c7e8 msp 0x2001c7e8 control 0x00 + r4 0x00002299 r9 0x00011fb1 lr 0x00002257 psp 0xfdff677c +### Source ########################################################################################################## + 10 #include "p_i2c.h" + 11 #include "p_tcc.h" + 12 #include "lvgl/lvgl.h" + 13 #include "p_ssd1963.h" + 14 #include "p_screen.h" + 15 + 16 + 17 void oracle_init(void) + 18 { + 19 // init mcu + 20 init_mcu(); + 21 // uart init + 22 p_usart_init(); + 23 // i2c init + 24 p_i2c_init(); + 25 // gpio init + 26 p_gpio_init(); + 27 // time init + 28 p_tcc_init(); + 29 +### Stack ########################################################################################################### +[0] from 0x00002266 in oracle_init+2 at .././oracle.c:20 +[1] from 0x00002256 in main+6 at .././main.c:6 +### Threads ######################################################################################################### +[1] id 0 from 0x00002266 in oracle_init+2 at .././oracle.c:20 +### Variables ####################################################################################################### +##################################################################################################################### +### Output/messages ################################################################################################# +22 p_usart_init(); +### Assembly ######################################################################################################## +~ +~ + 0x00002264 oracle_init+0 push {r3, lr} + 0x00002266 oracle_init+2 ldr r3, [pc, #24] ; (0x2280 ) + 0x00002268 oracle_init+4 blx r3 + 0x0000226a oracle_init+6 ldr r3, [pc, #24] ; (0x2284 ) + 0x0000226c oracle_init+8 blx r3 + 0x0000226e oracle_init+10 ldr r3, [pc, #24] ; (0x2288 ) + 0x00002270 oracle_init+12 blx r3 + 0x00002272 oracle_init+14 ldr r3, [pc, #24] ; (0x228c ) +### Breakpoints ##################################################################################################### +[1] break at 0x00002252 in .././main.c:6 for main hit 1 time +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x00000fff r5 0x00011065 r10 0xfffdfdff pc 0x0000226a primask 0x00 + r1 0x40001c00 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x61000000 basepri 0x00 + r2 0x00003ffd r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x00001c39 r8 0x2000c67c sp 0x2001c7e8 msp 0x2001c7e8 control 0x00 + r4 0x00002299 r9 0x00011fb1 lr 0x00001c5f psp 0xfdff677c +### Source ########################################################################################################## + 12 #include "lvgl/lvgl.h" + 13 #include "p_ssd1963.h" + 14 #include "p_screen.h" + 15 + 16 + 17 void oracle_init(void) + 18 { + 19 // init mcu + 20 init_mcu(); + 21 // uart init + 22 p_usart_init(); + 23 // i2c init + 24 p_i2c_init(); + 25 // gpio init + 26 p_gpio_init(); + 27 // time init + 28 p_tcc_init(); + 29 + 30 p_screen_init(); + 31 } +### Stack ########################################################################################################### +[0] from 0x0000226a in oracle_init+6 at .././oracle.c:22 +[1] from 0x00002256 in main+6 at .././main.c:6 +### Threads ######################################################################################################### +[1] id 0 from 0x0000226a in oracle_init+6 at .././oracle.c:22 +### Variables ####################################################################################################### +##################################################################################################################### +### Output/messages ################################################################################################# +p_usart_init () at ../drivers/p_usart.c:13 +warning: Source file is more recent than executable. +13 hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); +### Assembly ######################################################################################################## +~ +~ +~ + 0x000014c4 p_usart_init+0 push {r4, r5, lr} + 0x000014c6 p_usart_init+2 sub sp, #12 + 0x000014c8 p_usart_init+4 ldr r3, [pc, #124] ; (0x1548 ) + 0x000014ca p_usart_init+6 movs r2, #64 ; 0x40 + 0x000014cc p_usart_init+8 str.w r2, [r3, #220] ; 0xdc + 0x000014d0 p_usart_init+12 movs r2, #67 ; 0x43 + 0x000014d2 p_usart_init+14 str.w r2, [r3, #140] ; 0x8c +### Breakpoints ##################################################################################################### +[1] break at 0x00002252 in .././main.c:6 for main hit 1 time +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x00000fff r5 0x00011065 r10 0xfffdfdff pc 0x000014c8 primask 0x00 + r1 0x40001c00 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x61000000 basepri 0x00 + r2 0x00003ffd r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x000014c5 r8 0x2000c67c sp 0x2001c7d0 msp 0x2001c7d0 control 0x00 + r4 0x00002299 r9 0x00011fb1 lr 0x0000226f psp 0xfdff677c +### Source ########################################################################################################## + 3 #define DEBUG_USART_EX_BUFF_SIZE 16 + 4 struct usart_async_descriptor p_usart_debug_inst; + 5 + 6 static uint8_t example_USART_0[12] = "Hello World!"; + 7 + 8 static uint8_t debug_buffer[DEBUG_MAX_BUFFER_SIZE]; + 9 static uint8_t debug_rx_buff[DEBUG_USART_EX_BUFF_SIZE]; + 10 void p_usart_init(void) + 11 { + 12 // clock init + 13 hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + 14 hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + 15 + 16 hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK); + 17 + 18 usart_async_init(&p_usart_debug_inst, USART_DEBUG_SERCOM, debug_rx_buff, DEBUG_USART_EX_BUFF_SIZE, (void*)NULL); + 19 + 20 // port init + 21 gpio_set_pin_function(USART_DEBUG_RX, USART_DEBUG_RX_MUX); + 22 gpio_set_pin_function(USART_DEBUG_TX, USART_DEBUG_TX_MUX); +### Stack ########################################################################################################### +[0] from 0x000014c8 in p_usart_init+4 at ../drivers/p_usart.c:13 +[1] from 0x0000226e in oracle_init+10 at .././oracle.c:22 +[2] from 0x00002256 in main+6 at .././main.c:6 +### Threads ######################################################################################################### +[1] id 0 from 0x000014c8 in p_usart_init+4 at ../drivers/p_usart.c:13 +### Variables ####################################################################################################### +##################################################################################################################### +### Output/messages ################################################################################################# +14 hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); +### Assembly ######################################################################################################## + 0x000014c4 p_usart_init+0 push {r4, r5, lr} + 0x000014c6 p_usart_init+2 sub sp, #12 + 0x000014c8 p_usart_init+4 ldr r3, [pc, #124] ; (0x1548 ) + 0x000014ca p_usart_init+6 movs r2, #64 ; 0x40 + 0x000014cc p_usart_init+8 str.w r2, [r3, #220] ; 0xdc + 0x000014d0 p_usart_init+12 movs r2, #67 ; 0x43 + 0x000014d2 p_usart_init+14 str.w r2, [r3, #140] ; 0x8c + 0x000014d6 p_usart_init+18 ldr r2, [pc, #116] ; (0x154c ) + 0x000014d8 p_usart_init+20 ldr r3, [r2, #24] + 0x000014da p_usart_init+22 orr.w r3, r3, #512 ; 0x200 +### Breakpoints ##################################################################################################### +[1] break at 0x00002252 in .././main.c:6 for main hit 1 time +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x00000fff r5 0x00011065 r10 0xfffdfdff pc 0x000014d0 primask 0x00 + r1 0x40001c00 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x21000000 basepri 0x00 + r2 0x00000040 r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x40001c00 r8 0x2000c67c sp 0x2001c7d0 msp 0x2001c7d0 control 0x00 + r4 0x00002299 r9 0x00011fb1 lr 0x0000226f psp 0xfdff677c +### Source ########################################################################################################## + 4 struct usart_async_descriptor p_usart_debug_inst; + 5 + 6 static uint8_t example_USART_0[12] = "Hello World!"; + 7 + 8 static uint8_t debug_buffer[DEBUG_MAX_BUFFER_SIZE]; + 9 static uint8_t debug_rx_buff[DEBUG_USART_EX_BUFF_SIZE]; + 10 void p_usart_init(void) + 11 { + 12 // clock init + 13 hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + 14 hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + 15 + 16 hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK); + 17 + 18 usart_async_init(&p_usart_debug_inst, USART_DEBUG_SERCOM, debug_rx_buff, DEBUG_USART_EX_BUFF_SIZE, (void*)NULL); + 19 + 20 // port init + 21 gpio_set_pin_function(USART_DEBUG_RX, USART_DEBUG_RX_MUX); + 22 gpio_set_pin_function(USART_DEBUG_TX, USART_DEBUG_TX_MUX); + 23 +### Stack ########################################################################################################### +[0] from 0x000014d0 in p_usart_init+12 at ../drivers/p_usart.c:14 +[1] from 0x0000226e in oracle_init+10 at .././oracle.c:22 +[2] from 0x00002256 in main+6 at .././main.c:6 +### Threads ######################################################################################################### +[1] id 0 from 0x000014d0 in p_usart_init+12 at ../drivers/p_usart.c:14 +### Variables ####################################################################################################### +##################################################################################################################### +### Output/messages ################################################################################################# +16 hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK); +### Assembly ######################################################################################################## + 0x000014c8 p_usart_init+4 ldr r3, [pc, #124] ; (0x1548 ) + 0x000014ca p_usart_init+6 movs r2, #64 ; 0x40 + 0x000014cc p_usart_init+8 str.w r2, [r3, #220] ; 0xdc + 0x000014d0 p_usart_init+12 movs r2, #67 ; 0x43 + 0x000014d2 p_usart_init+14 str.w r2, [r3, #140] ; 0x8c + 0x000014d6 p_usart_init+18 ldr r2, [pc, #116] ; (0x154c ) + 0x000014d8 p_usart_init+20 ldr r3, [r2, #24] + 0x000014da p_usart_init+22 orr.w r3, r3, #512 ; 0x200 + 0x000014de p_usart_init+26 str r3, [r2, #24] + 0x000014e0 p_usart_init+28 ldr r4, [pc, #108] ; (0x1550 ) +### Breakpoints ##################################################################################################### +[1] break at 0x00002252 in .././main.c:6 for main hit 1 time +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x00000fff r5 0x00011065 r10 0xfffdfdff pc 0x000014d6 primask 0x00 + r1 0x40001c00 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x21000000 basepri 0x00 + r2 0x00000043 r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x40001c00 r8 0x2000c67c sp 0x2001c7d0 msp 0x2001c7d0 control 0x00 + r4 0x00002299 r9 0x00011fb1 lr 0x0000226f psp 0xfdff677c +### Source ########################################################################################################## + 6 static uint8_t example_USART_0[12] = "Hello World!"; + 7 + 8 static uint8_t debug_buffer[DEBUG_MAX_BUFFER_SIZE]; + 9 static uint8_t debug_rx_buff[DEBUG_USART_EX_BUFF_SIZE]; + 10 void p_usart_init(void) + 11 { + 12 // clock init + 13 hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + 14 hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + 15 + 16 hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK); + 17 + 18 usart_async_init(&p_usart_debug_inst, USART_DEBUG_SERCOM, debug_rx_buff, DEBUG_USART_EX_BUFF_SIZE, (void*)NULL); + 19 + 20 // port init + 21 gpio_set_pin_function(USART_DEBUG_RX, USART_DEBUG_RX_MUX); + 22 gpio_set_pin_function(USART_DEBUG_TX, USART_DEBUG_TX_MUX); + 23 + 24 usart_async_enable(&p_usart_debug_inst); + 25 +### Stack ########################################################################################################### +[0] from 0x000014d6 in p_usart_init+18 at ../drivers/p_usart.c:16 +[1] from 0x0000226e in oracle_init+10 at .././oracle.c:22 +[2] from 0x00002256 in main+6 at .././main.c:6 +### Threads ######################################################################################################### +[1] id 0 from 0x000014d6 in p_usart_init+18 at ../drivers/p_usart.c:16 +### Variables ####################################################################################################### +##################################################################################################################### +### Output/messages ################################################################################################# +18 usart_async_init(&p_usart_debug_inst, USART_DEBUG_SERCOM, debug_rx_buff, DEBUG_USART_EX_BUFF_SIZE, (void*)NULL); +### Assembly ######################################################################################################## + 0x000014d2 p_usart_init+14 str.w r2, [r3, #140] ; 0x8c + 0x000014d6 p_usart_init+18 ldr r2, [pc, #116] ; (0x154c ) + 0x000014d8 p_usart_init+20 ldr r3, [r2, #24] + 0x000014da p_usart_init+22 orr.w r3, r3, #512 ; 0x200 + 0x000014de p_usart_init+26 str r3, [r2, #24] + 0x000014e0 p_usart_init+28 ldr r4, [pc, #108] ; (0x1550 ) + 0x000014e2 p_usart_init+30 movs r3, #0 + 0x000014e4 p_usart_init+32 str r3, [sp, #0] + 0x000014e6 p_usart_init+34 movs r3, #16 + 0x000014e8 p_usart_init+36 ldr r2, [pc, #104] ; (0x1554 ) +### Breakpoints ##################################################################################################### +[1] break at 0x00002252 in .././main.c:6 for main hit 1 time +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x00000fff r5 0x00011065 r10 0xfffdfdff pc 0x000014e0 primask 0x00 + r1 0x40001c00 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x21000000 basepri 0x00 + r2 0x40000800 r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x00018256 r8 0x2000c67c sp 0x2001c7d0 msp 0x2001c7d0 control 0x00 + r4 0x00002299 r9 0x00011fb1 lr 0x0000226f psp 0xfdff677c +### Source ########################################################################################################## + 8 static uint8_t debug_buffer[DEBUG_MAX_BUFFER_SIZE]; + 9 static uint8_t debug_rx_buff[DEBUG_USART_EX_BUFF_SIZE]; + 10 void p_usart_init(void) + 11 { + 12 // clock init + 13 hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + 14 hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + 15 + 16 hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK); + 17 + 18 usart_async_init(&p_usart_debug_inst, USART_DEBUG_SERCOM, debug_rx_buff, DEBUG_USART_EX_BUFF_SIZE, (void*)NULL); + 19 + 20 // port init + 21 gpio_set_pin_function(USART_DEBUG_RX, USART_DEBUG_RX_MUX); + 22 gpio_set_pin_function(USART_DEBUG_TX, USART_DEBUG_TX_MUX); + 23 + 24 usart_async_enable(&p_usart_debug_inst); + 25 + 26 io_write(&p_usart_debug_inst.io, example_USART_0, 12); + 27 +### Stack ########################################################################################################### +[0] from 0x000014e0 in p_usart_init+28 at ../drivers/p_usart.c:18 +[1] from 0x0000226e in oracle_init+10 at .././oracle.c:22 +[2] from 0x00002256 in main+6 at .././main.c:6 +### Threads ######################################################################################################### +[1] id 0 from 0x000014e0 in p_usart_init+28 at ../drivers/p_usart.c:18 +### Variables ####################################################################################################### +##################################################################################################################### +### Output/messages ################################################################################################# +21 gpio_set_pin_function(USART_DEBUG_RX, USART_DEBUG_RX_MUX); +### Assembly ######################################################################################################## + 0x000014e8 p_usart_init+36 ldr r2, [pc, #104] ; (0x1554 ) + 0x000014ea p_usart_init+38 ldr r1, [pc, #108] ; (0x1558 ) + 0x000014ec p_usart_init+40 mov r0, r4 + 0x000014ee p_usart_init+42 ldr r5, [pc, #108] ; (0x155c ) + 0x000014f0 p_usart_init+44 blx r5 + 0x000014f2 p_usart_init+46 ldr r3, [pc, #108] ; (0x1560 ) + 0x000014f4 p_usart_init+48 ldrb.w r2, [r3, #216] ; 0xd8 + 0x000014f8 p_usart_init+52 and.w r2, r2, #254 ; 0xfe + 0x000014fc p_usart_init+56 orr.w r2, r2, #1 + 0x00001500 p_usart_init+60 strb.w r2, [r3, #216] ; 0xd8 +### Breakpoints ##################################################################################################### +[1] break at 0x00002252 in .././main.c:6 for main hit 1 time +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x00000000 r5 0x000019b9 r10 0xfffdfdff pc 0x000014f2 primask 0x00 + r1 0x0000003a r6 0x00000000 r11 0xfb9ff7bf xPSR 0x61000000 basepri 0x00 + r2 0x0000181d r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x00000010 r8 0x2000c67c sp 0x2001c7d0 msp 0x2001c7d0 control 0x00 + r4 0x2000c61c r9 0x00011fb1 lr 0x00001e0f psp 0xfdff677c +### Source ########################################################################################################## + 11 { + 12 // clock init + 13 hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + 14 hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + 15 + 16 hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK); + 17 + 18 usart_async_init(&p_usart_debug_inst, USART_DEBUG_SERCOM, debug_rx_buff, DEBUG_USART_EX_BUFF_SIZE, (void*)NULL); + 19 + 20 // port init + 21 gpio_set_pin_function(USART_DEBUG_RX, USART_DEBUG_RX_MUX); + 22 gpio_set_pin_function(USART_DEBUG_TX, USART_DEBUG_TX_MUX); + 23 + 24 usart_async_enable(&p_usart_debug_inst); + 25 + 26 io_write(&p_usart_debug_inst.io, example_USART_0, 12); + 27 + 28 + 29 } + 30 +### Stack ########################################################################################################### +[0] from 0x000014f2 in p_usart_init+46 at ../drivers/p_usart.c:21 +[1] from 0x0000226e in oracle_init+10 at .././oracle.c:22 +[2] from 0x00002256 in main+6 at .././main.c:6 +### Threads ######################################################################################################### +[1] id 0 from 0x000014f2 in p_usart_init+46 at ../drivers/p_usart.c:21 +### Variables ####################################################################################################### +##################################################################################################################### +### Output/messages ################################################################################################# +22 gpio_set_pin_function(USART_DEBUG_TX, USART_DEBUG_TX_MUX); +### Assembly ######################################################################################################## + 0x00001500 p_usart_init+60 strb.w r2, [r3, #216] ; 0xd8 + 0x00001504 p_usart_init+64 ldrb.w r2, [r3, #188] ; 0xbc + 0x00001508 p_usart_init+68 and.w r2, r2, #240 ; 0xf0 + 0x0000150c p_usart_init+72 orr.w r2, r2, #3 + 0x00001510 p_usart_init+76 strb.w r2, [r3, #188] ; 0xbc + 0x00001514 p_usart_init+80 ldrb.w r2, [r3, #217] ; 0xd9 + 0x00001518 p_usart_init+84 and.w r2, r2, #254 ; 0xfe + 0x0000151c p_usart_init+88 orr.w r2, r2, #1 + 0x00001520 p_usart_init+92 strb.w r2, [r3, #217] ; 0xd9 + 0x00001524 p_usart_init+96 ldrb.w r2, [r3, #188] ; 0xbc +### Breakpoints ##################################################################################################### +[1] break at 0x00002252 in .././main.c:6 for main hit 1 time +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x00000000 r5 0x000019b9 r10 0xfffdfdff pc 0x00001514 primask 0x00 + r1 0x0000003a r6 0x00000000 r11 0xfb9ff7bf xPSR 0x61000000 basepri 0x00 + r2 0x00000003 r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x41008000 r8 0x2000c67c sp 0x2001c7d0 msp 0x2001c7d0 control 0x00 + r4 0x2000c61c r9 0x00011fb1 lr 0x00001e0f psp 0xfdff677c +### Source ########################################################################################################## + 12 // clock init + 13 hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_CORE, CONF_GCLK_SERCOM2_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + 14 hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + 15 + 16 hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK); + 17 + 18 usart_async_init(&p_usart_debug_inst, USART_DEBUG_SERCOM, debug_rx_buff, DEBUG_USART_EX_BUFF_SIZE, (void*)NULL); + 19 + 20 // port init + 21 gpio_set_pin_function(USART_DEBUG_RX, USART_DEBUG_RX_MUX); + 22 gpio_set_pin_function(USART_DEBUG_TX, USART_DEBUG_TX_MUX); + 23 + 24 usart_async_enable(&p_usart_debug_inst); + 25 + 26 io_write(&p_usart_debug_inst.io, example_USART_0, 12); + 27 + 28 + 29 } + 30 + 31 void p_write(struct usart_async_descriptor* const inst, const uint8_t* data, uint16_t len) +### Stack ########################################################################################################### +[0] from 0x00001514 in p_usart_init+80 at ../drivers/p_usart.c:22 +[1] from 0x0000226e in oracle_init+10 at .././oracle.c:22 +[2] from 0x00002256 in main+6 at .././main.c:6 +### Threads ######################################################################################################### +[1] id 0 from 0x00001514 in p_usart_init+80 at ../drivers/p_usart.c:22 +### Variables ####################################################################################################### +##################################################################################################################### +### Output/messages ################################################################################################# +24 usart_async_enable(&p_usart_debug_inst); +### Assembly ######################################################################################################## + 0x00001520 p_usart_init+92 strb.w r2, [r3, #217] ; 0xd9 + 0x00001524 p_usart_init+96 ldrb.w r2, [r3, #188] ; 0xbc + 0x00001528 p_usart_init+100 and.w r2, r2, #15 + 0x0000152c p_usart_init+104 orr.w r2, r2, #48 ; 0x30 + 0x00001530 p_usart_init+108 strb.w r2, [r3, #188] ; 0xbc + 0x00001534 p_usart_init+112 mov r0, r4 + 0x00001536 p_usart_init+114 ldr r3, [pc, #44] ; (0x1564 ) + 0x00001538 p_usart_init+116 blx r3 + 0x0000153a p_usart_init+118 movs r2, #12 + 0x0000153c p_usart_init+120 ldr r1, [pc, #40] ; (0x1568 ) +### Breakpoints ##################################################################################################### +[1] break at 0x00002252 in .././main.c:6 for main hit 1 time +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x00000000 r5 0x000019b9 r10 0xfffdfdff pc 0x00001534 primask 0x00 + r1 0x0000003a r6 0x00000000 r11 0xfb9ff7bf xPSR 0x61000000 basepri 0x00 + r2 0x00000033 r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x41008000 r8 0x2000c67c sp 0x2001c7d0 msp 0x2001c7d0 control 0x00 + r4 0x2000c61c r9 0x00011fb1 lr 0x00001e0f psp 0xfdff677c +### Source ########################################################################################################## + 14 hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM2_GCLK_ID_SLOW, CONF_GCLK_SERCOM2_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + 15 + 16 hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK); + 17 + 18 usart_async_init(&p_usart_debug_inst, USART_DEBUG_SERCOM, debug_rx_buff, DEBUG_USART_EX_BUFF_SIZE, (void*)NULL); + 19 + 20 // port init + 21 gpio_set_pin_function(USART_DEBUG_RX, USART_DEBUG_RX_MUX); + 22 gpio_set_pin_function(USART_DEBUG_TX, USART_DEBUG_TX_MUX); + 23 + 24 usart_async_enable(&p_usart_debug_inst); + 25 + 26 io_write(&p_usart_debug_inst.io, example_USART_0, 12); + 27 + 28 + 29 } + 30 + 31 void p_write(struct usart_async_descriptor* const inst, const uint8_t* data, uint16_t len) + 32 { + 33 +### Stack ########################################################################################################### +[0] from 0x00001534 in p_usart_init+112 at ../drivers/p_usart.c:24 +[1] from 0x0000226e in oracle_init+10 at .././oracle.c:22 +[2] from 0x00002256 in main+6 at .././main.c:6 +### Threads ######################################################################################################### +[1] id 0 from 0x00001534 in p_usart_init+112 at ../drivers/p_usart.c:24 +### Variables ####################################################################################################### +##################################################################################################################### +### Output/messages ################################################################################################# +26 io_write(&p_usart_debug_inst.io, example_USART_0, 12); +### Assembly ######################################################################################################## + 0x0000152c p_usart_init+104 orr.w r2, r2, #48 ; 0x30 + 0x00001530 p_usart_init+108 strb.w r2, [r3, #188] ; 0xbc + 0x00001534 p_usart_init+112 mov r0, r4 + 0x00001536 p_usart_init+114 ldr r3, [pc, #44] ; (0x1564 ) + 0x00001538 p_usart_init+116 blx r3 + 0x0000153a p_usart_init+118 movs r2, #12 + 0x0000153c p_usart_init+120 ldr r1, [pc, #40] ; (0x1568 ) + 0x0000153e p_usart_init+122 mov r0, r4 + 0x00001540 p_usart_init+124 ldr r3, [pc, #40] ; (0x156c ) + 0x00001542 p_usart_init+126 blx r3 +### Breakpoints ##################################################################################################### +[1] break at 0x00002252 in .././main.c:6 for main hit 1 time +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x00000000 r5 0x000019b9 r10 0xfffdfdff pc 0x0000153a primask 0x00 + r1 0x00023ae0 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x41000000 basepri 0x00 + r2 0x41012000 r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x00000000 r8 0x2000c67c sp 0x2001c7d0 msp 0x2001c7d0 control 0x00 + r4 0x2000c61c r9 0x00011fb1 lr 0x00001a63 psp 0xfdff677c +### Source ########################################################################################################## + 16 hri_mclk_set_APBBMASK_SERCOM2_bit(MCLK); + 17 + 18 usart_async_init(&p_usart_debug_inst, USART_DEBUG_SERCOM, debug_rx_buff, DEBUG_USART_EX_BUFF_SIZE, (void*)NULL); + 19 + 20 // port init + 21 gpio_set_pin_function(USART_DEBUG_RX, USART_DEBUG_RX_MUX); + 22 gpio_set_pin_function(USART_DEBUG_TX, USART_DEBUG_TX_MUX); + 23 + 24 usart_async_enable(&p_usart_debug_inst); + 25 + 26 io_write(&p_usart_debug_inst.io, example_USART_0, 12); + 27 + 28 + 29 } + 30 + 31 void p_write(struct usart_async_descriptor* const inst, const uint8_t* data, uint16_t len) + 32 { + 33 + 34 } + 35 +### Stack ########################################################################################################### +[0] from 0x0000153a in p_usart_init+118 at ../drivers/p_usart.c:26 +[1] from 0x0000226e in oracle_init+10 at .././oracle.c:22 +[2] from 0x00002256 in main+6 at .././main.c:6 +### Threads ######################################################################################################### +[1] id 0 from 0x0000153a in p_usart_init+118 at ../drivers/p_usart.c:26 +### Variables ####################################################################################################### +##################################################################################################################### +### Output/messages ################################################################################################# +29 } +### Assembly ######################################################################################################## + 0x0000153a p_usart_init+118 movs r2, #12 + 0x0000153c p_usart_init+120 ldr r1, [pc, #40] ; (0x1568 ) + 0x0000153e p_usart_init+122 mov r0, r4 + 0x00001540 p_usart_init+124 ldr r3, [pc, #40] ; (0x156c ) + 0x00001542 p_usart_init+126 blx r3 + 0x00001544 p_usart_init+128 add sp, #12 + 0x00001546 p_usart_init+130 pop {r4, r5, pc} + 0x00001548 p_usart_init+132 adds r0, r0, #0 + 0x0000154a p_usart_init+134 ands r0, r0 + 0x0000154c p_usart_init+136 lsrs r0, r0, #32 +### Breakpoints ##################################################################################################### +[1] break at 0x00002252 in .././main.c:6 for main hit 1 time +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x0000000c r5 0x000019b9 r10 0xfffdfdff pc 0x00001544 primask 0x00 + r1 0x00023ae0 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x21000000 basepri 0x00 + r2 0x00000001 r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x41012000 r8 0x2000c67c sp 0x2001c7d0 msp 0x2001c7d0 control 0x00 + r4 0x2000c61c r9 0x00011fb1 lr 0x0000188d psp 0xfdff677c +### Source ########################################################################################################## + 19 + 20 // port init + 21 gpio_set_pin_function(USART_DEBUG_RX, USART_DEBUG_RX_MUX); + 22 gpio_set_pin_function(USART_DEBUG_TX, USART_DEBUG_TX_MUX); + 23 + 24 usart_async_enable(&p_usart_debug_inst); + 25 + 26 io_write(&p_usart_debug_inst.io, example_USART_0, 12); + 27 + 28 + 29 } + 30 + 31 void p_write(struct usart_async_descriptor* const inst, const uint8_t* data, uint16_t len) + 32 { + 33 + 34 } + 35 + 36 void p_debug(const char* str, ...) + 37 { + 38 +### Stack ########################################################################################################### +[0] from 0x00001544 in p_usart_init+128 at ../drivers/p_usart.c:29 +[1] from 0x0000226e in oracle_init+10 at .././oracle.c:22 +[2] from 0x00002256 in main+6 at .././main.c:6 +### Threads ######################################################################################################### +[1] id 0 from 0x00001544 in p_usart_init+128 at ../drivers/p_usart.c:29 +### Variables ####################################################################################################### +##################################################################################################################### +Starting program: /storage/Shared/Projects/Embedded-Graphics-Learning/software/firmware/oracle_e54_edition_pre_port/e54_gfx_learning/e54_gfx_learning/Debug/e54_gfx_learning.elf +### Output/messages ################################################################################################# + +Breakpoint 1, main () at .././main.c:6 +6 oracle_init(); +### Assembly ######################################################################################################## +~ +~ +~ +~ + 0x00002250 main+0 push {r3, lr} +!0x00002252 main+2 ldr r3, [pc, #8] ; (0x225c ) + 0x00002254 main+4 blx r3 + 0x00002256 main+6 ldr r4, [pc, #8] ; (0x2260 ) + 0x00002258 main+8 blx r4 + 0x0000225a main+10 b.n 0x2258 +### Breakpoints ##################################################################################################### +[1] break at 0x00002252 in .././main.c:6 for main hit 1 time +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x00029a30 r5 0x000019b9 r10 0xfffdfdff pc 0x00002252 primask 0x00 + r1 0x00000000 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x61000000 basepri 0x00 + r2 0x00f00000 r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x00002251 r8 0x2000c67c sp 0x2001c7f0 msp 0x2001c7f0 control 0x00 + r4 0x2000c61c r9 0x00011fb1 lr 0x000010a1 psp 0xfdff677c +### Source ########################################################################################################## +~ +~ +~ +~ +~ + 1 #include "oracle.h" + 2 + 3 + 4 int main(void) + 5 { +! 6 oracle_init(); + 7 + 8 for(;;) + 9 { + 10 oracle_service(); + 11 } + 12 } +~ +~ +~ +### Stack ########################################################################################################### +[0] from 0x00002252 in main+2 at .././main.c:6 +### Threads ######################################################################################################### +[1] id 0 from 0x00002252 in main+2 at .././main.c:6 +### Variables ####################################################################################################### +##################################################################################################################### +### Output/messages ################################################################################################# +oracle_init () at .././oracle.c:20 +20 init_mcu(); +### Assembly ######################################################################################################## +~ +~ +~ +~ + 0x00002264 oracle_init+0 push {r3, lr} + 0x00002266 oracle_init+2 ldr r3, [pc, #24] ; (0x2280 ) + 0x00002268 oracle_init+4 blx r3 + 0x0000226a oracle_init+6 ldr r3, [pc, #24] ; (0x2284 ) + 0x0000226c oracle_init+8 blx r3 + 0x0000226e oracle_init+10 ldr r3, [pc, #24] ; (0x2288 ) +### Breakpoints ##################################################################################################### +[1] break at 0x00002252 in .././main.c:6 for main hit 1 time +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x00029a30 r5 0x000019b9 r10 0xfffdfdff pc 0x00002266 primask 0x00 + r1 0x00000000 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x61000000 basepri 0x00 + r2 0x00f00000 r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x00002265 r8 0x2000c67c sp 0x2001c7e8 msp 0x2001c7e8 control 0x00 + r4 0x2000c61c r9 0x00011fb1 lr 0x00002257 psp 0xfdff677c +### Source ########################################################################################################## + 10 #include "p_i2c.h" + 11 #include "p_tcc.h" + 12 #include "lvgl/lvgl.h" + 13 #include "p_ssd1963.h" + 14 #include "p_screen.h" + 15 + 16 + 17 void oracle_init(void) + 18 { + 19 // init mcu + 20 init_mcu(); + 21 // uart init + 22 p_usart_init(); + 23 // i2c init + 24 p_i2c_init(); + 25 // gpio init + 26 p_gpio_init(); + 27 // time init + 28 p_tcc_init(); + 29 +### Stack ########################################################################################################### +[0] from 0x00002266 in oracle_init+2 at .././oracle.c:20 +[1] from 0x00002256 in main+6 at .././main.c:6 +### Threads ######################################################################################################### +[1] id 0 from 0x00002266 in oracle_init+2 at .././oracle.c:20 +### Variables ####################################################################################################### +##################################################################################################################### +### Output/messages ################################################################################################# +22 p_usart_init(); +### Assembly ######################################################################################################## +~ +~ + 0x00002264 oracle_init+0 push {r3, lr} + 0x00002266 oracle_init+2 ldr r3, [pc, #24] ; (0x2280 ) + 0x00002268 oracle_init+4 blx r3 + 0x0000226a oracle_init+6 ldr r3, [pc, #24] ; (0x2284 ) + 0x0000226c oracle_init+8 blx r3 + 0x0000226e oracle_init+10 ldr r3, [pc, #24] ; (0x2288 ) + 0x00002270 oracle_init+12 blx r3 + 0x00002272 oracle_init+14 ldr r3, [pc, #24] ; (0x228c ) +### Breakpoints ##################################################################################################### +[1] break at 0x00002252 in .././main.c:6 for main hit 1 time +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x00000fff r5 0x000019b9 r10 0xfffdfdff pc 0x0000226a primask 0x00 + r1 0x40001c00 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x61000000 basepri 0x00 + r2 0x00003ffd r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x00001c39 r8 0x2000c67c sp 0x2001c7e8 msp 0x2001c7e8 control 0x00 + r4 0x2000c61c r9 0x00011fb1 lr 0x00001c5f psp 0xfdff677c +### Source ########################################################################################################## + 12 #include "lvgl/lvgl.h" + 13 #include "p_ssd1963.h" + 14 #include "p_screen.h" + 15 + 16 + 17 void oracle_init(void) + 18 { + 19 // init mcu + 20 init_mcu(); + 21 // uart init + 22 p_usart_init(); + 23 // i2c init + 24 p_i2c_init(); + 25 // gpio init + 26 p_gpio_init(); + 27 // time init + 28 p_tcc_init(); + 29 + 30 p_screen_init(); + 31 } +### Stack ########################################################################################################### +[0] from 0x0000226a in oracle_init+6 at .././oracle.c:22 +[1] from 0x00002256 in main+6 at .././main.c:6 +### Threads ######################################################################################################### +[1] id 0 from 0x0000226a in oracle_init+6 at .././oracle.c:22 +### Variables ####################################################################################################### +##################################################################################################################### +### Output/messages ################################################################################################# +24 p_i2c_init(); +### Assembly ######################################################################################################## + 0x00002264 oracle_init+0 push {r3, lr} + 0x00002266 oracle_init+2 ldr r3, [pc, #24] ; (0x2280 ) + 0x00002268 oracle_init+4 blx r3 + 0x0000226a oracle_init+6 ldr r3, [pc, #24] ; (0x2284 ) + 0x0000226c oracle_init+8 blx r3 + 0x0000226e oracle_init+10 ldr r3, [pc, #24] ; (0x2288 ) + 0x00002270 oracle_init+12 blx r3 + 0x00002272 oracle_init+14 ldr r3, [pc, #24] ; (0x228c ) + 0x00002274 oracle_init+16 blx r3 + 0x00002276 oracle_init+18 ldr r3, [pc, #24] ; (0x2290 ) +### Breakpoints ##################################################################################################### +[1] break at 0x00002252 in .././main.c:6 for main hit 1 time +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x0000000c r5 0x000019b9 r10 0xfffdfdff pc 0x0000226e primask 0x00 + r1 0x00023ae0 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x21000000 basepri 0x00 + r2 0x00000001 r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x41012000 r8 0x2000c67c sp 0x2001c7e8 msp 0x2001c7e8 control 0x00 + r4 0x2000c61c r9 0x00011fb1 lr 0x0000188d psp 0xfdff677c +### Source ########################################################################################################## + 14 #include "p_screen.h" + 15 + 16 + 17 void oracle_init(void) + 18 { + 19 // init mcu + 20 init_mcu(); + 21 // uart init + 22 p_usart_init(); + 23 // i2c init + 24 p_i2c_init(); + 25 // gpio init + 26 p_gpio_init(); + 27 // time init + 28 p_tcc_init(); + 29 + 30 p_screen_init(); + 31 } + 32 + 33 void oracle_service(void) +### Stack ########################################################################################################### +[0] from 0x0000226e in oracle_init+10 at .././oracle.c:24 +[1] from 0x00002256 in main+6 at .././main.c:6 +### Threads ######################################################################################################### +[1] id 0 from 0x0000226e in oracle_init+10 at .././oracle.c:24 +### Variables ####################################################################################################### +##################################################################################################################### +### Output/messages ################################################################################################# +26 p_gpio_init(); +### Assembly ######################################################################################################## + 0x00002268 oracle_init+4 blx r3 + 0x0000226a oracle_init+6 ldr r3, [pc, #24] ; (0x2284 ) + 0x0000226c oracle_init+8 blx r3 + 0x0000226e oracle_init+10 ldr r3, [pc, #24] ; (0x2288 ) + 0x00002270 oracle_init+12 blx r3 + 0x00002272 oracle_init+14 ldr r3, [pc, #24] ; (0x228c ) + 0x00002274 oracle_init+16 blx r3 + 0x00002276 oracle_init+18 ldr r3, [pc, #24] ; (0x2290 ) + 0x00002278 oracle_init+20 blx r3 + 0x0000227a oracle_init+22 ldr r3, [pc, #24] ; (0x2294 ) +### Breakpoints ##################################################################################################### +[1] break at 0x00002252 in .././main.c:6 for main hit 1 time +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x0000000c r5 0x000019b9 r10 0xfffdfdff pc 0x00002272 primask 0x00 + r1 0x00023ae0 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x21000000 basepri 0x00 + r2 0x00000001 r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x00001425 r8 0x2000c67c sp 0x2001c7e8 msp 0x2001c7e8 control 0x00 + r4 0x2000c61c r9 0x00011fb1 lr 0x00002273 psp 0xfdff677c +### Source ########################################################################################################## + 16 + 17 void oracle_init(void) + 18 { + 19 // init mcu + 20 init_mcu(); + 21 // uart init + 22 p_usart_init(); + 23 // i2c init + 24 p_i2c_init(); + 25 // gpio init + 26 p_gpio_init(); + 27 // time init + 28 p_tcc_init(); + 29 + 30 p_screen_init(); + 31 } + 32 + 33 void oracle_service(void) + 34 { + 35 p_screen_service(); +### Stack ########################################################################################################### +[0] from 0x00002272 in oracle_init+14 at .././oracle.c:26 +[1] from 0x00002256 in main+6 at .././main.c:6 +### Threads ######################################################################################################### +[1] id 0 from 0x00002272 in oracle_init+14 at .././oracle.c:26 +### Variables ####################################################################################################### +##################################################################################################################### +### Output/messages ################################################################################################# +28 p_tcc_init(); +### Assembly ######################################################################################################## + 0x0000226c oracle_init+8 blx r3 + 0x0000226e oracle_init+10 ldr r3, [pc, #24] ; (0x2288 ) + 0x00002270 oracle_init+12 blx r3 + 0x00002272 oracle_init+14 ldr r3, [pc, #24] ; (0x228c ) + 0x00002274 oracle_init+16 blx r3 + 0x00002276 oracle_init+18 ldr r3, [pc, #24] ; (0x2290 ) + 0x00002278 oracle_init+20 blx r3 + 0x0000227a oracle_init+22 ldr r3, [pc, #24] ; (0x2294 ) + 0x0000227c oracle_init+24 blx r3 + 0x0000227e oracle_init+26 pop {r3, pc} +### Breakpoints ##################################################################################################### +[1] break at 0x00002252 in .././main.c:6 for main hit 1 time +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x00000080 r5 0x000019b9 r10 0xfffdfdff pc 0x00002276 primask 0x00 + r1 0x00000006 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x01000000 basepri 0x00 + r2 0x00000006 r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x41008000 r8 0x2000c67c sp 0x2001c7e8 msp 0x2001c7e8 control 0x00 + r4 0x2000c61c r9 0x00011fb1 lr 0x0000130f psp 0xfdff677c +### Source ########################################################################################################## + 18 { + 19 // init mcu + 20 init_mcu(); + 21 // uart init + 22 p_usart_init(); + 23 // i2c init + 24 p_i2c_init(); + 25 // gpio init + 26 p_gpio_init(); + 27 // time init + 28 p_tcc_init(); + 29 + 30 p_screen_init(); + 31 } + 32 + 33 void oracle_service(void) + 34 { + 35 p_screen_service(); + 36 } +~ +### Stack ########################################################################################################### +[0] from 0x00002276 in oracle_init+18 at .././oracle.c:28 +[1] from 0x00002256 in main+6 at .././main.c:6 +### Threads ######################################################################################################### +[1] id 0 from 0x00002276 in oracle_init+18 at .././oracle.c:28 +### Variables ####################################################################################################### +##################################################################################################################### +### Output/messages ################################################################################################# +30 p_screen_init(); +### Assembly ######################################################################################################## + 0x00002270 oracle_init+12 blx r3 + 0x00002272 oracle_init+14 ldr r3, [pc, #24] ; (0x228c ) + 0x00002274 oracle_init+16 blx r3 + 0x00002276 oracle_init+18 ldr r3, [pc, #24] ; (0x2290 ) + 0x00002278 oracle_init+20 blx r3 + 0x0000227a oracle_init+22 ldr r3, [pc, #24] ; (0x2294 ) + 0x0000227c oracle_init+24 blx r3 + 0x0000227e oracle_init+26 pop {r3, pc} + 0x00002280 oracle_init+28 adds r1, r7, #0 + 0x00002282 oracle_init+30 movs r0, r0 +### Breakpoints ##################################################################################################### +[1] break at 0x00002252 in .././main.c:6 for main hit 1 time +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x00000000 r5 0x000019b9 r10 0xfffdfdff pc 0x0000227a primask 0x00 + r1 0x00023ac8 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x41000000 basepri 0x00 + r2 0x40003800 r7 0x20008590 r12 0x2000c614 fpscr 0x00000000 faultmask 0x00 + r3 0x00000000 r8 0x2000c67c sp 0x2001c7e8 msp 0x2001c7e8 control 0x00 + r4 0x2000c61c r9 0x00011fb1 lr 0x00001745 psp 0xfdff677c +### Source ########################################################################################################## + 20 init_mcu(); + 21 // uart init + 22 p_usart_init(); + 23 // i2c init + 24 p_i2c_init(); + 25 // gpio init + 26 p_gpio_init(); + 27 // time init + 28 p_tcc_init(); + 29 + 30 p_screen_init(); + 31 } + 32 + 33 void oracle_service(void) + 34 { + 35 p_screen_service(); + 36 } +~ +~ +~ +### Stack ########################################################################################################### +[0] from 0x0000227a in oracle_init+22 at .././oracle.c:30 +[1] from 0x00002256 in main+6 at .././main.c:6 +### Threads ######################################################################################################### +[1] id 0 from 0x0000227a in oracle_init+22 at .././oracle.c:30 +### Variables ####################################################################################################### +##################################################################################################################### +### Output/messages ################################################################################################# +main () at .././main.c:10 +10 oracle_service(); +### Assembly ######################################################################################################## +~ +~ + 0x00002250 main+0 push {r3, lr} +!0x00002252 main+2 ldr r3, [pc, #8] ; (0x225c ) + 0x00002254 main+4 blx r3 + 0x00002256 main+6 ldr r4, [pc, #8] ; (0x2260 ) + 0x00002258 main+8 blx r4 + 0x0000225a main+10 b.n 0x2258 + 0x0000225c main+12 movs r2, #101 ; 0x65 + 0x0000225e main+14 movs r0, r0 +### Breakpoints ##################################################################################################### +[1] break at 0x00002252 in .././main.c:6 for main hit 1 time +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x00000001 r5 0x000019b9 r10 0xfffdfdff pc 0x00002256 primask 0x00 + r1 0x20008fe8 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x81000000 basepri 0x00 + r2 0x00000000 r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x00002265 r8 0x2000c67c sp 0x2001c7f0 msp 0x2001c7f0 control 0x00 + r4 0x2000c61c r9 0x00011fb1 lr 0x00005eb5 psp 0xfdff677c +### Source ########################################################################################################## +~ + 1 #include "oracle.h" + 2 + 3 + 4 int main(void) + 5 { +! 6 oracle_init(); + 7 + 8 for(;;) + 9 { + 10 oracle_service(); + 11 } + 12 } +~ +~ +~ +~ +~ +~ +~ +### Stack ########################################################################################################### +[0] from 0x00002256 in main+6 at .././main.c:10 +### Threads ######################################################################################################### +[1] id 0 from 0x00002256 in main+6 at .././main.c:10 +### Variables ####################################################################################################### +##################################################################################################################### +### Output/messages ################################################################################################# +oracle_service () at .././oracle.c:35 +35 p_screen_service(); +### Assembly ######################################################################################################## +~ +~ +~ +~ + 0x00002298 oracle_service+0 push {r3, lr} + 0x0000229a oracle_service+2 ldr r3, [pc, #4] ; (0x22a0 ) + 0x0000229c oracle_service+4 blx r3 + 0x0000229e oracle_service+6 pop {r3, pc} + 0x000022a0 oracle_service+8 asrs r1, r4, #32 + 0x000022a2 oracle_service+10 movs r0, r0 +### Breakpoints ##################################################################################################### +[1] break at 0x00002252 in .././main.c:6 for main hit 1 time +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x00000001 r5 0x000019b9 r10 0xfffdfdff pc 0x0000229a primask 0x00 + r1 0x20008fe8 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x81000000 basepri 0x00 + r2 0x00000000 r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x00002265 r8 0x2000c67c sp 0x2001c7e8 msp 0x2001c7e8 control 0x00 + r4 0x00002299 r9 0x00011fb1 lr 0x0000225b psp 0xfdff677c +### Source ########################################################################################################## + 25 // gpio init + 26 p_gpio_init(); + 27 // time init + 28 p_tcc_init(); + 29 + 30 p_screen_init(); + 31 } + 32 + 33 void oracle_service(void) + 34 { + 35 p_screen_service(); + 36 } +~ +~ +~ +~ +~ +~ +~ +~ +### Stack ########################################################################################################### +[0] from 0x0000229a in oracle_service+2 at .././oracle.c:35 +[1] from 0x0000225a in main+10 at .././main.c:10 +### Threads ######################################################################################################### +[1] id 0 from 0x0000229a in oracle_service+2 at .././oracle.c:35 +### Variables ####################################################################################################### +##################################################################################################################### +### Output/messages ################################################################################################# +p_screen_service () at ../devices/p_screen.c:43 +warning: Source file is more recent than executable. +43 lv_task_handler(); +### Assembly ######################################################################################################## +~ +~ +~ +~ + 0x00001020 p_screen_service+0 push {r3, lr} + 0x00001022 p_screen_service+2 ldr r3, [pc, #4] ; (0x1028 ) + 0x00001024 p_screen_service+4 blx r3 + 0x00001026 p_screen_service+6 pop {r3, pc} + 0x00001028 p_screen_service+8 adds r7, #193 ; 0xc1 + 0x0000102a p_screen_service+10 movs r1, r0 +### Breakpoints ##################################################################################################### +[1] break at 0x00002252 in .././main.c:6 for main hit 1 time +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x00000001 r5 0x000019b9 r10 0xfffdfdff pc 0x00001022 primask 0x00 + r1 0x20008fe8 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x81000000 basepri 0x00 + r2 0x00000000 r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x00001021 r8 0x2000c67c sp 0x2001c7e0 msp 0x2001c7e0 control 0x00 + r4 0x00002299 r9 0x00011fb1 lr 0x0000229f psp 0xfdff677c +### Source ########################################################################################################## + 33 lv_img_set_src(hornet_image, &hornet); + 34 lv_obj_set_pos(hornet_image, 0, 0); + 35 + 36 lv_obj_t* random_text = lv_label_create(scr, NULL); + 37 lv_obj_set_pos(random_text, 90, 35); + 38 lv_label_set_text(random_text, "Hello World"); + 39 } + 40 + 41 void p_screen_service(void) + 42 { + 43 lv_task_handler(); + 44 } +~ +~ +~ +~ +~ +~ +~ +~ +### Stack ########################################################################################################### +[0] from 0x00001022 in p_screen_service+2 at ../devices/p_screen.c:43 +[1] from 0x0000229e in oracle_service+6 at .././oracle.c:35 +[2] from 0x0000225a in main+10 at .././main.c:10 +### Threads ######################################################################################################### +[1] id 0 from 0x00001022 in p_screen_service+2 at ../devices/p_screen.c:43 +### Variables ####################################################################################################### +##################################################################################################################### +### Output/messages ################################################################################################# +lv_task_handler () at ../thirdparty/lvgl/src/lv_misc/lv_task.c:78 +78 if(already_running) return 1; +### Assembly ######################################################################################################## +~ +~ +~ +~ + 0x000137c0 lv_task_handler+0 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 0x000137c4 lv_task_handler+4 ldr r3, [pc, #352] ; (0x13928 ) + 0x000137c6 lv_task_handler+6 ldrb r3, [r3, #4] + 0x000137c8 lv_task_handler+8 cmp r3, #0 + 0x000137ca lv_task_handler+10 bne.w 0x13920 + 0x000137ce lv_task_handler+14 ldr r3, [pc, #344] ; (0x13928 ) +### Breakpoints ##################################################################################################### +[1] break at 0x00002252 in .././main.c:6 for main hit 1 time +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x00000001 r5 0x000019b9 r10 0xfffdfdff pc 0x000137c4 primask 0x00 + r1 0x20008fe8 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x81000000 basepri 0x00 + r2 0x00000000 r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x000137c1 r8 0x2000c67c sp 0x2001c7c0 msp 0x2001c7c0 control 0x00 + r4 0x00002299 r9 0x00011fb1 lr 0x00001027 psp 0xfdff677c +### Source ########################################################################################################## + 68 * @return the time after which it must be called again + 69 */ + 70 LV_ATTRIBUTE_TASK_HANDLER uint32_t lv_task_handler(void) + 71 { + 72 + 73 + 74 LV_LOG_TRACE("lv_task_handler started"); + 75 + 76 /*Avoid concurrent running of the task handler*/ + 77 static bool already_running = false; + 78 if(already_running) return 1; + 79 already_running = true; + 80 + 81 static uint32_t idle_period_start = 0; + 82 static uint32_t handler_start = 0; + 83 static uint32_t busy_time = 0; + 84 static uint32_t time_till_next; + 85 + 86 if(lv_task_run == false) { + 87 already_running = false; /*Release mutex*/ +### Stack ########################################################################################################### +[0] from 0x000137c4 in lv_task_handler+4 at ../thirdparty/lvgl/src/lv_misc/lv_task.c:78 +[1] from 0x00001026 in p_screen_service+6 at ../devices/p_screen.c:43 +[2] from 0x0000229e in oracle_service+6 at .././oracle.c:35 +[3] from 0x0000225a in main+10 at .././main.c:10 +### Threads ######################################################################################################### +[1] id 0 from 0x000137c4 in lv_task_handler+4 at ../thirdparty/lvgl/src/lv_misc/lv_task.c:78 +### Variables ####################################################################################################### +loc already_running = false, idle_period_start = 0, handler_start = 0, busy_time = 0, time_till_next = 0, task_interrupter = , next = , end_flag = , idle_period_time = +##################################################################################################################### +Continuing. +### Output/messages ################################################################################################# + +Program received signal SIGINT, Interrupt. +lv_task_handler () at ../thirdparty/lvgl/src/lv_misc/lv_task.c:168 +168 busy_time += lv_tick_elaps(handler_start); +### Assembly ######################################################################################################## + 0x0001384e lv_task_handler+142 ldrb r3, [r5, #2] + 0x00013850 lv_task_handler+144 cbnz r3, 0x13858 + 0x00013852 lv_task_handler+146 ldrb r3, [r5, #3] + 0x00013854 lv_task_handler+148 cmp r3, #0 + 0x00013856 lv_task_handler+150 beq.n 0x138b8 + 0x00013858 lv_task_handler+152 ldr r4, [pc, #204] ; (0x13928 ) + 0x0001385a lv_task_handler+154 ldr r0, [r4, #8] + 0x0001385c lv_task_handler+156 ldr r5, [pc, #216] ; (0x13938 ) + 0x0001385e lv_task_handler+158 blx r5 + 0x00013860 lv_task_handler+160 ldr r3, [r4, #12] +### Breakpoints ##################################################################################################### +[1] break at 0x00002252 in .././main.c:6 for main hit 1 time +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x20008e30 r5 0x2000c5b4 r10 0xfffdfdff pc 0x00013858 primask 0x00 + r1 0x20008e30 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x41000000 basepri 0x00 + r2 0x20008e4c r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x00000000 r8 0x2000c67c sp 0x2001c7c0 msp 0x2001c7c0 control 0x00 + r4 0x2000c748 r9 0x00011fb1 lr 0x0001381f psp 0xfdff677c +### Source ########################################################################################################## + 158 task_interrupter = NULL; + 159 end_flag = false; + 160 task_list_changed = false; + 161 break; + 162 } + 163 + 164 LV_GC_ROOT(_lv_task_act) = next; /*Load the next task*/ + 165 } + 166 } while(!end_flag); + 167 + 168 busy_time += lv_tick_elaps(handler_start); + 169 uint32_t idle_period_time = lv_tick_elaps(idle_period_start); + 170 if(idle_period_time >= IDLE_MEAS_PERIOD) { + 171 + 172 idle_last = (uint32_t)((uint32_t)busy_time * 100) / IDLE_MEAS_PERIOD; /*Calculate the busy percentage*/ + 173 idle_last = idle_last > 100 ? 0 : 100 - idle_last; /*But we need idle time*/ + 174 busy_time = 0; + 175 idle_period_start = lv_tick_get(); + 176 } + 177 +### Stack ########################################################################################################### +[0] from 0x00013858 in lv_task_handler+152 at ../thirdparty/lvgl/src/lv_misc/lv_task.c:168 +[1] from 0x00001026 in p_screen_service+6 at ../devices/p_screen.c:43 +[2] from 0x0000229e in oracle_service+6 at .././oracle.c:35 +[3] from 0x0000225a in main+10 at .././main.c:10 +### Threads ######################################################################################################### +[1] id 0 from 0x00013858 in lv_task_handler+152 at ../thirdparty/lvgl/src/lv_misc/lv_task.c:168 +### Variables ####################################################################################################### +loc already_running = true, idle_period_start = 9500, handler_start = 9537, busy_time = 14, time_till_next = 4294967295, task_interrupter = , next = , end_flag = true, idle_period_time = +##################################################################################################################### +Detaching from program: /storage/Shared/Projects/Embedded-Graphics-Learning/software/firmware/oracle_e54_edition_pre_port/e54_gfx_learning/e54_gfx_learning/Debug/e54_gfx_learning.elf, Remote target +[Inferior 1 (Remote target) detached] +lv_task_handler () at ../thirdparty/lvgl/src/lv_misc/lv_task.c:168 +warning: Source file is more recent than executable. +168 busy_time += lv_tick_elaps(handler_start); +### Assembly ######################################################################################################## + 0x0001384e lv_task_handler+142 ldrb r3, [r5, #2] + 0x00013850 lv_task_handler+144 cbnz r3, 0x13858 + 0x00013852 lv_task_handler+146 ldrb r3, [r5, #3] + 0x00013854 lv_task_handler+148 cmp r3, #0 + 0x00013856 lv_task_handler+150 beq.n 0x138b8 + 0x00013858 lv_task_handler+152 ldr r4, [pc, #204] ; (0x13928 ) + 0x0001385a lv_task_handler+154 ldr r0, [r4, #8] + 0x0001385c lv_task_handler+156 ldr r5, [pc, #216] ; (0x13938 ) + 0x0001385e lv_task_handler+158 blx r5 + 0x00013860 lv_task_handler+160 ldr r3, [r4, #12] +### Breakpoints ##################################################################################################### +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x20008e30 r5 0x2000c5b4 r10 0xfffdfdff pc 0x00013858 primask 0x00 + r1 0x20008e30 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x41000000 basepri 0x00 + r2 0x20008e4c r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x00000000 r8 0x2000c67c sp 0x2001c7c0 msp 0x2001c7c0 control 0x00 + r4 0x2000c748 r9 0x00011fb1 lr 0x0001381f psp 0xfdff677c +### Source ########################################################################################################## + 158 task_interrupter = NULL; + 159 end_flag = false; + 160 task_list_changed = false; + 161 break; + 162 } + 163 + 164 LV_GC_ROOT(_lv_task_act) = next; /*Load the next task*/ + 165 } + 166 } while(!end_flag); + 167 + 168 busy_time += lv_tick_elaps(handler_start); + 169 uint32_t idle_period_time = lv_tick_elaps(idle_period_start); + 170 if(idle_period_time >= IDLE_MEAS_PERIOD) { + 171 + 172 idle_last = (uint32_t)((uint32_t)busy_time * 100) / IDLE_MEAS_PERIOD; /*Calculate the busy percentage*/ + 173 idle_last = idle_last > 100 ? 0 : 100 - idle_last; /*But we need idle time*/ + 174 busy_time = 0; + 175 idle_period_start = lv_tick_get(); + 176 } + 177 +### Stack ########################################################################################################### +[0] from 0x00013858 in lv_task_handler+152 at ../thirdparty/lvgl/src/lv_misc/lv_task.c:168 +[1] from 0x00001026 in p_screen_service+6 at ../devices/p_screen.c:43 +[2] from 0x0000229e in oracle_service+6 at .././oracle.c:35 +[3] from 0x0000225a in main+10 at .././main.c:10 +### Threads ######################################################################################################### +[1] id 0 from 0x00013858 in lv_task_handler+152 at ../thirdparty/lvgl/src/lv_misc/lv_task.c:168 +### Variables ####################################################################################################### +loc already_running = true, idle_period_start = 9500, handler_start = 9537, busy_time = 14, time_till_next = 4294967295, task_interrupter = , next = , end_flag = true, idle_period_time = +##################################################################################################################### +target halted due to debug-request, current mode: Thread +xPSR: 0x01000000 pc: 0x00001030 msp: 0x2001c800 +Loading section .text, size 0x29a28 lma 0x0 +Loading section .ARM.exidx, size 0x8 lma 0x29a28 +Loading section .relocate, size 0x74 lma 0x29a30 +Start address 0x00000000, load size 170660 +Transfer rate: 46 KB/sec, 13127 bytes/write. +Detaching from program: /storage/Shared/Projects/Embedded-Graphics-Learning/software/firmware/oracle_e54_edition_pre_port/e54_gfx_learning/e54_gfx_learning/Debug/e54_gfx_learning.elf, Remote target +[Inferior 1 (Remote target) detached] +0x0000229c in ?? () +### Assembly ######################################################################################################## + 0x0000229c ? blx r3 + 0x0000229e ? pop {r3, pc} + 0x000022a0 ? asrs r1, r4, #32 + 0x000022a2 ? movs r0, r0 + 0x000022a4 ? adds r0, #0 + 0x000022a6 ? it ne + 0x000022a8 ? movne r0, #1 + 0x000022aa ? bx lr + 0x000022ac ? push {r4, r5, r6, r7, lr} + 0x000022ae ? sub sp, #268 ; 0x10c +### Breakpoints ##################################################################################################### +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0xffffffff r5 0xf7bfffff r10 0xfffdfdff pc 0x0000229c primask 0x00 + r1 0x20008590 r6 0xffff7fff r11 0xfb9ff7bf xPSR 0x41000000 basepri 0x00 + r2 0x00000000 r7 0x6fbf7fdd r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x00001021 r8 0xdfff5aeb sp 0x2001c7e8 msp 0x2001c7e8 control 0x00 + r4 0x00002299 r9 0x57f7dfff lr 0x0000225b psp 0xfdff277c +### Source ########################################################################################################## +### Stack ########################################################################################################### +[0] from 0x0000229c +[1] from 0x0000225a +### Threads ######################################################################################################### +[1] id 0 from 0x0000229c +### Variables ####################################################################################################### +##################################################################################################################### +Loading section .sec1, size 0x10000 lma 0x0 +Loading section .sec2, size 0x10000 lma 0x10000 +Loading section .sec3, size 0x9aa4 lma 0x20000 +Start address 0x00000000, load size 170660 +Transfer rate: 46 KB/sec, 13127 bytes/write. +A debugging session is active. + + Inferior 1 [Remote target] will be detached. + +Quit anyway? (y or n) [answered Y; input not from terminal] +[Inferior 1 (Remote target) detached] +warning: No executable has been specified and target does not support +determining executable automatically. Try using the "file" command. +0x00001026 in ?? () +### Assembly ######################################################################################################## + 0x00001026 ? pop {r3, pc} + 0x00001028 ? adds r7, #193 ; 0xc1 + 0x0000102a ? movs r1, r0 + 0x0000102c ? b.n 0x102c + 0x0000102e ? movs r0, r0 + 0x00001030 ? push {r3, lr} + 0x00001032 ? ldr r3, [pc, #112] ; (0x10a4) + 0x00001034 ? ldr r2, [pc, #112] ; (0x10a8) + 0x00001036 ? cmp r2, r3 + 0x00001038 ? beq.n 0x105c +### Breakpoints ##################################################################################################### +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0xffffffff r5 0xf7bfffff r10 0xfffdfdff pc 0x00001026 primask 0x00 + r1 0x20008590 r6 0xffff7fff r11 0xfb9ff7bf xPSR 0x41000000 basepri 0x00 + r2 0x00000000 r7 0x6fbf7fdd r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x000137c1 r8 0xdfff5aeb sp 0x2001c7e0 msp 0x2001c7e0 control 0x00 + r4 0x00002299 r9 0x57f7dfff lr 0x000138f1 psp 0xfdff277c +### Source ########################################################################################################## +### Stack ########################################################################################################### +[0] from 0x00001026 +[1] from 0x000138f0 +### Threads ######################################################################################################### +[1] id 0 from 0x00001026 +### Variables ####################################################################################################### +##################################################################################################################### +scripts/push.gdb:7: Error in sourced command file: +No executable file specified. +Use the "file" or "exec-file" command. +Quit +Undefined command: "qq". Try "help". +Detaching from program: , Remote target +[Inferior 1 (Remote target) detached] diff --git a/software/firmware/oracle_e54_edition_pre_port/e54_gfx_learning/e54_gfx_learning/Debug/scripts/.gdb_history b/software/firmware/oracle_e54_edition_pre_port/e54_gfx_learning/e54_gfx_learning/Debug/scripts/.gdb_history new file mode 100644 index 00000000..e88ec7cc --- /dev/null +++ b/software/firmware/oracle_e54_edition_pre_port/e54_gfx_learning/e54_gfx_learning/Debug/scripts/.gdb_history @@ -0,0 +1,46 @@ +q +q +q +q +tar extended-remote /dev/ttyBmpGdb +mon swdp +mon swdp +mon swdp +mon swdp +mon swdp +mon swdp +mon swdp +q +tar extended-remote /dev/ttyBmpGdb +mon swdp +mon swdp +mon swdp +q +tar extended-remote /dev/ttyBmpGdb +mon s +version +help +help user-defined +monitor version +q +tar extended-remote /dev/ttyBmpGdb +mon s +mon s +mon s +mon s +mon s +mon s +mon s +mon s +tar extended-remote /dev/ttyBmpGdb +mon s +mon s +mon s +mon s +tar extended-remote /dev/ttyBmpGdb +mon s +mon s +q +target extended-remote /dev/ttyBmpGdb +q +q diff --git a/software/firmware/oracle_e54_edition_pre_port/e54_gfx_learning/e54_gfx_learning/Debug/scripts/core b/software/firmware/oracle_e54_edition_pre_port/e54_gfx_learning/e54_gfx_learning/Debug/scripts/core new file mode 100644 index 00000000..e69de29b diff --git a/software/firmware/oracle_e54_edition_pre_port/e54_gfx_learning/e54_gfx_learning/Debug/scripts/debug.gdb b/software/firmware/oracle_e54_edition_pre_port/e54_gfx_learning/e54_gfx_learning/Debug/scripts/debug.gdb new file mode 100644 index 00000000..909796ef --- /dev/null +++ b/software/firmware/oracle_e54_edition_pre_port/e54_gfx_learning/e54_gfx_learning/Debug/scripts/debug.gdb @@ -0,0 +1,7 @@ +set pagination off +set logging file gdb.txt +set logging on +set mem inaccessible-by-default off +target extended-remote localhost:3333 +monitor reset halt +load diff --git a/software/firmware/oracle_e54_edition_pre_port/e54_gfx_learning/e54_gfx_learning/Debug/scripts/gdb.txt b/software/firmware/oracle_e54_edition_pre_port/e54_gfx_learning/e54_gfx_learning/Debug/scripts/gdb.txt new file mode 100644 index 00000000..76de99dc --- /dev/null +++ b/software/firmware/oracle_e54_edition_pre_port/e54_gfx_learning/e54_gfx_learning/Debug/scripts/gdb.txt @@ -0,0 +1,145 @@ +push.gdb:5: Error in sourced command file: +/dev/blackmagic_0: No such file or directory. +push.gdb:6: Error in sourced command file: +Attaching to Remote target failed +push.gdb:6: Error in sourced command file: +Attaching to Remote target failed +push.gdb:6: Error in sourced command file: +Attaching to Remote target failed +0x000139a6 in lv_task_set_prio (task=0x200059d8 , prio=) at ../thirdparty/lvgl/src/lv_misc/lv_task.c:321 +321 ../thirdparty/lvgl/src/lv_misc/lv_task.c: No such file or directory. +### Assembly ######################################################################################################## + 0x00013998 lv_task_set_prio+76 ldr r7, [pc, #288] ; (0x13abc ) + 0x0001399a lv_task_set_prio+78 str.w r0, [r10] + 0x0001399e lv_task_set_prio+82 ldr.w r1, [r10] + 0x000139a2 lv_task_set_prio+86 cbz r1, 0x139d4 + 0x000139a4 lv_task_set_prio+88 ldr r3, [pc, #280] ; (0x13ac0 ) + 0x000139a6 lv_task_set_prio+90 mov r0, r9 + 0x000139a8 lv_task_set_prio+92 blx r3 + 0x000139aa lv_task_set_prio+94 mov r6, r0 + 0x000139ac lv_task_set_prio+96 ldr.w r0, [r10] + 0x000139b0 lv_task_set_prio+100 ldrb r1, [r0, #20] +### Breakpoints ##################################################################################################### +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x20005b78 r5 0x000119c1 r10 0x20005a48 pc 0x000139a6 primask 0x00 + r1 0x20005b78 r6 0xffff7fff r11 0x2000db94 xPSR 0x61000000 basepri 0x00 + r2 0x00000000 r7 0x000138f9 r12 0x00000000 fpscr 0x00000000 faultmask 0x00 + r3 0x000125c1 r8 0x000125b5 sp 0x20019de8 msp 0x20019de8 control 0x04 + r4 0x00000000 r9 0x200059d8 lr 0x00013995 psp 0xfdff277c +### Source ########################################################################################################## +Cannot display "lv_task.c" +### Stack ########################################################################################################### +[0] from 0x000139a6 in lv_task_set_prio+90 at ../thirdparty/lvgl/src/lv_misc/lv_task.c:321 +[1] from 0xfffdfdfe +### Threads ######################################################################################################### +[1] id 0 from 0x000139a6 in lv_task_set_prio+90 at ../thirdparty/lvgl/src/lv_misc/lv_task.c:321 +### Variables ####################################################################################################### +arg task = 0x200059d8 : {period = 24,last_run = 536894328,task_cb = 0x200064d4 ,…, prio = +loc i = 0x0 : {period = 536976928,last_run = 6981,task_cb = 0x1b41 + 0x0001381a lv_task_handler+90 mov r0, r8 + 0x0001381c lv_task_handler+92 blx r9 + 0x0001381e lv_task_handler+94 mov r7, r0 + 0x00013820 lv_task_handler+96 ldr r0, [r4, #0] + 0x00013822 lv_task_handler+98 ldrb r3, [r0, #20] + 0x00013824 lv_task_handler+100 ands.w r3, r3, #7 + 0x00013828 lv_task_handler+104 beq.n 0x13858 + 0x0001382a lv_task_handler+106 cmp r6, r0 +### Breakpoints ##################################################################################################### +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x20008590 r5 0x2000c5b4 r10 0xfffdfdff pc 0x00013820 primask 0x00 + r1 0x20008e30 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x01000000 basepri 0x00 + r2 0x20008e4c r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x00000020 r8 0x2000c67c sp 0x2001c7c0 msp 0x2001c7c0 control 0x00 + r4 0x2000c748 r9 0x00011fb1 lr 0x0001381f psp 0xfdff677c +### Source ########################################################################################################## +Cannot display "lv_task.c" +### Stack ########################################################################################################### +[0] from 0x00013820 in lv_task_handler+96 at ../thirdparty/lvgl/src/lv_misc/lv_task.c:110 +[1] from 0x00001026 in p_screen_service+6 at ../devices/p_screen.c:43 +[2] from 0x0000229e in oracle_service+6 at .././oracle.c:35 +[3] from 0x0000225a in main+10 at .././main.c:10 +### Threads ######################################################################################################### +[1] id 0 from 0x00013820 in lv_task_handler+96 at ../thirdparty/lvgl/src/lv_misc/lv_task.c:110 +### Variables ####################################################################################################### +loc already_running = true, idle_period_start = 9000, handler_start = 9091, busy_time = 31, time_till_next = 4294967295, task_interrupter = 0x0 : {period = 536987648,last_run = 4145,task_cb = 0x102d …, next = 0x20008590 : {period = 30,last_run = 0,task_cb = 0x110d1 ,user_d…, end_flag = true, idle_period_time = +##################################################################################################################### +Loading section .text, size 0x29a28 lma 0x0 +Loading section .ARM.exidx, size 0x8 lma 0x29a28 +Loading section .relocate, size 0x74 lma 0x29a30 +Start address 0x00000000, load size 170660 +Transfer rate: 46 KB/sec, 13127 bytes/write. +A debugging session is active. + + Inferior 1 [Remote target] will be detached. + +Quit anyway? (y or n) [answered Y; input not from terminal] +[Inferior 1 (Remote target) detached] +lv_tick_get () at ../thirdparty/lvgl/src/lv_hal/lv_hal_tick.c:63 +63 ../thirdparty/lvgl/src/lv_hal/lv_hal_tick.c: No such file or directory. +### Assembly ######################################################################################################## +~ +~ + 0x0001104c lv_tick_get+0 ldr r3, [pc, #16] ; (0x11060 ) + 0x0001104e lv_tick_get+2 mov.w r1, #1 + 0x00011052 lv_tick_get+6 strb r1, [r3, #0] + 0x00011054 lv_tick_get+8 ldrb r2, [r3, #0] + 0x00011056 lv_tick_get+10 cmp r2, #0 + 0x00011058 lv_tick_get+12 beq.n 0x11052 + 0x0001105a lv_tick_get+14 ldr r3, [pc, #4] ; (0x11060 ) + 0x0001105c lv_tick_get+16 ldr r0, [r3, #4] +### Breakpoints ##################################################################################################### +### Expressions ##################################################################################################### +### History ######################################################################################################### +### Memory ########################################################################################################## +### Registers ####################################################################################################### + r0 0x0002180b r5 0x00011065 r10 0xfffdfdff pc 0x00011054 primask 0x00 + r1 0x00000001 r6 0x00000000 r11 0xfb9ff7bf xPSR 0x41000000 basepri 0x00 + r2 0x20008e4c r7 0x20008590 r12 0x200085b4 fpscr 0x00000000 faultmask 0x00 + r3 0x20008570 r8 0x2000c67c sp 0x2001c7b8 msp 0x2001c7b8 control 0x00 + r4 0x0002180b r9 0x00011fb1 lr 0x0001106d psp 0xfdff677c +### Source ########################################################################################################## +Cannot display "lv_hal_tick.c" +### Stack ########################################################################################################### +[0] from 0x00011054 in lv_tick_get+8 at ../thirdparty/lvgl/src/lv_hal/lv_hal_tick.c:63 +[1] from 0x0001106c in lv_tick_elaps+8 at ../thirdparty/lvgl/src/lv_hal/lv_hal_tick.c:79 +[2] from 0x00013860 in lv_task_handler+160 at ../thirdparty/lvgl/src/lv_misc/lv_task.c:168 +[3] from 0x00001026 in p_screen_service+6 at ../devices/p_screen.c:43 +[4] from 0x0000229e in oracle_service+6 at .././oracle.c:35 +[5] from 0x0000225a in main+10 at .././main.c:10 +### Threads ######################################################################################################### +[1] id 0 from 0x00011054 in lv_tick_get+8 at ../thirdparty/lvgl/src/lv_hal/lv_hal_tick.c:63 +### Variables ####################################################################################################### +loc result = 137227 +##################################################################################################################### +target halted due to debug-request, current mode: Thread +xPSR: 0x01000000 pc: 0x00001030 msp: 0x2001c800 +Loading section .text, size 0x29a28 lma 0x0 +Loading section .ARM.exidx, size 0x8 lma 0x29a28 +Loading section .relocate, size 0x74 lma 0x29a30 +Start address 0x00000000, load size 170660 +Transfer rate: 46 KB/sec, 13127 bytes/write. +Detaching from program: /storage/Shared/Projects/Embedded-Graphics-Learning/software/firmware/oracle_e54_edition_pre_port/e54_gfx_learning/e54_gfx_learning/Debug/e54_gfx_learning.elf, Remote target +[Inferior 1 (Remote target) detached] diff --git a/software/firmware/oracle_e54_edition_pre_port/e54_gfx_learning/e54_gfx_learning/Debug/scripts/openocd.cfg b/software/firmware/oracle_e54_edition_pre_port/e54_gfx_learning/e54_gfx_learning/Debug/scripts/openocd.cfg new file mode 100644 index 00000000..e458c73d --- /dev/null +++ b/software/firmware/oracle_e54_edition_pre_port/e54_gfx_learning/e54_gfx_learning/Debug/scripts/openocd.cfg @@ -0,0 +1,9 @@ +# +# Atmel SAMD21 Xplained Pro evaluation kit. +# + +source [find interface/jlink.cfg] +transport select swd +# chip name +set CHIPNAME atsame54p20a +source [find target/atsame5x.cfg] diff --git a/software/firmware/oracle_e54_edition_pre_port/e54_gfx_learning/e54_gfx_learning/Debug/scripts/push.gdb b/software/firmware/oracle_e54_edition_pre_port/e54_gfx_learning/e54_gfx_learning/Debug/scripts/push.gdb new file mode 100644 index 00000000..a6b7af93 --- /dev/null +++ b/software/firmware/oracle_e54_edition_pre_port/e54_gfx_learning/e54_gfx_learning/Debug/scripts/push.gdb @@ -0,0 +1,11 @@ +set pagination off +set logging file gdb.txt +set logging redirect on +set logging on +set remotetimeout 1 +target extended-remote localhost:3333 +load +monitor reset +q +y + diff --git a/software/firmware/oracle_esf_edition/esf/arm/SAME54/SAME54A/ld b/software/firmware/oracle_esf_edition/esf/arm/SAME54/SAME54A/ld deleted file mode 120000 index 81799038..00000000 --- a/software/firmware/oracle_esf_edition/esf/arm/SAME54/SAME54A/ld +++ /dev/null @@ -1 +0,0 @@ -/storage/Shared/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/ld \ No newline at end of file diff --git a/software/firmware/oracle_esf_edition/esf/arm/SAME54/SAME54A/mcu b/software/firmware/oracle_esf_edition/esf/arm/SAME54/SAME54A/mcu deleted file mode 120000 index 985bac73..00000000 --- a/software/firmware/oracle_esf_edition/esf/arm/SAME54/SAME54A/mcu +++ /dev/null @@ -1 +0,0 @@ -/storage/Shared/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu \ No newline at end of file diff --git a/software/firmware/oracle_esf_edition/esf/arm/common b/software/firmware/oracle_esf_edition/esf/arm/common deleted file mode 120000 index 112ec462..00000000 --- a/software/firmware/oracle_esf_edition/esf/arm/common +++ /dev/null @@ -1 +0,0 @@ -/storage/Shared/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/common \ No newline at end of file diff --git a/software/firmware/oracle_esf_edition/igloo/igloo.toml b/software/firmware/oracle_esf_edition/igloo/igloo.toml deleted file mode 100644 index 7b1103f5..00000000 --- a/software/firmware/oracle_esf_edition/igloo/igloo.toml +++ /dev/null @@ -1,3 +0,0 @@ -[profile] -name = "oracle_esf_edition" -targets = ["same54p20a"] diff --git a/software/firmware/oracle_esf_edition/igloo/targets/same54p20a/Makefile b/software/firmware/oracle_esf_edition/igloo/targets/same54p20a/Makefile deleted file mode 100644 index 6ebd73ef..00000000 --- a/software/firmware/oracle_esf_edition/igloo/targets/same54p20a/Makefile +++ /dev/null @@ -1,205 +0,0 @@ -## ePenguin Generated Makefile -PROJECT_NAME=oracle_esf_edition -TARGET_NAME=same54p20a - -## Toolchain Variables -TOOLCHAIN=arm-none-eabi -CC=${TOOLCHAIN}-gcc -CXX=${TOOLCHAIN}-g++ -OBJCOPY=${TOOLCHAIN}-objcopy -OBJDUMP=${TOOLCHAIN}-objdump -GDB=${TOOLCHAIN}-gdb -SIZE=${TOOLCHAIN}-size -AS=${TOOLCHAIN}-as - -## MCU Specific Variables -MCPU=cortex-m4 -MCU=__SAME54P20A__ -LD_PATH=../../../esf/arm/SAME54/SAME54A/ld -LD_SCRIPT=$(LD_PATH)/same54p20a_flash.ld - -## Compiler Flags -CFLAGS=\ --D$(MCU)\ --mcpu=$(MCPU)\ --x c\ --DDEBUG\ --Os\ --g3\ --Wall\ --c\ --std=gnu99\ -$(DIR_INCLUDES)\ --MD -MP\ --MF$(QUOTE)$(@:%.o=%.d)$(QUOTE)\ --MT$(QUOTE)$(@:%.o=%.d)$(QUOTE)\ --MT$(QUOTE)$(@:%.o=%.o)$(QUOTE) - -ELF_FLAGS=\ --D$(MCU)\ --mcpu=$(MCPU)\ --Wl,--start-group -l m\ --Wl,--end-group -mthumb\ --Wl,-Map=$(QUOTE)$(PROJECT_NAME).map$(QUOTE)\ ---specs=nano.specs\ --Wl,--gc-sections\ --T$(QUOTE)$(LD_SCRIPT)$(QUOTE)\ --L$(QUOTE)$(LD_PATH)$(QUOTE) - -HEX_FLAGS=\ --R .eeprom\ --R .fuse\ --R .lock\ --R .signature -EEP_FLAGS=\ --j .eeprom --set-section-flags=.eeprom=alloc,load\ ---change-section-lma\ -.eeprom=0\ ---no-change-warnings - -ifdef SystemRoot - SHELL = cmd.exe - MK_DIR = mkdir -else - ifeq ($(shell uname), Linux) - MK_DIR = mkdir -p - endif - - ifeq ($(shell uname | cut -d _ -f 1), CYGWIN) - MK_DIR = mkdir -p - endif - - ifeq ($(shell uname | cut -d _ -f 1), MINGW32) - MK_DIR = mkdir -p - endif - - ifeq ($(shell uname | cut -d _ -f 1), MINGW64) - MK_DIR = mkdir -p - endif - - ifeq ($(shell uname | cut -d _ -f 1), DARWIN) - MK_DIR = mkdir -p - endif -endif - -SUB_DIRS=\ -esf/arm/SAME54/SAME54A/mcu/src\ -src - -OBJS=\ -esf/arm/SAME54/SAME54A/mcu/src/startup_same54.o\ -esf/arm/SAME54/SAME54A/mcu/src/system_same54.o\ -src/main.o - -OBJS_AS_ARGS=\ -$(QUOTE)esf/arm/SAME54/SAME54A/mcu/src/startup_same54.o$(QUOTE)\ -$(QUOTE)esf/arm/SAME54/SAME54A/mcu/src/system_same54.o$(QUOTE)\ -$(QUOTE)src/main.o$(QUOTE) - -DEPS=$(OBJS:%.o=%.d) -DEPS_AS_ARGS=$(OBJS_AS_ARGS:%.o=%.d) - - -DIR_INCLUDES=\ --I$(QUOTE)../../../esf/arm/SAME54/SAME54A/mcu/inc$(QUOTE)\ --I$(QUOTE)../../../esf/arm/common/inc$(QUOTE)\ --I$(QUOTE)../../../esf/arm/common/inc/cmsis$(QUOTE)\ --I$(QUOTE)../../../inc$(QUOTE) - -vpath %.c ../../../ -vpath %.s ../../../ -vpath %.S ../../../ - -.PHONY: debug push clean - - -all:\ -$(SUB_DIRS)\ -$(PROJECT_NAME).elf\ -$(PROJECT_NAME).bin\ -$(PROJECT_NAME).hex\ -$(PROJECT_NAME).eep\ -$(PROJECT_NAME).lss - $(QUOTE)$(SIZE)$(QUOTE) $(QUOTE)$(PROJECT_NAME).elf$(QUOTE) - - -$(PROJECT_NAME).elf:\ -$(OBJS) - $(QUOTE)$(CC)$(QUOTE) -o $@ $(OBJS_AS_ARGS) $(ELF_FLAGS) - - -$(PROJECT_NAME).bin:\ -$(PROJECT_NAME).elf - $(QUOTE)$(OBJCOPY)$(QUOTE) -O binary $(QUOTE)$<$(QUOTE) $(QUOTE)$@$(QUOTE) - - -$(PROJECT_NAME).hex:\ -$(PROJECT_NAME).elf - $(QUOTE)$(OBJCOPY)$(QUOTE) -O ihex $(HEX_FLAGS) $(QUOTE)$<$(QUOTE) $(QUOTE)$@$(QUOTE) - - -$(PROJECT_NAME).eep:\ -$(PROJECT_NAME).elf - $(QUOTE)$(OBJCOPY)$(QUOTE) $(EEP_FLAGS) -O binary $(QUOTE)$<$(QUOTE) $(QUOTE)$@$(QUOTE) || exit 0 - - -$(PROJECT_NAME).lss:\ -$(PROJECT_NAME).elf - $(QUOTE)$(OBJDUMP)$(QUOTE) -h -S $(QUOTE)$<$(QUOTE) > $(QUOTE)$@$(QUOTE) - - -# Compiler targets -%.o: %.c - @echo Building file: $< - @echo ARM/GNU C Compiler - $(QUOTE)$(CC)$(QUOTE) $(CFLAGS) -o $(QUOTE)$@$(QUOTE) $(QUOTE)$<$(QUOTE) - @echo Finished building: $< - -%.o: %.s - @echo Building file: $< - @echo ARM/GNU Assembler - $(QUOTE)$(AS)$(QUOTE) $(CFLAGS) -o $(QUOTE)$@$(QUOTE) $(QUOTE)$<$(QUOTE) - @echo Finished building: $< - -%.o: %.S - @echo Building file: $< - @echo ARM/GNU Preprocessing Assembler - $(QUOTE)$(CC)$(QUOTE) $(CFLAGS) -o $(QUOTE)$@$(QUOTE) $(QUOTE)$<$(QUOTE) - @echo Finished building: $< - - -$(SUB_DIRS): - $(MK_DIR) $(QUOTE)$@$(QUOTE) - -ifneq ($(MAKECMDGOALS),clean) -ifneq ($(strip $(DEPS)),) --include $(DEPS) -endif -endif - -clean: - @rm -f $(PROJECT_NAME).a - @rm -f $(PROJECT_NAME).lss - @rm -f $(PROJECT_NAME).srec - @rm -f $(PROJECT_NAME).map - @rm -f $(PROJECT_NAME).eep - @rm -f $(OBJS_AS_ARGS) - @rm -f $(DEPS_AS_ARGS) - @rm -f $(PROJECT_NAME).bin - @rm -f $(PROJECT_NAME).elf - @rm -f $(PROJECT_NAME).hex - -push:\ -all - @echo $(QUOTE)$(QUOTE) - @echo $(QUOTE)Uploading $(PROJECT_NAME).elf...$(QUOTE) - @$(GDB) $(PROJECT_NAME).elf -x $(QUOTE)scripts/push.gdb$(QUOTE) >/dev/null - @echo $(QUOTE)$(QUOTE)$(PROJECT_NAME).elf $(QUOTE) uploaded!$(QUOTE) - @$(QUOTE)$(SIZE)$(QUOTE) $(QUOTE)$(PROJECT_NAME).elf$(QUOTE) - -debug:\ -all - @$(GDB) $(PROJECT_NAME).elf -x $(QUOTE)scripts/debug.gdb$(QUOTE) - - -QUOTE:=" diff --git a/software/firmware/oracle_esf_edition/igloo/targets/same54p20a/same54p20a.toml b/software/firmware/oracle_esf_edition/igloo/targets/same54p20a/same54p20a.toml deleted file mode 100644 index b3982fd8..00000000 --- a/software/firmware/oracle_esf_edition/igloo/targets/same54p20a/same54p20a.toml +++ /dev/null @@ -1,8 +0,0 @@ -[esf] -name = "same54p20a" -links = ["arch/arm/common", "arch/arm/SAME54/SAME54A/mcu", "arch/arm/SAME54/SAME54A/ld"] -includes = ["sam.h"] -scripts = ["arch/arm/SAME54/SAME54A/scripts/same54p20a.cfg", "scripts/push.gdb", "scripts/debug.gdb"] -series = "arch.arm.same54a.same54p20a" - -[user] diff --git a/software/firmware/oracle_esf_edition/igloo/targets/same54p20a/scripts/debug.gdb b/software/firmware/oracle_esf_edition/igloo/targets/same54p20a/scripts/debug.gdb deleted file mode 120000 index 57739618..00000000 --- a/software/firmware/oracle_esf_edition/igloo/targets/same54p20a/scripts/debug.gdb +++ /dev/null @@ -1 +0,0 @@ -/storage/Shared/Projects/ePenguin/ePenguin-Software-Framework/scripts/debug.gdb \ No newline at end of file diff --git a/software/firmware/oracle_esf_edition/igloo/targets/same54p20a/scripts/push.gdb b/software/firmware/oracle_esf_edition/igloo/targets/same54p20a/scripts/push.gdb deleted file mode 120000 index 30836d13..00000000 --- a/software/firmware/oracle_esf_edition/igloo/targets/same54p20a/scripts/push.gdb +++ /dev/null @@ -1 +0,0 @@ -/storage/Shared/Projects/ePenguin/ePenguin-Software-Framework/scripts/push.gdb \ No newline at end of file diff --git a/software/firmware/oracle_esf_edition/igloo/targets/same54p20a/scripts/same54p20a.cfg b/software/firmware/oracle_esf_edition/igloo/targets/same54p20a/scripts/same54p20a.cfg deleted file mode 120000 index bb0d210d..00000000 --- a/software/firmware/oracle_esf_edition/igloo/targets/same54p20a/scripts/same54p20a.cfg +++ /dev/null @@ -1 +0,0 @@ -/storage/Shared/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/scripts/same54p20a.cfg \ No newline at end of file diff --git a/software/firmware/oracle_esf_edition/inc/igloo.h b/software/firmware/oracle_esf_edition/inc/igloo.h deleted file mode 100644 index 866a55d9..00000000 --- a/software/firmware/oracle_esf_edition/inc/igloo.h +++ /dev/null @@ -1,7 +0,0 @@ -#ifndef _IGLOO_H_ -#define _IGLOO_H_ - -// Header files for same54p20a -#include "sam.h" - -#endif diff --git a/software/firmware/oracle_esf_edition/src/main.c b/software/firmware/oracle_esf_edition/src/main.c deleted file mode 100644 index 7c2ce159..00000000 --- a/software/firmware/oracle_esf_edition/src/main.c +++ /dev/null @@ -1,9 +0,0 @@ -#include "igloo.h" - -int main() -{ - for(;;){} - - // should never get here - return 0; -} diff --git a/software/firmware/oracle_same54n19a/AtmelStart.env_conf b/software/firmware/oracle_same54n19a/AtmelStart.env_conf new file mode 100644 index 00000000..236b0636 --- /dev/null +++ b/software/firmware/oracle_same54n19a/AtmelStart.env_conf @@ -0,0 +1,6 @@ + + + + + + diff --git a/software/firmware/oracle_same54n19a/AtmelStart.gpdsc b/software/firmware/oracle_same54n19a/AtmelStart.gpdsc new file mode 100644 index 00000000..c0b68185 --- /dev/null +++ b/software/firmware/oracle_same54n19a/AtmelStart.gpdsc @@ -0,0 +1,215 @@ + + Atmel + My Project + Project generated by Atmel Start + http://start.atmel.com/ + + Initial version + + + Configuration Files generated by Atmel Start + + + + Atmel Start + + + + + + + + + +
+ +
+
+
+ +
+ + + + +
+ +
+ +
+
+
Overview
+
+
+

CMSIS-Core (Cortex-M) implements the basic run-time system for a Cortex-M device and gives the user access to the processor core and the device peripherals. In detail it defines:

+
    +
  • Hardware Abstraction Layer (HAL) for Cortex-M processor registers with standardized definitions for the SysTick, NVIC, System Control Block registers, MPU registers, FPU registers, and core access functions.
    • +
  • System exception names to interface to system exceptions without having compatibility issues.
    • +
  • Methods to organize header files that makes it easy to learn new Cortex-M microcontroller products and improve software portability. This includes naming conventions for device-specific interrupts.
    • +
  • Methods for system initialization to be used by each MCU vendor. For example, the standardized SystemInit() function is essential for configuring the clock system of the device.
    • +
  • Intrinsic functions used to generate CPU instructions that are not supported by standard C functions.
    • +
  • A variable to determine the system clock frequency which simplifies the setup the SysTick timer.
    • +
+

The following sections provide details about the CMSIS-Core (Cortex-M):

+ +
+

CMSIS-Core (Cortex-M) in ARM::CMSIS Pack

+

Files relevant to CMSIS-Core (Cortex-M) are present in the following ARM::CMSIS directories:

+ + + + + + + + + + + +
File/Folder Content
CMSIS\Documentation\Core This documentation
CMSIS\Core\Include CMSIS-Core (Cortex-M) header files (for example core_cm3.h, core_cmInstr.h, etc.)
Device Arm reference implementations of Cortex-M devices
Device\_Template_Vendor CMSIS-Core Device Templates for extension by silicon vendors
+
+

+Processor Support

+

CMSIS supports the complete range of Cortex-M processors (with exception of Cortex-M1) and the Armv8-M architecture including security extensions.

+

+Cortex-M Reference Manuals

+

The Cortex-M Device Generic User Guides contain the programmers model and detailed information about the core peripherals and are available for:

+ +

The Cortex-M23 and Cortex-M33 are described with Technical Reference Manuals that are available here:

+ +

+Armv8-M Architecture

+

Armv8-M introduces two profiles baseline (for power and area constrained applications) and mainline (full-featured with optional SIMD, floating-point, and co-processor extensions). Both Armv8-M profiles are supported by CMSIS.

+

The Armv8-M Architecture is described in the Armv8-M Architecture Reference Manual.

+
+

+Tested and Verified Toolchains

+

The CMSIS-Core Device Templates supplied by Arm have been tested and verified with the following toolchains:

+
    +
  • Arm: Arm Compiler 5.06 update 6 (not for Cortex-M23, Cortex-M33, Armv8-M)
    • +
  • Arm: Arm Compiler 6.9
    • +
  • Arm: Arm Compiler 6.6.2 (not for Cortex-M0, Cortex-M23, Cortex-M33, Armv8-M)
    • +
  • GNU: GNU Tools for Arm Embedded 6.3.1 20170620
    • +
  • IAR: IAR ANSI C/C++ Compiler for Arm 8.20.1.14183
    • +
+
+
+
+ + + + diff --git a/software/firmware/oracle_same54n19a/armcc/Makefile b/software/firmware/oracle_same54n19a/armcc/Makefile new file mode 100644 index 00000000..ff889662 --- /dev/null +++ b/software/firmware/oracle_same54n19a/armcc/Makefile @@ -0,0 +1,231 @@ + +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +ifdef SystemRoot + SHELL = cmd.exe + MK_DIR = mkdir +else + ifeq ($(shell uname), Linux) + MK_DIR = mkdir -p + endif + + ifeq ($(shell uname | cut -d _ -f 1), CYGWIN) + MK_DIR = mkdir -p + endif + + ifeq ($(shell uname | cut -d _ -f 1), MINGW32) + MK_DIR = mkdir -p + endif + + ifeq ($(shell uname | cut -d _ -f 1), MINGW64) + MK_DIR = mkdir -p + endif +endif + +# List the subdirectories for creating object files +SUB_DIRS += \ + \ +hpl/pm \ +hpl/tc \ +hpl/osc32kctrl \ +hpl/ramecc \ +hpl/dmac \ +hal/src \ +hpl/mclk \ +hpl/eic \ +hpl/sercom \ +examples \ +hpl/gclk \ +hpl/oscctrl \ +hal/utils/src \ +armcc/arm_addon/armcc/arm \ +armcc/arm_addon/armcc \ +hpl/core \ +hpl/cmcc + +# List the object files +OBJS += \ +hal/src/hal_io.o \ +armcc/arm_addon/armcc/system_same54.o \ +hpl/eic/hpl_eic.o \ +hpl/core/hpl_core_m4.o \ +hal/src/hal_timer.o \ +hal/src/hal_i2c_m_sync.o \ +hal/src/hal_delay.o \ +hpl/pm/hpl_pm.o \ +hpl/core/hpl_init.o \ +hpl/ramecc/hpl_ramecc.o \ +hal/utils/src/utils_list.o \ +hal/utils/src/utils_assert.o \ +hpl/dmac/hpl_dmac.o \ +hpl/oscctrl/hpl_oscctrl.o \ +hpl/mclk/hpl_mclk.o \ +hpl/sercom/hpl_sercom.o \ +hpl/gclk/hpl_gclk.o \ +hal/src/hal_init.o \ +main.o \ +hpl/osc32kctrl/hpl_osc32kctrl.o \ +examples/driver_examples.o \ +driver_init.o \ +hal/src/hal_usart_async.o \ +hal/src/hal_ext_irq.o \ +hal/utils/src/utils_ringbuffer.o \ +hal/src/hal_gpio.o \ +hal/utils/src/utils_event.o \ +hal/src/hal_sleep.o \ +hal/src/hal_cache.o \ +hpl/cmcc/hpl_cmcc.o \ +atmel_start.o \ +hpl/tc/hpl_tc.o \ +hal/src/hal_atomic.o \ +armcc/arm_addon/armcc/arm/startup_same54.o + +OBJS_AS_ARGS += \ +"hal/src/hal_io.o" \ +"armcc/arm_addon/armcc/system_same54.o" \ +"hpl/eic/hpl_eic.o" \ +"hpl/core/hpl_core_m4.o" \ +"hal/src/hal_timer.o" \ +"hal/src/hal_i2c_m_sync.o" \ +"hal/src/hal_delay.o" \ +"hpl/pm/hpl_pm.o" \ +"hpl/core/hpl_init.o" \ +"hpl/ramecc/hpl_ramecc.o" \ +"hal/utils/src/utils_list.o" \ +"hal/utils/src/utils_assert.o" \ +"hpl/dmac/hpl_dmac.o" \ +"hpl/oscctrl/hpl_oscctrl.o" \ +"hpl/mclk/hpl_mclk.o" \ +"hpl/sercom/hpl_sercom.o" \ +"hpl/gclk/hpl_gclk.o" \ +"hal/src/hal_init.o" \ +"main.o" \ +"hpl/osc32kctrl/hpl_osc32kctrl.o" \ +"examples/driver_examples.o" \ +"driver_init.o" \ +"hal/src/hal_usart_async.o" \ +"hal/src/hal_ext_irq.o" \ +"hal/utils/src/utils_ringbuffer.o" \ +"hal/src/hal_gpio.o" \ +"hal/utils/src/utils_event.o" \ +"hal/src/hal_sleep.o" \ +"hal/src/hal_cache.o" \ +"hpl/cmcc/hpl_cmcc.o" \ +"atmel_start.o" \ +"hpl/tc/hpl_tc.o" \ +"hal/src/hal_atomic.o" \ +"armcc/arm_addon/armcc/arm/startup_same54.o" + +# List the dependency files +DEPS := $(OBJS:%.o=%.d) + +DEPS_AS_ARGS += \ +"hal/utils/src/utils_event.d" \ +"hal/src/hal_io.d" \ +"armcc/arm_addon/armcc/system_same54.d" \ +"hpl/ramecc/hpl_ramecc.d" \ +"hpl/core/hpl_core_m4.d" \ +"hpl/eic/hpl_eic.d" \ +"hal/src/hal_i2c_m_sync.d" \ +"hal/src/hal_timer.d" \ +"hal/utils/src/utils_list.d" \ +"hpl/cmcc/hpl_cmcc.d" \ +"hpl/dmac/hpl_dmac.d" \ +"hal/utils/src/utils_assert.d" \ +"hal/src/hal_delay.d" \ +"hpl/core/hpl_init.d" \ +"hpl/pm/hpl_pm.d" \ +"hpl/gclk/hpl_gclk.d" \ +"hpl/sercom/hpl_sercom.d" \ +"hal/src/hal_init.d" \ +"hpl/mclk/hpl_mclk.d" \ +"driver_init.d" \ +"hal/src/hal_usart_async.d" \ +"hpl/osc32kctrl/hpl_osc32kctrl.d" \ +"main.d" \ +"examples/driver_examples.d" \ +"hal/src/hal_cache.d" \ +"hal/src/hal_sleep.d" \ +"hal/utils/src/utils_ringbuffer.d" \ +"hal/src/hal_ext_irq.d" \ +"hal/src/hal_gpio.d" \ +"hal/src/hal_atomic.d" \ +"hpl/tc/hpl_tc.d" \ +"hpl/oscctrl/hpl_oscctrl.d" \ +"armcc/arm_addon/armcc/arm/startup_same54.d" \ +"atmel_start.d" + +OUTPUT_FILE_NAME :=AtmelStart +QUOTE := " +OUTPUT_FILE_PATH +=$(OUTPUT_FILE_NAME).elf +OUTPUT_FILE_PATH_AS_ARGS +=$(OUTPUT_FILE_NAME).elf + +vpath %.c ../ +vpath %.s ../ +vpath %.S ../ + +# All Target +all: $(SUB_DIRS) $(OUTPUT_FILE_PATH) + +# Linker target + +$(OUTPUT_FILE_PATH): $(OBJS) + @echo Building target: $@ + @echo Invoking: ARMCC Linker + $(QUOTE)armlink$(QUOTE) --ro-base 0x00000000 --entry 0x00000000 --rw-base 0x20000000 --entry Reset_Handler --first __Vectors \ +--strict --summary_stderr --info summarysizes --map --xref --callgraph --symbols \ +--info sizes --info totals --info unused --info veneers --list $(OUTPUT_FILE_NAME).map \ +-o $(OUTPUT_FILE_NAME).elf --cpu Cortex-M4 \ +$(OBJS_AS_ARGS) + + @echo Finished building target: $@ + +# Compiler target(s) + + + + +%.o: %.c + @echo Building file: $< + @echo ARMCC Compiler + $(QUOTE)armcc$(QUOTE) --c99 -c -DDEBUG -O1 -g --apcs=interwork --split_sections --cpu Cortex-M4 -D__SAME54N19A__ \ +-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/cmcc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/sercom" -I"../hpl/tc" -I"../hri" -I"../" -I"../CMSIS/Core/Include" -I"../include" \ +--depend "$@" -o "$@" "$<" + + @echo Finished building: $< + +%.o: %.s + @echo Building file: $< + @echo ARMCC Assembler + $(QUOTE)armasm$(QUOTE) -g --apcs=interwork --cpu Cortex-M4 --pd "D__SAME54N19A__ SETA 1" \ +-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/cmcc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/sercom" -I"../hpl/tc" -I"../hri" -I"../" -I"../CMSIS/Core/Include" -I"../include" \ +--depend "$(@:%.o=%.d)" -o "$@" "$<" + + @echo Finished building: $< + +%.o: %.S + @echo Building file: $< + @echo ARMCC Preprocessing Assembler + $(QUOTE)armcc$(QUOTE) --c99 -c -DDEBUG -O1 -g --apcs=interwork --split_sections --cpu Cortex-M4 -D__SAME54N19A__ \ +-I"../" -I"../config" -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/cmcc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/ramecc" -I"../hpl/sercom" -I"../hpl/tc" -I"../hri" -I"../" -I"../CMSIS/Core/Include" -I"../include" \ +--depend "$@" -o "$@" "$<" + + @echo Finished building: $< + +# Detect changes in the dependent files and recompile the respective object files. +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(DEPS)),) +-include $(DEPS) +endif +endif + +$(SUB_DIRS): + $(MK_DIR) "$@" + +clean: + rm -f $(OBJS_AS_ARGS) + rm -f $(OUTPUT_FILE_PATH) + rm -f $(DEPS_AS_ARGS) + rm -f $(OUTPUT_FILE_NAME).map $(OUTPUT_FILE_NAME).elf diff --git a/software/firmware/oracle_same54n19a/armcc/arm_addon/armcc/arm/startup_same54.s b/software/firmware/oracle_same54n19a/armcc/arm_addon/armcc/arm/startup_same54.s new file mode 100644 index 00000000..3e17c253 --- /dev/null +++ b/software/firmware/oracle_same54n19a/armcc/arm_addon/armcc/arm/startup_same54.s @@ -0,0 +1,588 @@ +;/***************************************************************************** +; * @file startup_SAME54.s +; * @brief CMSIS Cortex-M4 Core Device Startup File for +; * Atmel SAME54 Device Series +; * @version V1.0.0 +; * @date 16. January 2017 +; * +; * @note +; * Copyright (C) 2017 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000200 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PM_Handler ; 0 Power Manager + DCD MCLK_Handler ; 1 Main Clock + DCD OSCCTRL_0_Handler ; 2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 + DCD OSCCTRL_1_Handler ; 3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 + DCD OSCCTRL_2_Handler ; 4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, OSCCTRL_DFLLRDY + DCD OSCCTRL_3_Handler ; 5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 + DCD OSCCTRL_4_Handler ; 6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 + DCD OSC32KCTRL_Handler ; 7 32kHz Oscillators Control + DCD SUPC_0_Handler ; 8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY + DCD SUPC_1_Handler ; 9 SUPC_BOD12DET, SUPC_BOD33DET + DCD WDT_Handler ; 10 Watchdog Timer + DCD RTC_Handler ; 11 Real-Time Counter + DCD EIC_0_Handler ; 12 EIC_EXTINT_0 + DCD EIC_1_Handler ; 13 EIC_EXTINT_1 + DCD EIC_2_Handler ; 14 EIC_EXTINT_2 + DCD EIC_3_Handler ; 15 EIC_EXTINT_3 + DCD EIC_4_Handler ; 16 EIC_EXTINT_4 + DCD EIC_5_Handler ; 17 EIC_EXTINT_5 + DCD EIC_6_Handler ; 18 EIC_EXTINT_6 + DCD EIC_7_Handler ; 19 EIC_EXTINT_7 + DCD EIC_8_Handler ; 20 EIC_EXTINT_8 + DCD EIC_9_Handler ; 21 EIC_EXTINT_9 + DCD EIC_10_Handler ; 22 EIC_EXTINT_10 + DCD EIC_11_Handler ; 23 EIC_EXTINT_11 + DCD EIC_12_Handler ; 24 EIC_EXTINT_12 + DCD EIC_13_Handler ; 25 EIC_EXTINT_13 + DCD EIC_14_Handler ; 26 EIC_EXTINT_14 + DCD EIC_15_Handler ; 27 EIC_EXTINT_15 + DCD FREQM_Handler ; 28 Frequency Meter + DCD NVMCTRL_0_Handler ; 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, NVMCTRL_7 + DCD NVMCTRL_1_Handler ; 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 + DCD DMAC_0_Handler ; 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 + DCD DMAC_1_Handler ; 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 + DCD DMAC_2_Handler ; 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 + DCD DMAC_3_Handler ; 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 + DCD DMAC_4_Handler ; 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 + DCD EVSYS_0_Handler ; 36 EVSYS_EVD_0, EVSYS_OVR_0 + DCD EVSYS_1_Handler ; 37 EVSYS_EVD_1, EVSYS_OVR_1 + DCD EVSYS_2_Handler ; 38 EVSYS_EVD_2, EVSYS_OVR_2 + DCD EVSYS_3_Handler ; 39 EVSYS_EVD_3, EVSYS_OVR_3 + DCD EVSYS_4_Handler ; 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 + DCD PAC_Handler ; 41 Peripheral Access Controller + DCD TAL_0_Handler ; 42 TAL_BRK + DCD TAL_1_Handler ; 43 TAL_IPS_0, TAL_IPS_1 + DCD 0 ; 44 Reserved + DCD RAMECC_Handler ; 45 RAM ECC + DCD SERCOM0_0_Handler ; 46 SERCOM0_0 + DCD SERCOM0_1_Handler ; 47 SERCOM0_1 + DCD SERCOM0_2_Handler ; 48 SERCOM0_2 + DCD SERCOM0_3_Handler ; 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 + DCD SERCOM1_0_Handler ; 50 SERCOM1_0 + DCD SERCOM1_1_Handler ; 51 SERCOM1_1 + DCD SERCOM1_2_Handler ; 52 SERCOM1_2 + DCD SERCOM1_3_Handler ; 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 + DCD SERCOM2_0_Handler ; 54 SERCOM2_0 + DCD SERCOM2_1_Handler ; 55 SERCOM2_1 + DCD SERCOM2_2_Handler ; 56 SERCOM2_2 + DCD SERCOM2_3_Handler ; 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 + DCD SERCOM3_0_Handler ; 58 SERCOM3_0 + DCD SERCOM3_1_Handler ; 59 SERCOM3_1 + DCD SERCOM3_2_Handler ; 60 SERCOM3_2 + DCD SERCOM3_3_Handler ; 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 + DCD SERCOM4_0_Handler ; 62 SERCOM4_0 + DCD SERCOM4_1_Handler ; 63 SERCOM4_1 + DCD SERCOM4_2_Handler ; 64 SERCOM4_2 + DCD SERCOM4_3_Handler ; 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 + DCD SERCOM5_0_Handler ; 66 SERCOM5_0 + DCD SERCOM5_1_Handler ; 67 SERCOM5_1 + DCD SERCOM5_2_Handler ; 68 SERCOM5_2 + DCD SERCOM5_3_Handler ; 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 + DCD SERCOM6_0_Handler ; 70 SERCOM6_0 + DCD SERCOM6_1_Handler ; 71 SERCOM6_1 + DCD SERCOM6_2_Handler ; 72 SERCOM6_2 + DCD SERCOM6_3_Handler ; 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 + DCD SERCOM7_0_Handler ; 74 SERCOM7_0 + DCD SERCOM7_1_Handler ; 75 SERCOM7_1 + DCD SERCOM7_2_Handler ; 76 SERCOM7_2 + DCD SERCOM7_3_Handler ; 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 + DCD CAN0_Handler ; 78 Control Area Network 0 + DCD CAN1_Handler ; 79 Control Area Network 1 + DCD USB_0_Handler ; 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP + DCD USB_1_Handler ; 81 USB_SOF_HSOF + DCD USB_2_Handler ; 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 + DCD USB_3_Handler ; 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 + DCD GMAC_Handler ; 84 Ethernet MAC + DCD TCC0_0_Handler ; 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A + DCD TCC0_1_Handler ; 86 TCC0_MC_0 + DCD TCC0_2_Handler ; 87 TCC0_MC_1 + DCD TCC0_3_Handler ; 88 TCC0_MC_2 + DCD TCC0_4_Handler ; 89 TCC0_MC_3 + DCD TCC0_5_Handler ; 90 TCC0_MC_4 + DCD TCC0_6_Handler ; 91 TCC0_MC_5 + DCD TCC1_0_Handler ; 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A + DCD TCC1_1_Handler ; 93 TCC1_MC_0 + DCD TCC1_2_Handler ; 94 TCC1_MC_1 + DCD TCC1_3_Handler ; 95 TCC1_MC_2 + DCD TCC1_4_Handler ; 96 TCC1_MC_3 + DCD TCC2_0_Handler ; 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A + DCD TCC2_1_Handler ; 98 TCC2_MC_0 + DCD TCC2_2_Handler ; 99 TCC2_MC_1 + DCD TCC2_3_Handler ; 100 TCC2_MC_2 + DCD TCC3_0_Handler ; 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A + DCD TCC3_1_Handler ; 102 TCC3_MC_0 + DCD TCC3_2_Handler ; 103 TCC3_MC_1 + DCD TCC4_0_Handler ; 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A + DCD TCC4_1_Handler ; 105 TCC4_MC_0 + DCD TCC4_2_Handler ; 106 TCC4_MC_1 + DCD TC0_Handler ; 107 Basic Timer Counter 0 + DCD TC1_Handler ; 108 Basic Timer Counter 1 + DCD TC2_Handler ; 109 Basic Timer Counter 2 + DCD TC3_Handler ; 110 Basic Timer Counter 3 + DCD TC4_Handler ; 111 Basic Timer Counter 4 + DCD TC5_Handler ; 112 Basic Timer Counter 5 + DCD TC6_Handler ; 113 Basic Timer Counter 6 + DCD TC7_Handler ; 114 Basic Timer Counter 7 + DCD PDEC_0_Handler ; 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A + DCD PDEC_1_Handler ; 116 PDEC_MC_0 + DCD PDEC_2_Handler ; 117 PDEC_MC_1 + DCD ADC0_0_Handler ; 118 ADC0_OVERRUN, ADC0_WINMON + DCD ADC0_1_Handler ; 119 ADC0_RESRDY + DCD ADC1_0_Handler ; 120 ADC1_OVERRUN, ADC1_WINMON + DCD ADC1_1_Handler ; 121 ADC1_RESRDY + DCD AC_Handler ; 122 Analog Comparators + DCD DAC_0_Handler ; 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 + DCD DAC_1_Handler ; 124 DAC_EMPTY_0 + DCD DAC_2_Handler ; 125 DAC_EMPTY_1 + DCD DAC_3_Handler ; 126 DAC_RESRDY_0 + DCD DAC_4_Handler ; 127 DAC_RESRDY_1 + DCD I2S_Handler ; 128 Inter-IC Sound Interface + DCD PCC_Handler ; 129 Parallel Capture Controller + DCD AES_Handler ; 130 Advanced Encryption Standard + DCD TRNG_Handler ; 131 True Random Generator + DCD ICM_Handler ; 132 Integrity Check Monitor + DCD PUKCC_Handler ; 133 PUblic-Key Cryptography Controller + DCD QSPI_Handler ; 134 Quad SPI interface + DCD SDHC0_Handler ; 135 SD/MMC Host Controller 0 + DCD SDHC1_Handler ; 136 SD/MMC Host Controller 1 +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT PM_Handler [WEAK] + EXPORT MCLK_Handler [WEAK] + EXPORT OSCCTRL_0_Handler [WEAK] + EXPORT OSCCTRL_1_Handler [WEAK] + EXPORT OSCCTRL_2_Handler [WEAK] + EXPORT OSCCTRL_3_Handler [WEAK] + EXPORT OSCCTRL_4_Handler [WEAK] + EXPORT OSC32KCTRL_Handler [WEAK] + EXPORT SUPC_0_Handler [WEAK] + EXPORT SUPC_1_Handler [WEAK] + EXPORT WDT_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT EIC_0_Handler [WEAK] + EXPORT EIC_1_Handler [WEAK] + EXPORT EIC_2_Handler [WEAK] + EXPORT EIC_3_Handler [WEAK] + EXPORT EIC_4_Handler [WEAK] + EXPORT EIC_5_Handler [WEAK] + EXPORT EIC_6_Handler [WEAK] + EXPORT EIC_7_Handler [WEAK] + EXPORT EIC_8_Handler [WEAK] + EXPORT EIC_9_Handler [WEAK] + EXPORT EIC_10_Handler [WEAK] + EXPORT EIC_11_Handler [WEAK] + EXPORT EIC_12_Handler [WEAK] + EXPORT EIC_13_Handler [WEAK] + EXPORT EIC_14_Handler [WEAK] + EXPORT EIC_15_Handler [WEAK] + EXPORT FREQM_Handler [WEAK] + EXPORT NVMCTRL_0_Handler [WEAK] + EXPORT NVMCTRL_1_Handler [WEAK] + EXPORT DMAC_0_Handler [WEAK] + EXPORT DMAC_1_Handler [WEAK] + EXPORT DMAC_2_Handler [WEAK] + EXPORT DMAC_3_Handler [WEAK] + EXPORT DMAC_4_Handler [WEAK] + EXPORT EVSYS_0_Handler [WEAK] + EXPORT EVSYS_1_Handler [WEAK] + EXPORT EVSYS_2_Handler [WEAK] + EXPORT EVSYS_3_Handler [WEAK] + EXPORT EVSYS_4_Handler [WEAK] + EXPORT PAC_Handler [WEAK] + EXPORT TAL_0_Handler [WEAK] + EXPORT TAL_1_Handler [WEAK] + EXPORT RAMECC_Handler [WEAK] + EXPORT SERCOM0_0_Handler [WEAK] + EXPORT SERCOM0_1_Handler [WEAK] + EXPORT SERCOM0_2_Handler [WEAK] + EXPORT SERCOM0_3_Handler [WEAK] + EXPORT SERCOM1_0_Handler [WEAK] + EXPORT SERCOM1_1_Handler [WEAK] + EXPORT SERCOM1_2_Handler [WEAK] + EXPORT SERCOM1_3_Handler [WEAK] + EXPORT SERCOM2_0_Handler [WEAK] + EXPORT SERCOM2_1_Handler [WEAK] + EXPORT SERCOM2_2_Handler [WEAK] + EXPORT SERCOM2_3_Handler [WEAK] + EXPORT SERCOM3_0_Handler [WEAK] + EXPORT SERCOM3_1_Handler [WEAK] + EXPORT SERCOM3_2_Handler [WEAK] + EXPORT SERCOM3_3_Handler [WEAK] + EXPORT SERCOM4_0_Handler [WEAK] + EXPORT SERCOM4_1_Handler [WEAK] + EXPORT SERCOM4_2_Handler [WEAK] + EXPORT SERCOM4_3_Handler [WEAK] + EXPORT SERCOM5_0_Handler [WEAK] + EXPORT SERCOM5_1_Handler [WEAK] + EXPORT SERCOM5_2_Handler [WEAK] + EXPORT SERCOM5_3_Handler [WEAK] + EXPORT SERCOM6_0_Handler [WEAK] + EXPORT SERCOM6_1_Handler [WEAK] + EXPORT SERCOM6_2_Handler [WEAK] + EXPORT SERCOM6_3_Handler [WEAK] + EXPORT SERCOM7_0_Handler [WEAK] + EXPORT SERCOM7_1_Handler [WEAK] + EXPORT SERCOM7_2_Handler [WEAK] + EXPORT SERCOM7_3_Handler [WEAK] + EXPORT CAN0_Handler [WEAK] + EXPORT CAN1_Handler [WEAK] + EXPORT USB_0_Handler [WEAK] + EXPORT USB_1_Handler [WEAK] + EXPORT USB_2_Handler [WEAK] + EXPORT USB_3_Handler [WEAK] + EXPORT GMAC_Handler [WEAK] + EXPORT TCC0_0_Handler [WEAK] + EXPORT TCC0_1_Handler [WEAK] + EXPORT TCC0_2_Handler [WEAK] + EXPORT TCC0_3_Handler [WEAK] + EXPORT TCC0_4_Handler [WEAK] + EXPORT TCC0_5_Handler [WEAK] + EXPORT TCC0_6_Handler [WEAK] + EXPORT TCC1_0_Handler [WEAK] + EXPORT TCC1_1_Handler [WEAK] + EXPORT TCC1_2_Handler [WEAK] + EXPORT TCC1_3_Handler [WEAK] + EXPORT TCC1_4_Handler [WEAK] + EXPORT TCC2_0_Handler [WEAK] + EXPORT TCC2_1_Handler [WEAK] + EXPORT TCC2_2_Handler [WEAK] + EXPORT TCC2_3_Handler [WEAK] + EXPORT TCC3_0_Handler [WEAK] + EXPORT TCC3_1_Handler [WEAK] + EXPORT TCC3_2_Handler [WEAK] + EXPORT TCC4_0_Handler [WEAK] + EXPORT TCC4_1_Handler [WEAK] + EXPORT TCC4_2_Handler [WEAK] + EXPORT TC0_Handler [WEAK] + EXPORT TC1_Handler [WEAK] + EXPORT TC2_Handler [WEAK] + EXPORT TC3_Handler [WEAK] + EXPORT TC4_Handler [WEAK] + EXPORT TC5_Handler [WEAK] + EXPORT TC6_Handler [WEAK] + EXPORT TC7_Handler [WEAK] + EXPORT PDEC_0_Handler [WEAK] + EXPORT PDEC_1_Handler [WEAK] + EXPORT PDEC_2_Handler [WEAK] + EXPORT ADC0_0_Handler [WEAK] + EXPORT ADC0_1_Handler [WEAK] + EXPORT ADC1_0_Handler [WEAK] + EXPORT ADC1_1_Handler [WEAK] + EXPORT AC_Handler [WEAK] + EXPORT DAC_0_Handler [WEAK] + EXPORT DAC_1_Handler [WEAK] + EXPORT DAC_2_Handler [WEAK] + EXPORT DAC_3_Handler [WEAK] + EXPORT DAC_4_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + EXPORT PCC_Handler [WEAK] + EXPORT AES_Handler [WEAK] + EXPORT TRNG_Handler [WEAK] + EXPORT ICM_Handler [WEAK] + EXPORT PUKCC_Handler [WEAK] + EXPORT QSPI_Handler [WEAK] + EXPORT SDHC0_Handler [WEAK] + EXPORT SDHC1_Handler [WEAK] + +PM_Handler +MCLK_Handler +OSCCTRL_0_Handler +OSCCTRL_1_Handler +OSCCTRL_2_Handler +OSCCTRL_3_Handler +OSCCTRL_4_Handler +OSC32KCTRL_Handler +SUPC_0_Handler +SUPC_1_Handler +WDT_Handler +RTC_Handler +EIC_0_Handler +EIC_1_Handler +EIC_2_Handler +EIC_3_Handler +EIC_4_Handler +EIC_5_Handler +EIC_6_Handler +EIC_7_Handler +EIC_8_Handler +EIC_9_Handler +EIC_10_Handler +EIC_11_Handler +EIC_12_Handler +EIC_13_Handler +EIC_14_Handler +EIC_15_Handler +FREQM_Handler +NVMCTRL_0_Handler +NVMCTRL_1_Handler +DMAC_0_Handler +DMAC_1_Handler +DMAC_2_Handler +DMAC_3_Handler +DMAC_4_Handler +EVSYS_0_Handler +EVSYS_1_Handler +EVSYS_2_Handler +EVSYS_3_Handler +EVSYS_4_Handler +PAC_Handler +TAL_0_Handler +TAL_1_Handler +RAMECC_Handler +SERCOM0_0_Handler +SERCOM0_1_Handler +SERCOM0_2_Handler +SERCOM0_3_Handler +SERCOM1_0_Handler +SERCOM1_1_Handler +SERCOM1_2_Handler +SERCOM1_3_Handler +SERCOM2_0_Handler +SERCOM2_1_Handler +SERCOM2_2_Handler +SERCOM2_3_Handler +SERCOM3_0_Handler +SERCOM3_1_Handler +SERCOM3_2_Handler +SERCOM3_3_Handler +SERCOM4_0_Handler +SERCOM4_1_Handler +SERCOM4_2_Handler +SERCOM4_3_Handler +SERCOM5_0_Handler +SERCOM5_1_Handler +SERCOM5_2_Handler +SERCOM5_3_Handler +SERCOM6_0_Handler +SERCOM6_1_Handler +SERCOM6_2_Handler +SERCOM6_3_Handler +SERCOM7_0_Handler +SERCOM7_1_Handler +SERCOM7_2_Handler +SERCOM7_3_Handler +CAN0_Handler +CAN1_Handler +USB_0_Handler +USB_1_Handler +USB_2_Handler +USB_3_Handler +GMAC_Handler +TCC0_0_Handler +TCC0_1_Handler +TCC0_2_Handler +TCC0_3_Handler +TCC0_4_Handler +TCC0_5_Handler +TCC0_6_Handler +TCC1_0_Handler +TCC1_1_Handler +TCC1_2_Handler +TCC1_3_Handler +TCC1_4_Handler +TCC2_0_Handler +TCC2_1_Handler +TCC2_2_Handler +TCC2_3_Handler +TCC3_0_Handler +TCC3_1_Handler +TCC3_2_Handler +TCC4_0_Handler +TCC4_1_Handler +TCC4_2_Handler +TC0_Handler +TC1_Handler +TC2_Handler +TC3_Handler +TC4_Handler +TC5_Handler +TC6_Handler +TC7_Handler +PDEC_0_Handler +PDEC_1_Handler +PDEC_2_Handler +ADC0_0_Handler +ADC0_1_Handler +ADC1_0_Handler +ADC1_1_Handler +AC_Handler +DAC_0_Handler +DAC_1_Handler +DAC_2_Handler +DAC_3_Handler +DAC_4_Handler +I2S_Handler +PCC_Handler +AES_Handler +TRNG_Handler +ICM_Handler +PUKCC_Handler +QSPI_Handler +SDHC0_Handler +SDHC1_Handler + B . + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/software/firmware/oracle_same54n19a/armcc/arm_addon/armcc/system_same54.c b/software/firmware/oracle_same54n19a/armcc/arm_addon/armcc/system_same54.c new file mode 100644 index 00000000..95d30360 --- /dev/null +++ b/software/firmware/oracle_same54n19a/armcc/arm_addon/armcc/system_same54.c @@ -0,0 +1,70 @@ +/** + * \file + * + * \brief Low-level initialization functions called upon chip startup. + * + * Copyright (c) 2016 Atmel Corporation, + * a wholly owned subsidiary of Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#include "same54.h" + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (48000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ +#if __FPU_USED + /* Enable FPU */ + SCB->CPACR |= (0xFu << 20); + __DSB(); + __ISB(); +#endif + + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} diff --git a/software/firmware/oracle_same54n19a/atmel_start.c b/software/firmware/oracle_same54n19a/atmel_start.c new file mode 100644 index 00000000..79f252ae --- /dev/null +++ b/software/firmware/oracle_same54n19a/atmel_start.c @@ -0,0 +1,9 @@ +#include + +/** + * Initializes MCU, drivers and middleware in the project + **/ +void atmel_start_init(void) +{ + system_init(); +} diff --git a/software/firmware/oracle_same54n19a/atmel_start.h b/software/firmware/oracle_same54n19a/atmel_start.h new file mode 100644 index 00000000..0de62f52 --- /dev/null +++ b/software/firmware/oracle_same54n19a/atmel_start.h @@ -0,0 +1,18 @@ +#ifndef ATMEL_START_H_INCLUDED +#define ATMEL_START_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include "driver_init.h" + +/** + * Initializes MCU, drivers and middleware in the project + **/ +void atmel_start_init(void); + +#ifdef __cplusplus +} +#endif +#endif diff --git a/software/firmware/oracle_same54n19a/atmel_start_config.atstart b/software/firmware/oracle_same54n19a/atmel_start_config.atstart new file mode 100644 index 00000000..00db73c4 --- /dev/null +++ b/software/firmware/oracle_same54n19a/atmel_start_config.atstart @@ -0,0 +1,1201 @@ +format_version: '2' +name: My Project +versions: + api: '1.0' + backend: 1.8.580 + commit: f3d8d96e294de8dee688333bbbe8d8458a4f6b4c + content: unknown + content_pack_name: unknown + format: '2' + frontend: 1.8.580 + packs_version_avr8: 1.0.1463 + packs_version_qtouch: unknown + packs_version_sam: 1.0.1726 + version_backend: 1.8.580 + version_frontend: '' +board: + identifier: CustomBoard + device: SAME54N19A-AF +details: null +application: null +middlewares: {} +drivers: + CMCC: + user_label: CMCC + definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::CMCC::driver_config_definition::CMCC::HAL:HPL:CMCC + functionality: System + api: HAL:HPL:CMCC + configuration: + cache_size: 4 KB + cmcc_advanced_configuration: false + cmcc_clock_gating_disable: false + cmcc_data_cache_disable: false + cmcc_enable: false + cmcc_inst_cache_disable: false + optional_signals: [] + variant: null + clocks: + domain_group: null + DMAC: + user_label: DMAC + definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::DMAC::driver_config_definition::DMAC::HAL:HPL:DMAC + functionality: System + api: HAL:HPL:DMAC + configuration: + dmac_beatsize_0: 8-bit bus transfer + dmac_beatsize_1: 8-bit bus transfer + dmac_beatsize_10: 8-bit bus transfer + dmac_beatsize_11: 8-bit bus transfer + dmac_beatsize_12: 8-bit bus transfer + dmac_beatsize_13: 8-bit bus transfer + dmac_beatsize_14: 8-bit bus transfer + dmac_beatsize_15: 8-bit bus transfer + dmac_beatsize_16: 8-bit bus transfer + dmac_beatsize_17: 8-bit bus transfer + dmac_beatsize_18: 8-bit bus transfer + dmac_beatsize_19: 8-bit bus transfer + dmac_beatsize_2: 8-bit bus transfer + dmac_beatsize_20: 8-bit bus transfer + dmac_beatsize_21: 8-bit bus transfer + dmac_beatsize_22: 8-bit bus transfer + dmac_beatsize_23: 8-bit bus transfer + dmac_beatsize_24: 8-bit bus transfer + dmac_beatsize_25: 8-bit bus transfer + dmac_beatsize_26: 8-bit bus transfer + dmac_beatsize_27: 8-bit bus transfer + dmac_beatsize_28: 8-bit bus transfer + dmac_beatsize_29: 8-bit bus transfer + dmac_beatsize_3: 8-bit bus transfer + dmac_beatsize_30: 8-bit bus transfer + dmac_beatsize_31: 8-bit bus transfer + dmac_beatsize_4: 8-bit bus transfer + dmac_beatsize_5: 8-bit bus transfer + dmac_beatsize_6: 8-bit bus transfer + dmac_beatsize_7: 8-bit bus transfer + dmac_beatsize_8: 8-bit bus transfer + dmac_beatsize_9: 8-bit bus transfer + dmac_blockact_0: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_1: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_10: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_11: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_12: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_13: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_14: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_15: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_16: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_17: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_18: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_19: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_2: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_20: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_21: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_22: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_23: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_24: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_25: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_26: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_27: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_28: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_29: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_3: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_30: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_31: Channel will be disabled if it is the last block transfer + in the transaction + dmac_blockact_4: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_5: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_6: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_7: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_8: Channel will be disabled if it is the last block transfer in + the transaction + dmac_blockact_9: Channel will be disabled if it is the last block transfer in + the transaction + dmac_channel_0_settings: false + dmac_channel_10_settings: false + dmac_channel_11_settings: false + dmac_channel_12_settings: false + dmac_channel_13_settings: false + dmac_channel_14_settings: false + dmac_channel_15_settings: false + dmac_channel_16_settings: false + dmac_channel_17_settings: false + dmac_channel_18_settings: false + dmac_channel_19_settings: false + dmac_channel_1_settings: false + dmac_channel_20_settings: false + dmac_channel_21_settings: false + dmac_channel_22_settings: false + dmac_channel_23_settings: false + dmac_channel_24_settings: false + dmac_channel_25_settings: false + dmac_channel_26_settings: false + dmac_channel_27_settings: false + dmac_channel_28_settings: false + dmac_channel_29_settings: false + dmac_channel_2_settings: false + dmac_channel_30_settings: false + dmac_channel_31_settings: false + dmac_channel_3_settings: false + dmac_channel_4_settings: false + dmac_channel_5_settings: false + dmac_channel_6_settings: false + dmac_channel_7_settings: false + dmac_channel_8_settings: false + dmac_channel_9_settings: false + dmac_dbgrun: false + dmac_dstinc_0: false + dmac_dstinc_1: false + dmac_dstinc_10: false + dmac_dstinc_11: false + dmac_dstinc_12: false + dmac_dstinc_13: false + dmac_dstinc_14: false + dmac_dstinc_15: false + dmac_dstinc_16: false + dmac_dstinc_17: false + dmac_dstinc_18: false + dmac_dstinc_19: false + dmac_dstinc_2: false + dmac_dstinc_20: false + dmac_dstinc_21: false + dmac_dstinc_22: false + dmac_dstinc_23: false + dmac_dstinc_24: false + dmac_dstinc_25: false + dmac_dstinc_26: false + dmac_dstinc_27: false + dmac_dstinc_28: false + dmac_dstinc_29: false + dmac_dstinc_3: false + dmac_dstinc_30: false + dmac_dstinc_31: false + dmac_dstinc_4: false + dmac_dstinc_5: false + dmac_dstinc_6: false + dmac_dstinc_7: false + dmac_dstinc_8: false + dmac_dstinc_9: false + dmac_enable: false + dmac_evact_0: No action + dmac_evact_1: No action + dmac_evact_10: No action + dmac_evact_11: No action + dmac_evact_12: No action + dmac_evact_13: No action + dmac_evact_14: No action + dmac_evact_15: No action + dmac_evact_16: No action + dmac_evact_17: No action + dmac_evact_18: No action + dmac_evact_19: No action + dmac_evact_2: No action + dmac_evact_20: No action + dmac_evact_21: No action + dmac_evact_22: No action + dmac_evact_23: No action + dmac_evact_24: No action + dmac_evact_25: No action + dmac_evact_26: No action + dmac_evact_27: No action + dmac_evact_28: No action + dmac_evact_29: No action + dmac_evact_3: No action + dmac_evact_30: No action + dmac_evact_31: No action + dmac_evact_4: No action + dmac_evact_5: No action + dmac_evact_6: No action + dmac_evact_7: No action + dmac_evact_8: No action + dmac_evact_9: No action + dmac_evie_0: false + dmac_evie_1: false + dmac_evie_10: false + dmac_evie_11: false + dmac_evie_12: false + dmac_evie_13: false + dmac_evie_14: false + dmac_evie_15: false + dmac_evie_16: false + dmac_evie_17: false + dmac_evie_18: false + dmac_evie_19: false + dmac_evie_2: false + dmac_evie_20: false + dmac_evie_21: false + dmac_evie_22: false + dmac_evie_23: false + dmac_evie_24: false + dmac_evie_25: false + dmac_evie_26: false + dmac_evie_27: false + dmac_evie_28: false + dmac_evie_29: false + dmac_evie_3: false + dmac_evie_30: false + dmac_evie_31: false + dmac_evie_4: false + dmac_evie_5: false + dmac_evie_6: false + dmac_evie_7: false + dmac_evie_8: false + dmac_evie_9: false + dmac_evoe_0: false + dmac_evoe_1: false + dmac_evoe_10: false + dmac_evoe_11: false + dmac_evoe_12: false + dmac_evoe_13: false + dmac_evoe_14: false + dmac_evoe_15: false + dmac_evoe_16: false + dmac_evoe_17: false + dmac_evoe_18: false + dmac_evoe_19: false + dmac_evoe_2: false + dmac_evoe_20: false + dmac_evoe_21: false + dmac_evoe_22: false + dmac_evoe_23: false + dmac_evoe_24: false + dmac_evoe_25: false + dmac_evoe_26: false + dmac_evoe_27: false + dmac_evoe_28: false + dmac_evoe_29: false + dmac_evoe_3: false + dmac_evoe_30: false + dmac_evoe_31: false + dmac_evoe_4: false + dmac_evoe_5: false + dmac_evoe_6: false + dmac_evoe_7: false + dmac_evoe_8: false + dmac_evoe_9: false + dmac_evosel_0: Event generation disabled + dmac_evosel_1: Event generation disabled + dmac_evosel_10: Event generation disabled + dmac_evosel_11: Event generation disabled + dmac_evosel_12: Event generation disabled + dmac_evosel_13: Event generation disabled + dmac_evosel_14: Event generation disabled + dmac_evosel_15: Event generation disabled + dmac_evosel_16: Event generation disabled + dmac_evosel_17: Event generation disabled + dmac_evosel_18: Event generation disabled + dmac_evosel_19: Event generation disabled + dmac_evosel_2: Event generation disabled + dmac_evosel_20: Event generation disabled + dmac_evosel_21: Event generation disabled + dmac_evosel_22: Event generation disabled + dmac_evosel_23: Event generation disabled + dmac_evosel_24: Event generation disabled + dmac_evosel_25: Event generation disabled + dmac_evosel_26: Event generation disabled + dmac_evosel_27: Event generation disabled + dmac_evosel_28: Event generation disabled + dmac_evosel_29: Event generation disabled + dmac_evosel_3: Event generation disabled + dmac_evosel_30: Event generation disabled + dmac_evosel_31: Event generation disabled + dmac_evosel_4: Event generation disabled + dmac_evosel_5: Event generation disabled + dmac_evosel_6: Event generation disabled + dmac_evosel_7: Event generation disabled + dmac_evosel_8: Event generation disabled + dmac_evosel_9: Event generation disabled + dmac_lvl_0: Channel priority 0 + dmac_lvl_1: Channel priority 0 + dmac_lvl_10: Channel priority 0 + dmac_lvl_11: Channel priority 0 + dmac_lvl_12: Channel priority 0 + dmac_lvl_13: Channel priority 0 + dmac_lvl_14: Channel priority 0 + dmac_lvl_15: Channel priority 0 + dmac_lvl_16: Channel priority 0 + dmac_lvl_17: Channel priority 0 + dmac_lvl_18: Channel priority 0 + dmac_lvl_19: Channel priority 0 + dmac_lvl_2: Channel priority 0 + dmac_lvl_20: Channel priority 0 + dmac_lvl_21: Channel priority 0 + dmac_lvl_22: Channel priority 0 + dmac_lvl_23: Channel priority 0 + dmac_lvl_24: Channel priority 0 + dmac_lvl_25: Channel priority 0 + dmac_lvl_26: Channel priority 0 + dmac_lvl_27: Channel priority 0 + dmac_lvl_28: Channel priority 0 + dmac_lvl_29: Channel priority 0 + dmac_lvl_3: Channel priority 0 + dmac_lvl_30: Channel priority 0 + dmac_lvl_31: Channel priority 0 + dmac_lvl_4: Channel priority 0 + dmac_lvl_5: Channel priority 0 + dmac_lvl_6: Channel priority 0 + dmac_lvl_7: Channel priority 0 + dmac_lvl_8: Channel priority 0 + dmac_lvl_9: Channel priority 0 + dmac_lvlen0: true + dmac_lvlen1: true + dmac_lvlen2: true + dmac_lvlen3: true + dmac_lvlpri0: 0 + dmac_lvlpri1: 0 + dmac_lvlpri2: 0 + dmac_lvlpri3: 0 + dmac_rrlvlen0: Static arbitration scheme for channel with priority 0 + dmac_rrlvlen1: Static arbitration scheme for channel with priority 1 + dmac_rrlvlen2: Static arbitration scheme for channel with priority 2 + dmac_rrlvlen3: Static arbitration scheme for channel with priority 3 + dmac_runstdby_0: false + dmac_runstdby_1: false + dmac_runstdby_10: false + dmac_runstdby_11: false + dmac_runstdby_12: false + dmac_runstdby_13: false + dmac_runstdby_14: false + dmac_runstdby_15: false + dmac_runstdby_16: false + dmac_runstdby_17: false + dmac_runstdby_18: false + dmac_runstdby_19: false + dmac_runstdby_2: false + dmac_runstdby_20: false + dmac_runstdby_21: false + dmac_runstdby_22: false + dmac_runstdby_23: false + dmac_runstdby_24: false + dmac_runstdby_25: false + dmac_runstdby_26: false + dmac_runstdby_27: false + dmac_runstdby_28: false + dmac_runstdby_29: false + dmac_runstdby_3: false + dmac_runstdby_30: false + dmac_runstdby_31: false + dmac_runstdby_4: false + dmac_runstdby_5: false + dmac_runstdby_6: false + dmac_runstdby_7: false + dmac_runstdby_8: false + dmac_runstdby_9: false + dmac_srcinc_0: false + dmac_srcinc_1: false + dmac_srcinc_10: false + dmac_srcinc_11: false + dmac_srcinc_12: false + dmac_srcinc_13: false + dmac_srcinc_14: false + dmac_srcinc_15: false + dmac_srcinc_16: false + dmac_srcinc_17: false + dmac_srcinc_18: false + dmac_srcinc_19: false + dmac_srcinc_2: false + dmac_srcinc_20: false + dmac_srcinc_21: false + dmac_srcinc_22: false + dmac_srcinc_23: false + dmac_srcinc_24: false + dmac_srcinc_25: false + dmac_srcinc_26: false + dmac_srcinc_27: false + dmac_srcinc_28: false + dmac_srcinc_29: false + dmac_srcinc_3: false + dmac_srcinc_30: false + dmac_srcinc_31: false + dmac_srcinc_4: false + dmac_srcinc_5: false + dmac_srcinc_6: false + dmac_srcinc_7: false + dmac_srcinc_8: false + dmac_srcinc_9: false + dmac_stepsel_0: Step size settings apply to the destination address + dmac_stepsel_1: Step size settings apply to the destination address + dmac_stepsel_10: Step size settings apply to the destination address + dmac_stepsel_11: Step size settings apply to the destination address + dmac_stepsel_12: Step size settings apply to the destination address + dmac_stepsel_13: Step size settings apply to the destination address + dmac_stepsel_14: Step size settings apply to the destination address + dmac_stepsel_15: Step size settings apply to the destination address + dmac_stepsel_16: Step size settings apply to the destination address + dmac_stepsel_17: Step size settings apply to the destination address + dmac_stepsel_18: Step size settings apply to the destination address + dmac_stepsel_19: Step size settings apply to the destination address + dmac_stepsel_2: Step size settings apply to the destination address + dmac_stepsel_20: Step size settings apply to the destination address + dmac_stepsel_21: Step size settings apply to the destination address + dmac_stepsel_22: Step size settings apply to the destination address + dmac_stepsel_23: Step size settings apply to the destination address + dmac_stepsel_24: Step size settings apply to the destination address + dmac_stepsel_25: Step size settings apply to the destination address + dmac_stepsel_26: Step size settings apply to the destination address + dmac_stepsel_27: Step size settings apply to the destination address + dmac_stepsel_28: Step size settings apply to the destination address + dmac_stepsel_29: Step size settings apply to the destination address + dmac_stepsel_3: Step size settings apply to the destination address + dmac_stepsel_30: Step size settings apply to the destination address + dmac_stepsel_31: Step size settings apply to the destination address + dmac_stepsel_4: Step size settings apply to the destination address + dmac_stepsel_5: Step size settings apply to the destination address + dmac_stepsel_6: Step size settings apply to the destination address + dmac_stepsel_7: Step size settings apply to the destination address + dmac_stepsel_8: Step size settings apply to the destination address + dmac_stepsel_9: Step size settings apply to the destination address + dmac_stepsize_0: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_1: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_10: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_11: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_12: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_13: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_14: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_15: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_16: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_17: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_18: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_19: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_2: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_20: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_21: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_22: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_23: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_24: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_25: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_26: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_27: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_28: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_29: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_3: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_30: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_31: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_4: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_5: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_6: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_7: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_8: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_stepsize_9: Next ADDR = ADDR + (BEATSIZE + 1) * 1 + dmac_trifsrc_0: Only software/event triggers + dmac_trifsrc_1: Only software/event triggers + dmac_trifsrc_10: Only software/event triggers + dmac_trifsrc_11: Only software/event triggers + dmac_trifsrc_12: Only software/event triggers + dmac_trifsrc_13: Only software/event triggers + dmac_trifsrc_14: Only software/event triggers + dmac_trifsrc_15: Only software/event triggers + dmac_trifsrc_16: Only software/event triggers + dmac_trifsrc_17: Only software/event triggers + dmac_trifsrc_18: Only software/event triggers + dmac_trifsrc_19: Only software/event triggers + dmac_trifsrc_2: Only software/event triggers + dmac_trifsrc_20: Only software/event triggers + dmac_trifsrc_21: Only software/event triggers + dmac_trifsrc_22: Only software/event triggers + dmac_trifsrc_23: Only software/event triggers + dmac_trifsrc_24: Only software/event triggers + dmac_trifsrc_25: Only software/event triggers + dmac_trifsrc_26: Only software/event triggers + dmac_trifsrc_27: Only software/event triggers + dmac_trifsrc_28: Only software/event triggers + dmac_trifsrc_29: Only software/event triggers + dmac_trifsrc_3: Only software/event triggers + dmac_trifsrc_30: Only software/event triggers + dmac_trifsrc_31: Only software/event triggers + dmac_trifsrc_4: Only software/event triggers + dmac_trifsrc_5: Only software/event triggers + dmac_trifsrc_6: Only software/event triggers + dmac_trifsrc_7: Only software/event triggers + dmac_trifsrc_8: Only software/event triggers + dmac_trifsrc_9: Only software/event triggers + dmac_trigact_0: One trigger required for each block transfer + dmac_trigact_1: One trigger required for each block transfer + dmac_trigact_10: One trigger required for each block transfer + dmac_trigact_11: One trigger required for each block transfer + dmac_trigact_12: One trigger required for each block transfer + dmac_trigact_13: One trigger required for each block transfer + dmac_trigact_14: One trigger required for each block transfer + dmac_trigact_15: One trigger required for each block transfer + dmac_trigact_16: One trigger required for each block transfer + dmac_trigact_17: One trigger required for each block transfer + dmac_trigact_18: One trigger required for each block transfer + dmac_trigact_19: One trigger required for each block transfer + dmac_trigact_2: One trigger required for each block transfer + dmac_trigact_20: One trigger required for each block transfer + dmac_trigact_21: One trigger required for each block transfer + dmac_trigact_22: One trigger required for each block transfer + dmac_trigact_23: One trigger required for each block transfer + dmac_trigact_24: One trigger required for each block transfer + dmac_trigact_25: One trigger required for each block transfer + dmac_trigact_26: One trigger required for each block transfer + dmac_trigact_27: One trigger required for each block transfer + dmac_trigact_28: One trigger required for each block transfer + dmac_trigact_29: One trigger required for each block transfer + dmac_trigact_3: One trigger required for each block transfer + dmac_trigact_30: One trigger required for each block transfer + dmac_trigact_31: One trigger required for each block transfer + dmac_trigact_4: One trigger required for each block transfer + dmac_trigact_5: One trigger required for each block transfer + dmac_trigact_6: One trigger required for each block transfer + dmac_trigact_7: One trigger required for each block transfer + dmac_trigact_8: One trigger required for each block transfer + dmac_trigact_9: One trigger required for each block transfer + optional_signals: [] + variant: null + clocks: + domain_group: null + EXTERNAL_IRQ_0: + user_label: EXTERNAL_IRQ_0 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::EIC::driver_config_definition::Default::HAL:Driver:Ext.IRQ + functionality: External_IRQ + api: HAL:Driver:Ext_IRQ + configuration: + eic_arch_asynch0: false + eic_arch_asynch1: false + eic_arch_asynch10: false + eic_arch_asynch11: false + eic_arch_asynch12: false + eic_arch_asynch13: false + eic_arch_asynch14: false + eic_arch_asynch15: false + eic_arch_asynch2: false + eic_arch_asynch3: false + eic_arch_asynch4: false + eic_arch_asynch5: false + eic_arch_asynch6: false + eic_arch_asynch7: false + eic_arch_asynch8: false + eic_arch_asynch9: false + eic_arch_cksel: Clocked by GCLK + eic_arch_debounce_enable0: false + eic_arch_debounce_enable1: false + eic_arch_debounce_enable10: false + eic_arch_debounce_enable11: false + eic_arch_debounce_enable12: false + eic_arch_debounce_enable13: false + eic_arch_debounce_enable14: false + eic_arch_debounce_enable15: false + eic_arch_debounce_enable2: false + eic_arch_debounce_enable3: false + eic_arch_debounce_enable4: false + eic_arch_debounce_enable5: false + eic_arch_debounce_enable6: false + eic_arch_debounce_enable7: false + eic_arch_debounce_enable8: false + eic_arch_debounce_enable9: false + eic_arch_enable_irq_setting0: false + eic_arch_enable_irq_setting1: false + eic_arch_enable_irq_setting10: false + eic_arch_enable_irq_setting11: false + eic_arch_enable_irq_setting12: false + eic_arch_enable_irq_setting13: false + eic_arch_enable_irq_setting14: false + eic_arch_enable_irq_setting15: false + eic_arch_enable_irq_setting2: false + eic_arch_enable_irq_setting3: false + eic_arch_enable_irq_setting4: false + eic_arch_enable_irq_setting5: false + eic_arch_enable_irq_setting6: false + eic_arch_enable_irq_setting7: false + eic_arch_enable_irq_setting8: false + eic_arch_enable_irq_setting9: false + eic_arch_extinteo0: false + eic_arch_extinteo1: false + eic_arch_extinteo10: false + eic_arch_extinteo11: false + eic_arch_extinteo12: false + eic_arch_extinteo13: false + eic_arch_extinteo14: false + eic_arch_extinteo15: false + eic_arch_extinteo2: false + eic_arch_extinteo3: false + eic_arch_extinteo4: false + eic_arch_extinteo5: false + eic_arch_extinteo6: false + eic_arch_extinteo7: false + eic_arch_extinteo8: false + eic_arch_extinteo9: false + eic_arch_filten0: false + eic_arch_filten1: false + eic_arch_filten10: false + eic_arch_filten11: false + eic_arch_filten12: false + eic_arch_filten13: false + eic_arch_filten14: false + eic_arch_filten15: false + eic_arch_filten2: false + eic_arch_filten3: false + eic_arch_filten4: false + eic_arch_filten5: false + eic_arch_filten6: false + eic_arch_filten7: false + eic_arch_filten8: false + eic_arch_filten9: false + eic_arch_nmi_ctrl: false + eic_arch_nmiasynch: false + eic_arch_nmifilten: false + eic_arch_nmisense: No detection + eic_arch_prescaler0: Divided by 2 + eic_arch_prescaler1: Divided by 2 + eic_arch_sense0: No detection + eic_arch_sense1: No detection + eic_arch_sense10: No detection + eic_arch_sense11: No detection + eic_arch_sense12: No detection + eic_arch_sense13: No detection + eic_arch_sense14: No detection + eic_arch_sense15: No detection + eic_arch_sense2: No detection + eic_arch_sense3: No detection + eic_arch_sense4: No detection + eic_arch_sense5: No detection + eic_arch_sense6: No detection + eic_arch_sense7: No detection + eic_arch_sense8: No detection + eic_arch_sense9: No detection + eic_arch_states0: '3' + eic_arch_states1: '3' + eic_arch_tickon: The sampling rate is EIC clock + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: EIC + input: Generic clock generator 0 + external: false + external_frequency: 0 + configuration: + eic_gclk_selection: Generic clock generator 0 + GCLK: + user_label: GCLK + definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::GCLK::driver_config_definition::GCLK::HAL:HPL:GCLK + functionality: System + api: HAL:HPL:GCLK + configuration: + $input: 12000000 + $input_id: External Crystal Oscillator 8-48MHz (XOSC1) + RESERVED_InputFreq: 12000000 + RESERVED_InputFreq_id: External Crystal Oscillator 8-48MHz (XOSC1) + _$freq_output_Generic clock generator 0: 119997440 + _$freq_output_Generic clock generator 1: 48000000 + _$freq_output_Generic clock generator 10: 12000000 + _$freq_output_Generic clock generator 11: 12000000 + _$freq_output_Generic clock generator 2: 3000000 + _$freq_output_Generic clock generator 3: 32768 + _$freq_output_Generic clock generator 4: 12000000 + _$freq_output_Generic clock generator 5: 12000000 + _$freq_output_Generic clock generator 6: 12000000 + _$freq_output_Generic clock generator 7: 12000000 + _$freq_output_Generic clock generator 8: 12000000 + _$freq_output_Generic clock generator 9: 12000000 + enable_gclk_gen_0: true + enable_gclk_gen_0__externalclock: 1000000 + enable_gclk_gen_1: false + enable_gclk_gen_10: false + enable_gclk_gen_10__externalclock: 1000000 + enable_gclk_gen_11: false + enable_gclk_gen_11__externalclock: 1000000 + enable_gclk_gen_1__externalclock: 1000000 + enable_gclk_gen_2: false + enable_gclk_gen_2__externalclock: 1000000 + enable_gclk_gen_3: false + enable_gclk_gen_3__externalclock: 1000000 + enable_gclk_gen_4: false + enable_gclk_gen_4__externalclock: 1000000 + enable_gclk_gen_5: false + enable_gclk_gen_5__externalclock: 1000000 + enable_gclk_gen_6: false + enable_gclk_gen_6__externalclock: 1000000 + enable_gclk_gen_7: false + enable_gclk_gen_7__externalclock: 1000000 + enable_gclk_gen_8: false + enable_gclk_gen_8__externalclock: 1000000 + enable_gclk_gen_9: false + enable_gclk_gen_9__externalclock: 1000000 + gclk_arch_gen_0_enable: true + gclk_arch_gen_0_idc: false + gclk_arch_gen_0_oe: false + gclk_arch_gen_0_oov: false + gclk_arch_gen_0_runstdby: false + gclk_arch_gen_10_enable: false + gclk_arch_gen_10_idc: false + gclk_arch_gen_10_oe: false + gclk_arch_gen_10_oov: false + gclk_arch_gen_10_runstdby: false + gclk_arch_gen_11_enable: false + gclk_arch_gen_11_idc: false + gclk_arch_gen_11_oe: false + gclk_arch_gen_11_oov: false + gclk_arch_gen_11_runstdby: false + gclk_arch_gen_1_enable: false + gclk_arch_gen_1_idc: false + gclk_arch_gen_1_oe: false + gclk_arch_gen_1_oov: false + gclk_arch_gen_1_runstdby: false + gclk_arch_gen_2_enable: false + gclk_arch_gen_2_idc: false + gclk_arch_gen_2_oe: false + gclk_arch_gen_2_oov: false + gclk_arch_gen_2_runstdby: false + gclk_arch_gen_3_enable: false + gclk_arch_gen_3_idc: false + gclk_arch_gen_3_oe: false + gclk_arch_gen_3_oov: false + gclk_arch_gen_3_runstdby: false + gclk_arch_gen_4_enable: false + gclk_arch_gen_4_idc: false + gclk_arch_gen_4_oe: false + gclk_arch_gen_4_oov: false + gclk_arch_gen_4_runstdby: false + gclk_arch_gen_5_enable: false + gclk_arch_gen_5_idc: false + gclk_arch_gen_5_oe: false + gclk_arch_gen_5_oov: false + gclk_arch_gen_5_runstdby: false + gclk_arch_gen_6_enable: false + gclk_arch_gen_6_idc: false + gclk_arch_gen_6_oe: false + gclk_arch_gen_6_oov: false + gclk_arch_gen_6_runstdby: false + gclk_arch_gen_7_enable: false + gclk_arch_gen_7_idc: false + gclk_arch_gen_7_oe: false + gclk_arch_gen_7_oov: false + gclk_arch_gen_7_runstdby: false + gclk_arch_gen_8_enable: false + gclk_arch_gen_8_idc: false + gclk_arch_gen_8_oe: false + gclk_arch_gen_8_oov: false + gclk_arch_gen_8_runstdby: false + gclk_arch_gen_9_enable: false + gclk_arch_gen_9_idc: false + gclk_arch_gen_9_oe: false + gclk_arch_gen_9_oov: false + gclk_arch_gen_9_runstdby: false + gclk_gen_0_div: 1 + gclk_gen_0_div_sel: false + gclk_gen_0_oscillator: Digital Phase Locked Loop (DPLL0) + gclk_gen_10_div: 1 + gclk_gen_10_div_sel: false + gclk_gen_10_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_11_div: 1 + gclk_gen_11_div_sel: false + gclk_gen_11_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_1_div: 1 + gclk_gen_1_div_sel: false + gclk_gen_1_oscillator: Digital Frequency Locked Loop (DFLL48M) + gclk_gen_2_div: 1 + gclk_gen_2_div_sel: true + gclk_gen_2_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_3_div: 1 + gclk_gen_3_div_sel: false + gclk_gen_3_oscillator: 32kHz External Crystal Oscillator (XOSC32K) + gclk_gen_4_div: 1 + gclk_gen_4_div_sel: false + gclk_gen_4_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_5_div: 1 + gclk_gen_5_div_sel: false + gclk_gen_5_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_6_div: 1 + gclk_gen_6_div_sel: false + gclk_gen_6_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_7_div: 1 + gclk_gen_7_div_sel: false + gclk_gen_7_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_8_div: 1 + gclk_gen_8_div_sel: false + gclk_gen_8_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + gclk_gen_9_div: 1 + gclk_gen_9_div_sel: false + gclk_gen_9_oscillator: External Crystal Oscillator 8-48MHz (XOSC1) + optional_signals: [] + variant: null + clocks: + domain_group: null + MCLK: + user_label: MCLK + definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::MCLK::driver_config_definition::MCLK::HAL:HPL:MCLK + functionality: System + api: HAL:HPL:MCLK + configuration: + $input: 119997440 + $input_id: Generic clock generator 0 + RESERVED_InputFreq: 119997440 + RESERVED_InputFreq_id: Generic clock generator 0 + _$freq_output_CPU: 119997440 + cpu_clock_source: Generic clock generator 0 + cpu_div: '1' + enable_cpu_clock: true + mclk_arch_bupdiv: Divide by 8 + mclk_arch_hsdiv: Divide by 1 + mclk_arch_lpdiv: Divide by 4 + nvm_wait_states: '5' + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: CPU + input: CPU + external: false + external_frequency: 0 + configuration: {} + OSC32KCTRL: + user_label: OSC32KCTRL + definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::OSC32KCTRL::driver_config_definition::OSC32KCTRL::HAL:HPL:OSC32KCTRL + functionality: System + api: HAL:HPL:OSC32KCTRL + configuration: + $input: 32768 + $input_id: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) + RESERVED_InputFreq: 32768 + RESERVED_InputFreq_id: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) + _$freq_output_RTC source: 32768 + enable_osculp32k: true + enable_rtc_source: false + enable_xosc32k: true + osculp32k_calib: 0 + osculp32k_calib_enable: false + rtc_1khz_selection: false + rtc_source_oscillator: 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) + xosc32k_arch_cfden: false + xosc32k_arch_cfdeo: false + xosc32k_arch_cgm: Standard mode + xosc32k_arch_en1k: false + xosc32k_arch_en32k: true + xosc32k_arch_enable: true + xosc32k_arch_ondemand: true + xosc32k_arch_runstdby: false + xosc32k_arch_startup: 1000092us + xosc32k_arch_swben: false + xosc32k_arch_xtalen: true + optional_signals: [] + variant: null + clocks: + domain_group: null + OSCCTRL: + user_label: OSCCTRL + definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::OSCCTRL::driver_config_definition::OSCCTRL::HAL:HPL:OSCCTRL + functionality: System + api: HAL:HPL:OSCCTRL + configuration: + $input: 32768 + $input_id: 32kHz External Crystal Oscillator (XOSC32K) + RESERVED_InputFreq: 32768 + RESERVED_InputFreq_id: 32kHz External Crystal Oscillator (XOSC32K) + _$freq_output_Digital Frequency Locked Loop (DFLL48M): 48000000 + _$freq_output_Digital Phase Locked Loop (DPLL0): 119997440 + _$freq_output_Digital Phase Locked Loop (DPLL1): 47985664 + _$freq_output_External Crystal Oscillator 8-48MHz (XOSC0): 12000000 + _$freq_output_External Crystal Oscillator 8-48MHz (XOSC1): 12000000 + dfll_arch_bplckc: false + dfll_arch_calibration: false + dfll_arch_ccdis: false + dfll_arch_coarse: 31 + dfll_arch_cstep: 1 + dfll_arch_enable: false + dfll_arch_fine: 128 + dfll_arch_fstep: 1 + dfll_arch_llaw: false + dfll_arch_ondemand: false + dfll_arch_qldis: false + dfll_arch_runstdby: false + dfll_arch_stable: false + dfll_arch_usbcrm: false + dfll_arch_waitlock: true + dfll_mode: Open Loop Mode + dfll_mul: 0 + dfll_ref_clock: Generic clock generator 3 + enable_dfll: false + enable_fdpll0: true + enable_fdpll1: false + enable_xosc0: false + enable_xosc1: false + fdpll0_arch_dcoen: false + fdpll0_arch_enable: true + fdpll0_arch_filter: 0 + fdpll0_arch_lbypass: true + fdpll0_arch_ltime: No time-out, automatic lock + fdpll0_arch_ondemand: false + fdpll0_arch_refclk: XOSC32K clock reference + fdpll0_arch_runstdby: false + fdpll0_arch_wuf: false + fdpll0_clock_dcofilter: 0 + fdpll0_clock_div: 0 + fdpll0_ldr: 3661 + fdpll0_ldrfrac: 1 + fdpll0_ref_clock: 32kHz External Crystal Oscillator (XOSC32K) + fdpll1_arch_dcoen: false + fdpll1_arch_enable: false + fdpll1_arch_filter: 0 + fdpll1_arch_lbypass: false + fdpll1_arch_ltime: No time-out, automatic lock + fdpll1_arch_ondemand: false + fdpll1_arch_refclk: XOSC32K clock reference + fdpll1_arch_runstdby: false + fdpll1_arch_wuf: false + fdpll1_clock_dcofilter: 0 + fdpll1_clock_div: 0 + fdpll1_ldr: 1463 + fdpll1_ldrfrac: 13 + fdpll1_ref_clock: 32kHz External Crystal Oscillator (XOSC32K) + xosc0_arch_cfden: false + xosc0_arch_enable: false + xosc0_arch_enalc: false + xosc0_arch_lowbufgain: false + xosc0_arch_ondemand: false + xosc0_arch_runstdby: false + xosc0_arch_startup: 31us + xosc0_arch_swben: false + xosc0_arch_xtalen: false + xosc0_frequency: 12000000 + xosc1_arch_cfden: false + xosc1_arch_enable: false + xosc1_arch_enalc: false + xosc1_arch_lowbufgain: false + xosc1_arch_ondemand: false + xosc1_arch_runstdby: false + xosc1_arch_startup: 31us + xosc1_arch_swben: false + xosc1_arch_xtalen: true + xosc1_frequency: 12000000 + optional_signals: [] + variant: null + clocks: + domain_group: null + PORT: + user_label: PORT + definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::PORT::driver_config_definition::PORT::HAL:HPL:PORT + functionality: System + api: HAL:HPL:PORT + configuration: + enable_port_input_event_0: false + enable_port_input_event_1: false + enable_port_input_event_2: false + enable_port_input_event_3: false + porta_event_action_0: Output register of pin will be set to level of event + porta_event_action_1: Output register of pin will be set to level of event + porta_event_action_2: Output register of pin will be set to level of event + porta_event_action_3: Output register of pin will be set to level of event + porta_event_pin_identifier_0: 0 + porta_event_pin_identifier_1: 0 + porta_event_pin_identifier_2: 0 + porta_event_pin_identifier_3: 0 + porta_input_event_enable_0: false + porta_input_event_enable_1: false + porta_input_event_enable_2: false + porta_input_event_enable_3: false + portb_event_action_0: Output register of pin will be set to level of event + portb_event_action_1: Output register of pin will be set to level of event + portb_event_action_2: Output register of pin will be set to level of event + portb_event_action_3: Output register of pin will be set to level of event + portb_event_pin_identifier_0: 0 + portb_event_pin_identifier_1: 0 + portb_event_pin_identifier_2: 0 + portb_event_pin_identifier_3: 0 + portb_input_event_enable_0: false + portb_input_event_enable_1: false + portb_input_event_enable_2: false + portb_input_event_enable_3: false + portc_event_action_0: Output register of pin will be set to level of event + portc_event_action_1: Output register of pin will be set to level of event + portc_event_action_2: Output register of pin will be set to level of event + portc_event_action_3: Output register of pin will be set to level of event + portc_event_pin_identifier_0: 0 + portc_event_pin_identifier_1: 0 + portc_event_pin_identifier_2: 0 + portc_event_pin_identifier_3: 0 + portc_input_event_enable_0: false + portc_input_event_enable_1: false + portc_input_event_enable_2: false + portc_input_event_enable_3: false + optional_signals: [] + variant: null + clocks: + domain_group: null + RAMECC: + user_label: RAMECC + definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::RAMECC::driver_config_definition::RAMECC::HAL:HPL:RAMECC + functionality: System + api: HAL:HPL:RAMECC + configuration: {} + optional_signals: [] + variant: null + clocks: + domain_group: null + USART_0: + user_label: USART_0 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::SERCOM0::driver_config_definition::UART::HAL:Driver:USART.Async + functionality: USART + api: HAL:Driver:USART_Async + configuration: + usart_advanced: false + usart_arch_clock_mode: USART with internal clock + usart_arch_cloden: false + usart_arch_dbgstop: Keep running + usart_arch_dord: LSB is transmitted first + usart_arch_enc: No encoding + usart_arch_fractional: 0 + usart_arch_ibon: false + usart_arch_lin_slave_enable: Disable + usart_arch_runstdby: false + usart_arch_sampa: 7-8-9 (3-4-5 8-bit over-sampling) + usart_arch_sampr: 16x arithmetic + usart_arch_sfde: false + usart_baud_rate: 115200 + usart_character_size: 8 bits + usart_parity: No parity + usart_rx_enable: true + usart_stop_bit: One stop bit + usart_tx_enable: true + optional_signals: [] + variant: + specification: TXPO=0, RXPO=1, CMODE=0 + required_signals: + - name: SERCOM0/PAD/0 + pad: PA04 + label: TX + - name: SERCOM0/PAD/1 + pad: PA05 + label: RX + clocks: + domain_group: + nodes: + - name: Core + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Slow + input: Generic clock generator 3 + external: false + external_frequency: 0 + configuration: + core_gclk_selection: Generic clock generator 0 + slow_gclk_selection: Generic clock generator 3 + I2C_0: + user_label: I2C_0 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::SERCOM3::driver_config_definition::I2C.Master.Standard~2FFast-mode::HAL:Driver:I2C.Master.Sync + functionality: I2C + api: HAL:Driver:I2C_Master_Sync + configuration: + i2c_master_advanced: false + i2c_master_arch_dbgstop: Keep running + i2c_master_arch_inactout: Disabled + i2c_master_arch_lowtout: false + i2c_master_arch_mexttoen: false + i2c_master_arch_runstdby: false + i2c_master_arch_sdahold: 300-600ns hold time + i2c_master_arch_sexttoen: false + i2c_master_arch_trise: 215 + i2c_master_baud_rate: 100000 + optional_signals: [] + variant: + specification: SDA=0, SCL=1 + required_signals: + - name: SERCOM3/PAD/0 + pad: PA22 + label: SDA + - name: SERCOM3/PAD/1 + pad: PA23 + label: SCL + clocks: + domain_group: + nodes: + - name: Core + input: Generic clock generator 0 + external: false + external_frequency: 0 + - name: Slow + input: Generic clock generator 3 + external: false + external_frequency: 0 + configuration: + core_gclk_selection: Generic clock generator 0 + slow_gclk_selection: Generic clock generator 3 + TIMER_0: + user_label: TIMER_0 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::TC0::driver_config_definition::Timer::HAL:Driver:Timer + functionality: Timer + api: HAL:Driver:Timer + configuration: + tc_arch_dbgrun: false + tc_arch_evact: Event action disabled + tc_arch_mceo0: false + tc_arch_mceo1: false + tc_arch_ondemand: false + tc_arch_ovfeo: false + tc_arch_presync: Reload or reset counter on next GCLK + tc_arch_runstdby: false + tc_arch_tcei: false + tc_arch_tcinv: false + timer_advanced_configuration: false + timer_event_control: false + timer_prescaler: Divide by 8 + timer_tick: 1000 + optional_signals: [] + variant: null + clocks: + domain_group: + nodes: + - name: TC + input: Generic clock generator 0 + external: false + external_frequency: 0 + configuration: + tc_gclk_selection: Generic clock generator 0 +pads: + PA04: + name: PA04 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PA04 + mode: Peripheral IO + user_label: PA04 + configuration: null + PA05: + name: PA05 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PA05 + mode: Peripheral IO + user_label: PA05 + configuration: null + PA22: + name: PA22 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PA22 + mode: I2C + user_label: PA22 + configuration: null + PA23: + name: PA23 + definition: Atmel:SAME54_Drivers:0.0.1::SAME54N19A-AF::pad::PA23 + mode: I2C + user_label: PA23 + configuration: null +toolchain_options: [] +static_files: [] diff --git a/software/firmware/oracle_same54n19a/atmel_start_pins.h b/software/firmware/oracle_same54n19a/atmel_start_pins.h new file mode 100644 index 00000000..468e099a --- /dev/null +++ b/software/firmware/oracle_same54n19a/atmel_start_pins.h @@ -0,0 +1,35 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ +#ifndef ATMEL_START_PINS_H_INCLUDED +#define ATMEL_START_PINS_H_INCLUDED + +#include + +// SAME54 has 14 pin functions + +#define GPIO_PIN_FUNCTION_A 0 +#define GPIO_PIN_FUNCTION_B 1 +#define GPIO_PIN_FUNCTION_C 2 +#define GPIO_PIN_FUNCTION_D 3 +#define GPIO_PIN_FUNCTION_E 4 +#define GPIO_PIN_FUNCTION_F 5 +#define GPIO_PIN_FUNCTION_G 6 +#define GPIO_PIN_FUNCTION_H 7 +#define GPIO_PIN_FUNCTION_I 8 +#define GPIO_PIN_FUNCTION_J 9 +#define GPIO_PIN_FUNCTION_K 10 +#define GPIO_PIN_FUNCTION_L 11 +#define GPIO_PIN_FUNCTION_M 12 +#define GPIO_PIN_FUNCTION_N 13 + +#define PA04 GPIO(GPIO_PORTA, 4) +#define PA05 GPIO(GPIO_PORTA, 5) +#define PA22 GPIO(GPIO_PORTA, 22) +#define PA23 GPIO(GPIO_PORTA, 23) + +#endif // ATMEL_START_PINS_H_INCLUDED diff --git a/software/firmware/oracle_same54n19a/config/hpl_cmcc_config.h b/software/firmware/oracle_same54n19a/config/hpl_cmcc_config.h new file mode 100644 index 00000000..85907361 --- /dev/null +++ b/software/firmware/oracle_same54n19a/config/hpl_cmcc_config.h @@ -0,0 +1,54 @@ +/* Auto-generated config file hpl_cmcc_config.h */ +#ifndef HPL_CMCC_CONFIG_H +#define HPL_CMCC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Basic Configuration + +// Cache enable +// Defines the cache should be enabled or not. +// cmcc_enable +#ifndef CONF_CMCC_ENABLE +#define CONF_CMCC_ENABLE 0x0 +#endif + +// Cache Size +// Defines the cache memory size to be configured. +// <0x0=>1 KB +// <0x1=>2 KB +// <0x2=>4 KB +// cache_size +#ifndef CONF_CMCC_CACHE_SIZE +#define CONF_CMCC_CACHE_SIZE 0x2 +#endif + +// Advanced Configuration +// cmcc_advanced_configuration +// Data cache disable +// Defines the data cache should be disabled or not. +// cmcc_data_cache_disable +#ifndef CONF_CMCC_DATA_CACHE_DISABLE +#define CONF_CMCC_DATA_CACHE_DISABLE 0x0 +#endif + +// Instruction cache disable +// Defines the Instruction cache should be disabled or not. +// cmcc_inst_cache_disable +#ifndef CONF_CMCC_INST_CACHE_DISABLE +#define CONF_CMCC_INST_CACHE_DISABLE 0x0 +#endif + +// Clock Gating disable +// Defines the clock gating should be disabled or not. +// cmcc_clock_gating_disable +#ifndef CONF_CMCC_CLK_GATING_DISABLE +#define CONF_CMCC_CLK_GATING_DISABLE 0x0 +#endif + +// +// + +// <<< end of configuration section >>> + +#endif // HPL_CMCC_CONFIG_H diff --git a/software/firmware/oracle_same54n19a/config/hpl_dmac_config.h b/software/firmware/oracle_same54n19a/config/hpl_dmac_config.h new file mode 100644 index 00000000..90499fc2 --- /dev/null +++ b/software/firmware/oracle_same54n19a/config/hpl_dmac_config.h @@ -0,0 +1,7277 @@ +/* Auto-generated config file hpl_dmac_config.h */ +#ifndef HPL_DMAC_CONFIG_H +#define HPL_DMAC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// DMAC enable +// Indicates whether dmac is enabled or not +// dmac_enable +#ifndef CONF_DMAC_ENABLE +#define CONF_DMAC_ENABLE 0 +#endif + +// Priority Level 0 +// Indicates whether Priority Level 0 is enabled or not +// dmac_lvlen0 +#ifndef CONF_DMAC_LVLEN0 +#define CONF_DMAC_LVLEN0 1 +#endif + +// Level 0 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 0 +// <1=> Round-robin arbitration scheme for channel with priority 0 +// Defines Level 0 Arbitration for DMA channels +// dmac_rrlvlen0 +#ifndef CONF_DMAC_RRLVLEN0 +#define CONF_DMAC_RRLVLEN0 0 +#endif + +// Level 0 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri0 +#ifndef CONF_DMAC_LVLPRI0 +#define CONF_DMAC_LVLPRI0 0 +#endif +// Priority Level 1 +// Indicates whether Priority Level 1 is enabled or not +// dmac_lvlen1 +#ifndef CONF_DMAC_LVLEN1 +#define CONF_DMAC_LVLEN1 1 +#endif + +// Level 1 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 1 +// <1=> Round-robin arbitration scheme for channel with priority 1 +// Defines Level 1 Arbitration for DMA channels +// dmac_rrlvlen1 +#ifndef CONF_DMAC_RRLVLEN1 +#define CONF_DMAC_RRLVLEN1 0 +#endif + +// Level 1 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri1 +#ifndef CONF_DMAC_LVLPRI1 +#define CONF_DMAC_LVLPRI1 0 +#endif +// Priority Level 2 +// Indicates whether Priority Level 2 is enabled or not +// dmac_lvlen2 +#ifndef CONF_DMAC_LVLEN2 +#define CONF_DMAC_LVLEN2 1 +#endif + +// Level 2 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 2 +// <1=> Round-robin arbitration scheme for channel with priority 2 +// Defines Level 2 Arbitration for DMA channels +// dmac_rrlvlen2 +#ifndef CONF_DMAC_RRLVLEN2 +#define CONF_DMAC_RRLVLEN2 0 +#endif + +// Level 2 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri2 +#ifndef CONF_DMAC_LVLPRI2 +#define CONF_DMAC_LVLPRI2 0 +#endif +// Priority Level 3 +// Indicates whether Priority Level 3 is enabled or not +// dmac_lvlen3 +#ifndef CONF_DMAC_LVLEN3 +#define CONF_DMAC_LVLEN3 1 +#endif + +// Level 3 Round-Robin Arbitration +// <0=> Static arbitration scheme for channel with priority 3 +// <1=> Round-robin arbitration scheme for channel with priority 3 +// Defines Level 3 Arbitration for DMA channels +// dmac_rrlvlen3 +#ifndef CONF_DMAC_RRLVLEN3 +#define CONF_DMAC_RRLVLEN3 0 +#endif + +// Level 3 Channel Priority Number <0x00-0xFF> +// dmac_lvlpri3 +#ifndef CONF_DMAC_LVLPRI3 +#define CONF_DMAC_LVLPRI3 0 +#endif +// Debug Run +// Indicates whether Debug Run is enabled or not +// dmac_dbgrun +#ifndef CONF_DMAC_DBGRUN +#define CONF_DMAC_DBGRUN 0 +#endif + +// Channel 0 settings +// dmac_channel_0_settings +#ifndef CONF_DMAC_CHANNEL_0_SETTINGS +#define CONF_DMAC_CHANNEL_0_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 0 is running in standby mode or not +// dmac_runstdby_0 +#ifndef CONF_DMAC_RUNSTDBY_0 +#define CONF_DMAC_RUNSTDBY_0 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_0 +#ifndef CONF_DMAC_TRIGACT_0 +#define CONF_DMAC_TRIGACT_0 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_0 +#ifndef CONF_DMAC_TRIGSRC_0 +#define CONF_DMAC_TRIGSRC_0 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_0 +#ifndef CONF_DMAC_LVL_0 +#define CONF_DMAC_LVL_0 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_0 +#ifndef CONF_DMAC_EVOE_0 +#define CONF_DMAC_EVOE_0 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_0 +#ifndef CONF_DMAC_EVIE_0 +#define CONF_DMAC_EVIE_0 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_0 +#ifndef CONF_DMAC_EVACT_0 +#define CONF_DMAC_EVACT_0 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_0 +#ifndef CONF_DMAC_STEPSIZE_0 +#define CONF_DMAC_STEPSIZE_0 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_0 +#ifndef CONF_DMAC_STEPSEL_0 +#define CONF_DMAC_STEPSEL_0 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_0 +#ifndef CONF_DMAC_SRCINC_0 +#define CONF_DMAC_SRCINC_0 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_0 +#ifndef CONF_DMAC_DSTINC_0 +#define CONF_DMAC_DSTINC_0 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_0 +#ifndef CONF_DMAC_BEATSIZE_0 +#define CONF_DMAC_BEATSIZE_0 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_0 +#ifndef CONF_DMAC_BLOCKACT_0 +#define CONF_DMAC_BLOCKACT_0 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_0 +#ifndef CONF_DMAC_EVOSEL_0 +#define CONF_DMAC_EVOSEL_0 0 +#endif +// + +// Channel 1 settings +// dmac_channel_1_settings +#ifndef CONF_DMAC_CHANNEL_1_SETTINGS +#define CONF_DMAC_CHANNEL_1_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 1 is running in standby mode or not +// dmac_runstdby_1 +#ifndef CONF_DMAC_RUNSTDBY_1 +#define CONF_DMAC_RUNSTDBY_1 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_1 +#ifndef CONF_DMAC_TRIGACT_1 +#define CONF_DMAC_TRIGACT_1 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_1 +#ifndef CONF_DMAC_TRIGSRC_1 +#define CONF_DMAC_TRIGSRC_1 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_1 +#ifndef CONF_DMAC_LVL_1 +#define CONF_DMAC_LVL_1 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_1 +#ifndef CONF_DMAC_EVOE_1 +#define CONF_DMAC_EVOE_1 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_1 +#ifndef CONF_DMAC_EVIE_1 +#define CONF_DMAC_EVIE_1 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_1 +#ifndef CONF_DMAC_EVACT_1 +#define CONF_DMAC_EVACT_1 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_1 +#ifndef CONF_DMAC_STEPSIZE_1 +#define CONF_DMAC_STEPSIZE_1 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_1 +#ifndef CONF_DMAC_STEPSEL_1 +#define CONF_DMAC_STEPSEL_1 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_1 +#ifndef CONF_DMAC_SRCINC_1 +#define CONF_DMAC_SRCINC_1 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_1 +#ifndef CONF_DMAC_DSTINC_1 +#define CONF_DMAC_DSTINC_1 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_1 +#ifndef CONF_DMAC_BEATSIZE_1 +#define CONF_DMAC_BEATSIZE_1 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_1 +#ifndef CONF_DMAC_BLOCKACT_1 +#define CONF_DMAC_BLOCKACT_1 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_1 +#ifndef CONF_DMAC_EVOSEL_1 +#define CONF_DMAC_EVOSEL_1 0 +#endif +// + +// Channel 2 settings +// dmac_channel_2_settings +#ifndef CONF_DMAC_CHANNEL_2_SETTINGS +#define CONF_DMAC_CHANNEL_2_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 2 is running in standby mode or not +// dmac_runstdby_2 +#ifndef CONF_DMAC_RUNSTDBY_2 +#define CONF_DMAC_RUNSTDBY_2 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_2 +#ifndef CONF_DMAC_TRIGACT_2 +#define CONF_DMAC_TRIGACT_2 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_2 +#ifndef CONF_DMAC_TRIGSRC_2 +#define CONF_DMAC_TRIGSRC_2 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_2 +#ifndef CONF_DMAC_LVL_2 +#define CONF_DMAC_LVL_2 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_2 +#ifndef CONF_DMAC_EVOE_2 +#define CONF_DMAC_EVOE_2 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_2 +#ifndef CONF_DMAC_EVIE_2 +#define CONF_DMAC_EVIE_2 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_2 +#ifndef CONF_DMAC_EVACT_2 +#define CONF_DMAC_EVACT_2 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_2 +#ifndef CONF_DMAC_STEPSIZE_2 +#define CONF_DMAC_STEPSIZE_2 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_2 +#ifndef CONF_DMAC_STEPSEL_2 +#define CONF_DMAC_STEPSEL_2 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_2 +#ifndef CONF_DMAC_SRCINC_2 +#define CONF_DMAC_SRCINC_2 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_2 +#ifndef CONF_DMAC_DSTINC_2 +#define CONF_DMAC_DSTINC_2 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_2 +#ifndef CONF_DMAC_BEATSIZE_2 +#define CONF_DMAC_BEATSIZE_2 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_2 +#ifndef CONF_DMAC_BLOCKACT_2 +#define CONF_DMAC_BLOCKACT_2 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_2 +#ifndef CONF_DMAC_EVOSEL_2 +#define CONF_DMAC_EVOSEL_2 0 +#endif +// + +// Channel 3 settings +// dmac_channel_3_settings +#ifndef CONF_DMAC_CHANNEL_3_SETTINGS +#define CONF_DMAC_CHANNEL_3_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 3 is running in standby mode or not +// dmac_runstdby_3 +#ifndef CONF_DMAC_RUNSTDBY_3 +#define CONF_DMAC_RUNSTDBY_3 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_3 +#ifndef CONF_DMAC_TRIGACT_3 +#define CONF_DMAC_TRIGACT_3 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_3 +#ifndef CONF_DMAC_TRIGSRC_3 +#define CONF_DMAC_TRIGSRC_3 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_3 +#ifndef CONF_DMAC_LVL_3 +#define CONF_DMAC_LVL_3 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_3 +#ifndef CONF_DMAC_EVOE_3 +#define CONF_DMAC_EVOE_3 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_3 +#ifndef CONF_DMAC_EVIE_3 +#define CONF_DMAC_EVIE_3 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_3 +#ifndef CONF_DMAC_EVACT_3 +#define CONF_DMAC_EVACT_3 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_3 +#ifndef CONF_DMAC_STEPSIZE_3 +#define CONF_DMAC_STEPSIZE_3 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_3 +#ifndef CONF_DMAC_STEPSEL_3 +#define CONF_DMAC_STEPSEL_3 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_3 +#ifndef CONF_DMAC_SRCINC_3 +#define CONF_DMAC_SRCINC_3 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_3 +#ifndef CONF_DMAC_DSTINC_3 +#define CONF_DMAC_DSTINC_3 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_3 +#ifndef CONF_DMAC_BEATSIZE_3 +#define CONF_DMAC_BEATSIZE_3 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_3 +#ifndef CONF_DMAC_BLOCKACT_3 +#define CONF_DMAC_BLOCKACT_3 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_3 +#ifndef CONF_DMAC_EVOSEL_3 +#define CONF_DMAC_EVOSEL_3 0 +#endif +// + +// Channel 4 settings +// dmac_channel_4_settings +#ifndef CONF_DMAC_CHANNEL_4_SETTINGS +#define CONF_DMAC_CHANNEL_4_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 4 is running in standby mode or not +// dmac_runstdby_4 +#ifndef CONF_DMAC_RUNSTDBY_4 +#define CONF_DMAC_RUNSTDBY_4 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_4 +#ifndef CONF_DMAC_TRIGACT_4 +#define CONF_DMAC_TRIGACT_4 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_4 +#ifndef CONF_DMAC_TRIGSRC_4 +#define CONF_DMAC_TRIGSRC_4 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_4 +#ifndef CONF_DMAC_LVL_4 +#define CONF_DMAC_LVL_4 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_4 +#ifndef CONF_DMAC_EVOE_4 +#define CONF_DMAC_EVOE_4 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_4 +#ifndef CONF_DMAC_EVIE_4 +#define CONF_DMAC_EVIE_4 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_4 +#ifndef CONF_DMAC_EVACT_4 +#define CONF_DMAC_EVACT_4 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_4 +#ifndef CONF_DMAC_STEPSIZE_4 +#define CONF_DMAC_STEPSIZE_4 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_4 +#ifndef CONF_DMAC_STEPSEL_4 +#define CONF_DMAC_STEPSEL_4 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_4 +#ifndef CONF_DMAC_SRCINC_4 +#define CONF_DMAC_SRCINC_4 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_4 +#ifndef CONF_DMAC_DSTINC_4 +#define CONF_DMAC_DSTINC_4 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_4 +#ifndef CONF_DMAC_BEATSIZE_4 +#define CONF_DMAC_BEATSIZE_4 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_4 +#ifndef CONF_DMAC_BLOCKACT_4 +#define CONF_DMAC_BLOCKACT_4 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_4 +#ifndef CONF_DMAC_EVOSEL_4 +#define CONF_DMAC_EVOSEL_4 0 +#endif +// + +// Channel 5 settings +// dmac_channel_5_settings +#ifndef CONF_DMAC_CHANNEL_5_SETTINGS +#define CONF_DMAC_CHANNEL_5_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 5 is running in standby mode or not +// dmac_runstdby_5 +#ifndef CONF_DMAC_RUNSTDBY_5 +#define CONF_DMAC_RUNSTDBY_5 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_5 +#ifndef CONF_DMAC_TRIGACT_5 +#define CONF_DMAC_TRIGACT_5 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_5 +#ifndef CONF_DMAC_TRIGSRC_5 +#define CONF_DMAC_TRIGSRC_5 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_5 +#ifndef CONF_DMAC_LVL_5 +#define CONF_DMAC_LVL_5 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_5 +#ifndef CONF_DMAC_EVOE_5 +#define CONF_DMAC_EVOE_5 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_5 +#ifndef CONF_DMAC_EVIE_5 +#define CONF_DMAC_EVIE_5 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_5 +#ifndef CONF_DMAC_EVACT_5 +#define CONF_DMAC_EVACT_5 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_5 +#ifndef CONF_DMAC_STEPSIZE_5 +#define CONF_DMAC_STEPSIZE_5 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_5 +#ifndef CONF_DMAC_STEPSEL_5 +#define CONF_DMAC_STEPSEL_5 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_5 +#ifndef CONF_DMAC_SRCINC_5 +#define CONF_DMAC_SRCINC_5 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_5 +#ifndef CONF_DMAC_DSTINC_5 +#define CONF_DMAC_DSTINC_5 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_5 +#ifndef CONF_DMAC_BEATSIZE_5 +#define CONF_DMAC_BEATSIZE_5 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_5 +#ifndef CONF_DMAC_BLOCKACT_5 +#define CONF_DMAC_BLOCKACT_5 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_5 +#ifndef CONF_DMAC_EVOSEL_5 +#define CONF_DMAC_EVOSEL_5 0 +#endif +// + +// Channel 6 settings +// dmac_channel_6_settings +#ifndef CONF_DMAC_CHANNEL_6_SETTINGS +#define CONF_DMAC_CHANNEL_6_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 6 is running in standby mode or not +// dmac_runstdby_6 +#ifndef CONF_DMAC_RUNSTDBY_6 +#define CONF_DMAC_RUNSTDBY_6 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_6 +#ifndef CONF_DMAC_TRIGACT_6 +#define CONF_DMAC_TRIGACT_6 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_6 +#ifndef CONF_DMAC_TRIGSRC_6 +#define CONF_DMAC_TRIGSRC_6 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_6 +#ifndef CONF_DMAC_LVL_6 +#define CONF_DMAC_LVL_6 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_6 +#ifndef CONF_DMAC_EVOE_6 +#define CONF_DMAC_EVOE_6 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_6 +#ifndef CONF_DMAC_EVIE_6 +#define CONF_DMAC_EVIE_6 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_6 +#ifndef CONF_DMAC_EVACT_6 +#define CONF_DMAC_EVACT_6 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_6 +#ifndef CONF_DMAC_STEPSIZE_6 +#define CONF_DMAC_STEPSIZE_6 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_6 +#ifndef CONF_DMAC_STEPSEL_6 +#define CONF_DMAC_STEPSEL_6 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_6 +#ifndef CONF_DMAC_SRCINC_6 +#define CONF_DMAC_SRCINC_6 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_6 +#ifndef CONF_DMAC_DSTINC_6 +#define CONF_DMAC_DSTINC_6 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_6 +#ifndef CONF_DMAC_BEATSIZE_6 +#define CONF_DMAC_BEATSIZE_6 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_6 +#ifndef CONF_DMAC_BLOCKACT_6 +#define CONF_DMAC_BLOCKACT_6 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_6 +#ifndef CONF_DMAC_EVOSEL_6 +#define CONF_DMAC_EVOSEL_6 0 +#endif +// + +// Channel 7 settings +// dmac_channel_7_settings +#ifndef CONF_DMAC_CHANNEL_7_SETTINGS +#define CONF_DMAC_CHANNEL_7_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 7 is running in standby mode or not +// dmac_runstdby_7 +#ifndef CONF_DMAC_RUNSTDBY_7 +#define CONF_DMAC_RUNSTDBY_7 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_7 +#ifndef CONF_DMAC_TRIGACT_7 +#define CONF_DMAC_TRIGACT_7 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_7 +#ifndef CONF_DMAC_TRIGSRC_7 +#define CONF_DMAC_TRIGSRC_7 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_7 +#ifndef CONF_DMAC_LVL_7 +#define CONF_DMAC_LVL_7 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_7 +#ifndef CONF_DMAC_EVOE_7 +#define CONF_DMAC_EVOE_7 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_7 +#ifndef CONF_DMAC_EVIE_7 +#define CONF_DMAC_EVIE_7 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_7 +#ifndef CONF_DMAC_EVACT_7 +#define CONF_DMAC_EVACT_7 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_7 +#ifndef CONF_DMAC_STEPSIZE_7 +#define CONF_DMAC_STEPSIZE_7 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_7 +#ifndef CONF_DMAC_STEPSEL_7 +#define CONF_DMAC_STEPSEL_7 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_7 +#ifndef CONF_DMAC_SRCINC_7 +#define CONF_DMAC_SRCINC_7 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_7 +#ifndef CONF_DMAC_DSTINC_7 +#define CONF_DMAC_DSTINC_7 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_7 +#ifndef CONF_DMAC_BEATSIZE_7 +#define CONF_DMAC_BEATSIZE_7 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_7 +#ifndef CONF_DMAC_BLOCKACT_7 +#define CONF_DMAC_BLOCKACT_7 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_7 +#ifndef CONF_DMAC_EVOSEL_7 +#define CONF_DMAC_EVOSEL_7 0 +#endif +// + +// Channel 8 settings +// dmac_channel_8_settings +#ifndef CONF_DMAC_CHANNEL_8_SETTINGS +#define CONF_DMAC_CHANNEL_8_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 8 is running in standby mode or not +// dmac_runstdby_8 +#ifndef CONF_DMAC_RUNSTDBY_8 +#define CONF_DMAC_RUNSTDBY_8 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_8 +#ifndef CONF_DMAC_TRIGACT_8 +#define CONF_DMAC_TRIGACT_8 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_8 +#ifndef CONF_DMAC_TRIGSRC_8 +#define CONF_DMAC_TRIGSRC_8 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_8 +#ifndef CONF_DMAC_LVL_8 +#define CONF_DMAC_LVL_8 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_8 +#ifndef CONF_DMAC_EVOE_8 +#define CONF_DMAC_EVOE_8 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_8 +#ifndef CONF_DMAC_EVIE_8 +#define CONF_DMAC_EVIE_8 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_8 +#ifndef CONF_DMAC_EVACT_8 +#define CONF_DMAC_EVACT_8 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_8 +#ifndef CONF_DMAC_STEPSIZE_8 +#define CONF_DMAC_STEPSIZE_8 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_8 +#ifndef CONF_DMAC_STEPSEL_8 +#define CONF_DMAC_STEPSEL_8 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_8 +#ifndef CONF_DMAC_SRCINC_8 +#define CONF_DMAC_SRCINC_8 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_8 +#ifndef CONF_DMAC_DSTINC_8 +#define CONF_DMAC_DSTINC_8 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_8 +#ifndef CONF_DMAC_BEATSIZE_8 +#define CONF_DMAC_BEATSIZE_8 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_8 +#ifndef CONF_DMAC_BLOCKACT_8 +#define CONF_DMAC_BLOCKACT_8 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_8 +#ifndef CONF_DMAC_EVOSEL_8 +#define CONF_DMAC_EVOSEL_8 0 +#endif +// + +// Channel 9 settings +// dmac_channel_9_settings +#ifndef CONF_DMAC_CHANNEL_9_SETTINGS +#define CONF_DMAC_CHANNEL_9_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 9 is running in standby mode or not +// dmac_runstdby_9 +#ifndef CONF_DMAC_RUNSTDBY_9 +#define CONF_DMAC_RUNSTDBY_9 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_9 +#ifndef CONF_DMAC_TRIGACT_9 +#define CONF_DMAC_TRIGACT_9 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_9 +#ifndef CONF_DMAC_TRIGSRC_9 +#define CONF_DMAC_TRIGSRC_9 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_9 +#ifndef CONF_DMAC_LVL_9 +#define CONF_DMAC_LVL_9 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_9 +#ifndef CONF_DMAC_EVOE_9 +#define CONF_DMAC_EVOE_9 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_9 +#ifndef CONF_DMAC_EVIE_9 +#define CONF_DMAC_EVIE_9 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_9 +#ifndef CONF_DMAC_EVACT_9 +#define CONF_DMAC_EVACT_9 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_9 +#ifndef CONF_DMAC_STEPSIZE_9 +#define CONF_DMAC_STEPSIZE_9 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_9 +#ifndef CONF_DMAC_STEPSEL_9 +#define CONF_DMAC_STEPSEL_9 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_9 +#ifndef CONF_DMAC_SRCINC_9 +#define CONF_DMAC_SRCINC_9 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_9 +#ifndef CONF_DMAC_DSTINC_9 +#define CONF_DMAC_DSTINC_9 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_9 +#ifndef CONF_DMAC_BEATSIZE_9 +#define CONF_DMAC_BEATSIZE_9 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_9 +#ifndef CONF_DMAC_BLOCKACT_9 +#define CONF_DMAC_BLOCKACT_9 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_9 +#ifndef CONF_DMAC_EVOSEL_9 +#define CONF_DMAC_EVOSEL_9 0 +#endif +// + +// Channel 10 settings +// dmac_channel_10_settings +#ifndef CONF_DMAC_CHANNEL_10_SETTINGS +#define CONF_DMAC_CHANNEL_10_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 10 is running in standby mode or not +// dmac_runstdby_10 +#ifndef CONF_DMAC_RUNSTDBY_10 +#define CONF_DMAC_RUNSTDBY_10 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_10 +#ifndef CONF_DMAC_TRIGACT_10 +#define CONF_DMAC_TRIGACT_10 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_10 +#ifndef CONF_DMAC_TRIGSRC_10 +#define CONF_DMAC_TRIGSRC_10 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_10 +#ifndef CONF_DMAC_LVL_10 +#define CONF_DMAC_LVL_10 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_10 +#ifndef CONF_DMAC_EVOE_10 +#define CONF_DMAC_EVOE_10 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_10 +#ifndef CONF_DMAC_EVIE_10 +#define CONF_DMAC_EVIE_10 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_10 +#ifndef CONF_DMAC_EVACT_10 +#define CONF_DMAC_EVACT_10 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_10 +#ifndef CONF_DMAC_STEPSIZE_10 +#define CONF_DMAC_STEPSIZE_10 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_10 +#ifndef CONF_DMAC_STEPSEL_10 +#define CONF_DMAC_STEPSEL_10 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_10 +#ifndef CONF_DMAC_SRCINC_10 +#define CONF_DMAC_SRCINC_10 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_10 +#ifndef CONF_DMAC_DSTINC_10 +#define CONF_DMAC_DSTINC_10 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_10 +#ifndef CONF_DMAC_BEATSIZE_10 +#define CONF_DMAC_BEATSIZE_10 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_10 +#ifndef CONF_DMAC_BLOCKACT_10 +#define CONF_DMAC_BLOCKACT_10 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_10 +#ifndef CONF_DMAC_EVOSEL_10 +#define CONF_DMAC_EVOSEL_10 0 +#endif +// + +// Channel 11 settings +// dmac_channel_11_settings +#ifndef CONF_DMAC_CHANNEL_11_SETTINGS +#define CONF_DMAC_CHANNEL_11_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 11 is running in standby mode or not +// dmac_runstdby_11 +#ifndef CONF_DMAC_RUNSTDBY_11 +#define CONF_DMAC_RUNSTDBY_11 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_11 +#ifndef CONF_DMAC_TRIGACT_11 +#define CONF_DMAC_TRIGACT_11 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_11 +#ifndef CONF_DMAC_TRIGSRC_11 +#define CONF_DMAC_TRIGSRC_11 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_11 +#ifndef CONF_DMAC_LVL_11 +#define CONF_DMAC_LVL_11 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_11 +#ifndef CONF_DMAC_EVOE_11 +#define CONF_DMAC_EVOE_11 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_11 +#ifndef CONF_DMAC_EVIE_11 +#define CONF_DMAC_EVIE_11 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_11 +#ifndef CONF_DMAC_EVACT_11 +#define CONF_DMAC_EVACT_11 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_11 +#ifndef CONF_DMAC_STEPSIZE_11 +#define CONF_DMAC_STEPSIZE_11 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_11 +#ifndef CONF_DMAC_STEPSEL_11 +#define CONF_DMAC_STEPSEL_11 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_11 +#ifndef CONF_DMAC_SRCINC_11 +#define CONF_DMAC_SRCINC_11 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_11 +#ifndef CONF_DMAC_DSTINC_11 +#define CONF_DMAC_DSTINC_11 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_11 +#ifndef CONF_DMAC_BEATSIZE_11 +#define CONF_DMAC_BEATSIZE_11 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_11 +#ifndef CONF_DMAC_BLOCKACT_11 +#define CONF_DMAC_BLOCKACT_11 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_11 +#ifndef CONF_DMAC_EVOSEL_11 +#define CONF_DMAC_EVOSEL_11 0 +#endif +// + +// Channel 12 settings +// dmac_channel_12_settings +#ifndef CONF_DMAC_CHANNEL_12_SETTINGS +#define CONF_DMAC_CHANNEL_12_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 12 is running in standby mode or not +// dmac_runstdby_12 +#ifndef CONF_DMAC_RUNSTDBY_12 +#define CONF_DMAC_RUNSTDBY_12 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_12 +#ifndef CONF_DMAC_TRIGACT_12 +#define CONF_DMAC_TRIGACT_12 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_12 +#ifndef CONF_DMAC_TRIGSRC_12 +#define CONF_DMAC_TRIGSRC_12 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_12 +#ifndef CONF_DMAC_LVL_12 +#define CONF_DMAC_LVL_12 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_12 +#ifndef CONF_DMAC_EVOE_12 +#define CONF_DMAC_EVOE_12 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_12 +#ifndef CONF_DMAC_EVIE_12 +#define CONF_DMAC_EVIE_12 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_12 +#ifndef CONF_DMAC_EVACT_12 +#define CONF_DMAC_EVACT_12 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_12 +#ifndef CONF_DMAC_STEPSIZE_12 +#define CONF_DMAC_STEPSIZE_12 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_12 +#ifndef CONF_DMAC_STEPSEL_12 +#define CONF_DMAC_STEPSEL_12 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_12 +#ifndef CONF_DMAC_SRCINC_12 +#define CONF_DMAC_SRCINC_12 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_12 +#ifndef CONF_DMAC_DSTINC_12 +#define CONF_DMAC_DSTINC_12 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_12 +#ifndef CONF_DMAC_BEATSIZE_12 +#define CONF_DMAC_BEATSIZE_12 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_12 +#ifndef CONF_DMAC_BLOCKACT_12 +#define CONF_DMAC_BLOCKACT_12 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_12 +#ifndef CONF_DMAC_EVOSEL_12 +#define CONF_DMAC_EVOSEL_12 0 +#endif +// + +// Channel 13 settings +// dmac_channel_13_settings +#ifndef CONF_DMAC_CHANNEL_13_SETTINGS +#define CONF_DMAC_CHANNEL_13_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 13 is running in standby mode or not +// dmac_runstdby_13 +#ifndef CONF_DMAC_RUNSTDBY_13 +#define CONF_DMAC_RUNSTDBY_13 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_13 +#ifndef CONF_DMAC_TRIGACT_13 +#define CONF_DMAC_TRIGACT_13 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_13 +#ifndef CONF_DMAC_TRIGSRC_13 +#define CONF_DMAC_TRIGSRC_13 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_13 +#ifndef CONF_DMAC_LVL_13 +#define CONF_DMAC_LVL_13 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_13 +#ifndef CONF_DMAC_EVOE_13 +#define CONF_DMAC_EVOE_13 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_13 +#ifndef CONF_DMAC_EVIE_13 +#define CONF_DMAC_EVIE_13 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_13 +#ifndef CONF_DMAC_EVACT_13 +#define CONF_DMAC_EVACT_13 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_13 +#ifndef CONF_DMAC_STEPSIZE_13 +#define CONF_DMAC_STEPSIZE_13 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_13 +#ifndef CONF_DMAC_STEPSEL_13 +#define CONF_DMAC_STEPSEL_13 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_13 +#ifndef CONF_DMAC_SRCINC_13 +#define CONF_DMAC_SRCINC_13 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_13 +#ifndef CONF_DMAC_DSTINC_13 +#define CONF_DMAC_DSTINC_13 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_13 +#ifndef CONF_DMAC_BEATSIZE_13 +#define CONF_DMAC_BEATSIZE_13 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_13 +#ifndef CONF_DMAC_BLOCKACT_13 +#define CONF_DMAC_BLOCKACT_13 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_13 +#ifndef CONF_DMAC_EVOSEL_13 +#define CONF_DMAC_EVOSEL_13 0 +#endif +// + +// Channel 14 settings +// dmac_channel_14_settings +#ifndef CONF_DMAC_CHANNEL_14_SETTINGS +#define CONF_DMAC_CHANNEL_14_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 14 is running in standby mode or not +// dmac_runstdby_14 +#ifndef CONF_DMAC_RUNSTDBY_14 +#define CONF_DMAC_RUNSTDBY_14 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_14 +#ifndef CONF_DMAC_TRIGACT_14 +#define CONF_DMAC_TRIGACT_14 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_14 +#ifndef CONF_DMAC_TRIGSRC_14 +#define CONF_DMAC_TRIGSRC_14 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_14 +#ifndef CONF_DMAC_LVL_14 +#define CONF_DMAC_LVL_14 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_14 +#ifndef CONF_DMAC_EVOE_14 +#define CONF_DMAC_EVOE_14 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_14 +#ifndef CONF_DMAC_EVIE_14 +#define CONF_DMAC_EVIE_14 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_14 +#ifndef CONF_DMAC_EVACT_14 +#define CONF_DMAC_EVACT_14 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_14 +#ifndef CONF_DMAC_STEPSIZE_14 +#define CONF_DMAC_STEPSIZE_14 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_14 +#ifndef CONF_DMAC_STEPSEL_14 +#define CONF_DMAC_STEPSEL_14 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_14 +#ifndef CONF_DMAC_SRCINC_14 +#define CONF_DMAC_SRCINC_14 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_14 +#ifndef CONF_DMAC_DSTINC_14 +#define CONF_DMAC_DSTINC_14 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_14 +#ifndef CONF_DMAC_BEATSIZE_14 +#define CONF_DMAC_BEATSIZE_14 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_14 +#ifndef CONF_DMAC_BLOCKACT_14 +#define CONF_DMAC_BLOCKACT_14 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_14 +#ifndef CONF_DMAC_EVOSEL_14 +#define CONF_DMAC_EVOSEL_14 0 +#endif +// + +// Channel 15 settings +// dmac_channel_15_settings +#ifndef CONF_DMAC_CHANNEL_15_SETTINGS +#define CONF_DMAC_CHANNEL_15_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 15 is running in standby mode or not +// dmac_runstdby_15 +#ifndef CONF_DMAC_RUNSTDBY_15 +#define CONF_DMAC_RUNSTDBY_15 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_15 +#ifndef CONF_DMAC_TRIGACT_15 +#define CONF_DMAC_TRIGACT_15 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_15 +#ifndef CONF_DMAC_TRIGSRC_15 +#define CONF_DMAC_TRIGSRC_15 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_15 +#ifndef CONF_DMAC_LVL_15 +#define CONF_DMAC_LVL_15 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_15 +#ifndef CONF_DMAC_EVOE_15 +#define CONF_DMAC_EVOE_15 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_15 +#ifndef CONF_DMAC_EVIE_15 +#define CONF_DMAC_EVIE_15 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_15 +#ifndef CONF_DMAC_EVACT_15 +#define CONF_DMAC_EVACT_15 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_15 +#ifndef CONF_DMAC_STEPSIZE_15 +#define CONF_DMAC_STEPSIZE_15 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_15 +#ifndef CONF_DMAC_STEPSEL_15 +#define CONF_DMAC_STEPSEL_15 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_15 +#ifndef CONF_DMAC_SRCINC_15 +#define CONF_DMAC_SRCINC_15 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_15 +#ifndef CONF_DMAC_DSTINC_15 +#define CONF_DMAC_DSTINC_15 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_15 +#ifndef CONF_DMAC_BEATSIZE_15 +#define CONF_DMAC_BEATSIZE_15 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_15 +#ifndef CONF_DMAC_BLOCKACT_15 +#define CONF_DMAC_BLOCKACT_15 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_15 +#ifndef CONF_DMAC_EVOSEL_15 +#define CONF_DMAC_EVOSEL_15 0 +#endif +// + +// Channel 16 settings +// dmac_channel_16_settings +#ifndef CONF_DMAC_CHANNEL_16_SETTINGS +#define CONF_DMAC_CHANNEL_16_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 16 is running in standby mode or not +// dmac_runstdby_16 +#ifndef CONF_DMAC_RUNSTDBY_16 +#define CONF_DMAC_RUNSTDBY_16 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_16 +#ifndef CONF_DMAC_TRIGACT_16 +#define CONF_DMAC_TRIGACT_16 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_16 +#ifndef CONF_DMAC_TRIGSRC_16 +#define CONF_DMAC_TRIGSRC_16 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_16 +#ifndef CONF_DMAC_LVL_16 +#define CONF_DMAC_LVL_16 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_16 +#ifndef CONF_DMAC_EVOE_16 +#define CONF_DMAC_EVOE_16 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_16 +#ifndef CONF_DMAC_EVIE_16 +#define CONF_DMAC_EVIE_16 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_16 +#ifndef CONF_DMAC_EVACT_16 +#define CONF_DMAC_EVACT_16 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_16 +#ifndef CONF_DMAC_STEPSIZE_16 +#define CONF_DMAC_STEPSIZE_16 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_16 +#ifndef CONF_DMAC_STEPSEL_16 +#define CONF_DMAC_STEPSEL_16 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_16 +#ifndef CONF_DMAC_SRCINC_16 +#define CONF_DMAC_SRCINC_16 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_16 +#ifndef CONF_DMAC_DSTINC_16 +#define CONF_DMAC_DSTINC_16 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_16 +#ifndef CONF_DMAC_BEATSIZE_16 +#define CONF_DMAC_BEATSIZE_16 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_16 +#ifndef CONF_DMAC_BLOCKACT_16 +#define CONF_DMAC_BLOCKACT_16 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_16 +#ifndef CONF_DMAC_EVOSEL_16 +#define CONF_DMAC_EVOSEL_16 0 +#endif +// + +// Channel 17 settings +// dmac_channel_17_settings +#ifndef CONF_DMAC_CHANNEL_17_SETTINGS +#define CONF_DMAC_CHANNEL_17_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 17 is running in standby mode or not +// dmac_runstdby_17 +#ifndef CONF_DMAC_RUNSTDBY_17 +#define CONF_DMAC_RUNSTDBY_17 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_17 +#ifndef CONF_DMAC_TRIGACT_17 +#define CONF_DMAC_TRIGACT_17 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_17 +#ifndef CONF_DMAC_TRIGSRC_17 +#define CONF_DMAC_TRIGSRC_17 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_17 +#ifndef CONF_DMAC_LVL_17 +#define CONF_DMAC_LVL_17 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_17 +#ifndef CONF_DMAC_EVOE_17 +#define CONF_DMAC_EVOE_17 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_17 +#ifndef CONF_DMAC_EVIE_17 +#define CONF_DMAC_EVIE_17 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_17 +#ifndef CONF_DMAC_EVACT_17 +#define CONF_DMAC_EVACT_17 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_17 +#ifndef CONF_DMAC_STEPSIZE_17 +#define CONF_DMAC_STEPSIZE_17 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_17 +#ifndef CONF_DMAC_STEPSEL_17 +#define CONF_DMAC_STEPSEL_17 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_17 +#ifndef CONF_DMAC_SRCINC_17 +#define CONF_DMAC_SRCINC_17 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_17 +#ifndef CONF_DMAC_DSTINC_17 +#define CONF_DMAC_DSTINC_17 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_17 +#ifndef CONF_DMAC_BEATSIZE_17 +#define CONF_DMAC_BEATSIZE_17 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_17 +#ifndef CONF_DMAC_BLOCKACT_17 +#define CONF_DMAC_BLOCKACT_17 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_17 +#ifndef CONF_DMAC_EVOSEL_17 +#define CONF_DMAC_EVOSEL_17 0 +#endif +// + +// Channel 18 settings +// dmac_channel_18_settings +#ifndef CONF_DMAC_CHANNEL_18_SETTINGS +#define CONF_DMAC_CHANNEL_18_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 18 is running in standby mode or not +// dmac_runstdby_18 +#ifndef CONF_DMAC_RUNSTDBY_18 +#define CONF_DMAC_RUNSTDBY_18 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_18 +#ifndef CONF_DMAC_TRIGACT_18 +#define CONF_DMAC_TRIGACT_18 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_18 +#ifndef CONF_DMAC_TRIGSRC_18 +#define CONF_DMAC_TRIGSRC_18 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_18 +#ifndef CONF_DMAC_LVL_18 +#define CONF_DMAC_LVL_18 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_18 +#ifndef CONF_DMAC_EVOE_18 +#define CONF_DMAC_EVOE_18 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_18 +#ifndef CONF_DMAC_EVIE_18 +#define CONF_DMAC_EVIE_18 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_18 +#ifndef CONF_DMAC_EVACT_18 +#define CONF_DMAC_EVACT_18 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_18 +#ifndef CONF_DMAC_STEPSIZE_18 +#define CONF_DMAC_STEPSIZE_18 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_18 +#ifndef CONF_DMAC_STEPSEL_18 +#define CONF_DMAC_STEPSEL_18 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_18 +#ifndef CONF_DMAC_SRCINC_18 +#define CONF_DMAC_SRCINC_18 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_18 +#ifndef CONF_DMAC_DSTINC_18 +#define CONF_DMAC_DSTINC_18 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_18 +#ifndef CONF_DMAC_BEATSIZE_18 +#define CONF_DMAC_BEATSIZE_18 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_18 +#ifndef CONF_DMAC_BLOCKACT_18 +#define CONF_DMAC_BLOCKACT_18 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_18 +#ifndef CONF_DMAC_EVOSEL_18 +#define CONF_DMAC_EVOSEL_18 0 +#endif +// + +// Channel 19 settings +// dmac_channel_19_settings +#ifndef CONF_DMAC_CHANNEL_19_SETTINGS +#define CONF_DMAC_CHANNEL_19_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 19 is running in standby mode or not +// dmac_runstdby_19 +#ifndef CONF_DMAC_RUNSTDBY_19 +#define CONF_DMAC_RUNSTDBY_19 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_19 +#ifndef CONF_DMAC_TRIGACT_19 +#define CONF_DMAC_TRIGACT_19 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_19 +#ifndef CONF_DMAC_TRIGSRC_19 +#define CONF_DMAC_TRIGSRC_19 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_19 +#ifndef CONF_DMAC_LVL_19 +#define CONF_DMAC_LVL_19 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_19 +#ifndef CONF_DMAC_EVOE_19 +#define CONF_DMAC_EVOE_19 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_19 +#ifndef CONF_DMAC_EVIE_19 +#define CONF_DMAC_EVIE_19 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_19 +#ifndef CONF_DMAC_EVACT_19 +#define CONF_DMAC_EVACT_19 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_19 +#ifndef CONF_DMAC_STEPSIZE_19 +#define CONF_DMAC_STEPSIZE_19 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_19 +#ifndef CONF_DMAC_STEPSEL_19 +#define CONF_DMAC_STEPSEL_19 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_19 +#ifndef CONF_DMAC_SRCINC_19 +#define CONF_DMAC_SRCINC_19 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_19 +#ifndef CONF_DMAC_DSTINC_19 +#define CONF_DMAC_DSTINC_19 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_19 +#ifndef CONF_DMAC_BEATSIZE_19 +#define CONF_DMAC_BEATSIZE_19 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_19 +#ifndef CONF_DMAC_BLOCKACT_19 +#define CONF_DMAC_BLOCKACT_19 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_19 +#ifndef CONF_DMAC_EVOSEL_19 +#define CONF_DMAC_EVOSEL_19 0 +#endif +// + +// Channel 20 settings +// dmac_channel_20_settings +#ifndef CONF_DMAC_CHANNEL_20_SETTINGS +#define CONF_DMAC_CHANNEL_20_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 20 is running in standby mode or not +// dmac_runstdby_20 +#ifndef CONF_DMAC_RUNSTDBY_20 +#define CONF_DMAC_RUNSTDBY_20 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_20 +#ifndef CONF_DMAC_TRIGACT_20 +#define CONF_DMAC_TRIGACT_20 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_20 +#ifndef CONF_DMAC_TRIGSRC_20 +#define CONF_DMAC_TRIGSRC_20 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_20 +#ifndef CONF_DMAC_LVL_20 +#define CONF_DMAC_LVL_20 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_20 +#ifndef CONF_DMAC_EVOE_20 +#define CONF_DMAC_EVOE_20 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_20 +#ifndef CONF_DMAC_EVIE_20 +#define CONF_DMAC_EVIE_20 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_20 +#ifndef CONF_DMAC_EVACT_20 +#define CONF_DMAC_EVACT_20 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_20 +#ifndef CONF_DMAC_STEPSIZE_20 +#define CONF_DMAC_STEPSIZE_20 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_20 +#ifndef CONF_DMAC_STEPSEL_20 +#define CONF_DMAC_STEPSEL_20 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_20 +#ifndef CONF_DMAC_SRCINC_20 +#define CONF_DMAC_SRCINC_20 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_20 +#ifndef CONF_DMAC_DSTINC_20 +#define CONF_DMAC_DSTINC_20 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_20 +#ifndef CONF_DMAC_BEATSIZE_20 +#define CONF_DMAC_BEATSIZE_20 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_20 +#ifndef CONF_DMAC_BLOCKACT_20 +#define CONF_DMAC_BLOCKACT_20 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_20 +#ifndef CONF_DMAC_EVOSEL_20 +#define CONF_DMAC_EVOSEL_20 0 +#endif +// + +// Channel 21 settings +// dmac_channel_21_settings +#ifndef CONF_DMAC_CHANNEL_21_SETTINGS +#define CONF_DMAC_CHANNEL_21_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 21 is running in standby mode or not +// dmac_runstdby_21 +#ifndef CONF_DMAC_RUNSTDBY_21 +#define CONF_DMAC_RUNSTDBY_21 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_21 +#ifndef CONF_DMAC_TRIGACT_21 +#define CONF_DMAC_TRIGACT_21 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_21 +#ifndef CONF_DMAC_TRIGSRC_21 +#define CONF_DMAC_TRIGSRC_21 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_21 +#ifndef CONF_DMAC_LVL_21 +#define CONF_DMAC_LVL_21 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_21 +#ifndef CONF_DMAC_EVOE_21 +#define CONF_DMAC_EVOE_21 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_21 +#ifndef CONF_DMAC_EVIE_21 +#define CONF_DMAC_EVIE_21 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_21 +#ifndef CONF_DMAC_EVACT_21 +#define CONF_DMAC_EVACT_21 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_21 +#ifndef CONF_DMAC_STEPSIZE_21 +#define CONF_DMAC_STEPSIZE_21 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_21 +#ifndef CONF_DMAC_STEPSEL_21 +#define CONF_DMAC_STEPSEL_21 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_21 +#ifndef CONF_DMAC_SRCINC_21 +#define CONF_DMAC_SRCINC_21 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_21 +#ifndef CONF_DMAC_DSTINC_21 +#define CONF_DMAC_DSTINC_21 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_21 +#ifndef CONF_DMAC_BEATSIZE_21 +#define CONF_DMAC_BEATSIZE_21 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_21 +#ifndef CONF_DMAC_BLOCKACT_21 +#define CONF_DMAC_BLOCKACT_21 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_21 +#ifndef CONF_DMAC_EVOSEL_21 +#define CONF_DMAC_EVOSEL_21 0 +#endif +// + +// Channel 22 settings +// dmac_channel_22_settings +#ifndef CONF_DMAC_CHANNEL_22_SETTINGS +#define CONF_DMAC_CHANNEL_22_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 22 is running in standby mode or not +// dmac_runstdby_22 +#ifndef CONF_DMAC_RUNSTDBY_22 +#define CONF_DMAC_RUNSTDBY_22 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_22 +#ifndef CONF_DMAC_TRIGACT_22 +#define CONF_DMAC_TRIGACT_22 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_22 +#ifndef CONF_DMAC_TRIGSRC_22 +#define CONF_DMAC_TRIGSRC_22 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_22 +#ifndef CONF_DMAC_LVL_22 +#define CONF_DMAC_LVL_22 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_22 +#ifndef CONF_DMAC_EVOE_22 +#define CONF_DMAC_EVOE_22 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_22 +#ifndef CONF_DMAC_EVIE_22 +#define CONF_DMAC_EVIE_22 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_22 +#ifndef CONF_DMAC_EVACT_22 +#define CONF_DMAC_EVACT_22 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_22 +#ifndef CONF_DMAC_STEPSIZE_22 +#define CONF_DMAC_STEPSIZE_22 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_22 +#ifndef CONF_DMAC_STEPSEL_22 +#define CONF_DMAC_STEPSEL_22 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_22 +#ifndef CONF_DMAC_SRCINC_22 +#define CONF_DMAC_SRCINC_22 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_22 +#ifndef CONF_DMAC_DSTINC_22 +#define CONF_DMAC_DSTINC_22 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_22 +#ifndef CONF_DMAC_BEATSIZE_22 +#define CONF_DMAC_BEATSIZE_22 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_22 +#ifndef CONF_DMAC_BLOCKACT_22 +#define CONF_DMAC_BLOCKACT_22 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_22 +#ifndef CONF_DMAC_EVOSEL_22 +#define CONF_DMAC_EVOSEL_22 0 +#endif +// + +// Channel 23 settings +// dmac_channel_23_settings +#ifndef CONF_DMAC_CHANNEL_23_SETTINGS +#define CONF_DMAC_CHANNEL_23_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 23 is running in standby mode or not +// dmac_runstdby_23 +#ifndef CONF_DMAC_RUNSTDBY_23 +#define CONF_DMAC_RUNSTDBY_23 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_23 +#ifndef CONF_DMAC_TRIGACT_23 +#define CONF_DMAC_TRIGACT_23 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_23 +#ifndef CONF_DMAC_TRIGSRC_23 +#define CONF_DMAC_TRIGSRC_23 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_23 +#ifndef CONF_DMAC_LVL_23 +#define CONF_DMAC_LVL_23 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_23 +#ifndef CONF_DMAC_EVOE_23 +#define CONF_DMAC_EVOE_23 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_23 +#ifndef CONF_DMAC_EVIE_23 +#define CONF_DMAC_EVIE_23 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_23 +#ifndef CONF_DMAC_EVACT_23 +#define CONF_DMAC_EVACT_23 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_23 +#ifndef CONF_DMAC_STEPSIZE_23 +#define CONF_DMAC_STEPSIZE_23 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_23 +#ifndef CONF_DMAC_STEPSEL_23 +#define CONF_DMAC_STEPSEL_23 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_23 +#ifndef CONF_DMAC_SRCINC_23 +#define CONF_DMAC_SRCINC_23 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_23 +#ifndef CONF_DMAC_DSTINC_23 +#define CONF_DMAC_DSTINC_23 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_23 +#ifndef CONF_DMAC_BEATSIZE_23 +#define CONF_DMAC_BEATSIZE_23 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_23 +#ifndef CONF_DMAC_BLOCKACT_23 +#define CONF_DMAC_BLOCKACT_23 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_23 +#ifndef CONF_DMAC_EVOSEL_23 +#define CONF_DMAC_EVOSEL_23 0 +#endif +// + +// Channel 24 settings +// dmac_channel_24_settings +#ifndef CONF_DMAC_CHANNEL_24_SETTINGS +#define CONF_DMAC_CHANNEL_24_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 24 is running in standby mode or not +// dmac_runstdby_24 +#ifndef CONF_DMAC_RUNSTDBY_24 +#define CONF_DMAC_RUNSTDBY_24 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_24 +#ifndef CONF_DMAC_TRIGACT_24 +#define CONF_DMAC_TRIGACT_24 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_24 +#ifndef CONF_DMAC_TRIGSRC_24 +#define CONF_DMAC_TRIGSRC_24 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_24 +#ifndef CONF_DMAC_LVL_24 +#define CONF_DMAC_LVL_24 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_24 +#ifndef CONF_DMAC_EVOE_24 +#define CONF_DMAC_EVOE_24 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_24 +#ifndef CONF_DMAC_EVIE_24 +#define CONF_DMAC_EVIE_24 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_24 +#ifndef CONF_DMAC_EVACT_24 +#define CONF_DMAC_EVACT_24 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_24 +#ifndef CONF_DMAC_STEPSIZE_24 +#define CONF_DMAC_STEPSIZE_24 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_24 +#ifndef CONF_DMAC_STEPSEL_24 +#define CONF_DMAC_STEPSEL_24 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_24 +#ifndef CONF_DMAC_SRCINC_24 +#define CONF_DMAC_SRCINC_24 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_24 +#ifndef CONF_DMAC_DSTINC_24 +#define CONF_DMAC_DSTINC_24 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_24 +#ifndef CONF_DMAC_BEATSIZE_24 +#define CONF_DMAC_BEATSIZE_24 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_24 +#ifndef CONF_DMAC_BLOCKACT_24 +#define CONF_DMAC_BLOCKACT_24 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_24 +#ifndef CONF_DMAC_EVOSEL_24 +#define CONF_DMAC_EVOSEL_24 0 +#endif +// + +// Channel 25 settings +// dmac_channel_25_settings +#ifndef CONF_DMAC_CHANNEL_25_SETTINGS +#define CONF_DMAC_CHANNEL_25_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 25 is running in standby mode or not +// dmac_runstdby_25 +#ifndef CONF_DMAC_RUNSTDBY_25 +#define CONF_DMAC_RUNSTDBY_25 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_25 +#ifndef CONF_DMAC_TRIGACT_25 +#define CONF_DMAC_TRIGACT_25 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_25 +#ifndef CONF_DMAC_TRIGSRC_25 +#define CONF_DMAC_TRIGSRC_25 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_25 +#ifndef CONF_DMAC_LVL_25 +#define CONF_DMAC_LVL_25 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_25 +#ifndef CONF_DMAC_EVOE_25 +#define CONF_DMAC_EVOE_25 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_25 +#ifndef CONF_DMAC_EVIE_25 +#define CONF_DMAC_EVIE_25 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_25 +#ifndef CONF_DMAC_EVACT_25 +#define CONF_DMAC_EVACT_25 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_25 +#ifndef CONF_DMAC_STEPSIZE_25 +#define CONF_DMAC_STEPSIZE_25 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_25 +#ifndef CONF_DMAC_STEPSEL_25 +#define CONF_DMAC_STEPSEL_25 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_25 +#ifndef CONF_DMAC_SRCINC_25 +#define CONF_DMAC_SRCINC_25 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_25 +#ifndef CONF_DMAC_DSTINC_25 +#define CONF_DMAC_DSTINC_25 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_25 +#ifndef CONF_DMAC_BEATSIZE_25 +#define CONF_DMAC_BEATSIZE_25 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_25 +#ifndef CONF_DMAC_BLOCKACT_25 +#define CONF_DMAC_BLOCKACT_25 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_25 +#ifndef CONF_DMAC_EVOSEL_25 +#define CONF_DMAC_EVOSEL_25 0 +#endif +// + +// Channel 26 settings +// dmac_channel_26_settings +#ifndef CONF_DMAC_CHANNEL_26_SETTINGS +#define CONF_DMAC_CHANNEL_26_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 26 is running in standby mode or not +// dmac_runstdby_26 +#ifndef CONF_DMAC_RUNSTDBY_26 +#define CONF_DMAC_RUNSTDBY_26 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_26 +#ifndef CONF_DMAC_TRIGACT_26 +#define CONF_DMAC_TRIGACT_26 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_26 +#ifndef CONF_DMAC_TRIGSRC_26 +#define CONF_DMAC_TRIGSRC_26 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_26 +#ifndef CONF_DMAC_LVL_26 +#define CONF_DMAC_LVL_26 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_26 +#ifndef CONF_DMAC_EVOE_26 +#define CONF_DMAC_EVOE_26 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_26 +#ifndef CONF_DMAC_EVIE_26 +#define CONF_DMAC_EVIE_26 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_26 +#ifndef CONF_DMAC_EVACT_26 +#define CONF_DMAC_EVACT_26 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_26 +#ifndef CONF_DMAC_STEPSIZE_26 +#define CONF_DMAC_STEPSIZE_26 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_26 +#ifndef CONF_DMAC_STEPSEL_26 +#define CONF_DMAC_STEPSEL_26 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_26 +#ifndef CONF_DMAC_SRCINC_26 +#define CONF_DMAC_SRCINC_26 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_26 +#ifndef CONF_DMAC_DSTINC_26 +#define CONF_DMAC_DSTINC_26 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_26 +#ifndef CONF_DMAC_BEATSIZE_26 +#define CONF_DMAC_BEATSIZE_26 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_26 +#ifndef CONF_DMAC_BLOCKACT_26 +#define CONF_DMAC_BLOCKACT_26 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_26 +#ifndef CONF_DMAC_EVOSEL_26 +#define CONF_DMAC_EVOSEL_26 0 +#endif +// + +// Channel 27 settings +// dmac_channel_27_settings +#ifndef CONF_DMAC_CHANNEL_27_SETTINGS +#define CONF_DMAC_CHANNEL_27_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 27 is running in standby mode or not +// dmac_runstdby_27 +#ifndef CONF_DMAC_RUNSTDBY_27 +#define CONF_DMAC_RUNSTDBY_27 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_27 +#ifndef CONF_DMAC_TRIGACT_27 +#define CONF_DMAC_TRIGACT_27 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_27 +#ifndef CONF_DMAC_TRIGSRC_27 +#define CONF_DMAC_TRIGSRC_27 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_27 +#ifndef CONF_DMAC_LVL_27 +#define CONF_DMAC_LVL_27 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_27 +#ifndef CONF_DMAC_EVOE_27 +#define CONF_DMAC_EVOE_27 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_27 +#ifndef CONF_DMAC_EVIE_27 +#define CONF_DMAC_EVIE_27 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_27 +#ifndef CONF_DMAC_EVACT_27 +#define CONF_DMAC_EVACT_27 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_27 +#ifndef CONF_DMAC_STEPSIZE_27 +#define CONF_DMAC_STEPSIZE_27 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_27 +#ifndef CONF_DMAC_STEPSEL_27 +#define CONF_DMAC_STEPSEL_27 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_27 +#ifndef CONF_DMAC_SRCINC_27 +#define CONF_DMAC_SRCINC_27 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_27 +#ifndef CONF_DMAC_DSTINC_27 +#define CONF_DMAC_DSTINC_27 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_27 +#ifndef CONF_DMAC_BEATSIZE_27 +#define CONF_DMAC_BEATSIZE_27 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_27 +#ifndef CONF_DMAC_BLOCKACT_27 +#define CONF_DMAC_BLOCKACT_27 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_27 +#ifndef CONF_DMAC_EVOSEL_27 +#define CONF_DMAC_EVOSEL_27 0 +#endif +// + +// Channel 28 settings +// dmac_channel_28_settings +#ifndef CONF_DMAC_CHANNEL_28_SETTINGS +#define CONF_DMAC_CHANNEL_28_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 28 is running in standby mode or not +// dmac_runstdby_28 +#ifndef CONF_DMAC_RUNSTDBY_28 +#define CONF_DMAC_RUNSTDBY_28 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_28 +#ifndef CONF_DMAC_TRIGACT_28 +#define CONF_DMAC_TRIGACT_28 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_28 +#ifndef CONF_DMAC_TRIGSRC_28 +#define CONF_DMAC_TRIGSRC_28 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_28 +#ifndef CONF_DMAC_LVL_28 +#define CONF_DMAC_LVL_28 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_28 +#ifndef CONF_DMAC_EVOE_28 +#define CONF_DMAC_EVOE_28 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_28 +#ifndef CONF_DMAC_EVIE_28 +#define CONF_DMAC_EVIE_28 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_28 +#ifndef CONF_DMAC_EVACT_28 +#define CONF_DMAC_EVACT_28 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_28 +#ifndef CONF_DMAC_STEPSIZE_28 +#define CONF_DMAC_STEPSIZE_28 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_28 +#ifndef CONF_DMAC_STEPSEL_28 +#define CONF_DMAC_STEPSEL_28 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_28 +#ifndef CONF_DMAC_SRCINC_28 +#define CONF_DMAC_SRCINC_28 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_28 +#ifndef CONF_DMAC_DSTINC_28 +#define CONF_DMAC_DSTINC_28 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_28 +#ifndef CONF_DMAC_BEATSIZE_28 +#define CONF_DMAC_BEATSIZE_28 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_28 +#ifndef CONF_DMAC_BLOCKACT_28 +#define CONF_DMAC_BLOCKACT_28 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_28 +#ifndef CONF_DMAC_EVOSEL_28 +#define CONF_DMAC_EVOSEL_28 0 +#endif +// + +// Channel 29 settings +// dmac_channel_29_settings +#ifndef CONF_DMAC_CHANNEL_29_SETTINGS +#define CONF_DMAC_CHANNEL_29_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 29 is running in standby mode or not +// dmac_runstdby_29 +#ifndef CONF_DMAC_RUNSTDBY_29 +#define CONF_DMAC_RUNSTDBY_29 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_29 +#ifndef CONF_DMAC_TRIGACT_29 +#define CONF_DMAC_TRIGACT_29 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_29 +#ifndef CONF_DMAC_TRIGSRC_29 +#define CONF_DMAC_TRIGSRC_29 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_29 +#ifndef CONF_DMAC_LVL_29 +#define CONF_DMAC_LVL_29 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_29 +#ifndef CONF_DMAC_EVOE_29 +#define CONF_DMAC_EVOE_29 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_29 +#ifndef CONF_DMAC_EVIE_29 +#define CONF_DMAC_EVIE_29 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_29 +#ifndef CONF_DMAC_EVACT_29 +#define CONF_DMAC_EVACT_29 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_29 +#ifndef CONF_DMAC_STEPSIZE_29 +#define CONF_DMAC_STEPSIZE_29 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_29 +#ifndef CONF_DMAC_STEPSEL_29 +#define CONF_DMAC_STEPSEL_29 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_29 +#ifndef CONF_DMAC_SRCINC_29 +#define CONF_DMAC_SRCINC_29 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_29 +#ifndef CONF_DMAC_DSTINC_29 +#define CONF_DMAC_DSTINC_29 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_29 +#ifndef CONF_DMAC_BEATSIZE_29 +#define CONF_DMAC_BEATSIZE_29 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_29 +#ifndef CONF_DMAC_BLOCKACT_29 +#define CONF_DMAC_BLOCKACT_29 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_29 +#ifndef CONF_DMAC_EVOSEL_29 +#define CONF_DMAC_EVOSEL_29 0 +#endif +// + +// Channel 30 settings +// dmac_channel_30_settings +#ifndef CONF_DMAC_CHANNEL_30_SETTINGS +#define CONF_DMAC_CHANNEL_30_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 30 is running in standby mode or not +// dmac_runstdby_30 +#ifndef CONF_DMAC_RUNSTDBY_30 +#define CONF_DMAC_RUNSTDBY_30 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_30 +#ifndef CONF_DMAC_TRIGACT_30 +#define CONF_DMAC_TRIGACT_30 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_30 +#ifndef CONF_DMAC_TRIGSRC_30 +#define CONF_DMAC_TRIGSRC_30 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_30 +#ifndef CONF_DMAC_LVL_30 +#define CONF_DMAC_LVL_30 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_30 +#ifndef CONF_DMAC_EVOE_30 +#define CONF_DMAC_EVOE_30 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_30 +#ifndef CONF_DMAC_EVIE_30 +#define CONF_DMAC_EVIE_30 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_30 +#ifndef CONF_DMAC_EVACT_30 +#define CONF_DMAC_EVACT_30 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_30 +#ifndef CONF_DMAC_STEPSIZE_30 +#define CONF_DMAC_STEPSIZE_30 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_30 +#ifndef CONF_DMAC_STEPSEL_30 +#define CONF_DMAC_STEPSEL_30 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_30 +#ifndef CONF_DMAC_SRCINC_30 +#define CONF_DMAC_SRCINC_30 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_30 +#ifndef CONF_DMAC_DSTINC_30 +#define CONF_DMAC_DSTINC_30 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_30 +#ifndef CONF_DMAC_BEATSIZE_30 +#define CONF_DMAC_BEATSIZE_30 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_30 +#ifndef CONF_DMAC_BLOCKACT_30 +#define CONF_DMAC_BLOCKACT_30 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_30 +#ifndef CONF_DMAC_EVOSEL_30 +#define CONF_DMAC_EVOSEL_30 0 +#endif +// + +// Channel 31 settings +// dmac_channel_31_settings +#ifndef CONF_DMAC_CHANNEL_31_SETTINGS +#define CONF_DMAC_CHANNEL_31_SETTINGS 0 +#endif + +// Channel Run in Standby +// Indicates whether channel 31 is running in standby mode or not +// dmac_runstdby_31 +#ifndef CONF_DMAC_RUNSTDBY_31 +#define CONF_DMAC_RUNSTDBY_31 0 +#endif + +// Trigger action +// <0=> One trigger required for each block transfer +// <2=> One trigger required for each beat transfer +// <3=> One trigger required for each transaction +// Defines the trigger action used for a transfer +// dmac_trigact_31 +#ifndef CONF_DMAC_TRIGACT_31 +#define CONF_DMAC_TRIGACT_31 0 +#endif + +// Trigger source +// <0x00=> Only software/event triggers +// <0x01=> RTC Time Stamp Trigger +// <0x02=> DSU Debug Communication Channel 0 Trigger +// <0x03=> DSU Debug Communication Channel 1 Trigger +// <0x04=> SERCOM0 RX Trigger +// <0x05=> SERCOM0 TX Trigger +// <0x06=> SERCOM1 RX Trigger +// <0x07=> SERCOM1 TX Trigger +// <0x08=> SERCOM2 RX Trigger +// <0x09=> SERCOM2 TX Trigger +// <0x0A=> SERCOM3 RX Trigger +// <0x0B=> SERCOM3 TX Trigger +// <0x0C=> SERCOM4 RX Trigger +// <0x0D=> SERCOM4 TX Trigger +// <0x0E=> SERCOM5 RX Trigger +// <0x0F=> SERCOM5 TX Trigger +// <0x10=> SERCOM6 RX Trigger +// <0x11=> SERCOM6 TX Trigger +// <0x12=> SERCOM7 RX Trigger +// <0x13=> SERCOM7 TX Trigger +// <0x14=> CAN0 DEBUG Trigger +// <0x15=> CAN1 DEBUG Trigger +// <0x16=> TCC0 Overflow Trigger Trigger +// <0x17=> TCC0 Match/Compare 0 Trigger Trigger +// <0x18=> TCC0 Match/Compare 1 Trigger Trigger +// <0x19=> TCC0 Match/Compare 2 Trigger Trigger +// <0x1A=> TCC0 Match/Compare 3 Trigger Trigger +// <0x1B=> TCC0 Match/Compare 4 Trigger Trigger +// <0x1C=> TCC0 Match/Compare 5 Trigger Trigger +// <0x1D=> TCC1 Overflow Trigger Trigger +// <0x1E=> TCC1 Match/Compare 0 Trigger Trigger +// <0x1F=> TCC1 Match/Compare 1 Trigger Trigger +// <0x20=> TCC1 Match/Compare 2 Trigger Trigger +// <0x21=> TCC1 Match/Compare 3 Trigger Trigger +// <0x22=> TCC2 Overflow Trigger Trigger +// <0x23=> TCC2 Match/Compare 0 Trigger Trigger +// <0x24=> TCC2 Match/Compare 1 Trigger Trigger +// <0x25=> TCC2 Match/Compare 2 Trigger Trigger +// <0x26=> TCC3 Overflow Trigger Trigger +// <0x27=> TCC3 Match/Compare 0 Trigger Trigger +// <0x28=> TCC3 Match/Compare 1 Trigger Trigger +// <0x29=> TCC4 Overflow Trigger Trigger +// <0x2A=> TCC4 Match/Compare 0 Trigger Trigger +// <0x2B=> TCC4 Match/Compare 1 Trigger Trigger +// <0x2C=> TC0 Overflow Trigger +// <0x2D=> TC0 Match/Compare 0 Trigger +// <0x2E=> TC0 Match/Compare 1 Trigger +// <0x2F=> TC1 Overflow Trigger +// <0x30=> TC1 Match/Compare 0 Trigger +// <0x31=> TC1 Match/Compare 1 Trigger +// <0x32=> TC2 Overflow Trigger +// <0x33=> TC2 Match/Compare 0 Trigger +// <0x34=> TC2 Match/Compare 1 Trigger +// <0x35=> TC3 Overflow Trigger +// <0x36=> TC3 Match/Compare 0 Trigger +// <0x37=> TC3 Match/Compare 1 Trigger +// <0x38=> TC4 Overflow Trigger +// <0x39=> TC4 Match/Compare 0 Trigger +// <0x3A=> TC4 Match/Compare 1 Trigger +// <0x3B=> TC5 Overflow Trigger +// <0x3C=> TC5 Match/Compare 0 Trigger +// <0x3D=> TC5 Match/Compare 1 Trigger +// <0x3E=> TC6 Overflow Trigger +// <0x3F=> TC6 Match/Compare 0 Trigger +// <0x40=> TC6 Match/Compare 1 Trigger +// <0x41=> TC7 Overflow Trigger +// <0x42=> TC7 Match/Compare 0 Trigger +// <0x43=> TC7 Match/Compare 1 Trigger +// <0x44=> ADC0 Result Ready Trigger +// <0x45=> ADC0 Sequencing Trigger +// <0x46=> ADC1 Result Ready Trigger +// <0x47=> ADC1 Sequencing Trigger +// <0x48=> DAC Empty 0 Trigger +// <0x49=> DAC Empty 1 Trigger +// <0x4A=> DAC Result Ready 0 Trigger +// <0x4B=> DAC Result Ready 1 Trigger +// <0x4C=> I2S Rx 0 Trigger +// <0x4D=> I2S Rx 1 Trigger +// <0x4E=> I2S Tx 0 Trigger +// <0x4F=> I2S Tx 1 Trigger +// <0x50=> PCC RX Trigger +// <0x51=> AES Write Trigger +// <0x52=> AES Read Trigger +// <0x53=> QSPI Rx Trigger +// <0x54=> QSPI Tx Trigger +// Defines the peripheral trigger which is source of the transfer +// dmac_trifsrc_31 +#ifndef CONF_DMAC_TRIGSRC_31 +#define CONF_DMAC_TRIGSRC_31 0 +#endif + +// Channel Arbitration Level +// <0=> Channel priority 0 +// <1=> Channel priority 1 +// <2=> Channel priority 2 +// <3=> Channel priority 3 +// Defines the arbitration level for this channel +// dmac_lvl_31 +#ifndef CONF_DMAC_LVL_31 +#define CONF_DMAC_LVL_31 0 +#endif + +// Channel Event Output +// Indicates whether channel event generation is enabled or not +// dmac_evoe_31 +#ifndef CONF_DMAC_EVOE_31 +#define CONF_DMAC_EVOE_31 0 +#endif + +// Channel Event Input +// Indicates whether channel event reception is enabled or not +// dmac_evie_31 +#ifndef CONF_DMAC_EVIE_31 +#define CONF_DMAC_EVIE_31 0 +#endif + +// Event Input Action +// <0=> No action +// <1=> Normal transfer and conditional transfer on strobe trigger +// <2=> Conditional transfer trigger +// <3=> Conditional block transfer +// <4=> Channel suspend operation +// <5=> Channel resume operation +// <6=> Skip next block suspend action +// Defines the event input action +// dmac_evact_31 +#ifndef CONF_DMAC_EVACT_31 +#define CONF_DMAC_EVACT_31 0 +#endif + +// Address Increment Step Size +// <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 +// <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 +// <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 +// <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 +// <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 +// <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 +// <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 +// <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 +// Defines the address increment step size, applies to source or destination address +// dmac_stepsize_31 +#ifndef CONF_DMAC_STEPSIZE_31 +#define CONF_DMAC_STEPSIZE_31 0 +#endif + +// Step Selection +// <0=> Step size settings apply to the destination address +// <1=> Step size settings apply to the source address +// Defines whether source or destination addresses are using the step size settings +// dmac_stepsel_31 +#ifndef CONF_DMAC_STEPSEL_31 +#define CONF_DMAC_STEPSEL_31 0 +#endif + +// Source Address Increment +// Indicates whether the source address incrementation is enabled or not +// dmac_srcinc_31 +#ifndef CONF_DMAC_SRCINC_31 +#define CONF_DMAC_SRCINC_31 0 +#endif + +// Destination Address Increment +// Indicates whether the destination address incrementation is enabled or not +// dmac_dstinc_31 +#ifndef CONF_DMAC_DSTINC_31 +#define CONF_DMAC_DSTINC_31 0 +#endif + +// Beat Size +// <0=> 8-bit bus transfer +// <1=> 16-bit bus transfer +// <2=> 32-bit bus transfer +// Defines the size of one beat +// dmac_beatsize_31 +#ifndef CONF_DMAC_BEATSIZE_31 +#define CONF_DMAC_BEATSIZE_31 0 +#endif + +// Block Action +// <0=> Channel will be disabled if it is the last block transfer in the transaction +// <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt +// <2=> Channel suspend operation is complete +// <3=> Both channel suspend operation and block interrupt +// Defines the the DMAC should take after a block transfer has completed +// dmac_blockact_31 +#ifndef CONF_DMAC_BLOCKACT_31 +#define CONF_DMAC_BLOCKACT_31 0 +#endif + +// Event Output Selection +// <0=> Event generation disabled +// <1=> Event strobe when block transfer complete +// <3=> Event strobe when beat transfer complete +// Defines the event output selection +// dmac_evosel_31 +#ifndef CONF_DMAC_EVOSEL_31 +#define CONF_DMAC_EVOSEL_31 0 +#endif +// + +// + +// <<< end of configuration section >>> + +#endif // HPL_DMAC_CONFIG_H diff --git a/software/firmware/oracle_same54n19a/config/hpl_eic_config.h b/software/firmware/oracle_same54n19a/config/hpl_eic_config.h new file mode 100644 index 00000000..12946dfe --- /dev/null +++ b/software/firmware/oracle_same54n19a/config/hpl_eic_config.h @@ -0,0 +1,911 @@ +/* Auto-generated config file hpl_eic_config.h */ +#ifndef HPL_EIC_CONFIG_H +#define HPL_EIC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Basic Settings +// Clock Selection +// Indicates which clock used, The EIC can be clocked either by GCLK_EIC when higher frequency than 32KHz is required for filtering or +// either by CLK_ULP32K when power consumption is the priority. +// <0x0=> Clocked by GCLK +// <0x1=> Clocked by ULPOSC32K +// eic_arch_cksel +#ifndef CONF_EIC_CKSEL +#define CONF_EIC_CKSEL 0 +#endif + +// Pin Sampler frequency selection +// Indicates the sampling rate of the EXTINT pin. +// <0x0=> The sampling rate is EIC clock +// <0x1=> The sampling rate is the prescaled clock +// eic_arch_tickon +#ifndef CONF_EIC_TICKON +#define CONF_EIC_TICKON 0 +#endif + +// + +// Non-Maskable Interrupt Control +// eic_arch_nmi_ctrl +#ifndef CONF_EIC_ENABLE_NMI_CTRL +#define CONF_EIC_ENABLE_NMI_CTRL 0 +#endif + +// Non-Maskable Interrupt Filter Enable +// Indicates whether the mon-maskable interrupt filter is enabled or not +// eic_arch_nmifilten +#ifndef CONF_EIC_NMIFILTEN +#define CONF_EIC_NMIFILTEN 0 +#endif + +// Non-Maskable Interrupt Sense +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines non-maskable interrupt sense +// eic_arch_nmisense +#ifndef CONF_EIC_NMISENSE +#define CONF_EIC_NMISENSE EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// Asynchronous Edge Detection Mode +// Indicates the interrupt detection mode operated synchronously or asynchronousl +// eic_arch_nmiasynch +#ifndef CONF_EIC_NMIASYNCH +#define CONF_EIC_NMIASYNCH 0 +#endif +// + +// Interrupt 0 Settings +// eic_arch_enable_irq_setting0 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING0 +#define CONF_EIC_ENABLE_IRQ_SETTING0 0 +#endif + +// External Interrupt 0 Filter Enable +// Indicates whether the external interrupt 0 filter is enabled or not +// eic_arch_filten0 +#ifndef CONF_EIC_FILTEN0 +#define CONF_EIC_FILTEN0 0 +#endif + +// External Interrupt 0 Debounce Enable +// Indicates whether the external interrupt 0 debounce is enabled or not +// eic_arch_debounce_enable0 +#ifndef CONF_EIC_DEBOUNCE_ENABLE0 +#define CONF_EIC_DEBOUNCE_ENABLE0 0 +#endif + +// External Interrupt 0 Event Output Enable +// Indicates whether the external interrupt 0 event output is enabled or not +// eic_arch_extinteo0 +#ifndef CONF_EIC_EXTINTEO0 +#define CONF_EIC_EXTINTEO0 0 +#endif + +// Input 0 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense0 +#ifndef CONF_EIC_SENSE0 +#define CONF_EIC_SENSE0 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 0 Asynchronous Edge Detection Mode +// Indicates the external interrupt 0 detection mode operated synchronously or asynchronousl +// eic_arch_asynch0 +#ifndef CONF_EIC_ASYNCH0 +#define CONF_EIC_ASYNCH0 0 +#endif + +// + +// Interrupt 1 Settings +// eic_arch_enable_irq_setting1 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING1 +#define CONF_EIC_ENABLE_IRQ_SETTING1 0 +#endif + +// External Interrupt 1 Filter Enable +// Indicates whether the external interrupt 1 filter is enabled or not +// eic_arch_filten1 +#ifndef CONF_EIC_FILTEN1 +#define CONF_EIC_FILTEN1 0 +#endif + +// External Interrupt 1 Debounce Enable +// Indicates whether the external interrupt 1 debounce is enabled or not +// eic_arch_debounce_enable1 +#ifndef CONF_EIC_DEBOUNCE_ENABLE1 +#define CONF_EIC_DEBOUNCE_ENABLE1 0 +#endif + +// External Interrupt 1 Event Output Enable +// Indicates whether the external interrupt 1 event output is enabled or not +// eic_arch_extinteo1 +#ifndef CONF_EIC_EXTINTEO1 +#define CONF_EIC_EXTINTEO1 0 +#endif + +// Input 1 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense1 +#ifndef CONF_EIC_SENSE1 +#define CONF_EIC_SENSE1 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 1 Asynchronous Edge Detection Mode +// Indicates the external interrupt 1 detection mode operated synchronously or asynchronousl +// eic_arch_asynch1 +#ifndef CONF_EIC_ASYNCH1 +#define CONF_EIC_ASYNCH1 0 +#endif + +// + +// Interrupt 2 Settings +// eic_arch_enable_irq_setting2 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING2 +#define CONF_EIC_ENABLE_IRQ_SETTING2 0 +#endif + +// External Interrupt 2 Filter Enable +// Indicates whether the external interrupt 2 filter is enabled or not +// eic_arch_filten2 +#ifndef CONF_EIC_FILTEN2 +#define CONF_EIC_FILTEN2 0 +#endif + +// External Interrupt 2 Debounce Enable +// Indicates whether the external interrupt 2 debounce is enabled or not +// eic_arch_debounce_enable2 +#ifndef CONF_EIC_DEBOUNCE_ENABLE2 +#define CONF_EIC_DEBOUNCE_ENABLE2 0 +#endif + +// External Interrupt 2 Event Output Enable +// Indicates whether the external interrupt 2 event output is enabled or not +// eic_arch_extinteo2 +#ifndef CONF_EIC_EXTINTEO2 +#define CONF_EIC_EXTINTEO2 0 +#endif + +// Input 2 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense2 +#ifndef CONF_EIC_SENSE2 +#define CONF_EIC_SENSE2 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 2 Asynchronous Edge Detection Mode +// Indicates the external interrupt 2 detection mode operated synchronously or asynchronousl +// eic_arch_asynch2 +#ifndef CONF_EIC_ASYNCH2 +#define CONF_EIC_ASYNCH2 0 +#endif + +// + +// Interrupt 3 Settings +// eic_arch_enable_irq_setting3 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING3 +#define CONF_EIC_ENABLE_IRQ_SETTING3 0 +#endif + +// External Interrupt 3 Filter Enable +// Indicates whether the external interrupt 3 filter is enabled or not +// eic_arch_filten3 +#ifndef CONF_EIC_FILTEN3 +#define CONF_EIC_FILTEN3 0 +#endif + +// External Interrupt 3 Debounce Enable +// Indicates whether the external interrupt 3 debounce is enabled or not +// eic_arch_debounce_enable3 +#ifndef CONF_EIC_DEBOUNCE_ENABLE3 +#define CONF_EIC_DEBOUNCE_ENABLE3 0 +#endif + +// External Interrupt 3 Event Output Enable +// Indicates whether the external interrupt 3 event output is enabled or not +// eic_arch_extinteo3 +#ifndef CONF_EIC_EXTINTEO3 +#define CONF_EIC_EXTINTEO3 0 +#endif + +// Input 3 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense3 +#ifndef CONF_EIC_SENSE3 +#define CONF_EIC_SENSE3 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 3 Asynchronous Edge Detection Mode +// Indicates the external interrupt 3 detection mode operated synchronously or asynchronousl +// eic_arch_asynch3 +#ifndef CONF_EIC_ASYNCH3 +#define CONF_EIC_ASYNCH3 0 +#endif + +// + +// Interrupt 4 Settings +// eic_arch_enable_irq_setting4 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING4 +#define CONF_EIC_ENABLE_IRQ_SETTING4 0 +#endif + +// External Interrupt 4 Filter Enable +// Indicates whether the external interrupt 4 filter is enabled or not +// eic_arch_filten4 +#ifndef CONF_EIC_FILTEN4 +#define CONF_EIC_FILTEN4 0 +#endif + +// External Interrupt 4 Debounce Enable +// Indicates whether the external interrupt 4 debounce is enabled or not +// eic_arch_debounce_enable4 +#ifndef CONF_EIC_DEBOUNCE_ENABLE4 +#define CONF_EIC_DEBOUNCE_ENABLE4 0 +#endif + +// External Interrupt 4 Event Output Enable +// Indicates whether the external interrupt 4 event output is enabled or not +// eic_arch_extinteo4 +#ifndef CONF_EIC_EXTINTEO4 +#define CONF_EIC_EXTINTEO4 0 +#endif + +// Input 4 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense4 +#ifndef CONF_EIC_SENSE4 +#define CONF_EIC_SENSE4 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 4 Asynchronous Edge Detection Mode +// Indicates the external interrupt 4 detection mode operated synchronously or asynchronousl +// eic_arch_asynch4 +#ifndef CONF_EIC_ASYNCH4 +#define CONF_EIC_ASYNCH4 0 +#endif + +// + +// Interrupt 5 Settings +// eic_arch_enable_irq_setting5 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING5 +#define CONF_EIC_ENABLE_IRQ_SETTING5 0 +#endif + +// External Interrupt 5 Filter Enable +// Indicates whether the external interrupt 5 filter is enabled or not +// eic_arch_filten5 +#ifndef CONF_EIC_FILTEN5 +#define CONF_EIC_FILTEN5 0 +#endif + +// External Interrupt 5 Debounce Enable +// Indicates whether the external interrupt 5 debounce is enabled or not +// eic_arch_debounce_enable5 +#ifndef CONF_EIC_DEBOUNCE_ENABLE5 +#define CONF_EIC_DEBOUNCE_ENABLE5 0 +#endif + +// External Interrupt 5 Event Output Enable +// Indicates whether the external interrupt 5 event output is enabled or not +// eic_arch_extinteo5 +#ifndef CONF_EIC_EXTINTEO5 +#define CONF_EIC_EXTINTEO5 0 +#endif + +// Input 5 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense5 +#ifndef CONF_EIC_SENSE5 +#define CONF_EIC_SENSE5 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 5 Asynchronous Edge Detection Mode +// Indicates the external interrupt 5 detection mode operated synchronously or asynchronousl +// eic_arch_asynch5 +#ifndef CONF_EIC_ASYNCH5 +#define CONF_EIC_ASYNCH5 0 +#endif + +// + +// Interrupt 6 Settings +// eic_arch_enable_irq_setting6 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING6 +#define CONF_EIC_ENABLE_IRQ_SETTING6 0 +#endif + +// External Interrupt 6 Filter Enable +// Indicates whether the external interrupt 6 filter is enabled or not +// eic_arch_filten6 +#ifndef CONF_EIC_FILTEN6 +#define CONF_EIC_FILTEN6 0 +#endif + +// External Interrupt 6 Debounce Enable +// Indicates whether the external interrupt 6 debounce is enabled or not +// eic_arch_debounce_enable6 +#ifndef CONF_EIC_DEBOUNCE_ENABLE6 +#define CONF_EIC_DEBOUNCE_ENABLE6 0 +#endif + +// External Interrupt 6 Event Output Enable +// Indicates whether the external interrupt 6 event output is enabled or not +// eic_arch_extinteo6 +#ifndef CONF_EIC_EXTINTEO6 +#define CONF_EIC_EXTINTEO6 0 +#endif + +// Input 6 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense6 +#ifndef CONF_EIC_SENSE6 +#define CONF_EIC_SENSE6 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 6 Asynchronous Edge Detection Mode +// Indicates the external interrupt 6 detection mode operated synchronously or asynchronousl +// eic_arch_asynch6 +#ifndef CONF_EIC_ASYNCH6 +#define CONF_EIC_ASYNCH6 0 +#endif + +// + +// Interrupt 7 Settings +// eic_arch_enable_irq_setting7 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING7 +#define CONF_EIC_ENABLE_IRQ_SETTING7 0 +#endif + +// External Interrupt 7 Filter Enable +// Indicates whether the external interrupt 7 filter is enabled or not +// eic_arch_filten7 +#ifndef CONF_EIC_FILTEN7 +#define CONF_EIC_FILTEN7 0 +#endif + +// External Interrupt 7 Debounce Enable +// Indicates whether the external interrupt 7 debounce is enabled or not +// eic_arch_debounce_enable7 +#ifndef CONF_EIC_DEBOUNCE_ENABLE7 +#define CONF_EIC_DEBOUNCE_ENABLE7 0 +#endif + +// External Interrupt 7 Event Output Enable +// Indicates whether the external interrupt 7 event output is enabled or not +// eic_arch_extinteo7 +#ifndef CONF_EIC_EXTINTEO7 +#define CONF_EIC_EXTINTEO7 0 +#endif + +// Input 7 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense7 +#ifndef CONF_EIC_SENSE7 +#define CONF_EIC_SENSE7 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 7 Asynchronous Edge Detection Mode +// Indicates the external interrupt 7 detection mode operated synchronously or asynchronousl +// eic_arch_asynch7 +#ifndef CONF_EIC_ASYNCH7 +#define CONF_EIC_ASYNCH7 0 +#endif + +// + +// Interrupt 8 Settings +// eic_arch_enable_irq_setting8 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING8 +#define CONF_EIC_ENABLE_IRQ_SETTING8 0 +#endif + +// External Interrupt 8 Filter Enable +// Indicates whether the external interrupt 8 filter is enabled or not +// eic_arch_filten8 +#ifndef CONF_EIC_FILTEN8 +#define CONF_EIC_FILTEN8 0 +#endif + +// External Interrupt 8 Debounce Enable +// Indicates whether the external interrupt 8 debounce is enabled or not +// eic_arch_debounce_enable8 +#ifndef CONF_EIC_DEBOUNCE_ENABLE8 +#define CONF_EIC_DEBOUNCE_ENABLE8 0 +#endif + +// External Interrupt 8 Event Output Enable +// Indicates whether the external interrupt 8 event output is enabled or not +// eic_arch_extinteo8 +#ifndef CONF_EIC_EXTINTEO8 +#define CONF_EIC_EXTINTEO8 0 +#endif + +// Input 8 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense8 +#ifndef CONF_EIC_SENSE8 +#define CONF_EIC_SENSE8 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 8 Asynchronous Edge Detection Mode +// Indicates the external interrupt 8 detection mode operated synchronously or asynchronousl +// eic_arch_asynch8 +#ifndef CONF_EIC_ASYNCH8 +#define CONF_EIC_ASYNCH8 0 +#endif + +// + +// Interrupt 9 Settings +// eic_arch_enable_irq_setting9 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING9 +#define CONF_EIC_ENABLE_IRQ_SETTING9 0 +#endif + +// External Interrupt 9 Filter Enable +// Indicates whether the external interrupt 9 filter is enabled or not +// eic_arch_filten9 +#ifndef CONF_EIC_FILTEN9 +#define CONF_EIC_FILTEN9 0 +#endif + +// External Interrupt 9 Debounce Enable +// Indicates whether the external interrupt 9 debounce is enabled or not +// eic_arch_debounce_enable9 +#ifndef CONF_EIC_DEBOUNCE_ENABLE9 +#define CONF_EIC_DEBOUNCE_ENABLE9 0 +#endif + +// External Interrupt 9 Event Output Enable +// Indicates whether the external interrupt 9 event output is enabled or not +// eic_arch_extinteo9 +#ifndef CONF_EIC_EXTINTEO9 +#define CONF_EIC_EXTINTEO9 0 +#endif + +// Input 9 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense9 +#ifndef CONF_EIC_SENSE9 +#define CONF_EIC_SENSE9 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 9 Asynchronous Edge Detection Mode +// Indicates the external interrupt 9 detection mode operated synchronously or asynchronousl +// eic_arch_asynch9 +#ifndef CONF_EIC_ASYNCH9 +#define CONF_EIC_ASYNCH9 0 +#endif + +// + +// Interrupt 10 Settings +// eic_arch_enable_irq_setting10 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING10 +#define CONF_EIC_ENABLE_IRQ_SETTING10 0 +#endif + +// External Interrupt 10 Filter Enable +// Indicates whether the external interrupt 10 filter is enabled or not +// eic_arch_filten10 +#ifndef CONF_EIC_FILTEN10 +#define CONF_EIC_FILTEN10 0 +#endif + +// External Interrupt 10 Debounce Enable +// Indicates whether the external interrupt 10 debounce is enabled or not +// eic_arch_debounce_enable10 +#ifndef CONF_EIC_DEBOUNCE_ENABLE10 +#define CONF_EIC_DEBOUNCE_ENABLE10 0 +#endif + +// External Interrupt 10 Event Output Enable +// Indicates whether the external interrupt 10 event output is enabled or not +// eic_arch_extinteo10 +#ifndef CONF_EIC_EXTINTEO10 +#define CONF_EIC_EXTINTEO10 0 +#endif + +// Input 10 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense10 +#ifndef CONF_EIC_SENSE10 +#define CONF_EIC_SENSE10 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 10 Asynchronous Edge Detection Mode +// Indicates the external interrupt 10 detection mode operated synchronously or asynchronousl +// eic_arch_asynch10 +#ifndef CONF_EIC_ASYNCH10 +#define CONF_EIC_ASYNCH10 0 +#endif + +// + +// Interrupt 11 Settings +// eic_arch_enable_irq_setting11 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING11 +#define CONF_EIC_ENABLE_IRQ_SETTING11 0 +#endif + +// External Interrupt 11 Filter Enable +// Indicates whether the external interrupt 11 filter is enabled or not +// eic_arch_filten11 +#ifndef CONF_EIC_FILTEN11 +#define CONF_EIC_FILTEN11 0 +#endif + +// External Interrupt 11 Debounce Enable +// Indicates whether the external interrupt 11 debounce is enabled or not +// eic_arch_debounce_enable11 +#ifndef CONF_EIC_DEBOUNCE_ENABLE11 +#define CONF_EIC_DEBOUNCE_ENABLE11 0 +#endif + +// External Interrupt 11 Event Output Enable +// Indicates whether the external interrupt 11 event output is enabled or not +// eic_arch_extinteo11 +#ifndef CONF_EIC_EXTINTEO11 +#define CONF_EIC_EXTINTEO11 0 +#endif + +// Input 11 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense11 +#ifndef CONF_EIC_SENSE11 +#define CONF_EIC_SENSE11 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 11 Asynchronous Edge Detection Mode +// Indicates the external interrupt 11 detection mode operated synchronously or asynchronousl +// eic_arch_asynch11 +#ifndef CONF_EIC_ASYNCH11 +#define CONF_EIC_ASYNCH11 0 +#endif + +// + +// Interrupt 12 Settings +// eic_arch_enable_irq_setting12 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING12 +#define CONF_EIC_ENABLE_IRQ_SETTING12 0 +#endif + +// External Interrupt 12 Filter Enable +// Indicates whether the external interrupt 12 filter is enabled or not +// eic_arch_filten12 +#ifndef CONF_EIC_FILTEN12 +#define CONF_EIC_FILTEN12 0 +#endif + +// External Interrupt 12 Debounce Enable +// Indicates whether the external interrupt 12 debounce is enabled or not +// eic_arch_debounce_enable12 +#ifndef CONF_EIC_DEBOUNCE_ENABLE12 +#define CONF_EIC_DEBOUNCE_ENABLE12 0 +#endif + +// External Interrupt 12 Event Output Enable +// Indicates whether the external interrupt 12 event output is enabled or not +// eic_arch_extinteo12 +#ifndef CONF_EIC_EXTINTEO12 +#define CONF_EIC_EXTINTEO12 0 +#endif + +// Input 12 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense12 +#ifndef CONF_EIC_SENSE12 +#define CONF_EIC_SENSE12 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 12 Asynchronous Edge Detection Mode +// Indicates the external interrupt 12 detection mode operated synchronously or asynchronousl +// eic_arch_asynch12 +#ifndef CONF_EIC_ASYNCH12 +#define CONF_EIC_ASYNCH12 0 +#endif + +// + +// Interrupt 13 Settings +// eic_arch_enable_irq_setting13 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING13 +#define CONF_EIC_ENABLE_IRQ_SETTING13 0 +#endif + +// External Interrupt 13 Filter Enable +// Indicates whether the external interrupt 13 filter is enabled or not +// eic_arch_filten13 +#ifndef CONF_EIC_FILTEN13 +#define CONF_EIC_FILTEN13 0 +#endif + +// External Interrupt 13 Debounce Enable +// Indicates whether the external interrupt 13 debounce is enabled or not +// eic_arch_debounce_enable13 +#ifndef CONF_EIC_DEBOUNCE_ENABLE13 +#define CONF_EIC_DEBOUNCE_ENABLE13 0 +#endif + +// External Interrupt 13 Event Output Enable +// Indicates whether the external interrupt 13 event output is enabled or not +// eic_arch_extinteo13 +#ifndef CONF_EIC_EXTINTEO13 +#define CONF_EIC_EXTINTEO13 0 +#endif + +// Input 13 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense13 +#ifndef CONF_EIC_SENSE13 +#define CONF_EIC_SENSE13 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 13 Asynchronous Edge Detection Mode +// Indicates the external interrupt 13 detection mode operated synchronously or asynchronousl +// eic_arch_asynch13 +#ifndef CONF_EIC_ASYNCH13 +#define CONF_EIC_ASYNCH13 0 +#endif + +// + +// Interrupt 14 Settings +// eic_arch_enable_irq_setting14 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING14 +#define CONF_EIC_ENABLE_IRQ_SETTING14 0 +#endif + +// External Interrupt 14 Filter Enable +// Indicates whether the external interrupt 14 filter is enabled or not +// eic_arch_filten14 +#ifndef CONF_EIC_FILTEN14 +#define CONF_EIC_FILTEN14 0 +#endif + +// External Interrupt 14 Debounce Enable +// Indicates whether the external interrupt 14 debounce is enabled or not +// eic_arch_debounce_enable14 +#ifndef CONF_EIC_DEBOUNCE_ENABLE14 +#define CONF_EIC_DEBOUNCE_ENABLE14 0 +#endif + +// External Interrupt 14 Event Output Enable +// Indicates whether the external interrupt 14 event output is enabled or not +// eic_arch_extinteo14 +#ifndef CONF_EIC_EXTINTEO14 +#define CONF_EIC_EXTINTEO14 0 +#endif + +// Input 14 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense14 +#ifndef CONF_EIC_SENSE14 +#define CONF_EIC_SENSE14 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 14 Asynchronous Edge Detection Mode +// Indicates the external interrupt 14 detection mode operated synchronously or asynchronousl +// eic_arch_asynch14 +#ifndef CONF_EIC_ASYNCH14 +#define CONF_EIC_ASYNCH14 0 +#endif + +// + +// Interrupt 15 Settings +// eic_arch_enable_irq_setting15 +#ifndef CONF_EIC_ENABLE_IRQ_SETTING15 +#define CONF_EIC_ENABLE_IRQ_SETTING15 0 +#endif + +// External Interrupt 15 Filter Enable +// Indicates whether the external interrupt 15 filter is enabled or not +// eic_arch_filten15 +#ifndef CONF_EIC_FILTEN15 +#define CONF_EIC_FILTEN15 0 +#endif + +// External Interrupt 15 Debounce Enable +// Indicates whether the external interrupt 15 debounce is enabled or not +// eic_arch_debounce_enable15 +#ifndef CONF_EIC_DEBOUNCE_ENABLE15 +#define CONF_EIC_DEBOUNCE_ENABLE15 0 +#endif + +// External Interrupt 15 Event Output Enable +// Indicates whether the external interrupt 15 event output is enabled or not +// eic_arch_extinteo15 +#ifndef CONF_EIC_EXTINTEO15 +#define CONF_EIC_EXTINTEO15 0 +#endif + +// Input 15 Sense Configuration +// No detection +// Rising-edge detection +// Falling-edge detection +// Both-edges detection +// High-level detection +// Low-level detection +// This defines input sense trigger +// eic_arch_sense15 +#ifndef CONF_EIC_SENSE15 +#define CONF_EIC_SENSE15 EIC_NMICTRL_NMISENSE_NONE_Val +#endif + +// External Interrupt 15 Asynchronous Edge Detection Mode +// Indicates the external interrupt 15 detection mode operated synchronously or asynchronousl +// eic_arch_asynch15 +#ifndef CONF_EIC_ASYNCH15 +#define CONF_EIC_ASYNCH15 0 +#endif + +// + +// Debouncer 0 Settings +// Debouncer Frequency Selection +// <0x0=>Divided by 2 +// <0x1=>Divided by 4 +// <0x2=>Divided by 8 +// <0x3=>Divided by 16 +// <0x4=>Divided by 32 +// <0x5=>Divided by 64 +// <0x6=>Divided by 128 +// <0x7=>Divided by 256 +// Select the debouncer low frequency clock for pins + +// EXTINT[7:0]. + +// eic_arch_prescaler0 +#ifndef CONF_EIC_DPRESCALER0 +#define CONF_EIC_DPRESCALER0 EIC_DPRESCALER_PRESCALER0(0x0) +#endif + +// Low frequency samples +// <0x0=>3 +// <0x1=>7 +// Indicates the number of samples by the debouncer low frequency clock needed to validate a transition from +// current pin state to next pin state in synchronous debouncing mode. +// eic_arch_states0 +#ifndef CONF_EIC_STATES0 +#define CONF_EIC_STATES0 0x0 +#endif + +// + +// Debouncer 1 Settings +// Debouncer Frequency Selection +// <0x0=>Divided by 2 +// <0x1=>Divided by 4 +// <0x2=>Divided by 8 +// <0x3=>Divided by 16 +// <0x4=>Divided by 32 +// <0x5=>Divided by 64 +// <0x6=>Divided by 128 +// <0x7=>Divided by 256 +// Select the debouncer low frequency clock for pins + +// EXTINT[15:8]. + +// eic_arch_prescaler1 +#ifndef CONF_EIC_DPRESCALER1 +#define CONF_EIC_DPRESCALER1 EIC_DPRESCALER_PRESCALER1(0x0) +#endif + +// Low frequency samples +// <0x0=>3 +// <0x1=>7 +// Indicates the number of samples by the debouncer low frequency clock needed to validate a transition from +// current pin state to next pin state in synchronous debouncing mode. +// eic_arch_states1 +#ifndef CONF_EIC_STATES1 +#define CONF_EIC_STATES1 0x0 +#endif + +// + +// <<< end of configuration section >>> + +#endif // HPL_EIC_CONFIG_H diff --git a/software/firmware/oracle_same54n19a/config/hpl_gclk_config.h b/software/firmware/oracle_same54n19a/config/hpl_gclk_config.h new file mode 100644 index 00000000..fbce1188 --- /dev/null +++ b/software/firmware/oracle_same54n19a/config/hpl_gclk_config.h @@ -0,0 +1,920 @@ +/* Auto-generated config file hpl_gclk_config.h */ +#ifndef HPL_GCLK_CONFIG_H +#define HPL_GCLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// Generic clock generator 0 configuration +// Indicates whether generic clock 0 configuration is enabled or not +// enable_gclk_gen_0 +#ifndef CONF_GCLK_GENERATOR_0_CONFIG +#define CONF_GCLK_GENERATOR_0_CONFIG 1 +#endif + +// Generic Clock Generator Control +// Generic clock generator 0 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 0 +// gclk_gen_0_oscillator +#ifndef CONF_GCLK_GEN_0_SOURCE +#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_DPLL0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_0_runstdby +#ifndef CONF_GCLK_GEN_0_RUNSTDBY +#define CONF_GCLK_GEN_0_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_0_div_sel +#ifndef CONF_GCLK_GEN_0_DIVSEL +#define CONF_GCLK_GEN_0_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_0_oe +#ifndef CONF_GCLK_GEN_0_OE +#define CONF_GCLK_GEN_0_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_0_oov +#ifndef CONF_GCLK_GEN_0_OOV +#define CONF_GCLK_GEN_0_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_0_idc +#ifndef CONF_GCLK_GEN_0_IDC +#define CONF_GCLK_GEN_0_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_0_enable +#ifndef CONF_GCLK_GEN_0_GENEN +#define CONF_GCLK_GEN_0_GENEN 1 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 0 division <0x0000-0xFFFF> +// gclk_gen_0_div +#ifndef CONF_GCLK_GEN_0_DIV +#define CONF_GCLK_GEN_0_DIV 1 +#endif +// +// + +// Generic clock generator 1 configuration +// Indicates whether generic clock 1 configuration is enabled or not +// enable_gclk_gen_1 +#ifndef CONF_GCLK_GENERATOR_1_CONFIG +#define CONF_GCLK_GENERATOR_1_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 1 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 1 +// gclk_gen_1_oscillator +#ifndef CONF_GCLK_GEN_1_SOURCE +#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_DFLL +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_1_runstdby +#ifndef CONF_GCLK_GEN_1_RUNSTDBY +#define CONF_GCLK_GEN_1_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_1_div_sel +#ifndef CONF_GCLK_GEN_1_DIVSEL +#define CONF_GCLK_GEN_1_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_1_oe +#ifndef CONF_GCLK_GEN_1_OE +#define CONF_GCLK_GEN_1_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_1_oov +#ifndef CONF_GCLK_GEN_1_OOV +#define CONF_GCLK_GEN_1_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_1_idc +#ifndef CONF_GCLK_GEN_1_IDC +#define CONF_GCLK_GEN_1_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_1_enable +#ifndef CONF_GCLK_GEN_1_GENEN +#define CONF_GCLK_GEN_1_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 1 division <0x0000-0xFFFF> +// gclk_gen_1_div +#ifndef CONF_GCLK_GEN_1_DIV +#define CONF_GCLK_GEN_1_DIV 1 +#endif +// +// + +// Generic clock generator 2 configuration +// Indicates whether generic clock 2 configuration is enabled or not +// enable_gclk_gen_2 +#ifndef CONF_GCLK_GENERATOR_2_CONFIG +#define CONF_GCLK_GENERATOR_2_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 2 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 2 +// gclk_gen_2_oscillator +#ifndef CONF_GCLK_GEN_2_SOURCE +#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_2_runstdby +#ifndef CONF_GCLK_GEN_2_RUNSTDBY +#define CONF_GCLK_GEN_2_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_2_div_sel +#ifndef CONF_GCLK_GEN_2_DIVSEL +#define CONF_GCLK_GEN_2_DIVSEL 1 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_2_oe +#ifndef CONF_GCLK_GEN_2_OE +#define CONF_GCLK_GEN_2_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_2_oov +#ifndef CONF_GCLK_GEN_2_OOV +#define CONF_GCLK_GEN_2_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_2_idc +#ifndef CONF_GCLK_GEN_2_IDC +#define CONF_GCLK_GEN_2_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_2_enable +#ifndef CONF_GCLK_GEN_2_GENEN +#define CONF_GCLK_GEN_2_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 2 division <0x0000-0xFFFF> +// gclk_gen_2_div +#ifndef CONF_GCLK_GEN_2_DIV +#define CONF_GCLK_GEN_2_DIV 1 +#endif +// +// + +// Generic clock generator 3 configuration +// Indicates whether generic clock 3 configuration is enabled or not +// enable_gclk_gen_3 +#ifndef CONF_GCLK_GENERATOR_3_CONFIG +#define CONF_GCLK_GENERATOR_3_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 3 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 3 +// gclk_gen_3_oscillator +#ifndef CONF_GCLK_GEN_3_SOURCE +#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC32K +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_3_runstdby +#ifndef CONF_GCLK_GEN_3_RUNSTDBY +#define CONF_GCLK_GEN_3_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_3_div_sel +#ifndef CONF_GCLK_GEN_3_DIVSEL +#define CONF_GCLK_GEN_3_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_3_oe +#ifndef CONF_GCLK_GEN_3_OE +#define CONF_GCLK_GEN_3_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_3_oov +#ifndef CONF_GCLK_GEN_3_OOV +#define CONF_GCLK_GEN_3_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_3_idc +#ifndef CONF_GCLK_GEN_3_IDC +#define CONF_GCLK_GEN_3_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_3_enable +#ifndef CONF_GCLK_GEN_3_GENEN +#define CONF_GCLK_GEN_3_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 3 division <0x0000-0xFFFF> +// gclk_gen_3_div +#ifndef CONF_GCLK_GEN_3_DIV +#define CONF_GCLK_GEN_3_DIV 1 +#endif +// +// + +// Generic clock generator 4 configuration +// Indicates whether generic clock 4 configuration is enabled or not +// enable_gclk_gen_4 +#ifndef CONF_GCLK_GENERATOR_4_CONFIG +#define CONF_GCLK_GENERATOR_4_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 4 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 4 +// gclk_gen_4_oscillator +#ifndef CONF_GCLK_GEN_4_SOURCE +#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_4_runstdby +#ifndef CONF_GCLK_GEN_4_RUNSTDBY +#define CONF_GCLK_GEN_4_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_4_div_sel +#ifndef CONF_GCLK_GEN_4_DIVSEL +#define CONF_GCLK_GEN_4_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_4_oe +#ifndef CONF_GCLK_GEN_4_OE +#define CONF_GCLK_GEN_4_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_4_oov +#ifndef CONF_GCLK_GEN_4_OOV +#define CONF_GCLK_GEN_4_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_4_idc +#ifndef CONF_GCLK_GEN_4_IDC +#define CONF_GCLK_GEN_4_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_4_enable +#ifndef CONF_GCLK_GEN_4_GENEN +#define CONF_GCLK_GEN_4_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 4 division <0x0000-0xFFFF> +// gclk_gen_4_div +#ifndef CONF_GCLK_GEN_4_DIV +#define CONF_GCLK_GEN_4_DIV 1 +#endif +// +// + +// Generic clock generator 5 configuration +// Indicates whether generic clock 5 configuration is enabled or not +// enable_gclk_gen_5 +#ifndef CONF_GCLK_GENERATOR_5_CONFIG +#define CONF_GCLK_GENERATOR_5_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 5 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 5 +// gclk_gen_5_oscillator +#ifndef CONF_GCLK_GEN_5_SOURCE +#define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_5_runstdby +#ifndef CONF_GCLK_GEN_5_RUNSTDBY +#define CONF_GCLK_GEN_5_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_5_div_sel +#ifndef CONF_GCLK_GEN_5_DIVSEL +#define CONF_GCLK_GEN_5_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_5_oe +#ifndef CONF_GCLK_GEN_5_OE +#define CONF_GCLK_GEN_5_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_5_oov +#ifndef CONF_GCLK_GEN_5_OOV +#define CONF_GCLK_GEN_5_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_5_idc +#ifndef CONF_GCLK_GEN_5_IDC +#define CONF_GCLK_GEN_5_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_5_enable +#ifndef CONF_GCLK_GEN_5_GENEN +#define CONF_GCLK_GEN_5_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 5 division <0x0000-0xFFFF> +// gclk_gen_5_div +#ifndef CONF_GCLK_GEN_5_DIV +#define CONF_GCLK_GEN_5_DIV 1 +#endif +// +// + +// Generic clock generator 6 configuration +// Indicates whether generic clock 6 configuration is enabled or not +// enable_gclk_gen_6 +#ifndef CONF_GCLK_GENERATOR_6_CONFIG +#define CONF_GCLK_GENERATOR_6_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 6 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 6 +// gclk_gen_6_oscillator +#ifndef CONF_GCLK_GEN_6_SOURCE +#define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_6_runstdby +#ifndef CONF_GCLK_GEN_6_RUNSTDBY +#define CONF_GCLK_GEN_6_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_6_div_sel +#ifndef CONF_GCLK_GEN_6_DIVSEL +#define CONF_GCLK_GEN_6_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_6_oe +#ifndef CONF_GCLK_GEN_6_OE +#define CONF_GCLK_GEN_6_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_6_oov +#ifndef CONF_GCLK_GEN_6_OOV +#define CONF_GCLK_GEN_6_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_6_idc +#ifndef CONF_GCLK_GEN_6_IDC +#define CONF_GCLK_GEN_6_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_6_enable +#ifndef CONF_GCLK_GEN_6_GENEN +#define CONF_GCLK_GEN_6_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 6 division <0x0000-0xFFFF> +// gclk_gen_6_div +#ifndef CONF_GCLK_GEN_6_DIV +#define CONF_GCLK_GEN_6_DIV 1 +#endif +// +// + +// Generic clock generator 7 configuration +// Indicates whether generic clock 7 configuration is enabled or not +// enable_gclk_gen_7 +#ifndef CONF_GCLK_GENERATOR_7_CONFIG +#define CONF_GCLK_GENERATOR_7_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 7 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 7 +// gclk_gen_7_oscillator +#ifndef CONF_GCLK_GEN_7_SOURCE +#define CONF_GCLK_GEN_7_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_7_runstdby +#ifndef CONF_GCLK_GEN_7_RUNSTDBY +#define CONF_GCLK_GEN_7_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_7_div_sel +#ifndef CONF_GCLK_GEN_7_DIVSEL +#define CONF_GCLK_GEN_7_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_7_oe +#ifndef CONF_GCLK_GEN_7_OE +#define CONF_GCLK_GEN_7_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_7_oov +#ifndef CONF_GCLK_GEN_7_OOV +#define CONF_GCLK_GEN_7_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_7_idc +#ifndef CONF_GCLK_GEN_7_IDC +#define CONF_GCLK_GEN_7_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_7_enable +#ifndef CONF_GCLK_GEN_7_GENEN +#define CONF_GCLK_GEN_7_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 7 division <0x0000-0xFFFF> +// gclk_gen_7_div +#ifndef CONF_GCLK_GEN_7_DIV +#define CONF_GCLK_GEN_7_DIV 1 +#endif +// +// + +// Generic clock generator 8 configuration +// Indicates whether generic clock 8 configuration is enabled or not +// enable_gclk_gen_8 +#ifndef CONF_GCLK_GENERATOR_8_CONFIG +#define CONF_GCLK_GENERATOR_8_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 8 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 8 +// gclk_gen_8_oscillator +#ifndef CONF_GCLK_GEN_8_SOURCE +#define CONF_GCLK_GEN_8_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_8_runstdby +#ifndef CONF_GCLK_GEN_8_RUNSTDBY +#define CONF_GCLK_GEN_8_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_8_div_sel +#ifndef CONF_GCLK_GEN_8_DIVSEL +#define CONF_GCLK_GEN_8_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_8_oe +#ifndef CONF_GCLK_GEN_8_OE +#define CONF_GCLK_GEN_8_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_8_oov +#ifndef CONF_GCLK_GEN_8_OOV +#define CONF_GCLK_GEN_8_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_8_idc +#ifndef CONF_GCLK_GEN_8_IDC +#define CONF_GCLK_GEN_8_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_8_enable +#ifndef CONF_GCLK_GEN_8_GENEN +#define CONF_GCLK_GEN_8_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 8 division <0x0000-0xFFFF> +// gclk_gen_8_div +#ifndef CONF_GCLK_GEN_8_DIV +#define CONF_GCLK_GEN_8_DIV 1 +#endif +// +// + +// Generic clock generator 9 configuration +// Indicates whether generic clock 9 configuration is enabled or not +// enable_gclk_gen_9 +#ifndef CONF_GCLK_GENERATOR_9_CONFIG +#define CONF_GCLK_GENERATOR_9_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 9 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 9 +// gclk_gen_9_oscillator +#ifndef CONF_GCLK_GEN_9_SOURCE +#define CONF_GCLK_GEN_9_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_9_runstdby +#ifndef CONF_GCLK_GEN_9_RUNSTDBY +#define CONF_GCLK_GEN_9_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_9_div_sel +#ifndef CONF_GCLK_GEN_9_DIVSEL +#define CONF_GCLK_GEN_9_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_9_oe +#ifndef CONF_GCLK_GEN_9_OE +#define CONF_GCLK_GEN_9_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_9_oov +#ifndef CONF_GCLK_GEN_9_OOV +#define CONF_GCLK_GEN_9_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_9_idc +#ifndef CONF_GCLK_GEN_9_IDC +#define CONF_GCLK_GEN_9_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_9_enable +#ifndef CONF_GCLK_GEN_9_GENEN +#define CONF_GCLK_GEN_9_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 9 division <0x0000-0xFFFF> +// gclk_gen_9_div +#ifndef CONF_GCLK_GEN_9_DIV +#define CONF_GCLK_GEN_9_DIV 1 +#endif +// +// + +// Generic clock generator 10 configuration +// Indicates whether generic clock 10 configuration is enabled or not +// enable_gclk_gen_10 +#ifndef CONF_GCLK_GENERATOR_10_CONFIG +#define CONF_GCLK_GENERATOR_10_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 10 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 10 +// gclk_gen_10_oscillator +#ifndef CONF_GCLK_GEN_10_SOURCE +#define CONF_GCLK_GEN_10_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_10_runstdby +#ifndef CONF_GCLK_GEN_10_RUNSTDBY +#define CONF_GCLK_GEN_10_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_10_div_sel +#ifndef CONF_GCLK_GEN_10_DIVSEL +#define CONF_GCLK_GEN_10_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_10_oe +#ifndef CONF_GCLK_GEN_10_OE +#define CONF_GCLK_GEN_10_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_10_oov +#ifndef CONF_GCLK_GEN_10_OOV +#define CONF_GCLK_GEN_10_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_10_idc +#ifndef CONF_GCLK_GEN_10_IDC +#define CONF_GCLK_GEN_10_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_10_enable +#ifndef CONF_GCLK_GEN_10_GENEN +#define CONF_GCLK_GEN_10_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 10 division <0x0000-0xFFFF> +// gclk_gen_10_div +#ifndef CONF_GCLK_GEN_10_DIV +#define CONF_GCLK_GEN_10_DIV 1 +#endif +// +// + +// Generic clock generator 11 configuration +// Indicates whether generic clock 11 configuration is enabled or not +// enable_gclk_gen_11 +#ifndef CONF_GCLK_GENERATOR_11_CONFIG +#define CONF_GCLK_GENERATOR_11_CONFIG 0 +#endif + +// Generic Clock Generator Control +// Generic clock generator 11 source +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator input pad +// Generic clock generator 1 +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// Digital Frequency Locked Loop (DFLL48M) +// Digital Phase Locked Loop (DPLL0) +// Digital Phase Locked Loop (DPLL1) +// This defines the clock source for generic clock generator 11 +// gclk_gen_11_oscillator +#ifndef CONF_GCLK_GEN_11_SOURCE +#define CONF_GCLK_GEN_11_SOURCE GCLK_GENCTRL_SRC_XOSC1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// gclk_arch_gen_11_runstdby +#ifndef CONF_GCLK_GEN_11_RUNSTDBY +#define CONF_GCLK_GEN_11_RUNSTDBY 0 +#endif + +// Divide Selection +// Indicates whether Divide Selection is enabled or not +// gclk_gen_11_div_sel +#ifndef CONF_GCLK_GEN_11_DIVSEL +#define CONF_GCLK_GEN_11_DIVSEL 0 +#endif + +// Output Enable +// Indicates whether Output Enable is enabled or not +// gclk_arch_gen_11_oe +#ifndef CONF_GCLK_GEN_11_OE +#define CONF_GCLK_GEN_11_OE 0 +#endif + +// Output Off Value +// Indicates whether Output Off Value is enabled or not +// gclk_arch_gen_11_oov +#ifndef CONF_GCLK_GEN_11_OOV +#define CONF_GCLK_GEN_11_OOV 0 +#endif + +// Improve Duty Cycle +// Indicates whether Improve Duty Cycle is enabled or not +// gclk_arch_gen_11_idc +#ifndef CONF_GCLK_GEN_11_IDC +#define CONF_GCLK_GEN_11_IDC 0 +#endif + +// Generic Clock Generator Enable +// Indicates whether Generic Clock Generator Enable is enabled or not +// gclk_arch_gen_11_enable +#ifndef CONF_GCLK_GEN_11_GENEN +#define CONF_GCLK_GEN_11_GENEN 0 +#endif +// + +// Generic Clock Generator Division +// Generic clock generator 11 division <0x0000-0xFFFF> +// gclk_gen_11_div +#ifndef CONF_GCLK_GEN_11_DIV +#define CONF_GCLK_GEN_11_DIV 1 +#endif +// +// + +// <<< end of configuration section >>> + +#endif // HPL_GCLK_CONFIG_H diff --git a/software/firmware/oracle_same54n19a/config/hpl_mclk_config.h b/software/firmware/oracle_same54n19a/config/hpl_mclk_config.h new file mode 100644 index 00000000..4089d836 --- /dev/null +++ b/software/firmware/oracle_same54n19a/config/hpl_mclk_config.h @@ -0,0 +1,104 @@ +/* Auto-generated config file hpl_mclk_config.h */ +#ifndef HPL_MCLK_CONFIG_H +#define HPL_MCLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +// System Configuration +// Indicates whether configuration for system is enabled or not +// enable_cpu_clock +#ifndef CONF_SYSTEM_CONFIG +#define CONF_SYSTEM_CONFIG 1 +#endif + +// Basic settings +// CPU Clock source +// Generic clock generator 0 +// This defines the clock source for the CPU +// cpu_clock_source +#ifndef CONF_CPU_SRC +#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// CPU Clock Division Factor +// 1 +// 2 +// 4 +// 8 +// 16 +// 32 +// 64 +// 128 +// Prescalar for CPU clock +// cpu_div +#ifndef CONF_MCLK_CPUDIV +#define CONF_MCLK_CPUDIV MCLK_CPUDIV_DIV_DIV1_Val +#endif +// Low Power Clock Division +// Divide by 1 +// Divide by 2 +// Divide by 4 +// Divide by 8 +// Divide by 16 +// Divide by 32 +// Divide by 64 +// Divide by 128 +// mclk_arch_lpdiv +#ifndef CONF_MCLK_LPDIV +#define CONF_MCLK_LPDIV MCLK_LPDIV_LPDIV_DIV4_Val +#endif + +// Backup Clock Division +// Divide by 1 +// Divide by 2 +// Divide by 4 +// Divide by 8 +// Divide by 16 +// Divide by 32 +// Divide by 64 +// Divide by 128 +// mclk_arch_bupdiv +#ifndef CONF_MCLK_BUPDIV +#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV8_Val +#endif +// High-Speed Clock Division +// Divide by 1 +// mclk_arch_hsdiv +#ifndef CONF_MCLK_HSDIV +#define CONF_MCLK_HSDIV MCLK_HSDIV_DIV_DIV1_Val +#endif +// + +// NVM Settings +// NVM Wait States +// These bits select the number of wait states for a read operation. +// <0=> 0 +// <1=> 1 +// <2=> 2 +// <3=> 3 +// <4=> 4 +// <5=> 5 +// <6=> 6 +// <7=> 7 +// <8=> 8 +// <9=> 9 +// <10=> 10 +// <11=> 11 +// <12=> 12 +// <13=> 13 +// <14=> 14 +// <15=> 15 +// nvm_wait_states +#ifndef CONF_NVM_WAIT_STATE +#define CONF_NVM_WAIT_STATE 5 +#endif + +// + +// + +// <<< end of configuration section >>> + +#endif // HPL_MCLK_CONFIG_H diff --git a/software/firmware/oracle_same54n19a/config/hpl_osc32kctrl_config.h b/software/firmware/oracle_same54n19a/config/hpl_osc32kctrl_config.h new file mode 100644 index 00000000..1126a131 --- /dev/null +++ b/software/firmware/oracle_same54n19a/config/hpl_osc32kctrl_config.h @@ -0,0 +1,165 @@ +/* Auto-generated config file hpl_osc32kctrl_config.h */ +#ifndef HPL_OSC32KCTRL_CONFIG_H +#define HPL_OSC32KCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// RTC Source configuration +// enable_rtc_source +#ifndef CONF_RTCCTRL_CONFIG +#define CONF_RTCCTRL_CONFIG 0 +#endif + +// RTC source control +// RTC Clock Source Selection +// 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) +// 32kHz External Crystal Oscillator (XOSC32K) +// This defines the clock source for RTC +// rtc_source_oscillator +#ifndef CONF_RTCCTRL_SRC +#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K +#endif + +// Use 1 kHz output +// rtc_1khz_selection +#ifndef CONF_RTCCTRL_1KHZ + +#define CONF_RTCCTRL_1KHZ 0 + +#endif + +#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K +#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val) +#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K +#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val) +#else +#error unexpected CONF_RTCCTRL_SRC +#endif + +// +// + +// 32kHz External Crystal Oscillator Configuration +// Indicates whether configuration for External 32K Osc is enabled or not +// enable_xosc32k +#ifndef CONF_XOSC32K_CONFIG +#define CONF_XOSC32K_CONFIG 1 +#endif + +// 32kHz External Crystal Oscillator Control +// Oscillator enable +// Indicates whether 32kHz External Crystal Oscillator is enabled or not +// xosc32k_arch_enable +#ifndef CONF_XOSC32K_ENABLE +#define CONF_XOSC32K_ENABLE 1 +#endif + +// Start-Up Time +// <0x0=>62592us +// <0x1=>125092us +// <0x2=>500092us +// <0x3=>1000092us +// <0x4=>2000092us +// <0x5=>4000092us +// <0x6=>8000092us +// xosc32k_arch_startup +#ifndef CONF_XOSC32K_STARTUP +#define CONF_XOSC32K_STARTUP 0x3 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// xosc32k_arch_ondemand +#ifndef CONF_XOSC32K_ONDEMAND +#define CONF_XOSC32K_ONDEMAND 1 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// xosc32k_arch_runstdby +#ifndef CONF_XOSC32K_RUNSTDBY +#define CONF_XOSC32K_RUNSTDBY 0 +#endif + +// 1kHz Output Enable +// Indicates whether 1kHz Output is enabled or not +// xosc32k_arch_en1k +#ifndef CONF_XOSC32K_EN1K +#define CONF_XOSC32K_EN1K 0 +#endif + +// 32kHz Output Enable +// Indicates whether 32kHz Output is enabled or not +// xosc32k_arch_en32k +#ifndef CONF_XOSC32K_EN32K +#define CONF_XOSC32K_EN32K 1 +#endif + +// Clock Switch Back +// Indicates whether Clock Switch Back is enabled or not +// xosc32k_arch_swben +#ifndef CONF_XOSC32K_SWBEN +#define CONF_XOSC32K_SWBEN 0 +#endif + +// Clock Failure Detector +// Indicates whether Clock Failure Detector is enabled or not +// xosc32k_arch_cfden +#ifndef CONF_XOSC32K_CFDEN +#define CONF_XOSC32K_CFDEN 0 +#endif + +// Clock Failure Detector Event Out +// Indicates whether Clock Failure Detector Event Out is enabled or not +// xosc32k_arch_cfdeo +#ifndef CONF_XOSC32K_CFDEO +#define CONF_XOSC32K_CFDEO 0 +#endif + +// Crystal connected to XIN32/XOUT32 Enable +// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not +// xosc32k_arch_xtalen +#ifndef CONF_XOSC32K_XTALEN +#define CONF_XOSC32K_XTALEN 1 +#endif + +// Control Gain Mode +// <0x0=>Low Power mode +// <0x1=>Standard mode +// <0x2=>High Speed mode +// xosc32k_arch_cgm +#ifndef CONF_XOSC32K_CGM +#define CONF_XOSC32K_CGM 0x1 +#endif + +// +// + +// 32kHz Ultra Low Power Internal Oscillator Configuration +// Indicates whether configuration for OSCULP32K is enabled or not +// enable_osculp32k +#ifndef CONF_OSCULP32K_CONFIG +#define CONF_OSCULP32K_CONFIG 1 +#endif + +// 32kHz Ultra Low Power Internal Oscillator Control + +// Oscillator Calibration Control +// Indicates whether Oscillator Calibration is enabled or not +// osculp32k_calib_enable +#ifndef CONF_OSCULP32K_CALIB_ENABLE +#define CONF_OSCULP32K_CALIB_ENABLE 0 +#endif + +// Oscillator Calibration <0x0-0x3F> +// osculp32k_calib +#ifndef CONF_OSCULP32K_CALIB +#define CONF_OSCULP32K_CALIB 0x0 +#endif + +// +// + +// <<< end of configuration section >>> + +#endif // HPL_OSC32KCTRL_CONFIG_H diff --git a/software/firmware/oracle_same54n19a/config/hpl_oscctrl_config.h b/software/firmware/oracle_same54n19a/config/hpl_oscctrl_config.h new file mode 100644 index 00000000..2404d960 --- /dev/null +++ b/software/firmware/oracle_same54n19a/config/hpl_oscctrl_config.h @@ -0,0 +1,640 @@ +/* Auto-generated config file hpl_oscctrl_config.h */ +#ifndef HPL_OSCCTRL_CONFIG_H +#define HPL_OSCCTRL_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// External Multipurpose Crystal Oscillator Configuration +// Indicates whether configuration for XOSC0 is enabled or not +// enable_xosc0 +#ifndef CONF_XOSC0_CONFIG +#define CONF_XOSC0_CONFIG 0 +#endif + +// Frequency <8000000-48000000> +// Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. +// xosc0_frequency +#ifndef CONF_XOSC_FREQUENCY +#define CONF_XOSC0_FREQUENCY 12000000 +#endif + +// External Multipurpose Crystal Oscillator Control +// Oscillator enable +// Indicates whether External Multipurpose Crystal Oscillator is enabled or not +// xosc0_arch_enable +#ifndef CONF_XOSC0_ENABLE +#define CONF_XOSC0_ENABLE 0 +#endif + +// Start-Up Time +// <0x0=>31us +// <0x1=>61us +// <0x2=>122us +// <0x3=>244us +// <0x4=>488us +// <0x5=>977us +// <0x6=>1953us +// <0x7=>3906us +// <0x8=>7813us +// <0x9=>15625us +// <0xA=>31250us +// <0xB=>62500us +// <0xC=>125000us +// <0xD=>250000us +// <0xE=>500000us +// <0xF=>1000000us +// xosc0_arch_startup +#ifndef CONF_XOSC0_STARTUP +#define CONF_XOSC0_STARTUP 0 +#endif + +// Clock Switch Back +// Indicates whether Clock Switch Back is enabled or not +// xosc0_arch_swben +#ifndef CONF_XOSC0_SWBEN +#define CONF_XOSC0_SWBEN 0 +#endif + +// Clock Failure Detector +// Indicates whether Clock Failure Detector is enabled or not +// xosc0_arch_cfden +#ifndef CONF_XOSC0_CFDEN +#define CONF_XOSC0_CFDEN 0 +#endif + +// Automatic Loop Control Enable +// Indicates whether Automatic Loop Control is enabled or not +// xosc0_arch_enalc +#ifndef CONF_XOSC0_ENALC +#define CONF_XOSC0_ENALC 0 +#endif + +// Low Buffer Gain Enable +// Indicates whether Low Buffer Gain is enabled or not +// xosc0_arch_lowbufgain +#ifndef CONF_XOSC0_LOWBUFGAIN +#define CONF_XOSC0_LOWBUFGAIN 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// xosc0_arch_ondemand +#ifndef CONF_XOSC0_ONDEMAND +#define CONF_XOSC0_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// xosc0_arch_runstdby +#ifndef CONF_XOSC0_RUNSTDBY +#define CONF_XOSC0_RUNSTDBY 0 +#endif + +// Crystal connected to XIN/XOUT Enable +// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not +// xosc0_arch_xtalen +#ifndef CONF_XOSC0_XTALEN +#define CONF_XOSC0_XTALEN 0 +#endif +// +// + +#if CONF_XOSC0_FREQUENCY >= 32000000 +#define CONF_XOSC0_CFDPRESC 0x0 +#define CONF_XOSC0_IMULT 0x7 +#define CONF_XOSC0_IPTAT 0x3 +#elif CONF_XOSC0_FREQUENCY >= 24000000 +#define CONF_XOSC0_CFDPRESC 0x1 +#define CONF_XOSC0_IMULT 0x6 +#define CONF_XOSC0_IPTAT 0x3 +#elif CONF_XOSC0_FREQUENCY >= 16000000 +#define CONF_XOSC0_CFDPRESC 0x2 +#define CONF_XOSC0_IMULT 0x5 +#define CONF_XOSC0_IPTAT 0x3 +#elif CONF_XOSC0_FREQUENCY >= 8000000 +#define CONF_XOSC0_CFDPRESC 0x3 +#define CONF_XOSC0_IMULT 0x4 +#define CONF_XOSC0_IPTAT 0x3 +#endif + +// External Multipurpose Crystal Oscillator Configuration +// Indicates whether configuration for XOSC1 is enabled or not +// enable_xosc1 +#ifndef CONF_XOSC1_CONFIG +#define CONF_XOSC1_CONFIG 0 +#endif + +// Frequency <8000000-48000000> +// Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. +// xosc1_frequency +#ifndef CONF_XOSC_FREQUENCY +#define CONF_XOSC1_FREQUENCY 12000000 +#endif + +// External Multipurpose Crystal Oscillator Control +// Oscillator enable +// Indicates whether External Multipurpose Crystal Oscillator is enabled or not +// xosc1_arch_enable +#ifndef CONF_XOSC1_ENABLE +#define CONF_XOSC1_ENABLE 0 +#endif + +// Start-Up Time +// <0x0=>31us +// <0x1=>61us +// <0x2=>122us +// <0x3=>244us +// <0x4=>488us +// <0x5=>977us +// <0x6=>1953us +// <0x7=>3906us +// <0x8=>7813us +// <0x9=>15625us +// <0xA=>31250us +// <0xB=>62500us +// <0xC=>125000us +// <0xD=>250000us +// <0xE=>500000us +// <0xF=>1000000us +// xosc1_arch_startup +#ifndef CONF_XOSC1_STARTUP +#define CONF_XOSC1_STARTUP 0 +#endif + +// Clock Switch Back +// Indicates whether Clock Switch Back is enabled or not +// xosc1_arch_swben +#ifndef CONF_XOSC1_SWBEN +#define CONF_XOSC1_SWBEN 0 +#endif + +// Clock Failure Detector +// Indicates whether Clock Failure Detector is enabled or not +// xosc1_arch_cfden +#ifndef CONF_XOSC1_CFDEN +#define CONF_XOSC1_CFDEN 0 +#endif + +// Automatic Loop Control Enable +// Indicates whether Automatic Loop Control is enabled or not +// xosc1_arch_enalc +#ifndef CONF_XOSC1_ENALC +#define CONF_XOSC1_ENALC 0 +#endif + +// Low Buffer Gain Enable +// Indicates whether Low Buffer Gain is enabled or not +// xosc1_arch_lowbufgain +#ifndef CONF_XOSC1_LOWBUFGAIN +#define CONF_XOSC1_LOWBUFGAIN 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// xosc1_arch_ondemand +#ifndef CONF_XOSC1_ONDEMAND +#define CONF_XOSC1_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// xosc1_arch_runstdby +#ifndef CONF_XOSC1_RUNSTDBY +#define CONF_XOSC1_RUNSTDBY 0 +#endif + +// Crystal connected to XIN/XOUT Enable +// Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not +// xosc1_arch_xtalen +#ifndef CONF_XOSC1_XTALEN +#define CONF_XOSC1_XTALEN 1 +#endif +// +// + +#if CONF_XOSC1_FREQUENCY >= 32000000 +#define CONF_XOSC1_CFDPRESC 0x0 +#define CONF_XOSC1_IMULT 0x7 +#define CONF_XOSC1_IPTAT 0x3 +#elif CONF_XOSC1_FREQUENCY >= 24000000 +#define CONF_XOSC1_CFDPRESC 0x1 +#define CONF_XOSC1_IMULT 0x6 +#define CONF_XOSC1_IPTAT 0x3 +#elif CONF_XOSC1_FREQUENCY >= 16000000 +#define CONF_XOSC1_CFDPRESC 0x2 +#define CONF_XOSC1_IMULT 0x5 +#define CONF_XOSC1_IPTAT 0x3 +#elif CONF_XOSC1_FREQUENCY >= 8000000 +#define CONF_XOSC1_CFDPRESC 0x3 +#define CONF_XOSC1_IMULT 0x4 +#define CONF_XOSC1_IPTAT 0x3 +#endif + +// DFLL Configuration +// Indicates whether configuration for DFLL is enabled or not +// enable_dfll +#ifndef CONF_DFLL_CONFIG +#define CONF_DFLL_CONFIG 0 +#endif + +// Reference Clock Source +// Generic clock generator 0 +// Generic clock generator 1 +// Generic clock generator 2 +// Generic clock generator 3 +// Generic clock generator 4 +// Generic clock generator 5 +// Generic clock generator 6 +// Generic clock generator 7 +// Generic clock generator 8 +// Generic clock generator 9 +// Generic clock generator 10 +// Generic clock generator 11 +// Select the clock source +// dfll_ref_clock +#ifndef CONF_DFLL_GCLK +#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +// Digital Frequency Locked Loop Control +// DFLL Enable +// Indicates whether DFLL is enabled or not +// dfll_arch_enable +#ifndef CONF_DFLL_ENABLE +#define CONF_DFLL_ENABLE 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// dfll_arch_ondemand +#ifndef CONF_DFLL_ONDEMAND +#define CONF_DFLL_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// dfll_arch_runstdby +#ifndef CONF_DFLL_RUNSTDBY +#define CONF_DFLL_RUNSTDBY 0 +#endif + +// USB Clock Recovery Mode +// Indicates whether USB Clock Recovery Mode is enabled or not +// dfll_arch_usbcrm +#ifndef CONF_DFLL_USBCRM +#define CONF_DFLL_USBCRM 0 +#endif + +// Wait Lock +// Indicates whether Wait Lock is enabled or not +// dfll_arch_waitlock +#ifndef CONF_DFLL_WAITLOCK +#define CONF_DFLL_WAITLOCK 1 +#endif + +// Bypass Coarse Lock +// Indicates whether Bypass Coarse Lock is enabled or not +// dfll_arch_bplckc +#ifndef CONF_DFLL_BPLCKC +#define CONF_DFLL_BPLCKC 0 +#endif + +// Quick Lock Disable +// Indicates whether Quick Lock Disable is enabled or not +// dfll_arch_qldis +#ifndef CONF_DFLL_QLDIS +#define CONF_DFLL_QLDIS 0 +#endif + +// Chill Cycle Disable +// Indicates whether Chill Cycle Disable is enabled or not +// dfll_arch_ccdis +#ifndef CONF_DFLL_CCDIS +#define CONF_DFLL_CCDIS 0 +#endif + +// Lose Lock After Wake +// Indicates whether Lose Lock After Wake is enabled or not +// dfll_arch_llaw +#ifndef CONF_DFLL_LLAW +#define CONF_DFLL_LLAW 0 +#endif + +// Stable DFLL Frequency +// Indicates whether Stable DFLL Frequency is enabled or not +// dfll_arch_stable +#ifndef CONF_DFLL_STABLE +#define CONF_DFLL_STABLE 0 +#endif + +// Operating Mode Selection +// <0=>Open Loop Mode +// <1=>Closed Loop Mode +// dfll_mode +#ifndef CONF_DFLL_MODE +#define CONF_DFLL_MODE 0x0 +#endif + +// Coarse Maximum Step <0x0-0x1F> +// dfll_arch_cstep +#ifndef CONF_DFLL_CSTEP +#define CONF_DFLL_CSTEP 0x1 +#endif + +// Fine Maximum Step <0x0-0xFF> +// dfll_arch_fstep +#ifndef CONF_DFLL_FSTEP +#define CONF_DFLL_FSTEP 0x1 +#endif + +// DFLL Multiply Factor <0x0-0xFFFF> +// dfll_mul +#ifndef CONF_DFLL_MUL +#define CONF_DFLL_MUL 0x0 +#endif + +// DFLL Calibration Overwrite +// Indicates whether Overwrite Calibration value of DFLL +// dfll_arch_calibration +#ifndef CONF_DFLL_OVERWRITE_CALIBRATION +#define CONF_DFLL_OVERWRITE_CALIBRATION 0 +#endif + +// Coarse Value <0x0-0x3F> +// dfll_arch_coarse +#ifndef CONF_DFLL_COARSE +#define CONF_DFLL_COARSE (0x1f / 4) +#endif + +// Fine Value <0x0-0xFF> +// dfll_arch_fine +#ifndef CONF_DFLL_FINE +#define CONF_DFLL_FINE (0x80) +#endif + +// + +// + +// + +// FDPLL0 Configuration +// Indicates whether configuration for FDPLL0 is enabled or not +// enable_fdpll0 +#ifndef CONF_FDPLL0_CONFIG +#define CONF_FDPLL0_CONFIG 1 +#endif + +// Reference Clock Source +// 32kHz External Crystal Oscillator (XOSC32K) +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator 0 +// Generic clock generator 1 +// Generic clock generator 2 +// Generic clock generator 3 +// Generic clock generator 4 +// Generic clock generator 5 +// Generic clock generator 6 +// Generic clock generator 7 +// Generic clock generator 8 +// Generic clock generator 9 +// Generic clock generator 10 +// Generic clock generator 11 +// Select the clock source. +// fdpll0_ref_clock +#ifndef CONF_FDPLL0_GCLK +#define CONF_FDPLL0_GCLK GCLK_GENCTRL_SRC_XOSC32K +#endif + +// Digital Phase Locked Loop Control +// Enable +// Indicates whether Digital Phase Locked Loop is enabled or not +// fdpll0_arch_enable +#ifndef CONF_FDPLL0_ENABLE +#define CONF_FDPLL0_ENABLE 1 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// fdpll0_arch_ondemand +#ifndef CONF_FDPLL0_ONDEMAND +#define CONF_FDPLL0_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// fdpll0_arch_runstdby +#ifndef CONF_FDPLL0_RUNSTDBY +#define CONF_FDPLL0_RUNSTDBY 0 +#endif + +// Loop Divider Ratio Fractional Part <0x0-0x1F> +// Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register +// fdpll0_ldrfrac +#ifndef CONF_FDPLL0_LDRFRAC +#define CONF_FDPLL0_LDRFRAC 0x1 +#endif + +// Loop Divider Ratio Integer Part <0x0-0x1FFF> +// Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register +// fdpll0_ldr +#ifndef CONF_FDPLL0_LDR +#define CONF_FDPLL0_LDR 0xe4d +#endif + +// Clock Divider <0x0-0x7FF> +// This Clock divider is only for XOSC clock input to DPLL +// fdpll0_clock_div +#ifndef CONF_FDPLL0_DIV +#define CONF_FDPLL0_DIV 0x0 +#endif + +// DCO Filter Enable +// Indicates whether DCO Filter Enable is enabled or not +// fdpll0_arch_dcoen +#ifndef CONF_FDPLL0_DCOEN +#define CONF_FDPLL0_DCOEN 0 +#endif + +// Sigma-Delta DCO Filter Selection <0x0-0x7> +// fdpll0_clock_dcofilter +#ifndef CONF_FDPLL0_DCOFILTER +#define CONF_FDPLL0_DCOFILTER 0x0 +#endif + +// Lock Bypass +// Indicates whether Lock Bypass is enabled or not +// fdpll0_arch_lbypass +#ifndef CONF_FDPLL0_LBYPASS +#define CONF_FDPLL0_LBYPASS 1 +#endif + +// Lock Time +// <0x0=>No time-out, automatic lock +// <0x4=>The Time-out if no lock within 800 us +// <0x5=>The Time-out if no lock within 900 us +// <0x6=>The Time-out if no lock within 1 ms +// <0x7=>The Time-out if no lock within 11 ms +// fdpll0_arch_ltime +#ifndef CONF_FDPLL0_LTIME +#define CONF_FDPLL0_LTIME 0x0 +#endif + +// Reference Clock Selection +// <0x0=>GCLK clock reference +// <0x1=>XOSC32K clock reference +// <0x2=>XOSC0 clock reference +// <0x3=>XOSC1 clock reference +// fdpll0_arch_refclk +#ifndef CONF_FDPLL0_REFCLK +#define CONF_FDPLL0_REFCLK 0x1 +#endif + +// Wake Up Fast +// Indicates whether Wake Up Fast is enabled or not +// fdpll0_arch_wuf +#ifndef CONF_FDPLL0_WUF +#define CONF_FDPLL0_WUF 0 +#endif + +// Proportional Integral Filter Selection <0x0-0xF> +// fdpll0_arch_filter +#ifndef CONF_FDPLL0_FILTER +#define CONF_FDPLL0_FILTER 0x0 +#endif + +// +// +// FDPLL1 Configuration +// Indicates whether configuration for FDPLL1 is enabled or not +// enable_fdpll1 +#ifndef CONF_FDPLL1_CONFIG +#define CONF_FDPLL1_CONFIG 0 +#endif + +// Reference Clock Source +// 32kHz External Crystal Oscillator (XOSC32K) +// External Crystal Oscillator 8-48MHz (XOSC0) +// External Crystal Oscillator 8-48MHz (XOSC1) +// Generic clock generator 0 +// Generic clock generator 1 +// Generic clock generator 2 +// Generic clock generator 3 +// Generic clock generator 4 +// Generic clock generator 5 +// Generic clock generator 6 +// Generic clock generator 7 +// Generic clock generator 8 +// Generic clock generator 9 +// Generic clock generator 10 +// Generic clock generator 11 +// Select the clock source. +// fdpll1_ref_clock +#ifndef CONF_FDPLL1_GCLK +#define CONF_FDPLL1_GCLK GCLK_GENCTRL_SRC_XOSC32K +#endif + +// Digital Phase Locked Loop Control +// Enable +// Indicates whether Digital Phase Locked Loop is enabled or not +// fdpll1_arch_enable +#ifndef CONF_FDPLL1_ENABLE +#define CONF_FDPLL1_ENABLE 0 +#endif + +// On Demand Control +// Indicates whether On Demand Control is enabled or not +// fdpll1_arch_ondemand +#ifndef CONF_FDPLL1_ONDEMAND +#define CONF_FDPLL1_ONDEMAND 0 +#endif + +// Run in Standby +// Indicates whether Run in Standby is enabled or not +// fdpll1_arch_runstdby +#ifndef CONF_FDPLL1_RUNSTDBY +#define CONF_FDPLL1_RUNSTDBY 0 +#endif + +// Loop Divider Ratio Fractional Part <0x0-0x1F> +// Value of LDRFRAC is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register +// fdpll1_ldrfrac +#ifndef CONF_FDPLL1_LDRFRAC +#define CONF_FDPLL1_LDRFRAC 0xd +#endif + +// Loop Divider Ratio Integer Part <0x0-0x1FFF> +// Value of LDR is calculated using Fclk_dpll=Fckr*(LDR+1+LDRFRAC/32) formula as given in datasheet. This value is directly written in to DPLLRATIO register +// fdpll1_ldr +#ifndef CONF_FDPLL1_LDR +#define CONF_FDPLL1_LDR 0x5b7 +#endif + +// Clock Divider <0x0-0x7FF> +// This Clock divider is only for XOSC clock input to DPLL +// fdpll1_clock_div +#ifndef CONF_FDPLL1_DIV +#define CONF_FDPLL1_DIV 0x0 +#endif + +// DCO Filter Enable +// Indicates whether DCO Filter Enable is enabled or not +// fdpll1_arch_dcoen +#ifndef CONF_FDPLL1_DCOEN +#define CONF_FDPLL1_DCOEN 0 +#endif + +// Sigma-Delta DCO Filter Selection <0x0-0x7> +// fdpll1_clock_dcofilter +#ifndef CONF_FDPLL1_DCOFILTER +#define CONF_FDPLL1_DCOFILTER 0x0 +#endif + +// Lock Bypass +// Indicates whether Lock Bypass is enabled or not +// fdpll1_arch_lbypass +#ifndef CONF_FDPLL1_LBYPASS +#define CONF_FDPLL1_LBYPASS 0 +#endif + +// Lock Time +// <0x0=>No time-out, automatic lock +// <0x4=>The Time-out if no lock within 800 us +// <0x5=>The Time-out if no lock within 900 us +// <0x6=>The Time-out if no lock within 1 ms +// <0x7=>The Time-out if no lock within 11 ms +// fdpll1_arch_ltime +#ifndef CONF_FDPLL1_LTIME +#define CONF_FDPLL1_LTIME 0x0 +#endif + +// Reference Clock Selection +// <0x0=>GCLK clock reference +// <0x1=>XOSC32K clock reference +// <0x2=>XOSC0 clock reference +// <0x3=>XOSC1 clock reference +// fdpll1_arch_refclk +#ifndef CONF_FDPLL1_REFCLK +#define CONF_FDPLL1_REFCLK 0x1 +#endif + +// Wake Up Fast +// Indicates whether Wake Up Fast is enabled or not +// fdpll1_arch_wuf +#ifndef CONF_FDPLL1_WUF +#define CONF_FDPLL1_WUF 0 +#endif + +// Proportional Integral Filter Selection <0x0-0xF> +// fdpll1_arch_filter +#ifndef CONF_FDPLL1_FILTER +#define CONF_FDPLL1_FILTER 0x0 +#endif + +// +// + +// <<< end of configuration section >>> + +#endif // HPL_OSCCTRL_CONFIG_H diff --git a/software/firmware/oracle_same54n19a/config/hpl_port_config.h b/software/firmware/oracle_same54n19a/config/hpl_port_config.h new file mode 100644 index 00000000..a7bd3797 --- /dev/null +++ b/software/firmware/oracle_same54n19a/config/hpl_port_config.h @@ -0,0 +1,403 @@ +/* Auto-generated config file hpl_port_config.h */ +#ifndef HPL_PORT_CONFIG_H +#define HPL_PORT_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// PORT Input Event 0 configuration +// enable_port_input_event_0 +#ifndef CONF_PORT_EVCTRL_PORT_0 +#define CONF_PORT_EVCTRL_PORT_0 0 +#endif + +// PORT Input Event 0 configuration on PORT A + +// PORTA Input Event 0 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 0 configuration is enabled +// porta_input_event_enable_0 +#ifndef CONF_PORTA_EVCTRL_PORTEI_0 +#define CONF_PORTA_EVCTRL_PORTEI_0 0x0 +#endif + +// PORTA Event 0 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_0 +#ifndef CONF_PORTA_EVCTRL_PID_0 +#define CONF_PORTA_EVCTRL_PID_0 0x0 +#endif + +// PORTA Event 0 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 0 +// porta_event_action_0 +#ifndef CONF_PORTA_EVCTRL_EVACT_0 +#define CONF_PORTA_EVCTRL_EVACT_0 0 +#endif + +// +// PORT Input Event 0 configuration on PORT B + +// PORTB Input Event 0 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 0 configuration is enabled +// portb_input_event_enable_0 +#ifndef CONF_PORTB_EVCTRL_PORTEI_0 +#define CONF_PORTB_EVCTRL_PORTEI_0 0x0 +#endif + +// PORTB Event 0 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_0 +#ifndef CONF_PORTB_EVCTRL_PID_0 +#define CONF_PORTB_EVCTRL_PID_0 0x0 +#endif + +// PORTB Event 0 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 0 +// portb_event_action_0 +#ifndef CONF_PORTB_EVCTRL_EVACT_0 +#define CONF_PORTB_EVCTRL_EVACT_0 0 +#endif + +// +// PORT Input Event 0 configuration on PORT C + +// PORTC Input Event 0 Enable +// The event action will be triggered on any incoming event if PORT C Input Event 0 configuration is enabled +// portc_input_event_enable_0 +#ifndef CONF_PORTC_EVCTRL_PORTEI_0 +#define CONF_PORTC_EVCTRL_PORTEI_0 0x0 +#endif + +// PORTC Event 0 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port C on which the event action will be performed +// portc_event_pin_identifier_0 +#ifndef CONF_PORTC_EVCTRL_PID_0 +#define CONF_PORTC_EVCTRL_PID_0 0x0 +#endif + +// PORTC Event 0 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT C will perform on event input 0 +// portc_event_action_0 +#ifndef CONF_PORTC_EVCTRL_EVACT_0 +#define CONF_PORTC_EVCTRL_EVACT_0 0 +#endif + +// + +// + +// PORT Input Event 1 configuration +// enable_port_input_event_1 +#ifndef CONF_PORT_EVCTRL_PORT_1 +#define CONF_PORT_EVCTRL_PORT_1 0 +#endif + +// PORT Input Event 1 configuration on PORT A + +// PORTA Input Event 1 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 1 configuration is enabled +// porta_input_event_enable_1 +#ifndef CONF_PORTA_EVCTRL_PORTEI_1 +#define CONF_PORTA_EVCTRL_PORTEI_1 0x0 +#endif + +// PORTA Event 1 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_1 +#ifndef CONF_PORTA_EVCTRL_PID_1 +#define CONF_PORTA_EVCTRL_PID_1 0x0 +#endif + +// PORTA Event 1 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 1 +// porta_event_action_1 +#ifndef CONF_PORTA_EVCTRL_EVACT_1 +#define CONF_PORTA_EVCTRL_EVACT_1 0 +#endif + +// +// PORT Input Event 1 configuration on PORT B + +// PORTB Input Event 1 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 1 configuration is enabled +// portb_input_event_enable_1 +#ifndef CONF_PORTB_EVCTRL_PORTEI_1 +#define CONF_PORTB_EVCTRL_PORTEI_1 0x0 +#endif + +// PORTB Event 1 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_1 +#ifndef CONF_PORTB_EVCTRL_PID_1 +#define CONF_PORTB_EVCTRL_PID_1 0x0 +#endif + +// PORTB Event 1 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 1 +// portb_event_action_1 +#ifndef CONF_PORTB_EVCTRL_EVACT_1 +#define CONF_PORTB_EVCTRL_EVACT_1 0 +#endif + +// +// PORT Input Event 1 configuration on PORT C + +// PORTC Input Event 1 Enable +// The event action will be triggered on any incoming event if PORT C Input Event 1 configuration is enabled +// portc_input_event_enable_1 +#ifndef CONF_PORTC_EVCTRL_PORTEI_1 +#define CONF_PORTC_EVCTRL_PORTEI_1 0x0 +#endif + +// PORTC Event 1 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port C on which the event action will be performed +// portc_event_pin_identifier_1 +#ifndef CONF_PORTC_EVCTRL_PID_1 +#define CONF_PORTC_EVCTRL_PID_1 0x0 +#endif + +// PORTC Event 1 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT C will perform on event input 1 +// portc_event_action_1 +#ifndef CONF_PORTC_EVCTRL_EVACT_1 +#define CONF_PORTC_EVCTRL_EVACT_1 0 +#endif + +// + +// + +// PORT Input Event 2 configuration +// enable_port_input_event_2 +#ifndef CONF_PORT_EVCTRL_PORT_2 +#define CONF_PORT_EVCTRL_PORT_2 0 +#endif + +// PORT Input Event 2 configuration on PORT A + +// PORTA Input Event 2 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 2 configuration is enabled +// porta_input_event_enable_2 +#ifndef CONF_PORTA_EVCTRL_PORTEI_2 +#define CONF_PORTA_EVCTRL_PORTEI_2 0x0 +#endif + +// PORTA Event 2 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_2 +#ifndef CONF_PORTA_EVCTRL_PID_2 +#define CONF_PORTA_EVCTRL_PID_2 0x0 +#endif + +// PORTA Event 2 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 2 +// porta_event_action_2 +#ifndef CONF_PORTA_EVCTRL_EVACT_2 +#define CONF_PORTA_EVCTRL_EVACT_2 0 +#endif + +// +// PORT Input Event 2 configuration on PORT B + +// PORTB Input Event 2 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 2 configuration is enabled +// portb_input_event_enable_2 +#ifndef CONF_PORTB_EVCTRL_PORTEI_2 +#define CONF_PORTB_EVCTRL_PORTEI_2 0x0 +#endif + +// PORTB Event 2 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_2 +#ifndef CONF_PORTB_EVCTRL_PID_2 +#define CONF_PORTB_EVCTRL_PID_2 0x0 +#endif + +// PORTB Event 2 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 2 +// portb_event_action_2 +#ifndef CONF_PORTB_EVCTRL_EVACT_2 +#define CONF_PORTB_EVCTRL_EVACT_2 0 +#endif + +// +// PORT Input Event 2 configuration on PORT C + +// PORTC Input Event 2 Enable +// The event action will be triggered on any incoming event if PORT C Input Event 2 configuration is enabled +// portc_input_event_enable_2 +#ifndef CONF_PORTC_EVCTRL_PORTEI_2 +#define CONF_PORTC_EVCTRL_PORTEI_2 0x0 +#endif + +// PORTC Event 2 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port C on which the event action will be performed +// portc_event_pin_identifier_2 +#ifndef CONF_PORTC_EVCTRL_PID_2 +#define CONF_PORTC_EVCTRL_PID_2 0x0 +#endif + +// PORTC Event 2 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT C will perform on event input 2 +// portc_event_action_2 +#ifndef CONF_PORTC_EVCTRL_EVACT_2 +#define CONF_PORTC_EVCTRL_EVACT_2 0 +#endif + +// + +// + +// PORT Input Event 3 configuration +// enable_port_input_event_3 +#ifndef CONF_PORT_EVCTRL_PORT_3 +#define CONF_PORT_EVCTRL_PORT_3 0 +#endif + +// PORT Input Event 3 configuration on PORT A + +// PORTA Input Event 3 Enable +// The event action will be triggered on any incoming event if PORT A Input Event 3 configuration is enabled +// porta_input_event_enable_3 +#ifndef CONF_PORTA_EVCTRL_PORTEI_3 +#define CONF_PORTA_EVCTRL_PORTEI_3 0x0 +#endif + +// PORTA Event 3 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port A on which the event action will be performed +// porta_event_pin_identifier_3 +#ifndef CONF_PORTA_EVCTRL_PID_3 +#define CONF_PORTA_EVCTRL_PID_3 0x0 +#endif + +// PORTA Event 3 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT A will perform on event input 3 +// porta_event_action_3 +#ifndef CONF_PORTA_EVCTRL_EVACT_3 +#define CONF_PORTA_EVCTRL_EVACT_3 0 +#endif + +// +// PORT Input Event 3 configuration on PORT B + +// PORTB Input Event 3 Enable +// The event action will be triggered on any incoming event if PORT B Input Event 3 configuration is enabled +// portb_input_event_enable_3 +#ifndef CONF_PORTB_EVCTRL_PORTEI_3 +#define CONF_PORTB_EVCTRL_PORTEI_3 0x0 +#endif + +// PORTB Event 3 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port B on which the event action will be performed +// portb_event_pin_identifier_3 +#ifndef CONF_PORTB_EVCTRL_PID_3 +#define CONF_PORTB_EVCTRL_PID_3 0x0 +#endif + +// PORTB Event 3 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT B will perform on event input 3 +// portb_event_action_3 +#ifndef CONF_PORTB_EVCTRL_EVACT_3 +#define CONF_PORTB_EVCTRL_EVACT_3 0 +#endif + +// +// PORT Input Event 3 configuration on PORT C + +// PORTC Input Event 3 Enable +// The event action will be triggered on any incoming event if PORT C Input Event 3 configuration is enabled +// portc_input_event_enable_3 +#ifndef CONF_PORTC_EVCTRL_PORTEI_3 +#define CONF_PORTC_EVCTRL_PORTEI_3 0x0 +#endif + +// PORTC Event 3 Pin Identifier <0x00-0x1F> +// These bits define the I/O pin from port C on which the event action will be performed +// portc_event_pin_identifier_3 +#ifndef CONF_PORTC_EVCTRL_PID_3 +#define CONF_PORTC_EVCTRL_PID_3 0x0 +#endif + +// PORTC Event 3 Action +// <0=> Output register of pin will be set to level of event +// <1=> Set output register of pin on event +// <2=> Clear output register of pin on event +// <3=> Toggle output register of pin on event +// These bits define the event action the PORT C will perform on event input 3 +// portc_event_action_3 +#ifndef CONF_PORTC_EVCTRL_EVACT_3 +#define CONF_PORTC_EVCTRL_EVACT_3 0 +#endif + +// + +// + +#define CONF_PORTA_EVCTRL \ + (0 | PORT_EVCTRL_EVACT0(CONF_PORTA_EVCTRL_EVACT_0) | CONF_PORTA_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ + | PORT_EVCTRL_PID0(CONF_PORTA_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTA_EVCTRL_EVACT_1) \ + | CONF_PORTA_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTA_EVCTRL_PID_1) \ + | PORT_EVCTRL_EVACT2(CONF_PORTA_EVCTRL_EVACT_2) | CONF_PORTA_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ + | PORT_EVCTRL_PID2(CONF_PORTA_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTA_EVCTRL_EVACT_3) \ + | CONF_PORTA_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTA_EVCTRL_PID_3)) +#define CONF_PORTB_EVCTRL \ + (0 | PORT_EVCTRL_EVACT0(CONF_PORTB_EVCTRL_EVACT_0) | CONF_PORTB_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ + | PORT_EVCTRL_PID0(CONF_PORTB_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTB_EVCTRL_EVACT_1) \ + | CONF_PORTB_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTB_EVCTRL_PID_1) \ + | PORT_EVCTRL_EVACT2(CONF_PORTB_EVCTRL_EVACT_2) | CONF_PORTB_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ + | PORT_EVCTRL_PID2(CONF_PORTB_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTB_EVCTRL_EVACT_3) \ + | CONF_PORTB_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTB_EVCTRL_PID_3)) +#define CONF_PORTC_EVCTRL \ + (0 | PORT_EVCTRL_EVACT0(CONF_PORTC_EVCTRL_EVACT_0) | CONF_PORTC_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \ + | PORT_EVCTRL_PID0(CONF_PORTC_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTC_EVCTRL_EVACT_1) \ + | CONF_PORTC_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTC_EVCTRL_PID_1) \ + | PORT_EVCTRL_EVACT2(CONF_PORTC_EVCTRL_EVACT_2) | CONF_PORTC_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \ + | PORT_EVCTRL_PID2(CONF_PORTC_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTC_EVCTRL_EVACT_3) \ + | CONF_PORTC_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTC_EVCTRL_PID_3)) + +// <<< end of configuration section >>> + +#endif // HPL_PORT_CONFIG_H diff --git a/software/firmware/oracle_same54n19a/config/hpl_sercom_config.h b/software/firmware/oracle_same54n19a/config/hpl_sercom_config.h new file mode 100644 index 00000000..a0c6c176 --- /dev/null +++ b/software/firmware/oracle_same54n19a/config/hpl_sercom_config.h @@ -0,0 +1,413 @@ +/* Auto-generated config file hpl_sercom_config.h */ +#ifndef HPL_SERCOM_CONFIG_H +#define HPL_SERCOM_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#include + +#ifndef CONF_SERCOM_0_USART_ENABLE +#define CONF_SERCOM_0_USART_ENABLE 1 +#endif + +// Basic Configuration + +// Receive buffer enable +// Enable input buffer in SERCOM module +// usart_rx_enable +#ifndef CONF_SERCOM_0_USART_RXEN +#define CONF_SERCOM_0_USART_RXEN 1 +#endif + +// Transmitt buffer enable +// Enable output buffer in SERCOM module +// usart_tx_enable +#ifndef CONF_SERCOM_0_USART_TXEN +#define CONF_SERCOM_0_USART_TXEN 1 +#endif + +// Frame parity +// <0x0=>No parity +// <0x1=>Even parity +// <0x2=>Odd parity +// Parity bit mode for USART frame +// usart_parity +#ifndef CONF_SERCOM_0_USART_PARITY +#define CONF_SERCOM_0_USART_PARITY 0x0 +#endif + +// Character Size +// <0x0=>8 bits +// <0x1=>9 bits +// <0x5=>5 bits +// <0x6=>6 bits +// <0x7=>7 bits +// Data character size in USART frame +// usart_character_size +#ifndef CONF_SERCOM_0_USART_CHSIZE +#define CONF_SERCOM_0_USART_CHSIZE 0x0 +#endif + +// Stop Bit +// <0=>One stop bit +// <1=>Two stop bits +// Number of stop bits in USART frame +// usart_stop_bit +#ifndef CONF_SERCOM_0_USART_SBMODE +#define CONF_SERCOM_0_USART_SBMODE 0 +#endif + +// Baud rate <1-6250000> +// USART baud rate setting +// usart_baud_rate +#ifndef CONF_SERCOM_0_USART_BAUD +#define CONF_SERCOM_0_USART_BAUD 115200 +#endif + +// + +// Advanced configuration +// usart_advanced +#ifndef CONF_SERCOM_0_USART_ADVANCED_CONFIG +#define CONF_SERCOM_0_USART_ADVANCED_CONFIG 0 +#endif + +// Run in stand-by +// Keep the module running in standby sleep mode +// usart_arch_runstdby +#ifndef CONF_SERCOM_0_USART_RUNSTDBY +#define CONF_SERCOM_0_USART_RUNSTDBY 0 +#endif + +// Immediate Buffer Overflow Notification +// Controls when the BUFOVF status bit is asserted +// usart_arch_ibon +#ifndef CONF_SERCOM_0_USART_IBON +#define CONF_SERCOM_0_USART_IBON 0 +#endif + +// Start of Frame Detection Enable +// Will wake the device from any sleep mode if usart_init and usart_enable was run priort to going to sleep. (receive buffer must be enabled) +// usart_arch_sfde +#ifndef CONF_SERCOM_0_USART_SFDE +#define CONF_SERCOM_0_USART_SFDE 0 +#endif + +// Collision Detection Enable +// Collision detection enable +// usart_arch_cloden +#ifndef CONF_SERCOM_0_USART_CLODEN +#define CONF_SERCOM_0_USART_CLODEN 0 +#endif + +// Operating Mode +// <0x0=>USART with external clock +// <0x1=>USART with internal clock +// Drive the shift register by an internal clock generated by the baud rate generator or an external clock supplied on the XCK pin. +// usart_arch_clock_mode +#ifndef CONF_SERCOM_0_USART_MODE +#define CONF_SERCOM_0_USART_MODE 0x1 +#endif + +// Sample Rate +// <0x0=>16x arithmetic +// <0x1=>16x fractional +// <0x2=>8x arithmetic +// <0x3=>8x fractional +// <0x4=>3x arithmetic +// How many over-sampling bits used when sampling data state +// usart_arch_sampr +#ifndef CONF_SERCOM_0_USART_SAMPR +#define CONF_SERCOM_0_USART_SAMPR 0x0 +#endif + +// Sample Adjustment +// <0x0=>7-8-9 (3-4-5 8-bit over-sampling) +// <0x1=>9-10-11 (4-5-6 8-bit over-sampling) +// <0x2=>11-12-13 (5-6-7 8-bit over-sampling) +// <0x3=>13-14-15 (6-7-8 8-bit over-sampling) +// Adjust which samples to use for data sampling in asynchronous mode +// usart_arch_sampa +#ifndef CONF_SERCOM_0_USART_SAMPA +#define CONF_SERCOM_0_USART_SAMPA 0x0 +#endif + +// Fractional Part <0-7> +// Fractional part of the baud rate if baud rate generator is in fractional mode +// usart_arch_fractional +#ifndef CONF_SERCOM_0_USART_FRACTIONAL +#define CONF_SERCOM_0_USART_FRACTIONAL 0x0 +#endif + +// Data Order +// <0=>MSB is transmitted first +// <1=>LSB is transmitted first +// Data order of the data bits in the frame +// usart_arch_dord +#ifndef CONF_SERCOM_0_USART_DORD +#define CONF_SERCOM_0_USART_DORD 1 +#endif + +// Does not do anything in UART mode +#define CONF_SERCOM_0_USART_CPOL 0 + +// Encoding Format +// <0=>No encoding +// <1=>IrDA encoded +// usart_arch_enc +#ifndef CONF_SERCOM_0_USART_ENC +#define CONF_SERCOM_0_USART_ENC 0 +#endif + +// LIN Slave Enable +// Break Character Detection and Auto-Baud/LIN Slave Enable. +// Additional setting needed: 16x sample rate using fractional baud rate generation (CTRLA.SAMPR = 1). +// <0=>Disable +// <1=>Enable +// usart_arch_lin_slave_enable +#ifndef CONF_SERCOM_0_USART_LIN_SLAVE_ENABLE +#define CONF_SERCOM_0_USART_LIN_SLAVE_ENABLE 0 +#endif + +// Debug Stop Mode +// Behavior of the baud-rate generator when CPU is halted by external debugger. +// <0=>Keep running +// <1=>Halt +// usart_arch_dbgstop +#ifndef CONF_SERCOM_0_USART_DEBUG_STOP_MODE +#define CONF_SERCOM_0_USART_DEBUG_STOP_MODE 0 +#endif + +// + +#ifndef CONF_SERCOM_0_USART_INACK +#define CONF_SERCOM_0_USART_INACK 0x0 +#endif + +#ifndef CONF_SERCOM_0_USART_DSNACK +#define CONF_SERCOM_0_USART_DSNACK 0x0 +#endif + +#ifndef CONF_SERCOM_0_USART_MAXITER +#define CONF_SERCOM_0_USART_MAXITER 0x7 +#endif + +#ifndef CONF_SERCOM_0_USART_GTIME +#define CONF_SERCOM_0_USART_GTIME 0x2 +#endif + +#define CONF_SERCOM_0_USART_RXINV 0x0 +#define CONF_SERCOM_0_USART_TXINV 0x0 + +#ifndef CONF_SERCOM_0_USART_CMODE +#define CONF_SERCOM_0_USART_CMODE 0 +#endif + +#ifndef CONF_SERCOM_0_USART_RXPO +#define CONF_SERCOM_0_USART_RXPO 1 /* RX is on PIN_PA05 */ +#endif + +#ifndef CONF_SERCOM_0_USART_TXPO +#define CONF_SERCOM_0_USART_TXPO 0 /* TX is on PIN_PA04 */ +#endif + +/* Set correct parity settings in register interface based on PARITY setting */ +#if CONF_SERCOM_0_USART_LIN_SLAVE_ENABLE == 1 +#if CONF_SERCOM_0_USART_PARITY == 0 +#define CONF_SERCOM_0_USART_PMODE 0 +#define CONF_SERCOM_0_USART_FORM 4 +#else +#define CONF_SERCOM_0_USART_PMODE CONF_SERCOM_0_USART_PARITY - 1 +#define CONF_SERCOM_0_USART_FORM 5 +#endif +#else /* #if CONF_SERCOM_0_USART_LIN_SLAVE_ENABLE == 0 */ +#if CONF_SERCOM_0_USART_PARITY == 0 +#define CONF_SERCOM_0_USART_PMODE 0 +#define CONF_SERCOM_0_USART_FORM 0 +#else +#define CONF_SERCOM_0_USART_PMODE CONF_SERCOM_0_USART_PARITY - 1 +#define CONF_SERCOM_0_USART_FORM 1 +#endif +#endif + +// Calculate BAUD register value in UART mode +#if CONF_SERCOM_0_USART_SAMPR == 0 +#ifndef CONF_SERCOM_0_USART_BAUD_RATE +#define CONF_SERCOM_0_USART_BAUD_RATE \ + 65536 - ((65536 * 16.0f * CONF_SERCOM_0_USART_BAUD) / CONF_GCLK_SERCOM0_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_0_USART_SAMPR == 1 +#ifndef CONF_SERCOM_0_USART_BAUD_RATE +#define CONF_SERCOM_0_USART_BAUD_RATE \ + ((CONF_GCLK_SERCOM0_CORE_FREQUENCY) / (CONF_SERCOM_0_USART_BAUD * 16)) - (CONF_SERCOM_0_USART_FRACTIONAL / 8) +#endif +#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_0_USART_SAMPR == 2 +#ifndef CONF_SERCOM_0_USART_BAUD_RATE +#define CONF_SERCOM_0_USART_BAUD_RATE \ + 65536 - ((65536 * 8.0f * CONF_SERCOM_0_USART_BAUD) / CONF_GCLK_SERCOM0_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_0_USART_SAMPR == 3 +#ifndef CONF_SERCOM_0_USART_BAUD_RATE +#define CONF_SERCOM_0_USART_BAUD_RATE \ + ((CONF_GCLK_SERCOM0_CORE_FREQUENCY) / (CONF_SERCOM_0_USART_BAUD * 8)) - (CONF_SERCOM_0_USART_FRACTIONAL / 8) +#endif +#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#elif CONF_SERCOM_0_USART_SAMPR == 4 +#ifndef CONF_SERCOM_0_USART_BAUD_RATE +#define CONF_SERCOM_0_USART_BAUD_RATE \ + 65536 - ((65536 * 3.0f * CONF_SERCOM_0_USART_BAUD) / CONF_GCLK_SERCOM0_CORE_FREQUENCY) +#endif +#ifndef CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH +#define CONF_SERCOM_0_USART_RECEIVE_PULSE_LENGTH 0 +#endif +#endif + +#include + +#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER +#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2) +#endif + +#ifndef CONF_SERCOM_3_I2CM_ENABLE +#define CONF_SERCOM_3_I2CM_ENABLE 1 +#endif + +// Basic + +// I2C Bus clock speed (Hz) <1-400000> +// I2C Bus clock (SCL) speed measured in Hz +// i2c_master_baud_rate +#ifndef CONF_SERCOM_3_I2CM_BAUD +#define CONF_SERCOM_3_I2CM_BAUD 100000 +#endif + +// + +// Advanced +// i2c_master_advanced +#ifndef CONF_SERCOM_3_I2CM_ADVANCED_CONFIG +#define CONF_SERCOM_3_I2CM_ADVANCED_CONFIG 0 +#endif + +// TRise (ns) <0-300> +// Determined by the bus impedance, check electric characteristics in the datasheet +// Standard Fast Mode: typical 215ns, max 300ns +// Fast Mode +: typical 60ns, max 100ns +// High Speed Mode: typical 20ns, max 40ns +// i2c_master_arch_trise + +#ifndef CONF_SERCOM_3_I2CM_TRISE +#define CONF_SERCOM_3_I2CM_TRISE 215 +#endif + +// Master SCL Low Extended Time-Out (MEXTTOEN) +// This enables the master SCL low extend time-out +// i2c_master_arch_mexttoen +#ifndef CONF_SERCOM_3_I2CM_MEXTTOEN +#define CONF_SERCOM_3_I2CM_MEXTTOEN 0 +#endif + +// Slave SCL Low Extend Time-Out (SEXTTOEN) +// Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine +// i2c_master_arch_sexttoen +#ifndef CONF_SERCOM_3_I2CM_SEXTTOEN +#define CONF_SERCOM_3_I2CM_SEXTTOEN 0 +#endif + +// SCL Low Time-Out (LOWTOUT) +// Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold +// i2c_master_arch_lowtout +#ifndef CONF_SERCOM_3_I2CM_LOWTOUT +#define CONF_SERCOM_3_I2CM_LOWTOUT 0 +#endif + +// Inactive Time-Out (INACTOUT) +// <0x0=>Disabled +// <0x1=>5-6 SCL cycle time-out(50-60us) +// <0x2=>10-11 SCL cycle time-out(100-110us) +// <0x3=>20-21 SCL cycle time-out(200-210us) +// Defines if inactivity time-out should be enabled, and how long the time-out should be +// i2c_master_arch_inactout +#ifndef CONF_SERCOM_3_I2CM_INACTOUT +#define CONF_SERCOM_3_I2CM_INACTOUT 0x0 +#endif + +// SDA Hold Time (SDAHOLD) +// <0=>Disabled +// <1=>50-100ns hold time +// <2=>300-600ns hold time +// <3=>400-800ns hold time +// Defines the SDA hold time with respect to the negative edge of SCL +// i2c_master_arch_sdahold +#ifndef CONF_SERCOM_3_I2CM_SDAHOLD +#define CONF_SERCOM_3_I2CM_SDAHOLD 0x2 +#endif + +// Run in stand-by +// Determine if the module shall run in standby sleep mode +// i2c_master_arch_runstdby +#ifndef CONF_SERCOM_3_I2CM_RUNSTDBY +#define CONF_SERCOM_3_I2CM_RUNSTDBY 0 +#endif + +// Debug Stop Mode +// Behavior of the baud-rate generator when CPU is halted by external debugger. +// <0=>Keep running +// <1=>Halt +// i2c_master_arch_dbgstop +#ifndef CONF_SERCOM_3_I2CM_DEBUG_STOP_MODE +#define CONF_SERCOM_3_I2CM_DEBUG_STOP_MODE 0 +#endif + +// + +#ifndef CONF_SERCOM_3_I2CM_SPEED +#define CONF_SERCOM_3_I2CM_SPEED 0x00 // Speed: Standard/Fast mode +#endif +#if CONF_SERCOM_3_I2CM_TRISE < 215 || CONF_SERCOM_3_I2CM_TRISE > 300 +#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns +#undef CONF_SERCOM_3_I2CM_TRISE +#define CONF_SERCOM_3_I2CM_TRISE 215U +#endif + +// gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise) +// BAUD + BAUDLOW = -------------------------------------------------------------------- +// i2c_scl_freq +// BAUD: register value low [7:0] +// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW +#define CONF_SERCOM_3_I2CM_BAUD_BAUDLOW \ + (((CONF_GCLK_SERCOM3_CORE_FREQUENCY - (CONF_SERCOM_3_I2CM_BAUD * 10U) \ + - (CONF_SERCOM_3_I2CM_TRISE * (CONF_SERCOM_3_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM3_CORE_FREQUENCY / 10000U) \ + / 1000U)) \ + * 10U \ + + 5U) \ + / (CONF_SERCOM_3_I2CM_BAUD * 10U)) +#ifndef CONF_SERCOM_3_I2CM_BAUD_RATE +#if CONF_SERCOM_3_I2CM_BAUD_BAUDLOW > (0xFF * 2) +#warning Requested I2C baudrate too low, please check +#define CONF_SERCOM_3_I2CM_BAUD_RATE 0xFF +#elif CONF_SERCOM_3_I2CM_BAUD_BAUDLOW <= 1 +#warning Requested I2C baudrate too high, please check +#define CONF_SERCOM_3_I2CM_BAUD_RATE 1 +#else +#define CONF_SERCOM_3_I2CM_BAUD_RATE \ + ((CONF_SERCOM_3_I2CM_BAUD_BAUDLOW & 0x1) \ + ? (CONF_SERCOM_3_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_3_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \ + : (CONF_SERCOM_3_I2CM_BAUD_BAUDLOW / 2)) +#endif +#endif + +// <<< end of configuration section >>> + +#endif // HPL_SERCOM_CONFIG_H diff --git a/software/firmware/oracle_same54n19a/config/hpl_tc_config.h b/software/firmware/oracle_same54n19a/config/hpl_tc_config.h new file mode 100644 index 00000000..ae5921cd --- /dev/null +++ b/software/firmware/oracle_same54n19a/config/hpl_tc_config.h @@ -0,0 +1,180 @@ +/* Auto-generated config file hpl_tc_config.h */ +#ifndef HPL_TC_CONFIG_H +#define HPL_TC_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +#ifndef CONF_TC0_ENABLE +#define CONF_TC0_ENABLE 1 +#endif + +#include "peripheral_clk_config.h" + +// Basic configuration + +// Prescaler +// <0x0=> No division +// <0x1=> Divide by 2 +// <0x2=> Divide by 4 +// <0x3=> Divide by 8 +// <0x4=> Divide by 16 +// <0x5=> Divide by 64 +// <0x6=> Divide by 256 +// <0x7=> Divide by 1024 +// This defines the prescaler value +// timer_prescaler +#ifndef CONF_TC0_PRESCALER +#define CONF_TC0_PRESCALER 0x3 +#endif + +// Length of one timer tick in uS <0-4294967295> +// timer_tick +#ifndef CONF_TC0_TIMER_TICK +#define CONF_TC0_TIMER_TICK 1000 +#endif +// + +// Advanced configuration +// timer_advanced_configuration +#ifndef CONF_TC0__ADVANCED_CONFIGURATION_ENABLE +#define CONF_TC0__ADVANCED_CONFIGURATION_ENABLE 0 +#endif + +// Prescaler and Counter Synchronization Selection +// Reload or reset counter on next GCLK +// Reload or reset counter on next prescaler clock +// Reload or reset counter on next GCLK and reset prescaler counter +// These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCx clock or on the next prescaled GCLK_TCx clock. +// tc_arch_presync +#ifndef CONF_TC0_PRESCSYNC +#define CONF_TC0_PRESCSYNC TC_CTRLA_PRESCSYNC_GCLK_Val +#endif + +// Run in standby +// Indicates whether the module will continue to run in standby sleep mode +// tc_arch_runstdby +#ifndef CONF_TC0_RUNSTDBY +#define CONF_TC0_RUNSTDBY 0 +#endif + +// Run in debug mode +// Indicates whether the module will run in debug mode +// tc_arch_dbgrun +#ifndef CONF_TC0_DBGRUN +#define CONF_TC0_DBGRUN 0 +#endif + +// Run on demand +// Run if requested by some other peripheral in the device +// tc_arch_ondemand +#ifndef CONF_TC0_ONDEMAND +#define CONF_TC0_ONDEMAND 0 +#endif + +// + +// Event control +// timer_event_control +#ifndef CONF_TC0_EVENT_CONTROL_ENABLE +#define CONF_TC0_EVENT_CONTROL_ENABLE 0 +#endif + +// Output Event On Match or Capture on Channel 0 +// Enable output of event on timer tick +// tc_arch_mceo0 +#ifndef CONF_TC0_MCEO0 +#define CONF_TC0_MCEO0 0 +#endif + +// Output Event On Match or Capture on Channel 1 +// Enable output of event on timer tick +// tc_arch_mceo1 +#ifndef CONF_TC0_MCEO1 +#define CONF_TC0_MCEO1 0 +#endif + +// Output Event On Timer Tick +// Enable output of event on timer tick +// tc_arch_ovfeo +#ifndef CONF_TC0_OVFEO +#define CONF_TC0_OVFEO 0 +#endif + +// Event Input +// Enable asynchronous input events +// tc_arch_tcei +#ifndef CONF_TC0_TCEI +#define CONF_TC0_TCEI 0 +#endif + +// Inverted Event Input +// Invert the asynchronous input events +// tc_arch_tcinv +#ifndef CONF_TC0_TCINV +#define CONF_TC0_TCINV 0 +#endif + +// Event action +// <0=> Event action disabled +// <1=> Start, restart or re-trigger TC on event +// <2=> Count on event +// <3=> Start on event +// <4=> Time stamp capture +// <5=> Period captured in CC0, pulse width in CC1 +// <6=> Period captured in CC1, pulse width in CC0 +// <7=> Pulse width capture +// Event which will be performed on an event +// tc_arch_evact +#ifndef CONF_TC0_EVACT +#define CONF_TC0_EVACT 0 +#endif +// + +// Default values which the driver needs in order to work correctly + +// Mode set to 32-bit +#ifndef CONF_TC0_MODE +#define CONF_TC0_MODE TC_CTRLA_MODE_COUNT32_Val +#endif + +// CC 1 register set to 0 +#ifndef CONF_TC0_CC1 +#define CONF_TC0_CC1 0 +#endif + +#ifndef CONF_TC0_ALOCK +#define CONF_TC0_ALOCK 0 +#endif + +// Not used in 32-bit mode +#define CONF_TC0_PER 0 + +// Calculating correct top value based on requested tick interval. +#define CONF_TC0_PRESCALE (1 << CONF_TC0_PRESCALER) + +// Prescaler set to 64 +#if CONF_TC0_PRESCALER > 0x4 +#undef CONF_TC0_PRESCALE +#define CONF_TC0_PRESCALE 64 +#endif + +// Prescaler set to 256 +#if CONF_TC0_PRESCALER > 0x5 +#undef CONF_TC0_PRESCALE +#define CONF_TC0_PRESCALE 256 +#endif + +// Prescaler set to 1024 +#if CONF_TC0_PRESCALER > 0x6 +#undef CONF_TC0_PRESCALE +#define CONF_TC0_PRESCALE 1024 +#endif + +#ifndef CONF_TC0_CC0 +#define CONF_TC0_CC0 \ + (uint32_t)(((float)CONF_TC0_TIMER_TICK / 1000000.f) / (1.f / (CONF_GCLK_TC0_FREQUENCY / CONF_TC0_PRESCALE))) +#endif + +// <<< end of configuration section >>> + +#endif // HPL_TC_CONFIG_H diff --git a/software/firmware/oracle_same54n19a/config/lv_conf.h b/software/firmware/oracle_same54n19a/config/lv_conf.h new file mode 100644 index 00000000..66f247d9 --- /dev/null +++ b/software/firmware/oracle_same54n19a/config/lv_conf.h @@ -0,0 +1,699 @@ +/** + * @file lv_conf.h + * + */ + +/* + * COPY THIS FILE AS `lv_conf.h` NEXT TO the `lvgl` FOLDER + */ + +#if 1 /*Set it to "1" to enable content*/ + +#ifndef LV_CONF_H +#define LV_CONF_H +/* clang-format off */ + +#include + +/*==================== + Graphical settings + *====================*/ + +/* Maximal horizontal and vertical resolution to support by the library.*/ +#define LV_HOR_RES_MAX (480) +#define LV_VER_RES_MAX (272) + +/* Color depth: + * - 1: 1 byte per pixel + * - 8: RGB233 + * - 16: RGB565 + * - 32: ARGB8888 + */ +#define LV_COLOR_DEPTH 16 + +/* Swap the 2 bytes of RGB565 color. + * Useful if the display has a 8 bit interface (e.g. SPI)*/ +#define LV_COLOR_16_SWAP 0 + +/* 1: Enable screen transparency. + * Useful for OSD or other overlapping GUIs. + * Requires `LV_COLOR_DEPTH = 32` colors and the screen's style should be modified: `style.body.opa = ...`*/ +#define LV_COLOR_SCREEN_TRANSP 0 + +/*Images pixels with this color will not be drawn (with chroma keying)*/ +#define LV_COLOR_TRANSP LV_COLOR_LIME /*LV_COLOR_LIME: pure green*/ + +/* Enable anti-aliasing (lines, and radiuses will be smoothed) */ +#define LV_ANTIALIAS 1 + +/* Default display refresh period. + * Can be changed in the display driver (`lv_disp_drv_t`).*/ +#define LV_DISP_DEF_REFR_PERIOD 30 /*[ms]*/ + +/* Dot Per Inch: used to initialize default sizes. + * E.g. a button with width = LV_DPI / 2 -> half inch wide + * (Not so important, you can adjust it to modify default sizes and spaces)*/ +#define LV_DPI 130 /*[px]*/ + +/* The the real width of the display changes some default values: + * default object sizes, layout of examples, etc. + * According to the width of the display (hor. res. / dpi) + * the displays fall in 4 categories. + * The 4th is extra large which has no upper limit so not listed here + * The upper limit of the categories are set below in 0.1 inch unit. + */ +#define LV_DISP_SMALL_LIMIT 30 +#define LV_DISP_MEDIUM_LIMIT 50 +#define LV_DISP_LARGE_LIMIT 70 + +/* Type of coordinates. Should be `int16_t` (or `int32_t` for extreme cases) */ +typedef int16_t lv_coord_t; + +/*========================= + Memory manager settings + *=========================*/ + +/* LittelvGL's internal memory manager's settings. + * The graphical objects and other related data are stored here. */ + +/* 1: use custom malloc/free, 0: use the built-in `lv_mem_alloc` and `lv_mem_free` */ +#define LV_MEM_CUSTOM 0 +#if LV_MEM_CUSTOM == 0 +/* Size of the memory used by `lv_mem_alloc` in bytes (>= 2kB)*/ +# define LV_MEM_SIZE (16U * 1024U) + +/* Complier prefix for a big array declaration */ +# define LV_MEM_ATTR + +/* Set an address for the memory pool instead of allocating it as an array. + * Can be in external SRAM too. */ +# define LV_MEM_ADR 0 + +/* Automatically defrag. on free. Defrag. means joining the adjacent free cells. */ +# define LV_MEM_AUTO_DEFRAG 1 +#else /*LV_MEM_CUSTOM*/ +# define LV_MEM_CUSTOM_INCLUDE /*Header for the dynamic memory function*/ +# define LV_MEM_CUSTOM_ALLOC malloc /*Wrapper to malloc*/ +# define LV_MEM_CUSTOM_FREE free /*Wrapper to free*/ +#endif /*LV_MEM_CUSTOM*/ + +/* Garbage Collector settings + * Used if lvgl is binded to higher level language and the memory is managed by that language */ +#define LV_ENABLE_GC 0 +#if LV_ENABLE_GC != 0 +# define LV_GC_INCLUDE "gc.h" /*Include Garbage Collector related things*/ +# define LV_MEM_CUSTOM_REALLOC your_realloc /*Wrapper to realloc*/ +# define LV_MEM_CUSTOM_GET_SIZE your_mem_get_size /*Wrapper to lv_mem_get_size*/ +#endif /* LV_ENABLE_GC */ + +/*======================= + Input device settings + *=======================*/ + +/* Input device default settings. + * Can be changed in the Input device driver (`lv_indev_drv_t`)*/ + +/* Input device read period in milliseconds */ +#define LV_INDEV_DEF_READ_PERIOD 30 + +/* Drag threshold in pixels */ +#define LV_INDEV_DEF_DRAG_LIMIT 10 + +/* Drag throw slow-down in [%]. Greater value -> faster slow-down */ +#define LV_INDEV_DEF_DRAG_THROW 10 + +/* Long press time in milliseconds. + * Time to send `LV_EVENT_LONG_PRESSSED`) */ +#define LV_INDEV_DEF_LONG_PRESS_TIME 400 + +/* Repeated trigger period in long press [ms] + * Time between `LV_EVENT_LONG_PRESSED_REPEAT */ +#define LV_INDEV_DEF_LONG_PRESS_REP_TIME 100 + + +/* Gesture threshold in pixels */ +#define LV_INDEV_DEF_GESTURE_LIMIT 50 + +/* Gesture min velocity at release before swipe (pixels)*/ +#define LV_INDEV_DEF_GESTURE_MIN_VELOCITY 3 + +/*================== + * Feature usage + *==================*/ + +/*1: Enable the Animations */ +#define LV_USE_ANIMATION 1 +#if LV_USE_ANIMATION + +/*Declare the type of the user data of animations (can be e.g. `void *`, `int`, `struct`)*/ +typedef void * lv_anim_user_data_t; + +#endif + +/* 1: Enable shadow drawing*/ +#define LV_USE_SHADOW 1 +#if LV_USE_SHADOW +/* Allow buffering some shadow calculation + * LV_SHADOW_CACHE_SIZE is the max. shadow size to buffer, + * where shadow size is `shadow_width + radius` + * Caching has LV_SHADOW_CACHE_SIZE^2 RAM cost*/ +#define LV_SHADOW_CACHE_SIZE 0 +#endif + +/* 1: Use other blend modes than normal (`LV_BLEND_MODE_...`)*/ +#define LV_USE_BLEND_MODES 1 + +/* 1: Use the `opa_scale` style property to set the opacity of an object and its children at once*/ +#define LV_USE_OPA_SCALE 1 + +/* 1: Use image zoom and rotation*/ +#define LV_USE_IMG_TRANSFORM 1 + +/* 1: Enable object groups (for keyboard/encoder navigation) */ +#define LV_USE_GROUP 1 +#if LV_USE_GROUP +typedef void * lv_group_user_data_t; +#endif /*LV_USE_GROUP*/ + +/* 1: Enable GPU interface*/ +#define LV_USE_GPU 1 /*Only enables `gpu_fill_cb` and `gpu_blend_cb` in the disp. drv- */ +#define LV_USE_GPU_STM32_DMA2D 0 + +/* 1: Enable file system (might be required for images */ +#define LV_USE_FILESYSTEM 1 +#if LV_USE_FILESYSTEM +/*Declare the type of the user data of file system drivers (can be e.g. `void *`, `int`, `struct`)*/ +typedef void * lv_fs_drv_user_data_t; +#endif + +/*1: Add a `user_data` to drivers and objects*/ +#define LV_USE_USER_DATA 0 + +/*1: Show CPU usage and FPS count in the right bottom corner*/ +#define LV_USE_PERF_MONITOR 0 + +/*1: Use the functions and types from the older API if possible */ +#define LV_USE_API_EXTENSION_V6 1 + +/*======================== + * Image decoder and cache + *========================*/ + +/* 1: Enable indexed (palette) images */ +#define LV_IMG_CF_INDEXED 1 + +/* 1: Enable alpha indexed images */ +#define LV_IMG_CF_ALPHA 1 + +/* Default image cache size. Image caching keeps the images opened. + * If only the built-in image formats are used there is no real advantage of caching. + * (I.e. no new image decoder is added) + * With complex image decoders (e.g. PNG or JPG) caching can save the continuous open/decode of images. + * However the opened images might consume additional RAM. + * LV_IMG_CACHE_DEF_SIZE must be >= 1 */ +#define LV_IMG_CACHE_DEF_SIZE 1 + +/*Declare the type of the user data of image decoder (can be e.g. `void *`, `int`, `struct`)*/ +typedef void * lv_img_decoder_user_data_t; + +/*===================== + * Compiler settings + *====================*/ +/* Define a custom attribute to `lv_tick_inc` function */ +#define LV_ATTRIBUTE_TICK_INC + +/* Define a custom attribute to `lv_task_handler` function */ +#define LV_ATTRIBUTE_TASK_HANDLER + +/* Define a custom attribute to `lv_disp_flush_ready` function */ +#define LV_ATTRIBUTE_FLUSH_READY + +/* With size optimization (-Os) the compiler might not align data to + * 4 or 8 byte boundary. This alignment will be explicitly applied where needed. + * E.g. __attribute__((aligned(4))) */ +#define LV_ATTRIBUTE_MEM_ALIGN + +/* Attribute to mark large constant arrays for example + * font's bitmaps */ +#define LV_ATTRIBUTE_LARGE_CONST + +/* Prefix performance critical functions to place them into a faster memory (e.g RAM) + * Uses 15-20 kB extra memory */ +#define LV_ATTRIBUTE_FAST_MEM + +/* Export integer constant to binding. + * This macro is used with constants in the form of LV_ that + * should also appear on lvgl binding API such as Micropython + * + * The default value just prevents a GCC warning. + */ +#define LV_EXPORT_CONST_INT(int_value) struct _silence_gcc_warning + +/*=================== + * HAL settings + *==================*/ + +/* 1: use a custom tick source. + * It removes the need to manually update the tick with `lv_tick_inc`) */ +#define LV_TICK_CUSTOM 0 +#if LV_TICK_CUSTOM == 1 +#define LV_TICK_CUSTOM_INCLUDE "something.h" /*Header for the sys time function*/ +#define LV_TICK_CUSTOM_SYS_TIME_EXPR (millis()) /*Expression evaluating to current systime in ms*/ +#endif /*LV_TICK_CUSTOM*/ + +typedef void * lv_disp_drv_user_data_t; /*Type of user data in the display driver*/ +typedef void * lv_indev_drv_user_data_t; /*Type of user data in the input device driver*/ + +/*================ + * Log settings + *===============*/ + +/*1: Enable the log module*/ +#define LV_USE_LOG 1 +#if LV_USE_LOG +/* How important log should be added: + * LV_LOG_LEVEL_TRACE A lot of logs to give detailed information + * LV_LOG_LEVEL_INFO Log important events + * LV_LOG_LEVEL_WARN Log if something unwanted happened but didn't cause a problem + * LV_LOG_LEVEL_ERROR Only critical issue, when the system may fail + * LV_LOG_LEVEL_NONE Do not log anything + */ +# define LV_LOG_LEVEL LV_LOG_LEVEL_INFO + +/* 1: Print the log with 'printf'; + * 0: user need to register a callback with `lv_log_register_print_cb`*/ +# define LV_LOG_PRINTF 0 +#endif /*LV_USE_LOG*/ + +/*================= + * Debug settings + *================*/ + +/* If Debug is enabled LittelvGL validates the parameters of the functions. + * If an invalid parameter is found an error log message is printed and + * the MCU halts at the error. (`LV_USE_LOG` should be enabled) + * If you are debugging the MCU you can pause + * the debugger to see exactly where the issue is. + * + * The behavior of asserts can be overwritten by redefining them here. + * E.g. #define LV_ASSERT_MEM(p) + */ +#define LV_USE_DEBUG 1 +#if LV_USE_DEBUG + +/*Check if the parameter is NULL. (Quite fast) */ +#define LV_USE_ASSERT_NULL 1 + +/*Checks is the memory is successfully allocated or no. (Quite fast)*/ +#define LV_USE_ASSERT_MEM 1 + +/*Check the integrity of `lv_mem` after critical operations. (Slow)*/ +#define LV_USE_ASSERT_MEM_INTEGRITY 0 + +/* Check the strings. + * Search for NULL, very long strings, invalid characters, and unnatural repetitions. (Slow) + * If disabled `LV_USE_ASSERT_NULL` will be performed instead (if it's enabled) */ +#define LV_USE_ASSERT_STR 0 + +/* Check NULL, the object's type and existence (e.g. not deleted). (Quite slow) + * If disabled `LV_USE_ASSERT_NULL` will be performed instead (if it's enabled) */ +#define LV_USE_ASSERT_OBJ 0 + +/*Check if the styles are properly initialized. (Fast)*/ +#define LV_USE_ASSERT_STYLE 0 + +#endif /*LV_USE_DEBUG*/ + +/*================== + * FONT USAGE + *===================*/ + +/* The built-in fonts contains the ASCII range and some Symbols with 4 bit-per-pixel. + * The symbols are available via `LV_SYMBOL_...` defines + * More info about fonts: https://docs.lvgl.com/#Fonts + * To create a new font go to: https://lvgl.com/ttf-font-to-c-array + */ + +/* Montserrat fonts with bpp = 4 + * https://fonts.google.com/specimen/Montserrat */ +#define LV_FONT_MONTSERRAT_12 0 +#define LV_FONT_MONTSERRAT_14 0 +#define LV_FONT_MONTSERRAT_16 1 +#define LV_FONT_MONTSERRAT_18 0 +#define LV_FONT_MONTSERRAT_20 0 +#define LV_FONT_MONTSERRAT_22 0 +#define LV_FONT_MONTSERRAT_24 0 +#define LV_FONT_MONTSERRAT_26 0 +#define LV_FONT_MONTSERRAT_28 0 +#define LV_FONT_MONTSERRAT_30 0 +#define LV_FONT_MONTSERRAT_32 0 +#define LV_FONT_MONTSERRAT_34 0 +#define LV_FONT_MONTSERRAT_36 0 +#define LV_FONT_MONTSERRAT_38 0 +#define LV_FONT_MONTSERRAT_40 0 +#define LV_FONT_MONTSERRAT_42 0 +#define LV_FONT_MONTSERRAT_44 0 +#define LV_FONT_MONTSERRAT_46 0 +#define LV_FONT_MONTSERRAT_48 0 + +/* Demonstrate special features */ +#define LV_FONT_MONTSERRAT_12_SUBPX 0 +#define LV_FONT_MONTSERRAT_28_COMPRESSED 0 /*bpp = 3*/ +#define LV_FONT_DEJAVU_16_PERSIAN_HEBREW 0 /*Hebrew, Arabic, PErisan letters and all their forms*/ +#define LV_FONT_SIMSUN_16_CJK 0 /*1000 most common CJK radicals*/ + +/*Pixel perfect monospace font + * http://pelulamu.net/unscii/ */ +#define LV_FONT_UNSCII_8 0 + +/* Optionally declare your custom fonts here. + * You can use these fonts as default font too + * and they will be available globally. E.g. + * #define LV_FONT_CUSTOM_DECLARE LV_FONT_DECLARE(my_font_1) \ + * LV_FONT_DECLARE(my_font_2) + */ +#define LV_FONT_CUSTOM_DECLARE + +/* Enable it if you have fonts with a lot of characters. + * The limit depends on the font size, font face and bpp + * but with > 10,000 characters if you see issues probably you need to enable it.*/ +#define LV_FONT_FMT_TXT_LARGE 0 + +/* Set the pixel order of the display. + * Important only if "subpx fonts" are used. + * With "normal" font it doesn't matter. + */ +#define LV_FONT_SUBPX_BGR 0 + +/*Declare the type of the user data of fonts (can be e.g. `void *`, `int`, `struct`)*/ +typedef void * lv_font_user_data_t; + +/*================ + * THEME USAGE + *================*/ + +/*Always enable at least on theme*/ + +/* No theme, you can apply your styles as you need + * No flags. Set LV_THEME_DEFAULT_FLAG 0 */ + #define LV_USE_THEME_EMPTY 1 + +/*Simple to the create your theme based on it + * No flags. Set LV_THEME_DEFAULT_FLAG 0 */ + #define LV_USE_THEME_TEMPLATE 1 + +/* A fast and impressive theme. + * Flags: + * LV_THEME_MATERIAL_FLAG_LIGHT: light theme + * LV_THEME_MATERIAL_FLAG_DARK: dark theme*/ + #define LV_USE_THEME_MATERIAL 1 + +/* Mono-color theme for monochrome displays. + * If LV_THEME_DEFAULT_COLOR_PRIMARY is LV_COLOR_BLACK the + * texts and borders will be black and the background will be + * white. Else the colors are inverted. + * No flags. Set LV_THEME_DEFAULT_FLAG 0 */ + #define LV_USE_THEME_MONO 1 + +#define LV_THEME_DEFAULT_INCLUDE /*Include a header for the init. function*/ +#define LV_THEME_DEFAULT_INIT lv_theme_material_init +#define LV_THEME_DEFAULT_COLOR_PRIMARY LV_COLOR_RED +#define LV_THEME_DEFAULT_COLOR_SECONDARY LV_COLOR_BLUE +#define LV_THEME_DEFAULT_FLAG LV_THEME_MATERIAL_FLAG_LIGHT +#define LV_THEME_DEFAULT_FONT_SMALL &lv_font_montserrat_16 +#define LV_THEME_DEFAULT_FONT_NORMAL &lv_font_montserrat_16 +#define LV_THEME_DEFAULT_FONT_SUBTITLE &lv_font_montserrat_16 +#define LV_THEME_DEFAULT_FONT_TITLE &lv_font_montserrat_16 + +/*================= + * Text settings + *=================*/ + +/* Select a character encoding for strings. + * Your IDE or editor should have the same character encoding + * - LV_TXT_ENC_UTF8 + * - LV_TXT_ENC_ASCII + * */ +#define LV_TXT_ENC LV_TXT_ENC_UTF8 + + /*Can break (wrap) texts on these chars*/ +#define LV_TXT_BREAK_CHARS " ,.;:-_" + +/* If a word is at least this long, will break wherever "prettiest" + * To disable, set to a value <= 0 */ +#define LV_TXT_LINE_BREAK_LONG_LEN 0 + +/* Minimum number of characters in a long word to put on a line before a break. + * Depends on LV_TXT_LINE_BREAK_LONG_LEN. */ +#define LV_TXT_LINE_BREAK_LONG_PRE_MIN_LEN 3 + +/* Minimum number of characters in a long word to put on a line after a break. + * Depends on LV_TXT_LINE_BREAK_LONG_LEN. */ +#define LV_TXT_LINE_BREAK_LONG_POST_MIN_LEN 3 + +/* The control character to use for signalling text recoloring. */ +#define LV_TXT_COLOR_CMD "#" + +/* Support bidirectional texts. + * Allows mixing Left-to-Right and Right-to-Left texts. + * The direction will be processed according to the Unicode Bidirectioanl Algorithm: + * https://www.w3.org/International/articles/inline-bidi-markup/uba-basics*/ +#define LV_USE_BIDI 0 +#if LV_USE_BIDI +/* Set the default direction. Supported values: + * `LV_BIDI_DIR_LTR` Left-to-Right + * `LV_BIDI_DIR_RTL` Right-to-Left + * `LV_BIDI_DIR_AUTO` detect texts base direction */ +#define LV_BIDI_BASE_DIR_DEF LV_BIDI_DIR_AUTO +#endif + +/* Enable Arabic/Persian processing + * In these languages characters should be replaced with + * an other form based on their position in the text */ +#define LV_USE_ARABIC_PERSIAN_CHARS 0 + +/*Change the built in (v)snprintf functions*/ +#define LV_SPRINTF_CUSTOM 0 +#if LV_SPRINTF_CUSTOM +# define LV_SPRINTF_INCLUDE +# define lv_snprintf snprintf +# define lv_vsnprintf vsnprintf +#endif /*LV_SPRINTF_CUSTOM*/ + +/*=================== + * LV_OBJ SETTINGS + *==================*/ + +#if LV_USE_USER_DATA +/*Declare the type of the user data of object (can be e.g. `void *`, `int`, `struct`)*/ +typedef void * lv_obj_user_data_t; +/*Provide a function to free user data*/ +#define LV_USE_USER_DATA_FREE 0 +#if LV_USE_USER_DATA_FREE +# define LV_USER_DATA_FREE_INCLUDE "something.h" /*Header for user data free function*/ +/* Function prototype : void user_data_free(lv_obj_t * obj); */ +# define LV_USER_DATA_FREE (user_data_free) /*Invoking for user data free function*/ +#endif +#endif + +/*1: enable `lv_obj_realaign()` based on `lv_obj_align()` parameters*/ +#define LV_USE_OBJ_REALIGN 1 + +/* Enable to make the object clickable on a larger area. + * LV_EXT_CLICK_AREA_OFF or 0: Disable this feature + * LV_EXT_CLICK_AREA_TINY: The extra area can be adjusted horizontally and vertically (0..255 px) + * LV_EXT_CLICK_AREA_FULL: The extra area can be adjusted in all 4 directions (-32k..+32k px) + */ +#define LV_USE_EXT_CLICK_AREA LV_EXT_CLICK_AREA_TINY + +/*================== + * LV OBJ X USAGE + *================*/ +/* + * Documentation of the object types: https://docs.lvgl.com/#Object-types + */ + +/*Arc (dependencies: -)*/ +#define LV_USE_ARC 1 + +/*Bar (dependencies: -)*/ +#define LV_USE_BAR 1 + +/*Button (dependencies: lv_cont*/ +#define LV_USE_BTN 1 + +/*Button matrix (dependencies: -)*/ +#define LV_USE_BTNMATRIX 1 + +/*Calendar (dependencies: -)*/ +#define LV_USE_CALENDAR 1 + +/*Canvas (dependencies: lv_img)*/ +#define LV_USE_CANVAS 1 + +/*Check box (dependencies: lv_btn, lv_label)*/ +#define LV_USE_CHECKBOX 1 + +/*Chart (dependencies: -)*/ +#define LV_USE_CHART 1 +#if LV_USE_CHART +# define LV_CHART_AXIS_TICK_LABEL_MAX_LEN 256 +#endif + +/*Container (dependencies: -*/ +#define LV_USE_CONT 1 + +/*Color picker (dependencies: -*/ +#define LV_USE_CPICKER 1 + +/*Drop down list (dependencies: lv_page, lv_label, lv_symbol_def.h)*/ +#define LV_USE_DROPDOWN 1 +#if LV_USE_DROPDOWN != 0 +/*Open and close default animation time [ms] (0: no animation)*/ +# define LV_DROPDOWN_DEF_ANIM_TIME 200 +#endif + +/*Gauge (dependencies:lv_bar, lv_linemeter)*/ +#define LV_USE_GAUGE 1 + +/*Image (dependencies: lv_label*/ +#define LV_USE_IMG 1 + +/*Image Button (dependencies: lv_btn*/ +#define LV_USE_IMGBTN 1 +#if LV_USE_IMGBTN +/*1: The imgbtn requires left, mid and right parts and the width can be set freely*/ +# define LV_IMGBTN_TILED 0 +#endif + +/*Keyboard (dependencies: lv_btnm)*/ +#define LV_USE_KEYBOARD 1 + +/*Label (dependencies: -*/ +#define LV_USE_LABEL 1 +#if LV_USE_LABEL != 0 +/*Hor, or ver. scroll speed [px/sec] in 'LV_LABEL_LONG_ROLL/ROLL_CIRC' mode*/ +# define LV_LABEL_DEF_SCROLL_SPEED 25 + +/* Waiting period at beginning/end of animation cycle */ +# define LV_LABEL_WAIT_CHAR_COUNT 3 + +/*Enable selecting text of the label */ +# define LV_LABEL_TEXT_SEL 0 + +/*Store extra some info in labels (12 bytes) to speed up drawing of very long texts*/ +# define LV_LABEL_LONG_TXT_HINT 0 +#endif + +/*LED (dependencies: -)*/ +#define LV_USE_LED 1 +#if LV_USE_LED +# define LV_LED_BRIGHT_MIN 120 /*Minimal brightness*/ +# define LV_LED_BRIGHT_MAX 255 /*Maximal brightness*/ +#endif + +/*Line (dependencies: -*/ +#define LV_USE_LINE 1 + +/*List (dependencies: lv_page, lv_btn, lv_label, (lv_img optionally for icons ))*/ +#define LV_USE_LIST 1 +#if LV_USE_LIST != 0 +/*Default animation time of focusing to a list element [ms] (0: no animation) */ +# define LV_LIST_DEF_ANIM_TIME 100 +#endif + +/*Line meter (dependencies: *;)*/ +#define LV_USE_LINEMETER 1 +#if LV_USE_LINEMETER +/* Draw line more precisely at cost of performance. + * Useful if there are lot of lines any minor are visible + * 0: No extra precision + * 1: Some extra precision + * 2: Best precision + */ +# define LV_LINEMETER_PRECISE 0 +#endif + +/*Mask (dependencies: -)*/ +#define LV_USE_OBJMASK 1 + +/*Message box (dependencies: lv_rect, lv_btnm, lv_label)*/ +#define LV_USE_MSGBOX 1 + +/*Page (dependencies: lv_cont)*/ +#define LV_USE_PAGE 1 +#if LV_USE_PAGE != 0 +/*Focus default animation time [ms] (0: no animation)*/ +# define LV_PAGE_DEF_ANIM_TIME 400 +#endif + +/*Preload (dependencies: lv_arc, lv_anim)*/ +#define LV_USE_SPINNER 1 +#if LV_USE_SPINNER != 0 +# define LV_SPINNER_DEF_ARC_LENGTH 60 /*[deg]*/ +# define LV_SPINNER_DEF_SPIN_TIME 1000 /*[ms]*/ +# define LV_SPINNER_DEF_ANIM LV_SPINNER_TYPE_SPINNING_ARC +#endif + +/*Roller (dependencies: lv_ddlist)*/ +#define LV_USE_ROLLER 1 +#if LV_USE_ROLLER != 0 +/*Focus animation time [ms] (0: no animation)*/ +# define LV_ROLLER_DEF_ANIM_TIME 200 + +/*Number of extra "pages" when the roller is infinite*/ +# define LV_ROLLER_INF_PAGES 7 +#endif + +/*Slider (dependencies: lv_bar)*/ +#define LV_USE_SLIDER 1 + +/*Spinbox (dependencies: lv_ta)*/ +#define LV_USE_SPINBOX 1 + +/*Switch (dependencies: lv_slider)*/ +#define LV_USE_SWITCH 1 + +/*Text area (dependencies: lv_label, lv_page)*/ +#define LV_USE_TEXTAREA 1 +#if LV_USE_TEXTAREA != 0 +# define LV_TEXTAREA_DEF_CURSOR_BLINK_TIME 400 /*ms*/ +# define LV_TEXTAREA_DEF_PWD_SHOW_TIME 1500 /*ms*/ +#endif + +/*Table (dependencies: lv_label)*/ +#define LV_USE_TABLE 1 +#if LV_USE_TABLE +# define LV_TABLE_COL_MAX 12 +#endif + +/*Tab (dependencies: lv_page, lv_btnm)*/ +#define LV_USE_TABVIEW 1 +# if LV_USE_TABVIEW != 0 +/*Time of slide animation [ms] (0: no animation)*/ +# define LV_TABVIEW_DEF_ANIM_TIME 300 +#endif + +/*Tileview (dependencies: lv_page) */ +#define LV_USE_TILEVIEW 1 +#if LV_USE_TILEVIEW +/*Time of slide animation [ms] (0: no animation)*/ +# define LV_TILEVIEW_DEF_ANIM_TIME 300 +#endif + +/*Window (dependencies: lv_cont, lv_btn, lv_label, lv_img, lv_page)*/ +#define LV_USE_WIN 1 + +/*================== + * Non-user section + *==================*/ + +#if defined(_MSC_VER) && !defined(_CRT_SECURE_NO_WARNINGS) /* Disable warnings for Visual Studio*/ +# define _CRT_SECURE_NO_WARNINGS +#endif + +/*--END OF LV_CONF_H--*/ + +#endif /*LV_CONF_H*/ + +#endif /*End of "Content enable"*/ diff --git a/software/firmware/oracle_same54n19a/config/pc_board.h b/software/firmware/oracle_same54n19a/config/pc_board.h new file mode 100644 index 00000000..bd4941e8 --- /dev/null +++ b/software/firmware/oracle_same54n19a/config/pc_board.h @@ -0,0 +1,103 @@ +/* + * pc_board.h + * + * Created: 5/3/2020 6:47:40 PM + * Author: Penguin + */ +#ifndef _PC_BOARD_H_ +#define _PC_BOARD_H_ + +#include + +// SAME54 has 14 pin functions +#define GPIO_PIN_FUNCTION_A 0 +#define GPIO_PIN_FUNCTION_B 1 +#define GPIO_PIN_FUNCTION_C 2 +#define GPIO_PIN_FUNCTION_D 3 +#define GPIO_PIN_FUNCTION_E 4 +#define GPIO_PIN_FUNCTION_F 5 +#define GPIO_PIN_FUNCTION_G 6 +#define GPIO_PIN_FUNCTION_H 7 +#define GPIO_PIN_FUNCTION_I 8 +#define GPIO_PIN_FUNCTION_J 9 +#define GPIO_PIN_FUNCTION_K 10 +#define GPIO_PIN_FUNCTION_L 11 +#define GPIO_PIN_FUNCTION_M 12 +#define GPIO_PIN_FUNCTION_N 13 + +// I2C Config +#define I2C_MASTER_SDA (GPIO_PORTA, 22) +#define I2C_MASTER_SDA_MUX PINMUX_PA22C_SERCOM3_PAD0 + +#define I2C_MASTER_SCL (GPIO_PORTA, 23) +#define I2C_MASTER_SCL_MUX PINMUX_PA23C_SERCOM3_PAD1 +#define I2C_MASTER_SERCOM SERCOM3 + +// Debug USART Config +#define USART_DEBUG_RX GPIO(GPIO_PORTB, 24) +#define USART_DEBUG_RX_MUX PINMUX_PB24D_SERCOM2_PAD1 + +#define USART_DEBUG_TX GPIO(GPIO_PORTB, 25) +#define USART_DEBUG_TX_MUX PINMUX_PB25D_SERCOM2_PAD0 + +#define USART_DEBUG_SERCOM SERCOM2 + +//SSD1963 HW Config +#define SSD1963_TFT_DATA_MASK (0x1C03C3F7) +#define SSD1963_TFT_DATA_GROUP ((PortGroup*)&PORT->Group[1]) +#define SSD1963_TFT_DATA_PORT GPIO_PORTB +#define SSD1963_TFT_DATA_PORT_GROUP (&PORT->Group[1]) +#define SSD1963_TFT_DATA_DIRECTION GPIO_DIRECTION_OUT +#define SSD1963_TFT_DATA_PULL_MODE GPIO_PULL_OFF +#define SSD1963_TFT_DATA_FUNCTION GPIO_PIN_FUNCTION_OFF + +#define SSD1963_TFT_nRST_PIN PIN_PA04 +#define SSD1963_TFT_nRST_PORT_PIN 4 +#define SSD1963_TFT_nRST_PORT GPIO_PORTA +#define SSD1963_TFT_nRST_FUNCTION GPIO_PIN_FUNCTION_OFF +#define SSD1963_TFT_nRST_DIRECTION GPIO_DIRECTION_OUT +#define SSD1963_TFT_nRST_PULL_MODE GPIO_PULL_UP +#define SSD1963_TFT_nRST GPIO(SSD1963_TFT_nRST_PORT, SSD1963_TFT_nRST_PORT_PIN) + +#define SSD1963_TFT_RSDC_PIN PIN_PA05 +#define SSD1963_TFT_RSDC_PORT_PIN 5 +#define SSD1963_TFT_RSDC_PORT GPIO_PORTA +#define SSD1963_TFT_RSDC_FUNCTION GPIO_PIN_FUNCTION_OFF +#define SSD1963_TFT_RSDC_DIRECTION GPIO_DIRECTION_OUT +#define SSD1963_TFT_RSDC_PULL_MODE GPIO_PULL_DOWN +#define SSD1963_TFT_RSDC GPIO(SSD1963_TFT_RSDC_PORT, SSD1963_TFT_RSDC_PORT_PIN) + +#define SSD1963_TFT_CS_PIN PIN_PA06 +#define SSD1963_TFT_CS_PORT_PIN 6 +#define SSD1963_TFT_CS_PORT GPIO_PORTA +#define SSD1963_TFT_CS_FUNCTION GPIO_PIN_FUNCTION_OFF +#define SSD1963_TFT_CS_DIRECTION GPIO_DIRECTION_OUT +#define SSD1963_TFT_CS_PULL_MODE GPIO_PULL_DOWN +#define SSD1963_TFT_CS GPIO(SSD1963_TFT_CS_PORT, SSD1963_TFT_CS_PORT_PIN) + +#define SSD1963_TFT_WR_PIN PIN_PA07 +#define SSD1963_TFT_WR_PORT_PIN 7 +#define SSD1963_TFT_WR_PORT GPIO_PORTA +#define SSD1963_TFT_WR_FUNCTION GPIO_PIN_FUNCTION_OFF +#define SSD1963_TFT_WR_DIRECTION GPIO_DIRECTION_OUT +#define SSD1963_TFT_WR_PULL_MODE GPIO_PULL_DOWN +#define SSD1963_TFT_WR GPIO(SSD1963_TFT_WR_PORT, SSD1963_TFT_WR_PORT_PIN) + +#define SSD1963_TFT_RD_PIN PIN_PA03 +#define SSD1963_TFT_RD_PORT_PIN 3 +#define SSD1963_TFT_RD_PORT GPIO_PORTA +#define SSD1963_TFT_RD_FUNCTION GPIO_PIN_FUNCTION_OFF +#define SSD1963_TFT_RD_DIRECTION GPIO_DIRECTION_OUT +#define SSD1963_TFT_RD_PULL_MODE GPIO_PULL_DOWN +#define SSD1963_TFT_RD GPIO(SSD1963_TFT_RD_PORT, SSD1963_TFT_RD_PORT_PIN) + +#define SSD1963_TFT_TE_PIN PIN_PD08 +#define SSD1963_TFT_TE_PORT_PIN 8 +#define SSD1963_TFT_TE_PORT GPIO_PORTD +#define SSD1963_TFT_TE_FUNCTION GPIO_PIN_FUNCTION_OFF +#define SSD1963_TFT_TE_DIRECTION GPIO_DIRECTION_IN +#define SSD1963_TFT_TE_PULL_MODE GPIO_PULL_DOWN +#define SSD1963_TFT_TE GPIO(SSD1963_TFT_TE_PORT, SSD1963_TFT_TE_PORT_PIN) + + +#endif diff --git a/software/firmware/oracle_same54n19a/config/pc_master.h b/software/firmware/oracle_same54n19a/config/pc_master.h new file mode 100644 index 00000000..ad9832e4 --- /dev/null +++ b/software/firmware/oracle_same54n19a/config/pc_master.h @@ -0,0 +1,14 @@ +/* + * pc_master.h + * + * Created: 5/3/2020 6:47:27 PM + * Author: Penguin + */ +#ifndef _PC_MASTER_H_ +#define _PC_MASTER_H_ + +// usart debug settings +#define DEBUG_MAX_BUFFER_SIZE (128) + + +#endif \ No newline at end of file diff --git a/software/firmware/oracle_same54n19a/config/peripheral_clk_config.h b/software/firmware/oracle_same54n19a/config/peripheral_clk_config.h new file mode 100644 index 00000000..c8359e70 --- /dev/null +++ b/software/firmware/oracle_same54n19a/config/peripheral_clk_config.h @@ -0,0 +1,257 @@ +/* Auto-generated config file peripheral_clk_config.h */ +#ifndef PERIPHERAL_CLK_CONFIG_H +#define PERIPHERAL_CLK_CONFIG_H + +// <<< Use Configuration Wizard in Context Menu >>> + +// EIC Clock Source +// eic_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for EIC. +#ifndef CONF_GCLK_EIC_SRC +#define CONF_GCLK_EIC_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_EIC_FREQUENCY + * \brief EIC's Clock frequency + */ +#ifndef CONF_GCLK_EIC_FREQUENCY +#define CONF_GCLK_EIC_FREQUENCY 119997440 +#endif + +/** + * \def CONF_CPU_FREQUENCY + * \brief CPU's Clock frequency + */ +#ifndef CONF_CPU_FREQUENCY +#define CONF_CPU_FREQUENCY 119997440 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM0_CORE_SRC +#define CONF_GCLK_SERCOM0_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM0_SLOW_SRC +#define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM0_CORE_FREQUENCY + * \brief SERCOM0's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY +#define CONF_GCLK_SERCOM0_CORE_FREQUENCY 119997440 +#endif + +/** + * \def CONF_GCLK_SERCOM0_SLOW_FREQUENCY + * \brief SERCOM0's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM0_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 32768 +#endif + +// Core Clock Source +// core_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for CORE. +#ifndef CONF_GCLK_SERCOM3_CORE_SRC +#define CONF_GCLK_SERCOM3_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +// Slow Clock Source +// slow_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the slow clock source. +#ifndef CONF_GCLK_SERCOM3_SLOW_SRC +#define CONF_GCLK_SERCOM3_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val +#endif + +/** + * \def CONF_GCLK_SERCOM3_CORE_FREQUENCY + * \brief SERCOM3's Core Clock frequency + */ +#ifndef CONF_GCLK_SERCOM3_CORE_FREQUENCY +#define CONF_GCLK_SERCOM3_CORE_FREQUENCY 119997440 +#endif + +/** + * \def CONF_GCLK_SERCOM3_SLOW_FREQUENCY + * \brief SERCOM3's Slow Clock frequency + */ +#ifndef CONF_GCLK_SERCOM3_SLOW_FREQUENCY +#define CONF_GCLK_SERCOM3_SLOW_FREQUENCY 32768 +#endif + +// TC Clock Source +// tc_gclk_selection + +// Generic clock generator 0 + +// Generic clock generator 1 + +// Generic clock generator 2 + +// Generic clock generator 3 + +// Generic clock generator 4 + +// Generic clock generator 5 + +// Generic clock generator 6 + +// Generic clock generator 7 + +// Generic clock generator 8 + +// Generic clock generator 9 + +// Generic clock generator 10 + +// Generic clock generator 11 + +// Select the clock source for TC. +#ifndef CONF_GCLK_TC0_SRC +#define CONF_GCLK_TC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val +#endif + +/** + * \def CONF_GCLK_TC0_FREQUENCY + * \brief TC0's Clock frequency + */ +#ifndef CONF_GCLK_TC0_FREQUENCY +#define CONF_GCLK_TC0_FREQUENCY 119997440 +#endif + +// <<< end of configuration section >>> + +#endif // PERIPHERAL_CLK_CONFIG_H diff --git a/software/firmware/oracle_same54n19a/driver_init.c b/software/firmware/oracle_same54n19a/driver_init.c new file mode 100644 index 00000000..fd77cdac --- /dev/null +++ b/software/firmware/oracle_same54n19a/driver_init.c @@ -0,0 +1,134 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ + +#include "driver_init.h" +#include +#include +#include + +/*! The buffer size for USART */ +#define USART_0_BUFFER_SIZE 16 + +struct usart_async_descriptor USART_0; +struct timer_descriptor TIMER_0; + +static uint8_t USART_0_buffer[USART_0_BUFFER_SIZE]; + +struct i2c_m_sync_desc I2C_0; + +void EXTERNAL_IRQ_0_init(void) +{ + hri_gclk_write_PCHCTRL_reg(GCLK, EIC_GCLK_ID, CONF_GCLK_EIC_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + hri_mclk_set_APBAMASK_EIC_bit(MCLK); + + ext_irq_init(); +} + +/** + * \brief USART Clock initialization function + * + * Enables register interface and peripheral clock + */ +void USART_0_CLOCK_init() +{ + + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_CORE, CONF_GCLK_SERCOM0_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_SLOW, CONF_GCLK_SERCOM0_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + + hri_mclk_set_APBAMASK_SERCOM0_bit(MCLK); +} + +/** + * \brief USART pinmux initialization function + * + * Set each required pin to USART functionality + */ +void USART_0_PORT_init() +{ + + gpio_set_pin_function(PA04, PINMUX_PA04D_SERCOM0_PAD0); + + gpio_set_pin_function(PA05, PINMUX_PA05D_SERCOM0_PAD1); +} + +/** + * \brief USART initialization function + * + * Enables USART peripheral, clocks and initializes USART driver + */ +void USART_0_init(void) +{ + USART_0_CLOCK_init(); + usart_async_init(&USART_0, SERCOM0, USART_0_buffer, USART_0_BUFFER_SIZE, (void *)NULL); + USART_0_PORT_init(); +} + +void I2C_0_PORT_init(void) +{ + + gpio_set_pin_pull_mode(PA22, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA22, PINMUX_PA22C_SERCOM3_PAD0); + + gpio_set_pin_pull_mode(PA23, + // Pull configuration + // pad_pull_config + // Off + // Pull-up + // Pull-down + GPIO_PULL_OFF); + + gpio_set_pin_function(PA23, PINMUX_PA23C_SERCOM3_PAD1); +} + +void I2C_0_CLOCK_init(void) +{ + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM3_GCLK_ID_CORE, CONF_GCLK_SERCOM3_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM3_GCLK_ID_SLOW, CONF_GCLK_SERCOM3_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + + hri_mclk_set_APBBMASK_SERCOM3_bit(MCLK); +} + +void I2C_0_init(void) +{ + I2C_0_CLOCK_init(); + i2c_m_sync_init(&I2C_0, SERCOM3); + I2C_0_PORT_init(); +} + +/** + * \brief Timer initialization function + * + * Enables Timer peripheral, clocks and initializes Timer driver + */ +static void TIMER_0_init(void) +{ + hri_mclk_set_APBAMASK_TC0_bit(MCLK); + hri_gclk_write_PCHCTRL_reg(GCLK, TC0_GCLK_ID, CONF_GCLK_TC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + + timer_init(&TIMER_0, TC0, _tc_get_timer()); +} + +void system_init(void) +{ + init_mcu(); + + EXTERNAL_IRQ_0_init(); + + USART_0_init(); + + I2C_0_init(); + + TIMER_0_init(); +} diff --git a/software/firmware/oracle_same54n19a/driver_init.h b/software/firmware/oracle_same54n19a/driver_init.h new file mode 100644 index 00000000..16d4f9f8 --- /dev/null +++ b/software/firmware/oracle_same54n19a/driver_init.h @@ -0,0 +1,54 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ +#ifndef DRIVER_INIT_INCLUDED +#define DRIVER_INIT_INCLUDED + +#include "atmel_start_pins.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include +#include +#include + +extern struct usart_async_descriptor USART_0; + +extern struct i2c_m_sync_desc I2C_0; +extern struct timer_descriptor TIMER_0; + +void USART_0_PORT_init(void); +void USART_0_CLOCK_init(void); +void USART_0_init(void); + +void I2C_0_CLOCK_init(void); +void I2C_0_init(void); +void I2C_0_PORT_init(void); + +/** + * \brief Perform system initialization, initialize pins and clocks for + * peripherals + */ +void system_init(void); + +#ifdef __cplusplus +} +#endif +#endif // DRIVER_INIT_INCLUDED diff --git a/software/firmware/oracle_same54n19a/examples/driver_examples.c b/software/firmware/oracle_same54n19a/examples/driver_examples.c new file mode 100644 index 00000000..7cf9ca84 --- /dev/null +++ b/software/firmware/oracle_same54n19a/examples/driver_examples.c @@ -0,0 +1,84 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ + +#include "driver_examples.h" +#include "driver_init.h" +#include "utils.h" + +/** + * Example of using EXTERNAL_IRQ_0 + */ +void EXTERNAL_IRQ_0_example(void) +{ +} + +/** + * Example of using USART_0 to write "Hello World" using the IO abstraction. + * + * Since the driver is asynchronous we need to use statically allocated memory for string + * because driver initiates transfer and then returns before the transmission is completed. + * + * Once transfer has been completed the tx_cb function will be called. + */ + +static uint8_t example_USART_0[12] = "Hello World!"; + +static void tx_cb_USART_0(const struct usart_async_descriptor *const io_descr) +{ + /* Transfer completed */ +} + +void USART_0_example(void) +{ + struct io_descriptor *io; + + usart_async_register_callback(&USART_0, USART_ASYNC_TXC_CB, tx_cb_USART_0); + /*usart_async_register_callback(&USART_0, USART_ASYNC_RXC_CB, rx_cb); + usart_async_register_callback(&USART_0, USART_ASYNC_ERROR_CB, err_cb);*/ + usart_async_get_io_descriptor(&USART_0, &io); + usart_async_enable(&USART_0); + + io_write(io, example_USART_0, 12); +} + +void I2C_0_example(void) +{ + struct io_descriptor *I2C_0_io; + + i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_0_io); + i2c_m_sync_enable(&I2C_0); + i2c_m_sync_set_slaveaddr(&I2C_0, 0x12, I2C_M_SEVEN); + io_write(I2C_0_io, (uint8_t *)"Hello World!", 12); +} + +static struct timer_task TIMER_0_task1, TIMER_0_task2; + +/** + * Example of using TIMER_0. + */ +static void TIMER_0_task1_cb(const struct timer_task *const timer_task) +{ +} + +static void TIMER_0_task2_cb(const struct timer_task *const timer_task) +{ +} + +void TIMER_0_example(void) +{ + TIMER_0_task1.interval = 100; + TIMER_0_task1.cb = TIMER_0_task1_cb; + TIMER_0_task1.mode = TIMER_TASK_REPEAT; + TIMER_0_task2.interval = 200; + TIMER_0_task2.cb = TIMER_0_task2_cb; + TIMER_0_task2.mode = TIMER_TASK_REPEAT; + + timer_add_task(&TIMER_0, &TIMER_0_task1); + timer_add_task(&TIMER_0, &TIMER_0_task2); + timer_start(&TIMER_0); +} diff --git a/software/firmware/oracle_same54n19a/examples/driver_examples.h b/software/firmware/oracle_same54n19a/examples/driver_examples.h new file mode 100644 index 00000000..8e0cea14 --- /dev/null +++ b/software/firmware/oracle_same54n19a/examples/driver_examples.h @@ -0,0 +1,26 @@ +/* + * Code generated from Atmel Start. + * + * This file will be overwritten when reconfiguring your Atmel Start project. + * Please copy examples or other code you want to keep to a separate file + * to avoid losing it when reconfiguring. + */ +#ifndef DRIVER_EXAMPLES_H_INCLUDED +#define DRIVER_EXAMPLES_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +void EXTERNAL_IRQ_0_example(void); + +void USART_0_example(void); + +void I2C_0_example(void); + +void TIMER_0_example(void); + +#ifdef __cplusplus +} +#endif +#endif // DRIVER_EXAMPLES_H_INCLUDED diff --git a/software/firmware/oracle_same54n19a/gcc/.gdb_history b/software/firmware/oracle_same54n19a/gcc/.gdb_history new file mode 100644 index 00000000..c0209fa7 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/.gdb_history @@ -0,0 +1,31 @@ +tar ext /dev/ttyBmpGdb +tar ext /dev/ttyBmpGdb +mon s +mon s +mon s +mon s +mon s +mon s +mon s +mon s +mon s +att 1 +load +r +n +del +r +c +r +b main +r +s +s +n +n +r +s +s +n +s +q diff --git a/software/firmware/oracle_same54n19a/gcc/AtmelStart.bin b/software/firmware/oracle_same54n19a/gcc/AtmelStart.bin new file mode 100644 index 00000000..8c988f11 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+:10471400F801020010000250000000000000000038 +:1047240000000000A4C700201000000094C700206F +:104734001000000059FC00008FFC0000A1FD0000E7 +:10474400FDFD0000D5FD000061FD0000B9FE000084 +:0447540025FE00003E +:00000001FF diff --git a/software/firmware/oracle_same54n19a/gcc/AtmelStart.lss b/software/firmware/oracle_same54n19a/gcc/AtmelStart.lss new file mode 100644 index 00000000..3c761c09 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/AtmelStart.lss @@ -0,0 +1,54816 @@ + +AtmelStart.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .text 000246dc 00000000 00000000 00010000 2**3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 .ARM.exidx 00000008 000246dc 000246dc 000346dc 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 2 .relocate 00000074 20000000 000246e4 00040000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 3 .bkupram 00000000 47000000 47000000 00040074 2**0 + CONTENTS + 4 .qspi 00000000 04000000 04000000 00040074 2**0 + CONTENTS + 5 .bss 0000c788 20000078 00024760 00040078 2**3 + ALLOC + 6 .stack 0000c000 2000c800 00030ee8 00040078 2**0 + ALLOC + 7 .ARM.attributes 0000002e 00000000 00000000 00040074 2**0 + CONTENTS, READONLY + 8 .comment 00000064 00000000 00000000 000400a2 2**0 + CONTENTS, READONLY + 9 .debug_info 000761b4 00000000 00000000 00040106 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 10 .debug_abbrev 0000d478 00000000 00000000 000b62ba 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 11 .debug_loclists 00029747 00000000 00000000 000c3732 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 12 .debug_aranges 00002158 00000000 00000000 000ece80 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 13 .debug_rnglists 0000488d 00000000 00000000 000eefd8 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 14 .debug_macro 0003fc44 00000000 00000000 000f3865 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 15 .debug_line 00055a74 00000000 00000000 001334a9 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 16 .debug_str 00128539 00000000 00000000 00188f1d 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 17 .debug_frame 00006948 00000000 00000000 002b1458 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_line_str 00000075 00000000 00000000 002b7da0 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +Disassembly of section .text: + +00000000 : + +/** + * \brief I/O read interface + */ +int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) +{ + 0: 00 88 01 20 59 09 00 00 55 09 00 00 55 09 00 00 ... Y...U...U... + ASSERT(io_descr && buf); + 10: 55 09 00 00 55 09 00 00 55 09 00 00 00 00 00 00 U...U...U....... + ... + return io_descr->read(io_descr, buf, length); + 2c: 55 09 00 00 55 09 00 00 00 00 00 00 55 09 00 00 U...U.......U... + + descr->flags |= TIMER_FLAG_QUEUE_IS_TAKEN; + if (!is_list_element(&descr->tasks, task)) { + descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; + ASSERT(false); + return ERR_NOT_FOUND; + 3c: 55 09 00 00 55 09 00 00 55 09 00 00 55 09 00 00 U...U...U...U... + } + list_delete_element(&descr->tasks, task); + + descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; + 4c: 55 09 00 00 55 09 00 00 55 09 00 00 55 09 00 00 U...U...U...U... + if (descr->flags & TIMER_FLAG_INTERRUPT_TRIGERRED) { + CRITICAL_SECTION_ENTER() + 5c: 55 09 00 00 55 09 00 00 55 09 00 00 55 09 00 00 U...U...U...U... + descr->flags &= ~TIMER_FLAG_INTERRUPT_TRIGERRED; + _timer_set_irq(&descr->device); + 6c: 55 09 00 00 55 09 00 00 55 09 00 00 55 09 00 00 U...U...U...U... + CRITICAL_SECTION_LEAVE() + } + + return ERR_NONE; + 7c: 55 09 00 00 55 09 00 00 55 09 00 00 55 09 00 00 U...U...U...U... + 8c: 55 09 00 00 55 09 00 00 55 09 00 00 55 09 00 00 U...U...U...U... + } else { + /* error baudrate */ + return ERR_INVALID_ARG; + } + + return ERR_NONE; + 9c: 55 09 00 00 55 09 00 00 55 09 00 00 55 09 00 00 U...U...U...U... + +static inline void hri_sercomi2cm_write_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + ac: 55 09 00 00 55 09 00 00 55 09 00 00 55 09 00 00 U...U...U...U... + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + bc: 55 09 00 00 55 09 00 00 55 09 00 00 55 09 00 00 U...U...U...U... + cc: 55 09 00 00 55 09 00 00 55 09 00 00 55 09 00 00 U...U...U...U... + dc: 55 09 00 00 55 09 00 00 55 09 00 00 00 00 00 00 U...U...U....... + ... + f4: cd 05 00 00 b1 08 00 00 1d 09 00 00 25 09 00 00 ............%... + / (2 * baudrate)); + 104: 2d 09 00 00 55 09 00 00 55 09 00 00 55 09 00 00 -...U...U...U... + tmp &= ~SERCOM_I2CM_BAUD_BAUD_Msk; + tmp |= SERCOM_I2CM_BAUD_BAUD(data); + 114: 55 09 00 00 55 09 00 00 55 09 00 00 55 09 00 00 U...U...U...U... + tmp = (clkrate - 2 * baudrate) / (2 * baudrate); + 124: 55 09 00 00 55 09 00 00 55 09 00 00 55 09 00 00 U...U...U...U... +static inline void hri_sercomi2cm_write_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_HSBAUD_Msk; + 134: 55 09 00 00 55 09 00 00 55 09 00 00 55 09 00 00 U...U...U...U... + return ERR_DENIED; + 144: 55 09 00 00 55 09 00 00 55 09 00 00 55 09 00 00 U...U...U...U... + return ERR_INVALID_ARG; + 154: 55 09 00 00 55 09 00 00 55 09 00 00 55 09 00 00 U...U...U...U... + 164: 55 09 00 00 55 09 00 00 55 09 00 00 55 09 00 00 U...U...U...U... + 174: 55 09 00 00 55 09 00 00 55 09 00 00 55 09 00 00 U...U...U...U... + ver_en = true; + } + } + + /*If a move is greater then LV_DRAG_LIMIT then begin the drag*/ + if((hor_en && LV_MATH_ABS(proc->types.pointer.drag_sum.x) >= indev_act->driver.drag_limit) || + 184: 55 09 00 00 55 09 00 00 55 09 00 00 55 09 00 00 U...U...U...U... + 194: 55 09 00 00 55 09 00 00 55 09 00 00 55 09 00 00 U...U...U...U... + (ver_en && LV_MATH_ABS(proc->types.pointer.drag_sum.y) >= indev_act->driver.drag_limit)) { + 1a4: 55 09 00 00 55 09 00 00 55 09 00 00 55 09 00 00 U...U...U...U... + drag_just_started = true; + } + } + + /*If the drag limit is exceeded handle the dragging*/ + if(proc->types.pointer.drag_limit_out != 0) { + 1b4: 55 09 00 00 55 09 00 00 55 09 00 00 55 09 00 00 U...U...U...U... + /*Set new position if the vector is not zero*/ + if(proc->types.pointer.vect.x != 0 || proc->types.pointer.vect.y != 0) { + 1c4: 55 09 00 00 55 09 00 00 55 09 00 00 55 09 00 00 U...U...U...U... + + lv_coord_t prev_x = drag_obj->coords.x1; + lv_coord_t prev_y = drag_obj->coords.y1; + 1d4: 55 09 00 00 55 09 00 00 55 09 00 00 55 09 00 00 U...U...U...U... + lv_coord_t prev_par_w = lv_obj_get_width(lv_obj_get_parent(drag_obj)); + lv_coord_t prev_par_h = lv_obj_get_height(lv_obj_get_parent(drag_obj)); + 1e4: 55 09 00 00 55 09 00 00 2d 0f 00 00 55 09 00 00 U...U...-...U... + + /*Get the coordinates of the object and modify them*/ + lv_coord_t act_x = lv_obj_get_x(drag_obj); + lv_coord_t act_y = lv_obj_get_y(drag_obj); + 1f4: 55 09 00 00 55 09 00 00 55 09 00 00 55 09 00 00 U...U...U...U... + + if(allowed_dirs == LV_DRAG_DIR_BOTH) { + if(drag_just_started) { + proc->types.pointer.drag_dir = LV_DRAG_DIR_BOTH; + 204: 55 09 00 00 55 09 00 00 55 09 00 00 55 09 00 00 U...U...U...U... + act_x += proc->types.pointer.drag_sum.x; + 214: 55 09 00 00 55 09 00 00 55 09 00 00 55 09 00 00 U...U...U...U... + /*Move the object*/ + if(allowed_dirs == LV_DRAG_DIR_HOR || + allowed_dirs == LV_DRAG_DIR_BOTH || + (allowed_dirs == LV_DRAG_DIR_ONE && + LV_MATH_ABS(proc->types.pointer.drag_sum.x) > LV_MATH_ABS(proc->types.pointer.drag_sum.y))) { + act_x += proc->types.pointer.vect.x; + 224: 55 09 00 00 55 09 00 00 55 09 00 00 55 09 00 00 U...U...U...U... + 234: 55 09 00 00 55 09 00 00 55 09 00 00 55 09 00 00 U...U...U...U... + 244: 55 09 00 00 55 09 00 00 55 09 00 00 55 09 00 00 U...U...U...U... + 254: 55 09 00 00 55 09 00 00 55 09 00 00 55 09 00 00 U...U...U...U... + +00000264 : + 264: 4803 ldr r0, [pc, #12] ; (274 ) + 266: 4b04 ldr r3, [pc, #16] ; (278 ) + 268: 4283 cmp r3, r0 + 26a: d002 beq.n 272 + 26c: 4b03 ldr r3, [pc, #12] ; (27c ) + 26e: b103 cbz r3, 272 + proc->types.pointer.last_point.x = proc->types.pointer.act_point.x; + 270: 4718 bx r3 + if(proc->types.pointer.act_obj != NULL) { + 272: 4770 bx lr + 274: 000246e4 .word 0x000246e4 + proc->types.pointer.last_obj = indev_obj_act; + 278: 000246e4 .word 0x000246e4 + if(indev_obj_act != NULL) { + 27c: 00000000 .word 0x00000000 + +00000280 : + 280: 4805 ldr r0, [pc, #20] ; (298 ) + proc->pr_timestamp = lv_tick_get(); + 282: 4b06 ldr r3, [pc, #24] ; (29c ) + i = lv_obj_get_parent(i); + 284: 1a1b subs r3, r3, r0 + proc->pr_timestamp = lv_tick_get(); + 286: 0fd9 lsrs r1, r3, #31 + proc->types.pointer.drag_limit_out = 0; + 288: eb01 01a3 add.w r1, r1, r3, asr #2 + proc->long_pr_sent = 0; + 28c: 1049 asrs r1, r1, #1 + 28e: d002 beq.n 296 + proc->pr_timestamp = lv_tick_get(); + 290: 4b03 ldr r3, [pc, #12] ; (2a0 ) + proc->types.pointer.gesture_sum.x = 0; + 292: b103 cbz r3, 296 + proc->types.pointer.drag_limit_out = 0; + 294: 4718 bx r3 + 296: 4770 bx lr + proc->types.pointer.drag_sum.x = 0; + 298: 000246e4 .word 0x000246e4 + proc->long_pr_sent = 0; + 29c: 000246e4 .word 0x000246e4 + proc->types.pointer.drag_limit_out = 0; + 2a0: 00000000 .word 0x00000000 + +000002a4 <__do_global_dtors_aux>: + lv_obj_t * i = indev_obj_act; + 2a4: b510 push {r4, lr} + proc->long_pr_sent = 0; + 2a6: 4c06 ldr r4, [pc, #24] ; (2c0 <__do_global_dtors_aux+0x1c>) + 2a8: 7823 ldrb r3, [r4, #0] + proc->types.pointer.gesture_sum.x = 0; + 2aa: b943 cbnz r3, 2be <__do_global_dtors_aux+0x1a> + proc->types.pointer.gesture_sum.y = 0; + 2ac: f7ff ffda bl 264 + proc->types.pointer.drag_limit_out = 0; + 2b0: 4b04 ldr r3, [pc, #16] ; (2c4 <__do_global_dtors_aux+0x20>) + while(i != NULL) { + 2b2: b113 cbz r3, 2ba <__do_global_dtors_aux+0x16> + 2b4: 4804 ldr r0, [pc, #16] ; (2c8 <__do_global_dtors_aux+0x24>) + if(last_top != NULL) { + 2b6: f3af 8000 nop.w + lv_obj_move_foreground(last_top); + 2ba: 2301 movs r3, #1 + 2bc: 7023 strb r3, [r4, #0] + indev_obj_act->signal_cb(indev_obj_act, LV_SIGNAL_PRESSED, indev_act); + 2be: bd10 pop {r4, pc} + 2c0: 20000078 .word 0x20000078 + if(indev_reset_check(proc)) return; + 2c4: 00000000 .word 0x00000000 + indev_obj_act->signal_cb(indev_obj_act, LV_SIGNAL_PRESSED, indev_act); + 2c8: 000246e4 .word 0x000246e4 + +000002cc : + if(indev_reset_check(proc)) return; + 2cc: b508 push {r3, lr} + 2ce: 4b04 ldr r3, [pc, #16] ; (2e0 ) + 2d0: b11b cbz r3, 2da + 2d2: 4904 ldr r1, [pc, #16] ; (2e4 ) + lv_event_send(indev_obj_act, LV_EVENT_PRESSED, NULL); + 2d4: 4804 ldr r0, [pc, #16] ; (2e8 ) + 2d6: f3af 8000 nop.w + 2da: e8bd 4008 ldmia.w sp!, {r3, lr} + if(indev_reset_check(proc)) return; + 2de: e7cf b.n 280 + 2e0: 00000000 .word 0x00000000 + 2e4: 2000007c .word 0x2000007c + if(indev_act->proc.wait_until_release) return; + 2e8: 000246e4 .word 0x000246e4 + +000002ec : +{ + 2ec: b570 push {r4, r5, r6, lr} + 2ee: 460d mov r5, r1 + 2f0: 4616 mov r6, r2 + ASSERT(io_descr && buf); + 2f2: 4604 mov r4, r0 + 2f4: b110 cbz r0, 2fc + 2f6: 1e08 subs r0, r1, #0 + 2f8: bf18 it ne + 2fa: 2001 movne r0, #1 + 2fc: 4905 ldr r1, [pc, #20] ; (314 ) + 2fe: 4b06 ldr r3, [pc, #24] ; (318 ) + 300: 2234 movs r2, #52 ; 0x34 + 302: 4798 blx r3 + return io_descr->write(io_descr, buf, length); + 304: 6823 ldr r3, [r4, #0] + 306: 4632 mov r2, r6 + 308: 4629 mov r1, r5 + 30a: 4620 mov r0, r4 +} + 30c: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + return io_descr->write(io_descr, buf, length); + 310: 4718 bx r3 + 312: bf00 nop + 314: 00016348 .word 0x00016348 + 318: 00000655 .word 0x00000655 + +0000031c <_irq_set>: + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 31c: 0943 lsrs r3, r0, #5 + 31e: 4904 ldr r1, [pc, #16] ; (330 <_irq_set+0x14>) + 320: f000 001f and.w r0, r0, #31 + 324: 2201 movs r2, #1 + 326: 3340 adds r3, #64 ; 0x40 + 328: 4082 lsls r2, r0 + 32a: f841 2023 str.w r2, [r1, r3, lsl #2] + * \brief Set the given IRQ + */ +void _irq_set(uint8_t n) +{ + NVIC_SetPendingIRQ((IRQn_Type)n); +} + 32e: 4770 bx lr + 330: e000e100 .word 0xe000e100 + +00000334 <_get_cycles_for_us>: + */ +static inline uint32_t _get_cycles_for_us_internal(const uint16_t us, const uint32_t freq, const uint8_t power) +{ + switch (power) { + case 9: + return (us * (freq / 1000000) + 2) / 3; + 334: 2377 movs r3, #119 ; 0x77 + 336: 4358 muls r0, r3 + 338: 3002 adds r0, #2 + * \brief Retrieve the amount of cycles to delay for the given amount of us + */ +uint32_t _get_cycles_for_us(const uint16_t us) +{ + return _get_cycles_for_us_internal(us, CONF_CPU_FREQUENCY, CPU_FREQ_POWER); +} + 33a: 2303 movs r3, #3 + 33c: fbb0 f0f3 udiv r0, r0, r3 + 340: 4770 bx lr + +00000342 <_get_cycles_for_ms>: + */ +static inline uint32_t _get_cycles_for_ms_internal(const uint16_t ms, const uint32_t freq, const uint8_t power) +{ + switch (power) { + case 9: + return (ms * (freq / 1000000) + 2) / 3 * 1000; + 342: 2377 movs r3, #119 ; 0x77 + 344: 4358 muls r0, r3 + 346: 3002 adds r0, #2 + 348: 2303 movs r3, #3 + 34a: fbb0 f0f3 udiv r0, r0, r3 + * \brief Retrieve the amount of cycles to delay for the given amount of ms + */ +uint32_t _get_cycles_for_ms(const uint16_t ms) +{ + return _get_cycles_for_ms_internal(ms, CONF_CPU_FREQUENCY, CPU_FREQ_POWER); +} + 34e: f44f 737a mov.w r3, #1000 ; 0x3e8 + 352: 4358 muls r0, r3 + 354: 4770 bx lr + +00000356 <_delay_init>: + * \brief Initialize delay functionality + */ +void _delay_init(void *const hw) +{ + (void)hw; +} + 356: 4770 bx lr + +00000358 <_delay_cycles>: + __asm(".align 3 \n" + "__delay:\n" + "subs r1, r1, #1\n" + "bhi __delay\n"); +#elif defined __GNUC__ + __asm(".syntax unified\n" + 358: 3901 subs r1, #1 + 35a: d8fd bhi.n 358 <_delay_cycles> + __asm("__delay:\n" + "subs r1, r1, #1\n" + "bhi.n __delay\n"); +#endif +#endif +} + 35c: 4770 bx lr + if(indev_reset_check(proc)) return; + 35e: bf00 nop + +00000360 : + * \param[in] head The pointer to the head of timer task list + * \param[in] task The pointer to task to add + * \param[in] time Current timer time + */ +static void timer_add_timer_task(struct list_descriptor *list, struct timer_task *const new_task, const uint32_t time) +{ + 360: b5f0 push {r4, r5, r6, r7, lr} + * \return A pointer to the head of the given list or NULL if the list is + * empty + */ +static inline void *list_get_head(const struct list_descriptor *const list) +{ + return (void *)list->head; + 362: 6805 ldr r5, [r0, #0] + struct timer_task *it, *prev = NULL, *head = (struct timer_task *)list_get_head(list); + + if (!head) { + 364: b91d cbnz r5, 36e + list_insert_as_head(list, new_task); + 366: 4b0f ldr r3, [pc, #60] ; (3a4 ) + if (it == head) { + list_insert_as_head(list, new_task); + } else { + list_insert_after(prev, new_task); + } +} + 368: e8bd 40f0 ldmia.w sp!, {r4, r5, r6, r7, lr} + list_insert_after(prev, new_task); + 36c: 4718 bx r3 + if (time_left >= new_task->interval) + 36e: f8d1 c008 ldr.w ip, [r1, #8] + 372: 462c mov r4, r5 + struct timer_task *it, *prev = NULL, *head = (struct timer_task *)list_get_head(list); + 374: 2600 movs r6, #0 + time_left = it->interval - (0xFFFFFFFF - it->time_label) - time; + 376: f1c2 0e01 rsb lr, r2, #1 + time_left = it->interval - (time - it->time_label); + 37a: e9d4 3701 ldrd r3, r7, [r4, #4] + if (it->time_label <= time) { + 37e: 4293 cmp r3, r2 + time_left = it->interval - (time - it->time_label); + 380: bf95 itete ls + 382: 19db addls r3, r3, r7 + time_left = it->interval - (0xFFFFFFFF - it->time_label) - time; + 384: 4473 addhi r3, lr + time_left = it->interval - (time - it->time_label); + 386: 1a9b subls r3, r3, r2 + time_left = it->interval - (0xFFFFFFFF - it->time_label) - time; + 388: 19db addhi r3, r3, r7 + if (time_left >= new_task->interval) + 38a: 459c cmp ip, r3 + 38c: d907 bls.n 39e + * \return A pointer to the next list element or NULL if there is not next + * element + */ +static inline void *list_get_next_element(const void *const element) +{ + return element ? ((struct list_element *)element)->next : NULL; + 38e: 6823 ldr r3, [r4, #0] + for (it = head; it; it = (struct timer_task *)list_get_next_element(it)) { + 390: 4626 mov r6, r4 + 392: b913 cbnz r3, 39a + list_insert_after(prev, new_task); + 394: 4b04 ldr r3, [pc, #16] ; (3a8 ) + 396: 4630 mov r0, r6 + 398: e7e6 b.n 368 + 39a: 461c mov r4, r3 + 39c: e7ed b.n 37a + if (it == head) { + 39e: 42a5 cmp r5, r4 + 3a0: d0e1 beq.n 366 + 3a2: e7f7 b.n 394 + 3a4: 00000615 .word 0x00000615 + 3a8: 00000641 .word 0x00000641 + +000003ac : + +/** + * \internal Process interrupts + */ +static void timer_process_counted(struct _timer_device *device) +{ + 3ac: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + struct timer_descriptor *timer = CONTAINER_OF(device, struct timer_descriptor, device); + struct timer_task * it = (struct timer_task *)list_get_head(&timer->tasks); + uint32_t time = ++timer->time; + 3b0: e9d0 6504 ldrd r6, r5, [r0, #16] + + if ((timer->flags & TIMER_FLAG_QUEUE_IS_TAKEN) || (timer->flags & TIMER_FLAG_INTERRUPT_TRIGERRED)) { + 3b4: 7e03 ldrb r3, [r0, #24] + uint32_t time = ++timer->time; + 3b6: 3601 adds r6, #1 + if ((timer->flags & TIMER_FLAG_QUEUE_IS_TAKEN) || (timer->flags & TIMER_FLAG_INTERRUPT_TRIGERRED)) { + 3b8: 07da lsls r2, r3, #31 +{ + 3ba: 4604 mov r4, r0 + uint32_t time = ++timer->time; + 3bc: 6106 str r6, [r0, #16] + if ((timer->flags & TIMER_FLAG_QUEUE_IS_TAKEN) || (timer->flags & TIMER_FLAG_INTERRUPT_TRIGERRED)) { + 3be: d41f bmi.n 400 + 3c0: 7e03 ldrb r3, [r0, #24] + 3c2: 079b lsls r3, r3, #30 + 3c4: d41c bmi.n 400 + } + + while (it && ((time - it->time_label) >= it->interval)) { + struct timer_task *tmp = it; + + list_remove_head(&timer->tasks); + 3c6: f8df 8044 ldr.w r8, [pc, #68] ; 40c + if (TIMER_TASK_REPEAT == tmp->mode) { + tmp->time_label = time; + timer_add_timer_task(&timer->tasks, tmp, time); + 3ca: f8df 9044 ldr.w r9, [pc, #68] ; 410 + list_remove_head(&timer->tasks); + 3ce: f100 0714 add.w r7, r0, #20 + while (it && ((time - it->time_label) >= it->interval)) { + 3d2: b1cd cbz r5, 408 + 3d4: 686b ldr r3, [r5, #4] + 3d6: 68aa ldr r2, [r5, #8] + 3d8: 1af3 subs r3, r6, r3 + 3da: 4293 cmp r3, r2 + 3dc: d314 bcc.n 408 + list_remove_head(&timer->tasks); + 3de: 4638 mov r0, r7 + 3e0: 47c0 blx r8 + if (TIMER_TASK_REPEAT == tmp->mode) { + 3e2: 7c2b ldrb r3, [r5, #16] + 3e4: 2b01 cmp r3, #1 + 3e6: d104 bne.n 3f2 + tmp->time_label = time; + 3e8: 606e str r6, [r5, #4] + timer_add_timer_task(&timer->tasks, tmp, time); + 3ea: 4632 mov r2, r6 + 3ec: 4629 mov r1, r5 + 3ee: 4638 mov r0, r7 + 3f0: 47c8 blx r9 + return (void *)list->head; + 3f2: f8d4 a014 ldr.w sl, [r4, #20] + } + it = (struct timer_task *)list_get_head(&timer->tasks); + + tmp->cb(tmp); + 3f6: 68eb ldr r3, [r5, #12] + 3f8: 4628 mov r0, r5 + 3fa: 4798 blx r3 + it = (struct timer_task *)list_get_head(&timer->tasks); + 3fc: 4655 mov r5, sl + 3fe: e7e8 b.n 3d2 + timer->flags |= TIMER_FLAG_INTERRUPT_TRIGERRED; + 400: 7e23 ldrb r3, [r4, #24] + 402: f043 0302 orr.w r3, r3, #2 + 406: 7623 strb r3, [r4, #24] + } +} + 408: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 40c: 00000649 .word 0x00000649 + 410: 00000361 .word 0x00000361 + +00000414 : +{ + 414: b538 push {r3, r4, r5, lr} + 416: 460d mov r5, r1 + ASSERT(descr && hw); + 418: 4604 mov r4, r0 + 41a: b110 cbz r0, 422 + 41c: 1e08 subs r0, r1, #0 + 41e: bf18 it ne + 420: 2001 movne r0, #1 + 422: 223b movs r2, #59 ; 0x3b + 424: 4905 ldr r1, [pc, #20] ; (43c ) + 426: 4b06 ldr r3, [pc, #24] ; (440 ) + 428: 4798 blx r3 + _timer_init(&descr->device, hw); + 42a: 4b06 ldr r3, [pc, #24] ; (444 ) + 42c: 4629 mov r1, r5 + 42e: 4620 mov r0, r4 + 430: 4798 blx r3 + descr->device.timer_cb.period_expired = timer_process_counted; + 432: 4b05 ldr r3, [pc, #20] ; (448 ) + 434: 6023 str r3, [r4, #0] + descr->time = 0; + 436: 2000 movs r0, #0 + 438: 6120 str r0, [r4, #16] +} + 43a: bd38 pop {r3, r4, r5, pc} + 43c: 0001635c .word 0x0001635c + 440: 00000655 .word 0x00000655 + 444: 00000d81 .word 0x00000d81 + 448: 000003ad .word 0x000003ad + +0000044c : +{ + 44c: b538 push {r3, r4, r5, lr} + ASSERT(descr); + 44e: 4605 mov r5, r0 + 450: 3800 subs r0, #0 + 452: bf18 it ne + 454: 2001 movne r0, #1 + 456: 4908 ldr r1, [pc, #32] ; (478 ) + 458: 4b08 ldr r3, [pc, #32] ; (47c ) + 45a: 2253 movs r2, #83 ; 0x53 + 45c: 4798 blx r3 + if (_timer_is_started(&descr->device)) { + 45e: 4b08 ldr r3, [pc, #32] ; (480 ) + 460: 4628 mov r0, r5 + 462: 4798 blx r3 + 464: 4604 mov r4, r0 + 466: b920 cbnz r0, 472 + _timer_start(&descr->device); + 468: 4628 mov r0, r5 + 46a: 4b06 ldr r3, [pc, #24] ; (484 ) + 46c: 4798 blx r3 + return ERR_NONE; + 46e: 4620 mov r0, r4 +} + 470: bd38 pop {r3, r4, r5, pc} + return ERR_DENIED; + 472: f06f 0010 mvn.w r0, #16 + 476: e7fb b.n 470 + 478: 0001635c .word 0x0001635c + 47c: 00000655 .word 0x00000655 + 480: 00000ed1 .word 0x00000ed1 + 484: 00000ebd .word 0x00000ebd + +00000488 : +{ + 488: e92d 41f3 stmdb sp!, {r0, r1, r4, r5, r6, r7, r8, lr} + 48c: 460d mov r5, r1 + ASSERT(descr && task); + 48e: 4604 mov r4, r0 + 490: b110 cbz r0, 498 + 492: 1e08 subs r0, r1, #0 + 494: bf18 it ne + 496: 2001 movne r0, #1 + 498: 491e ldr r1, [pc, #120] ; (514 ) + 49a: f8df 8090 ldr.w r8, [pc, #144] ; 52c + 49e: 227a movs r2, #122 ; 0x7a + 4a0: 47c0 blx r8 + descr->flags |= TIMER_FLAG_QUEUE_IS_TAKEN; + 4a2: 7e23 ldrb r3, [r4, #24] + if (is_list_element(&descr->tasks, task)) { + 4a4: f104 0714 add.w r7, r4, #20 + descr->flags |= TIMER_FLAG_QUEUE_IS_TAKEN; + 4a8: f043 0301 orr.w r3, r3, #1 + 4ac: 7623 strb r3, [r4, #24] + if (is_list_element(&descr->tasks, task)) { + 4ae: 4629 mov r1, r5 + 4b0: 4b19 ldr r3, [pc, #100] ; (518 ) + 4b2: 4638 mov r0, r7 + 4b4: 4798 blx r3 + 4b6: 4606 mov r6, r0 + 4b8: b160 cbz r0, 4d4 + descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; + 4ba: 7e23 ldrb r3, [r4, #24] + ASSERT(false); + 4bc: 4915 ldr r1, [pc, #84] ; (514 ) + descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; + 4be: f003 03fe and.w r3, r3, #254 ; 0xfe + ASSERT(false); + 4c2: 2000 movs r0, #0 + descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; + 4c4: 7623 strb r3, [r4, #24] + ASSERT(false); + 4c6: 227f movs r2, #127 ; 0x7f + 4c8: 47c0 blx r8 + return ERR_ALREADY_INITIALIZED; + 4ca: f06f 0011 mvn.w r0, #17 +} + 4ce: b002 add sp, #8 + 4d0: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + task->time_label = descr->time; + 4d4: 6922 ldr r2, [r4, #16] + timer_add_timer_task(&descr->tasks, task, descr->time); + 4d6: 4b11 ldr r3, [pc, #68] ; (51c ) + task->time_label = descr->time; + 4d8: 606a str r2, [r5, #4] + timer_add_timer_task(&descr->tasks, task, descr->time); + 4da: 4629 mov r1, r5 + 4dc: 4638 mov r0, r7 + 4de: 4798 blx r3 + descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; + 4e0: 7e23 ldrb r3, [r4, #24] + 4e2: f003 03fe and.w r3, r3, #254 ; 0xfe + 4e6: 7623 strb r3, [r4, #24] + if (descr->flags & TIMER_FLAG_INTERRUPT_TRIGERRED) { + 4e8: 7e23 ldrb r3, [r4, #24] + 4ea: f013 0302 ands.w r3, r3, #2 + 4ee: d00e beq.n 50e + CRITICAL_SECTION_ENTER() + 4f0: 4b0b ldr r3, [pc, #44] ; (520 ) + 4f2: a801 add r0, sp, #4 + 4f4: 4798 blx r3 + descr->flags &= ~TIMER_FLAG_INTERRUPT_TRIGERRED; + 4f6: 7e23 ldrb r3, [r4, #24] + 4f8: f003 03fd and.w r3, r3, #253 ; 0xfd + 4fc: 7623 strb r3, [r4, #24] + _timer_set_irq(&descr->device); + 4fe: 4620 mov r0, r4 + 500: 4b08 ldr r3, [pc, #32] ; (524 ) + 502: 4798 blx r3 + CRITICAL_SECTION_LEAVE() + 504: a801 add r0, sp, #4 + 506: 4b08 ldr r3, [pc, #32] ; (528 ) + 508: 4798 blx r3 + return ERR_NONE; + 50a: 4630 mov r0, r6 + 50c: e7df b.n 4ce + 50e: 4618 mov r0, r3 + 510: e7dd b.n 4ce + 512: bf00 nop + 514: 0001635c .word 0x0001635c + 518: 00000605 .word 0x00000605 + 51c: 00000361 .word 0x00000361 + 520: 00000f49 .word 0x00000f49 + 524: 00000eed .word 0x00000eed + 528: 00000f57 .word 0x00000f57 + 52c: 00000655 .word 0x00000655 + +00000530 : +/** + * \brief Initialize Delay driver + */ +void delay_init(void *const hw) +{ + _delay_init(hardware = hw); + 530: 4b01 ldr r3, [pc, #4] ; (538 ) + 532: 6018 str r0, [r3, #0] + 534: 4b01 ldr r3, [pc, #4] ; (53c ) + 536: 4718 bx r3 + 538: 20000094 .word 0x20000094 + 53c: 00000357 .word 0x00000357 + +00000540 : +/** + * \brief Perform delay in us + */ +void delay_us(const uint16_t us) +{ + _delay_cycles(hardware, _get_cycles_for_us(us)); + 540: 4b05 ldr r3, [pc, #20] ; (558 ) +{ + 542: b510 push {r4, lr} + _delay_cycles(hardware, _get_cycles_for_us(us)); + 544: 681c ldr r4, [r3, #0] + 546: 4b05 ldr r3, [pc, #20] ; (55c ) + 548: 4798 blx r3 + 54a: 4b05 ldr r3, [pc, #20] ; (560 ) + 54c: 4601 mov r1, r0 + 54e: 4620 mov r0, r4 +} + 550: e8bd 4010 ldmia.w sp!, {r4, lr} + _delay_cycles(hardware, _get_cycles_for_us(us)); + 554: 4718 bx r3 + 556: bf00 nop + 558: 20000094 .word 0x20000094 + 55c: 00000335 .word 0x00000335 + 560: 00000359 .word 0x00000359 + +00000564 : +/** + * \brief Perform delay in ms + */ +void delay_ms(const uint16_t ms) +{ + _delay_cycles(hardware, _get_cycles_for_ms(ms)); + 564: 4b05 ldr r3, [pc, #20] ; (57c ) +{ + 566: b510 push {r4, lr} + _delay_cycles(hardware, _get_cycles_for_ms(ms)); + 568: 681c ldr r4, [r3, #0] + 56a: 4b05 ldr r3, [pc, #20] ; (580 ) + 56c: 4798 blx r3 + 56e: 4b05 ldr r3, [pc, #20] ; (584 ) + 570: 4601 mov r1, r0 + 572: 4620 mov r0, r4 +} + 574: e8bd 4010 ldmia.w sp!, {r4, lr} + _delay_cycles(hardware, _get_cycles_for_ms(ms)); + 578: 4718 bx r3 + 57a: bf00 nop + 57c: 20000094 .word 0x20000094 + 580: 00000343 .word 0x00000343 + 584: 00000359 .word 0x00000359 + +00000588 <_init_chip>: +} + +static inline void hri_nvmctrl_set_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_RWS(mask); + 588: 4a0a ldr r2, [pc, #40] ; (5b4 <_init_chip+0x2c>) + 58a: 8813 ldrh r3, [r2, #0] + 58c: b29b uxth r3, r3 + +/** + * \brief Initialize the hardware abstraction layer + */ +void _init_chip(void) +{ + 58e: b510 push {r4, lr} + 590: f443 63a0 orr.w r3, r3, #1280 ; 0x500 + 594: 8013 strh r3, [r2, #0] + hri_nvmctrl_set_CTRLA_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE); + + _osc32kctrl_init_sources(); + 596: 4b08 ldr r3, [pc, #32] ; (5b8 <_init_chip+0x30>) + 598: 4798 blx r3 + _oscctrl_init_sources(); + 59a: 4b08 ldr r3, [pc, #32] ; (5bc <_init_chip+0x34>) + 59c: 4798 blx r3 + _mclk_init(); + 59e: 4b08 ldr r3, [pc, #32] ; (5c0 <_init_chip+0x38>) + 5a0: 4798 blx r3 +#if _GCLK_INIT_1ST + _gclk_init_generators_by_fref(_GCLK_INIT_1ST); +#endif + _oscctrl_init_referenced_generators(); + 5a2: 4b08 ldr r3, [pc, #32] ; (5c4 <_init_chip+0x3c>) + 5a4: 4798 blx r3 +#endif + +#if CONF_CMCC_ENABLE + cache_init(); +#endif +} + 5a6: e8bd 4010 ldmia.w sp!, {r4, lr} + _gclk_init_generators_by_fref(_GCLK_INIT_LAST); + 5aa: 4b07 ldr r3, [pc, #28] ; (5c8 <_init_chip+0x40>) + 5ac: f640 70ff movw r0, #4095 ; 0xfff + 5b0: 4718 bx r3 + 5b2: bf00 nop + 5b4: 41004000 .word 0x41004000 + 5b8: 00000a3d .word 0x00000a3d + 5bc: 0000065b .word 0x0000065b + 5c0: 00000699 .word 0x00000699 + 5c4: 0000065d .word 0x0000065d + 5c8: 00000935 .word 0x00000935 + +000005cc : + return tmp; +} + +static inline hri_ramecc_intflag_reg_t hri_ramecc_read_INTFLAG_reg(const void *const hw) +{ + return ((Ramecc *)hw)->INTFLAG.reg; + 5cc: 4a0b ldr r2, [pc, #44] ; (5fc ) + 5ce: 7893 ldrb r3, [r2, #2] + +/** + * \internal RAMECC interrupt handler + */ +void RAMECC_Handler(void) +{ + 5d0: b082 sub sp, #8 + 5d2: b2db uxtb r3, r3 + struct _ramecc_device *dev = (struct _ramecc_device *)&device; + volatile uint32_t int_mask = hri_ramecc_read_INTFLAG_reg(RAMECC); + 5d4: 9301 str r3, [sp, #4] + + if (int_mask & RAMECC_INTFLAG_DUALE && dev->ramecc_cb.dual_bit_err) { + 5d6: 9b01 ldr r3, [sp, #4] + 5d8: 0799 lsls r1, r3, #30 + 5da: d505 bpl.n 5e8 + 5dc: 4b08 ldr r3, [pc, #32] ; (600 ) + 5de: 681b ldr r3, [r3, #0] + 5e0: b113 cbz r3, 5e8 + return tmp; +} + +static inline hri_ramecc_erraddr_reg_t hri_ramecc_read_ERRADDR_reg(const void *const hw) +{ + return ((Ramecc *)hw)->ERRADDR.reg; + 5e2: 6850 ldr r0, [r2, #4] + } else if (int_mask & RAMECC_INTFLAG_SINGLEE && dev->ramecc_cb.single_bit_err) { + dev->ramecc_cb.single_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC)); + } else { + return; + } +} + 5e4: b002 add sp, #8 + dev->ramecc_cb.single_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC)); + 5e6: 4718 bx r3 + } else if (int_mask & RAMECC_INTFLAG_SINGLEE && dev->ramecc_cb.single_bit_err) { + 5e8: 9b01 ldr r3, [sp, #4] + 5ea: 07db lsls r3, r3, #31 + 5ec: d504 bpl.n 5f8 + 5ee: 4b04 ldr r3, [pc, #16] ; (600 ) + 5f0: 685b ldr r3, [r3, #4] + 5f2: b10b cbz r3, 5f8 + 5f4: 4a01 ldr r2, [pc, #4] ; (5fc ) + 5f6: e7f4 b.n 5e2 +} + 5f8: b002 add sp, #8 + 5fa: 4770 bx lr + 5fc: 41020000 .word 0x41020000 + 600: 20000098 .word 0x20000098 + +00000604 : + * \brief Check whether element belongs to list + */ +bool is_list_element(const struct list_descriptor *const list, const void *const element) +{ + struct list_element *it; + for (it = list->head; it; it = it->next) { + 604: 6800 ldr r0, [r0, #0] + 606: b900 cbnz r0, 60a + 608: 4770 bx lr + if (it == element) { + 60a: 4288 cmp r0, r1 + 60c: d1fa bne.n 604 + return true; + 60e: 2001 movs r0, #1 + } + } + + return false; +} + 610: 4770 bx lr + ... + +00000614 : + +/** + * \brief Insert an element as list head + */ +void list_insert_as_head(struct list_descriptor *const list, void *const element) +{ + 614: b538 push {r3, r4, r5, lr} + ASSERT(!is_list_element(list, element)); + 616: 4b07 ldr r3, [pc, #28] ; (634 ) +{ + 618: 4604 mov r4, r0 + ASSERT(!is_list_element(list, element)); + 61a: 4798 blx r3 + 61c: f080 0001 eor.w r0, r0, #1 +{ + 620: 460d mov r5, r1 + ASSERT(!is_list_element(list, element)); + 622: 4b05 ldr r3, [pc, #20] ; (638 ) + 624: 4905 ldr r1, [pc, #20] ; (63c ) + 626: 2239 movs r2, #57 ; 0x39 + 628: b2c0 uxtb r0, r0 + 62a: 4798 blx r3 + + ((struct list_element *)element)->next = list->head; + 62c: 6823 ldr r3, [r4, #0] + 62e: 602b str r3, [r5, #0] + list->head = (struct list_element *)element; + 630: 6025 str r5, [r4, #0] +} + 632: bd38 pop {r3, r4, r5, pc} + 634: 00000605 .word 0x00000605 + 638: 00000655 .word 0x00000655 + 63c: 00016373 .word 0x00016373 + +00000640 : +/** + * \brief Insert an element after the given list element + */ +void list_insert_after(void *const after, void *const element) +{ + ((struct list_element *)element)->next = ((struct list_element *)after)->next; + 640: 6803 ldr r3, [r0, #0] + 642: 600b str r3, [r1, #0] + ((struct list_element *)after)->next = (struct list_element *)element; + 644: 6001 str r1, [r0, #0] +} + 646: 4770 bx lr + +00000648 : +/** + * \brief Removes list head + */ +void *list_remove_head(struct list_descriptor *const list) +{ + if (list->head) { + 648: 6803 ldr r3, [r0, #0] + 64a: b10b cbz r3, 650 + struct list_element *tmp = list->head; + + list->head = list->head->next; + 64c: 681a ldr r2, [r3, #0] + 64e: 6002 str r2, [r0, #0] + return (void *)tmp; + } + + return NULL; +} + 650: 4618 mov r0, r3 + 652: 4770 bx lr + +00000654 : +/** + * \brief Assert function + */ +void assert(const bool condition, const char *const file, const int line) +{ + if (!(condition)) { + 654: b900 cbnz r0, 658 + __asm("BKPT #0"); + 656: be00 bkpt 0x0000 + } + (void)file; + (void)line; +} + 658: 4770 bx lr + +0000065a <_oscctrl_init_sources>: + hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(hw, 1); +#endif +#endif + + (void)hw; +} + 65a: 4770 bx lr + +0000065c <_oscctrl_init_referenced_generators>: + +static inline void hri_oscctrl_write_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = data; + 65c: 4b0c ldr r3, [pc, #48] ; (690 <_oscctrl_init_referenced_generators+0x34>) + 65e: 4a0d ldr r2, [pc, #52] ; (694 <_oscctrl_init_referenced_generators+0x38>) + 660: 635a str r2, [r3, #52] ; 0x34 + while (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & reg) { + 662: 6bda ldr r2, [r3, #60] ; 0x3c + 664: f012 0f06 tst.w r2, #6 + 668: d1fb bne.n 662 <_oscctrl_init_referenced_generators+0x6> + +static inline void hri_oscctrl_write_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = data; + 66a: f44f 6202 mov.w r2, #2080 ; 0x820 + 66e: 639a str r2, [r3, #56] ; 0x38 + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = data; + 670: 2202 movs r2, #2 + 672: f883 2030 strb.w r2, [r3, #48] ; 0x30 + while (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & reg) { + 676: 4a06 ldr r2, [pc, #24] ; (690 <_oscctrl_init_referenced_generators+0x34>) + 678: 6bd3 ldr r3, [r2, #60] ; 0x3c + 67a: 0798 lsls r0, r3, #30 + 67c: d4fc bmi.n 678 <_oscctrl_init_referenced_generators+0x1c> + return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK) + 67e: 4b04 ldr r3, [pc, #16] ; (690 <_oscctrl_init_referenced_generators+0x34>) + 680: 6c1a ldr r2, [r3, #64] ; 0x40 +#endif +#endif + +#if CONF_FDPLL0_CONFIG == 1 +#if CONF_FDPLL0_ENABLE == 1 + while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw, 0) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw, 0))) + 682: 07d1 lsls r1, r2, #31 + 684: d402 bmi.n 68c <_oscctrl_init_referenced_generators+0x30> + return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY) + 686: 6c1a ldr r2, [r3, #64] ; 0x40 + 688: 0792 lsls r2, r2, #30 + 68a: d5f9 bpl.n 680 <_oscctrl_init_referenced_generators+0x24> + hri_gclk_write_GENCTRL_SRC_bf(GCLK, 0, CONF_GCLK_GEN_0_SOURCE); + while (hri_gclk_get_SYNCBUSY_GENCTRL0_bit(GCLK)) + ; +#endif + (void)hw; +} + 68c: 4770 bx lr + 68e: bf00 nop + 690: 40001000 .word 0x40001000 + 694: 00010e4d .word 0x00010e4d + +00000698 <_mclk_init>: +} + +static inline void hri_mclk_write_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg = data; + 698: 4b01 ldr r3, [pc, #4] ; (6a0 <_mclk_init+0x8>) + 69a: 2201 movs r2, #1 + 69c: 715a strb r2, [r3, #5] + */ +void _mclk_init(void) +{ + void *hw = (void *)MCLK; + hri_mclk_write_CPUDIV_reg(hw, MCLK_CPUDIV_DIV(CONF_MCLK_CPUDIV)); +} + 69e: 4770 bx lr + 6a0: 40000800 .word 0x40000800 + +000006a4 : + while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) { + 6a4: 69c3 ldr r3, [r0, #28] + 6a6: 420b tst r3, r1 + 6a8: d1fc bne.n 6a4 +} + 6aa: 4770 bx lr + +000006ac : + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE; + 6ac: 6802 ldr r2, [r0, #0] + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + 6ae: 4b03 ldr r3, [pc, #12] ; (6bc ) + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE; + 6b0: f042 0202 orr.w r2, r2, #2 + 6b4: 6002 str r2, [r0, #0] + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + 6b6: 2103 movs r1, #3 + 6b8: 4718 bx r3 + 6ba: bf00 nop + 6bc: 000006a5 .word 0x000006a5 + +000006c0 : + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE; + 6c0: 6802 ldr r2, [r0, #0] + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + 6c2: 4b03 ldr r3, [pc, #12] ; (6d0 ) + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE; + 6c4: f022 0202 bic.w r2, r2, #2 + 6c8: 6002 str r2, [r0, #0] + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + 6ca: 2103 movs r1, #3 + 6cc: 4718 bx r3 + 6ce: bf00 nop + 6d0: 000006a5 .word 0x000006a5 + +000006d4 : + ((Sercom *)hw)->I2CM.CTRLA.reg = data; + 6d4: 6001 str r1, [r0, #0] + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + 6d6: 4b01 ldr r3, [pc, #4] ; (6dc ) + 6d8: 2103 movs r1, #3 + 6da: 4718 bx r3 + 6dc: 000006a5 .word 0x000006a5 + +000006e0 <_sercom_get_hardware_index>: +{ + 6e0: b570 push {r4, r5, r6, lr} + Sercom *const sercom_modules[] = SERCOM_INSTS; + 6e2: 4d0c ldr r5, [pc, #48] ; (714 <_sercom_get_hardware_index+0x34>) +{ + 6e4: 4606 mov r6, r0 + Sercom *const sercom_modules[] = SERCOM_INSTS; + 6e6: cd0f ldmia r5!, {r0, r1, r2, r3} +{ + 6e8: b088 sub sp, #32 + Sercom *const sercom_modules[] = SERCOM_INSTS; + 6ea: 466c mov r4, sp + 6ec: c40f stmia r4!, {r0, r1, r2, r3} + 6ee: e895 000f ldmia.w r5, {r0, r1, r2, r3} + 6f2: e884 000f stmia.w r4, {r0, r1, r2, r3} + for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) { + 6f6: 466a mov r2, sp + 6f8: 2300 movs r3, #0 + if ((uint32_t)hw == (uint32_t)sercom_modules[i]) { + 6fa: f852 1b04 ldr.w r1, [r2], #4 + 6fe: 42b1 cmp r1, r6 + 700: d102 bne.n 708 <_sercom_get_hardware_index+0x28> + return i; + 702: b2d8 uxtb r0, r3 +} + 704: b008 add sp, #32 + 706: bd70 pop {r4, r5, r6, pc} + for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) { + 708: 3301 adds r3, #1 + 70a: 2b08 cmp r3, #8 + 70c: d1f5 bne.n 6fa <_sercom_get_hardware_index+0x1a> + return 0; + 70e: 2000 movs r0, #0 + 710: e7f8 b.n 704 <_sercom_get_hardware_index+0x24> + 712: bf00 nop + 714: 000163ac .word 0x000163ac + +00000718 <_sercom_get_irq_num>: +{ + 718: b508 push {r3, lr} + return SERCOM0_0_IRQn + (_sercom_get_hardware_index(hw) << 2); + 71a: 4b03 ldr r3, [pc, #12] ; (728 <_sercom_get_irq_num+0x10>) + 71c: 4798 blx r3 + 71e: 0080 lsls r0, r0, #2 + 720: 302e adds r0, #46 ; 0x2e +} + 722: f000 00fe and.w r0, r0, #254 ; 0xfe + 726: bd08 pop {r3, pc} + 728: 000006e1 .word 0x000006e1 + +0000072c <__NVIC_EnableIRQ>: + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 72c: 0941 lsrs r1, r0, #5 + 72e: 4a04 ldr r2, [pc, #16] ; (740 <__NVIC_EnableIRQ+0x14>) + 730: f000 001f and.w r0, r0, #31 + 734: 2301 movs r3, #1 + 736: 4083 lsls r3, r0 + 738: f842 3021 str.w r3, [r2, r1, lsl #2] +} + 73c: 4770 bx lr + 73e: bf00 nop + 740: e000e100 .word 0xe000e100 + +00000744 <__NVIC_DisableIRQ>: + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 744: 0943 lsrs r3, r0, #5 + 746: 4906 ldr r1, [pc, #24] ; (760 <__NVIC_DisableIRQ+0x1c>) + 748: f000 001f and.w r0, r0, #31 + 74c: 3320 adds r3, #32 + 74e: 2201 movs r2, #1 + 750: 4082 lsls r2, r0 + 752: f841 2023 str.w r2, [r1, r3, lsl #2] + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); + 756: f3bf 8f4f dsb sy + __ASM volatile ("isb 0xF":::"memory"); + 75a: f3bf 8f6f isb sy +} + 75e: 4770 bx lr + 760: e000e100 .word 0xe000e100 + +00000764 <__NVIC_ClearPendingIRQ>: + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 764: 0943 lsrs r3, r0, #5 + 766: 4904 ldr r1, [pc, #16] ; (778 <__NVIC_ClearPendingIRQ+0x14>) + 768: f000 001f and.w r0, r0, #31 + 76c: 2201 movs r2, #1 + 76e: 3360 adds r3, #96 ; 0x60 + 770: 4082 lsls r2, r0 + 772: f841 2023 str.w r2, [r1, r3, lsl #2] + } +} + 776: 4770 bx lr + 778: e000e100 .word 0xe000e100 + +0000077c <_usart_init>: +{ + 77c: b570 push {r4, r5, r6, lr} + uint8_t sercom_offset = _sercom_get_hardware_index(hw); + 77e: 4b19 ldr r3, [pc, #100] ; (7e4 <_usart_init+0x68>) +{ + 780: 4604 mov r4, r0 + uint8_t sercom_offset = _sercom_get_hardware_index(hw); + 782: 4798 blx r3 + if (_usarts[i].number == sercom_offset) { + 784: b128 cbz r0, 792 <_usart_init+0x16> + ASSERT(false); + 786: 4918 ldr r1, [pc, #96] ; (7e8 <_usart_init+0x6c>) + 788: 4b18 ldr r3, [pc, #96] ; (7ec <_usart_init+0x70>) + 78a: f240 226b movw r2, #619 ; 0x26b + 78e: 2000 movs r0, #0 + 790: 4798 blx r3 + return ((Sercom *)hw)->USART.SYNCBUSY.reg & reg; + 792: 69e3 ldr r3, [r4, #28] + 794: 4d16 ldr r5, [pc, #88] ; (7f0 <_usart_init+0x74>) + 796: 4e17 ldr r6, [pc, #92] ; (7f4 <_usart_init+0x78>) + if (!hri_sercomusart_is_syncing(hw, SERCOM_USART_SYNCBUSY_SWRST)) { + 798: f013 0f01 tst.w r3, #1 + 79c: d10d bne.n 7ba <_usart_init+0x3e> + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + 79e: 4b16 ldr r3, [pc, #88] ; (7f8 <_usart_init+0x7c>) + 7a0: 2103 movs r1, #3 + 7a2: 4620 mov r0, r4 + 7a4: 4798 blx r3 + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + 7a6: 6823 ldr r3, [r4, #0] + if (hri_sercomusart_get_CTRLA_reg(hw, SERCOM_USART_CTRLA_ENABLE)) { + 7a8: 079b lsls r3, r3, #30 + 7aa: d503 bpl.n 7b4 <_usart_init+0x38> + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + 7ac: 4b13 ldr r3, [pc, #76] ; (7fc <_usart_init+0x80>) + 7ae: 4798 blx r3 + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + 7b0: 2102 movs r1, #2 + 7b2: 47a8 blx r5 + hri_sercomusart_write_CTRLA_reg(hw, SERCOM_USART_CTRLA_SWRST | mode); + 7b4: 2105 movs r1, #5 + 7b6: 4620 mov r0, r4 + 7b8: 47b0 blx r6 + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); + 7ba: 4620 mov r0, r4 + 7bc: 2101 movs r1, #1 + 7be: 47a8 blx r5 + hri_sercomusart_write_CTRLA_reg(hw, _usarts[i].ctrl_a); + 7c0: 490f ldr r1, [pc, #60] ; (800 <_usart_init+0x84>) + 7c2: 47b0 blx r6 + ((Sercom *)hw)->USART.CTRLB.reg = data; + 7c4: f44f 3340 mov.w r3, #196608 ; 0x30000 + 7c8: 6063 str r3, [r4, #4] + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + 7ca: 211f movs r1, #31 + 7cc: 47a8 blx r5 + ((Sercom *)hw)->USART.CTRLC.reg = data; + 7ce: 4b0d ldr r3, [pc, #52] ; (804 <_usart_init+0x88>) + 7d0: 60a3 str r3, [r4, #8] +} + +static inline void hri_sercomusart_write_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg = data; + 7d2: f64f 4311 movw r3, #64529 ; 0xfc11 + 7d6: 81a3 strh r3, [r4, #12] +} + +static inline void hri_sercomusart_write_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg = data; + 7d8: 2300 movs r3, #0 + 7da: 73a3 strb r3, [r4, #14] +} + 7dc: 4618 mov r0, r3 +} + +static inline void hri_sercomusart_write_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg = data; + 7de: f884 3030 strb.w r3, [r4, #48] ; 0x30 + 7e2: bd70 pop {r4, r5, r6, pc} + 7e4: 000006e1 .word 0x000006e1 + 7e8: 00016391 .word 0x00016391 + 7ec: 00000655 .word 0x00000655 + 7f0: 000006a5 .word 0x000006a5 + 7f4: 000006d5 .word 0x000006d5 + 7f8: 000006a5 .word 0x000006a5 + 7fc: 000006c1 .word 0x000006c1 + 800: 40100004 .word 0x40100004 + 804: 00700002 .word 0x00700002 + +00000808 <_usart_async_init>: +{ + 808: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr} + ASSERT(device); + 80c: 4605 mov r5, r0 + 80e: 3800 subs r0, #0 + 810: bf18 it ne + 812: 2001 movne r0, #1 + 814: 4b14 ldr r3, [pc, #80] ; (868 <_usart_async_init+0x60>) +{ + 816: 460c mov r4, r1 + ASSERT(device); + 818: 22cb movs r2, #203 ; 0xcb + 81a: 4914 ldr r1, [pc, #80] ; (86c <_usart_async_init+0x64>) + 81c: 4798 blx r3 + init_status = _usart_init(hw); + 81e: 4b14 ldr r3, [pc, #80] ; (870 <_usart_async_init+0x68>) + 820: 4620 mov r0, r4 + 822: 4798 blx r3 + if (init_status) { + 824: 4606 mov r6, r0 + 826: b9d8 cbnz r0, 860 <_usart_async_init+0x58> + if (hw == SERCOM0) { + 828: 4b12 ldr r3, [pc, #72] ; (874 <_usart_async_init+0x6c>) + device->hw = hw; + 82a: 61ac str r4, [r5, #24] + if (hw == SERCOM0) { + 82c: 429c cmp r4, r3 + _sercom0_dev = (struct _usart_async_device *)dev; + 82e: bf08 it eq + 830: 4b11 ldreq r3, [pc, #68] ; (878 <_usart_async_init+0x70>) + NVIC_DisableIRQ((IRQn_Type)irq); + 832: f8df 9050 ldr.w r9, [pc, #80] ; 884 <_usart_async_init+0x7c> + _sercom0_dev = (struct _usart_async_device *)dev; + 836: bf08 it eq + 838: 601d streq r5, [r3, #0] + uint8_t irq = _sercom_get_irq_num(hw); + 83a: 4620 mov r0, r4 + 83c: 4b0f ldr r3, [pc, #60] ; (87c <_usart_async_init+0x74>) + NVIC_ClearPendingIRQ((IRQn_Type)irq); + 83e: f8df 8048 ldr.w r8, [pc, #72] ; 888 <_usart_async_init+0x80> + NVIC_EnableIRQ((IRQn_Type)irq); + 842: 4f0f ldr r7, [pc, #60] ; (880 <_usart_async_init+0x78>) + uint8_t irq = _sercom_get_irq_num(hw); + 844: 4798 blx r3 + for (uint32_t i = 0; i < 4; i++) { + 846: 2400 movs r4, #0 + uint8_t irq = _sercom_get_irq_num(hw); + 848: 4605 mov r5, r0 + NVIC_DisableIRQ((IRQn_Type)irq); + 84a: 192b adds r3, r5, r4 + 84c: b2d8 uxtb r0, r3 + 84e: 9001 str r0, [sp, #4] + 850: 47c8 blx r9 + NVIC_ClearPendingIRQ((IRQn_Type)irq); + 852: 9801 ldr r0, [sp, #4] + 854: 47c0 blx r8 + for (uint32_t i = 0; i < 4; i++) { + 856: 3401 adds r4, #1 + NVIC_EnableIRQ((IRQn_Type)irq); + 858: 9801 ldr r0, [sp, #4] + 85a: 47b8 blx r7 + for (uint32_t i = 0; i < 4; i++) { + 85c: 2c04 cmp r4, #4 + 85e: d1f4 bne.n 84a <_usart_async_init+0x42> +} + 860: 4630 mov r0, r6 + 862: b003 add sp, #12 + 864: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + 868: 00000655 .word 0x00000655 + 86c: 00016391 .word 0x00016391 + 870: 0000077d .word 0x0000077d + 874: 40003000 .word 0x40003000 + 878: 200000a8 .word 0x200000a8 + 87c: 00000719 .word 0x00000719 + 880: 0000072d .word 0x0000072d + 884: 00000745 .word 0x00000745 + 888: 00000765 .word 0x00000765 + +0000088c <_usart_async_enable>: + hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw); + 88c: 6980 ldr r0, [r0, #24] + 88e: 4b01 ldr r3, [pc, #4] ; (894 <_usart_async_enable+0x8>) + 890: 4718 bx r3 + 892: bf00 nop + 894: 000006ad .word 0x000006ad + +00000898 <_usart_async_write_byte>: + hri_sercomusart_write_DATA_reg(device->hw, data); + 898: 6983 ldr r3, [r0, #24] + ((Sercom *)hw)->USART.DATA.reg = data; + 89a: 6299 str r1, [r3, #40] ; 0x28 +} + 89c: 4770 bx lr + +0000089e <_usart_async_enable_byte_sent_irq>: + hri_sercomusart_set_INTEN_DRE_bit(device->hw); + 89e: 6983 ldr r3, [r0, #24] + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; + 8a0: 2201 movs r2, #1 + 8a2: 759a strb r2, [r3, #22] +} + 8a4: 4770 bx lr + +000008a6 <_usart_async_enable_tx_done_irq>: + hri_sercomusart_set_INTEN_TXC_bit(device->hw); + 8a6: 6983 ldr r3, [r0, #24] + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; + 8a8: 2202 movs r2, #2 + 8aa: 759a strb r2, [r3, #22] +} + 8ac: 4770 bx lr + ... + +000008b0 : +/** + * \internal Sercom interrupt handler + */ +void SERCOM0_0_Handler(void) +{ + _sercom_usart_interrupt_handler(_sercom0_dev); + 8b0: 4b19 ldr r3, [pc, #100] ; (918 ) + 8b2: 6818 ldr r0, [r3, #0] +{ + 8b4: b510 push {r4, lr} + void *hw = device->hw; + 8b6: 6984 ldr r4, [r0, #24] + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; + 8b8: 7e23 ldrb r3, [r4, #24] + if (hri_sercomusart_get_interrupt_DRE_bit(hw) && hri_sercomusart_get_INTEN_DRE_bit(hw)) { + 8ba: 07da lsls r2, r3, #31 + 8bc: d508 bpl.n 8d0 + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_DRE) >> SERCOM_USART_INTENSET_DRE_Pos; + 8be: 7da3 ldrb r3, [r4, #22] + 8c0: 07db lsls r3, r3, #31 + 8c2: d505 bpl.n 8d0 + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; + 8c4: 2301 movs r3, #1 + 8c6: 7523 strb r3, [r4, #20] + device->usart_cb.tx_byte_sent(device); + 8c8: 6803 ldr r3, [r0, #0] +} + 8ca: e8bd 4010 ldmia.w sp!, {r4, lr} + device->usart_cb.tx_done_cb(device); + 8ce: 4718 bx r3 + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; + 8d0: 7e23 ldrb r3, [r4, #24] + } else if (hri_sercomusart_get_interrupt_TXC_bit(hw) && hri_sercomusart_get_INTEN_TXC_bit(hw)) { + 8d2: 0799 lsls r1, r3, #30 + 8d4: d506 bpl.n 8e4 + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_TXC) >> SERCOM_USART_INTENSET_TXC_Pos; + 8d6: 7da3 ldrb r3, [r4, #22] + 8d8: 079a lsls r2, r3, #30 + 8da: d503 bpl.n 8e4 + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; + 8dc: 2302 movs r3, #2 + 8de: 7523 strb r3, [r4, #20] + device->usart_cb.tx_done_cb(device); + 8e0: 6883 ldr r3, [r0, #8] + 8e2: e7f2 b.n 8ca + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; + 8e4: 7e23 ldrb r3, [r4, #24] + } else if (hri_sercomusart_get_interrupt_RXC_bit(hw)) { + 8e6: 075b lsls r3, r3, #29 + 8e8: d50c bpl.n 904 + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_status_reg_t hri_sercomusart_read_STATUS_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.STATUS.reg; + 8ea: 8b63 ldrh r3, [r4, #26] + if (hri_sercomusart_read_STATUS_reg(hw) + 8ec: f003 0337 and.w r3, r3, #55 ; 0x37 + 8f0: b113 cbz r3, 8f8 + ((Sercom *)hw)->USART.STATUS.reg = mask; + 8f2: 23ff movs r3, #255 ; 0xff + 8f4: 8363 strh r3, [r4, #26] +} + 8f6: bd10 pop {r4, pc} + return ((Sercom *)hw)->USART.DATA.reg; + 8f8: 6aa1 ldr r1, [r4, #40] ; 0x28 + device->usart_cb.rx_done_cb(device, hri_sercomusart_read_DATA_reg(hw)); + 8fa: 6843 ldr r3, [r0, #4] +} + 8fc: e8bd 4010 ldmia.w sp!, {r4, lr} + device->usart_cb.rx_done_cb(device, hri_sercomusart_read_DATA_reg(hw)); + 900: b2c9 uxtb r1, r1 + 902: 4718 bx r3 + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; + 904: 7e23 ldrb r3, [r4, #24] + } else if (hri_sercomusart_get_interrupt_ERROR_bit(hw)) { + 906: 09db lsrs r3, r3, #7 + 908: d0f5 beq.n 8f6 + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; + 90a: 2380 movs r3, #128 ; 0x80 + 90c: 7623 strb r3, [r4, #24] + device->usart_cb.error_cb(device); + 90e: 68c3 ldr r3, [r0, #12] + 910: 4798 blx r3 + return ((Sercom *)hw)->USART.STATUS.reg; + 912: 8b63 ldrh r3, [r4, #26] + 914: b29b uxth r3, r3 + 916: e7ed b.n 8f4 + 918: 200000a8 .word 0x200000a8 + +0000091c : + 91c: 4b00 ldr r3, [pc, #0] ; (920 ) + 91e: 4718 bx r3 + 920: 000008b1 .word 0x000008b1 + +00000924 : + 924: 4b00 ldr r3, [pc, #0] ; (928 ) + 926: 4718 bx r3 + 928: 000008b1 .word 0x000008b1 + +0000092c : + 92c: 4b00 ldr r3, [pc, #0] ; (930 ) + 92e: 4718 bx r3 + 930: 000008b1 .word 0x000008b1 + +00000934 <_gclk_init_generators_by_fref>: + +void _gclk_init_generators_by_fref(uint32_t bm) +{ + +#if CONF_GCLK_GENERATOR_0_CONFIG == 1 + if (bm & (1ul << 0)) { + 934: 07c3 lsls r3, r0, #31 + 936: d507 bpl.n 948 <_gclk_init_generators_by_fref+0x14> +} + +static inline void hri_gclk_write_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg = data; + 938: 4b04 ldr r3, [pc, #16] ; (94c <_gclk_init_generators_by_fref+0x18>) + 93a: 4a05 ldr r2, [pc, #20] ; (950 <_gclk_init_generators_by_fref+0x1c>) + 93c: 621a str r2, [r3, #32] + while (((Gclk *)hw)->SYNCBUSY.reg & reg) { + 93e: f643 72fd movw r2, #16381 ; 0x3ffd + 942: 6859 ldr r1, [r3, #4] + 944: 4211 tst r1, r2 + 946: d1fc bne.n 942 <_gclk_init_generators_by_fref+0xe> + | (CONF_GCLK_GEN_11_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_11_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_11_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_11_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_11_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_11_SOURCE); + } +#endif +} + 948: 4770 bx lr + 94a: bf00 nop + 94c: 40001c00 .word 0x40001c00 + 950: 00010107 .word 0x00010107 + +00000954 : +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + 954: e7fe b.n 954 + ... + +00000958 : + if (pSrc != pDest) { + 958: 4918 ldr r1, [pc, #96] ; (9bc ) + 95a: 4819 ldr r0, [pc, #100] ; (9c0 ) + 95c: 4281 cmp r1, r0 +{ + 95e: b510 push {r4, lr} + if (pSrc != pDest) { + 960: d00a beq.n 978 + *pDest++ = *pSrc++; + 962: 4b18 ldr r3, [pc, #96] ; (9c4 ) + 964: 1cda adds r2, r3, #3 + 966: 1a12 subs r2, r2, r0 + 968: f022 0203 bic.w r2, r2, #3 + 96c: 1ec4 subs r4, r0, #3 + 96e: 42a3 cmp r3, r4 + 970: bf38 it cc + 972: 2200 movcc r2, #0 + 974: 4b14 ldr r3, [pc, #80] ; (9c8 ) + 976: 4798 blx r3 + *pDest++ = 0; + 978: 4b14 ldr r3, [pc, #80] ; (9cc ) + 97a: 4815 ldr r0, [pc, #84] ; (9d0 ) + 97c: 1cda adds r2, r3, #3 + 97e: 1a12 subs r2, r2, r0 + 980: 1ec1 subs r1, r0, #3 + 982: f022 0203 bic.w r2, r2, #3 + 986: 4299 cmp r1, r3 + 988: bf88 it hi + 98a: 2200 movhi r2, #0 + 98c: 4b11 ldr r3, [pc, #68] ; (9d4 ) + 98e: 2100 movs r1, #0 + 990: 4798 blx r3 + SCB->VTOR = ((uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk); + 992: 4a11 ldr r2, [pc, #68] ; (9d8 ) + 994: 4b11 ldr r3, [pc, #68] ; (9dc ) + 996: f022 027f bic.w r2, r2, #127 ; 0x7f + 99a: 609a str r2, [r3, #8] + SCB->CPACR |= (0xFu << 20); + 99c: f8d3 2088 ldr.w r2, [r3, #136] ; 0x88 + 9a0: f442 0270 orr.w r2, r2, #15728640 ; 0xf00000 + 9a4: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + __ASM volatile ("dsb 0xF":::"memory"); + 9a8: f3bf 8f4f dsb sy + __ASM volatile ("isb 0xF":::"memory"); + 9ac: f3bf 8f6f isb sy + __libc_init_array(); + 9b0: 4b0b ldr r3, [pc, #44] ; (9e0 ) + 9b2: 4798 blx r3 + main(); + 9b4: 4b0b ldr r3, [pc, #44] ; (9e4 ) + 9b6: 4798 blx r3 + while (1) + 9b8: e7fe b.n 9b8 + 9ba: bf00 nop + 9bc: 000246e4 .word 0x000246e4 + 9c0: 20000000 .word 0x20000000 + 9c4: 20000074 .word 0x20000074 + 9c8: 000162b5 .word 0x000162b5 + 9cc: 2000c800 .word 0x2000c800 + 9d0: 20000078 .word 0x20000078 + 9d4: 00016305 .word 0x00016305 + 9d8: 00000000 .word 0x00000000 + 9dc: e000ed00 .word 0xe000ed00 + 9e0: 0001624d .word 0x0001624d + 9e4: 000009e9 .word 0x000009e9 + +000009e8
: +#include "oracle.h" + + +int main(void) +{ + 9e8: b508 push {r3, lr} + oracle_init(); + 9ea: 4b02 ldr r3, [pc, #8] ; (9f4 ) + + for(;;) + { + oracle_service(); + 9ec: 4c02 ldr r4, [pc, #8] ; (9f8 ) + oracle_init(); + 9ee: 4798 blx r3 + oracle_service(); + 9f0: 47a0 blx r4 + for(;;) + 9f2: e7fd b.n 9f0 + 9f4: 000009fd .word 0x000009fd + 9f8: 00000a35 .word 0x00000a35 + +000009fc : +#include "p_ssd1963.h" +#include "p_screen.h" + + +void oracle_init(void) +{ + 9fc: b510 push {r4, lr} + * Currently the following initialization functions are supported: + * - System clock initialization + */ +static inline void init_mcu(void) +{ + _init_chip(); + 9fe: 4b07 ldr r3, [pc, #28] ; (a1c ) + a00: 4798 blx r3 + // init mcu + init_mcu(); + // uart init + p_usart_init(); + a02: 4b07 ldr r3, [pc, #28] ; (a20 ) + a04: 4798 blx r3 + // i2c init + p_i2c_init(); + a06: 4b07 ldr r3, [pc, #28] ; (a24 ) + a08: 4798 blx r3 + // gpio init + p_gpio_init(); + a0a: 4b07 ldr r3, [pc, #28] ; (a28 ) + a0c: 4798 blx r3 + // time init + p_tcc_init(); + a0e: 4b07 ldr r3, [pc, #28] ; (a2c ) + a10: 4798 blx r3 + + p_screen_init(); +} + a12: e8bd 4010 ldmia.w sp!, {r4, lr} + p_screen_init(); + a16: 4b06 ldr r3, [pc, #24] ; (a30 ) + a18: 4718 bx r3 + a1a: bf00 nop + a1c: 00000589 .word 0x00000589 + a20: 0000130d .word 0x0000130d + a24: 0000126d .word 0x0000126d + a28: 000011a5 .word 0x000011a5 + a2c: 00001295 .word 0x00001295 + a30: 000013b9 .word 0x000013b9 + +00000a34 : + +void oracle_service(void) +{ + p_screen_service(); + a34: 4b00 ldr r3, [pc, #0] ; (a38 ) + a36: 4718 bx r3 + a38: 00001465 .word 0x00001465 + +00000a3c <_osc32kctrl_init_sources>: +} + +static inline void hri_osc32kctrl_write_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg = data; + a3c: 4b06 ldr r3, [pc, #24] ; (a58 <_osc32kctrl_init_sources+0x1c>) + a3e: f242 328e movw r2, #9102 ; 0x238e + a42: 829a strh r2, [r3, #20] +} + +static inline void hri_osc32kctrl_write_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg = data; + a44: 2200 movs r2, #0 + a46: 759a strb r2, [r3, #22] +} + +static inline void hri_osc32kctrl_write_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg = data; + a48: 75da strb r2, [r3, #23] +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_CALIB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + a4a: 69da ldr r2, [r3, #28] + calib = hri_osc32kctrl_read_OSCULP32K_CALIB_bf(hw); + hri_osc32kctrl_write_OSCULP32K_reg(hw, +#if CONF_OSCULP32K_CALIB_ENABLE == 1 + OSC32KCTRL_OSCULP32K_CALIB(CONF_OSCULP32K_CALIB) +#else + OSC32KCTRL_OSCULP32K_CALIB(calib) + a4c: f402 527c and.w r2, r2, #16128 ; 0x3f00 +} + +static inline void hri_osc32kctrl_write_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg = data; + a50: 61da str r2, [r3, #28] + ((Osc32kctrl *)hw)->RTCCTRL.reg = data; + a52: 2201 movs r2, #1 + a54: 741a strb r2, [r3, #16] +#endif +#endif + + hri_osc32kctrl_write_RTCCTRL_reg(hw, OSC32KCTRL_RTCCTRL_RTCSEL(CONF_RTCCTRL)); + (void)calib; +} + a56: 4770 bx lr + a58: 40001400 .word 0x40001400 + +00000a5c : + */ +static void usart_transmission_complete(struct _usart_async_device *device) +{ + struct usart_async_descriptor *descr = CONTAINER_OF(device, struct usart_async_descriptor, device); + + descr->stat = 0; + a5c: 2300 movs r3, #0 + a5e: 6283 str r3, [r0, #40] ; 0x28 + if (descr->usart_cb.tx_done) { + a60: 69c3 ldr r3, [r0, #28] + a62: b10b cbz r3, a68 + descr->usart_cb.tx_done(descr); + a64: 3808 subs r0, #8 + a66: 4718 bx r3 + } +} + a68: 4770 bx lr + +00000a6a : + */ +static void usart_error(struct _usart_async_device *device) +{ + struct usart_async_descriptor *descr = CONTAINER_OF(device, struct usart_async_descriptor, device); + + descr->stat = 0; + a6a: 2300 movs r3, #0 + a6c: 6283 str r3, [r0, #40] ; 0x28 + if (descr->usart_cb.error) { + a6e: 6a43 ldr r3, [r0, #36] ; 0x24 + a70: b10b cbz r3, a76 + descr->usart_cb.error(descr); + a72: 3808 subs r0, #8 + a74: 4718 bx r3 + } +} + a76: 4770 bx lr + +00000a78 : +{ + a78: b570 push {r4, r5, r6, lr} + a7a: 4604 mov r4, r0 + ringbuffer_put(&descr->rx, data); + a7c: 4b05 ldr r3, [pc, #20] ; (a94 ) + a7e: f1a0 0508 sub.w r5, r0, #8 + a82: 302c adds r0, #44 ; 0x2c + a84: 4798 blx r3 + if (descr->usart_cb.rx_done) { + a86: 6a23 ldr r3, [r4, #32] + a88: b11b cbz r3, a92 + descr->usart_cb.rx_done(descr); + a8a: 4628 mov r0, r5 +} + a8c: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + descr->usart_cb.rx_done(descr); + a90: 4718 bx r3 +} + a92: bd70 pop {r4, r5, r6, pc} + a94: 00000cc9 .word 0x00000cc9 + +00000a98 : +{ + a98: b570 push {r4, r5, r6, lr} + a9a: 460e mov r6, r1 + a9c: 4615 mov r5, r2 + ASSERT(descr && buf && length); + a9e: 4604 mov r4, r0 + aa0: b118 cbz r0, aaa + aa2: b1d9 cbz r1, adc + aa4: 1e10 subs r0, r2, #0 + aa6: bf18 it ne + aa8: 2001 movne r0, #1 + aaa: 4b0f ldr r3, [pc, #60] ; (ae8 ) + aac: 490f ldr r1, [pc, #60] ; (aec ) + aae: f240 123b movw r2, #315 ; 0x13b + ab2: 4798 blx r3 + if (descr->tx_por != descr->tx_buffer_length) { + ab4: f8b4 2044 ldrh.w r2, [r4, #68] ; 0x44 + ab8: f8b4 304c ldrh.w r3, [r4, #76] ; 0x4c + abc: 429a cmp r2, r3 + abe: d10f bne.n ae0 + descr->tx_por = 0; + ac0: 2300 movs r3, #0 + ac2: f8a4 3044 strh.w r3, [r4, #68] ; 0x44 + descr->stat = USART_ASYNC_STATUS_BUSY; + ac6: 2301 movs r3, #1 + ac8: 6323 str r3, [r4, #48] ; 0x30 + _usart_async_enable_byte_sent_irq(&descr->device); + aca: f104 0008 add.w r0, r4, #8 + ace: 4b08 ldr r3, [pc, #32] ; (af0 ) + descr->tx_buffer = (uint8_t *)buf; + ad0: 64a6 str r6, [r4, #72] ; 0x48 + descr->tx_buffer_length = length; + ad2: f8a4 504c strh.w r5, [r4, #76] ; 0x4c + _usart_async_enable_byte_sent_irq(&descr->device); + ad6: 4798 blx r3 + return (int32_t)length; + ad8: 4628 mov r0, r5 +} + ada: bd70 pop {r4, r5, r6, pc} + ASSERT(descr && buf && length); + adc: 4608 mov r0, r1 + ade: e7e4 b.n aaa + return ERR_NO_RESOURCE; + ae0: f06f 001b mvn.w r0, #27 + ae4: e7f9 b.n ada + ae6: bf00 nop + ae8: 00000655 .word 0x00000655 + aec: 000163f5 .word 0x000163f5 + af0: 0000089f .word 0x0000089f + +00000af4 : + if (descr->tx_por != descr->tx_buffer_length) { + af4: 8f83 ldrh r3, [r0, #60] ; 0x3c + af6: f8b0 2044 ldrh.w r2, [r0, #68] ; 0x44 + afa: 429a cmp r2, r3 +{ + afc: b510 push {r4, lr} + afe: 4604 mov r4, r0 + if (descr->tx_por != descr->tx_buffer_length) { + b00: d00a beq.n b18 + _usart_async_write_byte(&descr->device, descr->tx_buffer[descr->tx_por++]); + b02: 6c02 ldr r2, [r0, #64] ; 0x40 + b04: 1c59 adds r1, r3, #1 + b06: 8781 strh r1, [r0, #60] ; 0x3c + b08: 5cd1 ldrb r1, [r2, r3] + b0a: 4b04 ldr r3, [pc, #16] ; (b1c ) + b0c: 4798 blx r3 + _usart_async_enable_byte_sent_irq(&descr->device); + b0e: 4b04 ldr r3, [pc, #16] ; (b20 ) + b10: 4620 mov r0, r4 +} + b12: e8bd 4010 ldmia.w sp!, {r4, lr} + _usart_async_enable_tx_done_irq(&descr->device); + b16: 4718 bx r3 + b18: 4b02 ldr r3, [pc, #8] ; (b24 ) + b1a: e7fa b.n b12 + b1c: 00000899 .word 0x00000899 + b20: 0000089f .word 0x0000089f + b24: 000008a7 .word 0x000008a7 + +00000b28 : +{ + b28: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr} + b2c: 460e mov r6, r1 + b2e: 4617 mov r7, r2 + ASSERT(descr && buf && length); + b30: 4604 mov r4, r0 + b32: b118 cbz r0, b3c + b34: b1e9 cbz r1, b72 + b36: 1e10 subs r0, r2, #0 + b38: bf18 it ne + b3a: 2001 movne r0, #1 + b3c: 4910 ldr r1, [pc, #64] ; (b80 ) + b3e: 4b11 ldr r3, [pc, #68] ; (b84 ) + ringbuffer_get(&descr->rx, &buf[was_read++]); + b40: f8df 9050 ldr.w r9, [pc, #80] ; b94 + ASSERT(descr && buf && length); + b44: f44f 72ac mov.w r2, #344 ; 0x158 + b48: 4798 blx r3 + num = ringbuffer_num(&descr->rx); + b4a: 3434 adds r4, #52 ; 0x34 + CRITICAL_SECTION_ENTER() + b4c: 4b0e ldr r3, [pc, #56] ; (b88 ) + b4e: a801 add r0, sp, #4 + b50: 4798 blx r3 + num = ringbuffer_num(&descr->rx); + b52: 4b0e ldr r3, [pc, #56] ; (b8c ) + b54: 4620 mov r0, r4 + b56: 4798 blx r3 + CRITICAL_SECTION_LEAVE() + b58: 4b0d ldr r3, [pc, #52] ; (b90 ) + num = ringbuffer_num(&descr->rx); + b5a: 4680 mov r8, r0 + CRITICAL_SECTION_LEAVE() + b5c: a801 add r0, sp, #4 + b5e: 4798 blx r3 + while ((was_read < num) && (was_read < length)) { + b60: 2500 movs r5, #0 + b62: 45a8 cmp r8, r5 + b64: d001 beq.n b6a + b66: 42bd cmp r5, r7 + b68: d105 bne.n b76 +} + b6a: 4628 mov r0, r5 + b6c: b003 add sp, #12 + b6e: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + ASSERT(descr && buf && length); + b72: 4608 mov r0, r1 + b74: e7e2 b.n b3c + ringbuffer_get(&descr->rx, &buf[was_read++]); + b76: 1971 adds r1, r6, r5 + b78: 4620 mov r0, r4 + b7a: 47c8 blx r9 + b7c: 3501 adds r5, #1 + b7e: e7f0 b.n b62 + b80: 000163f5 .word 0x000163f5 + b84: 00000655 .word 0x00000655 + b88: 00000f49 .word 0x00000f49 + b8c: 00000d09 .word 0x00000d09 + b90: 00000f57 .word 0x00000f57 + b94: 00000c89 .word 0x00000c89 + +00000b98 : +{ + b98: b5f8 push {r3, r4, r5, r6, r7, lr} + b9a: 460d mov r5, r1 + b9c: 4616 mov r6, r2 + b9e: 461f mov r7, r3 + ASSERT(descr && hw && rx_buffer && rx_buffer_length); + ba0: 4604 mov r4, r0 + ba2: b120 cbz r0, bae + ba4: b309 cbz r1, bea + ba6: b312 cbz r2, bee + ba8: 1e18 subs r0, r3, #0 + baa: bf18 it ne + bac: 2001 movne r0, #1 + bae: 4912 ldr r1, [pc, #72] ; (bf8 ) + bb0: 4b12 ldr r3, [pc, #72] ; (bfc ) + bb2: 223a movs r2, #58 ; 0x3a + bb4: 4798 blx r3 + if (ERR_NONE != ringbuffer_init(&descr->rx, rx_buffer, rx_buffer_length)) { + bb6: 4b12 ldr r3, [pc, #72] ; (c00 ) + bb8: 463a mov r2, r7 + bba: 4631 mov r1, r6 + bbc: f104 0034 add.w r0, r4, #52 ; 0x34 + bc0: 4798 blx r3 + bc2: b9b0 cbnz r0, bf2 + init_status = _usart_async_init(&descr->device, hw); + bc4: 4b0f ldr r3, [pc, #60] ; (c04 ) + bc6: 4629 mov r1, r5 + bc8: f104 0008 add.w r0, r4, #8 + bcc: 4798 blx r3 + if (init_status) { + bce: b958 cbnz r0, be8 + descr->io.read = usart_async_read; + bd0: 4b0d ldr r3, [pc, #52] ; (c08 ) + bd2: 6063 str r3, [r4, #4] + descr->io.write = usart_async_write; + bd4: 4b0d ldr r3, [pc, #52] ; (c0c ) + bd6: 6023 str r3, [r4, #0] + descr->device.usart_cb.tx_byte_sent = usart_process_byte_sent; + bd8: 4b0d ldr r3, [pc, #52] ; (c10 ) + bda: 60a3 str r3, [r4, #8] + descr->device.usart_cb.rx_done_cb = usart_fill_rx_buffer; + bdc: 4b0d ldr r3, [pc, #52] ; (c14 ) + bde: 60e3 str r3, [r4, #12] + descr->device.usart_cb.tx_done_cb = usart_transmission_complete; + be0: 4b0d ldr r3, [pc, #52] ; (c18 ) + be2: 6123 str r3, [r4, #16] + descr->device.usart_cb.error_cb = usart_error; + be4: 4b0d ldr r3, [pc, #52] ; (c1c ) + be6: 6163 str r3, [r4, #20] +} + be8: bdf8 pop {r3, r4, r5, r6, r7, pc} + ASSERT(descr && hw && rx_buffer && rx_buffer_length); + bea: 4608 mov r0, r1 + bec: e7df b.n bae + bee: 4610 mov r0, r2 + bf0: e7dd b.n bae + return ERR_INVALID_ARG; + bf2: f06f 000c mvn.w r0, #12 + bf6: e7f7 b.n be8 + bf8: 000163f5 .word 0x000163f5 + bfc: 00000655 .word 0x00000655 + c00: 00000c4d .word 0x00000c4d + c04: 00000809 .word 0x00000809 + c08: 00000b29 .word 0x00000b29 + c0c: 00000a99 .word 0x00000a99 + c10: 00000af5 .word 0x00000af5 + c14: 00000a79 .word 0x00000a79 + c18: 00000a5d .word 0x00000a5d + c1c: 00000a6b .word 0x00000a6b + +00000c20 : +{ + c20: b510 push {r4, lr} + ASSERT(descr); + c22: 4604 mov r4, r0 + c24: 3800 subs r0, #0 + c26: bf18 it ne + c28: 2001 movne r0, #1 + c2a: 4905 ldr r1, [pc, #20] ; (c40 ) + c2c: 4b05 ldr r3, [pc, #20] ; (c44 ) + c2e: 2261 movs r2, #97 ; 0x61 + c30: 4798 blx r3 + _usart_async_enable(&descr->device); + c32: f104 0008 add.w r0, r4, #8 + c36: 4b04 ldr r3, [pc, #16] ; (c48 ) + c38: 4798 blx r3 +} + c3a: 2000 movs r0, #0 + c3c: bd10 pop {r4, pc} + c3e: bf00 nop + c40: 000163f5 .word 0x000163f5 + c44: 00000655 .word 0x00000655 + c48: 0000088d .word 0x0000088d + +00000c4c : + +/** + * \brief Ringbuffer init + */ +int32_t ringbuffer_init(struct ringbuffer *const rb, void *buf, uint32_t size) +{ + c4c: b570 push {r4, r5, r6, lr} + c4e: 460e mov r6, r1 + c50: 4614 mov r4, r2 + ASSERT(rb && buf && size); + c52: 4605 mov r5, r0 + c54: b118 cbz r0, c5e + c56: b189 cbz r1, c7c + c58: 1e10 subs r0, r2, #0 + c5a: bf18 it ne + c5c: 2001 movne r0, #1 + c5e: 4908 ldr r1, [pc, #32] ; (c80 ) + c60: 4b08 ldr r3, [pc, #32] ; (c84 ) + c62: 2228 movs r2, #40 ; 0x28 + c64: 4798 blx r3 + + /* + * buf size must be aligned to power of 2 + */ + if ((size & (size - 1)) != 0) { + c66: 1e63 subs r3, r4, #1 + c68: ea13 0004 ands.w r0, r3, r4 + return ERR_INVALID_ARG; + } + + /* size - 1 is faster in calculation */ + rb->size = size - 1; + rb->read_index = 0; + c6c: bf03 ittte eq + c6e: e9c5 3001 strdeq r3, r0, [r5, #4] + rb->write_index = rb->read_index; + c72: 60e8 streq r0, [r5, #12] + rb->buf = (uint8_t *)buf; + c74: 602e streq r6, [r5, #0] + return ERR_INVALID_ARG; + c76: f06f 000c mvnne.w r0, #12 + + return ERR_NONE; +} + c7a: bd70 pop {r4, r5, r6, pc} + ASSERT(rb && buf && size); + c7c: 4608 mov r0, r1 + c7e: e7ee b.n c5e + c80: 00016412 .word 0x00016412 + c84: 00000655 .word 0x00000655 + +00000c88 : +/** + * \brief Get one byte from ringbuffer + * + */ +int32_t ringbuffer_get(struct ringbuffer *const rb, uint8_t *data) +{ + c88: b538 push {r3, r4, r5, lr} + c8a: 460d mov r5, r1 + ASSERT(rb && data); + c8c: 4604 mov r4, r0 + c8e: b110 cbz r0, c96 + c90: 1e08 subs r0, r1, #0 + c92: bf18 it ne + c94: 2001 movne r0, #1 + c96: 4b0a ldr r3, [pc, #40] ; (cc0 ) + c98: 490a ldr r1, [pc, #40] ; (cc4 ) + c9a: 2240 movs r2, #64 ; 0x40 + c9c: 4798 blx r3 + + if (rb->write_index != rb->read_index) { + c9e: e9d4 3202 ldrd r3, r2, [r4, #8] + ca2: 429a cmp r2, r3 + ca4: d009 beq.n cba + *data = rb->buf[rb->read_index & rb->size]; + ca6: 6862 ldr r2, [r4, #4] + ca8: 4013 ands r3, r2 + caa: 6822 ldr r2, [r4, #0] + cac: 5cd3 ldrb r3, [r2, r3] + cae: 702b strb r3, [r5, #0] + rb->read_index++; + cb0: 68a3 ldr r3, [r4, #8] + cb2: 3301 adds r3, #1 + cb4: 60a3 str r3, [r4, #8] + return ERR_NONE; + cb6: 2000 movs r0, #0 + } + + return ERR_NOT_FOUND; +} + cb8: bd38 pop {r3, r4, r5, pc} + return ERR_NOT_FOUND; + cba: f06f 0009 mvn.w r0, #9 + cbe: e7fb b.n cb8 + cc0: 00000655 .word 0x00000655 + cc4: 00016412 .word 0x00016412 + +00000cc8 : +/** + * \brief Put one byte to ringbuffer + * + */ +int32_t ringbuffer_put(struct ringbuffer *const rb, uint8_t data) +{ + cc8: b538 push {r3, r4, r5, lr} + cca: 4604 mov r4, r0 + ccc: 460d mov r5, r1 + ASSERT(rb); + cce: 4b0c ldr r3, [pc, #48] ; (d00 ) + cd0: 490c ldr r1, [pc, #48] ; (d04 ) + cd2: 2251 movs r2, #81 ; 0x51 + cd4: 2001 movs r0, #1 + cd6: 4798 blx r3 + + rb->buf[rb->write_index & rb->size] = data; + cd8: 68e3 ldr r3, [r4, #12] + cda: 6862 ldr r2, [r4, #4] + cdc: 4013 ands r3, r2 + cde: 6822 ldr r2, [r4, #0] + ce0: 54d5 strb r5, [r2, r3] + + /* + * buffer full strategy: new data will overwrite the oldest data in + * the buffer + */ + if ((rb->write_index - rb->read_index) > rb->size) { + ce2: e9d4 2101 ldrd r2, r1, [r4, #4] + ce6: 68e3 ldr r3, [r4, #12] + ce8: 1a59 subs r1, r3, r1 + cea: 4291 cmp r1, r2 + rb->read_index = rb->write_index - rb->size; + cec: bf88 it hi + cee: 1a9a subhi r2, r3, r2 + } + + rb->write_index++; + cf0: f103 0301 add.w r3, r3, #1 + rb->read_index = rb->write_index - rb->size; + cf4: bf88 it hi + cf6: 60a2 strhi r2, [r4, #8] + rb->write_index++; + cf8: 60e3 str r3, [r4, #12] + + return ERR_NONE; +} + cfa: 2000 movs r0, #0 + cfc: bd38 pop {r3, r4, r5, pc} + cfe: bf00 nop + d00: 00000655 .word 0x00000655 + d04: 00016412 .word 0x00016412 + +00000d08 : + +/** + * \brief Return the element number of ringbuffer + */ +uint32_t ringbuffer_num(const struct ringbuffer *const rb) +{ + d08: b510 push {r4, lr} + ASSERT(rb); + d0a: 4905 ldr r1, [pc, #20] ; (d20 ) + d0c: 4b05 ldr r3, [pc, #20] ; (d24 ) +{ + d0e: 4604 mov r4, r0 + ASSERT(rb); + d10: 2267 movs r2, #103 ; 0x67 + d12: 2001 movs r0, #1 + d14: 4798 blx r3 + + return rb->write_index - rb->read_index; + d16: e9d4 3002 ldrd r3, r0, [r4, #8] +} + d1a: 1ac0 subs r0, r0, r3 + d1c: bd10 pop {r4, pc} + d1e: bf00 nop + d20: 00016412 .word 0x00016412 + d24: 00000655 .word 0x00000655 + +00000d28 : +typedef uint8_t hri_tccount8_per_reg_t; +typedef uint8_t hri_tccount8_perbuf_reg_t; + +static inline void hri_tc_wait_for_sync(const void *const hw, hri_tc_syncbusy_reg_t reg) +{ + while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) { + d28: 6903 ldr r3, [r0, #16] + d2a: 420b tst r3, r1 + d2c: d1fc bne.n d28 + }; +} + d2e: 4770 bx lr + +00000d30 : + * \param[in] hw The pointer to hardware instance + * + * \return The index of TC configuration + */ +static int8_t get_tc_index(const void *const hw) +{ + d30: b570 push {r4, r5, r6, lr} + * \param[in] hw The pointer to hardware instance + */ +static inline uint8_t _get_hardware_offset(const void *const hw) +{ + /* List of available TC modules. */ + Tc *const tc_modules[TC_INST_NUM] = TC_INSTS; + d32: 4d10 ldr r5, [pc, #64] ; (d74 ) +{ + d34: 4606 mov r6, r0 + Tc *const tc_modules[TC_INST_NUM] = TC_INSTS; + d36: cd0f ldmia r5!, {r0, r1, r2, r3} +{ + d38: b088 sub sp, #32 + Tc *const tc_modules[TC_INST_NUM] = TC_INSTS; + d3a: 466c mov r4, sp + d3c: c40f stmia r4!, {r0, r1, r2, r3} + d3e: e895 000f ldmia.w r5, {r0, r1, r2, r3} + d42: e884 000f stmia.w r4, {r0, r1, r2, r3} + + /* Find index for TC instance. */ + for (uint32_t i = 0; i < TC_INST_NUM; i++) { + d46: 466a mov r2, sp + d48: 2000 movs r0, #0 + if ((uint32_t)hw == (uint32_t)tc_modules[i]) { + d4a: f852 1b04 ldr.w r1, [r2], #4 + d4e: 42b1 cmp r1, r6 + d50: d102 bne.n d58 + if (_tcs[i].number == index) { + d52: b930 cbnz r0, d62 +} + d54: b008 add sp, #32 + d56: bd70 pop {r4, r5, r6, pc} + for (uint32_t i = 0; i < TC_INST_NUM; i++) { + d58: 3001 adds r0, #1 + d5a: 2808 cmp r0, #8 + d5c: d1f5 bne.n d4a + return i; + d5e: 2000 movs r0, #0 + d60: e7f8 b.n d54 + ASSERT(false); + d62: 2000 movs r0, #0 + d64: 4904 ldr r1, [pc, #16] ; (d78 ) + d66: 4b05 ldr r3, [pc, #20] ; (d7c ) + d68: f44f 729e mov.w r2, #316 ; 0x13c + d6c: 4798 blx r3 + d6e: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + d72: e7ef b.n d54 + d74: 0001644c .word 0x0001644c + d78: 00016436 .word 0x00016436 + d7c: 00000655 .word 0x00000655 + +00000d80 <_timer_init>: +{ + d80: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + int8_t i = get_tc_index(hw); + d84: 4b45 ldr r3, [pc, #276] ; (e9c <_timer_init+0x11c>) +{ + d86: 4681 mov r9, r0 + int8_t i = get_tc_index(hw); + d88: 4608 mov r0, r1 +{ + d8a: 460c mov r4, r1 + int8_t i = get_tc_index(hw); + d8c: 4798 blx r3 + ASSERT(ARRAY_SIZE(_tcs)); + d8e: 4b44 ldr r3, [pc, #272] ; (ea0 <_timer_init+0x120>) + d90: 4944 ldr r1, [pc, #272] ; (ea4 <_timer_init+0x124>) + device->hw = hw; + d92: f8c9 400c str.w r4, [r9, #12] + ASSERT(ARRAY_SIZE(_tcs)); + d96: 228d movs r2, #141 ; 0x8d + int8_t i = get_tc_index(hw); + d98: 4680 mov r8, r0 + ASSERT(ARRAY_SIZE(_tcs)); + d9a: 2001 movs r0, #1 + d9c: 4798 blx r3 + +static inline bool hri_tc_is_syncing(const void *const hw, hri_tc_syncbusy_reg_t reg) +{ + return ((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg; + d9e: 6923 ldr r3, [r4, #16] + da0: 4a41 ldr r2, [pc, #260] ; (ea8 <_timer_init+0x128>) + if (!hri_tc_is_syncing(hw, TC_SYNCBUSY_SWRST)) { + da2: f013 0f01 tst.w r3, #1 + da6: d111 bne.n dcc <_timer_init+0x4c> +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + da8: 2103 movs r1, #3 + daa: 4620 mov r0, r4 + dac: 4790 blx r2 + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + dae: 6823 ldr r3, [r4, #0] + if (hri_tc_get_CTRLA_reg(hw, TC_CTRLA_ENABLE)) { + db0: 079b lsls r3, r3, #30 + db2: d506 bpl.n dc2 <_timer_init+0x42> + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE; + db4: 6823 ldr r3, [r4, #0] + db6: f023 0302 bic.w r3, r3, #2 + dba: 6023 str r3, [r4, #0] + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + dbc: 4790 blx r2 + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_ENABLE); + dbe: 2102 movs r1, #2 + dc0: 4790 blx r2 +} + +static inline void hri_tc_write_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg = data; + dc2: 2301 movs r3, #1 + dc4: 6023 str r3, [r4, #0] + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + dc6: 2103 movs r1, #3 + dc8: 4620 mov r0, r4 + dca: 4790 blx r2 + hri_tc_write_CTRLA_reg(hw, _tcs[i].ctrl_a); + dcc: 4f37 ldr r7, [pc, #220] ; (eac <_timer_init+0x12c>) + dce: 2514 movs r5, #20 + dd0: fb05 7508 mla r5, r5, r8, r7 + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); + dd4: 2101 movs r1, #1 + dd6: 4620 mov r0, r4 + dd8: 4790 blx r2 + hri_tc_write_CTRLA_reg(hw, _tcs[i].ctrl_a); + dda: 6a6e ldr r6, [r5, #36] ; 0x24 + ((Tc *)hw)->COUNT16.CTRLA.reg = data; + ddc: 6026 str r6, [r4, #0] + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + dde: 2103 movs r1, #3 + de0: 4790 blx r2 + hri_tc_write_DBGCTRL_reg(hw, _tcs[i].dbg_ctrl); + de2: f895 302a ldrb.w r3, [r5, #42] ; 0x2a +} + +static inline void hri_tc_write_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg = data; + de6: 73e3 strb r3, [r4, #15] + if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) { + de8: f006 060c and.w r6, r6, #12 + hri_tc_write_EVCTRL_reg(hw, _tcs[i].event_ctrl); + dec: 8d2b ldrh r3, [r5, #40] ; 0x28 + ((Tc *)hw)->COUNT16.EVCTRL.reg = data; + dee: 80e3 strh r3, [r4, #6] + if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) { + df0: 2e08 cmp r6, #8 + ((Tc *)hw)->COUNT16.WAVE.reg = data; + df2: f04f 0301 mov.w r3, #1 + df6: 7323 strb r3, [r4, #12] + df8: d13a bne.n e70 <_timer_init+0xf0> + hri_tccount32_write_CC_reg(hw, 0, _tcs[i].cc0); + dfa: 6aeb ldr r3, [r5, #44] ; 0x2c +} + +static inline void hri_tccount32_write_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg = data; + dfc: 61e3 str r3, [r4, #28] + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + dfe: 21c0 movs r1, #192 ; 0xc0 + e00: 4790 blx r2 + ((Tc *)hw)->COUNT32.CC[index].reg = data; + e02: 2300 movs r3, #0 + e04: 6223 str r3, [r4, #32] + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + e06: 4790 blx r2 + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF; + e08: 2301 movs r3, #1 + e0a: 7263 strb r3, [r4, #9] + if (hw == TC0) { + e0c: 4b28 ldr r3, [pc, #160] ; (eb0 <_timer_init+0x130>) + e0e: 429c cmp r4, r3 + _tc0_dev = (struct _timer_device *)dev; + e10: bf04 itt eq + e12: 4b28 ldreq r3, [pc, #160] ; (eb4 <_timer_init+0x134>) + e14: f8c3 9000 streq.w r9, [r3] + NVIC_DisableIRQ(_tcs[i].irq); + e18: 2314 movs r3, #20 + e1a: fb03 7308 mla r3, r3, r8, r7 + e1e: f9b3 3022 ldrsh.w r3, [r3, #34] ; 0x22 + if ((int32_t)(IRQn) >= 0) + e22: 2b00 cmp r3, #0 + e24: db0d blt.n e42 <_timer_init+0xc2> + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + e26: 095a lsrs r2, r3, #5 + e28: 2101 movs r1, #1 + e2a: f003 031f and.w r3, r3, #31 + e2e: 4099 lsls r1, r3 + e30: f102 0320 add.w r3, r2, #32 + e34: 4a20 ldr r2, [pc, #128] ; (eb8 <_timer_init+0x138>) + e36: f842 1023 str.w r1, [r2, r3, lsl #2] + __ASM volatile ("dsb 0xF":::"memory"); + e3a: f3bf 8f4f dsb sy + __ASM volatile ("isb 0xF":::"memory"); + e3e: f3bf 8f6f isb sy + NVIC_ClearPendingIRQ(_tcs[i].irq); + e42: 2314 movs r3, #20 + e44: fb03 7008 mla r0, r3, r8, r7 + e48: f9b0 3022 ldrsh.w r3, [r0, #34] ; 0x22 + if ((int32_t)(IRQn) >= 0) + e4c: 2b00 cmp r3, #0 + e4e: db0c blt.n e6a <_timer_init+0xea> + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + e50: f003 011f and.w r1, r3, #31 + e54: 095b lsrs r3, r3, #5 + e56: 009b lsls r3, r3, #2 + e58: f103 4360 add.w r3, r3, #3758096384 ; 0xe0000000 + e5c: f503 4361 add.w r3, r3, #57600 ; 0xe100 + e60: 2201 movs r2, #1 + e62: 408a lsls r2, r1 + e64: f8c3 2180 str.w r2, [r3, #384] ; 0x180 + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + e68: 601a str r2, [r3, #0] +} + e6a: 2000 movs r0, #0 + e6c: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + } else if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT16) { + e70: b92e cbnz r6, e7e <_timer_init+0xfe> + hri_tccount16_write_CC_reg(hw, 0, (uint16_t)_tcs[i].cc0); + e72: 8dab ldrh r3, [r5, #44] ; 0x2c + ((Tc *)hw)->COUNT16.CC[index].reg = data; + e74: 83a3 strh r3, [r4, #28] + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + e76: 21c0 movs r1, #192 ; 0xc0 + e78: 4790 blx r2 + ((Tc *)hw)->COUNT16.CC[index].reg = data; + e7a: 83e6 strh r6, [r4, #30] + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + e7c: e7c3 b.n e06 <_timer_init+0x86> + } else if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT8) { + e7e: 2e04 cmp r6, #4 + e80: d1c2 bne.n e08 <_timer_init+0x88> + hri_tccount8_write_CC_reg(hw, 0, (uint8_t)_tcs[i].cc0); + e82: f895 302c ldrb.w r3, [r5, #44] ; 0x2c + ((Tc *)hw)->COUNT8.CC[index].reg = data; + e86: 7723 strb r3, [r4, #28] + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + e88: 21c0 movs r1, #192 ; 0xc0 + e8a: 4790 blx r2 + ((Tc *)hw)->COUNT8.CC[index].reg = data; + e8c: 2300 movs r3, #0 + e8e: 7763 strb r3, [r4, #29] + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + e90: 4790 blx r2 + hri_tccount8_write_PER_reg(hw, _tcs[i].per); + e92: f895 302b ldrb.w r3, [r5, #43] ; 0x2b + ((Tc *)hw)->COUNT8.PER.reg = data; + e96: 76e3 strb r3, [r4, #27] + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + e98: 2120 movs r1, #32 + e9a: e7b4 b.n e06 <_timer_init+0x86> + e9c: 00000d31 .word 0x00000d31 + ea0: 00000655 .word 0x00000655 + ea4: 00016436 .word 0x00016436 + ea8: 00000d29 .word 0x00000d29 + eac: 0001644c .word 0x0001644c + eb0: 40003800 .word 0x40003800 + eb4: 200000ac .word 0x200000ac + eb8: e000e100 .word 0xe000e100 + +00000ebc <_timer_start>: + hri_tc_set_CTRLA_ENABLE_bit(device->hw); + ebc: 68c0 ldr r0, [r0, #12] + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ENABLE; + ebe: 6803 ldr r3, [r0, #0] + ec0: f043 0302 orr.w r3, r3, #2 + ec4: 6003 str r3, [r0, #0] + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + ec6: 2103 movs r1, #3 + ec8: 4b00 ldr r3, [pc, #0] ; (ecc <_timer_start+0x10>) + eca: 4718 bx r3 + ecc: 00000d29 .word 0x00000d29 + +00000ed0 <_timer_is_started>: +{ + ed0: b508 push {r3, lr} + return hri_tc_get_CTRLA_ENABLE_bit(device->hw); + ed2: 68c0 ldr r0, [r0, #12] + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + ed4: 4b03 ldr r3, [pc, #12] ; (ee4 <_timer_is_started+0x14>) + ed6: 2103 movs r1, #3 + ed8: 4798 blx r3 + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + eda: 6800 ldr r0, [r0, #0] +} + edc: f3c0 0040 ubfx r0, r0, #1, #1 + ee0: bd08 pop {r3, pc} + ee2: bf00 nop + ee4: 00000d29 .word 0x00000d29 + +00000ee8 <_tc_get_timer>: +} + ee8: 2000 movs r0, #0 + eea: 4770 bx lr + +00000eec <_timer_set_irq>: +{ + eec: b510 push {r4, lr} + int8_t i = get_tc_index(hw); + eee: 4b0a ldr r3, [pc, #40] ; (f18 <_timer_set_irq+0x2c>) + ef0: 68c0 ldr r0, [r0, #12] + ef2: 4798 blx r3 + ASSERT(ARRAY_SIZE(_tcs)); + ef4: 4b09 ldr r3, [pc, #36] ; (f1c <_timer_set_irq+0x30>) + ef6: 490a ldr r1, [pc, #40] ; (f20 <_timer_set_irq+0x34>) + int8_t i = get_tc_index(hw); + ef8: 4604 mov r4, r0 + ASSERT(ARRAY_SIZE(_tcs)); + efa: f240 120f movw r2, #271 ; 0x10f + efe: 2001 movs r0, #1 + f00: 4798 blx r3 + _irq_set(_tcs[i].irq); + f02: 4808 ldr r0, [pc, #32] ; (f24 <_timer_set_irq+0x38>) + f04: 4b08 ldr r3, [pc, #32] ; (f28 <_timer_set_irq+0x3c>) + f06: 2214 movs r2, #20 + f08: fb02 0004 mla r0, r2, r4, r0 +} + f0c: e8bd 4010 ldmia.w sp!, {r4, lr} + _irq_set(_tcs[i].irq); + f10: f890 0022 ldrb.w r0, [r0, #34] ; 0x22 + f14: 4718 bx r3 + f16: bf00 nop + f18: 00000d31 .word 0x00000d31 + f1c: 00000655 .word 0x00000655 + f20: 00016436 .word 0x00016436 + f24: 0001644c .word 0x0001644c + f28: 0000031d .word 0x0000031d + +00000f2c : + tc_interrupt_handler(_tc0_dev); + f2c: 4b05 ldr r3, [pc, #20] ; (f44 ) + f2e: 6818 ldr r0, [r3, #0] + void *const hw = device->hw; + f30: 68c3 ldr r3, [r0, #12] + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; + f32: 7a9a ldrb r2, [r3, #10] + if (hri_tc_get_interrupt_OVF_bit(hw)) { + f34: 07d2 lsls r2, r2, #31 + f36: d503 bpl.n f40 + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF; + f38: 2201 movs r2, #1 + f3a: 729a strb r2, [r3, #10] + device->timer_cb.period_expired(device); + f3c: 6803 ldr r3, [r0, #0] + f3e: 4718 bx r3 +} + f40: 4770 bx lr + f42: bf00 nop + f44: 200000ac .word 0x200000ac + +00000f48 : + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + f48: f3ef 8310 mrs r3, PRIMASK +/** + * \brief Disable interrupts, enter critical section + */ +void atomic_enter_critical(hal_atomic_t volatile *atomic) +{ + *atomic = __get_PRIMASK(); + f4c: 6003 str r3, [r0, #0] + __ASM volatile ("cpsid i" : : : "memory"); + f4e: b672 cpsid i + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); + f50: f3bf 8f5f dmb sy + __disable_irq(); + __DMB(); +} + f54: 4770 bx lr + +00000f56 : + f56: f3bf 8f5f dmb sy + * \brief Exit atomic section + */ +void atomic_leave_critical(hal_atomic_t volatile *atomic) +{ + __DMB(); + __set_PRIMASK(*atomic); + f5a: 6803 ldr r3, [r0, #0] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + f5c: f383 8810 msr PRIMASK, r3 +} + f60: 4770 bx lr + ... + +00000f64 : + * GPIO_DIRECTION_OFF = Disables the pin + * (low power state) + */ +static inline void gpio_set_pin_direction(const uint8_t pin, const enum gpio_direction direction) +{ + _gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction); + f64: 0943 lsrs r3, r0, #5 + f66: 2201 movs r2, #1 + f68: f000 001f and.w r0, r0, #31 + * \brief Set direction on port with mask + */ +static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction) +{ + switch (direction) { + f6c: 2901 cmp r1, #1 + f6e: fa02 f200 lsl.w r2, r2, r0 + f72: d010 beq.n f96 + f74: 2902 cmp r1, #2 + f76: d01f beq.n fb8 + f78: bb29 cbnz r1, fc6 + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~data; +} + +static inline void hri_port_clear_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask; + f7a: 01db lsls r3, r3, #7 + f7c: f103 4382 add.w r3, r3, #1090519040 ; 0x41000000 + f80: f503 4300 add.w r3, r3, #32768 ; 0x8000 + f84: 605a str r2, [r3, #4] + | ((mask & 0xffff0000) >> 16)); + break; + + case GPIO_DIRECTION_OUT: + hri_port_set_DIR_reg(PORT, port, mask); + hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); + f86: b291 uxth r1, r2 + f88: f041 4180 orr.w r1, r1, #1073741824 ; 0x40000000 + hri_port_write_WRCONFIG_reg( + PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); + f8c: 0c12 lsrs r2, r2, #16 + +static inline void hri_port_write_WRCONFIG_reg(const void *const hw, uint8_t submodule_index, + hri_port_wrconfig_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; + f8e: 6299 str r1, [r3, #40] ; 0x28 + hri_port_write_WRCONFIG_reg( + f90: f042 4240 orr.w r2, r2, #3221225472 ; 0xc0000000 + f94: e00e b.n fb4 + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask; + f96: 01db lsls r3, r3, #7 + hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN | (mask & 0xffff)); + f98: b291 uxth r1, r2 + f9a: f103 4382 add.w r3, r3, #1090519040 ; 0x41000000 + f9e: f503 4300 add.w r3, r3, #32768 ; 0x8000 + fa2: f041 4180 orr.w r1, r1, #1073741824 ; 0x40000000 + fa6: f441 3100 orr.w r1, r1, #131072 ; 0x20000 + faa: 605a str r2, [r3, #4] + ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; + fac: 6299 str r1, [r3, #40] ; 0x28 + hri_port_write_WRCONFIG_reg(PORT, + fae: 4908 ldr r1, [pc, #32] ; (fd0 ) + fb0: ea41 4212 orr.w r2, r1, r2, lsr #16 + fb4: 629a str r2, [r3, #40] ; 0x28 +} + fb6: 4770 bx lr + ((Port *)hw)->Group[submodule_index].DIRSET.reg = mask; + fb8: 01db lsls r3, r3, #7 + fba: f103 4382 add.w r3, r3, #1090519040 ; 0x41000000 + fbe: f503 4300 add.w r3, r3, #32768 ; 0x8000 + fc2: 609a str r2, [r3, #8] + fc4: e7df b.n f86 + break; + + default: + ASSERT(false); + fc6: 4903 ldr r1, [pc, #12] ; (fd4 ) + fc8: 4b03 ldr r3, [pc, #12] ; (fd8 ) + fca: 2246 movs r2, #70 ; 0x46 + fcc: 2000 movs r0, #0 + fce: 4718 bx r3 + fd0: c0020000 .word 0xc0020000 + fd4: 00016480 .word 0x00016480 + fd8: 00000655 .word 0x00000655 + +00000fdc <_gpio_set_pin_function>: + +/** + * \brief Set gpio pin function + */ +static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function) +{ + fdc: b530 push {r4, r5, lr} + uint8_t port = GPIO_PORT(gpio); + uint8_t pin = GPIO_PIN(gpio); + + if (function == GPIO_PIN_FUNCTION_OFF) { + fde: 1c4b adds r3, r1, #1 + uint8_t pin = GPIO_PIN(gpio); + fe0: b2c5 uxtb r5, r0 + fe2: 4b18 ldr r3, [pc, #96] ; (1044 <_gpio_set_pin_function+0x68>) + fe4: f000 041f and.w r4, r0, #31 + uint8_t port = GPIO_PORT(gpio); + fe8: ea4f 1050 mov.w r0, r0, lsr #5 + fec: ea4f 10c0 mov.w r0, r0, lsl #7 + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + ff0: 4403 add r3, r0 + if (function == GPIO_PIN_FUNCTION_OFF) { + ff2: d107 bne.n 1004 <_gpio_set_pin_function+0x28> + ff4: 4423 add r3, r4 + ff6: f893 2040 ldrb.w r2, [r3, #64] ; 0x40 + tmp &= ~PORT_PINCFG_PMUXEN; + ffa: f002 02fe and.w r2, r2, #254 ; 0xfe + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + ffe: f883 2040 strb.w r2, [r3, #64] ; 0x40 + } else { + // Even numbered pin + hri_port_write_PMUX_PMUXE_bf(PORT, port, pin >> 1, function & 0xffff); + } + } +} + 1002: bd30 pop {r4, r5, pc} + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + 1004: 1918 adds r0, r3, r4 + 1006: eb03 0354 add.w r3, r3, r4, lsr #1 + 100a: f890 2040 ldrb.w r2, [r0, #64] ; 0x40 + tmp &= ~PORT_PINCFG_PMUXEN; + 100e: f002 02fe and.w r2, r2, #254 ; 0xfe + tmp |= value << PORT_PINCFG_PMUXEN_Pos; + 1012: f042 0201 orr.w r2, r2, #1 + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + 1016: f880 2040 strb.w r2, [r0, #64] ; 0x40 + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + 101a: f893 2030 ldrb.w r2, [r3, #48] ; 0x30 + if (pin & 1) { + 101e: f015 0f01 tst.w r5, #1 + hri_port_write_PMUX_PMUXO_bf(PORT, port, pin >> 1, function & 0xffff); + 1022: b2c9 uxtb r1, r1 + tmp &= ~PORT_PMUX_PMUXO_Msk; + 1024: bf19 ittee ne + 1026: f002 020f andne.w r2, r2, #15 + tmp |= PORT_PMUX_PMUXO(data); + 102a: ea42 1201 orrne.w r2, r2, r1, lsl #4 + tmp &= ~PORT_PMUX_PMUXE_Msk; + 102e: f002 02f0 andeq.w r2, r2, #240 ; 0xf0 + tmp |= PORT_PMUX_PMUXE(data); + 1032: f001 010f andeq.w r1, r1, #15 + tmp |= PORT_PMUX_PMUXO(data); + 1036: bf14 ite ne + 1038: b2d2 uxtbne r2, r2 + tmp |= PORT_PMUX_PMUXE(data); + 103a: 430a orreq r2, r1 + ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; + 103c: f883 2030 strb.w r2, [r3, #48] ; 0x30 +} + 1040: e7df b.n 1002 <_gpio_set_pin_function+0x26> + 1042: bf00 nop + 1044: 41008000 .word 0x41008000 + +00001048 : + switch (pull_mode) { + 1048: 2901 cmp r1, #1 + _gpio_set_pin_pull_mode((enum gpio_port)GPIO_PORT(pin), pin & 0x1F, pull_mode); + 104a: ea4f 1350 mov.w r3, r0, lsr #5 + 104e: f000 001f and.w r0, r0, #31 + 1052: d00f beq.n 1074 + 1054: 2902 cmp r1, #2 + 1056: d01d beq.n 1094 + 1058: bb69 cbnz r1, 10b6 + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; + 105a: eb00 10c3 add.w r0, r0, r3, lsl #7 + 105e: f100 4082 add.w r0, r0, #1090519040 ; 0x41000000 + 1062: f500 4000 add.w r0, r0, #32768 ; 0x8000 + 1066: f890 3040 ldrb.w r3, [r0, #64] ; 0x40 + 106a: f003 03fb and.w r3, r3, #251 ; 0xfb + 106e: f880 3040 strb.w r3, [r0, #64] ; 0x40 +} + 1072: 4770 bx lr + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask; + 1074: 01db lsls r3, r3, #7 + 1076: f103 4382 add.w r3, r3, #1090519040 ; 0x41000000 + 107a: f503 4300 add.w r3, r3, #32768 ; 0x8000 + hri_port_clear_DIR_reg(PORT, port, 1U << pin); + 107e: 4081 lsls r1, r0 + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PULLEN; + 1080: 4418 add r0, r3 + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask; + 1082: 6059 str r1, [r3, #4] + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PULLEN; + 1084: f890 2040 ldrb.w r2, [r0, #64] ; 0x40 + 1088: f042 0204 orr.w r2, r2, #4 + 108c: f880 2040 strb.w r2, [r0, #64] ; 0x40 + ((Port *)hw)->Group[submodule_index].OUTSET.reg = mask; + 1090: 6199 str r1, [r3, #24] +} + 1092: 4770 bx lr + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask; + 1094: 01db lsls r3, r3, #7 + 1096: f103 4382 add.w r3, r3, #1090519040 ; 0x41000000 + 109a: f503 4300 add.w r3, r3, #32768 ; 0x8000 + hri_port_clear_DIR_reg(PORT, port, 1U << pin); + 109e: 2201 movs r2, #1 + 10a0: 4082 lsls r2, r0 + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PULLEN; + 10a2: 4418 add r0, r3 + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask; + 10a4: 605a str r2, [r3, #4] + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PULLEN; + 10a6: f890 1040 ldrb.w r1, [r0, #64] ; 0x40 + 10aa: f041 0104 orr.w r1, r1, #4 + 10ae: f880 1040 strb.w r1, [r0, #64] ; 0x40 + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask; + 10b2: 615a str r2, [r3, #20] +} + 10b4: 4770 bx lr + ASSERT(false); + 10b6: 4902 ldr r1, [pc, #8] ; (10c0 ) + 10b8: 4b02 ldr r3, [pc, #8] ; (10c4 ) + 10ba: 2289 movs r2, #137 ; 0x89 + 10bc: 2000 movs r0, #0 + 10be: 4718 bx r3 + 10c0: 00016480 .word 0x00016480 + 10c4: 00000655 .word 0x00000655 + +000010c8 : + } +} + +void p_gpio_set_port_data(PortGroup* const port, const uint32_t mask, const uint32_t data) +{ + uint32_t dword = (uint32_t)(SSD1963_TFT_DATA_FIX(data)); + 10c8: 0053 lsls r3, r2, #1 +{ + 10ca: b510 push {r4, lr} + uint32_t dword = (uint32_t)(SSD1963_TFT_DATA_FIX(data)); + 10cc: 0154 lsls r4, r2, #5 + 10ce: f404 3470 and.w r4, r4, #245760 ; 0x3c000 + 10d2: f403 737c and.w r3, r3, #1008 ; 0x3f0 + 10d6: 4323 orrs r3, r4 + 10d8: f002 0407 and.w r4, r2, #7 + 10dc: 0352 lsls r2, r2, #13 + 10de: f002 52e0 and.w r2, r2, #469762048 ; 0x1c000000 + 10e2: 4323 orrs r3, r4 + 10e4: 4313 orrs r3, r2 + port->OUTSET.reg = (mask & dword); + 10e6: ea03 0201 and.w r2, r3, r1 + port->OUTCLR.reg = (mask & ~dword); + 10ea: ea21 0103 bic.w r1, r1, r3 + port->OUTSET.reg = (mask & dword); + 10ee: 6182 str r2, [r0, #24] + port->OUTCLR.reg = (mask & ~dword); + 10f0: 6141 str r1, [r0, #20] +} + 10f2: bd10 pop {r4, pc} + +000010f4 : +{ + 10f4: b538 push {r3, r4, r5, lr} + 10f6: 4c05 ldr r4, [pc, #20] ; (110c ) + p_gpio_set_port_data(group, mask, (uint32_t)data); + 10f8: 4b05 ldr r3, [pc, #20] ; (1110 ) + 10fa: 2540 movs r5, #64 ; 0x40 + 10fc: 6165 str r5, [r4, #20] + 10fe: 4798 blx r3 + 1100: 2380 movs r3, #128 ; 0x80 + 1102: 6163 str r3, [r4, #20] + ((Port *)hw)->Group[submodule_index].OUTSET.reg = mask; + 1104: 61a3 str r3, [r4, #24] + 1106: 61a5 str r5, [r4, #24] +} + 1108: bd38 pop {r3, r4, r5, pc} + 110a: bf00 nop + 110c: 41008000 .word 0x41008000 + 1110: 000010c9 .word 0x000010c9 + +00001114 : +{ + 1114: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + p_gpio_parallel_write(group, mask, data[ind]); + 1118: 4f07 ldr r7, [pc, #28] ; (1138 ) +{ + 111a: 4688 mov r8, r1 + 111c: 4616 mov r6, r2 + 111e: 461d mov r5, r3 + for(int ind = 0; ind < len; ind++) + 1120: 2400 movs r4, #0 + 1122: 42a5 cmp r5, r4 + 1124: dc01 bgt.n 112a +} + 1126: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + p_gpio_parallel_write(group, mask, data[ind]); + 112a: f836 2014 ldrh.w r2, [r6, r4, lsl #1] + 112e: 4641 mov r1, r8 + 1130: 47b8 blx r7 + for(int ind = 0; ind < len; ind++) + 1132: 3401 adds r4, #1 + 1134: e7f5 b.n 1122 + 1136: bf00 nop + 1138: 000010f5 .word 0x000010f5 + +0000113c : + +void p_gpio_set_port_group_config(enum gpio_port port, const uint32_t mask, p_port_config* config) +{ + 113c: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} + for(uint8_t i = 0; i < 32; i++) + { + if(mask & (1UL << i)) + { + uint32_t _gpio_pin = GPIO(port, i); + 1140: 0147 lsls r7, r0, #5 + gpio_set_pin_direction(_gpio_pin, config->direction); + 1142: 4b15 ldr r3, [pc, #84] ; (1198 ) + _gpio_set_pin_function(pin, function); + 1144: f8df a058 ldr.w sl, [pc, #88] ; 11a0 +{ + 1148: 4688 mov r8, r1 + 114a: 4616 mov r6, r2 + uint32_t _gpio_pin = GPIO(port, i); + 114c: fa5f fb87 uxtb.w fp, r7 + 1150: 2500 movs r5, #0 + if(mask & (1UL << i)) + 1152: fa28 f205 lsr.w r2, r8, r5 + 1156: 07d2 lsls r2, r2, #31 + 1158: d519 bpl.n 118e + uint32_t _gpio_pin = GPIO(port, i); + 115a: 19ec adds r4, r5, r7 + 115c: b2e4 uxtb r4, r4 + gpio_set_pin_direction(_gpio_pin, config->direction); + 115e: 4620 mov r0, r4 + 1160: 7871 ldrb r1, [r6, #1] + 1162: 4798 blx r3 + 1164: eb0b 0905 add.w r9, fp, r5 + gpio_set_pin_pull_mode(_gpio_pin, config->pull_mode); + 1168: 4b0c ldr r3, [pc, #48] ; (119c ) + 116a: 7831 ldrb r1, [r6, #0] + 116c: 4620 mov r0, r4 + 116e: 4798 blx r3 + 1170: 6871 ldr r1, [r6, #4] + 1172: 4648 mov r0, r9 + 1174: 47d0 blx sl + * \param[in] level true = Pin level set to "high" state + * false = Pin level set to "low" state + */ +static inline void gpio_set_pin_level(const uint8_t pin, const bool level) +{ + _gpio_set_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), level); + 1176: f004 011f and.w r1, r4, #31 + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask; + 117a: 0964 lsrs r4, r4, #5 + 117c: 01e4 lsls r4, r4, #7 + 117e: f104 4482 add.w r4, r4, #1090519040 ; 0x41000000 + 1182: 2201 movs r2, #1 + 1184: f504 4400 add.w r4, r4, #32768 ; 0x8000 + 1188: 408a lsls r2, r1 + 118a: 4b03 ldr r3, [pc, #12] ; (1198 ) + 118c: 6162 str r2, [r4, #20] + for(uint8_t i = 0; i < 32; i++) + 118e: 3501 adds r5, #1 + 1190: 2d20 cmp r5, #32 + 1192: d1de bne.n 1152 + gpio_set_pin_function(_gpio_pin, config->function); + gpio_set_pin_level(_gpio_pin, 0); + } + + } +} + 1194: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} + 1198: 00000f65 .word 0x00000f65 + 119c: 00001049 .word 0x00001049 + 11a0: 00000fdd .word 0x00000fdd + +000011a4 : +{ + 11a4: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr} + memset(&data_config, 0, sizeof(data_config)); + 11a8: f04f 0900 mov.w r9, #0 + p_gpio_set_port_group_config(SSD1963_TFT_DATA_PORT, SSD1963_TFT_DATA_MASK, &data_config); + 11ac: 466a mov r2, sp + 11ae: 4b29 ldr r3, [pc, #164] ; (1254 ) + memset(&data_config, 0, sizeof(data_config)); + 11b0: f8cd 9000 str.w r9, [sp] + data_config.direction = GPIO_DIRECTION_OUT; + 11b4: 2502 movs r5, #2 + data_config.function = GPIO_PIN_FUNCTION_OFF; + 11b6: f04f 34ff mov.w r4, #4294967295 ; 0xffffffff + p_gpio_set_port_group_config(SSD1963_TFT_DATA_PORT, SSD1963_TFT_DATA_MASK, &data_config); + 11ba: 4927 ldr r1, [pc, #156] ; (1258 ) + gpio_set_pin_direction(SSD1963_TFT_CS, GPIO_DIRECTION_OUT); + 11bc: f8df 80a8 ldr.w r8, [pc, #168] ; 1268 + data_config.direction = GPIO_DIRECTION_OUT; + 11c0: f88d 5001 strb.w r5, [sp, #1] + p_gpio_set_port_group_config(SSD1963_TFT_DATA_PORT, SSD1963_TFT_DATA_MASK, &data_config); + 11c4: 2001 movs r0, #1 + data_config.function = GPIO_PIN_FUNCTION_OFF; + 11c6: 9401 str r4, [sp, #4] + p_gpio_set_port_group_config(SSD1963_TFT_DATA_PORT, SSD1963_TFT_DATA_MASK, &data_config); + 11c8: 4798 blx r3 + gpio_set_pin_direction(SSD1963_TFT_CS, GPIO_DIRECTION_OUT); + 11ca: 4629 mov r1, r5 + 11cc: 2006 movs r0, #6 + gpio_set_pin_pull_mode(SSD1963_TFT_CS, GPIO_PULL_OFF); + 11ce: 4f23 ldr r7, [pc, #140] ; (125c ) + _gpio_set_pin_function(pin, function); + 11d0: 4e23 ldr r6, [pc, #140] ; (1260 ) + gpio_set_pin_direction(SSD1963_TFT_CS, GPIO_DIRECTION_OUT); + 11d2: 47c0 blx r8 + gpio_set_pin_pull_mode(SSD1963_TFT_CS, GPIO_PULL_OFF); + 11d4: 4649 mov r1, r9 + 11d6: 2006 movs r0, #6 + 11d8: 47b8 blx r7 + 11da: 4621 mov r1, r4 + 11dc: 2006 movs r0, #6 + 11de: 47b0 blx r6 + gpio_set_pin_direction(SSD1963_TFT_nRST, GPIO_DIRECTION_OUT); + 11e0: 4629 mov r1, r5 + 11e2: 2004 movs r0, #4 + 11e4: 47c0 blx r8 + gpio_set_pin_pull_mode(SSD1963_TFT_nRST, GPIO_PULL_OFF); + 11e6: 4649 mov r1, r9 + 11e8: 2004 movs r0, #4 + 11ea: 47b8 blx r7 + 11ec: 4621 mov r1, r4 + 11ee: 2004 movs r0, #4 + 11f0: 47b0 blx r6 + gpio_set_pin_direction(SSD1963_TFT_RD, GPIO_DIRECTION_OUT); + 11f2: 4629 mov r1, r5 + 11f4: 2003 movs r0, #3 + 11f6: 47c0 blx r8 + gpio_set_pin_pull_mode(SSD1963_TFT_RD, GPIO_PULL_OFF); + 11f8: 4649 mov r1, r9 + 11fa: 2003 movs r0, #3 + 11fc: 47b8 blx r7 + 11fe: 4621 mov r1, r4 + 1200: 2003 movs r0, #3 + 1202: 47b0 blx r6 + gpio_set_pin_direction(SSD1963_TFT_RSDC, GPIO_DIRECTION_OUT); + 1204: 4629 mov r1, r5 + 1206: 2005 movs r0, #5 + 1208: 47c0 blx r8 + gpio_set_pin_pull_mode(SSD1963_TFT_RSDC, GPIO_PULL_OFF); + 120a: 4649 mov r1, r9 + 120c: 2005 movs r0, #5 + 120e: 47b8 blx r7 + 1210: 4621 mov r1, r4 + 1212: 2005 movs r0, #5 + 1214: 47b0 blx r6 + gpio_set_pin_direction(SSD1963_TFT_WR, GPIO_DIRECTION_OUT); + 1216: 4629 mov r1, r5 + 1218: 2007 movs r0, #7 + 121a: 47c0 blx r8 + gpio_set_pin_pull_mode(SSD1963_TFT_WR, GPIO_PULL_OFF); + 121c: 4649 mov r1, r9 + 121e: 2007 movs r0, #7 + 1220: 47b8 blx r7 + 1222: 4621 mov r1, r4 + 1224: 2007 movs r0, #7 + 1226: 47b0 blx r6 + gpio_set_pin_direction(SSD1963_TFT_TE, GPIO_DIRECTION_IN); + 1228: 2101 movs r1, #1 + 122a: 2068 movs r0, #104 ; 0x68 + 122c: 47c0 blx r8 + gpio_set_pin_pull_mode(SSD1963_TFT_TE, GPIO_PULL_DOWN); + 122e: 4629 mov r1, r5 + 1230: 2068 movs r0, #104 ; 0x68 + 1232: 47b8 blx r7 + 1234: 4621 mov r1, r4 + 1236: 2068 movs r0, #104 ; 0x68 + 1238: 47b0 blx r6 + ((Port *)hw)->Group[submodule_index].OUTSET.reg = mask; + 123a: 4b0a ldr r3, [pc, #40] ; (1264 ) + 123c: 2240 movs r2, #64 ; 0x40 + 123e: 619a str r2, [r3, #24] + 1240: 2210 movs r2, #16 + 1242: 619a str r2, [r3, #24] + 1244: 2208 movs r2, #8 + 1246: 619a str r2, [r3, #24] + 1248: 2280 movs r2, #128 ; 0x80 + 124a: 619a str r2, [r3, #24] +} + 124c: b003 add sp, #12 + 124e: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + 1252: bf00 nop + 1254: 0000113d .word 0x0000113d + 1258: 1c03c3f7 .word 0x1c03c3f7 + 125c: 00001049 .word 0x00001049 + 1260: 00000fdd .word 0x00000fdd + 1264: 41008000 .word 0x41008000 + 1268: 00000f65 .word 0x00000f65 + +0000126c : + //// port init + //gpio_set_pin_pull_mode(I2C_MASTER_SDA, GPIO_PULL_OFF); + //gpio_set_pin_function(I2C_MASTER_SDA, I2C_MASTER_SDA_MUX); + //gpio_set_pin_pull_mode(I2C_MASTER_SCL, GPIO_PULL_OFF); + //gpio_set_pin_function(I2C_MASTER_SCL, I2C_MASTER_SCL_MUX); +} + 126c: 4770 bx lr + ... + +00001270 : +static volatile uint64_t sys_time = 0; +/** + * Example of using TIMER_0. + */ +static void TIMER_0_task1_cb(const struct timer_task *const timer_task) +{ + 1270: b410 push {r4} + sys_time++; + 1272: 4c06 ldr r4, [pc, #24] ; (128c ) + 1274: e9d4 2300 ldrd r2, r3, [r4] + 1278: 1c50 adds r0, r2, #1 + 127a: f143 0100 adc.w r1, r3, #0 + 127e: e9c4 0100 strd r0, r1, [r4] + lv_tick_inc(1); + 1282: 4b03 ldr r3, [pc, #12] ; (1290 ) +} + 1284: f85d 4b04 ldr.w r4, [sp], #4 + lv_tick_inc(1); + 1288: 2001 movs r0, #1 + 128a: 4718 bx r3 + 128c: 200000b0 .word 0x200000b0 + 1290: 0000da35 .word 0x0000da35 + +00001294 : + //timer_add_task(&p_tcc_inst, &TIMER_0_task2); + timer_start(&p_tcc_inst); +} + +void p_tcc_init(void) +{ + 1294: b570 push {r4, r5, r6, lr} + delay_init(SysTick); + 1296: 4812 ldr r0, [pc, #72] ; (12e0 ) + 1298: 4b12 ldr r3, [pc, #72] ; (12e4 ) + hri_mclk_set_APBAMASK_TC0_bit(MCLK); + hri_gclk_write_PCHCTRL_reg(GCLK, TC0_GCLK_ID, CONF_GCLK_TC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + + timer_init(&p_tcc_inst, TC0, _tc_get_timer()); + 129a: 4c13 ldr r4, [pc, #76] ; (12e8 ) + delay_init(SysTick); + 129c: 4798 blx r3 +} + +static inline void hri_mclk_set_APBAMASK_TC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_TC0; + 129e: 4a13 ldr r2, [pc, #76] ; (12ec ) + 12a0: 6953 ldr r3, [r2, #20] + 12a2: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 12a6: 6153 str r3, [r2, #20] +} + +static inline void hri_gclk_write_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg = data; + 12a8: 4b11 ldr r3, [pc, #68] ; (12f0 ) + 12aa: 2240 movs r2, #64 ; 0x40 + 12ac: f8c3 20a4 str.w r2, [r3, #164] ; 0xa4 + timer_init(&p_tcc_inst, TC0, _tc_get_timer()); + 12b0: 4b10 ldr r3, [pc, #64] ; (12f4 ) + 12b2: 4798 blx r3 + 12b4: f104 051c add.w r5, r4, #28 + 12b8: 4602 mov r2, r0 + 12ba: 490f ldr r1, [pc, #60] ; (12f8 ) + 12bc: 4b0f ldr r3, [pc, #60] ; (12fc ) + 12be: 4628 mov r0, r5 + 12c0: 4798 blx r3 + + TIMER_0_task1.interval = 1; + 12c2: 2301 movs r3, #1 + 12c4: 6123 str r3, [r4, #16] + TIMER_0_task1.cb = TIMER_0_task1_cb; + TIMER_0_task1.mode = TIMER_TASK_REPEAT; + 12c6: 7623 strb r3, [r4, #24] + TIMER_0_task1.cb = TIMER_0_task1_cb; + 12c8: 4a0d ldr r2, [pc, #52] ; (1300 ) + //TIMER_0_task2.interval = 200; + //TIMER_0_task2.cb = TIMER_0_task2_cb; + //TIMER_0_task2.mode = TIMER_TASK_REPEAT; + + timer_add_task(&p_tcc_inst, &TIMER_0_task1); + 12ca: 4b0e ldr r3, [pc, #56] ; (1304 ) + TIMER_0_task1.cb = TIMER_0_task1_cb; + 12cc: 6162 str r2, [r4, #20] + timer_add_task(&p_tcc_inst, &TIMER_0_task1); + 12ce: f104 0108 add.w r1, r4, #8 + 12d2: 4628 mov r0, r5 + 12d4: 4798 blx r3 + //timer_add_task(&p_tcc_inst, &TIMER_0_task2); + timer_start(&p_tcc_inst); + 12d6: 4628 mov r0, r5 + 12d8: 4b0b ldr r3, [pc, #44] ; (1308 ) +} + 12da: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + timer_start(&p_tcc_inst); + 12de: 4718 bx r3 + 12e0: e000e010 .word 0xe000e010 + 12e4: 00000531 .word 0x00000531 + 12e8: 200000b0 .word 0x200000b0 + 12ec: 40000800 .word 0x40000800 + 12f0: 40001c00 .word 0x40001c00 + 12f4: 00000ee9 .word 0x00000ee9 + 12f8: 40003800 .word 0x40003800 + 12fc: 00000415 .word 0x00000415 + 1300: 00001271 .word 0x00001271 + 1304: 00000489 .word 0x00000489 + 1308: 0000044d .word 0x0000044d + +0000130c : + 130c: 4b21 ldr r3, [pc, #132] ; (1394 ) +static uint8_t example_USART_0[12] = "Hello World!"; + +static uint8_t debug_buffer[DEBUG_MAX_BUFFER_SIZE]; +static uint8_t debug_rx_buff[DEBUG_USART_EX_BUFF_SIZE]; +void p_usart_init(void) +{ + 130e: b537 push {r0, r1, r2, r4, r5, lr} + 1310: 2240 movs r2, #64 ; 0x40 + 1312: f8c3 209c str.w r2, [r3, #156] ; 0x9c + 1316: 2243 movs r2, #67 ; 0x43 + 1318: f8c3 208c str.w r2, [r3, #140] ; 0x8c + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SERCOM0; + 131c: 4a1e ldr r2, [pc, #120] ; (1398 ) + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_CORE, CONF_GCLK_SERCOM0_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_SLOW, CONF_GCLK_SERCOM0_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + + hri_mclk_set_APBAMASK_SERCOM0_bit(MCLK); + + usart_async_init(&p_usart_debug_inst, USART_DEBUG_SERCOM, debug_rx_buff, DEBUG_USART_EX_BUFF_SIZE, (void*)NULL); + 131e: 491f ldr r1, [pc, #124] ; (139c ) + 1320: 6953 ldr r3, [r2, #20] + 1322: 4d1f ldr r5, [pc, #124] ; (13a0 ) + 1324: f443 5380 orr.w r3, r3, #4096 ; 0x1000 + 1328: 6153 str r3, [r2, #20] + 132a: 4a1e ldr r2, [pc, #120] ; (13a4 ) + 132c: 2300 movs r3, #0 + 132e: f102 0410 add.w r4, r2, #16 + 1332: 9300 str r3, [sp, #0] + 1334: 4620 mov r0, r4 + 1336: 2310 movs r3, #16 + 1338: 47a8 blx r5 + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + 133a: 4b1b ldr r3, [pc, #108] ; (13a8 ) + 133c: f893 20d8 ldrb.w r2, [r3, #216] ; 0xd8 + tmp &= ~PORT_PINCFG_PMUXEN; + 1340: f002 02fe and.w r2, r2, #254 ; 0xfe + tmp |= value << PORT_PINCFG_PMUXEN_Pos; + 1344: f042 0201 orr.w r2, r2, #1 + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + 1348: f883 20d8 strb.w r2, [r3, #216] ; 0xd8 + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + 134c: f893 20bc ldrb.w r2, [r3, #188] ; 0xbc + tmp &= ~PORT_PMUX_PMUXE_Msk; + 1350: f002 02f0 and.w r2, r2, #240 ; 0xf0 + tmp |= PORT_PMUX_PMUXE(data); + 1354: f042 0203 orr.w r2, r2, #3 + ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; + 1358: f883 20bc strb.w r2, [r3, #188] ; 0xbc + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + 135c: f893 20d9 ldrb.w r2, [r3, #217] ; 0xd9 + tmp &= ~PORT_PINCFG_PMUXEN; + 1360: f002 02fe and.w r2, r2, #254 ; 0xfe + tmp |= value << PORT_PINCFG_PMUXEN_Pos; + 1364: f042 0201 orr.w r2, r2, #1 + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + 1368: f883 20d9 strb.w r2, [r3, #217] ; 0xd9 + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + 136c: f893 20bc ldrb.w r2, [r3, #188] ; 0xbc + tmp &= ~PORT_PMUX_PMUXO_Msk; + 1370: f002 020f and.w r2, r2, #15 + tmp |= PORT_PMUX_PMUXO(data); + 1374: f042 0230 orr.w r2, r2, #48 ; 0x30 + ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; + 1378: f883 20bc strb.w r2, [r3, #188] ; 0xbc + + // port init + gpio_set_pin_function(USART_DEBUG_RX, USART_DEBUG_RX_MUX); + gpio_set_pin_function(USART_DEBUG_TX, USART_DEBUG_TX_MUX); + + usart_async_enable(&p_usart_debug_inst); + 137c: 4620 mov r0, r4 + 137e: 4b0b ldr r3, [pc, #44] ; (13ac ) + 1380: 4798 blx r3 + + io_write(&p_usart_debug_inst.io, example_USART_0, 12); + 1382: 490b ldr r1, [pc, #44] ; (13b0 ) + 1384: 4b0b ldr r3, [pc, #44] ; (13b4 ) + 1386: 220c movs r2, #12 + 1388: 4620 mov r0, r4 + + +} + 138a: b003 add sp, #12 + 138c: e8bd 4030 ldmia.w sp!, {r4, r5, lr} + io_write(&p_usart_debug_inst.io, example_USART_0, 12); + 1390: 4718 bx r3 + 1392: bf00 nop + 1394: 40001c00 .word 0x40001c00 + 1398: 40000800 .word 0x40000800 + 139c: 41012000 .word 0x41012000 + 13a0: 00000b99 .word 0x00000b99 + 13a4: 200000e8 .word 0x200000e8 + 13a8: 41008000 .word 0x41008000 + 13ac: 00000c21 .word 0x00000c21 + 13b0: 20000000 .word 0x20000000 + 13b4: 000002ed .word 0x000002ed + +000013b8 : + +static lv_disp_buf_t disp_buf; +static lv_color_t buf[LV_HOR_RES_MAX * 34]; /*Declare a buffer for 10 lines*/ + +void p_screen_init(void) +{ + 13b8: b530 push {r4, r5, lr} + // devices init + lv_init(); + 13ba: 4b1a ldr r3, [pc, #104] ; (1424 ) + + ssd1963_init(); + + + lv_disp_buf_init(&disp_buf, buf, NULL, LV_HOR_RES_MAX * 34); /*Initialize the display buffer*/ + 13bc: 4c1a ldr r4, [pc, #104] ; (1428 ) + 13be: 4d1b ldr r5, [pc, #108] ; (142c ) +{ + 13c0: b08d sub sp, #52 ; 0x34 + lv_init(); + 13c2: 4798 blx r3 + ssd1963_init(); + 13c4: 4b1a ldr r3, [pc, #104] ; (1430 ) + 13c6: 4798 blx r3 + lv_disp_buf_init(&disp_buf, buf, NULL, LV_HOR_RES_MAX * 34); /*Initialize the display buffer*/ + 13c8: 2200 movs r2, #0 + 13ca: 491a ldr r1, [pc, #104] ; (1434 ) + 13cc: 4620 mov r0, r4 + 13ce: f44f 537f mov.w r3, #16320 ; 0x3fc0 + 13d2: 47a8 blx r5 + lv_disp_drv_t disp_drv; /*Descriptor of a display driver*/ + lv_disp_drv_init(&disp_drv); /*Basic initialization*/ + 13d4: a801 add r0, sp, #4 + 13d6: 4b18 ldr r3, [pc, #96] ; (1438 ) + 13d8: 4798 blx r3 + disp_drv.flush_cb = ssd1963_flush; /*Set your driver function*/ + 13da: 4b18 ldr r3, [pc, #96] ; (143c ) + 13dc: 9304 str r3, [sp, #16] + disp_drv.buffer = &disp_buf; /*Assign the buffer to the display*/ + lv_disp_drv_register(&disp_drv); /*Finally register the driver*/ + 13de: a801 add r0, sp, #4 + 13e0: 4b17 ldr r3, [pc, #92] ; (1440 ) + disp_drv.buffer = &disp_buf; /*Assign the buffer to the display*/ + 13e2: 9402 str r4, [sp, #8] + lv_disp_drv_register(&disp_drv); /*Finally register the driver*/ + 13e4: 4798 blx r3 + + lv_obj_t* scr = lv_disp_get_scr_act(NULL); + 13e6: 4b17 ldr r3, [pc, #92] ; (1444 ) + 13e8: 2000 movs r0, #0 + 13ea: 4798 blx r3 + + lv_obj_t* hornet_image = lv_img_create(scr, NULL); + 13ec: 4b16 ldr r3, [pc, #88] ; (1448 ) + 13ee: 2100 movs r1, #0 + lv_obj_t* scr = lv_disp_get_scr_act(NULL); + 13f0: 4604 mov r4, r0 + lv_obj_t* hornet_image = lv_img_create(scr, NULL); + 13f2: 4798 blx r3 + lv_img_set_src(hornet_image, &hornet); + 13f4: 4b15 ldr r3, [pc, #84] ; (144c ) + 13f6: 4916 ldr r1, [pc, #88] ; (1450 ) + lv_obj_t* hornet_image = lv_img_create(scr, NULL); + 13f8: 4605 mov r5, r0 + lv_img_set_src(hornet_image, &hornet); + 13fa: 4798 blx r3 + lv_obj_set_pos(hornet_image, 0, 0); + 13fc: 2200 movs r2, #0 + 13fe: 4611 mov r1, r2 + 1400: 4628 mov r0, r5 + 1402: 4d14 ldr r5, [pc, #80] ; (1454 ) + 1404: 47a8 blx r5 + + lv_obj_t* random_text = lv_label_create(scr, NULL); + 1406: 4b14 ldr r3, [pc, #80] ; (1458 ) + 1408: 2100 movs r1, #0 + 140a: 4620 mov r0, r4 + 140c: 4798 blx r3 + lv_obj_set_pos(random_text, 90, 35); + 140e: 2223 movs r2, #35 ; 0x23 + lv_obj_t* random_text = lv_label_create(scr, NULL); + 1410: 4604 mov r4, r0 + lv_obj_set_pos(random_text, 90, 35); + 1412: 215a movs r1, #90 ; 0x5a + 1414: 47a8 blx r5 + lv_label_set_text(random_text, "Hello World"); + 1416: 4911 ldr r1, [pc, #68] ; (145c ) + 1418: 4b11 ldr r3, [pc, #68] ; (1460 ) + 141a: 4620 mov r0, r4 + 141c: 4798 blx r3 +} + 141e: b00d add sp, #52 ; 0x34 + 1420: bd30 pop {r4, r5, pc} + 1422: bf00 nop + 1424: 00001d2d .word 0x00001d2d + 1428: 20000148 .word 0x20000148 + 142c: 0000d79d .word 0x0000d79d + 1430: 000014e5 .word 0x000014e5 + 1434: 2000016c .word 0x2000016c + 1438: 0000d75d .word 0x0000d75d + 143c: 00001689 .word 0x00001689 + 1440: 0000d7bd .word 0x0000d7bd + 1444: 00001871 .word 0x00001871 + 1448: 00014719 .word 0x00014719 + 144c: 000144c5 .word 0x000144c5 + 1450: 000164a8 .word 0x000164a8 + 1454: 000028a1 .word 0x000028a1 + 1458: 00015931 .word 0x00015931 + 145c: 0001649c .word 0x0001649c + 1460: 00015635 .word 0x00015635 + +00001464 : + +void p_screen_service(void) +{ + lv_task_handler(); + 1464: 4b00 ldr r3, [pc, #0] ; (1468 ) + 1466: 4718 bx r3 + 1468: 0000f9fd .word 0x0000f9fd + +0000146c : + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask; + 146c: 4909 ldr r1, [pc, #36] ; (1494 ) +/** + * Write command + * @param cmd the command + */ +static inline void ssd1963_cmd(uint8_t cmd) +{ + 146e: b508 push {r3, lr} + 1470: 2340 movs r3, #64 ; 0x40 + 1472: 614b str r3, [r1, #20] + if(cmd_mode == false) { + 1474: 4b08 ldr r3, [pc, #32] ; (1498 ) +{ + 1476: 4602 mov r2, r0 + if(cmd_mode == false) { + 1478: 7818 ldrb r0, [r3, #0] + 147a: b918 cbnz r0, 1484 + 147c: 2020 movs r0, #32 + 147e: 6148 str r0, [r1, #20] + cmd_mode = true; + 1480: 2101 movs r1, #1 + 1482: 7019 strb r1, [r3, #0] + + LV_DRV_DISP_PAR_CS(0); + ssd1963_cmd_mode(); + LV_DRV_DISP_PAR_WR_WORD(cmd); + 1484: 4b05 ldr r3, [pc, #20] ; (149c ) + 1486: 4906 ldr r1, [pc, #24] ; (14a0 ) + 1488: 4806 ldr r0, [pc, #24] ; (14a4 ) + 148a: 4798 blx r3 + ((Port *)hw)->Group[submodule_index].OUTSET.reg = mask; + 148c: 4b01 ldr r3, [pc, #4] ; (1494 ) + 148e: 2240 movs r2, #64 ; 0x40 + 1490: 619a str r2, [r3, #24] + LV_DRV_DISP_PAR_CS(1); + +} + 1492: bd08 pop {r3, pc} + 1494: 41008000 .word 0x41008000 + 1498: 2000000c .word 0x2000000c + 149c: 000010f5 .word 0x000010f5 + 14a0: 1c03c3f7 .word 0x1c03c3f7 + 14a4: 41008080 .word 0x41008080 + +000014a8 : + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask; + 14a8: 4909 ldr r1, [pc, #36] ; (14d0 ) +/** + * Write data + * @param data the data + */ +static inline void ssd1963_data(uint8_t data) +{ + 14aa: b508 push {r3, lr} + 14ac: 2340 movs r3, #64 ; 0x40 + 14ae: 614b str r3, [r1, #20] + if(cmd_mode != false) { + 14b0: 4b08 ldr r3, [pc, #32] ; (14d4 ) +{ + 14b2: 4602 mov r2, r0 + if(cmd_mode != false) { + 14b4: 7818 ldrb r0, [r3, #0] + 14b6: b118 cbz r0, 14c0 + ((Port *)hw)->Group[submodule_index].OUTSET.reg = mask; + 14b8: 2020 movs r0, #32 + 14ba: 6188 str r0, [r1, #24] + cmd_mode = false; + 14bc: 2100 movs r1, #0 + 14be: 7019 strb r1, [r3, #0] + + LV_DRV_DISP_PAR_CS(0); + ssd1963_data_mode(); + LV_DRV_DISP_PAR_WR_WORD(data); + 14c0: 4b05 ldr r3, [pc, #20] ; (14d8 ) + 14c2: 4906 ldr r1, [pc, #24] ; (14dc ) + 14c4: 4806 ldr r0, [pc, #24] ; (14e0 ) + 14c6: 4798 blx r3 + 14c8: 4b01 ldr r3, [pc, #4] ; (14d0 ) + 14ca: 2240 movs r2, #64 ; 0x40 + 14cc: 619a str r2, [r3, #24] + LV_DRV_DISP_PAR_CS(1); + +} + 14ce: bd08 pop {r3, pc} + 14d0: 41008000 .word 0x41008000 + 14d4: 2000000c .word 0x2000000c + 14d8: 000010f5 .word 0x000010f5 + 14dc: 1c03c3f7 .word 0x1c03c3f7 + 14e0: 41008080 .word 0x41008080 + +000014e4 : +{ + 14e4: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + asm volatile("nop"); + 14e8: bf00 nop + 14ea: 4f5f ldr r7, [pc, #380] ; (1668 ) + LV_DRV_DELAY_MS(50); + 14ec: 4e5f ldr r6, [pc, #380] ; (166c ) + 14ee: 2410 movs r4, #16 + 14f0: 61bc str r4, [r7, #24] + 14f2: 2032 movs r0, #50 ; 0x32 + 14f4: 47b0 blx r6 + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask; + 14f6: 617c str r4, [r7, #20] + asm volatile("nop"); + 14f8: bf00 nop + LV_DRV_DELAY_MS(50); + 14fa: 2032 movs r0, #50 ; 0x32 + 14fc: 47b0 blx r6 + ((Port *)hw)->Group[submodule_index].OUTSET.reg = mask; + 14fe: 61bc str r4, [r7, #24] + LV_DRV_DELAY_MS(50); + 1500: 2032 movs r0, #50 ; 0x32 + 1502: 47b0 blx r6 + asm volatile("nop"); + 1504: bf00 nop + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask; + 1506: f04f 0840 mov.w r8, #64 ; 0x40 + LV_DRV_DELAY_MS(10); + 150a: 200a movs r0, #10 + 150c: f8c7 8014 str.w r8, [r7, #20] + 1510: 47b0 blx r6 + LV_DRV_DELAY_MS(5); + 1512: 2005 movs r0, #5 + ((Port *)hw)->Group[submodule_index].OUTSET.reg = mask; + 1514: f8c7 8018 str.w r8, [r7, #24] + ssd1963_cmd(0x01); + 1518: 4d55 ldr r5, [pc, #340] ; (1670 ) + ssd1963_data(0x2F); //N=0x36 for 6.5M, 0x23 for 10M crystal + 151a: 4c56 ldr r4, [pc, #344] ; (1674 ) + ssd1963_data((SSD1963_HOR_RES-1)>>8); //Set panel size + 151c: f8df 9160 ldr.w r9, [pc, #352] ; 1680 + LV_DRV_DELAY_MS(5); + 1520: 47b0 blx r6 + ssd1963_cmd(0x01); + 1522: 2001 movs r0, #1 + 1524: 47a8 blx r5 + LV_DRV_DELAY_MS(20); + 1526: 2014 movs r0, #20 + 1528: 47b0 blx r6 + ssd1963_cmd(0x01); + 152a: 2001 movs r0, #1 + 152c: 47a8 blx r5 + LV_DRV_DELAY_MS(20); + 152e: 2014 movs r0, #20 + 1530: 47b0 blx r6 + ssd1963_cmd(0x01); + 1532: 2001 movs r0, #1 + 1534: 47a8 blx r5 + LV_DRV_DELAY_MS(20); + 1536: 2014 movs r0, #20 + 1538: 47b0 blx r6 + ssd1963_cmd(0xE2); //PLL multiplier, set PLL clock to 120M + 153a: 20e2 movs r0, #226 ; 0xe2 + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask; + 153c: f8c7 8014 str.w r8, [r7, #20] + 1540: 47a8 blx r5 + ssd1963_data(0x2F); //N=0x36 for 6.5M, 0x23 for 10M crystal + 1542: 202f movs r0, #47 ; 0x2f + 1544: 47a0 blx r4 + ssd1963_data(0x03); + 1546: 2003 movs r0, #3 + 1548: 47a0 blx r4 + ssd1963_data(0x54); + 154a: 2054 movs r0, #84 ; 0x54 + 154c: 47a0 blx r4 + ssd1963_cmd(0xE0); // PLL enable + 154e: 20e0 movs r0, #224 ; 0xe0 + 1550: 47a8 blx r5 + ssd1963_data(0x01); + 1552: 2001 movs r0, #1 + 1554: 47a0 blx r4 + delay_us(100); + 1556: 4b48 ldr r3, [pc, #288] ; (1678 ) + 1558: 2064 movs r0, #100 ; 0x64 + 155a: 4798 blx r3 + ssd1963_cmd(0xE0); + 155c: 20e0 movs r0, #224 ; 0xe0 + 155e: 47a8 blx r5 + ssd1963_data(0x03); // now, use PLL output as system clock + 1560: 2003 movs r0, #3 + 1562: 47a0 blx r4 + delay_ms(1); + 1564: 2001 movs r0, #1 + 1566: 47b0 blx r6 + ssd1963_cmd(0x01); + 1568: 2001 movs r0, #1 + 156a: 47a8 blx r5 + delay_ms(1); + 156c: 2001 movs r0, #1 + 156e: 47b0 blx r6 + ssd1963_cmd(0xE6); //PLL setting for PCLK, depends on resolution + 1570: 20e6 movs r0, #230 ; 0xe6 + 1572: 47a8 blx r5 + ssd1963_data(0x01); + 1574: 2001 movs r0, #1 + 1576: 47a0 blx r4 + ssd1963_data(0xCC); + 1578: 20cc movs r0, #204 ; 0xcc + 157a: 47a0 blx r4 + ssd1963_data(0xCC); + 157c: 20cc movs r0, #204 ; 0xcc + 157e: 47a0 blx r4 + ssd1963_cmd(0xB0); + 1580: 20b0 movs r0, #176 ; 0xb0 + 1582: 47a8 blx r5 + ssd1963_data(0x28); // set 18-bit for 7" panel TY700TFT800480 + 1584: 2028 movs r0, #40 ; 0x28 + 1586: 47a0 blx r4 + ssd1963_data((SSD1963_HOR_RES-1)>>8); //Set panel size + 1588: 4e3c ldr r6, [pc, #240] ; (167c ) + ssd1963_data(0x80); // set TTL mode + 158a: 2080 movs r0, #128 ; 0x80 + 158c: 47a0 blx r4 + ssd1963_data((SSD1963_HOR_RES-1)>>8); //Set panel size + 158e: 47b0 blx r6 + 1590: 47c8 blx r9 + 1592: 3801 subs r0, #1 + 1594: f3c0 2007 ubfx r0, r0, #8, #8 + 1598: 47a0 blx r4 + ssd1963_data(SSD1963_HOR_RES-1); + 159a: 47b0 blx r6 + 159c: 47c8 blx r9 + 159e: 3801 subs r0, #1 + 15a0: b2c0 uxtb r0, r0 + 15a2: 47a0 blx r4 + ssd1963_data((SSD1963_VER_RES-1)>>8); + 15a4: f8df 90dc ldr.w r9, [pc, #220] ; 1684 + 15a8: 47b0 blx r6 + 15aa: 47c8 blx r9 + 15ac: 3801 subs r0, #1 + 15ae: f3c0 2007 ubfx r0, r0, #8, #8 + 15b2: 47a0 blx r4 + ssd1963_data(SSD1963_VER_RES-1); + 15b4: 47b0 blx r6 + 15b6: 47c8 blx r9 + 15b8: 3801 subs r0, #1 + 15ba: b2c0 uxtb r0, r0 + 15bc: 47a0 blx r4 + ssd1963_data(0x00); + 15be: 2000 movs r0, #0 + 15c0: 47a0 blx r4 + ssd1963_cmd(0xF0); //Pixel Data Interface Format + 15c2: 20f0 movs r0, #240 ; 0xf0 + 15c4: 47a8 blx r5 + ssd1963_data(0x03); //16-bit(565 format) data + 15c6: 2003 movs r0, #3 + 15c8: 47a0 blx r4 + ssd1963_cmd(0x3A); //Set the current pixel format for RGB image data + 15ca: 203a movs r0, #58 ; 0x3a + 15cc: 47a8 blx r5 + ssd1963_data(0x55); //16-bit/pixel + 15ce: 2055 movs r0, #85 ; 0x55 + 15d0: 47a0 blx r4 + ssd1963_cmd(0xb4); //SET HBP, + 15d2: 20b4 movs r0, #180 ; 0xb4 + 15d4: 47a8 blx r5 + ssd1963_data(0x02); //SET HSYNC Tatol 525 + 15d6: 2002 movs r0, #2 + 15d8: 47a0 blx r4 + ssd1963_data(0x0d); + 15da: 200d movs r0, #13 + 15dc: 47a0 blx r4 + ssd1963_data(0x00); //SET HBP 43 + 15de: 2000 movs r0, #0 + 15e0: 47a0 blx r4 + ssd1963_data(0x2b); + 15e2: 202b movs r0, #43 ; 0x2b + 15e4: 47a0 blx r4 + ssd1963_data(0x28); //SET VBP 41=40+1 + 15e6: 2028 movs r0, #40 ; 0x28 + 15e8: 47a0 blx r4 + ssd1963_data(0x00); //SET Hsync pulse start position + 15ea: 2000 movs r0, #0 + 15ec: 47a0 blx r4 + ssd1963_data(0x00); + 15ee: 2000 movs r0, #0 + 15f0: 47a0 blx r4 + ssd1963_data(0x00); //SET Hsync pulse subpixel start position + 15f2: 2000 movs r0, #0 + 15f4: 47a0 blx r4 + ssd1963_cmd(0xb6); //SET VBP, + 15f6: 20b6 movs r0, #182 ; 0xb6 + 15f8: 47a8 blx r5 + ssd1963_data(0x01); //SET Vsync total 286=285+1 + 15fa: 2001 movs r0, #1 + 15fc: 47a0 blx r4 + ssd1963_data(0x1d); + 15fe: 201d movs r0, #29 + 1600: 47a0 blx r4 + ssd1963_data(0x00); //SET VBP=12 + 1602: 2000 movs r0, #0 + 1604: 47a0 blx r4 + ssd1963_data(0x0c); + 1606: 200c movs r0, #12 + 1608: 47a0 blx r4 + ssd1963_data(0x09); //SET Vsync pulse 10=9+1 + 160a: 2009 movs r0, #9 + 160c: 47a0 blx r4 + ssd1963_data(0x00); //SET Vsync pulse start position + 160e: 2000 movs r0, #0 + 1610: 47a0 blx r4 + ssd1963_data(0x00); + 1612: 2000 movs r0, #0 + 1614: 47a0 blx r4 + ssd1963_cmd(0x2a); //SET column address + 1616: 202a movs r0, #42 ; 0x2a + 1618: 47a8 blx r5 + ssd1963_data(0x00); //SET start column address=0 + 161a: 2000 movs r0, #0 + 161c: 47a0 blx r4 + ssd1963_data(0x00); + 161e: 2000 movs r0, #0 + 1620: 47a0 blx r4 + ssd1963_data(0x01); //SET end column address=479 + 1622: 2001 movs r0, #1 + 1624: 47a0 blx r4 + ssd1963_data(0xDF); + 1626: 20df movs r0, #223 ; 0xdf + 1628: 47a0 blx r4 + ssd1963_cmd(0x2b); //SET page address + 162a: 202b movs r0, #43 ; 0x2b + 162c: 47a8 blx r5 + ssd1963_data(0x00); //SET start page address=0 + 162e: 2000 movs r0, #0 + 1630: 47a0 blx r4 + ssd1963_data(0x00); + 1632: 2000 movs r0, #0 + 1634: 47a0 blx r4 + ssd1963_data(0x01); //SET end page address=271 + 1636: 2001 movs r0, #1 + 1638: 47a0 blx r4 + ssd1963_data(0x0F); + 163a: 200f movs r0, #15 + 163c: 47a0 blx r4 + ssd1963_cmd(0x29); //display on + 163e: 2029 movs r0, #41 ; 0x29 + 1640: 47a8 blx r5 + ssd1963_cmd(0xBE); + 1642: 20be movs r0, #190 ; 0xbe + 1644: 47a8 blx r5 + ssd1963_data(0x06); + 1646: 2006 movs r0, #6 + 1648: 47a0 blx r4 + ssd1963_data(0xFF); + 164a: 20ff movs r0, #255 ; 0xff + 164c: 47a0 blx r4 + ssd1963_data(0x01); + 164e: 2001 movs r0, #1 + 1650: 47a0 blx r4 + ssd1963_data(0xFF); + 1652: 20ff movs r0, #255 ; 0xff + 1654: 47a0 blx r4 + ssd1963_data(0x00); + 1656: 2000 movs r0, #0 + 1658: 47a0 blx r4 + ssd1963_data(0x01); + 165a: 2001 movs r0, #1 + 165c: 47a0 blx r4 + ((Port *)hw)->Group[submodule_index].OUTSET.reg = mask; + 165e: f8c7 8018 str.w r8, [r7, #24] +} + 1662: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + 1666: bf00 nop + 1668: 41008000 .word 0x41008000 + 166c: 00000565 .word 0x00000565 + 1670: 0000146d .word 0x0000146d + 1674: 000014a9 .word 0x000014a9 + 1678: 00000541 .word 0x00000541 + 167c: 0000d8fd .word 0x0000d8fd + 1680: 0000d909 .word 0x0000d909 + 1684: 0000d92d .word 0x0000d92d + +00001688 : +{ + 1688: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + if(area->x2 < 0) return; + 168c: f9b1 3004 ldrsh.w r3, [r1, #4] +{ + 1690: ed2d 8b02 vpush {d8} + if(area->x2 < 0) return; + 1694: 2b00 cmp r3, #0 +{ + 1696: ee08 0a10 vmov s16, r0 + 169a: b081 sub sp, #4 + 169c: 460d mov r5, r1 + 169e: 4690 mov r8, r2 + if(area->x2 < 0) return; + 16a0: f2c0 8082 blt.w 17a8 + if(area->y2 < 0) return; + 16a4: f9b1 3006 ldrsh.w r3, [r1, #6] + 16a8: 2b00 cmp r3, #0 + 16aa: db7d blt.n 17a8 + if(area->x1 > SSD1963_HOR_RES - 1) return; + 16ac: 4f41 ldr r7, [pc, #260] ; (17b4 ) + 16ae: f8df a118 ldr.w sl, [pc, #280] ; 17c8 + 16b2: 47b8 blx r7 + 16b4: 47d0 blx sl + 16b6: f9b5 3000 ldrsh.w r3, [r5] + 16ba: 4283 cmp r3, r0 + 16bc: da74 bge.n 17a8 + if(area->y1 > SSD1963_VER_RES - 1) return; + 16be: 47b8 blx r7 + 16c0: f8df b108 ldr.w fp, [pc, #264] ; 17cc + 16c4: 47d8 blx fp + 16c6: f9b5 6002 ldrsh.w r6, [r5, #2] + 16ca: 42b0 cmp r0, r6 + 16cc: dd6c ble.n 17a8 + int32_t act_x1 = area->x1 < 0 ? 0 : area->x1; + 16ce: f9b5 4000 ldrsh.w r4, [r5] + int32_t act_x2 = area->x2 > SSD1963_HOR_RES - 1 ? SSD1963_HOR_RES - 1 : area->x2; + 16d2: 47b8 blx r7 + 16d4: 47d0 blx sl + 16d6: f9b5 3004 ldrsh.w r3, [r5, #4] + 16da: 4298 cmp r0, r3 + int32_t act_x1 = area->x1 < 0 ? 0 : area->x1; + 16dc: ea24 74e4 bic.w r4, r4, r4, asr #31 + int32_t act_y1 = area->y1 < 0 ? 0 : area->y1; + 16e0: ea26 76e6 bic.w r6, r6, r6, asr #31 + int32_t act_x2 = area->x2 > SSD1963_HOR_RES - 1 ? SSD1963_HOR_RES - 1 : area->x2; + 16e4: dc53 bgt.n 178e + 16e6: 47b8 blx r7 + 16e8: 47d0 blx sl + 16ea: f100 3aff add.w sl, r0, #4294967295 ; 0xffffffff + int32_t act_y2 = area->y2 > SSD1963_VER_RES - 1 ? SSD1963_VER_RES - 1 : area->y2; + 16ee: 47b8 blx r7 + 16f0: 47d8 blx fp + 16f2: f9b5 3006 ldrsh.w r3, [r5, #6] + 16f6: 4298 cmp r0, r3 + 16f8: dc4b bgt.n 1792 + 16fa: 47b8 blx r7 + 16fc: 47d8 blx fp + 16fe: 1e47 subs r7, r0, #1 + ssd1963_cmd(0x002A); + 1700: f8df 90cc ldr.w r9, [pc, #204] ; 17d0 + ssd1963_data(act_x1 >> 8); + 1704: f8df b0cc ldr.w fp, [pc, #204] ; 17d4 + ssd1963_cmd(0x002A); + 1708: 202a movs r0, #42 ; 0x2a + 170a: 47c8 blx r9 + ssd1963_data(act_x1 >> 8); + 170c: f3c4 2007 ubfx r0, r4, #8, #8 + 1710: 47d8 blx fp + ssd1963_data(0x00FF & act_x1); + 1712: b2e0 uxtb r0, r4 + 1714: 47d8 blx fp + ssd1963_data(act_x2 >> 8); + 1716: f3ca 2007 ubfx r0, sl, #8, #8 + 171a: 47d8 blx fp + ssd1963_data(0x00FF & act_x2); + 171c: fa5f f08a uxtb.w r0, sl + 1720: 47d8 blx fp + ssd1963_cmd(0x002B); + 1722: 202b movs r0, #43 ; 0x2b + 1724: 47c8 blx r9 + ssd1963_data(act_y1 >> 8); + 1726: f3c6 2007 ubfx r0, r6, #8, #8 + 172a: 47d8 blx fp + ssd1963_data(0x00FF & act_y1); + 172c: b2f0 uxtb r0, r6 + 172e: 47d8 blx fp + ssd1963_data(act_y2 >> 8); + 1730: f3c7 2007 ubfx r0, r7, #8, #8 + 1734: 47d8 blx fp + ssd1963_data(0x00FF & act_y2); + 1736: b2f8 uxtb r0, r7 + 1738: 47d8 blx fp + ssd1963_cmd(0x2c); + 173a: 202c movs r0, #44 ; 0x2c + 173c: 47c8 blx r9 + uint16_t full_w = area->x2 - area->x1 + 1; + 173e: 88ab ldrh r3, [r5, #4] + 1740: 882a ldrh r2, [r5, #0] + 1742: 3301 adds r3, #1 + 1744: 1a9d subs r5, r3, r2 + if(cmd_mode != false) { + 1746: 4a1c ldr r2, [pc, #112] ; (17b8 ) + 1748: 4b1c ldr r3, [pc, #112] ; (17bc ) + 174a: 7811 ldrb r1, [r2, #0] + uint16_t full_w = area->x2 - area->x1 + 1; + 174c: b2ad uxth r5, r5 + if(cmd_mode != false) { + 174e: b119 cbz r1, 1758 + 1750: 2120 movs r1, #32 + 1752: 6199 str r1, [r3, #24] + cmd_mode = false; + 1754: 2100 movs r1, #0 + 1756: 7011 strb r1, [r2, #0] + uint16_t act_w = act_x2 - act_x1 + 1; + 1758: f1c4 0401 rsb r4, r4, #1 + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask; + 175c: 2240 movs r2, #64 ; 0x40 + 175e: 615a str r2, [r3, #20] + LV_DRV_DISP_PAR_WR_ARRAY((uint16_t *)color_p, act_w); + 1760: 4817 ldr r0, [pc, #92] ; (17c0 ) + 1762: f8df b074 ldr.w fp, [pc, #116] ; 17d8 + uint16_t act_w = act_x2 - act_x1 + 1; + 1766: eb04 030a add.w r3, r4, sl + LV_DRV_DISP_PAR_WR_ARRAY((uint16_t *)color_p, act_w); + 176a: f8df a070 ldr.w sl, [pc, #112] ; 17dc + uint16_t act_w = act_x2 - act_x1 + 1; + 176e: b29c uxth r4, r3 + color_p += full_w; + 1770: 006d lsls r5, r5, #1 + for(i = act_y1; i <= act_y2; i++) { + 1772: 42be cmp r6, r7 + 1774: dd0f ble.n 1796 + ((Port *)hw)->Group[submodule_index].OUTSET.reg = mask; + 1776: 4b11 ldr r3, [pc, #68] ; (17bc ) + 1778: 2240 movs r2, #64 ; 0x40 + 177a: 619a str r2, [r3, #24] + lv_disp_flush_ready(disp_drv); + 177c: ee18 0a10 vmov r0, s16 + 1780: 4b10 ldr r3, [pc, #64] ; (17c4 ) +} + 1782: b001 add sp, #4 + 1784: ecbd 8b02 vpop {d8} + 1788: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + lv_disp_flush_ready(disp_drv); + 178c: 4718 bx r3 + int32_t act_x2 = area->x2 > SSD1963_HOR_RES - 1 ? SSD1963_HOR_RES - 1 : area->x2; + 178e: 469a mov sl, r3 + 1790: e7ad b.n 16ee + int32_t act_y2 = area->y2 > SSD1963_VER_RES - 1 ? SSD1963_VER_RES - 1 : area->y2; + 1792: 461f mov r7, r3 + 1794: e7b4 b.n 1700 + LV_DRV_DISP_PAR_WR_ARRAY((uint16_t *)color_p, act_w); + 1796: 4642 mov r2, r8 + 1798: 4623 mov r3, r4 + 179a: 4651 mov r1, sl + 179c: 3601 adds r6, #1 + 179e: 47d8 blx fp + color_p += full_w; + 17a0: 44a8 add r8, r5 + for(i = act_y1; i <= act_y2; i++) { + 17a2: 4807 ldr r0, [pc, #28] ; (17c0 ) + 17a4: b236 sxth r6, r6 + 17a6: e7e4 b.n 1772 +} + 17a8: b001 add sp, #4 + 17aa: ecbd 8b02 vpop {d8} + 17ae: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 17b2: bf00 nop + 17b4: 0000d8fd .word 0x0000d8fd + 17b8: 2000000c .word 0x2000000c + 17bc: 41008000 .word 0x41008000 + 17c0: 41008080 .word 0x41008080 + 17c4: 0000d9b9 .word 0x0000d9b9 + 17c8: 0000d909 .word 0x0000d909 + 17cc: 0000d92d .word 0x0000d92d + 17d0: 0000146d .word 0x0000146d + 17d4: 000014a9 .word 0x000014a9 + 17d8: 00001115 .word 0x00001115 + 17dc: 1c03c3f7 .word 0x1c03c3f7 + +000017e0 : +bool lv_debug_check_null(const void * p) +{ + if(p) return true; + + return false; +} + 17e0: 3800 subs r0, #0 + 17e2: bf18 it ne + 17e4: 2001 movne r0, #1 + 17e6: 4770 bx lr + +000017e8 : + LV_LOG_WARN("lv_debug_check_str: string is longer than LV_DEBUG_STR_MAX_LENGTH"); + return false; +} + +void lv_debug_log_error(const char * msg, uint64_t value) +{ + 17e8: b5f0 push {r4, r5, r6, r7, lr} + static const char hex[] = "0123456789ABCDEF"; + + size_t msg_len = strlen(msg); + 17ea: 4b1b ldr r3, [pc, #108] ; (1858 ) +{ + 17ec: b0c3 sub sp, #268 ; 0x10c + 17ee: 4607 mov r7, r0 + 17f0: 4616 mov r6, r2 + size_t msg_len = strlen(msg); + 17f2: 4798 blx r3 + uint32_t value_len = sizeof(unsigned long int); + + if(msg_len < 230) { + 17f4: 28e5 cmp r0, #229 ; 0xe5 + size_t msg_len = strlen(msg); + 17f6: 4604 mov r4, r0 + if(msg_len < 230) { + 17f8: d829 bhi.n 184e + char buf[255]; + char * bufp = buf; + + /*Add the function name*/ + _lv_memcpy(bufp, msg, msg_len); + 17fa: ad02 add r5, sp, #8 + 17fc: 4602 mov r2, r0 + 17fe: 4b17 ldr r3, [pc, #92] ; (185c ) + 1800: 4639 mov r1, r7 + 1802: 4628 mov r0, r5 + 1804: 4798 blx r3 + bufp += msg_len; + 1806: 192b adds r3, r5, r4 + + /*Add value in hey*/ + *bufp = ' '; + 1808: 2220 movs r2, #32 + 180a: 552a strb r2, [r5, r4] + bufp ++; + *bufp = '('; + 180c: 2228 movs r2, #40 ; 0x28 + 180e: 705a strb r2, [r3, #1] + bufp ++; + *bufp = '0'; + 1810: 2230 movs r2, #48 ; 0x30 + 1812: 709a strb r2, [r3, #2] + + int8_t i; + for(i = value_len * 2 - 1; i >= 0; i--) { + uint8_t x = (unsigned long int)((unsigned long int)value >> (i * 4)) & 0xF; + + *bufp = hex[x]; + 1814: 4c12 ldr r4, [pc, #72] ; (1860 ) + *bufp = 'x'; + 1816: 2278 movs r2, #120 ; 0x78 + 1818: 70da strb r2, [r3, #3] + bufp ++; + 181a: 1d18 adds r0, r3, #4 + 181c: 221c movs r2, #28 + uint8_t x = (unsigned long int)((unsigned long int)value >> (i * 4)) & 0xF; + 181e: fa26 f102 lsr.w r1, r6, r2 + *bufp = hex[x]; + 1822: f001 010f and.w r1, r1, #15 + 1826: 4421 add r1, r4 + for(i = value_len * 2 - 1; i >= 0; i--) { + 1828: 3a04 subs r2, #4 + *bufp = hex[x]; + 182a: 7cc9 ldrb r1, [r1, #19] + 182c: f800 1b01 strb.w r1, [r0], #1 + for(i = value_len * 2 - 1; i >= 0; i--) { + 1830: 1d11 adds r1, r2, #4 + 1832: d1f4 bne.n 181e + bufp++; + } + + *bufp = ')'; + 1834: 2229 movs r2, #41 ; 0x29 + 1836: 731a strb r2, [r3, #12] + bufp ++; + + *bufp = '\0'; + 1838: 2200 movs r2, #0 + 183a: 735a strb r2, [r3, #13] + LV_LOG_ERROR(buf); + 183c: 4b09 ldr r3, [pc, #36] ; (1864 ) + 183e: 9500 str r5, [sp, #0] + 1840: 22bc movs r2, #188 ; 0xbc + } + else { + LV_LOG_ERROR(msg); + 1842: 4909 ldr r1, [pc, #36] ; (1868 ) + 1844: 4c09 ldr r4, [pc, #36] ; (186c ) + 1846: 2003 movs r0, #3 + 1848: 47a0 blx r4 + } +} + 184a: b043 add sp, #268 ; 0x10c + 184c: bdf0 pop {r4, r5, r6, r7, pc} + LV_LOG_ERROR(msg); + 184e: 4b05 ldr r3, [pc, #20] ; (1864 ) + 1850: 9700 str r7, [sp, #0] + 1852: 22bf movs r2, #191 ; 0xbf + 1854: e7f5 b.n 1842 + 1856: bf00 nop + 1858: 00016339 .word 0x00016339 + 185c: 0000ec31 .word 0x0000ec31 + 1860: 0001eb19 .word 0x0001eb19 + 1864: 0001eb3d .word 0x0001eb3d + 1868: 0001ea0f .word 0x0001ea0f + 186c: 0000e8e9 .word 0x0000e8e9 + +00001870 : + * @param disp pointer to display which active screen should be get. (NULL to use the default + * screen) + * @return pointer to the active screen object (loaded by 'lv_scr_load()') + */ +lv_obj_t * lv_disp_get_scr_act(lv_disp_t * disp) +{ + 1870: b537 push {r0, r1, r2, r4, r5, lr} + if(!disp) disp = lv_disp_get_default(); + 1872: 4604 mov r4, r0 + 1874: b970 cbnz r0, 1894 + 1876: 4b08 ldr r3, [pc, #32] ; (1898 ) + 1878: 4798 blx r3 + if(!disp) { + 187a: 4604 mov r4, r0 + 187c: b950 cbnz r0, 1894 + LV_LOG_WARN("lv_scr_act: no display registered to get its act. screen"); + 187e: 4b07 ldr r3, [pc, #28] ; (189c ) + 1880: 9300 str r3, [sp, #0] + 1882: 4907 ldr r1, [pc, #28] ; (18a0 ) + 1884: 4b07 ldr r3, [pc, #28] ; (18a4 ) + 1886: 4d08 ldr r5, [pc, #32] ; (18a8 ) + 1888: 222e movs r2, #46 ; 0x2e + 188a: 2002 movs r0, #2 + 188c: 47a8 blx r5 + return NULL; + } + + return disp->act_scr; +} + 188e: 4620 mov r0, r4 + 1890: b003 add sp, #12 + 1892: bd30 pop {r4, r5, pc} + return disp->act_scr; + 1894: 6be4 ldr r4, [r4, #60] ; 0x3c + 1896: e7fa b.n 188e + 1898: 0000d8fd .word 0x0000d8fd + 189c: 0001eb80 .word 0x0001eb80 + 18a0: 0001eb50 .word 0x0001eb50 + 18a4: 0001ecf0 .word 0x0001ecf0 + 18a8: 0000e8e9 .word 0x0000e8e9 + +000018ac : + * Return with the top layer. (Same on every screen and it is above the normal screen layer) + * @param disp pointer to display which top layer should be get. (NULL to use the default screen) + * @return pointer to the top layer object (transparent screen sized lv_obj) + */ +lv_obj_t * lv_disp_get_layer_top(lv_disp_t * disp) +{ + 18ac: b537 push {r0, r1, r2, r4, r5, lr} + if(!disp) disp = lv_disp_get_default(); + 18ae: 4604 mov r4, r0 + 18b0: b970 cbnz r0, 18d0 + 18b2: 4b08 ldr r3, [pc, #32] ; (18d4 ) + 18b4: 4798 blx r3 + if(!disp) { + 18b6: 4604 mov r4, r0 + 18b8: b950 cbnz r0, 18d0 + LV_LOG_WARN("lv_layer_top: no display registered to get its top layer"); + 18ba: 4b07 ldr r3, [pc, #28] ; (18d8 ) + 18bc: 9300 str r3, [sp, #0] + 18be: 4907 ldr r1, [pc, #28] ; (18dc ) + 18c0: 4b07 ldr r3, [pc, #28] ; (18e0 ) + 18c2: 4d08 ldr r5, [pc, #32] ; (18e4 ) + 18c4: 224b movs r2, #75 ; 0x4b + 18c6: 2002 movs r0, #2 + 18c8: 47a8 blx r5 + return NULL; + } + + return disp->top_layer; +} + 18ca: 4620 mov r0, r4 + 18cc: b003 add sp, #12 + 18ce: bd30 pop {r4, r5, pc} + return disp->top_layer; + 18d0: 6c24 ldr r4, [r4, #64] ; 0x40 + 18d2: e7fa b.n 18ca + 18d4: 0000d8fd .word 0x0000d8fd + 18d8: 0001ebb9 .word 0x0001ebb9 + 18dc: 0001eb50 .word 0x0001eb50 + 18e0: 0001ed04 .word 0x0001ed04 + 18e4: 0000e8e9 .word 0x0000e8e9 + +000018e8 : + * layer) + * @param disp pointer to display which sys. layer should be get. (NULL to use the default screen) + * @return pointer to the sys layer object (transparent screen sized lv_obj) + */ +lv_obj_t * lv_disp_get_layer_sys(lv_disp_t * disp) +{ + 18e8: b537 push {r0, r1, r2, r4, r5, lr} + if(!disp) disp = lv_disp_get_default(); + 18ea: 4604 mov r4, r0 + 18ec: b970 cbnz r0, 190c + 18ee: 4b08 ldr r3, [pc, #32] ; (1910 ) + 18f0: 4798 blx r3 + if(!disp) { + 18f2: 4604 mov r4, r0 + 18f4: b950 cbnz r0, 190c + LV_LOG_WARN("lv_layer_sys: no display registered to get its sys. layer"); + 18f6: 4b07 ldr r3, [pc, #28] ; (1914 ) + 18f8: 9300 str r3, [sp, #0] + 18fa: 4907 ldr r1, [pc, #28] ; (1918 ) + 18fc: 4b07 ldr r3, [pc, #28] ; (191c ) + 18fe: 4d08 ldr r5, [pc, #32] ; (1920 ) + 1900: 225c movs r2, #92 ; 0x5c + 1902: 2002 movs r0, #2 + 1904: 47a8 blx r5 + return NULL; + } + + return disp->sys_layer; +} + 1906: 4620 mov r0, r4 + 1908: b003 add sp, #12 + 190a: bd30 pop {r4, r5, pc} + return disp->sys_layer; + 190c: 6c64 ldr r4, [r4, #68] ; 0x44 + 190e: e7fa b.n 1906 + 1910: 0000d8fd .word 0x0000d8fd + 1914: 0001ebf2 .word 0x0001ebf2 + 1918: 0001eb50 .word 0x0001eb50 + 191c: 0001ed1a .word 0x0001ed1a + 1920: 0000e8e9 .word 0x0000e8e9 + +00001924 : + + if(group->focus_cb) group->focus_cb(group); +} + +static void obj_to_foreground(lv_obj_t * obj) +{ + 1924: b570 push {r4, r5, r6, lr} + /*Search for 'top' attribute*/ + lv_obj_t * i = obj; + lv_obj_t * last_top = NULL; + while(i != NULL) { + if(i->top != 0) last_top = i; + i = lv_obj_get_parent(i); + 1926: 4d09 ldr r5, [pc, #36] ; (194c ) + lv_obj_t * last_top = NULL; + 1928: 2400 movs r4, #0 + while(i != NULL) { + 192a: b928 cbnz r0, 1938 + } + + if(last_top != NULL) { + 192c: b164 cbz r4, 1948 + /*Move the last_top object to the foreground*/ + lv_obj_move_foreground(last_top); + 192e: 4620 mov r0, r4 + 1930: 4b07 ldr r3, [pc, #28] ; (1950 ) + } +} + 1932: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + lv_obj_move_foreground(last_top); + 1936: 4718 bx r3 + if(i->top != 0) last_top = i; + 1938: f890 3034 ldrb.w r3, [r0, #52] ; 0x34 + 193c: f013 0f20 tst.w r3, #32 + 1940: bf18 it ne + 1942: 4604 movne r4, r0 + i = lv_obj_get_parent(i); + 1944: 47a8 blx r5 + 1946: e7f0 b.n 192a +} + 1948: bd70 pop {r4, r5, r6, pc} + 194a: bf00 nop + 194c: 00002125 .word 0x00002125 + 1950: 00002811 .word 0x00002811 + +00001954 : +{ + 1954: e92d 47f3 stmdb sp!, {r0, r1, r4, r5, r6, r7, r8, r9, sl, lr} + if(group->frozen) return; + 1958: 7d06 ldrb r6, [r0, #20] + 195a: f016 0601 ands.w r6, r6, #1 +{ + 195e: 4605 mov r5, r0 + 1960: 4688 mov r8, r1 + 1962: 4617 mov r7, r2 + if(group->frozen) return; + 1964: d15c bne.n 1a20 + lv_obj_t ** obj_next = group->obj_focus; + 1966: 68c4 ldr r4, [r0, #12] + if(!lv_obj_get_hidden(*obj_next)) break; + 1968: f8df a0c8 ldr.w sl, [pc, #200] ; 1a34 + bool can_begin = true; + 196c: f04f 0901 mov.w r9, #1 + if(obj_next == NULL) { + 1970: 2c00 cmp r4, #0 + 1972: d14c bne.n 1a0e + if(group->wrap || obj_sentinel == NULL) { + 1974: 7d2b ldrb r3, [r5, #20] + 1976: 06db lsls r3, r3, #27 + 1978: d401 bmi.n 197e + 197a: 2e00 cmp r6, #0 + 197c: d150 bne.n 1a20 + if(!can_begin) return; + 197e: f1b9 0f00 cmp.w r9, #0 + 1982: d04d beq.n 1a20 + obj_next = begin(&group->obj_ll); + 1984: 4628 mov r0, r5 + 1986: 47c0 blx r8 + 1988: 4604 mov r4, r0 + if(obj_sentinel == NULL) { + 198a: 2e00 cmp r6, #0 + 198c: d13a bne.n 1a04 + if(obj_sentinel == NULL) return; /*Group is empty*/ + 198e: 2800 cmp r0, #0 + 1990: d046 beq.n 1a20 + 1992: 4606 mov r6, r0 + can_begin = false; + 1994: f04f 0900 mov.w r9, #0 + if(!lv_obj_get_hidden(*obj_next)) break; + 1998: 6820 ldr r0, [r4, #0] + 199a: 47d0 blx sl + 199c: 4602 mov r2, r0 + 199e: 2800 cmp r0, #0 + 19a0: d1e6 bne.n 1970 + if(obj_next == group->obj_focus) return; /*There's only one visible object and it's already focused*/ + 19a2: 68eb ldr r3, [r5, #12] + 19a4: 42a3 cmp r3, r4 + 19a6: d03b beq.n 1a20 + if(group->obj_focus) { + 19a8: 4e1f ldr r6, [pc, #124] ; (1a28 ) + 19aa: b17b cbz r3, 19cc + (*group->obj_focus)->signal_cb(*group->obj_focus, LV_SIGNAL_DEFOCUS, NULL); + 19ac: 6818 ldr r0, [r3, #0] + 19ae: 9201 str r2, [sp, #4] + 19b0: 69c3 ldr r3, [r0, #28] + 19b2: 2117 movs r1, #23 + 19b4: 4798 blx r3 + lv_res_t res = lv_event_send(*group->obj_focus, LV_EVENT_DEFOCUSED, NULL); + 19b6: 68eb ldr r3, [r5, #12] + 19b8: 9a01 ldr r2, [sp, #4] + 19ba: 6818 ldr r0, [r3, #0] + 19bc: 210e movs r1, #14 + 19be: 47b0 blx r6 + if(res != LV_RES_OK) return; + 19c0: 2801 cmp r0, #1 + 19c2: d12d bne.n 1a20 + lv_obj_invalidate(*group->obj_focus); + 19c4: 68eb ldr r3, [r5, #12] + 19c6: 6818 ldr r0, [r3, #0] + 19c8: 4b18 ldr r3, [pc, #96] ; (1a2c ) + 19ca: 4798 blx r3 + (*group->obj_focus)->signal_cb(*group->obj_focus, LV_SIGNAL_FOCUS, NULL); + 19cc: 6820 ldr r0, [r4, #0] + group->obj_focus = obj_next; + 19ce: 60ec str r4, [r5, #12] + (*group->obj_focus)->signal_cb(*group->obj_focus, LV_SIGNAL_FOCUS, NULL); + 19d0: 69c3 ldr r3, [r0, #28] + 19d2: 2200 movs r2, #0 + 19d4: 2116 movs r1, #22 + 19d6: 4798 blx r3 + lv_res_t res = lv_event_send(*group->obj_focus, LV_EVENT_FOCUSED, NULL); + 19d8: 68eb ldr r3, [r5, #12] + 19da: 2200 movs r2, #0 + 19dc: 6818 ldr r0, [r3, #0] + 19de: 210d movs r1, #13 + 19e0: 47b0 blx r6 + if(res != LV_RES_OK) return; + 19e2: 2801 cmp r0, #1 + 19e4: d11c bne.n 1a20 + obj_to_foreground(*group->obj_focus); + 19e6: 68eb ldr r3, [r5, #12] + 19e8: 6818 ldr r0, [r3, #0] + 19ea: 4b11 ldr r3, [pc, #68] ; (1a30 ) + 19ec: 4798 blx r3 + lv_obj_invalidate(*group->obj_focus); + 19ee: 68eb ldr r3, [r5, #12] + 19f0: 6818 ldr r0, [r3, #0] + 19f2: 4b0e ldr r3, [pc, #56] ; (1a2c ) + 19f4: 4798 blx r3 + if(group->focus_cb) group->focus_cb(group); + 19f6: 692b ldr r3, [r5, #16] + 19f8: b193 cbz r3, 1a20 + 19fa: 4628 mov r0, r5 +} + 19fc: b002 add sp, #8 + 19fe: e8bd 47f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + if(group->focus_cb) group->focus_cb(group); + 1a02: 4718 bx r3 + can_begin = false; + 1a04: f04f 0900 mov.w r9, #0 + if(obj_next == NULL) continue; + 1a08: 2c00 cmp r4, #0 + 1a0a: d1c5 bne.n 1998 + 1a0c: e7b2 b.n 1974 + obj_next = move(&group->obj_ll, obj_next); + 1a0e: 4621 mov r1, r4 + 1a10: 4628 mov r0, r5 + 1a12: 47b8 blx r7 + if(obj_sentinel == NULL) { + 1a14: 2e00 cmp r6, #0 + 1a16: bf08 it eq + 1a18: 4626 moveq r6, r4 + if(obj_next == obj_sentinel) return; + 1a1a: 42b0 cmp r0, r6 + obj_next = move(&group->obj_ll, obj_next); + 1a1c: 4604 mov r4, r0 + if(obj_next == obj_sentinel) return; + 1a1e: d1f3 bne.n 1a08 +} + 1a20: b002 add sp, #8 + 1a22: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 1a26: bf00 nop + 1a28: 00001f79 .word 0x00001f79 + 1a2c: 00002785 .word 0x00002785 + 1a30: 00001925 .word 0x00001925 + 1a34: 0000261d .word 0x0000261d + +00001a38 <_lv_group_init>: + _lv_ll_init(&LV_GC_ROOT(_lv_group_ll), sizeof(lv_group_t)); + 1a38: 4801 ldr r0, [pc, #4] ; (1a40 <_lv_group_init+0x8>) + 1a3a: 4b02 ldr r3, [pc, #8] ; (1a44 <_lv_group_init+0xc>) + 1a3c: 2118 movs r1, #24 + 1a3e: 4718 bx r3 + 1a40: 20008648 .word 0x20008648 + 1a44: 0000e605 .word 0x0000e605 + +00001a48 : + focus_next_core(group, _lv_ll_get_head, _lv_ll_get_next); + 1a48: 4a01 ldr r2, [pc, #4] ; (1a50 ) + 1a4a: 4902 ldr r1, [pc, #8] ; (1a54 ) + 1a4c: 4b02 ldr r3, [pc, #8] ; (1a58 ) + 1a4e: 4718 bx r3 + 1a50: 0000e6b5 .word 0x0000e6b5 + 1a54: 0000e6a9 .word 0x0000e6a9 + 1a58: 00001955 .word 0x00001955 + +00001a5c : + focus_next_core(group, _lv_ll_get_tail, _lv_ll_get_prev); + 1a5c: 4a01 ldr r2, [pc, #4] ; (1a64 ) + 1a5e: 4902 ldr r1, [pc, #8] ; (1a68 ) + 1a60: 4b02 ldr r3, [pc, #8] ; (1a6c ) + 1a62: 4718 bx r3 + 1a64: 0000e6d5 .word 0x0000e6d5 + 1a68: 0000e6af .word 0x0000e6af + 1a6c: 00001955 .word 0x00001955 + +00001a70 : +{ + 1a70: b538 push {r3, r4, r5, lr} + uint8_t temp_wrap = g->wrap; + 1a72: 7d03 ldrb r3, [r0, #20] + 1a74: f3c3 1500 ubfx r5, r3, #4, #1 + g->wrap = 1; + 1a78: f043 0310 orr.w r3, r3, #16 + 1a7c: 7503 strb r3, [r0, #20] +{ + 1a7e: 4604 mov r4, r0 + if(g->refocus_policy == LV_GROUP_REFOCUS_POLICY_NEXT) + 1a80: 071b lsls r3, r3, #28 + lv_group_focus_next(g); + 1a82: bf54 ite pl + 1a84: 4b03 ldrpl r3, [pc, #12] ; (1a94 ) + lv_group_focus_prev(g); + 1a86: 4b04 ldrmi r3, [pc, #16] ; (1a98 ) + 1a88: 4798 blx r3 + g->wrap = temp_wrap; + 1a8a: 7d23 ldrb r3, [r4, #20] + 1a8c: f365 1304 bfi r3, r5, #4, #1 + 1a90: 7523 strb r3, [r4, #20] +} + 1a92: bd38 pop {r3, r4, r5, pc} + 1a94: 00001a49 .word 0x00001a49 + 1a98: 00001a5d .word 0x00001a5d + +00001a9c : +{ + 1a9c: e92d 41f3 stmdb sp!, {r0, r1, r4, r5, r6, r7, r8, lr} + 1aa0: 460d mov r5, r1 + if(group == NULL) return; + 1aa2: 4604 mov r4, r0 + 1aa4: 2800 cmp r0, #0 + 1aa6: d036 beq.n 1b16 + _LV_LL_READ(group->obj_ll, obj_i) { + 1aa8: f8df 80c4 ldr.w r8, [pc, #196] ; 1b70 + 1aac: 4e24 ldr r6, [pc, #144] ; (1b40 ) + 1aae: 47c0 blx r8 + 1ab0: bb30 cbnz r0, 1b00 + if(obj->group_p) { + 1ab2: 6bab ldr r3, [r5, #56] ; 0x38 + 1ab4: b173 cbz r3, 1ad4 + if(lv_obj_is_focused(obj)) { + 1ab6: 4b23 ldr r3, [pc, #140] ; (1b44 ) + 1ab8: 4628 mov r0, r5 + 1aba: 4798 blx r3 + 1abc: b150 cbz r0, 1ad4 + lv_group_refocus(obj->group_p); + 1abe: 6ba8 ldr r0, [r5, #56] ; 0x38 + 1ac0: 4b21 ldr r3, [pc, #132] ; (1b48 ) + LV_LOG_INFO("lv_group_add_obj: assign object to an other group"); + 1ac2: 4e22 ldr r6, [pc, #136] ; (1b4c ) + lv_group_refocus(obj->group_p); + 1ac4: 4798 blx r3 + LV_LOG_INFO("lv_group_add_obj: assign object to an other group"); + 1ac6: 4b22 ldr r3, [pc, #136] ; (1b50 ) + 1ac8: 9300 str r3, [sp, #0] + 1aca: 4922 ldr r1, [pc, #136] ; (1b54 ) + 1acc: 4b22 ldr r3, [pc, #136] ; (1b58 ) + 1ace: 227f movs r2, #127 ; 0x7f + 1ad0: 2001 movs r0, #1 + 1ad2: 47b0 blx r6 + lv_obj_t ** next = _lv_ll_ins_tail(&group->obj_ll); + 1ad4: 4b21 ldr r3, [pc, #132] ; (1b5c ) + obj->group_p = group; + 1ad6: 63ac str r4, [r5, #56] ; 0x38 + lv_obj_t ** next = _lv_ll_ins_tail(&group->obj_ll); + 1ad8: 4620 mov r0, r4 + 1ada: 4798 blx r3 + LV_ASSERT_MEM(next); + 1adc: 4b20 ldr r3, [pc, #128] ; (1b60 ) + lv_obj_t ** next = _lv_ll_ins_tail(&group->obj_ll); + 1ade: 4606 mov r6, r0 + LV_ASSERT_MEM(next); + 1ae0: 4798 blx r3 + 1ae2: 4607 mov r7, r0 + 1ae4: b9f0 cbnz r0, 1b24 + 1ae6: 4b1c ldr r3, [pc, #112] ; (1b58 ) + 1ae8: 491a ldr r1, [pc, #104] ; (1b54 ) + 1aea: 9300 str r3, [sp, #0] + 1aec: 2285 movs r2, #133 ; 0x85 + 1aee: 2003 movs r0, #3 + 1af0: 4c16 ldr r4, [pc, #88] ; (1b4c ) + 1af2: 47a0 blx r4 + 1af4: 481b ldr r0, [pc, #108] ; (1b64 ) + 1af6: 491c ldr r1, [pc, #112] ; (1b68 ) + 1af8: 4632 mov r2, r6 + 1afa: 463b mov r3, r7 + 1afc: 4788 blx r1 + 1afe: e7fe b.n 1afe + if((*obj_i) == obj) { + 1b00: 6803 ldr r3, [r0, #0] + 1b02: 42ab cmp r3, r5 + 1b04: d10a bne.n 1b1c + LV_LOG_INFO("lv_group_add_obj: the object is already added to this group"); + 1b06: 4b19 ldr r3, [pc, #100] ; (1b6c ) + 1b08: 9300 str r3, [sp, #0] + 1b0a: 4912 ldr r1, [pc, #72] ; (1b54 ) + 1b0c: 4b12 ldr r3, [pc, #72] ; (1b58 ) + 1b0e: 4c0f ldr r4, [pc, #60] ; (1b4c ) + 1b10: 2275 movs r2, #117 ; 0x75 + 1b12: 2001 movs r0, #1 + 1b14: 47a0 blx r4 +} + 1b16: b002 add sp, #8 + 1b18: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + _LV_LL_READ(group->obj_ll, obj_i) { + 1b1c: 4601 mov r1, r0 + 1b1e: 4620 mov r0, r4 + 1b20: 47b0 blx r6 + 1b22: e7c5 b.n 1ab0 + if(next == NULL) return; + 1b24: 2e00 cmp r6, #0 + 1b26: d0f6 beq.n 1b16 + *next = obj; + 1b28: 6035 str r5, [r6, #0] + if(_lv_ll_get_head(&group->obj_ll) == next) { + 1b2a: 4620 mov r0, r4 + 1b2c: 47c0 blx r8 + 1b2e: 4286 cmp r6, r0 + 1b30: d1f1 bne.n 1b16 + lv_group_refocus(group); + 1b32: 4b05 ldr r3, [pc, #20] ; (1b48 ) + 1b34: 4620 mov r0, r4 +} + 1b36: b002 add sp, #8 + 1b38: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} + lv_group_refocus(group); + 1b3c: 4718 bx r3 + 1b3e: bf00 nop + 1b40: 0000e6b5 .word 0x0000e6b5 + 1b44: 000041f9 .word 0x000041f9 + 1b48: 00001a71 .word 0x00001a71 + 1b4c: 0000e8e9 .word 0x0000e8e9 + 1b50: 0001ee08 .word 0x0001ee08 + 1b54: 0001ed8d .word 0x0001ed8d + 1b58: 0001ee4a .word 0x0001ee4a + 1b5c: 0000e661 .word 0x0000e661 + 1b60: 000017e1 .word 0x000017e1 + 1b64: 0001edbe .word 0x0001edbe + 1b68: 000017e9 .word 0x000017e9 + 1b6c: 0001edcc .word 0x0001edcc + 1b70: 0000e6a9 .word 0x0000e6a9 + +00001b74 : +{ + 1b74: b5f8 push {r3, r4, r5, r6, r7, lr} + lv_group_t * g = obj->group_p; + 1b76: 6b84 ldr r4, [r0, #56] ; 0x38 +{ + 1b78: 4606 mov r6, r0 + if(g == NULL) return; + 1b7a: 2c00 cmp r4, #0 + 1b7c: d033 beq.n 1be6 + if(g->obj_focus == NULL) return; /*Just to be sure (Not possible if there is at least one object in the group)*/ + 1b7e: 68e3 ldr r3, [r4, #12] + 1b80: 2b00 cmp r3, #0 + 1b82: d030 beq.n 1be6 + if(*g->obj_focus == obj) { + 1b84: 681b ldr r3, [r3, #0] + 1b86: 4d1c ldr r5, [pc, #112] ; (1bf8 ) + 1b88: 4283 cmp r3, r0 + 1b8a: d11b bne.n 1bc4 + if(g->frozen) g->frozen = 0; + 1b8c: 7d23 ldrb r3, [r4, #20] + 1b8e: 07da lsls r2, r3, #31 + 1b90: bf44 itt mi + 1b92: f36f 0300 bfcmi r3, #0, #1 + 1b96: 7523 strbmi r3, [r4, #20] + if(_lv_ll_get_head(&g->obj_ll) == g->obj_focus && _lv_ll_get_tail(&g->obj_ll) == g->obj_focus) { + 1b98: 4620 mov r0, r4 + 1b9a: 47a8 blx r5 + 1b9c: 68e3 ldr r3, [r4, #12] + 1b9e: 4283 cmp r3, r0 + 1ba0: d122 bne.n 1be8 + 1ba2: 4b16 ldr r3, [pc, #88] ; (1bfc ) + 1ba4: 4620 mov r0, r4 + 1ba6: 4798 blx r3 + 1ba8: 68e3 ldr r3, [r4, #12] + 1baa: 4298 cmp r0, r3 + 1bac: d11c bne.n 1be8 + (*g->obj_focus)->signal_cb(*g->obj_focus, LV_SIGNAL_DEFOCUS, NULL); + 1bae: 6800 ldr r0, [r0, #0] + 1bb0: 2200 movs r2, #0 + 1bb2: 69c3 ldr r3, [r0, #28] + 1bb4: 2117 movs r1, #23 + 1bb6: 4798 blx r3 + if(*g->obj_focus == obj) { + 1bb8: 68e3 ldr r3, [r4, #12] + 1bba: 681b ldr r3, [r3, #0] + 1bbc: 42b3 cmp r3, r6 + g->obj_focus = NULL; + 1bbe: bf04 itt eq + 1bc0: 2300 moveq r3, #0 + 1bc2: 60e3 streq r3, [r4, #12] + _LV_LL_READ(g->obj_ll, i) { + 1bc4: 4620 mov r0, r4 + 1bc6: 47a8 blx r5 + 1bc8: 4f0d ldr r7, [pc, #52] ; (1c00 ) + 1bca: 4605 mov r5, r0 + 1bcc: b15d cbz r5, 1be6 + if(*i == obj) { + 1bce: 682b ldr r3, [r5, #0] + 1bd0: 42b3 cmp r3, r6 + _lv_ll_remove(&g->obj_ll, i); + 1bd2: 4629 mov r1, r5 + 1bd4: 4620 mov r0, r4 + if(*i == obj) { + 1bd6: d10b bne.n 1bf0 + _lv_ll_remove(&g->obj_ll, i); + 1bd8: 4b0a ldr r3, [pc, #40] ; (1c04 ) + 1bda: 4798 blx r3 + lv_mem_free(i); + 1bdc: 4b0a ldr r3, [pc, #40] ; (1c08 ) + 1bde: 4628 mov r0, r5 + 1be0: 4798 blx r3 + obj->group_p = NULL; + 1be2: 2300 movs r3, #0 + 1be4: 63b3 str r3, [r6, #56] ; 0x38 +} + 1be6: bdf8 pop {r3, r4, r5, r6, r7, pc} + lv_group_refocus(g); + 1be8: 4b08 ldr r3, [pc, #32] ; (1c0c ) + 1bea: 4620 mov r0, r4 + 1bec: 4798 blx r3 + 1bee: e7e3 b.n 1bb8 + _LV_LL_READ(g->obj_ll, i) { + 1bf0: 47b8 blx r7 + 1bf2: 4605 mov r5, r0 + 1bf4: e7ea b.n 1bcc + 1bf6: bf00 nop + 1bf8: 0000e6a9 .word 0x0000e6a9 + 1bfc: 0000e6af .word 0x0000e6af + 1c00: 0000e6b5 .word 0x0000e6b5 + 1c04: 0000e76d .word 0x0000e76d + 1c08: 0000eae5 .word 0x0000eae5 + 1c0c: 00001a71 .word 0x00001a71 + +00001c10 : + if(!group) return NULL; + 1c10: b110 cbz r0, 1c18 + if(group->obj_focus == NULL) return NULL; + 1c12: 68c0 ldr r0, [r0, #12] + 1c14: b100 cbz r0, 1c18 + return *group->obj_focus; + 1c16: 6800 ldr r0, [r0, #0] +} + 1c18: 4770 bx lr + +00001c1a : + if(!group) return false; + 1c1a: b110 cbz r0, 1c22 + return group->editing ? true : false; + 1c1c: 7d00 ldrb r0, [r0, #20] + 1c1e: f3c0 0040 ubfx r0, r0, #1, #1 +} + 1c22: 4770 bx lr + +00001c24 : +void lv_indev_reset(lv_indev_t * indev, lv_obj_t * obj) + 1c24: b5f8 push {r3, r4, r5, r6, r7, lr} + lv_indev_t * i = lv_indev_get_next(NULL); + 1c26: 4d0c ldr r5, [pc, #48] ; (1c58 ) + if(indev_act == i) indev_obj_act = NULL; + 1c28: 4e0c ldr r6, [pc, #48] ; (1c5c ) +void lv_indev_reset(lv_indev_t * indev, lv_obj_t * obj) + 1c2a: 4604 mov r4, r0 + lv_indev_t * i = lv_indev_get_next(NULL); + 1c2c: 2000 movs r0, #0 + 1c2e: 47a8 blx r5 + if(indev_act == i) indev_obj_act = NULL; + 1c30: 2700 movs r7, #0 + while(i) { + 1c32: b900 cbnz r0, 1c36 +} + 1c34: bdf8 pop {r3, r4, r5, r6, r7, pc} + i->proc.reset_query = 1; + 1c36: f890 3050 ldrb.w r3, [r0, #80] ; 0x50 + 1c3a: f043 0302 orr.w r3, r3, #2 + 1c3e: f880 3050 strb.w r3, [r0, #80] ; 0x50 + if(indev_act == i) indev_obj_act = NULL; + 1c42: 6873 ldr r3, [r6, #4] + 1c44: 4298 cmp r0, r3 + 1c46: bf08 it eq + 1c48: 6037 streq r7, [r6, #0] + if(obj == NULL || i->proc.types.pointer.last_pressed == obj) { + 1c4a: b114 cbz r4, 1c52 + 1c4c: 6bc3 ldr r3, [r0, #60] ; 0x3c + 1c4e: 429c cmp r4, r3 + 1c50: d100 bne.n 1c54 + i->proc.types.pointer.last_pressed = NULL; + 1c52: 63c7 str r7, [r0, #60] ; 0x3c + i = lv_indev_get_next(i); + 1c54: 47a8 blx r5 + 1c56: e7ec b.n 1c32 + 1c58: 0000da19 .word 0x0000da19 + 1c5c: 200080ec .word 0x200080ec + +00001c60 <_lv_indev_init>: + if(indev) { + 1c60: 4b01 ldr r3, [pc, #4] ; (1c68 <_lv_indev_init+0x8>) + 1c62: 2000 movs r0, #0 + 1c64: 4718 bx r3 + 1c66: bf00 nop + 1c68: 00001c25 .word 0x00001c25 + +00001c6c : +} + 1c6c: 4b01 ldr r3, [pc, #4] ; (1c74 ) + 1c6e: 6858 ldr r0, [r3, #4] + 1c70: 4770 bx lr + 1c72: bf00 nop + 1c74: 200080ec .word 0x200080ec + +00001c78 : + if(indev) { + 1c78: 4603 mov r3, r0 + 1c7a: b190 cbz r0, 1ca2 + indev->proc.reset_query = 1; + 1c7c: f890 2050 ldrb.w r2, [r0, #80] ; 0x50 + 1c80: f042 0202 orr.w r2, r2, #2 + 1c84: f880 2050 strb.w r2, [r0, #80] ; 0x50 + if(indev_act == indev) indev_obj_act = NULL; + 1c88: 4a08 ldr r2, [pc, #32] ; (1cac ) + 1c8a: 6850 ldr r0, [r2, #4] + 1c8c: 4298 cmp r0, r3 + 1c8e: bf04 itt eq + 1c90: 2000 moveq r0, #0 + 1c92: 6010 streq r0, [r2, #0] + if(obj == NULL || indev->proc.types.pointer.last_pressed == obj) { + 1c94: b111 cbz r1, 1c9c + 1c96: 6bda ldr r2, [r3, #60] ; 0x3c + 1c98: 428a cmp r2, r1 + 1c9a: d105 bne.n 1ca8 + indev->proc.types.pointer.last_pressed = NULL; + 1c9c: 2200 movs r2, #0 + 1c9e: 63da str r2, [r3, #60] ; 0x3c + 1ca0: 4770 bx lr + 1ca2: 4b03 ldr r3, [pc, #12] ; (1cb0 ) + 1ca4: 4608 mov r0, r1 + 1ca6: 4718 bx r3 +} + 1ca8: 4770 bx lr + 1caa: bf00 nop + 1cac: 200080ec .word 0x200080ec + 1cb0: 00001c25 .word 0x00001c25 + +00001cb4 : +} + 1cb4: 4b01 ldr r3, [pc, #4] ; (1cbc ) + 1cb6: 6818 ldr r0, [r3, #0] + 1cb8: 4770 bx lr + 1cba: bf00 nop + 1cbc: 200080ec .word 0x200080ec + +00001cc0 : + * @param obj pointer to an object which children will be repositioned + * @param x_diff x coordinate shift + * @param y_diff y coordinate shift + */ +static void refresh_children_position(lv_obj_t * obj, lv_coord_t x_diff, lv_coord_t y_diff) +{ + 1cc0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + lv_obj_t * i; + _LV_LL_READ(obj->child_ll, i) { + 1cc4: 1d05 adds r5, r0, #4 + 1cc6: 4b12 ldr r3, [pc, #72] ; (1d10 ) + 1cc8: f8df 9048 ldr.w r9, [pc, #72] ; 1d14 + 1ccc: 4628 mov r0, r5 +{ + 1cce: 460e mov r6, r1 + 1cd0: 4617 mov r7, r2 + _LV_LL_READ(obj->child_ll, i) { + 1cd2: 4798 blx r3 + i->coords.x1 += x_diff; + 1cd4: fa1f f886 uxth.w r8, r6 + _LV_LL_READ(obj->child_ll, i) { + 1cd8: 4604 mov r4, r0 + i->coords.y1 += y_diff; + 1cda: fa1f fa87 uxth.w sl, r7 + _LV_LL_READ(obj->child_ll, i) { + 1cde: b90c cbnz r4, 1ce4 + i->coords.x2 += x_diff; + i->coords.y2 += y_diff; + + refresh_children_position(i, x_diff, y_diff); + } +} + 1ce0: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + i->coords.x1 += x_diff; + 1ce4: 8a23 ldrh r3, [r4, #16] + 1ce6: 4443 add r3, r8 + 1ce8: 8223 strh r3, [r4, #16] + i->coords.y1 += y_diff; + 1cea: 8a63 ldrh r3, [r4, #18] + 1cec: 4453 add r3, sl + 1cee: 8263 strh r3, [r4, #18] + i->coords.x2 += x_diff; + 1cf0: 8aa3 ldrh r3, [r4, #20] + 1cf2: 4443 add r3, r8 + 1cf4: 82a3 strh r3, [r4, #20] + i->coords.y2 += y_diff; + 1cf6: 8ae3 ldrh r3, [r4, #22] + 1cf8: 4453 add r3, sl + 1cfa: 82e3 strh r3, [r4, #22] + refresh_children_position(i, x_diff, y_diff); + 1cfc: 4620 mov r0, r4 + 1cfe: 463a mov r2, r7 + 1d00: 4631 mov r1, r6 + 1d02: f7ff ffdd bl 1cc0 + _LV_LL_READ(obj->child_ll, i) { + 1d06: 4621 mov r1, r4 + 1d08: 4628 mov r0, r5 + 1d0a: 47c8 blx r9 + 1d0c: 4604 mov r4, r0 + 1d0e: e7e6 b.n 1cde + 1d10: 0000e6a9 .word 0x0000e6a9 + 1d14: 0000e6b5 .word 0x0000e6b5 + +00001d18 : +LV_ATTRIBUTE_FAST_MEM static inline void * _lv_memcpy_small(void * dst, const void * src, size_t len) +{ + uint8_t * d8 = (uint8_t *)dst; + const uint8_t * s8 = (const uint8_t *)src; + + while(len) { + 1d18: 3901 subs r1, #1 + 1d1a: f100 0308 add.w r3, r0, #8 + *d8 = *s8; + 1d1e: f811 2f01 ldrb.w r2, [r1, #1]! + 1d22: f800 2b01 strb.w r2, [r0], #1 + while(len) { + 1d26: 4298 cmp r0, r3 + 1d28: d1f9 bne.n 1d1e + * @param src pointer to the source area + */ +inline static void lv_area_copy(lv_area_t * dest, const lv_area_t * src) +{ + _lv_memcpy_small(dest, src, sizeof(lv_area_t)); +} + 1d2a: 4770 bx lr + +00001d2c : +{ + 1d2c: b5f0 push {r4, r5, r6, r7, lr} + if(lv_initialized) { + 1d2e: 4e20 ldr r6, [pc, #128] ; (1db0 ) + 1d30: 4d20 ldr r5, [pc, #128] ; (1db4 ) + 1d32: 7833 ldrb r3, [r6, #0] +{ + 1d34: b085 sub sp, #20 + if(lv_initialized) { + 1d36: b143 cbz r3, 1d4a + LV_LOG_WARN("lv_init: already inited"); + 1d38: 4b1f ldr r3, [pc, #124] ; (1db8 ) + 1d3a: 9300 str r3, [sp, #0] + 1d3c: 491f ldr r1, [pc, #124] ; (1dbc ) + 1d3e: 4b20 ldr r3, [pc, #128] ; (1dc0 ) + 1d40: 2278 movs r2, #120 ; 0x78 + 1d42: 2002 movs r0, #2 + LV_LOG_INFO("lv_init ready"); + 1d44: 47a8 blx r5 +} + 1d46: b005 add sp, #20 + 1d48: bdf0 pop {r4, r5, r6, r7, pc} + _lv_mem_init(); + 1d4a: 4b1e ldr r3, [pc, #120] ; (1dc4 ) + _lv_ll_init(&LV_GC_ROOT(_lv_obj_style_trans_ll), sizeof(lv_style_trans_t)); + 1d4c: 4c1e ldr r4, [pc, #120] ; (1dc8 ) + lv_theme_t * th = LV_THEME_DEFAULT_INIT(LV_THEME_DEFAULT_COLOR_PRIMARY, LV_THEME_DEFAULT_COLOR_SECONDARY, + 1d4e: 4f1f ldr r7, [pc, #124] ; (1dcc ) + _lv_mem_init(); + 1d50: 4798 blx r3 + _lv_task_core_init(); + 1d52: 4b1f ldr r3, [pc, #124] ; (1dd0 ) + 1d54: 4798 blx r3 + _lv_fs_init(); + 1d56: 4b1f ldr r3, [pc, #124] ; (1dd4 ) + 1d58: 4798 blx r3 + _lv_anim_core_init(); + 1d5a: 4b1f ldr r3, [pc, #124] ; (1dd8 ) + 1d5c: 4798 blx r3 + _lv_group_init(); + 1d5e: 4b1f ldr r3, [pc, #124] ; (1ddc ) + 1d60: 4798 blx r3 + _lv_ll_init(&LV_GC_ROOT(_lv_obj_style_trans_ll), sizeof(lv_style_trans_t)); + 1d62: 481f ldr r0, [pc, #124] ; (1de0 ) + 1d64: 2110 movs r1, #16 + 1d66: 47a0 blx r4 + lv_theme_t * th = LV_THEME_DEFAULT_INIT(LV_THEME_DEFAULT_COLOR_PRIMARY, LV_THEME_DEFAULT_COLOR_SECONDARY, + 1d68: 4b1e ldr r3, [pc, #120] ; (1de4 ) + 1d6a: 9300 str r3, [sp, #0] + 1d6c: 2202 movs r2, #2 + 1d6e: f04f 011f mov.w r1, #31 + 1d72: e9cd 3301 strd r3, r3, [sp, #4] + 1d76: f64f 0000 movw r0, #63488 ; 0xf800 + 1d7a: 47b8 blx r7 + lv_theme_set_act(th); + 1d7c: 4b1a ldr r3, [pc, #104] ; (1de8 ) + 1d7e: 4798 blx r3 + _lv_refr_init(); + 1d80: 4b1a ldr r3, [pc, #104] ; (1dec ) + 1d82: 4798 blx r3 + _lv_ll_init(&LV_GC_ROOT(_lv_disp_ll), sizeof(lv_disp_t)); + 1d84: 481a ldr r0, [pc, #104] ; (1df0 ) + 1d86: f44f 71b8 mov.w r1, #368 ; 0x170 + 1d8a: 47a0 blx r4 + _lv_ll_init(&LV_GC_ROOT(_lv_indev_ll), sizeof(lv_indev_t)); + 1d8c: 2160 movs r1, #96 ; 0x60 + 1d8e: 4819 ldr r0, [pc, #100] ; (1df4 ) + 1d90: 47a0 blx r4 + _lv_indev_init(); + 1d92: 4b19 ldr r3, [pc, #100] ; (1df8 ) + 1d94: 4798 blx r3 + _lv_img_decoder_init(); + 1d96: 4b19 ldr r3, [pc, #100] ; (1dfc ) + 1d98: 4798 blx r3 + lv_img_cache_set_size(LV_IMG_CACHE_DEF_SIZE); + 1d9a: 4b19 ldr r3, [pc, #100] ; (1e00 ) + 1d9c: 2001 movs r0, #1 + 1d9e: 4798 blx r3 + LV_LOG_INFO("lv_init ready"); + 1da0: 4b18 ldr r3, [pc, #96] ; (1e04 ) + 1da2: 9300 str r3, [sp, #0] + lv_initialized = true; + 1da4: 2001 movs r0, #1 + LV_LOG_INFO("lv_init ready"); + 1da6: 4b06 ldr r3, [pc, #24] ; (1dc0 ) + 1da8: 4904 ldr r1, [pc, #16] ; (1dbc ) + lv_initialized = true; + 1daa: 7030 strb r0, [r6, #0] + LV_LOG_INFO("lv_init ready"); + 1dac: 22a2 movs r2, #162 ; 0xa2 + 1dae: e7c9 b.n 1d44 + 1db0: 200080f4 .word 0x200080f4 + 1db4: 0000e8e9 .word 0x0000e8e9 + 1db8: 0001ee8a .word 0x0001ee8a + 1dbc: 0001ee5b .word 0x0001ee5b + 1dc0: 0001f062 .word 0x0001f062 + 1dc4: 0000ea15 .word 0x0000ea15 + 1dc8: 0000e605 .word 0x0000e605 + 1dcc: 00012509 .word 0x00012509 + 1dd0: 0000f831 .word 0x0000f831 + 1dd4: 0000e3d9 .word 0x0000e3d9 + 1dd8: 0000dc31 .word 0x0000dc31 + 1ddc: 00001a39 .word 0x00001a39 + 1de0: 20008660 .word 0x20008660 + 1de4: 20000010 .word 0x20000010 + 1de8: 000102cd .word 0x000102cd + 1dec: 00004f09 .word 0x00004f09 + 1df0: 2000860c .word 0x2000860c + 1df4: 20008618 .word 0x20008618 + 1df8: 00001c61 .word 0x00001c61 + 1dfc: 0000d0d5 .word 0x0000d0d5 + 1e00: 0000c6a9 .word 0x0000c6a9 + 1e04: 0001eea2 .word 0x0001eea2 + +00001e08 : +{ + 1e08: b573 push {r0, r1, r4, r5, r6, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 1e0a: 4b0e ldr r3, [pc, #56] ; (1e44 ) +{ + 1e0c: 4604 mov r4, r0 + 1e0e: 460e mov r6, r1 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 1e10: 4798 blx r3 + 1e12: 4605 mov r5, r0 + 1e14: b968 cbnz r0, 1e32 + 1e16: 4b0c ldr r3, [pc, #48] ; (1e48 ) + 1e18: 490c ldr r1, [pc, #48] ; (1e4c ) + 1e1a: 9300 str r3, [sp, #0] + 1e1c: f240 5294 movw r2, #1428 ; 0x594 + 1e20: 2003 movs r0, #3 + 1e22: 4e0b ldr r6, [pc, #44] ; (1e50 ) + 1e24: 47b0 blx r6 + 1e26: 480b ldr r0, [pc, #44] ; (1e54 ) + 1e28: 490b ldr r1, [pc, #44] ; (1e58 ) + 1e2a: 4622 mov r2, r4 + 1e2c: 462b mov r3, r5 + 1e2e: 4788 blx r1 + 1e30: e7fe b.n 1e30 + obj->adv_hittest = en == false ? 0 : 1; + 1e32: f894 3034 ldrb.w r3, [r4, #52] ; 0x34 + 1e36: f366 13c7 bfi r3, r6, #7, #1 + 1e3a: f884 3034 strb.w r3, [r4, #52] ; 0x34 +} + 1e3e: b002 add sp, #8 + 1e40: bd70 pop {r4, r5, r6, pc} + 1e42: bf00 nop + 1e44: 000017e1 .word 0x000017e1 + 1e48: 0001f0b7 .word 0x0001f0b7 + 1e4c: 0001ee5b .word 0x0001ee5b + 1e50: 0000e8e9 .word 0x0000e8e9 + 1e54: 0001eebf .word 0x0001eebf + 1e58: 000017e9 .word 0x000017e9 + +00001e5c : +{ + 1e5c: b573 push {r0, r1, r4, r5, r6, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 1e5e: 4b0e ldr r3, [pc, #56] ; (1e98 ) +{ + 1e60: 4604 mov r4, r0 + 1e62: 460e mov r6, r1 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 1e64: 4798 blx r3 + 1e66: 4605 mov r5, r0 + 1e68: b968 cbnz r0, 1e86 + 1e6a: 4b0c ldr r3, [pc, #48] ; (1e9c ) + 1e6c: 490c ldr r1, [pc, #48] ; (1ea0 ) + 1e6e: 9300 str r3, [sp, #0] + 1e70: f44f 62b4 mov.w r2, #1440 ; 0x5a0 + 1e74: 2003 movs r0, #3 + 1e76: 4e0b ldr r6, [pc, #44] ; (1ea4 ) + 1e78: 47b0 blx r6 + 1e7a: 480b ldr r0, [pc, #44] ; (1ea8 ) + 1e7c: 490b ldr r1, [pc, #44] ; (1eac ) + 1e7e: 4622 mov r2, r4 + 1e80: 462b mov r3, r5 + 1e82: 4788 blx r1 + 1e84: e7fe b.n 1e84 + obj->click = (en == true ? 1 : 0); + 1e86: f894 3034 ldrb.w r3, [r4, #52] ; 0x34 + 1e8a: f366 0300 bfi r3, r6, #0, #1 + 1e8e: f884 3034 strb.w r3, [r4, #52] ; 0x34 +} + 1e92: b002 add sp, #8 + 1e94: bd70 pop {r4, r5, r6, pc} + 1e96: bf00 nop + 1e98: 000017e1 .word 0x000017e1 + 1e9c: 0001f0ce .word 0x0001f0ce + 1ea0: 0001ee5b .word 0x0001ee5b + 1ea4: 0000e8e9 .word 0x0000e8e9 + 1ea8: 0001eebf .word 0x0001eebf + 1eac: 000017e9 .word 0x000017e9 + +00001eb0 : +{ + 1eb0: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} + 1eb4: 4680 mov r8, r0 + 1eb6: b087 sub sp, #28 + 1eb8: 4616 mov r6, r2 + 1eba: 461f mov r7, r3 + if(obj != NULL) { + 1ebc: 460c mov r4, r1 + 1ebe: b191 cbz r1, 1ee6 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 1ec0: 4b24 ldr r3, [pc, #144] ; (1f54 ) + 1ec2: 4608 mov r0, r1 + 1ec4: 4798 blx r3 + 1ec6: 4605 mov r5, r0 + 1ec8: b968 cbnz r0, 1ee6 + 1eca: 4b23 ldr r3, [pc, #140] ; (1f58 ) + 1ecc: 4923 ldr r1, [pc, #140] ; (1f5c ) + 1ece: 9300 str r3, [sp, #0] + 1ed0: f44f 62db mov.w r2, #1752 ; 0x6d8 + 1ed4: 2003 movs r0, #3 + 1ed6: 4e22 ldr r6, [pc, #136] ; (1f60 ) + 1ed8: 47b0 blx r6 + 1eda: 4822 ldr r0, [pc, #136] ; (1f64 ) + 1edc: 4922 ldr r1, [pc, #136] ; (1f68 ) + 1ede: 4622 mov r2, r4 + 1ee0: 462b mov r3, r5 + 1ee2: 4788 blx r1 + 1ee4: e7fe b.n 1ee4 + if(event_temp_data_head) { + 1ee6: 4d21 ldr r5, [pc, #132] ; (1f6c ) + event_temp_data.obj = obj; + 1ee8: 9403 str r4, [sp, #12] + event_temp_data.deleted = false; + 1eea: 2300 movs r3, #0 + 1eec: f88d 3010 strb.w r3, [sp, #16] + if(event_temp_data_head) { + 1ef0: 686b ldr r3, [r5, #4] + 1ef2: 9305 str r3, [sp, #20] + event_temp_data_head = &event_temp_data; + 1ef4: ab03 add r3, sp, #12 + 1ef6: 606b str r3, [r5, #4] + lv_indev_t * indev_act = lv_indev_get_act(); + 1ef8: 4b1d ldr r3, [pc, #116] ; (1f70 ) + const void * event_act_data_save = event_act_data; + 1efa: f8d5 9008 ldr.w r9, [r5, #8] + event_act_data = data; + 1efe: 60af str r7, [r5, #8] + lv_indev_t * indev_act = lv_indev_get_act(); + 1f00: 4798 blx r3 + if(indev_act) { + 1f02: b118 cbz r0, 1f0c + if(indev_act->driver.feedback_cb) indev_act->driver.feedback_cb(&indev_act->driver, event); + 1f04: 6883 ldr r3, [r0, #8] + 1f06: b10b cbz r3, 1f0c + 1f08: 4631 mov r1, r6 + 1f0a: 4798 blx r3 + if(event_xcb) event_xcb(obj, event); + 1f0c: f1b8 0f00 cmp.w r8, #0 + 1f10: d002 beq.n 1f18 + 1f12: 4631 mov r1, r6 + 1f14: 4620 mov r0, r4 + 1f16: 47c0 blx r8 + event_temp_data_head = event_temp_data_head->prev; + 1f18: 686b ldr r3, [r5, #4] + event_act_data = event_act_data_save; + 1f1a: f8c5 9008 str.w r9, [r5, #8] + event_temp_data_head = event_temp_data_head->prev; + 1f1e: 689b ldr r3, [r3, #8] + 1f20: 606b str r3, [r5, #4] + if(event_temp_data.deleted) { + 1f22: f89d 3010 ldrb.w r3, [sp, #16] + 1f26: b983 cbnz r3, 1f4a + if(obj) { + 1f28: b18c cbz r4, 1f4e + if(obj->parent_event && obj->parent) { + 1f2a: f894 3034 ldrb.w r3, [r4, #52] ; 0x34 + 1f2e: 065a lsls r2, r3, #25 + 1f30: d50d bpl.n 1f4e + 1f32: 6820 ldr r0, [r4, #0] + 1f34: b158 cbz r0, 1f4e + lv_res_t res = lv_event_send(obj->parent, event, data); + 1f36: 4b0f ldr r3, [pc, #60] ; (1f74 ) + 1f38: 463a mov r2, r7 + 1f3a: 4631 mov r1, r6 + 1f3c: 4798 blx r3 + return LV_RES_INV; + 1f3e: 1e43 subs r3, r0, #1 + 1f40: 4258 negs r0, r3 + 1f42: 4158 adcs r0, r3 +} + 1f44: b007 add sp, #28 + 1f46: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + return LV_RES_INV; + 1f4a: 2000 movs r0, #0 + 1f4c: e7fa b.n 1f44 + return LV_RES_OK; + 1f4e: 2001 movs r0, #1 + 1f50: e7f8 b.n 1f44 + 1f52: bf00 nop + 1f54: 000017e1 .word 0x000017e1 + 1f58: 0001f193 .word 0x0001f193 + 1f5c: 0001ee5b .word 0x0001ee5b + 1f60: 0000e8e9 .word 0x0000e8e9 + 1f64: 0001eebf .word 0x0001eebf + 1f68: 000017e9 .word 0x000017e9 + 1f6c: 200080f4 .word 0x200080f4 + 1f70: 00001c6d .word 0x00001c6d + 1f74: 00001f79 .word 0x00001f79 + +00001f78 : +{ + 1f78: b57f push {r0, r1, r2, r3, r4, r5, r6, lr} + 1f7a: 460e mov r6, r1 + 1f7c: 9203 str r2, [sp, #12] + if(obj == NULL) return LV_RES_OK; + 1f7e: 4604 mov r4, r0 + 1f80: b1d8 cbz r0, 1fba + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 1f82: 4a0f ldr r2, [pc, #60] ; (1fc0 ) + 1f84: 4790 blx r2 + 1f86: 9b03 ldr r3, [sp, #12] + 1f88: 4605 mov r5, r0 + 1f8a: b968 cbnz r0, 1fa8 + 1f8c: 4b0d ldr r3, [pc, #52] ; (1fc4 ) + 1f8e: 490e ldr r1, [pc, #56] ; (1fc8 ) + 1f90: 9300 str r3, [sp, #0] + 1f92: f240 62c4 movw r2, #1732 ; 0x6c4 + 1f96: 2003 movs r0, #3 + 1f98: 4e0c ldr r6, [pc, #48] ; (1fcc ) + 1f9a: 47b0 blx r6 + 1f9c: 480c ldr r0, [pc, #48] ; (1fd0 ) + 1f9e: 490d ldr r1, [pc, #52] ; (1fd4 ) + 1fa0: 4622 mov r2, r4 + 1fa2: 462b mov r3, r5 + 1fa4: 4788 blx r1 + 1fa6: e7fe b.n 1fa6 + res = lv_event_send_func(obj->event_cb, obj, event, data); + 1fa8: 69a0 ldr r0, [r4, #24] + 1faa: 4621 mov r1, r4 + 1fac: 4c0a ldr r4, [pc, #40] ; (1fd8 ) + 1fae: 4632 mov r2, r6 + 1fb0: 46a4 mov ip, r4 +} + 1fb2: b004 add sp, #16 + 1fb4: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + res = lv_event_send_func(obj->event_cb, obj, event, data); + 1fb8: 4760 bx ip +} + 1fba: 2001 movs r0, #1 + 1fbc: b004 add sp, #16 + 1fbe: bd70 pop {r4, r5, r6, pc} + 1fc0: 000017e1 .word 0x000017e1 + 1fc4: 0001f1a6 .word 0x0001f1a6 + 1fc8: 0001ee5b .word 0x0001ee5b + 1fcc: 0000e8e9 .word 0x0000e8e9 + 1fd0: 0001eebf .word 0x0001eebf + 1fd4: 000017e9 .word 0x000017e9 + 1fd8: 00001eb1 .word 0x00001eb1 + +00001fdc : +{ + 1fdc: b573 push {r0, r1, r4, r5, r6, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 1fde: 4b0b ldr r3, [pc, #44] ; (200c ) +{ + 1fe0: 4604 mov r4, r0 + 1fe2: 460e mov r6, r1 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 1fe4: 4798 blx r3 + 1fe6: 4605 mov r5, r0 + 1fe8: b968 cbnz r0, 2006 + 1fea: 4b09 ldr r3, [pc, #36] ; (2010 ) + 1fec: 4909 ldr r1, [pc, #36] ; (2014 ) + 1fee: 9300 str r3, [sp, #0] + 1ff0: f240 721b movw r2, #1819 ; 0x71b + 1ff4: 2003 movs r0, #3 + 1ff6: 4e08 ldr r6, [pc, #32] ; (2018 ) + 1ff8: 47b0 blx r6 + 1ffa: 4808 ldr r0, [pc, #32] ; (201c ) + 1ffc: 4908 ldr r1, [pc, #32] ; (2020 ) + 1ffe: 4622 mov r2, r4 + 2000: 462b mov r3, r5 + 2002: 4788 blx r1 + 2004: e7fe b.n 2004 + obj->signal_cb = signal_cb; + 2006: 61e6 str r6, [r4, #28] +} + 2008: b002 add sp, #8 + 200a: bd70 pop {r4, r5, r6, pc} + 200c: 000017e1 .word 0x000017e1 + 2010: 0001f1b4 .word 0x0001f1b4 + 2014: 0001ee5b .word 0x0001ee5b + 2018: 0000e8e9 .word 0x0000e8e9 + 201c: 0001eebf .word 0x0001eebf + 2020: 000017e9 .word 0x000017e9 + +00002024 : + if(obj == NULL) return LV_RES_OK; + 2024: b110 cbz r0, 202c + if(obj->signal_cb) res = obj->signal_cb(obj, signal, param); + 2026: 69c3 ldr r3, [r0, #28] + 2028: b103 cbz r3, 202c + 202a: 4718 bx r3 +} + 202c: 2001 movs r0, #1 + 202e: 4770 bx lr + +00002030 : +{ + 2030: b573 push {r0, r1, r4, r5, r6, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 2032: 4b0b ldr r3, [pc, #44] ; (2060 ) +{ + 2034: 4604 mov r4, r0 + 2036: 460e mov r6, r1 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 2038: 4798 blx r3 + 203a: 4605 mov r5, r0 + 203c: b968 cbnz r0, 205a + 203e: 4b09 ldr r3, [pc, #36] ; (2064 ) + 2040: 4909 ldr r1, [pc, #36] ; (2068 ) + 2042: 9300 str r3, [sp, #0] + 2044: f240 7237 movw r2, #1847 ; 0x737 + 2048: 2003 movs r0, #3 + 204a: 4e08 ldr r6, [pc, #32] ; (206c ) + 204c: 47b0 blx r6 + 204e: 4808 ldr r0, [pc, #32] ; (2070 ) + 2050: 4908 ldr r1, [pc, #32] ; (2074 ) + 2052: 4622 mov r2, r4 + 2054: 462b mov r3, r5 + 2056: 4788 blx r1 + 2058: e7fe b.n 2058 + obj->design_cb = design_cb; + 205a: 6226 str r6, [r4, #32] +} + 205c: b002 add sp, #8 + 205e: bd70 pop {r4, r5, r6, pc} + 2060: 000017e1 .word 0x000017e1 + 2064: 0001f1c9 .word 0x0001f1c9 + 2068: 0001ee5b .word 0x0001ee5b + 206c: 0000e8e9 .word 0x0000e8e9 + 2070: 0001eebf .word 0x0001eebf + 2074: 000017e9 .word 0x000017e9 + +00002078 : +{ + 2078: b57f push {r0, r1, r2, r3, r4, r5, r6, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 207a: 4b0e ldr r3, [pc, #56] ; (20b4 ) +{ + 207c: 9103 str r1, [sp, #12] + 207e: 4604 mov r4, r0 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 2080: 4798 blx r3 + 2082: 9903 ldr r1, [sp, #12] + 2084: 4605 mov r5, r0 + 2086: b968 cbnz r0, 20a4 + 2088: 4b0b ldr r3, [pc, #44] ; (20b8 ) + 208a: 490c ldr r1, [pc, #48] ; (20bc ) + 208c: 9300 str r3, [sp, #0] + 208e: f240 7249 movw r2, #1865 ; 0x749 + 2092: 2003 movs r0, #3 + 2094: 4e0a ldr r6, [pc, #40] ; (20c0 ) + 2096: 47b0 blx r6 + 2098: 480a ldr r0, [pc, #40] ; (20c4 ) + 209a: 490b ldr r1, [pc, #44] ; (20c8 ) + 209c: 4622 mov r2, r4 + 209e: 462b mov r3, r5 + 20a0: 4788 blx r1 + 20a2: e7fe b.n 20a2 + void * new_ext = lv_mem_realloc(obj->ext_attr, ext_size); + 20a4: 6a60 ldr r0, [r4, #36] ; 0x24 + 20a6: 4b09 ldr r3, [pc, #36] ; (20cc ) + 20a8: 4798 blx r3 + if(new_ext == NULL) return NULL; + 20aa: b100 cbz r0, 20ae + obj->ext_attr = new_ext; + 20ac: 6260 str r0, [r4, #36] ; 0x24 +} + 20ae: b004 add sp, #16 + 20b0: bd70 pop {r4, r5, r6, pc} + 20b2: bf00 nop + 20b4: 000017e1 .word 0x000017e1 + 20b8: 0001f1de .word 0x0001f1de + 20bc: 0001ee5b .word 0x0001ee5b + 20c0: 0000e8e9 .word 0x0000e8e9 + 20c4: 0001eebf .word 0x0001eebf + 20c8: 000017e9 .word 0x000017e9 + 20cc: 0000ee15 .word 0x0000ee15 + +000020d0 : +{ + 20d0: b573 push {r0, r1, r4, r5, r6, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 20d2: 4b0e ldr r3, [pc, #56] ; (210c ) +{ + 20d4: 4604 mov r4, r0 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 20d6: 4798 blx r3 + 20d8: 4605 mov r5, r0 + 20da: b968 cbnz r0, 20f8 + 20dc: 4b0c ldr r3, [pc, #48] ; (2110 ) + 20de: 490d ldr r1, [pc, #52] ; (2114 ) + 20e0: 9300 str r3, [sp, #0] + 20e2: f240 7259 movw r2, #1881 ; 0x759 + 20e6: 2003 movs r0, #3 + 20e8: 4e0b ldr r6, [pc, #44] ; (2118 ) + 20ea: 47b0 blx r6 + 20ec: 480b ldr r0, [pc, #44] ; (211c ) + 20ee: 490c ldr r1, [pc, #48] ; (2120 ) + 20f0: 4622 mov r2, r4 + 20f2: 462b mov r3, r5 + 20f4: 4788 blx r1 + 20f6: e7fe b.n 20f6 + obj->signal_cb(obj, LV_SIGNAL_REFR_EXT_DRAW_PAD, NULL); + 20f8: 69e3 ldr r3, [r4, #28] + obj->ext_draw_pad = 0; + 20fa: 2200 movs r2, #0 + obj->signal_cb(obj, LV_SIGNAL_REFR_EXT_DRAW_PAD, NULL); + 20fc: 2106 movs r1, #6 + 20fe: 4620 mov r0, r4 + obj->ext_draw_pad = 0; + 2100: 8662 strh r2, [r4, #50] ; 0x32 +} + 2102: b002 add sp, #8 + 2104: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + obj->signal_cb(obj, LV_SIGNAL_REFR_EXT_DRAW_PAD, NULL); + 2108: 4718 bx r3 + 210a: bf00 nop + 210c: 000017e1 .word 0x000017e1 + 2110: 0001f1f7 .word 0x0001f1f7 + 2114: 0001ee5b .word 0x0001ee5b + 2118: 0000e8e9 .word 0x0000e8e9 + 211c: 0001eebf .word 0x0001eebf + 2120: 000017e9 .word 0x000017e9 + +00002124 : +{ + 2124: b573 push {r0, r1, r4, r5, r6, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 2126: 4b0b ldr r3, [pc, #44] ; (2154 ) +{ + 2128: 4604 mov r4, r0 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 212a: 4798 blx r3 + 212c: 4605 mov r5, r0 + 212e: b968 cbnz r0, 214c + 2130: 4b09 ldr r3, [pc, #36] ; (2158 ) + 2132: 490a ldr r1, [pc, #40] ; (215c ) + 2134: 9300 str r3, [sp, #0] + 2136: f240 729f movw r2, #1951 ; 0x79f + 213a: 2003 movs r0, #3 + 213c: 4e08 ldr r6, [pc, #32] ; (2160 ) + 213e: 47b0 blx r6 + 2140: 4808 ldr r0, [pc, #32] ; (2164 ) + 2142: 4909 ldr r1, [pc, #36] ; (2168 ) + 2144: 4622 mov r2, r4 + 2146: 462b mov r3, r5 + 2148: 4788 blx r1 + 214a: e7fe b.n 214a +} + 214c: 6820 ldr r0, [r4, #0] + 214e: b002 add sp, #8 + 2150: bd70 pop {r4, r5, r6, pc} + 2152: bf00 nop + 2154: 000017e1 .word 0x000017e1 + 2158: 0001f213 .word 0x0001f213 + 215c: 0001ee5b .word 0x0001ee5b + 2160: 0000e8e9 .word 0x0000e8e9 + 2164: 0001eebf .word 0x0001eebf + 2168: 000017e9 .word 0x000017e9 + +0000216c : +{ + 216c: b573 push {r0, r1, r4, r5, r6, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 216e: 4b0e ldr r3, [pc, #56] ; (21a8 ) +{ + 2170: 4604 mov r4, r0 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 2172: 4798 blx r3 + 2174: 4605 mov r5, r0 + 2176: b148 cbz r0, 218c + par = lv_obj_get_parent(act_p); + 2178: 4e0c ldr r6, [pc, #48] ; (21ac ) + 217a: 4620 mov r0, r4 + 217c: 47b0 blx r6 + } while(par != NULL); + 217e: 4625 mov r5, r4 + 2180: 4604 mov r4, r0 + 2182: 2800 cmp r0, #0 + 2184: d1f9 bne.n 217a +} + 2186: 4628 mov r0, r5 + 2188: b002 add sp, #8 + 218a: bd70 pop {r4, r5, r6, pc} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 218c: 4b08 ldr r3, [pc, #32] ; (21b0 ) + 218e: 4909 ldr r1, [pc, #36] ; (21b4 ) + 2190: 9300 str r3, [sp, #0] + 2192: f240 726b movw r2, #1899 ; 0x76b + 2196: 2003 movs r0, #3 + 2198: 4e07 ldr r6, [pc, #28] ; (21b8 ) + 219a: 47b0 blx r6 + 219c: 4807 ldr r0, [pc, #28] ; (21bc ) + 219e: 4908 ldr r1, [pc, #32] ; (21c0 ) + 21a0: 4622 mov r2, r4 + 21a2: 462b mov r3, r5 + 21a4: 4788 blx r1 + 21a6: e7fe b.n 21a6 + 21a8: 000017e1 .word 0x000017e1 + 21ac: 00002125 .word 0x00002125 + 21b0: 0001f225 .word 0x0001f225 + 21b4: 0001ee5b .word 0x0001ee5b + 21b8: 0000e8e9 .word 0x0000e8e9 + 21bc: 0001eebf .word 0x0001eebf + 21c0: 000017e9 .word 0x000017e9 + +000021c4 : +{ + 21c4: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 21c8: 4b1e ldr r3, [pc, #120] ; (2244 ) +{ + 21ca: 4605 mov r5, r0 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 21cc: 4798 blx r3 + 21ce: 4604 mov r4, r0 + 21d0: b968 cbnz r0, 21ee + 21d2: 4b1d ldr r3, [pc, #116] ; (2248 ) + 21d4: 491d ldr r1, [pc, #116] ; (224c ) + 21d6: 9300 str r3, [sp, #0] + 21d8: f240 727f movw r2, #1919 ; 0x77f + 21dc: 2003 movs r0, #3 + 21de: 4e1c ldr r6, [pc, #112] ; (2250 ) + 21e0: 47b0 blx r6 + 21e2: 481c ldr r0, [pc, #112] ; (2254 ) + 21e4: 491c ldr r1, [pc, #112] ; (2258 ) + 21e6: 462a mov r2, r5 + 21e8: 4623 mov r3, r4 + 21ea: 4788 blx r1 + 21ec: e7fe b.n 21ec + if(obj->parent == NULL) + 21ee: 682b ldr r3, [r5, #0] + 21f0: b11b cbz r3, 21fa + scr = lv_obj_get_screen(obj); /*get the screen of `obj`*/ + 21f2: 4628 mov r0, r5 + 21f4: 4b19 ldr r3, [pc, #100] ; (225c ) + 21f6: 4798 blx r3 + 21f8: 4605 mov r5, r0 + _LV_LL_READ(LV_GC_ROOT(_lv_disp_ll), d) { + 21fa: 4819 ldr r0, [pc, #100] ; (2260 ) + 21fc: 4e19 ldr r6, [pc, #100] ; (2264 ) + _LV_LL_READ(d->scr_ll, s) { + 21fe: 4f1a ldr r7, [pc, #104] ; (2268 ) + _LV_LL_READ(LV_GC_ROOT(_lv_disp_ll), d) { + 2200: f8df 805c ldr.w r8, [pc, #92] ; 2260 + 2204: 47b0 blx r6 + 2206: 4604 mov r4, r0 + 2208: b964 cbnz r4, 2224 + LV_LOG_WARN("lv_scr_get_disp: screen not found") + 220a: 4b18 ldr r3, [pc, #96] ; (226c ) + 220c: 9300 str r3, [sp, #0] + 220e: 490f ldr r1, [pc, #60] ; (224c ) + 2210: 4b0d ldr r3, [pc, #52] ; (2248 ) + 2212: 4d0f ldr r5, [pc, #60] ; (2250 ) + 2214: f44f 62f2 mov.w r2, #1936 ; 0x790 + 2218: 2002 movs r0, #2 + 221a: 47a8 blx r5 +} + 221c: 4620 mov r0, r4 + 221e: b003 add sp, #12 + 2220: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + _LV_LL_READ(d->scr_ll, s) { + 2224: f104 0930 add.w r9, r4, #48 ; 0x30 + 2228: 4648 mov r0, r9 + 222a: 47b0 blx r6 + 222c: b920 cbnz r0, 2238 + _LV_LL_READ(LV_GC_ROOT(_lv_disp_ll), d) { + 222e: 4621 mov r1, r4 + 2230: 4640 mov r0, r8 + 2232: 47b8 blx r7 + 2234: 4604 mov r4, r0 + 2236: e7e7 b.n 2208 + if(s == scr) return d; + 2238: 4285 cmp r5, r0 + 223a: d0ef beq.n 221c + _LV_LL_READ(d->scr_ll, s) { + 223c: 4601 mov r1, r0 + 223e: 4648 mov r0, r9 + 2240: 47b8 blx r7 + 2242: e7f3 b.n 222c + 2244: 000017e1 .word 0x000017e1 + 2248: 0001f237 .word 0x0001f237 + 224c: 0001ee5b .word 0x0001ee5b + 2250: 0000e8e9 .word 0x0000e8e9 + 2254: 0001eebf .word 0x0001eebf + 2258: 000017e9 .word 0x000017e9 + 225c: 0000216d .word 0x0000216d + 2260: 2000860c .word 0x2000860c + 2264: 0000e6a9 .word 0x0000e6a9 + 2268: 0000e6b5 .word 0x0000e6b5 + 226c: 0001eecc .word 0x0001eecc + +00002270 : +{ + 2270: b573 push {r0, r1, r4, r5, r6, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 2272: 4b10 ldr r3, [pc, #64] ; (22b4 ) +{ + 2274: 4604 mov r4, r0 + 2276: 460d mov r5, r1 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 2278: 4798 blx r3 + 227a: 4606 mov r6, r0 + 227c: b968 cbnz r0, 229a + 227e: 4b0e ldr r3, [pc, #56] ; (22b8 ) + 2280: 490e ldr r1, [pc, #56] ; (22bc ) + 2282: 9300 str r3, [sp, #0] + 2284: f240 72ad movw r2, #1965 ; 0x7ad + 2288: 2003 movs r0, #3 + 228a: 4d0d ldr r5, [pc, #52] ; (22c0 ) + 228c: 47a8 blx r5 + 228e: 480d ldr r0, [pc, #52] ; (22c4 ) + 2290: 490d ldr r1, [pc, #52] ; (22c8 ) + 2292: 4622 mov r2, r4 + 2294: 4633 mov r3, r6 + 2296: 4788 blx r1 + 2298: e7fe b.n 2298 + result = _lv_ll_get_head(&obj->child_ll); + 229a: 1d20 adds r0, r4, #4 + if(child == NULL) { + 229c: b925 cbnz r5, 22a8 + result = _lv_ll_get_head(&obj->child_ll); + 229e: 4b0b ldr r3, [pc, #44] ; (22cc ) +} + 22a0: b002 add sp, #8 + 22a2: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + result = _lv_ll_get_head(&obj->child_ll); + 22a6: 4718 bx r3 + result = _lv_ll_get_next(&obj->child_ll, child); + 22a8: 4b09 ldr r3, [pc, #36] ; (22d0 ) + 22aa: 4629 mov r1, r5 +} + 22ac: b002 add sp, #8 + 22ae: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + result = _lv_ll_get_next(&obj->child_ll, child); + 22b2: 4718 bx r3 + 22b4: 000017e1 .word 0x000017e1 + 22b8: 0001f247 .word 0x0001f247 + 22bc: 0001ee5b .word 0x0001ee5b + 22c0: 0000e8e9 .word 0x0000e8e9 + 22c4: 0001eebf .word 0x0001eebf + 22c8: 000017e9 .word 0x000017e9 + 22cc: 0000e6a9 .word 0x0000e6a9 + 22d0: 0000e6b5 .word 0x0000e6b5 + +000022d4 : +{ + 22d4: b573 push {r0, r1, r4, r5, r6, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 22d6: 4b0e ldr r3, [pc, #56] ; (2310 ) +{ + 22d8: 4604 mov r4, r0 + 22da: 460e mov r6, r1 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 22dc: 4798 blx r3 + 22de: 4605 mov r5, r0 + 22e0: b968 cbnz r0, 22fe + 22e2: 4b0c ldr r3, [pc, #48] ; (2314 ) + 22e4: 490c ldr r1, [pc, #48] ; (2318 ) + 22e6: 9300 str r3, [sp, #0] + 22e8: f640 0201 movw r2, #2049 ; 0x801 + 22ec: 2003 movs r0, #3 + 22ee: 4e0b ldr r6, [pc, #44] ; (231c ) + 22f0: 47b0 blx r6 + 22f2: 480b ldr r0, [pc, #44] ; (2320 ) + 22f4: 490b ldr r1, [pc, #44] ; (2324 ) + 22f6: 4622 mov r2, r4 + 22f8: 462b mov r3, r5 + 22fa: 4788 blx r1 + 22fc: e7fe b.n 22fc + lv_area_copy(cords_p, &obj->coords); + 22fe: 4b0a ldr r3, [pc, #40] ; (2328 ) + 2300: f104 0110 add.w r1, r4, #16 + 2304: 4630 mov r0, r6 +} + 2306: b002 add sp, #8 + 2308: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + lv_area_copy(cords_p, &obj->coords); + 230c: 4718 bx r3 + 230e: bf00 nop + 2310: 000017e1 .word 0x000017e1 + 2314: 0001f2b8 .word 0x0001f2b8 + 2318: 0001ee5b .word 0x0001ee5b + 231c: 0000e8e9 .word 0x0000e8e9 + 2320: 0001eebf .word 0x0001eebf + 2324: 000017e9 .word 0x000017e9 + 2328: 00001d19 .word 0x00001d19 + +0000232c : +{ + 232c: b573 push {r0, r1, r4, r5, r6, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 232e: 4b10 ldr r3, [pc, #64] ; (2370 ) +{ + 2330: 4604 mov r4, r0 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 2332: 4798 blx r3 + 2334: 4605 mov r5, r0 + 2336: b968 cbnz r0, 2354 + 2338: 4b0e ldr r3, [pc, #56] ; (2374 ) + 233a: 490f ldr r1, [pc, #60] ; (2378 ) + 233c: 9300 str r3, [sp, #0] + 233e: f640 0222 movw r2, #2082 ; 0x822 + 2342: 2003 movs r0, #3 + 2344: 4e0d ldr r6, [pc, #52] ; (237c ) + 2346: 47b0 blx r6 + 2348: 480d ldr r0, [pc, #52] ; (2380 ) + 234a: 490e ldr r1, [pc, #56] ; (2384 ) + 234c: 4622 mov r2, r4 + 234e: 462b mov r3, r5 + 2350: 4788 blx r1 + 2352: e7fe b.n 2352 + lv_obj_t * parent = lv_obj_get_parent(obj); + 2354: 4b0c ldr r3, [pc, #48] ; (2388 ) + 2356: 4620 mov r0, r4 + 2358: 4798 blx r3 + if(parent) { + 235a: b128 cbz r0, 2368 + rel_x = obj->coords.x1 - parent->coords.x1; + 235c: 8a23 ldrh r3, [r4, #16] + 235e: 8a02 ldrh r2, [r0, #16] + 2360: 1a98 subs r0, r3, r2 + 2362: b200 sxth r0, r0 +} + 2364: b002 add sp, #8 + 2366: bd70 pop {r4, r5, r6, pc} + rel_x = obj->coords.x1; + 2368: f9b4 0010 ldrsh.w r0, [r4, #16] + 236c: e7fa b.n 2364 + 236e: bf00 nop + 2370: 000017e1 .word 0x000017e1 + 2374: 0001f2ca .word 0x0001f2ca + 2378: 0001ee5b .word 0x0001ee5b + 237c: 0000e8e9 .word 0x0000e8e9 + 2380: 0001eebf .word 0x0001eebf + 2384: 000017e9 .word 0x000017e9 + 2388: 00002125 .word 0x00002125 + +0000238c : +{ + 238c: b573 push {r0, r1, r4, r5, r6, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 238e: 4b10 ldr r3, [pc, #64] ; (23d0 ) +{ + 2390: 4604 mov r4, r0 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 2392: 4798 blx r3 + 2394: 4605 mov r5, r0 + 2396: b968 cbnz r0, 23b4 + 2398: 4b0e ldr r3, [pc, #56] ; (23d4 ) + 239a: 490f ldr r1, [pc, #60] ; (23d8 ) + 239c: 9300 str r3, [sp, #0] + 239e: f640 0236 movw r2, #2102 ; 0x836 + 23a2: 2003 movs r0, #3 + 23a4: 4e0d ldr r6, [pc, #52] ; (23dc ) + 23a6: 47b0 blx r6 + 23a8: 480d ldr r0, [pc, #52] ; (23e0 ) + 23aa: 490e ldr r1, [pc, #56] ; (23e4 ) + 23ac: 4622 mov r2, r4 + 23ae: 462b mov r3, r5 + 23b0: 4788 blx r1 + 23b2: e7fe b.n 23b2 + lv_obj_t * parent = lv_obj_get_parent(obj); + 23b4: 4b0c ldr r3, [pc, #48] ; (23e8 ) + 23b6: 4620 mov r0, r4 + 23b8: 4798 blx r3 + if(parent) { + 23ba: b128 cbz r0, 23c8 + rel_y = obj->coords.y1 - parent->coords.y1; + 23bc: 8a63 ldrh r3, [r4, #18] + 23be: 8a42 ldrh r2, [r0, #18] + 23c0: 1a98 subs r0, r3, r2 + 23c2: b200 sxth r0, r0 +} + 23c4: b002 add sp, #8 + 23c6: bd70 pop {r4, r5, r6, pc} + rel_y = obj->coords.y1; + 23c8: f9b4 0012 ldrsh.w r0, [r4, #18] + 23cc: e7fa b.n 23c4 + 23ce: bf00 nop + 23d0: 000017e1 .word 0x000017e1 + 23d4: 0001f2d7 .word 0x0001f2d7 + 23d8: 0001ee5b .word 0x0001ee5b + 23dc: 0000e8e9 .word 0x0000e8e9 + 23e0: 0001eebf .word 0x0001eebf + 23e4: 000017e9 .word 0x000017e9 + 23e8: 00002125 .word 0x00002125 + +000023ec : +{ + 23ec: b573 push {r0, r1, r4, r5, r6, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 23ee: 4b0d ldr r3, [pc, #52] ; (2424 ) +{ + 23f0: 4604 mov r4, r0 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 23f2: 4798 blx r3 + 23f4: 4605 mov r5, r0 + 23f6: b968 cbnz r0, 2414 + 23f8: 4b0b ldr r3, [pc, #44] ; (2428 ) + 23fa: 490c ldr r1, [pc, #48] ; (242c ) + 23fc: 9300 str r3, [sp, #0] + 23fe: f640 024a movw r2, #2122 ; 0x84a + 2402: 2003 movs r0, #3 + 2404: 4e0a ldr r6, [pc, #40] ; (2430 ) + 2406: 47b0 blx r6 + 2408: 480a ldr r0, [pc, #40] ; (2434 ) + 240a: 490b ldr r1, [pc, #44] ; (2438 ) + 240c: 4622 mov r2, r4 + 240e: 462b mov r3, r5 + 2410: 4788 blx r1 + 2412: e7fe b.n 2412 + * @param area_p pointer to an area + * @return the width of the area (if x1 == x2 -> width = 1) + */ +static inline lv_coord_t lv_area_get_width(const lv_area_t * area_p) +{ + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + 2414: 8aa3 ldrh r3, [r4, #20] + 2416: 8a22 ldrh r2, [r4, #16] + 2418: 3301 adds r3, #1 + 241a: 1a98 subs r0, r3, r2 +} + 241c: b200 sxth r0, r0 + 241e: b002 add sp, #8 + 2420: bd70 pop {r4, r5, r6, pc} + 2422: bf00 nop + 2424: 000017e1 .word 0x000017e1 + 2428: 0001f2e4 .word 0x0001f2e4 + 242c: 0001ee5b .word 0x0001ee5b + 2430: 0000e8e9 .word 0x0000e8e9 + 2434: 0001eebf .word 0x0001eebf + 2438: 000017e9 .word 0x000017e9 + +0000243c : +{ + 243c: b573 push {r0, r1, r4, r5, r6, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 243e: 4b0d ldr r3, [pc, #52] ; (2474 ) +{ + 2440: 4604 mov r4, r0 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 2442: 4798 blx r3 + 2444: 4605 mov r5, r0 + 2446: b968 cbnz r0, 2464 + 2448: 4b0b ldr r3, [pc, #44] ; (2478 ) + 244a: 490c ldr r1, [pc, #48] ; (247c ) + 244c: 9300 str r3, [sp, #0] + 244e: f640 0256 movw r2, #2134 ; 0x856 + 2452: 2003 movs r0, #3 + 2454: 4e0a ldr r6, [pc, #40] ; (2480 ) + 2456: 47b0 blx r6 + 2458: 480a ldr r0, [pc, #40] ; (2484 ) + 245a: 490b ldr r1, [pc, #44] ; (2488 ) + 245c: 4622 mov r2, r4 + 245e: 462b mov r3, r5 + 2460: 4788 blx r1 + 2462: e7fe b.n 2462 + * @param area_p pointer to an area + * @return the height of the area (if y1 == y2 -> height = 1) + */ +static inline lv_coord_t lv_area_get_height(const lv_area_t * area_p) +{ + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + 2464: 8ae3 ldrh r3, [r4, #22] + 2466: 8a62 ldrh r2, [r4, #18] + 2468: 3301 adds r3, #1 + 246a: 1a98 subs r0, r3, r2 +} + 246c: b200 sxth r0, r0 + 246e: b002 add sp, #8 + 2470: bd70 pop {r4, r5, r6, pc} + 2472: bf00 nop + 2474: 000017e1 .word 0x000017e1 + 2478: 0001f2f5 .word 0x0001f2f5 + 247c: 0001ee5b .word 0x0001ee5b + 2480: 0000e8e9 .word 0x0000e8e9 + 2484: 0001eebf .word 0x0001eebf + 2488: 000017e9 .word 0x000017e9 + +0000248c : +{ + 248c: b513 push {r0, r1, r4, lr} + if(part == LV_OBJ_PART_MAIN) return &((lv_obj_t *)obj)->style_list; + 248e: b911 cbnz r1, 2496 + 2490: 3028 adds r0, #40 ; 0x28 +} + 2492: b002 add sp, #8 + 2494: bd10 pop {r4, pc} + info.part = part; + 2496: f88d 1000 strb.w r1, [sp] + info.result = NULL; + 249a: 2400 movs r4, #0 + res = lv_signal_send((lv_obj_t *)obj, LV_SIGNAL_GET_STYLE, &info); + 249c: 4b04 ldr r3, [pc, #16] ; (24b0 ) + info.result = NULL; + 249e: 9401 str r4, [sp, #4] + res = lv_signal_send((lv_obj_t *)obj, LV_SIGNAL_GET_STYLE, &info); + 24a0: 466a mov r2, sp + 24a2: 2108 movs r1, #8 + 24a4: 4798 blx r3 + if(res != LV_RES_OK) return NULL; + 24a6: 2801 cmp r0, #1 + return info.result; + 24a8: bf0c ite eq + 24aa: 9801 ldreq r0, [sp, #4] + if(res != LV_RES_OK) return NULL; + 24ac: 4620 movne r0, r4 + 24ae: e7f0 b.n 2492 + 24b0: 00002025 .word 0x00002025 + +000024b4 : + * @param part a part of object or 0xFF to remove from all parts + * @param prop a property or 0xFF to remove all porpeties + * @param tr_limit delete transitions only "older" then this. `NULL` is not used + */ +static void trans_del(lv_obj_t * obj, uint8_t part, lv_style_property_t prop, lv_style_trans_t * tr_limit) +{ + 24b4: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} + 24b8: 4607 mov r7, r0 + 24ba: 4698 mov r8, r3 + lv_style_trans_t * tr; + lv_style_trans_t * tr_prev; + tr = _lv_ll_get_tail(&LV_GC_ROOT(_lv_obj_style_trans_ll)); + 24bc: 4819 ldr r0, [pc, #100] ; (2524 ) + 24be: 4b1a ldr r3, [pc, #104] ; (2528 ) + while(tr != NULL) { + if(tr == tr_limit) break; + + /*'tr' might be deleted, so get the next object while 'tr' is valid*/ + tr_prev = _lv_ll_get_prev(&LV_GC_ROOT(_lv_obj_style_trans_ll), tr); + 24c0: f8df 9060 ldr.w r9, [pc, #96] ; 2524 + + if(tr->obj == obj && (part == tr->part || part == 0xFF) && (prop == tr->prop || prop == 0xFF)) { + /* Remove the transitioned property from trans. style + * to allow changing it by normal styles*/ + lv_style_list_t * list = lv_obj_get_style_list(tr->obj, tr->part); + 24c4: f8df b07c ldr.w fp, [pc, #124] ; 2544 +{ + 24c8: 460d mov r5, r1 + 24ca: 4616 mov r6, r2 + tr = _lv_ll_get_tail(&LV_GC_ROOT(_lv_obj_style_trans_ll)); + 24cc: 4798 blx r3 + 24ce: 4604 mov r4, r0 + while(tr != NULL) { + 24d0: b90c cbnz r4, 24d6 + _lv_ll_remove(&LV_GC_ROOT(_lv_obj_style_trans_ll), tr); + lv_mem_free(tr); + } + tr = tr_prev; + } +} + 24d2: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} + if(tr == tr_limit) break; + 24d6: 4544 cmp r4, r8 + 24d8: d0fb beq.n 24d2 + tr_prev = _lv_ll_get_prev(&LV_GC_ROOT(_lv_obj_style_trans_ll), tr); + 24da: 4b14 ldr r3, [pc, #80] ; (252c ) + 24dc: 4621 mov r1, r4 + 24de: 4648 mov r0, r9 + 24e0: 4798 blx r3 + 24e2: 4682 mov sl, r0 + if(tr->obj == obj && (part == tr->part || part == 0xFF) && (prop == tr->prop || prop == 0xFF)) { + 24e4: 6820 ldr r0, [r4, #0] + 24e6: 42b8 cmp r0, r7 + 24e8: d11a bne.n 2520 + 24ea: 79a1 ldrb r1, [r4, #6] + 24ec: 42a9 cmp r1, r5 + 24ee: d001 beq.n 24f4 + 24f0: 2dff cmp r5, #255 ; 0xff + 24f2: d115 bne.n 2520 + 24f4: 88a2 ldrh r2, [r4, #4] + 24f6: 42b2 cmp r2, r6 + 24f8: d001 beq.n 24fe + 24fa: 2eff cmp r6, #255 ; 0xff + 24fc: d110 bne.n 2520 + lv_style_list_t * list = lv_obj_get_style_list(tr->obj, tr->part); + 24fe: 47d8 blx fp + lv_style_t * style_trans = _lv_style_list_get_transition_style(list); + 2500: 4a0b ldr r2, [pc, #44] ; (2530 ) + 2502: 4790 blx r2 + lv_style_remove_prop(style_trans, tr->prop); + 2504: 88a1 ldrh r1, [r4, #4] + 2506: 4a0b ldr r2, [pc, #44] ; (2534 ) + 2508: 4790 blx r2 + lv_anim_del(tr, NULL); + 250a: 4a0b ldr r2, [pc, #44] ; (2538 ) + 250c: 2100 movs r1, #0 + 250e: 4620 mov r0, r4 + 2510: 4790 blx r2 + _lv_ll_remove(&LV_GC_ROOT(_lv_obj_style_trans_ll), tr); + 2512: 4a0a ldr r2, [pc, #40] ; (253c ) + 2514: 4648 mov r0, r9 + 2516: 4621 mov r1, r4 + 2518: 4790 blx r2 + lv_mem_free(tr); + 251a: 4a09 ldr r2, [pc, #36] ; (2540 ) + 251c: 4620 mov r0, r4 + 251e: 4790 blx r2 +{ + 2520: 4654 mov r4, sl + 2522: e7d5 b.n 24d0 + 2524: 20008660 .word 0x20008660 + 2528: 0000e6af .word 0x0000e6af + 252c: 0000e6d5 .word 0x0000e6d5 + 2530: 00005cb9 .word 0x00005cb9 + 2534: 00005811 .word 0x00005811 + 2538: 0000dcb1 .word 0x0000dcb1 + 253c: 0000e76d .word 0x0000e76d + 2540: 0000eae5 .word 0x0000eae5 + 2544: 0000248d .word 0x0000248d + +00002548 : +{ + 2548: b537 push {r0, r1, r2, r4, r5, lr} + lv_style_list_t * style_dsc = lv_obj_get_style_list(obj, part); + 254a: 4b0e ldr r3, [pc, #56] ; (2584 ) +{ + 254c: 4604 mov r4, r0 + 254e: 460d mov r5, r1 + lv_style_list_t * style_dsc = lv_obj_get_style_list(obj, part); + 2550: 4798 blx r3 + if(style_dsc == NULL) { + 2552: b950 cbnz r0, 256a + LV_LOG_WARN("lv_obj_clean_style_list: can't find style with `part`"); + 2554: 4b0c ldr r3, [pc, #48] ; (2588 ) + 2556: 9300 str r3, [sp, #0] + 2558: 490c ldr r1, [pc, #48] ; (258c ) + 255a: 4b0d ldr r3, [pc, #52] ; (2590 ) + 255c: 4c0d ldr r4, [pc, #52] ; (2594 ) + 255e: f240 4292 movw r2, #1170 ; 0x492 + 2562: 2002 movs r0, #2 + 2564: 47a0 blx r4 +} + 2566: b003 add sp, #12 + 2568: bd30 pop {r4, r5, pc} + _lv_style_list_reset(style_dsc); + 256a: 4b0b ldr r3, [pc, #44] ; (2598 ) + 256c: 4798 blx r3 + trans_del(obj, part, 0xFF, NULL); + 256e: 4620 mov r0, r4 + 2570: 4c0a ldr r4, [pc, #40] ; (259c ) + 2572: 2300 movs r3, #0 + 2574: 22ff movs r2, #255 ; 0xff + 2576: 4629 mov r1, r5 + 2578: 46a4 mov ip, r4 +} + 257a: b003 add sp, #12 + 257c: e8bd 4030 ldmia.w sp!, {r4, r5, lr} + trans_del(obj, part, 0xFF, NULL); + 2580: 4760 bx ip + 2582: bf00 nop + 2584: 0000248d .word 0x0000248d + 2588: 0001ef14 .word 0x0001ef14 + 258c: 0001ee5b .word 0x0001ee5b + 2590: 0001f3b1 .word 0x0001f3b1 + 2594: 0000e8e9 .word 0x0000e8e9 + 2598: 00005cc9 .word 0x00005cc9 + 259c: 000024b5 .word 0x000024b5 + +000025a0 : + tr->prop = prop_tmp; + +} + +static void trans_anim_ready_cb(lv_anim_t * a) +{ + 25a0: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + * if there no more transitions for this property + * It allows changing it by normal styles*/ + + bool running = false; + lv_style_trans_t * tr_i; + _LV_LL_READ(LV_GC_ROOT(_lv_obj_style_trans_ll), tr_i) { + 25a4: 4b15 ldr r3, [pc, #84] ; (25fc ) + lv_style_trans_t * tr = a->var; + 25a6: 6804 ldr r4, [r0, #0] + _LV_LL_READ(LV_GC_ROOT(_lv_obj_style_trans_ll), tr_i) { + 25a8: 4815 ldr r0, [pc, #84] ; (2600 ) + 25aa: 4e15 ldr r6, [pc, #84] ; (2600 ) + 25ac: 4f15 ldr r7, [pc, #84] ; (2604 ) + 25ae: 4798 blx r3 + bool running = false; + 25b0: 2500 movs r5, #0 + _LV_LL_READ(LV_GC_ROOT(_lv_obj_style_trans_ll), tr_i) { + 25b2: b990 cbnz r0, 25da + if(tr_i != tr && tr_i->obj == tr->obj && tr_i->part == tr->part && tr_i->prop == tr->prop) { + running = true; + } + } + + if(!running) { + 25b4: b945 cbnz r5, 25c8 + lv_style_list_t * list = lv_obj_get_style_list(tr->obj, tr->part); + 25b6: 79a1 ldrb r1, [r4, #6] + 25b8: 4b13 ldr r3, [pc, #76] ; (2608 ) + 25ba: 6820 ldr r0, [r4, #0] + 25bc: 4798 blx r3 + lv_style_t * style_trans = _lv_style_list_get_transition_style(list); + 25be: 4b13 ldr r3, [pc, #76] ; (260c ) + 25c0: 4798 blx r3 + lv_style_remove_prop(style_trans, tr->prop); + 25c2: 88a1 ldrh r1, [r4, #4] + 25c4: 4b12 ldr r3, [pc, #72] ; (2610 ) + 25c6: 4798 blx r3 + } + + _lv_ll_remove(&LV_GC_ROOT(_lv_obj_style_trans_ll), tr); + 25c8: 480d ldr r0, [pc, #52] ; (2600 ) + 25ca: 4b12 ldr r3, [pc, #72] ; (2614 ) + 25cc: 4621 mov r1, r4 + 25ce: 4798 blx r3 + lv_mem_free(tr); + 25d0: 4620 mov r0, r4 + 25d2: 4b11 ldr r3, [pc, #68] ; (2618 ) +} + 25d4: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} + lv_mem_free(tr); + 25d8: 4718 bx r3 + if(tr_i != tr && tr_i->obj == tr->obj && tr_i->part == tr->part && tr_i->prop == tr->prop) { + 25da: 42a0 cmp r0, r4 + 25dc: d00a beq.n 25f4 + 25de: 6802 ldr r2, [r0, #0] + 25e0: 6823 ldr r3, [r4, #0] + 25e2: 429a cmp r2, r3 + 25e4: d106 bne.n 25f4 + 25e6: 6843 ldr r3, [r0, #4] + 25e8: 6862 ldr r2, [r4, #4] + 25ea: 4053 eors r3, r2 + running = true; + 25ec: f033 437f bics.w r3, r3, #4278190080 ; 0xff000000 + 25f0: bf08 it eq + 25f2: 2501 moveq r5, #1 + _LV_LL_READ(LV_GC_ROOT(_lv_obj_style_trans_ll), tr_i) { + 25f4: 4601 mov r1, r0 + 25f6: 4630 mov r0, r6 + 25f8: 47b8 blx r7 + 25fa: e7da b.n 25b2 + 25fc: 0000e6a9 .word 0x0000e6a9 + 2600: 20008660 .word 0x20008660 + 2604: 0000e6b5 .word 0x0000e6b5 + 2608: 0000248d .word 0x0000248d + 260c: 00005cb9 .word 0x00005cb9 + 2610: 00005811 .word 0x00005811 + 2614: 0000e76d .word 0x0000e76d + 2618: 0000eae5 .word 0x0000eae5 + +0000261c : +{ + 261c: b573 push {r0, r1, r4, r5, r6, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 261e: 4b0c ldr r3, [pc, #48] ; (2650 ) +{ + 2620: 4604 mov r4, r0 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 2622: 4798 blx r3 + 2624: 4605 mov r5, r0 + 2626: b968 cbnz r0, 2644 + 2628: 4b0a ldr r3, [pc, #40] ; (2654 ) + 262a: 490b ldr r1, [pc, #44] ; (2658 ) + 262c: 9300 str r3, [sp, #0] + 262e: f640 2241 movw r2, #2625 ; 0xa41 + 2632: 2003 movs r0, #3 + 2634: 4e09 ldr r6, [pc, #36] ; (265c ) + 2636: 47b0 blx r6 + 2638: 4809 ldr r0, [pc, #36] ; (2660 ) + 263a: 490a ldr r1, [pc, #40] ; (2664 ) + 263c: 4622 mov r2, r4 + 263e: 462b mov r3, r5 + 2640: 4788 blx r1 + 2642: e7fe b.n 2642 + return obj->hidden == 0 ? false : true; + 2644: f894 0034 ldrb.w r0, [r4, #52] ; 0x34 +} + 2648: f3c0 1000 ubfx r0, r0, #4, #1 + 264c: b002 add sp, #8 + 264e: bd70 pop {r4, r5, r6, pc} + 2650: 000017e1 .word 0x000017e1 + 2654: 0001f3ff .word 0x0001f3ff + 2658: 0001ee5b .word 0x0001ee5b + 265c: 0000e8e9 .word 0x0000e8e9 + 2660: 0001eebf .word 0x0001eebf + 2664: 000017e9 .word 0x000017e9 + +00002668 : +{ + 2668: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 266c: 4b35 ldr r3, [pc, #212] ; (2744 ) +{ + 266e: b086 sub sp, #24 + 2670: 4604 mov r4, r0 + 2672: 4688 mov r8, r1 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 2674: 4798 blx r3 + 2676: 4605 mov r5, r0 + 2678: b968 cbnz r0, 2696 + 267a: 4b33 ldr r3, [pc, #204] ; (2748 ) + 267c: 4933 ldr r1, [pc, #204] ; (274c ) + 267e: 9300 str r3, [sp, #0] + 2680: f44f 72f0 mov.w r2, #480 ; 0x1e0 + 2684: 2003 movs r0, #3 + 2686: 4e32 ldr r6, [pc, #200] ; (2750 ) + 2688: 47b0 blx r6 + 268a: 4832 ldr r0, [pc, #200] ; (2754 ) + 268c: 4932 ldr r1, [pc, #200] ; (2758 ) + 268e: 4622 mov r2, r4 + 2690: 462b mov r3, r5 + 2692: 4788 blx r1 + 2694: e7fe b.n 2694 + if(lv_obj_get_hidden(obj)) return; + 2696: 4f31 ldr r7, [pc, #196] ; (275c ) + 2698: 4620 mov r0, r4 + 269a: 47b8 blx r7 + 269c: 2800 cmp r0, #0 + 269e: d141 bne.n 2724 + lv_obj_t * obj_scr = lv_obj_get_screen(obj); + 26a0: 4b2f ldr r3, [pc, #188] ; (2760 ) + 26a2: 4620 mov r0, r4 + 26a4: 4798 blx r3 + lv_disp_t * disp = lv_obj_get_disp(obj_scr); + 26a6: 4b2f ldr r3, [pc, #188] ; (2764 ) + lv_obj_t * obj_scr = lv_obj_get_screen(obj); + 26a8: 4605 mov r5, r0 + lv_disp_t * disp = lv_obj_get_disp(obj_scr); + 26aa: 4798 blx r3 + if(obj_scr == lv_disp_get_scr_act(disp) || obj_scr == lv_disp_get_layer_top(disp) || + 26ac: 4b2e ldr r3, [pc, #184] ; (2768 ) + lv_disp_t * disp = lv_obj_get_disp(obj_scr); + 26ae: 4606 mov r6, r0 + if(obj_scr == lv_disp_get_scr_act(disp) || obj_scr == lv_disp_get_layer_top(disp) || + 26b0: 4798 blx r3 + 26b2: 4285 cmp r5, r0 + 26b4: d12c bne.n 2710 + lv_coord_t ext_size = obj->ext_draw_pad; + 26b6: f9b4 5032 ldrsh.w r5, [r4, #50] ; 0x32 + lv_area_copy(&obj_coords, &obj->coords); + 26ba: 4b2c ldr r3, [pc, #176] ; (276c ) + 26bc: f104 0110 add.w r1, r4, #16 + 26c0: a802 add r0, sp, #8 + 26c2: 4798 blx r3 + obj_coords.x1 -= ext_size; + 26c4: f8bd 2008 ldrh.w r2, [sp, #8] + 26c8: b2ab uxth r3, r5 + 26ca: 1ad2 subs r2, r2, r3 + 26cc: f8ad 2008 strh.w r2, [sp, #8] + obj_coords.y1 -= ext_size; + 26d0: f8bd 200a ldrh.w r2, [sp, #10] + is_common = _lv_area_intersect(&area_trunc, area, &obj_coords); + 26d4: 4d26 ldr r5, [pc, #152] ; (2770 ) + obj_coords.y1 -= ext_size; + 26d6: 1ad2 subs r2, r2, r3 + 26d8: f8ad 200a strh.w r2, [sp, #10] + obj_coords.x2 += ext_size; + 26dc: f8bd 200c ldrh.w r2, [sp, #12] + 26e0: 441a add r2, r3 + 26e2: f8ad 200c strh.w r2, [sp, #12] + obj_coords.y2 += ext_size; + 26e6: f8bd 200e ldrh.w r2, [sp, #14] + is_common = _lv_area_intersect(&area_trunc, area, &obj_coords); + 26ea: 4641 mov r1, r8 + obj_coords.y2 += ext_size; + 26ec: 4413 add r3, r2 + is_common = _lv_area_intersect(&area_trunc, area, &obj_coords); + 26ee: a804 add r0, sp, #16 + 26f0: aa02 add r2, sp, #8 + obj_coords.y2 += ext_size; + 26f2: f8ad 300e strh.w r3, [sp, #14] + is_common = _lv_area_intersect(&area_trunc, area, &obj_coords); + 26f6: 47a8 blx r5 + if(is_common == false) return; /*The area is not on the object*/ + 26f8: b1a0 cbz r0, 2724 + lv_obj_t * par = lv_obj_get_parent(obj); + 26fa: f8df 8084 ldr.w r8, [pc, #132] ; 2780 + 26fe: 4620 mov r0, r4 + par = lv_obj_get_parent(par); + 2700: 47c0 blx r8 + 2702: 4604 mov r4, r0 + while(par != NULL) { + 2704: b988 cbnz r0, 272a + if(is_common) _lv_inv_area(disp, &area_trunc); + 2706: 4b1b ldr r3, [pc, #108] ; (2774 ) + 2708: a904 add r1, sp, #16 + 270a: 4630 mov r0, r6 + 270c: 4798 blx r3 + 270e: e009 b.n 2724 + if(obj_scr == lv_disp_get_scr_act(disp) || obj_scr == lv_disp_get_layer_top(disp) || + 2710: 4b19 ldr r3, [pc, #100] ; (2778 ) + 2712: 4630 mov r0, r6 + 2714: 4798 blx r3 + 2716: 4285 cmp r5, r0 + 2718: d0cd beq.n 26b6 + obj_scr == lv_disp_get_layer_sys(disp)) { + 271a: 4b18 ldr r3, [pc, #96] ; (277c ) + 271c: 4630 mov r0, r6 + 271e: 4798 blx r3 + if(obj_scr == lv_disp_get_scr_act(disp) || obj_scr == lv_disp_get_layer_top(disp) || + 2720: 4285 cmp r5, r0 + 2722: d0c8 beq.n 26b6 +} + 2724: b006 add sp, #24 + 2726: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + is_common = _lv_area_intersect(&area_trunc, &area_trunc, &par->coords); + 272a: a904 add r1, sp, #16 + 272c: f104 0210 add.w r2, r4, #16 + 2730: 4608 mov r0, r1 + 2732: 47a8 blx r5 + if(is_common == false) break; /*If no common parts with parent break;*/ + 2734: 2800 cmp r0, #0 + 2736: d0f5 beq.n 2724 + if(lv_obj_get_hidden(par)) return; /*If the parent is hidden then the child is hidden and won't be drawn*/ + 2738: 4620 mov r0, r4 + 273a: 47b8 blx r7 + 273c: 2800 cmp r0, #0 + 273e: d1f1 bne.n 2724 + par = lv_obj_get_parent(par); + 2740: 4620 mov r0, r4 + 2742: e7dd b.n 2700 + 2744: 000017e1 .word 0x000017e1 + 2748: 0001f411 .word 0x0001f411 + 274c: 0001ee5b .word 0x0001ee5b + 2750: 0000e8e9 .word 0x0000e8e9 + 2754: 0001eebf .word 0x0001eebf + 2758: 000017e9 .word 0x000017e9 + 275c: 0000261d .word 0x0000261d + 2760: 0000216d .word 0x0000216d + 2764: 000021c5 .word 0x000021c5 + 2768: 00001871 .word 0x00001871 + 276c: 00001d19 .word 0x00001d19 + 2770: 0000de8d .word 0x0000de8d + 2774: 00004f0d .word 0x00004f0d + 2778: 000018ad .word 0x000018ad + 277c: 000018e9 .word 0x000018e9 + 2780: 00002125 .word 0x00002125 + +00002784 : +{ + 2784: b57f push {r0, r1, r2, r3, r4, r5, r6, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 2786: 4b1a ldr r3, [pc, #104] ; (27f0 ) +{ + 2788: 4605 mov r5, r0 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 278a: 4798 blx r3 + 278c: 4604 mov r4, r0 + 278e: b968 cbnz r0, 27ac + 2790: 4b18 ldr r3, [pc, #96] ; (27f4 ) + 2792: 4919 ldr r1, [pc, #100] ; (27f8 ) + 2794: 9300 str r3, [sp, #0] + 2796: f240 220d movw r2, #525 ; 0x20d + 279a: 2003 movs r0, #3 + 279c: 4e17 ldr r6, [pc, #92] ; (27fc ) + 279e: 47b0 blx r6 + 27a0: 4817 ldr r0, [pc, #92] ; (2800 ) + 27a2: 4918 ldr r1, [pc, #96] ; (2804 ) + 27a4: 462a mov r2, r5 + 27a6: 4623 mov r3, r4 + 27a8: 4788 blx r1 + 27aa: e7fe b.n 27aa + lv_coord_t ext_size = obj->ext_draw_pad; + 27ac: f9b5 4032 ldrsh.w r4, [r5, #50] ; 0x32 + lv_area_copy(&obj_coords, &obj->coords); + 27b0: 4b15 ldr r3, [pc, #84] ; (2808 ) + 27b2: f105 0110 add.w r1, r5, #16 + 27b6: a802 add r0, sp, #8 + 27b8: 4798 blx r3 + obj_coords.x1 -= ext_size; + 27ba: f8bd 2008 ldrh.w r2, [sp, #8] + 27be: b2a3 uxth r3, r4 + 27c0: 1ad2 subs r2, r2, r3 + 27c2: f8ad 2008 strh.w r2, [sp, #8] + obj_coords.y1 -= ext_size; + 27c6: f8bd 200a ldrh.w r2, [sp, #10] + 27ca: 1ad2 subs r2, r2, r3 + 27cc: f8ad 200a strh.w r2, [sp, #10] + obj_coords.x2 += ext_size; + 27d0: f8bd 200c ldrh.w r2, [sp, #12] + 27d4: 441a add r2, r3 + 27d6: f8ad 200c strh.w r2, [sp, #12] + obj_coords.y2 += ext_size; + 27da: f8bd 200e ldrh.w r2, [sp, #14] + 27de: 4413 add r3, r2 + 27e0: f8ad 300e strh.w r3, [sp, #14] + lv_obj_invalidate_area(obj, &obj_coords); + 27e4: a902 add r1, sp, #8 + 27e6: 4b09 ldr r3, [pc, #36] ; (280c ) + 27e8: 4628 mov r0, r5 + 27ea: 4798 blx r3 +} + 27ec: b004 add sp, #16 + 27ee: bd70 pop {r4, r5, r6, pc} + 27f0: 000017e1 .word 0x000017e1 + 27f4: 0001f428 .word 0x0001f428 + 27f8: 0001ee5b .word 0x0001ee5b + 27fc: 0000e8e9 .word 0x0000e8e9 + 2800: 0001eebf .word 0x0001eebf + 2804: 000017e9 .word 0x000017e9 + 2808: 00001d19 .word 0x00001d19 + 280c: 00002669 .word 0x00002669 + +00002810 : +{ + 2810: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 2812: 4b19 ldr r3, [pc, #100] ; (2878 ) +{ + 2814: 4605 mov r5, r0 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 2816: 4798 blx r3 + 2818: 4604 mov r4, r0 + 281a: b968 cbnz r0, 2838 + 281c: 4b17 ldr r3, [pc, #92] ; (287c ) + 281e: 4918 ldr r1, [pc, #96] ; (2880 ) + 2820: 9300 str r3, [sp, #0] + 2822: f240 2262 movw r2, #610 ; 0x262 + 2826: 2003 movs r0, #3 + 2828: 4e16 ldr r6, [pc, #88] ; (2884 ) + 282a: 47b0 blx r6 + 282c: 4816 ldr r0, [pc, #88] ; (2888 ) + 282e: 4917 ldr r1, [pc, #92] ; (288c ) + 2830: 462a mov r2, r5 + 2832: 4623 mov r3, r4 + 2834: 4788 blx r1 + 2836: e7fe b.n 2836 + lv_obj_t * parent = lv_obj_get_parent(obj); + 2838: 4b15 ldr r3, [pc, #84] ; (2890 ) + 283a: 4628 mov r0, r5 + 283c: 4798 blx r3 + if(_lv_ll_get_head(&parent->child_ll) == obj) return; + 283e: 1d07 adds r7, r0, #4 + 2840: 4b14 ldr r3, [pc, #80] ; (2894 ) + lv_obj_t * parent = lv_obj_get_parent(obj); + 2842: 4604 mov r4, r0 + if(_lv_ll_get_head(&parent->child_ll) == obj) return; + 2844: 4638 mov r0, r7 + 2846: 4798 blx r3 + 2848: 4285 cmp r5, r0 + 284a: d013 beq.n 2874 + lv_obj_invalidate(parent); + 284c: 4e12 ldr r6, [pc, #72] ; (2898 ) + 284e: 4620 mov r0, r4 + 2850: 47b0 blx r6 + _lv_ll_chg_list(&parent->child_ll, &parent->child_ll, obj, true); + 2852: 462a mov r2, r5 + 2854: 4639 mov r1, r7 + 2856: 4638 mov r0, r7 + 2858: 2301 movs r3, #1 + 285a: 4f10 ldr r7, [pc, #64] ; (289c ) + 285c: 47b8 blx r7 + parent->signal_cb(parent, LV_SIGNAL_CHILD_CHG, obj); + 285e: 69e3 ldr r3, [r4, #28] + 2860: 462a mov r2, r5 + 2862: 2101 movs r1, #1 + 2864: 4620 mov r0, r4 + 2866: 4798 blx r3 + lv_obj_invalidate(parent); + 2868: 4620 mov r0, r4 + 286a: 4633 mov r3, r6 +} + 286c: b003 add sp, #12 + 286e: e8bd 40f0 ldmia.w sp!, {r4, r5, r6, r7, lr} + lv_obj_invalidate(parent); + 2872: 4718 bx r3 +} + 2874: b003 add sp, #12 + 2876: bdf0 pop {r4, r5, r6, r7, pc} + 2878: 000017e1 .word 0x000017e1 + 287c: 0001f43a .word 0x0001f43a + 2880: 0001ee5b .word 0x0001ee5b + 2884: 0000e8e9 .word 0x0000e8e9 + 2888: 0001eebf .word 0x0001eebf + 288c: 000017e9 .word 0x000017e9 + 2890: 00002125 .word 0x00002125 + 2894: 0000e6a9 .word 0x0000e6a9 + 2898: 00002785 .word 0x00002785 + 289c: 0000e7ed .word 0x0000e7ed + +000028a0 : +{ + 28a0: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 28a4: 4b2e ldr r3, [pc, #184] ; (2960 ) +{ + 28a6: b087 sub sp, #28 + 28a8: 4604 mov r4, r0 + 28aa: 4688 mov r8, r1 + 28ac: 4617 mov r7, r2 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 28ae: 4798 blx r3 + 28b0: 4605 mov r5, r0 + 28b2: b968 cbnz r0, 28d0 + 28b4: 4b2b ldr r3, [pc, #172] ; (2964 ) + 28b6: 492c ldr r1, [pc, #176] ; (2968 ) + 28b8: 9300 str r3, [sp, #0] + 28ba: f240 2296 movw r2, #662 ; 0x296 + 28be: 2003 movs r0, #3 + 28c0: 4e2a ldr r6, [pc, #168] ; (296c ) + 28c2: 47b0 blx r6 + 28c4: 482a ldr r0, [pc, #168] ; (2970 ) + 28c6: 492b ldr r1, [pc, #172] ; (2974 ) + 28c8: 4622 mov r2, r4 + 28ca: 462b mov r3, r5 + 28cc: 4788 blx r1 + 28ce: e7fe b.n 28ce + lv_obj_t * par = obj->parent; + 28d0: 6826 ldr r6, [r4, #0] + if(par == NULL) { + 28d2: b95e cbnz r6, 28ec + LV_LOG_WARN("lv_obj_set_pos: not changing position of screen object"); + 28d4: 4b28 ldr r3, [pc, #160] ; (2978 ) + 28d6: 9300 str r3, [sp, #0] + 28d8: 4923 ldr r1, [pc, #140] ; (2968 ) + 28da: 4b22 ldr r3, [pc, #136] ; (2964 ) + 28dc: 4c23 ldr r4, [pc, #140] ; (296c ) + 28de: f44f 7227 mov.w r2, #668 ; 0x29c + 28e2: 2002 movs r0, #2 + 28e4: 47a0 blx r4 +} + 28e6: b007 add sp, #28 + 28e8: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + diff.x = x - obj->coords.x1; + 28ec: 8a22 ldrh r2, [r4, #16] + 28ee: 8a33 ldrh r3, [r6, #16] + 28f0: 1a9b subs r3, r3, r2 + 28f2: eb03 0108 add.w r1, r3, r8 + diff.y = y - obj->coords.y1; + 28f6: 8a62 ldrh r2, [r4, #18] + 28f8: 8a73 ldrh r3, [r6, #18] + 28fa: 1a9b subs r3, r3, r2 + 28fc: 19da adds r2, r3, r7 + 28fe: b297 uxth r7, r2 + diff.x = x - obj->coords.x1; + 2900: fa1f f881 uxth.w r8, r1 + diff.y = y - obj->coords.y1; + 2904: b212 sxth r2, r2 + if(diff.x == 0 && diff.y == 0) return; + 2906: ea58 0307 orrs.w r3, r8, r7 + diff.x = x - obj->coords.x1; + 290a: b20d sxth r5, r1 + diff.y = y - obj->coords.y1; + 290c: 9203 str r2, [sp, #12] + if(diff.x == 0 && diff.y == 0) return; + 290e: d0ea beq.n 28e6 + lv_obj_invalidate(obj); + 2910: 4620 mov r0, r4 + 2912: f8df 9070 ldr.w r9, [pc, #112] ; 2984 + 2916: 47c8 blx r9 + lv_obj_get_coords(obj, &ori); + 2918: a904 add r1, sp, #16 + 291a: 4620 mov r0, r4 + 291c: 4b17 ldr r3, [pc, #92] ; (297c ) + 291e: 4798 blx r3 + obj->coords.x1 += diff.x; + 2920: 8a23 ldrh r3, [r4, #16] + refresh_children_position(obj, diff.x, diff.y); + 2922: 9a03 ldr r2, [sp, #12] + obj->coords.x1 += diff.x; + 2924: 4443 add r3, r8 + 2926: 8223 strh r3, [r4, #16] + obj->coords.y1 += diff.y; + 2928: 8a63 ldrh r3, [r4, #18] + 292a: 443b add r3, r7 + 292c: 8263 strh r3, [r4, #18] + obj->coords.x2 += diff.x; + 292e: 8aa3 ldrh r3, [r4, #20] + 2930: 4498 add r8, r3 + obj->coords.y2 += diff.y; + 2932: 8ae3 ldrh r3, [r4, #22] + obj->coords.x2 += diff.x; + 2934: f8a4 8014 strh.w r8, [r4, #20] + obj->coords.y2 += diff.y; + 2938: 441f add r7, r3 + refresh_children_position(obj, diff.x, diff.y); + 293a: 4629 mov r1, r5 + 293c: 4620 mov r0, r4 + 293e: 4b10 ldr r3, [pc, #64] ; (2980 ) + obj->coords.y2 += diff.y; + 2940: 82e7 strh r7, [r4, #22] + refresh_children_position(obj, diff.x, diff.y); + 2942: 4798 blx r3 + obj->signal_cb(obj, LV_SIGNAL_COORD_CHG, &ori); + 2944: 69e3 ldr r3, [r4, #28] + 2946: aa04 add r2, sp, #16 + 2948: 2102 movs r1, #2 + 294a: 4620 mov r0, r4 + 294c: 4798 blx r3 + par->signal_cb(par, LV_SIGNAL_CHILD_CHG, obj); + 294e: 69f3 ldr r3, [r6, #28] + 2950: 4622 mov r2, r4 + 2952: 2101 movs r1, #1 + 2954: 4630 mov r0, r6 + 2956: 4798 blx r3 + lv_obj_invalidate(obj); + 2958: 4620 mov r0, r4 + 295a: 47c8 blx r9 + 295c: e7c3 b.n 28e6 + 295e: bf00 nop + 2960: 000017e1 .word 0x000017e1 + 2964: 0001f468 .word 0x0001f468 + 2968: 0001ee5b .word 0x0001ee5b + 296c: 0000e8e9 .word 0x0000e8e9 + 2970: 0001eebf .word 0x0001eebf + 2974: 000017e9 .word 0x000017e9 + 2978: 0001ef4a .word 0x0001ef4a + 297c: 000022d5 .word 0x000022d5 + 2980: 00001cc1 .word 0x00001cc1 + 2984: 00002785 .word 0x00002785 + +00002988 : +{ + 2988: b573 push {r0, r1, r4, r5, r6, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 298a: 4b0f ldr r3, [pc, #60] ; (29c8 ) +{ + 298c: 4604 mov r4, r0 + 298e: 460e mov r6, r1 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 2990: 4798 blx r3 + 2992: 4605 mov r5, r0 + 2994: b968 cbnz r0, 29b2 + 2996: 4b0d ldr r3, [pc, #52] ; (29cc ) + 2998: 490d ldr r1, [pc, #52] ; (29d0 ) + 299a: 9300 str r3, [sp, #0] + 299c: f44f 7233 mov.w r2, #716 ; 0x2cc + 29a0: 2003 movs r0, #3 + 29a2: 4e0c ldr r6, [pc, #48] ; (29d4 ) + 29a4: 47b0 blx r6 + 29a6: 480c ldr r0, [pc, #48] ; (29d8 ) + 29a8: 490c ldr r1, [pc, #48] ; (29dc ) + 29aa: 4622 mov r2, r4 + 29ac: 462b mov r3, r5 + 29ae: 4788 blx r1 + 29b0: e7fe b.n 29b0 + lv_obj_set_pos(obj, x, lv_obj_get_y(obj)); + 29b2: 4b0b ldr r3, [pc, #44] ; (29e0 ) + 29b4: 4620 mov r0, r4 + 29b6: 4798 blx r3 + 29b8: 4b0a ldr r3, [pc, #40] ; (29e4 ) + 29ba: 4602 mov r2, r0 + 29bc: 4631 mov r1, r6 + 29be: 4620 mov r0, r4 +} + 29c0: b002 add sp, #8 + 29c2: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + lv_obj_set_pos(obj, x, lv_obj_get_y(obj)); + 29c6: 4718 bx r3 + 29c8: 000017e1 .word 0x000017e1 + 29cc: 0001f477 .word 0x0001f477 + 29d0: 0001ee5b .word 0x0001ee5b + 29d4: 0000e8e9 .word 0x0000e8e9 + 29d8: 0001eebf .word 0x0001eebf + 29dc: 000017e9 .word 0x000017e9 + 29e0: 0000238d .word 0x0000238d + 29e4: 000028a1 .word 0x000028a1 + +000029e8 : +{ + 29e8: b573 push {r0, r1, r4, r5, r6, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 29ea: 4b0f ldr r3, [pc, #60] ; (2a28 ) +{ + 29ec: 4604 mov r4, r0 + 29ee: 460e mov r6, r1 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 29f0: 4798 blx r3 + 29f2: 4605 mov r5, r0 + 29f4: b968 cbnz r0, 2a12 + 29f6: 4b0d ldr r3, [pc, #52] ; (2a2c ) + 29f8: 490d ldr r1, [pc, #52] ; (2a30 ) + 29fa: 9300 str r3, [sp, #0] + 29fc: f44f 7236 mov.w r2, #728 ; 0x2d8 + 2a00: 2003 movs r0, #3 + 2a02: 4e0c ldr r6, [pc, #48] ; (2a34 ) + 2a04: 47b0 blx r6 + 2a06: 480c ldr r0, [pc, #48] ; (2a38 ) + 2a08: 490c ldr r1, [pc, #48] ; (2a3c ) + 2a0a: 4622 mov r2, r4 + 2a0c: 462b mov r3, r5 + 2a0e: 4788 blx r1 + 2a10: e7fe b.n 2a10 + lv_obj_set_pos(obj, lv_obj_get_x(obj), y); + 2a12: 4b0b ldr r3, [pc, #44] ; (2a40 ) + 2a14: 4620 mov r0, r4 + 2a16: 4798 blx r3 + 2a18: 4b0a ldr r3, [pc, #40] ; (2a44 ) + 2a1a: 4601 mov r1, r0 + 2a1c: 4632 mov r2, r6 + 2a1e: 4620 mov r0, r4 +} + 2a20: b002 add sp, #8 + 2a22: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + lv_obj_set_pos(obj, lv_obj_get_x(obj), y); + 2a26: 4718 bx r3 + 2a28: 000017e1 .word 0x000017e1 + 2a2c: 0001f484 .word 0x0001f484 + 2a30: 0001ee5b .word 0x0001ee5b + 2a34: 0000e8e9 .word 0x0000e8e9 + 2a38: 0001eebf .word 0x0001eebf + 2a3c: 000017e9 .word 0x000017e9 + 2a40: 0000232d .word 0x0000232d + 2a44: 000028a1 .word 0x000028a1 + +00002a48 : +{ + 2a48: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 2a4c: f8df a0d8 ldr.w sl, [pc, #216] ; 2b28 +{ + 2a50: f9bd 8030 ldrsh.w r8, [sp, #48] ; 0x30 + 2a54: 4604 mov r4, r0 + 2a56: 460d mov r5, r1 + 2a58: 4617 mov r7, r2 + 2a5a: 461e mov r6, r3 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 2a5c: 47d0 blx sl + 2a5e: 4681 mov r9, r0 + 2a60: b968 cbnz r0, 2a7e + 2a62: 4b2a ldr r3, [pc, #168] ; (2b0c ) + 2a64: 492a ldr r1, [pc, #168] ; (2b10 ) + 2a66: 9300 str r3, [sp, #0] + 2a68: f240 326d movw r2, #877 ; 0x36d + 2a6c: 2003 movs r0, #3 + 2a6e: 4d29 ldr r5, [pc, #164] ; (2b14 ) + 2a70: 47a8 blx r5 + 2a72: 4829 ldr r0, [pc, #164] ; (2b18 ) + 2a74: 4929 ldr r1, [pc, #164] ; (2b1c ) + 2a76: 4622 mov r2, r4 + 2a78: 464b mov r3, r9 + 2a7a: 4788 blx r1 + 2a7c: e7fe b.n 2a7c + if(base == NULL) base = lv_obj_get_parent(obj); + 2a7e: b91d cbnz r5, 2a88 + 2a80: 4b27 ldr r3, [pc, #156] ; (2b20 ) + 2a82: 4620 mov r0, r4 + 2a84: 4798 blx r3 + 2a86: 4605 mov r5, r0 + LV_ASSERT_OBJ(base, LV_OBJX_NAME); + 2a88: 4628 mov r0, r5 + 2a8a: 47d0 blx sl + 2a8c: 4681 mov r9, r0 + 2a8e: b968 cbnz r0, 2aac + 2a90: 4b1e ldr r3, [pc, #120] ; (2b0c ) + 2a92: 491f ldr r1, [pc, #124] ; (2b10 ) + 2a94: 9300 str r3, [sp, #0] + 2a96: f240 3271 movw r2, #881 ; 0x371 + 2a9a: 2003 movs r0, #3 + 2a9c: 4c1d ldr r4, [pc, #116] ; (2b14 ) + 2a9e: 47a0 blx r4 + 2aa0: 481d ldr r0, [pc, #116] ; (2b18 ) + 2aa2: 491e ldr r1, [pc, #120] ; (2b1c ) + 2aa4: 462a mov r2, r5 + 2aa6: 464b mov r3, r9 + 2aa8: 4788 blx r1 + 2aaa: e7fe b.n 2aaa + _lv_area_align(&base->coords, &obj->coords, align, &new_pos); + 2aac: 463a mov r2, r7 + 2aae: f104 0110 add.w r1, r4, #16 + 2ab2: ab03 add r3, sp, #12 + 2ab4: f105 0010 add.w r0, r5, #16 + 2ab8: f8df 9070 ldr.w r9, [pc, #112] ; 2b2c + 2abc: 47c8 blx r9 + lv_obj_t * par = lv_obj_get_parent(obj); + 2abe: 4b18 ldr r3, [pc, #96] ; (2b20 ) + 2ac0: 4620 mov r0, r4 + 2ac2: 4798 blx r3 + new_pos.y += y_ofs; + 2ac4: f8bd 200e ldrh.w r2, [sp, #14] + new_pos.x += x_ofs; + 2ac8: f8bd 100c ldrh.w r1, [sp, #12] + lv_coord_t par_abs_y = par->coords.y1; + 2acc: f9b0 3012 ldrsh.w r3, [r0, #18] + new_pos.x -= par_abs_x; + 2ad0: 8a00 ldrh r0, [r0, #16] + new_pos.y += y_ofs; + 2ad2: 4442 add r2, r8 + new_pos.x += x_ofs; + 2ad4: 4431 add r1, r6 + new_pos.x -= par_abs_x; + 2ad6: 1a09 subs r1, r1, r0 + new_pos.y -= par_abs_y; + 2ad8: 1ad2 subs r2, r2, r3 + new_pos.x -= par_abs_x; + 2ada: b209 sxth r1, r1 + new_pos.y -= par_abs_y; + 2adc: b212 sxth r2, r2 + lv_obj_set_pos(obj, new_pos.x, new_pos.y); + 2ade: 4b11 ldr r3, [pc, #68] ; (2b24 ) + new_pos.x -= par_abs_x; + 2ae0: f8ad 100c strh.w r1, [sp, #12] + lv_obj_set_pos(obj, new_pos.x, new_pos.y); + 2ae4: 4620 mov r0, r4 + new_pos.y -= par_abs_y; + 2ae6: f8ad 200e strh.w r2, [sp, #14] + lv_obj_set_pos(obj, new_pos.x, new_pos.y); + 2aea: 4798 blx r3 + obj->realign.origo_align = 0; + 2aec: f894 3049 ldrb.w r3, [r4, #73] ; 0x49 + obj->realign.align = align; + 2af0: f884 7048 strb.w r7, [r4, #72] ; 0x48 + obj->realign.origo_align = 0; + 2af4: f36f 0341 bfc r3, #1, #1 + obj->realign.xofs = x_ofs; + 2af8: f8a4 6044 strh.w r6, [r4, #68] ; 0x44 + obj->realign.yofs = y_ofs; + 2afc: f8a4 8046 strh.w r8, [r4, #70] ; 0x46 + obj->realign.base = base; + 2b00: 6425 str r5, [r4, #64] ; 0x40 + obj->realign.origo_align = 0; + 2b02: f884 3049 strb.w r3, [r4, #73] ; 0x49 +} + 2b06: b004 add sp, #16 + 2b08: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 2b0c: 0001f491 .word 0x0001f491 + 2b10: 0001ee5b .word 0x0001ee5b + 2b14: 0000e8e9 .word 0x0000e8e9 + 2b18: 0001eebf .word 0x0001eebf + 2b1c: 000017e9 .word 0x000017e9 + 2b20: 00002125 .word 0x00002125 + 2b24: 000028a1 .word 0x000028a1 + 2b28: 000017e1 .word 0x000017e1 + 2b2c: 0000e131 .word 0x0000e131 + +00002b30 : +{ + 2b30: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 2b34: b087 sub sp, #28 + 2b36: e9cd 2303 strd r2, r3, [sp, #12] + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 2b3a: f8df b1a4 ldr.w fp, [pc, #420] ; 2ce0 +{ + 2b3e: f9bd 3040 ldrsh.w r3, [sp, #64] ; 0x40 + 2b42: 9305 str r3, [sp, #20] + 2b44: 4680 mov r8, r0 + 2b46: 460e mov r6, r1 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 2b48: 47d8 blx fp + 2b4a: 4604 mov r4, r0 + 2b4c: b968 cbnz r0, 2b6a + 2b4e: 4b5a ldr r3, [pc, #360] ; (2cb8 ) + 2b50: 495a ldr r1, [pc, #360] ; (2cbc ) + 2b52: 9300 str r3, [sp, #0] + 2b54: f240 3295 movw r2, #917 ; 0x395 + 2b58: 2003 movs r0, #3 + 2b5a: 4d59 ldr r5, [pc, #356] ; (2cc0 ) + 2b5c: 47a8 blx r5 + 2b5e: 4859 ldr r0, [pc, #356] ; (2cc4 ) + 2b60: 4959 ldr r1, [pc, #356] ; (2cc8 ) + 2b62: 4642 mov r2, r8 + 2b64: 4623 mov r3, r4 + 2b66: 4788 blx r1 + 2b68: e7fe b.n 2b68 + lv_coord_t new_x = lv_obj_get_x(obj); + 2b6a: 4b58 ldr r3, [pc, #352] ; (2ccc ) + lv_coord_t obj_h_half = lv_obj_get_height(obj) / 2; + 2b6c: f8df 9174 ldr.w r9, [pc, #372] ; 2ce4 + lv_coord_t new_x = lv_obj_get_x(obj); + 2b70: 4640 mov r0, r8 + 2b72: 4798 blx r3 + lv_coord_t new_y = lv_obj_get_y(obj); + 2b74: 4b56 ldr r3, [pc, #344] ; (2cd0 ) + lv_coord_t new_x = lv_obj_get_x(obj); + 2b76: 4604 mov r4, r0 + lv_coord_t new_y = lv_obj_get_y(obj); + 2b78: 4640 mov r0, r8 + 2b7a: 4798 blx r3 + lv_coord_t obj_w_half = lv_obj_get_width(obj) / 2; + 2b7c: 4a55 ldr r2, [pc, #340] ; (2cd4 ) + lv_coord_t new_y = lv_obj_get_y(obj); + 2b7e: 4682 mov sl, r0 + lv_coord_t obj_w_half = lv_obj_get_width(obj) / 2; + 2b80: 4640 mov r0, r8 + 2b82: 4790 blx r2 + 2b84: 4605 mov r5, r0 + lv_coord_t obj_h_half = lv_obj_get_height(obj) / 2; + 2b86: 4640 mov r0, r8 + 2b88: 47c8 blx r9 + 2b8a: 4607 mov r7, r0 + if(base == NULL) { + 2b8c: b91e cbnz r6, 2b96 + base = lv_obj_get_parent(obj); + 2b8e: 4952 ldr r1, [pc, #328] ; (2cd8 ) + 2b90: 4640 mov r0, r8 + 2b92: 4788 blx r1 + 2b94: 4606 mov r6, r0 + LV_ASSERT_OBJ(base, LV_OBJX_NAME); + 2b96: 4630 mov r0, r6 + 2b98: 47d8 blx fp + 2b9a: 4a4e ldr r2, [pc, #312] ; (2cd4 ) + 2b9c: 4683 mov fp, r0 + 2b9e: b968 cbnz r0, 2bbc + 2ba0: 4b45 ldr r3, [pc, #276] ; (2cb8 ) + 2ba2: 4946 ldr r1, [pc, #280] ; (2cbc ) + 2ba4: 9300 str r3, [sp, #0] + 2ba6: f240 32a1 movw r2, #929 ; 0x3a1 + 2baa: 2003 movs r0, #3 + 2bac: 4c44 ldr r4, [pc, #272] ; (2cc0 ) + 2bae: 47a0 blx r4 + 2bb0: 4844 ldr r0, [pc, #272] ; (2cc4 ) + 2bb2: 4945 ldr r1, [pc, #276] ; (2cc8 ) + 2bb4: 4632 mov r2, r6 + 2bb6: 465b mov r3, fp + 2bb8: 4788 blx r1 + 2bba: e7fe b.n 2bba + switch(align) { + 2bbc: 9b03 ldr r3, [sp, #12] + lv_coord_t obj_w_half = lv_obj_get_width(obj) / 2; + 2bbe: eb05 75d5 add.w r5, r5, r5, lsr #31 + lv_coord_t obj_h_half = lv_obj_get_height(obj) / 2; + 2bc2: eb07 77d7 add.w r7, r7, r7, lsr #31 + lv_coord_t obj_w_half = lv_obj_get_width(obj) / 2; + 2bc6: f345 054f sbfx r5, r5, #1, #16 + lv_coord_t obj_h_half = lv_obj_get_height(obj) / 2; + 2bca: f347 074f sbfx r7, r7, #1, #16 + switch(align) { + 2bce: 2b14 cmp r3, #20 + 2bd0: d824 bhi.n 2c1c + 2bd2: e8df f003 tbb [pc, r3] + 2bd6: 580b .short 0x580b + 2bd8: 4b5e6119 .word 0x4b5e6119 + 2bdc: 58665b6b .word 0x58665b6b + 2be0: 4b5e6119 .word 0x4b5e6119 + 2be4: 5e5b586b .word 0x5e5b586b + 2be8: 6661 .short 0x6661 + 2bea: 6b .byte 0x6b + 2beb: 00 .byte 0x00 + new_x = lv_obj_get_width(base) / 2 - obj_w_half; + 2bec: 4630 mov r0, r6 + 2bee: 4790 blx r2 + 2bf0: eb00 70d0 add.w r0, r0, r0, lsr #31 + 2bf4: ebc5 0460 rsb r4, r5, r0, asr #1 + 2bf8: b224 sxth r4, r4 + new_y = lv_obj_get_height(base) / 2 - obj_h_half; + 2bfa: 4630 mov r0, r6 + 2bfc: 47c8 blx r9 + 2bfe: eb00 70d0 add.w r0, r0, r0, lsr #31 + 2c02: ebc7 0360 rsb r3, r7, r0, asr #1 + 2c06: e007 b.n 2c18 + new_x = lv_obj_get_width(base) / 2 - obj_w_half; + 2c08: 4630 mov r0, r6 + 2c0a: 4790 blx r2 + 2c0c: eb00 70d0 add.w r0, r0, r0, lsr #31 + 2c10: ebc5 0460 rsb r4, r5, r0, asr #1 + 2c14: b224 sxth r4, r4 + new_y = -obj_h_half; + 2c16: 427b negs r3, r7 + new_y = lv_obj_get_height(base) / 2 - obj_h_half; + 2c18: fa0f fa83 sxth.w sl, r3 + lv_obj_t * par = lv_obj_get_parent(obj); + 2c1c: 4a2e ldr r2, [pc, #184] ; (2cd8 ) + 2c1e: 4640 mov r0, r8 + 2c20: 4790 blx r2 + new_x += x_ofs + base_abs_x; + 2c22: 9b04 ldr r3, [sp, #16] + 2c24: 8a31 ldrh r1, [r6, #16] + new_x -= par_abs_x; + 2c26: 8a02 ldrh r2, [r0, #16] + new_x += x_ofs + base_abs_x; + 2c28: 4419 add r1, r3 + 2c2a: 4421 add r1, r4 + new_y += y_ofs + base_abs_y; + 2c2c: 9b05 ldr r3, [sp, #20] + new_x -= par_abs_x; + 2c2e: 1a89 subs r1, r1, r2 + new_y += y_ofs + base_abs_y; + 2c30: 8a72 ldrh r2, [r6, #18] + 2c32: 441a add r2, r3 + new_y -= par_abs_y; + 2c34: 8a43 ldrh r3, [r0, #18] + new_y += y_ofs + base_abs_y; + 2c36: 4452 add r2, sl + new_y -= par_abs_y; + 2c38: 1ad2 subs r2, r2, r3 + lv_obj_set_pos(obj, new_x, new_y); + 2c3a: b212 sxth r2, r2 + 2c3c: 4b27 ldr r3, [pc, #156] ; (2cdc ) + 2c3e: b209 sxth r1, r1 + 2c40: 4640 mov r0, r8 + 2c42: 4798 blx r3 + obj->realign.align = align; + 2c44: 9b03 ldr r3, [sp, #12] + 2c46: f888 3048 strb.w r3, [r8, #72] ; 0x48 + obj->realign.xofs = x_ofs; + 2c4a: 9b04 ldr r3, [sp, #16] + 2c4c: f8a8 3044 strh.w r3, [r8, #68] ; 0x44 + obj->realign.yofs = y_ofs; + 2c50: 9b05 ldr r3, [sp, #20] + 2c52: f8a8 3046 strh.w r3, [r8, #70] ; 0x46 + obj->realign.origo_align = 1; + 2c56: f898 3049 ldrb.w r3, [r8, #73] ; 0x49 + obj->realign.base = base; + 2c5a: f8c8 6040 str.w r6, [r8, #64] ; 0x40 + obj->realign.origo_align = 1; + 2c5e: f043 0302 orr.w r3, r3, #2 + 2c62: f888 3049 strb.w r3, [r8, #73] ; 0x49 +} + 2c66: b007 add sp, #28 + 2c68: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + new_x = lv_obj_get_width(base) / 2 - obj_w_half; + 2c6c: 4630 mov r0, r6 + 2c6e: 4790 blx r2 + 2c70: eb00 70d0 add.w r0, r0, r0, lsr #31 + 2c74: ebc5 0460 rsb r4, r5, r0, asr #1 + 2c78: b224 sxth r4, r4 + new_y = lv_obj_get_height(base) - obj_h_half; + 2c7a: 4630 mov r0, r6 + 2c7c: 47c8 blx r9 + 2c7e: 1bc0 subs r0, r0, r7 + 2c80: fa0f fa80 sxth.w sl, r0 + break; + 2c84: e7ca b.n 2c1c + new_x = -obj_w_half; + 2c86: 426d negs r5, r5 + 2c88: b22c sxth r4, r5 + new_y = -obj_h_half; + 2c8a: e7c4 b.n 2c16 + new_x = -obj_w_half; + 2c8c: 426d negs r5, r5 + 2c8e: b22c sxth r4, r5 + new_y = lv_obj_get_height(base) / 2 - obj_h_half; + 2c90: e7b3 b.n 2bfa + new_x = -obj_w_half; + 2c92: 426d negs r5, r5 + 2c94: b22c sxth r4, r5 + new_y = lv_obj_get_height(base) - obj_h_half; + 2c96: e7f0 b.n 2c7a + new_x = lv_obj_get_width(base) - obj_w_half; + 2c98: 4630 mov r0, r6 + 2c9a: 4790 blx r2 + 2c9c: 1b40 subs r0, r0, r5 + 2c9e: b204 sxth r4, r0 + 2ca0: e7b9 b.n 2c16 + new_x = lv_obj_get_width(base) - obj_w_half; + 2ca2: 4630 mov r0, r6 + 2ca4: 4790 blx r2 + 2ca6: 1b40 subs r0, r0, r5 + 2ca8: b204 sxth r4, r0 + 2caa: e7a6 b.n 2bfa + new_x = lv_obj_get_width(base) - obj_w_half; + 2cac: 4630 mov r0, r6 + 2cae: 4790 blx r2 + 2cb0: 1b40 subs r0, r0, r5 + 2cb2: b204 sxth r4, r0 + 2cb4: e7e1 b.n 2c7a + 2cb6: bf00 nop + 2cb8: 0001f49e .word 0x0001f49e + 2cbc: 0001ee5b .word 0x0001ee5b + 2cc0: 0000e8e9 .word 0x0000e8e9 + 2cc4: 0001eebf .word 0x0001eebf + 2cc8: 000017e9 .word 0x000017e9 + 2ccc: 0000232d .word 0x0000232d + 2cd0: 0000238d .word 0x0000238d + 2cd4: 000023ed .word 0x000023ed + 2cd8: 00002125 .word 0x00002125 + 2cdc: 000028a1 .word 0x000028a1 + 2ce0: 000017e1 .word 0x000017e1 + 2ce4: 0000243d .word 0x0000243d + +00002ce8 : +{ + 2ce8: b573 push {r0, r1, r4, r5, r6, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 2cea: 4b12 ldr r3, [pc, #72] ; (2d34 ) +{ + 2cec: 4604 mov r4, r0 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 2cee: 4798 blx r3 + 2cf0: 4605 mov r5, r0 + 2cf2: b968 cbnz r0, 2d10 + 2cf4: 4b10 ldr r3, [pc, #64] ; (2d38 ) + 2cf6: 4911 ldr r1, [pc, #68] ; (2d3c ) + 2cf8: 9300 str r3, [sp, #0] + 2cfa: f240 422a movw r2, #1066 ; 0x42a + 2cfe: 2003 movs r0, #3 + 2d00: 4e0f ldr r6, [pc, #60] ; (2d40 ) + 2d02: 47b0 blx r6 + 2d04: 480f ldr r0, [pc, #60] ; (2d44 ) + 2d06: 4910 ldr r1, [pc, #64] ; (2d48 ) + 2d08: 4622 mov r2, r4 + 2d0a: 462b mov r3, r5 + 2d0c: 4788 blx r1 + 2d0e: e7fe b.n 2d0e + if(obj->realign.origo_align) + 2d10: f894 5049 ldrb.w r5, [r4, #73] ; 0x49 + lv_obj_align_origo(obj, obj->realign.base, obj->realign.align, obj->realign.xofs, obj->realign.yofs); + 2d14: f9b4 0046 ldrsh.w r0, [r4, #70] ; 0x46 + 2d18: 6c21 ldr r1, [r4, #64] ; 0x40 + 2d1a: f894 2048 ldrb.w r2, [r4, #72] ; 0x48 + 2d1e: f9b4 3044 ldrsh.w r3, [r4, #68] ; 0x44 + 2d22: 9000 str r0, [sp, #0] + 2d24: 4620 mov r0, r4 + if(obj->realign.origo_align) + 2d26: 07ac lsls r4, r5, #30 + lv_obj_align_origo(obj, obj->realign.base, obj->realign.align, obj->realign.xofs, obj->realign.yofs); + 2d28: bf4c ite mi + 2d2a: 4c08 ldrmi r4, [pc, #32] ; (2d4c ) + lv_obj_align(obj, obj->realign.base, obj->realign.align, obj->realign.xofs, obj->realign.yofs); + 2d2c: 4c08 ldrpl r4, [pc, #32] ; (2d50 ) + 2d2e: 47a0 blx r4 +} + 2d30: b002 add sp, #8 + 2d32: bd70 pop {r4, r5, r6, pc} + 2d34: 000017e1 .word 0x000017e1 + 2d38: 0001f4b1 .word 0x0001f4b1 + 2d3c: 0001ee5b .word 0x0001ee5b + 2d40: 0000e8e9 .word 0x0000e8e9 + 2d44: 0001eebf .word 0x0001eebf + 2d48: 000017e9 .word 0x000017e9 + 2d4c: 00002b31 .word 0x00002b31 + 2d50: 00002a49 .word 0x00002a49 + +00002d54 : +{ + 2d54: b5f8 push {r3, r4, r5, r6, r7, lr} + lv_obj_t * child = lv_obj_get_child(obj, NULL); + 2d56: 2100 movs r1, #0 + 2d58: 4e0b ldr r6, [pc, #44] ; (2d88 ) + lv_obj_invalidate(child); + 2d5a: 4f0c ldr r7, [pc, #48] ; (2d8c ) +{ + 2d5c: 4605 mov r5, r0 + lv_obj_t * child = lv_obj_get_child(obj, NULL); + 2d5e: 47b0 blx r6 + 2d60: 4604 mov r4, r0 + while(child != NULL) { + 2d62: b904 cbnz r4, 2d66 +} + 2d64: bdf8 pop {r3, r4, r5, r6, r7, pc} + lv_obj_invalidate(child); + 2d66: 4620 mov r0, r4 + 2d68: 47b8 blx r7 + child->signal_cb(child, LV_SIGNAL_STYLE_CHG, NULL); + 2d6a: 69e3 ldr r3, [r4, #28] + 2d6c: 2200 movs r2, #0 + 2d6e: 2104 movs r1, #4 + 2d70: 4620 mov r0, r4 + 2d72: 4798 blx r3 + lv_obj_invalidate(child); + 2d74: 4620 mov r0, r4 + 2d76: 47b8 blx r7 + refresh_children_style(child); /*Check children too*/ + 2d78: 4620 mov r0, r4 + 2d7a: f7ff ffeb bl 2d54 + child = lv_obj_get_child(obj, child); + 2d7e: 4621 mov r1, r4 + 2d80: 4628 mov r0, r5 + 2d82: 47b0 blx r6 + 2d84: 4604 mov r4, r0 + 2d86: e7ec b.n 2d62 + 2d88: 00002271 .word 0x00002271 + 2d8c: 00002785 .word 0x00002785 + +00002d90 : +{ + 2d90: b573 push {r0, r1, r4, r5, r6, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 2d92: 4b36 ldr r3, [pc, #216] ; (2e6c ) +{ + 2d94: 4605 mov r5, r0 + 2d96: 460c mov r4, r1 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 2d98: 4798 blx r3 + 2d9a: 4606 mov r6, r0 + 2d9c: b968 cbnz r0, 2dba + 2d9e: 4b34 ldr r3, [pc, #208] ; (2e70 ) + 2da0: 4934 ldr r1, [pc, #208] ; (2e74 ) + 2da2: 9300 str r3, [sp, #0] + 2da4: f240 521d movw r2, #1309 ; 0x51d + 2da8: 2003 movs r0, #3 + 2daa: 4c33 ldr r4, [pc, #204] ; (2e78 ) + 2dac: 47a0 blx r4 + 2dae: 4833 ldr r0, [pc, #204] ; (2e7c ) + 2db0: 4933 ldr r1, [pc, #204] ; (2e80 ) + 2db2: 462a mov r2, r5 + 2db4: 4633 mov r3, r6 + 2db6: 4788 blx r1 + 2db8: e7fe b.n 2db8 + switch(prop) { + 2dba: 2c90 cmp r4, #144 ; 0x90 + 2dbc: 4e31 ldr r6, [pc, #196] ; (2e84 ) + 2dbe: d838 bhi.n 2e32 + 2dc0: 2c72 cmp r4, #114 ; 0x72 + 2dc2: d819 bhi.n 2df8 + 2dc4: 2c53 cmp r4, #83 ; 0x53 + 2dc6: d82e bhi.n 2e26 + 2dc8: 2c3f cmp r4, #63 ; 0x3f + 2dca: d822 bhi.n 2e12 + 2dcc: 2c07 cmp r4, #7 + 2dce: d825 bhi.n 2e1c + 2dd0: 2c01 cmp r4, #1 + 2dd2: d918 bls.n 2e06 + lv_obj_invalidate(obj); + 2dd4: 4628 mov r0, r5 + 2dd6: 47b0 blx r6 + obj->signal_cb(obj, LV_SIGNAL_STYLE_CHG, NULL); + 2dd8: 69eb ldr r3, [r5, #28] + 2dda: 2200 movs r2, #0 + 2ddc: 2104 movs r1, #4 + 2dde: 4628 mov r0, r5 + 2de0: 4798 blx r3 + switch(prop) { + 2de2: 2c18 cmp r4, #24 + 2de4: d834 bhi.n 2e50 + 2de6: 2c14 cmp r4, #20 + 2de8: d934 bls.n 2e54 + if(obj->parent) obj->parent->signal_cb(obj->parent, LV_SIGNAL_CHILD_CHG, NULL); + 2dea: 6828 ldr r0, [r5, #0] + 2dec: b390 cbz r0, 2e54 + 2dee: 69c3 ldr r3, [r0, #28] + 2df0: 2200 movs r2, #0 + 2df2: 2101 movs r1, #1 + 2df4: 4798 blx r3 + 2df6: e02d b.n 2e54 + 2df8: f1a4 0273 sub.w r2, r4, #115 ; 0x73 + 2dfc: 4b22 ldr r3, [pc, #136] ; (2e88 ) + 2dfe: b292 uxth r2, r2 + 2e00: 40d3 lsrs r3, r2 + 2e02: 07da lsls r2, r3, #31 + 2e04: d4e6 bmi.n 2dd4 + lv_obj_invalidate(obj); + 2e06: 4628 mov r0, r5 + 2e08: 4633 mov r3, r6 +} + 2e0a: b002 add sp, #8 + 2e0c: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + if(prop == LV_STYLE_PROP_ALL || (prop & LV_STYLE_INHERIT_MASK)) refresh_children_style(obj); + 2e10: 4718 bx r3 + 2e12: f1a4 0240 sub.w r2, r4, #64 ; 0x40 + 2e16: 4b1d ldr r3, [pc, #116] ; (2e8c ) + 2e18: b292 uxth r2, r2 + 2e1a: e7f1 b.n 2e00 + switch(prop) { + 2e1c: f1a4 0310 sub.w r3, r4, #16 + 2e20: 2b08 cmp r3, #8 + 2e22: d8f0 bhi.n 2e06 + 2e24: e7d6 b.n 2dd4 + 2e26: 2c5c cmp r4, #92 ; 0x5c + 2e28: d0d4 beq.n 2dd4 + 2e2a: f1a4 0370 sub.w r3, r4, #112 ; 0x70 + 2e2e: 2b01 cmp r3, #1 + 2e30: e7f7 b.n 2e22 + 2e32: f248 0381 movw r3, #32897 ; 0x8081 + 2e36: 429c cmp r4, r3 + 2e38: d806 bhi.n 2e48 + 2e3a: f248 037f movw r3, #32895 ; 0x807f + 2e3e: 429c cmp r4, r3 + 2e40: d8c8 bhi.n 2dd4 + 2e42: 2cff cmp r4, #255 ; 0xff + 2e44: d1df bne.n 2e06 + 2e46: e7c5 b.n 2dd4 + 2e48: f248 038e movw r3, #32910 ; 0x808e + 2e4c: 429c cmp r4, r3 + 2e4e: e7f9 b.n 2e44 + switch(prop) { + 2e50: 2cff cmp r4, #255 ; 0xff + 2e52: d0ca beq.n 2dea + lv_obj_invalidate(obj); + 2e54: 4628 mov r0, r5 + 2e56: 47b0 blx r6 + if(prop == LV_STYLE_PROP_ALL || (prop & LV_STYLE_INHERIT_MASK)) refresh_children_style(obj); + 2e58: 2cff cmp r4, #255 ; 0xff + 2e5a: d001 beq.n 2e60 + 2e5c: 0423 lsls r3, r4, #16 + 2e5e: d502 bpl.n 2e66 + 2e60: 4b0b ldr r3, [pc, #44] ; (2e90 ) + 2e62: 4628 mov r0, r5 + 2e64: e7d1 b.n 2e0a +} + 2e66: b002 add sp, #8 + 2e68: bd70 pop {r4, r5, r6, pc} + 2e6a: bf00 nop + 2e6c: 000017e1 .word 0x000017e1 + 2e70: 0001f4c0 .word 0x0001f4c0 + 2e74: 0001ee5b .word 0x0001ee5b + 2e78: 0000e8e9 .word 0x0000e8e9 + 2e7c: 0001eebf .word 0x0001eebf + 2e80: 000017e9 .word 0x000017e9 + 2e84: 00002785 .word 0x00002785 + 2e88: 20001a07 .word 0x20001a07 + 2e8c: 000f1003 .word 0x000f1003 + 2e90: 00002d55 .word 0x00002d55 + +00002e94 : +{ + 2e94: b510 push {r4, lr} + lv_obj_clean_style_list(obj, part); + 2e96: 4b04 ldr r3, [pc, #16] ; (2ea8 ) +{ + 2e98: 4604 mov r4, r0 + lv_obj_clean_style_list(obj, part); + 2e9a: 4798 blx r3 + lv_obj_refresh_style(obj, LV_STYLE_PROP_ALL); + 2e9c: 4620 mov r0, r4 + 2e9e: 4b03 ldr r3, [pc, #12] ; (2eac ) +} + 2ea0: e8bd 4010 ldmia.w sp!, {r4, lr} + lv_obj_refresh_style(obj, LV_STYLE_PROP_ALL); + 2ea4: 21ff movs r1, #255 ; 0xff + 2ea6: 4718 bx r3 + 2ea8: 00002549 .word 0x00002549 + 2eac: 00002d91 .word 0x00002d91 + +00002eb0 : +{ + 2eb0: b5f8 push {r3, r4, r5, r6, r7, lr} + lv_style_list_t * dsc = lv_obj_get_style_list(obj, part_sub); + 2eb2: 4c1e ldr r4, [pc, #120] ; (2f2c ) +{ + 2eb4: 4606 mov r6, r0 + 2eb6: 460d mov r5, r1 + 2eb8: 2700 movs r7, #0 + lv_style_list_t * dsc = lv_obj_get_style_list(obj, part_sub); + 2eba: b2f9 uxtb r1, r7 + 2ebc: 4628 mov r0, r5 + 2ebe: 47a0 blx r4 + if(dsc == NULL) break; + 2ec0: 4602 mov r2, r0 + 2ec2: b1f8 cbz r0, 2f04 + for(ci = 0; ci < dsc->style_cnt; ci++) { + 2ec4: 7901 ldrb r1, [r0, #4] + 2ec6: f04f 0c00 mov.w ip, #0 + 2eca: fa5f f38c uxtb.w r3, ip + 2ece: 4299 cmp r1, r3 + 2ed0: d915 bls.n 2efe + */ +void _lv_style_list_reset(lv_style_list_t * style_list); + +static inline lv_style_t * lv_style_list_get_style(lv_style_list_t * list, uint8_t id) +{ + if(list->has_trans && list->skip_trans) id++; + 2ed2: 7950 ldrb r0, [r2, #5] + 2ed4: f000 0006 and.w r0, r0, #6 + 2ed8: 2806 cmp r0, #6 + 2eda: d123 bne.n 2f24 + 2edc: 3301 adds r3, #1 + 2ede: b2db uxtb r3, r3 + if(list->style_cnt == 0 || id >= list->style_cnt) return NULL; + 2ee0: 4299 cmp r1, r3 + 2ee2: d916 bls.n 2f12 + return list->style_list[id]; + 2ee4: 6810 ldr r0, [r2, #0] + 2ee6: f850 3023 ldr.w r3, [r0, r3, lsl #2] + if(class == style || style == NULL) { + 2eea: 429e cmp r6, r3 + 2eec: d003 beq.n 2ef6 + 2eee: f10c 0c01 add.w ip, ip, #1 + 2ef2: 2e00 cmp r6, #0 + 2ef4: d1e9 bne.n 2eca + lv_obj_refresh_style(obj, LV_STYLE_PROP_ALL); + 2ef6: 4b0e ldr r3, [pc, #56] ; (2f30 ) + 2ef8: 21ff movs r1, #255 ; 0xff + 2efa: 4628 mov r0, r5 + 2efc: 4798 blx r3 + for(part_sub = 0; part_sub != _LV_OBJ_PART_REAL_LAST; part_sub++) { + 2efe: 3701 adds r7, #1 + 2f00: 2f40 cmp r7, #64 ; 0x40 + 2f02: d1da bne.n 2eba + lv_obj_t * child = lv_obj_get_child(obj, NULL); + 2f04: 4f0b ldr r7, [pc, #44] ; (2f34 ) + 2f06: 2100 movs r1, #0 + 2f08: 4628 mov r0, r5 + child = lv_obj_get_child(obj, child); + 2f0a: 47b8 blx r7 + 2f0c: 4604 mov r4, r0 + while(child) { + 2f0e: b910 cbnz r0, 2f16 +} + 2f10: bdf8 pop {r3, r4, r5, r6, r7, pc} + if(list->style_cnt == 0 || id >= list->style_cnt) return NULL; + 2f12: 2300 movs r3, #0 + 2f14: e7e9 b.n 2eea + report_style_mod_core(style, child); + 2f16: 4621 mov r1, r4 + 2f18: 4630 mov r0, r6 + 2f1a: f7ff ffc9 bl 2eb0 + child = lv_obj_get_child(obj, child); + 2f1e: 4621 mov r1, r4 + 2f20: 4628 mov r0, r5 + 2f22: e7f2 b.n 2f0a + 2f24: 2900 cmp r1, #0 + 2f26: d1dd bne.n 2ee4 + 2f28: 460b mov r3, r1 + 2f2a: e7de b.n 2eea + 2f2c: 0000248d .word 0x0000248d + 2f30: 00002d91 .word 0x00002d91 + 2f34: 00002271 .word 0x00002271 + +00002f38 : +{ + 2f38: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} + lv_disp_t * d = lv_disp_get_next(NULL); + 2f3c: 4f0f ldr r7, [pc, #60] ; (2f7c ) + _LV_LL_READ(d->scr_ll, i) { + 2f3e: f8df 9040 ldr.w r9, [pc, #64] ; 2f80 + report_style_mod_core(style, i); + 2f42: f8df a040 ldr.w sl, [pc, #64] ; 2f84 +{ + 2f46: 4606 mov r6, r0 + lv_disp_t * d = lv_disp_get_next(NULL); + 2f48: 2000 movs r0, #0 + 2f4a: 47b8 blx r7 + 2f4c: 4604 mov r4, r0 + while(d) { + 2f4e: b90c cbnz r4, 2f54 +} + 2f50: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} + _LV_LL_READ(d->scr_ll, i) { + 2f54: f104 0830 add.w r8, r4, #48 ; 0x30 + 2f58: 4640 mov r0, r8 + 2f5a: 47c8 blx r9 + 2f5c: f8df b028 ldr.w fp, [pc, #40] ; 2f88 + 2f60: 4605 mov r5, r0 + 2f62: b91d cbnz r5, 2f6c + d = lv_disp_get_next(d); + 2f64: 4620 mov r0, r4 + 2f66: 47b8 blx r7 + 2f68: 4604 mov r4, r0 + 2f6a: e7f0 b.n 2f4e + report_style_mod_core(style, i); + 2f6c: 4629 mov r1, r5 + 2f6e: 4630 mov r0, r6 + 2f70: 47d0 blx sl + _LV_LL_READ(d->scr_ll, i) { + 2f72: 4629 mov r1, r5 + 2f74: 4640 mov r0, r8 + 2f76: 47d8 blx fp + 2f78: 4605 mov r5, r0 + 2f7a: e7f2 b.n 2f62 + 2f7c: 0000d9c5 .word 0x0000d9c5 + 2f80: 0000e6a9 .word 0x0000e6a9 + 2f84: 00002eb1 .word 0x00002eb1 + 2f88: 0000e6b5 .word 0x0000e6b5 + +00002f8c : +{ + 2f8c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + lv_style_list_t * list = lv_obj_get_style_list(tr->obj, tr->part); + 2f90: 4b3b ldr r3, [pc, #236] ; (3080 ) +{ + 2f92: 4604 mov r4, r0 + 2f94: 460d mov r5, r1 + lv_style_list_t * list = lv_obj_get_style_list(tr->obj, tr->part); + 2f96: 7981 ldrb r1, [r0, #6] + 2f98: 6800 ldr r0, [r0, #0] + 2f9a: 4798 blx r3 + lv_style_t * style = _lv_style_list_get_transition_style(list); + 2f9c: 4b39 ldr r3, [pc, #228] ; (3084 ) + 2f9e: 4798 blx r3 + if((tr->prop & 0xF) < LV_STYLE_ID_COLOR) { /*Value*/ + 2fa0: 88a1 ldrh r1, [r4, #4] + 2fa2: f001 030f and.w r3, r1, #15 + 2fa6: 2b08 cmp r3, #8 + 2fa8: d816 bhi.n 2fd8 + if(v == 0) x = tr->start_value._int; + 2faa: b94d cbnz r5, 2fc0 + 2fac: f9b4 2008 ldrsh.w r2, [r4, #8] + _lv_style_set_int(style, tr->prop, x); + 2fb0: 4b35 ldr r3, [pc, #212] ; (3088 ) + 2fb2: 4798 blx r3 + lv_obj_refresh_style(tr->obj, tr->prop); + 2fb4: 88a1 ldrh r1, [r4, #4] + 2fb6: 6820 ldr r0, [r4, #0] + 2fb8: 4b34 ldr r3, [pc, #208] ; (308c ) +} + 2fba: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} + lv_obj_refresh_style(tr->obj, tr->prop); + 2fbe: 4718 bx r3 + else if(v == 255) x = tr->end_value._int; + 2fc0: 2dff cmp r5, #255 ; 0xff + 2fc2: f9b4 200c ldrsh.w r2, [r4, #12] + 2fc6: d0f3 beq.n 2fb0 + else x = tr->start_value._int + ((int32_t)((int32_t)(tr->end_value._int - tr->start_value._int) * v) >> 8); + 2fc8: f9b4 3008 ldrsh.w r3, [r4, #8] + 2fcc: 1ad2 subs r2, r2, r3 + 2fce: 436a muls r2, r5 + 2fd0: eb03 2322 add.w r3, r3, r2, asr #8 + 2fd4: b21a sxth r2, r3 + 2fd6: e7eb b.n 2fb0 + else if((tr->prop & 0xF) < LV_STYLE_ID_OPA) { /*Color*/ + 2fd8: 2b0b cmp r3, #11 + 2fda: d838 bhi.n 304e + if(v <= 0) x = tr->start_value._color; + 2fdc: 2d00 cmp r5, #0 + 2fde: dc03 bgt.n 2fe8 + 2fe0: 8922 ldrh r2, [r4, #8] + _lv_style_set_color(style, tr->prop, x); + 2fe2: 4b2b ldr r3, [pc, #172] ; (3090 ) + 2fe4: 4798 blx r3 + 2fe6: e7e5 b.n 2fb4 + else if(v >= 255) x = tr->end_value._color; + 2fe8: 2dfe cmp r5, #254 ; 0xfe + 2fea: dd01 ble.n 2ff0 + 2fec: 89a2 ldrh r2, [r4, #12] + 2fee: e7f8 b.n 2fe2 +{ + lv_color_t ret; +#if LV_COLOR_DEPTH != 1 + /*LV_COLOR_DEPTH == 8, 16 or 32*/ + LV_COLOR_SET_R(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_R(c1) * mix + LV_COLOR_GET_R(c2) * (255 - mix))); + LV_COLOR_SET_G(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_G(c1) * mix + LV_COLOR_GET_G(c2) * (255 - mix))); + 2ff0: 8923 ldrh r3, [r4, #8] + 2ff2: 89a2 ldrh r2, [r4, #12] + LV_COLOR_SET_B(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_B(c1) * mix + LV_COLOR_GET_B(c2) * (255 - mix))); + 2ff4: f894 c008 ldrb.w ip, [r4, #8] + LV_COLOR_SET_R(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_R(c1) * mix + LV_COLOR_GET_R(c2) * (255 - mix))); + 2ff8: f1c5 07ff rsb r7, r5, #255 ; 0xff + LV_COLOR_SET_G(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_G(c1) * mix + LV_COLOR_GET_G(c2) * (255 - mix))); + 2ffc: f3c3 1345 ubfx r3, r3, #5, #6 + 3000: 437b muls r3, r7 + 3002: f3c2 1245 ubfx r2, r2, #5, #6 + 3006: fb15 3202 smlabb r2, r5, r2, r3 + LV_COLOR_SET_B(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_B(c1) * mix + LV_COLOR_GET_B(c2) * (255 - mix))); + 300a: 7b23 ldrb r3, [r4, #12] + 300c: f00c 0c1f and.w ip, ip, #31 + 3010: fb07 fc0c mul.w ip, r7, ip + 3014: f003 031f and.w r3, r3, #31 + LV_COLOR_SET_G(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_G(c1) * mix + LV_COLOR_GET_G(c2) * (255 - mix))); + 3018: f248 0681 movw r6, #32897 ; 0x8081 + LV_COLOR_SET_B(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_B(c1) * mix + LV_COLOR_GET_B(c2) * (255 - mix))); + 301c: fb15 c303 smlabb r3, r5, r3, ip + LV_COLOR_SET_G(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_G(c1) * mix + LV_COLOR_GET_G(c2) * (255 - mix))); + 3020: 4372 muls r2, r6 + LV_COLOR_SET_B(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_B(c1) * mix + LV_COLOR_GET_B(c2) * (255 - mix))); + 3022: 4373 muls r3, r6 + 3024: f3c3 53c4 ubfx r3, r3, #23, #5 + LV_COLOR_SET_R(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_R(c1) * mix + LV_COLOR_GET_R(c2) * (255 - mix))); + 3028: f894 c009 ldrb.w ip, [r4, #9] + 302c: f3c2 52c5 ubfx r2, r2, #23, #6 + 3030: ea43 1242 orr.w r2, r3, r2, lsl #5 + 3034: 7b63 ldrb r3, [r4, #13] + 3036: ea4f 0cdc mov.w ip, ip, lsr #3 + 303a: 08db lsrs r3, r3, #3 + 303c: fb07 f70c mul.w r7, r7, ip + 3040: fb15 7303 smlabb r3, r5, r3, r7 + 3044: 4373 muls r3, r6 + 3046: 0ddb lsrs r3, r3, #23 + 3048: ea42 22c3 orr.w r2, r2, r3, lsl #11 + 304c: e7c9 b.n 2fe2 + else if((tr->prop & 0xF) < LV_STYLE_ID_PTR) { /*Opa*/ + 304e: 2b0d cmp r3, #13 + 3050: d80f bhi.n 3072 + if(v <= 0) x = tr->start_value._opa; + 3052: 2d00 cmp r5, #0 + 3054: dc03 bgt.n 305e + 3056: 7a22 ldrb r2, [r4, #8] + _lv_style_set_opa(style, tr->prop, x); + 3058: 4b0e ldr r3, [pc, #56] ; (3094 ) + 305a: 4798 blx r3 + 305c: e7aa b.n 2fb4 + else if(v >= 255) x = tr->end_value._opa; + 305e: 2dfe cmp r5, #254 ; 0xfe + 3060: 7b22 ldrb r2, [r4, #12] + 3062: dcf9 bgt.n 3058 + else x = tr->start_value._opa + (((tr->end_value._opa - tr->start_value._opa) * v) >> 8); + 3064: 7a23 ldrb r3, [r4, #8] + 3066: 1ad2 subs r2, r2, r3 + 3068: 436a muls r2, r5 + 306a: eb03 2322 add.w r3, r3, r2, asr #8 + 306e: b2da uxtb r2, r3 + 3070: e7f2 b.n 3058 + if(v < 128) x = tr->start_value._ptr; + 3072: 2d7f cmp r5, #127 ; 0x7f + 3074: bfd4 ite le + 3076: 68a2 ldrle r2, [r4, #8] + else x = tr->end_value._ptr; + 3078: 68e2 ldrgt r2, [r4, #12] + _lv_style_set_ptr(style, tr->prop, x); + 307a: 4b07 ldr r3, [pc, #28] ; (3098 ) + 307c: 4798 blx r3 + 307e: e799 b.n 2fb4 + 3080: 0000248d .word 0x0000248d + 3084: 00005cb9 .word 0x00005cb9 + 3088: 00005879 .word 0x00005879 + 308c: 00002d91 .word 0x00002d91 + 3090: 00005949 .word 0x00005949 + 3094: 00005a19 .word 0x00005a19 + 3098: 00005aed .word 0x00005aed + +0000309c : +{ + 309c: b573 push {r0, r1, r4, r5, r6, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 309e: 4b0b ldr r3, [pc, #44] ; (30cc ) +{ + 30a0: 4605 mov r5, r0 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 30a2: 4798 blx r3 + 30a4: 4604 mov r4, r0 + 30a6: b968 cbnz r0, 30c4 + 30a8: 4b09 ldr r3, [pc, #36] ; (30d0 ) + 30aa: 490a ldr r1, [pc, #40] ; (30d4 ) + 30ac: 9300 str r3, [sp, #0] + 30ae: f640 22b1 movw r2, #2737 ; 0xab1 + 30b2: 2003 movs r0, #3 + 30b4: 4e08 ldr r6, [pc, #32] ; (30d8 ) + 30b6: 47b0 blx r6 + 30b8: 4808 ldr r0, [pc, #32] ; (30dc ) + 30ba: 4909 ldr r1, [pc, #36] ; (30e0 ) + 30bc: 462a mov r2, r5 + 30be: 4623 mov r3, r4 + 30c0: 4788 blx r1 + 30c2: e7fe b.n 30c2 +} + 30c4: 2000 movs r0, #0 + 30c6: b002 add sp, #8 + 30c8: bd70 pop {r4, r5, r6, pc} + 30ca: bf00 nop + 30cc: 000017e1 .word 0x000017e1 + 30d0: 0001f581 .word 0x0001f581 + 30d4: 0001ee5b .word 0x0001ee5b + 30d8: 0000e8e9 .word 0x0000e8e9 + 30dc: 0001eebf .word 0x0001eebf + 30e0: 000017e9 .word 0x000017e9 + +000030e4 : +{ + 30e4: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} + 30e8: 460d mov r5, r1 + if(parent == NULL) { + 30ea: 4606 mov r6, r0 + 30ec: 2800 cmp r0, #0 + 30ee: d177 bne.n 31e0 + lv_disp_t * disp = lv_disp_get_default(); + 30f0: 4b89 ldr r3, [pc, #548] ; (3318 ) + 30f2: 4798 blx r3 + if(!disp) { + 30f4: 4604 mov r4, r0 + 30f6: b940 cbnz r0, 310a + LV_LOG_WARN("lv_obj_create: not display created to so far. No place to assign the new screen"); + 30f8: 4b88 ldr r3, [pc, #544] ; (331c ) + 30fa: 9300 str r3, [sp, #0] + 30fc: 4988 ldr r1, [pc, #544] ; (3320 ) + 30fe: 4b89 ldr r3, [pc, #548] ; (3324 ) + 3100: 22cf movs r2, #207 ; 0xcf + 3102: 2002 movs r0, #2 + LV_LOG_INFO("Object create ready"); + 3104: 4d88 ldr r5, [pc, #544] ; (3328 ) + 3106: 47a8 blx r5 + return new_obj; + 3108: e016 b.n 3138 + new_obj = _lv_ll_ins_head(&disp->scr_ll); + 310a: 4b88 ldr r3, [pc, #544] ; (332c ) + 310c: 3030 adds r0, #48 ; 0x30 + 310e: 4798 blx r3 + LV_ASSERT_MEM(new_obj); + 3110: 4b87 ldr r3, [pc, #540] ; (3330 ) + new_obj = _lv_ll_ins_head(&disp->scr_ll); + 3112: 4604 mov r4, r0 + LV_ASSERT_MEM(new_obj); + 3114: 4798 blx r3 + 3116: 4607 mov r7, r0 + 3118: b960 cbnz r0, 3134 + 311a: 4b82 ldr r3, [pc, #520] ; (3324 ) + 311c: 4980 ldr r1, [pc, #512] ; (3320 ) + 311e: 9300 str r3, [sp, #0] + 3120: 22d4 movs r2, #212 ; 0xd4 + 3122: 2003 movs r0, #3 + 3124: 4d80 ldr r5, [pc, #512] ; (3328 ) + 3126: 47a8 blx r5 + 3128: 4882 ldr r0, [pc, #520] ; (3334 ) + 312a: 4983 ldr r1, [pc, #524] ; (3338 ) + 312c: 4622 mov r2, r4 + 312e: 463b mov r3, r7 + 3130: 4788 blx r1 + 3132: e7fe b.n 3132 + if(new_obj == NULL) return NULL; + 3134: b924 cbnz r4, 3140 + 3136: 2400 movs r4, #0 +} + 3138: 4620 mov r0, r4 + 313a: b004 add sp, #16 + 313c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + _lv_memset_00(new_obj, sizeof(lv_obj_t)); + 3140: 214c movs r1, #76 ; 0x4c + 3142: 4b7e ldr r3, [pc, #504] ; (333c ) + 3144: 4620 mov r0, r4 + 3146: 4798 blx r3 + new_obj->base_dir = LV_BIDI_DIR_LTR; + 3148: f894 3035 ldrb.w r3, [r4, #53] ; 0x35 + new_obj->event_cb = NULL; + 314c: 61a6 str r6, [r4, #24] + new_obj->base_dir = LV_BIDI_DIR_LTR; + 314e: f366 1305 bfi r3, r6, #4, #2 + 3152: f884 3035 strb.w r3, [r4, #53] ; 0x35 + new_obj->signal_cb = lv_obj_signal; + 3156: 4b7a ldr r3, [pc, #488] ; (3340 ) + 3158: 61e3 str r3, [r4, #28] + new_obj->design_cb = lv_obj_design; + 315a: 4b7a ldr r3, [pc, #488] ; (3344 ) + 315c: 6223 str r3, [r4, #32] + new_obj->coords.x1 = 0; + 315e: 6126 str r6, [r4, #16] + new_obj->coords.x2 = lv_disp_get_hor_res(NULL) - 1; + 3160: 4b79 ldr r3, [pc, #484] ; (3348 ) + 3162: 4630 mov r0, r6 + 3164: 4798 blx r3 + 3166: 3801 subs r0, #1 + 3168: 82a0 strh r0, [r4, #20] + new_obj->coords.y2 = lv_disp_get_ver_res(NULL) - 1; + 316a: 4b78 ldr r3, [pc, #480] ; (334c ) + 316c: 4630 mov r0, r6 + 316e: 4798 blx r3 + 3170: 3801 subs r0, #1 + 3172: 82e0 strh r0, [r4, #22] + _lv_ll_init(&(new_obj->child_ll), sizeof(lv_obj_t)); + 3174: 4b76 ldr r3, [pc, #472] ; (3350 ) + 3176: 214c movs r1, #76 ; 0x4c + 3178: 1d20 adds r0, r4, #4 + 317a: 4798 blx r3 + new_obj->realign.align = LV_ALIGN_CENTER; + 317c: f8b4 3048 ldrh.w r3, [r4, #72] ; 0x48 + 3180: f423 73ff bic.w r3, r3, #510 ; 0x1fe + 3184: f023 0301 bic.w r3, r3, #1 + 3188: f8a4 3048 strh.w r3, [r4, #72] ; 0x48 + new_obj->click = 1; + 318c: 8ea3 ldrh r3, [r4, #52] ; 0x34 + 318e: f423 637f bic.w r3, r3, #4080 ; 0xff0 + 3192: f023 030f bic.w r3, r3, #15 + 3196: f443 63e0 orr.w r3, r3, #1792 ; 0x700 + new_obj->realign.base = NULL; + 319a: 2200 movs r2, #0 + new_obj->click = 1; + 319c: f043 0301 orr.w r3, r3, #1 + lv_style_list_init(&new_obj->style_list); + 31a0: f104 0028 add.w r0, r4, #40 ; 0x28 + new_obj->click = 1; + 31a4: 86a3 strh r3, [r4, #52] ; 0x34 + new_obj->realign.xofs = 0; + 31a6: e9c4 2210 strd r2, r2, [r4, #64] ; 0x40 + lv_style_list_init(&new_obj->style_list); + 31aa: 4b6a ldr r3, [pc, #424] ; (3354 ) + new_obj->ext_click_pad_hor = 0; + 31ac: 6322 str r2, [r4, #48] ; 0x30 + new_obj->group_p = NULL; + 31ae: 63a2 str r2, [r4, #56] ; 0x38 + new_obj->protect = LV_PROTECT_NONE; + 31b0: 87a2 strh r2, [r4, #60] ; 0x3c + new_obj->ext_attr = NULL; + 31b2: 6262 str r2, [r4, #36] ; 0x24 + lv_style_list_init(&new_obj->style_list); + 31b4: 9003 str r0, [sp, #12] + 31b6: 4798 blx r3 + if(copy == NULL) { + 31b8: 9803 ldr r0, [sp, #12] + 31ba: 2d00 cmp r5, #0 + 31bc: f040 80d8 bne.w 3370 + if(parent != NULL) lv_theme_apply(new_obj, LV_THEME_OBJ); + 31c0: 4b65 ldr r3, [pc, #404] ; (3358 ) + 31c2: 2e00 cmp r6, #0 + 31c4: f000 809d beq.w 3302 + 31c8: 2102 movs r1, #2 + 31ca: 4620 mov r0, r4 + 31cc: 4798 blx r3 + parent->signal_cb(parent, LV_SIGNAL_CHILD_CHG, new_obj); + 31ce: 69f3 ldr r3, [r6, #28] + 31d0: 4622 mov r2, r4 + 31d2: 2101 movs r1, #1 + 31d4: 4630 mov r0, r6 + 31d6: 4798 blx r3 + lv_obj_invalidate(new_obj); + 31d8: 4b60 ldr r3, [pc, #384] ; (335c ) + 31da: 4620 mov r0, r4 + 31dc: 4798 blx r3 + 31de: e093 b.n 3308 + LV_ASSERT_OBJ(parent, LV_OBJX_NAME); + 31e0: 4f53 ldr r7, [pc, #332] ; (3330 ) + 31e2: 47b8 blx r7 + 31e4: 4604 mov r4, r0 + 31e6: b960 cbnz r0, 3202 + 31e8: 4b4e ldr r3, [pc, #312] ; (3324 ) + 31ea: 494d ldr r1, [pc, #308] ; (3320 ) + 31ec: 9300 str r3, [sp, #0] + 31ee: 22ed movs r2, #237 ; 0xed + 31f0: 2003 movs r0, #3 + 31f2: 4d4d ldr r5, [pc, #308] ; (3328 ) + 31f4: 47a8 blx r5 + 31f6: 485a ldr r0, [pc, #360] ; (3360 ) + 31f8: 494f ldr r1, [pc, #316] ; (3338 ) + 31fa: 4632 mov r2, r6 + 31fc: 4623 mov r3, r4 + 31fe: 4788 blx r1 + 3200: e7fe b.n 3200 + new_obj = _lv_ll_ins_head(&parent->child_ll); + 3202: 4b4a ldr r3, [pc, #296] ; (332c ) + 3204: 1d30 adds r0, r6, #4 + 3206: 4798 blx r3 + 3208: 4604 mov r4, r0 + LV_ASSERT_MEM(new_obj); + 320a: 47b8 blx r7 + 320c: 4607 mov r7, r0 + 320e: b960 cbnz r0, 322a + 3210: 4b44 ldr r3, [pc, #272] ; (3324 ) + 3212: 4943 ldr r1, [pc, #268] ; (3320 ) + 3214: 9300 str r3, [sp, #0] + 3216: 22f0 movs r2, #240 ; 0xf0 + 3218: 2003 movs r0, #3 + 321a: 4d43 ldr r5, [pc, #268] ; (3328 ) + 321c: 47a8 blx r5 + 321e: 4845 ldr r0, [pc, #276] ; (3334 ) + 3220: 4945 ldr r1, [pc, #276] ; (3338 ) + 3222: 4622 mov r2, r4 + 3224: 463b mov r3, r7 + 3226: 4788 blx r1 + 3228: e7fe b.n 3228 + if(new_obj == NULL) return NULL; + 322a: 2c00 cmp r4, #0 + 322c: d083 beq.n 3136 + _lv_memset_00(new_obj, sizeof(lv_obj_t)); + 322e: 4b43 ldr r3, [pc, #268] ; (333c ) + new_obj->coords.y2 = parent->coords.y1 + LV_OBJ_DEF_HEIGHT; + 3230: f8df 9138 ldr.w r9, [pc, #312] ; 336c + _lv_memset_00(new_obj, sizeof(lv_obj_t)); + 3234: 214c movs r1, #76 ; 0x4c + 3236: 4620 mov r0, r4 + 3238: 4798 blx r3 + new_obj->base_dir = LV_BIDI_DIR_LTR; + 323a: f894 3035 ldrb.w r3, [r4, #53] ; 0x35 + new_obj->parent = parent; + 323e: 6026 str r6, [r4, #0] + new_obj->base_dir = LV_BIDI_DIR_LTR; + 3240: f36f 1305 bfc r3, #4, #2 + 3244: f884 3035 strb.w r3, [r4, #53] ; 0x35 + new_obj->signal_cb = lv_obj_signal; + 3248: 4b3d ldr r3, [pc, #244] ; (3340 ) + 324a: 61e3 str r3, [r4, #28] + new_obj->design_cb = lv_obj_design; + 324c: 4b3d ldr r3, [pc, #244] ; (3344 ) + 324e: 6223 str r3, [r4, #32] + new_obj->event_cb = NULL; + 3250: f04f 0800 mov.w r8, #0 + new_obj->coords.y1 = parent->coords.y1; + 3254: f9b6 3012 ldrsh.w r3, [r6, #18] + 3258: 8263 strh r3, [r4, #18] + new_obj->event_cb = NULL; + 325a: f8c4 8018 str.w r8, [r4, #24] + new_obj->coords.y2 = parent->coords.y1 + LV_OBJ_DEF_HEIGHT; + 325e: 4640 mov r0, r8 + 3260: 8a77 ldrh r7, [r6, #18] + 3262: 47c8 blx r9 + 3264: f04f 0a32 mov.w sl, #50 ; 0x32 + 3268: fb00 f00a mul.w r0, r0, sl + 326c: 28ef cmp r0, #239 ; 0xef + 326e: dd2c ble.n 32ca + 3270: 4640 mov r0, r8 + 3272: 47c8 blx r9 + 3274: 2350 movs r3, #80 ; 0x50 + 3276: fb00 300a mla r0, r0, sl, r3 + 327a: 23a0 movs r3, #160 ; 0xa0 + 327c: fb90 f0f3 sdiv r0, r0, r3 + 3280: b280 uxth r0, r0 + 3282: 4407 add r7, r0 + 3284: 82e7 strh r7, [r4, #22] + if(lv_obj_get_base_dir(new_obj) == LV_BIDI_DIR_RTL) { + 3286: 4b37 ldr r3, [pc, #220] ; (3364 ) + 3288: 4620 mov r0, r4 + 328a: 4798 blx r3 + 328c: 2801 cmp r0, #1 + 328e: 4607 mov r7, r0 + 3290: d11d bne.n 32ce + new_obj->coords.x2 = parent->coords.x2; + 3292: f9b6 8014 ldrsh.w r8, [r6, #20] + 3296: f8a4 8014 strh.w r8, [r4, #20] + new_obj->coords.x1 = parent->coords.x2 - LV_OBJ_DEF_WIDTH; + 329a: 2000 movs r0, #0 + 329c: 47c8 blx r9 + 329e: f04f 0a64 mov.w sl, #100 ; 0x64 + 32a2: fb00 f00a mul.w r0, r0, sl + 32a6: 28ef cmp r0, #239 ; 0xef + 32a8: fa1f f888 uxth.w r8, r8 + 32ac: dd08 ble.n 32c0 + 32ae: 2000 movs r0, #0 + 32b0: 47c8 blx r9 + 32b2: 2750 movs r7, #80 ; 0x50 + 32b4: fb00 770a mla r7, r0, sl, r7 + 32b8: 23a0 movs r3, #160 ; 0xa0 + 32ba: fb97 f7f3 sdiv r7, r7, r3 + 32be: b2bf uxth r7, r7 + 32c0: eba8 0807 sub.w r8, r8, r7 + 32c4: f8a4 8010 strh.w r8, [r4, #16] + 32c8: e754 b.n 3174 + new_obj->coords.y2 = parent->coords.y1 + LV_OBJ_DEF_HEIGHT; + 32ca: 2001 movs r0, #1 + 32cc: e7d9 b.n 3282 + new_obj->coords.x1 = parent->coords.x1; + 32ce: f9b6 7010 ldrsh.w r7, [r6, #16] + 32d2: 8227 strh r7, [r4, #16] + new_obj->coords.x2 = parent->coords.x1 + LV_OBJ_DEF_WIDTH; + 32d4: 2000 movs r0, #0 + 32d6: 47c8 blx r9 + 32d8: f04f 0864 mov.w r8, #100 ; 0x64 + 32dc: fb00 f008 mul.w r0, r0, r8 + 32e0: 28ef cmp r0, #239 ; 0xef + 32e2: b2bf uxth r7, r7 + 32e4: dd0b ble.n 32fe + 32e6: 2000 movs r0, #0 + 32e8: 47c8 blx r9 + 32ea: 2350 movs r3, #80 ; 0x50 + 32ec: fb00 3008 mla r0, r0, r8, r3 + 32f0: 23a0 movs r3, #160 ; 0xa0 + 32f2: fb90 f0f3 sdiv r0, r0, r3 + 32f6: b280 uxth r0, r0 + 32f8: 4407 add r7, r0 + 32fa: 82a7 strh r7, [r4, #20] + 32fc: e73a b.n 3174 + 32fe: 2001 movs r0, #1 + 3300: e7fa b.n 32f8 + else lv_theme_apply(new_obj, LV_THEME_SCR); + 3302: 2101 movs r1, #1 + 3304: 4620 mov r0, r4 + 3306: 4798 blx r3 + LV_LOG_INFO("Object create ready"); + 3308: 4b17 ldr r3, [pc, #92] ; (3368 ) + 330a: 9300 str r3, [sp, #0] + 330c: 4904 ldr r1, [pc, #16] ; (3320 ) + 330e: 4b05 ldr r3, [pc, #20] ; (3324 ) + 3310: f240 1287 movw r2, #391 ; 0x187 + 3314: 2001 movs r0, #1 + 3316: e6f5 b.n 3104 + 3318: 0000d8fd .word 0x0000d8fd + 331c: 0001efb0 .word 0x0001efb0 + 3320: 0001ee5b .word 0x0001ee5b + 3324: 0001f595 .word 0x0001f595 + 3328: 0000e8e9 .word 0x0000e8e9 + 332c: 0000e619 .word 0x0000e619 + 3330: 000017e1 .word 0x000017e1 + 3334: 0001edbe .word 0x0001edbe + 3338: 000017e9 .word 0x000017e9 + 333c: 0000f019 .word 0x0000f019 + 3340: 00004b2d .word 0x00004b2d + 3344: 0000459d .word 0x0000459d + 3348: 0000d909 .word 0x0000d909 + 334c: 0000d92d .word 0x0000d92d + 3350: 0000e605 .word 0x0000e605 + 3354: 0000553d .word 0x0000553d + 3358: 000102e5 .word 0x000102e5 + 335c: 00002785 .word 0x00002785 + 3360: 0001eebf .word 0x0001eebf + 3364: 0000309d .word 0x0000309d + 3368: 0001f000 .word 0x0001f000 + 336c: 0000d951 .word 0x0000d951 + lv_style_list_copy(&new_obj->style_list, ©->style_list); + 3370: 4b54 ldr r3, [pc, #336] ; (34c4 ) + 3372: f105 0128 add.w r1, r5, #40 ; 0x28 + 3376: 4798 blx r3 + lv_area_copy(&new_obj->coords, ©->coords); + 3378: 4b53 ldr r3, [pc, #332] ; (34c8 ) + 337a: f104 0010 add.w r0, r4, #16 + 337e: f105 0110 add.w r1, r5, #16 + 3382: 4798 blx r3 + new_obj->ext_draw_pad = copy->ext_draw_pad; + 3384: f9b5 3032 ldrsh.w r3, [r5, #50] ; 0x32 + 3388: 8663 strh r3, [r4, #50] ; 0x32 + new_obj->ext_click_pad_hor = copy->ext_click_pad_hor; + 338a: f895 3030 ldrb.w r3, [r5, #48] ; 0x30 + 338e: f884 3030 strb.w r3, [r4, #48] ; 0x30 + new_obj->ext_click_pad_ver = copy->ext_click_pad_ver; + 3392: f895 3031 ldrb.w r3, [r5, #49] ; 0x31 + 3396: f884 3031 strb.w r3, [r4, #49] ; 0x31 + new_obj->realign.align = copy->realign.align; + 339a: f895 3048 ldrb.w r3, [r5, #72] ; 0x48 + 339e: f884 3048 strb.w r3, [r4, #72] ; 0x48 + new_obj->realign.xofs = copy->realign.xofs; + 33a2: f9b5 3044 ldrsh.w r3, [r5, #68] ; 0x44 + 33a6: f8a4 3044 strh.w r3, [r4, #68] ; 0x44 + new_obj->realign.yofs = copy->realign.yofs; + 33aa: f9b5 3046 ldrsh.w r3, [r5, #70] ; 0x46 + 33ae: f8a4 3046 strh.w r3, [r4, #70] ; 0x46 + new_obj->realign.base = copy->realign.base; + 33b2: 6c2b ldr r3, [r5, #64] ; 0x40 + new_obj->realign.auto_realign = copy->realign.auto_realign; + 33b4: f895 2049 ldrb.w r2, [r5, #73] ; 0x49 + new_obj->realign.base = copy->realign.base; + 33b8: 6423 str r3, [r4, #64] ; 0x40 + new_obj->realign.auto_realign = copy->realign.auto_realign; + 33ba: f894 3049 ldrb.w r3, [r4, #73] ; 0x49 + 33be: f362 0300 bfi r3, r2, #0, #1 + 33c2: f884 3049 strb.w r3, [r4, #73] ; 0x49 + new_obj->event_cb = copy->event_cb; + 33c6: 69ab ldr r3, [r5, #24] + 33c8: 61a3 str r3, [r4, #24] + new_obj->adv_hittest = copy->adv_hittest; + 33ca: f895 3034 ldrb.w r3, [r5, #52] ; 0x34 + 33ce: f894 2034 ldrb.w r2, [r4, #52] ; 0x34 + 33d2: 09db lsrs r3, r3, #7 + 33d4: f363 12c7 bfi r2, r3, #7, #1 + 33d8: f884 2034 strb.w r2, [r4, #52] ; 0x34 + new_obj->click = copy->click; + 33dc: f895 2034 ldrb.w r2, [r5, #52] ; 0x34 + 33e0: f894 3034 ldrb.w r3, [r4, #52] ; 0x34 + 33e4: f362 0300 bfi r3, r2, #0, #1 + 33e8: f884 3034 strb.w r3, [r4, #52] ; 0x34 + new_obj->drag = copy->drag; + 33ec: f895 3034 ldrb.w r3, [r5, #52] ; 0x34 + 33f0: f894 2034 ldrb.w r2, [r4, #52] ; 0x34 + 33f4: f3c3 0340 ubfx r3, r3, #1, #1 + 33f8: f363 0241 bfi r2, r3, #1, #1 + 33fc: f884 2034 strb.w r2, [r4, #52] ; 0x34 + new_obj->drag_dir = copy->drag_dir; + 3400: f895 3035 ldrb.w r3, [r5, #53] ; 0x35 + 3404: f894 2035 ldrb.w r2, [r4, #53] ; 0x35 + 3408: f3c3 0342 ubfx r3, r3, #1, #3 + 340c: f363 0243 bfi r2, r3, #1, #3 + 3410: f884 2035 strb.w r2, [r4, #53] ; 0x35 + new_obj->drag_throw = copy->drag_throw; + 3414: f895 3034 ldrb.w r3, [r5, #52] ; 0x34 + 3418: f894 2034 ldrb.w r2, [r4, #52] ; 0x34 + 341c: f3c3 0380 ubfx r3, r3, #2, #1 + 3420: f363 0282 bfi r2, r3, #2, #1 + 3424: f884 2034 strb.w r2, [r4, #52] ; 0x34 + new_obj->drag_parent = copy->drag_parent; + 3428: f895 3034 ldrb.w r3, [r5, #52] ; 0x34 + 342c: b2d2 uxtb r2, r2 + 342e: f3c3 03c0 ubfx r3, r3, #3, #1 + 3432: f363 02c3 bfi r2, r3, #3, #1 + 3436: f884 2034 strb.w r2, [r4, #52] ; 0x34 + new_obj->hidden = copy->hidden; + 343a: f895 3034 ldrb.w r3, [r5, #52] ; 0x34 + 343e: b2d2 uxtb r2, r2 + 3440: f3c3 1300 ubfx r3, r3, #4, #1 + 3444: f363 1204 bfi r2, r3, #4, #1 + 3448: f884 2034 strb.w r2, [r4, #52] ; 0x34 + new_obj->top = copy->top; + 344c: f895 3034 ldrb.w r3, [r5, #52] ; 0x34 + 3450: b2d2 uxtb r2, r2 + 3452: f3c3 1340 ubfx r3, r3, #5, #1 + 3456: f363 1245 bfi r2, r3, #5, #1 + 345a: f884 2034 strb.w r2, [r4, #52] ; 0x34 + new_obj->parent_event = copy->parent_event; + 345e: f895 3034 ldrb.w r3, [r5, #52] ; 0x34 + 3462: b2d2 uxtb r2, r2 + 3464: f3c3 1380 ubfx r3, r3, #6, #1 + 3468: f363 1286 bfi r2, r3, #6, #1 + 346c: f884 2034 strb.w r2, [r4, #52] ; 0x34 + new_obj->protect = copy->protect; + 3470: f895 303c ldrb.w r3, [r5, #60] ; 0x3c + 3474: f884 303c strb.w r3, [r4, #60] ; 0x3c + new_obj->gesture_parent = copy->gesture_parent; + 3478: f895 2035 ldrb.w r2, [r5, #53] ; 0x35 + 347c: f894 3035 ldrb.w r3, [r4, #53] ; 0x35 + 3480: f362 0300 bfi r3, r2, #0, #1 + 3484: f884 3035 strb.w r3, [r4, #53] ; 0x35 + if(copy->group_p != NULL) { + 3488: 6ba8 ldr r0, [r5, #56] ; 0x38 + 348a: b110 cbz r0, 3492 + lv_group_add_obj(copy->group_p, new_obj); + 348c: 4b0f ldr r3, [pc, #60] ; (34cc ) + 348e: 4621 mov r1, r4 + 3490: 4798 blx r3 + if(lv_obj_get_parent(copy) != NULL && parent != NULL) { + 3492: 4b0f ldr r3, [pc, #60] ; (34d0 ) + 3494: 4628 mov r0, r5 + 3496: 4798 blx r3 + 3498: b178 cbz r0, 34ba + 349a: 2e00 cmp r6, #0 + 349c: f43f af34 beq.w 3308 + lv_obj_set_pos(new_obj, lv_obj_get_x(copy), lv_obj_get_y(copy)); + 34a0: 4b0c ldr r3, [pc, #48] ; (34d4 ) + 34a2: 4628 mov r0, r5 + 34a4: 4798 blx r3 + 34a6: 4b0c ldr r3, [pc, #48] ; (34d8 ) + 34a8: 9003 str r0, [sp, #12] + 34aa: 4628 mov r0, r5 + 34ac: 4798 blx r3 + 34ae: 9903 ldr r1, [sp, #12] + 34b0: 4b0a ldr r3, [pc, #40] ; (34dc ) + 34b2: 4602 mov r2, r0 + 34b4: 4620 mov r0, r4 + 34b6: 4798 blx r3 + if(parent != NULL) { + 34b8: e689 b.n 31ce + 34ba: 2e00 cmp r6, #0 + 34bc: f47f ae87 bne.w 31ce + 34c0: e722 b.n 3308 + 34c2: bf00 nop + 34c4: 00005d2d .word 0x00005d2d + 34c8: 00001d19 .word 0x00001d19 + 34cc: 00001a9d .word 0x00001a9d + 34d0: 00002125 .word 0x00002125 + 34d4: 0000232d .word 0x0000232d + 34d8: 0000238d .word 0x0000238d + 34dc: 000028a1 .word 0x000028a1 + +000034e0 : +{ + 34e0: e92d 41ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 34e4: 4b33 ldr r3, [pc, #204] ; (35b4 ) +{ + 34e6: 4604 mov r4, r0 + 34e8: 460d mov r5, r1 + 34ea: 4617 mov r7, r2 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 34ec: 4798 blx r3 + 34ee: 4606 mov r6, r0 + 34f0: b968 cbnz r0, 350e + 34f2: 4b31 ldr r3, [pc, #196] ; (35b8 ) + 34f4: 4931 ldr r1, [pc, #196] ; (35bc ) + 34f6: 9300 str r3, [sp, #0] + 34f8: f240 22e5 movw r2, #741 ; 0x2e5 + 34fc: 2003 movs r0, #3 + 34fe: 4d30 ldr r5, [pc, #192] ; (35c0 ) + 3500: 47a8 blx r5 + 3502: 4830 ldr r0, [pc, #192] ; (35c4 ) + 3504: 4930 ldr r1, [pc, #192] ; (35c8 ) + 3506: 4622 mov r2, r4 + 3508: 4633 mov r3, r6 + 350a: 4788 blx r1 + 350c: e7fe b.n 350c + if(lv_obj_get_width(obj) == w && lv_obj_get_height(obj) == h) { + 350e: 4b2f ldr r3, [pc, #188] ; (35cc ) + 3510: 4620 mov r0, r4 + 3512: 4798 blx r3 + 3514: 4285 cmp r5, r0 + 3516: d104 bne.n 3522 + 3518: 4b2d ldr r3, [pc, #180] ; (35d0 ) + 351a: 4620 mov r0, r4 + 351c: 4798 blx r3 + 351e: 4287 cmp r7, r0 + 3520: d03a beq.n 3598 + lv_obj_invalidate(obj); + 3522: 4620 mov r0, r4 + 3524: 4e2b ldr r6, [pc, #172] ; (35d4 ) + 3526: 47b0 blx r6 + lv_obj_get_coords(obj, &ori); + 3528: a902 add r1, sp, #8 + 352a: 4b2b ldr r3, [pc, #172] ; (35d8 ) + 352c: 4620 mov r0, r4 + 352e: 4798 blx r3 + obj->coords.y2 = obj->coords.y1 + h - 1; + 3530: 8a63 ldrh r3, [r4, #18] + 3532: 3f01 subs r7, #1 + 3534: 441f add r7, r3 + 3536: 82e7 strh r7, [r4, #22] + if(lv_obj_get_base_dir(obj) == LV_BIDI_DIR_RTL) { + 3538: 4b28 ldr r3, [pc, #160] ; (35dc ) + 353a: 4620 mov r0, r4 + 353c: 4798 blx r3 + 353e: 2801 cmp r0, #1 + obj->coords.x1 = obj->coords.x2 - w + 1; + 3540: b2ad uxth r5, r5 + 3542: bf0b itete eq + 3544: 8aa3 ldrheq r3, [r4, #20] + obj->coords.x2 = obj->coords.x1 + w - 1; + 3546: 8a23 ldrhne r3, [r4, #16] + obj->coords.x1 = obj->coords.x2 - w + 1; + 3548: f1c5 0501 rsbeq r5, r5, #1 + obj->coords.x2 = obj->coords.x1 + w - 1; + 354c: f105 35ff addne.w r5, r5, #4294967295 ; 0xffffffff + obj->coords.x1 = obj->coords.x2 - w + 1; + 3550: bf0a itet eq + 3552: 18ed addeq r5, r5, r3 + obj->coords.x2 = obj->coords.x1 + w - 1; + 3554: 18ed addne r5, r5, r3 + obj->coords.x1 = obj->coords.x2 - w + 1; + 3556: 8225 strheq r5, [r4, #16] + obj->signal_cb(obj, LV_SIGNAL_COORD_CHG, &ori); + 3558: 69e3 ldr r3, [r4, #28] + obj->coords.x2 = obj->coords.x1 + w - 1; + 355a: bf18 it ne + 355c: 82a5 strhne r5, [r4, #20] + obj->signal_cb(obj, LV_SIGNAL_COORD_CHG, &ori); + 355e: aa02 add r2, sp, #8 + 3560: 2102 movs r1, #2 + 3562: 4620 mov r0, r4 + 3564: 4798 blx r3 + lv_obj_t * par = lv_obj_get_parent(obj); + 3566: 4b1e ldr r3, [pc, #120] ; (35e0 ) + 3568: 4620 mov r0, r4 + 356a: 4798 blx r3 + if(par != NULL) par->signal_cb(par, LV_SIGNAL_CHILD_CHG, obj); + 356c: b118 cbz r0, 3576 + 356e: 69c3 ldr r3, [r0, #28] + 3570: 4622 mov r2, r4 + 3572: 2101 movs r1, #1 + 3574: 4798 blx r3 + _LV_LL_READ(obj->child_ll, i) { + 3576: 1d27 adds r7, r4, #4 + 3578: 4b1a ldr r3, [pc, #104] ; (35e4 ) + 357a: f8df 8070 ldr.w r8, [pc, #112] ; 35ec + 357e: 4638 mov r0, r7 + 3580: 4798 blx r3 + 3582: 4605 mov r5, r0 + 3584: b95d cbnz r5, 359e + lv_obj_invalidate(obj); + 3586: 4620 mov r0, r4 + 3588: 47b0 blx r6 + if(obj->realign.auto_realign) lv_obj_realign(obj); + 358a: f894 3049 ldrb.w r3, [r4, #73] ; 0x49 + 358e: 07db lsls r3, r3, #31 + 3590: d502 bpl.n 3598 + 3592: 4b15 ldr r3, [pc, #84] ; (35e8 ) + 3594: 4620 mov r0, r4 + 3596: 4798 blx r3 +} + 3598: b004 add sp, #16 + 359a: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + i->signal_cb(i, LV_SIGNAL_PARENT_SIZE_CHG, &ori); + 359e: 69eb ldr r3, [r5, #28] + 35a0: aa02 add r2, sp, #8 + 35a2: 2103 movs r1, #3 + 35a4: 4628 mov r0, r5 + 35a6: 4798 blx r3 + _LV_LL_READ(obj->child_ll, i) { + 35a8: 4629 mov r1, r5 + 35aa: 4638 mov r0, r7 + 35ac: 47c0 blx r8 + 35ae: 4605 mov r5, r0 + 35b0: e7e8 b.n 3584 + 35b2: bf00 nop + 35b4: 000017e1 .word 0x000017e1 + 35b8: 0001f5b5 .word 0x0001f5b5 + 35bc: 0001ee5b .word 0x0001ee5b + 35c0: 0000e8e9 .word 0x0000e8e9 + 35c4: 0001eebf .word 0x0001eebf + 35c8: 000017e9 .word 0x000017e9 + 35cc: 000023ed .word 0x000023ed + 35d0: 0000243d .word 0x0000243d + 35d4: 00002785 .word 0x00002785 + 35d8: 000022d5 .word 0x000022d5 + 35dc: 0000309d .word 0x0000309d + 35e0: 00002125 .word 0x00002125 + 35e4: 0000e6a9 .word 0x0000e6a9 + 35e8: 00002ce9 .word 0x00002ce9 + 35ec: 0000e6b5 .word 0x0000e6b5 + +000035f0 : +{ + 35f0: b573 push {r0, r1, r4, r5, r6, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 35f2: 4b0f ldr r3, [pc, #60] ; (3630 ) +{ + 35f4: 4604 mov r4, r0 + 35f6: 460e mov r6, r1 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 35f8: 4798 blx r3 + 35fa: 4605 mov r5, r0 + 35fc: b968 cbnz r0, 361a + 35fe: 4b0d ldr r3, [pc, #52] ; (3634 ) + 3600: 490d ldr r1, [pc, #52] ; (3638 ) + 3602: 9300 str r3, [sp, #0] + 3604: f240 3227 movw r2, #807 ; 0x327 + 3608: 2003 movs r0, #3 + 360a: 4e0c ldr r6, [pc, #48] ; (363c ) + 360c: 47b0 blx r6 + 360e: 480c ldr r0, [pc, #48] ; (3640 ) + 3610: 490c ldr r1, [pc, #48] ; (3644 ) + 3612: 4622 mov r2, r4 + 3614: 462b mov r3, r5 + 3616: 4788 blx r1 + 3618: e7fe b.n 3618 + lv_obj_set_size(obj, lv_obj_get_width(obj), h); + 361a: 4b0b ldr r3, [pc, #44] ; (3648 ) + 361c: 4620 mov r0, r4 + 361e: 4798 blx r3 + 3620: 4b0a ldr r3, [pc, #40] ; (364c ) + 3622: 4601 mov r1, r0 + 3624: 4632 mov r2, r6 + 3626: 4620 mov r0, r4 +} + 3628: b002 add sp, #8 + 362a: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + lv_obj_set_size(obj, lv_obj_get_width(obj), h); + 362e: 4718 bx r3 + 3630: 000017e1 .word 0x000017e1 + 3634: 0001f5d6 .word 0x0001f5d6 + 3638: 0001ee5b .word 0x0001ee5b + 363c: 0000e8e9 .word 0x0000e8e9 + 3640: 0001eebf .word 0x0001eebf + 3644: 000017e9 .word 0x000017e9 + 3648: 000023ed .word 0x000023ed + 364c: 000034e1 .word 0x000034e1 + +00003650 : +{ + 3650: b573 push {r0, r1, r4, r5, r6, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 3652: 4b0e ldr r3, [pc, #56] ; (368c ) +{ + 3654: 4604 mov r4, r0 + 3656: 460e mov r6, r1 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 3658: 4798 blx r3 + 365a: 4605 mov r5, r0 + 365c: b968 cbnz r0, 367a + 365e: 4b0c ldr r3, [pc, #48] ; (3690 ) + 3660: 490c ldr r1, [pc, #48] ; (3694 ) + 3662: 9300 str r3, [sp, #0] + 3664: f640 22d7 movw r2, #2775 ; 0xad7 + 3668: 2003 movs r0, #3 + 366a: 4e0b ldr r6, [pc, #44] ; (3698 ) + 366c: 47b0 blx r6 + 366e: 480b ldr r0, [pc, #44] ; (369c ) + 3670: 490b ldr r1, [pc, #44] ; (36a0 ) + 3672: 4622 mov r2, r4 + 3674: 462b mov r3, r5 + 3676: 4788 blx r1 + 3678: e7fe b.n 3678 + return (obj->protect & prot) == 0 ? false : true; + 367a: f894 303c ldrb.w r3, [r4, #60] ; 0x3c + 367e: 421e tst r6, r3 +} + 3680: bf14 ite ne + 3682: 2001 movne r0, #1 + 3684: 2000 moveq r0, #0 + 3686: b002 add sp, #8 + 3688: bd70 pop {r4, r5, r6, pc} + 368a: bf00 nop + 368c: 000017e1 .word 0x000017e1 + 3690: 0001f5fb .word 0x0001f5fb + 3694: 0001ee5b .word 0x0001ee5b + 3698: 0000e8e9 .word 0x0000e8e9 + 369c: 0001eebf .word 0x0001eebf + 36a0: 000017e9 .word 0x000017e9 + +000036a4 : +{ + 36a4: b57f push {r0, r1, r2, r3, r4, r5, r6, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 36a6: 4b13 ldr r3, [pc, #76] ; (36f4 ) +{ + 36a8: 4604 mov r4, r0 + 36aa: 460d mov r5, r1 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 36ac: 4798 blx r3 + 36ae: 4606 mov r6, r0 + 36b0: b968 cbnz r0, 36ce + 36b2: 4b11 ldr r3, [pc, #68] ; (36f8 ) + 36b4: 4911 ldr r1, [pc, #68] ; (36fc ) + 36b6: 9300 str r3, [sp, #0] + 36b8: f640 22de movw r2, #2782 ; 0xade + 36bc: 2003 movs r0, #3 + 36be: 4d10 ldr r5, [pc, #64] ; (3700 ) + 36c0: 47a8 blx r5 + 36c2: 4810 ldr r0, [pc, #64] ; (3704 ) + 36c4: 4910 ldr r1, [pc, #64] ; (3708 ) + 36c6: 4622 mov r2, r4 + 36c8: 4633 mov r3, r6 + 36ca: 4788 blx r1 + 36cc: e7fe b.n 36cc + if(part < _LV_OBJ_PART_REAL_LAST) return ((lv_obj_t *)obj)->state; + 36ce: 2d3f cmp r5, #63 ; 0x3f + 36d0: d803 bhi.n 36da + 36d2: f894 003d ldrb.w r0, [r4, #61] ; 0x3d +} + 36d6: b004 add sp, #16 + 36d8: bd70 pop {r4, r5, r6, pc} + info.result = LV_STATE_DEFAULT; + 36da: 2300 movs r3, #0 + 36dc: f88d 300d strb.w r3, [sp, #13] + lv_signal_send((lv_obj_t *)obj, LV_SIGNAL_GET_STATE_DSC, &info); + 36e0: aa03 add r2, sp, #12 + 36e2: 4b0a ldr r3, [pc, #40] ; (370c ) + info.part = part; + 36e4: f88d 500c strb.w r5, [sp, #12] + lv_signal_send((lv_obj_t *)obj, LV_SIGNAL_GET_STATE_DSC, &info); + 36e8: 2109 movs r1, #9 + 36ea: 4620 mov r0, r4 + 36ec: 4798 blx r3 + return info.result; + 36ee: f89d 000d ldrb.w r0, [sp, #13] + 36f2: e7f0 b.n 36d6 + 36f4: 000017e1 .word 0x000017e1 + 36f8: 0001f60f .word 0x0001f60f + 36fc: 0001ee5b .word 0x0001ee5b + 3700: 0000e8e9 .word 0x0000e8e9 + 3704: 0001eebf .word 0x0001eebf + 3708: 000017e9 .word 0x000017e9 + 370c: 00002025 .word 0x00002025 + +00003710 <_lv_obj_get_style_int>: +{ + 3710: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} + lv_state_t state = lv_obj_get_state(parent, part); + 3714: f8df a094 ldr.w sl, [pc, #148] ; 37ac <_lv_obj_get_style_int+0x9c> + res = _lv_style_list_get_int(dsc, prop, &value_act); + 3718: f8df b094 ldr.w fp, [pc, #148] ; 37b0 <_lv_obj_get_style_int+0xa0> +{ + 371c: 4605 mov r5, r0 + 371e: 460e mov r6, r1 + 3720: 4617 mov r7, r2 + attr.full = prop_ori >> 8; + 3722: ea4f 2812 mov.w r8, r2, lsr #8 + while(parent) { + 3726: 4614 mov r4, r2 + 3728: b965 cbnz r5, 3744 <_lv_obj_get_style_int+0x34> + prop = prop & (~LV_STYLE_STATE_MASK); + 372a: f424 44fe bic.w r4, r4, #32512 ; 0x7f00 + switch(prop) { + 372e: 2c22 cmp r4, #34 ; 0x22 + prop = prop & (~LV_STYLE_STATE_MASK); + 3730: b2a0 uxth r0, r4 + switch(prop) { + 3732: d030 beq.n 3796 <_lv_obj_get_style_int+0x86> + 3734: d827 bhi.n 3786 <_lv_obj_get_style_int+0x76> + 3736: 2803 cmp r0, #3 + 3738: d02f beq.n 379a <_lv_obj_get_style_int+0x8a> + 373a: 1fc2 subs r2, r0, #7 + 373c: 4250 negs r0, r2 + 373e: 4150 adcs r0, r2 + 3740: 0200 lsls r0, r0, #8 + 3742: e013 b.n 376c <_lv_obj_get_style_int+0x5c> + lv_style_list_t * dsc = lv_obj_get_style_list(parent, part); + 3744: 4b17 ldr r3, [pc, #92] ; (37a4 <_lv_obj_get_style_int+0x94>) + 3746: 4631 mov r1, r6 + 3748: 4628 mov r0, r5 + 374a: 4798 blx r3 + lv_state_t state = lv_obj_get_state(parent, part); + 374c: 4631 mov r1, r6 + lv_style_list_t * dsc = lv_obj_get_style_list(parent, part); + 374e: 4681 mov r9, r0 + lv_state_t state = lv_obj_get_state(parent, part); + 3750: 4628 mov r0, r5 + 3752: 47d0 blx sl + prop = (uint16_t)prop_ori + ((uint16_t)state << LV_STYLE_STATE_POS); + 3754: eb07 2000 add.w r0, r7, r0, lsl #8 + 3758: b284 uxth r4, r0 + res = _lv_style_list_get_int(dsc, prop, &value_act); + 375a: f10d 0206 add.w r2, sp, #6 + 375e: 4621 mov r1, r4 + 3760: 4648 mov r0, r9 + 3762: 47d8 blx fp + if(res == LV_RES_OK) return value_act; + 3764: 2801 cmp r0, #1 + 3766: d104 bne.n 3772 <_lv_obj_get_style_int+0x62> + 3768: f9bd 0006 ldrsh.w r0, [sp, #6] +} + 376c: b003 add sp, #12 + 376e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + if(attr.bits.inherit == 0) break; + 3772: f018 0f80 tst.w r8, #128 ; 0x80 + 3776: d0d8 beq.n 372a <_lv_obj_get_style_int+0x1a> + if(part != LV_OBJ_PART_MAIN) { + 3778: b91e cbnz r6, 3782 <_lv_obj_get_style_int+0x72> + parent = lv_obj_get_parent(parent); + 377a: 4628 mov r0, r5 + 377c: 4b0a ldr r3, [pc, #40] ; (37a8 <_lv_obj_get_style_int+0x98>) + 377e: 4798 blx r3 + 3780: 4605 mov r5, r0 +{ + 3782: 2600 movs r6, #0 + 3784: e7d0 b.n 3728 <_lv_obj_get_style_int+0x18> + switch(prop) { + 3786: 2831 cmp r0, #49 ; 0x31 + 3788: d009 beq.n 379e <_lv_obj_get_style_int+0x8e> + 378a: f1a0 03c0 sub.w r3, r0, #192 ; 0xc0 + 378e: 4258 negs r0, r3 + 3790: 4158 adcs r0, r3 + 3792: 0100 lsls r0, r0, #4 + 3794: e7ea b.n 376c <_lv_obj_get_style_int+0x5c> + return 255; + 3796: 20ff movs r0, #255 ; 0xff + 3798: e7e8 b.n 376c <_lv_obj_get_style_int+0x5c> + switch(prop) { + 379a: 2006 movs r0, #6 + 379c: e7e6 b.n 376c <_lv_obj_get_style_int+0x5c> + return LV_BORDER_SIDE_FULL; + 379e: 200f movs r0, #15 + 37a0: e7e4 b.n 376c <_lv_obj_get_style_int+0x5c> + 37a2: bf00 nop + 37a4: 0000248d .word 0x0000248d + 37a8: 00002125 .word 0x00002125 + 37ac: 000036a5 .word 0x000036a5 + 37b0: 00005e8d .word 0x00005e8d + +000037b4 <_lv_obj_get_style_color>: +{ + 37b4: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} + lv_state_t state = lv_obj_get_state(parent, part); + 37b8: f8df a074 ldr.w sl, [pc, #116] ; 3830 <_lv_obj_get_style_color+0x7c> + res = _lv_style_list_get_color(dsc, prop, &value_act); + 37bc: f8df b074 ldr.w fp, [pc, #116] ; 3834 <_lv_obj_get_style_color+0x80> +{ + 37c0: 4605 mov r5, r0 + 37c2: 460e mov r6, r1 + 37c4: 4617 mov r7, r2 + attr.full = prop_ori >> 8; + 37c6: ea4f 2812 mov.w r8, r2, lsr #8 + while(parent) { + 37ca: 4614 mov r4, r2 + 37cc: b94d cbnz r5, 37e2 <_lv_obj_get_style_color+0x2e> + prop = prop & (~LV_STYLE_STATE_MASK); + 37ce: f424 44fe bic.w r4, r4, #32512 ; 0x7f00 + switch(prop) { + 37d2: 3c29 subs r4, #41 ; 0x29 + 37d4: 2c01 cmp r4, #1 + return LV_COLOR_WHITE; + 37d6: bf96 itet ls + 37d8: 4b12 ldrls r3, [pc, #72] ; (3824 <_lv_obj_get_style_color+0x70>) + return LV_COLOR_BLACK; + 37da: 2000 movhi r0, #0 + return LV_COLOR_WHITE; + 37dc: f8b3 0602 ldrhls.w r0, [r3, #1538] ; 0x602 + return LV_COLOR_BLACK; + 37e0: e012 b.n 3808 <_lv_obj_get_style_color+0x54> + lv_style_list_t * dsc = lv_obj_get_style_list(parent, part); + 37e2: 4b11 ldr r3, [pc, #68] ; (3828 <_lv_obj_get_style_color+0x74>) + 37e4: 4631 mov r1, r6 + 37e6: 4628 mov r0, r5 + 37e8: 4798 blx r3 + lv_state_t state = lv_obj_get_state(parent, part); + 37ea: 4631 mov r1, r6 + lv_style_list_t * dsc = lv_obj_get_style_list(parent, part); + 37ec: 4681 mov r9, r0 + lv_state_t state = lv_obj_get_state(parent, part); + 37ee: 4628 mov r0, r5 + 37f0: 47d0 blx sl + prop = (uint16_t)prop_ori + ((uint16_t)state << LV_STYLE_STATE_POS); + 37f2: eb07 2000 add.w r0, r7, r0, lsl #8 + 37f6: b284 uxth r4, r0 + res = _lv_style_list_get_color(dsc, prop, &value_act); + 37f8: aa01 add r2, sp, #4 + 37fa: 4621 mov r1, r4 + 37fc: 4648 mov r0, r9 + 37fe: 47d8 blx fp + if(res == LV_RES_OK) return value_act; + 3800: 2801 cmp r0, #1 + 3802: d104 bne.n 380e <_lv_obj_get_style_color+0x5a> + 3804: f8bd 0004 ldrh.w r0, [sp, #4] +} + 3808: b003 add sp, #12 + 380a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + if(attr.bits.inherit == 0) break; + 380e: f018 0f80 tst.w r8, #128 ; 0x80 + 3812: d0dc beq.n 37ce <_lv_obj_get_style_color+0x1a> + if(part != LV_OBJ_PART_MAIN) { + 3814: b91e cbnz r6, 381e <_lv_obj_get_style_color+0x6a> + parent = lv_obj_get_parent(parent); + 3816: 4628 mov r0, r5 + 3818: 4b04 ldr r3, [pc, #16] ; (382c <_lv_obj_get_style_color+0x78>) + 381a: 4798 blx r3 + 381c: 4605 mov r5, r0 +{ + 381e: 2600 movs r6, #0 + 3820: e7d4 b.n 37cc <_lv_obj_get_style_color+0x18> + 3822: bf00 nop + 3824: 0001f062 .word 0x0001f062 + 3828: 0000248d .word 0x0000248d + 382c: 00002125 .word 0x00002125 + 3830: 000036a5 .word 0x000036a5 + 3834: 00005f15 .word 0x00005f15 + +00003838 <_lv_obj_get_style_opa>: +{ + 3838: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} + lv_state_t state = lv_obj_get_state(parent, part); + 383c: f8df a080 ldr.w sl, [pc, #128] ; 38c0 <_lv_obj_get_style_opa+0x88> + res = _lv_style_list_get_opa(dsc, prop, &value_act); + 3840: f8df b080 ldr.w fp, [pc, #128] ; 38c4 <_lv_obj_get_style_opa+0x8c> +{ + 3844: 4605 mov r5, r0 + 3846: 460e mov r6, r1 + 3848: 4617 mov r7, r2 + attr.full = prop_ori >> 8; + 384a: ea4f 2812 mov.w r8, r2, lsr #8 + while(parent) { + 384e: 4614 mov r4, r2 + 3850: b975 cbnz r5, 3870 <_lv_obj_get_style_opa+0x38> + prop = prop & (~LV_STYLE_STATE_MASK); + 3852: f424 44fe bic.w r4, r4, #32512 ; 0x7f00 + switch(prop) { + 3856: 2c6d cmp r4, #109 ; 0x6d + prop = prop & (~LV_STYLE_STATE_MASK); + 3858: b2a0 uxth r0, r4 + switch(prop) { + 385a: d02a beq.n 38b2 <_lv_obj_get_style_opa+0x7a> + 385c: f248 03ad movw r3, #32941 ; 0x80ad + 3860: 4298 cmp r0, r3 + 3862: d026 beq.n 38b2 <_lv_obj_get_style_opa+0x7a> + 3864: 382c subs r0, #44 ; 0x2c + 3866: bf18 it ne + 3868: f04f 30ff movne.w r0, #4294967295 ; 0xffffffff + 386c: b2c0 uxtb r0, r0 + 386e: e013 b.n 3898 <_lv_obj_get_style_opa+0x60> + lv_style_list_t * dsc = lv_obj_get_style_list(parent, part); + 3870: 4b11 ldr r3, [pc, #68] ; (38b8 <_lv_obj_get_style_opa+0x80>) + 3872: 4631 mov r1, r6 + 3874: 4628 mov r0, r5 + 3876: 4798 blx r3 + lv_state_t state = lv_obj_get_state(parent, part); + 3878: 4631 mov r1, r6 + lv_style_list_t * dsc = lv_obj_get_style_list(parent, part); + 387a: 4681 mov r9, r0 + lv_state_t state = lv_obj_get_state(parent, part); + 387c: 4628 mov r0, r5 + 387e: 47d0 blx sl + prop = (uint16_t)prop_ori + ((uint16_t)state << LV_STYLE_STATE_POS); + 3880: eb07 2000 add.w r0, r7, r0, lsl #8 + 3884: b284 uxth r4, r0 + res = _lv_style_list_get_opa(dsc, prop, &value_act); + 3886: f10d 0207 add.w r2, sp, #7 + 388a: 4621 mov r1, r4 + 388c: 4648 mov r0, r9 + 388e: 47d8 blx fp + if(res == LV_RES_OK) return value_act; + 3890: 2801 cmp r0, #1 + 3892: d104 bne.n 389e <_lv_obj_get_style_opa+0x66> + 3894: f89d 0007 ldrb.w r0, [sp, #7] +} + 3898: b003 add sp, #12 + 389a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + if(attr.bits.inherit == 0) break; + 389e: f018 0f80 tst.w r8, #128 ; 0x80 + 38a2: d0d6 beq.n 3852 <_lv_obj_get_style_opa+0x1a> + if(part != LV_OBJ_PART_MAIN) { + 38a4: b91e cbnz r6, 38ae <_lv_obj_get_style_opa+0x76> + parent = lv_obj_get_parent(parent); + 38a6: 4628 mov r0, r5 + 38a8: 4b04 ldr r3, [pc, #16] ; (38bc <_lv_obj_get_style_opa+0x84>) + 38aa: 4798 blx r3 + 38ac: 4605 mov r5, r0 +{ + 38ae: 2600 movs r6, #0 + 38b0: e7ce b.n 3850 <_lv_obj_get_style_opa+0x18> + return LV_OPA_TRANSP; + 38b2: 2000 movs r0, #0 + 38b4: e7f0 b.n 3898 <_lv_obj_get_style_opa+0x60> + 38b6: bf00 nop + 38b8: 0000248d .word 0x0000248d + 38bc: 00002125 .word 0x00002125 + 38c0: 000036a5 .word 0x000036a5 + 38c4: 00005f9d .word 0x00005f9d + +000038c8 <_lv_obj_get_style_ptr>: +{ + 38c8: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} + lv_state_t state = lv_obj_get_state(parent, part); + 38cc: f8df a084 ldr.w sl, [pc, #132] ; 3954 <_lv_obj_get_style_ptr+0x8c> + res = _lv_style_list_get_ptr(dsc, prop, &value_act); + 38d0: f8df b084 ldr.w fp, [pc, #132] ; 3958 <_lv_obj_get_style_ptr+0x90> +{ + 38d4: 4605 mov r5, r0 + 38d6: 460e mov r6, r1 + 38d8: 4617 mov r7, r2 + attr.full = prop_ori >> 8; + 38da: ea4f 2812 mov.w r8, r2, lsr #8 + while(parent) { + 38de: 4614 mov r4, r2 + 38e0: b96d cbnz r5, 38fe <_lv_obj_get_style_ptr+0x36> + prop = prop & (~LV_STYLE_STATE_MASK); + 38e2: f424 44fe bic.w r4, r4, #32512 ; 0x7f00 + switch(prop) { + 38e6: 2cbe cmp r4, #190 ; 0xbe + prop = prop & (~LV_STYLE_STATE_MASK); + 38e8: b2a3 uxth r3, r4 + switch(prop) { + 38ea: d027 beq.n 393c <_lv_obj_get_style_ptr+0x74> + 38ec: f248 028e movw r2, #32910 ; 0x808e + 38f0: 4293 cmp r3, r2 + 38f2: d001 beq.n 38f8 <_lv_obj_get_style_ptr+0x30> + 38f4: 2b7e cmp r3, #126 ; 0x7e + 38f6: d123 bne.n 3940 <_lv_obj_get_style_ptr+0x78> + return lv_theme_get_font_normal(); + 38f8: 4b12 ldr r3, [pc, #72] ; (3944 <_lv_obj_get_style_ptr+0x7c>) + 38fa: 4798 blx r3 + 38fc: e011 b.n 3922 <_lv_obj_get_style_ptr+0x5a> + lv_style_list_t * dsc = lv_obj_get_style_list(parent, part); + 38fe: 4b12 ldr r3, [pc, #72] ; (3948 <_lv_obj_get_style_ptr+0x80>) + 3900: 4631 mov r1, r6 + 3902: 4628 mov r0, r5 + 3904: 4798 blx r3 + lv_state_t state = lv_obj_get_state(parent, part); + 3906: 4631 mov r1, r6 + lv_style_list_t * dsc = lv_obj_get_style_list(parent, part); + 3908: 4681 mov r9, r0 + lv_state_t state = lv_obj_get_state(parent, part); + 390a: 4628 mov r0, r5 + 390c: 47d0 blx sl + prop = (uint16_t)prop_ori + ((uint16_t)state << LV_STYLE_STATE_POS); + 390e: eb07 2000 add.w r0, r7, r0, lsl #8 + 3912: b284 uxth r4, r0 + res = _lv_style_list_get_ptr(dsc, prop, &value_act); + 3914: aa01 add r2, sp, #4 + 3916: 4621 mov r1, r4 + 3918: 4648 mov r0, r9 + 391a: 47d8 blx fp + if(res == LV_RES_OK) return value_act; + 391c: 2801 cmp r0, #1 + 391e: d103 bne.n 3928 <_lv_obj_get_style_ptr+0x60> + 3920: 9801 ldr r0, [sp, #4] +} + 3922: b003 add sp, #12 + 3924: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + if(attr.bits.inherit == 0) break; + 3928: f018 0f80 tst.w r8, #128 ; 0x80 + 392c: d0d9 beq.n 38e2 <_lv_obj_get_style_ptr+0x1a> + if(part != LV_OBJ_PART_MAIN) { + 392e: b91e cbnz r6, 3938 <_lv_obj_get_style_ptr+0x70> + parent = lv_obj_get_parent(parent); + 3930: 4628 mov r0, r5 + 3932: 4b06 ldr r3, [pc, #24] ; (394c <_lv_obj_get_style_ptr+0x84>) + 3934: 4798 blx r3 + 3936: 4605 mov r5, r0 +{ + 3938: 2600 movs r6, #0 + 393a: e7d1 b.n 38e0 <_lv_obj_get_style_ptr+0x18> + return &lv_anim_path_def; + 393c: 4804 ldr r0, [pc, #16] ; (3950 <_lv_obj_get_style_ptr+0x88>) + 393e: e7f0 b.n 3922 <_lv_obj_get_style_ptr+0x5a> + switch(prop) { + 3940: 2000 movs r0, #0 + 3942: e7ee b.n 3922 <_lv_obj_get_style_ptr+0x5a> + 3944: 000102d9 .word 0x000102d9 + 3948: 0000248d .word 0x0000248d + 394c: 00002125 .word 0x00002125 + 3950: 00023f24 .word 0x00023f24 + 3954: 000036a5 .word 0x000036a5 + 3958: 00006025 .word 0x00006025 + +0000395c : +{ + 395c: b570 push {r4, r5, r6, lr} + lv_style_trans_t * tr = a->var; + 395e: 6804 ldr r4, [r0, #0] + lv_style_property_t prop_tmp = tr->prop; + 3960: 88a5 ldrh r5, [r4, #4] + tr->start_value._int = _lv_obj_get_style_int(tr->obj, tr->part, prop_tmp); + 3962: 6820 ldr r0, [r4, #0] + 3964: 79a1 ldrb r1, [r4, #6] + 3966: f005 030f and.w r3, r5, #15 + if((prop_tmp & 0xF) < LV_STYLE_ID_COLOR) { /*Int*/ + 396a: 2b08 cmp r3, #8 + tr->start_value._int = _lv_obj_get_style_int(tr->obj, tr->part, prop_tmp); + 396c: 462a mov r2, r5 + if((prop_tmp & 0xF) < LV_STYLE_ID_COLOR) { /*Int*/ + 396e: d80c bhi.n 398a + tr->start_value._int = _lv_obj_get_style_int(tr->obj, tr->part, prop_tmp); + 3970: 4b0d ldr r3, [pc, #52] ; (39a8 ) + 3972: 4798 blx r3 + tr->start_value._color = _lv_obj_get_style_color(tr->obj, tr->part, prop_tmp); + 3974: 8120 strh r0, [r4, #8] + tr->prop = 0; + 3976: 2300 movs r3, #0 + 3978: 80a3 strh r3, [r4, #4] + trans_del(tr->obj, tr->part, prop_tmp, tr); + 397a: 79a1 ldrb r1, [r4, #6] + 397c: 6820 ldr r0, [r4, #0] + 397e: 4e0b ldr r6, [pc, #44] ; (39ac ) + 3980: 4623 mov r3, r4 + 3982: 462a mov r2, r5 + 3984: 47b0 blx r6 + tr->prop = prop_tmp; + 3986: 80a5 strh r5, [r4, #4] +} + 3988: bd70 pop {r4, r5, r6, pc} + else if((prop_tmp & 0xF) < LV_STYLE_ID_OPA) { /*Color*/ + 398a: 2b0b cmp r3, #11 + 398c: d802 bhi.n 3994 + tr->start_value._color = _lv_obj_get_style_color(tr->obj, tr->part, prop_tmp); + 398e: 4b08 ldr r3, [pc, #32] ; (39b0 ) + 3990: 4798 blx r3 + 3992: e7ef b.n 3974 + else if((prop_tmp & 0xF) < LV_STYLE_ID_PTR) { /*Opa*/ + 3994: 2b0d cmp r3, #13 + 3996: d803 bhi.n 39a0 + tr->start_value._opa = _lv_obj_get_style_opa(tr->obj, tr->part, prop_tmp); + 3998: 4b06 ldr r3, [pc, #24] ; (39b4 ) + 399a: 4798 blx r3 + 399c: 7220 strb r0, [r4, #8] + 399e: e7ea b.n 3976 + tr->start_value._ptr = _lv_obj_get_style_ptr(tr->obj, tr->part, prop_tmp); + 39a0: 4b05 ldr r3, [pc, #20] ; (39b8 ) + 39a2: 4798 blx r3 + 39a4: 60a0 str r0, [r4, #8] + 39a6: e7e6 b.n 3976 + 39a8: 00003711 .word 0x00003711 + 39ac: 000024b5 .word 0x000024b5 + 39b0: 000037b5 .word 0x000037b5 + 39b4: 00003839 .word 0x00003839 + 39b8: 000038c9 .word 0x000038c9 + +000039bc : +{ + 39bc: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + if(obj->state == new_state) return; + 39c0: f890 303d ldrb.w r3, [r0, #61] ; 0x3d + 39c4: 428b cmp r3, r1 +{ + 39c6: b09f sub sp, #124 ; 0x7c + 39c8: 4604 mov r4, r0 + 39ca: 4688 mov r8, r1 + if(obj->state == new_state) return; + 39cc: f000 8242 beq.w 3e54 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 39d0: 4b95 ldr r3, [pc, #596] ; (3c28 ) + 39d2: 4798 blx r3 + 39d4: 4605 mov r5, r0 + 39d6: b968 cbnz r0, 39f4 + 39d8: 4b94 ldr r3, [pc, #592] ; (3c2c ) + 39da: 4995 ldr r1, [pc, #596] ; (3c30 ) + 39dc: 9300 str r3, [sp, #0] + 39de: f240 6237 movw r2, #1591 ; 0x637 + 39e2: 2003 movs r0, #3 + 39e4: 4e93 ldr r6, [pc, #588] ; (3c34 ) + 39e6: 47b0 blx r6 + 39e8: 4893 ldr r0, [pc, #588] ; (3c38 ) + 39ea: 4994 ldr r1, [pc, #592] ; (3c3c ) + 39ec: 4622 mov r2, r4 + 39ee: 462b mov r3, r5 + 39f0: 4788 blx r1 + 39f2: e7fe b.n 39f2 + lv_state_t prev_state = obj->state; + 39f4: f894 303d ldrb.w r3, [r4, #61] ; 0x3d + 39f8: 9302 str r3, [sp, #8] + obj->state = new_state; + 39fa: 2300 movs r3, #0 + 39fc: f884 803d strb.w r8, [r4, #61] ; 0x3d + 3a00: 9303 str r3, [sp, #12] + 3a02: f89d 600c ldrb.w r6, [sp, #12] + lv_style_list_t * style_list = lv_obj_get_style_list(obj, part); + 3a06: 4b8e ldr r3, [pc, #568] ; (3c40 ) + 3a08: 4631 mov r1, r6 + 3a0a: 4620 mov r0, r4 + 3a0c: 4798 blx r3 + if(style_list == NULL) break; /*No more style lists*/ + 3a0e: 9005 str r0, [sp, #20] + 3a10: b140 cbz r0, 3a24 + if(style_list->ignore_trans) continue; + 3a12: 7947 ldrb r7, [r0, #5] + 3a14: f017 0708 ands.w r7, r7, #8 + 3a18: d00b beq.n 3a32 + for(part = 0; part < _LV_OBJ_PART_REAL_LAST; part++) { + 3a1a: 9b03 ldr r3, [sp, #12] + 3a1c: 3301 adds r3, #1 + 3a1e: 2b40 cmp r3, #64 ; 0x40 + 3a20: 9303 str r3, [sp, #12] + 3a22: d1ee bne.n 3a02 + lv_obj_refresh_style(obj, LV_STYLE_PROP_ALL); + 3a24: 4b87 ldr r3, [pc, #540] ; (3c44 ) + 3a26: 21ff movs r1, #255 ; 0xff + 3a28: 4620 mov r0, r4 +} + 3a2a: b01f add sp, #124 ; 0x7c + 3a2c: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + lv_obj_refresh_style(obj, LV_STYLE_PROP_ALL); + 3a30: 4718 bx r3 +_LV_OBJ_STYLE_SET_GET_DECLARE(LINE_OPA, line_opa, lv_opa_t, _opa, scalar) +_LV_OBJ_STYLE_SET_GET_DECLARE(IMAGE_BLEND_MODE, image_blend_mode, lv_blend_mode_t, _int, scalar) +_LV_OBJ_STYLE_SET_GET_DECLARE(IMAGE_RECOLOR, image_recolor, lv_color_t, _color, nonscalar) +_LV_OBJ_STYLE_SET_GET_DECLARE(IMAGE_OPA, image_opa, lv_opa_t, _opa, scalar) +_LV_OBJ_STYLE_SET_GET_DECLARE(IMAGE_RECOLOR_OPA, image_recolor_opa, lv_opa_t, _opa, scalar) +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSITION_TIME, transition_time, lv_style_int_t, _int, scalar) + 3a32: 4d85 ldr r5, [pc, #532] ; (3c48 ) + 3a34: 22b0 movs r2, #176 ; 0xb0 + 3a36: 4631 mov r1, r6 + 3a38: 4620 mov r0, r4 + 3a3a: 47a8 blx r5 +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSITION_DELAY, transition_delay, lv_style_int_t, _int, scalar) + 3a3c: 22b1 movs r2, #177 ; 0xb1 +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSITION_TIME, transition_time, lv_style_int_t, _int, scalar) + 3a3e: 9009 str r0, [sp, #36] ; 0x24 +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSITION_DELAY, transition_delay, lv_style_int_t, _int, scalar) + 3a40: 4631 mov r1, r6 + 3a42: 4620 mov r0, r4 + 3a44: 47a8 blx r5 +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSITION_PROP_3, transition_prop_3, lv_style_int_t, _int, scalar) +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSITION_PROP_4, transition_prop_4, lv_style_int_t, _int, scalar) +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSITION_PROP_5, transition_prop_5, lv_style_int_t, _int, scalar) +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSITION_PROP_6, transition_prop_6, lv_style_int_t, _int, scalar) +#if LV_USE_ANIMATION +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSITION_PATH, transition_path, lv_anim_path_t *, _ptr, scalar) + 3a46: 4b81 ldr r3, [pc, #516] ; (3c4c ) +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSITION_DELAY, transition_delay, lv_style_int_t, _int, scalar) + 3a48: 9008 str r0, [sp, #32] +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSITION_PATH, transition_path, lv_anim_path_t *, _ptr, scalar) + 3a4a: 22be movs r2, #190 ; 0xbe + 3a4c: 4631 mov r1, r6 + 3a4e: 4620 mov r0, r4 + 3a50: 4798 blx r3 +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSITION_PROP_1, transition_prop_1, lv_style_int_t, _int, scalar) + 3a52: 22b2 movs r2, #178 ; 0xb2 +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSITION_PATH, transition_path, lv_anim_path_t *, _ptr, scalar) + 3a54: 9006 str r0, [sp, #24] +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSITION_PROP_1, transition_prop_1, lv_style_int_t, _int, scalar) + 3a56: 4631 mov r1, r6 + 3a58: 4620 mov r0, r4 + 3a5a: 47a8 blx r5 +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSITION_PROP_2, transition_prop_2, lv_style_int_t, _int, scalar) + 3a5c: 22b3 movs r2, #179 ; 0xb3 + props[0] = lv_obj_get_style_transition_prop_1(obj, part); + 3a5e: f8ad 002c strh.w r0, [sp, #44] ; 0x2c + 3a62: 4631 mov r1, r6 + 3a64: 4620 mov r0, r4 + 3a66: 47a8 blx r5 +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSITION_PROP_3, transition_prop_3, lv_style_int_t, _int, scalar) + 3a68: 22b4 movs r2, #180 ; 0xb4 + props[1] = lv_obj_get_style_transition_prop_2(obj, part); + 3a6a: f8ad 002e strh.w r0, [sp, #46] ; 0x2e + 3a6e: 4631 mov r1, r6 + 3a70: 4620 mov r0, r4 + 3a72: 47a8 blx r5 +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSITION_PROP_4, transition_prop_4, lv_style_int_t, _int, scalar) + 3a74: 22b5 movs r2, #181 ; 0xb5 + props[2] = lv_obj_get_style_transition_prop_3(obj, part); + 3a76: f8ad 0030 strh.w r0, [sp, #48] ; 0x30 + 3a7a: 4631 mov r1, r6 + 3a7c: 4620 mov r0, r4 + 3a7e: 47a8 blx r5 +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSITION_PROP_5, transition_prop_5, lv_style_int_t, _int, scalar) + 3a80: 22b6 movs r2, #182 ; 0xb6 + props[3] = lv_obj_get_style_transition_prop_4(obj, part); + 3a82: f8ad 0032 strh.w r0, [sp, #50] ; 0x32 + 3a86: 4631 mov r1, r6 + 3a88: 4620 mov r0, r4 + 3a8a: 47a8 blx r5 +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSITION_PROP_6, transition_prop_6, lv_style_int_t, _int, scalar) + 3a8c: 22b7 movs r2, #183 ; 0xb7 + props[4] = lv_obj_get_style_transition_prop_5(obj, part); + 3a8e: f8ad 0034 strh.w r0, [sp, #52] ; 0x34 + 3a92: 4631 mov r1, r6 + 3a94: 4620 mov r0, r4 + 3a96: 47a8 blx r5 + props[5] = lv_obj_get_style_transition_prop_6(obj, part); + 3a98: 9704 str r7, [sp, #16] + 3a9a: f8ad 0036 strh.w r0, [sp, #54] ; 0x36 + if(props[i] != 0) { + 3a9e: 9a04 ldr r2, [sp, #16] + 3aa0: ab0b add r3, sp, #44 ; 0x2c + 3aa2: f833 7012 ldrh.w r7, [r3, r2, lsl #1] + 3aa6: 2f00 cmp r7, #0 + 3aa8: f000 80b6 beq.w 3c18 + _lv_style_list_add_trans_style(style_list); + 3aac: 4b68 ldr r3, [pc, #416] ; (3c50 ) + 3aae: 9805 ldr r0, [sp, #20] + 3ab0: 4798 blx r3 + lv_style_list_t * style_list = lv_obj_get_style_list(obj, part); + 3ab2: 4b63 ldr r3, [pc, #396] ; (3c40 ) + 3ab4: 4631 mov r1, r6 + 3ab6: 4620 mov r0, r4 + 3ab8: 4798 blx r3 + lv_style_t * style_trans = _lv_style_list_get_transition_style(style_list); + 3aba: 4b66 ldr r3, [pc, #408] ; (3c54 ) + lv_style_list_t * style_list = lv_obj_get_style_list(obj, part); + 3abc: 4605 mov r5, r0 + lv_style_t * style_trans = _lv_style_list_get_transition_style(style_list); + 3abe: 4798 blx r3 + 3ac0: f007 030f and.w r3, r7, #15 + if((prop & 0xF) < LV_STYLE_ID_COLOR) { /*Int*/ + 3ac4: 2b08 cmp r3, #8 + lv_style_t * style_trans = _lv_style_list_get_transition_style(style_list); + 3ac6: 4682 mov sl, r0 + if((prop & 0xF) < LV_STYLE_ID_COLOR) { /*Int*/ + 3ac8: f200 80dc bhi.w 3c84 + style_list->skip_trans = 1; + 3acc: 796b ldrb r3, [r5, #5] + lv_style_int_t int1 = _lv_obj_get_style_int(obj, part, prop); + 3ace: f8df b178 ldr.w fp, [pc, #376] ; 3c48 + style_list->skip_trans = 1; + 3ad2: f043 0304 orr.w r3, r3, #4 + 3ad6: 716b strb r3, [r5, #5] + obj->state = prev_state; + 3ad8: 9b02 ldr r3, [sp, #8] + 3ada: f884 303d strb.w r3, [r4, #61] ; 0x3d + lv_style_int_t int1 = _lv_obj_get_style_int(obj, part, prop); + 3ade: 463a mov r2, r7 + 3ae0: 4631 mov r1, r6 + 3ae2: 4620 mov r0, r4 + 3ae4: 47d8 blx fp + lv_style_int_t int2 = _lv_obj_get_style_int(obj, part, prop); + 3ae6: 463a mov r2, r7 + lv_style_int_t int1 = _lv_obj_get_style_int(obj, part, prop); + 3ae8: 9007 str r0, [sp, #28] + obj->state = new_state; + 3aea: f884 803d strb.w r8, [r4, #61] ; 0x3d + lv_style_int_t int2 = _lv_obj_get_style_int(obj, part, prop); + 3aee: 4631 mov r1, r6 + 3af0: 4620 mov r0, r4 + 3af2: 47d8 blx fp + style_list->skip_trans = 0; + 3af4: 796a ldrb r2, [r5, #5] + if(int1 == int2) return NULL; + 3af6: 9b07 ldr r3, [sp, #28] + style_list->skip_trans = 0; + 3af8: f36f 0282 bfc r2, #2, #1 + if(int1 == int2) return NULL; + 3afc: 4283 cmp r3, r0 + lv_style_int_t int2 = _lv_obj_get_style_int(obj, part, prop); + 3afe: 4681 mov r9, r0 + style_list->skip_trans = 0; + 3b00: 716a strb r2, [r5, #5] + if(int1 == int2) return NULL; + 3b02: f000 8089 beq.w 3c18 + obj->state = prev_state; + 3b06: 9b02 ldr r3, [sp, #8] + 3b08: f884 303d strb.w r3, [r4, #61] ; 0x3d + int1 = _lv_obj_get_style_int(obj, part, prop); + 3b0c: 463a mov r2, r7 + 3b0e: 4631 mov r1, r6 + 3b10: 4620 mov r0, r4 + 3b12: 47d8 blx fp + _lv_style_set_int(style_trans, prop, int1); /*Be sure `trans_style` has a valid value */ + 3b14: 4b50 ldr r3, [pc, #320] ; (3c58 ) + obj->state = new_state; + 3b16: f884 803d strb.w r8, [r4, #61] ; 0x3d + _lv_style_set_int(style_trans, prop, int1); /*Be sure `trans_style` has a valid value */ + 3b1a: 4602 mov r2, r0 + int1 = _lv_obj_get_style_int(obj, part, prop); + 3b1c: 4683 mov fp, r0 + _lv_style_set_int(style_trans, prop, int1); /*Be sure `trans_style` has a valid value */ + 3b1e: 4639 mov r1, r7 + 3b20: 4650 mov r0, sl + 3b22: 4798 blx r3 + if(prop == LV_STYLE_RADIUS) { + 3b24: 2f01 cmp r7, #1 + 3b26: d122 bne.n 3b6e + if(int1 == LV_RADIUS_CIRCLE || int2 == LV_RADIUS_CIRCLE) { + 3b28: f647 73ff movw r3, #32767 ; 0x7fff + 3b2c: 459b cmp fp, r3 + 3b2e: d001 beq.n 3b34 + 3b30: 4599 cmp r9, r3 + 3b32: d11c bne.n 3b6e + lv_coord_t whalf = lv_obj_get_width(obj) / 2; + 3b34: f8df a148 ldr.w sl, [pc, #328] ; 3c80 + 3b38: 4620 mov r0, r4 + 3b3a: 47d0 blx sl + 3b3c: eb00 70d0 add.w r0, r0, r0, lsr #31 + 3b40: f340 054f sbfx r5, r0, #1, #16 + lv_coord_t hhalf = lv_obj_get_width(obj) / 2; + 3b44: 4620 mov r0, r4 + 3b46: 47d0 blx sl + if(int1 == LV_RADIUS_CIRCLE) int1 = LV_MATH_MIN(whalf + 1, hhalf + 1); + 3b48: f647 73ff movw r3, #32767 ; 0x7fff + lv_coord_t hhalf = lv_obj_get_width(obj) / 2; + 3b4c: eb00 70d0 add.w r0, r0, r0, lsr #31 + if(int1 == LV_RADIUS_CIRCLE) int1 = LV_MATH_MIN(whalf + 1, hhalf + 1); + 3b50: 459b cmp fp, r3 + lv_coord_t hhalf = lv_obj_get_width(obj) / 2; + 3b52: f340 004f sbfx r0, r0, #1, #16 + if(int1 == LV_RADIUS_CIRCLE) int1 = LV_MATH_MIN(whalf + 1, hhalf + 1); + 3b56: d12a bne.n 3bae + 3b58: 4285 cmp r5, r0 + 3b5a: da1e bge.n 3b9a + 3b5c: f105 0b01 add.w fp, r5, #1 + if(int2 == LV_RADIUS_CIRCLE) int2 = LV_MATH_MIN(whalf + 1, hhalf + 1); + 3b60: 4599 cmp r9, r3 + if(int1 == LV_RADIUS_CIRCLE) int1 = LV_MATH_MIN(whalf + 1, hhalf + 1); + 3b62: fa0f fb8b sxth.w fp, fp + if(int2 == LV_RADIUS_CIRCLE) int2 = LV_MATH_MIN(whalf + 1, hhalf + 1); + 3b66: d102 bne.n 3b6e + 3b68: 3501 adds r5, #1 + 3b6a: fa0f f985 sxth.w r9, r5 + tr = _lv_ll_ins_head(&LV_GC_ROOT(_lv_obj_style_trans_ll)); + 3b6e: 4b3b ldr r3, [pc, #236] ; (3c5c ) + 3b70: 483b ldr r0, [pc, #236] ; (3c60 ) + 3b72: 4798 blx r3 + LV_ASSERT_MEM(tr); + 3b74: 4b2c ldr r3, [pc, #176] ; (3c28 ) + tr = _lv_ll_ins_head(&LV_GC_ROOT(_lv_obj_style_trans_ll)); + 3b76: 4605 mov r5, r0 + LV_ASSERT_MEM(tr); + 3b78: 4798 blx r3 + 3b7a: 4682 mov sl, r0 + 3b7c: b9e0 cbnz r0, 3bb8 + 3b7e: 4b39 ldr r3, [pc, #228] ; (3c64 ) + 3b80: 492b ldr r1, [pc, #172] ; (3c30 ) + 3b82: 9300 str r3, [sp, #0] + 3b84: f640 62b2 movw r2, #3762 ; 0xeb2 + 3b88: 2003 movs r0, #3 + 3b8a: 4c2a ldr r4, [pc, #168] ; (3c34 ) + 3b8c: 47a0 blx r4 + 3b8e: 4836 ldr r0, [pc, #216] ; (3c68 ) + 3b90: 492a ldr r1, [pc, #168] ; (3c3c ) + 3b92: 462a mov r2, r5 + 3b94: 4653 mov r3, sl + 3b96: 4788 blx r1 + 3b98: e7fe b.n 3b98 + if(int1 == LV_RADIUS_CIRCLE) int1 = LV_MATH_MIN(whalf + 1, hhalf + 1); + 3b9a: f100 0b01 add.w fp, r0, #1 + if(int2 == LV_RADIUS_CIRCLE) int2 = LV_MATH_MIN(whalf + 1, hhalf + 1); + 3b9e: 4599 cmp r9, r3 + if(int1 == LV_RADIUS_CIRCLE) int1 = LV_MATH_MIN(whalf + 1, hhalf + 1); + 3ba0: fa0f fb8b sxth.w fp, fp + if(int2 == LV_RADIUS_CIRCLE) int2 = LV_MATH_MIN(whalf + 1, hhalf + 1); + 3ba4: d1e3 bne.n 3b6e + 3ba6: 3001 adds r0, #1 + 3ba8: fa0f f980 sxth.w r9, r0 + 3bac: e7df b.n 3b6e + 3bae: 4599 cmp r9, r3 + 3bb0: d1dd bne.n 3b6e + 3bb2: 4285 cmp r5, r0 + 3bb4: daf7 bge.n 3ba6 + 3bb6: e7d7 b.n 3b68 + if(tr == NULL) return NULL; + 3bb8: 2d00 cmp r5, #0 + 3bba: d02d beq.n 3c18 + tr->start_value._int = int1; + 3bbc: f8a5 b008 strh.w fp, [r5, #8] + tr->end_value._int = int2; + 3bc0: f8a5 900c strh.w r9, [r5, #12] + lv_anim_init(&a); + 3bc4: 4b29 ldr r3, [pc, #164] ; (3c6c ) + tr->obj = obj; + 3bc6: 602c str r4, [r5, #0] + tr->prop = props[i]; + 3bc8: 80af strh r7, [r5, #4] + tr->part = part; + 3bca: 71ae strb r6, [r5, #6] + lv_anim_init(&a); + 3bcc: a80e add r0, sp, #56 ; 0x38 + 3bce: 4798 blx r3 + * LittelvGL's built-in functions can be used. + * E.g. lv_obj_set_x + */ +static inline void lv_anim_set_exec_cb(lv_anim_t * a, lv_anim_exec_xcb_t exec_cb) +{ + a->exec_cb = exec_cb; + 3bd0: 4b27 ldr r3, [pc, #156] ; (3c70 ) + 3bd2: 930f str r3, [sp, #60] ; 0x3c + * @param a pointer to an initialized `lv_anim_t` variable + * @param start_cb a function call when the animation starts + */ +static inline void lv_anim_set_start_cb(lv_anim_t * a, lv_anim_ready_cb_t start_cb) +{ + a->start_cb = start_cb; + 3bd4: 4b27 ldr r3, [pc, #156] ; (3c74 ) + 3bd6: 9310 str r3, [sp, #64] ; 0x40 + * @param a pointer to an initialized `lv_anim_t` variable + * @param ready_cb a function call when the animation is ready + */ +static inline void lv_anim_set_ready_cb(lv_anim_t * a, lv_anim_ready_cb_t ready_cb) +{ + a->ready_cb = ready_cb; + 3bd8: 4b27 ldr r3, [pc, #156] ; (3c78 ) + 3bda: 9311 str r3, [sp, #68] ; 0x44 + a->end = end; + 3bdc: 2200 movs r2, #0 + 3bde: 23ff movs r3, #255 ; 0xff + 3be0: e9cd 2314 strd r2, r3, [sp, #80] ; 0x50 + a->time = duration; + 3be4: 9b09 ldr r3, [sp, #36] ; 0x24 + 3be6: 9316 str r3, [sp, #88] ; 0x58 + a->act_time = (int32_t)(-delay); + 3be8: 9b08 ldr r3, [sp, #32] + 3bea: 9a06 ldr r2, [sp, #24] + a->var = var; + 3bec: 950e str r5, [sp, #56] ; 0x38 + a->act_time = (int32_t)(-delay); + 3bee: 425b negs r3, r3 + 3bf0: 9317 str r3, [sp, #92] ; 0x5c + 3bf2: 9b06 ldr r3, [sp, #24] + 3bf4: 1dd1 adds r1, r2, #7 + 3bf6: 3b01 subs r3, #1 + uint8_t * d8 = (uint8_t *)dst; + 3bf8: aa12 add r2, sp, #72 ; 0x48 + *d8 = *s8; + 3bfa: f813 0f01 ldrb.w r0, [r3, #1]! + 3bfe: f802 0b01 strb.w r0, [r2], #1 + while(len) { + 3c02: 4299 cmp r1, r3 + 3c04: d1f9 bne.n 3bfa + a.early_apply = 0; + 3c06: f89d 306e ldrb.w r3, [sp, #110] ; 0x6e + 3c0a: f36f 0300 bfc r3, #0, #1 + 3c0e: f88d 306e strb.w r3, [sp, #110] ; 0x6e + lv_anim_start(&a); + 3c12: a80e add r0, sp, #56 ; 0x38 + 3c14: 4b19 ldr r3, [pc, #100] ; (3c7c ) + 3c16: 4798 blx r3 + for(i = 0; i < LV_STYLE_TRANS_NUM_MAX; i++) { + 3c18: 9b04 ldr r3, [sp, #16] + 3c1a: 3301 adds r3, #1 + 3c1c: 2b06 cmp r3, #6 + 3c1e: 9304 str r3, [sp, #16] + 3c20: f47f af3d bne.w 3a9e + 3c24: e6f9 b.n 3a1a + 3c26: bf00 nop + 3c28: 000017e1 .word 0x000017e1 + 3c2c: 0001f666 .word 0x0001f666 + 3c30: 0001ee5b .word 0x0001ee5b + 3c34: 0000e8e9 .word 0x0000e8e9 + 3c38: 0001eebf .word 0x0001eebf + 3c3c: 000017e9 .word 0x000017e9 + 3c40: 0000248d .word 0x0000248d + 3c44: 00002d91 .word 0x00002d91 + 3c48: 00003711 .word 0x00003711 + 3c4c: 000038c9 .word 0x000038c9 + 3c50: 00005de1 .word 0x00005de1 + 3c54: 00005cb9 .word 0x00005cb9 + 3c58: 00005879 .word 0x00005879 + 3c5c: 0000e619 .word 0x0000e619 + 3c60: 20008660 .word 0x20008660 + 3c64: 0001f677 .word 0x0001f677 + 3c68: 0001edbe .word 0x0001edbe + 3c6c: 0000dc79 .word 0x0000dc79 + 3c70: 00002f8d .word 0x00002f8d + 3c74: 0000395d .word 0x0000395d + 3c78: 000025a1 .word 0x000025a1 + 3c7c: 0000dd21 .word 0x0000dd21 + 3c80: 000023ed .word 0x000023ed + else if((prop & 0xF) < LV_STYLE_ID_OPA) { /*Color*/ + 3c84: 2b0b cmp r3, #11 + 3c86: d84b bhi.n 3d20 + style_list->skip_trans = 1; + 3c88: 796b ldrb r3, [r5, #5] + lv_color_t c1 = _lv_obj_get_style_color(obj, part, prop); + 3c8a: f8df b200 ldr.w fp, [pc, #512] ; 3e8c + style_list->skip_trans = 1; + 3c8e: f043 0304 orr.w r3, r3, #4 + 3c92: 716b strb r3, [r5, #5] + obj->state = prev_state; + 3c94: 9b02 ldr r3, [sp, #8] + 3c96: f884 303d strb.w r3, [r4, #61] ; 0x3d + lv_color_t c1 = _lv_obj_get_style_color(obj, part, prop); + 3c9a: 463a mov r2, r7 + 3c9c: 4631 mov r1, r6 + 3c9e: 4620 mov r0, r4 + 3ca0: 47d8 blx fp + lv_color_t c2 = _lv_obj_get_style_color(obj, part, prop); + 3ca2: 463a mov r2, r7 + lv_color_t c1 = _lv_obj_get_style_color(obj, part, prop); + 3ca4: 4681 mov r9, r0 + obj->state = new_state; + 3ca6: f884 803d strb.w r8, [r4, #61] ; 0x3d + lv_color_t c2 = _lv_obj_get_style_color(obj, part, prop); + 3caa: 4631 mov r1, r6 + 3cac: 4620 mov r0, r4 + 3cae: 47d8 blx fp + style_list->skip_trans = 0; + 3cb0: 796a ldrb r2, [r5, #5] + lv_color_t c2 = _lv_obj_get_style_color(obj, part, prop); + 3cb2: f8ad 001c strh.w r0, [sp, #28] + style_list->skip_trans = 0; + 3cb6: f36f 0282 bfc r2, #2, #1 + 3cba: 716a strb r2, [r5, #5] + if(c1.full == c2.full) return NULL; + 3cbc: fa1f f989 uxth.w r9, r9 + 3cc0: b282 uxth r2, r0 + 3cc2: 4591 cmp r9, r2 + 3cc4: d0a8 beq.n 3c18 + obj->state = prev_state; + 3cc6: 9b02 ldr r3, [sp, #8] + 3cc8: f884 303d strb.w r3, [r4, #61] ; 0x3d + c1 = _lv_obj_get_style_color(obj, part, prop); + 3ccc: 463a mov r2, r7 + 3cce: 4631 mov r1, r6 + 3cd0: 4620 mov r0, r4 + 3cd2: 47d8 blx fp + _lv_style_set_color(style_trans, prop, c1); /*Be sure `trans_style` has a valid value */ + 3cd4: 4639 mov r1, r7 + 3cd6: 4602 mov r2, r0 + 3cd8: 4b60 ldr r3, [pc, #384] ; (3e5c ) + obj->state = new_state; + 3cda: f884 803d strb.w r8, [r4, #61] ; 0x3d + c1 = _lv_obj_get_style_color(obj, part, prop); + 3cde: 4681 mov r9, r0 + _lv_style_set_color(style_trans, prop, c1); /*Be sure `trans_style` has a valid value */ + 3ce0: 4650 mov r0, sl + 3ce2: 4798 blx r3 + tr = _lv_ll_ins_head(&LV_GC_ROOT(_lv_obj_style_trans_ll)); + 3ce4: 4b5e ldr r3, [pc, #376] ; (3e60 ) + 3ce6: 485f ldr r0, [pc, #380] ; (3e64 ) + 3ce8: 4798 blx r3 + LV_ASSERT_MEM(tr); + 3cea: 4b5f ldr r3, [pc, #380] ; (3e68 ) + tr = _lv_ll_ins_head(&LV_GC_ROOT(_lv_obj_style_trans_ll)); + 3cec: 4605 mov r5, r0 + LV_ASSERT_MEM(tr); + 3cee: 4798 blx r3 + 3cf0: 4682 mov sl, r0 + 3cf2: b968 cbnz r0, 3d10 + 3cf4: 4b5d ldr r3, [pc, #372] ; (3e6c ) + 3cf6: 495e ldr r1, [pc, #376] ; (3e70 ) + 3cf8: 9300 str r3, [sp, #0] + 3cfa: f640 62c6 movw r2, #3782 ; 0xec6 + 3cfe: 2003 movs r0, #3 + 3d00: 4c5c ldr r4, [pc, #368] ; (3e74 ) + 3d02: 47a0 blx r4 + 3d04: 485c ldr r0, [pc, #368] ; (3e78 ) + 3d06: 495d ldr r1, [pc, #372] ; (3e7c ) + 3d08: 462a mov r2, r5 + 3d0a: 4653 mov r3, sl + 3d0c: 4788 blx r1 + 3d0e: e7fe b.n 3d0e + if(tr == NULL) return NULL; + 3d10: 2d00 cmp r5, #0 + 3d12: d081 beq.n 3c18 + tr->end_value._color = c2; + 3d14: f8bd 301c ldrh.w r3, [sp, #28] + tr->start_value._color = c1; + 3d18: f8a5 9008 strh.w r9, [r5, #8] + tr->end_value._color = c2; + 3d1c: 81ab strh r3, [r5, #12] + 3d1e: e751 b.n 3bc4 + else if((prop & 0xF) < LV_STYLE_ID_PTR) { /*Opa*/ + 3d20: 2b0d cmp r3, #13 + 3d22: d849 bhi.n 3db8 + style_list->skip_trans = 1; + 3d24: 796b ldrb r3, [r5, #5] + lv_opa_t o1 = _lv_obj_get_style_opa(obj, part, prop); + 3d26: f8df b168 ldr.w fp, [pc, #360] ; 3e90 + style_list->skip_trans = 1; + 3d2a: f043 0304 orr.w r3, r3, #4 + 3d2e: 716b strb r3, [r5, #5] + obj->state = prev_state; + 3d30: 9b02 ldr r3, [sp, #8] + 3d32: f884 303d strb.w r3, [r4, #61] ; 0x3d + lv_opa_t o1 = _lv_obj_get_style_opa(obj, part, prop); + 3d36: 463a mov r2, r7 + 3d38: 4631 mov r1, r6 + 3d3a: 4620 mov r0, r4 + 3d3c: 47d8 blx fp + lv_opa_t o2 = _lv_obj_get_style_opa(obj, part, prop); + 3d3e: 463a mov r2, r7 + lv_opa_t o1 = _lv_obj_get_style_opa(obj, part, prop); + 3d40: 9007 str r0, [sp, #28] + obj->state = new_state; + 3d42: f884 803d strb.w r8, [r4, #61] ; 0x3d + lv_opa_t o2 = _lv_obj_get_style_opa(obj, part, prop); + 3d46: 4631 mov r1, r6 + 3d48: 4620 mov r0, r4 + 3d4a: 47d8 blx fp + style_list->skip_trans = 0; + 3d4c: 796a ldrb r2, [r5, #5] + if(o1 == o2) return NULL; + 3d4e: 9b07 ldr r3, [sp, #28] + style_list->skip_trans = 0; + 3d50: f36f 0282 bfc r2, #2, #1 + if(o1 == o2) return NULL; + 3d54: 4283 cmp r3, r0 + lv_opa_t o2 = _lv_obj_get_style_opa(obj, part, prop); + 3d56: 4681 mov r9, r0 + style_list->skip_trans = 0; + 3d58: 716a strb r2, [r5, #5] + if(o1 == o2) return NULL; + 3d5a: f43f af5d beq.w 3c18 + obj->state = prev_state; + 3d5e: 9b02 ldr r3, [sp, #8] + 3d60: f884 303d strb.w r3, [r4, #61] ; 0x3d + o1 = _lv_obj_get_style_opa(obj, part, prop); + 3d64: 463a mov r2, r7 + 3d66: 4631 mov r1, r6 + 3d68: 4620 mov r0, r4 + 3d6a: 47d8 blx fp + _lv_style_set_opa(style_trans, prop, o1); /*Be sure `trans_style` has a valid value */ + 3d6c: 4639 mov r1, r7 + 3d6e: 4602 mov r2, r0 + 3d70: 4b43 ldr r3, [pc, #268] ; (3e80 ) + obj->state = new_state; + 3d72: f884 803d strb.w r8, [r4, #61] ; 0x3d + o1 = _lv_obj_get_style_opa(obj, part, prop); + 3d76: 4683 mov fp, r0 + _lv_style_set_opa(style_trans, prop, o1); /*Be sure `trans_style` has a valid value */ + 3d78: 4650 mov r0, sl + 3d7a: 4798 blx r3 + tr = _lv_ll_ins_head(&LV_GC_ROOT(_lv_obj_style_trans_ll)); + 3d7c: 4b38 ldr r3, [pc, #224] ; (3e60 ) + 3d7e: 4839 ldr r0, [pc, #228] ; (3e64 ) + 3d80: 4798 blx r3 + LV_ASSERT_MEM(tr); + 3d82: 4b39 ldr r3, [pc, #228] ; (3e68 ) + tr = _lv_ll_ins_head(&LV_GC_ROOT(_lv_obj_style_trans_ll)); + 3d84: 4605 mov r5, r0 + LV_ASSERT_MEM(tr); + 3d86: 4798 blx r3 + 3d88: 4682 mov sl, r0 + 3d8a: b968 cbnz r0, 3da8 + 3d8c: 4b37 ldr r3, [pc, #220] ; (3e6c ) + 3d8e: 4938 ldr r1, [pc, #224] ; (3e70 ) + 3d90: 9300 str r3, [sp, #0] + 3d92: f640 62db movw r2, #3803 ; 0xedb + 3d96: 2003 movs r0, #3 + 3d98: 4c36 ldr r4, [pc, #216] ; (3e74 ) + 3d9a: 47a0 blx r4 + 3d9c: 4836 ldr r0, [pc, #216] ; (3e78 ) + 3d9e: 4937 ldr r1, [pc, #220] ; (3e7c ) + 3da0: 462a mov r2, r5 + 3da2: 4653 mov r3, sl + 3da4: 4788 blx r1 + 3da6: e7fe b.n 3da6 + if(tr == NULL) return NULL; + 3da8: 2d00 cmp r5, #0 + 3daa: f43f af35 beq.w 3c18 + tr->start_value._opa = o1; + 3dae: f885 b008 strb.w fp, [r5, #8] + tr->end_value._opa = o2; + 3db2: f885 900c strb.w r9, [r5, #12] + 3db6: e705 b.n 3bc4 + obj->state = prev_state; + 3db8: 9b02 ldr r3, [sp, #8] + 3dba: f884 303d strb.w r3, [r4, #61] ; 0x3d + style_list->skip_trans = 1; + 3dbe: 796b ldrb r3, [r5, #5] + const void * p1 = _lv_obj_get_style_ptr(obj, part, prop); + 3dc0: f8df b0d0 ldr.w fp, [pc, #208] ; 3e94 + style_list->skip_trans = 1; + 3dc4: f043 0304 orr.w r3, r3, #4 + 3dc8: 716b strb r3, [r5, #5] + const void * p1 = _lv_obj_get_style_ptr(obj, part, prop); + 3dca: 463a mov r2, r7 + 3dcc: 4631 mov r1, r6 + 3dce: 4620 mov r0, r4 + 3dd0: 47d8 blx fp + const void * p2 = _lv_obj_get_style_ptr(obj, part, prop); + 3dd2: 463a mov r2, r7 + const void * p1 = _lv_obj_get_style_ptr(obj, part, prop); + 3dd4: 900a str r0, [sp, #40] ; 0x28 + const void * p2 = _lv_obj_get_style_ptr(obj, part, prop); + 3dd6: 4631 mov r1, r6 + obj->state = new_state; + 3dd8: f884 803d strb.w r8, [r4, #61] ; 0x3d + const void * p2 = _lv_obj_get_style_ptr(obj, part, prop); + 3ddc: 4620 mov r0, r4 + 3dde: 47d8 blx fp + 3de0: 900e str r0, [sp, #56] ; 0x38 + style_list->skip_trans = 0; + 3de2: 796b ldrb r3, [r5, #5] + 3de4: f36f 0382 bfc r3, #2, #1 + const void * p2 = _lv_obj_get_style_ptr(obj, part, prop); + 3de8: 4681 mov r9, r0 + style_list->skip_trans = 0; + 3dea: 716b strb r3, [r5, #5] + if(memcmp(&p1, &p2, sizeof(const void *)) == 0) return NULL; + 3dec: 2204 movs r2, #4 + 3dee: 4b25 ldr r3, [pc, #148] ; (3e84 ) + 3df0: a90e add r1, sp, #56 ; 0x38 + 3df2: a80a add r0, sp, #40 ; 0x28 + 3df4: 4798 blx r3 + 3df6: 2800 cmp r0, #0 + 3df8: f43f af0e beq.w 3c18 + obj->state = prev_state; + 3dfc: 9b02 ldr r3, [sp, #8] + 3dfe: f884 303d strb.w r3, [r4, #61] ; 0x3d + p1 = _lv_obj_get_style_ptr(obj, part, prop); + 3e02: 463a mov r2, r7 + 3e04: 4631 mov r1, r6 + 3e06: 4620 mov r0, r4 + 3e08: 47d8 blx fp + _lv_style_set_ptr(style_trans, prop, p1); /*Be sure `trans_style` has a valid value */ + 3e0a: 4639 mov r1, r7 + 3e0c: 4602 mov r2, r0 + 3e0e: 4b1e ldr r3, [pc, #120] ; (3e88 ) + p1 = _lv_obj_get_style_ptr(obj, part, prop); + 3e10: 900a str r0, [sp, #40] ; 0x28 + 3e12: 4683 mov fp, r0 + obj->state = new_state; + 3e14: f884 803d strb.w r8, [r4, #61] ; 0x3d + _lv_style_set_ptr(style_trans, prop, p1); /*Be sure `trans_style` has a valid value */ + 3e18: 4650 mov r0, sl + 3e1a: 4798 blx r3 + tr = _lv_ll_ins_head(&LV_GC_ROOT(_lv_obj_style_trans_ll)); + 3e1c: 4b10 ldr r3, [pc, #64] ; (3e60 ) + 3e1e: 4811 ldr r0, [pc, #68] ; (3e64 ) + 3e20: 4798 blx r3 + LV_ASSERT_MEM(tr); + 3e22: 4b11 ldr r3, [pc, #68] ; (3e68 ) + tr = _lv_ll_ins_head(&LV_GC_ROOT(_lv_obj_style_trans_ll)); + 3e24: 4605 mov r5, r0 + LV_ASSERT_MEM(tr); + 3e26: 4798 blx r3 + 3e28: 4682 mov sl, r0 + 3e2a: b968 cbnz r0, 3e48 + 3e2c: 4b0f ldr r3, [pc, #60] ; (3e6c ) + 3e2e: 4910 ldr r1, [pc, #64] ; (3e70 ) + 3e30: 9300 str r3, [sp, #0] + 3e32: f640 62ef movw r2, #3823 ; 0xeef + 3e36: 2003 movs r0, #3 + 3e38: 4c0e ldr r4, [pc, #56] ; (3e74 ) + 3e3a: 47a0 blx r4 + 3e3c: 480e ldr r0, [pc, #56] ; (3e78 ) + 3e3e: 490f ldr r1, [pc, #60] ; (3e7c ) + 3e40: 462a mov r2, r5 + 3e42: 4653 mov r3, sl + 3e44: 4788 blx r1 + 3e46: e7fe b.n 3e46 + if(tr == NULL) return NULL; + 3e48: 2d00 cmp r5, #0 + 3e4a: f43f aee5 beq.w 3c18 + tr->end_value._ptr = p2; + 3e4e: e9c5 b902 strd fp, r9, [r5, #8] + 3e52: e6b7 b.n 3bc4 +} + 3e54: b01f add sp, #124 ; 0x7c + 3e56: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 3e5a: bf00 nop + 3e5c: 00005949 .word 0x00005949 + 3e60: 0000e619 .word 0x0000e619 + 3e64: 20008660 .word 0x20008660 + 3e68: 000017e1 .word 0x000017e1 + 3e6c: 0001f677 .word 0x0001f677 + 3e70: 0001ee5b .word 0x0001ee5b + 3e74: 0000e8e9 .word 0x0000e8e9 + 3e78: 0001edbe .word 0x0001edbe + 3e7c: 000017e9 .word 0x000017e9 + 3e80: 00005a19 .word 0x00005a19 + 3e84: 00016295 .word 0x00016295 + 3e88: 00005aed .word 0x00005aed + 3e8c: 000037b5 .word 0x000037b5 + 3e90: 00003839 .word 0x00003839 + 3e94: 000038c9 .word 0x000038c9 + +00003e98 : +{ + 3e98: b573 push {r0, r1, r4, r5, r6, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 3e9a: 4b11 ldr r3, [pc, #68] ; (3ee0 ) +{ + 3e9c: 4604 mov r4, r0 + 3e9e: 460d mov r5, r1 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 3ea0: 4798 blx r3 + 3ea2: 4606 mov r6, r0 + 3ea4: b968 cbnz r0, 3ec2 + 3ea6: 4b0f ldr r3, [pc, #60] ; (3ee4 ) + 3ea8: 490f ldr r1, [pc, #60] ; (3ee8 ) + 3eaa: 9300 str r3, [sp, #0] + 3eac: f240 627e movw r2, #1662 ; 0x67e + 3eb0: 2003 movs r0, #3 + 3eb2: 4d0e ldr r5, [pc, #56] ; (3eec ) + 3eb4: 47a8 blx r5 + 3eb6: 480e ldr r0, [pc, #56] ; (3ef0 ) + 3eb8: 490e ldr r1, [pc, #56] ; (3ef4 ) + 3eba: 4622 mov r2, r4 + 3ebc: 4633 mov r3, r6 + 3ebe: 4788 blx r1 + 3ec0: e7fe b.n 3ec0 + lv_state_t new_state = obj->state | state; + 3ec2: f894 303d ldrb.w r3, [r4, #61] ; 0x3d + 3ec6: ea43 0105 orr.w r1, r3, r5 + if(obj->state != new_state) { + 3eca: 439d bics r5, r3 + 3ecc: d005 beq.n 3eda + lv_obj_set_state(obj, new_state); + 3ece: 4b0a ldr r3, [pc, #40] ; (3ef8 ) + 3ed0: 4620 mov r0, r4 +} + 3ed2: b002 add sp, #8 + 3ed4: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + lv_obj_set_state(obj, new_state); + 3ed8: 4718 bx r3 +} + 3eda: b002 add sp, #8 + 3edc: bd70 pop {r4, r5, r6, pc} + 3ede: bf00 nop + 3ee0: 000017e1 .word 0x000017e1 + 3ee4: 0001f684 .word 0x0001f684 + 3ee8: 0001ee5b .word 0x0001ee5b + 3eec: 0000e8e9 .word 0x0000e8e9 + 3ef0: 0001eebf .word 0x0001eebf + 3ef4: 000017e9 .word 0x000017e9 + 3ef8: 000039bd .word 0x000039bd + +00003efc : +{ + 3efc: b573 push {r0, r1, r4, r5, r6, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 3efe: 4b11 ldr r3, [pc, #68] ; (3f44 ) +{ + 3f00: 4604 mov r4, r0 + 3f02: 460d mov r5, r1 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 3f04: 4798 blx r3 + 3f06: 4606 mov r6, r0 + 3f08: b968 cbnz r0, 3f26 + 3f0a: 4b0f ldr r3, [pc, #60] ; (3f48 ) + 3f0c: 490f ldr r1, [pc, #60] ; (3f4c ) + 3f0e: 9300 str r3, [sp, #0] + 3f10: f240 628f movw r2, #1679 ; 0x68f + 3f14: 2003 movs r0, #3 + 3f16: 4d0e ldr r5, [pc, #56] ; (3f50 ) + 3f18: 47a8 blx r5 + 3f1a: 480e ldr r0, [pc, #56] ; (3f54 ) + 3f1c: 490e ldr r1, [pc, #56] ; (3f58 ) + 3f1e: 4622 mov r2, r4 + 3f20: 4633 mov r3, r6 + 3f22: 4788 blx r1 + 3f24: e7fe b.n 3f24 + lv_state_t new_state = obj->state & (~state); + 3f26: f894 303d ldrb.w r3, [r4, #61] ; 0x3d + if(obj->state != new_state) { + 3f2a: 421d tst r5, r3 + lv_state_t new_state = obj->state & (~state); + 3f2c: ea23 0105 bic.w r1, r3, r5 + if(obj->state != new_state) { + 3f30: d005 beq.n 3f3e + lv_obj_set_state(obj, new_state); + 3f32: 4b0a ldr r3, [pc, #40] ; (3f5c ) + 3f34: 4620 mov r0, r4 +} + 3f36: b002 add sp, #8 + 3f38: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + lv_obj_set_state(obj, new_state); + 3f3c: 4718 bx r3 +} + 3f3e: b002 add sp, #8 + 3f40: bd70 pop {r4, r5, r6, pc} + 3f42: bf00 nop + 3f44: 000017e1 .word 0x000017e1 + 3f48: 0001f695 .word 0x0001f695 + 3f4c: 0001ee5b .word 0x0001ee5b + 3f50: 0000e8e9 .word 0x0000e8e9 + 3f54: 0001eebf .word 0x0001eebf + 3f58: 000017e9 .word 0x000017e9 + 3f5c: 000039bd .word 0x000039bd + +00003f60 : +{ + 3f60: b573 push {r0, r1, r4, r5, r6, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 3f62: 4b0b ldr r3, [pc, #44] ; (3f90 ) +{ + 3f64: 4604 mov r4, r0 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 3f66: 4798 blx r3 + 3f68: 4605 mov r5, r0 + 3f6a: b968 cbnz r0, 3f88 + 3f6c: 4b09 ldr r3, [pc, #36] ; (3f94 ) + 3f6e: 490a ldr r1, [pc, #40] ; (3f98 ) + 3f70: 9300 str r3, [sp, #0] + 3f72: f640 22f5 movw r2, #2805 ; 0xaf5 + 3f76: 2003 movs r0, #3 + 3f78: 4e08 ldr r6, [pc, #32] ; (3f9c ) + 3f7a: 47b0 blx r6 + 3f7c: 4808 ldr r0, [pc, #32] ; (3fa0 ) + 3f7e: 4909 ldr r1, [pc, #36] ; (3fa4 ) + 3f80: 4622 mov r2, r4 + 3f82: 462b mov r3, r5 + 3f84: 4788 blx r1 + 3f86: e7fe b.n 3f86 +} + 3f88: 69e0 ldr r0, [r4, #28] + 3f8a: b002 add sp, #8 + 3f8c: bd70 pop {r4, r5, r6, pc} + 3f8e: bf00 nop + 3f90: 000017e1 .word 0x000017e1 + 3f94: 0001f6a8 .word 0x0001f6a8 + 3f98: 0001ee5b .word 0x0001ee5b + 3f9c: 0000e8e9 .word 0x0000e8e9 + 3fa0: 0001eebf .word 0x0001eebf + 3fa4: 000017e9 .word 0x000017e9 + +00003fa8 : +{ + 3fa8: b573 push {r0, r1, r4, r5, r6, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 3faa: 4b0b ldr r3, [pc, #44] ; (3fd8 ) +{ + 3fac: 4604 mov r4, r0 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 3fae: 4798 blx r3 + 3fb0: 4605 mov r5, r0 + 3fb2: b968 cbnz r0, 3fd0 + 3fb4: 4b09 ldr r3, [pc, #36] ; (3fdc ) + 3fb6: 490a ldr r1, [pc, #40] ; (3fe0 ) + 3fb8: 9300 str r3, [sp, #0] + 3fba: f640 321e movw r2, #2846 ; 0xb1e + 3fbe: 2003 movs r0, #3 + 3fc0: 4e08 ldr r6, [pc, #32] ; (3fe4 ) + 3fc2: 47b0 blx r6 + 3fc4: 4808 ldr r0, [pc, #32] ; (3fe8 ) + 3fc6: 4909 ldr r1, [pc, #36] ; (3fec ) + 3fc8: 4622 mov r2, r4 + 3fca: 462b mov r3, r5 + 3fcc: 4788 blx r1 + 3fce: e7fe b.n 3fce +} + 3fd0: 6a60 ldr r0, [r4, #36] ; 0x24 + 3fd2: b002 add sp, #8 + 3fd4: bd70 pop {r4, r5, r6, pc} + 3fd6: bf00 nop + 3fd8: 000017e1 .word 0x000017e1 + 3fdc: 0001f6e6 .word 0x0001f6e6 + 3fe0: 0001ee5b .word 0x0001ee5b + 3fe4: 0000e8e9 .word 0x0000e8e9 + 3fe8: 0001eebf .word 0x0001eebf + 3fec: 000017e9 .word 0x000017e9 + +00003ff0 : +{ + 3ff0: b573 push {r0, r1, r4, r5, r6, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 3ff2: 4b0b ldr r3, [pc, #44] ; (4020 ) +{ + 3ff4: 4604 mov r4, r0 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 3ff6: 4798 blx r3 + 3ff8: 4605 mov r5, r0 + 3ffa: b968 cbnz r0, 4018 + 3ffc: 4b09 ldr r3, [pc, #36] ; (4024 ) + 3ffe: 490a ldr r1, [pc, #40] ; (4028 ) + 4000: 9300 str r3, [sp, #0] + 4002: f640 326f movw r2, #2927 ; 0xb6f + 4006: 2003 movs r0, #3 + 4008: 4e08 ldr r6, [pc, #32] ; (402c ) + 400a: 47b0 blx r6 + 400c: 4808 ldr r0, [pc, #32] ; (4030 ) + 400e: 4909 ldr r1, [pc, #36] ; (4034 ) + 4010: 4622 mov r2, r4 + 4012: 462b mov r3, r5 + 4014: 4788 blx r1 + 4016: e7fe b.n 4016 +} + 4018: 6ba0 ldr r0, [r4, #56] ; 0x38 + 401a: b002 add sp, #8 + 401c: bd70 pop {r4, r5, r6, pc} + 401e: bf00 nop + 4020: 000017e1 .word 0x000017e1 + 4024: 0001f70a .word 0x0001f70a + 4028: 0001ee5b .word 0x0001ee5b + 402c: 0000e8e9 .word 0x0000e8e9 + 4030: 0001eebf .word 0x0001eebf + 4034: 000017e9 .word 0x000017e9 + +00004038 : +{ + 4038: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + lv_event_send(obj, LV_EVENT_DELETE, NULL); + 403c: 4b39 ldr r3, [pc, #228] ; (4124 ) +{ + 403e: 4604 mov r4, r0 + lv_event_send(obj, LV_EVENT_DELETE, NULL); + 4040: 2200 movs r2, #0 + 4042: 2115 movs r1, #21 + 4044: 4798 blx r3 + lv_group_t * group = lv_obj_get_group(obj); + 4046: 4b38 ldr r3, [pc, #224] ; (4128 ) + 4048: 4620 mov r0, r4 + 404a: 4798 blx r3 + if(group) lv_group_remove_obj(obj); + 404c: 4607 mov r7, r0 + 404e: b110 cbz r0, 4056 + 4050: 4b36 ldr r3, [pc, #216] ; (412c ) + 4052: 4620 mov r0, r4 + 4054: 4798 blx r3 + lv_anim_del(obj, NULL); + 4056: 4b36 ldr r3, [pc, #216] ; (4130 ) + trans_del(obj, 0xFF, 0xFF, NULL); + 4058: 4d36 ldr r5, [pc, #216] ; (4134 ) + i_next = _lv_ll_get_next(&(obj->child_ll), i); + 405a: f8df 90f4 ldr.w r9, [pc, #244] ; 4150 + lv_anim_del(obj, NULL); + 405e: 2100 movs r1, #0 + 4060: 4620 mov r0, r4 + 4062: 4798 blx r3 + trans_del(obj, 0xFF, 0xFF, NULL); + 4064: 22ff movs r2, #255 ; 0xff + 4066: 2300 movs r3, #0 + 4068: 4611 mov r1, r2 + 406a: 4620 mov r0, r4 + i = _lv_ll_get_head(&(obj->child_ll)); + 406c: f104 0804 add.w r8, r4, #4 + trans_del(obj, 0xFF, 0xFF, NULL); + 4070: 47a8 blx r5 + i = _lv_ll_get_head(&(obj->child_ll)); + 4072: 4b31 ldr r3, [pc, #196] ; (4138 ) + 4074: 4640 mov r0, r8 + 4076: 4798 blx r3 + 4078: 4605 mov r5, r0 + while(i != NULL) { + 407a: bb3d cbnz r5, 40cc + +#endif + +static void lv_event_mark_deleted(lv_obj_t * obj) +{ + lv_event_temp_data_t * t = event_temp_data_head; + 407c: 4b2f ldr r3, [pc, #188] ; (413c ) + 407e: 685e ldr r6, [r3, #4] + + while(t) { + if(t->obj == obj) t->deleted = true; + 4080: 2301 movs r3, #1 + while(t) { + 4082: bb66 cbnz r6, 40de + lv_indev_t * indev = lv_indev_get_next(NULL); + 4084: f8df 80cc ldr.w r8, [pc, #204] ; 4154 + lv_indev_reset(indev, obj); + 4088: f8df 90cc ldr.w r9, [pc, #204] ; 4158 + if(indev->group == group && obj == lv_indev_get_obj_act()) { + 408c: f8df a0cc ldr.w sl, [pc, #204] ; 415c + lv_indev_t * indev = lv_indev_get_next(NULL); + 4090: 4630 mov r0, r6 + 4092: 47c0 blx r8 + 4094: 4605 mov r5, r0 + while(indev) { + 4096: bb45 cbnz r5, 40ea + obj->signal_cb(obj, LV_SIGNAL_CLEANUP, NULL); + 4098: 462a mov r2, r5 + 409a: 4629 mov r1, r5 + 409c: 69e3 ldr r3, [r4, #28] + 409e: 4d28 ldr r5, [pc, #160] ; (4140 ) + 40a0: 4620 mov r0, r4 + 40a2: 4798 blx r3 + lv_obj_t * par = lv_obj_get_parent(obj); + 40a4: 4b27 ldr r3, [pc, #156] ; (4144 ) + 40a6: 4620 mov r0, r4 + 40a8: 4798 blx r3 + if(par == NULL) { /*It is a screen*/ + 40aa: 2800 cmp r0, #0 + 40ac: d137 bne.n 411e + lv_disp_t * d = lv_obj_get_disp(obj); + 40ae: 4b26 ldr r3, [pc, #152] ; (4148 ) + 40b0: 4620 mov r0, r4 + 40b2: 4798 blx r3 + _lv_ll_remove(&d->scr_ll, obj); + 40b4: 4621 mov r1, r4 + 40b6: 3030 adds r0, #48 ; 0x30 + _lv_ll_remove(&(par->child_ll), obj); + 40b8: 47a8 blx r5 + if(obj->ext_attr != NULL) lv_mem_free(obj->ext_attr); + 40ba: 6a60 ldr r0, [r4, #36] ; 0x24 + 40bc: 4d23 ldr r5, [pc, #140] ; (414c ) + 40be: b100 cbz r0, 40c2 + 40c0: 47a8 blx r5 + lv_mem_free(obj); /*Free the object itself*/ + 40c2: 4620 mov r0, r4 + 40c4: 462b mov r3, r5 +} + 40c6: e8bd 47f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + lv_mem_free(obj); /*Free the object itself*/ + 40ca: 4718 bx r3 + i_next = _lv_ll_get_next(&(obj->child_ll), i); + 40cc: 4629 mov r1, r5 + 40ce: 4640 mov r0, r8 + 40d0: 47c8 blx r9 + 40d2: 4606 mov r6, r0 + obj_del_core(i); + 40d4: 4628 mov r0, r5 + 40d6: f7ff ffaf bl 4038 + i = i_next; + 40da: 4635 mov r5, r6 + 40dc: e7cd b.n 407a + if(t->obj == obj) t->deleted = true; + 40de: 6832 ldr r2, [r6, #0] + 40e0: 4294 cmp r4, r2 + 40e2: bf08 it eq + 40e4: 7133 strbeq r3, [r6, #4] + t = t->prev; + 40e6: 68b6 ldr r6, [r6, #8] + 40e8: e7cb b.n 4082 + if(indev->proc.types.pointer.act_obj == obj || indev->proc.types.pointer.last_obj == obj) { + 40ea: 6b6b ldr r3, [r5, #52] ; 0x34 + 40ec: 42a3 cmp r3, r4 + 40ee: d002 beq.n 40f6 + 40f0: 6bab ldr r3, [r5, #56] ; 0x38 + 40f2: 42a3 cmp r3, r4 + 40f4: d102 bne.n 40fc + lv_indev_reset(indev, obj); + 40f6: 4621 mov r1, r4 + 40f8: 4628 mov r0, r5 + 40fa: 47c8 blx r9 + if(indev->proc.types.pointer.last_pressed == obj) { + 40fc: 6beb ldr r3, [r5, #60] ; 0x3c + 40fe: 42a3 cmp r3, r4 + if(indev->group == group && obj == lv_indev_get_obj_act()) { + 4100: 6dab ldr r3, [r5, #88] ; 0x58 + indev->proc.types.pointer.last_pressed = NULL; + 4102: bf08 it eq + 4104: 63ee streq r6, [r5, #60] ; 0x3c + if(indev->group == group && obj == lv_indev_get_obj_act()) { + 4106: 42bb cmp r3, r7 + 4108: d105 bne.n 4116 + 410a: 47d0 blx sl + 410c: 4284 cmp r4, r0 + 410e: d102 bne.n 4116 + lv_indev_reset(indev, obj); + 4110: 4621 mov r1, r4 + 4112: 4628 mov r0, r5 + 4114: 47c8 blx r9 + indev = lv_indev_get_next(indev); + 4116: 4628 mov r0, r5 + 4118: 47c0 blx r8 + 411a: 4605 mov r5, r0 + 411c: e7bb b.n 4096 + _lv_ll_remove(&(par->child_ll), obj); + 411e: 4621 mov r1, r4 + 4120: 3004 adds r0, #4 + 4122: e7c9 b.n 40b8 + 4124: 00001f79 .word 0x00001f79 + 4128: 00003ff1 .word 0x00003ff1 + 412c: 00001b75 .word 0x00001b75 + 4130: 0000dcb1 .word 0x0000dcb1 + 4134: 000024b5 .word 0x000024b5 + 4138: 0000e6a9 .word 0x0000e6a9 + 413c: 200080f4 .word 0x200080f4 + 4140: 0000e76d .word 0x0000e76d + 4144: 00002125 .word 0x00002125 + 4148: 000021c5 .word 0x000021c5 + 414c: 0000eae5 .word 0x0000eae5 + 4150: 0000e6b5 .word 0x0000e6b5 + 4154: 0000da19 .word 0x0000da19 + 4158: 00001c79 .word 0x00001c79 + 415c: 00001cb5 .word 0x00001cb5 + +00004160 : +{ + 4160: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 4162: 4b1b ldr r3, [pc, #108] ; (41d0 ) +{ + 4164: 4604 mov r4, r0 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 4166: 4798 blx r3 + 4168: 4605 mov r5, r0 + 416a: b968 cbnz r0, 4188 + 416c: 4b19 ldr r3, [pc, #100] ; (41d4 ) + 416e: 491a ldr r1, [pc, #104] ; (41d8 ) + 4170: 9300 str r3, [sp, #0] + 4172: f240 1293 movw r2, #403 ; 0x193 + 4176: 2003 movs r0, #3 + 4178: 4e18 ldr r6, [pc, #96] ; (41dc ) + 417a: 47b0 blx r6 + 417c: 4818 ldr r0, [pc, #96] ; (41e0 ) + 417e: 4919 ldr r1, [pc, #100] ; (41e4 ) + 4180: 4622 mov r2, r4 + 4182: 462b mov r3, r5 + 4184: 4788 blx r1 + 4186: e7fe b.n 4186 + lv_obj_invalidate(obj); + 4188: 4b17 ldr r3, [pc, #92] ; (41e8 ) + 418a: 4620 mov r0, r4 + 418c: 4798 blx r3 + lv_obj_t * par = lv_obj_get_parent(obj); + 418e: 4b17 ldr r3, [pc, #92] ; (41ec ) + 4190: 4620 mov r0, r4 + 4192: 4798 blx r3 + if(par == NULL) { + 4194: 4606 mov r6, r0 + 4196: b9b8 cbnz r0, 41c8 + disp = lv_obj_get_disp(obj); + 4198: 4b15 ldr r3, [pc, #84] ; (41f0 ) + 419a: 4620 mov r0, r4 + 419c: 4798 blx r3 + if(!disp) return LV_RES_INV; /*Shouldn't happen*/ + 419e: 4605 mov r5, r0 + 41a0: b178 cbz r0, 41c2 + if(disp->act_scr == obj) act_scr_del = true; + 41a2: 6bc7 ldr r7, [r0, #60] ; 0x3c + 41a4: 1b3b subs r3, r7, r4 + 41a6: 425f negs r7, r3 + 41a8: 415f adcs r7, r3 + obj_del_core(obj); + 41aa: 4b12 ldr r3, [pc, #72] ; (41f4 ) + 41ac: 4620 mov r0, r4 + 41ae: 4798 blx r3 + if(par) { + 41b0: b126 cbz r6, 41bc + par->signal_cb(par, LV_SIGNAL_CHILD_CHG, NULL); + 41b2: 69f3 ldr r3, [r6, #28] + 41b4: 2200 movs r2, #0 + 41b6: 2101 movs r1, #1 + 41b8: 4630 mov r0, r6 + 41ba: 4798 blx r3 + if(act_scr_del) { + 41bc: b10f cbz r7, 41c2 + disp->act_scr = NULL; + 41be: 2300 movs r3, #0 + 41c0: 63eb str r3, [r5, #60] ; 0x3c +} + 41c2: 2000 movs r0, #0 + 41c4: b003 add sp, #12 + 41c6: bdf0 pop {r4, r5, r6, r7, pc} + bool act_scr_del = false; + 41c8: 2700 movs r7, #0 + lv_disp_t * disp = NULL; + 41ca: 463d mov r5, r7 + 41cc: e7ed b.n 41aa + 41ce: bf00 nop + 41d0: 000017e1 .word 0x000017e1 + 41d4: 0001f71b .word 0x0001f71b + 41d8: 0001ee5b .word 0x0001ee5b + 41dc: 0000e8e9 .word 0x0000e8e9 + 41e0: 0001eebf .word 0x0001eebf + 41e4: 000017e9 .word 0x000017e9 + 41e8: 00002785 .word 0x00002785 + 41ec: 00002125 .word 0x00002125 + 41f0: 000021c5 .word 0x000021c5 + 41f4: 00004039 .word 0x00004039 + +000041f8 : +{ + 41f8: b573 push {r0, r1, r4, r5, r6, lr} + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 41fa: 4b0e ldr r3, [pc, #56] ; (4234 ) +{ + 41fc: 4604 mov r4, r0 + LV_ASSERT_OBJ(obj, LV_OBJX_NAME); + 41fe: 4798 blx r3 + 4200: 4605 mov r5, r0 + 4202: b968 cbnz r0, 4220 + 4204: 4b0c ldr r3, [pc, #48] ; (4238 ) + 4206: 490d ldr r1, [pc, #52] ; (423c ) + 4208: 9300 str r3, [sp, #0] + 420a: f44f 6238 mov.w r2, #2944 ; 0xb80 + 420e: 2003 movs r0, #3 + 4210: 4e0b ldr r6, [pc, #44] ; (4240 ) + 4212: 47b0 blx r6 + 4214: 480b ldr r0, [pc, #44] ; (4244 ) + 4216: 490c ldr r1, [pc, #48] ; (4248 ) + 4218: 4622 mov r2, r4 + 421a: 462b mov r3, r5 + 421c: 4788 blx r1 + 421e: e7fe b.n 421e + if(obj->group_p) { + 4220: 6ba0 ldr r0, [r4, #56] ; 0x38 + 4222: b120 cbz r0, 422e + if(lv_group_get_focused(obj->group_p) == obj) return true; + 4224: 4b09 ldr r3, [pc, #36] ; (424c ) + 4226: 4798 blx r3 + 4228: 1a23 subs r3, r4, r0 + 422a: 4258 negs r0, r3 + 422c: 4158 adcs r0, r3 +} + 422e: b002 add sp, #8 + 4230: bd70 pop {r4, r5, r6, pc} + 4232: bf00 nop + 4234: 000017e1 .word 0x000017e1 + 4238: 0001f747 .word 0x0001f747 + 423c: 0001ee5b .word 0x0001ee5b + 4240: 0000e8e9 .word 0x0000e8e9 + 4244: 0001eebf .word 0x0001eebf + 4248: 000017e9 .word 0x000017e9 + 424c: 00001c11 .word 0x00001c11 + +00004250 : +{ + 4250: b507 push {r0, r1, r2, lr} + ext_area.x1 = obj->coords.x1 - obj->ext_click_pad_hor; + 4252: 8a02 ldrh r2, [r0, #16] + 4254: f890 3030 ldrb.w r3, [r0, #48] ; 0x30 + 4258: 1ad2 subs r2, r2, r3 + 425a: f8ad 2000 strh.w r2, [sp] + ext_area.x2 = obj->coords.x2 + obj->ext_click_pad_hor; + 425e: 8a82 ldrh r2, [r0, #20] + 4260: 4413 add r3, r2 + 4262: f8ad 3004 strh.w r3, [sp, #4] + ext_area.y1 = obj->coords.y1 - obj->ext_click_pad_ver; + 4266: 8a42 ldrh r2, [r0, #18] + 4268: f890 3031 ldrb.w r3, [r0, #49] ; 0x31 + 426c: 1ad2 subs r2, r2, r3 + 426e: f8ad 2002 strh.w r2, [sp, #2] + ext_area.y2 = obj->coords.y2 + obj->ext_click_pad_ver; + 4272: 8ac2 ldrh r2, [r0, #22] + 4274: 4413 add r3, r2 + 4276: f8ad 3006 strh.w r3, [sp, #6] + if(!_lv_area_is_point_on(&ext_area, point, 0)) { + 427a: 2200 movs r2, #0 + 427c: 4b02 ldr r3, [pc, #8] ; (4288 ) + 427e: 4668 mov r0, sp + 4280: 4798 blx r3 +} + 4282: b003 add sp, #12 + 4284: f85d fb04 ldr.w pc, [sp], #4 + 4288: 0000df25 .word 0x0000df25 + +0000428c : +{ + 428c: b510 push {r4, lr} + 428e: 2300 movs r3, #0 + if(buf->type[i] == NULL) break; + 4290: f850 4023 ldr.w r4, [r0, r3, lsl #2] + 4294: b2da uxtb r2, r3 + 4296: b11c cbz r4, 42a0 + for(i = 0; i < LV_MAX_ANCESTOR_NUM - 1; i++) { /*Find the last set data*/ + 4298: 3301 adds r3, #1 + 429a: 2b07 cmp r3, #7 + 429c: d1f8 bne.n 4290 + 429e: 461a mov r2, r3 + buf->type[i] = name; + 42a0: f840 1022 str.w r1, [r0, r2, lsl #2] +} + 42a4: 2001 movs r0, #1 + 42a6: bd10 pop {r4, pc} + +000042a8 : +{ + 42a8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 42ac: 4614 mov r4, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(RADIUS, radius, lv_style_int_t, _int, scalar) + 42ae: 4fb6 ldr r7, [pc, #728] ; (4588 ) +_LV_OBJ_STYLE_SET_GET_DECLARE(OPA_SCALE, opa_scale, lv_opa_t, _opa, scalar) + 42b0: f8df 82e0 ldr.w r8, [pc, #736] ; 4594 +_LV_OBJ_STYLE_SET_GET_DECLARE(RADIUS, radius, lv_style_int_t, _int, scalar) + 42b4: 2201 movs r2, #1 + 42b6: 4605 mov r5, r0 + 42b8: 460e mov r6, r1 + 42ba: 47b8 blx r7 +_LV_OBJ_STYLE_SET_GET_DECLARE(OPA_SCALE, opa_scale, lv_opa_t, _opa, scalar) + 42bc: f248 020c movw r2, #32780 ; 0x800c + draw_dsc->radius = lv_obj_get_style_radius(obj, part); + 42c0: 8020 strh r0, [r4, #0] + 42c2: 4631 mov r1, r6 + 42c4: 4628 mov r0, r5 + 42c6: 47c0 blx r8 + if(opa_scale <= LV_OPA_MIN) { + 42c8: 2805 cmp r0, #5 + 42ca: 4681 mov r9, r0 + 42cc: d80a bhi.n 42e4 + draw_dsc->bg_opa = LV_OPA_TRANSP; + 42ce: 2300 movs r3, #0 + 42d0: 7323 strb r3, [r4, #12] + draw_dsc->border_opa = LV_OPA_TRANSP; + 42d2: 7523 strb r3, [r4, #20] + draw_dsc->shadow_opa = LV_OPA_TRANSP; + 42d4: f884 3028 strb.w r3, [r4, #40] ; 0x28 + draw_dsc->pattern_opa = LV_OPA_TRANSP; + 42d8: f884 3036 strb.w r3, [r4, #54] ; 0x36 + draw_dsc->value_opa = (uint16_t)((uint16_t)draw_dsc->value_opa * opa_scale) >> 8; + 42dc: f884 3044 strb.w r3, [r4, #68] ; 0x44 +} + 42e0: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + if(draw_dsc->bg_opa != LV_OPA_TRANSP) { + 42e4: 7b23 ldrb r3, [r4, #12] + 42e6: b343 cbz r3, 433a +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_OPA, bg_opa, lv_opa_t, _opa, scalar) + 42e8: 222c movs r2, #44 ; 0x2c + 42ea: 4631 mov r1, r6 + 42ec: 4628 mov r0, r5 + 42ee: 47c0 blx r8 + if(draw_dsc->bg_opa > LV_OPA_MIN) { + 42f0: 2805 cmp r0, #5 + draw_dsc->bg_opa = lv_obj_get_style_bg_opa(obj, part); + 42f2: 7320 strb r0, [r4, #12] + if(draw_dsc->bg_opa > LV_OPA_MIN) { + 42f4: d921 bls.n 433a +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_COLOR, bg_color, lv_color_t, _color, nonscalar) + 42f6: 2229 movs r2, #41 ; 0x29 + 42f8: 4631 mov r1, r6 + 42fa: f8df a290 ldr.w sl, [pc, #656] ; 458c + 42fe: 4628 mov r0, r5 + 4300: 47d0 blx sl +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_GRAD_DIR, bg_grad_dir, lv_grad_dir_t, _int, scalar) + 4302: 2223 movs r2, #35 ; 0x23 + draw_dsc->bg_color = lv_obj_get_style_bg_color(obj, part); + 4304: 8060 strh r0, [r4, #2] + 4306: 4631 mov r1, r6 + 4308: 4628 mov r0, r5 + 430a: 47b8 blx r7 + 430c: b2c0 uxtb r0, r0 + draw_dsc->bg_grad_dir = lv_obj_get_style_bg_grad_dir(obj, part); + 430e: 71a0 strb r0, [r4, #6] + if(draw_dsc->bg_grad_dir != LV_GRAD_DIR_NONE) { + 4310: b170 cbz r0, 4330 +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_GRAD_COLOR, bg_grad_color, lv_color_t, _color, nonscalar) + 4312: 222a movs r2, #42 ; 0x2a + 4314: 4631 mov r1, r6 + 4316: 4628 mov r0, r5 + 4318: 47d0 blx sl +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_MAIN_STOP, bg_main_stop, lv_style_int_t, _int, scalar) + 431a: 2221 movs r2, #33 ; 0x21 + draw_dsc->bg_grad_color = lv_obj_get_style_bg_grad_color(obj, part); + 431c: 80a0 strh r0, [r4, #4] + 431e: 4631 mov r1, r6 + 4320: 4628 mov r0, r5 + 4322: 47b8 blx r7 +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_GRAD_STOP, bg_grad_stop, lv_style_int_t, _int, scalar) + 4324: 2222 movs r2, #34 ; 0x22 + draw_dsc->bg_main_color_stop = lv_obj_get_style_bg_main_stop(obj, part); + 4326: 8120 strh r0, [r4, #8] + 4328: 4631 mov r1, r6 + 432a: 4628 mov r0, r5 + 432c: 47b8 blx r7 + draw_dsc->bg_grad_color_stop = lv_obj_get_style_bg_grad_stop(obj, part); + 432e: 8160 strh r0, [r4, #10] +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_BLEND_MODE, bg_blend_mode, lv_blend_mode_t, _int, scalar) + 4330: 2220 movs r2, #32 + 4332: 4631 mov r1, r6 + 4334: 4628 mov r0, r5 + 4336: 47b8 blx r7 + 4338: 7360 strb r0, [r4, #13] + if(draw_dsc->border_opa != LV_OPA_TRANSP) { + 433a: 7d23 ldrb r3, [r4, #20] + 433c: b1eb cbz r3, 437a +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_WIDTH, border_width, lv_style_int_t, _int, scalar) + 433e: 2230 movs r2, #48 ; 0x30 + 4340: 4631 mov r1, r6 + 4342: 4628 mov r0, r5 + 4344: 47b8 blx r7 + draw_dsc->border_width = lv_obj_get_style_border_width(obj, part); + 4346: 8220 strh r0, [r4, #16] + if(draw_dsc->border_width) { + 4348: b1b8 cbz r0, 437a +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_OPA, border_opa, lv_opa_t, _opa, scalar) + 434a: 223c movs r2, #60 ; 0x3c + 434c: 4631 mov r1, r6 + 434e: 4628 mov r0, r5 + 4350: 47c0 blx r8 + if(draw_dsc->border_opa > LV_OPA_MIN) { + 4352: 2805 cmp r0, #5 + draw_dsc->border_opa = lv_obj_get_style_border_opa(obj, part); + 4354: 7520 strb r0, [r4, #20] + if(draw_dsc->border_opa > LV_OPA_MIN) { + 4356: d90b bls.n 4370 +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_SIDE, border_side, lv_border_side_t, _int, scalar) + 4358: 2231 movs r2, #49 ; 0x31 + 435a: 4631 mov r1, r6 + 435c: 4628 mov r0, r5 + 435e: 47b8 blx r7 + draw_dsc->border_side = lv_obj_get_style_border_side(obj, part); + 4360: b2c0 uxtb r0, r0 + 4362: 8260 strh r0, [r4, #18] +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_COLOR, border_color, lv_color_t, _color, nonscalar) + 4364: 4b89 ldr r3, [pc, #548] ; (458c ) + 4366: 2239 movs r2, #57 ; 0x39 + 4368: 4631 mov r1, r6 + 436a: 4628 mov r0, r5 + 436c: 4798 blx r3 + draw_dsc->border_color = lv_obj_get_style_border_color(obj, part); + 436e: 81e0 strh r0, [r4, #14] +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_BLEND_MODE, border_blend_mode, lv_blend_mode_t, _int, scalar) + 4370: 2232 movs r2, #50 ; 0x32 + 4372: 4631 mov r1, r6 + 4374: 4628 mov r0, r5 + 4376: 47b8 blx r7 + 4378: 7560 strb r0, [r4, #21] + if(draw_dsc->outline_opa != LV_OPA_TRANSP) { + 437a: 7f23 ldrb r3, [r4, #28] + 437c: b1e3 cbz r3, 43b8 +_LV_OBJ_STYLE_SET_GET_DECLARE(OUTLINE_WIDTH, outline_width, lv_style_int_t, _int, scalar) + 437e: 2240 movs r2, #64 ; 0x40 + 4380: 4631 mov r1, r6 + 4382: 4628 mov r0, r5 + 4384: 47b8 blx r7 + draw_dsc->outline_width = lv_obj_get_style_outline_width(obj, part); + 4386: 8320 strh r0, [r4, #24] + if(draw_dsc->outline_width) { + 4388: b1b0 cbz r0, 43b8 +_LV_OBJ_STYLE_SET_GET_DECLARE(OUTLINE_OPA, outline_opa, lv_opa_t, _opa, scalar) + 438a: 224c movs r2, #76 ; 0x4c + 438c: 4631 mov r1, r6 + 438e: 4628 mov r0, r5 + 4390: 47c0 blx r8 + if(draw_dsc->outline_opa > LV_OPA_MIN) { + 4392: 2805 cmp r0, #5 + draw_dsc->outline_opa = lv_obj_get_style_outline_opa(obj, part); + 4394: 7720 strb r0, [r4, #28] + if(draw_dsc->outline_opa > LV_OPA_MIN) { + 4396: d90a bls.n 43ae +_LV_OBJ_STYLE_SET_GET_DECLARE(OUTLINE_PAD, outline_pad, lv_style_int_t, _int, scalar) + 4398: 2241 movs r2, #65 ; 0x41 + 439a: 4631 mov r1, r6 + 439c: 4628 mov r0, r5 + 439e: 47b8 blx r7 +_LV_OBJ_STYLE_SET_GET_DECLARE(OUTLINE_COLOR, outline_color, lv_color_t, _color, nonscalar) + 43a0: 4b7a ldr r3, [pc, #488] ; (458c ) + draw_dsc->outline_pad = lv_obj_get_style_outline_pad(obj, part); + 43a2: 8360 strh r0, [r4, #26] + 43a4: 2249 movs r2, #73 ; 0x49 + 43a6: 4631 mov r1, r6 + 43a8: 4628 mov r0, r5 + 43aa: 4798 blx r3 + draw_dsc->outline_color = lv_obj_get_style_outline_color(obj, part); + 43ac: 82e0 strh r0, [r4, #22] +_LV_OBJ_STYLE_SET_GET_DECLARE(OUTLINE_BLEND_MODE, outline_blend_mode, lv_blend_mode_t, _int, scalar) + 43ae: 2242 movs r2, #66 ; 0x42 + 43b0: 4631 mov r1, r6 + 43b2: 4628 mov r0, r5 + 43b4: 47b8 blx r7 + 43b6: 7760 strb r0, [r4, #29] + if(draw_dsc->pattern_opa != LV_OPA_TRANSP) { + 43b8: f894 3036 ldrb.w r3, [r4, #54] ; 0x36 + 43bc: 2b00 cmp r3, #0 + 43be: d03b beq.n 4438 +_LV_OBJ_STYLE_SET_GET_DECLARE(PATTERN_IMAGE, pattern_image, const void *, _ptr, scalar) + 43c0: f8df a1d4 ldr.w sl, [pc, #468] ; 4598 + 43c4: 226e movs r2, #110 ; 0x6e + 43c6: 4631 mov r1, r6 + 43c8: 4628 mov r0, r5 + 43ca: 47d0 blx sl + draw_dsc->pattern_image = lv_obj_get_style_pattern_image(obj, part); + 43cc: 62e0 str r0, [r4, #44] ; 0x2c + if(draw_dsc->pattern_image) { + 43ce: 2800 cmp r0, #0 + 43d0: d032 beq.n 4438 +_LV_OBJ_STYLE_SET_GET_DECLARE(PATTERN_OPA, pattern_opa, lv_opa_t, _opa, scalar) + 43d2: 226c movs r2, #108 ; 0x6c + 43d4: 4631 mov r1, r6 + 43d6: 4628 mov r0, r5 + 43d8: 47c0 blx r8 + if(draw_dsc->pattern_opa > LV_OPA_MIN) { + 43da: 2805 cmp r0, #5 + draw_dsc->pattern_opa = lv_obj_get_style_pattern_opa(obj, part); + 43dc: f884 0036 strb.w r0, [r4, #54] ; 0x36 + if(draw_dsc->pattern_opa > LV_OPA_MIN) { + 43e0: d92a bls.n 4438 +_LV_OBJ_STYLE_SET_GET_DECLARE(PATTERN_RECOLOR_OPA, pattern_recolor_opa, lv_opa_t, _opa, scalar) + 43e2: 226d movs r2, #109 ; 0x6d + 43e4: 4631 mov r1, r6 + 43e6: 4628 mov r0, r5 + 43e8: 47c0 blx r8 +_LV_OBJ_STYLE_SET_GET_DECLARE(PATTERN_REPEAT, pattern_repeat, bool, _int, scalar) + 43ea: 2261 movs r2, #97 ; 0x61 + draw_dsc->pattern_recolor_opa = lv_obj_get_style_pattern_recolor_opa(obj, part); + 43ec: f884 0037 strb.w r0, [r4, #55] ; 0x37 + 43f0: 4631 mov r1, r6 + 43f2: 4628 mov r0, r5 + 43f4: 47b8 blx r7 + draw_dsc->pattern_repeat = lv_obj_get_style_pattern_repeat(obj, part); + 43f6: f894 3038 ldrb.w r3, [r4, #56] ; 0x38 + 43fa: 3800 subs r0, #0 + 43fc: bf18 it ne + 43fe: 2001 movne r0, #1 + 4400: f360 0300 bfi r3, r0, #0, #1 + 4404: f884 3038 strb.w r3, [r4, #56] ; 0x38 + if(lv_img_src_get_type(draw_dsc->pattern_image) == LV_IMG_SRC_SYMBOL) { + 4408: 6ae0 ldr r0, [r4, #44] ; 0x2c + 440a: 4b61 ldr r3, [pc, #388] ; (4590 ) + 440c: 4798 blx r3 + 440e: 2802 cmp r0, #2 + 4410: f040 80ad bne.w 456e +_LV_OBJ_STYLE_SET_GET_DECLARE(PATTERN_RECOLOR, pattern_recolor, lv_color_t, _color, nonscalar) + 4414: 4b5d ldr r3, [pc, #372] ; (458c ) + 4416: 2269 movs r2, #105 ; 0x69 + 4418: 4631 mov r1, r6 + 441a: 4628 mov r0, r5 + 441c: 4798 blx r3 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_FONT, text_font, const lv_font_t *, _ptr, scalar) + 441e: f248 028e movw r2, #32910 ; 0x808e + draw_dsc->pattern_recolor = lv_obj_get_style_pattern_recolor(obj, part); + 4422: 86a0 strh r0, [r4, #52] ; 0x34 + 4424: 4631 mov r1, r6 + 4426: 4628 mov r0, r5 + 4428: 47d0 blx sl + draw_dsc->pattern_font = lv_obj_get_style_text_font(obj, part); + 442a: 6320 str r0, [r4, #48] ; 0x30 +_LV_OBJ_STYLE_SET_GET_DECLARE(PATTERN_BLEND_MODE, pattern_blend_mode, lv_blend_mode_t, _int, scalar) + 442c: 2260 movs r2, #96 ; 0x60 + 442e: 4631 mov r1, r6 + 4430: 4628 mov r0, r5 + 4432: 47b8 blx r7 + 4434: f884 0039 strb.w r0, [r4, #57] ; 0x39 + if(draw_dsc->shadow_opa > LV_OPA_MIN) { + 4438: f894 3028 ldrb.w r3, [r4, #40] ; 0x28 + 443c: 2b05 cmp r3, #5 + 443e: d928 bls.n 4492 +_LV_OBJ_STYLE_SET_GET_DECLARE(SHADOW_WIDTH, shadow_width, lv_style_int_t, _int, scalar) + 4440: 2250 movs r2, #80 ; 0x50 + 4442: 4631 mov r1, r6 + 4444: 4628 mov r0, r5 + 4446: 47b8 blx r7 + draw_dsc->shadow_width = lv_obj_get_style_shadow_width(obj, part); + 4448: 8420 strh r0, [r4, #32] + if(draw_dsc->shadow_width) { + 444a: b310 cbz r0, 4492 +_LV_OBJ_STYLE_SET_GET_DECLARE(SHADOW_OPA, shadow_opa, lv_opa_t, _opa, scalar) + 444c: 225c movs r2, #92 ; 0x5c + 444e: 4631 mov r1, r6 + 4450: 4628 mov r0, r5 + 4452: 47c0 blx r8 + if(draw_dsc->shadow_opa > LV_OPA_MIN) { + 4454: 2805 cmp r0, #5 + draw_dsc->shadow_opa = lv_obj_get_style_shadow_opa(obj, part); + 4456: f884 0028 strb.w r0, [r4, #40] ; 0x28 + if(draw_dsc->shadow_opa > LV_OPA_MIN) { + 445a: d91a bls.n 4492 +_LV_OBJ_STYLE_SET_GET_DECLARE(SHADOW_OFS_X, shadow_ofs_x, lv_style_int_t, _int, scalar) + 445c: 2251 movs r2, #81 ; 0x51 + 445e: 4631 mov r1, r6 + 4460: 4628 mov r0, r5 + 4462: 47b8 blx r7 +_LV_OBJ_STYLE_SET_GET_DECLARE(SHADOW_OFS_Y, shadow_ofs_y, lv_style_int_t, _int, scalar) + 4464: 2252 movs r2, #82 ; 0x52 + draw_dsc->shadow_ofs_x = lv_obj_get_style_shadow_ofs_x(obj, part); + 4466: 8460 strh r0, [r4, #34] ; 0x22 + 4468: 4631 mov r1, r6 + 446a: 4628 mov r0, r5 + 446c: 47b8 blx r7 +_LV_OBJ_STYLE_SET_GET_DECLARE(SHADOW_SPREAD, shadow_spread, lv_style_int_t, _int, scalar) + 446e: 2253 movs r2, #83 ; 0x53 + draw_dsc->shadow_ofs_y = lv_obj_get_style_shadow_ofs_y(obj, part); + 4470: 84a0 strh r0, [r4, #36] ; 0x24 + 4472: 4631 mov r1, r6 + 4474: 4628 mov r0, r5 + 4476: 47b8 blx r7 +_LV_OBJ_STYLE_SET_GET_DECLARE(SHADOW_COLOR, shadow_color, lv_color_t, _color, nonscalar) + 4478: 4b44 ldr r3, [pc, #272] ; (458c ) + draw_dsc->shadow_spread = lv_obj_get_style_shadow_spread(obj, part); + 447a: 84e0 strh r0, [r4, #38] ; 0x26 + 447c: 2259 movs r2, #89 ; 0x59 + 447e: 4631 mov r1, r6 + 4480: 4628 mov r0, r5 + 4482: 4798 blx r3 +_LV_OBJ_STYLE_SET_GET_DECLARE(SHADOW_BLEND_MODE, shadow_blend_mode, lv_blend_mode_t, _int, scalar) + 4484: 2254 movs r2, #84 ; 0x54 + draw_dsc->shadow_color = lv_obj_get_style_shadow_color(obj, part); + 4486: 83e0 strh r0, [r4, #30] + 4488: 4631 mov r1, r6 + 448a: 4628 mov r0, r5 + 448c: 47b8 blx r7 + 448e: f884 0029 strb.w r0, [r4, #41] ; 0x29 + if(draw_dsc->value_opa > LV_OPA_MIN) { + 4492: f894 3044 ldrb.w r3, [r4, #68] ; 0x44 + 4496: 2b05 cmp r3, #5 + 4498: d940 bls.n 451c +_LV_OBJ_STYLE_SET_GET_DECLARE(VALUE_STR, value_str, const char *, _ptr, scalar) + 449a: f8df a0fc ldr.w sl, [pc, #252] ; 4598 + 449e: 227f movs r2, #127 ; 0x7f + 44a0: 4631 mov r1, r6 + 44a2: 4628 mov r0, r5 + 44a4: 47d0 blx sl + draw_dsc->value_str = lv_obj_get_style_value_str(obj, part); + 44a6: 63e0 str r0, [r4, #60] ; 0x3c + if(draw_dsc->value_str) { + 44a8: 2800 cmp r0, #0 + 44aa: d037 beq.n 451c +_LV_OBJ_STYLE_SET_GET_DECLARE(VALUE_OPA, value_opa, lv_opa_t, _opa, scalar) + 44ac: 227c movs r2, #124 ; 0x7c + 44ae: 4631 mov r1, r6 + 44b0: 4628 mov r0, r5 + 44b2: 47c0 blx r8 + if(draw_dsc->value_opa > LV_OPA_MIN) { + 44b4: 2805 cmp r0, #5 + draw_dsc->value_opa = lv_obj_get_style_value_opa(obj, part); + 44b6: f884 0044 strb.w r0, [r4, #68] ; 0x44 + if(draw_dsc->value_opa > LV_OPA_MIN) { + 44ba: d92f bls.n 451c +_LV_OBJ_STYLE_SET_GET_DECLARE(VALUE_OFS_X, value_ofs_x, lv_style_int_t, _int, scalar) + 44bc: 2273 movs r2, #115 ; 0x73 + 44be: 4631 mov r1, r6 + 44c0: 4628 mov r0, r5 + 44c2: 47b8 blx r7 +_LV_OBJ_STYLE_SET_GET_DECLARE(VALUE_OFS_Y, value_ofs_y, lv_style_int_t, _int, scalar) + 44c4: 2274 movs r2, #116 ; 0x74 + draw_dsc->value_ofs_x = lv_obj_get_style_value_ofs_x(obj, part); + 44c6: f8a4 0048 strh.w r0, [r4, #72] ; 0x48 + 44ca: 4631 mov r1, r6 + 44cc: 4628 mov r0, r5 + 44ce: 47b8 blx r7 +_LV_OBJ_STYLE_SET_GET_DECLARE(VALUE_COLOR, value_color, lv_color_t, _color, nonscalar) + 44d0: 4b2e ldr r3, [pc, #184] ; (458c ) + draw_dsc->value_ofs_y = lv_obj_get_style_value_ofs_y(obj, part); + 44d2: f8a4 004a strh.w r0, [r4, #74] ; 0x4a + 44d6: 2279 movs r2, #121 ; 0x79 + 44d8: 4631 mov r1, r6 + 44da: 4628 mov r0, r5 + 44dc: 4798 blx r3 +_LV_OBJ_STYLE_SET_GET_DECLARE(VALUE_FONT, value_font, const lv_font_t *, _ptr, scalar) + 44de: 227e movs r2, #126 ; 0x7e + draw_dsc->value_color = lv_obj_get_style_value_color(obj, part); + 44e0: f8a4 0046 strh.w r0, [r4, #70] ; 0x46 + 44e4: 4631 mov r1, r6 + 44e6: 4628 mov r0, r5 + 44e8: 47d0 blx sl +_LV_OBJ_STYLE_SET_GET_DECLARE(VALUE_LETTER_SPACE, value_letter_space, lv_style_int_t, _int, scalar) + 44ea: 2270 movs r2, #112 ; 0x70 + draw_dsc->value_font = lv_obj_get_style_value_font(obj, part); + 44ec: 6420 str r0, [r4, #64] ; 0x40 + 44ee: 4631 mov r1, r6 + 44f0: 4628 mov r0, r5 + 44f2: 47b8 blx r7 +_LV_OBJ_STYLE_SET_GET_DECLARE(VALUE_LINE_SPACE, value_line_space, lv_style_int_t, _int, scalar) + 44f4: 2271 movs r2, #113 ; 0x71 + draw_dsc->value_letter_space = lv_obj_get_style_value_letter_space(obj, part); + 44f6: f8a4 004c strh.w r0, [r4, #76] ; 0x4c + 44fa: 4631 mov r1, r6 + 44fc: 4628 mov r0, r5 + 44fe: 47b8 blx r7 +_LV_OBJ_STYLE_SET_GET_DECLARE(VALUE_ALIGN, value_align, lv_align_t, _int, scalar) + 4500: 2275 movs r2, #117 ; 0x75 + draw_dsc->value_line_space = lv_obj_get_style_value_line_space(obj, part); + 4502: f8a4 004e strh.w r0, [r4, #78] ; 0x4e + 4506: 4631 mov r1, r6 + 4508: 4628 mov r0, r5 + 450a: 47b8 blx r7 +_LV_OBJ_STYLE_SET_GET_DECLARE(VALUE_BLEND_MODE, value_blend_mode, lv_blend_mode_t, _int, scalar) + 450c: 2272 movs r2, #114 ; 0x72 +_LV_OBJ_STYLE_SET_GET_DECLARE(VALUE_ALIGN, value_align, lv_align_t, _int, scalar) + 450e: f884 0050 strb.w r0, [r4, #80] ; 0x50 +_LV_OBJ_STYLE_SET_GET_DECLARE(VALUE_BLEND_MODE, value_blend_mode, lv_blend_mode_t, _int, scalar) + 4512: 4631 mov r1, r6 + 4514: 4628 mov r0, r5 + 4516: 47b8 blx r7 + 4518: f884 0051 strb.w r0, [r4, #81] ; 0x51 + if(opa_scale < LV_OPA_MAX) { + 451c: f1b9 0ff9 cmp.w r9, #249 ; 0xf9 + 4520: f63f aede bhi.w 42e0 + draw_dsc->bg_opa = (uint16_t)((uint16_t)draw_dsc->bg_opa * opa_scale) >> 8; + 4524: 7b23 ldrb r3, [r4, #12] + 4526: fa1f f089 uxth.w r0, r9 + 452a: fb13 f300 smulbb r3, r3, r0 + 452e: f3c3 2307 ubfx r3, r3, #8, #8 + 4532: 7323 strb r3, [r4, #12] + draw_dsc->border_opa = (uint16_t)((uint16_t)draw_dsc->border_opa * opa_scale) >> 8; + 4534: 7d23 ldrb r3, [r4, #20] + 4536: fb13 f300 smulbb r3, r3, r0 + 453a: f3c3 2307 ubfx r3, r3, #8, #8 + 453e: 7523 strb r3, [r4, #20] + draw_dsc->shadow_opa = (uint16_t)((uint16_t)draw_dsc->shadow_opa * opa_scale) >> 8; + 4540: f894 3028 ldrb.w r3, [r4, #40] ; 0x28 + 4544: fb13 f300 smulbb r3, r3, r0 + 4548: f3c3 2307 ubfx r3, r3, #8, #8 + 454c: f884 3028 strb.w r3, [r4, #40] ; 0x28 + draw_dsc->pattern_opa = (uint16_t)((uint16_t)draw_dsc->pattern_opa * opa_scale) >> 8; + 4550: f894 3036 ldrb.w r3, [r4, #54] ; 0x36 + 4554: fb13 f300 smulbb r3, r3, r0 + 4558: f3c3 2307 ubfx r3, r3, #8, #8 + 455c: f884 3036 strb.w r3, [r4, #54] ; 0x36 + draw_dsc->value_opa = (uint16_t)((uint16_t)draw_dsc->value_opa * opa_scale) >> 8; + 4560: f894 3044 ldrb.w r3, [r4, #68] ; 0x44 + 4564: fb13 f300 smulbb r3, r3, r0 + 4568: f3c3 2307 ubfx r3, r3, #8, #8 + 456c: e6b6 b.n 42dc + else if(draw_dsc->pattern_recolor_opa > LV_OPA_MIN) { + 456e: f894 3037 ldrb.w r3, [r4, #55] ; 0x37 + 4572: 2b05 cmp r3, #5 + 4574: f67f af5a bls.w 442c +_LV_OBJ_STYLE_SET_GET_DECLARE(PATTERN_RECOLOR, pattern_recolor, lv_color_t, _color, nonscalar) + 4578: 4b04 ldr r3, [pc, #16] ; (458c ) + 457a: 2269 movs r2, #105 ; 0x69 + 457c: 4631 mov r1, r6 + 457e: 4628 mov r0, r5 + 4580: 4798 blx r3 + draw_dsc->pattern_recolor = lv_obj_get_style_pattern_recolor(obj, part); + 4582: 86a0 strh r0, [r4, #52] ; 0x34 + 4584: e752 b.n 442c + 4586: bf00 nop + 4588: 00003711 .word 0x00003711 + 458c: 000037b5 .word 0x000037b5 + 4590: 00007805 .word 0x00007805 + 4594: 00003839 .word 0x00003839 + 4598: 000038c9 .word 0x000038c9 + +0000459c : +{ + 459c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + if(mode == LV_DESIGN_COVER_CHK) { + 45a0: 2a02 cmp r2, #2 +{ + 45a2: b099 sub sp, #100 ; 0x64 + 45a4: 4604 mov r4, r0 + 45a6: 460f mov r7, r1 + 45a8: 4615 mov r5, r2 + if(mode == LV_DESIGN_COVER_CHK) { + 45aa: d159 bne.n 4660 +_LV_OBJ_STYLE_SET_GET_DECLARE(CLIP_CORNER, clip_corner, bool, _int, scalar) + 45ac: f8df 9230 ldr.w r9, [pc, #560] ; 47e0 + 45b0: 2100 movs r1, #0 + 45b2: 47c8 blx r9 + if(lv_obj_get_style_clip_corner(obj, LV_OBJ_PART_MAIN)) return LV_DESIGN_RES_MASKED; + 45b4: 4606 mov r6, r0 + 45b6: 2800 cmp r0, #0 + 45b8: d150 bne.n 465c +_LV_OBJ_STYLE_SET_GET_DECLARE(RADIUS, radius, lv_style_int_t, _int, scalar) + 45ba: 4601 mov r1, r0 + 45bc: 2201 movs r2, #1 + 45be: 4620 mov r0, r4 + 45c0: 47c8 blx r9 +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSFORM_WIDTH, transform_width, lv_style_int_t, _int, scalar) + 45c2: 2204 movs r2, #4 +_LV_OBJ_STYLE_SET_GET_DECLARE(RADIUS, radius, lv_style_int_t, _int, scalar) + 45c4: 4682 mov sl, r0 +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSFORM_WIDTH, transform_width, lv_style_int_t, _int, scalar) + 45c6: 4631 mov r1, r6 + 45c8: 4620 mov r0, r4 + 45ca: 47c8 blx r9 +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSFORM_HEIGHT, transform_height, lv_style_int_t, _int, scalar) + 45cc: 2205 movs r2, #5 +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSFORM_WIDTH, transform_width, lv_style_int_t, _int, scalar) + 45ce: 4683 mov fp, r0 +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSFORM_HEIGHT, transform_height, lv_style_int_t, _int, scalar) + 45d0: 4631 mov r1, r6 + 45d2: 4620 mov r0, r4 + 45d4: 47c8 blx r9 + lv_area_copy(&coords, &obj->coords); + 45d6: 4b77 ldr r3, [pc, #476] ; (47b4 ) + 45d8: 4680 mov r8, r0 + 45da: f104 0110 add.w r1, r4, #16 + 45de: a803 add r0, sp, #12 + 45e0: 4798 blx r3 + coords.x1 -= w; + 45e2: f8bd 300c ldrh.w r3, [sp, #12] + coords.y1 -= h; + 45e6: f8bd 200e ldrh.w r2, [sp, #14] + coords.x1 -= w; + 45ea: fa1f f08b uxth.w r0, fp + 45ee: 1a1b subs r3, r3, r0 + 45f0: f8ad 300c strh.w r3, [sp, #12] + coords.x2 += w; + 45f4: f8bd 3010 ldrh.w r3, [sp, #16] + 45f8: 4418 add r0, r3 + coords.y1 -= h; + 45fa: fa1f f388 uxth.w r3, r8 + 45fe: 1ad2 subs r2, r2, r3 + 4600: f8ad 200e strh.w r2, [sp, #14] + coords.y2 += h; + 4604: f8bd 2012 ldrh.w r2, [sp, #18] + coords.x2 += w; + 4608: f8ad 0010 strh.w r0, [sp, #16] + coords.y2 += h; + 460c: 4413 add r3, r2 + 460e: f8ad 3012 strh.w r3, [sp, #18] + if(_lv_area_is_in(clip_area, &coords, r) == false) return LV_DESIGN_RES_NOT_COVER; + 4612: 4652 mov r2, sl + 4614: 4b68 ldr r3, [pc, #416] ; (47b8 ) + 4616: a903 add r1, sp, #12 + 4618: 4638 mov r0, r7 + 461a: 4798 blx r3 + 461c: b1d0 cbz r0, 4654 +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_OPA, bg_opa, lv_opa_t, _opa, scalar) + 461e: 4f67 ldr r7, [pc, #412] ; (47bc ) + 4620: 222c movs r2, #44 ; 0x2c + 4622: 4631 mov r1, r6 + 4624: 4620 mov r0, r4 + 4626: 47b8 blx r7 + if(lv_obj_get_style_bg_opa(obj, LV_OBJ_PART_MAIN) < LV_OPA_MAX) return LV_DESIGN_RES_NOT_COVER; + 4628: 28f9 cmp r0, #249 ; 0xf9 + 462a: d913 bls.n 4654 +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_BLEND_MODE, bg_blend_mode, lv_blend_mode_t, _int, scalar) + 462c: 4631 mov r1, r6 + 462e: 2220 movs r2, #32 + 4630: 4620 mov r0, r4 + 4632: 47c8 blx r9 + if(lv_obj_get_style_bg_blend_mode(obj, LV_OBJ_PART_MAIN) != LV_BLEND_MODE_NORMAL) return LV_DESIGN_RES_NOT_COVER; + 4634: f010 01ff ands.w r1, r0, #255 ; 0xff + 4638: d10c bne.n 4654 +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_BLEND_MODE, border_blend_mode, lv_blend_mode_t, _int, scalar) + 463a: 2232 movs r2, #50 ; 0x32 + 463c: 4620 mov r0, r4 + 463e: 47c8 blx r9 + if(lv_obj_get_style_border_blend_mode(obj, LV_OBJ_PART_MAIN) != LV_BLEND_MODE_NORMAL) return LV_DESIGN_RES_NOT_COVER; + 4640: f010 01ff ands.w r1, r0, #255 ; 0xff + 4644: d106 bne.n 4654 +_LV_OBJ_STYLE_SET_GET_DECLARE(OPA_SCALE, opa_scale, lv_opa_t, _opa, scalar) + 4646: f248 020c movw r2, #32780 ; 0x800c + 464a: 4620 mov r0, r4 + 464c: 47b8 blx r7 + return LV_DESIGN_RES_COVER; + 464e: 28f9 cmp r0, #249 ; 0xf9 + 4650: bf88 it hi + 4652: 2501 movhi r5, #1 +} + 4654: 4628 mov r0, r5 + 4656: b019 add sp, #100 ; 0x64 + 4658: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + if(lv_obj_get_style_clip_corner(obj, LV_OBJ_PART_MAIN)) return LV_DESIGN_RES_MASKED; + 465c: 2503 movs r5, #3 + 465e: e7f9 b.n 4654 + else if(mode == LV_DESIGN_DRAW_MAIN) { + 4660: 2a00 cmp r2, #0 + 4662: d156 bne.n 4712 + lv_draw_rect_dsc_init(&draw_dsc); + 4664: a803 add r0, sp, #12 + 4666: 4b56 ldr r3, [pc, #344] ; (47c0 ) +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_POST, border_post, bool, _int, scalar) + 4668: f8df 8174 ldr.w r8, [pc, #372] ; 47e0 + 466c: 4798 blx r3 + 466e: 2233 movs r2, #51 ; 0x33 + 4670: 4629 mov r1, r5 + 4672: 4620 mov r0, r4 + 4674: 47c0 blx r8 + if(lv_obj_get_style_border_post(obj, LV_OBJ_PART_MAIN)) { + 4676: b108 cbz r0, 467c + draw_dsc.border_opa = LV_OPA_TRANSP; + 4678: f88d 5020 strb.w r5, [sp, #32] + lv_obj_init_draw_rect_dsc(obj, LV_OBJ_PART_MAIN, &draw_dsc); + 467c: 4b51 ldr r3, [pc, #324] ; (47c4 ) + 467e: aa03 add r2, sp, #12 + 4680: 2100 movs r1, #0 + 4682: 4620 mov r0, r4 + 4684: 4798 blx r3 +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSFORM_WIDTH, transform_width, lv_style_int_t, _int, scalar) + 4686: 2204 movs r2, #4 + 4688: 2100 movs r1, #0 + 468a: 4620 mov r0, r4 + 468c: 47c0 blx r8 +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSFORM_HEIGHT, transform_height, lv_style_int_t, _int, scalar) + 468e: 2205 movs r2, #5 +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSFORM_WIDTH, transform_width, lv_style_int_t, _int, scalar) + 4690: 4606 mov r6, r0 +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSFORM_HEIGHT, transform_height, lv_style_int_t, _int, scalar) + 4692: 2100 movs r1, #0 + 4694: 4620 mov r0, r4 + 4696: 47c0 blx r8 + lv_area_copy(&coords, &obj->coords); + 4698: f104 0910 add.w r9, r4, #16 + 469c: 4b45 ldr r3, [pc, #276] ; (47b4 ) + 469e: 4682 mov sl, r0 + 46a0: 4649 mov r1, r9 + 46a2: a801 add r0, sp, #4 + 46a4: 4798 blx r3 + coords.x1 -= w; + 46a6: f8bd 2004 ldrh.w r2, [sp, #4] + 46aa: b2b3 uxth r3, r6 + 46ac: 1ad2 subs r2, r2, r3 + 46ae: f8ad 2004 strh.w r2, [sp, #4] + coords.x2 += w; + 46b2: f8bd 2008 ldrh.w r2, [sp, #8] + 46b6: 4413 add r3, r2 + 46b8: f8ad 3008 strh.w r3, [sp, #8] + coords.y1 -= h; + 46bc: f8bd 3006 ldrh.w r3, [sp, #6] + 46c0: fa1f f08a uxth.w r0, sl + 46c4: 1a1b subs r3, r3, r0 + 46c6: f8ad 3006 strh.w r3, [sp, #6] + coords.y2 += h; + 46ca: f8bd 300a ldrh.w r3, [sp, #10] + 46ce: 4418 add r0, r3 + 46d0: f8ad 000a strh.w r0, [sp, #10] + lv_draw_rect(&coords, clip_area, &draw_dsc); + 46d4: aa03 add r2, sp, #12 + 46d6: 4639 mov r1, r7 + 46d8: a801 add r0, sp, #4 + 46da: 4b3b ldr r3, [pc, #236] ; (47c8 ) + 46dc: 4798 blx r3 +_LV_OBJ_STYLE_SET_GET_DECLARE(CLIP_CORNER, clip_corner, bool, _int, scalar) + 46de: 2202 movs r2, #2 + 46e0: 2100 movs r1, #0 + 46e2: 4620 mov r0, r4 + 46e4: 47c0 blx r8 + if(lv_obj_get_style_clip_corner(obj, LV_OBJ_PART_MAIN)) { + 46e6: 2800 cmp r0, #0 + 46e8: d0b4 beq.n 4654 + lv_draw_mask_radius_param_t * mp = _lv_mem_buf_get(sizeof(lv_draw_mask_radius_param_t)); + 46ea: 4b38 ldr r3, [pc, #224] ; (47cc ) + lv_draw_mask_radius_init(mp, &obj->coords, r, false); + 46ec: 4f38 ldr r7, [pc, #224] ; (47d0 ) + lv_draw_mask_radius_param_t * mp = _lv_mem_buf_get(sizeof(lv_draw_mask_radius_param_t)); + 46ee: 201c movs r0, #28 + 46f0: 4798 blx r3 +_LV_OBJ_STYLE_SET_GET_DECLARE(RADIUS, radius, lv_style_int_t, _int, scalar) + 46f2: 2201 movs r2, #1 + 46f4: 4606 mov r6, r0 + 46f6: 2100 movs r1, #0 + 46f8: 4620 mov r0, r4 + 46fa: 47c0 blx r8 + lv_draw_mask_radius_init(mp, &obj->coords, r, false); + 46fc: 4649 mov r1, r9 + 46fe: 4602 mov r2, r0 + 4700: 2300 movs r3, #0 + 4702: 4630 mov r0, r6 + 4704: 47b8 blx r7 + lv_draw_mask_add(mp, obj + 8); + 4706: 4b33 ldr r3, [pc, #204] ; (47d4 ) + 4708: f504 7118 add.w r1, r4, #608 ; 0x260 + 470c: 4630 mov r0, r6 + 470e: 4798 blx r3 + 4710: e7a0 b.n 4654 + else if(mode == LV_DESIGN_DRAW_POST) { + 4712: 2a01 cmp r2, #1 + 4714: d001 beq.n 471a + return LV_DESIGN_RES_OK; + 4716: 2500 movs r5, #0 + 4718: e79c b.n 4654 +_LV_OBJ_STYLE_SET_GET_DECLARE(CLIP_CORNER, clip_corner, bool, _int, scalar) + 471a: f8df 80c4 ldr.w r8, [pc, #196] ; 47e0 + 471e: 2202 movs r2, #2 + 4720: 2100 movs r1, #0 + 4722: 47c0 blx r8 + if(lv_obj_get_style_clip_corner(obj, LV_OBJ_PART_MAIN)) { + 4724: b128 cbz r0, 4732 + lv_draw_mask_radius_param_t * param = lv_draw_mask_remove_custom(obj + 8); + 4726: 4b2c ldr r3, [pc, #176] ; (47d8 ) + 4728: f504 7018 add.w r0, r4, #608 ; 0x260 + 472c: 4798 blx r3 + _lv_mem_buf_release(param); + 472e: 4b2b ldr r3, [pc, #172] ; (47dc ) + 4730: 4798 blx r3 +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_POST, border_post, bool, _int, scalar) + 4732: 2233 movs r2, #51 ; 0x33 + 4734: 2100 movs r1, #0 + 4736: 4620 mov r0, r4 + 4738: 47c0 blx r8 + if(lv_obj_get_style_border_post(obj, LV_OBJ_PART_MAIN)) { + 473a: 2800 cmp r0, #0 + 473c: d0eb beq.n 4716 + draw_dsc.bg_opa = LV_OPA_TRANSP; + 473e: 2500 movs r5, #0 + lv_draw_rect_dsc_init(&draw_dsc); + 4740: a803 add r0, sp, #12 + 4742: 4b1f ldr r3, [pc, #124] ; (47c0 ) + 4744: 4798 blx r3 + lv_obj_init_draw_rect_dsc(obj, LV_OBJ_PART_MAIN, &draw_dsc); + 4746: 4b1f ldr r3, [pc, #124] ; (47c4 ) + draw_dsc.bg_opa = LV_OPA_TRANSP; + 4748: f88d 5018 strb.w r5, [sp, #24] + lv_obj_init_draw_rect_dsc(obj, LV_OBJ_PART_MAIN, &draw_dsc); + 474c: aa03 add r2, sp, #12 + 474e: 4629 mov r1, r5 + 4750: 4620 mov r0, r4 + draw_dsc.pattern_opa = LV_OPA_TRANSP; + 4752: f88d 5042 strb.w r5, [sp, #66] ; 0x42 + draw_dsc.shadow_opa = LV_OPA_TRANSP; + 4756: f88d 5034 strb.w r5, [sp, #52] ; 0x34 + lv_obj_init_draw_rect_dsc(obj, LV_OBJ_PART_MAIN, &draw_dsc); + 475a: 4798 blx r3 +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSFORM_WIDTH, transform_width, lv_style_int_t, _int, scalar) + 475c: 4629 mov r1, r5 + 475e: 2204 movs r2, #4 + 4760: 4620 mov r0, r4 + 4762: 47c0 blx r8 +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSFORM_HEIGHT, transform_height, lv_style_int_t, _int, scalar) + 4764: 2205 movs r2, #5 +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSFORM_WIDTH, transform_width, lv_style_int_t, _int, scalar) + 4766: 4606 mov r6, r0 +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSFORM_HEIGHT, transform_height, lv_style_int_t, _int, scalar) + 4768: 4629 mov r1, r5 + 476a: 4620 mov r0, r4 + 476c: 47c0 blx r8 + lv_area_copy(&coords, &obj->coords); + 476e: f104 0110 add.w r1, r4, #16 + 4772: 4680 mov r8, r0 + 4774: 4b0f ldr r3, [pc, #60] ; (47b4 ) + 4776: a801 add r0, sp, #4 + 4778: 4798 blx r3 + coords.x1 -= w; + 477a: f8bd 2004 ldrh.w r2, [sp, #4] + 477e: b2b3 uxth r3, r6 + 4780: 1ad2 subs r2, r2, r3 + 4782: f8ad 2004 strh.w r2, [sp, #4] + coords.x2 += w; + 4786: f8bd 2008 ldrh.w r2, [sp, #8] + 478a: 4413 add r3, r2 + 478c: f8ad 3008 strh.w r3, [sp, #8] + coords.y1 -= h; + 4790: f8bd 3006 ldrh.w r3, [sp, #6] + 4794: fa1f f088 uxth.w r0, r8 + 4798: 1a1b subs r3, r3, r0 + 479a: f8ad 3006 strh.w r3, [sp, #6] + coords.y2 += h; + 479e: f8bd 300a ldrh.w r3, [sp, #10] + 47a2: 4418 add r0, r3 + 47a4: f8ad 000a strh.w r0, [sp, #10] + lv_draw_rect(&coords, clip_area, &draw_dsc); + 47a8: 4b07 ldr r3, [pc, #28] ; (47c8 ) + 47aa: aa03 add r2, sp, #12 + 47ac: 4639 mov r1, r7 + 47ae: a801 add r0, sp, #4 + 47b0: 4798 blx r3 + 47b2: e74f b.n 4654 + 47b4: 00001d19 .word 0x00001d19 + 47b8: 0000e091 .word 0x0000e091 + 47bc: 00003839 .word 0x00003839 + 47c0: 00009ba1 .word 0x00009ba1 + 47c4: 000042a9 .word 0x000042a9 + 47c8: 00009bed .word 0x00009bed + 47cc: 0000eeb5 .word 0x0000eeb5 + 47d0: 00009915 .word 0x00009915 + 47d4: 00009711 .word 0x00009711 + 47d8: 000097c9 .word 0x000097c9 + 47dc: 0000eb69 .word 0x0000eb69 + 47e0: 00003711 .word 0x00003711 + +000047e4 : +{ + 47e4: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 47e8: 4614 mov r4, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_OPA, text_opa, lv_opa_t, _opa, scalar) + 47ea: 4f28 ldr r7, [pc, #160] ; (488c ) + 47ec: f248 028c movw r2, #32908 ; 0x808c + 47f0: 4605 mov r5, r0 + 47f2: 460e mov r6, r1 + 47f4: 47b8 blx r7 + if(draw_dsc->opa <= LV_OPA_MIN) return; + 47f6: 2805 cmp r0, #5 + draw_dsc->opa = lv_obj_get_style_text_opa(obj, part); + 47f8: 7220 strb r0, [r4, #8] + if(draw_dsc->opa <= LV_OPA_MIN) return; + 47fa: d945 bls.n 4888 +_LV_OBJ_STYLE_SET_GET_DECLARE(OPA_SCALE, opa_scale, lv_opa_t, _opa, scalar) + 47fc: f248 020c movw r2, #32780 ; 0x800c + 4800: 4631 mov r1, r6 + 4802: 4628 mov r0, r5 + 4804: 47b8 blx r7 + if(opa_scale < LV_OPA_MAX) { + 4806: 28f9 cmp r0, #249 ; 0xf9 + draw_dsc->opa = (uint16_t)((uint16_t)draw_dsc->opa * opa_scale) >> 8; + 4808: bf9f itttt ls + 480a: 7a23 ldrbls r3, [r4, #8] + 480c: fb13 f000 smulbbls r0, r3, r0 + 4810: f3c0 2007 ubfxls r0, r0, #8, #8 + 4814: 7220 strbls r0, [r4, #8] + if(draw_dsc->opa <= LV_OPA_MIN) return; + 4816: 7a23 ldrb r3, [r4, #8] + 4818: 2b05 cmp r3, #5 + 481a: d935 bls.n 4888 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_COLOR, text_color, lv_color_t, _color, nonscalar) + 481c: f248 0289 movw r2, #32905 ; 0x8089 + 4820: 4631 mov r1, r6 + 4822: f8df 8074 ldr.w r8, [pc, #116] ; 4898 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_LETTER_SPACE, text_letter_space, lv_style_int_t, _int, scalar) + 4826: 4f1a ldr r7, [pc, #104] ; (4890 ) +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_COLOR, text_color, lv_color_t, _color, nonscalar) + 4828: 4628 mov r0, r5 + 482a: 47c0 blx r8 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_LETTER_SPACE, text_letter_space, lv_style_int_t, _int, scalar) + 482c: f248 0280 movw r2, #32896 ; 0x8080 + draw_dsc->color = lv_obj_get_style_text_color(obj, part); + 4830: 8020 strh r0, [r4, #0] + 4832: 4631 mov r1, r6 + 4834: 4628 mov r0, r5 + 4836: 47b8 blx r7 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_LINE_SPACE, text_line_space, lv_style_int_t, _int, scalar) + 4838: f248 0281 movw r2, #32897 ; 0x8081 + draw_dsc->letter_space = lv_obj_get_style_text_letter_space(obj, part); + 483c: 81a0 strh r0, [r4, #12] + 483e: 4631 mov r1, r6 + 4840: 4628 mov r0, r5 + 4842: 47b8 blx r7 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_DECOR, text_decor, lv_text_decor_t, _int, scalar) + 4844: f248 0282 movw r2, #32898 ; 0x8082 + draw_dsc->line_space = lv_obj_get_style_text_line_space(obj, part); + 4848: 8160 strh r0, [r4, #10] + 484a: 4631 mov r1, r6 + 484c: 4628 mov r0, r5 + 484e: 47b8 blx r7 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_BLEND_MODE, text_blend_mode, lv_blend_mode_t, _int, scalar) + 4850: f248 0283 movw r2, #32899 ; 0x8083 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_DECOR, text_decor, lv_text_decor_t, _int, scalar) + 4854: 7620 strb r0, [r4, #24] +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_BLEND_MODE, text_blend_mode, lv_blend_mode_t, _int, scalar) + 4856: 4631 mov r1, r6 + 4858: 4628 mov r0, r5 + 485a: 47b8 blx r7 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_FONT, text_font, const lv_font_t *, _ptr, scalar) + 485c: 4b0d ldr r3, [pc, #52] ; (4894 ) +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_BLEND_MODE, text_blend_mode, lv_blend_mode_t, _int, scalar) + 485e: 7660 strb r0, [r4, #25] +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_FONT, text_font, const lv_font_t *, _ptr, scalar) + 4860: f248 028e movw r2, #32910 ; 0x808e + 4864: 4631 mov r1, r6 + 4866: 4628 mov r0, r5 + 4868: 4798 blx r3 + if(draw_dsc->sel_start != LV_DRAW_LABEL_NO_TXT_SEL && draw_dsc->sel_end != LV_DRAW_LABEL_NO_TXT_SEL) { + 486a: 89e2 ldrh r2, [r4, #14] + draw_dsc->font = lv_obj_get_style_text_font(obj, part); + 486c: 6060 str r0, [r4, #4] + if(draw_dsc->sel_start != LV_DRAW_LABEL_NO_TXT_SEL && draw_dsc->sel_end != LV_DRAW_LABEL_NO_TXT_SEL) { + 486e: f64f 73ff movw r3, #65535 ; 0xffff + 4872: 429a cmp r2, r3 + 4874: d008 beq.n 4888 + 4876: 8a22 ldrh r2, [r4, #16] + 4878: 429a cmp r2, r3 + 487a: d005 beq.n 4888 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_SEL_COLOR, text_sel_color, lv_color_t, _color, nonscalar) + 487c: f248 028a movw r2, #32906 ; 0x808a + 4880: 4631 mov r1, r6 + 4882: 4628 mov r0, r5 + 4884: 47c0 blx r8 + draw_dsc->color = lv_obj_get_style_text_sel_color(obj, part); + 4886: 8020 strh r0, [r4, #0] +} + 4888: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + 488c: 00003839 .word 0x00003839 + 4890: 00003711 .word 0x00003711 + 4894: 000038c9 .word 0x000038c9 + 4898: 000037b5 .word 0x000037b5 + +0000489c : +{ + 489c: b5f8 push {r3, r4, r5, r6, r7, lr} + 489e: 4614 mov r4, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(IMAGE_OPA, image_opa, lv_opa_t, _opa, scalar) + 48a0: 4f23 ldr r7, [pc, #140] ; (4930 ) + 48a2: f248 02ac movw r2, #32940 ; 0x80ac + 48a6: 4605 mov r5, r0 + 48a8: 460e mov r6, r1 + 48aa: 47b8 blx r7 + if(draw_dsc->opa <= LV_OPA_MIN) return; + 48ac: 2805 cmp r0, #5 + draw_dsc->opa = lv_obj_get_style_image_opa(obj, part); + 48ae: 7020 strb r0, [r4, #0] + if(draw_dsc->opa <= LV_OPA_MIN) return; + 48b0: d93c bls.n 492c +_LV_OBJ_STYLE_SET_GET_DECLARE(OPA_SCALE, opa_scale, lv_opa_t, _opa, scalar) + 48b2: f248 020c movw r2, #32780 ; 0x800c + 48b6: 4631 mov r1, r6 + 48b8: 4628 mov r0, r5 + 48ba: 47b8 blx r7 + if(opa_scale < LV_OPA_MAX) { + 48bc: 28f9 cmp r0, #249 ; 0xf9 + draw_dsc->opa = (uint16_t)((uint16_t)draw_dsc->opa * opa_scale) >> 8; + 48be: bf9f itttt ls + 48c0: 7823 ldrbls r3, [r4, #0] + 48c2: fb13 f000 smulbbls r0, r3, r0 + 48c6: f3c0 2007 ubfxls r0, r0, #8, #8 + 48ca: 7020 strbls r0, [r4, #0] + if(draw_dsc->opa <= LV_OPA_MIN) return; + 48cc: 7823 ldrb r3, [r4, #0] + 48ce: 2b05 cmp r3, #5 + 48d0: d92c bls.n 492c + draw_dsc->angle = 0; + 48d2: 2300 movs r3, #0 + 48d4: 8063 strh r3, [r4, #2] + draw_dsc->zoom = LV_IMG_ZOOM_NONE; + 48d6: f44f 7380 mov.w r3, #256 ; 0x100 + 48da: 8123 strh r3, [r4, #8] + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + 48dc: 8aab ldrh r3, [r5, #20] + 48de: 8a2a ldrh r2, [r5, #16] + 48e0: 3301 adds r3, #1 + 48e2: 1a9b subs r3, r3, r2 + draw_dsc->pivot.x = lv_area_get_width(&obj->coords) / 2; + 48e4: f3c3 32c0 ubfx r2, r3, #15, #1 + 48e8: fa02 f383 sxtah r3, r2, r3 + 48ec: 105b asrs r3, r3, #1 + 48ee: 80a3 strh r3, [r4, #4] + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + 48f0: 8aeb ldrh r3, [r5, #22] + 48f2: 8a6a ldrh r2, [r5, #18] + 48f4: 3301 adds r3, #1 + 48f6: 1a9b subs r3, r3, r2 + draw_dsc->pivot.y = lv_area_get_height(&obj->coords) / 2; + 48f8: f3c3 32c0 ubfx r2, r3, #15, #1 + 48fc: fa02 f383 sxtah r3, r2, r3 + 4900: 105b asrs r3, r3, #1 + 4902: 80e3 strh r3, [r4, #6] +_LV_OBJ_STYLE_SET_GET_DECLARE(IMAGE_RECOLOR_OPA, image_recolor_opa, lv_opa_t, _opa, scalar) + 4904: f248 02ad movw r2, #32941 ; 0x80ad + 4908: 4631 mov r1, r6 + 490a: 4628 mov r0, r5 + 490c: 47b8 blx r7 +_LV_OBJ_STYLE_SET_GET_DECLARE(IMAGE_RECOLOR, image_recolor, lv_color_t, _color, nonscalar) + 490e: 4b09 ldr r3, [pc, #36] ; (4934 ) + draw_dsc->recolor_opa = lv_obj_get_style_image_recolor_opa(obj, part); + 4910: 72a0 strb r0, [r4, #10] + 4912: f248 02a9 movw r2, #32937 ; 0x80a9 + 4916: 4631 mov r1, r6 + 4918: 4628 mov r0, r5 + 491a: 4798 blx r3 +_LV_OBJ_STYLE_SET_GET_DECLARE(IMAGE_BLEND_MODE, image_blend_mode, lv_blend_mode_t, _int, scalar) + 491c: 4b06 ldr r3, [pc, #24] ; (4938 ) + draw_dsc->recolor = lv_obj_get_style_image_recolor(obj, part); + 491e: 81a0 strh r0, [r4, #12] + 4920: f248 02a0 movw r2, #32928 ; 0x80a0 + 4924: 4631 mov r1, r6 + 4926: 4628 mov r0, r5 + 4928: 4798 blx r3 + 492a: 73a0 strb r0, [r4, #14] +} + 492c: bdf8 pop {r3, r4, r5, r6, r7, pc} + 492e: bf00 nop + 4930: 00003839 .word 0x00003839 + 4934: 000037b5 .word 0x000037b5 + 4938: 00003711 .word 0x00003711 + +0000493c : +{ + 493c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} +_LV_OBJ_STYLE_SET_GET_DECLARE(SHADOW_WIDTH, shadow_width, lv_style_int_t, _int, scalar) + 4940: 2250 movs r2, #80 ; 0x50 + 4942: 4f75 ldr r7, [pc, #468] ; (4b18 ) + 4944: b08a sub sp, #40 ; 0x28 + 4946: 4604 mov r4, r0 + 4948: 460e mov r6, r1 + 494a: 47b8 blx r7 + if(sh_width) { + 494c: 4605 mov r5, r0 + 494e: 2800 cmp r0, #0 + 4950: f040 80b4 bne.w 4abc + lv_coord_t s = 0; + 4954: 2500 movs r5, #0 +_LV_OBJ_STYLE_SET_GET_DECLARE(VALUE_STR, value_str, const char *, _ptr, scalar) + 4956: f8df a1c8 ldr.w sl, [pc, #456] ; 4b20 + 495a: 227f movs r2, #127 ; 0x7f + 495c: 4631 mov r1, r6 + 495e: 4620 mov r0, r4 + 4960: 47d0 blx sl + if(value_str) { + 4962: 4680 mov r8, r0 + 4964: 2800 cmp r0, #0 + 4966: d07e beq.n 4a66 +_LV_OBJ_STYLE_SET_GET_DECLARE(VALUE_OPA, value_opa, lv_opa_t, _opa, scalar) + 4968: 4b6c ldr r3, [pc, #432] ; (4b1c ) + 496a: 227c movs r2, #124 ; 0x7c + 496c: 4631 mov r1, r6 + 496e: 4620 mov r0, r4 + 4970: 4798 blx r3 + if(value_opa > LV_OPA_MIN) { + 4972: 2805 cmp r0, #5 + 4974: d977 bls.n 4a66 +_LV_OBJ_STYLE_SET_GET_DECLARE(VALUE_LETTER_SPACE, value_letter_space, lv_style_int_t, _int, scalar) + 4976: 2270 movs r2, #112 ; 0x70 + 4978: 4631 mov r1, r6 + 497a: 4620 mov r0, r4 + 497c: 47b8 blx r7 + 497e: 2270 movs r2, #112 ; 0x70 + 4980: 9005 str r0, [sp, #20] + 4982: 4631 mov r1, r6 + 4984: 4620 mov r0, r4 + 4986: 47b8 blx r7 +_LV_OBJ_STYLE_SET_GET_DECLARE(VALUE_FONT, value_font, const lv_font_t *, _ptr, scalar) + 4988: 227e movs r2, #126 ; 0x7e +_LV_OBJ_STYLE_SET_GET_DECLARE(VALUE_LETTER_SPACE, value_letter_space, lv_style_int_t, _int, scalar) + 498a: 4681 mov r9, r0 +_LV_OBJ_STYLE_SET_GET_DECLARE(VALUE_FONT, value_font, const lv_font_t *, _ptr, scalar) + 498c: 4631 mov r1, r6 + 498e: 4620 mov r0, r4 + 4990: 47d0 blx sl + _lv_txt_get_size(&txt_size, value_str, font, letter_space, line_space, LV_COORD_MAX, LV_TXT_FLAG_NONE); + 4992: f04f 0a00 mov.w sl, #0 + 4996: f647 4118 movw r1, #31768 ; 0x7c18 + 499a: e9cd 1a01 strd r1, sl, [sp, #4] + 499e: 4602 mov r2, r0 + 49a0: 4641 mov r1, r8 + 49a2: 9b05 ldr r3, [sp, #20] + 49a4: f8df 817c ldr.w r8, [pc, #380] ; 4b24 + 49a8: f8cd 9000 str.w r9, [sp] + 49ac: a806 add r0, sp, #24 + 49ae: 47c0 blx r8 + value_area.x2 = txt_size.x - 1; + 49b0: f8bd 3018 ldrh.w r3, [sp, #24] + value_area.x1 = 0; + 49b4: f8cd a020 str.w sl, [sp, #32] + value_area.x2 = txt_size.x - 1; + 49b8: 3b01 subs r3, #1 + 49ba: f8ad 3024 strh.w r3, [sp, #36] ; 0x24 + value_area.y2 = txt_size.y - 1; + 49be: f8bd 301a ldrh.w r3, [sp, #26] +_LV_OBJ_STYLE_SET_GET_DECLARE(VALUE_ALIGN, value_align, lv_align_t, _int, scalar) + 49c2: 2275 movs r2, #117 ; 0x75 + 49c4: 3b01 subs r3, #1 + 49c6: 4631 mov r1, r6 + 49c8: 4620 mov r0, r4 + 49ca: f8ad 3026 strh.w r3, [sp, #38] ; 0x26 + 49ce: 47b8 blx r7 +_LV_OBJ_STYLE_SET_GET_DECLARE(VALUE_OFS_X, value_ofs_x, lv_style_int_t, _int, scalar) + 49d0: 2273 movs r2, #115 ; 0x73 +_LV_OBJ_STYLE_SET_GET_DECLARE(VALUE_ALIGN, value_align, lv_align_t, _int, scalar) + 49d2: 4682 mov sl, r0 +_LV_OBJ_STYLE_SET_GET_DECLARE(VALUE_OFS_X, value_ofs_x, lv_style_int_t, _int, scalar) + 49d4: 4631 mov r1, r6 + 49d6: 4620 mov r0, r4 + 49d8: 47b8 blx r7 +_LV_OBJ_STYLE_SET_GET_DECLARE(VALUE_OFS_Y, value_ofs_y, lv_style_int_t, _int, scalar) + 49da: 2274 movs r2, #116 ; 0x74 +_LV_OBJ_STYLE_SET_GET_DECLARE(VALUE_OFS_X, value_ofs_x, lv_style_int_t, _int, scalar) + 49dc: 4681 mov r9, r0 +_LV_OBJ_STYLE_SET_GET_DECLARE(VALUE_OFS_Y, value_ofs_y, lv_style_int_t, _int, scalar) + 49de: 4631 mov r1, r6 + 49e0: 4620 mov r0, r4 + 49e2: 47b8 blx r7 + _lv_area_align(&obj->coords, &value_area, align, &p_align); + 49e4: fa5f f28a uxtb.w r2, sl + 49e8: 4680 mov r8, r0 + 49ea: ab07 add r3, sp, #28 + 49ec: a908 add r1, sp, #32 + 49ee: f104 0010 add.w r0, r4, #16 + 49f2: f8df a134 ldr.w sl, [pc, #308] ; 4b28 + 49f6: 47d0 blx sl + value_area.y1 += p_align.y + yofs; + 49f8: f8bd 201e ldrh.w r2, [sp, #30] + value_area.x1 += p_align.x + xofs; + 49fc: f8bd 301c ldrh.w r3, [sp, #28] + s = LV_MATH_MAX(s, obj->coords.x1 - value_area.x1); + 4a00: f9b4 1010 ldrsh.w r1, [r4, #16] + value_area.y1 += p_align.y + yofs; + 4a04: eb08 0002 add.w r0, r8, r2 + value_area.x1 += p_align.x + xofs; + 4a08: f8bd 2020 ldrh.w r2, [sp, #32] + 4a0c: 444b add r3, r9 + 4a0e: fa12 f283 uxtah r2, r2, r3 + s = LV_MATH_MAX(s, obj->coords.x1 - value_area.x1); + 4a12: b212 sxth r2, r2 + 4a14: 1a89 subs r1, r1, r2 + 4a16: 42a9 cmp r1, r5 + 4a18: bfb8 it lt + 4a1a: 4629 movlt r1, r5 + value_area.y1 += p_align.y + yofs; + 4a1c: f8bd 5022 ldrh.w r5, [sp, #34] ; 0x22 + s = LV_MATH_MAX(s, obj->coords.y1 - value_area.y1); + 4a20: f9b4 2012 ldrsh.w r2, [r4, #18] + value_area.y1 += p_align.y + yofs; + 4a24: fa15 f580 uxtah r5, r5, r0 + s = LV_MATH_MAX(s, obj->coords.y1 - value_area.y1); + 4a28: b22d sxth r5, r5 + 4a2a: 1b52 subs r2, r2, r5 + 4a2c: b209 sxth r1, r1 + 4a2e: 428a cmp r2, r1 + 4a30: bfb8 it lt + 4a32: 460a movlt r2, r1 + value_area.x2 += p_align.x + xofs; + 4a34: f8bd 1024 ldrh.w r1, [sp, #36] ; 0x24 + 4a38: fa11 f383 uxtah r3, r1, r3 + s = LV_MATH_MAX(s, value_area.x2 - obj->coords.x2); + 4a3c: f9b4 1014 ldrsh.w r1, [r4, #20] + 4a40: b21b sxth r3, r3 + 4a42: 1a5b subs r3, r3, r1 + 4a44: b212 sxth r2, r2 + 4a46: 4293 cmp r3, r2 + 4a48: bfb8 it lt + 4a4a: 4613 movlt r3, r2 + value_area.y2 += p_align.y + yofs; + 4a4c: f8bd 2026 ldrh.w r2, [sp, #38] ; 0x26 + 4a50: fa12 f080 uxtah r0, r2, r0 + s = LV_MATH_MAX(s, value_area.y2 - obj->coords.y2); + 4a54: f9b4 2016 ldrsh.w r2, [r4, #22] + 4a58: b200 sxth r0, r0 + 4a5a: 1a80 subs r0, r0, r2 + 4a5c: b21b sxth r3, r3 + 4a5e: 4298 cmp r0, r3 + 4a60: bfb8 it lt + 4a62: 4618 movlt r0, r3 + 4a64: b205 sxth r5, r0 +_LV_OBJ_STYLE_SET_GET_DECLARE(OUTLINE_WIDTH, outline_width, lv_style_int_t, _int, scalar) + 4a66: 2240 movs r2, #64 ; 0x40 + 4a68: 4631 mov r1, r6 + 4a6a: 4620 mov r0, r4 + 4a6c: 47b8 blx r7 + if(outline_width) { + 4a6e: 4680 mov r8, r0 + 4a70: b178 cbz r0, 4a92 +_LV_OBJ_STYLE_SET_GET_DECLARE(OUTLINE_OPA, outline_opa, lv_opa_t, _opa, scalar) + 4a72: 4b2a ldr r3, [pc, #168] ; (4b1c ) + 4a74: 224c movs r2, #76 ; 0x4c + 4a76: 4631 mov r1, r6 + 4a78: 4620 mov r0, r4 + 4a7a: 4798 blx r3 + if(outline_opa > LV_OPA_MIN) { + 4a7c: 2805 cmp r0, #5 + 4a7e: d908 bls.n 4a92 +_LV_OBJ_STYLE_SET_GET_DECLARE(OUTLINE_PAD, outline_pad, lv_style_int_t, _int, scalar) + 4a80: 2241 movs r2, #65 ; 0x41 + 4a82: 4631 mov r1, r6 + 4a84: 4620 mov r0, r4 + 4a86: 47b8 blx r7 + s = LV_MATH_MAX(s, outline_pad + outline_width); + 4a88: 4440 add r0, r8 + 4a8a: 42a8 cmp r0, r5 + 4a8c: bfb8 it lt + 4a8e: 4628 movlt r0, r5 + 4a90: b205 sxth r5, r0 +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSFORM_WIDTH, transform_width, lv_style_int_t, _int, scalar) + 4a92: 4631 mov r1, r6 + 4a94: 2204 movs r2, #4 + 4a96: 4620 mov r0, r4 + 4a98: 47b8 blx r7 +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSFORM_HEIGHT, transform_height, lv_style_int_t, _int, scalar) + 4a9a: 2205 movs r2, #5 +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSFORM_WIDTH, transform_width, lv_style_int_t, _int, scalar) + 4a9c: 4680 mov r8, r0 +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSFORM_HEIGHT, transform_height, lv_style_int_t, _int, scalar) + 4a9e: 4631 mov r1, r6 + 4aa0: 4620 mov r0, r4 + 4aa2: 47b8 blx r7 + lv_coord_t wh = LV_MATH_MAX(w, h); + 4aa4: 4540 cmp r0, r8 + 4aa6: bfb8 it lt + 4aa8: 4640 movlt r0, r8 + 4aaa: b200 sxth r0, r0 + if(wh > 0) s += wh; + 4aac: 2800 cmp r0, #0 + 4aae: bfc4 itt gt + 4ab0: 1940 addgt r0, r0, r5 + 4ab2: b205 sxthgt r5, r0 +} + 4ab4: 4628 mov r0, r5 + 4ab6: b00a add sp, #40 ; 0x28 + 4ab8: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} +_LV_OBJ_STYLE_SET_GET_DECLARE(SHADOW_OPA, shadow_opa, lv_opa_t, _opa, scalar) + 4abc: 4b17 ldr r3, [pc, #92] ; (4b1c ) + 4abe: 225c movs r2, #92 ; 0x5c + 4ac0: 4631 mov r1, r6 + 4ac2: 4620 mov r0, r4 + 4ac4: 4798 blx r3 + if(sh_opa > LV_OPA_MIN) { + 4ac6: 2805 cmp r0, #5 + 4ac8: f67f af44 bls.w 4954 +_LV_OBJ_STYLE_SET_GET_DECLARE(SHADOW_SPREAD, shadow_spread, lv_style_int_t, _int, scalar) + 4acc: 2253 movs r2, #83 ; 0x53 + 4ace: 4631 mov r1, r6 + 4ad0: 4620 mov r0, r4 + 4ad2: 47b8 blx r7 + sh_width = sh_width / 2; /*THe blur adds only half width*/ + 4ad4: eb05 75d5 add.w r5, r5, r5, lsr #31 + sh_width++; + 4ad8: eb00 0565 add.w r5, r0, r5, asr #1 +_LV_OBJ_STYLE_SET_GET_DECLARE(SHADOW_OFS_X, shadow_ofs_x, lv_style_int_t, _int, scalar) + 4adc: 2251 movs r2, #81 ; 0x51 + 4ade: 4631 mov r1, r6 + 4ae0: 4620 mov r0, r4 + 4ae2: 47b8 blx r7 +_LV_OBJ_STYLE_SET_GET_DECLARE(SHADOW_OFS_Y, shadow_ofs_y, lv_style_int_t, _int, scalar) + 4ae4: 2252 movs r2, #82 ; 0x52 +_LV_OBJ_STYLE_SET_GET_DECLARE(SHADOW_OFS_X, shadow_ofs_x, lv_style_int_t, _int, scalar) + 4ae6: 4680 mov r8, r0 +_LV_OBJ_STYLE_SET_GET_DECLARE(SHADOW_OFS_Y, shadow_ofs_y, lv_style_int_t, _int, scalar) + 4ae8: 4631 mov r1, r6 + 4aea: 4620 mov r0, r4 + 4aec: 47b8 blx r7 + sh_width += LV_MATH_MAX(LV_MATH_ABS(sh_ofs_x), LV_MATH_ABS(sh_ofs_y)); + 4aee: 2800 cmp r0, #0 + 4af0: bfb8 it lt + 4af2: 4240 neglt r0, r0 + 4af4: f1b8 0f00 cmp.w r8, #0 + 4af8: bfb8 it lt + 4afa: f1c8 0800 rsblt r8, r8, #0 + sh_width += lv_obj_get_style_shadow_spread(obj, part); + 4afe: 3501 adds r5, #1 + 4b00: b2ad uxth r5, r5 + sh_width += LV_MATH_MAX(LV_MATH_ABS(sh_ofs_x), LV_MATH_ABS(sh_ofs_y)); + 4b02: b280 uxth r0, r0 + 4b04: fa1f f888 uxth.w r8, r8 + 4b08: 4540 cmp r0, r8 + 4b0a: bf2c ite cs + 4b0c: 182d addcs r5, r5, r0 + 4b0e: 4445 addcc r5, r8 + s = LV_MATH_MAX(s, sh_width); + 4b10: b22d sxth r5, r5 + 4b12: ea25 75e5 bic.w r5, r5, r5, asr #31 + 4b16: e71e b.n 4956 + 4b18: 00003711 .word 0x00003711 + 4b1c: 00003839 .word 0x00003839 + 4b20: 000038c9 .word 0x000038c9 + 4b24: 0001019d .word 0x0001019d + 4b28: 0000e131 .word 0x0000e131 + +00004b2c : +{ + 4b2c: b570 push {r4, r5, r6, lr} + 4b2e: 4605 mov r5, r0 + 4b30: 4610 mov r0, r2 + 4b32: 2917 cmp r1, #23 + 4b34: d811 bhi.n 4b5a + 4b36: e8df f001 tbb [pc, r1] + 4b3a: 1a55 .short 0x1a55 + 4b3c: 10372e10 .word 0x10372e10 + 4b40: 100c1523 .word 0x100c1523 + 4b44: 40103b10 .word 0x40103b10 + 4b48: 10101040 .word 0x10101040 + 4b4c: 10101010 .word 0x10101010 + 4b50: 5344 .short 0x5344 + if(info->part == LV_OBJ_PART_MAIN) info->result = &obj->style_list; + 4b52: 7813 ldrb r3, [r2, #0] + 4b54: b91b cbnz r3, 4b5e + 4b56: 3528 adds r5, #40 ; 0x28 + 4b58: 6055 str r5, [r2, #4] + lv_res_t res = LV_RES_OK; + 4b5a: 2401 movs r4, #1 + 4b5c: e00e b.n 4b7c + else info->result = NULL; + 4b5e: 2300 movs r3, #0 + 4b60: 6053 str r3, [r2, #4] + 4b62: e7fa b.n 4b5a +} + 4b64: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + else if(sign == LV_SIGNAL_GET_TYPE) return lv_obj_handle_get_type_signal(param, LV_OBJX_NAME); + 4b68: 4920 ldr r1, [pc, #128] ; (4bec ) + 4b6a: 4b21 ldr r3, [pc, #132] ; (4bf0 ) + 4b6c: 4718 bx r3 + if(lv_obj_is_protected(obj, LV_PROTECT_CHILD_CHG) != false) res = LV_RES_INV; + 4b6e: 4b21 ldr r3, [pc, #132] ; (4bf4 ) + 4b70: 2101 movs r1, #1 + 4b72: 4628 mov r0, r5 + 4b74: 4798 blx r3 + 4b76: f080 0001 eor.w r0, r0, #1 + return LV_RES_OK; + 4b7a: b2c4 uxtb r4, r0 +} + 4b7c: 4620 mov r0, r4 + 4b7e: bd70 pop {r4, r5, r6, pc} + lv_coord_t d = lv_obj_get_draw_rect_ext_pad_size(obj, LV_OBJ_PART_MAIN); + 4b80: 4b1d ldr r3, [pc, #116] ; (4bf8 ) + 4b82: 2100 movs r1, #0 + 4b84: 4628 mov r0, r5 + 4b86: 4798 blx r3 + obj->ext_draw_pad = LV_MATH_MAX(obj->ext_draw_pad, d); + 4b88: f9b5 3032 ldrsh.w r3, [r5, #50] ; 0x32 + 4b8c: 4298 cmp r0, r3 + 4b8e: bfb8 it lt + 4b90: 4618 movlt r0, r3 + 4b92: 8668 strh r0, [r5, #50] ; 0x32 + 4b94: e7e1 b.n 4b5a + if(obj->realign.auto_realign) { + 4b96: f895 4049 ldrb.w r4, [r5, #73] ; 0x49 + 4b9a: f014 0401 ands.w r4, r4, #1 + 4b9e: d0dc beq.n 4b5a + lv_obj_realign(obj); + 4ba0: 4b16 ldr r3, [pc, #88] ; (4bfc ) + 4ba2: 4628 mov r0, r5 + 4ba4: 4798 blx r3 + 4ba6: e7e9 b.n 4b7c + lv_obj_refresh_ext_draw_pad(obj); + 4ba8: 4b15 ldr r3, [pc, #84] ; (4c00 ) + 4baa: 4628 mov r0, r5 + 4bac: 4798 blx r3 + 4bae: e7d4 b.n 4b5a + lv_obj_add_state(obj, LV_STATE_PRESSED); + 4bb0: 4b14 ldr r3, [pc, #80] ; (4c04 ) + 4bb2: 2110 movs r1, #16 + 4bb4: 4628 mov r0, r5 + lv_obj_clean_style_list(obj, LV_OBJ_PART_MAIN); + 4bb6: 4798 blx r3 + 4bb8: e7cf b.n 4b5a + lv_obj_clear_state(obj, LV_STATE_PRESSED); + 4bba: 2110 movs r1, #16 + lv_obj_clear_state(obj, LV_STATE_EDITED); + 4bbc: 4b12 ldr r3, [pc, #72] ; (4c08 ) + 4bbe: 4628 mov r0, r5 + 4bc0: e7f9 b.n 4bb6 + if(lv_group_get_editing(lv_obj_get_group(obj))) { + 4bc2: 4b12 ldr r3, [pc, #72] ; (4c0c ) + 4bc4: 4628 mov r0, r5 + 4bc6: 4798 blx r3 + 4bc8: 4b11 ldr r3, [pc, #68] ; (4c10 ) + 4bca: 4798 blx r3 + 4bcc: 4b0d ldr r3, [pc, #52] ; (4c04 ) + 4bce: b110 cbz r0, 4bd6 + lv_obj_add_state(obj, state); + 4bd0: 2106 movs r1, #6 + 4bd2: 4628 mov r0, r5 + 4bd4: e7ef b.n 4bb6 + lv_obj_add_state(obj, LV_STATE_FOCUSED); + 4bd6: 2102 movs r1, #2 + 4bd8: 4628 mov r0, r5 + 4bda: 4798 blx r3 + lv_obj_clear_state(obj, LV_STATE_EDITED); + 4bdc: 2104 movs r1, #4 + 4bde: e7ed b.n 4bbc + lv_obj_clear_state(obj, LV_STATE_FOCUSED | LV_STATE_EDITED); + 4be0: 2106 movs r1, #6 + 4be2: e7eb b.n 4bbc + lv_obj_clean_style_list(obj, LV_OBJ_PART_MAIN); + 4be4: 4b0b ldr r3, [pc, #44] ; (4c14 ) + 4be6: 2100 movs r1, #0 + 4be8: 4628 mov r0, r5 + 4bea: e7e4 b.n 4bb6 + 4bec: 0001f05b .word 0x0001f05b + 4bf0: 0000428d .word 0x0000428d + 4bf4: 00003651 .word 0x00003651 + 4bf8: 0000493d .word 0x0000493d + 4bfc: 00002ce9 .word 0x00002ce9 + 4c00: 000020d1 .word 0x000020d1 + 4c04: 00003e99 .word 0x00003e99 + 4c08: 00003efd .word 0x00003efd + 4c0c: 00003ff1 .word 0x00003ff1 + 4c10: 00001c1b .word 0x00001c1b + 4c14: 00002549 .word 0x00002549 + +00004c18 : + +/** + * Flush the content of the VDB + */ +static void lv_refr_vdb_flush(void) +{ + 4c18: b538 push {r3, r4, r5, lr} + lv_disp_buf_t * vdb = lv_disp_get_buf(disp_refr); + 4c1a: 4d17 ldr r5, [pc, #92] ; (4c78 ) + 4c1c: 4b17 ldr r3, [pc, #92] ; (4c7c ) + 4c1e: 6828 ldr r0, [r5, #0] + 4c20: 4798 blx r3 + + /*In double buffered mode wait until the other buffer is flushed before flushing the current + * one*/ + if(lv_disp_is_double_buf(disp_refr)) { + 4c22: 4b17 ldr r3, [pc, #92] ; (4c80 ) + lv_disp_buf_t * vdb = lv_disp_get_buf(disp_refr); + 4c24: 4604 mov r4, r0 + if(lv_disp_is_double_buf(disp_refr)) { + 4c26: 6828 ldr r0, [r5, #0] + 4c28: 4798 blx r3 + 4c2a: b958 cbnz r0, 4c44 + } + } + + vdb->flushing = 1; + + if(disp_refr->driver.buffer->last_area && disp_refr->driver.buffer->last_part) vdb->flushing_last = 1; + 4c2c: 6828 ldr r0, [r5, #0] + vdb->flushing = 1; + 4c2e: 2301 movs r3, #1 + if(disp_refr->driver.buffer->last_area && disp_refr->driver.buffer->last_part) vdb->flushing_last = 1; + 4c30: 6842 ldr r2, [r0, #4] + vdb->flushing = 1; + 4c32: 61a3 str r3, [r4, #24] + if(disp_refr->driver.buffer->last_area && disp_refr->driver.buffer->last_part) vdb->flushing_last = 1; + 4c34: 6a11 ldr r1, [r2, #32] + 4c36: 07c9 lsls r1, r1, #31 + 4c38: d409 bmi.n 4c4e + else vdb->flushing_last = 0; + 4c3a: 2300 movs r3, #0 + 4c3c: e00a b.n 4c54 + if(disp_refr->driver.wait_cb) disp_refr->driver.wait_cb(&disp_refr->driver); + 4c3e: 69c3 ldr r3, [r0, #28] + 4c40: b10b cbz r3, 4c46 + 4c42: 4798 blx r3 + 4c44: 6828 ldr r0, [r5, #0] + while(vdb->flushing) { + 4c46: 69a3 ldr r3, [r4, #24] + 4c48: 2b00 cmp r3, #0 + 4c4a: d1f8 bne.n 4c3e + 4c4c: e7ee b.n 4c2c + if(disp_refr->driver.buffer->last_area && disp_refr->driver.buffer->last_part) vdb->flushing_last = 1; + 4c4e: 6a12 ldr r2, [r2, #32] + 4c50: 0792 lsls r2, r2, #30 + 4c52: d5f2 bpl.n 4c3a + else vdb->flushing_last = 0; + 4c54: 61e3 str r3, [r4, #28] + + /*Flush the rendered content to the display*/ + lv_disp_t * disp = _lv_refr_get_disp_refreshing(); + if(disp->driver.flush_cb) disp->driver.flush_cb(&disp->driver, &vdb->area, vdb->buf_act); + 4c56: 68c3 ldr r3, [r0, #12] + 4c58: b11b cbz r3, 4c62 + 4c5a: 68a2 ldr r2, [r4, #8] + 4c5c: f104 0110 add.w r1, r4, #16 + 4c60: 4798 blx r3 + + if(vdb->buf1 && vdb->buf2) { + 4c62: 6822 ldr r2, [r4, #0] + 4c64: b132 cbz r2, 4c74 + 4c66: 6863 ldr r3, [r4, #4] + 4c68: b123 cbz r3, 4c74 + if(vdb->buf_act == vdb->buf1) + 4c6a: 68a1 ldr r1, [r4, #8] + vdb->buf_act = vdb->buf2; + 4c6c: 428a cmp r2, r1 + 4c6e: bf18 it ne + 4c70: 4613 movne r3, r2 + 4c72: 60a3 str r3, [r4, #8] + else + vdb->buf_act = vdb->buf1; + } +} + 4c74: bd38 pop {r3, r4, r5, pc} + 4c76: bf00 nop + 4c78: 20008100 .word 0x20008100 + 4c7c: 0000d9e1 .word 0x0000d9e1 + 4c80: 0000d9e5 .word 0x0000d9e5 + +00004c84 : +{ + 4c84: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + if(_lv_area_is_in(area_p, &obj->coords, 0) && obj->hidden == 0) { + 4c88: 2200 movs r2, #0 +{ + 4c8a: 460c mov r4, r1 + if(_lv_area_is_in(area_p, &obj->coords, 0) && obj->hidden == 0) { + 4c8c: 4b17 ldr r3, [pc, #92] ; (4cec ) + 4c8e: 3110 adds r1, #16 +{ + 4c90: 4607 mov r7, r0 + if(_lv_area_is_in(area_p, &obj->coords, 0) && obj->hidden == 0) { + 4c92: 4798 blx r3 + 4c94: b910 cbnz r0, 4c9c + lv_obj_t * found_p = NULL; + 4c96: 2000 movs r0, #0 +} + 4c98: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + if(_lv_area_is_in(area_p, &obj->coords, 0) && obj->hidden == 0) { + 4c9c: f894 3034 ldrb.w r3, [r4, #52] ; 0x34 + 4ca0: 06db lsls r3, r3, #27 + 4ca2: d4f8 bmi.n 4c96 + lv_design_res_t design_res = obj->design_cb ? obj->design_cb(obj, area_p, + 4ca4: 6a23 ldr r3, [r4, #32] + 4ca6: b19b cbz r3, 4cd0 + 4ca8: 2202 movs r2, #2 + 4caa: 4639 mov r1, r7 + 4cac: 4620 mov r0, r4 + 4cae: 4798 blx r3 + if(design_res == LV_DESIGN_RES_MASKED) return NULL; + 4cb0: 2803 cmp r0, #3 + lv_design_res_t design_res = obj->design_cb ? obj->design_cb(obj, area_p, + 4cb2: 4606 mov r6, r0 + if(design_res == LV_DESIGN_RES_MASKED) return NULL; + 4cb4: d0ef beq.n 4c96 + _LV_LL_READ(obj->child_ll, i) { + 4cb6: f104 0804 add.w r8, r4, #4 + 4cba: 4b0d ldr r3, [pc, #52] ; (4cf0 ) + 4cbc: f8df 9034 ldr.w r9, [pc, #52] ; 4cf4 + 4cc0: 4640 mov r0, r8 + 4cc2: 4798 blx r3 + 4cc4: 4605 mov r5, r0 + 4cc6: b92d cbnz r5, 4cd4 + if(design_res == LV_DESIGN_RES_COVER) { + 4cc8: 2e01 cmp r6, #1 + 4cca: d1e4 bne.n 4c96 + 4ccc: 4620 mov r0, r4 + 4cce: e7e3 b.n 4c98 + lv_design_res_t design_res = obj->design_cb ? obj->design_cb(obj, area_p, + 4cd0: 2602 movs r6, #2 + 4cd2: e7f0 b.n 4cb6 + found_p = lv_refr_get_top_obj(area_p, i); + 4cd4: 4629 mov r1, r5 + 4cd6: 4638 mov r0, r7 + 4cd8: f7ff ffd4 bl 4c84 + if(found_p != NULL) { + 4cdc: 2800 cmp r0, #0 + 4cde: d1db bne.n 4c98 + _LV_LL_READ(obj->child_ll, i) { + 4ce0: 4629 mov r1, r5 + 4ce2: 4640 mov r0, r8 + 4ce4: 47c8 blx r9 + 4ce6: 4605 mov r5, r0 + 4ce8: e7ed b.n 4cc6 + 4cea: bf00 nop + 4cec: 0000e091 .word 0x0000e091 + 4cf0: 0000e6a9 .word 0x0000e6a9 + 4cf4: 0000e6b5 .word 0x0000e6b5 + +00004cf8 : +{ + 4cf8: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} + if(obj->hidden != 0) return; + 4cfc: f890 8034 ldrb.w r8, [r0, #52] ; 0x34 + 4d00: f018 0810 ands.w r8, r8, #16 +{ + 4d04: b08b sub sp, #44 ; 0x2c + 4d06: 4604 mov r4, r0 + 4d08: 460f mov r7, r1 + if(obj->hidden != 0) return; + 4d0a: d13c bne.n 4d86 + lv_coord_t ext_size = obj->ext_draw_pad; + 4d0c: f9b0 5032 ldrsh.w r5, [r0, #50] ; 0x32 + lv_obj_get_coords(obj, &obj_area); + 4d10: 4e31 ldr r6, [pc, #196] ; (4dd8 ) + union_ok = _lv_area_intersect(&obj_ext_mask, mask_ori_p, &obj_area); + 4d12: f8df 90cc ldr.w r9, [pc, #204] ; 4de0 + lv_obj_get_coords(obj, &obj_area); + 4d16: a904 add r1, sp, #16 + 4d18: 47b0 blx r6 + obj_area.x1 -= ext_size; + 4d1a: f8bd 2010 ldrh.w r2, [sp, #16] + 4d1e: b2ab uxth r3, r5 + 4d20: 1ad2 subs r2, r2, r3 + 4d22: f8ad 2010 strh.w r2, [sp, #16] + obj_area.y1 -= ext_size; + 4d26: f8bd 2012 ldrh.w r2, [sp, #18] + 4d2a: 1ad2 subs r2, r2, r3 + 4d2c: f8ad 2012 strh.w r2, [sp, #18] + obj_area.x2 += ext_size; + 4d30: f8bd 2014 ldrh.w r2, [sp, #20] + 4d34: 441a add r2, r3 + 4d36: f8ad 2014 strh.w r2, [sp, #20] + obj_area.y2 += ext_size; + 4d3a: f8bd 2016 ldrh.w r2, [sp, #22] + union_ok = _lv_area_intersect(&obj_ext_mask, mask_ori_p, &obj_area); + 4d3e: 4639 mov r1, r7 + obj_area.y2 += ext_size; + 4d40: 4413 add r3, r2 + union_ok = _lv_area_intersect(&obj_ext_mask, mask_ori_p, &obj_area); + 4d42: a802 add r0, sp, #8 + 4d44: aa04 add r2, sp, #16 + obj_area.y2 += ext_size; + 4d46: f8ad 3016 strh.w r3, [sp, #22] + union_ok = _lv_area_intersect(&obj_ext_mask, mask_ori_p, &obj_area); + 4d4a: 47c8 blx r9 + if(union_ok != false) { + 4d4c: b1d8 cbz r0, 4d86 + if(obj->design_cb) obj->design_cb(obj, &obj_ext_mask, LV_DESIGN_DRAW_MAIN); + 4d4e: 6a23 ldr r3, [r4, #32] + 4d50: b11b cbz r3, 4d5a + 4d52: 4642 mov r2, r8 + 4d54: a902 add r1, sp, #8 + 4d56: 4620 mov r0, r4 + 4d58: 4798 blx r3 + lv_obj_get_coords(obj, &obj_area); + 4d5a: a904 add r1, sp, #16 + 4d5c: 4620 mov r0, r4 + 4d5e: 47b0 blx r6 + union_ok = _lv_area_intersect(&obj_mask, mask_ori_p, &obj_area); + 4d60: aa04 add r2, sp, #16 + 4d62: 4639 mov r1, r7 + 4d64: 4668 mov r0, sp + 4d66: 47c8 blx r9 + if(union_ok != false) { + 4d68: b138 cbz r0, 4d7a + _LV_LL_READ_BACK(obj->child_ll, child_p) { + 4d6a: 1d27 adds r7, r4, #4 + 4d6c: 4b1b ldr r3, [pc, #108] ; (4ddc ) + 4d6e: f8df 8074 ldr.w r8, [pc, #116] ; 4de4 + 4d72: 4638 mov r0, r7 + 4d74: 4798 blx r3 + 4d76: 4605 mov r5, r0 + 4d78: b945 cbnz r5, 4d8c + if(obj->design_cb) obj->design_cb(obj, &obj_ext_mask, LV_DESIGN_DRAW_POST); + 4d7a: 6a23 ldr r3, [r4, #32] + 4d7c: b11b cbz r3, 4d86 + 4d7e: 2201 movs r2, #1 + 4d80: a902 add r1, sp, #8 + 4d82: 4620 mov r0, r4 + 4d84: 4798 blx r3 +} + 4d86: b00b add sp, #44 ; 0x2c + 4d88: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + lv_obj_get_coords(child_p, &child_area); + 4d8c: a908 add r1, sp, #32 + 4d8e: 4628 mov r0, r5 + 4d90: 47b0 blx r6 + child_area.x1 -= ext_size; + 4d92: 8e6b ldrh r3, [r5, #50] ; 0x32 + 4d94: f8bd 2020 ldrh.w r2, [sp, #32] + 4d98: 1ad2 subs r2, r2, r3 + 4d9a: f8ad 2020 strh.w r2, [sp, #32] + child_area.y1 -= ext_size; + 4d9e: f8bd 2022 ldrh.w r2, [sp, #34] ; 0x22 + 4da2: 1ad2 subs r2, r2, r3 + 4da4: f8ad 2022 strh.w r2, [sp, #34] ; 0x22 + child_area.x2 += ext_size; + 4da8: f8bd 2024 ldrh.w r2, [sp, #36] ; 0x24 + 4dac: 441a add r2, r3 + 4dae: f8ad 2024 strh.w r2, [sp, #36] ; 0x24 + child_area.y2 += ext_size; + 4db2: f8bd 2026 ldrh.w r2, [sp, #38] ; 0x26 + union_ok = _lv_area_intersect(&mask_child, &obj_mask, &child_area); + 4db6: 4669 mov r1, sp + child_area.y2 += ext_size; + 4db8: 4413 add r3, r2 + union_ok = _lv_area_intersect(&mask_child, &obj_mask, &child_area); + 4dba: a806 add r0, sp, #24 + 4dbc: aa08 add r2, sp, #32 + child_area.y2 += ext_size; + 4dbe: f8ad 3026 strh.w r3, [sp, #38] ; 0x26 + union_ok = _lv_area_intersect(&mask_child, &obj_mask, &child_area); + 4dc2: 47c8 blx r9 + if(union_ok) { + 4dc4: b118 cbz r0, 4dce + lv_refr_obj(child_p, &mask_child); + 4dc6: a906 add r1, sp, #24 + 4dc8: 4628 mov r0, r5 + 4dca: f7ff ff95 bl 4cf8 + _LV_LL_READ_BACK(obj->child_ll, child_p) { + 4dce: 4629 mov r1, r5 + 4dd0: 4638 mov r0, r7 + 4dd2: 47c0 blx r8 + 4dd4: 4605 mov r5, r0 + 4dd6: e7cf b.n 4d78 + 4dd8: 000022d5 .word 0x000022d5 + 4ddc: 0000e6af .word 0x0000e6af + 4de0: 0000de8d .word 0x0000de8d + 4de4: 0000e6d5 .word 0x0000e6d5 + +00004de8 : +{ + 4de8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 4dec: 460e mov r6, r1 + if(top_p == NULL) top_p = lv_disp_get_scr_act(disp_refr); + 4dee: 4604 mov r4, r0 + 4df0: b928 cbnz r0, 4dfe + 4df2: 4b15 ldr r3, [pc, #84] ; (4e48 ) + 4df4: 6818 ldr r0, [r3, #0] + 4df6: 4b15 ldr r3, [pc, #84] ; (4e4c ) + 4df8: 4798 blx r3 + if(top_p == NULL) return; /*Shouldn't happen*/ + 4dfa: 4604 mov r4, r0 + 4dfc: b158 cbz r0, 4e16 + lv_refr_obj(top_p, mask_p); + 4dfe: 4631 mov r1, r6 + 4e00: 4620 mov r0, r4 + 4e02: 4f13 ldr r7, [pc, #76] ; (4e50 ) + par = lv_obj_get_parent(top_p); + 4e04: f8df 804c ldr.w r8, [pc, #76] ; 4e54 + lv_obj_t * i = _lv_ll_get_prev(&(par->child_ll), border_p); + 4e08: f8df 904c ldr.w r9, [pc, #76] ; 4e58 + lv_refr_obj(top_p, mask_p); + 4e0c: 47b8 blx r7 + par = lv_obj_get_parent(top_p); + 4e0e: 4620 mov r0, r4 + 4e10: 47c0 blx r8 + 4e12: 4605 mov r5, r0 + while(par != NULL) { + 4e14: b90d cbnz r5, 4e1a +} + 4e16: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + lv_obj_t * i = _lv_ll_get_prev(&(par->child_ll), border_p); + 4e1a: f105 0a04 add.w sl, r5, #4 + i = _lv_ll_get_prev(&(par->child_ll), i); + 4e1e: 4621 mov r1, r4 + 4e20: 4650 mov r0, sl + 4e22: 47c8 blx r9 + 4e24: 4604 mov r4, r0 + while(i != NULL) { + 4e26: b950 cbnz r0, 4e3e + if(par->design_cb) par->design_cb(par, mask_p, LV_DESIGN_DRAW_POST); + 4e28: 6a2b ldr r3, [r5, #32] + 4e2a: b11b cbz r3, 4e34 + 4e2c: 2201 movs r2, #1 + 4e2e: 4631 mov r1, r6 + 4e30: 4628 mov r0, r5 + 4e32: 4798 blx r3 + par = lv_obj_get_parent(par); + 4e34: 4628 mov r0, r5 + 4e36: 47c0 blx r8 + 4e38: 462c mov r4, r5 + 4e3a: 4605 mov r5, r0 + 4e3c: e7ea b.n 4e14 + lv_refr_obj(i, mask_p); + 4e3e: 4631 mov r1, r6 + 4e40: 4620 mov r0, r4 + 4e42: 47b8 blx r7 + 4e44: e7eb b.n 4e1e + 4e46: bf00 nop + 4e48: 20008100 .word 0x20008100 + 4e4c: 00001871 .word 0x00001871 + 4e50: 00004cf9 .word 0x00004cf9 + 4e54: 00002125 .word 0x00002125 + 4e58: 0000e6d5 .word 0x0000e6d5 + +00004e5c : +{ + 4e5c: b573 push {r0, r1, r4, r5, r6, lr} + lv_disp_buf_t * vdb = lv_disp_get_buf(disp_refr); + 4e5e: 4c1a ldr r4, [pc, #104] ; (4ec8 ) + 4e60: 4b1a ldr r3, [pc, #104] ; (4ecc ) +{ + 4e62: 4606 mov r6, r0 + lv_disp_buf_t * vdb = lv_disp_get_buf(disp_refr); + 4e64: 6820 ldr r0, [r4, #0] + 4e66: 4798 blx r3 + if(lv_disp_is_double_buf(disp_refr) == false) { + 4e68: 4b19 ldr r3, [pc, #100] ; (4ed0 ) + lv_disp_buf_t * vdb = lv_disp_get_buf(disp_refr); + 4e6a: 4605 mov r5, r0 + if(lv_disp_is_double_buf(disp_refr) == false) { + 4e6c: 6820 ldr r0, [r4, #0] + 4e6e: 4798 blx r3 + 4e70: b320 cbz r0, 4ebc + _lv_area_intersect(&start_mask, area_p, &vdb->area); + 4e72: f105 0210 add.w r2, r5, #16 + 4e76: 4631 mov r1, r6 + 4e78: 4b16 ldr r3, [pc, #88] ; (4ed4 ) + lv_refr_obj_and_children(top_p, &start_mask); + 4e7a: 4d17 ldr r5, [pc, #92] ; (4ed8 ) + _lv_area_intersect(&start_mask, area_p, &vdb->area); + 4e7c: 4668 mov r0, sp + 4e7e: 4798 blx r3 + top_p = lv_refr_get_top_obj(&start_mask, lv_disp_get_scr_act(disp_refr)); + 4e80: 4b16 ldr r3, [pc, #88] ; (4edc ) + 4e82: 6820 ldr r0, [r4, #0] + 4e84: 4798 blx r3 + 4e86: 4b16 ldr r3, [pc, #88] ; (4ee0 ) + 4e88: 4601 mov r1, r0 + 4e8a: 4668 mov r0, sp + 4e8c: 4798 blx r3 + lv_refr_obj_and_children(top_p, &start_mask); + 4e8e: 4669 mov r1, sp + 4e90: 47a8 blx r5 + lv_refr_obj_and_children(lv_disp_get_layer_top(disp_refr), &start_mask); + 4e92: 4b14 ldr r3, [pc, #80] ; (4ee4 ) + 4e94: 6820 ldr r0, [r4, #0] + 4e96: 4798 blx r3 + 4e98: 4669 mov r1, sp + 4e9a: 47a8 blx r5 + lv_refr_obj_and_children(lv_disp_get_layer_sys(disp_refr), &start_mask); + 4e9c: 4b12 ldr r3, [pc, #72] ; (4ee8 ) + 4e9e: 6820 ldr r0, [r4, #0] + 4ea0: 4798 blx r3 + 4ea2: 4669 mov r1, sp + 4ea4: 47a8 blx r5 + if(lv_disp_is_true_double_buf(disp_refr) == false) { + 4ea6: 6820 ldr r0, [r4, #0] + 4ea8: 4b10 ldr r3, [pc, #64] ; (4eec ) + 4eaa: 4798 blx r3 + 4eac: b908 cbnz r0, 4eb2 + lv_refr_vdb_flush(); + 4eae: 4b10 ldr r3, [pc, #64] ; (4ef0 ) + 4eb0: 4798 blx r3 +} + 4eb2: b002 add sp, #8 + 4eb4: bd70 pop {r4, r5, r6, pc} + if(disp_refr->driver.wait_cb) disp_refr->driver.wait_cb(&disp_refr->driver); + 4eb6: 69c3 ldr r3, [r0, #28] + 4eb8: b10b cbz r3, 4ebe + 4eba: 4798 blx r3 + 4ebc: 6820 ldr r0, [r4, #0] + while(vdb->flushing) { + 4ebe: 69ab ldr r3, [r5, #24] + 4ec0: 2b00 cmp r3, #0 + 4ec2: d1f8 bne.n 4eb6 + 4ec4: e7d5 b.n 4e72 + 4ec6: bf00 nop + 4ec8: 20008100 .word 0x20008100 + 4ecc: 0000d9e1 .word 0x0000d9e1 + 4ed0: 0000d9e5 .word 0x0000d9e5 + 4ed4: 0000de8d .word 0x0000de8d + 4ed8: 00004de9 .word 0x00004de9 + 4edc: 00001871 .word 0x00001871 + 4ee0: 00004c85 .word 0x00004c85 + 4ee4: 000018ad .word 0x000018ad + 4ee8: 000018e9 .word 0x000018e9 + 4eec: 0000d9f5 .word 0x0000d9f5 + 4ef0: 00004c19 .word 0x00004c19 + +00004ef4 : + 4ef4: 3901 subs r1, #1 + 4ef6: f100 0308 add.w r3, r0, #8 + *d8 = *s8; + 4efa: f811 2f01 ldrb.w r2, [r1, #1]! + 4efe: f800 2b01 strb.w r2, [r0], #1 + while(len) { + 4f02: 4298 cmp r0, r3 + 4f04: d1f9 bne.n 4efa +} + 4f06: 4770 bx lr + +00004f08 <_lv_refr_init>: +} + 4f08: 4770 bx lr + ... + +00004f0c <_lv_inv_area>: +{ + 4f0c: e92d 41ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, lr} + 4f10: 460d mov r5, r1 + if(!disp) disp = lv_disp_get_default(); + 4f12: 4604 mov r4, r0 + 4f14: b918 cbnz r0, 4f1e <_lv_inv_area+0x12> + 4f16: 4b2d ldr r3, [pc, #180] ; (4fcc <_lv_inv_area+0xc0>) + 4f18: 4798 blx r3 + if(!disp) return; + 4f1a: 4604 mov r4, r0 + 4f1c: b130 cbz r0, 4f2c <_lv_inv_area+0x20> + if(area_p == NULL) { + 4f1e: b945 cbnz r5, 4f32 <_lv_inv_area+0x26> + disp->inv_p = 0; + 4f20: f8b4 3168 ldrh.w r3, [r4, #360] ; 0x168 + 4f24: f365 0309 bfi r3, r5, #0, #10 + 4f28: f8a4 3168 strh.w r3, [r4, #360] ; 0x168 +} + 4f2c: b004 add sp, #16 + 4f2e: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + scr_area.x1 = 0; + 4f32: 2300 movs r3, #0 + 4f34: 9300 str r3, [sp, #0] + scr_area.x2 = lv_disp_get_hor_res(disp) - 1; + 4f36: 4620 mov r0, r4 + 4f38: 4b25 ldr r3, [pc, #148] ; (4fd0 <_lv_inv_area+0xc4>) + 4f3a: 4798 blx r3 + 4f3c: 3801 subs r0, #1 + scr_area.y2 = lv_disp_get_ver_res(disp) - 1; + 4f3e: 4b25 ldr r3, [pc, #148] ; (4fd4 <_lv_inv_area+0xc8>) + scr_area.x2 = lv_disp_get_hor_res(disp) - 1; + 4f40: f8ad 0004 strh.w r0, [sp, #4] + scr_area.y2 = lv_disp_get_ver_res(disp) - 1; + 4f44: 4620 mov r0, r4 + 4f46: 4798 blx r3 + 4f48: 3801 subs r0, #1 + 4f4a: f8ad 0006 strh.w r0, [sp, #6] + suc = _lv_area_intersect(&com_area, area_p, &scr_area); + 4f4e: 4b22 ldr r3, [pc, #136] ; (4fd8 <_lv_inv_area+0xcc>) + 4f50: 466a mov r2, sp + 4f52: 4629 mov r1, r5 + 4f54: a802 add r0, sp, #8 + 4f56: 4798 blx r3 + if(suc != false) { + 4f58: 2800 cmp r0, #0 + 4f5a: d0e7 beq.n 4f2c <_lv_inv_area+0x20> + if(disp->driver.rounder_cb) disp->driver.rounder_cb(&disp->driver, &com_area); + 4f5c: 6923 ldr r3, [r4, #16] + 4f5e: b113 cbz r3, 4f66 <_lv_inv_area+0x5a> + 4f60: a902 add r1, sp, #8 + 4f62: 4620 mov r0, r4 + 4f64: 4798 blx r3 + 4f66: f104 0548 add.w r5, r4, #72 ; 0x48 + if(_lv_area_is_in(&com_area, &disp->inv_areas[i], 0) != false) return; + 4f6a: f8df 8078 ldr.w r8, [pc, #120] ; 4fe4 <_lv_inv_area+0xd8> +{ + 4f6e: 2600 movs r6, #0 + 4f70: 462f mov r7, r5 + for(i = 0; i < disp->inv_p; i++) { + 4f72: f8b4 3168 ldrh.w r3, [r4, #360] ; 0x168 + 4f76: b2b2 uxth r2, r6 + 4f78: f3c3 0009 ubfx r0, r3, #0, #10 + 4f7c: 4290 cmp r0, r2 + 4f7e: d81c bhi.n 4fba <_lv_inv_area+0xae> + if(disp->inv_p < LV_INV_BUF_SIZE) { + 4f80: 281f cmp r0, #31 + lv_area_copy(&disp->inv_areas[disp->inv_p], &com_area); + 4f82: bf9b ittet ls + 4f84: 3009 addls r0, #9 + 4f86: f3c0 0009 ubfxls r0, r0, #0, #10 + disp->inv_p = 0; + 4f8a: f36f 0309 bfchi r3, #0, #10 + lv_area_copy(&disp->inv_areas[disp->inv_p], &com_area); + 4f8e: a902 addls r1, sp, #8 + 4f90: bf91 iteee ls + 4f92: eb04 00c0 addls.w r0, r4, r0, lsl #3 + disp->inv_p = 0; + 4f96: f8a4 3168 strhhi.w r3, [r4, #360] ; 0x168 + lv_area_copy(&disp->inv_areas[disp->inv_p], &scr_area); + 4f9a: 4669 movhi r1, sp + 4f9c: 4638 movhi r0, r7 + 4f9e: 4a0f ldr r2, [pc, #60] ; (4fdc <_lv_inv_area+0xd0>) + 4fa0: 4790 blx r2 + disp->inv_p++; + 4fa2: f8b4 3168 ldrh.w r3, [r4, #360] ; 0x168 + lv_task_set_prio(disp->refr_task, LV_REFR_TASK_PRIO); + 4fa6: 6ae0 ldr r0, [r4, #44] ; 0x2c + disp->inv_p++; + 4fa8: 1c5a adds r2, r3, #1 + 4faa: f362 0309 bfi r3, r2, #0, #10 + 4fae: f8a4 3168 strh.w r3, [r4, #360] ; 0x168 + lv_task_set_prio(disp->refr_task, LV_REFR_TASK_PRIO); + 4fb2: 2103 movs r1, #3 + 4fb4: 4b0a ldr r3, [pc, #40] ; (4fe0 <_lv_inv_area+0xd4>) + 4fb6: 4798 blx r3 + 4fb8: e7b8 b.n 4f2c <_lv_inv_area+0x20> + if(_lv_area_is_in(&com_area, &disp->inv_areas[i], 0) != false) return; + 4fba: 4629 mov r1, r5 + 4fbc: 2200 movs r2, #0 + 4fbe: a802 add r0, sp, #8 + 4fc0: 47c0 blx r8 + 4fc2: 3601 adds r6, #1 + 4fc4: 3508 adds r5, #8 + 4fc6: 2800 cmp r0, #0 + 4fc8: d0d3 beq.n 4f72 <_lv_inv_area+0x66> + 4fca: e7af b.n 4f2c <_lv_inv_area+0x20> + 4fcc: 0000d8fd .word 0x0000d8fd + 4fd0: 0000d909 .word 0x0000d909 + 4fd4: 0000d92d .word 0x0000d92d + 4fd8: 0000de8d .word 0x0000de8d + 4fdc: 00004ef5 .word 0x00004ef5 + 4fe0: 0000fb6d .word 0x0000fb6d + 4fe4: 0000e091 .word 0x0000e091 + +00004fe8 <_lv_refr_get_disp_refreshing>: +} + 4fe8: 4b01 ldr r3, [pc, #4] ; (4ff0 <_lv_refr_get_disp_refreshing+0x8>) + 4fea: 6818 ldr r0, [r3, #0] + 4fec: 4770 bx lr + 4fee: bf00 nop + 4ff0: 20008100 .word 0x20008100 + +00004ff4 <_lv_disp_refr_task>: +{ + 4ff4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 4ff8: ed2d 8b02 vpush {d8} + uint32_t start = lv_tick_get(); + 4ffc: 4b82 ldr r3, [pc, #520] ; (5208 <_lv_disp_refr_task+0x214>) + disp_refr = task->user_data; + 4ffe: 4c83 ldr r4, [pc, #524] ; (520c <_lv_disp_refr_task+0x218>) +{ + 5000: b08b sub sp, #44 ; 0x2c + 5002: 4605 mov r5, r0 + uint32_t start = lv_tick_get(); + 5004: 4798 blx r3 + disp_refr = task->user_data; + 5006: 68eb ldr r3, [r5, #12] + 5008: 6023 str r3, [r4, #0] + lv_task_set_prio(task, LV_TASK_PRIO_OFF); + 500a: 2100 movs r1, #0 + 500c: 4b80 ldr r3, [pc, #512] ; (5210 <_lv_disp_refr_task+0x21c>) + uint32_t start = lv_tick_get(); + 500e: ee08 0a90 vmov s17, r0 + lv_task_set_prio(task, LV_TASK_PRIO_OFF); + 5012: 4628 mov r0, r5 + 5014: 4798 blx r3 + if(disp_refr->act_scr == NULL) { + 5016: 6823 ldr r3, [r4, #0] + 5018: 6bd9 ldr r1, [r3, #60] ; 0x3c + 501a: 2900 cmp r1, #0 + 501c: f040 808b bne.w 5136 <_lv_disp_refr_task+0x142> + disp_refr->inv_p = 0; + 5020: f8b3 2168 ldrh.w r2, [r3, #360] ; 0x168 + 5024: f361 0209 bfi r2, r1, #0, #10 + 5028: f8a3 2168 strh.w r2, [r3, #360] ; 0x168 +} + 502c: b00b add sp, #44 ; 0x2c + 502e: ecbd 8b02 vpop {d8} + 5032: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + if(disp_refr->inv_area_joined[join_in] != 0) continue; + 5036: 4433 add r3, r6 + 5038: f893 5148 ldrb.w r5, [r3, #328] ; 0x148 + 503c: 2d00 cmp r5, #0 + 503e: d03c beq.n 50ba <_lv_disp_refr_task+0xc6> + for(join_in = 0; join_in < disp_refr->inv_p; join_in++) { + 5040: 3601 adds r6, #1 + 5042: 6823 ldr r3, [r4, #0] + 5044: f8b3 2168 ldrh.w r2, [r3, #360] ; 0x168 + 5048: f3c2 0109 ubfx r1, r2, #0, #10 + 504c: 428e cmp r6, r1 + 504e: d3f2 bcc.n 5036 <_lv_disp_refr_task+0x42> + px_num = 0; + 5050: 2000 movs r0, #0 + 5052: 6060 str r0, [r4, #4] + if(disp_refr->inv_p == 0) return; + 5054: 2900 cmp r1, #0 + 5056: d171 bne.n 513c <_lv_disp_refr_task+0x148> + if(disp_refr->inv_p != 0) { + 5058: 4f6c ldr r7, [pc, #432] ; (520c <_lv_disp_refr_task+0x218>) + 505a: 6838 ldr r0, [r7, #0] + 505c: f8b0 3168 ldrh.w r3, [r0, #360] ; 0x168 + 5060: f3c3 0309 ubfx r3, r3, #0, #10 + 5064: b303 cbz r3, 50a8 <_lv_disp_refr_task+0xb4> + if(lv_disp_is_true_double_buf(disp_refr) && disp_refr->driver.set_px_cb == NULL) { + 5066: 4b6b ldr r3, [pc, #428] ; (5214 <_lv_disp_refr_task+0x220>) + 5068: 4798 blx r3 + 506a: 2800 cmp r0, #0 + 506c: f040 81a1 bne.w 53b2 <_lv_disp_refr_task+0x3be> + _lv_memset_00(disp_refr->inv_areas, sizeof(disp_refr->inv_areas)); + 5070: 6820 ldr r0, [r4, #0] + 5072: 4d69 ldr r5, [pc, #420] ; (5218 <_lv_disp_refr_task+0x224>) + 5074: f44f 7180 mov.w r1, #256 ; 0x100 + 5078: 3048 adds r0, #72 ; 0x48 + 507a: 47a8 blx r5 + _lv_memset_00(disp_refr->inv_area_joined, sizeof(disp_refr->inv_area_joined)); + 507c: 6820 ldr r0, [r4, #0] + 507e: 2120 movs r1, #32 + 5080: f500 70a4 add.w r0, r0, #328 ; 0x148 + 5084: 47a8 blx r5 + disp_refr->inv_p = 0; + 5086: 6823 ldr r3, [r4, #0] + 5088: f8b3 2168 ldrh.w r2, [r3, #360] ; 0x168 + 508c: f36f 0209 bfc r2, #0, #10 + 5090: f8a3 2168 strh.w r2, [r3, #360] ; 0x168 + elaps = lv_tick_elaps(start); + 5094: ee18 0a90 vmov r0, s17 + 5098: 4b60 ldr r3, [pc, #384] ; (521c <_lv_disp_refr_task+0x228>) + 509a: 4798 blx r3 + 509c: 4601 mov r1, r0 + if(disp_refr->driver.monitor_cb) { + 509e: 6820 ldr r0, [r4, #0] + 50a0: 6983 ldr r3, [r0, #24] + 50a2: 2b00 cmp r3, #0 + 50a4: f040 81dd bne.w 5462 <_lv_disp_refr_task+0x46e> + _lv_mem_buf_free_all(); + 50a8: 4b5d ldr r3, [pc, #372] ; (5220 <_lv_disp_refr_task+0x22c>) + 50aa: 4798 blx r3 + _lv_font_clean_up_fmt_txt(); + 50ac: 4b5d ldr r3, [pc, #372] ; (5224 <_lv_disp_refr_task+0x230>) +} + 50ae: b00b add sp, #44 ; 0x2c + 50b0: ecbd 8b02 vpop {d8} + 50b4: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + _lv_font_clean_up_fmt_txt(); + 50b8: 4718 bx r3 + 50ba: ea4f 09c6 mov.w r9, r6, lsl #3 + if(lv_area_get_size(&joined_area) < (lv_area_get_size(&disp_refr->inv_areas[join_in]) + + 50be: f8df a184 ldr.w sl, [pc, #388] ; 5244 <_lv_disp_refr_task+0x250> + 50c2: f109 0948 add.w r9, r9, #72 ; 0x48 + for(join_from = 0; join_from < disp_refr->inv_p; join_from++) { + 50c6: 6820 ldr r0, [r4, #0] + 50c8: f8b0 3168 ldrh.w r3, [r0, #360] ; 0x168 + 50cc: f3c3 0309 ubfx r3, r3, #0, #10 + 50d0: 429d cmp r5, r3 + 50d2: d2b5 bcs.n 5040 <_lv_disp_refr_task+0x4c> + if(disp_refr->inv_area_joined[join_from] != 0 || join_in == join_from) { + 50d4: 1943 adds r3, r0, r5 + 50d6: f893 3148 ldrb.w r3, [r3, #328] ; 0x148 + 50da: bb53 cbnz r3, 5132 <_lv_disp_refr_task+0x13e> + 50dc: 42ae cmp r6, r5 + 50de: d028 beq.n 5132 <_lv_disp_refr_task+0x13e> + if(_lv_area_is_on(&disp_refr->inv_areas[join_in], &disp_refr->inv_areas[join_from]) == false) { + 50e0: ea4f 0bc5 mov.w fp, r5, lsl #3 + 50e4: f10b 0b48 add.w fp, fp, #72 ; 0x48 + 50e8: eb00 010b add.w r1, r0, fp + 50ec: 4448 add r0, r9 + 50ee: 47b8 blx r7 + 50f0: b1f8 cbz r0, 5132 <_lv_disp_refr_task+0x13e> + _lv_area_join(&joined_area, &disp_refr->inv_areas[join_in], &disp_refr->inv_areas[join_from]); + 50f2: 6821 ldr r1, [r4, #0] + 50f4: 4b4c ldr r3, [pc, #304] ; (5228 <_lv_disp_refr_task+0x234>) + 50f6: eb01 020b add.w r2, r1, fp + 50fa: a808 add r0, sp, #32 + 50fc: 4449 add r1, r9 + 50fe: 4798 blx r3 + if(lv_area_get_size(&joined_area) < (lv_area_get_size(&disp_refr->inv_areas[join_in]) + + 5100: a808 add r0, sp, #32 + 5102: 47d0 blx sl + 5104: 4680 mov r8, r0 + 5106: 6820 ldr r0, [r4, #0] + 5108: 4448 add r0, r9 + 510a: 47d0 blx sl + 510c: 9003 str r0, [sp, #12] + lv_area_get_size(&disp_refr->inv_areas[join_from]))) { + 510e: 6820 ldr r0, [r4, #0] + 5110: 4458 add r0, fp + 5112: 47d0 blx sl + if(lv_area_get_size(&joined_area) < (lv_area_get_size(&disp_refr->inv_areas[join_in]) + + 5114: 9b03 ldr r3, [sp, #12] + 5116: 4418 add r0, r3 + 5118: 4580 cmp r8, r0 + 511a: d20a bcs.n 5132 <_lv_disp_refr_task+0x13e> + lv_area_copy(&disp_refr->inv_areas[join_in], &joined_area); + 511c: f8d4 b000 ldr.w fp, [r4] + 5120: 4b42 ldr r3, [pc, #264] ; (522c <_lv_disp_refr_task+0x238>) + 5122: eb0b 0009 add.w r0, fp, r9 + 5126: a908 add r1, sp, #32 + disp_refr->inv_area_joined[join_from] = 1; + 5128: 44ab add fp, r5 + lv_area_copy(&disp_refr->inv_areas[join_in], &joined_area); + 512a: 4798 blx r3 + disp_refr->inv_area_joined[join_from] = 1; + 512c: 2301 movs r3, #1 + 512e: f88b 3148 strb.w r3, [fp, #328] ; 0x148 + for(join_from = 0; join_from < disp_refr->inv_p; join_from++) { + 5132: 3501 adds r5, #1 + 5134: e7c7 b.n 50c6 <_lv_disp_refr_task+0xd2> + if(_lv_area_is_on(&disp_refr->inv_areas[join_in], &disp_refr->inv_areas[join_from]) == false) { + 5136: 4f3e ldr r7, [pc, #248] ; (5230 <_lv_disp_refr_task+0x23c>) + for(join_in = 0; join_in < disp_refr->inv_p; join_in++) { + 5138: 2600 movs r6, #0 + 513a: e782 b.n 5042 <_lv_disp_refr_task+0x4e> + for(i = disp_refr->inv_p - 1; i >= 0; i--) { + 513c: 1e4f subs r7, r1, #1 + if(disp_refr->inv_area_joined[i] == 0) { + 513e: f503 72a4 add.w r2, r3, #328 ; 0x148 + for(i = disp_refr->inv_p - 1; i >= 0; i--) { + 5142: 1c79 adds r1, r7, #1 + 5144: d15b bne.n 51fe <_lv_disp_refr_task+0x20a> + int32_t last_i = 0; + 5146: 2700 movs r7, #0 + disp_refr->driver.buffer->last_area = 0; + 5148: 685b ldr r3, [r3, #4] + for(i = 0; i < disp_refr->inv_p; i++) { + 514a: f8df 80c0 ldr.w r8, [pc, #192] ; 520c <_lv_disp_refr_task+0x218> + disp_refr->driver.buffer->last_area = 0; + 514e: f893 2020 ldrb.w r2, [r3, #32] + 5152: f36f 0200 bfc r2, #0, #1 + 5156: f883 2020 strb.w r2, [r3, #32] + disp_refr->driver.buffer->last_part = 0; + 515a: f893 2020 ldrb.w r2, [r3, #32] + 515e: f36f 0241 bfc r2, #1, #1 + 5162: f883 2020 strb.w r2, [r3, #32] + for(i = 0; i < disp_refr->inv_p; i++) { + 5166: f04f 0b00 mov.w fp, #0 + 516a: f8d8 5000 ldr.w r5, [r8] + 516e: f8b5 3168 ldrh.w r3, [r5, #360] ; 0x168 + 5172: f3c3 0309 ubfx r3, r3, #0, #10 + 5176: 459b cmp fp, r3 + 5178: f6bf af6e bge.w 5058 <_lv_disp_refr_task+0x64> + if(disp_refr->inv_area_joined[i] == 0) { + 517c: eb05 030b add.w r3, r5, fp + 5180: f893 3148 ldrb.w r3, [r3, #328] ; 0x148 + 5184: 2b00 cmp r3, #0 + 5186: f040 80c6 bne.w 5316 <_lv_disp_refr_task+0x322> + if(i == last_i) disp_refr->driver.buffer->last_area = 1; + 518a: 686b ldr r3, [r5, #4] + 518c: 45bb cmp fp, r7 + 518e: bf02 ittt eq + 5190: f893 2020 ldrbeq.w r2, [r3, #32] + 5194: f042 0201 orreq.w r2, r2, #1 + 5198: f883 2020 strbeq.w r2, [r3, #32] + disp_refr->driver.buffer->last_part = 0; + 519c: f893 2020 ldrb.w r2, [r3, #32] + 51a0: ea4f 09cb mov.w r9, fp, lsl #3 + 51a4: f36f 0241 bfc r2, #1, #1 + 51a8: f883 2020 strb.w r2, [r3, #32] + lv_refr_area(&disp_refr->inv_areas[i]); + 51ac: f109 0348 add.w r3, r9, #72 ; 0x48 + 51b0: 9304 str r3, [sp, #16] + 51b2: 18eb adds r3, r5, r3 + 51b4: ee08 3a10 vmov s16, r3 + if(lv_disp_is_true_double_buf(disp_refr)) { + 51b8: 4628 mov r0, r5 + 51ba: 4b16 ldr r3, [pc, #88] ; (5214 <_lv_disp_refr_task+0x220>) + 51bc: 4798 blx r3 + 51be: 4b1d ldr r3, [pc, #116] ; (5234 <_lv_disp_refr_task+0x240>) + 51c0: 2800 cmp r0, #0 + 51c2: d041 beq.n 5248 <_lv_disp_refr_task+0x254> + lv_disp_buf_t * vdb = lv_disp_get_buf(disp_refr); + 51c4: 6820 ldr r0, [r4, #0] + 51c6: 4798 blx r3 + vdb->area.x1 = 0; + 51c8: 2600 movs r6, #0 + lv_disp_buf_t * vdb = lv_disp_get_buf(disp_refr); + 51ca: 4605 mov r5, r0 + vdb->area.x2 = lv_disp_get_hor_res(disp_refr) - 1; + 51cc: 4b1a ldr r3, [pc, #104] ; (5238 <_lv_disp_refr_task+0x244>) + vdb->area.x1 = 0; + 51ce: 8206 strh r6, [r0, #16] + vdb->area.x2 = lv_disp_get_hor_res(disp_refr) - 1; + 51d0: 6820 ldr r0, [r4, #0] + 51d2: 4798 blx r3 + 51d4: 3801 subs r0, #1 + vdb->area.y2 = lv_disp_get_ver_res(disp_refr) - 1; + 51d6: 4b19 ldr r3, [pc, #100] ; (523c <_lv_disp_refr_task+0x248>) + vdb->area.x2 = lv_disp_get_hor_res(disp_refr) - 1; + 51d8: 82a8 strh r0, [r5, #20] + vdb->area.y1 = 0; + 51da: 826e strh r6, [r5, #18] + vdb->area.y2 = lv_disp_get_ver_res(disp_refr) - 1; + 51dc: 6820 ldr r0, [r4, #0] + 51de: 4798 blx r3 + disp_refr->driver.buffer->last_part = 1; + 51e0: 6823 ldr r3, [r4, #0] + vdb->area.y2 = lv_disp_get_ver_res(disp_refr) - 1; + 51e2: 3801 subs r0, #1 + disp_refr->driver.buffer->last_part = 1; + 51e4: 685a ldr r2, [r3, #4] + vdb->area.y2 = lv_disp_get_ver_res(disp_refr) - 1; + 51e6: 82e8 strh r0, [r5, #22] + disp_refr->driver.buffer->last_part = 1; + 51e8: f892 3020 ldrb.w r3, [r2, #32] + 51ec: f043 0302 orr.w r3, r3, #2 + 51f0: f882 3020 strb.w r3, [r2, #32] + lv_refr_area_part(area_p); + 51f4: ee18 0a10 vmov r0, s16 + 51f8: 4b11 ldr r3, [pc, #68] ; (5240 <_lv_disp_refr_task+0x24c>) + 51fa: 4798 blx r3 + 51fc: e07e b.n 52fc <_lv_disp_refr_task+0x308> + if(disp_refr->inv_area_joined[i] == 0) { + 51fe: 5dd1 ldrb r1, [r2, r7] + 5200: 2900 cmp r1, #0 + 5202: d0a1 beq.n 5148 <_lv_disp_refr_task+0x154> + for(i = disp_refr->inv_p - 1; i >= 0; i--) { + 5204: 3f01 subs r7, #1 + 5206: e79c b.n 5142 <_lv_disp_refr_task+0x14e> + 5208: 0000da49 .word 0x0000da49 + 520c: 20008100 .word 0x20008100 + 5210: 0000fb6d .word 0x0000fb6d + 5214: 0000d9f5 .word 0x0000d9f5 + 5218: 0000f019 .word 0x0000f019 + 521c: 0000da5d .word 0x0000da5d + 5220: 0000ebdd .word 0x0000ebdd + 5224: 0000d741 .word 0x0000d741 + 5228: 0000dee1 .word 0x0000dee1 + 522c: 00004ef5 .word 0x00004ef5 + 5230: 0000e055 .word 0x0000e055 + 5234: 0000d9e1 .word 0x0000d9e1 + 5238: 0000d909 .word 0x0000d909 + 523c: 0000d92d .word 0x0000d92d + 5240: 00004e5d .word 0x00004e5d + 5244: 0000de71 .word 0x0000de71 + lv_disp_buf_t * vdb = lv_disp_get_buf(disp_refr); + 5248: 444d add r5, r9 + 524a: 6820 ldr r0, [r4, #0] + 524c: 4798 blx r3 + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + 524e: f8b5 904c ldrh.w r9, [r5, #76] ; 0x4c + 5252: f8b5 3048 ldrh.w r3, [r5, #72] ; 0x48 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + 5256: f9b5 204e ldrsh.w r2, [r5, #78] ; 0x4e + 525a: 9203 str r2, [sp, #12] + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + 525c: f109 0901 add.w r9, r9, #1 + 5260: eba9 0903 sub.w r9, r9, r3 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + 5264: f8b5 304a ldrh.w r3, [r5, #74] ; 0x4a + 5268: f102 0a01 add.w sl, r2, #1 + 526c: ebaa 0a03 sub.w sl, sl, r3 + 5270: 4606 mov r6, r0 + area_p->y2 >= lv_disp_get_ver_res(disp_refr) ? lv_disp_get_ver_res(disp_refr) - 1 : area_p->y2; + 5272: 4b7d ldr r3, [pc, #500] ; (5468 <_lv_disp_refr_task+0x474>) + 5274: 6820 ldr r0, [r4, #0] + 5276: 4798 blx r3 + lv_coord_t y2 = + 5278: 9a03 ldr r2, [sp, #12] + 527a: 4b7b ldr r3, [pc, #492] ; (5468 <_lv_disp_refr_task+0x474>) + 527c: 4282 cmp r2, r0 + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + 527e: fa0f f989 sxth.w r9, r9 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + 5282: fa0f fa8a sxth.w sl, sl + 5286: db49 blt.n 531c <_lv_disp_refr_task+0x328> + area_p->y2 >= lv_disp_get_ver_res(disp_refr) ? lv_disp_get_ver_res(disp_refr) - 1 : area_p->y2; + 5288: 6820 ldr r0, [r4, #0] + 528a: 4798 blx r3 + 528c: 3801 subs r0, #1 + lv_coord_t y2 = + 528e: b203 sxth r3, r0 + int32_t max_row = (uint32_t)vdb->size / w; + 5290: 68f2 ldr r2, [r6, #12] + 5292: fbb2 f2f9 udiv r2, r2, r9 + 5296: 4552 cmp r2, sl + 5298: bfa8 it ge + 529a: 4652 movge r2, sl + 529c: 9203 str r2, [sp, #12] + if(disp_refr->driver.rounder_cb) { + 529e: f8d8 2000 ldr.w r2, [r8] + 52a2: 6912 ldr r2, [r2, #16] + 52a4: 2a00 cmp r2, #0 + 52a6: d040 beq.n 532a <_lv_disp_refr_task+0x336> + tmp.x1 = 0; + 52a8: 2200 movs r2, #0 + lv_coord_t h_tmp = max_row; + 52aa: f9bd 900c ldrsh.w r9, [sp, #12] + tmp.x1 = 0; + 52ae: 9208 str r2, [sp, #32] + tmp.x2 = 0; + 52b0: f8ad 2024 strh.w r2, [sp, #36] ; 0x24 + disp_refr->driver.rounder_cb(&disp_refr->driver, &tmp); + 52b4: f8d8 0000 ldr.w r0, [r8] + 52b8: 9305 str r3, [sp, #20] + tmp.y2 = h_tmp - 1; + 52ba: 46ca mov sl, r9 + 52bc: f109 39ff add.w r9, r9, #4294967295 ; 0xffffffff + 52c0: fa0f f989 sxth.w r9, r9 + disp_refr->driver.rounder_cb(&disp_refr->driver, &tmp); + 52c4: 6902 ldr r2, [r0, #16] + tmp.y2 = h_tmp - 1; + 52c6: f8ad 9026 strh.w r9, [sp, #38] ; 0x26 + disp_refr->driver.rounder_cb(&disp_refr->driver, &tmp); + 52ca: a908 add r1, sp, #32 + 52cc: 4790 blx r2 + 52ce: f9bd 1026 ldrsh.w r1, [sp, #38] ; 0x26 + 52d2: f8bd 2022 ldrh.w r2, [sp, #34] ; 0x22 + if(lv_area_get_height(&tmp) <= max_row) break; + 52d6: 9b03 ldr r3, [sp, #12] + 52d8: 3101 adds r1, #1 + 52da: 1a8a subs r2, r1, r2 + 52dc: b212 sxth r2, r2 + 52de: 4293 cmp r3, r2 + 52e0: 9b05 ldr r3, [sp, #20] + 52e2: da1e bge.n 5322 <_lv_disp_refr_task+0x32e> + } while(h_tmp > 0); + 52e4: f1b9 0f00 cmp.w r9, #0 + 52e8: dce4 bgt.n 52b4 <_lv_disp_refr_task+0x2c0> + LV_LOG_WARN("Can't set VDB height using the round function. (Wrong round_cb or to " + 52ea: 4b60 ldr r3, [pc, #384] ; (546c <_lv_disp_refr_task+0x478>) + 52ec: 9300 str r3, [sp, #0] + 52ee: 4960 ldr r1, [pc, #384] ; (5470 <_lv_disp_refr_task+0x47c>) + 52f0: 4b60 ldr r3, [pc, #384] ; (5474 <_lv_disp_refr_task+0x480>) + 52f2: 4d61 ldr r5, [pc, #388] ; (5478 <_lv_disp_refr_task+0x484>) + 52f4: f44f 72cf mov.w r2, #414 ; 0x19e + 52f8: 2002 movs r0, #2 + 52fa: 47a8 blx r5 + if(disp_refr->driver.monitor_cb) px_num += lv_area_get_size(&disp_refr->inv_areas[i]); + 52fc: f8d8 0000 ldr.w r0, [r8] + 5300: 6983 ldr r3, [r0, #24] + 5302: b143 cbz r3, 5316 <_lv_disp_refr_task+0x322> + 5304: 9b04 ldr r3, [sp, #16] + 5306: 4418 add r0, r3 + 5308: 4b5c ldr r3, [pc, #368] ; (547c <_lv_disp_refr_task+0x488>) + 530a: 4798 blx r3 + 530c: f8d8 3004 ldr.w r3, [r8, #4] + 5310: 4418 add r0, r3 + 5312: f8c8 0004 str.w r0, [r8, #4] + for(i = 0; i < disp_refr->inv_p; i++) { + 5316: f10b 0b01 add.w fp, fp, #1 + 531a: e726 b.n 516a <_lv_disp_refr_task+0x176> + lv_coord_t y2 = + 531c: f9b5 304e ldrsh.w r3, [r5, #78] ; 0x4e + 5320: e7b6 b.n 5290 <_lv_disp_refr_task+0x29c> + if(h_tmp <= 0) { + 5322: f1ba 0f00 cmp.w sl, #0 + 5326: dde0 ble.n 52ea <_lv_disp_refr_task+0x2f6> + max_row = tmp.y2 + 1; + 5328: 9103 str r1, [sp, #12] + vdb->area.y2 = row + max_row - 1; + 532a: f8bd 100c ldrh.w r1, [sp, #12] + for(row = area_p->y1; row + max_row - 1 <= y2; row += max_row) { + 532e: f9b5 204a ldrsh.w r2, [r5, #74] ; 0x4a + 5332: 1e48 subs r0, r1, #1 + lv_coord_t row_last = 0; + 5334: f04f 0900 mov.w r9, #0 + 5338: 9005 str r0, [sp, #20] + for(row = area_p->y1; row + max_row - 1 <= y2; row += max_row) { + 533a: 9803 ldr r0, [sp, #12] + 533c: 1810 adds r0, r2, r0 + 533e: 3801 subs r0, #1 + 5340: 4298 cmp r0, r3 + 5342: dd0c ble.n 535e <_lv_disp_refr_task+0x36a> + if(y2 != row_last) { + 5344: 454b cmp r3, r9 + 5346: d0d9 beq.n 52fc <_lv_disp_refr_task+0x308> + vdb->area.x1 = area_p->x1; + 5348: f9b5 0048 ldrsh.w r0, [r5, #72] ; 0x48 + if(y2 == row_last) disp_refr->driver.buffer->last_part = 1; + 534c: 6821 ldr r1, [r4, #0] + vdb->area.x1 = area_p->x1; + 534e: 8230 strh r0, [r6, #16] + vdb->area.x2 = area_p->x2; + 5350: f9b5 004c ldrsh.w r0, [r5, #76] ; 0x4c + 5354: 82b0 strh r0, [r6, #20] + vdb->area.y1 = row; + 5356: 8272 strh r2, [r6, #18] + vdb->area.y2 = y2; + 5358: 82f3 strh r3, [r6, #22] + disp_refr->driver.buffer->last_part = 1; + 535a: 684a ldr r2, [r1, #4] + 535c: e744 b.n 51e8 <_lv_disp_refr_task+0x1f4> + vdb->area.x1 = area_p->x1; + 535e: f9b5 0048 ldrsh.w r0, [r5, #72] ; 0x48 + 5362: 8230 strh r0, [r6, #16] + vdb->area.x2 = area_p->x2; + 5364: f9b5 004c ldrsh.w r0, [r5, #76] ; 0x4c + 5368: 82b0 strh r0, [r6, #20] + vdb->area.y1 = row; + 536a: 9805 ldr r0, [sp, #20] + 536c: 8272 strh r2, [r6, #18] + vdb->area.y2 = row + max_row - 1; + 536e: fa1f fa82 uxth.w sl, r2 + 5372: fa10 f282 uxtah r2, r0, r2 + 5376: b212 sxth r2, r2 + if(vdb->area.y2 > y2) vdb->area.y2 = y2; + 5378: 4293 cmp r3, r2 + 537a: 4699 mov r9, r3 + 537c: bfa8 it ge + 537e: 4691 movge r9, r2 + if(y2 == row_last) disp_refr->driver.buffer->last_part = 1; + 5380: 4293 cmp r3, r2 + 5382: f8a6 9016 strh.w r9, [r6, #22] + 5386: dc08 bgt.n 539a <_lv_disp_refr_task+0x3a6> + 5388: f8d8 2000 ldr.w r2, [r8] + 538c: 6850 ldr r0, [r2, #4] + 538e: f890 2020 ldrb.w r2, [r0, #32] + 5392: f042 0202 orr.w r2, r2, #2 + 5396: f880 2020 strb.w r2, [r0, #32] + lv_refr_area_part(area_p); + 539a: 4a39 ldr r2, [pc, #228] ; (5480 <_lv_disp_refr_task+0x48c>) + 539c: ee18 0a10 vmov r0, s16 + 53a0: e9cd 3106 strd r3, r1, [sp, #24] + 53a4: 4790 blx r2 + for(row = area_p->y1; row + max_row - 1 <= y2; row += max_row) { + 53a6: 9907 ldr r1, [sp, #28] + 53a8: 9b06 ldr r3, [sp, #24] + 53aa: 448a add sl, r1 + 53ac: fa0f f28a sxth.w r2, sl + 53b0: e7c3 b.n 533a <_lv_disp_refr_task+0x346> + if(lv_disp_is_true_double_buf(disp_refr) && disp_refr->driver.set_px_cb == NULL) { + 53b2: 6838 ldr r0, [r7, #0] + 53b4: 6943 ldr r3, [r0, #20] + 53b6: 2b00 cmp r3, #0 + 53b8: f47f ae5a bne.w 5070 <_lv_disp_refr_task+0x7c> + lv_disp_buf_t * vdb = lv_disp_get_buf(disp_refr); + 53bc: 4b31 ldr r3, [pc, #196] ; (5484 <_lv_disp_refr_task+0x490>) + 53be: 4798 blx r3 + lv_refr_vdb_flush(); + 53c0: 4b31 ldr r3, [pc, #196] ; (5488 <_lv_disp_refr_task+0x494>) + lv_disp_buf_t * vdb = lv_disp_get_buf(disp_refr); + 53c2: 4605 mov r5, r0 + lv_refr_vdb_flush(); + 53c4: 4798 blx r3 + while(vdb->flushing) + 53c6: 69ab ldr r3, [r5, #24] + 53c8: 2b00 cmp r3, #0 + 53ca: d1fc bne.n 53c6 <_lv_disp_refr_task+0x3d2> + uint8_t * buf_ina = (uint8_t *)vdb->buf_act == vdb->buf1 ? vdb->buf2 : vdb->buf1; + 53cc: f8d5 9000 ldr.w r9, [r5] + uint8_t * buf_act = (uint8_t *)vdb->buf_act; + 53d0: f8d5 b008 ldr.w fp, [r5, #8] + lv_coord_t hres = lv_disp_get_hor_res(disp_refr); + 53d4: 4b2d ldr r3, [pc, #180] ; (548c <_lv_disp_refr_task+0x498>) + 53d6: 6838 ldr r0, [r7, #0] + uint8_t * buf_ina = (uint8_t *)vdb->buf_act == vdb->buf1 ? vdb->buf2 : vdb->buf1; + 53d8: 45d9 cmp r9, fp + 53da: bf08 it eq + 53dc: f8d5 9004 ldreq.w r9, [r5, #4] + lv_coord_t hres = lv_disp_get_hor_res(disp_refr); + 53e0: 4798 blx r3 + for(a = 0; a < disp_refr->inv_p; a++) { + 53e2: 2500 movs r5, #0 + lv_coord_t hres = lv_disp_get_hor_res(disp_refr); + 53e4: 4680 mov r8, r0 + start_offs += hres * sizeof(lv_color_t); + 53e6: 0043 lsls r3, r0, #1 + for(a = 0; a < disp_refr->inv_p; a++) { + 53e8: 683a ldr r2, [r7, #0] + 53ea: f8b2 1168 ldrh.w r1, [r2, #360] ; 0x168 + 53ee: b2a8 uxth r0, r5 + 53f0: f3c1 0109 ubfx r1, r1, #0, #10 + 53f4: 4281 cmp r1, r0 + 53f6: f67f ae3b bls.w 5070 <_lv_disp_refr_task+0x7c> + if(disp_refr->inv_area_joined[a] == 0) { + 53fa: 1951 adds r1, r2, r5 + 53fc: f891 1148 ldrb.w r1, [r1, #328] ; 0x148 + 5400: b109 cbz r1, 5406 <_lv_disp_refr_task+0x412> + for(a = 0; a < disp_refr->inv_p; a++) { + 5402: 3501 adds r5, #1 + 5404: e7f0 b.n 53e8 <_lv_disp_refr_task+0x3f4> + uint32_t start_offs = + 5406: eb02 02c5 add.w r2, r2, r5, lsl #3 + (hres * disp_refr->inv_areas[a].y1 + disp_refr->inv_areas[a].x1) * sizeof(lv_color_t); + 540a: f9b2 0048 ldrsh.w r0, [r2, #72] ; 0x48 + 540e: f9b2 604a ldrsh.w r6, [r2, #74] ; 0x4a + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + 5412: f8b2 204c ldrh.w r2, [r2, #76] ; 0x4c + 5416: 3201 adds r2, #1 + 5418: fb08 0106 mla r1, r8, r6, r0 + 541c: 1a12 subs r2, r2, r0 + for(y = disp_refr->inv_areas[a].y1; y <= disp_refr->inv_areas[a].y2; y++) { + 541e: f105 0009 add.w r0, r5, #9 + uint32_t line_length = lv_area_get_width(&disp_refr->inv_areas[a]) * sizeof(lv_color_t); + 5422: b212 sxth r2, r2 + for(y = disp_refr->inv_areas[a].y1; y <= disp_refr->inv_areas[a].y2; y++) { + 5424: 00c0 lsls r0, r0, #3 + 5426: eb0b 0a41 add.w sl, fp, r1, lsl #1 + uint32_t line_length = lv_area_get_width(&disp_refr->inv_areas[a]) * sizeof(lv_color_t); + 542a: ea4f 0c42 mov.w ip, r2, lsl #1 + for(y = disp_refr->inv_areas[a].y1; y <= disp_refr->inv_areas[a].y2; y++) { + 542e: eb09 0141 add.w r1, r9, r1, lsl #1 + 5432: 9003 str r0, [sp, #12] + 5434: 6838 ldr r0, [r7, #0] + 5436: 9a03 ldr r2, [sp, #12] + 5438: 4410 add r0, r2 + 543a: f9b0 0006 ldrsh.w r0, [r0, #6] + 543e: 42b0 cmp r0, r6 + 5440: dbdf blt.n 5402 <_lv_disp_refr_task+0x40e> + 5442: 9306 str r3, [sp, #24] + _lv_memcpy(buf_act + start_offs, buf_ina + start_offs, line_length); + 5444: 4662 mov r2, ip + 5446: 4b12 ldr r3, [pc, #72] ; (5490 <_lv_disp_refr_task+0x49c>) + 5448: 4650 mov r0, sl + 544a: e9cd 1c04 strd r1, ip, [sp, #16] + 544e: 4798 blx r3 + for(y = disp_refr->inv_areas[a].y1; y <= disp_refr->inv_areas[a].y2; y++) { + 5450: 9b06 ldr r3, [sp, #24] + 5452: 9904 ldr r1, [sp, #16] + 5454: f8dd c014 ldr.w ip, [sp, #20] + 5458: 3601 adds r6, #1 + 545a: b236 sxth r6, r6 + 545c: 449a add sl, r3 + 545e: 4419 add r1, r3 + 5460: e7e8 b.n 5434 <_lv_disp_refr_task+0x440> + disp_refr->driver.monitor_cb(&disp_refr->driver, elaps, px_num); + 5462: 6862 ldr r2, [r4, #4] + 5464: 4798 blx r3 + 5466: e61f b.n 50a8 <_lv_disp_refr_task+0xb4> + 5468: 0000d92d .word 0x0000d92d + 546c: 0001f789 .word 0x0001f789 + 5470: 0001f759 .word 0x0001f759 + 5474: 0001f7d9 .word 0x0001f7d9 + 5478: 0000e8e9 .word 0x0000e8e9 + 547c: 0000de71 .word 0x0000de71 + 5480: 00004e5d .word 0x00004e5d + 5484: 0000d9e1 .word 0x0000d9e1 + 5488: 00004c19 .word 0x00004c19 + 548c: 0000d909 .word 0x0000d909 + 5490: 0000ec31 .word 0x0000ec31 + +00005494 : + if(list->has_trans && list->skip_trans) id++; + 5494: 7943 ldrb r3, [r0, #5] + 5496: f003 0306 and.w r3, r3, #6 + 549a: 2b06 cmp r3, #6 + 549c: bf08 it eq + 549e: 3101 addeq r1, #1 + if(list->style_cnt == 0 || id >= list->style_cnt) return NULL; + 54a0: 7903 ldrb r3, [r0, #4] + if(list->has_trans && list->skip_trans) id++; + 54a2: bf08 it eq + 54a4: b2c9 uxtbeq r1, r1 + if(list->style_cnt == 0 || id >= list->style_cnt) return NULL; + 54a6: 428b cmp r3, r1 + return list->style_list[id]; + 54a8: bf86 itte hi + 54aa: 6803 ldrhi r3, [r0, #0] + 54ac: f853 0021 ldrhi.w r0, [r3, r1, lsl #2] + if(list->style_cnt == 0 || id >= list->style_cnt) return NULL; + 54b0: 2000 movls r0, #0 +} + 54b2: 4770 bx lr + +000054b4 : + * @param style pointer to a style + * @param prop a style property ORed with a state. + * E.g. `LV_STYLE_TEXT_FONT | (LV_STATE_PRESSED << LV_STYLE_STATE_POS)` + * @return + */ +LV_ATTRIBUTE_FAST_MEM static inline int32_t get_property_index(const lv_style_t * style, lv_style_property_t prop) + 54b4: b5f0 push {r4, r5, r6, r7, lr} +{ + LV_ASSERT_STYLE(style); + + if(style->map == NULL) return -1; + 54b6: b378 cbz r0, 5518 + uint8_t id_to_find = prop & 0xFF; + lv_style_attr_t attr; + attr.full = (prop >> 8) & 0xFF; + + int16_t weight = -1; + int16_t id_guess = -1; + 54b8: f04f 35ff mov.w r5, #4294967295 ; 0xffffffff + uint8_t id_to_find = prop & 0xFF; + 54bc: b2cf uxtb r7, r1 + attr.full = (prop >> 8) & 0xFF; + 54be: ea4f 2c11 mov.w ip, r1, lsr #8 + + size_t i = 0; + 54c2: 2300 movs r3, #0 + int16_t weight = -1; + 54c4: 462e mov r6, r5 + if(attr_i.bits.state == attr.bits.state) { + return i; + } + /* Be sure the property not specifies other state than the requested. + * E.g. For HOVER+PRESS, HOVER only is OK, but HOVER+FOCUS not*/ + else if((attr_i.bits.state & (~attr.bits.state)) == 0) { + 54c6: f3c1 2106 ubfx r1, r1, #8, #7 + while(style->map[i] != _LV_STYLE_CLOSEING_PROP) { + 54ca: 5cc2 ldrb r2, [r0, r3] + 54cc: 2aff cmp r2, #255 ; 0xff + 54ce: d101 bne.n 54d4 + else i += sizeof(const void *); + + i += sizeof(lv_style_property_t); + } + + return id_guess; + 54d0: 4628 mov r0, r5 + 54d2: e009 b.n 54e8 + if(style->map[i] == id_to_find) { + 54d4: 4297 cmp r7, r2 + 54d6: d111 bne.n 54fc + attr_i.full = style->map[i + 1]; + 54d8: 18c4 adds r4, r0, r3 + 54da: 7864 ldrb r4, [r4, #1] + if(attr_i.bits.state == attr.bits.state) { + 54dc: ea8c 0e04 eor.w lr, ip, r4 + 54e0: f01e 0f7f tst.w lr, #127 ; 0x7f + 54e4: d101 bne.n 54ea + return i; + 54e6: 4618 mov r0, r3 +} + 54e8: bdf0 pop {r4, r5, r6, r7, pc} + else if((attr_i.bits.state & (~attr.bits.state)) == 0) { + 54ea: f004 047f and.w r4, r4, #127 ; 0x7f + 54ee: ea34 0e01 bics.w lr, r4, r1 + 54f2: d103 bne.n 54fc + if(attr_i.bits.state > weight) { + 54f4: 42b4 cmp r4, r6 + weight = attr_i.bits.state; + 54f6: bfc4 itt gt + 54f8: b226 sxthgt r6, r4 + id_guess = i; + 54fa: b21d sxthgt r5, r3 + if((style->map[i] & 0xF) < LV_STYLE_ID_COLOR) i += sizeof(lv_style_int_t); + 54fc: f002 020f and.w r2, r2, #15 + 5500: 2a08 cmp r2, #8 + 5502: d802 bhi.n 550a + else if((style->map[i] & 0xF) < LV_STYLE_ID_OPA) i += sizeof(lv_color_t); + 5504: 3302 adds r3, #2 + i += sizeof(lv_style_property_t); + 5506: 3302 adds r3, #2 + 5508: e7df b.n 54ca + else if((style->map[i] & 0xF) < LV_STYLE_ID_OPA) i += sizeof(lv_color_t); + 550a: 2a0b cmp r2, #11 + 550c: d9fa bls.n 5504 + else if((style->map[i] & 0xF) < LV_STYLE_ID_PTR) i += sizeof(lv_opa_t); + 550e: 2a0d cmp r2, #13 + 5510: bf94 ite ls + 5512: 3301 addls r3, #1 + else i += sizeof(const void *); + 5514: 3304 addhi r3, #4 + 5516: e7f6 b.n 5506 + if(style->map == NULL) return -1; + 5518: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 551c: e7e4 b.n 54e8 + +0000551e <_lv_memcpy_small.isra.0>: + 551e: 3901 subs r1, #1 + 5520: 4402 add r2, r0 + *d8 = *s8; + 5522: f811 3f01 ldrb.w r3, [r1, #1]! + 5526: f800 3b01 strb.w r3, [r0], #1 + while(len) { + 552a: 4290 cmp r0, r2 + 552c: d1f9 bne.n 5522 <_lv_memcpy_small.isra.0+0x4> + s8++; + len--; + } + + return dst; +} + 552e: 4770 bx lr + +00005530 : + _lv_memset_00(style, sizeof(lv_style_t)); + 5530: 4b01 ldr r3, [pc, #4] ; (5538 ) + 5532: 2104 movs r1, #4 + 5534: 4718 bx r3 + 5536: bf00 nop + 5538: 0000f019 .word 0x0000f019 + +0000553c : + _lv_memset_00(list, sizeof(lv_style_list_t)); + 553c: 4b01 ldr r3, [pc, #4] ; (5544 ) + 553e: 2108 movs r1, #8 + 5540: 4718 bx r3 + 5542: bf00 nop + 5544: 0000f019 .word 0x0000f019 + +00005548 <_lv_style_list_remove_style>: +{ + 5548: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} + if(list->style_cnt == 0) return; + 554a: 7903 ldrb r3, [r0, #4] +{ + 554c: 4604 mov r4, r0 + 554e: 460e mov r6, r1 + if(list->style_cnt == 0) return; + 5550: b14b cbz r3, 5566 <_lv_style_list_remove_style+0x1e> + if(list->style_list[i] == style) { + 5552: 6800 ldr r0, [r0, #0] + 5554: 2200 movs r2, #0 + 5556: f850 1022 ldr.w r1, [r0, r2, lsl #2] + 555a: 42b1 cmp r1, r6 + 555c: d03c beq.n 55d8 <_lv_style_list_remove_style+0x90> + for(i = 0; i < list->style_cnt; i++) { + 555e: 3201 adds r2, #1 + 5560: b2d1 uxtb r1, r2 + 5562: 428b cmp r3, r1 + 5564: d8f7 bhi.n 5556 <_lv_style_list_remove_style+0xe> +} + 5566: b003 add sp, #12 + 5568: bdf0 pop {r4, r5, r6, r7, pc} + lv_style_t ** new_classes = lv_mem_realloc(list->style_list, sizeof(lv_style_t *) * (list->style_cnt - 1)); + 556a: 3b01 subs r3, #1 + 556c: 0099 lsls r1, r3, #2 + 556e: 4b21 ldr r3, [pc, #132] ; (55f4 <_lv_style_list_remove_style+0xac>) + 5570: 4798 blx r3 + LV_ASSERT_MEM(new_classes); + 5572: 4b21 ldr r3, [pc, #132] ; (55f8 <_lv_style_list_remove_style+0xb0>) + lv_style_t ** new_classes = lv_mem_realloc(list->style_list, sizeof(lv_style_t *) * (list->style_cnt - 1)); + 5574: 4605 mov r5, r0 + LV_ASSERT_MEM(new_classes); + 5576: 4798 blx r3 + 5578: 4607 mov r7, r0 + 557a: b968 cbnz r0, 5598 <_lv_style_list_remove_style+0x50> + 557c: 4b1f ldr r3, [pc, #124] ; (55fc <_lv_style_list_remove_style+0xb4>) + 557e: 4920 ldr r1, [pc, #128] ; (5600 <_lv_style_list_remove_style+0xb8>) + 5580: 9300 str r3, [sp, #0] + 5582: f44f 7282 mov.w r2, #260 ; 0x104 + 5586: 2003 movs r0, #3 + 5588: 4c1e ldr r4, [pc, #120] ; (5604 <_lv_style_list_remove_style+0xbc>) + 558a: 47a0 blx r4 + 558c: 481e ldr r0, [pc, #120] ; (5608 <_lv_style_list_remove_style+0xc0>) + 558e: 491f ldr r1, [pc, #124] ; (560c <_lv_style_list_remove_style+0xc4>) + 5590: 462a mov r2, r5 + 5592: 463b mov r3, r7 + 5594: 4788 blx r1 + 5596: e7fe b.n 5596 <_lv_style_list_remove_style+0x4e> + if(new_classes == NULL) { + 5598: b14d cbz r5, 55ae <_lv_style_list_remove_style+0x66> + for(i = 0, j = 0; i < list->style_cnt; i++) { + 559a: 2300 movs r3, #0 + 559c: 7921 ldrb r1, [r4, #4] + 559e: 461a mov r2, r3 + 55a0: b2d8 uxtb r0, r3 + 55a2: 4288 cmp r0, r1 + 55a4: d30d bcc.n 55c2 <_lv_style_list_remove_style+0x7a> + list->style_cnt--; + 55a6: 3901 subs r1, #1 + 55a8: 7121 strb r1, [r4, #4] + list->style_list = new_classes; + 55aa: 6025 str r5, [r4, #0] + 55ac: e7db b.n 5566 <_lv_style_list_remove_style+0x1e> + LV_LOG_WARN("lv_style_list_remove_style: couldn't reallocate class list"); + 55ae: 4b18 ldr r3, [pc, #96] ; (5610 <_lv_style_list_remove_style+0xc8>) + 55b0: 9300 str r3, [sp, #0] + 55b2: 4913 ldr r1, [pc, #76] ; (5600 <_lv_style_list_remove_style+0xb8>) + 55b4: 4b11 ldr r3, [pc, #68] ; (55fc <_lv_style_list_remove_style+0xb4>) + 55b6: 4c13 ldr r4, [pc, #76] ; (5604 <_lv_style_list_remove_style+0xbc>) + 55b8: f44f 7283 mov.w r2, #262 ; 0x106 + 55bc: 2002 movs r0, #2 + 55be: 47a0 blx r4 + return; + 55c0: e7d1 b.n 5566 <_lv_style_list_remove_style+0x1e> + if(list->style_list[i] == style) continue; + 55c2: 6820 ldr r0, [r4, #0] + 55c4: f850 0023 ldr.w r0, [r0, r3, lsl #2] + 55c8: 42b0 cmp r0, r6 + new_classes[j] = list->style_list[i]; + 55ca: bf1e ittt ne + 55cc: f845 0022 strne.w r0, [r5, r2, lsl #2] + j++; + 55d0: 3201 addne r2, #1 + 55d2: b2d2 uxtbne r2, r2 + for(i = 0, j = 0; i < list->style_cnt; i++) { + 55d4: 3301 adds r3, #1 + 55d6: e7e3 b.n 55a0 <_lv_style_list_remove_style+0x58> + if(list->style_cnt == 1) { + 55d8: 2b01 cmp r3, #1 + 55da: d1c6 bne.n 556a <_lv_style_list_remove_style+0x22> + lv_mem_free(list->style_list); + 55dc: 4b0d ldr r3, [pc, #52] ; (5614 <_lv_style_list_remove_style+0xcc>) + 55de: 4798 blx r3 + list->style_list = NULL; + 55e0: 2300 movs r3, #0 + 55e2: 6023 str r3, [r4, #0] + list->style_cnt = 0; + 55e4: 88a3 ldrh r3, [r4, #4] + 55e6: f423 73ff bic.w r3, r3, #510 ; 0x1fe + 55ea: f023 0301 bic.w r3, r3, #1 + 55ee: 80a3 strh r3, [r4, #4] + return; + 55f0: e7b9 b.n 5566 <_lv_style_list_remove_style+0x1e> + 55f2: bf00 nop + 55f4: 0000ee15 .word 0x0000ee15 + 55f8: 000017e1 .word 0x000017e1 + 55fc: 0001f8ef .word 0x0001f8ef + 5600: 0001f7e6 .word 0x0001f7e6 + 5604: 0000e8e9 .word 0x0000e8e9 + 5608: 0001edbe .word 0x0001edbe + 560c: 000017e9 .word 0x000017e9 + 5610: 0001f817 .word 0x0001f817 + 5614: 0000eae5 .word 0x0000eae5 + +00005618 <_lv_style_list_add_style>: +{ + 5618: e92d 41f3 stmdb sp!, {r0, r1, r4, r5, r6, r7, r8, lr} + 561c: 460f mov r7, r1 + if(list == NULL) return; + 561e: 4605 mov r5, r0 + 5620: b338 cbz r0, 5672 <_lv_style_list_add_style+0x5a> + _lv_style_list_remove_style(list, style); + 5622: 4b29 ldr r3, [pc, #164] ; (56c8 <_lv_style_list_add_style+0xb0>) + 5624: 4798 blx r3 + if(list->style_cnt == 0) new_classes = lv_mem_alloc(sizeof(lv_style_t *)); + 5626: 7929 ldrb r1, [r5, #4] + 5628: b9a1 cbnz r1, 5654 <_lv_style_list_add_style+0x3c> + 562a: 4b28 ldr r3, [pc, #160] ; (56cc <_lv_style_list_add_style+0xb4>) + 562c: 2004 movs r0, #4 + 562e: 4798 blx r3 + LV_ASSERT_MEM(new_classes); + 5630: 4b27 ldr r3, [pc, #156] ; (56d0 <_lv_style_list_add_style+0xb8>) + else new_classes = lv_mem_realloc(list->style_list, sizeof(lv_style_t *) * (list->style_cnt + 1)); + 5632: 4604 mov r4, r0 + LV_ASSERT_MEM(new_classes); + 5634: 4798 blx r3 + 5636: 4606 mov r6, r0 + 5638: b990 cbnz r0, 5660 <_lv_style_list_add_style+0x48> + 563a: 4b26 ldr r3, [pc, #152] ; (56d4 <_lv_style_list_add_style+0xbc>) + 563c: 4926 ldr r1, [pc, #152] ; (56d8 <_lv_style_list_add_style+0xc0>) + 563e: 9300 str r3, [sp, #0] + 5640: 22d0 movs r2, #208 ; 0xd0 + 5642: 2003 movs r0, #3 + 5644: 4d25 ldr r5, [pc, #148] ; (56dc <_lv_style_list_add_style+0xc4>) + 5646: 47a8 blx r5 + 5648: 4825 ldr r0, [pc, #148] ; (56e0 <_lv_style_list_add_style+0xc8>) + 564a: 4926 ldr r1, [pc, #152] ; (56e4 <_lv_style_list_add_style+0xcc>) + 564c: 4622 mov r2, r4 + 564e: 4633 mov r3, r6 + 5650: 4788 blx r1 + 5652: e7fe b.n 5652 <_lv_style_list_add_style+0x3a> + else new_classes = lv_mem_realloc(list->style_list, sizeof(lv_style_t *) * (list->style_cnt + 1)); + 5654: 3101 adds r1, #1 + 5656: 6828 ldr r0, [r5, #0] + 5658: 4b23 ldr r3, [pc, #140] ; (56e8 <_lv_style_list_add_style+0xd0>) + 565a: 0089 lsls r1, r1, #2 + 565c: 4798 blx r3 + 565e: e7e7 b.n 5630 <_lv_style_list_add_style+0x18> + if(new_classes == NULL) { + 5660: b954 cbnz r4, 5678 <_lv_style_list_add_style+0x60> + LV_LOG_WARN("lv_style_list_add_style: couldn't add the class"); + 5662: 4b22 ldr r3, [pc, #136] ; (56ec <_lv_style_list_add_style+0xd4>) + 5664: 9300 str r3, [sp, #0] + 5666: 491c ldr r1, [pc, #112] ; (56d8 <_lv_style_list_add_style+0xc0>) + 5668: 4b1a ldr r3, [pc, #104] ; (56d4 <_lv_style_list_add_style+0xbc>) + 566a: 4c1c ldr r4, [pc, #112] ; (56dc <_lv_style_list_add_style+0xc4>) + 566c: 22d2 movs r2, #210 ; 0xd2 + 566e: 2002 movs r0, #2 + 5670: 47a0 blx r4 +} + 5672: b002 add sp, #8 + 5674: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + if(list->has_trans) first_style++; + 5678: 796b ldrb r3, [r5, #5] + for(i = list->style_cnt; i > first_style; i--) { + 567a: 792e ldrb r6, [r5, #4] + uint8_t first_style = 0; + 567c: f3c3 0840 ubfx r8, r3, #1, #1 + if(list->has_local) first_style++; + 5680: 07db lsls r3, r3, #31 + 5682: bf48 it mi + 5684: f108 0801 addmi.w r8, r8, #1 + new_classes[i] = new_classes[i - 1]; + 5688: eba6 0208 sub.w r2, r6, r8 + 568c: b2d2 uxtb r2, r2 + 568e: 4546 cmp r6, r8 + 5690: f1c2 0001 rsb r0, r2, #1 + 5694: f106 4180 add.w r1, r6, #1073741824 ; 0x40000000 + 5698: ea4f 0080 mov.w r0, r0, lsl #2 + 569c: f101 31ff add.w r1, r1, #4294967295 ; 0xffffffff + 56a0: bf38 it cc + 56a2: 2004 movcc r0, #4 + 56a4: eb00 0181 add.w r1, r0, r1, lsl #2 + 56a8: eb00 0086 add.w r0, r0, r6, lsl #2 + 56ac: ea4f 0282 mov.w r2, r2, lsl #2 + 56b0: 4b0f ldr r3, [pc, #60] ; (56f0 <_lv_style_list_add_style+0xd8>) + 56b2: bf38 it cc + 56b4: 2200 movcc r2, #0 + 56b6: 4421 add r1, r4 + 56b8: 4420 add r0, r4 + list->style_cnt++; + 56ba: 3601 adds r6, #1 + new_classes[i] = new_classes[i - 1]; + 56bc: 4798 blx r3 + new_classes[first_style] = style; + 56be: f844 7028 str.w r7, [r4, r8, lsl #2] + list->style_cnt++; + 56c2: 712e strb r6, [r5, #4] + list->style_list = new_classes; + 56c4: 602c str r4, [r5, #0] + 56c6: e7d4 b.n 5672 <_lv_style_list_add_style+0x5a> + 56c8: 00005549 .word 0x00005549 + 56cc: 0000ea2d .word 0x0000ea2d + 56d0: 000017e1 .word 0x000017e1 + 56d4: 0001f90b .word 0x0001f90b + 56d8: 0001f7e6 .word 0x0001f7e6 + 56dc: 0000e8e9 .word 0x0000e8e9 + 56e0: 0001edbe .word 0x0001edbe + 56e4: 000017e9 .word 0x000017e9 + 56e8: 0000ee15 .word 0x0000ee15 + 56ec: 0001f852 .word 0x0001f852 + 56f0: 000162d1 .word 0x000162d1 + +000056f4 : + */ +static lv_style_t * get_alloc_local_style(lv_style_list_t * list) +{ + LV_ASSERT_STYLE_LIST(list); + + if(list->has_local) return lv_style_list_get_style(list, 0); + 56f4: 7943 ldrb r3, [r0, #5] + 56f6: 07db lsls r3, r3, #31 +{ + 56f8: b573 push {r0, r1, r4, r5, r6, lr} + 56fa: 4605 mov r5, r0 + if(list->has_local) return lv_style_list_get_style(list, 0); + 56fc: d505 bpl.n 570a + 56fe: 4b1a ldr r3, [pc, #104] ; (5768 ) + 5700: 2100 movs r1, #0 + /*Add the local style to the furst place*/ + _lv_style_list_add_style(list, local_style); + list->has_local = 1; + + return local_style; +} + 5702: b002 add sp, #8 + 5704: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + if(list->has_local) return lv_style_list_get_style(list, 0); + 5708: 4718 bx r3 + lv_style_t * local_style = lv_mem_alloc(sizeof(lv_style_t)); + 570a: 4b18 ldr r3, [pc, #96] ; (576c ) + 570c: 2004 movs r0, #4 + 570e: 4798 blx r3 + LV_ASSERT_MEM(local_style); + 5710: 4b17 ldr r3, [pc, #92] ; (5770 ) + lv_style_t * local_style = lv_mem_alloc(sizeof(lv_style_t)); + 5712: 4604 mov r4, r0 + LV_ASSERT_MEM(local_style); + 5714: 4798 blx r3 + 5716: 4606 mov r6, r0 + 5718: b968 cbnz r0, 5736 + 571a: 4b16 ldr r3, [pc, #88] ; (5774 ) + 571c: 4916 ldr r1, [pc, #88] ; (5778 ) + 571e: 9300 str r3, [sp, #0] + 5720: f240 4235 movw r2, #1077 ; 0x435 + 5724: 2003 movs r0, #3 + 5726: 4d15 ldr r5, [pc, #84] ; (577c ) + 5728: 47a8 blx r5 + 572a: 4815 ldr r0, [pc, #84] ; (5780 ) + 572c: 4915 ldr r1, [pc, #84] ; (5784 ) + 572e: 4622 mov r2, r4 + 5730: 4633 mov r3, r6 + 5732: 4788 blx r1 + 5734: e7fe b.n 5734 + if(local_style == NULL) { + 5736: b95c cbnz r4, 5750 + LV_LOG_WARN("get_local_style: couldn't create local style"); + 5738: 4b13 ldr r3, [pc, #76] ; (5788 ) + 573a: 9300 str r3, [sp, #0] + 573c: 490e ldr r1, [pc, #56] ; (5778 ) + 573e: 4b0d ldr r3, [pc, #52] ; (5774 ) + 5740: 4d0e ldr r5, [pc, #56] ; (577c ) + 5742: f240 4237 movw r2, #1079 ; 0x437 + 5746: 2002 movs r0, #2 + 5748: 47a8 blx r5 +} + 574a: 4620 mov r0, r4 + 574c: b002 add sp, #8 + 574e: bd70 pop {r4, r5, r6, pc} + lv_style_init(local_style); + 5750: 4b0e ldr r3, [pc, #56] ; (578c ) + 5752: 4620 mov r0, r4 + 5754: 4798 blx r3 + _lv_style_list_add_style(list, local_style); + 5756: 4b0e ldr r3, [pc, #56] ; (5790 ) + 5758: 4621 mov r1, r4 + 575a: 4628 mov r0, r5 + 575c: 4798 blx r3 + list->has_local = 1; + 575e: 796b ldrb r3, [r5, #5] + 5760: f043 0301 orr.w r3, r3, #1 + 5764: 716b strb r3, [r5, #5] + return local_style; + 5766: e7f0 b.n 574a + 5768: 00005495 .word 0x00005495 + 576c: 0000ea2d .word 0x0000ea2d + 5770: 000017e1 .word 0x000017e1 + 5774: 0001f924 .word 0x0001f924 + 5778: 0001f7e6 .word 0x0001f7e6 + 577c: 0000e8e9 .word 0x0000e8e9 + 5780: 0001edbe .word 0x0001edbe + 5784: 000017e9 .word 0x000017e9 + 5788: 0001f882 .word 0x0001f882 + 578c: 00005531 .word 0x00005531 + 5790: 00005619 .word 0x00005619 + +00005794 : +{ + 5794: b510 push {r4, lr} + lv_mem_free(style->map); + 5796: 4b03 ldr r3, [pc, #12] ; (57a4 ) +{ + 5798: 4604 mov r4, r0 + lv_mem_free(style->map); + 579a: 6800 ldr r0, [r0, #0] + 579c: 4798 blx r3 + style->map = NULL; + 579e: 2300 movs r3, #0 + 57a0: 6023 str r3, [r4, #0] +} + 57a2: bd10 pop {r4, pc} + 57a4: 0000eae5 .word 0x0000eae5 + +000057a8 <_lv_style_get_mem_size>: + if(style->map == NULL) return 0; + 57a8: 6800 ldr r0, [r0, #0] + 57aa: b128 cbz r0, 57b8 <_lv_style_get_mem_size+0x10> + size_t i = 0; + 57ac: 2300 movs r3, #0 + while(style->map[i] != _LV_STYLE_CLOSEING_PROP) { + 57ae: 5cc2 ldrb r2, [r0, r3] + 57b0: 2aff cmp r2, #255 ; 0xff + 57b2: d102 bne.n 57ba <_lv_style_get_mem_size+0x12> + return i + sizeof(lv_style_property_t); + 57b4: 3302 adds r3, #2 + 57b6: b298 uxth r0, r3 +} + 57b8: 4770 bx lr + if((style->map[i] & 0xF) < LV_STYLE_ID_COLOR) i += sizeof(lv_style_int_t); + 57ba: f002 020f and.w r2, r2, #15 + 57be: 2a08 cmp r2, #8 + 57c0: d802 bhi.n 57c8 <_lv_style_get_mem_size+0x20> + else if((style->map[i] & 0xF) < LV_STYLE_ID_OPA) i += sizeof(lv_color_t); + 57c2: 3302 adds r3, #2 + i += sizeof(lv_style_property_t); + 57c4: 3302 adds r3, #2 + 57c6: e7f2 b.n 57ae <_lv_style_get_mem_size+0x6> + else if((style->map[i] & 0xF) < LV_STYLE_ID_OPA) i += sizeof(lv_color_t); + 57c8: 2a0b cmp r2, #11 + 57ca: d9fa bls.n 57c2 <_lv_style_get_mem_size+0x1a> + else if((style->map[i] & 0xF) < LV_STYLE_ID_PTR) i += sizeof(lv_opa_t); + 57cc: 2a0d cmp r2, #13 + 57ce: bf94 ite ls + 57d0: 3301 addls r3, #1 + else i += sizeof(const void *); + 57d2: 3304 addhi r3, #4 + 57d4: e7f6 b.n 57c4 <_lv_style_get_mem_size+0x1c> + ... + +000057d8 : +{ + 57d8: b537 push {r0, r1, r2, r4, r5, lr} + 57da: 4605 mov r5, r0 + if(style_src == NULL) return; + 57dc: 460c mov r4, r1 + 57de: b179 cbz r1, 5800 + if(style_src->map == NULL) return; + 57e0: 680b ldr r3, [r1, #0] + 57e2: b16b cbz r3, 5800 + uint16_t size = _lv_style_get_mem_size(style_src); + 57e4: 4608 mov r0, r1 + 57e6: 4b07 ldr r3, [pc, #28] ; (5804 ) + 57e8: 4798 blx r3 + style_dest->map = lv_mem_alloc(size); + 57ea: 4b07 ldr r3, [pc, #28] ; (5808 ) + uint16_t size = _lv_style_get_mem_size(style_src); + 57ec: 9001 str r0, [sp, #4] + style_dest->map = lv_mem_alloc(size); + 57ee: 4798 blx r3 + 57f0: 6028 str r0, [r5, #0] + _lv_memcpy(style_dest->map, style_src->map, size); + 57f2: 9a01 ldr r2, [sp, #4] + 57f4: 6821 ldr r1, [r4, #0] + 57f6: 4b05 ldr r3, [pc, #20] ; (580c ) +} + 57f8: b003 add sp, #12 + 57fa: e8bd 4030 ldmia.w sp!, {r4, r5, lr} + _lv_memcpy(style_dest->map, style_src->map, size); + 57fe: 4718 bx r3 +} + 5800: b003 add sp, #12 + 5802: bd30 pop {r4, r5, pc} + 5804: 000057a9 .word 0x000057a9 + 5808: 0000ea2d .word 0x0000ea2d + 580c: 0000ec31 .word 0x0000ec31 + +00005810 : +{ + 5810: b5f8 push {r3, r4, r5, r6, r7, lr} + 5812: 460f mov r7, r1 + if(style == NULL) return false; + 5814: 4604 mov r4, r0 + 5816: b330 cbz r0, 5866 + int32_t id = get_property_index(style, prop); + 5818: 6806 ldr r6, [r0, #0] + 581a: 4b14 ldr r3, [pc, #80] ; (586c ) + 581c: 4630 mov r0, r6 + 581e: 4798 blx r3 + if(id >= 0) { + 5820: 1e05 subs r5, r0, #0 + 5822: db20 blt.n 5866 + attr_found.full = *(style->map + id + 1); + 5824: 442e add r6, r5 + if(attr_found.bits.state == attr_goal.bits.state) { + 5826: 7873 ldrb r3, [r6, #1] + 5828: ea83 2317 eor.w r3, r3, r7, lsr #8 + 582c: 065b lsls r3, r3, #25 + 582e: d11a bne.n 5866 + uint32_t map_size = _lv_style_get_mem_size(style); + 5830: 4b0f ldr r3, [pc, #60] ; (5870 ) + 5832: 4620 mov r0, r4 + 5834: f007 010f and.w r1, r7, #15 + 5838: 4798 blx r3 + else if((prop & 0xF) < LV_STYLE_ID_OPA) prop_size += sizeof(lv_color_t); + 583a: 290b cmp r1, #11 + 583c: d90c bls.n 5858 + else prop_size += sizeof(const void *); + 583e: 290e cmp r1, #14 + 5840: bf34 ite cc + 5842: 2303 movcc r3, #3 + 5844: 2306 movcs r3, #6 + for(i = id; i < map_size - prop_size; i++) { + 5846: 1ac1 subs r1, r0, r3 + 5848: 42a9 cmp r1, r5 + style->map[i] = style->map[i + prop_size]; + 584a: 6820 ldr r0, [r4, #0] + for(i = id; i < map_size - prop_size; i++) { + 584c: d806 bhi.n 585c + style->map = lv_mem_realloc(style->map, map_size - prop_size); + 584e: 4b09 ldr r3, [pc, #36] ; (5874 ) + 5850: 4798 blx r3 + 5852: 6020 str r0, [r4, #0] + return true; + 5854: 2001 movs r0, #1 +} + 5856: bdf8 pop {r3, r4, r5, r6, r7, pc} + else if((prop & 0xF) < LV_STYLE_ID_OPA) prop_size += sizeof(lv_color_t); + 5858: 2304 movs r3, #4 + 585a: e7f4 b.n 5846 + style->map[i] = style->map[i + prop_size]; + 585c: 1942 adds r2, r0, r5 + 585e: 5cd2 ldrb r2, [r2, r3] + 5860: 5542 strb r2, [r0, r5] + for(i = id; i < map_size - prop_size; i++) { + 5862: 3501 adds r5, #1 + 5864: e7f0 b.n 5848 + if(style == NULL) return false; + 5866: 2000 movs r0, #0 + 5868: e7f5 b.n 5856 + 586a: bf00 nop + 586c: 000054b5 .word 0x000054b5 + 5870: 000057a9 .word 0x000057a9 + 5874: 0000ee15 .word 0x0000ee15 + +00005878 <_lv_style_set_int>: +{ + 5878: b570 push {r4, r5, r6, lr} + 587a: 6806 ldr r6, [r0, #0] + int32_t id = get_property_index(style, prop); + 587c: 4b28 ldr r3, [pc, #160] ; (5920 <_lv_style_set_int+0xa8>) +{ + 587e: b086 sub sp, #24 + 5880: 4605 mov r5, r0 + int32_t id = get_property_index(style, prop); + 5882: 4630 mov r0, r6 +{ + 5884: f8ad 100e strh.w r1, [sp, #14] + 5888: f8ad 200c strh.w r2, [sp, #12] + int32_t id = get_property_index(style, prop); + 588c: 460c mov r4, r1 + 588e: 4798 blx r3 + if(id >= 0) { + 5890: 2800 cmp r0, #0 + 5892: db0d blt.n 58b0 <_lv_style_set_int+0x38> + attr_found.full = *(style->map + id + 1); + 5894: 1833 adds r3, r6, r0 + if(attr_found.bits.state == attr_goal.bits.state) { + 5896: 785b ldrb r3, [r3, #1] + 5898: ea83 2314 eor.w r3, r3, r4, lsr #8 + 589c: 065b lsls r3, r3, #25 + 589e: d107 bne.n 58b0 <_lv_style_set_int+0x38> + _lv_memcpy_small(style->map + id + sizeof(lv_style_property_t), &value, sizeof(lv_style_int_t)); + 58a0: 3002 adds r0, #2 + 58a2: 4b20 ldr r3, [pc, #128] ; (5924 <_lv_style_set_int+0xac>) + 58a4: 2202 movs r2, #2 + 58a6: a903 add r1, sp, #12 + 58a8: 4430 add r0, r6 + 58aa: 4798 blx r3 +} + 58ac: b006 add sp, #24 + 58ae: bd70 pop {r4, r5, r6, pc} + lv_style_property_t end_mark = _LV_STYLE_CLOSEING_PROP; + 58b0: 23ff movs r3, #255 ; 0xff + 58b2: f8ad 3016 strh.w r3, [sp, #22] + uint16_t size = _lv_style_get_mem_size(style); + 58b6: 4628 mov r0, r5 + 58b8: 4b1b ldr r3, [pc, #108] ; (5928 <_lv_style_set_int+0xb0>) + 58ba: 4798 blx r3 + if(size == 0) size += end_mark_size; + 58bc: 1e04 subs r4, r0, #0 + 58be: bf08 it eq + 58c0: 2402 moveq r4, #2 + size += sizeof(lv_style_property_t) + sizeof(lv_style_int_t); + 58c2: 3404 adds r4, #4 + style->map = lv_mem_realloc(style->map, size); + 58c4: b2a4 uxth r4, r4 + 58c6: 4b19 ldr r3, [pc, #100] ; (592c <_lv_style_set_int+0xb4>) + 58c8: 4621 mov r1, r4 + 58ca: 4630 mov r0, r6 + 58cc: 4798 blx r3 + LV_ASSERT_MEM(style->map); + 58ce: 4b18 ldr r3, [pc, #96] ; (5930 <_lv_style_set_int+0xb8>) + style->map = lv_mem_realloc(style->map, size); + 58d0: 6028 str r0, [r5, #0] + LV_ASSERT_MEM(style->map); + 58d2: 4798 blx r3 + 58d4: 4606 mov r6, r0 + 58d6: b968 cbnz r0, 58f4 <_lv_style_set_int+0x7c> + 58d8: 4b16 ldr r3, [pc, #88] ; (5934 <_lv_style_set_int+0xbc>) + 58da: 4917 ldr r1, [pc, #92] ; (5938 <_lv_style_set_int+0xc0>) + 58dc: 9300 str r3, [sp, #0] + 58de: f44f 72c3 mov.w r2, #390 ; 0x186 + 58e2: 2003 movs r0, #3 + 58e4: 4c15 ldr r4, [pc, #84] ; (593c <_lv_style_set_int+0xc4>) + 58e6: 47a0 blx r4 + 58e8: 682a ldr r2, [r5, #0] + 58ea: 4815 ldr r0, [pc, #84] ; (5940 <_lv_style_set_int+0xc8>) + 58ec: 4915 ldr r1, [pc, #84] ; (5944 <_lv_style_set_int+0xcc>) + 58ee: 4633 mov r3, r6 + 58f0: 4788 blx r1 + 58f2: e7fe b.n 58f2 <_lv_style_set_int+0x7a> + _lv_memcpy_small(style->map + size - new_prop_size - end_mark_size, &prop, sizeof(lv_style_property_t)); + 58f4: 6828 ldr r0, [r5, #0] + 58f6: 4e0b ldr r6, [pc, #44] ; (5924 <_lv_style_set_int+0xac>) + 58f8: 1fa3 subs r3, r4, #6 + 58fa: f10d 010e add.w r1, sp, #14 + 58fe: 4418 add r0, r3 + 5900: 2202 movs r2, #2 + 5902: 47b0 blx r6 + _lv_memcpy_small(style->map + size - sizeof(lv_style_int_t) - end_mark_size, &value, sizeof(lv_style_int_t)); + 5904: 6828 ldr r0, [r5, #0] + _lv_memcpy_small(style->map + size - new_prop_size - end_mark_size, &prop, sizeof(lv_style_property_t)); + 5906: 1f23 subs r3, r4, #4 + _lv_memcpy_small(style->map + size - sizeof(lv_style_int_t) - end_mark_size, &value, sizeof(lv_style_int_t)); + 5908: a903 add r1, sp, #12 + 590a: 4418 add r0, r3 + 590c: 2202 movs r2, #2 + 590e: 47b0 blx r6 + _lv_memcpy_small(style->map + size - end_mark_size, &end_mark, sizeof(end_mark)); + 5910: 6828 ldr r0, [r5, #0] + _lv_memcpy_small(style->map + size - sizeof(lv_style_int_t) - end_mark_size, &value, sizeof(lv_style_int_t)); + 5912: 3c02 subs r4, #2 + _lv_memcpy_small(style->map + size - end_mark_size, &end_mark, sizeof(end_mark)); + 5914: 2202 movs r2, #2 + 5916: f10d 0116 add.w r1, sp, #22 + 591a: 4420 add r0, r4 + 591c: 47b0 blx r6 + 591e: e7c5 b.n 58ac <_lv_style_set_int+0x34> + 5920: 000054b5 .word 0x000054b5 + 5924: 0000551f .word 0x0000551f + 5928: 000057a9 .word 0x000057a9 + 592c: 0000ee15 .word 0x0000ee15 + 5930: 000017e1 .word 0x000017e1 + 5934: 0001f93a .word 0x0001f93a + 5938: 0001f7e6 .word 0x0001f7e6 + 593c: 0000e8e9 .word 0x0000e8e9 + 5940: 0001edbe .word 0x0001edbe + 5944: 000017e9 .word 0x000017e9 + +00005948 <_lv_style_set_color>: +{ + 5948: b570 push {r4, r5, r6, lr} + 594a: 6806 ldr r6, [r0, #0] + int32_t id = get_property_index(style, prop); + 594c: 4b28 ldr r3, [pc, #160] ; (59f0 <_lv_style_set_color+0xa8>) +{ + 594e: b086 sub sp, #24 + 5950: 4605 mov r5, r0 + int32_t id = get_property_index(style, prop); + 5952: 4630 mov r0, r6 +{ + 5954: f8ad 200c strh.w r2, [sp, #12] + 5958: f8ad 100e strh.w r1, [sp, #14] + int32_t id = get_property_index(style, prop); + 595c: 460c mov r4, r1 + 595e: 4798 blx r3 + if(id >= 0) { + 5960: 2800 cmp r0, #0 + 5962: db0d blt.n 5980 <_lv_style_set_color+0x38> + attr_found.full = *(style->map + id + 1); + 5964: 1833 adds r3, r6, r0 + if(attr_found.bits.state == attr_goal.bits.state) { + 5966: 785b ldrb r3, [r3, #1] + 5968: ea83 2314 eor.w r3, r3, r4, lsr #8 + 596c: 065b lsls r3, r3, #25 + 596e: d107 bne.n 5980 <_lv_style_set_color+0x38> + _lv_memcpy_small(style->map + id + sizeof(lv_style_property_t), &color, sizeof(lv_color_t)); + 5970: 3002 adds r0, #2 + 5972: 4b20 ldr r3, [pc, #128] ; (59f4 <_lv_style_set_color+0xac>) + 5974: 2202 movs r2, #2 + 5976: a903 add r1, sp, #12 + 5978: 4430 add r0, r6 + 597a: 4798 blx r3 +} + 597c: b006 add sp, #24 + 597e: bd70 pop {r4, r5, r6, pc} + lv_style_property_t end_mark = _LV_STYLE_CLOSEING_PROP; + 5980: 23ff movs r3, #255 ; 0xff + 5982: f8ad 3016 strh.w r3, [sp, #22] + uint16_t size = _lv_style_get_mem_size(style); + 5986: 4628 mov r0, r5 + 5988: 4b1b ldr r3, [pc, #108] ; (59f8 <_lv_style_set_color+0xb0>) + 598a: 4798 blx r3 + if(size == 0) size += end_mark_size; + 598c: 1e04 subs r4, r0, #0 + 598e: bf08 it eq + 5990: 2402 moveq r4, #2 + size += sizeof(lv_style_property_t) + sizeof(lv_color_t); + 5992: 3404 adds r4, #4 + style->map = lv_mem_realloc(style->map, size); + 5994: b2a4 uxth r4, r4 + 5996: 4b19 ldr r3, [pc, #100] ; (59fc <_lv_style_set_color+0xb4>) + 5998: 4621 mov r1, r4 + 599a: 4630 mov r0, r6 + 599c: 4798 blx r3 + LV_ASSERT_MEM(style->map); + 599e: 4b18 ldr r3, [pc, #96] ; (5a00 <_lv_style_set_color+0xb8>) + style->map = lv_mem_realloc(style->map, size); + 59a0: 6028 str r0, [r5, #0] + LV_ASSERT_MEM(style->map); + 59a2: 4798 blx r3 + 59a4: 4606 mov r6, r0 + 59a6: b968 cbnz r0, 59c4 <_lv_style_set_color+0x7c> + 59a8: 4b16 ldr r3, [pc, #88] ; (5a04 <_lv_style_set_color+0xbc>) + 59aa: 4917 ldr r1, [pc, #92] ; (5a08 <_lv_style_set_color+0xc0>) + 59ac: 9300 str r3, [sp, #0] + 59ae: f240 12b5 movw r2, #437 ; 0x1b5 + 59b2: 2003 movs r0, #3 + 59b4: 4c15 ldr r4, [pc, #84] ; (5a0c <_lv_style_set_color+0xc4>) + 59b6: 47a0 blx r4 + 59b8: 682a ldr r2, [r5, #0] + 59ba: 4815 ldr r0, [pc, #84] ; (5a10 <_lv_style_set_color+0xc8>) + 59bc: 4915 ldr r1, [pc, #84] ; (5a14 <_lv_style_set_color+0xcc>) + 59be: 4633 mov r3, r6 + 59c0: 4788 blx r1 + 59c2: e7fe b.n 59c2 <_lv_style_set_color+0x7a> + _lv_memcpy_small(style->map + size - new_prop_size - end_mark_size, &prop, sizeof(lv_style_property_t)); + 59c4: 6828 ldr r0, [r5, #0] + 59c6: 4e0b ldr r6, [pc, #44] ; (59f4 <_lv_style_set_color+0xac>) + 59c8: 1fa3 subs r3, r4, #6 + 59ca: f10d 010e add.w r1, sp, #14 + 59ce: 4418 add r0, r3 + 59d0: 2202 movs r2, #2 + 59d2: 47b0 blx r6 + _lv_memcpy_small(style->map + size - sizeof(lv_color_t) - end_mark_size, &color, sizeof(lv_color_t)); + 59d4: 6828 ldr r0, [r5, #0] + _lv_memcpy_small(style->map + size - new_prop_size - end_mark_size, &prop, sizeof(lv_style_property_t)); + 59d6: 1f23 subs r3, r4, #4 + _lv_memcpy_small(style->map + size - sizeof(lv_color_t) - end_mark_size, &color, sizeof(lv_color_t)); + 59d8: a903 add r1, sp, #12 + 59da: 4418 add r0, r3 + 59dc: 2202 movs r2, #2 + 59de: 47b0 blx r6 + _lv_memcpy_small(style->map + size - end_mark_size, &end_mark, sizeof(end_mark)); + 59e0: 6828 ldr r0, [r5, #0] + _lv_memcpy_small(style->map + size - sizeof(lv_color_t) - end_mark_size, &color, sizeof(lv_color_t)); + 59e2: 3c02 subs r4, #2 + _lv_memcpy_small(style->map + size - end_mark_size, &end_mark, sizeof(end_mark)); + 59e4: 2202 movs r2, #2 + 59e6: f10d 0116 add.w r1, sp, #22 + 59ea: 4420 add r0, r4 + 59ec: 47b0 blx r6 + 59ee: e7c5 b.n 597c <_lv_style_set_color+0x34> + 59f0: 000054b5 .word 0x000054b5 + 59f4: 0000551f .word 0x0000551f + 59f8: 000057a9 .word 0x000057a9 + 59fc: 0000ee15 .word 0x0000ee15 + 5a00: 000017e1 .word 0x000017e1 + 5a04: 0001f94c .word 0x0001f94c + 5a08: 0001f7e6 .word 0x0001f7e6 + 5a0c: 0000e8e9 .word 0x0000e8e9 + 5a10: 0001edbe .word 0x0001edbe + 5a14: 000017e9 .word 0x000017e9 + +00005a18 <_lv_style_set_opa>: +{ + 5a18: b570 push {r4, r5, r6, lr} + 5a1a: 6806 ldr r6, [r0, #0] + int32_t id = get_property_index(style, prop); + 5a1c: 4b29 ldr r3, [pc, #164] ; (5ac4 <_lv_style_set_opa+0xac>) +{ + 5a1e: b086 sub sp, #24 + 5a20: 4605 mov r5, r0 + int32_t id = get_property_index(style, prop); + 5a22: 4630 mov r0, r6 +{ + 5a24: f8ad 100e strh.w r1, [sp, #14] + 5a28: f88d 200d strb.w r2, [sp, #13] + int32_t id = get_property_index(style, prop); + 5a2c: 460c mov r4, r1 + 5a2e: 4798 blx r3 + if(id >= 0) { + 5a30: 2800 cmp r0, #0 + 5a32: db0e blt.n 5a52 <_lv_style_set_opa+0x3a> + attr_found.full = *(style->map + id + 1); + 5a34: 1833 adds r3, r6, r0 + if(attr_found.bits.state == attr_goal.bits.state) { + 5a36: 785b ldrb r3, [r3, #1] + 5a38: ea83 2314 eor.w r3, r3, r4, lsr #8 + 5a3c: 065b lsls r3, r3, #25 + 5a3e: d108 bne.n 5a52 <_lv_style_set_opa+0x3a> + _lv_memcpy_small(style->map + id + sizeof(lv_style_property_t), &opa, sizeof(lv_opa_t)); + 5a40: 3002 adds r0, #2 + 5a42: 4b21 ldr r3, [pc, #132] ; (5ac8 <_lv_style_set_opa+0xb0>) + 5a44: 2201 movs r2, #1 + 5a46: f10d 010d add.w r1, sp, #13 + 5a4a: 4430 add r0, r6 + 5a4c: 4798 blx r3 +} + 5a4e: b006 add sp, #24 + 5a50: bd70 pop {r4, r5, r6, pc} + lv_style_property_t end_mark = _LV_STYLE_CLOSEING_PROP; + 5a52: 23ff movs r3, #255 ; 0xff + 5a54: f8ad 3016 strh.w r3, [sp, #22] + uint16_t size = _lv_style_get_mem_size(style); + 5a58: 4628 mov r0, r5 + 5a5a: 4b1c ldr r3, [pc, #112] ; (5acc <_lv_style_set_opa+0xb4>) + 5a5c: 4798 blx r3 + if(size == 0) size += end_mark_size; + 5a5e: 1e04 subs r4, r0, #0 + 5a60: bf08 it eq + 5a62: 2402 moveq r4, #2 + size += sizeof(lv_style_property_t) + sizeof(lv_opa_t); + 5a64: 3403 adds r4, #3 + style->map = lv_mem_realloc(style->map, size); + 5a66: b2a4 uxth r4, r4 + 5a68: 4b19 ldr r3, [pc, #100] ; (5ad0 <_lv_style_set_opa+0xb8>) + 5a6a: 4621 mov r1, r4 + 5a6c: 4630 mov r0, r6 + 5a6e: 4798 blx r3 + LV_ASSERT_MEM(style->map); + 5a70: 4b18 ldr r3, [pc, #96] ; (5ad4 <_lv_style_set_opa+0xbc>) + style->map = lv_mem_realloc(style->map, size); + 5a72: 6028 str r0, [r5, #0] + LV_ASSERT_MEM(style->map); + 5a74: 4798 blx r3 + 5a76: 4606 mov r6, r0 + 5a78: b968 cbnz r0, 5a96 <_lv_style_set_opa+0x7e> + 5a7a: 4b17 ldr r3, [pc, #92] ; (5ad8 <_lv_style_set_opa+0xc0>) + 5a7c: 4917 ldr r1, [pc, #92] ; (5adc <_lv_style_set_opa+0xc4>) + 5a7e: 9300 str r3, [sp, #0] + 5a80: f44f 72f2 mov.w r2, #484 ; 0x1e4 + 5a84: 2003 movs r0, #3 + 5a86: 4c16 ldr r4, [pc, #88] ; (5ae0 <_lv_style_set_opa+0xc8>) + 5a88: 47a0 blx r4 + 5a8a: 682a ldr r2, [r5, #0] + 5a8c: 4815 ldr r0, [pc, #84] ; (5ae4 <_lv_style_set_opa+0xcc>) + 5a8e: 4916 ldr r1, [pc, #88] ; (5ae8 <_lv_style_set_opa+0xd0>) + 5a90: 4633 mov r3, r6 + 5a92: 4788 blx r1 + 5a94: e7fe b.n 5a94 <_lv_style_set_opa+0x7c> + _lv_memcpy_small(style->map + size - new_prop_size - end_mark_size, &prop, sizeof(lv_style_property_t)); + 5a96: 6828 ldr r0, [r5, #0] + 5a98: 4e0b ldr r6, [pc, #44] ; (5ac8 <_lv_style_set_opa+0xb0>) + 5a9a: 1f63 subs r3, r4, #5 + 5a9c: f10d 010e add.w r1, sp, #14 + 5aa0: 4418 add r0, r3 + 5aa2: 2202 movs r2, #2 + 5aa4: 47b0 blx r6 + _lv_memcpy_small(style->map + size - sizeof(lv_opa_t) - end_mark_size, &opa, sizeof(lv_opa_t)); + 5aa6: 6828 ldr r0, [r5, #0] + _lv_memcpy_small(style->map + size - new_prop_size - end_mark_size, &prop, sizeof(lv_style_property_t)); + 5aa8: 1ee3 subs r3, r4, #3 + _lv_memcpy_small(style->map + size - sizeof(lv_opa_t) - end_mark_size, &opa, sizeof(lv_opa_t)); + 5aaa: f10d 010d add.w r1, sp, #13 + 5aae: 4418 add r0, r3 + 5ab0: 2201 movs r2, #1 + 5ab2: 47b0 blx r6 + _lv_memcpy_small(style->map + size - end_mark_size, &end_mark, sizeof(end_mark)); + 5ab4: 6828 ldr r0, [r5, #0] + _lv_memcpy_small(style->map + size - sizeof(lv_opa_t) - end_mark_size, &opa, sizeof(lv_opa_t)); + 5ab6: 3c02 subs r4, #2 + _lv_memcpy_small(style->map + size - end_mark_size, &end_mark, sizeof(end_mark)); + 5ab8: 2202 movs r2, #2 + 5aba: f10d 0116 add.w r1, sp, #22 + 5abe: 4420 add r0, r4 + 5ac0: 47b0 blx r6 + 5ac2: e7c4 b.n 5a4e <_lv_style_set_opa+0x36> + 5ac4: 000054b5 .word 0x000054b5 + 5ac8: 0000551f .word 0x0000551f + 5acc: 000057a9 .word 0x000057a9 + 5ad0: 0000ee15 .word 0x0000ee15 + 5ad4: 000017e1 .word 0x000017e1 + 5ad8: 0001f960 .word 0x0001f960 + 5adc: 0001f7e6 .word 0x0001f7e6 + 5ae0: 0000e8e9 .word 0x0000e8e9 + 5ae4: 0001edbe .word 0x0001edbe + 5ae8: 000017e9 .word 0x000017e9 + +00005aec <_lv_style_set_ptr>: +{ + 5aec: b570 push {r4, r5, r6, lr} + 5aee: 6806 ldr r6, [r0, #0] + int32_t id = get_property_index(style, prop); + 5af0: 4b28 ldr r3, [pc, #160] ; (5b94 <_lv_style_set_ptr+0xa8>) +{ + 5af2: b086 sub sp, #24 + 5af4: 4605 mov r5, r0 + int32_t id = get_property_index(style, prop); + 5af6: 4630 mov r0, r6 +{ + 5af8: 9202 str r2, [sp, #8] + 5afa: f8ad 100e strh.w r1, [sp, #14] + int32_t id = get_property_index(style, prop); + 5afe: 460c mov r4, r1 + 5b00: 4798 blx r3 + if(id >= 0) { + 5b02: 2800 cmp r0, #0 + 5b04: db0d blt.n 5b22 <_lv_style_set_ptr+0x36> + attr_found.full = *(style->map + id + 1); + 5b06: 1833 adds r3, r6, r0 + if(attr_found.bits.state == attr_goal.bits.state) { + 5b08: 785b ldrb r3, [r3, #1] + 5b0a: ea83 2314 eor.w r3, r3, r4, lsr #8 + 5b0e: 065b lsls r3, r3, #25 + 5b10: d107 bne.n 5b22 <_lv_style_set_ptr+0x36> + _lv_memcpy_small(style->map + id + sizeof(lv_style_property_t), &p, sizeof(const void *)); + 5b12: 3002 adds r0, #2 + 5b14: 4b20 ldr r3, [pc, #128] ; (5b98 <_lv_style_set_ptr+0xac>) + 5b16: 2204 movs r2, #4 + 5b18: a902 add r1, sp, #8 + 5b1a: 4430 add r0, r6 + 5b1c: 4798 blx r3 +} + 5b1e: b006 add sp, #24 + 5b20: bd70 pop {r4, r5, r6, pc} + lv_style_property_t end_mark = _LV_STYLE_CLOSEING_PROP; + 5b22: 23ff movs r3, #255 ; 0xff + 5b24: f8ad 3016 strh.w r3, [sp, #22] + uint16_t size = _lv_style_get_mem_size(style); + 5b28: 4628 mov r0, r5 + 5b2a: 4b1c ldr r3, [pc, #112] ; (5b9c <_lv_style_set_ptr+0xb0>) + 5b2c: 4798 blx r3 + if(size == 0) size += end_mark_size; + 5b2e: 1e04 subs r4, r0, #0 + 5b30: bf08 it eq + 5b32: 2402 moveq r4, #2 + size += sizeof(lv_style_property_t) + sizeof(const void *); + 5b34: 3406 adds r4, #6 + style->map = lv_mem_realloc(style->map, size); + 5b36: b2a4 uxth r4, r4 + 5b38: 4b19 ldr r3, [pc, #100] ; (5ba0 <_lv_style_set_ptr+0xb4>) + 5b3a: 4621 mov r1, r4 + 5b3c: 4630 mov r0, r6 + 5b3e: 4798 blx r3 + LV_ASSERT_MEM(style->map); + 5b40: 4b18 ldr r3, [pc, #96] ; (5ba4 <_lv_style_set_ptr+0xb8>) + style->map = lv_mem_realloc(style->map, size); + 5b42: 6028 str r0, [r5, #0] + LV_ASSERT_MEM(style->map); + 5b44: 4798 blx r3 + 5b46: 4606 mov r6, r0 + 5b48: b968 cbnz r0, 5b66 <_lv_style_set_ptr+0x7a> + 5b4a: 4b17 ldr r3, [pc, #92] ; (5ba8 <_lv_style_set_ptr+0xbc>) + 5b4c: 4917 ldr r1, [pc, #92] ; (5bac <_lv_style_set_ptr+0xc0>) + 5b4e: 9300 str r3, [sp, #0] + 5b50: f240 2213 movw r2, #531 ; 0x213 + 5b54: 2003 movs r0, #3 + 5b56: 4c16 ldr r4, [pc, #88] ; (5bb0 <_lv_style_set_ptr+0xc4>) + 5b58: 47a0 blx r4 + 5b5a: 682a ldr r2, [r5, #0] + 5b5c: 4815 ldr r0, [pc, #84] ; (5bb4 <_lv_style_set_ptr+0xc8>) + 5b5e: 4916 ldr r1, [pc, #88] ; (5bb8 <_lv_style_set_ptr+0xcc>) + 5b60: 4633 mov r3, r6 + 5b62: 4788 blx r1 + 5b64: e7fe b.n 5b64 <_lv_style_set_ptr+0x78> + _lv_memcpy_small(style->map + size - new_prop_size - end_mark_size, &prop, sizeof(lv_style_property_t)); + 5b66: 6828 ldr r0, [r5, #0] + 5b68: 4e0b ldr r6, [pc, #44] ; (5b98 <_lv_style_set_ptr+0xac>) + 5b6a: f1a4 0308 sub.w r3, r4, #8 + 5b6e: f10d 010e add.w r1, sp, #14 + 5b72: 4418 add r0, r3 + 5b74: 2202 movs r2, #2 + 5b76: 47b0 blx r6 + _lv_memcpy_small(style->map + size - sizeof(const void *) - end_mark_size, &p, sizeof(const void *)); + 5b78: 6828 ldr r0, [r5, #0] + _lv_memcpy_small(style->map + size - new_prop_size - end_mark_size, &prop, sizeof(lv_style_property_t)); + 5b7a: 1fa3 subs r3, r4, #6 + _lv_memcpy_small(style->map + size - sizeof(const void *) - end_mark_size, &p, sizeof(const void *)); + 5b7c: a902 add r1, sp, #8 + 5b7e: 4418 add r0, r3 + 5b80: 2204 movs r2, #4 + 5b82: 47b0 blx r6 + _lv_memcpy_small(style->map + size - end_mark_size, &end_mark, sizeof(end_mark)); + 5b84: 6828 ldr r0, [r5, #0] + _lv_memcpy_small(style->map + size - sizeof(const void *) - end_mark_size, &p, sizeof(const void *)); + 5b86: 3c02 subs r4, #2 + _lv_memcpy_small(style->map + size - end_mark_size, &end_mark, sizeof(end_mark)); + 5b88: 2202 movs r2, #2 + 5b8a: f10d 0116 add.w r1, sp, #22 + 5b8e: 4420 add r0, r4 + 5b90: 47b0 blx r6 + 5b92: e7c4 b.n 5b1e <_lv_style_set_ptr+0x32> + 5b94: 000054b5 .word 0x000054b5 + 5b98: 0000551f .word 0x0000551f + 5b9c: 000057a9 .word 0x000057a9 + 5ba0: 0000ee15 .word 0x0000ee15 + 5ba4: 000017e1 .word 0x000017e1 + 5ba8: 0001f972 .word 0x0001f972 + 5bac: 0001f7e6 .word 0x0001f7e6 + 5bb0: 0000e8e9 .word 0x0000e8e9 + 5bb4: 0001edbe .word 0x0001edbe + 5bb8: 000017e9 .word 0x000017e9 + +00005bbc <_lv_style_get_int>: +{ + 5bbc: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 5bc0: 460e mov r6, r1 + 5bc2: 4617 mov r7, r2 + if(style == NULL) return -1; + 5bc4: 4605 mov r5, r0 + 5bc6: b1c0 cbz r0, 5bfa <_lv_style_get_int+0x3e> + if(style->map == NULL) return -1; + 5bc8: f8d0 8000 ldr.w r8, [r0] + 5bcc: f1b8 0f00 cmp.w r8, #0 + 5bd0: d013 beq.n 5bfa <_lv_style_get_int+0x3e> + int32_t id = get_property_index(style, prop); + 5bd2: 4b0b ldr r3, [pc, #44] ; (5c00 <_lv_style_get_int+0x44>) + 5bd4: 4640 mov r0, r8 + 5bd6: 4798 blx r3 + if(id < 0) { + 5bd8: 1e04 subs r4, r0, #0 + 5bda: db0e blt.n 5bfa <_lv_style_get_int+0x3e> + _lv_memcpy_small(res, &style->map[id + sizeof(lv_style_property_t)], sizeof(lv_style_int_t)); + 5bdc: 1ca1 adds r1, r4, #2 + 5bde: 4b09 ldr r3, [pc, #36] ; (5c04 <_lv_style_get_int+0x48>) + 5be0: 4638 mov r0, r7 + 5be2: 2202 movs r2, #2 + 5be4: 4441 add r1, r8 + 5be6: 4798 blx r3 + attr_act.full = style->map[id + 1]; + 5be8: 682b ldr r3, [r5, #0] + 5bea: 4423 add r3, r4 + 5bec: 7858 ldrb r0, [r3, #1] + return attr_act.bits.state & attr_goal.bits.state; + 5bee: f3c0 0006 ubfx r0, r0, #0, #7 + 5bf2: ea00 2016 and.w r0, r0, r6, lsr #8 +} + 5bf6: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + if(style == NULL) return -1; + 5bfa: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 5bfe: e7fa b.n 5bf6 <_lv_style_get_int+0x3a> + 5c00: 000054b5 .word 0x000054b5 + 5c04: 0000551f .word 0x0000551f + +00005c08 <_lv_style_get_opa>: +{ + 5c08: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 5c0c: 460e mov r6, r1 + 5c0e: 4617 mov r7, r2 + if(style == NULL) return -1; + 5c10: 4605 mov r5, r0 + 5c12: b1c0 cbz r0, 5c46 <_lv_style_get_opa+0x3e> + if(style->map == NULL) return -1; + 5c14: f8d0 8000 ldr.w r8, [r0] + 5c18: f1b8 0f00 cmp.w r8, #0 + 5c1c: d013 beq.n 5c46 <_lv_style_get_opa+0x3e> + int32_t id = get_property_index(style, prop); + 5c1e: 4b0b ldr r3, [pc, #44] ; (5c4c <_lv_style_get_opa+0x44>) + 5c20: 4640 mov r0, r8 + 5c22: 4798 blx r3 + if(id < 0) { + 5c24: 1e04 subs r4, r0, #0 + 5c26: db0e blt.n 5c46 <_lv_style_get_opa+0x3e> + _lv_memcpy_small(res, &style->map[id + sizeof(lv_style_property_t)], sizeof(lv_opa_t)); + 5c28: 1ca1 adds r1, r4, #2 + 5c2a: 4b09 ldr r3, [pc, #36] ; (5c50 <_lv_style_get_opa+0x48>) + 5c2c: 4638 mov r0, r7 + 5c2e: 2201 movs r2, #1 + 5c30: 4441 add r1, r8 + 5c32: 4798 blx r3 + attr_act.full = style->map[id + 1]; + 5c34: 682b ldr r3, [r5, #0] + 5c36: 4423 add r3, r4 + 5c38: 7858 ldrb r0, [r3, #1] + return attr_act.bits.state & attr_goal.bits.state; + 5c3a: f3c0 0006 ubfx r0, r0, #0, #7 + 5c3e: ea00 2016 and.w r0, r0, r6, lsr #8 +} + 5c42: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + if(style == NULL) return -1; + 5c46: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 5c4a: e7fa b.n 5c42 <_lv_style_get_opa+0x3a> + 5c4c: 000054b5 .word 0x000054b5 + 5c50: 0000551f .word 0x0000551f + +00005c54 <_lv_style_get_ptr>: +{ + 5c54: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 5c58: 460e mov r6, r1 + 5c5a: 4617 mov r7, r2 + if(style == NULL) return -1; + 5c5c: 4605 mov r5, r0 + 5c5e: b1c0 cbz r0, 5c92 <_lv_style_get_ptr+0x3e> + if(style->map == NULL) return -1; + 5c60: f8d0 8000 ldr.w r8, [r0] + 5c64: f1b8 0f00 cmp.w r8, #0 + 5c68: d013 beq.n 5c92 <_lv_style_get_ptr+0x3e> + int32_t id = get_property_index(style, prop); + 5c6a: 4b0b ldr r3, [pc, #44] ; (5c98 <_lv_style_get_ptr+0x44>) + 5c6c: 4640 mov r0, r8 + 5c6e: 4798 blx r3 + if(id < 0) { + 5c70: 1e04 subs r4, r0, #0 + 5c72: db0e blt.n 5c92 <_lv_style_get_ptr+0x3e> + _lv_memcpy_small(res, &style->map[id + sizeof(lv_style_property_t)], sizeof(const void *)); + 5c74: 1ca1 adds r1, r4, #2 + 5c76: 4b09 ldr r3, [pc, #36] ; (5c9c <_lv_style_get_ptr+0x48>) + 5c78: 4638 mov r0, r7 + 5c7a: 2204 movs r2, #4 + 5c7c: 4441 add r1, r8 + 5c7e: 4798 blx r3 + attr_act.full = style->map[id + 1]; + 5c80: 682b ldr r3, [r5, #0] + 5c82: 4423 add r3, r4 + 5c84: 7858 ldrb r0, [r3, #1] + return attr_act.bits.state & attr_goal.bits.state; + 5c86: f3c0 0006 ubfx r0, r0, #0, #7 + 5c8a: ea00 2016 and.w r0, r0, r6, lsr #8 +} + 5c8e: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + if(style == NULL) return -1; + 5c92: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff + 5c96: e7fa b.n 5c8e <_lv_style_get_ptr+0x3a> + 5c98: 000054b5 .word 0x000054b5 + 5c9c: 0000551f .word 0x0000551f + +00005ca0 : + if(!list->has_local) return NULL; + 5ca0: 7942 ldrb r2, [r0, #5] + 5ca2: f012 0301 ands.w r3, r2, #1 + 5ca6: d005 beq.n 5cb4 + if(list->has_trans) return list->style_list[1]; + 5ca8: 6803 ldr r3, [r0, #0] + 5caa: 0792 lsls r2, r2, #30 + 5cac: bf4c ite mi + 5cae: 6858 ldrmi r0, [r3, #4] + else return list->style_list[0]; + 5cb0: 6818 ldrpl r0, [r3, #0] + 5cb2: 4770 bx lr + if(!list->has_local) return NULL; + 5cb4: 4618 mov r0, r3 +} + 5cb6: 4770 bx lr + +00005cb8 <_lv_style_list_get_transition_style>: + if(!list->has_trans) return NULL; + 5cb8: 7943 ldrb r3, [r0, #5] + 5cba: f013 0302 ands.w r3, r3, #2 + return list->style_list[0]; + 5cbe: bf1a itte ne + 5cc0: 6803 ldrne r3, [r0, #0] + 5cc2: 6818 ldrne r0, [r3, #0] + if(!list->has_trans) return NULL; + 5cc4: 4618 moveq r0, r3 +} + 5cc6: 4770 bx lr + +00005cc8 <_lv_style_list_reset>: +{ + 5cc8: b538 push {r3, r4, r5, lr} + if(list == NULL) return; + 5cca: 4604 mov r4, r0 + 5ccc: b328 cbz r0, 5d1a <_lv_style_list_reset+0x52> + if(list->has_local) { + 5cce: 7943 ldrb r3, [r0, #5] + 5cd0: 07da lsls r2, r3, #31 + 5cd2: d508 bpl.n 5ce6 <_lv_style_list_reset+0x1e> + lv_style_t * local = lv_style_list_get_local_style(list); + 5cd4: 4b11 ldr r3, [pc, #68] ; (5d1c <_lv_style_list_reset+0x54>) + 5cd6: 4798 blx r3 + if(local) { + 5cd8: 4605 mov r5, r0 + 5cda: b120 cbz r0, 5ce6 <_lv_style_list_reset+0x1e> + lv_style_reset(local); + 5cdc: 4b10 ldr r3, [pc, #64] ; (5d20 <_lv_style_list_reset+0x58>) + 5cde: 4798 blx r3 + lv_mem_free(local); + 5ce0: 4b10 ldr r3, [pc, #64] ; (5d24 <_lv_style_list_reset+0x5c>) + 5ce2: 4628 mov r0, r5 + 5ce4: 4798 blx r3 + if(list->has_trans) { + 5ce6: 7963 ldrb r3, [r4, #5] + 5ce8: 079b lsls r3, r3, #30 + 5cea: d509 bpl.n 5d00 <_lv_style_list_reset+0x38> + lv_style_t * trans = _lv_style_list_get_transition_style(list); + 5cec: 4b0e ldr r3, [pc, #56] ; (5d28 <_lv_style_list_reset+0x60>) + 5cee: 4620 mov r0, r4 + 5cf0: 4798 blx r3 + if(trans) { + 5cf2: 4605 mov r5, r0 + 5cf4: b120 cbz r0, 5d00 <_lv_style_list_reset+0x38> + lv_style_reset(trans); + 5cf6: 4b0a ldr r3, [pc, #40] ; (5d20 <_lv_style_list_reset+0x58>) + 5cf8: 4798 blx r3 + lv_mem_free(trans); + 5cfa: 4b0a ldr r3, [pc, #40] ; (5d24 <_lv_style_list_reset+0x5c>) + 5cfc: 4628 mov r0, r5 + 5cfe: 4798 blx r3 + if(list->style_cnt > 0) lv_mem_free(list->style_list); + 5d00: 7923 ldrb r3, [r4, #4] + 5d02: b113 cbz r3, 5d0a <_lv_style_list_reset+0x42> + 5d04: 6820 ldr r0, [r4, #0] + 5d06: 4b07 ldr r3, [pc, #28] ; (5d24 <_lv_style_list_reset+0x5c>) + 5d08: 4798 blx r3 + list->style_list = NULL; + 5d0a: 2300 movs r3, #0 + 5d0c: 6023 str r3, [r4, #0] + list->style_cnt = 0; + 5d0e: 88a3 ldrh r3, [r4, #4] + 5d10: f423 63ff bic.w r3, r3, #2040 ; 0x7f8 + 5d14: f023 0307 bic.w r3, r3, #7 + 5d18: 80a3 strh r3, [r4, #4] +} + 5d1a: bd38 pop {r3, r4, r5, pc} + 5d1c: 00005ca1 .word 0x00005ca1 + 5d20: 00005795 .word 0x00005795 + 5d24: 0000eae5 .word 0x0000eae5 + 5d28: 00005cb9 .word 0x00005cb9 + +00005d2c : +{ + 5d2c: b570 push {r4, r5, r6, lr} + 5d2e: 460c mov r4, r1 + _lv_style_list_reset(list_dest); + 5d30: 4b26 ldr r3, [pc, #152] ; (5dcc ) +{ + 5d32: 4605 mov r5, r0 + _lv_style_list_reset(list_dest); + 5d34: 4798 blx r3 + if(list_src->style_list == NULL) return; + 5d36: 6823 ldr r3, [r4, #0] + 5d38: b1b3 cbz r3, 5d68 + if(list_src->has_local == 0) { + 5d3a: 7963 ldrb r3, [r4, #5] + list_dest->style_list = lv_mem_alloc((list_src->style_cnt - 1) * sizeof(lv_style_t *)); + 5d3c: 7920 ldrb r0, [r4, #4] + 5d3e: 4e24 ldr r6, [pc, #144] ; (5dd0 ) + if(list_src->has_local == 0) { + 5d40: f013 0f01 tst.w r3, #1 + if(list_src->has_trans) { + 5d44: f003 0202 and.w r2, r3, #2 + 5d48: 4b22 ldr r3, [pc, #136] ; (5dd4 ) + if(list_src->has_local == 0) { + 5d4a: d117 bne.n 5d7c + if(list_src->has_trans) { + 5d4c: b16a cbz r2, 5d6a + list_dest->style_list = lv_mem_alloc((list_src->style_cnt - 1) * sizeof(lv_style_t *)); + 5d4e: 3801 subs r0, #1 + 5d50: 0080 lsls r0, r0, #2 + 5d52: 4798 blx r3 + 5d54: 6028 str r0, [r5, #0] + _lv_memcpy(list_dest->style_list, list_src->style_list + 1, (list_src->style_cnt - 1) * sizeof(lv_style_t *)); + 5d56: 7922 ldrb r2, [r4, #4] + 5d58: 6821 ldr r1, [r4, #0] + 5d5a: 3a01 subs r2, #1 + 5d5c: 0092 lsls r2, r2, #2 + 5d5e: 3104 adds r1, #4 + 5d60: 47b0 blx r6 + list_dest->style_cnt = list_src->style_cnt - 1; + 5d62: 7923 ldrb r3, [r4, #4] + 5d64: 3b01 subs r3, #1 + list_dest->style_cnt = list_src->style_cnt; + 5d66: 712b strb r3, [r5, #4] +} + 5d68: bd70 pop {r4, r5, r6, pc} + list_dest->style_list = lv_mem_alloc(list_src->style_cnt * sizeof(lv_style_t *)); + 5d6a: 0080 lsls r0, r0, #2 + 5d6c: 4798 blx r3 + 5d6e: 6028 str r0, [r5, #0] + _lv_memcpy(list_dest->style_list, list_src->style_list, list_src->style_cnt * sizeof(lv_style_t *)); + 5d70: 7922 ldrb r2, [r4, #4] + 5d72: 6821 ldr r1, [r4, #0] + 5d74: 0092 lsls r2, r2, #2 + 5d76: 47b0 blx r6 + list_dest->style_cnt = list_src->style_cnt; + 5d78: 7923 ldrb r3, [r4, #4] + 5d7a: e7f4 b.n 5d66 + if(list_src->has_trans) { + 5d7c: b1ca cbz r2, 5db2 + list_dest->style_list = lv_mem_alloc((list_src->style_cnt - 2) * sizeof(lv_style_t *)); + 5d7e: 3802 subs r0, #2 + 5d80: 0080 lsls r0, r0, #2 + 5d82: 4798 blx r3 + 5d84: 6028 str r0, [r5, #0] + _lv_memcpy(list_dest->style_list, list_src->style_list + 2, (list_src->style_cnt - 2) * sizeof(lv_style_t *)); + 5d86: 7922 ldrb r2, [r4, #4] + 5d88: 6821 ldr r1, [r4, #0] + 5d8a: 3a02 subs r2, #2 + 5d8c: 0092 lsls r2, r2, #2 + 5d8e: 3108 adds r1, #8 + 5d90: 47b0 blx r6 + list_dest->style_cnt = list_src->style_cnt - 2; + 5d92: 7923 ldrb r3, [r4, #4] + 5d94: 3b02 subs r3, #2 + list_dest->style_cnt = list_src->style_cnt - 1; + 5d96: b2db uxtb r3, r3 + list_dest->style_cnt = list_src->style_cnt - 2; + 5d98: 712b strb r3, [r5, #4] + lv_style_t * local_style = get_alloc_local_style(list_dest); + 5d9a: 4e0f ldr r6, [pc, #60] ; (5dd8 ) + 5d9c: 4628 mov r0, r5 + 5d9e: 47b0 blx r6 + 5da0: 4605 mov r5, r0 + lv_style_copy(local_style, get_alloc_local_style((lv_style_list_t *)list_src)); + 5da2: 4620 mov r0, r4 + 5da4: 47b0 blx r6 + 5da6: 4b0d ldr r3, [pc, #52] ; (5ddc ) + 5da8: 4601 mov r1, r0 + 5daa: 4628 mov r0, r5 +} + 5dac: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + lv_style_copy(local_style, get_alloc_local_style((lv_style_list_t *)list_src)); + 5db0: 4718 bx r3 + list_dest->style_list = lv_mem_alloc((list_src->style_cnt - 1) * sizeof(lv_style_t *)); + 5db2: 3801 subs r0, #1 + 5db4: 0080 lsls r0, r0, #2 + 5db6: 4798 blx r3 + 5db8: 6028 str r0, [r5, #0] + _lv_memcpy(list_dest->style_list, list_src->style_list + 1, (list_src->style_cnt - 1) * sizeof(lv_style_t *)); + 5dba: 7922 ldrb r2, [r4, #4] + 5dbc: 6821 ldr r1, [r4, #0] + 5dbe: 3a01 subs r2, #1 + 5dc0: 0092 lsls r2, r2, #2 + 5dc2: 3104 adds r1, #4 + 5dc4: 47b0 blx r6 + list_dest->style_cnt = list_src->style_cnt - 1; + 5dc6: 7923 ldrb r3, [r4, #4] + 5dc8: 3b01 subs r3, #1 + 5dca: e7e4 b.n 5d96 + 5dcc: 00005cc9 .word 0x00005cc9 + 5dd0: 0000ec31 .word 0x0000ec31 + 5dd4: 0000ea2d .word 0x0000ea2d + 5dd8: 000056f5 .word 0x000056f5 + 5ddc: 000057d9 .word 0x000057d9 + +00005de0 <_lv_style_list_add_trans_style>: + if(list->has_trans) return _lv_style_list_get_transition_style(list); + 5de0: 7943 ldrb r3, [r0, #5] + 5de2: 079a lsls r2, r3, #30 +{ + 5de4: b573 push {r0, r1, r4, r5, r6, lr} + 5de6: 4605 mov r5, r0 + if(list->has_trans) return _lv_style_list_get_transition_style(list); + 5de8: d504 bpl.n 5df4 <_lv_style_list_add_trans_style+0x14> + 5dea: 4b1d ldr r3, [pc, #116] ; (5e60 <_lv_style_list_add_trans_style+0x80>) +} + 5dec: b002 add sp, #8 + 5dee: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + if(list->has_trans) return _lv_style_list_get_transition_style(list); + 5df2: 4718 bx r3 + lv_style_t * trans_style = lv_mem_alloc(sizeof(lv_style_t)); + 5df4: 4b1b ldr r3, [pc, #108] ; (5e64 <_lv_style_list_add_trans_style+0x84>) + 5df6: 2004 movs r0, #4 + 5df8: 4798 blx r3 + LV_ASSERT_MEM(trans_style); + 5dfa: 4b1b ldr r3, [pc, #108] ; (5e68 <_lv_style_list_add_trans_style+0x88>) + lv_style_t * trans_style = lv_mem_alloc(sizeof(lv_style_t)); + 5dfc: 4604 mov r4, r0 + LV_ASSERT_MEM(trans_style); + 5dfe: 4798 blx r3 + 5e00: 4606 mov r6, r0 + 5e02: b968 cbnz r0, 5e20 <_lv_style_list_add_trans_style+0x40> + 5e04: 4b19 ldr r3, [pc, #100] ; (5e6c <_lv_style_list_add_trans_style+0x8c>) + 5e06: 491a ldr r1, [pc, #104] ; (5e70 <_lv_style_list_add_trans_style+0x90>) + 5e08: 9300 str r3, [sp, #0] + 5e0a: f240 22cd movw r2, #717 ; 0x2cd + 5e0e: 2003 movs r0, #3 + 5e10: 4d18 ldr r5, [pc, #96] ; (5e74 <_lv_style_list_add_trans_style+0x94>) + 5e12: 47a8 blx r5 + 5e14: 4818 ldr r0, [pc, #96] ; (5e78 <_lv_style_list_add_trans_style+0x98>) + 5e16: 4919 ldr r1, [pc, #100] ; (5e7c <_lv_style_list_add_trans_style+0x9c>) + 5e18: 4622 mov r2, r4 + 5e1a: 4633 mov r3, r6 + 5e1c: 4788 blx r1 + 5e1e: e7fe b.n 5e1e <_lv_style_list_add_trans_style+0x3e> + if(trans_style == NULL) { + 5e20: b95c cbnz r4, 5e3a <_lv_style_list_add_trans_style+0x5a> + LV_LOG_WARN("lv_style_list_add_trans_style: couldn't create transition style"); + 5e22: 4b17 ldr r3, [pc, #92] ; (5e80 <_lv_style_list_add_trans_style+0xa0>) + 5e24: 9300 str r3, [sp, #0] + 5e26: 4912 ldr r1, [pc, #72] ; (5e70 <_lv_style_list_add_trans_style+0x90>) + 5e28: 4b10 ldr r3, [pc, #64] ; (5e6c <_lv_style_list_add_trans_style+0x8c>) + 5e2a: 4d12 ldr r5, [pc, #72] ; (5e74 <_lv_style_list_add_trans_style+0x94>) + 5e2c: f240 22cf movw r2, #719 ; 0x2cf + 5e30: 2002 movs r0, #2 + 5e32: 47a8 blx r5 +} + 5e34: 4620 mov r0, r4 + 5e36: b002 add sp, #8 + 5e38: bd70 pop {r4, r5, r6, pc} + lv_style_init(trans_style); + 5e3a: 4b12 ldr r3, [pc, #72] ; (5e84 <_lv_style_list_add_trans_style+0xa4>) + 5e3c: 4620 mov r0, r4 + 5e3e: 4798 blx r3 + _lv_style_list_add_style(list, trans_style); + 5e40: 4621 mov r1, r4 + 5e42: 4b11 ldr r3, [pc, #68] ; (5e88 <_lv_style_list_add_trans_style+0xa8>) + 5e44: 4628 mov r0, r5 + 5e46: 4798 blx r3 + list->has_trans = 1; + 5e48: 796b ldrb r3, [r5, #5] + 5e4a: f043 0302 orr.w r3, r3, #2 + 5e4e: 716b strb r3, [r5, #5] + if(list->has_local) { + 5e50: 07db lsls r3, r3, #31 + lv_style_t * tmp = list->style_list[0]; + 5e52: bf42 ittt mi + 5e54: 682b ldrmi r3, [r5, #0] + list->style_list[0] = list->style_list[1]; + 5e56: e9d3 2100 ldrdmi r2, r1, [r3] + list->style_list[1] = tmp; + 5e5a: e9c3 1200 strdmi r1, r2, [r3] + 5e5e: e7e9 b.n 5e34 <_lv_style_list_add_trans_style+0x54> + 5e60: 00005cb9 .word 0x00005cb9 + 5e64: 0000ea2d .word 0x0000ea2d + 5e68: 000017e1 .word 0x000017e1 + 5e6c: 0001f984 .word 0x0001f984 + 5e70: 0001f7e6 .word 0x0001f7e6 + 5e74: 0000e8e9 .word 0x0000e8e9 + 5e78: 0001edbe .word 0x0001edbe + 5e7c: 000017e9 .word 0x000017e9 + 5e80: 0001f8af .word 0x0001f8af + 5e84: 00005531 .word 0x00005531 + 5e88: 00005619 .word 0x00005619 + +00005e8c <_lv_style_list_get_int>: +{ + 5e8c: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} + 5e90: 460f mov r7, r1 + 5e92: 4690 mov r8, r2 + if(list == NULL) return LV_RES_INV; + 5e94: 4605 mov r5, r0 + 5e96: b318 cbz r0, 5ee0 <_lv_style_list_get_int+0x54> + if(list->style_list == NULL) return LV_RES_INV; + 5e98: 6800 ldr r0, [r0, #0] + 5e9a: b308 cbz r0, 5ee0 <_lv_style_list_get_int+0x54> + lv_style_int_t value_act = 0; + 5e9c: 2600 movs r6, #0 + lv_style_t * class = lv_style_list_get_style(list, ci); + 5e9e: 4b1b ldr r3, [pc, #108] ; (5f0c <_lv_style_list_get_int+0x80>) + int16_t weight_act = _lv_style_get_int(class, prop, &value_act); + 5ea0: f8df b06c ldr.w fp, [pc, #108] ; 5f10 <_lv_style_list_get_int+0x84> + lv_style_int_t value_act = 0; + 5ea4: f8ad 6006 strh.w r6, [sp, #6] + int16_t weight_goal = attr.full; + 5ea8: ea4f 2a11 mov.w sl, r1, lsr #8 + int16_t weight = -1; + 5eac: f04f 34ff mov.w r4, #4294967295 ; 0xffffffff + for(ci = 0; ci < list->style_cnt; ci++) { + 5eb0: 792a ldrb r2, [r5, #4] + 5eb2: fa0f f986 sxth.w r9, r6 + 5eb6: 4591 cmp r9, r2 + 5eb8: db03 blt.n 5ec2 <_lv_style_list_get_int+0x36> + if(weight >= 0) return LV_RES_OK; + 5eba: 43e0 mvns r0, r4 + if(list == NULL) return LV_RES_INV; + 5ebc: f3c0 30c0 ubfx r0, r0, #15, #1 + 5ec0: e00e b.n 5ee0 <_lv_style_list_get_int+0x54> + lv_style_t * class = lv_style_list_get_style(list, ci); + 5ec2: b2f1 uxtb r1, r6 + 5ec4: 4628 mov r0, r5 + 5ec6: 4798 blx r3 + int16_t weight_act = _lv_style_get_int(class, prop, &value_act); + 5ec8: f10d 0206 add.w r2, sp, #6 + 5ecc: 4639 mov r1, r7 + 5ece: 47d8 blx fp + if(weight_act == weight_goal) { + 5ed0: 4582 cmp sl, r0 + 5ed2: 4b0e ldr r3, [pc, #56] ; (5f0c <_lv_style_list_get_int+0x80>) + 5ed4: d107 bne.n 5ee6 <_lv_style_list_get_int+0x5a> + *res = value_act; + 5ed6: f8bd 3006 ldrh.w r3, [sp, #6] + 5eda: f8a8 3000 strh.w r3, [r8] + return LV_RES_OK; + 5ede: 2001 movs r0, #1 +} + 5ee0: b003 add sp, #12 + 5ee2: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + else if(list->has_trans && weight_act >= 0 && ci == 0 && !list->skip_trans) { + 5ee6: 796a ldrb r2, [r5, #5] + 5ee8: 0791 lsls r1, r2, #30 + 5eea: d506 bpl.n 5efa <_lv_style_list_get_int+0x6e> + 5eec: 2800 cmp r0, #0 + 5eee: db04 blt.n 5efa <_lv_style_list_get_int+0x6e> + 5ef0: f1b9 0f00 cmp.w r9, #0 + 5ef4: d101 bne.n 5efa <_lv_style_list_get_int+0x6e> + 5ef6: 0752 lsls r2, r2, #29 + 5ef8: d5ed bpl.n 5ed6 <_lv_style_list_get_int+0x4a> + else if(weight_act > weight) { + 5efa: 4284 cmp r4, r0 + *res = value_act; + 5efc: bfbe ittt lt + 5efe: f8bd 2006 ldrhlt.w r2, [sp, #6] + 5f02: f8a8 2000 strhlt.w r2, [r8] + 5f06: 4604 movlt r4, r0 + for(ci = 0; ci < list->style_cnt; ci++) { + 5f08: 3601 adds r6, #1 + 5f0a: e7d1 b.n 5eb0 <_lv_style_list_get_int+0x24> + 5f0c: 00005495 .word 0x00005495 + 5f10: 00005bbd .word 0x00005bbd + +00005f14 <_lv_style_list_get_color>: +{ + 5f14: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} + 5f18: 460f mov r7, r1 + 5f1a: 4690 mov r8, r2 + if(list == NULL) return LV_RES_INV; + 5f1c: 4605 mov r5, r0 + 5f1e: b310 cbz r0, 5f66 <_lv_style_list_get_color+0x52> + if(list->style_list == NULL) return LV_RES_INV; + 5f20: 6800 ldr r0, [r0, #0] + 5f22: b300 cbz r0, 5f66 <_lv_style_list_get_color+0x52> + lv_color_t value_act = { 0 }; + 5f24: 2600 movs r6, #0 + lv_style_t * class = lv_style_list_get_style(list, ci); + 5f26: 4b1b ldr r3, [pc, #108] ; (5f94 <_lv_style_list_get_color+0x80>) + int16_t weight_act = _lv_style_get_color(class, prop, &value_act); + 5f28: f8df b06c ldr.w fp, [pc, #108] ; 5f98 <_lv_style_list_get_color+0x84> + lv_color_t value_act = { 0 }; + 5f2c: f8ad 6004 strh.w r6, [sp, #4] + int16_t weight_goal = attr.full; + 5f30: ea4f 2a11 mov.w sl, r1, lsr #8 + int16_t weight = -1; + 5f34: f04f 34ff mov.w r4, #4294967295 ; 0xffffffff + for(ci = 0; ci < list->style_cnt; ci++) { + 5f38: 792a ldrb r2, [r5, #4] + 5f3a: fa0f f986 sxth.w r9, r6 + 5f3e: 4591 cmp r9, r2 + 5f40: db03 blt.n 5f4a <_lv_style_list_get_color+0x36> + if(weight >= 0) return LV_RES_OK; + 5f42: 43e0 mvns r0, r4 + if(list == NULL) return LV_RES_INV; + 5f44: f3c0 30c0 ubfx r0, r0, #15, #1 + 5f48: e00d b.n 5f66 <_lv_style_list_get_color+0x52> + lv_style_t * class = lv_style_list_get_style(list, ci); + 5f4a: b2f1 uxtb r1, r6 + 5f4c: 4628 mov r0, r5 + 5f4e: 4798 blx r3 + int16_t weight_act = _lv_style_get_color(class, prop, &value_act); + 5f50: aa01 add r2, sp, #4 + 5f52: 4639 mov r1, r7 + 5f54: 47d8 blx fp + if(weight_act == weight_goal) { + 5f56: 4582 cmp sl, r0 + 5f58: 4b0e ldr r3, [pc, #56] ; (5f94 <_lv_style_list_get_color+0x80>) + 5f5a: d107 bne.n 5f6c <_lv_style_list_get_color+0x58> + *res = value_act; + 5f5c: f8bd 3004 ldrh.w r3, [sp, #4] + 5f60: f8a8 3000 strh.w r3, [r8] + return LV_RES_OK; + 5f64: 2001 movs r0, #1 +} + 5f66: b003 add sp, #12 + 5f68: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + else if(list->has_trans && weight_act >= 0 && ci == 0 && !list->skip_trans) { + 5f6c: 796a ldrb r2, [r5, #5] + 5f6e: 0791 lsls r1, r2, #30 + 5f70: d506 bpl.n 5f80 <_lv_style_list_get_color+0x6c> + 5f72: 2800 cmp r0, #0 + 5f74: db04 blt.n 5f80 <_lv_style_list_get_color+0x6c> + 5f76: f1b9 0f00 cmp.w r9, #0 + 5f7a: d101 bne.n 5f80 <_lv_style_list_get_color+0x6c> + 5f7c: 0752 lsls r2, r2, #29 + 5f7e: d5ed bpl.n 5f5c <_lv_style_list_get_color+0x48> + else if(weight_act > weight) { + 5f80: 4284 cmp r4, r0 + *res = value_act; + 5f82: bfbe ittt lt + 5f84: f8bd 2004 ldrhlt.w r2, [sp, #4] + 5f88: f8a8 2000 strhlt.w r2, [r8] + 5f8c: 4604 movlt r4, r0 + for(ci = 0; ci < list->style_cnt; ci++) { + 5f8e: 3601 adds r6, #1 + 5f90: e7d2 b.n 5f38 <_lv_style_list_get_color+0x24> + 5f92: bf00 nop + 5f94: 00005495 .word 0x00005495 + 5f98: 00005bbd .word 0x00005bbd + +00005f9c <_lv_style_list_get_opa>: +{ + 5f9c: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} + 5fa0: 460f mov r7, r1 + 5fa2: 4690 mov r8, r2 + if(list == NULL) return LV_RES_INV; + 5fa4: 4605 mov r5, r0 + 5fa6: b318 cbz r0, 5ff0 <_lv_style_list_get_opa+0x54> + if(list->style_list == NULL) return LV_RES_INV; + 5fa8: 6800 ldr r0, [r0, #0] + 5faa: b308 cbz r0, 5ff0 <_lv_style_list_get_opa+0x54> + lv_opa_t value_act = LV_OPA_TRANSP; + 5fac: 2600 movs r6, #0 + lv_style_t * class = lv_style_list_get_style(list, ci); + 5fae: 4b1b ldr r3, [pc, #108] ; (601c <_lv_style_list_get_opa+0x80>) + int16_t weight_act = _lv_style_get_opa(class, prop, &value_act); + 5fb0: f8df b06c ldr.w fp, [pc, #108] ; 6020 <_lv_style_list_get_opa+0x84> + lv_opa_t value_act = LV_OPA_TRANSP; + 5fb4: f88d 6007 strb.w r6, [sp, #7] + int16_t weight_goal = attr.full; + 5fb8: ea4f 2a11 mov.w sl, r1, lsr #8 + int16_t weight = -1; + 5fbc: f04f 34ff mov.w r4, #4294967295 ; 0xffffffff + for(ci = 0; ci < list->style_cnt; ci++) { + 5fc0: 792a ldrb r2, [r5, #4] + 5fc2: fa0f f986 sxth.w r9, r6 + 5fc6: 4591 cmp r9, r2 + 5fc8: db03 blt.n 5fd2 <_lv_style_list_get_opa+0x36> + if(weight >= 0) return LV_RES_OK; + 5fca: 43e0 mvns r0, r4 + if(list == NULL) return LV_RES_INV; + 5fcc: f3c0 30c0 ubfx r0, r0, #15, #1 + 5fd0: e00e b.n 5ff0 <_lv_style_list_get_opa+0x54> + lv_style_t * class = lv_style_list_get_style(list, ci); + 5fd2: b2f1 uxtb r1, r6 + 5fd4: 4628 mov r0, r5 + 5fd6: 4798 blx r3 + int16_t weight_act = _lv_style_get_opa(class, prop, &value_act); + 5fd8: f10d 0207 add.w r2, sp, #7 + 5fdc: 4639 mov r1, r7 + 5fde: 47d8 blx fp + if(weight_act == weight_goal) { + 5fe0: 4582 cmp sl, r0 + 5fe2: 4b0e ldr r3, [pc, #56] ; (601c <_lv_style_list_get_opa+0x80>) + 5fe4: d107 bne.n 5ff6 <_lv_style_list_get_opa+0x5a> + *res = value_act; + 5fe6: f89d 3007 ldrb.w r3, [sp, #7] + 5fea: f888 3000 strb.w r3, [r8] + return LV_RES_OK; + 5fee: 2001 movs r0, #1 +} + 5ff0: b003 add sp, #12 + 5ff2: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + else if(list->has_trans && weight_act >= 0 && ci == 0 && !list->skip_trans) { + 5ff6: 796a ldrb r2, [r5, #5] + 5ff8: 0791 lsls r1, r2, #30 + 5ffa: d506 bpl.n 600a <_lv_style_list_get_opa+0x6e> + 5ffc: 2800 cmp r0, #0 + 5ffe: db04 blt.n 600a <_lv_style_list_get_opa+0x6e> + 6000: f1b9 0f00 cmp.w r9, #0 + 6004: d101 bne.n 600a <_lv_style_list_get_opa+0x6e> + 6006: 0752 lsls r2, r2, #29 + 6008: d5ed bpl.n 5fe6 <_lv_style_list_get_opa+0x4a> + else if(weight_act > weight) { + 600a: 4284 cmp r4, r0 + *res = value_act; + 600c: bfbe ittt lt + 600e: f89d 2007 ldrblt.w r2, [sp, #7] + 6012: f888 2000 strblt.w r2, [r8] + 6016: 4604 movlt r4, r0 + for(ci = 0; ci < list->style_cnt; ci++) { + 6018: 3601 adds r6, #1 + 601a: e7d1 b.n 5fc0 <_lv_style_list_get_opa+0x24> + 601c: 00005495 .word 0x00005495 + 6020: 00005c09 .word 0x00005c09 + +00006024 <_lv_style_list_get_ptr>: +{ + 6024: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} + 6028: 460f mov r7, r1 + 602a: 4690 mov r8, r2 + if(list == NULL) return LV_RES_INV; + 602c: 4605 mov r5, r0 + 602e: b1f8 cbz r0, 6070 <_lv_style_list_get_ptr+0x4c> + if(list->style_list == NULL) return LV_RES_INV; + 6030: 6800 ldr r0, [r0, #0] + 6032: b1e8 cbz r0, 6070 <_lv_style_list_get_ptr+0x4c> + lv_style_t * class = lv_style_list_get_style(list, ci); + 6034: 4b19 ldr r3, [pc, #100] ; (609c <_lv_style_list_get_ptr+0x78>) + int16_t weight_act = _lv_style_get_ptr(class, prop, &value_act); + 6036: f8df b068 ldr.w fp, [pc, #104] ; 60a0 <_lv_style_list_get_ptr+0x7c> + int16_t weight_goal = attr.full; + 603a: ea4f 2a11 mov.w sl, r1, lsr #8 + for(ci = 0; ci < list->style_cnt; ci++) { + 603e: 2600 movs r6, #0 + int16_t weight = -1; + 6040: f04f 34ff mov.w r4, #4294967295 ; 0xffffffff + for(ci = 0; ci < list->style_cnt; ci++) { + 6044: 792a ldrb r2, [r5, #4] + 6046: fa0f f986 sxth.w r9, r6 + 604a: 4591 cmp r9, r2 + 604c: db03 blt.n 6056 <_lv_style_list_get_ptr+0x32> + if(weight >= 0) return LV_RES_OK; + 604e: 43e0 mvns r0, r4 + if(list == NULL) return LV_RES_INV; + 6050: f3c0 30c0 ubfx r0, r0, #15, #1 + 6054: e00c b.n 6070 <_lv_style_list_get_ptr+0x4c> + lv_style_t * class = lv_style_list_get_style(list, ci); + 6056: b2f1 uxtb r1, r6 + 6058: 4628 mov r0, r5 + 605a: 4798 blx r3 + int16_t weight_act = _lv_style_get_ptr(class, prop, &value_act); + 605c: aa01 add r2, sp, #4 + 605e: 4639 mov r1, r7 + 6060: 47d8 blx fp + if(weight_act == weight_goal) { + 6062: 4582 cmp sl, r0 + 6064: 4b0d ldr r3, [pc, #52] ; (609c <_lv_style_list_get_ptr+0x78>) + 6066: d106 bne.n 6076 <_lv_style_list_get_ptr+0x52> + *res = value_act; + 6068: 9b01 ldr r3, [sp, #4] + 606a: f8c8 3000 str.w r3, [r8] + return LV_RES_OK; + 606e: 2001 movs r0, #1 +} + 6070: b003 add sp, #12 + 6072: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + else if(list->has_trans && weight_act >= 0 && ci == 0 && !list->skip_trans) { + 6076: 796a ldrb r2, [r5, #5] + 6078: 0791 lsls r1, r2, #30 + 607a: d506 bpl.n 608a <_lv_style_list_get_ptr+0x66> + 607c: 2800 cmp r0, #0 + 607e: db04 blt.n 608a <_lv_style_list_get_ptr+0x66> + 6080: f1b9 0f00 cmp.w r9, #0 + 6084: d101 bne.n 608a <_lv_style_list_get_ptr+0x66> + 6086: 0752 lsls r2, r2, #29 + 6088: d5ee bpl.n 6068 <_lv_style_list_get_ptr+0x44> + else if(weight_act > weight) { + 608a: 4284 cmp r4, r0 + *res = value_act; + 608c: bfbe ittt lt + 608e: 9a01 ldrlt r2, [sp, #4] + 6090: f8c8 2000 strlt.w r2, [r8] + 6094: 4604 movlt r4, r0 + for(ci = 0; ci < list->style_cnt; ci++) { + 6096: 3601 adds r6, #1 + 6098: e7d4 b.n 6044 <_lv_style_list_get_ptr+0x20> + 609a: bf00 nop + 609c: 00005495 .word 0x00005495 + 60a0: 00005c55 .word 0x00005c55 + +000060a4 : + * @param c2 the second color to mix (usually the background) + * @param mix The ratio of the colors. 0: full `c2`, 255: full `c1`, 127: half `c1` and half`c2` + * @return the mixed color + */ +LV_ATTRIBUTE_FAST_MEM static inline lv_color_t lv_color_mix(lv_color_t c1, lv_color_t c2, uint8_t mix) +{ + 60a4: b5f0 push {r4, r5, r6, r7, lr} + lv_color_t ret; +#if LV_COLOR_DEPTH != 1 + /*LV_COLOR_DEPTH == 8, 16 or 32*/ + LV_COLOR_SET_R(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_R(c1) * mix + LV_COLOR_GET_R(c2) * (255 - mix))); + LV_COLOR_SET_G(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_G(c1) * mix + LV_COLOR_GET_G(c2) * (255 - mix))); + 60a6: f3c1 1345 ubfx r3, r1, #5, #6 + LV_COLOR_SET_R(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_R(c1) * mix + LV_COLOR_GET_R(c2) * (255 - mix))); + 60aa: f1c2 06ff rsb r6, r2, #255 ; 0xff + LV_COLOR_SET_G(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_G(c1) * mix + LV_COLOR_GET_G(c2) * (255 - mix))); + 60ae: f3c0 1445 ubfx r4, r0, #5, #6 + 60b2: 4373 muls r3, r6 + 60b4: fb04 3302 mla r3, r4, r2, r3 + LV_COLOR_SET_B(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_B(c1) * mix + LV_COLOR_GET_B(c2) * (255 - mix))); + 60b8: f001 041f and.w r4, r1, #31 + 60bc: f000 071f and.w r7, r0, #31 + 60c0: 4374 muls r4, r6 + LV_COLOR_SET_G(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_G(c1) * mix + LV_COLOR_GET_G(c2) * (255 - mix))); + 60c2: f248 0581 movw r5, #32897 ; 0x8081 + LV_COLOR_SET_B(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_B(c1) * mix + LV_COLOR_GET_B(c2) * (255 - mix))); + 60c6: fb07 4402 mla r4, r7, r2, r4 + LV_COLOR_SET_G(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_G(c1) * mix + LV_COLOR_GET_G(c2) * (255 - mix))); + 60ca: 436b muls r3, r5 + LV_COLOR_SET_B(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_B(c1) * mix + LV_COLOR_GET_B(c2) * (255 - mix))); + 60cc: 436c muls r4, r5 +#else + /*LV_COLOR_DEPTH == 1*/ + ret.full = mix > LV_OPA_50 ? c1.full : c2.full; +#endif + + return ret; + 60ce: f3c3 53c5 ubfx r3, r3, #23, #6 + 60d2: f3c4 54c4 ubfx r4, r4, #23, #5 + 60d6: ea44 1443 orr.w r4, r4, r3, lsl #5 + LV_COLOR_SET_R(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_R(c1) * mix + LV_COLOR_GET_R(c2) * (255 - mix))); + 60da: f3c1 23c4 ubfx r3, r1, #11, #5 + 60de: 4373 muls r3, r6 + 60e0: f3c0 20c4 ubfx r0, r0, #11, #5 + 60e4: fb00 3202 mla r2, r0, r2, r3 + 60e8: fb05 f302 mul.w r3, r5, r2 + 60ec: 0ddb lsrs r3, r3, #23 +} + 60ee: ea44 20c3 orr.w r0, r4, r3, lsl #11 + 60f2: bdf0 pop {r4, r5, r6, r7, pc} + +000060f4 : + } + } +} + +static inline lv_color_t color_blend_true_color_additive(lv_color_t fg, lv_color_t bg, lv_opa_t opa) +{ + 60f4: 460b mov r3, r1 + + if(opa <= LV_OPA_MIN) return bg; + 60f6: 2a05 cmp r2, #5 +{ + 60f8: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 60fc: f000 0c1f and.w ip, r0, #31 + 6100: f3c0 1e45 ubfx lr, r0, #5, #6 + 6104: f3c0 28c4 ubfx r8, r0, #11, #5 + 6108: f003 061f and.w r6, r3, #31 + 610c: f3c3 1545 ubfx r5, r3, #5, #6 + 6110: f3c3 24c4 ubfx r4, r3, #11, #5 + if(opa <= LV_OPA_MIN) return bg; + 6114: d802 bhi.n 611c + 6116: 4608 mov r0, r1 +#endif + + if(opa == LV_OPA_COVER) return fg; + + return lv_color_mix(fg, bg, opa); +} + 6118: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + tmp = bg.ch.red + fg.ch.red; + 611c: eb04 0308 add.w r3, r4, r8 + fg.ch.red = LV_MATH_MIN(tmp, 31); + 6120: 2b1f cmp r3, #31 + tmp = bg.ch.green + fg.ch.green; + 6122: eb05 040e add.w r4, r5, lr + fg.ch.red = LV_MATH_MIN(tmp, 31); + 6126: bf28 it cs + 6128: 231f movcs r3, #31 + tmp = bg.ch.blue + fg.ch.blue; + 612a: eb06 050c add.w r5, r6, ip + fg.ch.green = LV_MATH_MIN(tmp, 63); + 612e: 2c3f cmp r4, #63 ; 0x3f + 6130: bf28 it cs + 6132: 243f movcs r4, #63 ; 0x3f + fg.ch.blue = LV_MATH_MIN(tmp, 31); + 6134: 2d1f cmp r5, #31 + 6136: bf28 it cs + 6138: 251f movcs r5, #31 + if(opa == LV_OPA_COVER) return fg; + 613a: 2aff cmp r2, #255 ; 0xff + fg.ch.red = LV_MATH_MIN(tmp, 31); + 613c: f003 031f and.w r3, r3, #31 + fg.ch.green = LV_MATH_MIN(tmp, 63); + 6140: f004 043f and.w r4, r4, #63 ; 0x3f + fg.ch.blue = LV_MATH_MIN(tmp, 31); + 6144: f005 051f and.w r5, r5, #31 + if(opa == LV_OPA_COVER) return fg; + 6148: d108 bne.n 615c + 614a: f04f 0000 mov.w r0, #0 + 614e: f365 0004 bfi r0, r5, #0, #5 + 6152: f364 104a bfi r0, r4, #5, #6 + 6156: f363 20cf bfi r0, r3, #11, #5 + 615a: e7dd b.n 6118 + return lv_color_mix(fg, bg, opa); + 615c: f365 0004 bfi r0, r5, #0, #5 + 6160: f364 104a bfi r0, r4, #5, #6 + 6164: f363 20cf bfi r0, r3, #11, #5 +} + 6168: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} + return lv_color_mix(fg, bg, opa); + 616c: 4b00 ldr r3, [pc, #0] ; (6170 ) + 616e: 4718 bx r3 + 6170: 000060a5 .word 0x000060a5 + +00006174 : + +static inline lv_color_t color_blend_true_color_subtractive(lv_color_t fg, lv_color_t bg, lv_opa_t opa) +{ + 6174: 460b mov r3, r1 + + if(opa <= LV_OPA_MIN) return bg; + 6176: 2a05 cmp r2, #5 +{ + 6178: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 617c: f000 0c1f and.w ip, r0, #31 + 6180: f3c0 1e45 ubfx lr, r0, #5, #6 + 6184: f3c0 28c4 ubfx r8, r0, #11, #5 + 6188: f003 061f and.w r6, r3, #31 + 618c: f3c3 1545 ubfx r5, r3, #5, #6 + 6190: f3c3 24c4 ubfx r4, r3, #11, #5 + if(opa <= LV_OPA_MIN) return bg; + 6194: d802 bhi.n 619c + 6196: 4608 mov r0, r1 + fg.ch.blue = LV_MATH_MAX(tmp, 0); + + if(opa == LV_OPA_COVER) return fg; + + return lv_color_mix(fg, bg, opa); +} + 6198: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + tmp = bg.ch.red - fg.ch.red; + 619c: eba4 0308 sub.w r3, r4, r8 + tmp = bg.ch.green - fg.ch.green; + 61a0: eba5 040e sub.w r4, r5, lr + tmp = bg.ch.blue - fg.ch.blue; + 61a4: eba6 050c sub.w r5, r6, ip + fg.ch.red = LV_MATH_MAX(tmp, 0); + 61a8: ea23 73e3 bic.w r3, r3, r3, asr #31 + fg.ch.green = LV_MATH_MAX(tmp, 0); + 61ac: ea24 74e4 bic.w r4, r4, r4, asr #31 + fg.ch.blue = LV_MATH_MAX(tmp, 0); + 61b0: ea25 75e5 bic.w r5, r5, r5, asr #31 + if(opa == LV_OPA_COVER) return fg; + 61b4: 2aff cmp r2, #255 ; 0xff + fg.ch.red = LV_MATH_MAX(tmp, 0); + 61b6: f003 031f and.w r3, r3, #31 + fg.ch.green = LV_MATH_MAX(tmp, 0); + 61ba: f004 043f and.w r4, r4, #63 ; 0x3f + fg.ch.blue = LV_MATH_MAX(tmp, 0); + 61be: f005 051f and.w r5, r5, #31 + if(opa == LV_OPA_COVER) return fg; + 61c2: d108 bne.n 61d6 + 61c4: f04f 0000 mov.w r0, #0 + 61c8: f365 0004 bfi r0, r5, #0, #5 + 61cc: f364 104a bfi r0, r4, #5, #6 + 61d0: f363 20cf bfi r0, r3, #11, #5 + 61d4: e7e0 b.n 6198 + return lv_color_mix(fg, bg, opa); + 61d6: f365 0004 bfi r0, r5, #0, #5 + 61da: f364 104a bfi r0, r4, #5, #6 + 61de: f363 20cf bfi r0, r3, #11, #5 +} + 61e2: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} + return lv_color_mix(fg, bg, opa); + 61e6: 4b01 ldr r3, [pc, #4] ; (61ec ) + 61e8: 4718 bx r3 + 61ea: bf00 nop + 61ec: 000060a5 .word 0x000060a5 + +000061f0 <_lv_blend_fill>: +{ + 61f0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 61f4: b08d sub sp, #52 ; 0x34 + 61f6: 4605 mov r5, r0 + 61f8: 9305 str r3, [sp, #20] + 61fa: f89d 305c ldrb.w r3, [sp, #92] ; 0x5c + 61fe: f89d 7058 ldrb.w r7, [sp, #88] ; 0x58 + 6202: f89d b060 ldrb.w fp, [sp, #96] ; 0x60 + 6206: 9304 str r3, [sp, #16] + if(opa < LV_OPA_MIN) return; + 6208: 2b04 cmp r3, #4 +{ + 620a: 460e mov r6, r1 + 620c: 4614 mov r4, r2 + if(opa < LV_OPA_MIN) return; + 620e: f240 80a3 bls.w 6358 <_lv_blend_fill+0x168> + if(mask_res == LV_DRAW_MASK_RES_TRANSP) return; + 6212: 2f00 cmp r7, #0 + 6214: f000 80a0 beq.w 6358 <_lv_blend_fill+0x168> + lv_disp_t * disp = _lv_refr_get_disp_refreshing(); + 6218: 4ba4 ldr r3, [pc, #656] ; (64ac <_lv_blend_fill+0x2bc>) + 621a: 4798 blx r3 + lv_disp_buf_t * vdb = lv_disp_get_buf(disp); + 621c: 4ba4 ldr r3, [pc, #656] ; (64b0 <_lv_blend_fill+0x2c0>) + lv_disp_t * disp = _lv_refr_get_disp_refreshing(); + 621e: 4682 mov sl, r0 + lv_disp_buf_t * vdb = lv_disp_get_buf(disp); + 6220: 4798 blx r3 + is_common = _lv_area_intersect(&draw_area, clip_area, fill_area); + 6222: 4ba4 ldr r3, [pc, #656] ; (64b4 <_lv_blend_fill+0x2c4>) + lv_color_t * disp_buf = vdb->buf_act; + 6224: f8d0 9008 ldr.w r9, [r0, #8] + lv_disp_buf_t * vdb = lv_disp_get_buf(disp); + 6228: 4680 mov r8, r0 + is_common = _lv_area_intersect(&draw_area, clip_area, fill_area); + 622a: 4632 mov r2, r6 + 622c: 4629 mov r1, r5 + 622e: a80a add r0, sp, #40 ; 0x28 + 6230: 4798 blx r3 + if(!is_common) return; + 6232: 2800 cmp r0, #0 + 6234: f000 8090 beq.w 6358 <_lv_blend_fill+0x168> + draw_area.x1 -= disp_area->x1; + 6238: f8bd 2028 ldrh.w r2, [sp, #40] ; 0x28 + 623c: f8b8 0010 ldrh.w r0, [r8, #16] + draw_area.x2 -= disp_area->x1; + 6240: f8bd 302c ldrh.w r3, [sp, #44] ; 0x2c + draw_area.y1 -= disp_area->y1; + 6244: f8b8 6012 ldrh.w r6, [r8, #18] + 6248: f8bd 502a ldrh.w r5, [sp, #42] ; 0x2a + draw_area.x1 -= disp_area->x1; + 624c: 1a11 subs r1, r2, r0 + draw_area.x2 -= disp_area->x1; + 624e: 1a18 subs r0, r3, r0 + 6250: f8ad 002c strh.w r0, [sp, #44] ; 0x2c + draw_area.y2 -= disp_area->y1; + 6254: f8bd 002e ldrh.w r0, [sp, #46] ; 0x2e + 6258: 1b80 subs r0, r0, r6 + draw_area.y1 -= disp_area->y1; + 625a: 1bad subs r5, r5, r6 + draw_area.y2 -= disp_area->y1; + 625c: f8ad 002e strh.w r0, [sp, #46] ; 0x2e + if(mask && disp->driver.antialiasing == 0) + 6260: 9805 ldr r0, [sp, #20] + draw_area.x1 -= disp_area->x1; + 6262: b209 sxth r1, r1 + draw_area.y1 -= disp_area->y1; + 6264: b22d sxth r5, r5 + draw_area.x1 -= disp_area->x1; + 6266: f8ad 1028 strh.w r1, [sp, #40] ; 0x28 + draw_area.y1 -= disp_area->y1; + 626a: f8ad 502a strh.w r5, [sp, #42] ; 0x2a + if(mask && disp->driver.antialiasing == 0) + 626e: 2800 cmp r0, #0 + 6270: d145 bne.n 62fe <_lv_blend_fill+0x10e> + if(disp->driver.set_px_cb) { + 6272: f8da 0014 ldr.w r0, [sl, #20] + 6276: b2a6 uxth r6, r4 + 6278: 2800 cmp r0, #0 + 627a: d15a bne.n 6332 <_lv_blend_fill+0x142> + else if(mode == LV_BLEND_MODE_NORMAL) { + 627c: f1bb 0f00 cmp.w fp, #0 + 6280: f040 8227 bne.w 66d2 <_lv_blend_fill+0x4e2> + lv_disp_t * disp = _lv_refr_get_disp_refreshing(); + 6284: 4b89 ldr r3, [pc, #548] ; (64ac <_lv_blend_fill+0x2bc>) + 6286: 4798 blx r3 + * @param area_p pointer to an area + * @return the width of the area (if x1 == x2 -> width = 1) + */ +static inline lv_coord_t lv_area_get_width(const lv_area_t * area_p) +{ + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + 6288: f8b8 3014 ldrh.w r3, [r8, #20] + 628c: f8b8 2010 ldrh.w r2, [r8, #16] + * @param area_p pointer to an area + * @return the height of the area (if y1 == y2 -> height = 1) + */ +static inline lv_coord_t lv_area_get_height(const lv_area_t * area_p) +{ + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + 6290: f9bd 102a ldrsh.w r1, [sp, #42] ; 0x2a + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + 6294: 3301 adds r3, #1 + 6296: eba3 0802 sub.w r8, r3, r2 + 629a: f8bd 302c ldrh.w r3, [sp, #44] ; 0x2c + 629e: f9bd 2028 ldrsh.w r2, [sp, #40] ; 0x28 + 62a2: 3301 adds r3, #1 + 62a4: 1a9b subs r3, r3, r2 + 62a6: b21b sxth r3, r3 + 62a8: 9306 str r3, [sp, #24] + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + 62aa: f9bd 302e ldrsh.w r3, [sp, #46] ; 0x2e + 62ae: 9308 str r3, [sp, #32] + 62b0: 3301 adds r3, #1 + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + 62b2: fa0f f888 sxth.w r8, r8 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + 62b6: 1a5b subs r3, r3, r1 + int32_t draw_area_h = lv_area_get_height(draw_area); + 62b8: b21b sxth r3, r3 + lv_color_t * disp_buf_first = disp_buf + disp_w * draw_area->y1 + draw_area->x1; + 62ba: fb08 2201 mla r2, r8, r1, r2 + if(mask_res == LV_DRAW_MASK_RES_FULL_COVER) { + 62be: 2f01 cmp r7, #1 + int32_t draw_area_h = lv_area_get_height(draw_area); + 62c0: 9307 str r3, [sp, #28] + lv_disp_t * disp = _lv_refr_get_disp_refreshing(); + 62c2: 4682 mov sl, r0 + lv_color_t * disp_buf_first = disp_buf + disp_w * draw_area->y1 + draw_area->x1; + 62c4: 460b mov r3, r1 + 62c6: eb09 0542 add.w r5, r9, r2, lsl #1 + if(mask_res == LV_DRAW_MASK_RES_FULL_COVER) { + 62ca: f040 8132 bne.w 6532 <_lv_blend_fill+0x342> + if(opa > LV_OPA_MAX) { + 62ce: 9b04 ldr r3, [sp, #16] + 62d0: 2bfa cmp r3, #250 ; 0xfa + 62d2: f240 809e bls.w 6412 <_lv_blend_fill+0x222> + if(disp->driver.gpu_fill_cb && lv_area_get_size(draw_area) > GPU_SIZE_LIMIT) { + 62d6: 6a43 ldr r3, [r0, #36] ; 0x24 + 62d8: 2b00 cmp r3, #0 + 62da: f000 8095 beq.w 6408 <_lv_blend_fill+0x218> + 62de: 4b76 ldr r3, [pc, #472] ; (64b8 <_lv_blend_fill+0x2c8>) + 62e0: a80a add r0, sp, #40 ; 0x28 + 62e2: 4798 blx r3 + 62e4: 28f0 cmp r0, #240 ; 0xf0 + 62e6: f240 808f bls.w 6408 <_lv_blend_fill+0x218> + disp->driver.gpu_fill_cb(&disp->driver, disp_buf, disp_w, draw_area, color); + 62ea: f8da 5024 ldr.w r5, [sl, #36] ; 0x24 + 62ee: f8ad 4000 strh.w r4, [sp] + 62f2: ab0a add r3, sp, #40 ; 0x28 + 62f4: 4642 mov r2, r8 + 62f6: 4649 mov r1, r9 + 62f8: 4650 mov r0, sl + 62fa: 47a8 blx r5 + return; + 62fc: e02c b.n 6358 <_lv_blend_fill+0x168> + if(mask && disp->driver.antialiasing == 0) + 62fe: f89a 0008 ldrb.w r0, [sl, #8] + 6302: 07c0 lsls r0, r0, #31 + 6304: d4b5 bmi.n 6272 <_lv_blend_fill+0x82> + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + 6306: 1c58 adds r0, r3, #1 + 6308: 1a80 subs r0, r0, r2 + for(i = 0; i < mask_w; i++) mask[i] = mask[i] > 128 ? LV_OPA_COVER : LV_OPA_TRANSP; + 630a: 9e05 ldr r6, [sp, #20] + int32_t mask_w = lv_area_get_width(&draw_area); + 630c: fa0f fe80 sxth.w lr, r0 + for(i = 0; i < mask_w; i++) mask[i] = mask[i] > 128 ? LV_OPA_COVER : LV_OPA_TRANSP; + 6310: 9805 ldr r0, [sp, #20] + 6312: f1c6 0c01 rsb ip, r6, #1 + 6316: 3801 subs r0, #1 + 6318: eb0c 0600 add.w r6, ip, r0 + 631c: 45b6 cmp lr, r6 + 631e: dda8 ble.n 6272 <_lv_blend_fill+0x82> + 6320: f810 6f01 ldrb.w r6, [r0, #1]! + 6324: 2e80 cmp r6, #128 ; 0x80 + 6326: f04f 36ff mov.w r6, #4294967295 ; 0xffffffff + 632a: bf98 it ls + 632c: 2600 movls r6, #0 + 632e: 7006 strb r6, [r0, #0] + 6330: e7f2 b.n 6318 <_lv_blend_fill+0x128> + lv_disp_t * disp = _lv_refr_get_disp_refreshing(); + 6332: 4b5e ldr r3, [pc, #376] ; (64ac <_lv_blend_fill+0x2bc>) + 6334: 4798 blx r3 + 6336: f8b8 2014 ldrh.w r2, [r8, #20] + 633a: f8b8 3010 ldrh.w r3, [r8, #16] + 633e: f9bd 502a ldrsh.w r5, [sp, #42] ; 0x2a + 6342: 3201 adds r2, #1 + 6344: 1ad2 subs r2, r2, r3 + if(mask_res == LV_DRAW_MASK_RES_FULL_COVER) { + 6346: 2f01 cmp r7, #1 + lv_disp_t * disp = _lv_refr_get_disp_refreshing(); + 6348: 4606 mov r6, r0 + 634a: b212 sxth r2, r2 + if(mask_res == LV_DRAW_MASK_RES_FULL_COVER) { + 634c: d121 bne.n 6392 <_lv_blend_fill+0x1a2> + for(y = draw_area->y1; y <= draw_area->y2; y++) { + 634e: 46aa mov sl, r5 + 6350: f9bd 302e ldrsh.w r3, [sp, #46] ; 0x2e + 6354: 459a cmp sl, r3 + 6356: dd02 ble.n 635e <_lv_blend_fill+0x16e> +} + 6358: b00d add sp, #52 ; 0x34 + 635a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + for(x = draw_area->x1; x <= draw_area->x2; x++) { + 635e: f9bd 7028 ldrsh.w r7, [sp, #40] ; 0x28 + disp->driver.set_px_cb(&disp->driver, (void *)disp_buf, disp_w, x, y, color, opa); + 6362: fa0f f88a sxth.w r8, sl + for(x = draw_area->x1; x <= draw_area->x2; x++) { + 6366: f9bd 302c ldrsh.w r3, [sp, #44] ; 0x2c + 636a: 429f cmp r7, r3 + 636c: dd02 ble.n 6374 <_lv_blend_fill+0x184> + for(y = draw_area->y1; y <= draw_area->y2; y++) { + 636e: f10a 0a01 add.w sl, sl, #1 + 6372: e7ed b.n 6350 <_lv_blend_fill+0x160> + disp->driver.set_px_cb(&disp->driver, (void *)disp_buf, disp_w, x, y, color, opa); + 6374: 9b04 ldr r3, [sp, #16] + 6376: 9302 str r3, [sp, #8] + 6378: f8ad 4004 strh.w r4, [sp, #4] + 637c: f8cd 8000 str.w r8, [sp] + 6380: b23b sxth r3, r7 + 6382: 6975 ldr r5, [r6, #20] + 6384: 9205 str r2, [sp, #20] + 6386: 4649 mov r1, r9 + 6388: 4630 mov r0, r6 + 638a: 47a8 blx r5 + for(x = draw_area->x1; x <= draw_area->x2; x++) { + 638c: 3701 adds r7, #1 + 638e: 9a05 ldr r2, [sp, #20] + 6390: e7e9 b.n 6366 <_lv_blend_fill+0x176> + 6392: f8bd 702c ldrh.w r7, [sp, #44] ; 0x2c + const lv_opa_t * mask_tmp = mask - draw_area->x1; + 6396: f9bd 3028 ldrsh.w r3, [sp, #40] ; 0x28 + 639a: 9905 ldr r1, [sp, #20] + 639c: 3701 adds r7, #1 + 639e: 1aff subs r7, r7, r3 + 63a0: eba1 0a03 sub.w sl, r1, r3 + 63a4: b23b sxth r3, r7 + 63a6: 9305 str r3, [sp, #20] + for(y = draw_area->y1; y <= draw_area->y2; y++) { + 63a8: f9bd 302e ldrsh.w r3, [sp, #46] ; 0x2e + 63ac: 429d cmp r5, r3 + 63ae: dcd3 bgt.n 6358 <_lv_blend_fill+0x168> + for(x = draw_area->x1; x <= draw_area->x2; x++) { + 63b0: f9bd 8028 ldrsh.w r8, [sp, #40] ; 0x28 + disp->driver.set_px_cb(&disp->driver, (void *)disp_buf, disp_w, x, y, color, + 63b4: fa0f fb85 sxth.w fp, r5 + for(x = draw_area->x1; x <= draw_area->x2; x++) { + 63b8: f9bd 302c ldrsh.w r3, [sp, #44] ; 0x2c + 63bc: 4598 cmp r8, r3 + 63be: dd03 ble.n 63c8 <_lv_blend_fill+0x1d8> + mask_tmp += draw_area_w; + 63c0: 9b05 ldr r3, [sp, #20] + for(y = draw_area->y1; y <= draw_area->y2; y++) { + 63c2: 3501 adds r5, #1 + mask_tmp += draw_area_w; + 63c4: 449a add sl, r3 + for(y = draw_area->y1; y <= draw_area->y2; y++) { + 63c6: e7ef b.n 63a8 <_lv_blend_fill+0x1b8> + (uint32_t)((uint32_t)opa * mask_tmp[x]) >> 8); + 63c8: f81a 3008 ldrb.w r3, [sl, r8] + 63cc: 9904 ldr r1, [sp, #16] + disp->driver.set_px_cb(&disp->driver, (void *)disp_buf, disp_w, x, y, color, + 63ce: f8ad 4004 strh.w r4, [sp, #4] + (uint32_t)((uint32_t)opa * mask_tmp[x]) >> 8); + 63d2: fb13 f301 smulbb r3, r3, r1 + disp->driver.set_px_cb(&disp->driver, (void *)disp_buf, disp_w, x, y, color, + 63d6: 0a1b lsrs r3, r3, #8 + 63d8: 9302 str r3, [sp, #8] + 63da: f8cd b000 str.w fp, [sp] + 63de: fa0f f388 sxth.w r3, r8 + 63e2: 6977 ldr r7, [r6, #20] + 63e4: 9206 str r2, [sp, #24] + 63e6: 4649 mov r1, r9 + 63e8: 4630 mov r0, r6 + 63ea: 47b8 blx r7 + for(x = draw_area->x1; x <= draw_area->x2; x++) { + 63ec: f108 0801 add.w r8, r8, #1 + 63f0: 9a06 ldr r2, [sp, #24] + 63f2: e7e1 b.n 63b8 <_lv_blend_fill+0x1c8> + lv_color_fill(disp_buf_first, color, draw_area_w); + 63f4: 4628 mov r0, r5 + 63f6: 9a06 ldr r2, [sp, #24] + 63f8: 4631 mov r1, r6 + 63fa: 47b8 blx r7 + disp_buf_first += disp_w; + 63fc: 4445 add r5, r8 + for(y = 0; y < draw_area_h; y++) { + 63fe: 3401 adds r4, #1 + 6400: 9b07 ldr r3, [sp, #28] + 6402: 42a3 cmp r3, r4 + 6404: dcf6 bgt.n 63f4 <_lv_blend_fill+0x204> + 6406: e7a7 b.n 6358 <_lv_blend_fill+0x168> + lv_color_fill(disp_buf_first, color, draw_area_w); + 6408: 4f2c ldr r7, [pc, #176] ; (64bc <_lv_blend_fill+0x2cc>) + disp_buf_first += disp_w; + 640a: ea4f 0848 mov.w r8, r8, lsl #1 + 640e: 2400 movs r4, #0 + 6410: e7f6 b.n 6400 <_lv_blend_fill+0x210> + if(disp->driver.gpu_blend_cb && lv_area_get_size(draw_area) > GPU_SIZE_LIMIT) { + 6412: 6a03 ldr r3, [r0, #32] + 6414: b313 cbz r3, 645c <_lv_blend_fill+0x26c> + 6416: 4b28 ldr r3, [pc, #160] ; (64b8 <_lv_blend_fill+0x2c8>) + 6418: a80a add r0, sp, #40 ; 0x28 + 641a: 4798 blx r3 + 641c: 28f0 cmp r0, #240 ; 0xf0 + 641e: d91d bls.n 645c <_lv_blend_fill+0x26c> + 6420: 4b27 ldr r3, [pc, #156] ; (64c0 <_lv_blend_fill+0x2d0>) + for(x = 0; x < draw_area_w ; x++) blend_buf[x].full = color.full; + 6422: 9a06 ldr r2, [sp, #24] + 6424: 455a cmp r2, fp + 6426: dc14 bgt.n 6452 <_lv_blend_fill+0x262> + for(y = draw_area->y1; y <= draw_area->y2; y++) { + 6428: f9bd 602a ldrsh.w r6, [sp, #42] ; 0x2a + disp->driver.gpu_blend_cb(&disp->driver, disp_buf_first, blend_buf, draw_area_w, opa); + 642c: 4f24 ldr r7, [pc, #144] ; (64c0 <_lv_blend_fill+0x2d0>) + disp_buf_first += disp_w; + 642e: ea4f 0848 mov.w r8, r8, lsl #1 + for(y = draw_area->y1; y <= draw_area->y2; y++) { + 6432: f9bd 302e ldrsh.w r3, [sp, #46] ; 0x2e + 6436: 429e cmp r6, r3 + 6438: dc8e bgt.n 6358 <_lv_blend_fill+0x168> + disp->driver.gpu_blend_cb(&disp->driver, disp_buf_first, blend_buf, draw_area_w, opa); + 643a: 9b04 ldr r3, [sp, #16] + 643c: 9300 str r3, [sp, #0] + 643e: 4629 mov r1, r5 + 6440: f8da 4020 ldr.w r4, [sl, #32] + 6444: 9b06 ldr r3, [sp, #24] + 6446: 463a mov r2, r7 + 6448: 4650 mov r0, sl + 644a: 47a0 blx r4 + disp_buf_first += disp_w; + 644c: 4445 add r5, r8 + for(y = draw_area->y1; y <= draw_area->y2; y++) { + 644e: 3601 adds r6, #1 + 6450: e7ef b.n 6432 <_lv_blend_fill+0x242> + for(x = 0; x < draw_area_w ; x++) blend_buf[x].full = color.full; + 6452: f823 6b02 strh.w r6, [r3], #2 + 6456: f10b 0b01 add.w fp, fp, #1 + 645a: e7e2 b.n 6422 <_lv_blend_fill+0x232> + lv_color_t last_res_color = lv_color_mix(color, last_dest_color, opa); + 645c: 9a04 ldr r2, [sp, #16] + 645e: 4b19 ldr r3, [pc, #100] ; (64c4 <_lv_blend_fill+0x2d4>) + 6460: 4620 mov r0, r4 + lv_color_t last_dest_color = LV_COLOR_BLACK; + 6462: f04f 0100 mov.w r1, #0 + lv_color_t last_res_color = lv_color_mix(color, last_dest_color, opa); + 6466: 4798 blx r3 + +LV_ATTRIBUTE_FAST_MEM static inline void lv_color_premult(lv_color_t c, uint8_t mix, uint16_t * out) +{ +#if LV_COLOR_DEPTH != 1 + out[0] = (uint16_t) LV_COLOR_GET_R(c) * mix; + 6468: 9e04 ldr r6, [sp, #16] + 646a: f3c4 22c4 ubfx r2, r4, #11, #5 + 646e: 4372 muls r2, r6 + 6470: 9205 str r2, [sp, #20] + out[1] = (uint16_t) LV_COLOR_GET_G(c) * mix; + 6472: f3c4 1245 ubfx r2, r4, #5, #6 + out[2] = (uint16_t) LV_COLOR_GET_B(c) * mix; + 6476: f004 041f and.w r4, r4, #31 + out[1] = (uint16_t) LV_COLOR_GET_G(c) * mix; + 647a: fb02 fb06 mul.w fp, r2, r6 + out[2] = (uint16_t) LV_COLOR_GET_B(c) * mix; + 647e: fb04 fa06 mul.w sl, r4, r6 + disp_buf_first += disp_w; + 6482: ea4f 0248 mov.w r2, r8, lsl #1 + lv_opa_t opa_inv = 255 - opa; + 6486: 43f6 mvns r6, r6 + lv_color_t last_res_color = lv_color_mix(color, last_dest_color, opa); + 6488: f000 031f and.w r3, r0, #31 + 648c: f3c0 1c45 ubfx ip, r0, #5, #6 + disp_buf_first += disp_w; + 6490: 9204 str r2, [sp, #16] + lv_color_t last_res_color = lv_color_mix(color, last_dest_color, opa); + 6492: f3c0 20c4 ubfx r0, r0, #11, #5 + for(y = 0; y < draw_area_h; y++) { + 6496: f04f 0800 mov.w r8, #0 +LV_ATTRIBUTE_FAST_MEM static inline lv_color_t lv_color_mix_premult(uint16_t * premult_c1, lv_color_t c2, uint8_t mix) +{ + lv_color_t ret; +#if LV_COLOR_DEPTH != 1 + /*LV_COLOR_DEPTH == 8, 16 or 32*/ + LV_COLOR_SET_R(ret, (uint16_t)((uint16_t) premult_c1[0] + LV_COLOR_GET_R(c2) * mix) >> 8); + 649a: b2f6 uxtb r6, r6 + 649c: 9a07 ldr r2, [sp, #28] + 649e: 4542 cmp r2, r8 + 64a0: f77f af5a ble.w 6358 <_lv_blend_fill+0x168> + 64a4: 462f mov r7, r5 + for(x = 0; x < draw_area_w; x++) { + 64a6: f04f 0e00 mov.w lr, #0 + 64aa: e03a b.n 6522 <_lv_blend_fill+0x332> + 64ac: 00004fe9 .word 0x00004fe9 + 64b0: 0000d9e1 .word 0x0000d9e1 + 64b4: 0000de8d .word 0x0000de8d + 64b8: 0000de71 .word 0x0000de71 + 64bc: 0000e309 .word 0x0000e309 + 64c0: 20008108 .word 0x20008108 + 64c4: 000060a5 .word 0x000060a5 + if(last_dest_color.full != disp_buf_first[x].full) { + 64c8: 463a mov r2, r7 + 64ca: fa1f f981 uxth.w r9, r1 + 64ce: 8814 ldrh r4, [r2, #0] + 64d0: 45a1 cmp r9, r4 + 64d2: f107 0702 add.w r7, r7, #2 + 64d6: d015 beq.n 6504 <_lv_blend_fill+0x314> + 64d8: 7850 ldrb r0, [r2, #1] + 64da: 9b05 ldr r3, [sp, #20] + last_dest_color = disp_buf_first[x]; + 64dc: f837 1c02 ldrh.w r1, [r7, #-2] + 64e0: 08c0 lsrs r0, r0, #3 + 64e2: fb00 3006 mla r0, r0, r6, r3 + LV_COLOR_SET_G(ret, (uint16_t)((uint16_t) premult_c1[1] + LV_COLOR_GET_G(c2) * mix) >> 8); + LV_COLOR_SET_B(ret, (uint16_t)((uint16_t) premult_c1[2] + LV_COLOR_GET_B(c2) * mix) >> 8); + 64e6: 7813 ldrb r3, [r2, #0] + LV_COLOR_SET_G(ret, (uint16_t)((uint16_t) premult_c1[1] + LV_COLOR_GET_G(c2) * mix) >> 8); + 64e8: f3c4 1445 ubfx r4, r4, #5, #6 + LV_COLOR_SET_B(ret, (uint16_t)((uint16_t) premult_c1[2] + LV_COLOR_GET_B(c2) * mix) >> 8); + 64ec: f003 031f and.w r3, r3, #31 + LV_COLOR_SET_G(ret, (uint16_t)((uint16_t) premult_c1[1] + LV_COLOR_GET_G(c2) * mix) >> 8); + 64f0: fb04 b406 mla r4, r4, r6, fp + LV_COLOR_SET_B(ret, (uint16_t)((uint16_t) premult_c1[2] + LV_COLOR_GET_B(c2) * mix) >> 8); + 64f4: fb03 a306 mla r3, r3, r6, sl + LV_COLOR_SET_R(ret, (uint16_t)((uint16_t) premult_c1[0] + LV_COLOR_GET_R(c2) * mix) >> 8); + 64f8: f3c0 2004 ubfx r0, r0, #8, #5 + LV_COLOR_SET_G(ret, (uint16_t)((uint16_t) premult_c1[1] + LV_COLOR_GET_G(c2) * mix) >> 8); + 64fc: f3c4 2c05 ubfx ip, r4, #8, #6 + LV_COLOR_SET_B(ret, (uint16_t)((uint16_t) premult_c1[2] + LV_COLOR_GET_B(c2) * mix) >> 8); + 6500: f3c3 2304 ubfx r3, r3, #8, #5 + disp_buf_first[x] = last_res_color; + 6504: 7814 ldrb r4, [r2, #0] + 6506: f363 0404 bfi r4, r3, #0, #5 + 650a: 7014 strb r4, [r2, #0] + 650c: 8814 ldrh r4, [r2, #0] + 650e: f36c 144a bfi r4, ip, #5, #6 + 6512: 8014 strh r4, [r2, #0] + 6514: f3c4 2407 ubfx r4, r4, #8, #8 + 6518: f360 04c7 bfi r4, r0, #3, #5 + 651c: 7054 strb r4, [r2, #1] + for(x = 0; x < draw_area_w; x++) { + 651e: f10e 0e01 add.w lr, lr, #1 + 6522: 9a06 ldr r2, [sp, #24] + 6524: 4572 cmp r2, lr + 6526: dccf bgt.n 64c8 <_lv_blend_fill+0x2d8> + disp_buf_first += disp_w; + 6528: 9a04 ldr r2, [sp, #16] + for(y = 0; y < draw_area_h; y++) { + 652a: f108 0801 add.w r8, r8, #1 + disp_buf_first += disp_w; + 652e: 4415 add r5, r2 + for(y = 0; y < draw_area_h; y++) { + 6530: e7b4 b.n 649c <_lv_blend_fill+0x2ac> + last_dest_color.full = disp_buf_first[0].full; + 6532: f839 1012 ldrh.w r1, [r9, r2, lsl #1] + disp_buf_first += disp_w; + 6536: ea4f 0248 mov.w r2, r8, lsl #1 + 653a: 9209 str r2, [sp, #36] ; 0x24 + if(opa > LV_OPA_MAX) { + 653c: 9a04 ldr r2, [sp, #16] + 653e: 2afa cmp r2, #250 ; 0xfa + 6540: f240 80c4 bls.w 66cc <_lv_blend_fill+0x4dc> + int32_t x_end4 = draw_area_w - 4; + 6544: 9b06 ldr r3, [sp, #24] + FILL_NORMAL_MASK_PX(x, color) + 6546: f8df 8298 ldr.w r8, [pc, #664] ; 67e0 <_lv_blend_fill+0x5f0> + int32_t x_end4 = draw_area_w - 4; + 654a: 3b04 subs r3, #4 + 654c: 9304 str r3, [sp, #16] + for(y = 0; y < draw_area_h; y++) { + 654e: 9b07 ldr r3, [sp, #28] + 6550: 455b cmp r3, fp + 6552: f77f af01 ble.w 6358 <_lv_blend_fill+0x168> + 6556: f8dd a014 ldr.w sl, [sp, #20] + 655a: 46a9 mov r9, r5 + for(x = 0; x < draw_area_w && ((lv_uintptr_t)mask_tmp_x & 0x3); x++) { + 655c: 2400 movs r4, #0 + 655e: e013 b.n 6588 <_lv_blend_fill+0x398> + FILL_NORMAL_MASK_PX(x, color) + 6560: f8b9 1000 ldrh.w r1, [r9] + 6564: 4630 mov r0, r6 + 6566: 47c0 blx r8 + 6568: f8a9 0000 strh.w r0, [r9] + 656c: e009 b.n 6582 <_lv_blend_fill+0x392> + for(x = 0; x < draw_area_w && ((lv_uintptr_t)mask_tmp_x & 0x3); x++) { + 656e: f01a 0f03 tst.w sl, #3 + 6572: d00d beq.n 6590 <_lv_blend_fill+0x3a0> + FILL_NORMAL_MASK_PX(x, color) + 6574: f81a 2b01 ldrb.w r2, [sl], #1 + 6578: b11a cbz r2, 6582 <_lv_blend_fill+0x392> + 657a: 2aff cmp r2, #255 ; 0xff + 657c: d1f0 bne.n 6560 <_lv_blend_fill+0x370> + 657e: f8a9 6000 strh.w r6, [r9] + for(x = 0; x < draw_area_w && ((lv_uintptr_t)mask_tmp_x & 0x3); x++) { + 6582: 3401 adds r4, #1 + 6584: f109 0902 add.w r9, r9, #2 + 6588: 9b06 ldr r3, [sp, #24] + 658a: 42a3 cmp r3, r4 + 658c: 4657 mov r7, sl + 658e: dcee bgt.n 656e <_lv_blend_fill+0x37e> + 6590: eb05 0944 add.w r9, r5, r4, lsl #1 + for(; x <= x_end4; x += 4) { + 6594: 9b04 ldr r3, [sp, #16] + 6596: 42a3 cmp r3, r4 + 6598: da0e bge.n 65b8 <_lv_blend_fill+0x3c8> + 659a: 3f01 subs r7, #1 + 659c: eb05 0944 add.w r9, r5, r4, lsl #1 + for(; x < draw_area_w ; x++) { + 65a0: 9b06 ldr r3, [sp, #24] + 65a2: 42a3 cmp r3, r4 + 65a4: dc4c bgt.n 6640 <_lv_blend_fill+0x450> + disp_buf_first += disp_w; + 65a6: 9b09 ldr r3, [sp, #36] ; 0x24 + 65a8: 441d add r5, r3 + mask += draw_area_w; + 65aa: e9dd 3205 ldrd r3, r2, [sp, #20] + 65ae: 4413 add r3, r2 + 65b0: 9305 str r3, [sp, #20] + for(y = 0; y < draw_area_h; y++) { + 65b2: f10b 0b01 add.w fp, fp, #1 + 65b6: e7ca b.n 654e <_lv_blend_fill+0x35e> + if(*mask32) { + 65b8: 683b ldr r3, [r7, #0] + 65ba: b14b cbz r3, 65d0 <_lv_blend_fill+0x3e0> + if((*mask32) == 0xFFFFFFFF) { + 65bc: 3301 adds r3, #1 + 65be: d10c bne.n 65da <_lv_blend_fill+0x3ea> + disp_buf_first[x] = color; + 65c0: f8a9 6000 strh.w r6, [r9] + disp_buf_first[x + 1] = color; + 65c4: f8a9 6002 strh.w r6, [r9, #2] + disp_buf_first[x + 2] = color; + 65c8: f8a9 6004 strh.w r6, [r9, #4] + FILL_NORMAL_MASK_PX(x + 3, color) + 65cc: f8a9 6006 strh.w r6, [r9, #6] + mask32++; + 65d0: 3704 adds r7, #4 + for(; x <= x_end4; x += 4) { + 65d2: 3404 adds r4, #4 + 65d4: f109 0908 add.w r9, r9, #8 + 65d8: e7dc b.n 6594 <_lv_blend_fill+0x3a4> + FILL_NORMAL_MASK_PX(x, color) + 65da: 783a ldrb r2, [r7, #0] + 65dc: b11a cbz r2, 65e6 <_lv_blend_fill+0x3f6> + 65de: 2aff cmp r2, #255 ; 0xff + 65e0: d119 bne.n 6616 <_lv_blend_fill+0x426> + 65e2: f8a9 6000 strh.w r6, [r9] + FILL_NORMAL_MASK_PX(x + 1, color) + 65e6: 787a ldrb r2, [r7, #1] + 65e8: b11a cbz r2, 65f2 <_lv_blend_fill+0x402> + 65ea: 2aff cmp r2, #255 ; 0xff + 65ec: d11a bne.n 6624 <_lv_blend_fill+0x434> + 65ee: f8a9 6002 strh.w r6, [r9, #2] + FILL_NORMAL_MASK_PX(x + 2, color) + 65f2: 78ba ldrb r2, [r7, #2] + 65f4: b11a cbz r2, 65fe <_lv_blend_fill+0x40e> + 65f6: 2aff cmp r2, #255 ; 0xff + 65f8: d11b bne.n 6632 <_lv_blend_fill+0x442> + 65fa: f8a9 6004 strh.w r6, [r9, #4] + FILL_NORMAL_MASK_PX(x + 3, color) + 65fe: 78fa ldrb r2, [r7, #3] + 6600: 2a00 cmp r2, #0 + 6602: d0e5 beq.n 65d0 <_lv_blend_fill+0x3e0> + 6604: 2aff cmp r2, #255 ; 0xff + 6606: d0e1 beq.n 65cc <_lv_blend_fill+0x3dc> + 6608: f8b9 1006 ldrh.w r1, [r9, #6] + 660c: 4630 mov r0, r6 + 660e: 47c0 blx r8 + 6610: f8a9 0006 strh.w r0, [r9, #6] + 6614: e7dc b.n 65d0 <_lv_blend_fill+0x3e0> + FILL_NORMAL_MASK_PX(x, color) + 6616: f8b9 1000 ldrh.w r1, [r9] + 661a: 4630 mov r0, r6 + 661c: 47c0 blx r8 + 661e: f8a9 0000 strh.w r0, [r9] + 6622: e7e0 b.n 65e6 <_lv_blend_fill+0x3f6> + FILL_NORMAL_MASK_PX(x + 1, color) + 6624: f8b9 1002 ldrh.w r1, [r9, #2] + 6628: 4630 mov r0, r6 + 662a: 47c0 blx r8 + 662c: f8a9 0002 strh.w r0, [r9, #2] + 6630: e7df b.n 65f2 <_lv_blend_fill+0x402> + FILL_NORMAL_MASK_PX(x + 2, color) + 6632: f8b9 1004 ldrh.w r1, [r9, #4] + 6636: 4630 mov r0, r6 + 6638: 47c0 blx r8 + 663a: f8a9 0004 strh.w r0, [r9, #4] + 663e: e7de b.n 65fe <_lv_blend_fill+0x40e> + FILL_NORMAL_MASK_PX(x, color) + 6640: f817 2f01 ldrb.w r2, [r7, #1]! + 6644: b11a cbz r2, 664e <_lv_blend_fill+0x45e> + 6646: 2aff cmp r2, #255 ; 0xff + 6648: d105 bne.n 6656 <_lv_blend_fill+0x466> + 664a: f8a9 6000 strh.w r6, [r9] + for(; x < draw_area_w ; x++) { + 664e: 3401 adds r4, #1 + 6650: f109 0902 add.w r9, r9, #2 + 6654: e7a4 b.n 65a0 <_lv_blend_fill+0x3b0> + FILL_NORMAL_MASK_PX(x, color) + 6656: f8b9 1000 ldrh.w r1, [r9] + 665a: 4630 mov r0, r6 + 665c: 47c0 blx r8 + 665e: f8a9 0000 strh.w r0, [r9] + 6662: e7f4 b.n 664e <_lv_blend_fill+0x45e> + if(*mask_tmp_x) { + 6664: 9a05 ldr r2, [sp, #20] + 6666: f812 4008 ldrb.w r4, [r2, r8] + 666a: b1d4 cbz r4, 66a2 <_lv_blend_fill+0x4b2> + if(*mask_tmp_x != last_mask) opa_tmp = *mask_tmp_x == LV_OPA_COVER ? opa : + 666c: 455c cmp r4, fp + if(*mask_tmp_x != last_mask || last_dest_color.full != disp_buf_first[x].full) { + 666e: f8b7 9000 ldrh.w r9, [r7] + if(*mask_tmp_x != last_mask) opa_tmp = *mask_tmp_x == LV_OPA_COVER ? opa : + 6672: d012 beq.n 669a <_lv_blend_fill+0x4aa> + 6674: 2cff cmp r4, #255 ; 0xff + (uint32_t)((uint32_t)(*mask_tmp_x) * opa) >> 8; + 6676: bf17 itett ne + 6678: 9a04 ldrne r2, [sp, #16] + 667a: f8dd a010 ldreq.w sl, [sp, #16] + 667e: fb14 f202 smulbbne r2, r4, r2 + if(*mask_tmp_x != last_mask) opa_tmp = *mask_tmp_x == LV_OPA_COVER ? opa : + 6682: ea4f 2a12 movne.w sl, r2, lsr #8 + 6686: 9307 str r3, [sp, #28] + else last_res_color = lv_color_mix(color, disp_buf_first[x], opa_tmp); + 6688: 8839 ldrh r1, [r7, #0] + 668a: 4b55 ldr r3, [pc, #340] ; (67e0 <_lv_blend_fill+0x5f0>) + 668c: 4652 mov r2, sl + 668e: 4630 mov r0, r6 + 6690: 4798 blx r3 + 6692: 46a3 mov fp, r4 + 6694: 9b07 ldr r3, [sp, #28] + 6696: b280 uxth r0, r0 + last_dest_color.full = disp_buf_first[x].full; + 6698: e001 b.n 669e <_lv_blend_fill+0x4ae> + if(*mask_tmp_x != last_mask || last_dest_color.full != disp_buf_first[x].full) { + 669a: 4549 cmp r1, r9 + 669c: d1f3 bne.n 6686 <_lv_blend_fill+0x496> + disp_buf_first[x] = last_res_color; + 669e: 8038 strh r0, [r7, #0] + if(*mask_tmp_x != last_mask || last_dest_color.full != disp_buf_first[x].full) { + 66a0: 4649 mov r1, r9 + for(x = 0; x < draw_area_w; x++) { + 66a2: f108 0801 add.w r8, r8, #1 + 66a6: 3702 adds r7, #2 + 66a8: 9a06 ldr r2, [sp, #24] + 66aa: 4542 cmp r2, r8 + 66ac: dcda bgt.n 6664 <_lv_blend_fill+0x474> + disp_buf_first += disp_w; + 66ae: 9a09 ldr r2, [sp, #36] ; 0x24 + 66b0: 4415 add r5, r2 + mask += draw_area_w; + 66b2: e9dd 2405 ldrd r2, r4, [sp, #20] + 66b6: 4422 add r2, r4 + 66b8: 9205 str r2, [sp, #20] + for(y = draw_area->y1; y <= draw_area->y2; y++) { + 66ba: 3301 adds r3, #1 + 66bc: 9a08 ldr r2, [sp, #32] + 66be: 4293 cmp r3, r2 + 66c0: f73f ae4a bgt.w 6358 <_lv_blend_fill+0x168> + 66c4: 462f mov r7, r5 + for(x = 0; x < draw_area_w; x++) { + 66c6: f04f 0800 mov.w r8, #0 + 66ca: e7ed b.n 66a8 <_lv_blend_fill+0x4b8> + last_res_color.full = disp_buf_first[0].full; + 66cc: 4608 mov r0, r1 + lv_opa_t opa_tmp = LV_OPA_TRANSP; + 66ce: 46da mov sl, fp + 66d0: e7f4 b.n 66bc <_lv_blend_fill+0x4cc> + switch(mode) { + 66d2: f1bb 0f01 cmp.w fp, #1 + 66d6: f9b8 0010 ldrsh.w r0, [r8, #16] + 66da: f9b8 6014 ldrsh.w r6, [r8, #20] + 66de: d00c beq.n 66fa <_lv_blend_fill+0x50a> + 66e0: f1bb 0f02 cmp.w fp, #2 + 66e4: d02d beq.n 6742 <_lv_blend_fill+0x552> + LV_LOG_WARN("fill_blended: unsupported blend mode"); + 66e6: 4b3f ldr r3, [pc, #252] ; (67e4 <_lv_blend_fill+0x5f4>) + 66e8: 9300 str r3, [sp, #0] + 66ea: 493f ldr r1, [pc, #252] ; (67e8 <_lv_blend_fill+0x5f8>) + 66ec: 4b3f ldr r3, [pc, #252] ; (67ec <_lv_blend_fill+0x5fc>) + 66ee: 4c40 ldr r4, [pc, #256] ; (67f0 <_lv_blend_fill+0x600>) + 66f0: f44f 7204 mov.w r2, #528 ; 0x210 + 66f4: 2002 movs r0, #2 + 66f6: 47a0 blx r4 + return; + 66f8: e62e b.n 6358 <_lv_blend_fill+0x168> + blend_fp = color_blend_true_color_additive; + 66fa: f8df b0f8 ldr.w fp, [pc, #248] ; 67f4 <_lv_blend_fill+0x604> + 66fe: 3601 adds r6, #1 + 6700: 1a36 subs r6, r6, r0 + 6702: b236 sxth r6, r6 + lv_color_t * disp_buf_tmp = disp_buf + disp_w * draw_area->y1; + 6704: fb06 f005 mul.w r0, r6, r5 + if(mask_res == LV_DRAW_MASK_RES_FULL_COVER) { + 6708: 2f01 cmp r7, #1 + lv_color_t * disp_buf_tmp = disp_buf + disp_w * draw_area->y1; + 670a: eb09 0a40 add.w sl, r9, r0, lsl #1 + disp_buf_tmp += disp_w; + 670e: ea4f 0646 mov.w r6, r6, lsl #1 + if(mask_res == LV_DRAW_MASK_RES_FULL_COVER) { + 6712: d127 bne.n 6764 <_lv_blend_fill+0x574> + lv_color_t last_dest_color = LV_COLOR_BLACK; + 6714: f04f 0800 mov.w r8, #0 + lv_color_t last_res_color = lv_color_mix(color, last_dest_color, opa); + 6718: 9a04 ldr r2, [sp, #16] + 671a: 4b31 ldr r3, [pc, #196] ; (67e0 <_lv_blend_fill+0x5f0>) + 671c: 4641 mov r1, r8 + 671e: 4620 mov r0, r4 + 6720: 4798 blx r3 + for(y = draw_area->y1; y <= draw_area->y2; y++) { + 6722: f9bd 302e ldrsh.w r3, [sp, #46] ; 0x2e + 6726: 429d cmp r5, r3 + 6728: f73f ae16 bgt.w 6358 <_lv_blend_fill+0x168> + for(x = draw_area->x1; x <= draw_area->x2; x++) { + 672c: f9bd 7028 ldrsh.w r7, [sp, #40] ; 0x28 + 6730: eb0a 0947 add.w r9, sl, r7, lsl #1 + 6734: f9bd 302c ldrsh.w r3, [sp, #44] ; 0x2c + 6738: 429f cmp r7, r3 + 673a: dd05 ble.n 6748 <_lv_blend_fill+0x558> + disp_buf_tmp += disp_w; + 673c: 44b2 add sl, r6 + for(y = draw_area->y1; y <= draw_area->y2; y++) { + 673e: 3501 adds r5, #1 + 6740: e7ef b.n 6722 <_lv_blend_fill+0x532> + switch(mode) { + 6742: f8df b0b4 ldr.w fp, [pc, #180] ; 67f8 <_lv_blend_fill+0x608> + 6746: e7da b.n 66fe <_lv_blend_fill+0x50e> + if(last_dest_color.full != disp_buf_tmp[x].full) { + 6748: f8b9 1000 ldrh.w r1, [r9] + 674c: fa1f f388 uxth.w r3, r8 + 6750: 428b cmp r3, r1 + 6752: d003 beq.n 675c <_lv_blend_fill+0x56c> + last_res_color = blend_fp(color, disp_buf_tmp[x], opa); + 6754: 9a04 ldr r2, [sp, #16] + 6756: 4620 mov r0, r4 + last_dest_color = disp_buf_tmp[x]; + 6758: 4688 mov r8, r1 + last_res_color = blend_fp(color, disp_buf_tmp[x], opa); + 675a: 47d8 blx fp + disp_buf_tmp[x] = last_res_color; + 675c: f829 0b02 strh.w r0, [r9], #2 + for(x = draw_area->x1; x <= draw_area->x2; x++) { + 6760: 3701 adds r7, #1 + 6762: e7e7 b.n 6734 <_lv_blend_fill+0x544> + 6764: f1c2 0201 rsb r2, r2, #1 + 6768: eb03 0802 add.w r8, r3, r2 + const lv_opa_t * mask_tmp = mask - draw_area->x1; + 676c: 9b05 ldr r3, [sp, #20] + 676e: 1a5f subs r7, r3, r1 + last_dest_color.full = disp_buf_tmp[0].full; + 6770: f839 1010 ldrh.w r1, [r9, r0, lsl #1] + 6774: fa0f f888 sxth.w r8, r8 + last_res_color.full = disp_buf_tmp[0].full; + 6778: 4608 mov r0, r1 + lv_opa_t last_mask = LV_OPA_TRANSP; + 677a: f04f 0c00 mov.w ip, #0 + for(y = draw_area->y1; y <= draw_area->y2; y++) { + 677e: f9bd 302e ldrsh.w r3, [sp, #46] ; 0x2e + 6782: 429d cmp r5, r3 + 6784: f73f ade8 bgt.w 6358 <_lv_blend_fill+0x168> + for(x = draw_area->x1; x <= draw_area->x2; x++) { + 6788: f9bd 9028 ldrsh.w r9, [sp, #40] ; 0x28 + 678c: eb0a 0349 add.w r3, sl, r9, lsl #1 + 6790: f9bd 202c ldrsh.w r2, [sp, #44] ; 0x2c + 6794: 4591 cmp r9, r2 + 6796: dd03 ble.n 67a0 <_lv_blend_fill+0x5b0> + disp_buf_tmp += disp_w; + 6798: 44b2 add sl, r6 + mask_tmp += draw_area_w; + 679a: 4447 add r7, r8 + for(y = draw_area->y1; y <= draw_area->y2; y++) { + 679c: 3501 adds r5, #1 + 679e: e7ee b.n 677e <_lv_blend_fill+0x58e> + if(mask_tmp[x] == 0) continue; + 67a0: f817 2009 ldrb.w r2, [r7, r9] + 67a4: b1ba cbz r2, 67d6 <_lv_blend_fill+0x5e6> + if(mask_tmp[x] != last_mask || last_dest_color.full != disp_buf_tmp[x].full) { + 67a6: 4562 cmp r2, ip + 67a8: d103 bne.n 67b2 <_lv_blend_fill+0x5c2> + 67aa: f8b3 e000 ldrh.w lr, [r3] + 67ae: 458e cmp lr, r1 + 67b0: d010 beq.n 67d4 <_lv_blend_fill+0x5e4> + lv_opa_t opa_tmp = mask_tmp[x] >= LV_OPA_MAX ? opa : (uint32_t)((uint32_t)mask_tmp[x] * opa) >> 8; + 67b2: 2af9 cmp r2, #249 ; 0xf9 + 67b4: bf94 ite ls + 67b6: 9904 ldrls r1, [sp, #16] + 67b8: 9a04 ldrhi r2, [sp, #16] + last_res_color = blend_fp(color, disp_buf_tmp[x], opa_tmp); + 67ba: 9305 str r3, [sp, #20] + lv_opa_t opa_tmp = mask_tmp[x] >= LV_OPA_MAX ? opa : (uint32_t)((uint32_t)mask_tmp[x] * opa) >> 8; + 67bc: bf9c itt ls + 67be: fb12 f201 smulbbls r2, r2, r1 + 67c2: 0a12 lsrls r2, r2, #8 + last_res_color = blend_fp(color, disp_buf_tmp[x], opa_tmp); + 67c4: 8819 ldrh r1, [r3, #0] + 67c6: 4620 mov r0, r4 + 67c8: 47d8 blx fp + last_dest_color.full = disp_buf_tmp[x].full; + 67ca: 9b05 ldr r3, [sp, #20] + last_mask = mask_tmp[x]; + 67cc: f817 c009 ldrb.w ip, [r7, r9] + last_dest_color.full = disp_buf_tmp[x].full; + 67d0: 8819 ldrh r1, [r3, #0] + last_res_color = blend_fp(color, disp_buf_tmp[x], opa_tmp); + 67d2: b280 uxth r0, r0 + disp_buf_tmp[x] = last_res_color; + 67d4: 8018 strh r0, [r3, #0] + for(x = draw_area->x1; x <= draw_area->x2; x++) { + 67d6: f109 0901 add.w r9, r9, #1 + 67da: 3302 adds r3, #2 + 67dc: e7d8 b.n 6790 <_lv_blend_fill+0x5a0> + 67de: bf00 nop + 67e0: 000060a5 .word 0x000060a5 + 67e4: 0001f9d9 .word 0x0001f9d9 + 67e8: 0001f9a3 .word 0x0001f9a3 + 67ec: 0001f9fe .word 0x0001f9fe + 67f0: 0000e8e9 .word 0x0000e8e9 + 67f4: 000060f5 .word 0x000060f5 + 67f8: 00006175 .word 0x00006175 + +000067fc <_lv_blend_map>: +{ + 67fc: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 6800: b08f sub sp, #60 ; 0x3c + 6802: 4689 mov r9, r1 + 6804: 9306 str r3, [sp, #24] + 6806: f89d 3060 ldrb.w r3, [sp, #96] ; 0x60 + 680a: 930a str r3, [sp, #40] ; 0x28 + 680c: f89d 3064 ldrb.w r3, [sp, #100] ; 0x64 + 6810: f89d a068 ldrb.w sl, [sp, #104] ; 0x68 + 6814: 920b str r2, [sp, #44] ; 0x2c + if(opa < LV_OPA_MIN) return; + 6816: 2b04 cmp r3, #4 +{ + 6818: 9305 str r3, [sp, #20] + if(opa < LV_OPA_MIN) return; + 681a: f240 80d7 bls.w 69cc <_lv_blend_map+0x1d0> + if(mask_res == LV_DRAW_MASK_RES_TRANSP) return; + 681e: 9b0a ldr r3, [sp, #40] ; 0x28 + 6820: 2b00 cmp r3, #0 + 6822: f000 80d3 beq.w 69cc <_lv_blend_map+0x1d0> + is_common = _lv_area_intersect(&draw_area, clip_area, map_area); + 6826: 460a mov r2, r1 + 6828: 4bb6 ldr r3, [pc, #728] ; (6b04 <_lv_blend_map+0x308>) + 682a: 4601 mov r1, r0 + 682c: a80c add r0, sp, #48 ; 0x30 + 682e: 4798 blx r3 + if(!is_common) return; + 6830: 2800 cmp r0, #0 + 6832: f000 80cb beq.w 69cc <_lv_blend_map+0x1d0> + lv_disp_t * disp = _lv_refr_get_disp_refreshing(); + 6836: 4bb4 ldr r3, [pc, #720] ; (6b08 <_lv_blend_map+0x30c>) + 6838: 4798 blx r3 + lv_disp_buf_t * vdb = lv_disp_get_buf(disp); + 683a: 4bb4 ldr r3, [pc, #720] ; (6b0c <_lv_blend_map+0x310>) + lv_disp_t * disp = _lv_refr_get_disp_refreshing(); + 683c: 4605 mov r5, r0 + lv_disp_buf_t * vdb = lv_disp_get_buf(disp); + 683e: 4798 blx r3 + 6840: 4683 mov fp, r0 + lv_color_t * disp_buf = vdb->buf_act; + 6842: 6883 ldr r3, [r0, #8] + draw_area.y1 -= disp_area->y1; + 6844: f8bd e032 ldrh.w lr, [sp, #50] ; 0x32 + lv_color_t * disp_buf = vdb->buf_act; + 6848: 9308 str r3, [sp, #32] + draw_area.y1 -= disp_area->y1; + 684a: f8bb 3012 ldrh.w r3, [fp, #18] + draw_area.y2 -= disp_area->y1; + 684e: f8bd c036 ldrh.w ip, [sp, #54] ; 0x36 + draw_area.x1 -= disp_area->x1; + 6852: f8bd 4030 ldrh.w r4, [sp, #48] ; 0x30 + 6856: 8a00 ldrh r0, [r0, #16] + draw_area.y1 -= disp_area->y1; + 6858: ebae 0203 sub.w r2, lr, r3 + 685c: fa0f f882 sxth.w r8, r2 + draw_area.y2 -= disp_area->y1; + 6860: ebac 0303 sub.w r3, ip, r3 + draw_area.x2 -= disp_area->x1; + 6864: f8bd 2034 ldrh.w r2, [sp, #52] ; 0x34 + draw_area.y2 -= disp_area->y1; + 6868: f8ad 3036 strh.w r3, [sp, #54] ; 0x36 + draw_area.x1 -= disp_area->x1; + 686c: 1a21 subs r1, r4, r0 + if(mask && disp->driver.antialiasing == 0) + 686e: 9b06 ldr r3, [sp, #24] + draw_area.y1 -= disp_area->y1; + 6870: f8ad 8032 strh.w r8, [sp, #50] ; 0x32 + draw_area.x1 -= disp_area->x1; + 6874: b209 sxth r1, r1 + draw_area.x2 -= disp_area->x1; + 6876: 1a10 subs r0, r2, r0 + draw_area.x1 -= disp_area->x1; + 6878: f8ad 1030 strh.w r1, [sp, #48] ; 0x30 + draw_area.x2 -= disp_area->x1; + 687c: f8ad 0034 strh.w r0, [sp, #52] ; 0x34 + if(mask && disp->driver.antialiasing == 0) + 6880: 2b00 cmp r3, #0 + 6882: d15e bne.n 6942 <_lv_blend_map+0x146> + if(disp->driver.set_px_cb) { + 6884: 696b ldr r3, [r5, #20] + 6886: 2b00 cmp r3, #0 + 6888: d172 bne.n 6970 <_lv_blend_map+0x174> + 688a: f1c4 0401 rsb r4, r4, #1 + 688e: 4422 add r2, r4 + 6890: f8b9 7004 ldrh.w r7, [r9, #4] + 6894: f8bb 6014 ldrh.w r6, [fp, #20] + 6898: f9bb 3010 ldrsh.w r3, [fp, #16] + const lv_color_t * map_buf_first = map_buf + map_w * (draw_area->y1 - (map_area->y1 - disp_area->y1)); + 689c: f9bb 0012 ldrsh.w r0, [fp, #18] + 68a0: b212 sxth r2, r2 + 68a2: 9207 str r2, [sp, #28] + 68a4: f9b9 2000 ldrsh.w r2, [r9] + 68a8: f9b9 9002 ldrsh.w r9, [r9, #2] + 68ac: 3601 adds r6, #1 + 68ae: 3701 adds r7, #1 + 68b0: 1af6 subs r6, r6, r3 + 68b2: 1abf subs r7, r7, r2 + 68b4: eba9 0900 sub.w r9, r9, r0 + 68b8: b236 sxth r6, r6 + 68ba: b23f sxth r7, r7 + 68bc: eba8 0909 sub.w r9, r8, r9 + lv_color_t * disp_buf_first = disp_buf + disp_w * draw_area->y1 + draw_area->x1; + 68c0: fb06 f408 mul.w r4, r6, r8 + const lv_color_t * map_buf_first = map_buf + map_w * (draw_area->y1 - (map_area->y1 - disp_area->y1)); + 68c4: fb07 f909 mul.w r9, r7, r9 + else if(mode == LV_BLEND_MODE_NORMAL) { + 68c8: f1ba 0f00 cmp.w sl, #0 + 68cc: f040 81ea bne.w 6ca4 <_lv_blend_map+0x4a8> + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + 68d0: f1ce 0001 rsb r0, lr, #1 + map_buf_first += (draw_area->x1 - (map_area->x1 - disp_area->x1)); + 68d4: 1ad5 subs r5, r2, r3 + 68d6: 4484 add ip, r0 + 68d8: 9b0b ldr r3, [sp, #44] ; 0x2c + int32_t draw_area_h = lv_area_get_height(draw_area); + 68da: fa0f f08c sxth.w r0, ip + map_buf_first += (draw_area->x1 - (map_area->x1 - disp_area->x1)); + 68de: 1b4d subs r5, r1, r5 + int32_t draw_area_h = lv_area_get_height(draw_area); + 68e0: 9009 str r0, [sp, #36] ; 0x24 + map_buf_first += (draw_area->x1 - (map_area->x1 - disp_area->x1)); + 68e2: 444d add r5, r9 + lv_color_t * disp_buf_first = disp_buf + disp_w * draw_area->y1 + draw_area->x1; + 68e4: 9808 ldr r0, [sp, #32] + 68e6: 440c add r4, r1 + map_buf_first += (draw_area->x1 - (map_area->x1 - disp_area->x1)); + 68e8: eb03 0545 add.w r5, r3, r5, lsl #1 + lv_disp_t * disp = _lv_refr_get_disp_refreshing(); + 68ec: 4b86 ldr r3, [pc, #536] ; (6b08 <_lv_blend_map+0x30c>) + lv_color_t * disp_buf_first = disp_buf + disp_w * draw_area->y1 + draw_area->x1; + 68ee: eb00 0444 add.w r4, r0, r4, lsl #1 + lv_disp_t * disp = _lv_refr_get_disp_refreshing(); + 68f2: 4798 blx r3 + map_buf_first += map_w; + 68f4: 007b lsls r3, r7, #1 + 68f6: 9308 str r3, [sp, #32] + if(mask_res == LV_DRAW_MASK_RES_FULL_COVER) { + 68f8: 9b0a ldr r3, [sp, #40] ; 0x28 + 68fa: 2b01 cmp r3, #1 + lv_disp_t * disp = _lv_refr_get_disp_refreshing(); + 68fc: 4680 mov r8, r0 + disp_buf_first += disp_w; + 68fe: ea4f 0b46 mov.w fp, r6, lsl #1 + if(mask_res == LV_DRAW_MASK_RES_FULL_COVER) { + 6902: f040 80e0 bne.w 6ac6 <_lv_blend_map+0x2ca> + if(disp->driver.gpu_blend_cb && (lv_area_get_size(draw_area) > GPU_SIZE_LIMIT)) { + 6906: 6a03 ldr r3, [r0, #32] + 6908: 2b00 cmp r3, #0 + 690a: f000 80af beq.w 6a6c <_lv_blend_map+0x270> + 690e: 4b80 ldr r3, [pc, #512] ; (6b10 <_lv_blend_map+0x314>) + 6910: a80c add r0, sp, #48 ; 0x30 + 6912: 4798 blx r3 + 6914: 28f0 cmp r0, #240 ; 0xf0 + 6916: f240 80a9 bls.w 6a6c <_lv_blend_map+0x270> + for(y = draw_area->y1; y <= draw_area->y2; y++) { + 691a: f9bd 7032 ldrsh.w r7, [sp, #50] ; 0x32 + 691e: f9bd 3036 ldrsh.w r3, [sp, #54] ; 0x36 + 6922: 429f cmp r7, r3 + 6924: dc52 bgt.n 69cc <_lv_blend_map+0x1d0> + disp->driver.gpu_blend_cb(&disp->driver, disp_buf_first, map_buf_first, draw_area_w, opa); + 6926: 9b05 ldr r3, [sp, #20] + 6928: 9300 str r3, [sp, #0] + 692a: 462a mov r2, r5 + 692c: 9b07 ldr r3, [sp, #28] + 692e: f8d8 6020 ldr.w r6, [r8, #32] + 6932: 4621 mov r1, r4 + 6934: 4640 mov r0, r8 + 6936: 47b0 blx r6 + map_buf_first += map_w; + 6938: 9b08 ldr r3, [sp, #32] + disp_buf_first += disp_w; + 693a: 445c add r4, fp + map_buf_first += map_w; + 693c: 441d add r5, r3 + for(y = draw_area->y1; y <= draw_area->y2; y++) { + 693e: 3701 adds r7, #1 + 6940: e7ed b.n 691e <_lv_blend_map+0x122> + if(mask && disp->driver.antialiasing == 0) + 6942: 7a2b ldrb r3, [r5, #8] + 6944: 07d8 lsls r0, r3, #31 + 6946: d49d bmi.n 6884 <_lv_blend_map+0x88> + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + 6948: 9806 ldr r0, [sp, #24] + for(i = 0; i < mask_w; i++) mask[i] = mask[i] > 128 ? LV_OPA_COVER : LV_OPA_TRANSP; + 694a: 9e06 ldr r6, [sp, #24] + 694c: 1c53 adds r3, r2, #1 + 694e: 1b1b subs r3, r3, r4 + int32_t mask_w = lv_area_get_width(&draw_area); + 6950: b21b sxth r3, r3 + for(i = 0; i < mask_w; i++) mask[i] = mask[i] > 128 ? LV_OPA_COVER : LV_OPA_TRANSP; + 6952: 3801 subs r0, #1 + 6954: f1c6 0701 rsb r7, r6, #1 + 6958: 183e adds r6, r7, r0 + 695a: 42b3 cmp r3, r6 + 695c: dd92 ble.n 6884 <_lv_blend_map+0x88> + 695e: f810 6f01 ldrb.w r6, [r0, #1]! + 6962: 2e80 cmp r6, #128 ; 0x80 + 6964: f04f 36ff mov.w r6, #4294967295 ; 0xffffffff + 6968: bf98 it ls + 696a: 2600 movls r6, #0 + 696c: 7006 strb r6, [r0, #0] + 696e: e7f3 b.n 6958 <_lv_blend_map+0x15c> + lv_disp_t * disp = _lv_refr_get_disp_refreshing(); + 6970: 4b65 ldr r3, [pc, #404] ; (6b08 <_lv_blend_map+0x30c>) + 6972: 4798 blx r3 + 6974: f8b9 5004 ldrh.w r5, [r9, #4] + 6978: f9b9 1000 ldrsh.w r1, [r9] + 697c: f8bb 2014 ldrh.w r2, [fp, #20] + const lv_color_t * map_buf_tmp = map_buf + map_w * (draw_area->y1 - (map_area->y1 - disp_area->y1)); + 6980: f9bb c012 ldrsh.w ip, [fp, #18] + 6984: f9b9 7002 ldrsh.w r7, [r9, #2] + 6988: f9bb 4010 ldrsh.w r4, [fp, #16] + 698c: f9bd 6032 ldrsh.w r6, [sp, #50] ; 0x32 + 6990: f9bd 3030 ldrsh.w r3, [sp, #48] ; 0x30 + 6994: f9bd 8034 ldrsh.w r8, [sp, #52] ; 0x34 + 6998: 3501 adds r5, #1 + 699a: 1a6d subs r5, r5, r1 + 699c: 3201 adds r2, #1 + 699e: eba7 070c sub.w r7, r7, ip + 69a2: 1b12 subs r2, r2, r4 + 69a4: b22d sxth r5, r5 + map_buf_tmp -= draw_area->x1; + 69a6: 1a64 subs r4, r4, r1 + const lv_color_t * map_buf_tmp = map_buf + map_w * (draw_area->y1 - (map_area->y1 - disp_area->y1)); + 69a8: 1bf7 subs r7, r6, r7 + map_buf_tmp -= draw_area->x1; + 69aa: 990b ldr r1, [sp, #44] ; 0x2c + 69ac: fb05 4407 mla r4, r5, r7, r4 + 69b0: eb01 0444 add.w r4, r1, r4, lsl #1 + if(mask_res == LV_DRAW_MASK_RES_FULL_COVER) { + 69b4: 990a ldr r1, [sp, #40] ; 0x28 + 69b6: 2901 cmp r1, #1 + 69b8: b212 sxth r2, r2 + 69ba: f1c3 0a00 rsb sl, r3, #0 + 69be: ea4f 0b45 mov.w fp, r5, lsl #1 + 69c2: d123 bne.n 6a0c <_lv_blend_map+0x210> + for(y = draw_area->y1; y <= draw_area->y2; y++) { + 69c4: f9bd 3036 ldrsh.w r3, [sp, #54] ; 0x36 + 69c8: 429e cmp r6, r3 + 69ca: dd02 ble.n 69d2 <_lv_blend_map+0x1d6> +} + 69cc: b00f add sp, #60 ; 0x3c + 69ce: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + for(x = draw_area->x1; x <= draw_area->x2; x++) { + 69d2: f9bd 8030 ldrsh.w r8, [sp, #48] ; 0x30 + disp->driver.set_px_cb(&disp->driver, (void *)disp_buf, disp_w, x, y, map_buf_tmp[x], opa); + 69d6: b237 sxth r7, r6 + for(x = draw_area->x1; x <= draw_area->x2; x++) { + 69d8: f9bd 3034 ldrsh.w r3, [sp, #52] ; 0x34 + 69dc: 4598 cmp r8, r3 + 69de: dd02 ble.n 69e6 <_lv_blend_map+0x1ea> + map_buf_tmp += map_w; + 69e0: 445c add r4, fp + for(y = draw_area->y1; y <= draw_area->y2; y++) { + 69e2: 3601 adds r6, #1 + 69e4: e7ee b.n 69c4 <_lv_blend_map+0x1c8> + disp->driver.set_px_cb(&disp->driver, (void *)disp_buf, disp_w, x, y, map_buf_tmp[x], opa); + 69e6: 9b05 ldr r3, [sp, #20] + 69e8: 9302 str r3, [sp, #8] + 69ea: f834 3018 ldrh.w r3, [r4, r8, lsl #1] + 69ee: f8ad 3004 strh.w r3, [sp, #4] + 69f2: 9700 str r7, [sp, #0] + 69f4: 6945 ldr r5, [r0, #20] + 69f6: 9908 ldr r1, [sp, #32] + 69f8: 9207 str r2, [sp, #28] + 69fa: fa0f f388 sxth.w r3, r8 + 69fe: 9006 str r0, [sp, #24] + for(x = draw_area->x1; x <= draw_area->x2; x++) { + 6a00: f108 0801 add.w r8, r8, #1 + disp->driver.set_px_cb(&disp->driver, (void *)disp_buf, disp_w, x, y, map_buf_tmp[x], opa); + 6a04: 47a8 blx r5 + for(x = draw_area->x1; x <= draw_area->x2; x++) { + 6a06: e9dd 0206 ldrd r0, r2, [sp, #24] + 6a0a: e7e5 b.n 69d8 <_lv_blend_map+0x1dc> + 6a0c: f108 0801 add.w r8, r8, #1 + 6a10: eba8 0803 sub.w r8, r8, r3 + const lv_opa_t * mask_tmp = mask - draw_area->x1; + 6a14: 9b06 ldr r3, [sp, #24] + 6a16: 4453 add r3, sl + 6a18: fa0f f888 sxth.w r8, r8 + 6a1c: 469a mov sl, r3 + for(y = draw_area->y1; y <= draw_area->y2; y++) { + 6a1e: f9bd 3036 ldrsh.w r3, [sp, #54] ; 0x36 + 6a22: 429e cmp r6, r3 + 6a24: dcd2 bgt.n 69cc <_lv_blend_map+0x1d0> + for(x = draw_area->x1; x <= draw_area->x2; x++) { + 6a26: f9bd 9030 ldrsh.w r9, [sp, #48] ; 0x30 + disp->driver.set_px_cb(&disp->driver, (void *)disp_buf, disp_w, x, y, map_buf_tmp[x], + 6a2a: b237 sxth r7, r6 + for(x = draw_area->x1; x <= draw_area->x2; x++) { + 6a2c: f9bd 3034 ldrsh.w r3, [sp, #52] ; 0x34 + 6a30: 4599 cmp r9, r3 + 6a32: dd03 ble.n 6a3c <_lv_blend_map+0x240> + mask_tmp += draw_area_w; + 6a34: 44c2 add sl, r8 + map_buf_tmp += map_w; + 6a36: 445c add r4, fp + for(y = draw_area->y1; y <= draw_area->y2; y++) { + 6a38: 3601 adds r6, #1 + 6a3a: e7f0 b.n 6a1e <_lv_blend_map+0x222> + (uint32_t)((uint32_t)opa * mask_tmp[x]) >> 8); + 6a3c: f81a 3009 ldrb.w r3, [sl, r9] + 6a40: 9905 ldr r1, [sp, #20] + disp->driver.set_px_cb(&disp->driver, (void *)disp_buf, disp_w, x, y, map_buf_tmp[x], + 6a42: 9207 str r2, [sp, #28] + (uint32_t)((uint32_t)opa * mask_tmp[x]) >> 8); + 6a44: fb13 f301 smulbb r3, r3, r1 + disp->driver.set_px_cb(&disp->driver, (void *)disp_buf, disp_w, x, y, map_buf_tmp[x], + 6a48: 0a1b lsrs r3, r3, #8 + 6a4a: 9302 str r3, [sp, #8] + 6a4c: f834 3019 ldrh.w r3, [r4, r9, lsl #1] + 6a50: f8ad 3004 strh.w r3, [sp, #4] + 6a54: 9700 str r7, [sp, #0] + 6a56: 6945 ldr r5, [r0, #20] + 6a58: 9908 ldr r1, [sp, #32] + 6a5a: 9006 str r0, [sp, #24] + 6a5c: fa0f f389 sxth.w r3, r9 + 6a60: 47a8 blx r5 + for(x = draw_area->x1; x <= draw_area->x2; x++) { + 6a62: f109 0901 add.w r9, r9, #1 + 6a66: e9dd 0206 ldrd r0, r2, [sp, #24] + 6a6a: e7df b.n 6a2c <_lv_blend_map+0x230> + if(opa > LV_OPA_MAX) { + 6a6c: 9b05 ldr r3, [sp, #20] + 6a6e: 2bfa cmp r3, #250 ; 0xfa + 6a70: d925 bls.n 6abe <_lv_blend_map+0x2c2> + _lv_memcpy(disp_buf_first, map_buf_first, draw_area_w * sizeof(lv_color_t)); + 6a72: 9b07 ldr r3, [sp, #28] + 6a74: f8df 809c ldr.w r8, [pc, #156] ; 6b14 <_lv_blend_map+0x318> + 6a78: 005f lsls r7, r3, #1 + for(y = 0; y < draw_area_h; y++) { + 6a7a: 2600 movs r6, #0 + 6a7c: 9b09 ldr r3, [sp, #36] ; 0x24 + 6a7e: 42b3 cmp r3, r6 + 6a80: dda4 ble.n 69cc <_lv_blend_map+0x1d0> + _lv_memcpy(disp_buf_first, map_buf_first, draw_area_w * sizeof(lv_color_t)); + 6a82: 4629 mov r1, r5 + 6a84: 4620 mov r0, r4 + 6a86: 463a mov r2, r7 + 6a88: 47c0 blx r8 + map_buf_first += map_w; + 6a8a: 9b08 ldr r3, [sp, #32] + disp_buf_first += disp_w; + 6a8c: 445c add r4, fp + map_buf_first += map_w; + 6a8e: 441d add r5, r3 + for(y = 0; y < draw_area_h; y++) { + 6a90: 3601 adds r6, #1 + 6a92: e7f3 b.n 6a7c <_lv_blend_map+0x280> + disp_buf_first[x] = lv_color_mix(map_buf_first[x], disp_buf_first[x], opa); + 6a94: f834 1016 ldrh.w r1, [r4, r6, lsl #1] + 6a98: f835 0016 ldrh.w r0, [r5, r6, lsl #1] + 6a9c: 9a05 ldr r2, [sp, #20] + 6a9e: 47c0 blx r8 + 6aa0: f824 0016 strh.w r0, [r4, r6, lsl #1] + for(x = 0; x < draw_area_w; x++) { + 6aa4: 3601 adds r6, #1 + 6aa6: 9b07 ldr r3, [sp, #28] + 6aa8: 42b3 cmp r3, r6 + 6aaa: dcf3 bgt.n 6a94 <_lv_blend_map+0x298> + map_buf_first += map_w; + 6aac: 9b08 ldr r3, [sp, #32] + disp_buf_first += disp_w; + 6aae: 445c add r4, fp + map_buf_first += map_w; + 6ab0: 441d add r5, r3 + for(y = 0; y < draw_area_h; y++) { + 6ab2: 3701 adds r7, #1 + 6ab4: 9b09 ldr r3, [sp, #36] ; 0x24 + 6ab6: 42bb cmp r3, r7 + 6ab8: dd88 ble.n 69cc <_lv_blend_map+0x1d0> + for(x = 0; x < draw_area_w; x++) { + 6aba: 2600 movs r6, #0 + 6abc: e7f3 b.n 6aa6 <_lv_blend_map+0x2aa> + disp_buf_first[x] = lv_color_mix(map_buf_first[x], disp_buf_first[x], opa); + 6abe: f8df 8058 ldr.w r8, [pc, #88] ; 6b18 <_lv_blend_map+0x31c> + for(y = 0; y < draw_area_h; y++) { + 6ac2: 2700 movs r7, #0 + 6ac4: e7f6 b.n 6ab4 <_lv_blend_map+0x2b8> + if(opa > LV_OPA_MAX) { + 6ac6: 9b05 ldr r3, [sp, #20] + 6ac8: 2bfa cmp r3, #250 ; 0xfa + 6aca: f240 80e9 bls.w 6ca0 <_lv_blend_map+0x4a4> + int32_t x_end4 = draw_area_w - 4; + 6ace: 9b07 ldr r3, [sp, #28] + MAP_NORMAL_MASK_PX(x) + 6ad0: f8df 8044 ldr.w r8, [pc, #68] ; 6b18 <_lv_blend_map+0x31c> + for(y = 0; y < draw_area_h; y++) { + 6ad4: f8cd a014 str.w sl, [sp, #20] + int32_t x_end4 = draw_area_w - 4; + 6ad8: 3b04 subs r3, #4 + 6ada: 930a str r3, [sp, #40] ; 0x28 + for(y = 0; y < draw_area_h; y++) { + 6adc: 9b09 ldr r3, [sp, #36] ; 0x24 + 6ade: 9a05 ldr r2, [sp, #20] + 6ae0: 4293 cmp r3, r2 + 6ae2: f77f af73 ble.w 69cc <_lv_blend_map+0x1d0> + 6ae6: 9b06 ldr r3, [sp, #24] + 6ae8: 46aa mov sl, r5 + 6aea: 46a1 mov r9, r4 + for(x = 0; x < draw_area_w && ((lv_uintptr_t)mask_tmp_x & 0x3); x++) { + 6aec: 2600 movs r6, #0 + 6aee: e025 b.n 6b3c <_lv_blend_map+0x340> + MAP_NORMAL_MASK_PX(x) + 6af0: f8b9 1000 ldrh.w r1, [r9] + 6af4: f8ba 0000 ldrh.w r0, [sl] + 6af8: 930b str r3, [sp, #44] ; 0x2c + 6afa: 47c0 blx r8 + 6afc: 9b0b ldr r3, [sp, #44] ; 0x2c + 6afe: f8a9 0000 strh.w r0, [r9] + 6b02: e016 b.n 6b32 <_lv_blend_map+0x336> + 6b04: 0000de8d .word 0x0000de8d + 6b08: 00004fe9 .word 0x00004fe9 + 6b0c: 0000d9e1 .word 0x0000d9e1 + 6b10: 0000de71 .word 0x0000de71 + 6b14: 0000ec31 .word 0x0000ec31 + 6b18: 000060a5 .word 0x000060a5 + for(x = 0; x < draw_area_w && ((lv_uintptr_t)mask_tmp_x & 0x3); x++) { + 6b1c: 079a lsls r2, r3, #30 + 6b1e: d011 beq.n 6b44 <_lv_blend_map+0x348> + MAP_NORMAL_MASK_PX(x) + 6b20: f813 2b01 ldrb.w r2, [r3], #1 + 6b24: b12a cbz r2, 6b32 <_lv_blend_map+0x336> + 6b26: 2aff cmp r2, #255 ; 0xff + 6b28: d1e2 bne.n 6af0 <_lv_blend_map+0x2f4> + 6b2a: f8ba 2000 ldrh.w r2, [sl] + 6b2e: f8a9 2000 strh.w r2, [r9] + for(x = 0; x < draw_area_w && ((lv_uintptr_t)mask_tmp_x & 0x3); x++) { + 6b32: 3601 adds r6, #1 + 6b34: f10a 0a02 add.w sl, sl, #2 + 6b38: f109 0902 add.w r9, r9, #2 + 6b3c: 9a07 ldr r2, [sp, #28] + 6b3e: 42b2 cmp r2, r6 + 6b40: 461f mov r7, r3 + 6b42: dceb bgt.n 6b1c <_lv_blend_map+0x320> + 6b44: eb05 0a46 add.w sl, r5, r6, lsl #1 + 6b48: eb04 0946 add.w r9, r4, r6, lsl #1 + for(; x < x_end4; x += 4) { + 6b4c: 9b0a ldr r3, [sp, #40] ; 0x28 + 6b4e: 42b3 cmp r3, r6 + 6b50: dc12 bgt.n 6b78 <_lv_blend_map+0x37c> + 6b52: 3f01 subs r7, #1 + 6b54: eb05 0a46 add.w sl, r5, r6, lsl #1 + 6b58: eb04 0946 add.w r9, r4, r6, lsl #1 + for(; x < draw_area_w ; x++) { + 6b5c: 9b07 ldr r3, [sp, #28] + 6b5e: 42b3 cmp r3, r6 + 6b60: dc62 bgt.n 6c28 <_lv_blend_map+0x42c> + mask += draw_area_w; + 6b62: e9dd 3206 ldrd r3, r2, [sp, #24] + 6b66: 4413 add r3, r2 + 6b68: 9306 str r3, [sp, #24] + map_buf_first += map_w; + 6b6a: 9b08 ldr r3, [sp, #32] + 6b6c: 441d add r5, r3 + for(y = 0; y < draw_area_h; y++) { + 6b6e: 9b05 ldr r3, [sp, #20] + 6b70: 3301 adds r3, #1 + disp_buf_first += disp_w; + 6b72: 445c add r4, fp + for(y = 0; y < draw_area_h; y++) { + 6b74: 9305 str r3, [sp, #20] + 6b76: e7b1 b.n 6adc <_lv_blend_map+0x2e0> + if(*mask32) { + 6b78: 683b ldr r3, [r7, #0] + 6b7a: b18b cbz r3, 6ba0 <_lv_blend_map+0x3a4> + if((*mask32) == 0xFFFFFFFF) { + 6b7c: 3301 adds r3, #1 + 6b7e: d116 bne.n 6bae <_lv_blend_map+0x3b2> + disp_buf_first[x] = map_buf_first[x]; + 6b80: f8ba 3000 ldrh.w r3, [sl] + 6b84: f8a9 3000 strh.w r3, [r9] + disp_buf_first[x + 1] = map_buf_first[x + 1]; + 6b88: f8ba 3002 ldrh.w r3, [sl, #2] + 6b8c: f8a9 3002 strh.w r3, [r9, #2] + disp_buf_first[x + 2] = map_buf_first[x + 2]; + 6b90: f8ba 3004 ldrh.w r3, [sl, #4] + 6b94: f8a9 3004 strh.w r3, [r9, #4] + MAP_NORMAL_MASK_PX(x + 3) + 6b98: f8ba 3006 ldrh.w r3, [sl, #6] + 6b9c: f8a9 3006 strh.w r3, [r9, #6] + mask32++; + 6ba0: 3704 adds r7, #4 + for(; x < x_end4; x += 4) { + 6ba2: 3604 adds r6, #4 + 6ba4: f10a 0a08 add.w sl, sl, #8 + 6ba8: f109 0908 add.w r9, r9, #8 + 6bac: e7ce b.n 6b4c <_lv_blend_map+0x350> + MAP_NORMAL_MASK_PX(x) + 6bae: 783a ldrb r2, [r7, #0] + 6bb0: b12a cbz r2, 6bbe <_lv_blend_map+0x3c2> + 6bb2: 2aff cmp r2, #255 ; 0xff + 6bb4: d120 bne.n 6bf8 <_lv_blend_map+0x3fc> + 6bb6: f8ba 3000 ldrh.w r3, [sl] + 6bba: f8a9 3000 strh.w r3, [r9] + MAP_NORMAL_MASK_PX(x + 1) + 6bbe: 787a ldrb r2, [r7, #1] + 6bc0: b12a cbz r2, 6bce <_lv_blend_map+0x3d2> + 6bc2: 2aff cmp r2, #255 ; 0xff + 6bc4: d120 bne.n 6c08 <_lv_blend_map+0x40c> + 6bc6: f8ba 3002 ldrh.w r3, [sl, #2] + 6bca: f8a9 3002 strh.w r3, [r9, #2] + MAP_NORMAL_MASK_PX(x + 2) + 6bce: 78ba ldrb r2, [r7, #2] + 6bd0: b12a cbz r2, 6bde <_lv_blend_map+0x3e2> + 6bd2: 2aff cmp r2, #255 ; 0xff + 6bd4: d120 bne.n 6c18 <_lv_blend_map+0x41c> + 6bd6: f8ba 3004 ldrh.w r3, [sl, #4] + 6bda: f8a9 3004 strh.w r3, [r9, #4] + MAP_NORMAL_MASK_PX(x + 3) + 6bde: 78fa ldrb r2, [r7, #3] + 6be0: 2a00 cmp r2, #0 + 6be2: d0dd beq.n 6ba0 <_lv_blend_map+0x3a4> + 6be4: 2aff cmp r2, #255 ; 0xff + 6be6: d0d7 beq.n 6b98 <_lv_blend_map+0x39c> + 6be8: f8b9 1006 ldrh.w r1, [r9, #6] + 6bec: f8ba 0006 ldrh.w r0, [sl, #6] + 6bf0: 47c0 blx r8 + 6bf2: f8a9 0006 strh.w r0, [r9, #6] + 6bf6: e7d3 b.n 6ba0 <_lv_blend_map+0x3a4> + MAP_NORMAL_MASK_PX(x) + 6bf8: f8b9 1000 ldrh.w r1, [r9] + 6bfc: f8ba 0000 ldrh.w r0, [sl] + 6c00: 47c0 blx r8 + 6c02: f8a9 0000 strh.w r0, [r9] + 6c06: e7da b.n 6bbe <_lv_blend_map+0x3c2> + MAP_NORMAL_MASK_PX(x + 1) + 6c08: f8b9 1002 ldrh.w r1, [r9, #2] + 6c0c: f8ba 0002 ldrh.w r0, [sl, #2] + 6c10: 47c0 blx r8 + 6c12: f8a9 0002 strh.w r0, [r9, #2] + 6c16: e7da b.n 6bce <_lv_blend_map+0x3d2> + MAP_NORMAL_MASK_PX(x + 2) + 6c18: f8b9 1004 ldrh.w r1, [r9, #4] + 6c1c: f8ba 0004 ldrh.w r0, [sl, #4] + 6c20: 47c0 blx r8 + 6c22: f8a9 0004 strh.w r0, [r9, #4] + 6c26: e7da b.n 6bde <_lv_blend_map+0x3e2> + MAP_NORMAL_MASK_PX(x) + 6c28: f817 2f01 ldrb.w r2, [r7, #1]! + 6c2c: b12a cbz r2, 6c3a <_lv_blend_map+0x43e> + 6c2e: 2aff cmp r2, #255 ; 0xff + 6c30: d109 bne.n 6c46 <_lv_blend_map+0x44a> + 6c32: f8ba 3000 ldrh.w r3, [sl] + 6c36: f8a9 3000 strh.w r3, [r9] + for(; x < draw_area_w ; x++) { + 6c3a: 3601 adds r6, #1 + 6c3c: f10a 0a02 add.w sl, sl, #2 + 6c40: f109 0902 add.w r9, r9, #2 + 6c44: e78a b.n 6b5c <_lv_blend_map+0x360> + MAP_NORMAL_MASK_PX(x) + 6c46: f8b9 1000 ldrh.w r1, [r9] + 6c4a: f8ba 0000 ldrh.w r0, [sl] + 6c4e: 47c0 blx r8 + 6c50: f8a9 0000 strh.w r0, [r9] + 6c54: e7f1 b.n 6c3a <_lv_blend_map+0x43e> + if(mask[x]) { + 6c56: 9b06 ldr r3, [sp, #24] + 6c58: 5d9a ldrb r2, [r3, r6] + 6c5a: b172 cbz r2, 6c7a <_lv_blend_map+0x47e> + lv_opa_t opa_tmp = mask[x] >= LV_OPA_MAX ? opa : ((opa * mask[x]) >> 8); + 6c5c: 2af9 cmp r2, #249 ; 0xf9 + 6c5e: bf98 it ls + 6c60: 9b05 ldrls r3, [sp, #20] + disp_buf_first[x] = lv_color_mix(map_buf_first[x], disp_buf_first[x], opa_tmp); + 6c62: f834 1016 ldrh.w r1, [r4, r6, lsl #1] + 6c66: f835 0016 ldrh.w r0, [r5, r6, lsl #1] + 6c6a: bf8e itee hi + 6c6c: 9a05 ldrhi r2, [sp, #20] + lv_opa_t opa_tmp = mask[x] >= LV_OPA_MAX ? opa : ((opa * mask[x]) >> 8); + 6c6e: fb13 f202 smulbbls r2, r3, r2 + 6c72: 0a12 lsrls r2, r2, #8 + disp_buf_first[x] = lv_color_mix(map_buf_first[x], disp_buf_first[x], opa_tmp); + 6c74: 47b8 blx r7 + 6c76: f824 0016 strh.w r0, [r4, r6, lsl #1] + for(x = 0; x < draw_area_w; x++) { + 6c7a: 3601 adds r6, #1 + 6c7c: 9b07 ldr r3, [sp, #28] + 6c7e: 42b3 cmp r3, r6 + 6c80: dce9 bgt.n 6c56 <_lv_blend_map+0x45a> + mask += draw_area_w; + 6c82: e9dd 3206 ldrd r3, r2, [sp, #24] + 6c86: 4413 add r3, r2 + 6c88: 9306 str r3, [sp, #24] + map_buf_first += map_w; + 6c8a: 9b08 ldr r3, [sp, #32] + disp_buf_first += disp_w; + 6c8c: 445c add r4, fp + map_buf_first += map_w; + 6c8e: 441d add r5, r3 + for(y = 0; y < draw_area_h; y++) { + 6c90: f10a 0a01 add.w sl, sl, #1 + 6c94: 9b09 ldr r3, [sp, #36] ; 0x24 + 6c96: 4553 cmp r3, sl + 6c98: f77f ae98 ble.w 69cc <_lv_blend_map+0x1d0> + for(x = 0; x < draw_area_w; x++) { + 6c9c: 2600 movs r6, #0 + 6c9e: e7ed b.n 6c7c <_lv_blend_map+0x480> + disp_buf_first[x] = lv_color_mix(map_buf_first[x], disp_buf_first[x], opa_tmp); + 6ca0: 4f36 ldr r7, [pc, #216] ; (6d7c <_lv_blend_map+0x580>) + 6ca2: e7f7 b.n 6c94 <_lv_blend_map+0x498> + switch(mode) { + 6ca4: f1ba 0f01 cmp.w sl, #1 + 6ca8: d00c beq.n 6cc4 <_lv_blend_map+0x4c8> + 6caa: f1ba 0f02 cmp.w sl, #2 + 6cae: d02b beq.n 6d08 <_lv_blend_map+0x50c> + LV_LOG_WARN("fill_blended: unsupported blend mode"); + 6cb0: 4b33 ldr r3, [pc, #204] ; (6d80 <_lv_blend_map+0x584>) + 6cb2: 9300 str r3, [sp, #0] + 6cb4: 4933 ldr r1, [pc, #204] ; (6d84 <_lv_blend_map+0x588>) + 6cb6: 4b34 ldr r3, [pc, #208] ; (6d88 <_lv_blend_map+0x58c>) + 6cb8: 4c34 ldr r4, [pc, #208] ; (6d8c <_lv_blend_map+0x590>) + 6cba: f240 3253 movw r2, #851 ; 0x353 + 6cbe: 2002 movs r0, #2 + 6cc0: 47a0 blx r4 + return; + 6cc2: e683 b.n 69cc <_lv_blend_map+0x1d0> + blend_fp = color_blend_true_color_additive; + 6cc4: f8df b0c8 ldr.w fp, [pc, #200] ; 6d90 <_lv_blend_map+0x594> + lv_color_t * disp_buf_tmp = disp_buf + disp_w * draw_area->y1; + 6cc8: 9808 ldr r0, [sp, #32] + 6cca: eb00 0444 add.w r4, r0, r4, lsl #1 + const lv_color_t * map_buf_tmp = map_buf + map_w * (draw_area->y1 - (map_area->y1 - disp_area->y1)); + 6cce: 980b ldr r0, [sp, #44] ; 0x2c + 6cd0: eb00 0949 add.w r9, r0, r9, lsl #1 + if(mask_res == LV_DRAW_MASK_RES_FULL_COVER) { + 6cd4: 980a ldr r0, [sp, #40] ; 0x28 + 6cd6: 2801 cmp r0, #1 + disp_buf_first += disp_w; + 6cd8: ea4f 0646 mov.w r6, r6, lsl #1 + map_buf_first += map_w; + 6cdc: ea4f 0747 mov.w r7, r7, lsl #1 + if(mask_res == LV_DRAW_MASK_RES_FULL_COVER) { + 6ce0: d120 bne.n 6d24 <_lv_blend_map+0x528> + map_buf_tmp -= draw_area->x1; + 6ce2: 1a9b subs r3, r3, r2 + 6ce4: eb09 0543 add.w r5, r9, r3, lsl #1 + for(y = draw_area->y1; y <= draw_area->y2; y++) { + 6ce8: f9bd 3036 ldrsh.w r3, [sp, #54] ; 0x36 + 6cec: 4598 cmp r8, r3 + 6cee: f73f ae6d bgt.w 69cc <_lv_blend_map+0x1d0> + for(x = draw_area->x1; x <= draw_area->x2; x++) { + 6cf2: f9bd 9030 ldrsh.w r9, [sp, #48] ; 0x30 + 6cf6: f9bd 3034 ldrsh.w r3, [sp, #52] ; 0x34 + 6cfa: 4599 cmp r9, r3 + 6cfc: dd07 ble.n 6d0e <_lv_blend_map+0x512> + disp_buf_tmp += disp_w; + 6cfe: 4434 add r4, r6 + map_buf_tmp += map_w; + 6d00: 443d add r5, r7 + for(y = draw_area->y1; y <= draw_area->y2; y++) { + 6d02: f108 0801 add.w r8, r8, #1 + 6d06: e7ef b.n 6ce8 <_lv_blend_map+0x4ec> + switch(mode) { + 6d08: f8df b088 ldr.w fp, [pc, #136] ; 6d94 <_lv_blend_map+0x598> + 6d0c: e7dc b.n 6cc8 <_lv_blend_map+0x4cc> + disp_buf_tmp[x] = blend_fp(map_buf_tmp[x], disp_buf_tmp[x], opa); + 6d0e: f834 1019 ldrh.w r1, [r4, r9, lsl #1] + 6d12: f835 0019 ldrh.w r0, [r5, r9, lsl #1] + 6d16: 9a05 ldr r2, [sp, #20] + 6d18: 47d8 blx fp + 6d1a: f824 0019 strh.w r0, [r4, r9, lsl #1] + for(x = draw_area->x1; x <= draw_area->x2; x++) { + 6d1e: f109 0901 add.w r9, r9, #1 + 6d22: e7e8 b.n 6cf6 <_lv_blend_map+0x4fa> + const lv_opa_t * mask_tmp = mask - draw_area->x1; + 6d24: 9b06 ldr r3, [sp, #24] + map_buf_tmp -= draw_area->x1; + 6d26: eba9 0941 sub.w r9, r9, r1, lsl #1 + const lv_opa_t * mask_tmp = mask - draw_area->x1; + 6d2a: 1a5d subs r5, r3, r1 + for(y = draw_area->y1; y <= draw_area->y2; y++) { + 6d2c: f9bd 3036 ldrsh.w r3, [sp, #54] ; 0x36 + 6d30: 4598 cmp r8, r3 + 6d32: f73f ae4b bgt.w 69cc <_lv_blend_map+0x1d0> + for(x = draw_area->x1; x <= draw_area->x2; x++) { + 6d36: f9bd a030 ldrsh.w sl, [sp, #48] ; 0x30 + 6d3a: f9bd 3034 ldrsh.w r3, [sp, #52] ; 0x34 + 6d3e: 459a cmp sl, r3 + 6d40: dd06 ble.n 6d50 <_lv_blend_map+0x554> + mask_tmp += draw_area_w; + 6d42: 9b07 ldr r3, [sp, #28] + disp_buf_tmp += disp_w; + 6d44: 4434 add r4, r6 + mask_tmp += draw_area_w; + 6d46: 441d add r5, r3 + map_buf_tmp += map_w; + 6d48: 44b9 add r9, r7 + for(y = draw_area->y1; y <= draw_area->y2; y++) { + 6d4a: f108 0801 add.w r8, r8, #1 + 6d4e: e7ed b.n 6d2c <_lv_blend_map+0x530> + if(mask_tmp[x] == 0) continue; + 6d50: f815 200a ldrb.w r2, [r5, sl] + 6d54: b172 cbz r2, 6d74 <_lv_blend_map+0x578> + lv_opa_t opa_tmp = mask_tmp[x] >= LV_OPA_MAX ? opa : ((opa * mask_tmp[x]) >> 8); + 6d56: 2af9 cmp r2, #249 ; 0xf9 + 6d58: bf94 ite ls + 6d5a: 9b05 ldrls r3, [sp, #20] + 6d5c: 9a05 ldrhi r2, [sp, #20] + disp_buf_tmp[x] = blend_fp(map_buf_tmp[x], disp_buf_tmp[x], opa_tmp); + 6d5e: f834 101a ldrh.w r1, [r4, sl, lsl #1] + 6d62: f839 001a ldrh.w r0, [r9, sl, lsl #1] + lv_opa_t opa_tmp = mask_tmp[x] >= LV_OPA_MAX ? opa : ((opa * mask_tmp[x]) >> 8); + 6d66: bf9c itt ls + 6d68: fb13 f202 smulbbls r2, r3, r2 + 6d6c: 0a12 lsrls r2, r2, #8 + disp_buf_tmp[x] = blend_fp(map_buf_tmp[x], disp_buf_tmp[x], opa_tmp); + 6d6e: 47d8 blx fp + 6d70: f824 001a strh.w r0, [r4, sl, lsl #1] + for(x = draw_area->x1; x <= draw_area->x2; x++) { + 6d74: f10a 0a01 add.w sl, sl, #1 + 6d78: e7df b.n 6d3a <_lv_blend_map+0x53e> + 6d7a: bf00 nop + 6d7c: 000060a5 .word 0x000060a5 + 6d80: 0001f9d9 .word 0x0001f9d9 + 6d84: 0001f9a3 .word 0x0001f9a3 + 6d88: 0001fa0b .word 0x0001fa0b + 6d8c: 0000e8e9 .word 0x0000e8e9 + 6d90: 000060f5 .word 0x000060f5 + 6d94: 00006175 .word 0x00006175 + +00006d98 : + } + } +} + +static void show_error(const lv_area_t * coords, const lv_area_t * clip_area, const char * msg) +{ + 6d98: b530 push {r4, r5, lr} + 6d9a: b0a1 sub sp, #132 ; 0x84 + 6d9c: 4604 mov r4, r0 + 6d9e: 9203 str r2, [sp, #12] + lv_draw_rect_dsc_t rect_dsc; + lv_draw_rect_dsc_init(&rect_dsc); + 6da0: a80b add r0, sp, #44 ; 0x2c + 6da2: 4a0c ldr r2, [pc, #48] ; (6dd4 ) +{ + 6da4: 9102 str r1, [sp, #8] + lv_draw_rect_dsc_init(&rect_dsc); + 6da6: 4790 blx r2 + rect_dsc.bg_color = LV_COLOR_WHITE; + 6da8: 4a0b ldr r2, [pc, #44] ; (6dd8 ) + lv_draw_rect(coords, clip_area, &rect_dsc); + 6daa: 9902 ldr r1, [sp, #8] + rect_dsc.bg_color = LV_COLOR_WHITE; + 6dac: 8812 ldrh r2, [r2, #0] + 6dae: f8ad 202e strh.w r2, [sp, #46] ; 0x2e + lv_draw_rect(coords, clip_area, &rect_dsc); + 6db2: 4620 mov r0, r4 + 6db4: aa0b add r2, sp, #44 ; 0x2c + 6db6: 4d09 ldr r5, [pc, #36] ; (6ddc ) + 6db8: 47a8 blx r5 + + lv_draw_label_dsc_t label_dsc; + lv_draw_label_dsc_init(&label_dsc); + 6dba: a804 add r0, sp, #16 + 6dbc: 4a08 ldr r2, [pc, #32] ; (6de0 ) + 6dbe: 4790 blx r2 + lv_draw_label(coords, clip_area, &label_dsc, msg, NULL); + 6dc0: 2200 movs r2, #0 + 6dc2: 9200 str r2, [sp, #0] + 6dc4: 4620 mov r0, r4 + 6dc6: 9b03 ldr r3, [sp, #12] + 6dc8: 9902 ldr r1, [sp, #8] + 6dca: 4c06 ldr r4, [pc, #24] ; (6de4 ) + 6dcc: aa04 add r2, sp, #16 + 6dce: 47a0 blx r4 +} + 6dd0: b021 add sp, #132 ; 0x84 + 6dd2: bd30 pop {r4, r5, pc} + 6dd4: 00009ba1 .word 0x00009ba1 + 6dd8: 0001fa9c .word 0x0001fa9c + 6ddc: 00009bed .word 0x00009bed + 6de0: 00007845 .word 0x00007845 + 6de4: 00007875 .word 0x00007875 + +00006de8 : +LV_ATTRIBUTE_FAST_MEM static inline void * _lv_memcpy_small(void * dst, const void * src, size_t len) +{ + uint8_t * d8 = (uint8_t *)dst; + const uint8_t * s8 = (const uint8_t *)src; + + while(len) { + 6de8: 3901 subs r1, #1 + 6dea: f100 0308 add.w r3, r0, #8 + *d8 = *s8; + 6dee: f811 2f01 ldrb.w r2, [r1, #1]! + 6df2: f800 2b01 strb.w r2, [r0], #1 + while(len) { + 6df6: 4298 cmp r0, r3 + 6df8: d1f9 bne.n 6dee +} + 6dfa: 4770 bx lr + +00006dfc : +{ + 6dfc: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 6e00: ed2d 8b02 vpush {d8} + 6e04: b0b9 sub sp, #228 ; 0xe4 + 6e06: 461c mov r4, r3 + 6e08: f89d 3110 ldrb.w r3, [sp, #272] ; 0x110 + 6e0c: 930c str r3, [sp, #48] ; 0x30 + 6e0e: f89d 3114 ldrb.w r3, [sp, #276] ; 0x114 + 6e12: 9307 str r3, [sp, #28] + 6e14: 4682 mov sl, r0 + lv_area_copy(&draw_area, clip_area); + 6e16: 4b9c ldr r3, [pc, #624] ; (7088 ) + 6e18: a822 add r0, sp, #136 ; 0x88 +{ + 6e1a: 4689 mov r9, r1 + 6e1c: 4615 mov r5, r2 + lv_area_copy(&draw_area, clip_area); + 6e1e: 4798 blx r3 + lv_disp_t * disp = _lv_refr_get_disp_refreshing(); + 6e20: 4b9a ldr r3, [pc, #616] ; (708c ) + 6e22: 4798 blx r3 + lv_disp_buf_t * vdb = lv_disp_get_buf(disp); + 6e24: 4b9a ldr r3, [pc, #616] ; (7090 ) + 6e26: 4798 blx r3 + draw_area.x1 -= disp_area->x1; + 6e28: f8bd 3088 ldrh.w r3, [sp, #136] ; 0x88 + 6e2c: 8a01 ldrh r1, [r0, #16] + draw_area.y1 -= disp_area->y1; + 6e2e: 8a42 ldrh r2, [r0, #18] + lv_disp_buf_t * vdb = lv_disp_get_buf(disp); + 6e30: 9004 str r0, [sp, #16] + draw_area.x1 -= disp_area->x1; + 6e32: 1a5b subs r3, r3, r1 + 6e34: f8ad 3088 strh.w r3, [sp, #136] ; 0x88 + draw_area.y1 -= disp_area->y1; + 6e38: f8bd 308a ldrh.w r3, [sp, #138] ; 0x8a + 6e3c: 1a9b subs r3, r3, r2 + 6e3e: f8ad 308a strh.w r3, [sp, #138] ; 0x8a + draw_area.x2 -= disp_area->x1; + 6e42: f8bd 308c ldrh.w r3, [sp, #140] ; 0x8c + 6e46: 1a5b subs r3, r3, r1 + 6e48: f8ad 308c strh.w r3, [sp, #140] ; 0x8c + draw_area.y2 -= disp_area->y1; + 6e4c: f8bd 308e ldrh.w r3, [sp, #142] ; 0x8e + 6e50: 1a9b subs r3, r3, r2 + 6e52: f8ad 308e strh.w r3, [sp, #142] ; 0x8e + uint8_t other_mask_cnt = lv_draw_mask_get_cnt(); + 6e56: 4b8f ldr r3, [pc, #572] ; (7094 ) + 6e58: 4798 blx r3 + if(other_mask_cnt == 0 && draw_dsc->angle == 0 && draw_dsc->zoom == LV_IMG_ZOOM_NONE && + 6e5a: 900b str r0, [sp, #44] ; 0x2c + 6e5c: b9f8 cbnz r0, 6e9e + 6e5e: 8863 ldrh r3, [r4, #2] + 6e60: b9eb cbnz r3, 6e9e + 6e62: 8923 ldrh r3, [r4, #8] + 6e64: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 6e68: d119 bne.n 6e9e + 6e6a: 9b0c ldr r3, [sp, #48] ; 0x30 + 6e6c: b9bb cbnz r3, 6e9e + chroma_key == false && alpha_byte == false && draw_dsc->recolor_opa == LV_OPA_TRANSP) { + 6e6e: 9b07 ldr r3, [sp, #28] + 6e70: 2b00 cmp r3, #0 + 6e72: f040 8099 bne.w 6fa8 + 6e76: 7aa3 ldrb r3, [r4, #10] + 6e78: 2b00 cmp r3, #0 + 6e7a: f040 8097 bne.w 6fac + _lv_blend_map(clip_area, map_area, (lv_color_t *)map_p, NULL, LV_DRAW_MASK_RES_FULL_COVER, draw_dsc->opa, + 6e7e: 7ba2 ldrb r2, [r4, #14] + 6e80: 9202 str r2, [sp, #8] + 6e82: 7822 ldrb r2, [r4, #0] + 6e84: 9201 str r2, [sp, #4] + 6e86: 2201 movs r2, #1 + 6e88: 9200 str r2, [sp, #0] + 6e8a: 4c83 ldr r4, [pc, #524] ; (7098 ) + 6e8c: 462a mov r2, r5 + 6e8e: 4651 mov r1, sl + 6e90: 4648 mov r0, r9 + 6e92: 47a0 blx r4 +} + 6e94: b039 add sp, #228 ; 0xe4 + 6e96: ecbd 8b02 vpop {d8} + 6e9a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + uint8_t px_size_byte = alpha_byte ? LV_IMG_PX_SIZE_ALPHA_BYTE : sizeof(lv_color_t); + 6e9e: 9b07 ldr r3, [sp, #28] + 6ea0: 3302 adds r3, #2 + 6ea2: b2db uxtb r3, r3 + 6ea4: 9305 str r3, [sp, #20] + map_buf_tmp += map_w * (draw_area.y1 - (map_area->y1 - disp_area->y1)) * px_size_byte; + 6ea6: 9b04 ldr r3, [sp, #16] + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + 6ea8: f8ba 8004 ldrh.w r8, [sl, #4] + 6eac: f9b3 1012 ldrsh.w r1, [r3, #18] + 6eb0: f9ba 2000 ldrsh.w r2, [sl] + map_buf_tmp += (draw_area.x1 - (map_area->x1 - disp_area->x1)) * px_size_byte; + 6eb4: f9b3 3010 ldrsh.w r3, [r3, #16] + map_buf_tmp += map_w * (draw_area.y1 - (map_area->y1 - disp_area->y1)) * px_size_byte; + 6eb8: f9ba 7002 ldrsh.w r7, [sl, #2] + map_buf_tmp += (draw_area.x1 - (map_area->x1 - disp_area->x1)) * px_size_byte; + 6ebc: f9bd 6088 ldrsh.w r6, [sp, #136] ; 0x88 + map_buf_tmp += map_w * (draw_area.y1 - (map_area->y1 - disp_area->y1)) * px_size_byte; + 6ec0: f9bd 008a ldrsh.w r0, [sp, #138] ; 0x8a + 6ec4: f108 0801 add.w r8, r8, #1 + 6ec8: eba8 0802 sub.w r8, r8, r2 + 6ecc: 1a7f subs r7, r7, r1 + map_buf_tmp += (draw_area.x1 - (map_area->x1 - disp_area->x1)) * px_size_byte; + 6ece: 1ad2 subs r2, r2, r3 + map_buf_tmp += map_w * (draw_area.y1 - (map_area->y1 - disp_area->y1)) * px_size_byte; + 6ed0: 1bc7 subs r7, r0, r7 + map_buf_tmp += (draw_area.x1 - (map_area->x1 - disp_area->x1)) * px_size_byte; + 6ed2: 1ab2 subs r2, r6, r2 + 6ed4: fa0f f888 sxth.w r8, r8 + 6ed8: fb08 2207 mla r2, r8, r7, r2 + 6edc: 9f05 ldr r7, [sp, #20] + 6ede: fb02 5207 mla r2, r2, r7, r5 + 6ee2: 9208 str r2, [sp, #32] + 6ee4: f8bd 208c ldrh.w r2, [sp, #140] ; 0x8c + 6ee8: 3201 adds r2, #1 + 6eea: 1b92 subs r2, r2, r6 + blend_area.x1 = draw_area.x1 + disp_area->x1; + 6eec: fa13 f386 uxtah r3, r3, r6 + 6ef0: b296 uxth r6, r2 + 6ef2: b212 sxth r2, r2 + 6ef4: b29b uxth r3, r3 + 6ef6: 9211 str r2, [sp, #68] ; 0x44 + blend_area.x2 = blend_area.x1 + lv_area_get_width(&draw_area) - 1; + 6ef8: 1e72 subs r2, r6, #1 + blend_area.x1 = draw_area.x1 + disp_area->x1; + 6efa: f8ad 3090 strh.w r3, [sp, #144] ; 0x90 + blend_area.x2 = blend_area.x1 + lv_area_get_width(&draw_area) - 1; + 6efe: 4413 add r3, r2 + 6f00: f8ad 3094 strh.w r3, [sp, #148] ; 0x94 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + 6f04: f8bd 308e ldrh.w r3, [sp, #142] ; 0x8e + 6f08: 3301 adds r3, #1 + 6f0a: 1a1b subs r3, r3, r0 + 6f0c: b21b sxth r3, r3 + blend_area.y1 = disp_area->y1 + draw_area.y1; + 6f0e: fa11 f180 uxtah r1, r1, r0 + 6f12: 9317 str r3, [sp, #92] ; 0x5c + bool transform = draw_dsc->angle != 0 || draw_dsc->zoom != LV_IMG_ZOOM_NONE ? true : false; + 6f14: 8863 ldrh r3, [r4, #2] + blend_area.y1 = disp_area->y1 + draw_area.y1; + 6f16: b209 sxth r1, r1 + 6f18: f8ad 1092 strh.w r1, [sp, #146] ; 0x92 + blend_area.y2 = blend_area.y1; + 6f1c: f8ad 1096 strh.w r1, [sp, #150] ; 0x96 + bool transform = draw_dsc->angle != 0 || draw_dsc->zoom != LV_IMG_ZOOM_NONE ? true : false; + 6f20: 2b00 cmp r3, #0 + 6f22: f040 8264 bne.w 73ee + 6f26: 8923 ldrh r3, [r4, #8] + 6f28: f5b3 7280 subs.w r2, r3, #256 ; 0x100 + 6f2c: bf18 it ne + 6f2e: 2201 movne r2, #1 + 6f30: 9215 str r2, [sp, #84] ; 0x54 + if(other_mask_cnt == 0 && !transform && !chroma_key && draw_dsc->recolor_opa == LV_OPA_TRANSP && alpha_byte) { + 6f32: 9a0b ldr r2, [sp, #44] ; 0x2c + 6f34: 2a00 cmp r2, #0 + 6f36: f040 825c bne.w 73f2 + 6f3a: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 6f3e: f040 8258 bne.w 73f2 + 6f42: 9b0c ldr r3, [sp, #48] ; 0x30 + 6f44: 2b00 cmp r3, #0 + 6f46: f040 8254 bne.w 73f2 + 6f4a: 7aa3 ldrb r3, [r4, #10] + 6f4c: 2b00 cmp r3, #0 + 6f4e: f040 8250 bne.w 73f2 + 6f52: 9b07 ldr r3, [sp, #28] + 6f54: 2b00 cmp r3, #0 + 6f56: f000 824c beq.w 73f2 + uint32_t mask_buf_size = lv_area_get_size(&draw_area) > LV_HOR_RES_MAX ? LV_HOR_RES_MAX : lv_area_get_size(&draw_area); + 6f5a: 4d50 ldr r5, [pc, #320] ; (709c ) + 6f5c: a822 add r0, sp, #136 ; 0x88 + 6f5e: 47a8 blx r5 + 6f60: f5b0 7ff0 cmp.w r0, #480 ; 0x1e0 + 6f64: d824 bhi.n 6fb0 + 6f66: a822 add r0, sp, #136 ; 0x88 + 6f68: 47a8 blx r5 + 6f6a: 4607 mov r7, r0 + lv_color_t * map2 = _lv_mem_buf_get(mask_buf_size * sizeof(lv_color_t)); + 6f6c: 4e4c ldr r6, [pc, #304] ; (70a0 ) + 6f6e: 0078 lsls r0, r7, #1 + 6f70: 47b0 blx r6 + 6f72: ee08 0a10 vmov s16, r0 + lv_opa_t * mask_buf = _lv_mem_buf_get(mask_buf_size); + 6f76: 4638 mov r0, r7 + 6f78: 47b0 blx r6 + map_buf_tmp += map_w * px_size_byte; + 6f7a: 9b05 ldr r3, [sp, #20] + 6f7c: 9a11 ldr r2, [sp, #68] ; 0x44 + 6f7e: fb13 fa08 smulbb sl, r3, r8 + 6f82: ea22 72e2 bic.w r2, r2, r2, asr #31 + for(y = 0; y < draw_area_h; y++) { + 6f86: f04f 0800 mov.w r8, #0 + lv_opa_t * mask_buf = _lv_mem_buf_get(mask_buf_size); + 6f8a: 4606 mov r6, r0 + uint32_t px_i = 0; + 6f8c: 4643 mov r3, r8 + 6f8e: 9204 str r2, [sp, #16] + for(y = 0; y < draw_area_h; y++) { + 6f90: 9a17 ldr r2, [sp, #92] ; 0x5c + 6f92: 4542 cmp r2, r8 + 6f94: dd4d ble.n 7032 + 6f96: ee18 2a10 vmov r2, s16 + 6f9a: eb06 0c03 add.w ip, r6, r3 + 6f9e: eb02 0e43 add.w lr, r2, r3, lsl #1 + for(x = 0; x < draw_area_w; x++, map_px += px_size_byte, px_i++) { + 6fa2: 2100 movs r1, #0 + map_px = map_buf_tmp; + 6fa4: 9a08 ldr r2, [sp, #32] + 6fa6: e014 b.n 6fd2 + uint8_t px_size_byte = alpha_byte ? LV_IMG_PX_SIZE_ALPHA_BYTE : sizeof(lv_color_t); + 6fa8: 2303 movs r3, #3 + 6faa: e77b b.n 6ea4 + 6fac: 2302 movs r3, #2 + 6fae: e779 b.n 6ea4 + uint32_t mask_buf_size = lv_area_get_size(&draw_area) > LV_HOR_RES_MAX ? LV_HOR_RES_MAX : lv_area_get_size(&draw_area); + 6fb0: f44f 77f0 mov.w r7, #480 ; 0x1e0 + 6fb4: e7da b.n 6f6c + lv_opa_t px_opa = map_px[LV_IMG_PX_SIZE_ALPHA_BYTE - 1]; + 6fb6: 7890 ldrb r0, [r2, #2] + mask_buf[px_i] = px_opa; + 6fb8: f80c 0b01 strb.w r0, [ip], #1 + if(px_opa) { + 6fbc: b130 cbz r0, 6fcc + map2[px_i].full = map_px[0] + (map_px[1] << 8); + 6fbe: f892 b001 ldrb.w fp, [r2, #1] + 6fc2: 7810 ldrb r0, [r2, #0] + 6fc4: eb00 200b add.w r0, r0, fp, lsl #8 + 6fc8: f82e 0011 strh.w r0, [lr, r1, lsl #1] + for(x = 0; x < draw_area_w; x++, map_px += px_size_byte, px_i++) { + 6fcc: 9805 ldr r0, [sp, #20] + 6fce: 3101 adds r1, #1 + 6fd0: 4402 add r2, r0 + 6fd2: 9811 ldr r0, [sp, #68] ; 0x44 + 6fd4: 4288 cmp r0, r1 + 6fd6: dcee bgt.n 6fb6 + 6fd8: 9a04 ldr r2, [sp, #16] + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + 6fda: f8bd 1088 ldrh.w r1, [sp, #136] ; 0x88 + 6fde: 4413 add r3, r2 + map_buf_tmp += map_w * px_size_byte; + 6fe0: 9a08 ldr r2, [sp, #32] + 6fe2: 4452 add r2, sl + 6fe4: 9208 str r2, [sp, #32] + 6fe6: f8bd 208c ldrh.w r2, [sp, #140] ; 0x8c + 6fea: 3201 adds r2, #1 + 6fec: 1a52 subs r2, r2, r1 + if(px_i + lv_area_get_width(&draw_area) < mask_buf_size) { + 6fee: fa03 f282 sxtah r2, r3, r2 + 6ff2: 42ba cmp r2, r7 + 6ff4: d208 bcs.n 7008 + blend_area.y2 ++; + 6ff6: f8bd 2096 ldrh.w r2, [sp, #150] ; 0x96 + 6ffa: 3201 adds r2, #1 + 6ffc: b212 sxth r2, r2 + 6ffe: f8ad 2096 strh.w r2, [sp, #150] ; 0x96 + for(y = 0; y < draw_area_h; y++) { + 7002: f108 0801 add.w r8, r8, #1 + 7006: e7c3 b.n 6f90 + _lv_blend_map(clip_area, &blend_area, map2, mask_buf, LV_DRAW_MASK_RES_CHANGED, draw_dsc->opa, draw_dsc->blend_mode); + 7008: 7ba3 ldrb r3, [r4, #14] + 700a: 9302 str r3, [sp, #8] + 700c: 7823 ldrb r3, [r4, #0] + 700e: 9301 str r3, [sp, #4] + 7010: 2302 movs r3, #2 + 7012: ee18 2a10 vmov r2, s16 + 7016: 9300 str r3, [sp, #0] + 7018: 4d1f ldr r5, [pc, #124] ; (7098 ) + 701a: 4633 mov r3, r6 + 701c: a924 add r1, sp, #144 ; 0x90 + 701e: 4648 mov r0, r9 + 7020: 47a8 blx r5 + blend_area.y1 = blend_area.y2 + 1; + 7022: f8bd 2096 ldrh.w r2, [sp, #150] ; 0x96 + 7026: 3201 adds r2, #1 + 7028: b212 sxth r2, r2 + 702a: f8ad 2092 strh.w r2, [sp, #146] ; 0x92 + px_i = 0; + 702e: 2300 movs r3, #0 + 7030: e7e5 b.n 6ffe + if(blend_area.y1 != blend_area.y2) { + 7032: f9bd 3096 ldrsh.w r3, [sp, #150] ; 0x96 + 7036: f9bd 2092 ldrsh.w r2, [sp, #146] ; 0x92 + 703a: 429a cmp r2, r3 + 703c: d00f beq.n 705e + blend_area.y2--; + 703e: 3b01 subs r3, #1 + 7040: f8ad 3096 strh.w r3, [sp, #150] ; 0x96 + _lv_blend_map(clip_area, &blend_area, map2, mask_buf, LV_DRAW_MASK_RES_CHANGED, draw_dsc->opa, draw_dsc->blend_mode); + 7044: 7ba3 ldrb r3, [r4, #14] + 7046: 9302 str r3, [sp, #8] + 7048: 7823 ldrb r3, [r4, #0] + 704a: 9301 str r3, [sp, #4] + 704c: 2302 movs r3, #2 + 704e: 9300 str r3, [sp, #0] + 7050: ee18 2a10 vmov r2, s16 + 7054: 4c10 ldr r4, [pc, #64] ; (7098 ) + 7056: 4633 mov r3, r6 + 7058: a924 add r1, sp, #144 ; 0x90 + 705a: 4648 mov r0, r9 + 705c: 47a0 blx r4 + _lv_mem_buf_release(mask_buf); + 705e: 4630 mov r0, r6 + _lv_mem_buf_release(mask_buf); + 7060: 4c10 ldr r4, [pc, #64] ; (70a4 ) + 7062: 47a0 blx r4 + _lv_mem_buf_release(map2); + 7064: ee18 0a10 vmov r0, s16 + 7068: 47a0 blx r4 +} + 706a: e713 b.n 6e94 + uint32_t mask_buf_size = lv_area_get_size(&draw_area) > LV_HOR_RES_MAX ? LV_HOR_RES_MAX : lv_area_get_size(&draw_area); + 706c: f44f 73f0 mov.w r3, #480 ; 0x1e0 + 7070: 930a str r3, [sp, #40] ; 0x28 + 7072: e1c8 b.n 7406 + if(alpha_byte) cf = LV_IMG_CF_TRUE_COLOR_ALPHA; + 7074: 2205 movs r2, #5 + 7076: e1de b.n 7436 + uint16_t recolor_premult[3] = {0}; + 7078: 9310 str r3, [sp, #64] ; 0x40 + 707a: 9316 str r3, [sp, #88] ; 0x58 + 707c: 9319 str r3, [sp, #100] ; 0x64 + 707e: e213 b.n 74a8 + mask_res = (alpha_byte || chroma_key || draw_dsc->angle || + 7080: f04f 0b02 mov.w fp, #2 + 7084: e224 b.n 74d0 + 7086: bf00 nop + 7088: 00006de9 .word 0x00006de9 + 708c: 00004fe9 .word 0x00004fe9 + 7090: 0000d9e1 .word 0x0000d9e1 + 7094: 000097f1 .word 0x000097f1 + 7098: 000067fd .word 0x000067fd + 709c: 0000de71 .word 0x0000de71 + 70a0: 0000eeb5 .word 0x0000eeb5 + 70a4: 0000eb69 .word 0x0000eb69 + int32_t rot_x = disp_area->x1 + draw_area.x1 - map_area->x1; + 70a8: 9b04 ldr r3, [sp, #16] + 70aa: f9bd 2088 ldrsh.w r2, [sp, #136] ; 0x88 + 70ae: f9b3 3010 ldrsh.w r3, [r3, #16] + 70b2: 4413 add r3, r2 + 70b4: f9ba 2000 ldrsh.w r2, [sl] + 70b8: 1a9b subs r3, r3, r2 + 70ba: 931b str r3, [sp, #108] ; 0x6c + for(x = 0; x < draw_area_w; x++, map_px += px_size_byte, px_i++) { + 70bc: eb07 0308 add.w r3, r7, r8 + 70c0: ee08 3a90 vmov s17, r3 + 70c4: 9306 str r3, [sp, #24] + 70c6: ee18 3a10 vmov r3, s16 + 70ca: eb03 0348 add.w r3, r3, r8, lsl #1 + 70ce: 931d str r3, [sp, #116] ; 0x74 + map_px = map_buf_tmp; + 70d0: 9b08 ldr r3, [sp, #32] + 70d2: 930d str r3, [sp, #52] ; 0x34 + for(x = 0; x < draw_area_w; x++, map_px += px_size_byte, px_i++) { + 70d4: 2300 movs r3, #0 +{ + const uint8_t * src_u8 = (const uint8_t *)dsc->cfg.src; + + /*Get the target point relative coordinates to the pivot*/ + int32_t xt = x - dsc->cfg.pivot_x; + int32_t yt = y - dsc->cfg.pivot_y; + 70d6: 9a09 ldr r2, [sp, #36] ; 0x24 + 70d8: 930e str r3, [sp, #56] ; 0x38 + 70da: 9b1a ldr r3, [sp, #104] ; 0x68 + 70dc: 4413 add r3, r2 + 70de: b21b sxth r3, r3 + 70e0: 931e str r3, [sp, #120] ; 0x78 + 70e2: 9b11 ldr r3, [sp, #68] ; 0x44 + 70e4: 9a0e ldr r2, [sp, #56] ; 0x38 + 70e6: 4293 cmp r3, r2 + 70e8: dc43 bgt.n 7172 + 70ea: 9b1f ldr r3, [sp, #124] ; 0x7c + 70ec: 4498 add r8, r3 + if(other_mask_cnt) { + 70ee: 9b0b ldr r3, [sp, #44] ; 0x2c + 70f0: b333 cbz r3, 7140 + mask_res_sub = lv_draw_mask_apply(mask_buf + px_i_start, draw_area.x1 + vdb->area.x1, y + draw_area.y1 + vdb->area.y1, + 70f2: 9804 ldr r0, [sp, #16] + 70f4: f8bd 208a ldrh.w r2, [sp, #138] ; 0x8a + 70f8: 8a40 ldrh r0, [r0, #18] + 70fa: f8bd 308c ldrh.w r3, [sp, #140] ; 0x8c + 70fe: f8bd 1088 ldrh.w r1, [sp, #136] ; 0x88 + 7102: 4d9d ldr r5, [pc, #628] ; (7378 ) + 7104: 4402 add r2, r0 + 7106: 9809 ldr r0, [sp, #36] ; 0x24 + 7108: 4402 add r2, r0 + 710a: 9804 ldr r0, [sp, #16] + 710c: 8a00 ldrh r0, [r0, #16] + 710e: 3301 adds r3, #1 + 7110: 1a5b subs r3, r3, r1 + 7112: 4401 add r1, r0 + 7114: b21b sxth r3, r3 + 7116: ee18 0a90 vmov r0, s17 + 711a: b212 sxth r2, r2 + 711c: b209 sxth r1, r1 + 711e: 47a8 blx r5 + if(mask_res_sub == LV_DRAW_MASK_RES_TRANSP) { + 7120: 2800 cmp r0, #0 + 7122: f040 8123 bne.w 736c + 7126: f8bd 108c ldrh.w r1, [sp, #140] ; 0x8c + 712a: f8bd 3088 ldrh.w r3, [sp, #136] ; 0x88 + 712e: 3101 adds r1, #1 + 7130: 1ac9 subs r1, r1, r3 + _lv_memset_00(mask_buf + px_i_start, lv_area_get_width(&draw_area)); + 7132: ee18 0a90 vmov r0, s17 + 7136: 4b91 ldr r3, [pc, #580] ; (737c ) + 7138: b209 sxth r1, r1 + 713a: 4798 blx r3 + mask_res = LV_DRAW_MASK_RES_CHANGED; + 713c: f04f 0b02 mov.w fp, #2 + map_buf_tmp += map_w * px_size_byte; + 7140: 9b08 ldr r3, [sp, #32] + 7142: 9a1c ldr r2, [sp, #112] ; 0x70 + 7144: 4413 add r3, r2 + 7146: 9308 str r3, [sp, #32] + 7148: f8bd 308c ldrh.w r3, [sp, #140] ; 0x8c + 714c: f8bd 2088 ldrh.w r2, [sp, #136] ; 0x88 + 7150: 3301 adds r3, #1 + 7152: 1a9b subs r3, r3, r2 + if(px_i + lv_area_get_width(&draw_area) < mask_buf_size) { + 7154: 9a0a ldr r2, [sp, #40] ; 0x28 + 7156: fa08 f383 sxtah r3, r8, r3 + 715a: 4293 cmp r3, r2 + 715c: f080 8116 bcs.w 738c + blend_area.y2 ++; + 7160: f8bd 3096 ldrh.w r3, [sp, #150] ; 0x96 + 7164: 3301 adds r3, #1 + 7166: f8ad 3096 strh.w r3, [sp, #150] ; 0x96 + for(y = 0; y < draw_area_h; y++) { + 716a: 9b09 ldr r3, [sp, #36] ; 0x24 + 716c: 3301 adds r3, #1 + 716e: 9309 str r3, [sp, #36] ; 0x24 + 7170: e1c9 b.n 7506 + if(transform) { + 7172: 9b15 ldr r3, [sp, #84] ; 0x54 + 7174: 2b00 cmp r3, #0 + 7176: f000 80d7 beq.w 7328 + int32_t xt = x - dsc->cfg.pivot_x; + 717a: 9a0e ldr r2, [sp, #56] ; 0x38 + 717c: 9b1b ldr r3, [sp, #108] ; 0x6c + int32_t yt = y - dsc->cfg.pivot_y; + 717e: 991e ldr r1, [sp, #120] ; 0x78 + const uint8_t * src_u8 = (const uint8_t *)dsc->cfg.src; + 7180: 9826 ldr r0, [sp, #152] ; 0x98 + int32_t xt = x - dsc->cfg.pivot_x; + 7182: 4413 add r3, r2 + 7184: f9bd 20a0 ldrsh.w r2, [sp, #160] ; 0xa0 + 7188: b21b sxth r3, r3 + 718a: 1a9b subs r3, r3, r2 + int32_t yt = y - dsc->cfg.pivot_y; + 718c: f9bd 20a2 ldrsh.w r2, [sp, #162] ; 0xa2 + 7190: 1a8a subs r2, r1, r2 + + int32_t xs; + int32_t ys; + if(dsc->cfg.zoom == LV_IMG_ZOOM_NONE) { + 7192: f8bd 10a6 ldrh.w r1, [sp, #166] ; 0xa6 + 7196: f5b1 7f80 cmp.w r1, #256 ; 0x100 + /*Get the source pixel from the upscaled image*/ + xs = ((dsc->tmp.cosma * xt - dsc->tmp.sinma * yt) >> (LV_TRIGO_SHIFT - 8)) + dsc->tmp.pivot_x_256; + ys = ((dsc->tmp.sinma * xt + dsc->tmp.cosma * yt) >> (LV_TRIGO_SHIFT - 8)) + dsc->tmp.pivot_y_256; + 719a: e9dd 652f ldrd r6, r5, [sp, #188] ; 0xbc + if(dsc->cfg.zoom == LV_IMG_ZOOM_NONE) { + 719e: d119 bne.n 71d4 + xs = ((dsc->tmp.cosma * xt - dsc->tmp.sinma * yt) >> (LV_TRIGO_SHIFT - 8)) + dsc->tmp.pivot_x_256; + 71a0: e9dd e131 ldrd lr, r1, [sp, #196] ; 0xc4 + 71a4: fb01 fc03 mul.w ip, r1, r3 + ys = ((dsc->tmp.sinma * xt + dsc->tmp.cosma * yt) >> (LV_TRIGO_SHIFT - 8)) + dsc->tmp.pivot_y_256; + 71a8: 4351 muls r1, r2 + xs = ((dsc->tmp.cosma * xt - dsc->tmp.sinma * yt) >> (LV_TRIGO_SHIFT - 8)) + dsc->tmp.pivot_x_256; + 71aa: fb0e cc12 mls ip, lr, r2, ip + ys = ((dsc->tmp.sinma * xt + dsc->tmp.cosma * yt) >> (LV_TRIGO_SHIFT - 8)) + dsc->tmp.pivot_y_256; + 71ae: fb0e 1103 mla r1, lr, r3, r1 + xs = ((dsc->tmp.cosma * xt - dsc->tmp.sinma * yt) >> (LV_TRIGO_SHIFT - 8)) + dsc->tmp.pivot_x_256; + 71b2: eb06 16ec add.w r6, r6, ip, asr #7 + ys = ((dsc->tmp.sinma * xt + dsc->tmp.cosma * yt) >> (LV_TRIGO_SHIFT - 8)) + dsc->tmp.pivot_y_256; + 71b6: eb05 13e1 add.w r3, r5, r1, asr #7 + + /*Get the integer part of the source pixel*/ + int32_t xs_int = xs >> 8; + int32_t ys_int = ys >> 8; + + if(xs_int >= dsc->cfg.src_w) return false; + 71ba: f9bd 209c ldrsh.w r2, [sp, #156] ; 0x9c + ys = ((dsc->tmp.sinma * xt + dsc->tmp.cosma * yt) >> (LV_TRIGO_SHIFT)) + dsc->tmp.pivot_y_256; + 71be: 930f str r3, [sp, #60] ; 0x3c + if(xs_int >= dsc->cfg.src_w) return false; + 71c0: ebb2 2f26 cmp.w r2, r6, asr #8 + int32_t xs_int = xs >> 8; + 71c4: ea4f 2326 mov.w r3, r6, asr #8 + 71c8: 9318 str r3, [sp, #96] ; 0x60 + if(xs_int >= dsc->cfg.src_w) return false; + 71ca: dc1b bgt.n 7204 + mask_buf[px_i] = LV_OPA_TRANSP; + 71cc: 9a06 ldr r2, [sp, #24] + 71ce: 2300 movs r3, #0 + 71d0: 7013 strb r3, [r2, #0] + continue; + 71d2: e0b0 b.n 7336 + xt *= dsc->tmp.zoom_inv; + 71d4: f8bd 10ce ldrh.w r1, [sp, #206] ; 0xce + 71d8: 434b muls r3, r1 + yt *= dsc->tmp.zoom_inv; + 71da: 434a muls r2, r1 + else if(dsc->cfg.angle == 0) { + 71dc: f9bd 10a4 ldrsh.w r1, [sp, #164] ; 0xa4 + 71e0: b911 cbnz r1, 71e8 + xs = xt + dsc->tmp.pivot_x_256; + 71e2: 441e add r6, r3 + ys = yt + dsc->tmp.pivot_y_256; + 71e4: 18ab adds r3, r5, r2 + 71e6: e7e8 b.n 71ba + xs = ((dsc->tmp.cosma * xt - dsc->tmp.sinma * yt) >> (LV_TRIGO_SHIFT)) + dsc->tmp.pivot_x_256; + 71e8: e9dd e131 ldrd lr, r1, [sp, #196] ; 0xc4 + 71ec: fb03 fc01 mul.w ip, r3, r1 + ys = ((dsc->tmp.sinma * xt + dsc->tmp.cosma * yt) >> (LV_TRIGO_SHIFT)) + dsc->tmp.pivot_y_256; + 71f0: 4351 muls r1, r2 + xs = ((dsc->tmp.cosma * xt - dsc->tmp.sinma * yt) >> (LV_TRIGO_SHIFT)) + dsc->tmp.pivot_x_256; + 71f2: fb02 cc1e mls ip, r2, lr, ip + ys = ((dsc->tmp.sinma * xt + dsc->tmp.cosma * yt) >> (LV_TRIGO_SHIFT)) + dsc->tmp.pivot_y_256; + 71f6: fb03 110e mla r1, r3, lr, r1 + xs = ((dsc->tmp.cosma * xt - dsc->tmp.sinma * yt) >> (LV_TRIGO_SHIFT)) + dsc->tmp.pivot_x_256; + 71fa: eb06 36ec add.w r6, r6, ip, asr #15 + ys = ((dsc->tmp.sinma * xt + dsc->tmp.cosma * yt) >> (LV_TRIGO_SHIFT)) + dsc->tmp.pivot_y_256; + 71fe: eb05 33e1 add.w r3, r5, r1, asr #15 + 7202: e7da b.n 71ba + else if(xs_int < 0) return false; + 7204: 1233 asrs r3, r6, #8 + 7206: 2b00 cmp r3, #0 + 7208: dbe0 blt.n 71cc + int32_t ys_int = ys >> 8; + 720a: 9b0f ldr r3, [sp, #60] ; 0x3c + + if(ys_int >= dsc->cfg.src_h) return false; + 720c: 990f ldr r1, [sp, #60] ; 0x3c + int32_t ys_int = ys >> 8; + 720e: 121b asrs r3, r3, #8 + 7210: 9312 str r3, [sp, #72] ; 0x48 + if(ys_int >= dsc->cfg.src_h) return false; + 7212: f9bd 309e ldrsh.w r3, [sp, #158] ; 0x9e + 7216: ebb3 2f21 cmp.w r3, r1, asr #8 + 721a: ddd7 ble.n 71cc + else if(ys_int < 0) return false; + 721c: 9b12 ldr r3, [sp, #72] ; 0x48 + 721e: 2b00 cmp r3, #0 + 7220: dbd4 blt.n 71cc + + uint8_t px_size; + uint32_t pxi; + if(dsc->tmp.native_color) { + 7222: f89d 50cc ldrb.w r5, [sp, #204] ; 0xcc + 7226: f015 0104 ands.w r1, r5, #4 + 722a: 9113 str r1, [sp, #76] ; 0x4c + 722c: d066 beq.n 72fc + if(dsc->tmp.has_alpha == 0) { + 722e: 1231 asrs r1, r6, #8 + 7230: fb02 1203 mla r2, r2, r3, r1 + 7234: f015 0f02 tst.w r5, #2 + 7238: ea4f 0342 mov.w r3, r2, lsl #1 + 723c: d151 bne.n 72e2 + *d8 = *s8; + 723e: f810 2012 ldrb.w r2, [r0, r2, lsl #1] + 7242: f88d 20ac strb.w r2, [sp, #172] ; 0xac + px_size = LV_COLOR_SIZE >> 3; + + pxi = dsc->cfg.src_w * ys_int * px_size + xs_int * px_size; + _lv_memcpy_small(&dsc->res.color, &src_u8[pxi], px_size); + 7246: 18c1 adds r1, r0, r3 + 7248: 784a ldrb r2, [r1, #1] + 724a: f88d 20ad strb.w r2, [sp, #173] ; 0xad + px_size = LV_COLOR_SIZE >> 3; + 724e: 2202 movs r2, #2 + } + else { + px_size = LV_IMG_PX_SIZE_ALPHA_BYTE; + 7250: 9213 str r2, [sp, #76] ; 0x4c + px_size = 0; /*unused*/ + dsc->res.color = lv_img_buf_get_px_color(&dsc->tmp.img_dsc, xs_int, ys_int, dsc->cfg.color); + dsc->res.opa = lv_img_buf_get_px_alpha(&dsc->tmp.img_dsc, xs_int, ys_int); + } + + if(dsc->tmp.chroma_keyed) { + 7252: f89d 20cc ldrb.w r2, [sp, #204] ; 0xcc + 7256: 07d2 lsls r2, r2, #31 + 7258: d504 bpl.n 7264 + lv_color_t ct = LV_COLOR_TRANSP; + if(dsc->res.color.full == ct.full) return false; + 725a: f8bd 20ac ldrh.w r2, [sp, #172] ; 0xac + 725e: f5b2 6ffc cmp.w r2, #2016 ; 0x7e0 + 7262: d0b3 beq.n 71cc + } + + if(dsc->cfg.antialias == false) return true; + 7264: f89d 20ab ldrb.w r2, [sp, #171] ; 0xab + 7268: b19a cbz r2, 7292 + + dsc->tmp.xs = xs; + dsc->tmp.ys = ys; + 726a: 9a0f ldr r2, [sp, #60] ; 0x3c + 726c: f8ad 20d2 strh.w r2, [sp, #210] ; 0xd2 + dsc->tmp.xs_int = xs_int; + dsc->tmp.ys_int = ys_int; + dsc->tmp.pxi = pxi; + 7270: 9336 str r3, [sp, #216] ; 0xd8 + dsc->tmp.xs_int = xs_int; + 7272: 9a18 ldr r2, [sp, #96] ; 0x60 + dsc->tmp.px_size = px_size; + 7274: 9b13 ldr r3, [sp, #76] ; 0x4c + dsc->tmp.xs_int = xs_int; + 7276: f8ad 20d4 strh.w r2, [sp, #212] ; 0xd4 + dsc->tmp.px_size = px_size; + 727a: f88d 30dc strb.w r3, [sp, #220] ; 0xdc + dsc->tmp.ys_int = ys_int; + 727e: 9a12 ldr r2, [sp, #72] ; 0x48 + + bool ret; + ret = _lv_img_buf_transform_anti_alias(dsc); + 7280: 4b3f ldr r3, [pc, #252] ; (7380 ) + dsc->tmp.xs = xs; + 7282: f8ad 60d0 strh.w r6, [sp, #208] ; 0xd0 + ret = _lv_img_buf_transform_anti_alias(dsc); + 7286: a826 add r0, sp, #152 ; 0x98 + dsc->tmp.ys_int = ys_int; + 7288: f8ad 20d6 strh.w r2, [sp, #214] ; 0xd6 + ret = _lv_img_buf_transform_anti_alias(dsc); + 728c: 4798 blx r3 + if(ret == false) { + 728e: 2800 cmp r0, #0 + 7290: d09c beq.n 71cc + mask_buf[px_i] = trans_dsc.res.opa; + 7292: 9a06 ldr r2, [sp, #24] + 7294: f89d 30ae ldrb.w r3, [sp, #174] ; 0xae + 7298: 7013 strb r3, [r2, #0] + c.full = trans_dsc.res.color.full; + 729a: f8bd 30ac ldrh.w r3, [sp, #172] ; 0xac + if(draw_dsc->recolor_opa != 0) { + 729e: 7aa2 ldrb r2, [r4, #10] + 72a0: b1d2 cbz r2, 72d8 + LV_COLOR_SET_G(ret, (uint16_t)((uint16_t) premult_c1[1] + LV_COLOR_GET_G(c2) * mix) >> 8); + 72a2: 9916 ldr r1, [sp, #88] ; 0x58 + 72a4: 9814 ldr r0, [sp, #80] ; 0x50 + LV_COLOR_SET_B(ret, (uint16_t)((uint16_t) premult_c1[2] + LV_COLOR_GET_B(c2) * mix) >> 8); + 72a6: 9d14 ldr r5, [sp, #80] ; 0x50 + LV_COLOR_SET_G(ret, (uint16_t)((uint16_t) premult_c1[1] + LV_COLOR_GET_G(c2) * mix) >> 8); + 72a8: f3c3 1245 ubfx r2, r3, #5, #6 + 72ac: fb02 1200 mla r2, r2, r0, r1 + LV_COLOR_SET_B(ret, (uint16_t)((uint16_t) premult_c1[2] + LV_COLOR_GET_B(c2) * mix) >> 8); + 72b0: 9810 ldr r0, [sp, #64] ; 0x40 + 72b2: f003 011f and.w r1, r3, #31 + 72b6: 08d2 lsrs r2, r2, #3 + 72b8: fb01 0105 mla r1, r1, r5, r0 + 72bc: f3c1 2104 ubfx r1, r1, #8, #5 + 72c0: f402 62fc and.w r2, r2, #2016 ; 0x7e0 + 72c4: 430a orrs r2, r1 + LV_COLOR_SET_R(ret, (uint16_t)((uint16_t) premult_c1[0] + LV_COLOR_GET_R(c2) * mix) >> 8); + 72c6: 9919 ldr r1, [sp, #100] ; 0x64 + 72c8: 0adb lsrs r3, r3, #11 + 72ca: fb03 1305 mla r3, r3, r5, r1 + 72ce: f3c3 2307 ubfx r3, r3, #8, #8 + 72d2: ea42 23c3 orr.w r3, r2, r3, lsl #11 + 72d6: b29b uxth r3, r3 + map2[px_i].full = c.full; + 72d8: 9a1d ldr r2, [sp, #116] ; 0x74 + 72da: 990e ldr r1, [sp, #56] ; 0x38 + 72dc: f822 3011 strh.w r3, [r2, r1, lsl #1] + 72e0: e029 b.n 7336 + pxi = dsc->cfg.src_w * ys_int * px_size + xs_int * px_size; + 72e2: 4413 add r3, r2 + _lv_memcpy_small(&dsc->res.color, &src_u8[pxi], px_size - 1); + 72e4: 18c2 adds r2, r0, r3 + 72e6: 5cc1 ldrb r1, [r0, r3] + 72e8: f88d 10ac strb.w r1, [sp, #172] ; 0xac + 72ec: 7851 ldrb r1, [r2, #1] + 72ee: f88d 10ad strb.w r1, [sp, #173] ; 0xad + dsc->res.opa = src_u8[pxi + px_size - 1]; + 72f2: 7892 ldrb r2, [r2, #2] + 72f4: f88d 20ae strb.w r2, [sp, #174] ; 0xae + px_size = LV_IMG_PX_SIZE_ALPHA_BYTE; + 72f8: 2203 movs r2, #3 + 72fa: e7a9 b.n 7250 + dsc->res.color = lv_img_buf_get_px_color(&dsc->tmp.img_dsc, xs_int, ys_int, dsc->cfg.color); + 72fc: f9bd 1060 ldrsh.w r1, [sp, #96] ; 0x60 + 7300: f9bd 2048 ldrsh.w r2, [sp, #72] ; 0x48 + 7304: f8bd 30a8 ldrh.w r3, [sp, #168] ; 0xa8 + 7308: 4d1e ldr r5, [pc, #120] ; (7384 ) + 730a: a82c add r0, sp, #176 ; 0xb0 + 730c: e9cd 1220 strd r1, r2, [sp, #128] ; 0x80 + 7310: 47a8 blx r5 + dsc->res.opa = lv_img_buf_get_px_alpha(&dsc->tmp.img_dsc, xs_int, ys_int); + 7312: 4b1d ldr r3, [pc, #116] ; (7388 ) + dsc->res.color = lv_img_buf_get_px_color(&dsc->tmp.img_dsc, xs_int, ys_int, dsc->cfg.color); + 7314: f8ad 00ac strh.w r0, [sp, #172] ; 0xac + dsc->res.opa = lv_img_buf_get_px_alpha(&dsc->tmp.img_dsc, xs_int, ys_int); + 7318: e9dd 1220 ldrd r1, r2, [sp, #128] ; 0x80 + 731c: a82c add r0, sp, #176 ; 0xb0 + 731e: 4798 blx r3 + pxi = 0; /*unused*/ + 7320: 9b13 ldr r3, [sp, #76] ; 0x4c + dsc->res.opa = lv_img_buf_get_px_alpha(&dsc->tmp.img_dsc, xs_int, ys_int); + 7322: f88d 00ae strb.w r0, [sp, #174] ; 0xae + 7326: e794 b.n 7252 + if(alpha_byte) { + 7328: 9b07 ldr r3, [sp, #28] + 732a: b17b cbz r3, 734c + lv_opa_t px_opa = map_px[LV_IMG_PX_SIZE_ALPHA_BYTE - 1]; + 732c: 9b0d ldr r3, [sp, #52] ; 0x34 + mask_buf[px_i] = px_opa; + 732e: 9a06 ldr r2, [sp, #24] + lv_opa_t px_opa = map_px[LV_IMG_PX_SIZE_ALPHA_BYTE - 1]; + 7330: 789b ldrb r3, [r3, #2] + mask_buf[px_i] = px_opa; + 7332: 7013 strb r3, [r2, #0] + if(px_opa == 0) { + 7334: b96b cbnz r3, 7352 + for(x = 0; x < draw_area_w; x++, map_px += px_size_byte, px_i++) { + 7336: 9b0e ldr r3, [sp, #56] ; 0x38 + 7338: 9a05 ldr r2, [sp, #20] + 733a: 3301 adds r3, #1 + 733c: 930e str r3, [sp, #56] ; 0x38 + 733e: 9b0d ldr r3, [sp, #52] ; 0x34 + 7340: 4413 add r3, r2 + 7342: 930d str r3, [sp, #52] ; 0x34 + 7344: 9b06 ldr r3, [sp, #24] + 7346: 3301 adds r3, #1 + 7348: 9306 str r3, [sp, #24] + 734a: e6ca b.n 70e2 + mask_buf[px_i] = 0xFF; + 734c: 9a06 ldr r2, [sp, #24] + 734e: 23ff movs r3, #255 ; 0xff + 7350: 7013 strb r3, [r2, #0] + c.full = map_px[0] + (map_px[1] << 8); + 7352: 9b0d ldr r3, [sp, #52] ; 0x34 + 7354: 785a ldrb r2, [r3, #1] + 7356: 781b ldrb r3, [r3, #0] + 7358: eb03 2302 add.w r3, r3, r2, lsl #8 + if(chroma_key) { + 735c: 9a0c ldr r2, [sp, #48] ; 0x30 + c.full = map_px[0] + (map_px[1] << 8); + 735e: b29b uxth r3, r3 + if(chroma_key) { + 7360: 2a00 cmp r2, #0 + 7362: d09c beq.n 729e + if(c.full == chroma_keyed_color.full) { + 7364: f5b3 6ffc cmp.w r3, #2016 ; 0x7e0 + 7368: d199 bne.n 729e + 736a: e72f b.n 71cc + mask_res = LV_DRAW_MASK_RES_CHANGED; + 736c: 2802 cmp r0, #2 + 736e: bf08 it eq + 7370: f04f 0b02 moveq.w fp, #2 + 7374: e6e4 b.n 7140 + 7376: bf00 nop + 7378: 00009761 .word 0x00009761 + 737c: 0000f019 .word 0x0000f019 + 7380: 0000c1e5 .word 0x0000c1e5 + 7384: 0000bd89 .word 0x0000bd89 + 7388: 0000be79 .word 0x0000be79 + _lv_blend_map(clip_area, &blend_area, map2, mask_buf, mask_res, draw_dsc->opa, draw_dsc->blend_mode); + 738c: 7ba3 ldrb r3, [r4, #14] + 738e: 9302 str r3, [sp, #8] + 7390: 7823 ldrb r3, [r4, #0] + 7392: 4d6b ldr r5, [pc, #428] ; (7540 ) + 7394: e9cd b300 strd fp, r3, [sp] + 7398: ee18 2a10 vmov r2, s16 + 739c: 463b mov r3, r7 + 739e: a924 add r1, sp, #144 ; 0x90 + 73a0: 4648 mov r0, r9 + 73a2: 47a8 blx r5 + blend_area.y1 = blend_area.y2 + 1; + 73a4: f8bd 3096 ldrh.w r3, [sp, #150] ; 0x96 + 73a8: 3301 adds r3, #1 + 73aa: b21b sxth r3, r3 + 73ac: f8ad 3092 strh.w r3, [sp, #146] ; 0x92 + blend_area.y2 = blend_area.y1; + 73b0: f8ad 3096 strh.w r3, [sp, #150] ; 0x96 + mask_res = (alpha_byte || chroma_key || draw_dsc->angle || + 73b4: 9b07 ldr r3, [sp, #28] + 73b6: b9a3 cbnz r3, 73e2 + 73b8: 9b0c ldr r3, [sp, #48] ; 0x30 + 73ba: b993 cbnz r3, 73e2 + 73bc: 8863 ldrh r3, [r4, #2] + 73be: b983 cbnz r3, 73e2 + 73c0: 8923 ldrh r3, [r4, #8] + 73c2: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 73c6: bf14 ite ne + 73c8: f04f 0b02 movne.w fp, #2 + 73cc: f04f 0b01 moveq.w fp, #1 + if(other_mask_cnt) { + 73d0: 9b0b ldr r3, [sp, #44] ; 0x2c + 73d2: b14b cbz r3, 73e8 + _lv_memset_ff(mask_buf, mask_buf_size); + 73d4: 990a ldr r1, [sp, #40] ; 0x28 + 73d6: 4b5b ldr r3, [pc, #364] ; (7544 ) + 73d8: 4638 mov r0, r7 + 73da: 4798 blx r3 + px_i = 0; + 73dc: f04f 0800 mov.w r8, #0 + 73e0: e6c3 b.n 716a + mask_res = (alpha_byte || chroma_key || draw_dsc->angle || + 73e2: f04f 0b02 mov.w fp, #2 + 73e6: e7f3 b.n 73d0 + px_i = 0; + 73e8: f8dd 802c ldr.w r8, [sp, #44] ; 0x2c + 73ec: e6bd b.n 716a + bool transform = draw_dsc->angle != 0 || draw_dsc->zoom != LV_IMG_ZOOM_NONE ? true : false; + 73ee: 2301 movs r3, #1 + 73f0: 9315 str r3, [sp, #84] ; 0x54 + uint32_t mask_buf_size = lv_area_get_size(&draw_area) > LV_HOR_RES_MAX ? LV_HOR_RES_MAX : lv_area_get_size(&draw_area); + 73f2: 4e55 ldr r6, [pc, #340] ; (7548 ) + 73f4: a822 add r0, sp, #136 ; 0x88 + 73f6: 47b0 blx r6 + 73f8: f5b0 7ff0 cmp.w r0, #480 ; 0x1e0 + 73fc: f63f ae36 bhi.w 706c + 7400: a822 add r0, sp, #136 ; 0x88 + 7402: 47b0 blx r6 + 7404: 900a str r0, [sp, #40] ; 0x28 + lv_color_t * map2 = _lv_mem_buf_get(mask_buf_size * sizeof(lv_color_t)); + 7406: 9b0a ldr r3, [sp, #40] ; 0x28 + 7408: 4e50 ldr r6, [pc, #320] ; (754c ) + 740a: 0058 lsls r0, r3, #1 + 740c: 47b0 blx r6 + 740e: ee08 0a10 vmov s16, r0 + lv_opa_t * mask_buf = _lv_mem_buf_get(mask_buf_size); + 7412: 980a ldr r0, [sp, #40] ; 0x28 + 7414: 47b0 blx r6 + _lv_memset_00(&trans_dsc, sizeof(lv_img_transform_dsc_t)); + 7416: 4b4e ldr r3, [pc, #312] ; (7550 ) + lv_opa_t * mask_buf = _lv_mem_buf_get(mask_buf_size); + 7418: 4607 mov r7, r0 + _lv_memset_00(&trans_dsc, sizeof(lv_img_transform_dsc_t)); + 741a: 2148 movs r1, #72 ; 0x48 + 741c: a826 add r0, sp, #152 ; 0x98 + 741e: 4798 blx r3 + if(transform) { + 7420: 9b15 ldr r3, [sp, #84] ; 0x54 + 7422: b363 cbz r3, 747e + if(alpha_byte) cf = LV_IMG_CF_TRUE_COLOR_ALPHA; + 7424: 9b07 ldr r3, [sp, #28] + 7426: 2b00 cmp r3, #0 + 7428: f47f ae24 bne.w 7074 + else if(chroma_key) cf = LV_IMG_CF_TRUE_COLOR_CHROMA_KEYED; + 742c: 9b0c ldr r3, [sp, #48] ; 0x30 + 742e: 2b00 cmp r3, #0 + 7430: bf0c ite eq + 7432: 2204 moveq r2, #4 + 7434: 2206 movne r2, #6 + trans_dsc.cfg.angle = draw_dsc->angle; + 7436: 8863 ldrh r3, [r4, #2] + 7438: f8ad 30a4 strh.w r3, [sp, #164] ; 0xa4 + trans_dsc.cfg.zoom = draw_dsc->zoom; + 743c: 8923 ldrh r3, [r4, #8] + 743e: f8ad 30a6 strh.w r3, [sp, #166] ; 0xa6 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + 7442: f8ba 3006 ldrh.w r3, [sl, #6] + 7446: f8ba 1002 ldrh.w r1, [sl, #2] + trans_dsc.cfg.src = map_p; + 744a: 9526 str r5, [sp, #152] ; 0x98 + 744c: 3301 adds r3, #1 + 744e: 1a5b subs r3, r3, r1 + trans_dsc.cfg.src_h = lv_area_get_height(map_area);; + 7450: f8ad 309e strh.w r3, [sp, #158] ; 0x9e + trans_dsc.cfg.pivot_x = draw_dsc->pivot.x; + 7454: 88a3 ldrh r3, [r4, #4] + 7456: f8ad 30a0 strh.w r3, [sp, #160] ; 0xa0 + trans_dsc.cfg.pivot_y = draw_dsc->pivot.y; + 745a: 88e3 ldrh r3, [r4, #6] + 745c: f8ad 30a2 strh.w r3, [sp, #162] ; 0xa2 + trans_dsc.cfg.color = draw_dsc->recolor; + 7460: 89a3 ldrh r3, [r4, #12] + 7462: f8ad 30a8 strh.w r3, [sp, #168] ; 0xa8 + trans_dsc.cfg.antialias = draw_dsc->antialias; + 7466: 7be3 ldrb r3, [r4, #15] + trans_dsc.cfg.src_w = map_w; + 7468: f8ad 809c strh.w r8, [sp, #156] ; 0x9c + trans_dsc.cfg.antialias = draw_dsc->antialias; + 746c: f3c3 0300 ubfx r3, r3, #0, #1 + 7470: f88d 30ab strb.w r3, [sp, #171] ; 0xab + _lv_img_buf_transform_init(&trans_dsc); + 7474: a826 add r0, sp, #152 ; 0x98 + 7476: 4b37 ldr r3, [pc, #220] ; (7554 ) + trans_dsc.cfg.cf = cf; + 7478: f88d 20aa strb.w r2, [sp, #170] ; 0xaa + _lv_img_buf_transform_init(&trans_dsc); + 747c: 4798 blx r3 + lv_opa_t recolor_opa_inv = 255 - draw_dsc->recolor_opa; + 747e: 7aa3 ldrb r3, [r4, #10] + 7480: 43da mvns r2, r3 + 7482: b2d2 uxtb r2, r2 + 7484: 9214 str r2, [sp, #80] ; 0x50 + if(draw_dsc->recolor_opa != 0) { + 7486: 2b00 cmp r3, #0 + 7488: f43f adf6 beq.w 7078 + out[0] = (uint16_t) LV_COLOR_GET_R(c) * mix; + 748c: 7b62 ldrb r2, [r4, #13] + 748e: 08d2 lsrs r2, r2, #3 + 7490: 435a muls r2, r3 + 7492: 9219 str r2, [sp, #100] ; 0x64 + out[1] = (uint16_t) LV_COLOR_GET_G(c) * mix; + 7494: 89a2 ldrh r2, [r4, #12] + 7496: f3c2 1245 ubfx r2, r2, #5, #6 + 749a: 435a muls r2, r3 + 749c: 9216 str r2, [sp, #88] ; 0x58 + out[2] = (uint16_t) LV_COLOR_GET_B(c) * mix; + 749e: 7b22 ldrb r2, [r4, #12] + 74a0: f002 021f and.w r2, r2, #31 + 74a4: 4353 muls r3, r2 + 74a6: 9310 str r3, [sp, #64] ; 0x40 + mask_res = (alpha_byte || chroma_key || draw_dsc->angle || + 74a8: 9b07 ldr r3, [sp, #28] + 74aa: 2b00 cmp r3, #0 + 74ac: f47f ade8 bne.w 7080 + 74b0: 9b0c ldr r3, [sp, #48] ; 0x30 + 74b2: 2b00 cmp r3, #0 + 74b4: f47f ade4 bne.w 7080 + 74b8: 8863 ldrh r3, [r4, #2] + 74ba: 2b00 cmp r3, #0 + 74bc: f47f ade0 bne.w 7080 + 74c0: 8923 ldrh r3, [r4, #8] + 74c2: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 74c6: bf14 ite ne + 74c8: f04f 0b02 movne.w fp, #2 + 74cc: f04f 0b01 moveq.w fp, #1 + if(other_mask_cnt) { + 74d0: 9b0b ldr r3, [sp, #44] ; 0x2c + 74d2: b11b cbz r3, 74dc + _lv_memset_ff(mask_buf, mask_buf_size); + 74d4: 990a ldr r1, [sp, #40] ; 0x28 + 74d6: 4b1b ldr r3, [pc, #108] ; (7544 ) + 74d8: 4638 mov r0, r7 + 74da: 4798 blx r3 + int32_t rot_y = disp_area->y1 + draw_area.y1 - map_area->y1; + 74dc: 9b04 ldr r3, [sp, #16] + 74de: f9bd 208a ldrsh.w r2, [sp, #138] ; 0x8a + 74e2: f9b3 3012 ldrsh.w r3, [r3, #18] + 74e6: 4413 add r3, r2 + 74e8: f9ba 2002 ldrsh.w r2, [sl, #2] + 74ec: 1a9b subs r3, r3, r2 + 74ee: 931a str r3, [sp, #104] ; 0x68 + map_buf_tmp += map_w * px_size_byte; + 74f0: 9b05 ldr r3, [sp, #20] + 74f2: fb13 f308 smulbb r3, r3, r8 + 74f6: 931c str r3, [sp, #112] ; 0x70 + for(y = 0; y < draw_area_h; y++) { + 74f8: 2300 movs r3, #0 + 74fa: 9309 str r3, [sp, #36] ; 0x24 + uint32_t px_i = 0; + 74fc: 4698 mov r8, r3 + 74fe: 9b11 ldr r3, [sp, #68] ; 0x44 + 7500: ea23 73e3 bic.w r3, r3, r3, asr #31 + 7504: 931f str r3, [sp, #124] ; 0x7c + for(y = 0; y < draw_area_h; y++) { + 7506: 9b17 ldr r3, [sp, #92] ; 0x5c + 7508: 9a09 ldr r2, [sp, #36] ; 0x24 + 750a: 4293 cmp r3, r2 + 750c: f73f adcc bgt.w 70a8 + if(blend_area.y1 != blend_area.y2) { + 7510: f9bd 3096 ldrsh.w r3, [sp, #150] ; 0x96 + 7514: f9bd 2092 ldrsh.w r2, [sp, #146] ; 0x92 + 7518: 429a cmp r2, r3 + 751a: d00e beq.n 753a + blend_area.y2--; + 751c: 3b01 subs r3, #1 + 751e: f8ad 3096 strh.w r3, [sp, #150] ; 0x96 + _lv_blend_map(clip_area, &blend_area, map2, mask_buf, mask_res, draw_dsc->opa, draw_dsc->blend_mode); + 7522: 7ba3 ldrb r3, [r4, #14] + 7524: 9302 str r3, [sp, #8] + 7526: 7823 ldrb r3, [r4, #0] + 7528: 4c05 ldr r4, [pc, #20] ; (7540 ) + 752a: e9cd b300 strd fp, r3, [sp] + 752e: ee18 2a10 vmov r2, s16 + 7532: 463b mov r3, r7 + 7534: a924 add r1, sp, #144 ; 0x90 + 7536: 4648 mov r0, r9 + 7538: 47a0 blx r4 + _lv_mem_buf_release(mask_buf); + 753a: 4638 mov r0, r7 + 753c: e590 b.n 7060 + 753e: bf00 nop + 7540: 000067fd .word 0x000067fd + 7544: 0000f075 .word 0x0000f075 + 7548: 0000de71 .word 0x0000de71 + 754c: 0000eeb5 .word 0x0000eeb5 + 7550: 0000f019 .word 0x0000f019 + 7554: 0000bf65 .word 0x0000bf65 + +00007558 : +{ + 7558: b510 push {r4, lr} + _lv_memset_00(dsc, sizeof(lv_draw_img_dsc_t)); + 755a: 4b08 ldr r3, [pc, #32] ; (757c ) +{ + 755c: 4604 mov r4, r0 + _lv_memset_00(dsc, sizeof(lv_draw_img_dsc_t)); + 755e: 2110 movs r1, #16 + 7560: 4798 blx r3 + dsc->recolor = LV_COLOR_BLACK; + 7562: 2300 movs r3, #0 + 7564: 81a3 strh r3, [r4, #12] + dsc->opa = LV_OPA_COVER; + 7566: 23ff movs r3, #255 ; 0xff + 7568: 7023 strb r3, [r4, #0] + dsc->zoom = LV_IMG_ZOOM_NONE; + 756a: f44f 7380 mov.w r3, #256 ; 0x100 + 756e: 8123 strh r3, [r4, #8] + dsc->antialias = LV_ANTIALIAS; + 7570: 7be3 ldrb r3, [r4, #15] + 7572: f043 0301 orr.w r3, r3, #1 + 7576: 73e3 strb r3, [r4, #15] +} + 7578: bd10 pop {r4, pc} + 757a: bf00 nop + 757c: 0000f019 .word 0x0000f019 + +00007580 : + switch(cf) { + 7580: 3804 subs r0, #4 + 7582: b2c0 uxtb r0, r0 + 7584: 280a cmp r0, #10 + 7586: bf9d ittte ls + 7588: 4b02 ldrls r3, [pc, #8] ; (7594 ) + 758a: 181b addls r3, r3, r0 + 758c: 7898 ldrbls r0, [r3, #2] +{ + 758e: 2000 movhi r0, #0 +} + 7590: 4770 bx lr + 7592: bf00 nop + 7594: 0001fa9c .word 0x0001fa9c + +00007598 : + switch(cf) { + 7598: 2803 cmp r0, #3 + 759a: d005 beq.n 75a8 + 759c: 3806 subs r0, #6 + 759e: 2804 cmp r0, #4 + 75a0: bf8c ite hi + 75a2: 2000 movhi r0, #0 + 75a4: 2001 movls r0, #1 + 75a6: 4770 bx lr + is_chroma_keyed = true; + 75a8: 2001 movs r0, #1 +} + 75aa: 4770 bx lr + +000075ac : + switch(cf) { + 75ac: 280e cmp r0, #14 + 75ae: bf9d ittte ls + 75b0: f647 73a4 movwls r3, #32676 ; 0x7fa4 + 75b4: fa23 f000 lsrls.w r0, r3, r0 + 75b8: f000 0001 andls.w r0, r0, #1 +{ + 75bc: 2000 movhi r0, #0 +} + 75be: 4770 bx lr + +000075c0 : +{ + 75c0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 75c4: ed2d 8b02 vpush {d8} + 75c8: 4604 mov r4, r0 + 75ca: b08d sub sp, #52 ; 0x34 + 75cc: 4688 mov r8, r1 + 75ce: 461f mov r7, r3 + if(src == NULL) { + 75d0: 4610 mov r0, r2 + 75d2: b94a cbnz r2, 75e8 + LV_LOG_WARN("Image draw: src is NULL"); + 75d4: 4b76 ldr r3, [pc, #472] ; (77b0 ) + 75d6: 9300 str r3, [sp, #0] + 75d8: 4b76 ldr r3, [pc, #472] ; (77b4 ) + 75da: 224d movs r2, #77 ; 0x4d + LV_LOG_WARN("Image draw error"); + 75dc: 4976 ldr r1, [pc, #472] ; (77b8 ) + 75de: 4d77 ldr r5, [pc, #476] ; (77bc ) + 75e0: 2002 movs r0, #2 + 75e2: 47a8 blx r5 + show_error(coords, mask, "No\ndata"); + 75e4: 4a76 ldr r2, [pc, #472] ; (77c0 ) + 75e6: e017 b.n 7618 + if(dsc->opa <= LV_OPA_MIN) return; + 75e8: 781b ldrb r3, [r3, #0] + 75ea: 2b05 cmp r3, #5 + 75ec: d969 bls.n 76c2 + lv_img_cache_entry_t * cdsc = _lv_img_cache_open(src, draw_dsc->recolor); + 75ee: 89b9 ldrh r1, [r7, #12] + 75f0: 4b74 ldr r3, [pc, #464] ; (77c4 ) + 75f2: 4798 blx r3 + if(cdsc == NULL) return LV_RES_INV; + 75f4: 4605 mov r5, r0 + 75f6: 2800 cmp r0, #0 + 75f8: f000 80bc beq.w 7774 + bool chroma_keyed = lv_img_cf_is_chroma_keyed(cdsc->dec_dsc.header.cf); + 75fc: 7b03 ldrb r3, [r0, #12] + if(cdsc->dec_dsc.error_msg != NULL) { + 75fe: 6982 ldr r2, [r0, #24] + bool chroma_keyed = lv_img_cf_is_chroma_keyed(cdsc->dec_dsc.header.cf); + 7600: f003 031f and.w r3, r3, #31 + if(cdsc->dec_dsc.error_msg != NULL) { + 7604: b18a cbz r2, 762a + LV_LOG_WARN("Image draw error"); + 7606: 4b70 ldr r3, [pc, #448] ; (77c8 ) + 7608: 9300 str r3, [sp, #0] + 760a: 22f7 movs r2, #247 ; 0xf7 + 760c: 4b6f ldr r3, [pc, #444] ; (77cc ) + 760e: 496a ldr r1, [pc, #424] ; (77b8 ) + 7610: 4e6a ldr r6, [pc, #424] ; (77bc ) + 7612: 2002 movs r0, #2 + 7614: 47b0 blx r6 + show_error(coords, clip_area, cdsc->dec_dsc.error_msg); + 7616: 69aa ldr r2, [r5, #24] + show_error(coords, mask, "No\ndata"); + 7618: 4b6d ldr r3, [pc, #436] ; (77d0 ) + 761a: 4641 mov r1, r8 + 761c: 4620 mov r0, r4 +} + 761e: b00d add sp, #52 ; 0x34 + 7620: ecbd 8b02 vpop {d8} + 7624: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + show_error(coords, mask, "No\ndata"); + 7628: 4718 bx r3 + bool chroma_keyed = lv_img_cf_is_chroma_keyed(cdsc->dec_dsc.header.cf); + 762a: 4618 mov r0, r3 + 762c: 4a69 ldr r2, [pc, #420] ; (77d4 ) + 762e: 4790 blx r2 + 7630: 9003 str r0, [sp, #12] + bool alpha_byte = lv_img_cf_has_alpha(cdsc->dec_dsc.header.cf); + 7632: 4618 mov r0, r3 + 7634: 4b68 ldr r3, [pc, #416] ; (77d8 ) + 7636: 4798 blx r3 + else if(cdsc->dec_dsc.img_data) { + 7638: 692b ldr r3, [r5, #16] + bool alpha_byte = lv_img_cf_has_alpha(cdsc->dec_dsc.header.cf); + 763a: 9004 str r0, [sp, #16] + else if(cdsc->dec_dsc.img_data) { + 763c: 2b00 cmp r3, #0 + 763e: d045 beq.n 76cc + lv_area_copy(&map_area_rot, coords); + 7640: 4b66 ldr r3, [pc, #408] ; (77dc ) + 7642: a808 add r0, sp, #32 + 7644: 4621 mov r1, r4 + 7646: 4798 blx r3 + if(draw_dsc->angle || draw_dsc->zoom != LV_IMG_ZOOM_NONE) { + 7648: 887b ldrh r3, [r7, #2] + 764a: 8938 ldrh r0, [r7, #8] + 764c: b913 cbnz r3, 7654 + 764e: f5b0 7f80 cmp.w r0, #256 ; 0x100 + 7652: d026 beq.n 76a2 + 7654: 88e2 ldrh r2, [r4, #6] + 7656: 8861 ldrh r1, [r4, #2] + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + 7658: 8826 ldrh r6, [r4, #0] + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + 765a: 3201 adds r2, #1 + 765c: 1a52 subs r2, r2, r1 + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + 765e: 88a1 ldrh r1, [r4, #4] + 7660: 3101 adds r1, #1 + 7662: 1b89 subs r1, r1, r6 + _lv_img_buf_get_transformed_area(&map_area_rot, w, h, draw_dsc->angle, draw_dsc->zoom, &draw_dsc->pivot); + 7664: 1d3e adds r6, r7, #4 + 7666: e9cd 0600 strd r0, r6, [sp] + 766a: b21b sxth r3, r3 + 766c: b212 sxth r2, r2 + 766e: b209 sxth r1, r1 + 7670: 4e5b ldr r6, [pc, #364] ; (77e0 ) + 7672: a808 add r0, sp, #32 + 7674: 47b0 blx r6 + map_area_rot.x1 += coords->x1; + 7676: 8822 ldrh r2, [r4, #0] + 7678: f8bd 3020 ldrh.w r3, [sp, #32] + map_area_rot.y1 += coords->y1; + 767c: f8bd 1022 ldrh.w r1, [sp, #34] ; 0x22 + map_area_rot.x1 += coords->x1; + 7680: 4413 add r3, r2 + 7682: f8ad 3020 strh.w r3, [sp, #32] + map_area_rot.y1 += coords->y1; + 7686: 8863 ldrh r3, [r4, #2] + 7688: 4419 add r1, r3 + 768a: f8ad 1022 strh.w r1, [sp, #34] ; 0x22 + map_area_rot.x2 += coords->x1; + 768e: f8bd 1024 ldrh.w r1, [sp, #36] ; 0x24 + 7692: 440a add r2, r1 + 7694: f8ad 2024 strh.w r2, [sp, #36] ; 0x24 + map_area_rot.y2 += coords->y1; + 7698: f8bd 2026 ldrh.w r2, [sp, #38] ; 0x26 + 769c: 4413 add r3, r2 + 769e: f8ad 3026 strh.w r3, [sp, #38] ; 0x26 + union_ok = _lv_area_intersect(&mask_com, clip_area, &map_area_rot); + 76a2: 4b50 ldr r3, [pc, #320] ; (77e4 ) + 76a4: aa08 add r2, sp, #32 + 76a6: 4641 mov r1, r8 + 76a8: a80a add r0, sp, #40 ; 0x28 + 76aa: 4798 blx r3 + if(union_ok == false) { + 76ac: b148 cbz r0, 76c2 + lv_draw_map(coords, &mask_com, cdsc->dec_dsc.img_data, draw_dsc, chroma_keyed, alpha_byte); + 76ae: 9b04 ldr r3, [sp, #16] + 76b0: 9301 str r3, [sp, #4] + 76b2: 9b03 ldr r3, [sp, #12] + 76b4: 9300 str r3, [sp, #0] + 76b6: 4620 mov r0, r4 + 76b8: 692a ldr r2, [r5, #16] + 76ba: 4c4b ldr r4, [pc, #300] ; (77e8 ) + 76bc: 463b mov r3, r7 + 76be: a90a add r1, sp, #40 ; 0x28 + 76c0: 47a0 blx r4 +} + 76c2: b00d add sp, #52 ; 0x34 + 76c4: ecbd 8b02 vpop {d8} + 76c8: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + union_ok = _lv_area_intersect(&mask_com, clip_area, coords); + 76cc: 4b45 ldr r3, [pc, #276] ; (77e4 ) + 76ce: 4622 mov r2, r4 + 76d0: 4641 mov r1, r8 + 76d2: a806 add r0, sp, #24 + 76d4: 4798 blx r3 + if(union_ok == false) { + 76d6: 2800 cmp r0, #0 + 76d8: d0f3 beq.n 76c2 + 76da: f8bd 601c ldrh.w r6, [sp, #28] + 76de: f8bd 3018 ldrh.w r3, [sp, #24] + 76e2: 3601 adds r6, #1 + 76e4: 1af6 subs r6, r6, r3 + 76e6: b233 sxth r3, r6 + 76e8: 9305 str r3, [sp, #20] + uint8_t * buf = _lv_mem_buf_get(lv_area_get_width(&mask_com) * + 76ea: eb03 0043 add.w r0, r3, r3, lsl #1 + 76ee: 4b3f ldr r3, [pc, #252] ; (77ec ) + 76f0: 4798 blx r3 + lv_area_copy(&line, &mask_com); + 76f2: 4b3a ldr r3, [pc, #232] ; (77dc ) + 76f4: a906 add r1, sp, #24 + uint8_t * buf = _lv_mem_buf_get(lv_area_get_width(&mask_com) * + 76f6: 4681 mov r9, r0 + lv_area_copy(&line, &mask_com); + 76f8: a808 add r0, sp, #32 + 76fa: 4798 blx r3 + lv_area_set_height(&line, 1); + 76fc: 4b3c ldr r3, [pc, #240] ; (77f0 ) + 76fe: 2101 movs r1, #1 + 7700: a808 add r0, sp, #32 + 7702: 4798 blx r3 + int32_t x = mask_com.x1 - coords->x1; + 7704: f9bd 3018 ldrsh.w r3, [sp, #24] + 7708: f9b4 2000 ldrsh.w r2, [r4] + int32_t y = mask_com.y1 - coords->y1; + 770c: f9bd a01a ldrsh.w sl, [sp, #26] + 7710: f9b4 1002 ldrsh.w r1, [r4, #2] + read_res = lv_img_decoder_read_line(&cdsc->dec_dsc, x, y, width, buf); + 7714: 1a9b subs r3, r3, r2 + 7716: b21b sxth r3, r3 + 7718: ee08 3a10 vmov s16, r3 + int32_t y = mask_com.y1 - coords->y1; + 771c: ebaa 0b01 sub.w fp, sl, r1 + for(row = mask_com.y1; row <= mask_com.y2; row++) { + 7720: f9bd 301e ldrsh.w r3, [sp, #30] + 7724: 459a cmp sl, r3 + 7726: dd03 ble.n 7730 + _lv_mem_buf_release(buf); + 7728: 4b32 ldr r3, [pc, #200] ; (77f4 ) + 772a: 4648 mov r0, r9 + 772c: 4798 blx r3 + if(res == LV_RES_INV) { + 772e: e7c8 b.n 76c2 + union_ok = _lv_area_intersect(&mask_line, clip_area, &line); + 7730: 4b2c ldr r3, [pc, #176] ; (77e4 ) + 7732: aa08 add r2, sp, #32 + 7734: 4641 mov r1, r8 + 7736: a80a add r0, sp, #40 ; 0x28 + 7738: 4798 blx r3 + if(union_ok == false) continue; + 773a: 2800 cmp r0, #0 + 773c: d035 beq.n 77aa + read_res = lv_img_decoder_read_line(&cdsc->dec_dsc, x, y, width, buf); + 773e: 9b05 ldr r3, [sp, #20] + 7740: 4e2d ldr r6, [pc, #180] ; (77f8 ) + 7742: f8cd 9000 str.w r9, [sp] + 7746: ee18 1a10 vmov r1, s16 + 774a: fa0f f28b sxth.w r2, fp + 774e: 4628 mov r0, r5 + 7750: 47b0 blx r6 + if(read_res != LV_RES_OK) { + 7752: 2801 cmp r0, #1 + 7754: d013 beq.n 777e + lv_img_decoder_close(&cdsc->dec_dsc); + 7756: 4628 mov r0, r5 + 7758: 4b28 ldr r3, [pc, #160] ; (77fc ) + LV_LOG_WARN("Image draw can't read the line"); + 775a: 4d18 ldr r5, [pc, #96] ; (77bc ) + lv_img_decoder_close(&cdsc->dec_dsc); + 775c: 4798 blx r3 + LV_LOG_WARN("Image draw can't read the line"); + 775e: 4b28 ldr r3, [pc, #160] ; (7800 ) + 7760: 9300 str r3, [sp, #0] + 7762: 2002 movs r0, #2 + 7764: 4b19 ldr r3, [pc, #100] ; (77cc ) + 7766: 4914 ldr r1, [pc, #80] ; (77b8 ) + 7768: f44f 729a mov.w r2, #308 ; 0x134 + 776c: 47a8 blx r5 + _lv_mem_buf_release(buf); + 776e: 4b21 ldr r3, [pc, #132] ; (77f4 ) + 7770: 4648 mov r0, r9 + 7772: 4798 blx r3 + LV_LOG_WARN("Image draw error"); + 7774: 4b14 ldr r3, [pc, #80] ; (77c8 ) + 7776: 9300 str r3, [sp, #0] + 7778: 2258 movs r2, #88 ; 0x58 + 777a: 4b0e ldr r3, [pc, #56] ; (77b4 ) + 777c: e72e b.n 75dc + lv_draw_map(&line, &mask_line, buf, draw_dsc, chroma_keyed, alpha_byte); + 777e: 9b04 ldr r3, [sp, #16] + 7780: 9301 str r3, [sp, #4] + 7782: 9b03 ldr r3, [sp, #12] + 7784: 9300 str r3, [sp, #0] + 7786: 4e18 ldr r6, [pc, #96] ; (77e8 ) + 7788: 463b mov r3, r7 + 778a: 464a mov r2, r9 + 778c: a90a add r1, sp, #40 ; 0x28 + 778e: a808 add r0, sp, #32 + 7790: 47b0 blx r6 + line.y1++; + 7792: f8bd 3022 ldrh.w r3, [sp, #34] ; 0x22 + 7796: 3301 adds r3, #1 + 7798: f8ad 3022 strh.w r3, [sp, #34] ; 0x22 + line.y2++; + 779c: f8bd 3026 ldrh.w r3, [sp, #38] ; 0x26 + 77a0: 3301 adds r3, #1 + 77a2: f8ad 3026 strh.w r3, [sp, #38] ; 0x26 + y++; + 77a6: f10b 0b01 add.w fp, fp, #1 + for(row = mask_com.y1; row <= mask_com.y2; row++) { + 77aa: f10a 0a01 add.w sl, sl, #1 + 77ae: e7b7 b.n 7720 + 77b0: 0001fa4b .word 0x0001fa4b + 77b4: 0001faa9 .word 0x0001faa9 + 77b8: 0001fa17 .word 0x0001fa17 + 77bc: 0000e8e9 .word 0x0000e8e9 + 77c0: 0001fa63 .word 0x0001fa63 + 77c4: 0000c4a5 .word 0x0000c4a5 + 77c8: 0001fa6b .word 0x0001fa6b + 77cc: 0001fab5 .word 0x0001fab5 + 77d0: 00006d99 .word 0x00006d99 + 77d4: 00007599 .word 0x00007599 + 77d8: 000075ad .word 0x000075ad + 77dc: 00006de9 .word 0x00006de9 + 77e0: 0000c061 .word 0x0000c061 + 77e4: 0000de8d .word 0x0000de8d + 77e8: 00006dfd .word 0x00006dfd + 77ec: 0000eeb5 .word 0x0000eeb5 + 77f0: 0000de67 .word 0x0000de67 + 77f4: 0000eb69 .word 0x0000eb69 + 77f8: 0000d02d .word 0x0000d02d + 77fc: 0000d04d .word 0x0000d04d + 7800: 0001fa7c .word 0x0001fa7c + +00007804 : + if(src == NULL) return img_src_type; + 7804: b138 cbz r0, 7816 + if(u8_p[0] >= 0x20 && u8_p[0] <= 0x7F) { + 7806: 7800 ldrb r0, [r0, #0] + 7808: f1a0 0320 sub.w r3, r0, #32 + 780c: 2b5f cmp r3, #95 ; 0x5f + 780e: d904 bls.n 781a + else if(u8_p[0] >= 0x80) { + 7810: 09c0 lsrs r0, r0, #7 + 7812: 0040 lsls r0, r0, #1 + 7814: 4770 bx lr + if(src == NULL) return img_src_type; + 7816: 2003 movs r0, #3 + 7818: 4770 bx lr + img_src_type = LV_IMG_SRC_FILE; /*If it's an ASCII character then it's file name*/ + 781a: 2001 movs r0, #1 +} + 781c: 4770 bx lr + +0000781e : + */ +static uint8_t hex_char_to_num(char hex) +{ + uint8_t result = 0; + + if(hex >= '0' && hex <= '9') { + 781e: f1a0 0330 sub.w r3, r0, #48 ; 0x30 + 7822: b2db uxtb r3, r3 + 7824: 2b09 cmp r3, #9 + 7826: d90a bls.n 783e + result = hex - '0'; + } + else { + if(hex >= 'a') hex -= 'a' - 'A'; /*Convert to upper case*/ + 7828: 2860 cmp r0, #96 ; 0x60 + 782a: bf84 itt hi + 782c: 3820 subhi r0, #32 + 782e: b2c0 uxtbhi r0, r0 + + switch(hex) { + 7830: f1a0 0341 sub.w r3, r0, #65 ; 0x41 + 7834: 2b05 cmp r3, #5 + 7836: bf9a itte ls + 7838: 3837 subls r0, #55 ; 0x37 + 783a: b2c3 uxtbls r3, r0 +{ + 783c: 2300 movhi r3, #0 + break; + } + } + + return result; +} + 783e: 4618 mov r0, r3 + 7840: 4770 bx lr + ... + +00007844 : +{ + 7844: b510 push {r4, lr} + _lv_memset_00(dsc, sizeof(lv_draw_label_dsc_t)); + 7846: 4b09 ldr r3, [pc, #36] ; (786c ) +{ + 7848: 4604 mov r4, r0 + _lv_memset_00(dsc, sizeof(lv_draw_label_dsc_t)); + 784a: 211c movs r1, #28 + 784c: 4798 blx r3 + dsc->opa = LV_OPA_COVER; + 784e: 23ff movs r3, #255 ; 0xff + 7850: 7223 strb r3, [r4, #8] + dsc->font = LV_THEME_DEFAULT_FONT_NORMAL; + 7852: 4b07 ldr r3, [pc, #28] ; (7870 ) + 7854: 6063 str r3, [r4, #4] + dsc->sel_start = LV_DRAW_LABEL_NO_TXT_SEL; + 7856: f64f 73ff movw r3, #65535 ; 0xffff + 785a: 81e3 strh r3, [r4, #14] + dsc->sel_end = LV_DRAW_LABEL_NO_TXT_SEL; + 785c: 8223 strh r3, [r4, #16] + dsc->color = LV_COLOR_BLACK; + 785e: f44f 13f8 mov.w r3, #2031616 ; 0x1f0000 + 7862: 6023 str r3, [r4, #0] + dsc->bidi_dir = LV_BIDI_DIR_LTR; + 7864: 2300 movs r3, #0 + 7866: 75a3 strb r3, [r4, #22] +} + 7868: bd10 pop {r4, pc} + 786a: bf00 nop + 786c: 0000f019 .word 0x0000f019 + 7870: 20000010 .word 0x20000010 + +00007874 : +{ + 7874: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 7878: ed2d 8b04 vpush {d8-d9} + 787c: b0d1 sub sp, #324 ; 0x144 + 787e: 468a mov sl, r1 + 7880: 930a str r3, [sp, #40] ; 0x28 + 7882: 2300 movs r3, #0 + 7884: 9321 str r3, [sp, #132] ; 0x84 + if(dsc->opa <= LV_OPA_MIN) return; + 7886: 7a13 ldrb r3, [r2, #8] +{ + 7888: 9c5e ldr r4, [sp, #376] ; 0x178 + 788a: 9005 str r0, [sp, #20] + if(dsc->opa <= LV_OPA_MIN) return; + 788c: 2b05 cmp r3, #5 +{ + 788e: 4693 mov fp, r2 + if(dsc->opa <= LV_OPA_MIN) return; + 7890: f240 80db bls.w 7a4a + const lv_font_t * font = dsc->font; + 7894: 6853 ldr r3, [r2, #4] + 7896: ee08 3a10 vmov s16, r3 + if(txt[0] == '\0') return; + 789a: 9b0a ldr r3, [sp, #40] ; 0x28 + 789c: 781b ldrb r3, [r3, #0] + 789e: 2b00 cmp r3, #0 + 78a0: f000 80d3 beq.w 7a4a + bool clip_ok = _lv_area_intersect(&clipped_area, coords, mask); + 78a4: 460a mov r2, r1 + 78a6: 4b9c ldr r3, [pc, #624] ; (7b18 ) + 78a8: 4601 mov r1, r0 + 78aa: a831 add r0, sp, #196 ; 0xc4 + 78ac: 4798 blx r3 + if(!clip_ok) return; + 78ae: 2800 cmp r0, #0 + 78b0: f000 80cb beq.w 7a4a + if((dsc->flag & LV_TXT_FLAG_EXPAND) == 0) { + 78b4: f89b 3017 ldrb.w r3, [fp, #23] + 78b8: 079f lsls r7, r3, #30 + 78ba: f100 80cb bmi.w 7a54 + 78be: 9b05 ldr r3, [sp, #20] + 78c0: 9a05 ldr r2, [sp, #20] + 78c2: 889b ldrh r3, [r3, #4] + 78c4: 8812 ldrh r2, [r2, #0] + 78c6: 3301 adds r3, #1 + 78c8: 1a9b subs r3, r3, r2 + w = lv_area_get_width(coords); + 78ca: b21b sxth r3, r3 + int32_t line_height_font = lv_font_get_line_height(font); + 78cc: ee18 2a10 vmov r2, s16 + 78d0: f9b2 6008 ldrsh.w r6, [r2, #8] + pos.x = coords->x1; + 78d4: 9a05 ldr r2, [sp, #20] + int32_t line_height = line_height_font + dsc->line_space; + 78d6: f9bb 500a ldrsh.w r5, [fp, #10] + pos.x = coords->x1; + 78da: f9b2 2000 ldrsh.w r2, [r2] + 78de: 920b str r2, [sp, #44] ; 0x2c + pos.y = coords->y1; + 78e0: 9a05 ldr r2, [sp, #20] + 78e2: f9b2 0002 ldrsh.w r0, [r2, #2] + x_ofs = dsc->ofs_x; + 78e6: f9bb 2012 ldrsh.w r2, [fp, #18] + 78ea: 9224 str r2, [sp, #144] ; 0x90 + y_ofs = dsc->ofs_y; + 78ec: f9bb 2014 ldrsh.w r2, [fp, #20] + pos.y += y_ofs; + 78f0: 1887 adds r7, r0, r2 + 78f2: b2b9 uxth r1, r7 + 78f4: b23f sxth r7, r7 + int32_t line_height = line_height_font + dsc->line_space; + 78f6: 4435 add r5, r6 + pos.y += y_ofs; + 78f8: 9706 str r7, [sp, #24] + if(hint && y_ofs == 0 && coords->y1 < 0) { + 78fa: 2c00 cmp r4, #0 + 78fc: f000 80bc beq.w 7a78 + 7900: 2a00 cmp r2, #0 + 7902: f040 80bb bne.w 7a7c + 7906: 2800 cmp r0, #0 + 7908: f280 80b9 bge.w 7a7e + if(LV_MATH_ABS(hint->coord_y - coords->y1) > LV_LABEL_HINT_UPDATE_TH - 2 * line_height) { + 790c: 68a2 ldr r2, [r4, #8] + 790e: 1a12 subs r2, r2, r0 + 7910: 2a00 cmp r2, #0 + 7912: bfb8 it lt + 7914: 4252 neglt r2, r2 + 7916: f5c5 7000 rsb r0, r5, #512 ; 0x200 + 791a: ebb2 0f40 cmp.w r2, r0, lsl #1 + hint->line_start = -1; + 791e: bfc4 itt gt + 7920: f04f 32ff movgt.w r2, #4294967295 ; 0xffffffff + 7924: 6022 strgt r2, [r4, #0] + last_line_start = hint->line_start; + 7926: 6822 ldr r2, [r4, #0] + if(hint && last_line_start >= 0) { + 7928: 2a00 cmp r2, #0 + 792a: f2c0 80a7 blt.w 7a7c + line_start = last_line_start; + 792e: 9204 str r2, [sp, #16] + pos.y += hint->y; + 7930: 6862 ldr r2, [r4, #4] + 7932: 440a add r2, r1 + 7934: b212 sxth r2, r2 + 7936: 9206 str r2, [sp, #24] + uint32_t line_end = line_start + _lv_txt_get_next_line(&txt[line_start], font, dsc->letter_space, w, dsc->flag); + 7938: b21b sxth r3, r3 + 793a: 9f04 ldr r7, [sp, #16] + 793c: 980a ldr r0, [sp, #40] ; 0x28 + 793e: f9bb 200c ldrsh.w r2, [fp, #12] + 7942: ee09 3a10 vmov s18, r3 + 7946: f89b 3017 ldrb.w r3, [fp, #23] + 794a: 9300 str r3, [sp, #0] + 794c: 4438 add r0, r7 + 794e: ee19 3a10 vmov r3, s18 + 7952: ee18 1a10 vmov r1, s16 + 7956: 4f71 ldr r7, [pc, #452] ; (7b1c ) + 7958: 47b8 blx r7 + 795a: 9b04 ldr r3, [sp, #16] + 795c: 18c3 adds r3, r0, r3 + 795e: 9307 str r3, [sp, #28] + while(pos.y + line_height_font < mask->y1) { + 7960: 9a06 ldr r2, [sp, #24] + 7962: f9ba 1002 ldrsh.w r1, [sl, #2] + line_end += _lv_txt_get_next_line(&txt[line_start], font, dsc->letter_space, w, dsc->flag); + 7966: f89b 3017 ldrb.w r3, [fp, #23] + while(pos.y + line_height_font < mask->y1) { + 796a: 4432 add r2, r6 + 796c: 428a cmp r2, r1 + line_end += _lv_txt_get_next_line(&txt[line_start], font, dsc->letter_space, w, dsc->flag); + 796e: 9a0a ldr r2, [sp, #40] ; 0x28 + while(pos.y + line_height_font < mask->y1) { + 7970: f2c0 8087 blt.w 7a82 + line_width = _lv_txt_get_width(&txt[line_start], line_end - line_start, font, dsc->letter_space, dsc->flag); + 7974: 9904 ldr r1, [sp, #16] + if(dsc->flag & LV_TXT_FLAG_CENTER) { + 7976: 075e lsls r6, r3, #29 + line_width = _lv_txt_get_width(&txt[line_start], line_end - line_start, font, dsc->letter_space, dsc->flag); + 7978: eb02 0001 add.w r0, r2, r1 + if(dsc->flag & LV_TXT_FLAG_CENTER) { + 797c: f140 80ab bpl.w 7ad6 + line_width = _lv_txt_get_width(&txt[line_start], line_end - line_start, font, dsc->letter_space, dsc->flag); + 7980: 9a07 ldr r2, [sp, #28] + 7982: 9300 str r3, [sp, #0] + 7984: 1a51 subs r1, r2, r1 + 7986: f9bb 300c ldrsh.w r3, [fp, #12] + 798a: 4c65 ldr r4, [pc, #404] ; (7b20 ) + 798c: ee18 2a10 vmov r2, s16 + 7990: b289 uxth r1, r1 + 7992: 47a0 blx r4 + 7994: 9b05 ldr r3, [sp, #20] + 7996: 9a05 ldr r2, [sp, #20] + 7998: 889b ldrh r3, [r3, #4] + 799a: 8812 ldrh r2, [r2, #0] + 799c: 3301 adds r3, #1 + 799e: 1a9b subs r3, r3, r2 + pos.x += (lv_area_get_width(coords) - line_width) / 2; + 79a0: b21b sxth r3, r3 + 79a2: 1a18 subs r0, r3, r0 + 79a4: 9b0b ldr r3, [sp, #44] ; 0x2c + 79a6: eb00 70d0 add.w r0, r0, r0, lsr #31 + 79aa: eb03 0060 add.w r0, r3, r0, asr #1 + pos.x += lv_area_get_width(coords) - line_width; + 79ae: b203 sxth r3, r0 + 79b0: 930b str r3, [sp, #44] ; 0x2c + lv_opa_t opa = dsc->opa; + 79b2: f89b 3008 ldrb.w r3, [fp, #8] + 79b6: 9320 str r3, [sp, #128] ; 0x80 + uint16_t sel_start = dsc->sel_start; + 79b8: f8bb 300e ldrh.w r3, [fp, #14] + 79bc: 9310 str r3, [sp, #64] ; 0x40 + uint16_t sel_end = dsc->sel_end; + 79be: f8bb 3010 ldrh.w r3, [fp, #16] + 79c2: 9311 str r3, [sp, #68] ; 0x44 + if(sel_start > sel_end) { + 79c4: e9dd 3210 ldrd r3, r2, [sp, #64] ; 0x40 + 79c8: 4293 cmp r3, r2 + 79ca: bf88 it hi + 79cc: e9cd 2310 strdhi r2, r3, [sp, #64] ; 0x40 + if((dsc->decor & LV_TEXT_DECOR_UNDERLINE) || (dsc->decor & LV_TEXT_DECOR_STRIKETHROUGH)) { + 79d0: f89b 3018 ldrb.w r3, [fp, #24] + 79d4: 0799 lsls r1, r3, #30 + 79d6: d01c beq.n 7a12 + lv_draw_line_dsc_init(&line_dsc); + 79d8: 4b52 ldr r3, [pc, #328] ; (7b24 ) + 79da: a835 add r0, sp, #212 ; 0xd4 + 79dc: 4798 blx r3 + line_dsc.color = dsc->color; + 79de: f8bb 3000 ldrh.w r3, [fp] + 79e2: f8ad 30d4 strh.w r3, [sp, #212] ; 0xd4 + line_dsc.width = (dsc->font->line_height + 5) / 10; /*+5 for rounding*/ + 79e6: f8db 3004 ldr.w r3, [fp, #4] + 79ea: f9b3 3008 ldrsh.w r3, [r3, #8] + 79ee: 220a movs r2, #10 + 79f0: 3305 adds r3, #5 + 79f2: fb93 f3f2 sdiv r3, r3, r2 + 79f6: f8ad 30d6 strh.w r3, [sp, #214] ; 0xd6 + line_dsc.opa = dsc->opa; + 79fa: f89b 3008 ldrb.w r3, [fp, #8] + line_dsc.blend_mode = dsc->blend_mode; + 79fe: f89b 2019 ldrb.w r2, [fp, #25] + line_dsc.opa = dsc->opa; + 7a02: f88d 30dc strb.w r3, [sp, #220] ; 0xdc + line_dsc.blend_mode = dsc->blend_mode; + 7a06: f89d 30dd ldrb.w r3, [sp, #221] ; 0xdd + 7a0a: f362 0301 bfi r3, r2, #0, #2 + 7a0e: f88d 30dd strb.w r3, [sp, #221] ; 0xdd + lv_draw_rect_dsc_init(&draw_dsc_sel); + 7a12: 4b45 ldr r3, [pc, #276] ; (7b28 ) + 7a14: a83b add r0, sp, #236 ; 0xec + 7a16: 4798 blx r3 + draw_dsc_sel.bg_color = dsc->sel_color; + 7a18: f8bb 3002 ldrh.w r3, [fp, #2] + 7a1c: f8ad 30ee strh.w r3, [sp, #238] ; 0xee + while(txt[line_start] != '\0') { + 7a20: 9b20 ldr r3, [sp, #128] ; 0x80 + 7a22: 9c0b ldr r4, [sp, #44] ; 0x2c + 7a24: 2bfa cmp r3, #250 ; 0xfa + 7a26: bf88 it hi + 7a28: 23ff movhi r3, #255 ; 0xff + 7a2a: 9309 str r3, [sp, #36] ; 0x24 + 7a2c: b2ab uxth r3, r5 + 7a2e: 9322 str r3, [sp, #136] ; 0x88 + 7a30: f8bd 3018 ldrh.w r3, [sp, #24] + 7a34: 931e str r3, [sp, #120] ; 0x78 + uint16_t par_start = 0; + 7a36: 2300 movs r3, #0 + 7a38: 931d str r3, [sp, #116] ; 0x74 + while(txt[line_start] != '\0') { + 7a3a: 9a04 ldr r2, [sp, #16] + 7a3c: 9b0a ldr r3, [sp, #40] ; 0x28 + 7a3e: 4413 add r3, r2 + 7a40: 931c str r3, [sp, #112] ; 0x70 + 7a42: 9b0a ldr r3, [sp, #40] ; 0x28 + 7a44: 5c9b ldrb r3, [r3, r2] + 7a46: 2b00 cmp r3, #0 + 7a48: d15e bne.n 7b08 +} + 7a4a: b051 add sp, #324 ; 0x144 + 7a4c: ecbd 8b04 vpop {d8-d9} + 7a50: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + _lv_txt_get_size(&p, txt, dsc->font, dsc->letter_space, dsc->line_space, LV_COORD_MAX, + 7a54: 9302 str r3, [sp, #8] + 7a56: f647 4318 movw r3, #31768 ; 0x7c18 + 7a5a: 9301 str r3, [sp, #4] + 7a5c: f9bb 300a ldrsh.w r3, [fp, #10] + 7a60: 9300 str r3, [sp, #0] + 7a62: f8db 2004 ldr.w r2, [fp, #4] + 7a66: f9bb 300c ldrsh.w r3, [fp, #12] + 7a6a: 990a ldr r1, [sp, #40] ; 0x28 + 7a6c: 4d2f ldr r5, [pc, #188] ; (7b2c ) + 7a6e: a83b add r0, sp, #236 ; 0xec + 7a70: 47a8 blx r5 + w = p.x; + 7a72: f9bd 30ec ldrsh.w r3, [sp, #236] ; 0xec + 7a76: e729 b.n 78cc + uint32_t line_start = 0; + 7a78: 9404 str r4, [sp, #16] + 7a7a: e75d b.n 7938 + 7a7c: 2200 movs r2, #0 + 7a7e: 9204 str r2, [sp, #16] + 7a80: e75a b.n 7938 + line_end += _lv_txt_get_next_line(&txt[line_start], font, dsc->letter_space, w, dsc->flag); + 7a82: 9907 ldr r1, [sp, #28] + 7a84: 9300 str r3, [sp, #0] + 7a86: eb02 0801 add.w r8, r2, r1 + 7a8a: ee19 3a10 vmov r3, s18 + 7a8e: f9bb 200c ldrsh.w r2, [fp, #12] + 7a92: ee18 1a10 vmov r1, s16 + 7a96: 4640 mov r0, r8 + 7a98: 47b8 blx r7 + 7a9a: 9b07 ldr r3, [sp, #28] + 7a9c: 4418 add r0, r3 + pos.y += line_height; + 7a9e: 9b06 ldr r3, [sp, #24] + 7aa0: 442b add r3, r5 + 7aa2: b21b sxth r3, r3 + 7aa4: 9306 str r3, [sp, #24] + if(hint && pos.y >= -LV_LABEL_HINT_UPDATE_TH && hint->line_start < 0) { + 7aa6: b174 cbz r4, 7ac6 + 7aa8: f513 6f80 cmn.w r3, #1024 ; 0x400 + 7aac: db0b blt.n 7ac6 + 7aae: 6823 ldr r3, [r4, #0] + 7ab0: 2b00 cmp r3, #0 + 7ab2: da08 bge.n 7ac6 + hint->line_start = line_start; + 7ab4: 9b07 ldr r3, [sp, #28] + 7ab6: 6023 str r3, [r4, #0] + hint->y = pos.y - coords->y1; + 7ab8: 9b05 ldr r3, [sp, #20] + 7aba: 9a06 ldr r2, [sp, #24] + 7abc: f9b3 3002 ldrsh.w r3, [r3, #2] + 7ac0: 1ad2 subs r2, r2, r3 + hint->coord_y = coords->y1; + 7ac2: e9c4 2301 strd r2, r3, [r4, #4] + if(txt[line_start] == '\0') return; + 7ac6: 9b07 ldr r3, [sp, #28] + 7ac8: 9304 str r3, [sp, #16] + 7aca: f898 3000 ldrb.w r3, [r8] + 7ace: 2b00 cmp r3, #0 + 7ad0: d0bb beq.n 7a4a + line_end += _lv_txt_get_next_line(&txt[line_start], font, dsc->letter_space, w, dsc->flag); + 7ad2: 9007 str r0, [sp, #28] + 7ad4: e744 b.n 7960 + else if(dsc->flag & LV_TXT_FLAG_RIGHT) { + 7ad6: 071c lsls r4, r3, #28 + 7ad8: f57f af6b bpl.w 79b2 + line_width = _lv_txt_get_width(&txt[line_start], line_end - line_start, font, dsc->letter_space, dsc->flag); + 7adc: 9a07 ldr r2, [sp, #28] + 7ade: 9904 ldr r1, [sp, #16] + 7ae0: 9300 str r3, [sp, #0] + 7ae2: 1a51 subs r1, r2, r1 + 7ae4: f9bb 300c ldrsh.w r3, [fp, #12] + 7ae8: 4c0d ldr r4, [pc, #52] ; (7b20 ) + 7aea: ee18 2a10 vmov r2, s16 + 7aee: b289 uxth r1, r1 + 7af0: 47a0 blx r4 + 7af2: 9b05 ldr r3, [sp, #20] + 7af4: 9a05 ldr r2, [sp, #20] + 7af6: 889b ldrh r3, [r3, #4] + 7af8: 8812 ldrh r2, [r2, #0] + 7afa: 3301 adds r3, #1 + 7afc: 1a9b subs r3, r3, r2 + pos.x += lv_area_get_width(coords) - line_width; + 7afe: b21b sxth r3, r3 + 7b00: 1a18 subs r0, r3, r0 + 7b02: 9b0b ldr r3, [sp, #44] ; 0x2c + 7b04: 4418 add r0, r3 + 7b06: e752 b.n 79ae + pos.x += x_ofs; + 7b08: 9b24 ldr r3, [sp, #144] ; 0x90 + 7b0a: 441c add r4, r3 + 7b0c: b223 sxth r3, r4 + 7b0e: 930c str r3, [sp, #48] ; 0x30 + i = 0; + 7b10: 2300 movs r3, #0 + 7b12: 9330 str r3, [sp, #192] ; 0xc0 + cmd_state = CMD_STATE_WAIT; + 7b14: 9308 str r3, [sp, #32] + 7b16: e0c2 b.n 7c9e + 7b18: 0000de8d .word 0x0000de8d + 7b1c: 0000ffc5 .word 0x0000ffc5 + 7b20: 0000ff1d .word 0x0000ff1d + 7b24: 000085e1 .word 0x000085e1 + 7b28: 00009ba1 .word 0x00009ba1 + 7b2c: 0001019d .word 0x0001019d + if(sel_start != 0xFFFF && sel_end != 0xFFFF) { + 7b30: 9a10 ldr r2, [sp, #64] ; 0x40 + 7b32: f64f 73ff movw r3, #65535 ; 0xffff + 7b36: 429a cmp r2, r3 + 7b38: d024 beq.n 7b84 + 7b3a: 9a11 ldr r2, [sp, #68] ; 0x44 + 7b3c: 429a cmp r2, r3 + 7b3e: d021 beq.n 7b84 + logical_char_pos = _lv_txt_encoded_get_char_id(txt, line_start + i); + 7b40: 9a04 ldr r2, [sp, #16] + 7b42: 4ba3 ldr r3, [pc, #652] ; (7dd0 ) + 7b44: 980a ldr r0, [sp, #40] ; 0x28 + 7b46: 681b ldr r3, [r3, #0] + 7b48: 4411 add r1, r2 + 7b4a: 4798 blx r3 + 7b4c: b286 uxth r6, r0 + uint32_t letter = _lv_txt_encoded_next(bidi_txt, &i); + 7b4e: 4ca1 ldr r4, [pc, #644] ; (7dd4 ) + 7b50: 981c ldr r0, [sp, #112] ; 0x70 + 7b52: 6823 ldr r3, [r4, #0] + 7b54: a930 add r1, sp, #192 ; 0xc0 + 7b56: 4798 blx r3 + uint32_t letter_next = _lv_txt_encoded_next(&bidi_txt[i], NULL); + 7b58: 9a1c ldr r2, [sp, #112] ; 0x70 + 7b5a: 6823 ldr r3, [r4, #0] + uint32_t letter = _lv_txt_encoded_next(bidi_txt, &i); + 7b5c: 4605 mov r5, r0 + uint32_t letter_next = _lv_txt_encoded_next(&bidi_txt[i], NULL); + 7b5e: 9830 ldr r0, [sp, #192] ; 0xc0 + 7b60: 2100 movs r1, #0 + 7b62: 4410 add r0, r2 + 7b64: 4798 blx r3 + 7b66: f89b 3017 ldrb.w r3, [fp, #23] + if((dsc->flag & LV_TXT_FLAG_RECOLOR) != 0) { + 7b6a: f013 0301 ands.w r3, r3, #1 + uint32_t letter_next = _lv_txt_encoded_next(&bidi_txt[i], NULL); + 7b6e: 4602 mov r2, r0 + if((dsc->flag & LV_TXT_FLAG_RECOLOR) != 0) { + 7b70: f000 8125 beq.w 7dbe + if(letter == (uint32_t)LV_TXT_COLOR_CMD[0]) { + 7b74: 2d23 cmp r5, #35 ; 0x23 + 7b76: d10f bne.n 7b98 + if(cmd_state == CMD_STATE_WAIT) { /*Start char*/ + 7b78: 9908 ldr r1, [sp, #32] + 7b7a: b929 cbnz r1, 7b88 + par_start = i; + 7b7c: f8bd 20c0 ldrh.w r2, [sp, #192] ; 0xc0 + 7b80: 921d str r2, [sp, #116] ; 0x74 + continue; + 7b82: e7c7 b.n 7b14 + uint16_t logical_char_pos = 0; + 7b84: 2600 movs r6, #0 + 7b86: e7e2 b.n 7b4e + else if(cmd_state == CMD_STATE_PAR) { /*Other start char in parameter escaped cmd. char */ + 7b88: 9b08 ldr r3, [sp, #32] + 7b8a: 2b01 cmp r3, #1 + 7b8c: d045 beq.n 7c1a + else if(cmd_state == CMD_STATE_IN) { /*Command end */ + 7b8e: 2b02 cmp r3, #2 + 7b90: f040 8118 bne.w 7dc4 + cmd_state = CMD_STATE_WAIT; + 7b94: 2300 movs r3, #0 + 7b96: e7bd b.n 7b14 + if(cmd_state == CMD_STATE_PAR) { + 7b98: 9b08 ldr r3, [sp, #32] + 7b9a: 2b01 cmp r3, #1 + 7b9c: f040 810f bne.w 7dbe + if(letter == ' ') { + 7ba0: 2d20 cmp r5, #32 + 7ba2: d17c bne.n 7c9e + if(i - par_start == LABEL_RECOLOR_PAR_LENGTH + 1) { + 7ba4: 9b30 ldr r3, [sp, #192] ; 0xc0 + 7ba6: 9a1d ldr r2, [sp, #116] ; 0x74 + 7ba8: 1a9b subs r3, r3, r2 + 7baa: 2b07 cmp r3, #7 + 7bac: d132 bne.n 7c14 + _lv_memcpy_small(buf, &bidi_txt[par_start], LABEL_RECOLOR_PAR_LENGTH); + 7bae: 9b1c ldr r3, [sp, #112] ; 0x70 + 7bb0: 991d ldr r1, [sp, #116] ; 0x74 + 7bb2: 189a adds r2, r3, r2 + 7bb4: 5858 ldr r0, [r3, r1] + 7bb6: 8893 ldrh r3, [r2, #4] + 7bb8: f8ad 30e4 strh.w r3, [sp, #228] ; 0xe4 + r = (hex_char_to_num(buf[0]) << 4) + hex_char_to_num(buf[1]); + 7bbc: 4a86 ldr r2, [pc, #536] ; (7dd8 ) + 7bbe: 9038 str r0, [sp, #224] ; 0xe0 + 7bc0: f3c0 4507 ubfx r5, r0, #16, #8 + 7bc4: f3c0 6407 ubfx r4, r0, #24, #8 + 7bc8: f3c0 2607 ubfx r6, r0, #8, #8 + 7bcc: b2c0 uxtb r0, r0 + 7bce: 4790 blx r2 + 7bd0: 4601 mov r1, r0 + 7bd2: b2f0 uxtb r0, r6 + 7bd4: 4790 blx r2 + 7bd6: eb00 1101 add.w r1, r0, r1, lsl #4 + g = (hex_char_to_num(buf[2]) << 4) + hex_char_to_num(buf[3]); + 7bda: b2e8 uxtb r0, r5 + 7bdc: 4790 blx r2 + 7bde: 4605 mov r5, r0 + 7be0: b2e0 uxtb r0, r4 + 7be2: 4790 blx r2 + 7be4: eb00 1405 add.w r4, r0, r5, lsl #4 + b = (hex_char_to_num(buf[4]) << 4) + hex_char_to_num(buf[5]); + 7be8: f89d 00e4 ldrb.w r0, [sp, #228] ; 0xe4 + 7bec: 4790 blx r2 + 7bee: 4605 mov r5, r0 + 7bf0: f89d 00e5 ldrb.w r0, [sp, #229] ; 0xe5 + 7bf4: 4790 blx r2 + 7bf6: eb00 1005 add.w r0, r0, r5, lsl #4 + 7bfa: f3c0 00c4 ubfx r0, r0, #3, #5 + 7bfe: f3c4 0485 ubfx r4, r4, #2, #6 + 7c02: ea40 1044 orr.w r0, r0, r4, lsl #5 + 7c06: f3c1 01c4 ubfx r1, r1, #3, #5 + 7c0a: ea40 23c1 orr.w r3, r0, r1, lsl #11 + recolor.full = dsc->color.full; + 7c0e: 9321 str r3, [sp, #132] ; 0x84 + cmd_state = CMD_STATE_IN; /*After the parameter the text is in the command*/ + 7c10: 2302 movs r3, #2 + 7c12: e77f b.n 7b14 + recolor.full = dsc->color.full; + 7c14: f8bb 3000 ldrh.w r3, [fp] + 7c18: e7f9 b.n 7c0e + cmd_state = CMD_STATE_WAIT; + 7c1a: 2300 movs r3, #0 + lv_color_t color = dsc->color; + 7c1c: f8bb 4000 ldrh.w r4, [fp] + cmd_state = CMD_STATE_WAIT; + 7c20: 9308 str r3, [sp, #32] + letter_w = lv_font_get_glyph_width(font, letter, letter_next); + 7c22: 4b6e ldr r3, [pc, #440] ; (7ddc ) + 7c24: ee18 0a10 vmov r0, s16 + 7c28: 4629 mov r1, r5 + 7c2a: 4798 blx r3 + if(sel_start != 0xFFFF && sel_end != 0xFFFF) { + 7c2c: 9a10 ldr r2, [sp, #64] ; 0x40 + letter_w = lv_font_get_glyph_width(font, letter, letter_next); + 7c2e: 901f str r0, [sp, #124] ; 0x7c + if(sel_start != 0xFFFF && sel_end != 0xFFFF) { + 7c30: f64f 73ff movw r3, #65535 ; 0xffff + 7c34: 429a cmp r2, r3 + 7c36: d020 beq.n 7c7a + 7c38: 9a11 ldr r2, [sp, #68] ; 0x44 + 7c3a: 429a cmp r2, r3 + 7c3c: d01d beq.n 7c7a + if(logical_char_pos >= sel_start && logical_char_pos < sel_end) { + 7c3e: 9b10 ldr r3, [sp, #64] ; 0x40 + 7c40: 42b3 cmp r3, r6 + 7c42: d81a bhi.n 7c7a + 7c44: 42b2 cmp r2, r6 + 7c46: d918 bls.n 7c7a + sel_coords.x1 = pos.x; + 7c48: 9b0c ldr r3, [sp, #48] ; 0x30 + 7c4a: f8ad 30e0 strh.w r3, [sp, #224] ; 0xe0 + sel_coords.y1 = pos.y; + 7c4e: 9b06 ldr r3, [sp, #24] + 7c50: f8ad 30e2 strh.w r3, [sp, #226] ; 0xe2 + sel_coords.x2 = pos.x + letter_w + dsc->letter_space - 1; + 7c54: f8bb 300c ldrh.w r3, [fp, #12] + 7c58: 9a0c ldr r2, [sp, #48] ; 0x30 + 7c5a: 3b01 subs r3, #1 + 7c5c: 4413 add r3, r2 + 7c5e: 4403 add r3, r0 + 7c60: f8ad 30e4 strh.w r3, [sp, #228] ; 0xe4 + sel_coords.y2 = pos.y + line_height - 1; + 7c64: 9b22 ldr r3, [sp, #136] ; 0x88 + 7c66: 9a06 ldr r2, [sp, #24] + 7c68: 3b01 subs r3, #1 + 7c6a: 4413 add r3, r2 + 7c6c: f8ad 30e6 strh.w r3, [sp, #230] ; 0xe6 + lv_draw_rect(&sel_coords, mask, &draw_dsc_sel); + 7c70: aa3b add r2, sp, #236 ; 0xec + 7c72: 4b5b ldr r3, [pc, #364] ; (7de0 ) + 7c74: 4651 mov r1, sl + 7c76: a838 add r0, sp, #224 ; 0xe0 + 7c78: 4798 blx r3 + lv_draw_letter(&pos, mask, font, letter, color, opa, dsc->blend_mode); + 7c7a: f89b 3019 ldrb.w r3, [fp, #25] + 7c7e: 931b str r3, [sp, #108] ; 0x6c + if(opa < LV_OPA_MIN) return; + 7c80: 9b20 ldr r3, [sp, #128] ; 0x80 + 7c82: 2b04 cmp r3, #4 + 7c84: f200 8485 bhi.w 8592 + if(letter_w > 0) { + 7c88: 9b1f ldr r3, [sp, #124] ; 0x7c + 7c8a: b143 cbz r3, 7c9e + pos.x += letter_w + dsc->letter_space; + 7c8c: f8bb 300c ldrh.w r3, [fp, #12] + 7c90: 9a0c ldr r2, [sp, #48] ; 0x30 + 7c92: 441a add r2, r3 + 7c94: 4613 mov r3, r2 + 7c96: 9a1f ldr r2, [sp, #124] ; 0x7c + 7c98: 441a add r2, r3 + 7c9a: b213 sxth r3, r2 + 7c9c: 930c str r3, [sp, #48] ; 0x30 + while(i < line_end - line_start) { + 7c9e: 9b07 ldr r3, [sp, #28] + 7ca0: 9a04 ldr r2, [sp, #16] + 7ca2: 9930 ldr r1, [sp, #192] ; 0xc0 + 7ca4: 1a9b subs r3, r3, r2 + 7ca6: 428b cmp r3, r1 + 7ca8: f63f af42 bhi.w 7b30 + if(dsc->decor & LV_TEXT_DECOR_STRIKETHROUGH) { + 7cac: f89b 3018 ldrb.w r3, [fp, #24] + 7cb0: 079d lsls r5, r3, #30 + 7cb2: d51f bpl.n 7cf4 + p1.x = pos_x_start; + 7cb4: 9b0b ldr r3, [sp, #44] ; 0x2c + 7cb6: f8ad 30cc strh.w r3, [sp, #204] ; 0xcc + p1.y = pos.y + (dsc->font->line_height / 2) + line_dsc.width / 2; + 7cba: f8db 3004 ldr.w r3, [fp, #4] + lv_draw_line(&p1, &p2, mask, &line_dsc); + 7cbe: 4c49 ldr r4, [pc, #292] ; (7de4 ) + p1.y = pos.y + (dsc->font->line_height / 2) + line_dsc.width / 2; + 7cc0: f9b3 3008 ldrsh.w r3, [r3, #8] + 7cc4: eb03 72d3 add.w r2, r3, r3, lsr #31 + 7cc8: f9bd 30d6 ldrsh.w r3, [sp, #214] ; 0xd6 + 7ccc: eb03 73d3 add.w r3, r3, r3, lsr #31 + 7cd0: 105b asrs r3, r3, #1 + 7cd2: eb03 0362 add.w r3, r3, r2, asr #1 + 7cd6: 9a1e ldr r2, [sp, #120] ; 0x78 + 7cd8: 4413 add r3, r2 + 7cda: b21b sxth r3, r3 + p2.x = pos.x; + 7cdc: 9a0c ldr r2, [sp, #48] ; 0x30 + p1.y = pos.y + (dsc->font->line_height / 2) + line_dsc.width / 2; + 7cde: f8ad 30ce strh.w r3, [sp, #206] ; 0xce + p2.x = pos.x; + 7ce2: f8ad 20e0 strh.w r2, [sp, #224] ; 0xe0 + p2.y = p1.y; + 7ce6: f8ad 30e2 strh.w r3, [sp, #226] ; 0xe2 + lv_draw_line(&p1, &p2, mask, &line_dsc); + 7cea: 4652 mov r2, sl + 7cec: ab35 add r3, sp, #212 ; 0xd4 + 7cee: a938 add r1, sp, #224 ; 0xe0 + 7cf0: a833 add r0, sp, #204 ; 0xcc + 7cf2: 47a0 blx r4 + if(dsc->decor & LV_TEXT_DECOR_UNDERLINE) { + 7cf4: f89b 3018 ldrb.w r3, [fp, #24] + 7cf8: 07dc lsls r4, r3, #31 + 7cfa: d51e bpl.n 7d3a + p1.x = pos_x_start; + 7cfc: 9b0b ldr r3, [sp, #44] ; 0x2c + 7cfe: f8ad 30cc strh.w r3, [sp, #204] ; 0xcc + p1.y = pos.y + dsc->font->line_height - dsc->font->base_line + line_dsc.width / 2 + 1; + 7d02: f9bd 30d6 ldrsh.w r3, [sp, #214] ; 0xd6 + 7d06: f8db 2004 ldr.w r2, [fp, #4] + lv_draw_line(&p1, &p2, mask, &line_dsc); + 7d0a: 4c36 ldr r4, [pc, #216] ; (7de4 ) + p1.y = pos.y + dsc->font->line_height - dsc->font->base_line + line_dsc.width / 2 + 1; + 7d0c: 8911 ldrh r1, [r2, #8] + 7d0e: 8952 ldrh r2, [r2, #10] + 7d10: eb03 73d3 add.w r3, r3, r3, lsr #31 + 7d14: 105b asrs r3, r3, #1 + 7d16: 3301 adds r3, #1 + 7d18: 440b add r3, r1 + 7d1a: 1a9b subs r3, r3, r2 + 7d1c: 9a1e ldr r2, [sp, #120] ; 0x78 + 7d1e: 4413 add r3, r2 + 7d20: b21b sxth r3, r3 + p2.x = pos.x; + 7d22: 9a0c ldr r2, [sp, #48] ; 0x30 + p1.y = pos.y + dsc->font->line_height - dsc->font->base_line + line_dsc.width / 2 + 1; + 7d24: f8ad 30ce strh.w r3, [sp, #206] ; 0xce + p2.x = pos.x; + 7d28: f8ad 20e0 strh.w r2, [sp, #224] ; 0xe0 + p2.y = p1.y; + 7d2c: f8ad 30e2 strh.w r3, [sp, #226] ; 0xe2 + lv_draw_line(&p1, &p2, mask, &line_dsc); + 7d30: 4652 mov r2, sl + 7d32: ab35 add r3, sp, #212 ; 0xd4 + 7d34: a938 add r1, sp, #224 ; 0xe0 + 7d36: a833 add r0, sp, #204 ; 0xcc + 7d38: 47a0 blx r4 + line_end += _lv_txt_get_next_line(&txt[line_start], font, dsc->letter_space, w, dsc->flag); + 7d3a: 9b0a ldr r3, [sp, #40] ; 0x28 + 7d3c: 9a07 ldr r2, [sp, #28] + 7d3e: 4c2a ldr r4, [pc, #168] ; (7de8 ) + 7d40: 189e adds r6, r3, r2 + 7d42: f89b 3017 ldrb.w r3, [fp, #23] + 7d46: 9300 str r3, [sp, #0] + 7d48: ee18 1a10 vmov r1, s16 + 7d4c: ee19 3a10 vmov r3, s18 + 7d50: f9bb 200c ldrsh.w r2, [fp, #12] + 7d54: 4630 mov r0, r6 + 7d56: 47a0 blx r4 + 7d58: 9b07 ldr r3, [sp, #28] + 7d5a: 18c5 adds r5, r0, r3 + pos.x = coords->x1; + 7d5c: 9b05 ldr r3, [sp, #20] + 7d5e: f9b3 4000 ldrsh.w r4, [r3] + if(dsc->flag & LV_TXT_FLAG_CENTER) { + 7d62: f89b 3017 ldrb.w r3, [fp, #23] + line_end += _lv_txt_get_next_line(&txt[line_start], font, dsc->letter_space, w, dsc->flag); + 7d66: 4601 mov r1, r0 + if(dsc->flag & LV_TXT_FLAG_CENTER) { + 7d68: 0758 lsls r0, r3, #29 + 7d6a: f140 83fd bpl.w 8568 + _lv_txt_get_width(&txt[line_start], line_end - line_start, font, dsc->letter_space, dsc->flag); + 7d6e: ee18 2a10 vmov r2, s16 + 7d72: 9300 str r3, [sp, #0] + 7d74: 4630 mov r0, r6 + 7d76: f9bb 300c ldrsh.w r3, [fp, #12] + 7d7a: 4e1c ldr r6, [pc, #112] ; (7dec ) + 7d7c: 47b0 blx r6 + 7d7e: 9b05 ldr r3, [sp, #20] + 7d80: 9a05 ldr r2, [sp, #20] + 7d82: 889b ldrh r3, [r3, #4] + 7d84: 8812 ldrh r2, [r2, #0] + 7d86: 3301 adds r3, #1 + 7d88: 1a9b subs r3, r3, r2 + pos.x += (lv_area_get_width(coords) - line_width) / 2; + 7d8a: b21b sxth r3, r3 + 7d8c: 1a18 subs r0, r3, r0 + 7d8e: eb00 70d0 add.w r0, r0, r0, lsr #31 + 7d92: eb04 0060 add.w r0, r4, r0, asr #1 + pos.x += lv_area_get_width(coords) - line_width; + 7d96: b204 sxth r4, r0 + pos.y += line_height; + 7d98: 9a22 ldr r2, [sp, #136] ; 0x88 + 7d9a: 9b06 ldr r3, [sp, #24] + 7d9c: 4413 add r3, r2 + 7d9e: b21b sxth r3, r3 + 7da0: 9306 str r3, [sp, #24] + if(pos.y > mask->y2) return; + 7da2: 9b1e ldr r3, [sp, #120] ; 0x78 + 7da4: 4413 add r3, r2 + 7da6: b29b uxth r3, r3 + 7da8: 931e str r3, [sp, #120] ; 0x78 + line_start = line_end; + 7daa: 9b07 ldr r3, [sp, #28] + if(pos.y > mask->y2) return; + 7dac: 9a06 ldr r2, [sp, #24] + line_start = line_end; + 7dae: 9304 str r3, [sp, #16] + if(pos.y > mask->y2) return; + 7db0: f9ba 3006 ldrsh.w r3, [sl, #6] + 7db4: 4293 cmp r3, r2 + 7db6: f6ff ae48 blt.w 7a4a + line_end += _lv_txt_get_next_line(&txt[line_start], font, dsc->letter_space, w, dsc->flag); + 7dba: 9507 str r5, [sp, #28] + 7dbc: e63d b.n 7a3a + if(cmd_state == CMD_STATE_IN) color = recolor; + 7dbe: 9b08 ldr r3, [sp, #32] + 7dc0: 2b02 cmp r3, #2 + 7dc2: d002 beq.n 7dca + lv_color_t color = dsc->color; + 7dc4: f8bb 4000 ldrh.w r4, [fp] + 7dc8: e72b b.n 7c22 + 7dca: 9c21 ldr r4, [sp, #132] ; 0x84 + 7dcc: e729 b.n 7c22 + 7dce: bf00 nop + 7dd0: 20000064 .word 0x20000064 + 7dd4: 20000058 .word 0x20000058 + 7dd8: 0000781f .word 0x0000781f + 7ddc: 0000d175 .word 0x0000d175 + 7de0: 00009bed .word 0x00009bed + 7de4: 000085fd .word 0x000085fd + 7de8: 0000ffc5 .word 0x0000ffc5 + 7dec: 0000ff1d .word 0x0000ff1d + if((g.box_h == 0) && (g.box_w == 0)) return; + 7df0: f8bd 20e4 ldrh.w r2, [sp, #228] ; 0xe4 + 7df4: f8bd 10e2 ldrh.w r1, [sp, #226] ; 0xe2 + 7df8: ea52 0301 orrs.w r3, r2, r1 + 7dfc: f43f af44 beq.w 7c88 + int32_t pos_x = pos_p->x + g.ofs_x; + 7e00: 980c ldr r0, [sp, #48] ; 0x30 + 7e02: f9bd 30e6 ldrsh.w r3, [sp, #230] ; 0xe6 + 7e06: 4403 add r3, r0 + 7e08: 930d str r3, [sp, #52] ; 0x34 + if(pos_x + g.box_w < clip_area->x1 || + 7e0a: 9f0d ldr r7, [sp, #52] ; 0x34 + 7e0c: 4439 add r1, r7 + 7e0e: f9ba 7000 ldrsh.w r7, [sl] + int32_t pos_y = pos_p->y + (font_p->line_height - font_p->base_line) - g.box_h - g.ofs_y; + 7e12: ee18 0a10 vmov r0, s16 + 7e16: ee18 3a10 vmov r3, s16 + if(pos_x + g.box_w < clip_area->x1 || + 7e1a: 42b9 cmp r1, r7 + int32_t pos_y = pos_p->y + (font_p->line_height - font_p->base_line) - g.box_h - g.ofs_y; + 7e1c: f9b0 600a ldrsh.w r6, [r0, #10] + 7e20: f9b3 3008 ldrsh.w r3, [r3, #8] + 7e24: f9bd 00e8 ldrsh.w r0, [sp, #232] ; 0xe8 + if(pos_x + g.box_w < clip_area->x1 || + 7e28: f6ff af2e blt.w 7c88 + pos_x > clip_area->x2 || + 7e2c: f9ba 1004 ldrsh.w r1, [sl, #4] + if(pos_x + g.box_w < clip_area->x1 || + 7e30: 9f0d ldr r7, [sp, #52] ; 0x34 + 7e32: 428f cmp r7, r1 + 7e34: f73f af28 bgt.w 7c88 + int32_t pos_y = pos_p->y + (font_p->line_height - font_p->base_line) - g.box_h - g.ofs_y; + 7e38: 9906 ldr r1, [sp, #24] + 7e3a: 1b9b subs r3, r3, r6 + 7e3c: 440b add r3, r1 + 7e3e: 1a9b subs r3, r3, r2 + 7e40: 1a1b subs r3, r3, r0 + pos_y + g.box_h < clip_area->y1 || + 7e42: 441a add r2, r3 + int32_t pos_y = pos_p->y + (font_p->line_height - font_p->base_line) - g.box_h - g.ofs_y; + 7e44: 9316 str r3, [sp, #88] ; 0x58 + pos_y + g.box_h < clip_area->y1 || + 7e46: f9ba 3002 ldrsh.w r3, [sl, #2] + pos_x > clip_area->x2 || + 7e4a: 429a cmp r2, r3 + 7e4c: f6ff af1c blt.w 7c88 + pos_y > clip_area->y2) { + 7e50: f9ba 3006 ldrsh.w r3, [sl, #6] + pos_y + g.box_h < clip_area->y1 || + 7e54: 9a16 ldr r2, [sp, #88] ; 0x58 + 7e56: 429a cmp r2, r3 + 7e58: f73f af16 bgt.w 7c88 + const uint8_t * map_p = lv_font_get_glyph_bitmap(font_p, letter); + 7e5c: ee18 0a10 vmov r0, s16 + 7e60: 4ba9 ldr r3, [pc, #676] ; (8108 ) + 7e62: 4629 mov r1, r5 + 7e64: 4798 blx r3 + if(map_p == NULL) { + 7e66: 4607 mov r7, r0 + 7e68: b928 cbnz r0, 7e76 + LV_LOG_WARN("lv_draw_letter: character's bitmap not found"); + 7e6a: 4ba8 ldr r3, [pc, #672] ; (810c ) + 7e6c: 9300 str r3, [sp, #0] + 7e6e: f240 12b7 movw r2, #439 ; 0x1b7 + 7e72: 4ba7 ldr r3, [pc, #668] ; (8110 ) + 7e74: e39f b.n 85b6 + if(font_p->subpx) { + 7e76: ee18 3a10 vmov r3, s16 + 7e7a: 7b1a ldrb r2, [r3, #12] + draw_letter_subpx(pos_x, pos_y, &g, clip_area, map_p, color, opa, blend_mode); + 7e7c: f9bd 6034 ldrsh.w r6, [sp, #52] ; 0x34 + 7e80: f9bd 8058 ldrsh.w r8, [sp, #88] ; 0x58 + uint32_t bpp = g->bpp; + 7e84: f89d 30ea ldrb.w r3, [sp, #234] ; 0xea + if(font_p->subpx) { + 7e88: 0792 lsls r2, r2, #30 + 7e8a: f000 81fa beq.w 8282 + draw_letter_subpx(pos_x, pos_y, &g, clip_area, map_p, color, opa, blend_mode); + 7e8e: f004 021f and.w r2, r4, #31 + 7e92: 922a str r2, [sp, #168] ; 0xa8 + 7e94: f3c4 1245 ubfx r2, r4, #5, #6 + 7e98: 9226 str r2, [sp, #152] ; 0x98 + if(bpp == 3) bpp = 4; + 7e9a: 2b03 cmp r3, #3 + 7e9c: f3c4 22c4 ubfx r2, r4, #11, #5 + 7ea0: 9225 str r2, [sp, #148] ; 0x94 + 7ea2: f000 80e6 beq.w 8072 + switch(bpp) { + 7ea6: 3b01 subs r3, #1 + 7ea8: 2b07 cmp r3, #7 + 7eaa: f200 80d7 bhi.w 805c + 7eae: e8df f013 tbh [pc, r3, lsl #1] + 7eb2: 00db .short 0x00db + 7eb4: 00d50008 .word 0x00d50008 + 7eb8: 00d500e0 .word 0x00d500e0 + 7ebc: 00d500d5 .word 0x00d500d5 + 7ec0: 00d0 .short 0x00d0 + 7ec2: 23c0 movs r3, #192 ; 0xc0 + 7ec4: 9313 str r3, [sp, #76] ; 0x4c + 7ec6: 4b93 ldr r3, [pc, #588] ; (8114 ) + 7ec8: 2402 movs r4, #2 + bpp_opa_table = _lv_bpp4_opa_table; + 7eca: 9314 str r3, [sp, #80] ; 0x50 + int32_t box_w = g->box_w; + 7ecc: f8bd 30e2 ldrh.w r3, [sp, #226] ; 0xe2 + 7ed0: 9317 str r3, [sp, #92] ; 0x5c + int32_t width_bit = box_w * bpp; /*Letter width in bits*/ + 7ed2: fb04 f103 mul.w r1, r4, r3 + int32_t col_start = pos_x >= clip_area->x1 ? 0 : (clip_area->x1 - pos_x) * 3; + 7ed6: f9ba 3000 ldrsh.w r3, [sl] + int32_t col_end = pos_x + box_w / 3 <= clip_area->x2 ? box_w : (clip_area->x2 - pos_x + 1) * 3; + 7eda: 9d17 ldr r5, [sp, #92] ; 0x5c + int32_t box_h = g->box_h; + 7edc: f8bd 20e4 ldrh.w r2, [sp, #228] ; 0xe4 + int32_t col_start = pos_x >= clip_area->x1 ? 0 : (clip_area->x1 - pos_x) * 3; + 7ee0: 42b3 cmp r3, r6 + 7ee2: bfc6 itte gt + 7ee4: 1b9b subgt r3, r3, r6 + 7ee6: eb03 0343 addgt.w r3, r3, r3, lsl #1 + 7eea: 2300 movle r3, #0 + 7eec: 9312 str r3, [sp, #72] ; 0x48 + int32_t col_end = pos_x + box_w / 3 <= clip_area->x2 ? box_w : (clip_area->x2 - pos_x + 1) * 3; + 7eee: f9ba 3004 ldrsh.w r3, [sl, #4] + 7ef2: 2003 movs r0, #3 + 7ef4: fbb5 f0f0 udiv r0, r5, r0 + 7ef8: 4430 add r0, r6 + 7efa: 4298 cmp r0, r3 + 7efc: bfc5 ittet gt + 7efe: 1b9b subgt r3, r3, r6 + 7f00: 3301 addgt r3, #1 + 7f02: 9b17 ldrle r3, [sp, #92] ; 0x5c + 7f04: eb03 0343 addgt.w r3, r3, r3, lsl #1 + 7f08: 9319 str r3, [sp, #100] ; 0x64 + int32_t row_start = pos_y >= clip_area->y1 ? 0 : clip_area->y1 - pos_y; + 7f0a: f9ba 3002 ldrsh.w r3, [sl, #2] + 7f0e: 4543 cmp r3, r8 + 7f10: bfcc ite gt + 7f12: eba3 0308 subgt.w r3, r3, r8 + 7f16: 2300 movle r3, #0 + 7f18: 930e str r3, [sp, #56] ; 0x38 + int32_t row_end = pos_y + box_h <= clip_area->y2 ? box_h : clip_area->y2 - pos_y + 1; + 7f1a: f9ba 3006 ldrsh.w r3, [sl, #6] + 7f1e: eb02 0008 add.w r0, r2, r8 + 7f22: 4298 cmp r0, r3 + 7f24: bfc2 ittt gt + 7f26: eba3 0308 subgt.w r3, r3, r8 + 7f2a: 3301 addgt r3, #1 + 7f2c: 9323 strgt r3, [sp, #140] ; 0x8c + int32_t bit_ofs = (row_start * width_bit) + (col_start * bpp); + 7f2e: 9b12 ldr r3, [sp, #72] ; 0x48 + 7f30: 980e ldr r0, [sp, #56] ; 0x38 + int32_t row_end = pos_y + box_h <= clip_area->y2 ? box_h : clip_area->y2 - pos_y + 1; + 7f32: bfd8 it le + 7f34: 9223 strle r2, [sp, #140] ; 0x8c + int32_t bit_ofs = (row_start * width_bit) + (col_start * bpp); + 7f36: 4363 muls r3, r4 + 7f38: fb00 3301 mla r3, r0, r1, r3 + map_p += bit_ofs >> 3; + 7f3c: eb07 01e3 add.w r1, r7, r3, asr #3 + col_bit = bit_ofs & 0x7; /* "& 0x7" equals to "% 8" just faster */ + 7f40: f003 0307 and.w r3, r3, #7 + 7f44: 930f str r3, [sp, #60] ; 0x3c + int32_t mask_buf_size = box_w * box_h > LV_HOR_RES_MAX ? LV_HOR_RES_MAX : g->box_w * g->box_h; + 7f46: 9b17 ldr r3, [sp, #92] ; 0x5c + lv_opa_t * mask_buf = _lv_mem_buf_get(mask_buf_size); + 7f48: 4f73 ldr r7, [pc, #460] ; (8118 ) + map_p += bit_ofs >> 3; + 7f4a: 911a str r1, [sp, #104] ; 0x68 + int32_t mask_buf_size = box_w * box_h > LV_HOR_RES_MAX ? LV_HOR_RES_MAX : g->box_w * g->box_h; + 7f4c: 4353 muls r3, r2 + 7f4e: f5b3 7ff0 cmp.w r3, #480 ; 0x1e0 + 7f52: bfa8 it ge + 7f54: f44f 73f0 movge.w r3, #480 ; 0x1e0 + lv_opa_t * mask_buf = _lv_mem_buf_get(mask_buf_size); + 7f58: 4618 mov r0, r3 + 7f5a: 9318 str r3, [sp, #96] ; 0x60 + 7f5c: 47b8 blx r7 + lv_color_t * color_buf = _lv_mem_buf_get(mask_buf_size * sizeof(lv_color_t)); + 7f5e: 9b18 ldr r3, [sp, #96] ; 0x60 + lv_opa_t * mask_buf = _lv_mem_buf_get(mask_buf_size); + 7f60: 4605 mov r5, r0 + lv_color_t * color_buf = _lv_mem_buf_get(mask_buf_size * sizeof(lv_color_t)); + 7f62: 0058 lsls r0, r3, #1 + 7f64: 47b8 blx r7 + lv_disp_t * disp = _lv_refr_get_disp_refreshing(); + 7f66: 4b6d ldr r3, [pc, #436] ; (811c ) + lv_color_t * color_buf = _lv_mem_buf_get(mask_buf_size * sizeof(lv_color_t)); + 7f68: ee08 0a90 vmov s17, r0 + lv_disp_t * disp = _lv_refr_get_disp_refreshing(); + 7f6c: 4798 blx r3 + lv_disp_buf_t * vdb = lv_disp_get_buf(disp); + 7f6e: 4b6c ldr r3, [pc, #432] ; (8120 ) + 7f70: 4798 blx r3 + 7f72: f8b0 9014 ldrh.w r9, [r0, #20] + 7f76: f9b0 c010 ldrsh.w ip, [r0, #16] + vdb_buf_tmp += (row_start * vdb_width) + col_start / 3; + 7f7a: 9b12 ldr r3, [sp, #72] ; 0x48 + lv_color_t * vdb_buf_tmp = vdb->buf_act; + 7f7c: f8d0 e008 ldr.w lr, [r0, #8] + vdb_buf_tmp += (row_start * vdb_width) + col_start / 3; + 7f80: 2203 movs r2, #3 + 7f82: f109 0901 add.w r9, r9, #1 + 7f86: fb93 f1f2 sdiv r1, r3, r2 + vdb_buf_tmp += ((pos_y - vdb->area.y1) * vdb_width) + pos_x - vdb->area.x1; + 7f8a: f9b0 3012 ldrsh.w r3, [r0, #18] + vdb_buf_tmp += (row_start * vdb_width) + col_start / 3; + 7f8e: 980e ldr r0, [sp, #56] ; 0x38 + 7f90: eba9 090c sub.w r9, r9, ip + 7f94: fa0f f989 sxth.w r9, r9 + vdb_buf_tmp += ((pos_y - vdb->area.y1) * vdb_width) + pos_x - vdb->area.x1; + 7f98: eba8 0303 sub.w r3, r8, r3 + 7f9c: fb09 6303 mla r3, r9, r3, r6 + vdb_buf_tmp += (row_start * vdb_width) + col_start / 3; + 7fa0: fb09 1000 mla r0, r9, r0, r1 + vdb_buf_tmp += ((pos_y - vdb->area.y1) * vdb_width) + pos_x - vdb->area.x1; + 7fa4: eba3 030c sub.w r3, r3, ip + vdb_buf_tmp += (row_start * vdb_width) + col_start / 3; + 7fa8: 4403 add r3, r0 + 7faa: eb0e 0343 add.w r3, lr, r3, lsl #1 + map_area.x1 = col_start / 3 + pos_x; + 7fae: 980d ldr r0, [sp, #52] ; 0x34 + vdb_buf_tmp += (row_start * vdb_width) + col_start / 3; + 7fb0: 9315 str r3, [sp, #84] ; 0x54 + map_area.x1 = col_start / 3 + pos_x; + 7fb2: f8bd 3034 ldrh.w r3, [sp, #52] ; 0x34 + 7fb6: fa11 f180 uxtah r1, r1, r0 + map_area.x2 = col_end / 3 + pos_x - 1; + 7fba: 3b01 subs r3, #1 + map_area.x1 = col_start / 3 + pos_x; + 7fbc: f8ad 10cc strh.w r1, [sp, #204] ; 0xcc + map_area.x2 = col_end / 3 + pos_x - 1; + 7fc0: 9919 ldr r1, [sp, #100] ; 0x64 + 7fc2: fb91 f2f2 sdiv r2, r1, r2 + 7fc6: 441a add r2, r3 + 7fc8: f8ad 20d0 strh.w r2, [sp, #208] ; 0xd0 + map_area.y1 = row_start + pos_y; + 7fcc: 9b16 ldr r3, [sp, #88] ; 0x58 + 7fce: 9a0e ldr r2, [sp, #56] ; 0x38 + 7fd0: 4413 add r3, r2 + 7fd2: b21b sxth r3, r3 + 7fd4: f8ad 30ce strh.w r3, [sp, #206] ; 0xce + map_area.y2 = map_area.y1; + 7fd8: f8ad 30d2 strh.w r3, [sp, #210] ; 0xd2 + uint8_t other_mask_cnt = lv_draw_mask_get_cnt(); + 7fdc: 4b51 ldr r3, [pc, #324] ; (8124 ) + 7fde: 4798 blx r3 + if((int32_t) mask_p + (col_end - col_start) < mask_buf_size) { + 7fe0: 9a12 ldr r2, [sp, #72] ; 0x48 + 7fe2: 9b19 ldr r3, [sp, #100] ; 0x64 + uint8_t other_mask_cnt = lv_draw_mask_get_cnt(); + 7fe4: 9027 str r0, [sp, #156] ; 0x9c + if((int32_t) mask_p + (col_end - col_start) < mask_buf_size) { + 7fe6: 1a9b subs r3, r3, r2 + 7fe8: 9316 str r3, [sp, #88] ; 0x58 + col_bit += ((box_w - col_end) + col_start) * bpp; + 7fea: 9b17 ldr r3, [sp, #92] ; 0x5c + 7fec: 4413 add r3, r2 + 7fee: 9a19 ldr r2, [sp, #100] ; 0x64 + 7ff0: 1a9b subs r3, r3, r2 + 7ff2: 4363 muls r3, r4 + vdb_buf_tmp += vdb_width - (col_end - col_start) / 3; + 7ff4: 9a16 ldr r2, [sp, #88] ; 0x58 + col_bit += ((box_w - col_end) + col_start) * bpp; + 7ff6: 9328 str r3, [sp, #160] ; 0xa0 + vdb_buf_tmp += vdb_width - (col_end - col_start) / 3; + 7ff8: f06f 0302 mvn.w r3, #2 + 7ffc: fb92 f3f3 sdiv r3, r2, r3 + 8000: 444b add r3, r9 + 8002: 005b lsls r3, r3, #1 + 8004: 9329 str r3, [sp, #164] ; 0xa4 + int32_t mask_p = 0; + 8006: 2300 movs r3, #0 + 8008: 461f mov r7, r3 + if(col_bit < (int32_t) (8 - bpp)) { + 800a: f1c4 0308 rsb r3, r4, #8 + 800e: 932d str r3, [sp, #180] ; 0xb4 + for(row = row_start ; row < row_end; row++) { + 8010: 9b0e ldr r3, [sp, #56] ; 0x38 + 8012: 9a23 ldr r2, [sp, #140] ; 0x8c + 8014: 4293 cmp r3, r2 + 8016: db31 blt.n 807c + if(map_area.y1 != map_area.y2) { + 8018: f9bd 30d2 ldrsh.w r3, [sp, #210] ; 0xd2 + 801c: f9bd 20ce ldrsh.w r2, [sp, #206] ; 0xce + 8020: 429a cmp r2, r3 + 8022: d00f beq.n 8044 + map_area.y2--; + 8024: 3b01 subs r3, #1 + 8026: f8ad 30d2 strh.w r3, [sp, #210] ; 0xd2 + _lv_blend_map(clip_area, &map_area, color_buf, mask_buf, LV_DRAW_MASK_RES_CHANGED, opa, blend_mode); + 802a: 9b1b ldr r3, [sp, #108] ; 0x6c + 802c: 9302 str r3, [sp, #8] + 802e: 9b09 ldr r3, [sp, #36] ; 0x24 + 8030: 9301 str r3, [sp, #4] + 8032: 2302 movs r3, #2 + 8034: 9300 str r3, [sp, #0] + 8036: ee18 2a90 vmov r2, s17 + 803a: 4c3b ldr r4, [pc, #236] ; (8128 ) + 803c: 462b mov r3, r5 + 803e: a933 add r1, sp, #204 ; 0xcc + 8040: 4650 mov r0, sl + 8042: 47a0 blx r4 + _lv_mem_buf_release(mask_buf); + 8044: 4628 mov r0, r5 + 8046: 4c39 ldr r4, [pc, #228] ; (812c ) + 8048: 47a0 blx r4 + _lv_mem_buf_release(color_buf); + 804a: ee18 0a90 vmov r0, s17 + 804e: 47a0 blx r4 + 8050: e61a b.n 7c88 + bitmask_init = 0xFF; + 8052: 23ff movs r3, #255 ; 0xff + 8054: 9313 str r3, [sp, #76] ; 0x4c + uint32_t bpp = g->bpp; + 8056: 2408 movs r4, #8 + bpp_opa_table = _lv_bpp8_opa_table; + 8058: 4b35 ldr r3, [pc, #212] ; (8130 ) + 805a: e736 b.n 7eca + LV_LOG_WARN("lv_draw_letter: invalid bpp not found"); + 805c: 4b35 ldr r3, [pc, #212] ; (8134 ) + 805e: 9300 str r3, [sp, #0] + 8060: f240 227a movw r2, #634 ; 0x27a + 8064: 4b34 ldr r3, [pc, #208] ; (8138 ) + 8066: e2a6 b.n 85b6 + bitmask_init = 0x80; + 8068: 2380 movs r3, #128 ; 0x80 + 806a: 9313 str r3, [sp, #76] ; 0x4c + uint32_t bpp = g->bpp; + 806c: 2401 movs r4, #1 + bpp_opa_table = _lv_bpp1_opa_table; + 806e: 4b33 ldr r3, [pc, #204] ; (813c ) + 8070: e72b b.n 7eca + bitmask_init = 0xF0; + 8072: 23f0 movs r3, #240 ; 0xf0 + 8074: 9313 str r3, [sp, #76] ; 0x4c + switch(bpp) { + 8076: 2404 movs r4, #4 + bpp_opa_table = _lv_bpp4_opa_table; + 8078: 4b31 ldr r3, [pc, #196] ; (8140 ) + 807a: e726 b.n 7eca + bitmask = bitmask_init >> col_bit; + 807c: 9a0f ldr r2, [sp, #60] ; 0x3c + 807e: 9b13 ldr r3, [sp, #76] ; 0x4c + for(col = col_start; col < col_end; col++) { + 8080: f8dd e048 ldr.w lr, [sp, #72] ; 0x48 + bitmask = bitmask_init >> col_bit; + 8084: fa23 fc02 lsr.w ip, r3, r2 + for(col = col_start; col < col_end; col++) { + 8088: 463e mov r6, r7 + uint32_t subpx_cnt = 0; + 808a: 2200 movs r2, #0 + for(col = col_start; col < col_end; col++) { + 808c: 9b19 ldr r3, [sp, #100] ; 0x64 + 808e: 4573 cmp r3, lr + 8090: dc5c bgt.n 814c + if(other_mask_cnt) { + 8092: 9b27 ldr r3, [sp, #156] ; 0x9c + 8094: b1cb cbz r3, 80ca + lv_draw_mask_res_t mask_res = lv_draw_mask_apply(mask_buf + mask_p_start, map_area.x1, map_area.y2, + 8096: 463b mov r3, r7 + 8098: 442b add r3, r5 + 809a: 4698 mov r8, r3 + 809c: f8bd 30d0 ldrh.w r3, [sp, #208] ; 0xd0 + 80a0: f9bd 10cc ldrsh.w r1, [sp, #204] ; 0xcc + 80a4: f9bd 20d2 ldrsh.w r2, [sp, #210] ; 0xd2 + 80a8: 4f26 ldr r7, [pc, #152] ; (8144 ) + 80aa: 3301 adds r3, #1 + 80ac: 1a5b subs r3, r3, r1 + 80ae: b21b sxth r3, r3 + 80b0: 4640 mov r0, r8 + 80b2: 47b8 blx r7 + if(mask_res == LV_DRAW_MASK_RES_TRANSP) { + 80b4: b948 cbnz r0, 80ca + 80b6: f8bd 10d0 ldrh.w r1, [sp, #208] ; 0xd0 + 80ba: f8bd 30cc ldrh.w r3, [sp, #204] ; 0xcc + 80be: 3101 adds r1, #1 + 80c0: 1ac9 subs r1, r1, r3 + _lv_memset_00(mask_buf + mask_p_start, lv_area_get_width(&map_area)); + 80c2: b209 sxth r1, r1 + 80c4: 4b20 ldr r3, [pc, #128] ; (8148 ) + 80c6: 4640 mov r0, r8 + 80c8: 4798 blx r3 + if((int32_t) mask_p + (col_end - col_start) < mask_buf_size) { + 80ca: 9b16 ldr r3, [sp, #88] ; 0x58 + 80cc: 9a18 ldr r2, [sp, #96] ; 0x60 + 80ce: 18f3 adds r3, r6, r3 + 80d0: 429a cmp r2, r3 + 80d2: f340 80c1 ble.w 8258 + map_area.y2 ++; + 80d6: f8bd 30d2 ldrh.w r3, [sp, #210] ; 0xd2 + 80da: 3301 adds r3, #1 + 80dc: b21b sxth r3, r3 + col_bit += ((box_w - col_end) + col_start) * bpp; + 80de: 9a28 ldr r2, [sp, #160] ; 0xa0 + map_area.y2 ++; + 80e0: f8ad 30d2 strh.w r3, [sp, #210] ; 0xd2 + col_bit += ((box_w - col_end) + col_start) * bpp; + 80e4: 9b0f ldr r3, [sp, #60] ; 0x3c + 80e6: 4413 add r3, r2 + map_p += (col_bit >> 3); + 80e8: 9a1a ldr r2, [sp, #104] ; 0x68 + 80ea: eb02 02e3 add.w r2, r2, r3, asr #3 + col_bit = col_bit & 0x7; + 80ee: f003 0307 and.w r3, r3, #7 + map_p += (col_bit >> 3); + 80f2: 921a str r2, [sp, #104] ; 0x68 + col_bit = col_bit & 0x7; + 80f4: 930f str r3, [sp, #60] ; 0x3c + vdb_buf_tmp += vdb_width - (col_end - col_start) / 3; + 80f6: 9a29 ldr r2, [sp, #164] ; 0xa4 + 80f8: 9b15 ldr r3, [sp, #84] ; 0x54 + 80fa: 4413 add r3, r2 + 80fc: 9315 str r3, [sp, #84] ; 0x54 + for(row = row_start ; row < row_end; row++) { + 80fe: 9b0e ldr r3, [sp, #56] ; 0x38 + 8100: 3301 adds r3, #1 + 8102: 930e str r3, [sp, #56] ; 0x38 + 8104: 4637 mov r7, r6 + 8106: e783 b.n 8010 + 8108: 0000d165 .word 0x0000d165 + 810c: 0001fb21 .word 0x0001fb21 + 8110: 0001fca6 .word 0x0001fca6 + 8114: 0001fb92 .word 0x0001fb92 + 8118: 0000eeb5 .word 0x0000eeb5 + 811c: 00004fe9 .word 0x00004fe9 + 8120: 0000d9e1 .word 0x0000d9e1 + 8124: 000097f1 .word 0x000097f1 + 8128: 000067fd .word 0x000067fd + 812c: 0000eb69 .word 0x0000eb69 + 8130: 0001fba6 .word 0x0001fba6 + 8134: 0001fb4e .word 0x0001fb4e + 8138: 0001fcb5 .word 0x0001fcb5 + 813c: 0001fb90 .word 0x0001fb90 + 8140: 0001fb96 .word 0x0001fb96 + 8144: 00009761 .word 0x00009761 + 8148: 0000f019 .word 0x0000f019 + letter_px = (*map_p & bitmask) >> (8 - col_bit - bpp); + 814c: 9b0f ldr r3, [sp, #60] ; 0x3c + 814e: 18e3 adds r3, r4, r3 + 8150: 930d str r3, [sp, #52] ; 0x34 + 8152: 9b1a ldr r3, [sp, #104] ; 0x68 + 8154: 990d ldr r1, [sp, #52] ; 0x34 + 8156: 781b ldrb r3, [r3, #0] + 8158: f1c1 0108 rsb r1, r1, #8 + 815c: ea03 030c and.w r3, r3, ip + if(letter_px != 0) { + 8160: 40cb lsrs r3, r1 + 8162: d007 beq.n 8174 + if(opa == LV_OPA_COVER) { + 8164: 9909 ldr r1, [sp, #36] ; 0x24 + 8166: 29ff cmp r1, #255 ; 0xff + 8168: d160 bne.n 822c + px_opa = bpp == 8 ? letter_px : bpp_opa_table[letter_px]; + 816a: 2c08 cmp r4, #8 + 816c: bf1a itte ne + 816e: 9914 ldrne r1, [sp, #80] ; 0x50 + 8170: 5ccb ldrbne r3, [r1, r3] + letter_px = (*map_p & bitmask) >> (8 - col_bit - bpp); + 8172: b2db uxtbeq r3, r3 + font_rgb[subpx_cnt] = px_opa; + 8174: f502 71a0 add.w r1, r2, #320 ; 0x140 + 8178: 4469 add r1, sp + subpx_cnt ++; + 817a: 3201 adds r2, #1 + if(subpx_cnt == 3) { + 817c: 2a03 cmp r2, #3 + font_rgb[subpx_cnt] = px_opa; + 817e: f801 3c84 strb.w r3, [r1, #-132] + if(subpx_cnt == 3) { + 8182: d148 bne.n 8216 + uint8_t bg_rgb[3] = {vdb_buf_tmp->ch.red, vdb_buf_tmp->ch.green, vdb_buf_tmp->ch.blue}; + 8184: 9a15 ldr r2, [sp, #84] ; 0x54 + res_color.ch.red = (uint32_t)((uint16_t)txt_rgb[0] * font_rgb[0] + (bg_rgb[0] * (255 - font_rgb[0]))) >> 8; + 8186: f89d 30bc ldrb.w r3, [sp, #188] ; 0xbc + uint8_t bg_rgb[3] = {vdb_buf_tmp->ch.red, vdb_buf_tmp->ch.green, vdb_buf_tmp->ch.blue}; + 818a: 7851 ldrb r1, [r2, #1] + res_color.ch.red = (uint32_t)((uint16_t)txt_rgb[0] * font_rgb[0] + (bg_rgb[0] * (255 - font_rgb[0]))) >> 8; + 818c: 9a25 ldr r2, [sp, #148] ; 0x94 + res_color.ch.blue = (uint32_t)((uint16_t)txt_rgb[2] * font_rgb[2] + (bg_rgb[2] * (255 - font_rgb[2]))) >> 8; + 818e: f89d 90be ldrb.w r9, [sp, #190] ; 0xbe + res_color.ch.red = (uint32_t)((uint16_t)txt_rgb[0] * font_rgb[0] + (bg_rgb[0] * (255 - font_rgb[0]))) >> 8; + 8192: f1c3 00ff rsb r0, r3, #255 ; 0xff + 8196: 08c9 lsrs r1, r1, #3 + 8198: fb13 f202 smulbb r2, r3, r2 + 819c: fb00 2201 mla r2, r0, r1, r2 + 81a0: 0a12 lsrs r2, r2, #8 + 81a2: 9217 str r2, [sp, #92] ; 0x5c + uint8_t bg_rgb[3] = {vdb_buf_tmp->ch.red, vdb_buf_tmp->ch.green, vdb_buf_tmp->ch.blue}; + 81a4: 9a15 ldr r2, [sp, #84] ; 0x54 + 81a6: 7810 ldrb r0, [r2, #0] + res_color.ch.blue = (uint32_t)((uint16_t)txt_rgb[2] * font_rgb[2] + (bg_rgb[2] * (255 - font_rgb[2]))) >> 8; + 81a8: 9a2a ldr r2, [sp, #168] ; 0xa8 + 81aa: f000 001f and.w r0, r0, #31 + 81ae: f1c9 08ff rsb r8, r9, #255 ; 0xff + 81b2: fb19 f102 smulbb r1, r9, r2 + 81b6: fb08 1200 mla r2, r8, r0, r1 + 81ba: 922b str r2, [sp, #172] ; 0xac + uint8_t bg_rgb[3] = {vdb_buf_tmp->ch.red, vdb_buf_tmp->ch.green, vdb_buf_tmp->ch.blue}; + 81bc: 9a15 ldr r2, [sp, #84] ; 0x54 + res_color.ch.green = (uint32_t)((uint32_t)txt_rgb[1] * font_rgb[1] + (bg_rgb[1] * (255 - font_rgb[1]))) >> 8; + 81be: f89d 80bd ldrb.w r8, [sp, #189] ; 0xbd + uint8_t bg_rgb[3] = {vdb_buf_tmp->ch.red, vdb_buf_tmp->ch.green, vdb_buf_tmp->ch.blue}; + 81c2: f832 0b02 ldrh.w r0, [r2], #2 + 81c6: 9215 str r2, [sp, #84] ; 0x54 + res_color.ch.green = (uint32_t)((uint32_t)txt_rgb[1] * font_rgb[1] + (bg_rgb[1] * (255 - font_rgb[1]))) >> 8; + 81c8: f3c0 1245 ubfx r2, r0, #5, #6 + 81cc: 4611 mov r1, r2 + 81ce: f1c8 02ff rsb r2, r8, #255 ; 0xff + if(font_rgb[0] == 0 && font_rgb[1] == 0 && font_rgb[2] == 0) mask_buf[mask_p] = LV_OPA_TRANSP; + 81d2: ea43 0309 orr.w r3, r3, r9 + res_color.ch.green = (uint32_t)((uint32_t)txt_rgb[1] * font_rgb[1] + (bg_rgb[1] * (255 - font_rgb[1]))) >> 8; + 81d6: 922c str r2, [sp, #176] ; 0xb0 + 81d8: 9a26 ldr r2, [sp, #152] ; 0x98 + if(font_rgb[0] == 0 && font_rgb[1] == 0 && font_rgb[2] == 0) mask_buf[mask_p] = LV_OPA_TRANSP; + 81da: ea58 0303 orrs.w r3, r8, r3 + res_color.ch.green = (uint32_t)((uint32_t)txt_rgb[1] * font_rgb[1] + (bg_rgb[1] * (255 - font_rgb[1]))) >> 8; + 81de: fb18 f002 smulbb r0, r8, r2 + if(font_rgb[0] == 0 && font_rgb[1] == 0 && font_rgb[2] == 0) mask_buf[mask_p] = LV_OPA_TRANSP; + 81e2: bf18 it ne + 81e4: f04f 33ff movne.w r3, #4294967295 ; 0xffffffff + res_color.ch.green = (uint32_t)((uint32_t)txt_rgb[1] * font_rgb[1] + (bg_rgb[1] * (255 - font_rgb[1]))) >> 8; + 81e8: 460a mov r2, r1 + if(font_rgb[0] == 0 && font_rgb[1] == 0 && font_rgb[2] == 0) mask_buf[mask_p] = LV_OPA_TRANSP; + 81ea: bf08 it eq + 81ec: 2300 moveq r3, #0 + res_color.ch.green = (uint32_t)((uint32_t)txt_rgb[1] * font_rgb[1] + (bg_rgb[1] * (255 - font_rgb[1]))) >> 8; + 81ee: 992c ldr r1, [sp, #176] ; 0xb0 + if(font_rgb[0] == 0 && font_rgb[1] == 0 && font_rgb[2] == 0) mask_buf[mask_p] = LV_OPA_TRANSP; + 81f0: 55ab strb r3, [r5, r6] + color_buf[mask_p] = res_color; + 81f2: 9b2b ldr r3, [sp, #172] ; 0xac + res_color.ch.green = (uint32_t)((uint32_t)txt_rgb[1] * font_rgb[1] + (bg_rgb[1] * (255 - font_rgb[1]))) >> 8; + 81f4: fb01 0002 mla r0, r1, r2, r0 + color_buf[mask_p] = res_color; + 81f8: f3c0 2005 ubfx r0, r0, #8, #6 + 81fc: f3c3 2104 ubfx r1, r3, #8, #5 + 8200: 9b17 ldr r3, [sp, #92] ; 0x5c + 8202: ea41 1140 orr.w r1, r1, r0, lsl #5 + 8206: ea41 21c3 orr.w r1, r1, r3, lsl #11 + 820a: ee18 3a90 vmov r3, s17 + subpx_cnt = 0; + 820e: 2200 movs r2, #0 + color_buf[mask_p] = res_color; + 8210: f823 1016 strh.w r1, [r3, r6, lsl #1] + mask_p++; + 8214: 3601 adds r6, #1 + if(col_bit < (int32_t) (8 - bpp)) { + 8216: 9b0f ldr r3, [sp, #60] ; 0x3c + 8218: 992d ldr r1, [sp, #180] ; 0xb4 + 821a: 428b cmp r3, r1 + 821c: da14 bge.n 8248 + col_bit += bpp; + 821e: 9b0d ldr r3, [sp, #52] ; 0x34 + 8220: 930f str r3, [sp, #60] ; 0x3c + bitmask = bitmask >> bpp; + 8222: fa2c fc04 lsr.w ip, ip, r4 + for(col = col_start; col < col_end; col++) { + 8226: f10e 0e01 add.w lr, lr, #1 + 822a: e72f b.n 808c + px_opa = bpp == 8 ? (uint32_t)((uint32_t)letter_px * opa) >> 8 + 822c: 2c08 cmp r4, #8 + : (uint32_t)((uint32_t)bpp_opa_table[letter_px] * opa) >> 8; + 822e: bf17 itett ne + 8230: 9914 ldrne r1, [sp, #80] ; 0x50 + px_opa = bpp == 8 ? (uint32_t)((uint32_t)letter_px * opa) >> 8 + 8232: 9909 ldreq r1, [sp, #36] ; 0x24 + : (uint32_t)((uint32_t)bpp_opa_table[letter_px] * opa) >> 8; + 8234: 5ccb ldrbne r3, [r1, r3] + 8236: 9909 ldrne r1, [sp, #36] ; 0x24 + px_opa = bpp == 8 ? (uint32_t)((uint32_t)letter_px * opa) >> 8 + 8238: bf0b itete eq + 823a: 434b muleq r3, r1 + : (uint32_t)((uint32_t)bpp_opa_table[letter_px] * opa) >> 8; + 823c: fb13 f301 smulbbne r3, r3, r1 + px_opa = bpp == 8 ? (uint32_t)((uint32_t)letter_px * opa) >> 8 + 8240: f3c3 2307 ubfxeq r3, r3, #8, #8 + 8244: 0a1b lsrne r3, r3, #8 + 8246: e795 b.n 8174 + map_p++; + 8248: 9b1a ldr r3, [sp, #104] ; 0x68 + bitmask = bitmask_init; + 824a: f8dd c04c ldr.w ip, [sp, #76] ; 0x4c + map_p++; + 824e: 3301 adds r3, #1 + 8250: 931a str r3, [sp, #104] ; 0x68 + col_bit = 0; + 8252: 2300 movs r3, #0 + 8254: 930f str r3, [sp, #60] ; 0x3c + 8256: e7e6 b.n 8226 + _lv_blend_map(clip_area, &map_area, color_buf, mask_buf, LV_DRAW_MASK_RES_CHANGED, opa, blend_mode); + 8258: 9b1b ldr r3, [sp, #108] ; 0x6c + 825a: 9302 str r3, [sp, #8] + 825c: 9b09 ldr r3, [sp, #36] ; 0x24 + 825e: 9301 str r3, [sp, #4] + 8260: 2302 movs r3, #2 + 8262: 4ea7 ldr r6, [pc, #668] ; (8500 ) + 8264: 9300 str r3, [sp, #0] + 8266: ee18 2a90 vmov r2, s17 + 826a: 462b mov r3, r5 + 826c: a933 add r1, sp, #204 ; 0xcc + 826e: 4650 mov r0, sl + 8270: 47b0 blx r6 + map_area.y1 = map_area.y2 + 1; + 8272: f8bd 30d2 ldrh.w r3, [sp, #210] ; 0xd2 + 8276: 3301 adds r3, #1 + 8278: b21b sxth r3, r3 + 827a: f8ad 30ce strh.w r3, [sp, #206] ; 0xce + mask_p = 0; + 827e: 2600 movs r6, #0 + 8280: e72d b.n 80de + if(bpp == 3) bpp = 4; + 8282: 2b03 cmp r3, #3 + 8284: ee09 4a90 vmov s19, r4 + 8288: f000 80c0 beq.w 840c + switch(bpp) { + 828c: 3b01 subs r3, #1 + 828e: 2b07 cmp r3, #7 + 8290: f200 80b0 bhi.w 83f4 + 8294: e8df f003 tbb [pc, r3] + 8298: baae04b4 .word 0xbaae04b4 + 829c: a7aeaeae .word 0xa7aeaeae + 82a0: 22c0 movs r2, #192 ; 0xc0 + 82a2: 9213 str r2, [sp, #76] ; 0x4c + 82a4: 4a97 ldr r2, [pc, #604] ; (8504 ) + 82a6: 2502 movs r5, #2 + 82a8: 2304 movs r3, #4 + bpp_opa_table_p = _lv_bpp4_opa_table; + 82aa: 920e str r2, [sp, #56] ; 0x38 + if(opa < LV_OPA_MAX) { + 82ac: 9a09 ldr r2, [sp, #36] ; 0x24 + 82ae: 2af9 cmp r2, #249 ; 0xf9 + 82b0: d812 bhi.n 82d8 + if(prev_opa != opa || prev_bpp != bpp) { + 82b2: 4a95 ldr r2, [pc, #596] ; (8508 ) + 82b4: 9809 ldr r0, [sp, #36] ; 0x24 + 82b6: f892 1100 ldrb.w r1, [r2, #256] ; 0x100 + 82ba: 4281 cmp r1, r0 + 82bc: f040 80ac bne.w 8418 + 82c0: f8d2 2104 ldr.w r2, [r2, #260] ; 0x104 + 82c4: 42aa cmp r2, r5 + 82c6: f040 80a7 bne.w 8418 + prev_opa = opa; + 82ca: 4b8f ldr r3, [pc, #572] ; (8508 ) + 82cc: 9a09 ldr r2, [sp, #36] ; 0x24 + 82ce: f883 2100 strb.w r2, [r3, #256] ; 0x100 + prev_bpp = bpp; + 82d2: f8c3 5104 str.w r5, [r3, #260] ; 0x104 + bpp_opa_table_p = opa_table; + 82d6: 930e str r3, [sp, #56] ; 0x38 + int32_t col_start = pos_x >= clip_area->x1 ? 0 : clip_area->x1 - pos_x; + 82d8: f9ba 3000 ldrsh.w r3, [sl] + int32_t box_w = g->box_w; + 82dc: f8bd 90e2 ldrh.w r9, [sp, #226] ; 0xe2 + int32_t box_h = g->box_h; + 82e0: f8bd 20e4 ldrh.w r2, [sp, #228] ; 0xe4 + int32_t col_start = pos_x >= clip_area->x1 ? 0 : clip_area->x1 - pos_x; + 82e4: 42b3 cmp r3, r6 + 82e6: bfcc ite gt + 82e8: 1b9b subgt r3, r3, r6 + 82ea: 2300 movle r3, #0 + 82ec: 930f str r3, [sp, #60] ; 0x3c + int32_t col_end = pos_x + box_w <= clip_area->x2 ? box_w : clip_area->x2 - pos_x + 1; + 82ee: f9ba 3004 ldrsh.w r3, [sl, #4] + 82f2: eb09 0006 add.w r0, r9, r6 + 82f6: 4298 cmp r0, r3 + 82f8: bfc4 itt gt + 82fa: 1b9b subgt r3, r3, r6 + 82fc: 3301 addgt r3, #1 + int32_t row_start = pos_y >= clip_area->y1 ? 0 : clip_area->y1 - pos_y; + 82fe: f9ba 6002 ldrsh.w r6, [sl, #2] + int32_t col_end = pos_x + box_w <= clip_area->x2 ? box_w : clip_area->x2 - pos_x + 1; + 8302: bfc8 it gt + 8304: 9312 strgt r3, [sp, #72] ; 0x48 + int32_t row_end = pos_y + box_h <= clip_area->y2 ? box_h : clip_area->y2 - pos_y + 1; + 8306: f9ba 3006 ldrsh.w r3, [sl, #6] + int32_t col_end = pos_x + box_w <= clip_area->x2 ? box_w : clip_area->x2 - pos_x + 1; + 830a: bfd8 it le + 830c: f8cd 9048 strle.w r9, [sp, #72] ; 0x48 + int32_t row_end = pos_y + box_h <= clip_area->y2 ? box_h : clip_area->y2 - pos_y + 1; + 8310: eb02 0008 add.w r0, r2, r8 + int32_t row_start = pos_y >= clip_area->y1 ? 0 : clip_area->y1 - pos_y; + 8314: 4546 cmp r6, r8 + 8316: bfcc ite gt + 8318: eba6 0608 subgt.w r6, r6, r8 + 831c: 2600 movle r6, #0 + int32_t row_end = pos_y + box_h <= clip_area->y2 ? box_h : clip_area->y2 - pos_y + 1; + 831e: 4298 cmp r0, r3 + 8320: bfc2 ittt gt + 8322: eba3 0308 subgt.w r3, r3, r8 + 8326: 3301 addgt r3, #1 + 8328: 9317 strgt r3, [sp, #92] ; 0x5c + uint32_t bit_ofs = (row_start * width_bit) + (col_start * bpp); + 832a: 9b0f ldr r3, [sp, #60] ; 0x3c + int32_t row_end = pos_y + box_h <= clip_area->y2 ? box_h : clip_area->y2 - pos_y + 1; + 832c: bfd8 it le + 832e: 9217 strle r2, [sp, #92] ; 0x5c + int32_t width_bit = box_w * bpp; /*Letter width in bits*/ + 8330: fb05 f109 mul.w r1, r5, r9 + uint32_t bit_ofs = (row_start * width_bit) + (col_start * bpp); + 8334: fb03 f405 mul.w r4, r3, r5 + 8338: fb06 4401 mla r4, r6, r1, r4 + map_p += bit_ofs >> 3; + 833c: eb07 03d4 add.w r3, r7, r4, lsr #3 + 8340: 9314 str r3, [sp, #80] ; 0x50 + uint32_t mask_buf_size = box_w * box_h > LV_HOR_RES_MAX ? LV_HOR_RES_MAX : box_w * box_h; + 8342: fb02 f309 mul.w r3, r2, r9 + 8346: f5b3 7ff0 cmp.w r3, #480 ; 0x1e0 + 834a: bfa8 it ge + 834c: f44f 73f0 movge.w r3, #480 ; 0x1e0 + 8350: 9315 str r3, [sp, #84] ; 0x54 + lv_opa_t * mask_buf = _lv_mem_buf_get(mask_buf_size); + 8352: 4618 mov r0, r3 + 8354: 4b6d ldr r3, [pc, #436] ; (850c ) + 8356: 4798 blx r3 + fill_area.x1 = col_start + pos_x; + 8358: 9a0d ldr r2, [sp, #52] ; 0x34 + 835a: 990f ldr r1, [sp, #60] ; 0x3c + 835c: f8bd 3034 ldrh.w r3, [sp, #52] ; 0x34 + 8360: fa11 f282 uxtah r2, r1, r2 + 8364: f8ad 20cc strh.w r2, [sp, #204] ; 0xcc + fill_area.x2 = col_end + pos_x - 1; + 8368: 9a12 ldr r2, [sp, #72] ; 0x48 + 836a: 3b01 subs r3, #1 + 836c: 4413 add r3, r2 + 836e: f8ad 30d0 strh.w r3, [sp, #208] ; 0xd0 + fill_area.y1 = row_start + pos_y; + 8372: 9b16 ldr r3, [sp, #88] ; 0x58 + 8374: 4433 add r3, r6 + 8376: b21b sxth r3, r3 + 8378: f8ad 30ce strh.w r3, [sp, #206] ; 0xce + fill_area.y2 = fill_area.y1; + 837c: f8ad 30d2 strh.w r3, [sp, #210] ; 0xd2 + uint8_t other_mask_cnt = lv_draw_mask_get_cnt(); + 8380: 4b63 ldr r3, [pc, #396] ; (8510 ) + lv_opa_t * mask_buf = _lv_mem_buf_get(mask_buf_size); + 8382: ee08 0a90 vmov s17, r0 + uint8_t other_mask_cnt = lv_draw_mask_get_cnt(); + 8386: 4798 blx r3 + uint32_t col_bit_max = 8 - bpp; + 8388: f1c5 0308 rsb r3, r5, #8 + 838c: 930d str r3, [sp, #52] ; 0x34 + uint32_t col_bit_row_ofs = (box_w + col_start - col_end) * bpp; + 838e: 9b0f ldr r3, [sp, #60] ; 0x3c + uint8_t other_mask_cnt = lv_draw_mask_get_cnt(); + 8390: 9019 str r0, [sp, #100] ; 0x64 + uint32_t col_bit_row_ofs = (box_w + col_start - col_end) * bpp; + 8392: 4499 add r9, r3 + 8394: 9b12 ldr r3, [sp, #72] ; 0x48 + 8396: eba9 0903 sub.w r9, r9, r3 + 839a: fb05 f309 mul.w r3, r5, r9 + col_bit = bit_ofs & 0x7; /* "& 0x7" equals to "% 8" just faster */ + 839e: f004 0407 and.w r4, r4, #7 + uint32_t col_bit_row_ofs = (box_w + col_start - col_end) * bpp; + 83a2: 931a str r3, [sp, #104] ; 0x68 + int32_t mask_p = 0; + 83a4: f04f 0900 mov.w r9, #0 + for(row = row_start ; row < row_end; row++) { + 83a8: 9b17 ldr r3, [sp, #92] ; 0x5c + 83aa: 429e cmp r6, r3 + 83ac: db45 blt.n 843a + if(fill_area.y1 != fill_area.y2) { + 83ae: f9bd 30d2 ldrsh.w r3, [sp, #210] ; 0xd2 + 83b2: f9bd 20ce ldrsh.w r2, [sp, #206] ; 0xce + 83b6: 429a cmp r2, r3 + 83b8: d010 beq.n 83dc + fill_area.y2--; + 83ba: 3b01 subs r3, #1 + 83bc: f8ad 30d2 strh.w r3, [sp, #210] ; 0xd2 + _lv_blend_fill(clip_area, &fill_area, + 83c0: 9b1b ldr r3, [sp, #108] ; 0x6c + 83c2: 9302 str r3, [sp, #8] + 83c4: 26ff movs r6, #255 ; 0xff + 83c6: 2302 movs r3, #2 + 83c8: e9cd 3600 strd r3, r6, [sp] + 83cc: ee19 2a90 vmov r2, s19 + 83d0: ee18 3a90 vmov r3, s17 + 83d4: 4c4f ldr r4, [pc, #316] ; (8514 ) + 83d6: a933 add r1, sp, #204 ; 0xcc + 83d8: 4650 mov r0, sl + 83da: 47a0 blx r4 + _lv_mem_buf_release(mask_buf); + 83dc: ee18 0a90 vmov r0, s17 + 83e0: 4b4d ldr r3, [pc, #308] ; (8518 ) + 83e2: 4798 blx r3 + 83e4: e450 b.n 7c88 + bitmask_init = 0xFF; + 83e6: 22ff movs r2, #255 ; 0xff + 83e8: 9213 str r2, [sp, #76] ; 0x4c + uint32_t bpp = g->bpp; + 83ea: 2508 movs r5, #8 + bpp_opa_table_p = _lv_bpp8_opa_table; + 83ec: 4a4b ldr r2, [pc, #300] ; (851c ) + shades = 256; + 83ee: f44f 7380 mov.w r3, #256 ; 0x100 + 83f2: e75a b.n 82aa + LV_LOG_WARN("lv_draw_letter: invalid bpp"); + 83f4: 4b4a ldr r3, [pc, #296] ; (8520 ) + 83f6: 9300 str r3, [sp, #0] + 83f8: f240 12e5 movw r2, #485 ; 0x1e5 + 83fc: 4b49 ldr r3, [pc, #292] ; (8524 ) + 83fe: e0da b.n 85b6 + bitmask_init = 0x80; + 8400: 2280 movs r2, #128 ; 0x80 + 8402: 9213 str r2, [sp, #76] ; 0x4c + uint32_t bpp = g->bpp; + 8404: 2501 movs r5, #1 + bpp_opa_table_p = _lv_bpp1_opa_table; + 8406: 4a48 ldr r2, [pc, #288] ; (8528 ) + shades = 2; + 8408: 2302 movs r3, #2 + 840a: e74e b.n 82aa + bitmask_init = 0xF0; + 840c: 22f0 movs r2, #240 ; 0xf0 + 840e: 9213 str r2, [sp, #76] ; 0x4c + switch(bpp) { + 8410: 2504 movs r5, #4 + bpp_opa_table_p = _lv_bpp4_opa_table; + 8412: 4a46 ldr r2, [pc, #280] ; (852c ) + shades = 16; + 8414: 2310 movs r3, #16 + 8416: e748 b.n 82aa + 8418: 990e ldr r1, [sp, #56] ; 0x38 + 841a: 483b ldr r0, [pc, #236] ; (8508 ) + 841c: 440b add r3, r1 + opa_table[i] = bpp_opa_table_p[i] == LV_OPA_COVER ? opa : ((bpp_opa_table_p[i] * opa) >> 8); + 841e: f811 2b01 ldrb.w r2, [r1], #1 + 8422: 2aff cmp r2, #255 ; 0xff + 8424: bf17 itett ne + 8426: 9c09 ldrne r4, [sp, #36] ; 0x24 + 8428: 9a09 ldreq r2, [sp, #36] ; 0x24 + 842a: fb12 f204 smulbbne r2, r2, r4 + 842e: 0a12 lsrne r2, r2, #8 + for(i = 0; i < shades; i++) { + 8430: 4299 cmp r1, r3 + opa_table[i] = bpp_opa_table_p[i] == LV_OPA_COVER ? opa : ((bpp_opa_table_p[i] * opa) >> 8); + 8432: f800 2b01 strb.w r2, [r0], #1 + for(i = 0; i < shades; i++) { + 8436: d1f2 bne.n 841e + 8438: e747 b.n 82ca + bitmask = bitmask_init >> col_bit; + 843a: 9b13 ldr r3, [sp, #76] ; 0x4c + for(col = col_start; col < col_end; col++) { + 843c: 990f ldr r1, [sp, #60] ; 0x3c + 843e: f8cd 908c str.w r9, [sp, #140] ; 0x8c + bitmask = bitmask_init >> col_bit; + 8442: fa23 f204 lsr.w r2, r3, r4 + for(col = col_start; col < col_end; col++) { + 8446: ee18 3a90 vmov r3, s17 + 844a: eb03 0809 add.w r8, r3, r9 + 844e: 4647 mov r7, r8 + 8450: 9b12 ldr r3, [sp, #72] ; 0x48 + 8452: 428b cmp r3, r1 + 8454: dc3a bgt.n 84cc + 8456: 9a0f ldr r2, [sp, #60] ; 0x3c + 8458: 9912 ldr r1, [sp, #72] ; 0x48 + 845a: 1a9b subs r3, r3, r2 + 845c: 9316 str r3, [sp, #88] ; 0x58 + 845e: 428a cmp r2, r1 + 8460: bfc8 it gt + 8462: 2300 movgt r3, #0 + 8464: 9318 str r3, [sp, #96] ; 0x60 + 8466: 4499 add r9, r3 + if(other_mask_cnt) { + 8468: 9b19 ldr r3, [sp, #100] ; 0x64 + 846a: b1b3 cbz r3, 849a + 846c: f8bd 30d0 ldrh.w r3, [sp, #208] ; 0xd0 + lv_draw_mask_res_t mask_res = lv_draw_mask_apply(mask_buf + mask_p_start, fill_area.x1, fill_area.y2, + 8470: f9bd 10cc ldrsh.w r1, [sp, #204] ; 0xcc + 8474: f9bd 20d2 ldrsh.w r2, [sp, #210] ; 0xd2 + 8478: 4f2d ldr r7, [pc, #180] ; (8530 ) + 847a: 3301 adds r3, #1 + 847c: 1a5b subs r3, r3, r1 + 847e: b21b sxth r3, r3 + 8480: 4640 mov r0, r8 + 8482: 47b8 blx r7 + if(mask_res == LV_DRAW_MASK_RES_TRANSP) { + 8484: b948 cbnz r0, 849a + 8486: f8bd 10d0 ldrh.w r1, [sp, #208] ; 0xd0 + 848a: f8bd 30cc ldrh.w r3, [sp, #204] ; 0xcc + 848e: 3101 adds r1, #1 + 8490: 1ac9 subs r1, r1, r3 + _lv_memset_00(mask_buf + mask_p_start, lv_area_get_width(&fill_area)); + 8492: b209 sxth r1, r1 + 8494: 4b27 ldr r3, [pc, #156] ; (8534 ) + 8496: 4640 mov r0, r8 + 8498: 4798 blx r3 + if((uint32_t) mask_p + (col_end - col_start) < mask_buf_size) { + 849a: 9b18 ldr r3, [sp, #96] ; 0x60 + 849c: 9a16 ldr r2, [sp, #88] ; 0x58 + 849e: 4413 add r3, r2 + 84a0: 4698 mov r8, r3 + 84a2: 9b23 ldr r3, [sp, #140] ; 0x8c + 84a4: 4498 add r8, r3 + 84a6: 9b15 ldr r3, [sp, #84] ; 0x54 + 84a8: 4543 cmp r3, r8 + 84aa: d945 bls.n 8538 + fill_area.y2 ++; + 84ac: f8bd 30d2 ldrh.w r3, [sp, #210] ; 0xd2 + 84b0: 3301 adds r3, #1 + 84b2: b21b sxth r3, r3 + 84b4: f8ad 30d2 strh.w r3, [sp, #210] ; 0xd2 + col_bit += col_bit_row_ofs; + 84b8: 9b1a ldr r3, [sp, #104] ; 0x68 + 84ba: 441c add r4, r3 + map_p += (col_bit >> 3); + 84bc: 9b14 ldr r3, [sp, #80] ; 0x50 + 84be: eb03 03d4 add.w r3, r3, r4, lsr #3 + 84c2: 9314 str r3, [sp, #80] ; 0x50 + col_bit = col_bit & 0x7; + 84c4: f004 0407 and.w r4, r4, #7 + for(row = row_start ; row < row_end; row++) { + 84c8: 3601 adds r6, #1 + 84ca: e76d b.n 83a8 + letter_px = (*map_p & bitmask) >> (col_bit_max - col_bit); + 84cc: 9b14 ldr r3, [sp, #80] ; 0x50 + 84ce: 980d ldr r0, [sp, #52] ; 0x34 + 84d0: 781b ldrb r3, [r3, #0] + 84d2: eba0 0c04 sub.w ip, r0, r4 + 84d6: 4013 ands r3, r2 + if(letter_px) { + 84d8: fa33 f30c lsrs.w r3, r3, ip + mask_buf[mask_p] = bpp_opa_table_p[letter_px]; + 84dc: bf1c itt ne + 84de: 980e ldrne r0, [sp, #56] ; 0x38 + 84e0: 5cc3 ldrbne r3, [r0, r3] + 84e2: f807 3b01 strb.w r3, [r7], #1 + if(col_bit < col_bit_max) { + 84e6: 9b0d ldr r3, [sp, #52] ; 0x34 + 84e8: 42a3 cmp r3, r4 + map_p++; + 84ea: bf9d ittte ls + 84ec: 9b14 ldrls r3, [sp, #80] ; 0x50 + bitmask = bitmask_init; + 84ee: 9a13 ldrls r2, [sp, #76] ; 0x4c + map_p++; + 84f0: 3301 addls r3, #1 + col_bit += bpp; + 84f2: 1964 addhi r4, r4, r5 + bitmask = bitmask >> bpp; + 84f4: bf8e itee hi + 84f6: 40ea lsrhi r2, r5 + map_p++; + 84f8: 9314 strls r3, [sp, #80] ; 0x50 + col_bit = 0; + 84fa: 2400 movls r4, #0 + for(col = col_start; col < col_end; col++) { + 84fc: 3101 adds r1, #1 + 84fe: e7a7 b.n 8450 + 8500: 000067fd .word 0x000067fd + 8504: 0001fb92 .word 0x0001fb92 + 8508: 200084c8 .word 0x200084c8 + 850c: 0000eeb5 .word 0x0000eeb5 + 8510: 000097f1 .word 0x000097f1 + 8514: 000061f1 .word 0x000061f1 + 8518: 0000eb69 .word 0x0000eb69 + 851c: 0001fba6 .word 0x0001fba6 + 8520: 0001fb74 .word 0x0001fb74 + 8524: 0001fcc7 .word 0x0001fcc7 + 8528: 0001fb90 .word 0x0001fb90 + 852c: 0001fb96 .word 0x0001fb96 + 8530: 00009761 .word 0x00009761 + 8534: 0000f019 .word 0x0000f019 + _lv_blend_fill(clip_area, &fill_area, + 8538: 9b1b ldr r3, [sp, #108] ; 0x6c + 853a: 9302 str r3, [sp, #8] + 853c: 27ff movs r7, #255 ; 0xff + 853e: 2302 movs r3, #2 + 8540: e9cd 3700 strd r3, r7, [sp] + 8544: ee19 2a90 vmov r2, s19 + 8548: ee18 3a90 vmov r3, s17 + 854c: f8df 808c ldr.w r8, [pc, #140] ; 85dc + 8550: a933 add r1, sp, #204 ; 0xcc + 8552: 4650 mov r0, sl + 8554: 47c0 blx r8 + fill_area.y1 = fill_area.y2 + 1; + 8556: f8bd 30d2 ldrh.w r3, [sp, #210] ; 0xd2 + 855a: 3301 adds r3, #1 + 855c: b21b sxth r3, r3 + 855e: f8ad 30ce strh.w r3, [sp, #206] ; 0xce + mask_p = 0; + 8562: f04f 0900 mov.w r9, #0 + 8566: e7a5 b.n 84b4 + else if(dsc->flag & LV_TXT_FLAG_RIGHT) { + 8568: 071a lsls r2, r3, #28 + 856a: f57f ac15 bpl.w 7d98 + _lv_txt_get_width(&txt[line_start], line_end - line_start, font, dsc->letter_space, dsc->flag); + 856e: ee18 2a10 vmov r2, s16 + 8572: 9300 str r3, [sp, #0] + 8574: 4630 mov r0, r6 + 8576: f9bb 300c ldrsh.w r3, [fp, #12] + 857a: 4e12 ldr r6, [pc, #72] ; (85c4 ) + 857c: 47b0 blx r6 + 857e: 9b05 ldr r3, [sp, #20] + 8580: 9a05 ldr r2, [sp, #20] + 8582: 889b ldrh r3, [r3, #4] + 8584: 8812 ldrh r2, [r2, #0] + 8586: 3301 adds r3, #1 + 8588: 1a9b subs r3, r3, r2 + pos.x += lv_area_get_width(coords) - line_width; + 858a: b21b sxth r3, r3 + 858c: 1a18 subs r0, r3, r0 + 858e: 4420 add r0, r4 + 8590: e401 b.n 7d96 + bool g_ret = lv_font_get_glyph_dsc(font_p, &g, letter, '\0'); + 8592: ee18 0a10 vmov r0, s16 + 8596: 4e0c ldr r6, [pc, #48] ; (85c8 ) + 8598: 2300 movs r3, #0 + 859a: 462a mov r2, r5 + 859c: a938 add r1, sp, #224 ; 0xe0 + 859e: 47b0 blx r6 + if(g_ret == false) { + 85a0: 2800 cmp r0, #0 + 85a2: f47f ac25 bne.w 7df0 + if(letter >= 0x20) { + 85a6: 2d1f cmp r5, #31 + 85a8: f67f ab6e bls.w 7c88 + LV_LOG_WARN("lv_draw_letter: glyph dsc. not found"); + 85ac: 4b07 ldr r3, [pc, #28] ; (85cc ) + 85ae: 9300 str r3, [sp, #0] + 85b0: 4b07 ldr r3, [pc, #28] ; (85d0 ) + 85b2: f240 12a1 movw r2, #417 ; 0x1a1 + LV_LOG_WARN("lv_draw_letter: invalid bpp"); + 85b6: 4907 ldr r1, [pc, #28] ; (85d4 ) + 85b8: 4c07 ldr r4, [pc, #28] ; (85d8 ) + 85ba: 2002 movs r0, #2 + 85bc: 47a0 blx r4 + return; /*Invalid bpp. Can't render the letter*/ + 85be: f7ff bb63 b.w 7c88 + 85c2: bf00 nop + 85c4: 0000ff1d .word 0x0000ff1d + 85c8: 0000d169 .word 0x0000d169 + 85cc: 0001fafc .word 0x0001fafc + 85d0: 0001fca6 .word 0x0001fca6 + 85d4: 0001fac6 .word 0x0001fac6 + 85d8: 0000e8e9 .word 0x0000e8e9 + 85dc: 000061f1 .word 0x000061f1 + +000085e0 : +/********************** + * GLOBAL FUNCTIONS + **********************/ + +LV_ATTRIBUTE_FAST_MEM void lv_draw_line_dsc_init(lv_draw_line_dsc_t * dsc) +{ + 85e0: b510 push {r4, lr} + _lv_memset_00(dsc, sizeof(lv_draw_line_dsc_t)); + 85e2: 4b05 ldr r3, [pc, #20] ; (85f8 ) +{ + 85e4: 4604 mov r4, r0 + _lv_memset_00(dsc, sizeof(lv_draw_line_dsc_t)); + 85e6: 210a movs r1, #10 + 85e8: 4798 blx r3 + dsc->width = 1; + dsc->opa = LV_OPA_COVER; + 85ea: 23ff movs r3, #255 ; 0xff + 85ec: 7223 strb r3, [r4, #8] + dsc->color = LV_COLOR_BLACK; + 85ee: 2300 movs r3, #0 + 85f0: 8023 strh r3, [r4, #0] + dsc->width = 1; + 85f2: 2301 movs r3, #1 + 85f4: 8063 strh r3, [r4, #2] +} + 85f6: bd10 pop {r4, pc} + 85f8: 0000f019 .word 0x0000f019 + +000085fc : + * @param style pointer to a line's style + * @param opa_scale scale down all opacities by the factor + */ +LV_ATTRIBUTE_FAST_MEM void lv_draw_line(const lv_point_t * point1, const lv_point_t * point2, const lv_area_t * clip, + lv_draw_line_dsc_t * dsc) +{ + 85fc: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 8600: ed2d 8b04 vpush {d8-d9} + 8604: 469b mov fp, r3 + if(dsc->width == 0) return; + 8606: f9b3 3002 ldrsh.w r3, [r3, #2] +{ + 860a: b0c7 sub sp, #284 ; 0x11c + 860c: e9cd 0105 strd r0, r1, [sp, #20] + 8610: ee08 2a90 vmov s17, r2 + if(dsc->width == 0) return; + 8614: 2b00 cmp r3, #0 + 8616: f000 80e4 beq.w 87e2 + if(dsc->opa <= LV_OPA_MIN) return; + 861a: f89b 2008 ldrb.w r2, [fp, #8] + 861e: 2a05 cmp r2, #5 + 8620: f240 80df bls.w 87e2 + + if(point1->x == point2->x && point1->y == point2->y) return; + 8624: 9a05 ldr r2, [sp, #20] + 8626: f9b0 4000 ldrsh.w r4, [r0] + 862a: f9b1 0000 ldrsh.w r0, [r1] + 862e: f9b2 1002 ldrsh.w r1, [r2, #2] + 8632: 9a06 ldr r2, [sp, #24] + 8634: 4284 cmp r4, r0 + 8636: f9b2 2002 ldrsh.w r2, [r2, #2] + 863a: d102 bne.n 8642 + 863c: 4291 cmp r1, r2 + 863e: f000 80d0 beq.w 87e2 + + lv_area_t clip_line; + clip_line.x1 = LV_MATH_MIN(point1->x, point2->x) - dsc->width / 2; + 8642: eb03 73d3 add.w r3, r3, r3, lsr #31 + 8646: f3c3 034f ubfx r3, r3, #1, #16 + 864a: 4284 cmp r4, r0 + 864c: bfd4 ite le + 864e: ebc3 0504 rsble r5, r3, r4 + 8652: ebc3 0500 rsbgt r5, r3, r0 + 8656: f8ad 5028 strh.w r5, [sp, #40] ; 0x28 + clip_line.x2 = LV_MATH_MAX(point1->x, point2->x) + dsc->width / 2; + 865a: 4284 cmp r4, r0 + 865c: bfac ite ge + 865e: 191d addge r5, r3, r4 + 8660: 181d addlt r5, r3, r0 + clip_line.y1 = LV_MATH_MIN(point1->y, point2->y) - dsc->width / 2; + 8662: 4291 cmp r1, r2 + 8664: bfd4 ite le + 8666: ebc3 0001 rsble r0, r3, r1 + 866a: ebc3 0002 rsbgt r0, r3, r2 + clip_line.y2 = LV_MATH_MAX(point1->y, point2->y) + dsc->width / 2; + 866e: 4291 cmp r1, r2 + 8670: bfac ite ge + 8672: 185b addge r3, r3, r1 + 8674: 189b addlt r3, r3, r2 + + bool is_common; + is_common = _lv_area_intersect(&clip_line, &clip_line, clip); + 8676: a90a add r1, sp, #40 ; 0x28 + clip_line.y1 = LV_MATH_MIN(point1->y, point2->y) - dsc->width / 2; + 8678: f8ad 002a strh.w r0, [sp, #42] ; 0x2a + is_common = _lv_area_intersect(&clip_line, &clip_line, clip); + 867c: ee18 2a90 vmov r2, s17 + 8680: 4caa ldr r4, [pc, #680] ; (892c ) + clip_line.x2 = LV_MATH_MAX(point1->x, point2->x) + dsc->width / 2; + 8682: f8ad 502c strh.w r5, [sp, #44] ; 0x2c + is_common = _lv_area_intersect(&clip_line, &clip_line, clip); + 8686: 4608 mov r0, r1 + clip_line.y2 = LV_MATH_MAX(point1->y, point2->y) + dsc->width / 2; + 8688: f8ad 302e strh.w r3, [sp, #46] ; 0x2e + is_common = _lv_area_intersect(&clip_line, &clip_line, clip); + 868c: 47a0 blx r4 + if(!is_common) return; + 868e: 2800 cmp r0, #0 + 8690: f000 80a7 beq.w 87e2 + + if(point1->y == point2->y) draw_line_hor(point1, point2, &clip_line, dsc); + 8694: 9b05 ldr r3, [sp, #20] + 8696: f9b3 9002 ldrsh.w r9, [r3, #2] + 869a: 9b06 ldr r3, [sp, #24] + 869c: f9b3 8002 ldrsh.w r8, [r3, #2] + 86a0: 45c1 cmp r9, r8 + 86a2: f040 8159 bne.w 8958 + const lv_area_t * clip, + lv_draw_line_dsc_t * dsc) +{ + lv_opa_t opa = dsc->opa; + + lv_disp_t * disp = _lv_refr_get_disp_refreshing(); + 86a6: 4ba2 ldr r3, [pc, #648] ; (8930 ) + lv_opa_t opa = dsc->opa; + 86a8: f89b 4008 ldrb.w r4, [fp, #8] + lv_disp_t * disp = _lv_refr_get_disp_refreshing(); + 86ac: 4798 blx r3 + lv_disp_buf_t * vdb = lv_disp_get_buf(disp); + 86ae: 4ba1 ldr r3, [pc, #644] ; (8934 ) + 86b0: 4798 blx r3 + + const lv_area_t * disp_area = &vdb->area; + + int32_t w = dsc->width - 1; + 86b2: f9bb 3002 ldrsh.w r3, [fp, #2] + int32_t w_half0 = w >> 1; + int32_t w_half1 = w_half0 + (w & 0x1); /*Compensate rounding error*/ + + bool dashed = dsc->dash_gap && dsc->dash_width ? true : false; + 86b6: f9bb 5006 ldrsh.w r5, [fp, #6] + int32_t w = dsc->width - 1; + 86ba: 3b01 subs r3, #1 + int32_t w_half1 = w_half0 + (w & 0x1); /*Compensate rounding error*/ + 86bc: f003 0601 and.w r6, r3, #1 + lv_disp_buf_t * vdb = lv_disp_get_buf(disp); + 86c0: 4680 mov r8, r0 + int32_t w_half0 = w >> 1; + 86c2: 105f asrs r7, r3, #1 + int32_t w_half1 = w_half0 + (w & 0x1); /*Compensate rounding error*/ + 86c4: eb06 0663 add.w r6, r6, r3, asr #1 + bool dashed = dsc->dash_gap && dsc->dash_width ? true : false; + 86c8: b125 cbz r5, 86d4 + 86ca: f9bb 5004 ldrsh.w r5, [fp, #4] + 86ce: 3d00 subs r5, #0 + 86d0: bf18 it ne + 86d2: 2501 movne r5, #1 + + bool simple_mode = true; + if(lv_draw_mask_get_cnt()) simple_mode = false; + 86d4: 4b98 ldr r3, [pc, #608] ; (8938 ) + 86d6: 4798 blx r3 + 86d8: 2800 cmp r0, #0 + 86da: f040 8087 bne.w 87ec + else if(dashed) simple_mode = false; + 86de: f085 0201 eor.w r2, r5, #1 + + lv_area_t draw_area; + draw_area.x1 = LV_MATH_MIN(point1->x, point2->x); + 86e2: 9b06 ldr r3, [sp, #24] + 86e4: 9905 ldr r1, [sp, #20] + 86e6: f9b3 3000 ldrsh.w r3, [r3] + 86ea: f9b1 1000 ldrsh.w r1, [r1] + 86ee: 428b cmp r3, r1 + 86f0: 4618 mov r0, r3 + 86f2: bfa8 it ge + 86f4: 4608 movge r0, r1 + draw_area.x2 = LV_MATH_MAX(point1->x, point2->x) - 1; + 86f6: 428b cmp r3, r1 + 86f8: bfb8 it lt + 86fa: 460b movlt r3, r1 + 86fc: 3b01 subs r3, #1 + 86fe: f8ad 309c strh.w r3, [sp, #156] ; 0x9c + draw_area.y1 = point1->y - w_half1; + 8702: 9b05 ldr r3, [sp, #20] + draw_area.x1 = LV_MATH_MIN(point1->x, point2->x); + 8704: f8ad 0098 strh.w r0, [sp, #152] ; 0x98 + draw_area.y1 = point1->y - w_half1; + 8708: 885b ldrh r3, [r3, #2] + 870a: 1b9e subs r6, r3, r6 + draw_area.y2 = point1->y + w_half0; + 870c: 443b add r3, r7 + draw_area.y1 = point1->y - w_half1; + 870e: f8ad 609a strh.w r6, [sp, #154] ; 0x9a + draw_area.y2 = point1->y + w_half0; + 8712: f8ad 309e strh.w r3, [sp, #158] ; 0x9e + + /*If there is no mask then simply draw a rectangle*/ + if(simple_mode) { + 8716: 2a00 cmp r2, #0 + 8718: d06a beq.n 87f0 + _lv_blend_fill(clip, &draw_area, + dsc->color, NULL, LV_DRAW_MASK_RES_FULL_COVER, opa, + dsc->blend_mode); + 871a: f89b 3009 ldrb.w r3, [fp, #9] + _lv_blend_fill(clip, &draw_area, + 871e: f003 0303 and.w r3, r3, #3 + 8722: e9cd 4301 strd r4, r3, [sp, #4] + draw_area.y1 = LV_MATH_MIN(point1->y, point2->y); + draw_area.y2 = LV_MATH_MAX(point1->y, point2->y) - 1; + + /*If there is no mask then simply draw a rectangle*/ + if(simple_mode) { + _lv_blend_fill(clip, &draw_area, + 8726: 2301 movs r3, #1 + 8728: 9300 str r3, [sp, #0] + 872a: f8bb 2000 ldrh.w r2, [fp] + 872e: 4c83 ldr r4, [pc, #524] ; (893c ) + 8730: 2300 movs r3, #0 + 8732: a926 add r1, sp, #152 ; 0x98 + 8734: a80a add r0, sp, #40 ; 0x28 + 8736: 47a0 blx r4 + if(dsc->round_end || dsc->round_start) { + 8738: f89b 3009 ldrb.w r3, [fp, #9] + 873c: f013 0f0c tst.w r3, #12 + 8740: d04f beq.n 87e2 + lv_draw_rect_dsc_init(&cir_dsc); + 8742: 4b7f ldr r3, [pc, #508] ; (8940 ) + 8744: a831 add r0, sp, #196 ; 0xc4 + 8746: 4798 blx r3 + cir_dsc.bg_color = dsc->color; + 8748: f8bb 3000 ldrh.w r3, [fp] + 874c: f8ad 30c6 strh.w r3, [sp, #198] ; 0xc6 + cir_dsc.radius = LV_RADIUS_CIRCLE; + 8750: f647 73ff movw r3, #32767 ; 0x7fff + 8754: f8ad 30c4 strh.w r3, [sp, #196] ; 0xc4 + cir_dsc.bg_opa = dsc->opa; + 8758: f89b 3008 ldrb.w r3, [fp, #8] + int32_t r = (dsc->width >> 1); + 875c: f9bb 5002 ldrsh.w r5, [fp, #2] + cir_dsc.bg_opa = dsc->opa; + 8760: f88d 30d0 strb.w r3, [sp, #208] ; 0xd0 + if(dsc->round_start) { + 8764: f89b 3009 ldrb.w r3, [fp, #9] + int32_t r = (dsc->width >> 1); + 8768: 106c asrs r4, r5, #1 + if(dsc->round_start) { + 876a: 075a lsls r2, r3, #29 + 876c: ea6f 0505 mvn.w r5, r5 + 8770: f005 0501 and.w r5, r5, #1 + 8774: d518 bpl.n 87a8 + cir_area.x1 = point1->x - r; + 8776: 9b05 ldr r3, [sp, #20] + 8778: 881a ldrh r2, [r3, #0] + 877a: b2a3 uxth r3, r4 + 877c: 1ad1 subs r1, r2, r3 + 877e: f8ad 1098 strh.w r1, [sp, #152] ; 0x98 + cir_area.y1 = point1->y - r; + 8782: 9905 ldr r1, [sp, #20] + 8784: 8849 ldrh r1, [r1, #2] + cir_area.x2 = point1->x + r - r_corr; + 8786: 441a add r2, r3 + cir_area.y1 = point1->y - r; + 8788: 1ac8 subs r0, r1, r3 + cir_area.y2 = point1->y + r - r_corr ; + 878a: 440b add r3, r1 + cir_area.x2 = point1->x + r - r_corr; + 878c: 1b52 subs r2, r2, r5 + cir_area.y2 = point1->y + r - r_corr ; + 878e: 1b5b subs r3, r3, r5 + cir_area.y1 = point1->y - r; + 8790: f8ad 009a strh.w r0, [sp, #154] ; 0x9a + cir_area.x2 = point1->x + r - r_corr; + 8794: f8ad 209c strh.w r2, [sp, #156] ; 0x9c + cir_area.y2 = point1->y + r - r_corr ; + 8798: f8ad 309e strh.w r3, [sp, #158] ; 0x9e + lv_draw_rect(&cir_area, clip, &cir_dsc); + 879c: ee18 1a90 vmov r1, s17 + 87a0: 4b68 ldr r3, [pc, #416] ; (8944 ) + 87a2: aa31 add r2, sp, #196 ; 0xc4 + 87a4: a826 add r0, sp, #152 ; 0x98 + 87a6: 4798 blx r3 + if(dsc->round_end) { + 87a8: f89b 3009 ldrb.w r3, [fp, #9] + 87ac: 071b lsls r3, r3, #28 + 87ae: d518 bpl.n 87e2 + cir_area.x1 = point2->x - r; + 87b0: 9b06 ldr r3, [sp, #24] + 87b2: 881a ldrh r2, [r3, #0] + 87b4: b2a3 uxth r3, r4 + 87b6: 1ad1 subs r1, r2, r3 + 87b8: f8ad 1098 strh.w r1, [sp, #152] ; 0x98 + cir_area.y1 = point2->y - r; + 87bc: 9906 ldr r1, [sp, #24] + 87be: 8849 ldrh r1, [r1, #2] + cir_area.x2 = point2->x + r - r_corr; + 87c0: 441a add r2, r3 + cir_area.y1 = point2->y - r; + 87c2: 1ac8 subs r0, r1, r3 + cir_area.y2 = point2->y + r - r_corr ; + 87c4: 440b add r3, r1 + cir_area.x2 = point2->x + r - r_corr; + 87c6: 1b52 subs r2, r2, r5 + cir_area.y2 = point2->y + r - r_corr ; + 87c8: 1b5b subs r3, r3, r5 + cir_area.y1 = point2->y - r; + 87ca: f8ad 009a strh.w r0, [sp, #154] ; 0x9a + cir_area.x2 = point2->x + r - r_corr; + 87ce: f8ad 209c strh.w r2, [sp, #156] ; 0x9c + cir_area.y2 = point2->y + r - r_corr ; + 87d2: f8ad 309e strh.w r3, [sp, #158] ; 0x9e + lv_draw_rect(&cir_area, clip, &cir_dsc); + 87d6: ee18 1a90 vmov r1, s17 + 87da: 4b5a ldr r3, [pc, #360] ; (8944 ) + 87dc: aa31 add r2, sp, #196 ; 0xc4 + 87de: a826 add r0, sp, #152 ; 0x98 + 87e0: 4798 blx r3 +} + 87e2: b047 add sp, #284 ; 0x11c + 87e4: ecbd 8b04 vpop {d8-d9} + 87e8: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + if(lv_draw_mask_get_cnt()) simple_mode = false; + 87ec: 2200 movs r2, #0 + 87ee: e778 b.n 86e2 + is_common = _lv_area_intersect(&draw_area, clip, &draw_area); + 87f0: aa26 add r2, sp, #152 ; 0x98 + 87f2: 4b4e ldr r3, [pc, #312] ; (892c ) + 87f4: a90a add r1, sp, #40 ; 0x28 + 87f6: 4610 mov r0, r2 + 87f8: 4798 blx r3 + if(!is_common) return; + 87fa: 2800 cmp r0, #0 + 87fc: d09c beq.n 8738 + draw_area.y1 -= disp_area->y1; + 87fe: f8b8 e012 ldrh.w lr, [r8, #18] + 8802: f9bd 109a ldrsh.w r1, [sp, #154] ; 0x9a + draw_area.x1 -= disp_area->x1; + 8806: f8b8 2010 ldrh.w r2, [r8, #16] + 880a: f9b8 6010 ldrsh.w r6, [r8, #16] + 880e: f8bd 0098 ldrh.w r0, [sp, #152] ; 0x98 + draw_area.x2 -= disp_area->x1; + 8812: f9bd 709c ldrsh.w r7, [sp, #156] ; 0x9c + draw_area.x1 -= disp_area->x1; + 8816: f9bd c098 ldrsh.w ip, [sp, #152] ; 0x98 + fill_area.x1 = draw_area.x1 + disp_area->x1; + 881a: f8ad c0c4 strh.w ip, [sp, #196] ; 0xc4 + draw_area.y1 -= disp_area->y1; + 881e: eba1 040e sub.w r4, r1, lr + 8822: f8ad 409a strh.w r4, [sp, #154] ; 0x9a + draw_area.x2 -= disp_area->x1; + 8826: f8bd 409c ldrh.w r4, [sp, #156] ; 0x9c + fill_area.x2 = draw_area.x2 + disp_area->x1; + 882a: f8ad 70c8 strh.w r7, [sp, #200] ; 0xc8 + draw_area.x1 -= disp_area->x1; + 882e: 1a83 subs r3, r0, r2 + draw_area.x2 -= disp_area->x1; + 8830: 1aa2 subs r2, r4, r2 + 8832: f8ad 209c strh.w r2, [sp, #156] ; 0x9c + draw_area.y2 -= disp_area->y1; + 8836: f8bd 209e ldrh.w r2, [sp, #158] ; 0x9e + fill_area.y1 = draw_area.y1 + disp_area->y1; + 883a: f8ad 10c6 strh.w r1, [sp, #198] ; 0xc6 + 883e: 3401 adds r4, #1 + draw_area.x1 -= disp_area->x1; + 8840: b21b sxth r3, r3 + draw_area.y2 -= disp_area->y1; + 8842: eba2 020e sub.w r2, r2, lr + 8846: 1a24 subs r4, r4, r0 + draw_area.x1 -= disp_area->x1; + 8848: f8ad 3098 strh.w r3, [sp, #152] ; 0x98 + draw_area.y2 -= disp_area->y1; + 884c: f8ad 209e strh.w r2, [sp, #158] ; 0x9e + 8850: b224 sxth r4, r4 + fill_area.y2 = fill_area.y1; + 8852: f8ad 10ca strh.w r1, [sp, #202] ; 0xca + if(dashed) { + 8856: b1dd cbz r5, 8890 + dash_start = (vdb->area.x1 + draw_area.x1) % (dsc->dash_gap + dsc->dash_width); + 8858: 441e add r6, r3 + 885a: f9bb 2004 ldrsh.w r2, [fp, #4] + 885e: f9bb 3006 ldrsh.w r3, [fp, #6] + 8862: 4413 add r3, r2 + 8864: fb96 f2f3 sdiv r2, r6, r3 + 8868: fb03 6612 mls r6, r3, r2, r6 + 886c: b233 sxth r3, r6 + 886e: 9307 str r3, [sp, #28] + lv_opa_t * mask_buf = _lv_mem_buf_get(draw_area_w); + 8870: 4b35 ldr r3, [pc, #212] ; (8948 ) + _lv_blend_fill(clip, &fill_area, + 8872: f8df a0c8 ldr.w sl, [pc, #200] ; 893c + lv_opa_t * mask_buf = _lv_mem_buf_get(draw_area_w); + 8876: 4620 mov r0, r4 + 8878: 4798 blx r3 + for(h = draw_area.y1; h <= draw_area.y2; h++) { + 887a: f9bd 909a ldrsh.w r9, [sp, #154] ; 0x9a + lv_opa_t * mask_buf = _lv_mem_buf_get(draw_area_w); + 887e: 4607 mov r7, r0 + for(h = draw_area.y1; h <= draw_area.y2; h++) { + 8880: f9bd 309e ldrsh.w r3, [sp, #158] ; 0x9e + 8884: 4599 cmp r9, r3 + 8886: dd05 ble.n 8894 + _lv_mem_buf_release(mask_buf); + 8888: 4638 mov r0, r7 + LV_BLEND_MODE_NORMAL); + + fill_area.y1++; + fill_area.y2++; + } + _lv_mem_buf_release(mask_buf); + 888a: 4b30 ldr r3, [pc, #192] ; (894c ) + 888c: 4798 blx r3 + 888e: e753 b.n 8738 + lv_style_int_t dash_start = 0; + 8890: 9507 str r5, [sp, #28] + 8892: e7ed b.n 8870 + _lv_memset_ff(mask_buf, draw_area_w); + 8894: 4b2e ldr r3, [pc, #184] ; (8950 ) + lv_draw_mask_res_t mask_res = lv_draw_mask_apply(mask_buf, vdb->area.x1 + draw_area.x1, vdb->area.y1 + h, draw_area_w); + 8896: 4e2f ldr r6, [pc, #188] ; (8954 ) + _lv_memset_ff(mask_buf, draw_area_w); + 8898: 4621 mov r1, r4 + 889a: 4638 mov r0, r7 + 889c: 4798 blx r3 + lv_draw_mask_res_t mask_res = lv_draw_mask_apply(mask_buf, vdb->area.x1 + draw_area.x1, vdb->area.y1 + h, draw_area_w); + 889e: f8bd 3098 ldrh.w r3, [sp, #152] ; 0x98 + 88a2: f8b8 2012 ldrh.w r2, [r8, #18] + 88a6: f8b8 1010 ldrh.w r1, [r8, #16] + 88aa: 444a add r2, r9 + 88ac: 4419 add r1, r3 + 88ae: b212 sxth r2, r2 + 88b0: 4623 mov r3, r4 + 88b2: b209 sxth r1, r1 + 88b4: 4638 mov r0, r7 + 88b6: 47b0 blx r6 + 88b8: 4602 mov r2, r0 + if(dashed) { + 88ba: b195 cbz r5, 88e2 + if(mask_res != LV_DRAW_MASK_RES_TRANSP) { + 88bc: b188 cbz r0, 88e2 + for(i = 0; i < draw_area_w; i++, dash_cnt++) { + 88be: 2300 movs r3, #0 + lv_style_int_t dash_cnt = dash_start; + 88c0: 9907 ldr r1, [sp, #28] + 88c2: 4618 mov r0, r3 + 88c4: e00a b.n 88dc + if(dash_cnt <= dsc->dash_width) { + 88c6: f9bb 2004 ldrsh.w r2, [fp, #4] + 88ca: 428a cmp r2, r1 + 88cc: db25 blt.n 891a + i += diff; + 88ce: 4413 add r3, r2 + 88d0: 1a5b subs r3, r3, r1 + 88d2: b21b sxth r3, r3 + for(i = 0; i < draw_area_w; i++, dash_cnt++) { + 88d4: 3301 adds r3, #1 + 88d6: 3201 adds r2, #1 + 88d8: b21b sxth r3, r3 + 88da: b211 sxth r1, r2 + 88dc: 429c cmp r4, r3 + 88de: dcf2 bgt.n 88c6 + mask_res = LV_DRAW_MASK_RES_CHANGED; + 88e0: 2202 movs r2, #2 + dsc->blend_mode); + 88e2: f89b 3009 ldrb.w r3, [fp, #9] + _lv_blend_fill(clip, &fill_area, + 88e6: f003 0303 and.w r3, r3, #3 + 88ea: 9302 str r3, [sp, #8] + 88ec: f89b 3008 ldrb.w r3, [fp, #8] + 88f0: a931 add r1, sp, #196 ; 0xc4 + 88f2: e9cd 2300 strd r2, r3, [sp] + 88f6: a80a add r0, sp, #40 ; 0x28 + 88f8: 463b mov r3, r7 + 88fa: f8bb 2000 ldrh.w r2, [fp] + 88fe: 47d0 blx sl + fill_area.y1++; + 8900: f8bd 30c6 ldrh.w r3, [sp, #198] ; 0xc6 + 8904: 3301 adds r3, #1 + 8906: f8ad 30c6 strh.w r3, [sp, #198] ; 0xc6 + fill_area.y2++; + 890a: f8bd 30ca ldrh.w r3, [sp, #202] ; 0xca + 890e: 3301 adds r3, #1 + 8910: f8ad 30ca strh.w r3, [sp, #202] ; 0xca + for(h = draw_area.y1; h <= draw_area.y2; h++) { + 8914: f109 0901 add.w r9, r9, #1 + 8918: e7b2 b.n 8880 + else if(dash_cnt >= dsc->dash_gap + dsc->dash_width) { + 891a: f9bb c006 ldrsh.w ip, [fp, #6] + 891e: 4462 add r2, ip + 8920: 4291 cmp r1, r2 + mask_buf[i] = 0x00; + 8922: bfba itte lt + 8924: 54f8 strblt r0, [r7, r3] + 8926: 460a movlt r2, r1 + dash_cnt = 0; + 8928: 2200 movge r2, #0 + 892a: e7d3 b.n 88d4 + 892c: 0000de8d .word 0x0000de8d + 8930: 00004fe9 .word 0x00004fe9 + 8934: 0000d9e1 .word 0x0000d9e1 + 8938: 000097f1 .word 0x000097f1 + 893c: 000061f1 .word 0x000061f1 + 8940: 00009ba1 .word 0x00009ba1 + 8944: 00009bed .word 0x00009bed + 8948: 0000eeb5 .word 0x0000eeb5 + 894c: 0000eb69 .word 0x0000eb69 + 8950: 0000f075 .word 0x0000f075 + 8954: 00009761 .word 0x00009761 + else if(point1->x == point2->x) draw_line_ver(point1, point2, &clip_line, dsc); + 8958: 9b05 ldr r3, [sp, #20] + 895a: f9b3 7000 ldrsh.w r7, [r3] + 895e: 9b06 ldr r3, [sp, #24] + 8960: f9b3 6000 ldrsh.w r6, [r3] + 8964: 42b7 cmp r7, r6 + 8966: f040 80db bne.w 8b20 + lv_disp_t * disp = _lv_refr_get_disp_refreshing(); + 896a: 4b66 ldr r3, [pc, #408] ; (8b04 ) + lv_opa_t opa = dsc->opa; + 896c: f89b 6008 ldrb.w r6, [fp, #8] + lv_disp_t * disp = _lv_refr_get_disp_refreshing(); + 8970: 4798 blx r3 + lv_disp_buf_t * vdb = lv_disp_get_buf(disp); + 8972: 4b65 ldr r3, [pc, #404] ; (8b08 ) + 8974: 4798 blx r3 + int32_t w = dsc->width - 1; + 8976: f9bb 3002 ldrsh.w r3, [fp, #2] + bool dashed = dsc->dash_gap && dsc->dash_width ? true : false; + 897a: f9bb 5006 ldrsh.w r5, [fp, #6] + int32_t w = dsc->width - 1; + 897e: 3b01 subs r3, #1 + int32_t w_half1 = w_half0 + (w & 0x1); /*Compensate rounding error*/ + 8980: f003 0801 and.w r8, r3, #1 + lv_disp_buf_t * vdb = lv_disp_get_buf(disp); + 8984: 4607 mov r7, r0 + int32_t w_half0 = w >> 1; + 8986: ea4f 0963 mov.w r9, r3, asr #1 + int32_t w_half1 = w_half0 + (w & 0x1); /*Compensate rounding error*/ + 898a: eb08 0863 add.w r8, r8, r3, asr #1 + bool dashed = dsc->dash_gap && dsc->dash_width ? true : false; + 898e: b125 cbz r5, 899a + 8990: f9bb 5004 ldrsh.w r5, [fp, #4] + 8994: 3d00 subs r5, #0 + 8996: bf18 it ne + 8998: 2501 movne r5, #1 + if(lv_draw_mask_get_cnt()) simple_mode = false; + 899a: 4b5c ldr r3, [pc, #368] ; (8b0c ) + 899c: 4798 blx r3 + 899e: bb20 cbnz r0, 89ea + else if(dashed) simple_mode = false; + 89a0: f085 0201 eor.w r2, r5, #1 + draw_area.x1 = point1->x - w_half1; + 89a4: 9b05 ldr r3, [sp, #20] + draw_area.y1 = LV_MATH_MIN(point1->y, point2->y); + 89a6: 9905 ldr r1, [sp, #20] + draw_area.x1 = point1->x - w_half1; + 89a8: 881b ldrh r3, [r3, #0] + draw_area.y1 = LV_MATH_MIN(point1->y, point2->y); + 89aa: f9b1 1002 ldrsh.w r1, [r1, #2] + draw_area.x1 = point1->x - w_half1; + 89ae: eba3 0808 sub.w r8, r3, r8 + draw_area.x2 = point1->x + w_half0; + 89b2: 444b add r3, r9 + 89b4: f8ad 309c strh.w r3, [sp, #156] ; 0x9c + draw_area.y1 = LV_MATH_MIN(point1->y, point2->y); + 89b8: 9b06 ldr r3, [sp, #24] + draw_area.x1 = point1->x - w_half1; + 89ba: f8ad 8098 strh.w r8, [sp, #152] ; 0x98 + draw_area.y1 = LV_MATH_MIN(point1->y, point2->y); + 89be: f9b3 3002 ldrsh.w r3, [r3, #2] + 89c2: 428b cmp r3, r1 + 89c4: 4618 mov r0, r3 + 89c6: bfa8 it ge + 89c8: 4608 movge r0, r1 + draw_area.y2 = LV_MATH_MAX(point1->y, point2->y) - 1; + 89ca: 428b cmp r3, r1 + 89cc: bfb8 it lt + 89ce: 460b movlt r3, r1 + 89d0: 3b01 subs r3, #1 + draw_area.y1 = LV_MATH_MIN(point1->y, point2->y); + 89d2: f8ad 009a strh.w r0, [sp, #154] ; 0x9a + draw_area.y2 = LV_MATH_MAX(point1->y, point2->y) - 1; + 89d6: f8ad 309e strh.w r3, [sp, #158] ; 0x9e + if(simple_mode) { + 89da: b142 cbz r2, 89ee + dsc->blend_mode); + 89dc: f89b 3009 ldrb.w r3, [fp, #9] + _lv_blend_fill(clip, &draw_area, + 89e0: f003 0303 and.w r3, r3, #3 + 89e4: e9cd 6301 strd r6, r3, [sp, #4] + 89e8: e69d b.n 8726 + if(lv_draw_mask_get_cnt()) simple_mode = false; + 89ea: 2200 movs r2, #0 + 89ec: e7da b.n 89a4 + is_common = _lv_area_intersect(&draw_area, clip, &draw_area); + 89ee: aa26 add r2, sp, #152 ; 0x98 + 89f0: a90a add r1, sp, #40 ; 0x28 + 89f2: 4610 mov r0, r2 + 89f4: 47a0 blx r4 + if(!is_common) return; + 89f6: 2800 cmp r0, #0 + 89f8: f43f ae9e beq.w 8738 + draw_area.x1 -= vdb->area.x1; + 89fc: 8a3b ldrh r3, [r7, #16] + 89fe: f8bd 4098 ldrh.w r4, [sp, #152] ; 0x98 + draw_area.y1 -= vdb->area.y1; + 8a02: f8b7 c012 ldrh.w ip, [r7, #18] + draw_area.x1 -= vdb->area.x1; + 8a06: f9bd 0098 ldrsh.w r0, [sp, #152] ; 0x98 + draw_area.x2 -= vdb->area.x1; + 8a0a: f8bd 609c ldrh.w r6, [sp, #156] ; 0x9c + fill_area.x1 = draw_area.x1 + disp_area->x1; + 8a0e: f8ad 00c4 strh.w r0, [sp, #196] ; 0xc4 + draw_area.x1 -= vdb->area.x1; + 8a12: 1ae2 subs r2, r4, r3 + 8a14: f8ad 2098 strh.w r2, [sp, #152] ; 0x98 + draw_area.y1 -= vdb->area.y1; + 8a18: f9bd 209a ldrsh.w r2, [sp, #154] ; 0x9a + fill_area.y1 = draw_area.y1 + disp_area->y1; + 8a1c: f8ad 20c6 strh.w r2, [sp, #198] ; 0xc6 + draw_area.y1 -= vdb->area.y1; + 8a20: eba2 010c sub.w r1, r2, ip + draw_area.x2 -= vdb->area.x1; + 8a24: 1af3 subs r3, r6, r3 + draw_area.y1 -= vdb->area.y1; + 8a26: f8ad 109a strh.w r1, [sp, #154] ; 0x9a + draw_area.x2 -= vdb->area.x1; + 8a2a: f9bd 109c ldrsh.w r1, [sp, #156] ; 0x9c + 8a2e: f8ad 309c strh.w r3, [sp, #156] ; 0x9c + draw_area.y2 -= vdb->area.y1; + 8a32: f8bd 309e ldrh.w r3, [sp, #158] ; 0x9e + fill_area.x2 = draw_area.x2 + disp_area->x1; + 8a36: f8ad 10c8 strh.w r1, [sp, #200] ; 0xc8 + 8a3a: 3601 adds r6, #1 + draw_area.y2 -= vdb->area.y1; + 8a3c: eba3 030c sub.w r3, r3, ip + 8a40: 1b36 subs r6, r6, r4 + 8a42: f8ad 309e strh.w r3, [sp, #158] ; 0x9e + 8a46: b233 sxth r3, r6 + lv_opa_t * mask_buf = _lv_mem_buf_get(draw_area_w); + 8a48: 4618 mov r0, r3 + 8a4a: ee08 3a10 vmov s16, r3 + fill_area.y2 = fill_area.y1; + 8a4e: f8ad 20ca strh.w r2, [sp, #202] ; 0xca + lv_opa_t * mask_buf = _lv_mem_buf_get(draw_area_w); + 8a52: 4b2f ldr r3, [pc, #188] ; (8b10 ) + 8a54: 4798 blx r3 + 8a56: 4680 mov r8, r0 + if(dashed) { + 8a58: b1c5 cbz r5, 8a8c + dash_start = (vdb->area.x1 + draw_area.x1) % (dsc->dash_gap + dsc->dash_width); + 8a5a: f9bd 3098 ldrsh.w r3, [sp, #152] ; 0x98 + 8a5e: f9b7 4010 ldrsh.w r4, [r7, #16] + 8a62: f9bb 2004 ldrsh.w r2, [fp, #4] + 8a66: 441c add r4, r3 + 8a68: f9bb 3006 ldrsh.w r3, [fp, #6] + 8a6c: 4413 add r3, r2 + 8a6e: fb94 f2f3 sdiv r2, r4, r3 + 8a72: fb03 4412 mls r4, r3, r2, r4 + 8a76: b224 sxth r4, r4 + for(h = draw_area.y1; h <= draw_area.y2; h++) { + 8a78: f9bd 909a ldrsh.w r9, [sp, #154] ; 0x9a + _lv_blend_fill(clip, &fill_area, + 8a7c: f8df a09c ldr.w sl, [pc, #156] ; 8b1c + for(h = draw_area.y1; h <= draw_area.y2; h++) { + 8a80: f9bd 309e ldrsh.w r3, [sp, #158] ; 0x9e + 8a84: 4599 cmp r9, r3 + 8a86: dd03 ble.n 8a90 + _lv_mem_buf_release(mask_buf); + 8a88: 4640 mov r0, r8 + 8a8a: e6fe b.n 888a + lv_style_int_t dash_start = 0; + 8a8c: 462c mov r4, r5 + 8a8e: e7f3 b.n 8a78 + _lv_memset_ff(mask_buf, draw_area_w); + 8a90: ee18 1a10 vmov r1, s16 + 8a94: 4b1f ldr r3, [pc, #124] ; (8b14 ) + lv_draw_mask_res_t mask_res = lv_draw_mask_apply(mask_buf, vdb->area.x1 + draw_area.x1, vdb->area.y1 + h, draw_area_w); + 8a96: 4e20 ldr r6, [pc, #128] ; (8b18 ) + _lv_memset_ff(mask_buf, draw_area_w); + 8a98: 4640 mov r0, r8 + 8a9a: 4798 blx r3 + lv_draw_mask_res_t mask_res = lv_draw_mask_apply(mask_buf, vdb->area.x1 + draw_area.x1, vdb->area.y1 + h, draw_area_w); + 8a9c: f8bd 3098 ldrh.w r3, [sp, #152] ; 0x98 + 8aa0: 8a7a ldrh r2, [r7, #18] + 8aa2: 8a39 ldrh r1, [r7, #16] + 8aa4: 444a add r2, r9 + 8aa6: 4419 add r1, r3 + 8aa8: b212 sxth r2, r2 + 8aaa: ee18 3a10 vmov r3, s16 + 8aae: b209 sxth r1, r1 + 8ab0: 4640 mov r0, r8 + 8ab2: 47b0 blx r6 + if(dashed) { + 8ab4: b16d cbz r5, 8ad2 + if(mask_res != LV_DRAW_MASK_RES_TRANSP) { + 8ab6: b150 cbz r0, 8ace + if(dash_cnt > dsc->dash_width) { + 8ab8: f9bb 2004 ldrsh.w r2, [fp, #4] + if(dash_cnt >= dsc->dash_gap + dsc->dash_width) { + 8abc: f9bb 3006 ldrsh.w r3, [fp, #6] + 8ac0: 4413 add r3, r2 + mask_res = LV_DRAW_MASK_RES_TRANSP; + 8ac2: 42a2 cmp r2, r4 + 8ac4: bfb8 it lt + 8ac6: 2000 movlt r0, #0 + dash_cnt = 0; + 8ac8: 429c cmp r4, r3 + 8aca: bfa8 it ge + 8acc: 2400 movge r4, #0 + dash_cnt ++; + 8ace: 3401 adds r4, #1 + 8ad0: b224 sxth r4, r4 + _lv_blend_fill(clip, &fill_area, + 8ad2: 2300 movs r3, #0 + 8ad4: 9302 str r3, [sp, #8] + 8ad6: f89b 3008 ldrb.w r3, [fp, #8] + 8ada: f8bb 2000 ldrh.w r2, [fp] + 8ade: e9cd 0300 strd r0, r3, [sp] + 8ae2: a931 add r1, sp, #196 ; 0xc4 + 8ae4: 4643 mov r3, r8 + 8ae6: a80a add r0, sp, #40 ; 0x28 + 8ae8: 47d0 blx sl + fill_area.y1++; + 8aea: f8bd 30c6 ldrh.w r3, [sp, #198] ; 0xc6 + 8aee: 3301 adds r3, #1 + 8af0: f8ad 30c6 strh.w r3, [sp, #198] ; 0xc6 + fill_area.y2++; + 8af4: f8bd 30ca ldrh.w r3, [sp, #202] ; 0xca + 8af8: 3301 adds r3, #1 + 8afa: f8ad 30ca strh.w r3, [sp, #202] ; 0xca + for(h = draw_area.y1; h <= draw_area.y2; h++) { + 8afe: f109 0901 add.w r9, r9, #1 + 8b02: e7bd b.n 8a80 + 8b04: 00004fe9 .word 0x00004fe9 + 8b08: 0000d9e1 .word 0x0000d9e1 + 8b0c: 000097f1 .word 0x000097f1 + 8b10: 0000eeb5 .word 0x0000eeb5 + 8b14: 0000f075 .word 0x0000f075 + 8b18: 00009761 .word 0x00009761 + 8b1c: 000061f1 .word 0x000061f1 + lv_draw_line_dsc_t * dsc) +{ + /*Keep the great y in p1*/ + lv_point_t p1; + lv_point_t p2; + if(point1->y < point2->y) { + 8b20: 45c1 cmp r9, r8 + 8b22: db05 blt.n 8b30 + 8b24: 464b mov r3, r9 + 8b26: 46c1 mov r9, r8 + 8b28: 4698 mov r8, r3 + 8b2a: 463b mov r3, r7 + 8b2c: 4637 mov r7, r6 + 8b2e: 461e mov r6, r3 + p2.y = point1->y; + p1.x = point2->x; + p2.x = point1->x; + } + + int32_t xdiff = p2.x - p1.x; + 8b30: 1bf3 subs r3, r6, r7 + 8b32: 9309 str r3, [sp, #36] ; 0x24 + int32_t ydiff = p2.y - p1.y; + 8b34: eba8 0309 sub.w r3, r8, r9 + 8b38: 9308 str r3, [sp, #32] + bool flat = LV_MATH_ABS(xdiff) > LV_MATH_ABS(ydiff) ? true : false; + 8b3a: 1bf3 subs r3, r6, r7 + 8b3c: ea83 72e3 eor.w r2, r3, r3, asr #31 + 8b40: eba2 72e3 sub.w r2, r2, r3, asr #31 + 8b44: 9b08 ldr r3, [sp, #32] + 8b46: 9207 str r2, [sp, #28] + 8b48: ea83 7ae3 eor.w sl, r3, r3, asr #31 + 8b4c: ebaa 7ae3 sub.w sl, sl, r3, asr #31 + 181, + }; + + int32_t w = dsc->width; + int32_t wcorr_i = 0; + if(flat) wcorr_i = (LV_MATH_ABS(ydiff) << 5) / LV_MATH_ABS(xdiff); + 8b50: 4552 cmp r2, sl + 8b52: 4613 mov r3, r2 + else wcorr_i = (LV_MATH_ABS(xdiff) << 5) / LV_MATH_ABS(ydiff); + 8b54: bfd8 it le + 8b56: 9b07 ldrle r3, [sp, #28] + int32_t w = dsc->width; + 8b58: f9bb 5002 ldrsh.w r5, [fp, #2] + if(flat) wcorr_i = (LV_MATH_ABS(ydiff) << 5) / LV_MATH_ABS(xdiff); + 8b5c: bfca itet gt + 8b5e: ea4f 134a movgt.w r3, sl, lsl #5 + else wcorr_i = (LV_MATH_ABS(xdiff) << 5) / LV_MATH_ABS(ydiff); + 8b62: 015b lslle r3, r3, #5 + if(flat) wcorr_i = (LV_MATH_ABS(ydiff) << 5) / LV_MATH_ABS(xdiff); + 8b64: fbb3 f3f2 udivgt r3, r3, r2 + + w = (w * wcorr[wcorr_i] + 63) >> 7; /*+ 63 for rounding*/ + 8b68: 4ab3 ldr r2, [pc, #716] ; (8e38 ) + else wcorr_i = (LV_MATH_ABS(xdiff) << 5) / LV_MATH_ABS(ydiff); + 8b6a: bfd8 it le + 8b6c: fbb3 f3fa udivle r3, r3, sl + w = (w * wcorr[wcorr_i] + 63) >> 7; /*+ 63 for rounding*/ + 8b70: 5cd2 ldrb r2, [r2, r3] + 8b72: 233f movs r3, #63 ; 0x3f + 8b74: fb15 3502 smlabb r5, r5, r2, r3 + int32_t w_half0 = w >> 1; + int32_t w_half1 = w_half0 + (w & 0x1); /*Compensate rounding error*/ + + lv_area_t draw_area; + draw_area.x1 = LV_MATH_MIN(p1.x, p2.x) - w; + 8b78: f3c5 13cf ubfx r3, r5, #7, #16 + 8b7c: 42be cmp r6, r7 + 8b7e: bfd4 ite le + 8b80: ebc3 0206 rsble r2, r3, r6 + 8b84: ebc3 0207 rsbgt r2, r3, r7 + 8b88: f8ad 2030 strh.w r2, [sp, #48] ; 0x30 + draw_area.x2 = LV_MATH_MAX(p1.x, p2.x) + w; + 8b8c: 42be cmp r6, r7 + 8b8e: bfac ite ge + 8b90: 199a addge r2, r3, r6 + 8b92: 19da addlt r2, r3, r7 + 8b94: f8ad 2034 strh.w r2, [sp, #52] ; 0x34 + draw_area.y2 = LV_MATH_MAX(p1.y, p2.y) + w; + + /* Get the union of `coords` and `clip`*/ + /* `clip` is already truncated to the `vdb` size + * in 'lv_refr_area' function */ + bool is_common = _lv_area_intersect(&draw_area, &draw_area, clip); + 8b98: a90c add r1, sp, #48 ; 0x30 + draw_area.y1 = LV_MATH_MIN(p1.y, p2.y) - w; + 8b9a: 45c8 cmp r8, r9 + 8b9c: bfd4 ite le + 8b9e: ebc3 0208 rsble r2, r3, r8 + 8ba2: ebc3 0209 rsbgt r2, r3, r9 + draw_area.y2 = LV_MATH_MAX(p1.y, p2.y) + w; + 8ba6: 45c8 cmp r8, r9 + 8ba8: bfac ite ge + 8baa: 4443 addge r3, r8 + 8bac: 444b addlt r3, r9 + draw_area.y1 = LV_MATH_MIN(p1.y, p2.y) - w; + 8bae: f8ad 2032 strh.w r2, [sp, #50] ; 0x32 + draw_area.y2 = LV_MATH_MAX(p1.y, p2.y) + w; + 8bb2: f8ad 3036 strh.w r3, [sp, #54] ; 0x36 + bool is_common = _lv_area_intersect(&draw_area, &draw_area, clip); + 8bb6: aa0a add r2, sp, #40 ; 0x28 + 8bb8: 4ba0 ldr r3, [pc, #640] ; (8e3c ) + 8bba: 4608 mov r0, r1 + w = (w * wcorr[wcorr_i] + 63) >> 7; /*+ 63 for rounding*/ + 8bbc: 11ec asrs r4, r5, #7 + bool is_common = _lv_area_intersect(&draw_area, &draw_area, clip); + 8bbe: 4798 blx r3 + if(is_common == false) return; + 8bc0: 2800 cmp r0, #0 + 8bc2: f43f adb9 beq.w 8738 + lv_draw_mask_line_param_t mask_left_param; + lv_draw_mask_line_param_t mask_right_param; + lv_draw_mask_line_param_t mask_top_param; + lv_draw_mask_line_param_t mask_bottom_param; + + if(flat) { + 8bc6: 9b07 ldr r3, [sp, #28] + int32_t w_half1 = w_half0 + (w & 0x1); /*Compensate rounding error*/ + 8bc8: f004 0401 and.w r4, r4, #1 + 8bcc: eb04 2425 add.w r4, r4, r5, asr #8 + if(flat) { + 8bd0: 4553 cmp r3, sl + if(xdiff > 0) { + lv_draw_mask_line_points_init(&mask_left_param, p1.x, p1.y - w_half0, p2.x, p2.y - w_half0, + LV_DRAW_MASK_LINE_SIDE_LEFT); + lv_draw_mask_line_points_init(&mask_right_param, p1.x, p1.y + w_half1, p2.x, p2.y + w_half1, + 8bd2: b2a4 uxth r4, r4 + lv_draw_mask_line_points_init(&mask_left_param, p1.x, p1.y - w_half0, p2.x, p2.y - w_half0, + 8bd4: f3c5 250f ubfx r5, r5, #8, #16 + if(flat) { + 8bd8: f340 80ed ble.w 8db6 + lv_draw_mask_line_points_init(&mask_right_param, p1.x, p1.y + w_half1, p2.x, p2.y + w_half1, + 8bdc: fa14 f389 uxtah r3, r4, r9 + 8be0: b21b sxth r3, r3 + 8be2: ee08 3a10 vmov s16, r3 + if(xdiff > 0) { + 8be6: 1bf3 subs r3, r6, r7 + lv_draw_mask_line_points_init(&mask_left_param, p1.x, p1.y - w_half0, p2.x, p2.y - w_half0, + 8be8: eba9 0a05 sub.w sl, r9, r5 + lv_draw_mask_line_points_init(&mask_right_param, p1.x, p1.y + w_half1, p2.x, p2.y + w_half1, + 8bec: fa14 f488 uxtah r4, r4, r8 + lv_draw_mask_line_points_init(&mask_left_param, p1.x, p1.y - w_half0, p2.x, p2.y - w_half0, + 8bf0: eba8 0505 sub.w r5, r8, r5 + if(xdiff > 0) { + 8bf4: 2b00 cmp r3, #0 + 8bf6: f04f 0300 mov.w r3, #0 + lv_draw_mask_line_points_init(&mask_right_param, p1.x, p1.y + w_half1, p2.x, p2.y + w_half1, + 8bfa: b224 sxth r4, r4 + lv_draw_mask_line_points_init(&mask_left_param, p1.x, p1.y - w_half0, p2.x, p2.y - w_half0, + 8bfc: fa0f fa8a sxth.w sl, sl + 8c00: b22d sxth r5, r5 + 8c02: 9301 str r3, [sp, #4] + if(xdiff > 0) { + 8c04: f340 80c6 ble.w 8d94 + lv_draw_mask_line_points_init(&mask_left_param, p1.x, p1.y - w_half0, p2.x, p2.y - w_half0, + 8c08: 9500 str r5, [sp, #0] + 8c0a: 4633 mov r3, r6 + 8c0c: 4652 mov r2, sl + 8c0e: 4639 mov r1, r7 + 8c10: a810 add r0, sp, #64 ; 0x40 + 8c12: 4d8b ldr r5, [pc, #556] ; (8e40 ) + 8c14: 47a8 blx r5 + lv_draw_mask_line_points_init(&mask_right_param, p1.x, p1.y + w_half1, p2.x, p2.y + w_half1, + 8c16: 2301 movs r3, #1 + 8c18: e9cd 4300 strd r4, r3, [sp] + 8c1c: ee18 2a10 vmov r2, s16 + 8c20: 4633 mov r3, r6 + 8c22: 4639 mov r1, r7 + 8c24: a81b add r0, sp, #108 ; 0x6c + 8c26: 47a8 blx r5 + LV_DRAW_MASK_LINE_SIDE_RIGHT); + } + + /*Use the normal vector for the endings*/ + + int16_t mask_left_id = lv_draw_mask_add(&mask_left_param, NULL); + 8c28: f8df a240 ldr.w sl, [pc, #576] ; 8e6c + 8c2c: 2100 movs r1, #0 + 8c2e: a810 add r0, sp, #64 ; 0x40 + 8c30: 47d0 blx sl + int16_t mask_right_id = lv_draw_mask_add(&mask_right_param, NULL); + 8c32: 2100 movs r1, #0 + int16_t mask_left_id = lv_draw_mask_add(&mask_left_param, NULL); + 8c34: ee09 0a10 vmov s18, r0 + int16_t mask_right_id = lv_draw_mask_add(&mask_right_param, NULL); + 8c38: a81b add r0, sp, #108 ; 0x6c + 8c3a: 47d0 blx sl + int16_t mask_top_id = LV_MASK_ID_INV; + int16_t mask_bottom_id = LV_MASK_ID_INV; + + if(!dsc->raw_end) { + 8c3c: f89b 5009 ldrb.w r5, [fp, #9] + 8c40: f015 0510 ands.w r5, r5, #16 + int16_t mask_right_id = lv_draw_mask_add(&mask_right_param, NULL); + 8c44: ee09 0a90 vmov s19, r0 + if(!dsc->raw_end) { + 8c48: f040 80cf bne.w 8dea + lv_draw_mask_line_points_init(&mask_top_param, p1.x, p1.y, p1.x - ydiff, p1.y + xdiff, LV_DRAW_MASK_LINE_SIDE_BOTTOM); + 8c4c: 2203 movs r2, #3 + 8c4e: f8bd 4020 ldrh.w r4, [sp, #32] + 8c52: 9201 str r2, [sp, #4] + 8c54: 1bf2 subs r2, r6, r7 + 8c56: f8bd 3024 ldrh.w r3, [sp, #36] ; 0x24 + 8c5a: 9307 str r3, [sp, #28] + 8c5c: fa19 f282 uxtah r2, r9, r2 + 8c60: 1b3b subs r3, r7, r4 + 8c62: b212 sxth r2, r2 + 8c64: 4639 mov r1, r7 + 8c66: 9200 str r2, [sp, #0] + 8c68: 4f75 ldr r7, [pc, #468] ; (8e40 ) + 8c6a: b21b sxth r3, r3 + 8c6c: 464a mov r2, r9 + 8c6e: a826 add r0, sp, #152 ; 0x98 + 8c70: 47b8 blx r7 + lv_draw_mask_line_points_init(&mask_bottom_param, p2.x, p2.y, p2.x - ydiff, p2.y + xdiff, LV_DRAW_MASK_LINE_SIDE_TOP); + 8c72: 2202 movs r2, #2 + 8c74: 9201 str r2, [sp, #4] + 8c76: 9a07 ldr r2, [sp, #28] + 8c78: 4442 add r2, r8 + 8c7a: b212 sxth r2, r2 + 8c7c: 1b33 subs r3, r6, r4 + 8c7e: b21b sxth r3, r3 + 8c80: 9200 str r2, [sp, #0] + 8c82: 4631 mov r1, r6 + 8c84: 4642 mov r2, r8 + 8c86: a831 add r0, sp, #196 ; 0xc4 + 8c88: 47b8 blx r7 + mask_top_id = lv_draw_mask_add(&mask_top_param, NULL); + 8c8a: 4629 mov r1, r5 + 8c8c: a826 add r0, sp, #152 ; 0x98 + 8c8e: 47d0 blx sl + mask_bottom_id = lv_draw_mask_add(&mask_bottom_param, NULL); + 8c90: 4629 mov r1, r5 + mask_top_id = lv_draw_mask_add(&mask_top_param, NULL); + 8c92: 9009 str r0, [sp, #36] ; 0x24 + mask_bottom_id = lv_draw_mask_add(&mask_bottom_param, NULL); + 8c94: a831 add r0, sp, #196 ; 0xc4 + 8c96: 47d0 blx sl + 8c98: 4682 mov sl, r0 + } + + lv_disp_t * disp = _lv_refr_get_disp_refreshing(); + 8c9a: 4b6a ldr r3, [pc, #424] ; (8e44 ) + * So deal with it only with steep lines. */ + int32_t draw_area_w = lv_area_get_width(&draw_area); + + /*Draw the background line by line*/ + int32_t h; + size_t mask_buf_size = LV_MATH_MIN(lv_area_get_size(&draw_area), LV_HOR_RES_MAX); + 8c9c: 4e6a ldr r6, [pc, #424] ; (8e48 ) + lv_disp_t * disp = _lv_refr_get_disp_refreshing(); + 8c9e: 4798 blx r3 + lv_disp_buf_t * vdb = lv_disp_get_buf(disp); + 8ca0: 4b6a ldr r3, [pc, #424] ; (8e4c ) + 8ca2: 4798 blx r3 + draw_area.x1 -= disp_area->x1; + 8ca4: f8bd 2030 ldrh.w r2, [sp, #48] ; 0x30 + 8ca8: 8a03 ldrh r3, [r0, #16] + draw_area.x2 -= disp_area->x1; + 8caa: f8bd 4034 ldrh.w r4, [sp, #52] ; 0x34 + draw_area.x1 -= disp_area->x1; + 8cae: 1ad1 subs r1, r2, r3 + draw_area.x2 -= disp_area->x1; + 8cb0: 1ae3 subs r3, r4, r3 + draw_area.x1 -= disp_area->x1; + 8cb2: f8ad 1030 strh.w r1, [sp, #48] ; 0x30 + draw_area.x2 -= disp_area->x1; + 8cb6: f8ad 3034 strh.w r3, [sp, #52] ; 0x34 + draw_area.y1 -= disp_area->y1; + 8cba: 8a41 ldrh r1, [r0, #18] + draw_area.y2 -= disp_area->y1; + 8cbc: f8bd 3036 ldrh.w r3, [sp, #54] ; 0x36 + lv_disp_buf_t * vdb = lv_disp_get_buf(disp); + 8cc0: 4605 mov r5, r0 + draw_area.y1 -= disp_area->y1; + 8cc2: f8bd 0032 ldrh.w r0, [sp, #50] ; 0x32 + 8cc6: 3401 adds r4, #1 + 8cc8: 1a40 subs r0, r0, r1 + draw_area.y2 -= disp_area->y1; + 8cca: 1a5b subs r3, r3, r1 + 8ccc: 1aa4 subs r4, r4, r2 + draw_area.y1 -= disp_area->y1; + 8cce: f8ad 0032 strh.w r0, [sp, #50] ; 0x32 + draw_area.y2 -= disp_area->y1; + 8cd2: f8ad 3036 strh.w r3, [sp, #54] ; 0x36 + size_t mask_buf_size = LV_MATH_MIN(lv_area_get_size(&draw_area), LV_HOR_RES_MAX); + 8cd6: a80c add r0, sp, #48 ; 0x30 + 8cd8: b223 sxth r3, r4 + 8cda: 9307 str r3, [sp, #28] + 8cdc: 47b0 blx r6 + 8cde: f5b0 7ff0 cmp.w r0, #480 ; 0x1e0 + 8ce2: f080 8087 bcs.w 8df4 + 8ce6: a80c add r0, sp, #48 ; 0x30 + 8ce8: 47b0 blx r6 + 8cea: 4607 mov r7, r0 + lv_opa_t * mask_buf = _lv_mem_buf_get(mask_buf_size); + 8cec: 4b58 ldr r3, [pc, #352] ; (8e50 ) + 8cee: 4638 mov r0, r7 + 8cf0: 4798 blx r3 + + lv_area_t fill_area; + fill_area.x1 = draw_area.x1 + disp_area->x1; + 8cf2: 8a2b ldrh r3, [r5, #16] + 8cf4: f8bd 2030 ldrh.w r2, [sp, #48] ; 0x30 + 8cf8: 441a add r2, r3 + 8cfa: b212 sxth r2, r2 + 8cfc: 9208 str r2, [sp, #32] + 8cfe: f8ad 2038 strh.w r2, [sp, #56] ; 0x38 + fill_area.x2 = draw_area.x2 + disp_area->x1; + 8d02: f8bd 2034 ldrh.w r2, [sp, #52] ; 0x34 + 8d06: 4413 add r3, r2 + 8d08: f8ad 303c strh.w r3, [sp, #60] ; 0x3c + fill_area.y1 = draw_area.y1 + disp_area->y1; + 8d0c: 8a6a ldrh r2, [r5, #18] + 8d0e: f8bd 3032 ldrh.w r3, [sp, #50] ; 0x32 + 8d12: 4413 add r3, r2 + 8d14: b21b sxth r3, r3 + 8d16: f8ad 303a strh.w r3, [sp, #58] ; 0x3a + fill_area.y2 = fill_area.y1; + 8d1a: f8ad 303e strh.w r3, [sp, #62] ; 0x3e + + int32_t x = vdb->area.x1 + draw_area.x1; + + uint32_t mask_p = 0; + + _lv_memset_ff(mask_buf, mask_buf_size); + 8d1e: 4639 mov r1, r7 + 8d20: 4b4c ldr r3, [pc, #304] ; (8e54 ) + lv_opa_t * mask_buf = _lv_mem_buf_get(mask_buf_size); + 8d22: 4606 mov r6, r0 + _lv_memset_ff(mask_buf, mask_buf_size); + 8d24: 4798 blx r3 + /*Fill the first row with 'color'*/ + for(h = draw_area.y1 + disp_area->y1; h <= draw_area.y2 + disp_area->y1; h++) { + 8d26: f9bd 8032 ldrsh.w r8, [sp, #50] ; 0x32 + 8d2a: f9b5 3012 ldrsh.w r3, [r5, #18] + uint32_t mask_p = 0; + 8d2e: f04f 0900 mov.w r9, #0 + for(h = draw_area.y1 + disp_area->y1; h <= draw_area.y2 + disp_area->y1; h++) { + 8d32: 4498 add r8, r3 + 8d34: f9bd 3036 ldrsh.w r3, [sp, #54] ; 0x36 + 8d38: f9b5 2012 ldrsh.w r2, [r5, #18] + 8d3c: 4413 add r3, r2 + 8d3e: 4598 cmp r8, r3 + 8d40: dd5b ble.n 8dfa + _lv_memset_ff(mask_buf, mask_buf_size); + } + } + + /*Flush the last part*/ + if(fill_area.y1 != fill_area.y2) { + 8d42: f9bd 303e ldrsh.w r3, [sp, #62] ; 0x3e + 8d46: f9bd 203a ldrsh.w r2, [sp, #58] ; 0x3a + 8d4a: 429a cmp r2, r3 + 8d4c: d013 beq.n 8d76 + fill_area.y2--; + 8d4e: 3b01 subs r3, #1 + 8d50: f8ad 303e strh.w r3, [sp, #62] ; 0x3e + _lv_blend_fill(&fill_area, clip, + dsc->color, mask_buf, LV_DRAW_MASK_RES_CHANGED, dsc->opa, + dsc->blend_mode); + 8d54: f89b 3009 ldrb.w r3, [fp, #9] + _lv_blend_fill(&fill_area, clip, + 8d58: f8bb 2000 ldrh.w r2, [fp] + 8d5c: 4c3e ldr r4, [pc, #248] ; (8e58 ) + 8d5e: f003 0303 and.w r3, r3, #3 + 8d62: 9302 str r3, [sp, #8] + 8d64: f89b 3008 ldrb.w r3, [fp, #8] + 8d68: 9301 str r3, [sp, #4] + 8d6a: 2302 movs r3, #2 + 8d6c: 9300 str r3, [sp, #0] + 8d6e: a90a add r1, sp, #40 ; 0x28 + 8d70: 4633 mov r3, r6 + 8d72: a80e add r0, sp, #56 ; 0x38 + 8d74: 47a0 blx r4 + + } + + _lv_mem_buf_release(mask_buf); + 8d76: 4b39 ldr r3, [pc, #228] ; (8e5c ) + + lv_draw_mask_remove_id(mask_left_id); + 8d78: 4c39 ldr r4, [pc, #228] ; (8e60 ) + _lv_mem_buf_release(mask_buf); + 8d7a: 4630 mov r0, r6 + 8d7c: 4798 blx r3 + lv_draw_mask_remove_id(mask_left_id); + 8d7e: ee19 0a10 vmov r0, s18 + 8d82: 47a0 blx r4 + lv_draw_mask_remove_id(mask_right_id); + 8d84: ee19 0a90 vmov r0, s19 + 8d88: 47a0 blx r4 + lv_draw_mask_remove_id(mask_top_id); + 8d8a: 9809 ldr r0, [sp, #36] ; 0x24 + 8d8c: 47a0 blx r4 + lv_draw_mask_remove_id(mask_bottom_id); + 8d8e: 4650 mov r0, sl + 8d90: 47a0 blx r4 + 8d92: e4d1 b.n 8738 + lv_draw_mask_line_points_init(&mask_left_param, p1.x, p1.y + w_half1, p2.x, p2.y + w_half1, + 8d94: ee18 2a10 vmov r2, s16 + 8d98: 9400 str r4, [sp, #0] + 8d9a: 4633 mov r3, r6 + 8d9c: 4639 mov r1, r7 + 8d9e: 4c28 ldr r4, [pc, #160] ; (8e40 ) + 8da0: a810 add r0, sp, #64 ; 0x40 + 8da2: 47a0 blx r4 + lv_draw_mask_line_points_init(&mask_right_param, p1.x, p1.y - w_half0, p2.x, p2.y - w_half0, + 8da4: 2301 movs r3, #1 + 8da6: e9cd 5300 strd r5, r3, [sp] + 8daa: 4652 mov r2, sl + 8dac: 4633 mov r3, r6 + 8dae: 4639 mov r1, r7 + lv_draw_mask_line_points_init(&mask_right_param, p1.x - w_half0, p1.y, p2.x - w_half0, p2.y, + 8db0: a81b add r0, sp, #108 ; 0x6c + 8db2: 47a0 blx r4 + 8db4: e738 b.n 8c28 + lv_draw_mask_line_points_init(&mask_left_param, p1.x + w_half1, p1.y, p2.x + w_half1, p2.y, + 8db6: fa14 f386 uxtah r3, r4, r6 + 8dba: 2200 movs r2, #0 + 8dbc: fa14 f487 uxtah r4, r4, r7 + 8dc0: b221 sxth r1, r4 + 8dc2: e9cd 8200 strd r8, r2, [sp] + 8dc6: b21b sxth r3, r3 + 8dc8: 464a mov r2, r9 + 8dca: 4c1d ldr r4, [pc, #116] ; (8e40 ) + 8dcc: a810 add r0, sp, #64 ; 0x40 + 8dce: 47a0 blx r4 + 8dd0: fa1f fa86 uxth.w sl, r6 + lv_draw_mask_line_points_init(&mask_right_param, p1.x - w_half0, p1.y, p2.x - w_half0, p2.y, + 8dd4: b2ba uxth r2, r7 + 8dd6: 1b51 subs r1, r2, r5 + 8dd8: ebaa 0305 sub.w r3, sl, r5 + 8ddc: 2201 movs r2, #1 + 8dde: e9cd 8200 strd r8, r2, [sp] + 8de2: b21b sxth r3, r3 + 8de4: 464a mov r2, r9 + 8de6: b209 sxth r1, r1 + 8de8: e7e2 b.n 8db0 + int16_t mask_bottom_id = LV_MASK_ID_INV; + 8dea: f04f 3aff mov.w sl, #4294967295 ; 0xffffffff + int16_t mask_top_id = LV_MASK_ID_INV; + 8dee: f8cd a024 str.w sl, [sp, #36] ; 0x24 + 8df2: e752 b.n 8c9a + size_t mask_buf_size = LV_MATH_MIN(lv_area_get_size(&draw_area), LV_HOR_RES_MAX); + 8df4: f44f 77f0 mov.w r7, #480 ; 0x1e0 + 8df8: e778 b.n 8cec + lv_draw_mask_res_t mask_res = lv_draw_mask_apply(&mask_buf[mask_p], x, h, draw_area_w); + 8dfa: eb06 0309 add.w r3, r6, r9 + 8dfe: ee08 3a10 vmov s16, r3 + 8e02: 9908 ldr r1, [sp, #32] + 8e04: 9b07 ldr r3, [sp, #28] + 8e06: 4c17 ldr r4, [pc, #92] ; (8e64 ) + 8e08: ee18 0a10 vmov r0, s16 + 8e0c: fa0f f288 sxth.w r2, r8 + 8e10: 47a0 blx r4 + if(mask_res == LV_DRAW_MASK_RES_TRANSP) { + 8e12: b920 cbnz r0, 8e1e + _lv_memset_00(&mask_buf[mask_p], draw_area_w); + 8e14: 9907 ldr r1, [sp, #28] + 8e16: 4b14 ldr r3, [pc, #80] ; (8e68 ) + 8e18: ee18 0a10 vmov r0, s16 + 8e1c: 4798 blx r3 + mask_p += draw_area_w; + 8e1e: 9b07 ldr r3, [sp, #28] + 8e20: 4499 add r9, r3 + if((uint32_t) mask_p + draw_area_w < mask_buf_size) { + 8e22: 444b add r3, r9 + 8e24: 429f cmp r7, r3 + 8e26: d923 bls.n 8e70 + fill_area.y2 ++; + 8e28: f8bd 303e ldrh.w r3, [sp, #62] ; 0x3e + 8e2c: 3301 adds r3, #1 + 8e2e: f8ad 303e strh.w r3, [sp, #62] ; 0x3e + for(h = draw_area.y1 + disp_area->y1; h <= draw_area.y2 + disp_area->y1; h++) { + 8e32: f108 0801 add.w r8, r8, #1 + 8e36: e77d b.n 8d34 + 8e38: 0001fce2 .word 0x0001fce2 + 8e3c: 0000de8d .word 0x0000de8d + 8e40: 0000980d .word 0x0000980d + 8e44: 00004fe9 .word 0x00004fe9 + 8e48: 0000de71 .word 0x0000de71 + 8e4c: 0000d9e1 .word 0x0000d9e1 + 8e50: 0000eeb5 .word 0x0000eeb5 + 8e54: 0000f075 .word 0x0000f075 + 8e58: 000061f1 .word 0x000061f1 + 8e5c: 0000eb69 .word 0x0000eb69 + 8e60: 000097a1 .word 0x000097a1 + 8e64: 00009761 .word 0x00009761 + 8e68: 0000f019 .word 0x0000f019 + 8e6c: 00009711 .word 0x00009711 + dsc->blend_mode); + 8e70: f89b 3009 ldrb.w r3, [fp, #9] + _lv_blend_fill(&fill_area, clip, + 8e74: f8bb 2000 ldrh.w r2, [fp] + 8e78: 4c0d ldr r4, [pc, #52] ; (8eb0 ) + 8e7a: f003 0303 and.w r3, r3, #3 + 8e7e: 9302 str r3, [sp, #8] + 8e80: f89b 3008 ldrb.w r3, [fp, #8] + 8e84: 9301 str r3, [sp, #4] + 8e86: 2302 movs r3, #2 + 8e88: 9300 str r3, [sp, #0] + 8e8a: a90a add r1, sp, #40 ; 0x28 + 8e8c: 4633 mov r3, r6 + 8e8e: a80e add r0, sp, #56 ; 0x38 + 8e90: 47a0 blx r4 + fill_area.y1 = fill_area.y2 + 1; + 8e92: f8bd 303e ldrh.w r3, [sp, #62] ; 0x3e + 8e96: 3301 adds r3, #1 + 8e98: b21b sxth r3, r3 + 8e9a: f8ad 303a strh.w r3, [sp, #58] ; 0x3a + fill_area.y2 = fill_area.y1; + 8e9e: f8ad 303e strh.w r3, [sp, #62] ; 0x3e + _lv_memset_ff(mask_buf, mask_buf_size); + 8ea2: 4639 mov r1, r7 + 8ea4: 4b03 ldr r3, [pc, #12] ; (8eb4 ) + 8ea6: 4630 mov r0, r6 + 8ea8: 4798 blx r3 + mask_p = 0; + 8eaa: f04f 0900 mov.w r9, #0 + 8eae: e7c0 b.n 8e32 + 8eb0: 000061f1 .word 0x000061f1 + 8eb4: 0000f075 .word 0x0000f075 + +00008eb8 : +} + + +LV_ATTRIBUTE_FAST_MEM static inline lv_opa_t mask_mix(lv_opa_t mask_act, lv_opa_t mask_new) +{ + if(mask_new >= LV_OPA_MAX) return mask_act; + 8eb8: 29f9 cmp r1, #249 ; 0xf9 + 8eba: d80a bhi.n 8ed2 + if(mask_new <= LV_OPA_MIN) return 0; + 8ebc: 2905 cmp r1, #5 + 8ebe: d907 bls.n 8ed0 + + return LV_MATH_UDIV255(mask_act * mask_new);// >> 8); + 8ec0: fb10 f001 smulbb r0, r0, r1 + 8ec4: f248 0381 movw r3, #32897 ; 0x8081 + 8ec8: 4358 muls r0, r3 + 8eca: f3c0 50c7 ubfx r0, r0, #23, #8 + 8ece: 4770 bx lr + if(mask_new <= LV_OPA_MIN) return 0; + 8ed0: 2000 movs r0, #0 +} + 8ed2: 4770 bx lr + +00008ed4 : +{ + 8ed4: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 8ed8: 9e08 ldr r6, [sp, #32] + 8eda: 461c mov r4, r3 + abs_y -= p->origo.y; + 8edc: 8ab3 ldrh r3, [r6, #20] + 8ede: 1ad2 subs r2, r2, r3 + abs_x -= p->origo.x; + 8ee0: 8a73 ldrh r3, [r6, #18] + 8ee2: 1ac9 subs r1, r1, r3 + 8ee4: b20f sxth r7, r1 + if(p->flat) { + 8ee6: f896 3028 ldrb.w r3, [r6, #40] ; 0x28 + if(p->steep == 0) { + 8eea: 6a31 ldr r1, [r6, #32] +{ + 8eec: 4605 mov r5, r0 + abs_y -= p->origo.y; + 8eee: b212 sxth r2, r2 + if(p->flat) { + 8ef0: f003 0001 and.w r0, r3, #1 + if(p->steep == 0) { + 8ef4: bb99 cbnz r1, 8f5e + if(p->cfg.side == LV_DRAW_MASK_LINE_SIDE_LEFT || + 8ef6: 7c33 ldrb r3, [r6, #16] + 8ef8: f003 0602 and.w r6, r3, #2 + if(p->flat) { + 8efc: b180 cbz r0, 8f20 + if(p->cfg.side == LV_DRAW_MASK_LINE_SIDE_LEFT || + 8efe: b13e cbz r6, 8f10 + else if(p->cfg.side == LV_DRAW_MASK_LINE_SIDE_TOP && abs_y + 1 < 0) return LV_DRAW_MASK_RES_FULL_COVER; + 8f00: f003 0303 and.w r3, r3, #3 + 8f04: 2b02 cmp r3, #2 + 8f06: d105 bne.n 8f14 + p->cfg.side == LV_DRAW_MASK_LINE_SIDE_RIGHT) return LV_DRAW_MASK_RES_FULL_COVER; + 8f08: 3201 adds r2, #1 + 8f0a: bfac ite ge + 8f0c: 2000 movge r0, #0 + 8f0e: 2001 movlt r0, #1 +} + 8f10: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + else if(p->cfg.side == LV_DRAW_MASK_LINE_SIDE_BOTTOM && abs_y > 0) return LV_DRAW_MASK_RES_FULL_COVER; + 8f14: 2b03 cmp r3, #3 + 8f16: d101 bne.n 8f1c + 8f18: 2a00 cmp r2, #0 + 8f1a: dcf9 bgt.n 8f10 + return LV_DRAW_MASK_RES_TRANSP; + 8f1c: 2000 movs r0, #0 + 8f1e: e7f7 b.n 8f10 + if(p->cfg.side == LV_DRAW_MASK_LINE_SIDE_TOP || + 8f20: 2e00 cmp r6, #0 + 8f22: f040 8187 bne.w 9234 + else if(p->cfg.side == LV_DRAW_MASK_LINE_SIDE_RIGHT && abs_x > 0) return LV_DRAW_MASK_RES_FULL_COVER; + 8f26: f003 0003 and.w r0, r3, #3 + 8f2a: 2801 cmp r0, #1 + 8f2c: d10a bne.n 8f44 + 8f2e: 2f00 cmp r7, #0 + 8f30: dcee bgt.n 8f10 + if(abs_x + len < 0) return LV_DRAW_MASK_RES_TRANSP; + 8f32: 42e7 cmn r7, r4 + 8f34: d4f2 bmi.n 8f1c + if(k < 0) k = 0; + 8f36: 2f00 cmp r7, #0 + 8f38: f300 817e bgt.w 9238 + int32_t k = - abs_x; + 8f3c: 4279 negs r1, r7 + if(k >= len) return LV_DRAW_MASK_RES_TRANSP; + 8f3e: 428c cmp r4, r1 + 8f40: ddec ble.n 8f1c + 8f42: e09b b.n 907c + else if(p->cfg.side == LV_DRAW_MASK_LINE_SIDE_LEFT) { + 8f44: 2800 cmp r0, #0 + 8f46: d1f4 bne.n 8f32 + if(abs_x + len < 0) return LV_DRAW_MASK_RES_FULL_COVER; + 8f48: 1939 adds r1, r7, r4 + 8f4a: f100 8173 bmi.w 9234 + if(k < 0) return LV_DRAW_MASK_RES_TRANSP; + 8f4e: 2f00 cmp r7, #0 + 8f50: dce4 bgt.n 8f1c + int32_t k = - abs_x; + 8f52: 4278 negs r0, r7 + if(k >= 0 && k < len) _lv_memset_00(&mask_buf[k], len - k); + 8f54: 42a0 cmp r0, r4 + 8f56: f2c0 809c blt.w 9092 + return LV_DRAW_MASK_RES_CHANGED; + 8f5a: 2002 movs r0, #2 + 8f5c: e7d8 b.n 8f10 + if(p->flat) { + 8f5e: f003 0c02 and.w ip, r3, #2 + 8f62: 2800 cmp r0, #0 + 8f64: f000 8097 beq.w 9096 + y_at_x = (int32_t)((int32_t)p->yx_steep * abs_x) >> 10; + 8f68: 69f1 ldr r1, [r6, #28] + 8f6a: fb07 f301 mul.w r3, r7, r1 + if(p->yx_steep > 0) { + 8f6e: 2900 cmp r1, #0 + y_at_x = (int32_t)((int32_t)p->yx_steep * abs_x) >> 10; + 8f70: ea4f 23a3 mov.w r3, r3, asr #10 + if(p->inv) { + 8f74: fa5f f08c uxtb.w r0, ip + if(p->yx_steep > 0) { + 8f78: dd05 ble.n 8f86 + if(y_at_x > abs_y) { + 8f7a: 429a cmp r2, r3 + 8f7c: da05 bge.n 8f8a + p->cfg.side == LV_DRAW_MASK_LINE_SIDE_RIGHT) return LV_DRAW_MASK_RES_FULL_COVER; + 8f7e: 3800 subs r0, #0 + 8f80: bf18 it ne + 8f82: 2001 movne r0, #1 + 8f84: e7c4 b.n 8f10 + if(y_at_x < abs_y) { + 8f86: 429a cmp r2, r3 + 8f88: dcf9 bgt.n 8f7e + y_at_x = (int32_t)((int32_t)p->yx_steep * (abs_x + len)) >> 10; + 8f8a: 193b adds r3, r7, r4 + 8f8c: 434b muls r3, r1 + if(p->yx_steep > 0) { + 8f8e: 2900 cmp r1, #0 + y_at_x = (int32_t)((int32_t)p->yx_steep * (abs_x + len)) >> 10; + 8f90: ea4f 23a3 mov.w r3, r3, asr #10 + if(p->yx_steep > 0) { + 8f94: dd05 ble.n 8fa2 + if(y_at_x < abs_y) { + 8f96: 429a cmp r2, r3 + 8f98: dd06 ble.n 8fa8 + p->cfg.side == LV_DRAW_MASK_LINE_SIDE_RIGHT) return LV_DRAW_MASK_RES_FULL_COVER; + 8f9a: fab0 f080 clz r0, r0 + 8f9e: 0940 lsrs r0, r0, #5 + 8fa0: e7b6 b.n 8f10 + if(y_at_x > abs_y) { + 8fa2: 429a cmp r2, r3 + 8fa4: dbf9 blt.n 8f9a + else xe = (((abs_y + 1) << 8) * p->xy_steep) >> 10; + 8fa6: 3201 adds r2, #1 + 8fa8: 69b3 ldr r3, [r6, #24] + 8faa: 0212 lsls r2, r2, #8 + 8fac: 435a muls r2, r3 + 8fae: 1292 asrs r2, r2, #10 + int32_t xei = xe >> 8; + 8fb0: 1211 asrs r1, r2, #8 + if(xef == 0) px_h = 255; + 8fb2: f012 02ff ands.w r2, r2, #255 ; 0xff + else px_h = 255 - (((255 - xef) * p->spx) >> 8); + 8fb6: bf1f itttt ne + 8fb8: 6a73 ldrne r3, [r6, #36] ; 0x24 + 8fba: f1c2 08ff rsbne r8, r2, #255 ; 0xff + 8fbe: fb03 f808 mulne.w r8, r3, r8 + 8fc2: ea4f 2828 movne.w r8, r8, asr #8 + 8fc6: bf14 ite ne + 8fc8: f1c8 08ff rsbne r8, r8, #255 ; 0xff + if(xef == 0) px_h = 255; + 8fcc: f04f 08ff moveq.w r8, #255 ; 0xff + int32_t k = xei - abs_x; + 8fd0: 1bcf subs r7, r1, r7 + if(xef) { + 8fd2: 2a00 cmp r2, #0 + 8fd4: d054 beq.n 9080 + if(k >= 0 && k < len) { + 8fd6: 2f00 cmp r7, #0 + 8fd8: db0f blt.n 8ffa + 8fda: 42bc cmp r4, r7 + 8fdc: dd0d ble.n 8ffa + m = 255 - (((255 - xef) * (255 - px_h)) >> 9); + 8fde: f1c2 01ff rsb r1, r2, #255 ; 0xff + 8fe2: f1c8 03ff rsb r3, r8, #255 ; 0xff + 8fe6: 4359 muls r1, r3 + 8fe8: f3c1 2147 ubfx r1, r1, #9, #8 + if(p->inv) m = 255 - m; + 8fec: b908 cbnz r0, 8ff2 + m = 255 - (((255 - xef) * (255 - px_h)) >> 9); + 8fee: 43c9 mvns r1, r1 + 8ff0: b2c9 uxtb r1, r1 + mask_buf[k] = mask_mix(mask_buf[k], m); + 8ff2: 5de8 ldrb r0, [r5, r7] + 8ff4: 4ba3 ldr r3, [pc, #652] ; (9284 ) + 8ff6: 4798 blx r3 + 8ff8: 55e8 strb r0, [r5, r7] + k++; + 8ffa: 1c7a adds r2, r7, #1 + mask_buf[k] = mask_mix(mask_buf[k], m); + 8ffc: f8df 9284 ldr.w r9, [pc, #644] ; 9284 + while(px_h > p->spx) { + 9000: 6a71 ldr r1, [r6, #36] ; 0x24 + if(p->inv) m = 255 - m; + 9002: f896 3028 ldrb.w r3, [r6, #40] ; 0x28 + while(px_h > p->spx) { + 9006: 4588 cmp r8, r1 + if(p->inv) m = 255 - m; + 9008: f003 0302 and.w r3, r3, #2 + while(px_h > p->spx) { + 900c: dc18 bgt.n 9040 + if(k < len && k >= 0) { + 900e: 4294 cmp r4, r2 + 9010: dd29 ble.n 9066 + 9012: 2a00 cmp r2, #0 + 9014: db27 blt.n 9066 + int32_t x_inters = (px_h * p->xy_steep) >> 10; + 9016: 69b1 ldr r1, [r6, #24] + if(p->yx_steep < 0) m = 255 - m; + 9018: 69f0 ldr r0, [r6, #28] + int32_t x_inters = (px_h * p->xy_steep) >> 10; + 901a: fb01 f108 mul.w r1, r1, r8 + 901e: 1289 asrs r1, r1, #10 + m = (x_inters * px_h) >> 9; + 9020: fb08 f101 mul.w r1, r8, r1 + 9024: f3c1 2147 ubfx r1, r1, #9, #8 + if(p->yx_steep < 0) m = 255 - m; + 9028: 2800 cmp r0, #0 + 902a: bfbc itt lt + 902c: 43c9 mvnlt r1, r1 + 902e: b2c9 uxtblt r1, r1 + if(p->inv) m = 255 - m; + 9030: b10b cbz r3, 9036 + 9032: 43c9 mvns r1, r1 + 9034: b2c9 uxtb r1, r1 + mask_buf[k] = mask_mix(mask_buf[k], m); + 9036: 5ca8 ldrb r0, [r5, r2] + 9038: 4b92 ldr r3, [pc, #584] ; (9284 ) + 903a: 4798 blx r3 + 903c: 54a8 strb r0, [r5, r2] + 903e: e012 b.n 9066 + if(k >= 0 && k < len) { + 9040: 2a00 cmp r2, #0 + 9042: db0a blt.n 905a + 9044: 4294 cmp r4, r2 + 9046: dd08 ble.n 905a + m = px_h - (p->spx >> 1); + 9048: eba8 0161 sub.w r1, r8, r1, asr #1 + 904c: b2c9 uxtb r1, r1 + if(p->inv) m = 255 - m; + 904e: b10b cbz r3, 9054 + 9050: 43c9 mvns r1, r1 + 9052: b2c9 uxtb r1, r1 + mask_buf[k] = mask_mix(mask_buf[k], m); + 9054: 5ca8 ldrb r0, [r5, r2] + 9056: 47c8 blx r9 + 9058: 54a8 strb r0, [r5, r2] + px_h -= p->spx; + 905a: 6a73 ldr r3, [r6, #36] ; 0x24 + k++; + 905c: 3201 adds r2, #1 + if(k >= len) break; + 905e: 4294 cmp r4, r2 + px_h -= p->spx; + 9060: eba8 0803 sub.w r8, r8, r3 + if(k >= len) break; + 9064: dccc bgt.n 9000 + if(p->inv) { + 9066: f896 3028 ldrb.w r3, [r6, #40] ; 0x28 + 906a: 0799 lsls r1, r3, #30 + 906c: d50a bpl.n 9084 + if(k > len) { + 906e: 42bc cmp r4, r7 + 9070: f6ff af54 blt.w 8f1c + if(k >= 0) { + 9074: 2f00 cmp r7, #0 + 9076: f6ff af70 blt.w 8f5a + _lv_memset_00(&mask_buf[0], k); + 907a: 4639 mov r1, r7 + if(k >= 0) _lv_memset_00(&mask_buf[0], k); + 907c: 4628 mov r0, r5 + 907e: e083 b.n 9188 + int32_t k = xei - abs_x; + 9080: 463a mov r2, r7 + 9082: e7bb b.n 8ffc + if(k < 0) { + 9084: 1c50 adds r0, r2, #1 + 9086: f53f af49 bmi.w 8f1c + if(k <= len) { + 908a: 4284 cmp r4, r0 + if(k >= 0) _lv_memset_00(&mask_buf[k], len - k); + 908c: f6ff af65 blt.w 8f5a + 9090: 1a21 subs r1, r4, r0 + 9092: 4428 add r0, r5 + 9094: e078 b.n 9188 + x_at_y = (int32_t)((int32_t)p->xy_steep * abs_y) >> 10; + 9096: 69b1 ldr r1, [r6, #24] + 9098: fb01 f302 mul.w r3, r1, r2 + if(p->xy_steep > 0) x_at_y++; + 909c: 2900 cmp r1, #0 + x_at_y = (int32_t)((int32_t)p->xy_steep * abs_y) >> 10; + 909e: ea4f 23a3 mov.w r3, r3, asr #10 + if(p->xy_steep > 0) x_at_y++; + 90a2: bfcc ite gt + 90a4: f103 0e01 addgt.w lr, r3, #1 + x_at_y = (int32_t)((int32_t)p->xy_steep * abs_y) >> 10; + 90a8: 469e movle lr, r3 + if(x_at_y < abs_x) { + 90aa: 4577 cmp r7, lr + if(p->inv) { + 90ac: fa5f f08c uxtb.w r0, ip + if(x_at_y < abs_x) { + 90b0: f73f af65 bgt.w 8f7e + if(x_at_y > abs_x + len) { + 90b4: eb07 0c04 add.w ip, r7, r4 + 90b8: 4563 cmp r3, ip + 90ba: f73f af6e bgt.w 8f9a + int32_t xs = ((abs_y << 8) * p->xy_steep) >> 10; + 90be: ea4f 2c02 mov.w ip, r2, lsl #8 + int32_t xe = (((abs_y + 1) << 8) * p->xy_steep) >> 10; + 90c2: 3201 adds r2, #1 + 90c4: 0212 lsls r2, r2, #8 + 90c6: 434a muls r2, r1 + int32_t xs = ((abs_y << 8) * p->xy_steep) >> 10; + 90c8: fb01 fc0c mul.w ip, r1, ip + int32_t xei = xe >> 8; + 90cc: ea4f 49a2 mov.w r9, r2, asr #18 + if(xsi != xei && (p->xy_steep < 0 && xsf == 0)) { + 90d0: ebb9 4fac cmp.w r9, ip, asr #18 + int32_t xsf = xs & 0xFF; + 90d4: f3cc 2387 ubfx r3, ip, #10, #8 + k = xsi - abs_x; + 90d8: ebc7 4aac rsb sl, r7, ip, asr #18 + if(xsi != xei && (p->xy_steep < 0 && xsf == 0)) { + 90dc: f000 80ae beq.w 923c + 90e0: 2900 cmp r1, #0 + 90e2: da5a bge.n 919a + k--; + 90e4: f10a 38ff add.w r8, sl, #4294967295 ; 0xffffffff + if(xsi != xei && (p->xy_steep < 0 && xsf == 0)) { + 90e8: 2b00 cmp r3, #0 + 90ea: f000 80c9 beq.w 9280 + y_inters = (xsf * (-p->yx_steep)) >> 10; + 90ee: 69f2 ldr r2, [r6, #28] + 90f0: 4252 negs r2, r2 + 90f2: 435a muls r2, r3 + if(k >= 0 && k < len) { + 90f4: f1ba 0f00 cmp.w sl, #0 + y_inters = (xsf * (-p->yx_steep)) >> 10; + 90f8: ea4f 22a2 mov.w r2, r2, asr #10 + if(k >= 0 && k < len) { + 90fc: db0d blt.n 911a + 90fe: 4554 cmp r4, sl + 9100: dd0b ble.n 911a + m = (y_inters * xsf) >> 9; + 9102: 4353 muls r3, r2 + 9104: f3c3 2147 ubfx r1, r3, #9, #8 + if(p->inv) m = 255 - m; + 9108: b108 cbz r0, 910e + 910a: 43c9 mvns r1, r1 + 910c: b2c9 uxtb r1, r1 + mask_buf[k] = mask_mix(mask_buf[k], m); + 910e: f815 000a ldrb.w r0, [r5, sl] + 9112: 4b5c ldr r3, [pc, #368] ; (9284 ) + 9114: 4798 blx r3 + 9116: f805 000a strb.w r0, [r5, sl] + if(k >= 0 && k < len) { + 911a: f1b8 0f00 cmp.w r8, #0 + 911e: db17 blt.n 9150 + 9120: 4544 cmp r4, r8 + 9122: dd15 ble.n 9150 + int32_t x_inters = ((255 - y_inters) * (-p->xy_steep)) >> 10; + 9124: 69b3 ldr r3, [r6, #24] + mask_buf[k] = mask_mix(mask_buf[k], m); + 9126: f815 0008 ldrb.w r0, [r5, r8] + int32_t x_inters = ((255 - y_inters) * (-p->xy_steep)) >> 10; + 912a: f1c2 02ff rsb r2, r2, #255 ; 0xff + 912e: 4259 negs r1, r3 + 9130: 4351 muls r1, r2 + if(p->inv) m = 255 - m; + 9132: f896 3028 ldrb.w r3, [r6, #40] ; 0x28 + int32_t x_inters = ((255 - y_inters) * (-p->xy_steep)) >> 10; + 9136: 1289 asrs r1, r1, #10 + m = 255 - (((255 - y_inters) * x_inters) >> 9); + 9138: 4351 muls r1, r2 + if(p->inv) m = 255 - m; + 913a: 079f lsls r7, r3, #30 + m = 255 - (((255 - y_inters) * x_inters) >> 9); + 913c: f3c1 2147 ubfx r1, r1, #9, #8 + 9140: bf58 it pl + 9142: 43c9 mvnpl r1, r1 + mask_buf[k] = mask_mix(mask_buf[k], m); + 9144: 4b4f ldr r3, [pc, #316] ; (9284 ) + m = 255 - (((255 - y_inters) * x_inters) >> 9); + 9146: bf58 it pl + 9148: b2c9 uxtbpl r1, r1 + mask_buf[k] = mask_mix(mask_buf[k], m); + 914a: 4798 blx r3 + 914c: f805 0008 strb.w r0, [r5, r8] + if(p->inv) { + 9150: f896 3028 ldrb.w r3, [r6, #40] ; 0x28 + 9154: 079e lsls r6, r3, #30 + 9156: d51a bpl.n 918e + if(k > len) k = len; + 9158: 4544 cmp r4, r8 + 915a: f6ff aefe blt.w 8f5a + else if(k > 0) _lv_memset_00(&mask_buf[0], k); + 915e: f1b8 0f00 cmp.w r8, #0 + 9162: f77f aefa ble.w 8f5a + 9166: 4641 mov r1, r8 + 9168: e788 b.n 907c + k++; + 916a: f108 0801 add.w r8, r8, #1 + 916e: 45a0 cmp r8, r4 + 9170: bfa8 it ge + 9172: 46a0 movge r8, r4 + if(k == 0) return LV_DRAW_MASK_RES_TRANSP; + 9174: f1b8 0f00 cmp.w r8, #0 + 9178: f43f aed0 beq.w 8f1c + else if(k > 0) _lv_memset_00(&mask_buf[k], len - k); + 917c: f77f aeed ble.w 8f5a + 9180: eba4 0108 sub.w r1, r4, r8 + 9184: eb05 0008 add.w r0, r5, r8 + else if(k > 0) _lv_memset_00(&mask_buf[k], len - k); + 9188: 4b3f ldr r3, [pc, #252] ; (9288 ) + 918a: 4798 blx r3 + 918c: e6e5 b.n 8f5a + k += 2; + 918e: f10a 0001 add.w r0, sl, #1 + if(k > len) return LV_DRAW_MASK_RES_FULL_COVER; + 9192: 4284 cmp r4, r0 + 9194: db4e blt.n 9234 + if(k >= 0) _lv_memset_00(&mask_buf[k], len - k); + 9196: 2800 cmp r0, #0 + 9198: e778 b.n 908c + y_inters = ((255 - xsf) * p->yx_steep) >> 10; + 919a: 69f7 ldr r7, [r6, #28] + 919c: f1c3 03ff rsb r3, r3, #255 ; 0xff + 91a0: 435f muls r7, r3 + if(k >= 0 && k < len) { + 91a2: f1ba 0f00 cmp.w sl, #0 + y_inters = ((255 - xsf) * p->yx_steep) >> 10; + 91a6: ea4f 27a7 mov.w r7, r7, asr #10 + if(k >= 0 && k < len) { + 91aa: db0d blt.n 91c8 + 91ac: 4554 cmp r4, sl + 91ae: dd0b ble.n 91c8 + m = 255 - ((y_inters * (255 - xsf)) >> 9); + 91b0: 437b muls r3, r7 + 91b2: f3c3 2147 ubfx r1, r3, #9, #8 + if(p->inv) m = 255 - m; + 91b6: b908 cbnz r0, 91bc + m = 255 - ((y_inters * (255 - xsf)) >> 9); + 91b8: 43c9 mvns r1, r1 + 91ba: b2c9 uxtb r1, r1 + mask_buf[k] = mask_mix(mask_buf[k], m); + 91bc: f815 000a ldrb.w r0, [r5, sl] + 91c0: 4b30 ldr r3, [pc, #192] ; (9284 ) + 91c2: 4798 blx r3 + 91c4: f805 000a strb.w r0, [r5, sl] + if(k >= 0 && k < len) { + 91c8: f11a 0201 adds.w r2, sl, #1 + 91cc: d415 bmi.n 91fa + 91ce: 4294 cmp r4, r2 + 91d0: dd13 ble.n 91fa + int32_t x_inters = ((255 - y_inters) * p->xy_steep) >> 10; + 91d2: 69b3 ldr r3, [r6, #24] + 91d4: f1c7 07ff rsb r7, r7, #255 ; 0xff + 91d8: fb03 f107 mul.w r1, r3, r7 + 91dc: 1289 asrs r1, r1, #10 + if(p->inv) m = 255 - m; + 91de: f896 3028 ldrb.w r3, [r6, #40] ; 0x28 + m = ((255 - y_inters) * x_inters) >> 9; + 91e2: 4379 muls r1, r7 + if(p->inv) m = 255 - m; + 91e4: 0798 lsls r0, r3, #30 + m = ((255 - y_inters) * x_inters) >> 9; + 91e6: f3c1 2147 ubfx r1, r1, #9, #8 + if(p->inv) m = 255 - m; + 91ea: bf48 it mi + 91ec: 43c9 mvnmi r1, r1 + mask_buf[k] = mask_mix(mask_buf[k], m); + 91ee: 5ca8 ldrb r0, [r5, r2] + 91f0: 4b24 ldr r3, [pc, #144] ; (9284 ) + if(p->inv) m = 255 - m; + 91f2: bf48 it mi + 91f4: b2c9 uxtbmi r1, r1 + mask_buf[k] = mask_mix(mask_buf[k], m); + 91f6: 4798 blx r3 + 91f8: 54a8 strb r0, [r5, r2] + if(p->inv) { + 91fa: f896 3028 ldrb.w r3, [r6, #40] ; 0x28 + 91fe: 079b lsls r3, r3, #30 + 9200: d508 bpl.n 9214 + if(k > len) return LV_DRAW_MASK_RES_TRANSP; + 9202: 4554 cmp r4, sl + 9204: f6ff ae8a blt.w 8f1c + if(k >= 0) _lv_memset_00(&mask_buf[0], k); + 9208: f1ba 0f00 cmp.w sl, #0 + 920c: f6ff aea5 blt.w 8f5a + 9210: 4651 mov r1, sl + 9212: e733 b.n 907c + k++; + 9214: f10a 0a02 add.w sl, sl, #2 + 9218: 45a2 cmp sl, r4 + 921a: bfa8 it ge + 921c: 46a2 movge sl, r4 + if(k == 0) return LV_DRAW_MASK_RES_TRANSP; + 921e: f1ba 0f00 cmp.w sl, #0 + 9222: f43f ae7b beq.w 8f1c + else if(k > 0) _lv_memset_00(&mask_buf[k], len - k); + 9226: f77f ae98 ble.w 8f5a + 922a: eba4 010a sub.w r1, r4, sl + 922e: eb05 000a add.w r0, r5, sl + 9232: e7a9 b.n 9188 + if(k > len) return LV_DRAW_MASK_RES_FULL_COVER; + 9234: 2001 movs r0, #1 + 9236: e66b b.n 8f10 + if(k >= len) return LV_DRAW_MASK_RES_TRANSP; + 9238: 2c00 cmp r4, #0 + 923a: e681 b.n 8f40 + k = xsi - abs_x; + 923c: 46d0 mov r8, sl + if(k >= 0 && k < len) { + 923e: f1b8 0f00 cmp.w r8, #0 + 9242: db0f blt.n 9264 + 9244: 4544 cmp r4, r8 + 9246: dd0d ble.n 9264 + int32_t xef = xe & 0xFF; + 9248: f3c2 2187 ubfx r1, r2, #10, #8 + m = (xsf + xef) >> 1; + 924c: 4419 add r1, r3 + 924e: f3c1 0147 ubfx r1, r1, #1, #8 + if(p->inv) m = 255 - m; + 9252: b108 cbz r0, 9258 + 9254: 43c9 mvns r1, r1 + 9256: b2c9 uxtb r1, r1 + mask_buf[k] = mask_mix(mask_buf[k], m); + 9258: f815 0008 ldrb.w r0, [r5, r8] + 925c: 4b09 ldr r3, [pc, #36] ; (9284 ) + 925e: 4798 blx r3 + 9260: f805 0008 strb.w r0, [r5, r8] + if(p->inv) { + 9264: f896 3028 ldrb.w r3, [r6, #40] ; 0x28 + 9268: 079b lsls r3, r3, #30 + 926a: f57f af7e bpl.w 916a + k = xsi - abs_x; + 926e: eba9 0107 sub.w r1, r9, r7 + if(k >= len) { + 9272: 428c cmp r4, r1 + 9274: f77f ae52 ble.w 8f1c + if(k >= 0) _lv_memset_00(&mask_buf[0], k); + 9278: 2900 cmp r1, #0 + 927a: f6ff ae6e blt.w 8f5a + 927e: e6fd b.n 907c + xsf = 0xFF; + 9280: 23ff movs r3, #255 ; 0xff + 9282: e7dc b.n 923e + 9284: 00008eb9 .word 0x00008eb9 + 9288: 0000f019 .word 0x0000f019 + +0000928c : + while(len) { + 928c: 3901 subs r1, #1 + 928e: f100 0308 add.w r3, r0, #8 + *d8 = *s8; + 9292: f811 2f01 ldrb.w r2, [r1, #1]! + 9296: f800 2b01 strb.w r2, [r0], #1 + while(len) { + 929a: 4298 cmp r0, r3 + 929c: d1f9 bne.n 9292 +} + 929e: 4770 bx lr + +000092a0 : +{ + 92a0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 92a4: b08d sub sp, #52 ; 0x34 + 92a6: 461d mov r5, r3 + 92a8: f8dd 8058 ldr.w r8, [sp, #88] ; 0x58 + bool outer = p->cfg.outer; + 92ac: f898 9012 ldrb.w r9, [r8, #18] + int32_t radius = p->cfg.radius; + 92b0: f9b8 a010 ldrsh.w sl, [r8, #16] +{ + 92b4: 2300 movs r3, #0 + 92b6: e9cd 3302 strd r3, r3, [sp, #8] + 92ba: 4606 mov r6, r0 + lv_area_copy(&rect, &p->cfg.rect); + 92bc: 4b8b ldr r3, [pc, #556] ; (94ec ) +{ + 92be: 468b mov fp, r1 + lv_area_copy(&rect, &p->cfg.rect); + 92c0: a80a add r0, sp, #40 ; 0x28 + 92c2: f108 0108 add.w r1, r8, #8 + bool outer = p->cfg.outer; + 92c6: f009 0901 and.w r9, r9, #1 +{ + 92ca: 4617 mov r7, r2 + lv_area_copy(&rect, &p->cfg.rect); + 92cc: 4798 blx r3 + if(outer == false) { + 92ce: f9bd 302a ldrsh.w r3, [sp, #42] ; 0x2a + 92d2: f1b9 0f00 cmp.w r9, #0 + 92d6: d13a bne.n 934e + if(abs_y < rect.y1 || abs_y > rect.y2) { + 92d8: 42bb cmp r3, r7 + 92da: dd01 ble.n 92e0 + return LV_DRAW_MASK_RES_TRANSP; + 92dc: 2000 movs r0, #0 + 92de: e039 b.n 9354 + if(abs_y < rect.y1 || abs_y > rect.y2) { + 92e0: f9bd 202e ldrsh.w r2, [sp, #46] ; 0x2e + 92e4: 42ba cmp r2, r7 + 92e6: dbf9 blt.n 92dc + if((abs_x >= rect.x1 + radius && abs_x + len <= rect.x2 - radius) || + 92e8: f9bd 1028 ldrsh.w r1, [sp, #40] ; 0x28 + 92ec: eb01 020a add.w r2, r1, sl + 92f0: 4593 cmp fp, r2 + 92f2: eba1 040b sub.w r4, r1, fp + 92f6: db07 blt.n 9308 + 92f8: f9bd 202c ldrsh.w r2, [sp, #44] ; 0x2c + 92fc: eb05 000b add.w r0, r5, fp + 9300: eba2 020a sub.w r2, r2, sl + 9304: 4290 cmp r0, r2 + 9306: dd09 ble.n 931c + (abs_y >= rect.y1 + radius && abs_y <= rect.y2 - radius)) { + 9308: eb03 020a add.w r2, r3, sl + if((abs_x >= rect.x1 + radius && abs_x + len <= rect.x2 - radius) || + 930c: 4297 cmp r7, r2 + if(abs_y < rect.y1 || abs_y > rect.y2) { + 930e: f9bd 002e ldrsh.w r0, [sp, #46] ; 0x2e + if((abs_x >= rect.x1 + radius && abs_x + len <= rect.x2 - radius) || + 9312: db3d blt.n 9390 + (abs_y >= rect.y1 + radius && abs_y <= rect.y2 - radius)) { + 9314: eba0 020a sub.w r2, r0, sl + 9318: 4297 cmp r7, r2 + 931a: dc39 bgt.n 9390 + if(outer == false) { + 931c: f1b9 0f00 cmp.w r9, #0 + 9320: d125 bne.n 936e + if(last > len) return LV_DRAW_MASK_RES_TRANSP; + 9322: 42a5 cmp r5, r4 + 9324: dbda blt.n 92dc + if(last >= 0) { + 9326: 2c00 cmp r4, #0 + 9328: db03 blt.n 9332 + _lv_memset_00(&mask_buf[0], last); + 932a: 4b71 ldr r3, [pc, #452] ; (94f0 ) + 932c: 4621 mov r1, r4 + 932e: 4630 mov r0, r6 + 9330: 4798 blx r3 + int32_t first = rect.x2 - abs_x + 1; + 9332: f9bd 002c ldrsh.w r0, [sp, #44] ; 0x2c + 9336: eba0 000b sub.w r0, r0, fp + 933a: 3001 adds r0, #1 + if(first <= 0) return LV_DRAW_MASK_RES_TRANSP; + 933c: 2800 cmp r0, #0 + 933e: ddcd ble.n 92dc + else if(first < len) { + 9340: 42a8 cmp r0, r5 + 9342: da0f bge.n 9364 + _lv_memset_00(&mask_buf[kr], len - kr); + 9344: 1a29 subs r1, r5, r0 + _lv_memset_00(&mask_buf[first], len_tmp); + 9346: 4430 add r0, r6 + if(kr < len) _lv_memset_00(&mask_buf[kr], len - kr); + 9348: 4b69 ldr r3, [pc, #420] ; (94f0 ) + 934a: 4798 blx r3 + 934c: e00d b.n 936a + if(abs_y < rect.y1 || abs_y > rect.y2) { + 934e: 42bb cmp r3, r7 + 9350: dd03 ble.n 935a + return LV_DRAW_MASK_RES_FULL_COVER; + 9352: 2001 movs r0, #1 +} + 9354: b00d add sp, #52 ; 0x34 + 9356: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + if(abs_y < rect.y1 || abs_y > rect.y2) { + 935a: f9bd 202e ldrsh.w r2, [sp, #46] ; 0x2e + 935e: 42ba cmp r2, r7 + 9360: dac2 bge.n 92e8 + 9362: e7f6 b.n 9352 + if(last == 0 && first == len) return LV_DRAW_MASK_RES_FULL_COVER; + 9364: b90c cbnz r4, 936a + 9366: 42a8 cmp r0, r5 + 9368: d0f3 beq.n 9352 + return LV_DRAW_MASK_RES_CHANGED; + 936a: 2002 movs r0, #2 + 936c: e7f2 b.n 9354 + if(first < 0) first = 0; + 936e: ea24 70e4 bic.w r0, r4, r4, asr #31 + if(first <= len) { + 9372: 42a8 cmp r0, r5 + 9374: dcf9 bgt.n 936a + int32_t last = rect.x2 - abs_x - first + 1; + 9376: f9bd 102c ldrsh.w r1, [sp, #44] ; 0x2c + 937a: eba1 010b sub.w r1, r1, fp + 937e: 1a09 subs r1, r1, r0 + 9380: 3101 adds r1, #1 + if(first + last > len) last = len - first; + 9382: 1843 adds r3, r0, r1 + 9384: 42ab cmp r3, r5 + 9386: dd00 ble.n 938a + 9388: 1a29 subs r1, r5, r0 + if(first < len && len_tmp >= 0) { + 938a: 2900 cmp r1, #0 + 938c: dbed blt.n 936a + 938e: e7da b.n 9346 + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + 9390: f8bd 202c ldrh.w r2, [sp, #44] ; 0x2c + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + 9394: b29b uxth r3, r3 + 9396: 3001 adds r0, #1 + 9398: 1ac0 subs r0, r0, r3 + abs_y -= rect.y1; + 939a: 1aff subs r7, r7, r3 + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + 939c: 3201 adds r2, #1 + uint32_t r2 = p->cfg.radius * p->cfg.radius; + 939e: f9b8 3010 ldrsh.w r3, [r8, #16] + 93a2: 1a52 subs r2, r2, r1 + abs_y -= rect.y1; + 93a4: b23f sxth r7, r7 + int32_t w = lv_area_get_width(&rect); + 93a6: b212 sxth r2, r2 + uint32_t r2 = p->cfg.radius * p->cfg.radius; + 93a8: 435b muls r3, r3 + if(abs_y < radius || abs_y > h - radius - 1) { + 93aa: 45ba cmp sl, r7 + int32_t w = lv_area_get_width(&rect); + 93ac: 9204 str r2, [sp, #16] + int32_t h = lv_area_get_height(&rect); + 93ae: b200 sxth r0, r0 + uint32_t r2 = p->cfg.radius * p->cfg.radius; + 93b0: 9301 str r3, [sp, #4] + if(abs_y < radius || abs_y > h - radius - 1) { + 93b2: f300 8190 bgt.w 96d6 + 93b6: eba0 030a sub.w r3, r0, sl + 93ba: 429f cmp r7, r3 + 93bc: dbd5 blt.n 936a + y = radius - (h - abs_y) + 1; + 93be: 1bc0 subs r0, r0, r7 + if((y - 1) == p->y_prev) { + 93c0: f8d8 3014 ldr.w r3, [r8, #20] + if(radius <= 256) sqrt_mask = 0x800; + 93c4: f5ba 7f80 cmp.w sl, #256 ; 0x100 + y = radius - (h - abs_y) + 1; + 93c8: ebaa 0000 sub.w r0, sl, r0 + if(radius <= 256) sqrt_mask = 0x800; + 93cc: bfd4 ite le + 93ce: f44f 6200 movle.w r2, #2048 ; 0x800 + 93d2: f44f 4200 movgt.w r2, #32768 ; 0x8000 + if((y - 1) == p->y_prev) { + 93d6: 4298 cmp r0, r3 + y = radius - (h - abs_y) + 1; + 93d8: f100 0701 add.w r7, r0, #1 + if((y - 1) == p->y_prev) { + 93dc: d067 beq.n 94ae + _lv_sqrt(r2 - ((y - 1) * (y - 1)), &x1, sqrt_mask); + 93de: 9b01 ldr r3, [sp, #4] + 93e0: 9205 str r2, [sp, #20] + 93e2: fb00 3010 mls r0, r0, r0, r3 + 93e6: a907 add r1, sp, #28 + 93e8: 4b42 ldr r3, [pc, #264] ; (94f4 ) + 93ea: 4798 blx r3 + 93ec: 9a05 ldr r2, [sp, #20] + 93ee: e061 b.n 94b4 + x0.i = p->y_prev_x.i; + 93f0: f8d8 3018 ldr.w r3, [r8, #24] + 93f4: 9306 str r3, [sp, #24] + _lv_sqrt(r2 - ((y - 1) * (y - 1)), &x1, sqrt_mask); + 93f6: 9b01 ldr r3, [sp, #4] + 93f8: 9205 str r2, [sp, #20] + 93fa: f107 3bff add.w fp, r7, #4294967295 ; 0xffffffff + 93fe: fb0b 301b mls r0, fp, fp, r3 + 9402: a907 add r1, sp, #28 + 9404: 4b3b ldr r3, [pc, #236] ; (94f4 ) + 9406: 4798 blx r3 + p->y_prev_x.f = x1.f; + 9408: f8bd 301e ldrh.w r3, [sp, #30] + 940c: f8a8 301a strh.w r3, [r8, #26] + p->y_prev_x.i = x1.i; + 9410: f8bd 301c ldrh.w r3, [sp, #28] + p->y_prev = y - 1; + 9414: f8c8 b014 str.w fp, [r8, #20] + if(x0.i == x1.i - 1 && x1.f == 0) { + 9418: f8bd 101c ldrh.w r1, [sp, #28] + p->y_prev_x.i = x1.i; + 941c: f8a8 3018 strh.w r3, [r8, #24] + if(x0.i == x1.i - 1 && x1.f == 0) { + 9420: f8bd 3018 ldrh.w r3, [sp, #24] + p->y_prev_x.i = x0.i; + 9424: 9a05 ldr r2, [sp, #20] + if(x0.i == x1.i - 1 && x1.f == 0) { + 9426: 3901 subs r1, #1 + 9428: 428b cmp r3, r1 + 942a: d107 bne.n 943c + 942c: f8bd 101e ldrh.w r1, [sp, #30] + 9430: b921 cbnz r1, 943c + x1.f = 0xFF; + 9432: 21ff movs r1, #255 ; 0xff + x1.i--; + 9434: f8ad 301c strh.w r3, [sp, #28] + x1.f = 0xFF; + 9438: f8ad 101e strh.w r1, [sp, #30] + if(x0.i == x1.i) { + 943c: f8bd 101c ldrh.w r1, [sp, #28] + 9440: 4299 cmp r1, r3 + 9442: d15b bne.n 94fc + lv_opa_t m = (x0.f + x1.f) >> 1; + 9444: f8bd 101a ldrh.w r1, [sp, #26] + 9448: f8bd 201e ldrh.w r2, [sp, #30] + 944c: 4411 add r1, r2 + 944e: f3c1 0147 ubfx r1, r1, #1, #8 + if(outer) m = 255 - m; + 9452: f1b9 0f00 cmp.w r9, #0 + 9456: d001 beq.n 945c + 9458: 43c9 mvns r1, r1 + 945a: b2c9 uxtb r1, r1 + int32_t ofs = radius - x0.i - 1; + 945c: ebaa 0303 sub.w r3, sl, r3 + 9460: 1e5a subs r2, r3, #1 + if(kl >= 0 && kl < len) { + 9462: 18a7 adds r7, r4, r2 + 9464: d405 bmi.n 9472 + 9466: 42af cmp r7, r5 + 9468: da03 bge.n 9472 + mask_buf[kl] = mask_mix(mask_buf[kl], m); + 946a: 5df0 ldrb r0, [r6, r7] + 946c: 4b22 ldr r3, [pc, #136] ; (94f8 ) + 946e: 4798 blx r3 + 9470: 55f0 strb r0, [r6, r7] + int32_t kr = k + (w - ofs - 1); + 9472: 9b04 ldr r3, [sp, #16] + 9474: 1a9a subs r2, r3, r2 + 9476: 1e50 subs r0, r2, #1 + if(kr >= 0 && kr < len) { + 9478: 1904 adds r4, r0, r4 + 947a: d405 bmi.n 9488 + 947c: 42ac cmp r4, r5 + 947e: da03 bge.n 9488 + mask_buf[kr] = mask_mix(mask_buf[kr], m); + 9480: 5d30 ldrb r0, [r6, r4] + 9482: 4b1d ldr r3, [pc, #116] ; (94f8 ) + 9484: 4798 blx r3 + 9486: 5530 strb r0, [r6, r4] + if(outer == false) { + 9488: f1b9 0f00 cmp.w r9, #0 + 948c: d122 bne.n 94d4 + if(kl > len) { + 948e: 42af cmp r7, r5 + 9490: f73f af24 bgt.w 92dc + if(kl >= 0) { + 9494: 2f00 cmp r7, #0 + 9496: db03 blt.n 94a0 + _lv_memset_00(&mask_buf[0], kl); + 9498: 4b15 ldr r3, [pc, #84] ; (94f0 ) + 949a: 4639 mov r1, r7 + 949c: 4630 mov r0, r6 + 949e: 4798 blx r3 + if(kr < 0) { + 94a0: 1c60 adds r0, r4, #1 + 94a2: f53f af1b bmi.w 92dc + if(kr <= len) { + 94a6: 42a8 cmp r0, r5 + 94a8: f73f af5f bgt.w 936a + 94ac: e74a b.n 9344 + x1.i = p->y_prev_x.i; + 94ae: f8d8 3018 ldr.w r3, [r8, #24] + 94b2: 9307 str r3, [sp, #28] + _lv_sqrt(r2 - (y * y), &x0, sqrt_mask); + 94b4: 9b01 ldr r3, [sp, #4] + 94b6: 9205 str r2, [sp, #20] + 94b8: fb07 3017 mls r0, r7, r7, r3 + 94bc: a906 add r1, sp, #24 + 94be: 4b0d ldr r3, [pc, #52] ; (94f4 ) + 94c0: 4798 blx r3 + p->y_prev_x.f = x0.f; + 94c2: f8bd 301a ldrh.w r3, [sp, #26] + 94c6: f8a8 301a strh.w r3, [r8, #26] + p->y_prev = y; + 94ca: f8c8 7014 str.w r7, [r8, #20] + p->y_prev_x.i = x0.i; + 94ce: f8bd 3018 ldrh.w r3, [sp, #24] + 94d2: e7a1 b.n 9418 + kl++; + 94d4: 1c78 adds r0, r7, #1 + 94d6: ea20 70e0 bic.w r0, r0, r0, asr #31 + if(len_tmp + first > len) len_tmp = len - first; + 94da: 42ac cmp r4, r5 + int32_t len_tmp = kr - first; + 94dc: bfd4 ite le + 94de: 1a21 suble r1, r4, r0 + if(len_tmp + first > len) len_tmp = len - first; + 94e0: 1a29 subgt r1, r5, r0 + if(first < len && len_tmp >= 0) { + 94e2: 42a8 cmp r0, r5 + 94e4: f6bf af41 bge.w 936a + 94e8: e74f b.n 938a + 94ea: bf00 nop + 94ec: 0000928d .word 0x0000928d + 94f0: 0000f019 .word 0x0000f019 + 94f4: 0000e995 .word 0x0000e995 + 94f8: 00008eb9 .word 0x00008eb9 + int32_t kr = k + (w - ofs - 1); + 94fc: 9904 ldr r1, [sp, #16] + int32_t ofs = radius - (x0.i + 1); + 94fe: 3301 adds r3, #1 + 9500: ebaa 0303 sub.w r3, sl, r3 + int32_t kl = k + ofs; + 9504: eb04 0803 add.w r8, r4, r3 + int32_t kr = k + (w - ofs - 1); + 9508: 1acb subs r3, r1, r3 + 950a: 3b01 subs r3, #1 + 950c: 441c add r4, r3 + if(outer) { + 950e: f1b9 0f00 cmp.w r9, #0 + 9512: d010 beq.n 9536 + int32_t first = kl + 1; + 9514: f108 0001 add.w r0, r8, #1 + 9518: ea20 70e0 bic.w r0, r0, r0, asr #31 + if(len_tmp + first > len) len_tmp = len - first; + 951c: 42a5 cmp r5, r4 + int32_t len_tmp = kr - first; + 951e: bfac ite ge + 9520: 1a21 subge r1, r4, r0 + if(len_tmp + first > len) len_tmp = len - first; + 9522: 1a29 sublt r1, r5, r0 + if(first < len && len_tmp >= 0) { + 9524: 42a8 cmp r0, r5 + 9526: da06 bge.n 9536 + 9528: 2900 cmp r1, #0 + 952a: db04 blt.n 9536 + _lv_memset_00(&mask_buf[first], len_tmp); + 952c: 4b75 ldr r3, [pc, #468] ; (9704 ) + 952e: 9204 str r2, [sp, #16] + 9530: 4430 add r0, r6 + 9532: 4798 blx r3 + 9534: 9a04 ldr r2, [sp, #16] + uint32_t i = x0.i + 1; + 9536: f8bd b018 ldrh.w fp, [sp, #24] + _lv_sqrt(r2 - (x0.i * x0.i), &y_prev, sqrt_mask); + 953a: 9b01 ldr r3, [sp, #4] + 953c: 9204 str r2, [sp, #16] + 953e: a908 add r1, sp, #32 + 9540: fb0b 301b mls r0, fp, fp, r3 + 9544: 4b70 ldr r3, [pc, #448] ; (9708 ) + 9546: 4798 blx r3 + if(y_prev.f == 0) { + 9548: f8bd 1022 ldrh.w r1, [sp, #34] ; 0x22 + 954c: 4b6e ldr r3, [pc, #440] ; (9708 ) + 954e: 9a04 ldr r2, [sp, #16] + uint32_t i = x0.i + 1; + 9550: f10b 0a01 add.w sl, fp, #1 + if(y_prev.f == 0) { + 9554: b939 cbnz r1, 9566 + y_prev.i--; + 9556: f8bd 1020 ldrh.w r1, [sp, #32] + 955a: 3901 subs r1, #1 + 955c: f8ad 1020 strh.w r1, [sp, #32] + y_prev.f = 0xFF; + 9560: 21ff movs r1, #255 ; 0xff + 9562: f8ad 1022 strh.w r1, [sp, #34] ; 0x22 + if(y_prev.i >= y) { + 9566: f8bd 1020 ldrh.w r1, [sp, #32] + 956a: 42b9 cmp r1, r7 + 956c: db2e blt.n 95cc + _lv_sqrt(r2 - (i * i), &y_next, sqrt_mask); + 956e: 9801 ldr r0, [sp, #4] + 9570: a909 add r1, sp, #36 ; 0x24 + 9572: fb0a 001a mls r0, sl, sl, r0 + 9576: 4798 blx r3 + m = 255 - (((255 - x0.f) * (255 - y_next.f)) >> 9); + 9578: f8bd 2026 ldrh.w r2, [sp, #38] ; 0x26 + 957c: f8bd 101a ldrh.w r1, [sp, #26] + 9580: f1c2 03ff rsb r3, r2, #255 ; 0xff + 9584: f1c1 01ff rsb r1, r1, #255 ; 0xff + 9588: 4359 muls r1, r3 + 958a: f3c1 2147 ubfx r1, r1, #9, #8 + if(outer) m = 255 - m; + 958e: f1b9 0f00 cmp.w r9, #0 + 9592: d101 bne.n 9598 + m = 255 - (((255 - x0.f) * (255 - y_next.f)) >> 9); + 9594: 43c9 mvns r1, r1 + 9596: b2c9 uxtb r1, r1 + if(kl >= 0 && kl < len) mask_buf[kl] = mask_mix(mask_buf[kl], m); + 9598: f1b8 0f00 cmp.w r8, #0 + 959c: db07 blt.n 95ae + 959e: 4545 cmp r5, r8 + 95a0: dd05 ble.n 95ae + 95a2: f816 0008 ldrb.w r0, [r6, r8] + 95a6: 4b59 ldr r3, [pc, #356] ; (970c ) + 95a8: 4798 blx r3 + 95aa: f806 0008 strb.w r0, [r6, r8] + if(kr >= 0 && kr < len) mask_buf[kr] = mask_mix(mask_buf[kr], m); + 95ae: 2c00 cmp r4, #0 + 95b0: db05 blt.n 95be + 95b2: 42a5 cmp r5, r4 + 95b4: dd03 ble.n 95be + 95b6: 5d30 ldrb r0, [r6, r4] + 95b8: 4b54 ldr r3, [pc, #336] ; (970c ) + 95ba: 4798 blx r3 + 95bc: 5530 strb r0, [r6, r4] + kl--; + 95be: f108 38ff add.w r8, r8, #4294967295 ; 0xffffffff + kr++; + 95c2: 3401 adds r4, #1 + y_prev.f = y_next.f; + 95c4: f8ad 2022 strh.w r2, [sp, #34] ; 0x22 + i++; + 95c8: f10b 0a02 add.w sl, fp, #2 + */ +LV_ATTRIBUTE_FAST_MEM static inline void sqrt_approx(lv_sqrt_res_t * q, lv_sqrt_res_t * ref, uint32_t x) +{ + x = x << 8; /*Upscale for extra precision*/ + + uint32_t raw = (ref->i << 4) + (ref->f >> 4); + 95cc: f8bd 2020 ldrh.w r2, [sp, #32] + for(; i <= x1.i; i++) { + 95d0: f8bd b01c ldrh.w fp, [sp, #28] + 95d4: f8bd 1022 ldrh.w r1, [sp, #34] ; 0x22 + if(kl >= 0 && kl < len) mask_buf[kl] = mask_mix(mask_buf[kl], m); + 95d8: 4f4c ldr r7, [pc, #304] ; (970c ) + uint32_t raw = (ref->i << 4) + (ref->f >> 4); + 95da: 0112 lsls r2, r2, #4 + 95dc: 2300 movs r3, #0 + for(; i <= x1.i; i++) { + 95de: 45d3 cmp fp, sl + 95e0: d242 bcs.n 9668 + 95e2: b13b cbz r3, 95f4 + 95e4: 9b02 ldr r3, [sp, #8] + 95e6: f8ad 3026 strh.w r3, [sp, #38] ; 0x26 + 95ea: 9b03 ldr r3, [sp, #12] + 95ec: f8ad 3024 strh.w r3, [sp, #36] ; 0x24 + 95f0: f8ad 1022 strh.w r1, [sp, #34] ; 0x22 + if(y_prev.f) { + 95f4: f8bd 3022 ldrh.w r3, [sp, #34] ; 0x22 + 95f8: b1fb cbz r3, 963a + m = (y_prev.f * x1.f) >> 9; + 95fa: f8bd 101e ldrh.w r1, [sp, #30] + 95fe: 4359 muls r1, r3 + 9600: f3c1 2147 ubfx r1, r1, #9, #8 + if(outer) m = 255 - m; + 9604: f1b9 0f00 cmp.w r9, #0 + 9608: d001 beq.n 960e + 960a: 43c9 mvns r1, r1 + 960c: b2c9 uxtb r1, r1 + if(kl >= 0 && kl < len) mask_buf[kl] = mask_mix(mask_buf[kl], m); + 960e: f1b8 0f00 cmp.w r8, #0 + 9612: db07 blt.n 9624 + 9614: 4545 cmp r5, r8 + 9616: dd05 ble.n 9624 + 9618: f816 0008 ldrb.w r0, [r6, r8] + 961c: 4b3b ldr r3, [pc, #236] ; (970c ) + 961e: 4798 blx r3 + 9620: f806 0008 strb.w r0, [r6, r8] + if(kr >= 0 && kr < len) mask_buf[kr] = mask_mix(mask_buf[kr], m); + 9624: 2c00 cmp r4, #0 + 9626: db05 blt.n 9634 + 9628: 42a5 cmp r5, r4 + 962a: dd03 ble.n 9634 + 962c: 5d30 ldrb r0, [r6, r4] + 962e: 4b37 ldr r3, [pc, #220] ; (970c ) + 9630: 4798 blx r3 + 9632: 5530 strb r0, [r6, r4] + kl--; + 9634: f108 38ff add.w r8, r8, #4294967295 ; 0xffffffff + kr++; + 9638: 3401 adds r4, #1 + if(outer == 0) { + 963a: f1b9 0f00 cmp.w r9, #0 + 963e: f47f ae94 bne.w 936a + kl++; + 9642: f108 0101 add.w r1, r8, #1 + if(kl > len) { + 9646: 428d cmp r5, r1 + 9648: f6ff ae48 blt.w 92dc + if(kl >= 0) _lv_memset_00(&mask_buf[0], kl); + 964c: 2900 cmp r1, #0 + 964e: db02 blt.n 9656 + 9650: 4b2c ldr r3, [pc, #176] ; (9704 ) + 9652: 4630 mov r0, r6 + 9654: 4798 blx r3 + if(kr < 0) { + 9656: 2c00 cmp r4, #0 + 9658: f6ff ae40 blt.w 92dc + if(kr < len) _lv_memset_00(&mask_buf[kr], len - kr); + 965c: 42a5 cmp r5, r4 + 965e: f77f ae84 ble.w 936a + 9662: 1b29 subs r1, r5, r4 + 9664: 1930 adds r0, r6, r4 + 9666: e66f b.n 9348 + sqrt_approx(&y_next, &y_prev, r2 - (i * i)); + 9668: 9b01 ldr r3, [sp, #4] + uint32_t raw = (ref->i << 4) + (ref->f >> 4); + 966a: f3c1 100f ubfx r0, r1, #4, #16 + 966e: 4410 add r0, r2 + sqrt_approx(&y_next, &y_prev, r2 - (i * i)); + 9670: fb0a 3c1a mls ip, sl, sl, r3 + uint32_t raw2 = raw * raw; + 9674: fb00 f300 mul.w r3, r0, r0 + + int32_t d = x - raw2; + 9678: ebc3 230c rsb r3, r3, ip, lsl #8 + d = (int32_t)d / (int32_t)(2 * raw) + raw; + 967c: ea4f 0c40 mov.w ip, r0, lsl #1 + 9680: fb93 f3fc sdiv r3, r3, ip + 9684: 4403 add r3, r0 + + q->i = d >> 4; + 9686: f3c3 100f ubfx r0, r3, #4, #16 + q->f = (d & 0xF) << 4; + 968a: 011b lsls r3, r3, #4 + 968c: f003 03f0 and.w r3, r3, #240 ; 0xf0 + m = (y_prev.f + y_next.f) >> 1; + 9690: 4419 add r1, r3 + q->i = d >> 4; + 9692: 9003 str r0, [sp, #12] + q->f = (d & 0xF) << 4; + 9694: 9302 str r3, [sp, #8] + m = (y_prev.f + y_next.f) >> 1; + 9696: f3c1 0147 ubfx r1, r1, #1, #8 + if(outer) m = 255 - m; + 969a: f1b9 0f00 cmp.w r9, #0 + 969e: d001 beq.n 96a4 + 96a0: 43c9 mvns r1, r1 + 96a2: b2c9 uxtb r1, r1 + if(kl >= 0 && kl < len) mask_buf[kl] = mask_mix(mask_buf[kl], m); + 96a4: f1b8 0f00 cmp.w r8, #0 + 96a8: db06 blt.n 96b8 + 96aa: 4545 cmp r5, r8 + 96ac: dd04 ble.n 96b8 + 96ae: f816 0008 ldrb.w r0, [r6, r8] + 96b2: 47b8 blx r7 + 96b4: f806 0008 strb.w r0, [r6, r8] + if(kr >= 0 && kr < len) mask_buf[kr] = mask_mix(mask_buf[kr], m); + 96b8: 2c00 cmp r4, #0 + 96ba: db04 blt.n 96c6 + 96bc: 42a5 cmp r5, r4 + 96be: dd02 ble.n 96c6 + 96c0: 5d30 ldrb r0, [r6, r4] + 96c2: 47b8 blx r7 + 96c4: 5530 strb r0, [r6, r4] + y_prev.f = y_next.f; + 96c6: 9902 ldr r1, [sp, #8] + kl--; + 96c8: f108 38ff add.w r8, r8, #4294967295 ; 0xffffffff + kr++; + 96cc: 3401 adds r4, #1 + for(; i <= x1.i; i++) { + 96ce: f10a 0a01 add.w sl, sl, #1 + 96d2: 2301 movs r3, #1 + 96d4: e783 b.n 95de + if(y == p->y_prev) { + 96d6: f8d8 3014 ldr.w r3, [r8, #20] + if(radius <= 256) sqrt_mask = 0x800; + 96da: f5ba 7f80 cmp.w sl, #256 ; 0x100 + y = radius - abs_y; + 96de: ebaa 0707 sub.w r7, sl, r7 + if(radius <= 256) sqrt_mask = 0x800; + 96e2: bfd4 ite le + 96e4: f44f 6200 movle.w r2, #2048 ; 0x800 + 96e8: f44f 4200 movgt.w r2, #32768 ; 0x8000 + if(y == p->y_prev) { + 96ec: 42bb cmp r3, r7 + 96ee: f43f ae7f beq.w 93f0 + _lv_sqrt(r2 - (y * y), &x0, sqrt_mask); + 96f2: 9b01 ldr r3, [sp, #4] + 96f4: 9205 str r2, [sp, #20] + 96f6: fb07 3017 mls r0, r7, r7, r3 + 96fa: a906 add r1, sp, #24 + 96fc: 4b02 ldr r3, [pc, #8] ; (9708 ) + 96fe: 4798 blx r3 + 9700: 9a05 ldr r2, [sp, #20] + 9702: e678 b.n 93f6 + 9704: 0000f019 .word 0x0000f019 + 9708: 0000e995 .word 0x0000e995 + 970c: 00008eb9 .word 0x00008eb9 + +00009710 : +{ + 9710: b573 push {r0, r1, r4, r5, r6, lr} + if(LV_GC_ROOT(_lv_draw_mask_list[i]).param == NULL) break; + 9712: 4c0e ldr r4, [pc, #56] ; (974c ) +{ + 9714: 2300 movs r3, #0 + if(LV_GC_ROOT(_lv_draw_mask_list[i]).param == NULL) break; + 9716: f854 6033 ldr.w r6, [r4, r3, lsl #3] + 971a: b2da uxtb r2, r3 + 971c: eb04 05c3 add.w r5, r4, r3, lsl #3 + 9720: b176 cbz r6, 9740 + for(i = 0; i < _LV_MASK_MAX_NUM; i++) { + 9722: 3301 adds r3, #1 + 9724: 2b10 cmp r3, #16 + 9726: d1f6 bne.n 9716 + LV_LOG_WARN("lv_mask_add: no place to add the mask"); + 9728: 4b09 ldr r3, [pc, #36] ; (9750 ) + 972a: 9300 str r3, [sp, #0] + 972c: 2002 movs r0, #2 + 972e: 4b09 ldr r3, [pc, #36] ; (9754 ) + 9730: 4909 ldr r1, [pc, #36] ; (9758 ) + 9732: 4c0a ldr r4, [pc, #40] ; (975c ) + 9734: 2257 movs r2, #87 ; 0x57 + 9736: 47a0 blx r4 + return LV_MASK_ID_INV; + 9738: f04f 30ff mov.w r0, #4294967295 ; 0xffffffff +} + 973c: b002 add sp, #8 + 973e: bd70 pop {r4, r5, r6, pc} + LV_GC_ROOT(_lv_draw_mask_list[i]).param = param; + 9740: f844 0033 str.w r0, [r4, r3, lsl #3] + LV_GC_ROOT(_lv_draw_mask_list[i]).custom_id = custom_id; + 9744: 6069 str r1, [r5, #4] + return i; + 9746: b210 sxth r0, r2 + 9748: e7f8 b.n 973c + 974a: bf00 nop + 974c: 200086f4 .word 0x200086f4 + 9750: 0001fd38 .word 0x0001fd38 + 9754: 0001fd5e .word 0x0001fd5e + 9758: 0001fd03 .word 0x0001fd03 + 975c: 0000e8e9 .word 0x0000e8e9 + +00009760 : +{ + 9760: e92d 47f3 stmdb sp!, {r0, r1, r4, r5, r6, r7, r8, r9, sl, lr} + _lv_draw_mask_saved_t * m = LV_GC_ROOT(_lv_draw_mask_list); + 9764: 4e0d ldr r6, [pc, #52] ; (979c ) +{ + 9766: 4607 mov r7, r0 + 9768: 4688 mov r8, r1 + 976a: 4691 mov r9, r2 + 976c: 469a mov sl, r3 + bool changed = false; + 976e: 2400 movs r4, #0 + while(m->param) { + 9770: 6835 ldr r5, [r6, #0] + 9772: b925 cbnz r5, 977e + return changed ? LV_DRAW_MASK_RES_CHANGED : LV_DRAW_MASK_RES_FULL_COVER; + 9774: 3401 adds r4, #1 + 9776: b2e0 uxtb r0, r4 +} + 9778: b002 add sp, #8 + 977a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + res = dsc->cb(mask_buf, abs_x, abs_y, len, (void *)m->param); + 977e: 9500 str r5, [sp, #0] + 9780: 682d ldr r5, [r5, #0] + 9782: 4653 mov r3, sl + 9784: 464a mov r2, r9 + 9786: 4641 mov r1, r8 + 9788: 4638 mov r0, r7 + 978a: 47a8 blx r5 + if(res == LV_DRAW_MASK_RES_TRANSP) return LV_DRAW_MASK_RES_TRANSP; + 978c: 2800 cmp r0, #0 + 978e: d0f3 beq.n 9778 + else if(res == LV_DRAW_MASK_RES_CHANGED) changed = true; + 9790: 2802 cmp r0, #2 + 9792: bf08 it eq + 9794: 2401 moveq r4, #1 + m++; + 9796: 3608 adds r6, #8 + 9798: e7ea b.n 9770 + 979a: bf00 nop + 979c: 200086f4 .word 0x200086f4 + +000097a0 : + if(id != LV_MASK_ID_INV) { + 97a0: 1c43 adds r3, r0, #1 + p = LV_GC_ROOT(_lv_draw_mask_list[id]).param; + 97a2: bf18 it ne + 97a4: 4b07 ldrne r3, [pc, #28] ; (97c4 ) + 97a6: f04f 0200 mov.w r2, #0 + 97aa: bf1d ittte ne + 97ac: f853 1030 ldrne.w r1, [r3, r0, lsl #3] + LV_GC_ROOT(_lv_draw_mask_list[id]).param = NULL; + 97b0: f843 2030 strne.w r2, [r3, r0, lsl #3] + LV_GC_ROOT(_lv_draw_mask_list[id]).custom_id = NULL; + 97b4: eb03 03c0 addne.w r3, r3, r0, lsl #3 + void * p = NULL; + 97b8: 4611 moveq r1, r2 + LV_GC_ROOT(_lv_draw_mask_list[id]).custom_id = NULL; + 97ba: bf18 it ne + 97bc: 605a strne r2, [r3, #4] +} + 97be: 4608 mov r0, r1 + 97c0: 4770 bx lr + 97c2: bf00 nop + 97c4: 200086f4 .word 0x200086f4 + +000097c8 : +{ + 97c8: 2200 movs r2, #0 + 97ca: 4b08 ldr r3, [pc, #32] ; (97ec ) + 97cc: b530 push {r4, r5, lr} + void * p = NULL; + 97ce: 4611 mov r1, r2 + LV_GC_ROOT(_lv_draw_mask_list[i]).param = NULL; + 97d0: 4614 mov r4, r2 + if(LV_GC_ROOT(_lv_draw_mask_list[i]).custom_id == custom_id) { + 97d2: 685d ldr r5, [r3, #4] + for(i = 0; i < _LV_MASK_MAX_NUM; i++) { + 97d4: 3201 adds r2, #1 + if(LV_GC_ROOT(_lv_draw_mask_list[i]).custom_id == custom_id) { + 97d6: 4285 cmp r5, r0 + p = LV_GC_ROOT(_lv_draw_mask_list[i]).param; + 97d8: bf04 itt eq + 97da: 6819 ldreq r1, [r3, #0] + LV_GC_ROOT(_lv_draw_mask_list[i]).custom_id = NULL; + 97dc: e9c3 4400 strdeq r4, r4, [r3] + for(i = 0; i < _LV_MASK_MAX_NUM; i++) { + 97e0: 2a10 cmp r2, #16 + 97e2: f103 0308 add.w r3, r3, #8 + 97e6: d1f4 bne.n 97d2 +} + 97e8: 4608 mov r0, r1 + 97ea: bd30 pop {r4, r5, pc} + 97ec: 200086f4 .word 0x200086f4 + +000097f0 : +{ + 97f0: 2300 movs r3, #0 + if(LV_GC_ROOT(_lv_draw_mask_list[i]).param) cnt++; + 97f2: 4a05 ldr r2, [pc, #20] ; (9808 ) + uint8_t cnt = 0; + 97f4: 4618 mov r0, r3 + if(LV_GC_ROOT(_lv_draw_mask_list[i]).param) cnt++; + 97f6: f852 1033 ldr.w r1, [r2, r3, lsl #3] + 97fa: b109 cbz r1, 9800 + 97fc: 3001 adds r0, #1 + 97fe: b2c0 uxtb r0, r0 + for(i = 0; i < _LV_MASK_MAX_NUM; i++) { + 9800: 3301 adds r3, #1 + 9802: 2b10 cmp r3, #16 + 9804: d1f7 bne.n 97f6 +} + 9806: 4770 bx lr + 9808: 200086f4 .word 0x200086f4 + +0000980c : +{ + 980c: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 9810: f9bd 8018 ldrsh.w r8, [sp, #24] + 9814: 4615 mov r5, r2 + 9816: 460e mov r6, r1 + 9818: 461f mov r7, r3 + _lv_memset_00(param, sizeof(lv_draw_mask_line_param_t)); + 981a: 212c movs r1, #44 ; 0x2c + 981c: 4b3b ldr r3, [pc, #236] ; (990c ) +{ + 981e: 4604 mov r4, r0 + _lv_memset_00(param, sizeof(lv_draw_mask_line_param_t)); + 9820: 4798 blx r3 + if(p1y > p2y) { + 9822: 4545 cmp r5, r8 + 9824: dd05 ble.n 9832 + 9826: 462b mov r3, r5 + 9828: 4645 mov r5, r8 + 982a: 4698 mov r8, r3 + 982c: 4633 mov r3, r6 + p1x = t; + 982e: 463e mov r6, r7 + p2x = p1x; + 9830: 461f mov r7, r3 + param->cfg.side = side; + 9832: 7c23 ldrb r3, [r4, #16] + 9834: f89d 201c ldrb.w r2, [sp, #28] + param->cfg.p1.y = p1y; + 9838: 8165 strh r5, [r4, #10] + param->cfg.side = side; + 983a: f362 0301 bfi r3, r2, #0, #2 + 983e: 7423 strb r3, [r4, #16] + param->flat = (LV_MATH_ABS(p2x - p1x) > LV_MATH_ABS(p2y - p1y)) ? 1 : 0; + 9840: eba8 0205 sub.w r2, r8, r5 + 9844: 1bbb subs r3, r7, r6 + 9846: ea83 70e3 eor.w r0, r3, r3, asr #31 + 984a: ea82 71e2 eor.w r1, r2, r2, asr #31 + 984e: eba0 70e3 sub.w r0, r0, r3, asr #31 + 9852: eba1 71e2 sub.w r1, r1, r2, asr #31 + 9856: 4288 cmp r0, r1 + 9858: f894 1028 ldrb.w r1, [r4, #40] ; 0x28 + param->origo.y = p1y; + 985c: 82a5 strh r5, [r4, #20] + param->flat = (LV_MATH_ABS(p2x - p1x) > LV_MATH_ABS(p2y - p1y)) ? 1 : 0; + 985e: bfd4 ite le + 9860: 2000 movle r0, #0 + 9862: 2001 movgt r0, #1 + 9864: f360 0100 bfi r1, r0, #0, #1 + param->dsc.cb = (lv_draw_mask_xcb_t)lv_draw_mask_line; + 9868: 4d29 ldr r5, [pc, #164] ; (9910 ) + param->flat = (LV_MATH_ABS(p2x - p1x) > LV_MATH_ABS(p2y - p1y)) ? 1 : 0; + 986a: f884 1028 strb.w r1, [r4, #40] ; 0x28 + param->yx_steep = 0; + 986e: 2000 movs r0, #0 + if(param->flat) { + 9870: 07c9 lsls r1, r1, #31 + param->xy_steep = 0; + 9872: e9c4 0006 strd r0, r0, [r4, #24] + param->cfg.p1.x = p1x; + 9876: 8126 strh r6, [r4, #8] + param->cfg.p2.x = p2x; + 9878: 81a7 strh r7, [r4, #12] + param->cfg.p2.y = p2y; + 987a: f8a4 800e strh.w r8, [r4, #14] + param->origo.x = p1x; + 987e: 8266 strh r6, [r4, #18] + param->dsc.cb = (lv_draw_mask_xcb_t)lv_draw_mask_line; + 9880: 6025 str r5, [r4, #0] + param->dsc.type = LV_DRAW_MASK_TYPE_LINE; + 9882: 7120 strb r0, [r4, #4] + if(param->flat) { + 9884: d52b bpl.n 98de + if(dx) { + 9886: b133 cbz r3, 9896 + m = (1 << 20) / dx; /*m is multiplier to normalize y (upscaled by 1024)*/ + 9888: f44f 1180 mov.w r1, #1048576 ; 0x100000 + 988c: fb91 f1f3 sdiv r1, r1, r3 + param->yx_steep = (m * dy) >> 10; + 9890: 4351 muls r1, r2 + 9892: 1289 asrs r1, r1, #10 + 9894: 61e1 str r1, [r4, #28] + if(dy) { + 9896: b132 cbz r2, 98a6 + m = (1 << 20) / dy; /*m is multiplier to normalize x (upscaled by 1024)*/ + 9898: f44f 1180 mov.w r1, #1048576 ; 0x100000 + 989c: fb91 f2f2 sdiv r2, r1, r2 + param->xy_steep = (m * dx) >> 10; + 98a0: 4353 muls r3, r2 + 98a2: 129b asrs r3, r3, #10 + 98a4: 61a3 str r3, [r4, #24] + param->steep = param->yx_steep; + 98a6: 69e2 ldr r2, [r4, #28] + if(param->cfg.side == LV_DRAW_MASK_LINE_SIDE_LEFT) param->inv = 0; + 98a8: 7c23 ldrb r3, [r4, #16] + param->steep = param->yx_steep; + 98aa: 6222 str r2, [r4, #32] + if(param->cfg.side == LV_DRAW_MASK_LINE_SIDE_LEFT) param->inv = 0; + 98ac: f013 0303 ands.w r3, r3, #3 + 98b0: d007 beq.n 98c2 + else if(param->cfg.side == LV_DRAW_MASK_LINE_SIDE_RIGHT) param->inv = 1; + 98b2: 2b01 cmp r3, #1 + 98b4: d005 beq.n 98c2 + else if(param->cfg.side == LV_DRAW_MASK_LINE_SIDE_TOP) { + 98b6: 2b02 cmp r3, #2 + 98b8: d123 bne.n 9902 + if(param->steep > 0) param->inv = 1; + 98ba: 2a00 cmp r2, #0 + 98bc: bfd4 ite le + 98be: 2300 movle r3, #0 + 98c0: 2301 movgt r3, #1 + if(param->cfg.side == LV_DRAW_MASK_LINE_SIDE_LEFT) param->inv = 0; + 98c2: f894 1028 ldrb.w r1, [r4, #40] ; 0x28 + if(param->steep < 0) param->spx = -param->spx; + 98c6: 2a00 cmp r2, #0 + if(param->cfg.side == LV_DRAW_MASK_LINE_SIDE_LEFT) param->inv = 0; + 98c8: f363 0141 bfi r1, r3, #1, #1 + param->spx = param->steep >> 2; + 98cc: ea4f 03a2 mov.w r3, r2, asr #2 + if(param->steep < 0) param->spx = -param->spx; + 98d0: bfb8 it lt + 98d2: 425b neglt r3, r3 + if(param->cfg.side == LV_DRAW_MASK_LINE_SIDE_LEFT) param->inv = 0; + 98d4: f884 1028 strb.w r1, [r4, #40] ; 0x28 + if(param->steep < 0) param->spx = -param->spx; + 98d8: 6263 str r3, [r4, #36] ; 0x24 +} + 98da: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + if(dy) { + 98de: b132 cbz r2, 98ee + m = (1 << 20) / dy; /*m is multiplier to normalize x (upscaled by 1024)*/ + 98e0: f44f 1180 mov.w r1, #1048576 ; 0x100000 + 98e4: fb91 f1f2 sdiv r1, r1, r2 + param->xy_steep = (m * dx) >> 10; + 98e8: 4359 muls r1, r3 + 98ea: 1289 asrs r1, r1, #10 + 98ec: 61a1 str r1, [r4, #24] + if(dx) { + 98ee: b133 cbz r3, 98fe + m = (1 << 20) / dx; /*m is multiplier to normalize x (upscaled by 1024)*/ + 98f0: f44f 1180 mov.w r1, #1048576 ; 0x100000 + 98f4: fb91 f3f3 sdiv r3, r1, r3 + param->yx_steep = (m * dy) >> 10; + 98f8: 4353 muls r3, r2 + 98fa: 129b asrs r3, r3, #10 + 98fc: 61e3 str r3, [r4, #28] + param->steep = param->xy_steep; + 98fe: 69a2 ldr r2, [r4, #24] + 9900: e7d2 b.n 98a8 + if(param->steep > 0) param->inv = 0; + 9902: 2a00 cmp r2, #0 + 9904: bfcc ite gt + 9906: 2300 movgt r3, #0 + 9908: 2301 movle r3, #1 + 990a: e7da b.n 98c2 + 990c: 0000f019 .word 0x0000f019 + 9910: 00008ed5 .word 0x00008ed5 + +00009914 : +{ + 9914: b5f8 push {r3, r4, r5, r6, r7, lr} + 9916: 4604 mov r4, r0 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + 9918: 88c8 ldrh r0, [r1, #6] + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + 991a: 888d ldrh r5, [r1, #4] + 991c: 461f mov r7, r3 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + 991e: 884b ldrh r3, [r1, #2] + 9920: 3001 adds r0, #1 + 9922: 1ac0 subs r0, r0, r3 + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + 9924: 880b ldrh r3, [r1, #0] + 9926: 3501 adds r5, #1 + 9928: 1aed subs r5, r5, r3 + int32_t short_side = LV_MATH_MIN(w, h); + 992a: b200 sxth r0, r0 + 992c: b22d sxth r5, r5 + 992e: 42a8 cmp r0, r5 + 9930: bfa8 it ge + 9932: 4628 movge r0, r5 + if(radius > short_side >> 1) radius = short_side >> 1; + 9934: ebb2 0f60 cmp.w r2, r0, asr #1 + 9938: ea4f 0360 mov.w r3, r0, asr #1 +{ + 993c: 4616 mov r6, r2 + lv_area_copy(¶m->cfg.rect, rect); + 993e: f104 0008 add.w r0, r4, #8 + if(radius > short_side >> 1) radius = short_side >> 1; + 9942: bfc8 it gt + 9944: b21e sxthgt r6, r3 + lv_area_copy(¶m->cfg.rect, rect); + 9946: 4b08 ldr r3, [pc, #32] ; (9968 ) + 9948: 4798 blx r3 + param->cfg.outer = inv ? 1 : 0; + 994a: 7ca3 ldrb r3, [r4, #18] + param->cfg.radius = radius; + 994c: 8226 strh r6, [r4, #16] + param->cfg.outer = inv ? 1 : 0; + 994e: f367 0300 bfi r3, r7, #0, #1 + 9952: 74a3 strb r3, [r4, #18] + param->dsc.cb = (lv_draw_mask_xcb_t)lv_draw_mask_radius; + 9954: 4b05 ldr r3, [pc, #20] ; (996c ) + 9956: 6023 str r3, [r4, #0] + param->dsc.type = LV_DRAW_MASK_TYPE_RADIUS; + 9958: 2302 movs r3, #2 + 995a: 7123 strb r3, [r4, #4] + param->y_prev_x.i = 0; + 995c: f04f 4200 mov.w r2, #2147483648 ; 0x80000000 + 9960: 2300 movs r3, #0 + 9962: e9c4 2305 strd r2, r3, [r4, #20] +} + 9966: bdf8 pop {r3, r4, r5, r6, r7, pc} + 9968: 0000928d .word 0x0000928d + 996c: 000092a1 .word 0x000092a1 + +00009970 : + lv_draw_mask_remove_id(mask_rout_id); + _lv_mem_buf_release(mask_buf); +} + +LV_ATTRIBUTE_FAST_MEM static inline lv_color_t grad_get(lv_draw_rect_dsc_t * dsc, lv_coord_t s, lv_coord_t i) +{ + 9970: b570 push {r4, r5, r6, lr} + int32_t min = (dsc->bg_main_color_stop * s) >> 8; + 9972: f9b0 4008 ldrsh.w r4, [r0, #8] + 9976: fb04 f301 mul.w r3, r4, r1 + if(i <= min) return dsc->bg_color; + 997a: ebb2 2f23 cmp.w r2, r3, asr #8 + int32_t min = (dsc->bg_main_color_stop * s) >> 8; + 997e: ea4f 2523 mov.w r5, r3, asr #8 + if(i <= min) return dsc->bg_color; + 9982: dc01 bgt.n 9988 + 9984: 8840 ldrh r0, [r0, #2] + int32_t d = dsc->bg_grad_color_stop - dsc->bg_main_color_stop; + d = (s * d) >> 8; + i -= min; + lv_opa_t mix = (i * 255) / d; + return lv_color_mix(dsc->bg_grad_color, dsc->bg_color, mix); +} + 9986: bd70 pop {r4, r5, r6, pc} + int32_t max = (dsc->bg_grad_color_stop * s) >> 8; + 9988: f9b0 300a ldrsh.w r3, [r0, #10] + 998c: fb01 f603 mul.w r6, r1, r3 + if(i >= max) return dsc->bg_grad_color; + 9990: ebb2 2f26 cmp.w r2, r6, asr #8 + 9994: db01 blt.n 999a + 9996: 8880 ldrh r0, [r0, #4] + 9998: e7f5 b.n 9986 + int32_t d = dsc->bg_grad_color_stop - dsc->bg_main_color_stop; + 999a: 1b1b subs r3, r3, r4 + d = (s * d) >> 8; + 999c: 4359 muls r1, r3 + i -= min; + 999e: 1b52 subs r2, r2, r5 + d = (s * d) >> 8; + 99a0: 120b asrs r3, r1, #8 + lv_opa_t mix = (i * 255) / d; + 99a2: b212 sxth r2, r2 +{ + lv_color_t ret; +#if LV_COLOR_DEPTH != 1 + /*LV_COLOR_DEPTH == 8, 16 or 32*/ + LV_COLOR_SET_R(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_R(c1) * mix + LV_COLOR_GET_R(c2) * (255 - mix))); + LV_COLOR_SET_G(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_G(c1) * mix + LV_COLOR_GET_G(c2) * (255 - mix))); + 99a4: 8841 ldrh r1, [r0, #2] + LV_COLOR_SET_B(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_B(c1) * mix + LV_COLOR_GET_B(c2) * (255 - mix))); + 99a6: 7906 ldrb r6, [r0, #4] + 99a8: ebc2 2202 rsb r2, r2, r2, lsl #8 + 99ac: fb92 f3f3 sdiv r3, r2, r3 + LV_COLOR_SET_G(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_G(c1) * mix + LV_COLOR_GET_G(c2) * (255 - mix))); + 99b0: 8882 ldrh r2, [r0, #4] + 99b2: b2db uxtb r3, r3 + LV_COLOR_SET_R(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_R(c1) * mix + LV_COLOR_GET_R(c2) * (255 - mix))); + 99b4: f1c3 05ff rsb r5, r3, #255 ; 0xff + LV_COLOR_SET_G(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_G(c1) * mix + LV_COLOR_GET_G(c2) * (255 - mix))); + 99b8: f3c1 1145 ubfx r1, r1, #5, #6 + 99bc: f3c2 1245 ubfx r2, r2, #5, #6 + 99c0: 4369 muls r1, r5 + 99c2: fb03 1102 mla r1, r3, r2, r1 + LV_COLOR_SET_B(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_B(c1) * mix + LV_COLOR_GET_B(c2) * (255 - mix))); + 99c6: 7882 ldrb r2, [r0, #2] + 99c8: f002 021f and.w r2, r2, #31 + 99cc: f006 061f and.w r6, r6, #31 + 99d0: 436a muls r2, r5 + LV_COLOR_SET_G(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_G(c1) * mix + LV_COLOR_GET_G(c2) * (255 - mix))); + 99d2: f248 0481 movw r4, #32897 ; 0x8081 + LV_COLOR_SET_B(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_B(c1) * mix + LV_COLOR_GET_B(c2) * (255 - mix))); + 99d6: fb03 2206 mla r2, r3, r6, r2 + LV_COLOR_SET_G(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_G(c1) * mix + LV_COLOR_GET_G(c2) * (255 - mix))); + 99da: 4361 muls r1, r4 + LV_COLOR_SET_B(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_B(c1) * mix + LV_COLOR_GET_B(c2) * (255 - mix))); + 99dc: 4362 muls r2, r4 + 99de: f3c1 51c5 ubfx r1, r1, #23, #6 + 99e2: f3c2 52c4 ubfx r2, r2, #23, #5 + 99e6: ea42 1241 orr.w r2, r2, r1, lsl #5 + LV_COLOR_SET_R(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_R(c1) * mix + LV_COLOR_GET_R(c2) * (255 - mix))); + 99ea: 78c1 ldrb r1, [r0, #3] + 99ec: 7946 ldrb r6, [r0, #5] + 99ee: 08c9 lsrs r1, r1, #3 + 99f0: 08f6 lsrs r6, r6, #3 + 99f2: 4369 muls r1, r5 + 99f4: fb03 1306 mla r3, r3, r6, r1 + 99f8: 4363 muls r3, r4 + 99fa: 0ddb lsrs r3, r3, #23 + 99fc: ea42 20c3 orr.w r0, r2, r3, lsl #11 + return lv_color_mix(dsc->bg_grad_color, dsc->bg_color, mix); + 9a00: e7c1 b.n 9986 + ... + +00009a04 : +#endif + +} + +LV_ATTRIBUTE_FAST_MEM static void shadow_blur_corner(lv_coord_t size, lv_coord_t sw, uint16_t * sh_ups_buf) +{ + 9a04: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + int32_t s_left = sw >> 1; + int32_t s_right = (sw >> 1); + if((sw & 1) == 0) s_left--; + + /*Horizontal blur*/ + uint16_t * sh_ups_blur_buf = _lv_mem_buf_get(size * sizeof(uint16_t)); + 9a08: 0045 lsls r5, r0, #1 + int32_t s_left = sw >> 1; + 9a0a: ea4f 0961 mov.w r9, r1, asr #1 +{ + 9a0e: b087 sub sp, #28 + if((sw & 1) == 0) s_left--; + 9a10: 07cb lsls r3, r1, #31 +{ + 9a12: 4604 mov r4, r0 + uint16_t * sh_ups_blur_buf = _lv_mem_buf_get(size * sizeof(uint16_t)); + 9a14: 4b5a ldr r3, [pc, #360] ; (9b80 ) + 9a16: 4628 mov r0, r5 +{ + 9a18: 460e mov r6, r1 + 9a1a: 4617 mov r7, r2 + int32_t s_left = sw >> 1; + 9a1c: 46ca mov sl, r9 + if((sw & 1) == 0) s_left--; + 9a1e: bf58 it pl + 9a20: f109 3aff addpl.w sl, r9, #4294967295 ; 0xffffffff + uint16_t * sh_ups_blur_buf = _lv_mem_buf_get(size * sizeof(uint16_t)); + 9a24: 4798 blx r3 + int32_t y; + + uint16_t * sh_ups_tmp_buf = sh_ups_buf; + + for(y = 0; y < size; y++) { + int32_t v = sh_ups_tmp_buf[size - 1] * sw; + 9a26: 1eab subs r3, r5, #2 + 9a28: 9300 str r3, [sp, #0] + 9a2a: ea4f 0349 mov.w r3, r9, lsl #1 + 9a2e: 9301 str r3, [sp, #4] + 9a30: f06f 0301 mvn.w r3, #1 + 9a34: fb0a 3303 mla r3, sl, r3, r3 + uint16_t * sh_ups_blur_buf = _lv_mem_buf_get(size * sizeof(uint16_t)); + 9a38: 4601 mov r1, r0 + for(y = 0; y < size; y++) { + 9a3a: 46b8 mov r8, r7 + 9a3c: f04f 0b00 mov.w fp, #0 + 9a40: 9302 str r3, [sp, #8] + 9a42: 455c cmp r4, fp + 9a44: dc22 bgt.n 9a8c + sh_ups_tmp_buf += size; + } + + /*Vertical blur*/ + uint32_t i; + sh_ups_buf[0] = sh_ups_buf[0] / sw; + 9a46: 883b ldrh r3, [r7, #0] + 9a48: fb93 f3f6 sdiv r3, r3, r6 + for(i = 1; i < (uint32_t)size * size; i++) { + 9a4c: fb04 f804 mul.w r8, r4, r4 + sh_ups_buf[0] = sh_ups_buf[0] / sw; + 9a50: 803b strh r3, [r7, #0] + for(i = 1; i < (uint32_t)size * size; i++) { + 9a52: 463a mov r2, r7 + 9a54: 463b mov r3, r7 + 9a56: f04f 0c01 mov.w ip, #1 + 9a5a: 45c4 cmp ip, r8 + 9a5c: d341 bcc.n 9ae2 + 9a5e: 426b negs r3, r5 + 9a60: fb09 f303 mul.w r3, r9, r3 + 9a64: 9303 str r3, [sp, #12] + v -= top_val; + + /*Add the bottom pixel*/ + uint32_t bottom_val; + if(y + s_left + 1 < size) bottom_val = sh_ups_buf[(y + s_left + 1) * size + x]; + else bottom_val = sh_ups_buf[(size - 1) * size + x]; + 9a66: 1e63 subs r3, r4, #1 + 9a68: fb05 7303 mla r3, r5, r3, r7 + 9a6c: 9302 str r3, [sp, #8] + 9a6e: f10a 0301 add.w r3, sl, #1 + 9a72: 9301 str r3, [sp, #4] + 9a74: fb0a 5a05 mla sl, sl, r5, r5 + for(x = 0; x < size; x++) { + 9a78: f04f 0c00 mov.w ip, #0 + 9a7c: 4564 cmp r4, ip + 9a7e: dc3e bgt.n 9afe + for(y = 0; y < size; y++, sh_ups_tmp_buf += size) { + (*sh_ups_tmp_buf) = sh_ups_blur_buf[y]; + } + } + + _lv_mem_buf_release(sh_ups_blur_buf); + 9a80: 4b40 ldr r3, [pc, #256] ; (9b84 ) + 9a82: 4608 mov r0, r1 +} + 9a84: b007 add sp, #28 + 9a86: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + _lv_mem_buf_release(sh_ups_blur_buf); + 9a8a: 4718 bx r3 + int32_t v = sh_ups_tmp_buf[size - 1] * sw; + 9a8c: 9b00 ldr r3, [sp, #0] + 9a8e: 9801 ldr r0, [sp, #4] + 9a90: f838 2003 ldrh.w r2, [r8, r3] + 9a94: eb00 0c08 add.w ip, r0, r8 + 9a98: 9802 ldr r0, [sp, #8] + 9a9a: 4372 muls r2, r6 + for(x = size - 1; x >= 0; x--) { + 9a9c: 1e63 subs r3, r4, #1 + 9a9e: 4440 add r0, r8 + sh_ups_blur_buf[x] = v; + 9aa0: f821 2013 strh.w r2, [r1, r3, lsl #1] + if(x + s_right < size) right_val = sh_ups_tmp_buf[x + s_right]; + 9aa4: eb03 0e09 add.w lr, r3, r9 + 9aa8: 4574 cmp r4, lr + 9aaa: bfcc ite gt + 9aac: f83c e013 ldrhgt.w lr, [ip, r3, lsl #1] + uint32_t right_val = 0; + 9ab0: f04f 0e00 movle.w lr, #0 + v -= right_val; + 9ab4: eba2 0e0e sub.w lr, r2, lr + if(x - s_left - 1 < 0) left_val = sh_ups_tmp_buf[0]; + 9ab8: eba3 020a sub.w r2, r3, sl + 9abc: 2a00 cmp r2, #0 + 9abe: bfd4 ite le + 9ac0: f8b8 2000 ldrhle.w r2, [r8] + else left_val = sh_ups_tmp_buf[x - s_left - 1]; + 9ac4: f830 2013 ldrhgt.w r2, [r0, r3, lsl #1] + for(x = size - 1; x >= 0; x--) { + 9ac8: 3b01 subs r3, #1 + v += left_val; + 9aca: 4472 add r2, lr + for(x = size - 1; x >= 0; x--) { + 9acc: d2e8 bcs.n 9aa0 + _lv_memcpy(sh_ups_tmp_buf, sh_ups_blur_buf, size * sizeof(uint16_t)); + 9ace: 4640 mov r0, r8 + 9ad0: 4b2d ldr r3, [pc, #180] ; (9b88 ) + 9ad2: 9103 str r1, [sp, #12] + 9ad4: 462a mov r2, r5 + 9ad6: 4798 blx r3 + sh_ups_tmp_buf += size; + 9ad8: 44a8 add r8, r5 + for(y = 0; y < size; y++) { + 9ada: 9903 ldr r1, [sp, #12] + 9adc: f10b 0b01 add.w fp, fp, #1 + 9ae0: e7af b.n 9a42 + if(sh_ups_buf[i] == sh_ups_buf[i - 1]) sh_ups_buf[i] = sh_ups_buf[i - 1]; + 9ae2: 8858 ldrh r0, [r3, #2] + 9ae4: f833 eb02 ldrh.w lr, [r3], #2 + 9ae8: 4570 cmp r0, lr + else sh_ups_buf[i] = sh_ups_buf[i] / sw; + 9aea: bf1c itt ne + 9aec: fb90 f0f6 sdivne r0, r0, r6 + 9af0: fa1f fe80 uxthne.w lr, r0 + 9af4: f8a3 e000 strh.w lr, [r3] + for(i = 1; i < (uint32_t)size * size; i++) { + 9af8: f10c 0c01 add.w ip, ip, #1 + 9afc: e7ad b.n 9a5a + sh_ups_tmp_buf = &sh_ups_buf[x]; + 9afe: 9803 ldr r0, [sp, #12] + int32_t v = sh_ups_tmp_buf[0] * sw; + 9b00: 8813 ldrh r3, [r2, #0] + 9b02: 1810 adds r0, r2, r0 + 9b04: 4373 muls r3, r6 + 9b06: 9005 str r0, [sp, #20] + 9b08: 2700 movs r7, #0 + 9b0a: eb0a 0002 add.w r0, sl, r2 + 9b0e: 9004 str r0, [sp, #16] + sh_ups_tmp_buf = &sh_ups_buf[x]; + 9b10: 4696 mov lr, r2 + int32_t v = sh_ups_tmp_buf[0] * sw; + 9b12: 9300 str r3, [sp, #0] + 9b14: 4690 mov r8, r2 + for(y = 0; y < size ; y++, sh_ups_tmp_buf += size) { + 9b16: 4638 mov r0, r7 + sh_ups_blur_buf[y] = v < 0 ? 0 : (v >> SHADOW_UPSACALE_SHIFT); + 9b18: 9b00 ldr r3, [sp, #0] + 9b1a: 2b00 cmp r3, #0 + 9b1c: bfac ite ge + 9b1e: f3c3 1b8f ubfxge fp, r3, #6, #16 + 9b22: f04f 0b00 movlt.w fp, #0 + 9b26: f821 b010 strh.w fp, [r1, r0, lsl #1] + if(y - s_right <= 0) top_val = sh_ups_tmp_buf[0]; + 9b2a: eba0 0b09 sub.w fp, r0, r9 + 9b2e: f1bb 0f00 cmp.w fp, #0 + else top_val = sh_ups_buf[(y - s_right) * size + x]; + 9b32: bfca itet gt + 9b34: 9b05 ldrgt r3, [sp, #20] + if(y - s_right <= 0) top_val = sh_ups_tmp_buf[0]; + 9b36: f8b8 b000 ldrhle.w fp, [r8] + else top_val = sh_ups_buf[(y - s_right) * size + x]; + 9b3a: f833 b007 ldrhgt.w fp, [r3, r7] + v -= top_val; + 9b3e: 9b00 ldr r3, [sp, #0] + 9b40: eba3 0b0b sub.w fp, r3, fp + if(y + s_left + 1 < size) bottom_val = sh_ups_buf[(y + s_left + 1) * size + x]; + 9b44: 9b01 ldr r3, [sp, #4] + 9b46: 4403 add r3, r0 + 9b48: 429c cmp r4, r3 + 9b4a: bfcb itete gt + 9b4c: 9b04 ldrgt r3, [sp, #16] + else bottom_val = sh_ups_buf[(size - 1) * size + x]; + 9b4e: 9b02 ldrle r3, [sp, #8] + if(y + s_left + 1 < size) bottom_val = sh_ups_buf[(y + s_left + 1) * size + x]; + 9b50: 5bdb ldrhgt r3, [r3, r7] + else bottom_val = sh_ups_buf[(size - 1) * size + x]; + 9b52: f833 301c ldrhle.w r3, [r3, ip, lsl #1] + for(y = 0; y < size ; y++, sh_ups_tmp_buf += size) { + 9b56: 3001 adds r0, #1 + v += bottom_val; + 9b58: 445b add r3, fp + for(y = 0; y < size ; y++, sh_ups_tmp_buf += size) { + 9b5a: 4284 cmp r4, r0 + v += bottom_val; + 9b5c: 9300 str r3, [sp, #0] + for(y = 0; y < size ; y++, sh_ups_tmp_buf += size) { + 9b5e: 44a8 add r8, r5 + 9b60: 442f add r7, r5 + 9b62: dcd9 bgt.n 9b18 + for(y = 0; y < size; y++, sh_ups_tmp_buf += size) { + 9b64: 2300 movs r3, #0 + (*sh_ups_tmp_buf) = sh_ups_blur_buf[y]; + 9b66: f831 0013 ldrh.w r0, [r1, r3, lsl #1] + 9b6a: f8ae 0000 strh.w r0, [lr] + for(y = 0; y < size; y++, sh_ups_tmp_buf += size) { + 9b6e: 3301 adds r3, #1 + 9b70: 429c cmp r4, r3 + 9b72: 44ae add lr, r5 + 9b74: dcf7 bgt.n 9b66 + for(x = 0; x < size; x++) { + 9b76: f10c 0c01 add.w ip, ip, #1 + 9b7a: 3202 adds r2, #2 + 9b7c: e77e b.n 9a7c + 9b7e: bf00 nop + 9b80: 0000eeb5 .word 0x0000eeb5 + 9b84: 0000eb69 .word 0x0000eb69 + 9b88: 0000ec31 .word 0x0000ec31 + +00009b8c : +LV_ATTRIBUTE_FAST_MEM static inline void * _lv_memcpy_small(void * dst, const void * src, size_t len) +{ + uint8_t * d8 = (uint8_t *)dst; + const uint8_t * s8 = (const uint8_t *)src; + + while(len) { + 9b8c: 3901 subs r1, #1 + 9b8e: f100 0308 add.w r3, r0, #8 + *d8 = *s8; + 9b92: f811 2f01 ldrb.w r2, [r1, #1]! + 9b96: f800 2b01 strb.w r2, [r0], #1 + while(len) { + 9b9a: 4298 cmp r0, r3 + 9b9c: d1f9 bne.n 9b92 + * @param src pointer to the source area + */ +inline static void lv_area_copy(lv_area_t * dest, const lv_area_t * src) +{ + _lv_memcpy_small(dest, src, sizeof(lv_area_t)); +} + 9b9e: 4770 bx lr + +00009ba0 : +{ + 9ba0: b510 push {r4, lr} + _lv_memset_00(dsc, sizeof(lv_draw_rect_dsc_t)); + 9ba2: 4b0f ldr r3, [pc, #60] ; (9be0 ) + 9ba4: 2154 movs r1, #84 ; 0x54 +{ + 9ba6: 4604 mov r4, r0 + _lv_memset_00(dsc, sizeof(lv_draw_rect_dsc_t)); + 9ba8: 4798 blx r3 + dsc->bg_color = LV_COLOR_WHITE; + 9baa: 4b0e ldr r3, [pc, #56] ; (9be4 ) + 9bac: 881b ldrh r3, [r3, #0] + 9bae: 8063 strh r3, [r4, #2] + dsc->bg_grad_color = LV_COLOR_BLACK; + 9bb0: 2200 movs r2, #0 + dsc->bg_grad_color_stop = 0xFF; + 9bb2: 23ff movs r3, #255 ; 0xff + dsc->bg_grad_color = LV_COLOR_BLACK; + 9bb4: 80a2 strh r2, [r4, #4] + dsc->border_color = LV_COLOR_BLACK; + 9bb6: 81e2 strh r2, [r4, #14] + dsc->value_color = LV_COLOR_BLACK; + 9bb8: f8a4 2046 strh.w r2, [r4, #70] ; 0x46 + dsc->shadow_color = LV_COLOR_BLACK; + 9bbc: 83e2 strh r2, [r4, #30] + dsc->bg_grad_color_stop = 0xFF; + 9bbe: 8163 strh r3, [r4, #10] + dsc->bg_opa = LV_OPA_COVER; + 9bc0: 7323 strb r3, [r4, #12] + dsc->outline_opa = LV_OPA_COVER; + 9bc2: 7723 strb r3, [r4, #28] + dsc->border_opa = LV_OPA_COVER; + 9bc4: 7523 strb r3, [r4, #20] + dsc->pattern_recolor = LV_COLOR_BLACK; + 9bc6: 86a2 strh r2, [r4, #52] ; 0x34 + dsc->pattern_opa = LV_OPA_COVER; + 9bc8: f884 3036 strb.w r3, [r4, #54] ; 0x36 + dsc->pattern_font = LV_THEME_DEFAULT_FONT_NORMAL; + 9bcc: 4a06 ldr r2, [pc, #24] ; (9be8 ) + dsc->value_opa = LV_OPA_COVER; + 9bce: f884 3044 strb.w r3, [r4, #68] ; 0x44 + dsc->shadow_opa = LV_OPA_COVER; + 9bd2: f884 3028 strb.w r3, [r4, #40] ; 0x28 + dsc->border_side = LV_BORDER_SIDE_FULL; + 9bd6: 230f movs r3, #15 + dsc->pattern_font = LV_THEME_DEFAULT_FONT_NORMAL; + 9bd8: 6322 str r2, [r4, #48] ; 0x30 + dsc->value_font = LV_THEME_DEFAULT_FONT_NORMAL; + 9bda: 6422 str r2, [r4, #64] ; 0x40 + dsc->border_side = LV_BORDER_SIDE_FULL; + 9bdc: 8263 strh r3, [r4, #18] +} + 9bde: bd10 pop {r4, pc} + 9be0: 0000f019 .word 0x0000f019 + 9be4: 0001fdf0 .word 0x0001fdf0 + 9be8: 20000010 .word 0x20000010 + +00009bec : +{ + 9bec: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 9bf0: 4692 mov sl, r2 + * @param area_p pointer to an area + * @return the height of the area (if y1 == y2 -> height = 1) + */ +static inline lv_coord_t lv_area_get_height(const lv_area_t * area_p) +{ + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + 9bf2: 88c2 ldrh r2, [r0, #6] + 9bf4: 8845 ldrh r5, [r0, #2] + 9bf6: 1c53 adds r3, r2, #1 + 9bf8: ed2d 8b04 vpush {d8-d9} + 9bfc: 1b5b subs r3, r3, r5 + if(lv_area_get_height(coords) < 1 || lv_area_get_width(coords) < 1) return; + 9bfe: b21b sxth r3, r3 + 9c00: 2b00 cmp r3, #0 +{ + 9c02: b0ad sub sp, #180 ; 0xb4 + 9c04: 4683 mov fp, r0 + 9c06: 4688 mov r8, r1 + if(lv_area_get_height(coords) < 1 || lv_area_get_width(coords) < 1) return; + 9c08: f341 816e ble.w aee8 + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + 9c0c: 8881 ldrh r1, [r0, #4] + 9c0e: 8800 ldrh r0, [r0, #0] + 9c10: 1c4b adds r3, r1, #1 + 9c12: 1a1b subs r3, r3, r0 + 9c14: b21b sxth r3, r3 + 9c16: 2b00 cmp r3, #0 + 9c18: f341 8166 ble.w aee8 + if(dsc->shadow_width == 0) return; + 9c1c: f9ba 4020 ldrsh.w r4, [sl, #32] + 9c20: 2c00 cmp r4, #0 + 9c22: f000 8542 beq.w a6aa + if(dsc->shadow_opa <= LV_OPA_MIN) return; + 9c26: f89a 3028 ldrb.w r3, [sl, #40] ; 0x28 + 9c2a: 9308 str r3, [sp, #32] + 9c2c: 2b05 cmp r3, #5 + 9c2e: f240 853c bls.w a6aa + if(dsc->shadow_width == 1 && dsc->shadow_ofs_x == 0 && + 9c32: f8da 7020 ldr.w r7, [sl, #32] + dsc->shadow_ofs_y == 0 && dsc->shadow_spread <= 0) { + 9c36: f9ba 6024 ldrsh.w r6, [sl, #36] ; 0x24 + 9c3a: f9ba 3026 ldrsh.w r3, [sl, #38] ; 0x26 + if(dsc->shadow_width == 1 && dsc->shadow_ofs_x == 0 && + 9c3e: 2f01 cmp r7, #1 + 9c40: d103 bne.n 9c4a + 9c42: b916 cbnz r6, 9c4a + dsc->shadow_ofs_y == 0 && dsc->shadow_spread <= 0) { + 9c44: 2b00 cmp r3, #0 + 9c46: f340 8530 ble.w a6aa + sh_rect_area.x1 = coords->x1 + dsc->shadow_ofs_x - dsc->shadow_spread; + 9c4a: f8ba 7022 ldrh.w r7, [sl, #34] ; 0x22 + 9c4e: b29b uxth r3, r3 + 9c50: eba7 0c03 sub.w ip, r7, r3 + sh_rect_area.y1 = coords->y1 + dsc->shadow_ofs_y - dsc->shadow_spread; + 9c54: b2b6 uxth r6, r6 + sh_rect_area.x2 = coords->x2 + dsc->shadow_ofs_x + dsc->shadow_spread; + 9c56: 441f add r7, r3 + 9c58: 4439 add r1, r7 + sh_rect_area.y1 = coords->y1 + dsc->shadow_ofs_y - dsc->shadow_spread; + 9c5a: 1af7 subs r7, r6, r3 + sh_rect_area.y2 = coords->y2 + dsc->shadow_ofs_y + dsc->shadow_spread; + 9c5c: 4433 add r3, r6 + 9c5e: 441a add r2, r3 + sh_area.x1 = sh_rect_area.x1 - sw / 2 - 1; + 9c60: eb04 73d4 add.w r3, r4, r4, lsr #31 + 9c64: 105b asrs r3, r3, #1 + 9c66: 425b negs r3, r3 + sh_rect_area.y2 = coords->y2 + dsc->shadow_ofs_y + dsc->shadow_spread; + 9c68: b292 uxth r2, r2 + 9c6a: 1e5e subs r6, r3, #1 + sh_rect_area.x2 = coords->x2 + dsc->shadow_ofs_x + dsc->shadow_spread; + 9c6c: b289 uxth r1, r1 + 9c6e: f1c3 0301 rsb r3, r3, #1 + 9c72: f8ad 1044 strh.w r1, [sp, #68] ; 0x44 + sh_area.x2 = sh_rect_area.x2 + sw / 2 + 1; + 9c76: fa11 f183 uxtah r1, r1, r3 + sh_area.y2 = sh_rect_area.y2 + sw / 2 + 1; + 9c7a: fa12 f383 uxtah r3, r2, r3 + 9c7e: f8ad 304e strh.w r3, [sp, #78] ; 0x4e + if(opa > LV_OPA_MAX) opa = LV_OPA_COVER; + 9c82: 9b08 ldr r3, [sp, #32] + sh_rect_area.y2 = coords->y2 + dsc->shadow_ofs_y + dsc->shadow_spread; + 9c84: f8ad 2046 strh.w r2, [sp, #70] ; 0x46 + sh_rect_area.x1 = coords->x1 + dsc->shadow_ofs_x - dsc->shadow_spread; + 9c88: 4460 add r0, ip + sh_rect_area.y1 = coords->y1 + dsc->shadow_ofs_y - dsc->shadow_spread; + 9c8a: 443d add r5, r7 + if(opa > LV_OPA_MAX) opa = LV_OPA_COVER; + 9c8c: 2bfb cmp r3, #251 ; 0xfb + sh_rect_area.y1 = coords->y1 + dsc->shadow_ofs_y - dsc->shadow_spread; + 9c8e: b2ad uxth r5, r5 + sh_rect_area.x1 = coords->x1 + dsc->shadow_ofs_x - dsc->shadow_spread; + 9c90: b280 uxth r0, r0 + if(opa > LV_OPA_MAX) opa = LV_OPA_COVER; + 9c92: bf28 it cs + 9c94: 23ff movcs r3, #255 ; 0xff + sh_rect_area.x1 = coords->x1 + dsc->shadow_ofs_x - dsc->shadow_spread; + 9c96: f8ad 0040 strh.w r0, [sp, #64] ; 0x40 + sh_area.x1 = sh_rect_area.x1 - sw / 2 - 1; + 9c9a: fa10 f086 uxtah r0, r0, r6 + sh_area.y1 = sh_rect_area.y1 - sw / 2 - 1; + 9c9e: fa15 f686 uxtah r6, r5, r6 + sh_area.x2 = sh_rect_area.x2 + sw / 2 + 1; + 9ca2: f8ad 104c strh.w r1, [sp, #76] ; 0x4c + sh_rect_area.y1 = coords->y1 + dsc->shadow_ofs_y - dsc->shadow_spread; + 9ca6: f8ad 5042 strh.w r5, [sp, #66] ; 0x42 + if(opa > LV_OPA_MAX) opa = LV_OPA_COVER; + 9caa: 9308 str r3, [sp, #32] + sh_area.x1 = sh_rect_area.x1 - sw / 2 - 1; + 9cac: f8ad 0048 strh.w r0, [sp, #72] ; 0x48 + lv_disp_t * disp = _lv_refr_get_disp_refreshing(); + 9cb0: 4bac ldr r3, [pc, #688] ; (9f64 ) + sh_area.y1 = sh_rect_area.y1 - sw / 2 - 1; + 9cb2: f8ad 604a strh.w r6, [sp, #74] ; 0x4a + lv_disp_t * disp = _lv_refr_get_disp_refreshing(); + 9cb6: 4798 blx r3 + lv_disp_buf_t * vdb = lv_disp_get_buf(disp); + 9cb8: 4bab ldr r3, [pc, #684] ; (9f68 ) + 9cba: 4798 blx r3 + is_common = _lv_area_intersect(&draw_area, &sh_area, clip); + 9cbc: 4bab ldr r3, [pc, #684] ; (9f6c ) + lv_disp_buf_t * vdb = lv_disp_get_buf(disp); + 9cbe: 4605 mov r5, r0 + is_common = _lv_area_intersect(&draw_area, &sh_area, clip); + 9cc0: 4642 mov r2, r8 + 9cc2: a912 add r1, sp, #72 ; 0x48 + 9cc4: a814 add r0, sp, #80 ; 0x50 + 9cc6: 4798 blx r3 + if(is_common == false) return; + 9cc8: 2800 cmp r0, #0 + 9cca: f000 84ee beq.w a6aa + draw_area.x1 -= disp_area->x1; + 9cce: 8a29 ldrh r1, [r5, #16] + 9cd0: f8bd 3050 ldrh.w r3, [sp, #80] ; 0x50 + draw_area.y1 -= disp_area->y1; + 9cd4: 8a6a ldrh r2, [r5, #18] + draw_area.x1 -= disp_area->x1; + 9cd6: 1a5b subs r3, r3, r1 + 9cd8: f8ad 3050 strh.w r3, [sp, #80] ; 0x50 + draw_area.y1 -= disp_area->y1; + 9cdc: f8bd 3052 ldrh.w r3, [sp, #82] ; 0x52 + 9ce0: 1a9b subs r3, r3, r2 + 9ce2: f8ad 3052 strh.w r3, [sp, #82] ; 0x52 + draw_area.x2 -= disp_area->x1; + 9ce6: f8bd 3054 ldrh.w r3, [sp, #84] ; 0x54 + 9cea: 1a5b subs r3, r3, r1 + 9cec: f8ad 3054 strh.w r3, [sp, #84] ; 0x54 + draw_area.y2 -= disp_area->y1; + 9cf0: f8bd 3056 ldrh.w r3, [sp, #86] ; 0x56 + 9cf4: 1a9b subs r3, r3, r2 + 9cf6: f8ad 3056 strh.w r3, [sp, #86] ; 0x56 + lv_area_copy(&bg_coords, coords); + 9cfa: 4659 mov r1, fp + 9cfc: 4b9c ldr r3, [pc, #624] ; (9f70 ) + 9cfe: a816 add r0, sp, #88 ; 0x58 + 9d00: 4798 blx r3 + bg_coords.x1 += 1; + 9d02: f8bd 5058 ldrh.w r5, [sp, #88] ; 0x58 + bg_coords.y1 += 1; + 9d06: f8bd 005a ldrh.w r0, [sp, #90] ; 0x5a + bg_coords.x2 -= 1; + 9d0a: f8bd 205c ldrh.w r2, [sp, #92] ; 0x5c + bg_coords.y2 -= 1; + 9d0e: f8bd 105e ldrh.w r1, [sp, #94] ; 0x5e + 9d12: f8bd 7044 ldrh.w r7, [sp, #68] ; 0x44 + bg_coords.x1 += 1; + 9d16: 3501 adds r5, #1 + bg_coords.y1 += 1; + 9d18: 3001 adds r0, #1 + bg_coords.x1 += 1; + 9d1a: b2ad uxth r5, r5 + bg_coords.y1 += 1; + 9d1c: b280 uxth r0, r0 + bg_coords.x2 -= 1; + 9d1e: 1e53 subs r3, r2, #1 + 9d20: f8ad 305c strh.w r3, [sp, #92] ; 0x5c + 9d24: 1b52 subs r2, r2, r5 + bg_coords.y2 -= 1; + 9d26: 1e4b subs r3, r1, #1 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + 9d28: 1a09 subs r1, r1, r0 + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + 9d2a: b212 sxth r2, r2 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + 9d2c: b209 sxth r1, r1 + int32_t short_side = LV_MATH_MIN(lv_area_get_width(&bg_coords), lv_area_get_height(&bg_coords)); + 9d2e: 428a cmp r2, r1 + 9d30: bfa8 it ge + 9d32: 460a movge r2, r1 + bg_coords.y2 -= 1; + 9d34: f8ad 305e strh.w r3, [sp, #94] ; 0x5e + int32_t r_bg = dsc->radius; + 9d38: f9ba 3000 ldrsh.w r3, [sl] + 9d3c: f8bd 1042 ldrh.w r1, [sp, #66] ; 0x42 + bg_coords.y1 += 1; + 9d40: f8ad 005a strh.w r0, [sp, #90] ; 0x5a + if(r_bg > short_side >> 1) r_bg = short_side >> 1; + 9d44: 1052 asrs r2, r2, #1 + 9d46: 429a cmp r2, r3 + 9d48: bfa8 it ge + 9d4a: 461a movge r2, r3 + 9d4c: ee08 2a90 vmov s17, r2 + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + 9d50: f8bd 2040 ldrh.w r2, [sp, #64] ; 0x40 + bg_coords.x1 += 1; + 9d54: f8ad 5058 strh.w r5, [sp, #88] ; 0x58 + 9d58: 3701 adds r7, #1 + 9d5a: 1abf subs r7, r7, r2 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + 9d5c: f8bd 2046 ldrh.w r2, [sp, #70] ; 0x46 + sh_buf = _lv_mem_buf_get(corner_size * corner_size * sizeof(uint16_t)); + 9d60: 4d84 ldr r5, [pc, #528] ; (9f74 ) + 9d62: 3201 adds r2, #1 + 9d64: 1a52 subs r2, r2, r1 + 9d66: b212 sxth r2, r2 + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + 9d68: b23f sxth r7, r7 + short_side = LV_MATH_MIN(lv_area_get_width(&sh_rect_area), lv_area_get_height(&sh_rect_area)); + 9d6a: 4297 cmp r7, r2 + 9d6c: bfa8 it ge + 9d6e: 4617 movge r7, r2 + if(r_sh > short_side >> 1) r_sh = short_side >> 1; + 9d70: 107f asrs r7, r7, #1 + 9d72: 429f cmp r7, r3 + 9d74: bfa8 it ge + 9d76: 461f movge r7, r3 + int32_t corner_size = sw + r_sh; + 9d78: eb04 0907 add.w r9, r4, r7 + sh_buf = _lv_mem_buf_get(corner_size * corner_size * sizeof(uint16_t)); + 9d7c: fb09 f009 mul.w r0, r9, r9 + 9d80: 0040 lsls r0, r0, #1 + 9d82: 47a8 blx r5 + shadow_draw_corner_buf(&sh_rect_area, (uint16_t *)sh_buf, dsc->shadow_width, r_sh); + 9d84: f9ba 4020 ldrsh.w r4, [sl, #32] + lv_area_copy(&sh_area, coords); + 9d88: 4b79 ldr r3, [pc, #484] ; (9f70 ) + sh_buf = _lv_mem_buf_get(corner_size * corner_size * sizeof(uint16_t)); + 9d8a: 9006 str r0, [sp, #24] + lv_area_copy(&sh_area, coords); + 9d8c: a910 add r1, sp, #64 ; 0x40 + 9d8e: a81e add r0, sp, #120 ; 0x78 + 9d90: 4798 blx r3 + 9d92: f004 0201 and.w r2, r4, #1 + sh_area.x2 = sw / 2 + r - 1 - ((sw & 1) ? 0 : 1); + 9d96: eb04 73d4 add.w r3, r4, r4, lsr #31 + sh_area.x1 = sh_area.x2 - lv_area_get_width(coords); + 9d9a: f8bd 1040 ldrh.w r1, [sp, #64] ; 0x40 + 9d9e: 920a str r2, [sp, #40] ; 0x28 + sh_area.x2 = sw / 2 + r - 1 - ((sw & 1) ? 0 : 1); + 9da0: f3c3 034f ubfx r3, r3, #1, #16 + 9da4: f064 0201 orn r2, r4, #1 + sh_area.x1 = sh_area.x2 - lv_area_get_width(coords); + 9da8: f8bd 0044 ldrh.w r0, [sp, #68] ; 0x44 + sh_area.x2 = sw / 2 + r - 1 - ((sw & 1) ? 0 : 1); + 9dac: 441a add r2, r3 + 9dae: 443a add r2, r7 + sh_area.x1 = sh_area.x2 - lv_area_get_width(coords); + 9db0: 3901 subs r1, #1 + 9db2: 1a09 subs r1, r1, r0 + sh_area.x2 = sw / 2 + r - 1 - ((sw & 1) ? 0 : 1); + 9db4: b292 uxth r2, r2 + 9db6: f8ad 207c strh.w r2, [sp, #124] ; 0x7c + sh_area.x1 = sh_area.x2 - lv_area_get_width(coords); + 9dba: 440a add r2, r1 + 9dbc: f8ad 2078 strh.w r2, [sp, #120] ; 0x78 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + 9dc0: f8bd 2046 ldrh.w r2, [sp, #70] ; 0x46 + 9dc4: f8bd 1042 ldrh.w r1, [sp, #66] ; 0x42 + sh_area.y1 = sw / 2 + 1; + 9dc8: 3301 adds r3, #1 + 9dca: 3201 adds r2, #1 + 9dcc: 1a52 subs r2, r2, r1 + 9dce: b29b uxth r3, r3 + 9dd0: f8ad 307a strh.w r3, [sp, #122] ; 0x7a + sh_area.y2 = sh_area.y1 + lv_area_get_height(coords); + 9dd4: 4413 add r3, r2 + int32_t size = sw_ori + r; + 9dd6: 193e adds r6, r7, r4 + lv_draw_mask_radius_init(&mask_param, &sh_area, r, false); + 9dd8: 463a mov r2, r7 + sh_area.y2 = sh_area.y1 + lv_area_get_height(coords); + 9dda: f8ad 307e strh.w r3, [sp, #126] ; 0x7e + lv_draw_mask_radius_init(&mask_param, &sh_area, r, false); + 9dde: 4f66 ldr r7, [pc, #408] ; (9f78 ) + 9de0: 2300 movs r3, #0 + 9de2: a91e add r1, sp, #120 ; 0x78 + 9de4: a825 add r0, sp, #148 ; 0x94 + 9de6: 47b8 blx r7 + if(sw_ori == 1) sw = 1; + 9de8: 2c01 cmp r4, #1 + lv_opa_t * mask_line = _lv_mem_buf_get(size); + 9dea: 4630 mov r0, r6 + else sw = sw_ori >> 1; + 9dec: bf18 it ne + 9dee: 1064 asrne r4, r4, #1 + lv_opa_t * mask_line = _lv_mem_buf_get(size); + 9df0: 47a8 blx r5 + _lv_memset_00(sh_ups_tmp_buf, size * sizeof(sh_ups_tmp_buf[0])); + 9df2: 0073 lsls r3, r6, #1 + 9df4: 9309 str r3, [sp, #36] ; 0x24 + sh_buf = _lv_mem_buf_get(corner_size * corner_size * sizeof(uint16_t)); + 9df6: 9b06 ldr r3, [sp, #24] + 9df8: 9305 str r3, [sp, #20] + for(y = 0; y < size; y++) { + 9dfa: 2300 movs r3, #0 + 9dfc: 9307 str r3, [sp, #28] + lv_draw_mask_res_t mask_res = mask_param.dsc.cb(mask_line, 0, y, size, &mask_param); + 9dfe: b233 sxth r3, r6 + 9e00: ee08 3a10 vmov s16, r3 + lv_opa_t * mask_line = _lv_mem_buf_get(size); + 9e04: 4607 mov r7, r0 + for(y = 0; y < size; y++) { + 9e06: 9b07 ldr r3, [sp, #28] + 9e08: 429e cmp r6, r3 + 9e0a: dc08 bgt.n 9e1e + _lv_mem_buf_release(mask_line); + 9e0c: 4b5b ldr r3, [pc, #364] ; (9f7c ) + 9e0e: 4638 mov r0, r7 + 9e10: 4798 blx r3 + if(sw == 1) { + 9e12: 2c01 cmp r4, #1 + for(x = 0; x < size * size; x++) { + 9e14: fb06 f506 mul.w r5, r6, r6 + if(sw == 1) { + 9e18: d174 bne.n 9f04 + for(i = 0; i < size * size; i++) { + 9e1a: 2300 movs r3, #0 + 9e1c: e03e b.n 9e9c + _lv_memset_ff(mask_line, size); + 9e1e: 4b58 ldr r3, [pc, #352] ; (9f80 ) + 9e20: 4631 mov r1, r6 + 9e22: 4638 mov r0, r7 + 9e24: 4798 blx r3 + lv_draw_mask_res_t mask_res = mask_param.dsc.cb(mask_line, 0, y, size, &mask_param); + 9e26: ab25 add r3, sp, #148 ; 0x94 + 9e28: 9300 str r3, [sp, #0] + 9e2a: f9bd 201c ldrsh.w r2, [sp, #28] + 9e2e: 9d25 ldr r5, [sp, #148] ; 0x94 + 9e30: ee18 3a10 vmov r3, s16 + 9e34: 2100 movs r1, #0 + 9e36: 4638 mov r0, r7 + 9e38: 47a8 blx r5 + if(mask_res == LV_DRAW_MASK_RES_TRANSP) { + 9e3a: b958 cbnz r0, 9e54 + _lv_memset_00(sh_ups_tmp_buf, size * sizeof(sh_ups_tmp_buf[0])); + 9e3c: 9909 ldr r1, [sp, #36] ; 0x24 + 9e3e: 9805 ldr r0, [sp, #20] + 9e40: 4b50 ldr r3, [pc, #320] ; (9f84 ) + 9e42: 4798 blx r3 + sh_ups_tmp_buf += size; + 9e44: 9b09 ldr r3, [sp, #36] ; 0x24 + 9e46: 9a05 ldr r2, [sp, #20] + 9e48: 441a add r2, r3 + for(y = 0; y < size; y++) { + 9e4a: 9b07 ldr r3, [sp, #28] + sh_ups_tmp_buf += size; + 9e4c: 9205 str r2, [sp, #20] + for(y = 0; y < size; y++) { + 9e4e: 3301 adds r3, #1 + 9e50: 9307 str r3, [sp, #28] + 9e52: e7d8 b.n 9e06 + sh_ups_tmp_buf[0] = (mask_line[0] << SHADOW_UPSACALE_SHIFT) / sw; + 9e54: 783b ldrb r3, [r7, #0] + 9e56: 9a05 ldr r2, [sp, #20] + 9e58: 9805 ldr r0, [sp, #20] + 9e5a: 019b lsls r3, r3, #6 + 9e5c: fb93 f3f4 sdiv r3, r3, r4 + 9e60: f822 3b02 strh.w r3, [r2], #2 + for(i = 1; i < size; i++) { + 9e64: 9b09 ldr r3, [sp, #36] ; 0x24 + 9e66: 4639 mov r1, r7 + 9e68: 1818 adds r0, r3, r0 + 9e6a: 4282 cmp r2, r0 + 9e6c: d0ea beq.n 9e44 + if(mask_line[i] == mask_line[i - 1]) sh_ups_tmp_buf[i] = sh_ups_tmp_buf[i - 1]; + 9e6e: 468c mov ip, r1 + 9e70: f811 3f01 ldrb.w r3, [r1, #1]! + 9e74: f89c c000 ldrb.w ip, [ip] + 9e78: 459c cmp ip, r3 + else sh_ups_tmp_buf[i] = (mask_line[i] << SHADOW_UPSACALE_SHIFT) / sw; + 9e7a: bf17 itett ne + 9e7c: 019b lslne r3, r3, #6 + if(mask_line[i] == mask_line[i - 1]) sh_ups_tmp_buf[i] = sh_ups_tmp_buf[i - 1]; + 9e7e: f832 3c02 ldrheq.w r3, [r2, #-2] + else sh_ups_tmp_buf[i] = (mask_line[i] << SHADOW_UPSACALE_SHIFT) / sw; + 9e82: fb93 f3f4 sdivne r3, r3, r4 + 9e86: b29b uxthne r3, r3 + if(mask_line[i] == mask_line[i - 1]) sh_ups_tmp_buf[i] = sh_ups_tmp_buf[i - 1]; + 9e88: f822 3b02 strh.w r3, [r2], #2 + for(i = 1; i < size; i++) { + 9e8c: e7ed b.n 9e6a + res_buf[i] = (sh_buf[i] >> SHADOW_UPSACALE_SHIFT); + 9e8e: 9a06 ldr r2, [sp, #24] + 9e90: 9906 ldr r1, [sp, #24] + 9e92: f832 2013 ldrh.w r2, [r2, r3, lsl #1] + 9e96: 0992 lsrs r2, r2, #6 + 9e98: 54ca strb r2, [r1, r3] + for(i = 0; i < size * size; i++) { + 9e9a: 3301 adds r3, #1 + 9e9c: 42ab cmp r3, r5 + 9e9e: d1f6 bne.n 9e8e + 9ea0: f8bd 304e ldrh.w r3, [sp, #78] ; 0x4e + lv_coord_t h_half = sh_area.y1 + lv_area_get_height(&sh_area) / 2; + 9ea4: f8bd 204a ldrh.w r2, [sp, #74] ; 0x4a + 9ea8: 3301 adds r3, #1 + 9eaa: 1a9b subs r3, r3, r2 + 9eac: f3c3 31c0 ubfx r1, r3, #15, #1 + 9eb0: fa01 f383 sxtah r3, r1, r3 + 9eb4: eb02 0363 add.w r3, r2, r3, asr #1 + 9eb8: b29a uxth r2, r3 + 9eba: b21b sxth r3, r3 + 9ebc: 9309 str r3, [sp, #36] ; 0x24 + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + 9ebe: f8bd 304c ldrh.w r3, [sp, #76] ; 0x4c + 9ec2: 920b str r2, [sp, #44] ; 0x2c + lv_coord_t w_half = sh_area.x1 + lv_area_get_width(&sh_area) / 2; + 9ec4: f8bd 2048 ldrh.w r2, [sp, #72] ; 0x48 + 9ec8: 3301 adds r3, #1 + 9eca: 1a9b subs r3, r3, r2 + 9ecc: f3c3 31c0 ubfx r1, r3, #15, #1 + 9ed0: fa01 f383 sxtah r3, r1, r3 + 9ed4: eb02 0363 add.w r3, r2, r3, asr #1 + 9ed8: b29a uxth r2, r3 + 9eda: b21b sxth r3, r3 + 9edc: 930a str r3, [sp, #40] ; 0x28 + if(lv_draw_mask_get_cnt() > 0) simple_mode = false; + 9ede: 4b2a ldr r3, [pc, #168] ; (9f88 ) + lv_coord_t w_half = sh_area.x1 + lv_area_get_width(&sh_area) / 2; + 9ee0: 920c str r2, [sp, #48] ; 0x30 + if(lv_draw_mask_get_cnt() > 0) simple_mode = false; + 9ee2: 4798 blx r3 + 9ee4: 2800 cmp r0, #0 + 9ee6: d13b bne.n 9f60 + else if(dsc->shadow_ofs_x != 0 || dsc->shadow_ofs_y != 0) simple_mode = false; + 9ee8: f9ba 3022 ldrsh.w r3, [sl, #34] ; 0x22 + 9eec: 2b00 cmp r3, #0 + 9eee: d14f bne.n 9f90 + 9ef0: f9ba 2024 ldrsh.w r2, [sl, #36] ; 0x24 + 9ef4: b922 cbnz r2, 9f00 + else if(dsc->shadow_spread != 0) simple_mode = false; + 9ef6: f9ba 3026 ldrsh.w r3, [sl, #38] ; 0x26 + 9efa: fab3 f383 clz r3, r3 + 9efe: 095b lsrs r3, r3, #5 + if(lv_draw_mask_get_cnt() > 0) simple_mode = false; + 9f00: 9307 str r3, [sp, #28] + 9f02: e046 b.n 9f92 + shadow_blur_corner(size, sw, sh_buf); + 9f04: b230 sxth r0, r6 + 9f06: 4621 mov r1, r4 + 9f08: 9a06 ldr r2, [sp, #24] + 9f0a: 4f20 ldr r7, [pc, #128] ; (9f8c ) + 9f0c: 9005 str r0, [sp, #20] + 9f0e: 47b8 blx r7 + sw += sw_ori & 1; + 9f10: 990a ldr r1, [sp, #40] ; 0x28 + 9f12: 4421 add r1, r4 + if(sw > 1) { + 9f14: 2901 cmp r1, #1 + 9f16: dd0c ble.n 9f32 + sh_buf[0] = (sh_buf[0] << SHADOW_UPSACALE_SHIFT) / sw; + 9f18: 9b06 ldr r3, [sp, #24] + 9f1a: 9a06 ldr r2, [sp, #24] + 9f1c: 881b ldrh r3, [r3, #0] + for(i = 1; i < (uint32_t) size * size; i++) { + 9f1e: 9805 ldr r0, [sp, #20] + sh_buf[0] = (sh_buf[0] << SHADOW_UPSACALE_SHIFT) / sw; + 9f20: 019b lsls r3, r3, #6 + for(i = 1; i < (uint32_t) size * size; i++) { + 9f22: 2401 movs r4, #1 + sh_buf[0] = (sh_buf[0] << SHADOW_UPSACALE_SHIFT) / sw; + 9f24: fbb3 f3f1 udiv r3, r3, r1 + 9f28: 8013 strh r3, [r2, #0] + for(i = 1; i < (uint32_t) size * size; i++) { + 9f2a: 42ac cmp r4, r5 + 9f2c: d303 bcc.n 9f36 + shadow_blur_corner(size, sw, sh_buf); + 9f2e: 9a06 ldr r2, [sp, #24] + 9f30: 47b8 blx r7 + for(i = 1; i < (uint32_t) size * size; i++) { + 9f32: 2300 movs r3, #0 + 9f34: e011 b.n 9f5a + if(sh_buf[i] == sh_buf[i - 1]) sh_buf[i] = sh_buf[i - 1]; + 9f36: 8853 ldrh r3, [r2, #2] + 9f38: f832 6b02 ldrh.w r6, [r2], #2 + 9f3c: 42b3 cmp r3, r6 + else sh_buf[i] = (sh_buf[i] << SHADOW_UPSACALE_SHIFT) / sw; + 9f3e: bf1e ittt ne + 9f40: 019b lslne r3, r3, #6 + 9f42: fbb3 f3f1 udivne r3, r3, r1 + 9f46: b29e uxthne r6, r3 + 9f48: 8016 strh r6, [r2, #0] + for(i = 1; i < (uint32_t) size * size; i++) { + 9f4a: 3401 adds r4, #1 + 9f4c: e7ed b.n 9f2a + res_buf[x] = sh_buf[x]; + 9f4e: 9a06 ldr r2, [sp, #24] + 9f50: 9906 ldr r1, [sp, #24] + 9f52: f832 2013 ldrh.w r2, [r2, r3, lsl #1] + 9f56: 54ca strb r2, [r1, r3] + for(x = 0; x < size * size; x++) { + 9f58: 3301 adds r3, #1 + 9f5a: 42ab cmp r3, r5 + 9f5c: d1f7 bne.n 9f4e + 9f5e: e79f b.n 9ea0 + if(lv_draw_mask_get_cnt() > 0) simple_mode = false; + 9f60: 2300 movs r3, #0 + 9f62: e7cd b.n 9f00 + 9f64: 00004fe9 .word 0x00004fe9 + 9f68: 0000d9e1 .word 0x0000d9e1 + 9f6c: 0000de8d .word 0x0000de8d + 9f70: 00009b8d .word 0x00009b8d + 9f74: 0000eeb5 .word 0x0000eeb5 + 9f78: 00009915 .word 0x00009915 + 9f7c: 0000eb69 .word 0x0000eb69 + 9f80: 0000f075 .word 0x0000f075 + 9f84: 0000f019 .word 0x0000f019 + 9f88: 000097f1 .word 0x000097f1 + 9f8c: 00009a05 .word 0x00009a05 + 9f90: 9007 str r0, [sp, #28] + 9f92: f8bd 004c ldrh.w r0, [sp, #76] ; 0x4c + 9f96: f8bd 3048 ldrh.w r3, [sp, #72] ; 0x48 + lv_draw_mask_radius_init(&mask_rout_param, &bg_coords, r_bg, true); + 9f9a: 4db2 ldr r5, [pc, #712] ; (a264 ) + 9f9c: 3001 adds r0, #1 + 9f9e: 1ac0 subs r0, r0, r3 + lv_opa_t * mask_buf = _lv_mem_buf_get(lv_area_get_width(&sh_area)); + 9fa0: b200 sxth r0, r0 + 9fa2: 4bb1 ldr r3, [pc, #708] ; (a268 ) + 9fa4: 4798 blx r3 + lv_draw_mask_radius_init(&mask_rout_param, &bg_coords, r_bg, true); + 9fa6: ee18 2a90 vmov r2, s17 + 9faa: 2301 movs r3, #1 + 9fac: a916 add r1, sp, #88 ; 0x58 + lv_opa_t * mask_buf = _lv_mem_buf_get(lv_area_get_width(&sh_area)); + 9fae: ee08 0a10 vmov s16, r0 + lv_draw_mask_radius_init(&mask_rout_param, &bg_coords, r_bg, true); + 9fb2: a825 add r0, sp, #148 ; 0x94 + 9fb4: 47a8 blx r5 + int16_t mask_rout_id = lv_draw_mask_add(&mask_rout_param, NULL); + 9fb6: 4bad ldr r3, [pc, #692] ; (a26c ) + 9fb8: 2100 movs r1, #0 + 9fba: a825 add r0, sp, #148 ; 0x94 + 9fbc: 4798 blx r3 + a.x2 = sh_area.x2; + 9fbe: f9bd 304c ldrsh.w r3, [sp, #76] ; 0x4c + 9fc2: f8ad 3064 strh.w r3, [sp, #100] ; 0x64 + a.x1 = a.x2 - corner_size + 1; + 9fc6: fa1f f289 uxth.w r2, r9 + 9fca: 3301 adds r3, #1 + 9fcc: 1a9b subs r3, r3, r2 + 9fce: f8ad 3060 strh.w r3, [sp, #96] ; 0x60 + a.y1 = sh_area.y1; + 9fd2: f9bd 304a ldrsh.w r3, [sp, #74] ; 0x4a + 9fd6: f8ad 3062 strh.w r3, [sp, #98] ; 0x62 + a.y2 = a.y1 + corner_size - 1; + 9fda: 3b01 subs r3, #1 + 9fdc: 4413 add r3, r2 + int16_t mask_rout_id = lv_draw_mask_add(&mask_rout_param, NULL); + 9fde: ee08 0a90 vmov s17, r0 + a.x1 = a.x2 - corner_size + 1; + 9fe2: 9205 str r2, [sp, #20] + a.y2 = a.y1 + corner_size - 1; + 9fe4: f8ad 3066 strh.w r3, [sp, #102] ; 0x66 + bool has_com = _lv_area_intersect(&ca, &a, clip); + 9fe8: 4642 mov r2, r8 + 9fea: 4ba1 ldr r3, [pc, #644] ; (a270 ) + 9fec: a918 add r1, sp, #96 ; 0x60 + 9fee: a81a add r0, sp, #104 ; 0x68 + 9ff0: 4798 blx r3 + if(has_com) { + 9ff2: 2800 cmp r0, #0 + 9ff4: d039 beq.n a06a + if(ca.y2 > h_half) ca.y2 = h_half; + 9ff6: f9bd 306e ldrsh.w r3, [sp, #110] ; 0x6e + 9ffa: 9a09 ldr r2, [sp, #36] ; 0x24 + 9ffc: f8bd 606c ldrh.w r6, [sp, #108] ; 0x6c + a000: 4293 cmp r3, r2 + a002: bfc4 itt gt + a004: 4613 movgt r3, r2 + a006: f8ad 306e strhgt.w r3, [sp, #110] ; 0x6e + if(ca.x1 <= w_half) ca.x1 = w_half + 1; + a00a: 9a0a ldr r2, [sp, #40] ; 0x28 + a00c: f9bd 3068 ldrsh.w r3, [sp, #104] ; 0x68 + a010: 4293 cmp r3, r2 + a012: bfd8 it le + a014: 9b0c ldrle r3, [sp, #48] ; 0x30 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + a016: f9bd 206a ldrsh.w r2, [sp, #106] ; 0x6a + a01a: bfdc itt le + a01c: 3301 addle r3, #1 + a01e: f8ad 3068 strhle.w r3, [sp, #104] ; 0x68 + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + a022: f9bd 5068 ldrsh.w r5, [sp, #104] ; 0x68 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + a026: f9bd 306e ldrsh.w r3, [sp, #110] ; 0x6e + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + a02a: 3601 adds r6, #1 + a02c: 1b76 subs r6, r6, r5 + a02e: b236 sxth r6, r6 + if(w > 0) { + a030: 2e00 cmp r6, #0 + a032: dd1a ble.n a06a + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + a034: 3301 adds r3, #1 + a036: 1a9b subs r3, r3, r2 + a038: b21b sxth r3, r3 + a03a: 930d str r3, [sp, #52] ; 0x34 + sh_buf_tmp += corner_size * (ca.y1 - a.y1); + a03c: f9bd 3062 ldrsh.w r3, [sp, #98] ; 0x62 + a040: 1ad2 subs r2, r2, r3 + sh_buf_tmp = sh_buf + (ca.x1 - a.x1); + a042: f9bd 3060 ldrsh.w r3, [sp, #96] ; 0x60 + a046: 1aed subs r5, r5, r3 + sh_buf_tmp += corner_size * (ca.y1 - a.y1); + a048: 9b06 ldr r3, [sp, #24] + a04a: fb09 5502 mla r5, r9, r2, r5 + a04e: 441d add r5, r3 + lv_area_copy(&fa, &ca); + a050: a91a add r1, sp, #104 ; 0x68 + a052: 4b88 ldr r3, [pc, #544] ; (a274 ) + a054: a81e add r0, sp, #120 ; 0x78 + a056: 4798 blx r3 + fa.y2 = fa.y1; + a058: f9bd 307a ldrsh.w r3, [sp, #122] ; 0x7a + for(y = 0; y < h; y++) { + a05c: 2700 movs r7, #0 + fa.y2 = fa.y1; + a05e: f8ad 307e strh.w r3, [sp, #126] ; 0x7e + for(y = 0; y < h; y++) { + a062: 9b0d ldr r3, [sp, #52] ; 0x34 + a064: 429f cmp r7, r3 + a066: f2c0 80a3 blt.w a1b0 + a.x2 = sh_area.x2; + a06a: f9bd 304c ldrsh.w r3, [sp, #76] ; 0x4c + a.x1 = a.x2 - corner_size + 1; + a06e: 9a05 ldr r2, [sp, #20] + a.x2 = sh_area.x2; + a070: f8ad 3064 strh.w r3, [sp, #100] ; 0x64 + a.x1 = a.x2 - corner_size + 1; + a074: 3301 adds r3, #1 + a076: 1a9b subs r3, r3, r2 + a.y1 = sh_area.y2 - corner_size + 1; + a078: f9bd 204e ldrsh.w r2, [sp, #78] ; 0x4e + a07c: 9905 ldr r1, [sp, #20] + a.x1 = a.x2 - corner_size + 1; + a07e: f8ad 3060 strh.w r3, [sp, #96] ; 0x60 + a.y1 = sh_area.y2 - corner_size + 1; + a082: 1c53 adds r3, r2, #1 + a084: 1a5b subs r3, r3, r1 + a086: f8ad 3062 strh.w r3, [sp, #98] ; 0x62 + a.y2 = sh_area.y2; + a08a: f8ad 2066 strh.w r2, [sp, #102] ; 0x66 + has_com = _lv_area_intersect(&ca, &a, clip); + a08e: 4b78 ldr r3, [pc, #480] ; (a270 ) + a090: 4642 mov r2, r8 + a092: a918 add r1, sp, #96 ; 0x60 + a094: a81a add r0, sp, #104 ; 0x68 + a096: 4798 blx r3 + if(has_com) { + a098: 2800 cmp r0, #0 + a09a: d03a beq.n a112 + if(ca.y1 <= h_half) ca.y1 = h_half + 1; + a09c: f9bd 306a ldrsh.w r3, [sp, #106] ; 0x6a + a0a0: 9a09 ldr r2, [sp, #36] ; 0x24 + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + a0a2: f8bd 606c ldrh.w r6, [sp, #108] ; 0x6c + a0a6: 4293 cmp r3, r2 + a0a8: bfd8 it le + a0aa: 9b0b ldrle r3, [sp, #44] ; 0x2c + if(ca.x1 <= w_half) ca.x1 = w_half + 1; + a0ac: 9a0a ldr r2, [sp, #40] ; 0x28 + if(ca.y1 <= h_half) ca.y1 = h_half + 1; + a0ae: bfdc itt le + a0b0: 3301 addle r3, #1 + a0b2: f8ad 306a strhle.w r3, [sp, #106] ; 0x6a + if(ca.x1 <= w_half) ca.x1 = w_half + 1; + a0b6: f9bd 3068 ldrsh.w r3, [sp, #104] ; 0x68 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + a0ba: f9bd 106a ldrsh.w r1, [sp, #106] ; 0x6a + a0be: 4293 cmp r3, r2 + a0c0: bfd8 it le + a0c2: 9b0c ldrle r3, [sp, #48] ; 0x30 + a0c4: f9bd 206e ldrsh.w r2, [sp, #110] ; 0x6e + a0c8: bfdc itt le + a0ca: 3301 addle r3, #1 + a0cc: f8ad 3068 strhle.w r3, [sp, #104] ; 0x68 + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + a0d0: f9bd 5068 ldrsh.w r5, [sp, #104] ; 0x68 + a0d4: 3601 adds r6, #1 + a0d6: 1b76 subs r6, r6, r5 + a0d8: b236 sxth r6, r6 + if(w > 0) { + a0da: 2e00 cmp r6, #0 + a0dc: dd19 ble.n a112 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + a0de: 1c53 adds r3, r2, #1 + a0e0: 1a5b subs r3, r3, r1 + a0e2: b21b sxth r3, r3 + a0e4: 930c str r3, [sp, #48] ; 0x30 + sh_buf_tmp += corner_size * (a.y2 - ca.y2); + a0e6: f9bd 3066 ldrsh.w r3, [sp, #102] ; 0x66 + a0ea: 1a9b subs r3, r3, r2 + sh_buf_tmp = sh_buf + (ca.x1 - a.x1); + a0ec: f9bd 2060 ldrsh.w r2, [sp, #96] ; 0x60 + a0f0: 1aad subs r5, r5, r2 + sh_buf_tmp += corner_size * (a.y2 - ca.y2); + a0f2: fb09 5503 mla r5, r9, r3, r5 + a0f6: 9b06 ldr r3, [sp, #24] + lv_area_copy(&fa, &ca); + a0f8: a91a add r1, sp, #104 ; 0x68 + sh_buf_tmp += corner_size * (a.y2 - ca.y2); + a0fa: 441d add r5, r3 + lv_area_copy(&fa, &ca); + a0fc: a81e add r0, sp, #120 ; 0x78 + a0fe: 4b5d ldr r3, [pc, #372] ; (a274 ) + a100: 4798 blx r3 + fa.y1 = fa.y2; /*Fill from bottom to top*/ + a102: f8bd 307e ldrh.w r3, [sp, #126] ; 0x7e + a106: f8ad 307a strh.w r3, [sp, #122] ; 0x7a + for(y = 0; y < h; y++) { + a10a: 2700 movs r7, #0 + a10c: 9b0c ldr r3, [sp, #48] ; 0x30 + a10e: 429f cmp r7, r3 + a110: db7a blt.n a208 + a.x2 = sh_area.x2; + a112: f9bd 304c ldrsh.w r3, [sp, #76] ; 0x4c + a.x1 = a.x2 - corner_size + 1; + a116: 9a05 ldr r2, [sp, #20] + a.x2 = sh_area.x2; + a118: f8ad 3064 strh.w r3, [sp, #100] ; 0x64 + a.x1 = a.x2 - corner_size + 1; + a11c: 3301 adds r3, #1 + a11e: 1a9b subs r3, r3, r2 + a120: f8ad 3060 strh.w r3, [sp, #96] ; 0x60 + a.y1 = sh_area.y1 + corner_size; + a124: f8bd 304a ldrh.w r3, [sp, #74] ; 0x4a + a128: 4413 add r3, r2 + a12a: f8ad 3062 strh.w r3, [sp, #98] ; 0x62 + a.y2 = sh_area.y2 - corner_size; + a12e: f8bd 304e ldrh.w r3, [sp, #78] ; 0x4e + a132: 1a9b subs r3, r3, r2 + a134: f8ad 3066 strh.w r3, [sp, #102] ; 0x66 + has_com = _lv_area_intersect(&ca, &a, clip); + a138: 4642 mov r2, r8 + a13a: 4b4d ldr r3, [pc, #308] ; (a270 ) + a13c: a918 add r1, sp, #96 ; 0x60 + a13e: a81a add r0, sp, #104 ; 0x68 + a140: 4798 blx r3 + if(has_com) { + a142: b380 cbz r0, a1a6 + if(simple_mode) ca.x1 = LV_MATH_MAX(ca.x1, coords->x2); + a144: 9b07 ldr r3, [sp, #28] + a146: b143 cbz r3, a15a + a148: f9bb 3004 ldrsh.w r3, [fp, #4] + a14c: f9bd 2068 ldrsh.w r2, [sp, #104] ; 0x68 + a150: 4293 cmp r3, r2 + a152: bfb8 it lt + a154: 4613 movlt r3, r2 + a156: f8ad 3068 strh.w r3, [sp, #104] ; 0x68 + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + a15a: f8bd 506c ldrh.w r5, [sp, #108] ; 0x6c + a15e: f9bd 6068 ldrsh.w r6, [sp, #104] ; 0x68 + a162: 3501 adds r5, #1 + a164: 1bad subs r5, r5, r6 + a166: b22d sxth r5, r5 + if(w > 0) { + a168: 2d00 cmp r5, #0 + a16a: dd1c ble.n a1a6 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + a16c: f8bd 306e ldrh.w r3, [sp, #110] ; 0x6e + a170: f8bd 206a ldrh.w r2, [sp, #106] ; 0x6a + a174: 3301 adds r3, #1 + a176: 1a9b subs r3, r3, r2 + sh_buf_tmp += ca.x1 - a.x1; + a178: f9bd 2060 ldrsh.w r2, [sp, #96] ; 0x60 + a17c: b21b sxth r3, r3 + a17e: 930c str r3, [sp, #48] ; 0x30 + a180: 1ab6 subs r6, r6, r2 + sh_buf_tmp = sh_buf + corner_size * (corner_size - 1); + a182: f109 33ff add.w r3, r9, #4294967295 ; 0xffffffff + sh_buf_tmp += ca.x1 - a.x1; + a186: fb09 6603 mla r6, r9, r3, r6 + a18a: 9b06 ldr r3, [sp, #24] + lv_area_copy(&fa, &ca); + a18c: a91a add r1, sp, #104 ; 0x68 + sh_buf_tmp += ca.x1 - a.x1; + a18e: 441e add r6, r3 + lv_area_copy(&fa, &ca); + a190: a81e add r0, sp, #120 ; 0x78 + a192: 4b38 ldr r3, [pc, #224] ; (a274 ) + a194: 4798 blx r3 + fa.y2 = fa.y1; + a196: f9bd 307a ldrsh.w r3, [sp, #122] ; 0x7a + for(y = 0; y < h; y++) { + a19a: 2700 movs r7, #0 + fa.y2 = fa.y1; + a19c: f8ad 307e strh.w r3, [sp, #126] ; 0x7e + for(y = 0; y < h; y++) { + a1a0: 9b0c ldr r3, [sp, #48] ; 0x30 + a1a2: 429f cmp r7, r3 + a1a4: db6e blt.n a284 + sh_buf = _lv_mem_buf_get(corner_size * corner_size * sizeof(uint16_t)); + a1a6: 9a06 ldr r2, [sp, #24] + for(x = 0; x < corner_size / 2; x++) { + a1a8: ea4f 0669 mov.w r6, r9, asr #1 + a1ac: 2000 movs r0, #0 + a1ae: e0a3 b.n a2f8 + _lv_memcpy(mask_buf, sh_buf_tmp, w); + a1b0: 4629 mov r1, r5 + a1b2: 4b31 ldr r3, [pc, #196] ; (a278 ) + mask_res = lv_draw_mask_apply(mask_buf, fa.x1, fa.y1, w); + a1b4: 4c31 ldr r4, [pc, #196] ; (a27c ) + _lv_memcpy(mask_buf, sh_buf_tmp, w); + a1b6: 4632 mov r2, r6 + a1b8: ee18 0a10 vmov r0, s16 + a1bc: 4798 blx r3 + mask_res = lv_draw_mask_apply(mask_buf, fa.x1, fa.y1, w); + a1be: f9bd 207a ldrsh.w r2, [sp, #122] ; 0x7a + a1c2: f9bd 1078 ldrsh.w r1, [sp, #120] ; 0x78 + a1c6: 4633 mov r3, r6 + a1c8: ee18 0a10 vmov r0, s16 + a1cc: 47a0 blx r4 + _lv_blend_fill(clip, &fa, dsc->shadow_color, mask_buf, + a1ce: f89a 3029 ldrb.w r3, [sl, #41] ; 0x29 + a1d2: 9302 str r3, [sp, #8] + if(mask_res == LV_DRAW_MASK_RES_FULL_COVER) mask_res = LV_DRAW_MASK_RES_CHANGED; + a1d4: 2801 cmp r0, #1 + _lv_blend_fill(clip, &fa, dsc->shadow_color, mask_buf, + a1d6: 9b08 ldr r3, [sp, #32] + a1d8: 4c29 ldr r4, [pc, #164] ; (a280 ) + if(mask_res == LV_DRAW_MASK_RES_FULL_COVER) mask_res = LV_DRAW_MASK_RES_CHANGED; + a1da: bf08 it eq + a1dc: 2002 moveq r0, #2 + _lv_blend_fill(clip, &fa, dsc->shadow_color, mask_buf, + a1de: e9cd 0300 strd r0, r3, [sp] + a1e2: a91e add r1, sp, #120 ; 0x78 + a1e4: ee18 3a10 vmov r3, s16 + a1e8: f8ba 201e ldrh.w r2, [sl, #30] + a1ec: 4640 mov r0, r8 + a1ee: 47a0 blx r4 + fa.y1++; + a1f0: f8bd 307a ldrh.w r3, [sp, #122] ; 0x7a + a1f4: 3301 adds r3, #1 + a1f6: f8ad 307a strh.w r3, [sp, #122] ; 0x7a + fa.y2++; + a1fa: f8bd 307e ldrh.w r3, [sp, #126] ; 0x7e + a1fe: 3301 adds r3, #1 + a200: b21b sxth r3, r3 + sh_buf_tmp += corner_size; + a202: 444d add r5, r9 + for(y = 0; y < h; y++) { + a204: 3701 adds r7, #1 + a206: e72a b.n a05e + _lv_memcpy(mask_buf, sh_buf_tmp, w); + a208: 4629 mov r1, r5 + a20a: 4b1b ldr r3, [pc, #108] ; (a278 ) + mask_res = lv_draw_mask_apply(mask_buf, fa.x1, fa.y1, w); + a20c: 4c1b ldr r4, [pc, #108] ; (a27c ) + _lv_memcpy(mask_buf, sh_buf_tmp, w); + a20e: 4632 mov r2, r6 + a210: ee18 0a10 vmov r0, s16 + a214: 4798 blx r3 + mask_res = lv_draw_mask_apply(mask_buf, fa.x1, fa.y1, w); + a216: f9bd 207a ldrsh.w r2, [sp, #122] ; 0x7a + a21a: f9bd 1078 ldrsh.w r1, [sp, #120] ; 0x78 + a21e: 4633 mov r3, r6 + a220: ee18 0a10 vmov r0, s16 + a224: 47a0 blx r4 + _lv_blend_fill(clip, &fa, dsc->shadow_color, mask_buf, + a226: f89a 3029 ldrb.w r3, [sl, #41] ; 0x29 + a22a: 9302 str r3, [sp, #8] + if(mask_res == LV_DRAW_MASK_RES_FULL_COVER) mask_res = LV_DRAW_MASK_RES_CHANGED; + a22c: 2801 cmp r0, #1 + _lv_blend_fill(clip, &fa, dsc->shadow_color, mask_buf, + a22e: 9b08 ldr r3, [sp, #32] + a230: 4c13 ldr r4, [pc, #76] ; (a280 ) + if(mask_res == LV_DRAW_MASK_RES_FULL_COVER) mask_res = LV_DRAW_MASK_RES_CHANGED; + a232: bf08 it eq + a234: 2002 moveq r0, #2 + _lv_blend_fill(clip, &fa, dsc->shadow_color, mask_buf, + a236: e9cd 0300 strd r0, r3, [sp] + a23a: a91e add r1, sp, #120 ; 0x78 + a23c: ee18 3a10 vmov r3, s16 + a240: f8ba 201e ldrh.w r2, [sl, #30] + a244: 4640 mov r0, r8 + a246: 47a0 blx r4 + fa.y1--; + a248: f8bd 307a ldrh.w r3, [sp, #122] ; 0x7a + a24c: 3b01 subs r3, #1 + a24e: f8ad 307a strh.w r3, [sp, #122] ; 0x7a + fa.y2--; + a252: f8bd 307e ldrh.w r3, [sp, #126] ; 0x7e + a256: 3b01 subs r3, #1 + a258: f8ad 307e strh.w r3, [sp, #126] ; 0x7e + sh_buf_tmp += corner_size; + a25c: 444d add r5, r9 + for(y = 0; y < h; y++) { + a25e: 3701 adds r7, #1 + a260: e754 b.n a10c + a262: bf00 nop + a264: 00009915 .word 0x00009915 + a268: 0000eeb5 .word 0x0000eeb5 + a26c: 00009711 .word 0x00009711 + a270: 0000de8d .word 0x0000de8d + a274: 00009b8d .word 0x00009b8d + a278: 0000ec31 .word 0x0000ec31 + a27c: 00009761 .word 0x00009761 + a280: 000061f1 .word 0x000061f1 + _lv_memcpy(mask_buf, sh_buf_tmp, w); + a284: 4b20 ldr r3, [pc, #128] ; (a308 ) + a286: ee18 0a10 vmov r0, s16 + a28a: 462a mov r2, r5 + a28c: 4631 mov r1, r6 + a28e: 4798 blx r3 + if(simple_mode) { + a290: 9b07 ldr r3, [sp, #28] + a292: b953 cbnz r3, a2aa + mask_res = lv_draw_mask_apply(mask_buf, fa.x1, fa.y1, w); + a294: f9bd 207a ldrsh.w r2, [sp, #122] ; 0x7a + a298: f9bd 1078 ldrsh.w r1, [sp, #120] ; 0x78 + a29c: 4c1b ldr r4, [pc, #108] ; (a30c ) + a29e: ee18 0a10 vmov r0, s16 + a2a2: 462b mov r3, r5 + a2a4: 47a0 blx r4 + if(mask_res == LV_DRAW_MASK_RES_FULL_COVER) mask_res = LV_DRAW_MASK_RES_CHANGED; + a2a6: 2801 cmp r0, #1 + a2a8: d100 bne.n a2ac + a2aa: 2002 movs r0, #2 + _lv_blend_fill(clip, &fa, + a2ac: f89a 3029 ldrb.w r3, [sl, #41] ; 0x29 + a2b0: 9302 str r3, [sp, #8] + a2b2: f89a 3028 ldrb.w r3, [sl, #40] ; 0x28 + a2b6: 4c16 ldr r4, [pc, #88] ; (a310 ) + a2b8: e9cd 0300 strd r0, r3, [sp] + a2bc: a91e add r1, sp, #120 ; 0x78 + a2be: ee18 3a10 vmov r3, s16 + a2c2: f8ba 201e ldrh.w r2, [sl, #30] + a2c6: 4640 mov r0, r8 + a2c8: 47a0 blx r4 + fa.y1++; + a2ca: f8bd 307a ldrh.w r3, [sp, #122] ; 0x7a + a2ce: 3301 adds r3, #1 + a2d0: f8ad 307a strh.w r3, [sp, #122] ; 0x7a + fa.y2++; + a2d4: f8bd 307e ldrh.w r3, [sp, #126] ; 0x7e + a2d8: 3301 adds r3, #1 + a2da: b21b sxth r3, r3 + for(y = 0; y < h; y++) { + a2dc: 3701 adds r7, #1 + a2de: e75d b.n a19c + lv_opa_t tmp = sh_buf_tmp[x]; + a2e0: f811 7f01 ldrb.w r7, [r1, #1]! + sh_buf_tmp[x] = sh_buf_tmp[corner_size - x - 1]; + a2e4: f813 cd01 ldrb.w ip, [r3, #-1]! + a2e8: f881 c000 strb.w ip, [r1] + sh_buf_tmp[corner_size - x - 1] = tmp; + a2ec: 701f strb r7, [r3, #0] + for(x = 0; x < corner_size / 2; x++) { + a2ee: 1aef subs r7, r5, r3 + a2f0: 42be cmp r6, r7 + a2f2: dcf5 bgt.n a2e0 + sh_buf_tmp += corner_size; + a2f4: 444a add r2, r9 + for(y = 0; y < corner_size; y++) { + a2f6: 3001 adds r0, #1 + a2f8: 4581 cmp r9, r0 + a2fa: dd0b ble.n a314 + a2fc: eb09 0502 add.w r5, r9, r2 + a300: 1e51 subs r1, r2, #1 + a302: 462b mov r3, r5 + a304: e7f3 b.n a2ee + a306: bf00 nop + a308: 0000ec31 .word 0x0000ec31 + a30c: 00009761 .word 0x00009761 + a310: 000061f1 .word 0x000061f1 + a.x1 = sh_area.x1; + a314: f9bd 3048 ldrsh.w r3, [sp, #72] ; 0x48 + a.x2 = a.x1 + corner_size - 1; + a318: 9a05 ldr r2, [sp, #20] + a.x1 = sh_area.x1; + a31a: f8ad 3060 strh.w r3, [sp, #96] ; 0x60 + a.x2 = a.x1 + corner_size - 1; + a31e: 3b01 subs r3, #1 + a320: 4413 add r3, r2 + a322: f8ad 3064 strh.w r3, [sp, #100] ; 0x64 + a.y1 = sh_area.y1; + a326: f9bd 304a ldrsh.w r3, [sp, #74] ; 0x4a + a32a: f8ad 3062 strh.w r3, [sp, #98] ; 0x62 + a.y2 = a.y1 + corner_size - 1; + a32e: 3b01 subs r3, #1 + a330: 4413 add r3, r2 + a332: f8ad 3066 strh.w r3, [sp, #102] ; 0x66 + has_com = _lv_area_intersect(&ca, &a, clip); + a336: 4642 mov r2, r8 + a338: 4bb8 ldr r3, [pc, #736] ; (a61c ) + a33a: a918 add r1, sp, #96 ; 0x60 + a33c: a81a add r0, sp, #104 ; 0x68 + a33e: 4798 blx r3 + if(has_com) { + a340: 2800 cmp r0, #0 + a342: d037 beq.n a3b4 + if(ca.y2 > h_half) ca.y2 = h_half; + a344: f9bd 306e ldrsh.w r3, [sp, #110] ; 0x6e + a348: 9a09 ldr r2, [sp, #36] ; 0x24 + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + a34a: f9bd 5068 ldrsh.w r5, [sp, #104] ; 0x68 + a34e: 4293 cmp r3, r2 + a350: bfc4 itt gt + a352: 4613 movgt r3, r2 + a354: f8ad 306e strhgt.w r3, [sp, #110] ; 0x6e + if(ca.x2 > w_half) ca.x2 = w_half; + a358: 9a0a ldr r2, [sp, #40] ; 0x28 + a35a: f9bd 306c ldrsh.w r3, [sp, #108] ; 0x6c + a35e: 4293 cmp r3, r2 + a360: bfc4 itt gt + a362: 4613 movgt r3, r2 + a364: f8ad 306c strhgt.w r3, [sp, #108] ; 0x6c + a368: f8bd 606c ldrh.w r6, [sp, #108] ; 0x6c + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + a36c: f9bd 306e ldrsh.w r3, [sp, #110] ; 0x6e + a370: f9bd 206a ldrsh.w r2, [sp, #106] ; 0x6a + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + a374: 3601 adds r6, #1 + a376: 1b76 subs r6, r6, r5 + a378: b236 sxth r6, r6 + if(w > 0) { + a37a: 2e00 cmp r6, #0 + a37c: dd1a ble.n a3b4 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + a37e: 3301 adds r3, #1 + a380: 1a9b subs r3, r3, r2 + a382: b21b sxth r3, r3 + a384: 930c str r3, [sp, #48] ; 0x30 + sh_buf_tmp += corner_size * (ca.y1 - a.y1); + a386: f9bd 3062 ldrsh.w r3, [sp, #98] ; 0x62 + a38a: 1ad2 subs r2, r2, r3 + sh_buf_tmp = sh_buf + (ca.x1 - a.x1); + a38c: f9bd 3060 ldrsh.w r3, [sp, #96] ; 0x60 + a390: 1aed subs r5, r5, r3 + sh_buf_tmp += corner_size * (ca.y1 - a.y1); + a392: 9b06 ldr r3, [sp, #24] + a394: fb09 5502 mla r5, r9, r2, r5 + a398: 441d add r5, r3 + lv_area_copy(&fa, &ca); + a39a: a91a add r1, sp, #104 ; 0x68 + a39c: 4ba0 ldr r3, [pc, #640] ; (a620 ) + a39e: a81e add r0, sp, #120 ; 0x78 + a3a0: 4798 blx r3 + fa.y2 = fa.y1; + a3a2: f9bd 307a ldrsh.w r3, [sp, #122] ; 0x7a + for(y = 0; y < h; y++) { + a3a6: 2700 movs r7, #0 + fa.y2 = fa.y1; + a3a8: f8ad 307e strh.w r3, [sp, #126] ; 0x7e + for(y = 0; y < h; y++) { + a3ac: 9b0c ldr r3, [sp, #48] ; 0x30 + a3ae: 429f cmp r7, r3 + a3b0: f2c0 859f blt.w aef2 + a.x1 = sh_area.x1; + a3b4: f9bd 3048 ldrsh.w r3, [sp, #72] ; 0x48 + a.x2 = a.x1 + corner_size - 1; + a3b8: 9a05 ldr r2, [sp, #20] + a.x1 = sh_area.x1; + a3ba: f8ad 3060 strh.w r3, [sp, #96] ; 0x60 + a.x2 = a.x1 + corner_size - 1; + a3be: 3b01 subs r3, #1 + a3c0: 4413 add r3, r2 + a.y1 = sh_area.y2 - corner_size + 1; + a3c2: f9bd 204e ldrsh.w r2, [sp, #78] ; 0x4e + a3c6: 9905 ldr r1, [sp, #20] + a.x2 = a.x1 + corner_size - 1; + a3c8: f8ad 3064 strh.w r3, [sp, #100] ; 0x64 + a.y1 = sh_area.y2 - corner_size + 1; + a3cc: 1c53 adds r3, r2, #1 + a3ce: 1a5b subs r3, r3, r1 + a3d0: f8ad 3062 strh.w r3, [sp, #98] ; 0x62 + a.y2 = sh_area.y2; + a3d4: f8ad 2066 strh.w r2, [sp, #102] ; 0x66 + has_com = _lv_area_intersect(&ca, &a, clip); + a3d8: 4b90 ldr r3, [pc, #576] ; (a61c ) + a3da: 4642 mov r2, r8 + a3dc: a918 add r1, sp, #96 ; 0x60 + a3de: a81a add r0, sp, #104 ; 0x68 + a3e0: 4798 blx r3 + if(has_com) { + a3e2: 2800 cmp r0, #0 + a3e4: d039 beq.n a45a + if(ca.y1 <= h_half) ca.y1 = h_half + 1; + a3e6: f9bd 306a ldrsh.w r3, [sp, #106] ; 0x6a + a3ea: 9a09 ldr r2, [sp, #36] ; 0x24 + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + a3ec: f9bd 5068 ldrsh.w r5, [sp, #104] ; 0x68 + a3f0: 4293 cmp r3, r2 + a3f2: bfd8 it le + a3f4: 9b0b ldrle r3, [sp, #44] ; 0x2c + if(ca.x2 > w_half) ca.x2 = w_half; + a3f6: 9a0a ldr r2, [sp, #40] ; 0x28 + if(ca.y1 <= h_half) ca.y1 = h_half + 1; + a3f8: bfdc itt le + a3fa: 3301 addle r3, #1 + a3fc: f8ad 306a strhle.w r3, [sp, #106] ; 0x6a + if(ca.x2 > w_half) ca.x2 = w_half; + a400: f9bd 306c ldrsh.w r3, [sp, #108] ; 0x6c + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + a404: f9bd 106a ldrsh.w r1, [sp, #106] ; 0x6a + a408: 4293 cmp r3, r2 + a40a: bfc4 itt gt + a40c: 4613 movgt r3, r2 + a40e: f8ad 306c strhgt.w r3, [sp, #108] ; 0x6c + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + a412: f8bd 606c ldrh.w r6, [sp, #108] ; 0x6c + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + a416: f9bd 206e ldrsh.w r2, [sp, #110] ; 0x6e + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + a41a: 3601 adds r6, #1 + a41c: 1b76 subs r6, r6, r5 + a41e: b236 sxth r6, r6 + if(w > 0) { + a420: 2e00 cmp r6, #0 + a422: dd1a ble.n a45a + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + a424: 1c53 adds r3, r2, #1 + a426: 1a5b subs r3, r3, r1 + a428: b21b sxth r3, r3 + a42a: 9309 str r3, [sp, #36] ; 0x24 + sh_buf_tmp += corner_size * (a.y2 - ca.y2); + a42c: f9bd 3066 ldrsh.w r3, [sp, #102] ; 0x66 + a430: 1a9b subs r3, r3, r2 + sh_buf_tmp = sh_buf + (ca.x1 - a.x1); + a432: f9bd 2060 ldrsh.w r2, [sp, #96] ; 0x60 + a436: 1aad subs r5, r5, r2 + sh_buf_tmp += corner_size * (a.y2 - ca.y2); + a438: fb09 5503 mla r5, r9, r3, r5 + a43c: 9b06 ldr r3, [sp, #24] + lv_area_copy(&fa, &ca); + a43e: a91a add r1, sp, #104 ; 0x68 + sh_buf_tmp += corner_size * (a.y2 - ca.y2); + a440: 441d add r5, r3 + lv_area_copy(&fa, &ca); + a442: a81e add r0, sp, #120 ; 0x78 + a444: 4b76 ldr r3, [pc, #472] ; (a620 ) + a446: 4798 blx r3 + fa.y1 = fa.y2; /*Fill from bottom to top*/ + a448: f8bd 307e ldrh.w r3, [sp, #126] ; 0x7e + a44c: f8ad 307a strh.w r3, [sp, #122] ; 0x7a + for(y = 0; y < h; y++) { + a450: 2700 movs r7, #0 + a452: 9b09 ldr r3, [sp, #36] ; 0x24 + a454: 429f cmp r7, r3 + a456: f2c0 8579 blt.w af4c + a.x1 = sh_area.x1; + a45a: f9bd 3048 ldrsh.w r3, [sp, #72] ; 0x48 + a.x2 = a.x1 + corner_size - 1; + a45e: 9a05 ldr r2, [sp, #20] + a.x1 = sh_area.x1; + a460: f8ad 3060 strh.w r3, [sp, #96] ; 0x60 + a.x2 = a.x1 + corner_size - 1; + a464: 3b01 subs r3, #1 + a466: 4413 add r3, r2 + a468: f8ad 3064 strh.w r3, [sp, #100] ; 0x64 + a.y1 = sh_area.y1 + corner_size; + a46c: f8bd 304a ldrh.w r3, [sp, #74] ; 0x4a + a470: 4413 add r3, r2 + a472: f8ad 3062 strh.w r3, [sp, #98] ; 0x62 + a.y2 = sh_area.y2 - corner_size; + a476: f8bd 304e ldrh.w r3, [sp, #78] ; 0x4e + a47a: 1a9b subs r3, r3, r2 + a47c: f8ad 3066 strh.w r3, [sp, #102] ; 0x66 + has_com = _lv_area_intersect(&ca, &a, clip); + a480: 4642 mov r2, r8 + a482: 4b66 ldr r3, [pc, #408] ; (a61c ) + a484: a918 add r1, sp, #96 ; 0x60 + a486: a81a add r0, sp, #104 ; 0x68 + a488: 4798 blx r3 + if(has_com) { + a48a: b388 cbz r0, a4f0 + if(simple_mode) ca.x2 = LV_MATH_MIN(coords->x1, ca.x2); + a48c: 9b07 ldr r3, [sp, #28] + a48e: b143 cbz r3, a4a2 + a490: f9bb 3000 ldrsh.w r3, [fp] + a494: f9bd 206c ldrsh.w r2, [sp, #108] ; 0x6c + a498: 4293 cmp r3, r2 + a49a: bfa8 it ge + a49c: 4613 movge r3, r2 + a49e: f8ad 306c strh.w r3, [sp, #108] ; 0x6c + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + a4a2: f8bd 506c ldrh.w r5, [sp, #108] ; 0x6c + a4a6: f9bd 6068 ldrsh.w r6, [sp, #104] ; 0x68 + a4aa: 3501 adds r5, #1 + a4ac: 1bad subs r5, r5, r6 + a4ae: b22d sxth r5, r5 + if(w > 0) { + a4b0: 2d00 cmp r5, #0 + a4b2: dd1d ble.n a4f0 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + a4b4: f8bd 306e ldrh.w r3, [sp, #110] ; 0x6e + a4b8: f8bd 206a ldrh.w r2, [sp, #106] ; 0x6a + a4bc: 3301 adds r3, #1 + a4be: 1a9b subs r3, r3, r2 + sh_buf_tmp += ca.x1 - a.x1; + a4c0: f9bd 2060 ldrsh.w r2, [sp, #96] ; 0x60 + a4c4: b21b sxth r3, r3 + a4c6: 9309 str r3, [sp, #36] ; 0x24 + a4c8: 1ab6 subs r6, r6, r2 + sh_buf_tmp = sh_buf + corner_size * (corner_size - 1); + a4ca: f109 33ff add.w r3, r9, #4294967295 ; 0xffffffff + sh_buf_tmp += ca.x1 - a.x1; + a4ce: fb09 6603 mla r6, r9, r3, r6 + a4d2: 9b06 ldr r3, [sp, #24] + lv_area_copy(&fa, &ca); + a4d4: a91a add r1, sp, #104 ; 0x68 + sh_buf_tmp += ca.x1 - a.x1; + a4d6: 441e add r6, r3 + lv_area_copy(&fa, &ca); + a4d8: a81e add r0, sp, #120 ; 0x78 + a4da: 4b51 ldr r3, [pc, #324] ; (a620 ) + a4dc: 4798 blx r3 + fa.y2 = fa.y1; + a4de: f9bd 307a ldrsh.w r3, [sp, #122] ; 0x7a + for(y = 0; y < h; y++) { + a4e2: 2700 movs r7, #0 + fa.y2 = fa.y1; + a4e4: f8ad 307e strh.w r3, [sp, #126] ; 0x7e + for(y = 0; y < h; y++) { + a4e8: 9b09 ldr r3, [sp, #36] ; 0x24 + a4ea: 429f cmp r7, r3 + a4ec: f2c0 855c blt.w afa8 + a.x1 = sh_area.x1 + corner_size; + a4f0: 9a05 ldr r2, [sp, #20] + a4f2: f8bd 3048 ldrh.w r3, [sp, #72] ; 0x48 + a4f6: 4413 add r3, r2 + a4f8: f8ad 3060 strh.w r3, [sp, #96] ; 0x60 + a.x2 = sh_area.x2 - corner_size; + a4fc: f8bd 304c ldrh.w r3, [sp, #76] ; 0x4c + a500: 1a9b subs r3, r3, r2 + a502: f8ad 3064 strh.w r3, [sp, #100] ; 0x64 + a.y1 = sh_area.y1; + a506: f9bd 304a ldrsh.w r3, [sp, #74] ; 0x4a + a50a: f8ad 3062 strh.w r3, [sp, #98] ; 0x62 + a.y2 = sh_area.y1 + corner_size - 1; + a50e: 3b01 subs r3, #1 + a510: 4413 add r3, r2 + a512: f8ad 3066 strh.w r3, [sp, #102] ; 0x66 + has_com = _lv_area_intersect(&ca, &a, clip); + a516: 4642 mov r2, r8 + a518: 4b40 ldr r3, [pc, #256] ; (a61c ) + a51a: a918 add r1, sp, #96 ; 0x60 + a51c: a81a add r0, sp, #104 ; 0x68 + a51e: 4798 blx r3 + if(has_com) { + a520: b378 cbz r0, a582 + if(simple_mode) ca.y2 = LV_MATH_MIN(ca.y2, coords->y1); + a522: 9b07 ldr r3, [sp, #28] + a524: b143 cbz r3, a538 + a526: f9bb 3002 ldrsh.w r3, [fp, #2] + a52a: f9bd 206e ldrsh.w r2, [sp, #110] ; 0x6e + a52e: 4293 cmp r3, r2 + a530: bfa8 it ge + a532: 4613 movge r3, r2 + a534: f8ad 306e strh.w r3, [sp, #110] ; 0x6e + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + a538: f8bd 506c ldrh.w r5, [sp, #108] ; 0x6c + a53c: f8bd 3068 ldrh.w r3, [sp, #104] ; 0x68 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + a540: f9bd 206a ldrsh.w r2, [sp, #106] ; 0x6a + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + a544: 3501 adds r5, #1 + a546: 1aed subs r5, r5, r3 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + a548: f8bd 306e ldrh.w r3, [sp, #110] ; 0x6e + a54c: 3301 adds r3, #1 + a54e: 1a9b subs r3, r3, r2 + a550: b21b sxth r3, r3 + a552: 9309 str r3, [sp, #36] ; 0x24 + sh_buf_tmp += corner_size * (ca.y1 - a.y1); + a554: f9bd 3062 ldrsh.w r3, [sp, #98] ; 0x62 + sh_buf_tmp = sh_buf + corner_size - 1; + a558: f109 36ff add.w r6, r9, #4294967295 ; 0xffffffff + sh_buf_tmp += corner_size * (ca.y1 - a.y1); + a55c: 1ad2 subs r2, r2, r3 + a55e: 9b06 ldr r3, [sp, #24] + a560: fb09 6602 mla r6, r9, r2, r6 + a564: 441e add r6, r3 + lv_area_copy(&fa, &ca); + a566: a91a add r1, sp, #104 ; 0x68 + a568: 4b2d ldr r3, [pc, #180] ; (a620 ) + a56a: a81e add r0, sp, #120 ; 0x78 + a56c: 4798 blx r3 + fa.y2 = fa.y1; + a56e: f9bd 307a ldrsh.w r3, [sp, #122] ; 0x7a + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + a572: b22d sxth r5, r5 + for(y = 0; y < h; y++) { + a574: 2700 movs r7, #0 + fa.y2 = fa.y1; + a576: f8ad 307e strh.w r3, [sp, #126] ; 0x7e + for(y = 0; y < h; y++) { + a57a: 9b09 ldr r3, [sp, #36] ; 0x24 + a57c: 429f cmp r7, r3 + a57e: f2c0 8542 blt.w b006 + a.x1 = sh_area.x1 + corner_size; + a582: 9a05 ldr r2, [sp, #20] + a584: f8bd 3048 ldrh.w r3, [sp, #72] ; 0x48 + a.y1 = sh_area.y2 - corner_size + 1; + a588: 9905 ldr r1, [sp, #20] + a.x1 = sh_area.x1 + corner_size; + a58a: 4413 add r3, r2 + a58c: f8ad 3060 strh.w r3, [sp, #96] ; 0x60 + a.x2 = sh_area.x2 - corner_size; + a590: f8bd 304c ldrh.w r3, [sp, #76] ; 0x4c + a594: 1a9b subs r3, r3, r2 + a.y1 = sh_area.y2 - corner_size + 1; + a596: f9bd 204e ldrsh.w r2, [sp, #78] ; 0x4e + a.x2 = sh_area.x2 - corner_size; + a59a: f8ad 3064 strh.w r3, [sp, #100] ; 0x64 + a.y1 = sh_area.y2 - corner_size + 1; + a59e: 1c53 adds r3, r2, #1 + a5a0: 1a5b subs r3, r3, r1 + a5a2: f8ad 3062 strh.w r3, [sp, #98] ; 0x62 + a.y2 = sh_area.y2; + a5a6: f8ad 2066 strh.w r2, [sp, #102] ; 0x66 + has_com = _lv_area_intersect(&ca, &a, clip); + a5aa: 4b1c ldr r3, [pc, #112] ; (a61c ) + a5ac: 4642 mov r2, r8 + a5ae: a918 add r1, sp, #96 ; 0x60 + a5b0: a81a add r0, sp, #104 ; 0x68 + a5b2: 4798 blx r3 + if(has_com) { + a5b4: 2800 cmp r0, #0 + a5b6: d035 beq.n a624 + if(simple_mode) ca.y1 = LV_MATH_MAX(ca.y1, coords->y2); + a5b8: 9b07 ldr r3, [sp, #28] + a5ba: b143 cbz r3, a5ce + a5bc: f9bb 3006 ldrsh.w r3, [fp, #6] + a5c0: f9bd 206a ldrsh.w r2, [sp, #106] ; 0x6a + a5c4: 4293 cmp r3, r2 + a5c6: bfb8 it lt + a5c8: 4613 movlt r3, r2 + a5ca: f8ad 306a strh.w r3, [sp, #106] ; 0x6a + a5ce: f8bd 506c ldrh.w r5, [sp, #108] ; 0x6c + a5d2: f8bd 3068 ldrh.w r3, [sp, #104] ; 0x68 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + a5d6: f9bd 206e ldrsh.w r2, [sp, #110] ; 0x6e + a5da: f8bd 106a ldrh.w r1, [sp, #106] ; 0x6a + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + a5de: 3501 adds r5, #1 + a5e0: 1aed subs r5, r5, r3 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + a5e2: 1c53 adds r3, r2, #1 + a5e4: 1a5b subs r3, r3, r1 + a5e6: b21b sxth r3, r3 + a5e8: 9309 str r3, [sp, #36] ; 0x24 + sh_buf_tmp += corner_size * (a.y2 - ca.y2); + a5ea: f9bd 3066 ldrsh.w r3, [sp, #102] ; 0x66 + sh_buf_tmp = sh_buf + corner_size - 1; + a5ee: f109 36ff add.w r6, r9, #4294967295 ; 0xffffffff + sh_buf_tmp += corner_size * (a.y2 - ca.y2); + a5f2: 1a9b subs r3, r3, r2 + a5f4: fb09 6603 mla r6, r9, r3, r6 + a5f8: 9b06 ldr r3, [sp, #24] + lv_area_copy(&fa, &ca); + a5fa: a91a add r1, sp, #104 ; 0x68 + sh_buf_tmp += corner_size * (a.y2 - ca.y2); + a5fc: 441e add r6, r3 + lv_area_copy(&fa, &ca); + a5fe: a81e add r0, sp, #120 ; 0x78 + a600: 4b07 ldr r3, [pc, #28] ; (a620 ) + a602: 4798 blx r3 + fa.y1 = fa.y2; + a604: f8bd 307e ldrh.w r3, [sp, #126] ; 0x7e + a608: f8ad 307a strh.w r3, [sp, #122] ; 0x7a + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + a60c: b22d sxth r5, r5 + for(y = 0; y < h; y++) { + a60e: 2700 movs r7, #0 + a610: 9b09 ldr r3, [sp, #36] ; 0x24 + a612: 429f cmp r7, r3 + a614: f2c0 8542 blt.w b09c + a618: e004 b.n a624 + a61a: bf00 nop + a61c: 0000de8d .word 0x0000de8d + a620: 00009b8d .word 0x00009b8d + a.x1 = sh_area.x1 + corner_size; + a624: 9a05 ldr r2, [sp, #20] + a626: f8bd 3048 ldrh.w r3, [sp, #72] ; 0x48 + a62a: 4413 add r3, r2 + a62c: f8ad 3060 strh.w r3, [sp, #96] ; 0x60 + a.x2 = sh_area.x2 - corner_size; + a630: f8bd 304c ldrh.w r3, [sp, #76] ; 0x4c + a634: 1a9b subs r3, r3, r2 + a636: f8ad 3064 strh.w r3, [sp, #100] ; 0x64 + a.y1 = sh_area.y1 + corner_size; + a63a: f8bd 304a ldrh.w r3, [sp, #74] ; 0x4a + a63e: 4413 add r3, r2 + a640: f8ad 3062 strh.w r3, [sp, #98] ; 0x62 + a.y2 = sh_area.y2 - corner_size; + a644: f8bd 304e ldrh.w r3, [sp, #78] ; 0x4e + a648: 1a9b subs r3, r3, r2 + a64a: f8ad 3066 strh.w r3, [sp, #102] ; 0x66 + has_com = _lv_area_intersect(&ca, &a, clip); + a64e: 4642 mov r2, r8 + a650: 4bb9 ldr r3, [pc, #740] ; (a938 ) + a652: a918 add r1, sp, #96 ; 0x60 + a654: a81a add r0, sp, #104 ; 0x68 + a656: 4798 blx r3 + if(has_com && simple_mode == false) { + a658: b1e8 cbz r0, a696 + a65a: 9b07 ldr r3, [sp, #28] + a65c: b9db cbnz r3, a696 + a65e: f8bd 606c ldrh.w r6, [sp, #108] ; 0x6c + a662: f8bd 3068 ldrh.w r3, [sp, #104] ; 0x68 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + a666: f8bd 706e ldrh.w r7, [sp, #110] ; 0x6e + _lv_memset(mask_buf, dsc->shadow_opa, w); + a66a: f8df 9310 ldr.w r9, [pc, #784] ; a97c + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + a66e: 3601 adds r6, #1 + a670: 1af6 subs r6, r6, r3 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + a672: f8bd 306a ldrh.w r3, [sp, #106] ; 0x6a + a676: 3701 adds r7, #1 + a678: 1aff subs r7, r7, r3 + lv_area_copy(&fa, &ca); + a67a: a91a add r1, sp, #104 ; 0x68 + a67c: 4baf ldr r3, [pc, #700] ; (a93c ) + a67e: a81e add r0, sp, #120 ; 0x78 + a680: 4798 blx r3 + fa.y2 = fa.y1; + a682: f9bd 307a ldrsh.w r3, [sp, #122] ; 0x7a + for(y = 0; y < h; y++) { + a686: 9d07 ldr r5, [sp, #28] + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + a688: b236 sxth r6, r6 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + a68a: b23f sxth r7, r7 + a68c: 42bd cmp r5, r7 + fa.y2 = fa.y1; + a68e: f8ad 307e strh.w r3, [sp, #126] ; 0x7e + for(y = 0; y < h; y++) { + a692: f2c0 853c blt.w b10e + lv_draw_mask_remove_id(mask_rout_id); + a696: 4baa ldr r3, [pc, #680] ; (a940 ) + _lv_mem_buf_release(mask_buf); + a698: 4caa ldr r4, [pc, #680] ; (a944 ) + lv_draw_mask_remove_id(mask_rout_id); + a69a: ee18 0a90 vmov r0, s17 + a69e: 4798 blx r3 + _lv_mem_buf_release(mask_buf); + a6a0: ee18 0a10 vmov r0, s16 + a6a4: 47a0 blx r4 + _lv_mem_buf_release(sh_buf); + a6a6: 9806 ldr r0, [sp, #24] + a6a8: 47a0 blx r4 + if(dsc->bg_opa <= LV_OPA_MIN) return; + a6aa: f89a 300c ldrb.w r3, [sl, #12] + a6ae: 2b05 cmp r3, #5 + a6b0: f240 80a8 bls.w a804 + lv_area_copy(&coords_bg, coords); + a6b4: 4ba1 ldr r3, [pc, #644] ; (a93c ) + a6b6: 4659 mov r1, fp + a6b8: a816 add r0, sp, #88 ; 0x58 + a6ba: 4798 blx r3 + if(dsc->border_width > 1 && dsc->border_opa >= LV_OPA_MAX && dsc->radius != 0) { + a6bc: f9ba 3010 ldrsh.w r3, [sl, #16] + a6c0: 2b01 cmp r3, #1 + a6c2: dd24 ble.n a70e + a6c4: f89a 3014 ldrb.w r3, [sl, #20] + a6c8: 2bf9 cmp r3, #249 ; 0xf9 + a6ca: d920 bls.n a70e + a6cc: f9ba 3000 ldrsh.w r3, [sl] + a6d0: b1eb cbz r3, a70e + coords_bg.x1 += (dsc->border_side & LV_BORDER_SIDE_LEFT) ? 1 : 0; + a6d2: f8ba 3012 ldrh.w r3, [sl, #18] + a6d6: f8bd 1058 ldrh.w r1, [sp, #88] ; 0x58 + a6da: f3c3 0280 ubfx r2, r3, #2, #1 + a6de: 440a add r2, r1 + coords_bg.y1 += (dsc->border_side & LV_BORDER_SIDE_TOP) ? 1 : 0; + a6e0: f8bd 105a ldrh.w r1, [sp, #90] ; 0x5a + coords_bg.x1 += (dsc->border_side & LV_BORDER_SIDE_LEFT) ? 1 : 0; + a6e4: f8ad 2058 strh.w r2, [sp, #88] ; 0x58 + coords_bg.y1 += (dsc->border_side & LV_BORDER_SIDE_TOP) ? 1 : 0; + a6e8: f3c3 0240 ubfx r2, r3, #1, #1 + a6ec: 440a add r2, r1 + a6ee: f8ad 205a strh.w r2, [sp, #90] ; 0x5a + coords_bg.x2 -= (dsc->border_side & LV_BORDER_SIDE_RIGHT) ? 1 : 0; + a6f2: f8bd 205c ldrh.w r2, [sp, #92] ; 0x5c + a6f6: f3c3 01c0 ubfx r1, r3, #3, #1 + a6fa: 1a52 subs r2, r2, r1 + a6fc: f8ad 205c strh.w r2, [sp, #92] ; 0x5c + coords_bg.y2 -= (dsc->border_side & LV_BORDER_SIDE_BOTTOM) ? 1 : 0; + a700: f8bd 205e ldrh.w r2, [sp, #94] ; 0x5e + a704: f003 0301 and.w r3, r3, #1 + a708: 1ad3 subs r3, r2, r3 + a70a: f8ad 305e strh.w r3, [sp, #94] ; 0x5e + lv_opa_t opa = dsc->bg_opa; + a70e: f89a 900c ldrb.w r9, [sl, #12] + lv_disp_t * disp = _lv_refr_get_disp_refreshing(); + a712: 4b8d ldr r3, [pc, #564] ; (a948 ) + if(opa > LV_OPA_MAX) opa = LV_OPA_COVER; + a714: f1b9 0ffb cmp.w r9, #251 ; 0xfb + a718: bf28 it cs + a71a: f04f 09ff movcs.w r9, #255 ; 0xff + lv_disp_t * disp = _lv_refr_get_disp_refreshing(); + a71e: 4798 blx r3 + lv_disp_buf_t * vdb = lv_disp_get_buf(disp); + a720: 4b8a ldr r3, [pc, #552] ; (a94c ) + a722: 4798 blx r3 + is_common = _lv_area_intersect(&draw_area, &coords_bg, clip); + a724: 4b84 ldr r3, [pc, #528] ; (a938 ) + lv_disp_buf_t * vdb = lv_disp_get_buf(disp); + a726: 9005 str r0, [sp, #20] + is_common = _lv_area_intersect(&draw_area, &coords_bg, clip); + a728: 4642 mov r2, r8 + a72a: a916 add r1, sp, #88 ; 0x58 + a72c: a818 add r0, sp, #96 ; 0x60 + a72e: 4798 blx r3 + if(is_common == false) return; + a730: 2800 cmp r0, #0 + a732: d067 beq.n a804 + draw_area.x1 -= disp_area->x1; + a734: 9b05 ldr r3, [sp, #20] + a736: f8bd 1060 ldrh.w r1, [sp, #96] ; 0x60 + a73a: 8a1a ldrh r2, [r3, #16] + a73c: 1a8b subs r3, r1, r2 + a73e: f8ad 3060 strh.w r3, [sp, #96] ; 0x60 + draw_area.y1 -= disp_area->y1; + a742: 9b05 ldr r3, [sp, #20] + a744: 8a58 ldrh r0, [r3, #18] + a746: f8bd 3062 ldrh.w r3, [sp, #98] ; 0x62 + a74a: 1a1b subs r3, r3, r0 + a74c: f8ad 3062 strh.w r3, [sp, #98] ; 0x62 + draw_area.x2 -= disp_area->x1; + a750: f8bd 3064 ldrh.w r3, [sp, #100] ; 0x64 + a754: 1a9a subs r2, r3, r2 + a756: f8ad 2064 strh.w r2, [sp, #100] ; 0x64 + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + a75a: 3301 adds r3, #1 + draw_area.y2 -= disp_area->y1; + a75c: f8bd 2066 ldrh.w r2, [sp, #102] ; 0x66 + a760: 1a5b subs r3, r3, r1 + a762: 1a12 subs r2, r2, r0 + a764: b21b sxth r3, r3 + a766: f8ad 2066 strh.w r2, [sp, #102] ; 0x66 + lv_opa_t * mask_buf = _lv_mem_buf_get(draw_area_w); + a76a: 4618 mov r0, r3 + a76c: ee08 3a90 vmov s17, r3 + a770: 4b77 ldr r3, [pc, #476] ; (a950 ) + a772: 4798 blx r3 + uint16_t other_mask_cnt = lv_draw_mask_get_cnt(); + a774: 4b77 ldr r3, [pc, #476] ; (a954 ) + lv_opa_t * mask_buf = _lv_mem_buf_get(draw_area_w); + a776: 4605 mov r5, r0 + uint16_t other_mask_cnt = lv_draw_mask_get_cnt(); + a778: 4798 blx r3 + a77a: 900c str r0, [sp, #48] ; 0x30 + a77c: f8bd 3030 ldrh.w r3, [sp, #48] ; 0x30 + a780: 930d str r3, [sp, #52] ; 0x34 + if(other_mask_cnt) simple_mode = false; + a782: 2b00 cmp r3, #0 + a784: f040 84ef bne.w b166 + else if(dsc->bg_grad_dir == LV_GRAD_DIR_HOR) simple_mode = false; + a788: f89a 3006 ldrb.w r3, [sl, #6] + a78c: 3b02 subs r3, #2 + a78e: bf18 it ne + a790: 2301 movne r3, #1 + a792: f8bd 605c ldrh.w r6, [sp, #92] ; 0x5c + if(other_mask_cnt) simple_mode = false; + a796: 9308 str r3, [sp, #32] + a798: f8bd 3058 ldrh.w r3, [sp, #88] ; 0x58 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + a79c: f8bd 405e ldrh.w r4, [sp, #94] ; 0x5e + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + a7a0: 3601 adds r6, #1 + a7a2: 1af6 subs r6, r6, r3 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + a7a4: f8bd 305a ldrh.w r3, [sp, #90] ; 0x5a + a7a8: 3401 adds r4, #1 + a7aa: 1ae4 subs r4, r4, r3 + int32_t coords_h = lv_area_get_height(&coords_bg); + a7ac: b224 sxth r4, r4 + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + a7ae: b236 sxth r6, r6 + int32_t short_side = LV_MATH_MIN(coords_w, coords_h); + a7b0: 42b4 cmp r4, r6 + int32_t rout = dsc->radius; + a7b2: f9ba 3000 ldrsh.w r3, [sl] + int32_t short_side = LV_MATH_MIN(coords_w, coords_h); + a7b6: bfa8 it ge + a7b8: 4634 movge r4, r6 + if(rout > short_side >> 1) rout = short_side >> 1; + a7ba: 1064 asrs r4, r4, #1 + a7bc: 429c cmp r4, r3 + a7be: bfa8 it ge + a7c0: 461c movge r4, r3 + if(simple_mode && rout == 0 && (dsc->bg_grad_dir == LV_GRAD_DIR_NONE)) { + a7c2: 9b08 ldr r3, [sp, #32] + a7c4: 2b00 cmp r3, #0 + a7c6: f000 84d1 beq.w b16c + a7ca: 2c00 cmp r4, #0 + a7cc: f040 84ce bne.w b16c + a7d0: f89a 3006 ldrb.w r3, [sl, #6] + a7d4: 2b00 cmp r3, #0 + a7d6: f040 857c bne.w b2d2 + _lv_blend_fill(clip, &coords_bg, + a7da: f89a 200d ldrb.w r2, [sl, #13] + a7de: 4c5e ldr r4, [pc, #376] ; (a958 ) + a7e0: e9cd 9201 strd r9, r2, [sp, #4] + a7e4: 2201 movs r2, #1 + a7e6: 9200 str r2, [sp, #0] + a7e8: f8ba 2002 ldrh.w r2, [sl, #2] + a7ec: a916 add r1, sp, #88 ; 0x58 + a7ee: 4640 mov r0, r8 + a7f0: 47a0 blx r4 + int16_t mask_rout_id = LV_MASK_ID_INV; + a7f2: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + a7f6: 930b str r3, [sp, #44] ; 0x2c + lv_draw_mask_remove_id(mask_rout_id); + a7f8: 4b51 ldr r3, [pc, #324] ; (a940 ) + a7fa: 980b ldr r0, [sp, #44] ; 0x2c + a7fc: 4798 blx r3 + _lv_mem_buf_release(mask_buf); + a7fe: 4b51 ldr r3, [pc, #324] ; (a944 ) + a800: 4628 mov r0, r5 + a802: 4798 blx r3 + _lv_mem_buf_release(mask_buf); +} + +static void draw_pattern(const lv_area_t * coords, const lv_area_t * clip, lv_draw_rect_dsc_t * dsc) +{ + if(dsc->pattern_image == NULL) return; + a804: f8da 002c ldr.w r0, [sl, #44] ; 0x2c + a808: b1d0 cbz r0, a840 + if(dsc->pattern_opa <= LV_OPA_MIN) return; + a80a: f89a 3036 ldrb.w r3, [sl, #54] ; 0x36 + a80e: 2b05 cmp r3, #5 + a810: d916 bls.n a840 + + lv_img_src_t src_type = lv_img_src_get_type(dsc->pattern_image); + a812: 4b52 ldr r3, [pc, #328] ; (a95c ) + a814: 4798 blx r3 + lv_draw_img_dsc_t img_dsc; + lv_draw_label_dsc_t label_dsc; + int32_t img_w; + int32_t img_h; + + if(src_type == LV_IMG_SRC_FILE || src_type == LV_IMG_SRC_VARIABLE) { + a816: 2801 cmp r0, #1 + lv_img_src_t src_type = lv_img_src_get_type(dsc->pattern_image); + a818: 4606 mov r6, r0 + if(src_type == LV_IMG_SRC_FILE || src_type == LV_IMG_SRC_VARIABLE) { + a81a: f200 86bc bhi.w b596 + lv_img_header_t header; + lv_res_t res = lv_img_decoder_get_info(dsc->pattern_image, &header); + a81e: f8da 002c ldr.w r0, [sl, #44] ; 0x2c + a822: 4b4f ldr r3, [pc, #316] ; (a960 ) + a824: a925 add r1, sp, #148 ; 0x94 + a826: 4798 blx r3 + if(res != LV_RES_OK) { + a828: 2801 cmp r0, #1 + a82a: f000 8656 beq.w b4da + LV_LOG_WARN("draw_img: can't get image info"); + a82e: 4b4d ldr r3, [pc, #308] ; (a964 ) + a830: 9300 str r3, [sp, #0] + a832: 494d ldr r1, [pc, #308] ; (a968 ) + a834: 4b4d ldr r3, [pc, #308] ; (a96c ) + a836: 4c4e ldr r4, [pc, #312] ; (a970 ) + a838: f240 5294 movw r2, #1428 ; 0x594 + a83c: 2002 movs r0, #2 + a83e: 47a0 blx r4 + if(dsc->border_opa <= LV_OPA_MIN) return; + a840: f89a 3014 ldrb.w r3, [sl, #20] + a844: 9305 str r3, [sp, #20] + a846: 2b05 cmp r3, #5 + a848: f240 8174 bls.w ab34 + if(dsc->border_width == 0) return; + a84c: f9ba 3010 ldrsh.w r3, [sl, #16] + a850: 2b00 cmp r3, #0 + a852: f000 816f beq.w ab34 + if(dsc->border_side == LV_BORDER_SIDE_NONE) return; + a856: f9ba 3012 ldrsh.w r3, [sl, #18] + a85a: 2b00 cmp r3, #0 + a85c: f000 816a beq.w ab34 + if(opa > LV_OPA_MAX) opa = LV_OPA_COVER; + a860: 9b05 ldr r3, [sp, #20] + a862: 2bfb cmp r3, #251 ; 0xfb + a864: bf28 it cs + a866: 23ff movcs r3, #255 ; 0xff + a868: 9305 str r3, [sp, #20] + lv_disp_t * disp = _lv_refr_get_disp_refreshing(); + a86a: 4b37 ldr r3, [pc, #220] ; (a948 ) + a86c: 4798 blx r3 + lv_disp_buf_t * vdb = lv_disp_get_buf(disp); + a86e: 4b37 ldr r3, [pc, #220] ; (a94c ) + a870: 4798 blx r3 + is_common = _lv_area_intersect(&draw_area, coords, clip); + a872: 4b31 ldr r3, [pc, #196] ; (a938 ) + lv_disp_buf_t * vdb = lv_disp_get_buf(disp); + a874: 9006 str r0, [sp, #24] + is_common = _lv_area_intersect(&draw_area, coords, clip); + a876: 4642 mov r2, r8 + a878: 4659 mov r1, fp + a87a: a814 add r0, sp, #80 ; 0x50 + a87c: 4798 blx r3 + if(is_common == false) return; + a87e: 2800 cmp r0, #0 + a880: f000 8158 beq.w ab34 + draw_area.x1 -= disp_area->x1; + a884: 9b06 ldr r3, [sp, #24] + a886: f8bd 1050 ldrh.w r1, [sp, #80] ; 0x50 + a88a: 8a1a ldrh r2, [r3, #16] + a88c: 1a8b subs r3, r1, r2 + a88e: f8ad 3050 strh.w r3, [sp, #80] ; 0x50 + draw_area.y1 -= disp_area->y1; + a892: 9b06 ldr r3, [sp, #24] + a894: 8a58 ldrh r0, [r3, #18] + a896: f8bd 3052 ldrh.w r3, [sp, #82] ; 0x52 + a89a: 1a1b subs r3, r3, r0 + a89c: f8ad 3052 strh.w r3, [sp, #82] ; 0x52 + draw_area.x2 -= disp_area->x1; + a8a0: f8bd 3054 ldrh.w r3, [sp, #84] ; 0x54 + a8a4: 1a9a subs r2, r3, r2 + a8a6: f8ad 2054 strh.w r2, [sp, #84] ; 0x54 + a8aa: 3301 adds r3, #1 + draw_area.y2 -= disp_area->y1; + a8ac: f8bd 2056 ldrh.w r2, [sp, #86] ; 0x56 + a8b0: 1a5b subs r3, r3, r1 + a8b2: 1a12 subs r2, r2, r0 + a8b4: fa0f f983 sxth.w r9, r3 + a8b8: f8ad 2056 strh.w r2, [sp, #86] ; 0x56 + lv_opa_t * mask_buf = _lv_mem_buf_get(draw_area_w); + a8bc: 4b24 ldr r3, [pc, #144] ; (a950 ) + a8be: 4648 mov r0, r9 + a8c0: 4798 blx r3 + uint8_t other_mask_cnt = lv_draw_mask_get_cnt(); + a8c2: 4b24 ldr r3, [pc, #144] ; (a954 ) + lv_opa_t * mask_buf = _lv_mem_buf_get(draw_area_w); + a8c4: 4604 mov r4, r0 + uint8_t other_mask_cnt = lv_draw_mask_get_cnt(); + a8c6: 4798 blx r3 + if(other_mask_cnt) simple_mode = false; + a8c8: 2800 cmp r0, #0 + a8ca: f040 8749 bne.w b760 + else if(dsc->border_side != LV_BORDER_SIDE_FULL) simple_mode = false; + a8ce: f9ba 3012 ldrsh.w r3, [sl, #18] + a8d2: f1a3 050f sub.w r5, r3, #15 + a8d6: 426b negs r3, r5 + a8d8: 416b adcs r3, r5 + if(other_mask_cnt) simple_mode = false; + a8da: 461f mov r7, r3 + a8dc: f8bb 3004 ldrh.w r3, [fp, #4] + a8e0: f8bb 2000 ldrh.w r2, [fp] + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + a8e4: f8bb 1002 ldrh.w r1, [fp, #2] + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + a8e8: 3301 adds r3, #1 + a8ea: 1a9b subs r3, r3, r2 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + a8ec: f8bb 2006 ldrh.w r2, [fp, #6] + a8f0: 3201 adds r2, #1 + a8f2: 1a52 subs r2, r2, r1 + int32_t coords_w = lv_area_get_width(coords); + a8f4: b21b sxth r3, r3 + int32_t coords_h = lv_area_get_height(coords); + a8f6: b212 sxth r2, r2 + int32_t short_side = LV_MATH_MIN(coords_w, coords_h); + a8f8: 4293 cmp r3, r2 + a8fa: bfa8 it ge + a8fc: 4613 movge r3, r2 + int32_t rout = dsc->radius; + a8fe: f9ba 2000 ldrsh.w r2, [sl] + if(rout > short_side >> 1) rout = short_side >> 1; + a902: 105b asrs r3, r3, #1 + a904: 4293 cmp r3, r2 + a906: bfa8 it ge + a908: 4613 movge r3, r2 + if(rout > 0) { + a90a: 2b00 cmp r3, #0 + a90c: 9309 str r3, [sp, #36] ; 0x24 + a90e: f340 872a ble.w b766 + lv_draw_mask_radius_init(&mask_rout_param, coords, rout, false); + a912: 9a09 ldr r2, [sp, #36] ; 0x24 + a914: 4d17 ldr r5, [pc, #92] ; (a974 ) + a916: 2300 movs r3, #0 + a918: 4659 mov r1, fp + a91a: a81e add r0, sp, #120 ; 0x78 + a91c: 47a8 blx r5 + mask_rout_id = lv_draw_mask_add(&mask_rout_param, NULL); + a91e: 4b16 ldr r3, [pc, #88] ; (a978 ) + a920: 2100 movs r1, #0 + a922: a81e add r0, sp, #120 ; 0x78 + a924: 4798 blx r3 + a926: 900c str r0, [sp, #48] ; 0x30 + lv_area_copy(&area_small, coords); + a928: a816 add r0, sp, #88 ; 0x58 + a92a: 4b04 ldr r3, [pc, #16] ; (a93c ) + a92c: 4659 mov r1, fp + a92e: 4798 blx r3 + area_small.x1 += ((dsc->border_side & LV_BORDER_SIDE_LEFT) ? dsc->border_width : - (dsc->border_width + rout)); + a930: f8ba 1012 ldrh.w r1, [sl, #18] + a934: e024 b.n a980 + a936: bf00 nop + a938: 0000de8d .word 0x0000de8d + a93c: 00009b8d .word 0x00009b8d + a940: 000097a1 .word 0x000097a1 + a944: 0000eb69 .word 0x0000eb69 + a948: 00004fe9 .word 0x00004fe9 + a94c: 0000d9e1 .word 0x0000d9e1 + a950: 0000eeb5 .word 0x0000eeb5 + a954: 000097f1 .word 0x000097f1 + a958: 000061f1 .word 0x000061f1 + a95c: 00007805 .word 0x00007805 + a960: 0000cf29 .word 0x0000cf29 + a964: 0001fda4 .word 0x0001fda4 + a968: 0001fd6f .word 0x0001fd6f + a96c: 0001fdf2 .word 0x0001fdf2 + a970: 0000e8e9 .word 0x0000e8e9 + a974: 00009915 .word 0x00009915 + a978: 00009711 .word 0x00009711 + a97c: 0000efb9 .word 0x0000efb9 + a980: f8bd 5024 ldrh.w r5, [sp, #36] ; 0x24 + a984: f8ba 3010 ldrh.w r3, [sl, #16] + a988: f8bd 2058 ldrh.w r2, [sp, #88] ; 0x58 + a98c: 0748 lsls r0, r1, #29 + a98e: bf5e ittt pl + a990: 195b addpl r3, r3, r5 + a992: 425b negpl r3, r3 + a994: b29b uxthpl r3, r3 + a996: 4413 add r3, r2 + a998: f8ba 2010 ldrh.w r2, [sl, #16] + a99c: f8ad 3058 strh.w r3, [sp, #88] ; 0x58 + area_small.x2 -= ((dsc->border_side & LV_BORDER_SIDE_RIGHT) ? dsc->border_width : - (dsc->border_width + rout)); + a9a0: 070b lsls r3, r1, #28 + a9a2: bf58 it pl + a9a4: 1953 addpl r3, r2, r5 + a9a6: f8bd 005c ldrh.w r0, [sp, #92] ; 0x5c + a9aa: bf56 itet pl + a9ac: 425b negpl r3, r3 + a9ae: 4613 movmi r3, r2 + a9b0: b29b uxthpl r3, r3 + a9b2: 1ac3 subs r3, r0, r3 + area_small.y1 += ((dsc->border_side & LV_BORDER_SIDE_TOP) ? dsc->border_width : - (dsc->border_width + rout)); + a9b4: 078e lsls r6, r1, #30 + area_small.x2 -= ((dsc->border_side & LV_BORDER_SIDE_RIGHT) ? dsc->border_width : - (dsc->border_width + rout)); + a9b6: f8ad 305c strh.w r3, [sp, #92] ; 0x5c + area_small.y1 += ((dsc->border_side & LV_BORDER_SIDE_TOP) ? dsc->border_width : - (dsc->border_width + rout)); + a9ba: bf58 it pl + a9bc: 1953 addpl r3, r2, r5 + a9be: f8bd 005a ldrh.w r0, [sp, #90] ; 0x5a + lv_draw_mask_radius_init(&mask_rin_param, &area_small, rout - dsc->border_width, true); + a9c2: 4ec3 ldr r6, [pc, #780] ; (acd0 ) + area_small.y1 += ((dsc->border_side & LV_BORDER_SIDE_TOP) ? dsc->border_width : - (dsc->border_width + rout)); + a9c4: bf56 itet pl + a9c6: 425b negpl r3, r3 + a9c8: 4613 movmi r3, r2 + a9ca: b29b uxthpl r3, r3 + a9cc: 4403 add r3, r0 + a9ce: f8ad 305a strh.w r3, [sp, #90] ; 0x5a + area_small.y2 -= ((dsc->border_side & LV_BORDER_SIDE_BOTTOM) ? dsc->border_width : - (dsc->border_width + rout)); + a9d2: 07cb lsls r3, r1, #31 + a9d4: bf5c itt pl + a9d6: 1953 addpl r3, r2, r5 + a9d8: 425b negpl r3, r3 + a9da: f8bd 005e ldrh.w r0, [sp, #94] ; 0x5e + a9de: bf4c ite mi + a9e0: 4613 movmi r3, r2 + a9e2: b29b uxthpl r3, r3 + a9e4: 1ac3 subs r3, r0, r3 + lv_draw_mask_radius_init(&mask_rin_param, &area_small, rout - dsc->border_width, true); + a9e6: 1aaa subs r2, r5, r2 + a9e8: b212 sxth r2, r2 + area_small.y2 -= ((dsc->border_side & LV_BORDER_SIDE_BOTTOM) ? dsc->border_width : - (dsc->border_width + rout)); + a9ea: f8ad 305e strh.w r3, [sp, #94] ; 0x5e + lv_draw_mask_radius_init(&mask_rin_param, &area_small, rout - dsc->border_width, true); + a9ee: a916 add r1, sp, #88 ; 0x58 + a9f0: 2301 movs r3, #1 + a9f2: a825 add r0, sp, #148 ; 0x94 + a9f4: 47b0 blx r6 + int16_t mask_rin_id = lv_draw_mask_add(&mask_rin_param, NULL); + a9f6: 4bb7 ldr r3, [pc, #732] ; (acd4 ) + a9f8: 2100 movs r1, #0 + a9fa: a825 add r0, sp, #148 ; 0x94 + a9fc: 4798 blx r3 + int32_t corner_size = LV_MATH_MAX(rout, dsc->border_width - 1); + a9fe: f9ba 3010 ldrsh.w r3, [sl, #16] + aa02: 9a09 ldr r2, [sp, #36] ; 0x24 + fill_area.y1 = disp_area->y1 + draw_area.y1; + aa04: f9bd 6052 ldrsh.w r6, [sp, #82] ; 0x52 + upper_corner_end = LV_MATH_MIN(upper_corner_end, draw_area.y2); + aa08: f9bd c056 ldrsh.w ip, [sp, #86] ; 0x56 + fill_area.x1 = coords->x1; + aa0c: f9bb 1000 ldrsh.w r1, [fp] + int32_t corner_size = LV_MATH_MAX(rout, dsc->border_width - 1); + aa10: 429a cmp r2, r3 + aa12: bfa8 it ge + aa14: 9b09 ldrge r3, [sp, #36] ; 0x24 + fill_area.x2 = coords->x2; + aa16: f9bb 2004 ldrsh.w r2, [fp, #4] + int32_t corner_size = LV_MATH_MAX(rout, dsc->border_width - 1); + aa1a: bfb8 it lt + aa1c: f103 33ff addlt.w r3, r3, #4294967295 ; 0xffffffff + aa20: 9308 str r3, [sp, #32] + lv_color_t color = dsc->border_color; + aa22: f8ba 300e ldrh.w r3, [sl, #14] + aa26: ee08 3a10 vmov s16, r3 + lv_blend_mode_t blend_mode = dsc->border_blend_mode; + aa2a: f89a 3015 ldrb.w r3, [sl, #21] + aa2e: 9307 str r3, [sp, #28] + int32_t upper_corner_end = coords->y1 - disp_area->y1 + corner_size; + aa30: 9b06 ldr r3, [sp, #24] + aa32: f9b3 e012 ldrsh.w lr, [r3, #18] + fill_area.y1 = disp_area->y1 + draw_area.y1; + aa36: eb0e 0306 add.w r3, lr, r6 + int16_t mask_rin_id = lv_draw_mask_add(&mask_rin_param, NULL); + aa3a: ee08 0a90 vmov s17, r0 + fill_area.y1 = disp_area->y1 + draw_area.y1; + aa3e: b21b sxth r3, r3 + if(simple_mode) { + aa40: 2f00 cmp r7, #0 + aa42: f000 879d beq.w b980 + int32_t upper_corner_end = coords->y1 - disp_area->y1 + corner_size; + aa46: f9bb 0002 ldrsh.w r0, [fp, #2] + aa4a: 9f08 ldr r7, [sp, #32] + fill_area.x1 = coords->x1; + aa4c: f8ad 1060 strh.w r1, [sp, #96] ; 0x60 + int32_t upper_corner_end = coords->y1 - disp_area->y1 + corner_size; + aa50: eba0 000e sub.w r0, r0, lr + aa54: 4438 add r0, r7 + upper_corner_end = LV_MATH_MIN(upper_corner_end, draw_area.y2); + aa56: 4584 cmp ip, r0 + aa58: bfa8 it ge + aa5a: 4684 movge ip, r0 + aa5c: f8cd c028 str.w ip, [sp, #40] ; 0x28 + fill_area.x2 = coords->x2; + aa60: f8ad 2064 strh.w r2, [sp, #100] ; 0x64 + fill_area.y1 = disp_area->y1 + draw_area.y1; + aa64: f8ad 3062 strh.w r3, [sp, #98] ; 0x62 + fill_area.y2 = fill_area.y1; + aa68: f8ad 3066 strh.w r3, [sp, #102] ; 0x66 + for(h = draw_area.y1; h <= upper_corner_end; h++) { + aa6c: 9b0a ldr r3, [sp, #40] ; 0x28 + aa6e: 42b3 cmp r3, r6 + aa70: f280 867e bge.w b770 + int32_t lower_corner_end = coords->y2 - disp_area->y1 - corner_size; + aa74: 9b06 ldr r3, [sp, #24] + aa76: f9bb 2006 ldrsh.w r2, [fp, #6] + aa7a: f9b3 3012 ldrsh.w r3, [r3, #18] + aa7e: 9908 ldr r1, [sp, #32] + lower_corner_end = LV_MATH_MAX(lower_corner_end, draw_area.y1); + aa80: f9bd 6052 ldrsh.w r6, [sp, #82] ; 0x52 + int32_t lower_corner_end = coords->y2 - disp_area->y1 - corner_size; + aa84: 1ad2 subs r2, r2, r3 + aa86: 1a52 subs r2, r2, r1 + lower_corner_end = LV_MATH_MAX(lower_corner_end, draw_area.y1); + aa88: 4296 cmp r6, r2 + aa8a: bfb8 it lt + aa8c: 4616 movlt r6, r2 + if(lower_corner_end <= upper_corner_end) lower_corner_end = upper_corner_end + 1; + aa8e: 9a0a ldr r2, [sp, #40] ; 0x28 + aa90: 42b2 cmp r2, r6 + aa92: bfa4 itt ge + aa94: 4616 movge r6, r2 + aa96: 3601 addge r6, #1 + fill_area.y1 = disp_area->y1 + lower_corner_end; + aa98: 4433 add r3, r6 + aa9a: b21b sxth r3, r3 + aa9c: f8ad 3062 strh.w r3, [sp, #98] ; 0x62 + fill_area.y2 = fill_area.y1; + aaa0: f8ad 3066 strh.w r3, [sp, #102] ; 0x66 + for(h = lower_corner_end; h <= draw_area.y2; h++) { + aaa4: f9bd 3056 ldrsh.w r3, [sp, #86] ; 0x56 + aaa8: 429e cmp r6, r3 + aaaa: f340 86dd ble.w b868 + fill_area.y1 = coords->y1 + corner_size + 1; + aaae: f8bb 3002 ldrh.w r3, [fp, #2] + aab2: 9a08 ldr r2, [sp, #32] + _lv_blend_fill(clip, &fill_area, color, NULL, LV_DRAW_MASK_RES_FULL_COVER, opa, blend_mode); + aab4: 4d88 ldr r5, [pc, #544] ; (acd8 ) + fill_area.y1 = coords->y1 + corner_size + 1; + aab6: 3301 adds r3, #1 + aab8: fa13 f382 uxtah r3, r3, r2 + aabc: f8ad 3062 strh.w r3, [sp, #98] ; 0x62 + fill_area.y2 = coords->y2 - corner_size - 1; + aac0: f8bb 3006 ldrh.w r3, [fp, #6] + aac4: 3b01 subs r3, #1 + aac6: 1a9b subs r3, r3, r2 + fill_area.x2 = coords->x1 + dsc->border_width - 1; + aac8: f8ba 2010 ldrh.w r2, [sl, #16] + fill_area.y2 = coords->y2 - corner_size - 1; + aacc: f8ad 3066 strh.w r3, [sp, #102] ; 0x66 + fill_area.x1 = coords->x1; + aad0: f9bb 3000 ldrsh.w r3, [fp] + aad4: f8ad 3060 strh.w r3, [sp, #96] ; 0x60 + fill_area.x2 = coords->x1 + dsc->border_width - 1; + aad8: 3a01 subs r2, #1 + aada: 4413 add r3, r2 + aadc: f8ad 3064 strh.w r3, [sp, #100] ; 0x64 + _lv_blend_fill(clip, &fill_area, color, NULL, LV_DRAW_MASK_RES_FULL_COVER, opa, blend_mode); + aae0: 9b07 ldr r3, [sp, #28] + aae2: 9302 str r3, [sp, #8] + aae4: 2601 movs r6, #1 + aae6: 9b05 ldr r3, [sp, #20] + aae8: 9301 str r3, [sp, #4] + aaea: ee18 2a10 vmov r2, s16 + aaee: 2300 movs r3, #0 + aaf0: a918 add r1, sp, #96 ; 0x60 + aaf2: 4640 mov r0, r8 + aaf4: 9600 str r6, [sp, #0] + aaf6: 47a8 blx r5 + fill_area.x1 = coords->x2 - dsc->border_width + 1; + aaf8: f8ba 3010 ldrh.w r3, [sl, #16] + aafc: f9bb 2004 ldrsh.w r2, [fp, #4] + fill_area.x2 = coords->x2; + ab00: f8ad 2064 strh.w r2, [sp, #100] ; 0x64 + fill_area.x1 = coords->x2 - dsc->border_width + 1; + ab04: 1af3 subs r3, r6, r3 + ab06: 4413 add r3, r2 + ab08: f8ad 3060 strh.w r3, [sp, #96] ; 0x60 + _lv_blend_fill(clip, &fill_area, color, NULL, LV_DRAW_MASK_RES_FULL_COVER, opa, blend_mode); + ab0c: 9b07 ldr r3, [sp, #28] + ab0e: 9302 str r3, [sp, #8] + ab10: 9b05 ldr r3, [sp, #20] + ab12: ee18 2a10 vmov r2, s16 + ab16: e9cd 6300 strd r6, r3, [sp] + ab1a: a918 add r1, sp, #96 ; 0x60 + ab1c: 2300 movs r3, #0 + ab1e: 4640 mov r0, r8 + ab20: 47a8 blx r5 + lv_draw_mask_remove_id(mask_rin_id); + ab22: 4d6e ldr r5, [pc, #440] ; (acdc ) + ab24: ee18 0a90 vmov r0, s17 + ab28: 47a8 blx r5 + lv_draw_mask_remove_id(mask_rout_id); + ab2a: 980c ldr r0, [sp, #48] ; 0x30 + ab2c: 47a8 blx r5 + _lv_mem_buf_release(mask_buf); + ab2e: 4b6c ldr r3, [pc, #432] ; (ace0 ) + ab30: 4620 mov r0, r4 + ab32: 4798 blx r3 +} + + +static void draw_value(const lv_area_t * coords, const lv_area_t * clip, lv_draw_rect_dsc_t * dsc) +{ + if(dsc->value_str == NULL) return; + ab34: f8da 103c ldr.w r1, [sl, #60] ; 0x3c + ab38: 2900 cmp r1, #0 + ab3a: d064 beq.n ac06 + if(dsc->value_opa <= LV_OPA_MIN) return; + ab3c: f89a 3044 ldrb.w r3, [sl, #68] ; 0x44 + ab40: 2b05 cmp r3, #5 + ab42: d960 bls.n ac06 + + lv_point_t s; + _lv_txt_get_size(&s, dsc->value_str, dsc->value_font, dsc->value_letter_space, dsc->value_line_space, LV_COORD_MAX, + ab44: 2400 movs r4, #0 + ab46: f647 4318 movw r3, #31768 ; 0x7c18 + ab4a: e9cd 3401 strd r3, r4, [sp, #4] + ab4e: f9ba 304e ldrsh.w r3, [sl, #78] ; 0x4e + ab52: 9300 str r3, [sp, #0] + ab54: f9ba 304c ldrsh.w r3, [sl, #76] ; 0x4c + ab58: f8da 2040 ldr.w r2, [sl, #64] ; 0x40 + ab5c: 4d61 ldr r5, [pc, #388] ; (ace4 ) + ab5e: a818 add r0, sp, #96 ; 0x60 + ab60: 47a8 blx r5 + LV_TXT_FLAG_NONE); + + lv_area_t value_area; + value_area.x1 = 0; + value_area.y1 = 0; + value_area.x2 = s.x - 1; + ab62: f8bd 3060 ldrh.w r3, [sp, #96] ; 0x60 + value_area.y2 = s.y - 1; + + lv_point_t p_align; + _lv_area_align(coords, &value_area, dsc->value_align, &p_align); + ab66: f89a 2050 ldrb.w r2, [sl, #80] ; 0x50 + value_area.x1 = 0; + ab6a: 941e str r4, [sp, #120] ; 0x78 + value_area.x2 = s.x - 1; + ab6c: 3b01 subs r3, #1 + ab6e: f8ad 307c strh.w r3, [sp, #124] ; 0x7c + value_area.y2 = s.y - 1; + ab72: f8bd 3062 ldrh.w r3, [sp, #98] ; 0x62 + _lv_area_align(coords, &value_area, dsc->value_align, &p_align); + ab76: 4d5c ldr r5, [pc, #368] ; (ace8 ) + value_area.y2 = s.y - 1; + ab78: 3b01 subs r3, #1 + ab7a: f8ad 307e strh.w r3, [sp, #126] ; 0x7e + _lv_area_align(coords, &value_area, dsc->value_align, &p_align); + ab7e: a91e add r1, sp, #120 ; 0x78 + ab80: ab1a add r3, sp, #104 ; 0x68 + ab82: 4658 mov r0, fp + ab84: 47a8 blx r5 + + value_area.x1 += p_align.x + dsc->value_ofs_x; + ab86: f8ba 3048 ldrh.w r3, [sl, #72] ; 0x48 + ab8a: f8bd 2068 ldrh.w r2, [sp, #104] ; 0x68 + value_area.y1 += p_align.y + dsc->value_ofs_y; + ab8e: f8ba 104a ldrh.w r1, [sl, #74] ; 0x4a + value_area.x1 += p_align.x + dsc->value_ofs_x; + ab92: 441a add r2, r3 + ab94: f8bd 3078 ldrh.w r3, [sp, #120] ; 0x78 + ab98: fa13 f382 uxtah r3, r3, r2 + ab9c: f8ad 3078 strh.w r3, [sp, #120] ; 0x78 + value_area.y1 += p_align.y + dsc->value_ofs_y; + aba0: f8bd 306a ldrh.w r3, [sp, #106] ; 0x6a + aba4: 440b add r3, r1 + aba6: f8bd 107a ldrh.w r1, [sp, #122] ; 0x7a + abaa: fa11 f183 uxtah r1, r1, r3 + abae: f8ad 107a strh.w r1, [sp, #122] ; 0x7a + value_area.x2 += p_align.x + dsc->value_ofs_x; + abb2: f8bd 107c ldrh.w r1, [sp, #124] ; 0x7c + abb6: fa11 f282 uxtah r2, r1, r2 + abba: f8ad 207c strh.w r2, [sp, #124] ; 0x7c + value_area.y2 += p_align.y + dsc->value_ofs_y; + abbe: f8bd 207e ldrh.w r2, [sp, #126] ; 0x7e + abc2: fa12 f383 uxtah r3, r2, r3 + abc6: f8ad 307e strh.w r3, [sp, #126] ; 0x7e + + lv_draw_label_dsc_t label_dsc; + lv_draw_label_dsc_init(&label_dsc); + abca: a825 add r0, sp, #148 ; 0x94 + abcc: 4b47 ldr r3, [pc, #284] ; (acec ) + abce: 4798 blx r3 + label_dsc.font = dsc->value_font; + abd0: f8da 3040 ldr.w r3, [sl, #64] ; 0x40 + abd4: 9326 str r3, [sp, #152] ; 0x98 + label_dsc.letter_space = dsc->value_letter_space; + abd6: f8ba 304c ldrh.w r3, [sl, #76] ; 0x4c + abda: f8ad 30a0 strh.w r3, [sp, #160] ; 0xa0 + label_dsc.line_space = dsc->value_line_space; + abde: f8ba 304e ldrh.w r3, [sl, #78] ; 0x4e + abe2: f8ad 309e strh.w r3, [sp, #158] ; 0x9e + label_dsc.color = dsc->value_color; + abe6: f8ba 3046 ldrh.w r3, [sl, #70] ; 0x46 + abea: f8ad 3094 strh.w r3, [sp, #148] ; 0x94 + label_dsc.opa = dsc->value_opa; + abee: f89a 3044 ldrb.w r3, [sl, #68] ; 0x44 + + lv_draw_label(&value_area, clip, &label_dsc, dsc->value_str, NULL); + abf2: 9400 str r4, [sp, #0] + label_dsc.opa = dsc->value_opa; + abf4: f88d 309c strb.w r3, [sp, #156] ; 0x9c + lv_draw_label(&value_area, clip, &label_dsc, dsc->value_str, NULL); + abf8: 4c3d ldr r4, [pc, #244] ; (acf0 ) + abfa: f8da 303c ldr.w r3, [sl, #60] ; 0x3c + abfe: aa25 add r2, sp, #148 ; 0x94 + ac00: 4641 mov r1, r8 + ac02: a81e add r0, sp, #120 ; 0x78 + ac04: 47a0 blx r4 + if(dsc->outline_opa <= LV_OPA_MIN) return; + ac06: f89a 301c ldrb.w r3, [sl, #28] + ac0a: 9305 str r3, [sp, #20] + ac0c: 2b05 cmp r3, #5 + ac0e: f240 816b bls.w aee8 + if(dsc->outline_width == 0) return; + ac12: f9ba 3018 ldrsh.w r3, [sl, #24] + ac16: 2b00 cmp r3, #0 + ac18: f000 8166 beq.w aee8 + if(opa > LV_OPA_MAX) opa = LV_OPA_COVER; + ac1c: 9b05 ldr r3, [sp, #20] + lv_area_copy(&area_inner, coords); + ac1e: 4d35 ldr r5, [pc, #212] ; (acf4 ) + if(opa > LV_OPA_MAX) opa = LV_OPA_COVER; + ac20: 2bfb cmp r3, #251 ; 0xfb + ac22: bf28 it cs + ac24: 23ff movcs r3, #255 ; 0xff + ac26: 9305 str r3, [sp, #20] + uint8_t other_mask_cnt = lv_draw_mask_get_cnt(); + ac28: 4b33 ldr r3, [pc, #204] ; (acf8 ) + ac2a: 4798 blx r3 + lv_area_copy(&area_inner, coords); + ac2c: 4659 mov r1, fp + uint8_t other_mask_cnt = lv_draw_mask_get_cnt(); + ac2e: 900b str r0, [sp, #44] ; 0x2c + lv_area_copy(&area_inner, coords); + ac30: a812 add r0, sp, #72 ; 0x48 + ac32: 47a8 blx r5 + area_inner.x1 -= dsc->outline_pad; + ac34: f8ba 701a ldrh.w r7, [sl, #26] + ac38: f8bd 9048 ldrh.w r9, [sp, #72] ; 0x48 + area_inner.x2 += dsc->outline_pad; + ac3c: f8bd 404c ldrh.w r4, [sp, #76] ; 0x4c + area_inner.x1 -= dsc->outline_pad; + ac40: eba9 0307 sub.w r3, r9, r7 + ac44: f8ad 3048 strh.w r3, [sp, #72] ; 0x48 + area_inner.y1 -= dsc->outline_pad; + ac48: f8bd 304a ldrh.w r3, [sp, #74] ; 0x4a + ac4c: 9307 str r3, [sp, #28] + ac4e: 1bdb subs r3, r3, r7 + ac50: f8ad 304a strh.w r3, [sp, #74] ; 0x4a + area_inner.y2 += dsc->outline_pad; + ac54: f8bd 304e ldrh.w r3, [sp, #78] ; 0x4e + ac58: 443b add r3, r7 + ac5a: b29b uxth r3, r3 + area_inner.x2 += dsc->outline_pad; + ac5c: 443c add r4, r7 + area_inner.y2 += dsc->outline_pad; + ac5e: 9308 str r3, [sp, #32] + ac60: f8ad 304e strh.w r3, [sp, #78] ; 0x4e + area_inner.x2 += dsc->outline_pad; + ac64: b2a4 uxth r4, r4 + int32_t rin = dsc->radius; + ac66: f9ba 3000 ldrsh.w r3, [sl] + ac6a: 930c str r3, [sp, #48] ; 0x30 + lv_area_copy(&area_outer, &area_inner); + ac6c: a912 add r1, sp, #72 ; 0x48 + int32_t rout = rin + dsc->outline_width; + ac6e: f9ba 3018 ldrsh.w r3, [sl, #24] + area_inner.x2 += dsc->outline_pad; + ac72: f8ad 404c strh.w r4, [sp, #76] ; 0x4c + lv_area_copy(&area_outer, &area_inner); + ac76: a814 add r0, sp, #80 ; 0x50 + int32_t rout = rin + dsc->outline_width; + ac78: 930d str r3, [sp, #52] ; 0x34 + lv_area_copy(&area_outer, &area_inner); + ac7a: 47a8 blx r5 + area_outer.x1 -= dsc->outline_width; + ac7c: f8ba 6018 ldrh.w r6, [sl, #24] + ac80: f8bd 3050 ldrh.w r3, [sp, #80] ; 0x50 + ac84: 9309 str r3, [sp, #36] ; 0x24 + ac86: 1b9b subs r3, r3, r6 + ac88: f8ad 3050 strh.w r3, [sp, #80] ; 0x50 + area_outer.x2 += dsc->outline_width; + ac8c: f8bd 3054 ldrh.w r3, [sp, #84] ; 0x54 + area_outer.y2 += dsc->outline_width; + ac90: f8bd 5056 ldrh.w r5, [sp, #86] ; 0x56 + area_outer.x2 += dsc->outline_width; + ac94: 4433 add r3, r6 + ac96: fa1f fb83 uxth.w fp, r3 + area_outer.y1 -= dsc->outline_width; + ac9a: f8bd 3052 ldrh.w r3, [sp, #82] ; 0x52 + ac9e: 930a str r3, [sp, #40] ; 0x28 + area_outer.y2 += dsc->outline_width; + aca0: 4435 add r5, r6 + area_outer.y1 -= dsc->outline_width; + aca2: 1b9b subs r3, r3, r6 + area_outer.y2 += dsc->outline_width; + aca4: b2ad uxth r5, r5 + area_outer.y1 -= dsc->outline_width; + aca6: f8ad 3052 strh.w r3, [sp, #82] ; 0x52 + area_outer.x2 += dsc->outline_width; + acaa: f8ad b054 strh.w fp, [sp, #84] ; 0x54 + lv_disp_t * disp = _lv_refr_get_disp_refreshing(); + acae: 4b13 ldr r3, [pc, #76] ; (acfc ) + area_outer.y2 += dsc->outline_width; + acb0: f8ad 5056 strh.w r5, [sp, #86] ; 0x56 + lv_disp_t * disp = _lv_refr_get_disp_refreshing(); + acb4: 4798 blx r3 + lv_disp_buf_t * vdb = lv_disp_get_buf(disp); + acb6: 4b12 ldr r3, [pc, #72] ; (ad00 ) + acb8: 4798 blx r3 + is_common = _lv_area_intersect(&draw_area, &area_outer, clip); + acba: 4b12 ldr r3, [pc, #72] ; (ad04 ) + lv_disp_buf_t * vdb = lv_disp_get_buf(disp); + acbc: 9006 str r0, [sp, #24] + is_common = _lv_area_intersect(&draw_area, &area_outer, clip); + acbe: 4642 mov r2, r8 + acc0: a914 add r1, sp, #80 ; 0x50 + acc2: a816 add r0, sp, #88 ; 0x58 + acc4: 4798 blx r3 + if(is_common == false) return; + acc6: 2800 cmp r0, #0 + acc8: f000 810e beq.w aee8 + accc: e01c b.n ad08 + acce: bf00 nop + acd0: 00009915 .word 0x00009915 + acd4: 00009711 .word 0x00009711 + acd8: 000061f1 .word 0x000061f1 + acdc: 000097a1 .word 0x000097a1 + ace0: 0000eb69 .word 0x0000eb69 + ace4: 0001019d .word 0x0001019d + ace8: 0000e131 .word 0x0000e131 + acec: 00007845 .word 0x00007845 + acf0: 00007875 .word 0x00007875 + acf4: 00009b8d .word 0x00009b8d + acf8: 000097f1 .word 0x000097f1 + acfc: 00004fe9 .word 0x00004fe9 + ad00: 0000d9e1 .word 0x0000d9e1 + ad04: 0000de8d .word 0x0000de8d + ad08: 9b07 ldr r3, [sp, #28] + draw_area.x1 -= disp_area->x1; + ad0a: f8bd 1058 ldrh.w r1, [sp, #88] ; 0x58 + ad0e: f1c3 0301 rsb r3, r3, #1 + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + ad12: f1c9 0901 rsb r9, r9, #1 + ad16: 44b9 add r9, r7 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + ad18: 441f add r7, r3 + ad1a: 9b08 ldr r3, [sp, #32] + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + ad1c: eb04 0209 add.w r2, r4, r9 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + ad20: 443b add r3, r7 + int32_t inner_w = lv_area_get_width(&area_inner); + ad22: b212 sxth r2, r2 + int32_t inner_h = lv_area_get_height(&area_inner); + ad24: b21b sxth r3, r3 + int32_t short_side = LV_MATH_MIN(inner_w, inner_h); + ad26: 429a cmp r2, r3 + ad28: bfa8 it ge + ad2a: 461a movge r2, r3 + ad2c: 9b0c ldr r3, [sp, #48] ; 0x30 + if(rin > short_side >> 1) rin = short_side >> 1; + ad2e: 1052 asrs r2, r2, #1 + ad30: 429a cmp r2, r3 + ad32: bfa8 it ge + ad34: 461a movge r2, r3 + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + ad36: 9b09 ldr r3, [sp, #36] ; 0x24 + ad38: f1c3 0301 rsb r3, r3, #1 + ad3c: 4433 add r3, r6 + ad3e: 449b add fp, r3 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + ad40: 9b0a ldr r3, [sp, #40] ; 0x28 + ad42: f1c3 0301 rsb r3, r3, #1 + ad46: 441e add r6, r3 + ad48: 4435 add r5, r6 + int32_t coords_out_w = lv_area_get_width(&area_outer); + ad4a: fa0f fb8b sxth.w fp, fp + int32_t coords_out_h = lv_area_get_height(&area_outer); + ad4e: b22d sxth r5, r5 + short_side = LV_MATH_MIN(coords_out_w, coords_out_h); + ad50: 45ab cmp fp, r5 + int32_t rout = rin + dsc->outline_width; + ad52: 9b0d ldr r3, [sp, #52] ; 0x34 + lv_draw_mask_radius_init(&mask_rin_param, &area_inner, rin, true); + ad54: 4ec8 ldr r6, [pc, #800] ; (b078 ) + short_side = LV_MATH_MIN(coords_out_w, coords_out_h); + ad56: bfa8 it ge + ad58: 46ab movge fp, r5 + int32_t rout = rin + dsc->outline_width; + ad5a: 4413 add r3, r2 + if(rout > short_side >> 1) rout = short_side >> 1; + ad5c: ea4f 0b6b mov.w fp, fp, asr #1 + ad60: 459b cmp fp, r3 + ad62: 46d9 mov r9, fp + ad64: bfa8 it ge + ad66: 4699 movge r9, r3 + draw_area.x1 -= disp_area->x1; + ad68: 9b06 ldr r3, [sp, #24] + draw_area.x2 -= disp_area->x1; + ad6a: f8bd 505c ldrh.w r5, [sp, #92] ; 0x5c + draw_area.x1 -= disp_area->x1; + ad6e: 8a1b ldrh r3, [r3, #16] + ad70: 1ac8 subs r0, r1, r3 + ad72: f8ad 0058 strh.w r0, [sp, #88] ; 0x58 + draw_area.y1 -= disp_area->y1; + ad76: 9806 ldr r0, [sp, #24] + draw_area.x2 -= disp_area->x1; + ad78: 1aeb subs r3, r5, r3 + draw_area.y1 -= disp_area->y1; + ad7a: 8a44 ldrh r4, [r0, #18] + draw_area.x2 -= disp_area->x1; + ad7c: f8ad 305c strh.w r3, [sp, #92] ; 0x5c + draw_area.y2 -= disp_area->y1; + ad80: f8bd 305e ldrh.w r3, [sp, #94] ; 0x5e + draw_area.y1 -= disp_area->y1; + ad84: f8bd 005a ldrh.w r0, [sp, #90] ; 0x5a + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + ad88: 3501 adds r5, #1 + draw_area.y2 -= disp_area->y1; + ad8a: 1b1b subs r3, r3, r4 + ad8c: 1a6d subs r5, r5, r1 + draw_area.y1 -= disp_area->y1; + ad8e: 1b00 subs r0, r0, r4 + draw_area.y2 -= disp_area->y1; + ad90: f8ad 305e strh.w r3, [sp, #94] ; 0x5e + ad94: b22b sxth r3, r5 + ad96: ee08 3a10 vmov s16, r3 + draw_area.y1 -= disp_area->y1; + ad9a: f8ad 005a strh.w r0, [sp, #90] ; 0x5a + lv_draw_mask_radius_init(&mask_rin_param, &area_inner, rin, true); + ad9e: 2301 movs r3, #1 + ada0: a912 add r1, sp, #72 ; 0x48 + ada2: a81e add r0, sp, #120 ; 0x78 + ada4: 47b0 blx r6 + int16_t mask_rin_id = lv_draw_mask_add(&mask_rin_param, NULL); + ada6: 4cb5 ldr r4, [pc, #724] ; (b07c ) + ada8: 2100 movs r1, #0 + adaa: a81e add r0, sp, #120 ; 0x78 + adac: 47a0 blx r4 + lv_draw_mask_radius_init(&mask_rout_param, &area_outer, rout, false); + adae: fa0f f289 sxth.w r2, r9 + adb2: 2300 movs r3, #0 + adb4: a914 add r1, sp, #80 ; 0x50 + int16_t mask_rin_id = lv_draw_mask_add(&mask_rin_param, NULL); + adb6: ee08 0a90 vmov s17, r0 + lv_draw_mask_radius_init(&mask_rout_param, &area_outer, rout, false); + adba: a825 add r0, sp, #148 ; 0x94 + adbc: 47b0 blx r6 + int16_t mask_rout_id = lv_draw_mask_add(&mask_rout_param, NULL); + adbe: 2100 movs r1, #0 + adc0: a825 add r0, sp, #148 ; 0x94 + adc2: 47a0 blx r4 + lv_opa_t * mask_buf = _lv_mem_buf_get(draw_area_w); + adc4: 4bae ldr r3, [pc, #696] ; (b080 ) + int16_t mask_rout_id = lv_draw_mask_add(&mask_rout_param, NULL); + adc6: ee09 0a10 vmov s18, r0 + lv_opa_t * mask_buf = _lv_mem_buf_get(draw_area_w); + adca: ee18 0a10 vmov r0, s16 + adce: 4798 blx r3 + int32_t corner_size = LV_MATH_MAX(rout, dsc->outline_width - 1); + add0: f9ba 3018 ldrsh.w r3, [sl, #24] + fill_area.y1 = disp_area->y1 + draw_area.y1; + add4: f9bd 605a ldrsh.w r6, [sp, #90] ; 0x5a + if(simple_mode) { + add8: 9a0b ldr r2, [sp, #44] ; 0x2c + lv_color_t color = dsc->outline_color; + adda: f8ba 7016 ldrh.w r7, [sl, #22] + lv_blend_mode_t blend_mode = dsc->outline_blend_mode; + adde: f89a b01d ldrb.w fp, [sl, #29] + fill_area.x2 = area_outer.x2; + ade2: f9bd 1054 ldrsh.w r1, [sp, #84] ; 0x54 + int32_t corner_size = LV_MATH_MAX(rout, dsc->outline_width - 1); + ade6: 4599 cmp r9, r3 + ade8: bfbc itt lt + adea: f103 33ff addlt.w r3, r3, #4294967295 ; 0xffffffff + adee: 9307 strlt r3, [sp, #28] + int32_t upper_corner_end = area_outer.y1 - disp_area->y1 + corner_size; + adf0: 9b06 ldr r3, [sp, #24] + adf2: bfa8 it ge + adf4: f8cd 901c strge.w r9, [sp, #28] + adf8: f9b3 c012 ldrsh.w ip, [r3, #18] + fill_area.y1 = disp_area->y1 + draw_area.y1; + adfc: eb0c 0306 add.w r3, ip, r6 + lv_opa_t * mask_buf = _lv_mem_buf_get(draw_area_w); + ae00: 4604 mov r4, r0 + fill_area.y1 = disp_area->y1 + draw_area.y1; + ae02: b21b sxth r3, r3 + fill_area.x1 = area_outer.x1; + ae04: f9bd 0050 ldrsh.w r0, [sp, #80] ; 0x50 + if(simple_mode) { + ae08: 2a00 cmp r2, #0 + ae0a: f040 873f bne.w bc8c + int32_t upper_corner_end = area_outer.y1 - disp_area->y1 + corner_size; + ae0e: f9bd 2052 ldrsh.w r2, [sp, #82] ; 0x52 + ae12: 9d07 ldr r5, [sp, #28] + fill_area.x1 = area_outer.x1; + ae14: f8ad 0060 strh.w r0, [sp, #96] ; 0x60 + int32_t upper_corner_end = area_outer.y1 - disp_area->y1 + corner_size; + ae18: eba2 020c sub.w r2, r2, ip + ae1c: 442a add r2, r5 + ae1e: 9208 str r2, [sp, #32] + fill_area.x2 = area_outer.x2; + ae20: f8ad 1064 strh.w r1, [sp, #100] ; 0x64 + fill_area.y1 = disp_area->y1 + draw_area.y1; + ae24: f8ad 3062 strh.w r3, [sp, #98] ; 0x62 + fill_area.y2 = fill_area.y1; + ae28: f8ad 3066 strh.w r3, [sp, #102] ; 0x66 + for(h = draw_area.y1; h <= upper_corner_end; h++) { + ae2c: 9b08 ldr r3, [sp, #32] + ae2e: 42b3 cmp r3, r6 + ae30: f280 8624 bge.w ba7c + int32_t lower_corner_end = area_outer.y2 - disp_area->y1 - corner_size; + ae34: 9b06 ldr r3, [sp, #24] + ae36: f9bd 6056 ldrsh.w r6, [sp, #86] ; 0x56 + ae3a: f9b3 3012 ldrsh.w r3, [r3, #18] + ae3e: 9a07 ldr r2, [sp, #28] + ae40: 1af6 subs r6, r6, r3 + ae42: 1ab6 subs r6, r6, r2 + if(lower_corner_end <= upper_corner_end) lower_corner_end = upper_corner_end + 1; + ae44: 9a08 ldr r2, [sp, #32] + ae46: 42b2 cmp r2, r6 + ae48: bfa4 itt ge + ae4a: 4616 movge r6, r2 + ae4c: 3601 addge r6, #1 + fill_area.y1 = disp_area->y1 + lower_corner_end; + ae4e: 4433 add r3, r6 + ae50: b21b sxth r3, r3 + ae52: f8ad 3062 strh.w r3, [sp, #98] ; 0x62 + fill_area.y2 = fill_area.y1; + ae56: f8ad 3066 strh.w r3, [sp, #102] ; 0x66 + for(h = lower_corner_end; h <= draw_area.y2; h++) { + ae5a: f9bd 305e ldrsh.w r3, [sp, #94] ; 0x5e + ae5e: 429e cmp r6, r3 + ae60: f340 868d ble.w bb7e + fill_area.y1 = area_outer.y1 + corner_size + 1; + ae64: f8bd 3052 ldrh.w r3, [sp, #82] ; 0x52 + ae68: 9a07 ldr r2, [sp, #28] + _lv_blend_fill(clip, &fill_area, color, NULL, LV_DRAW_MASK_RES_FULL_COVER, opa, blend_mode); + ae6a: 4d86 ldr r5, [pc, #536] ; (b084 ) + fill_area.y1 = area_outer.y1 + corner_size + 1; + ae6c: 3301 adds r3, #1 + ae6e: fa13 f382 uxtah r3, r3, r2 + ae72: f8ad 3062 strh.w r3, [sp, #98] ; 0x62 + fill_area.y2 = area_outer.y2 - corner_size - 1; + ae76: f8bd 3056 ldrh.w r3, [sp, #86] ; 0x56 + ae7a: 3b01 subs r3, #1 + ae7c: 1a9b subs r3, r3, r2 + ae7e: f8ad 3066 strh.w r3, [sp, #102] ; 0x66 + fill_area.x1 = area_outer.x1; + ae82: f9bd 3050 ldrsh.w r3, [sp, #80] ; 0x50 + fill_area.x2 = area_outer.x1 + dsc->outline_width - 1; + ae86: f8ba 2018 ldrh.w r2, [sl, #24] + fill_area.x1 = area_outer.x1; + ae8a: f8ad 3060 strh.w r3, [sp, #96] ; 0x60 + fill_area.x2 = area_outer.x1 + dsc->outline_width - 1; + ae8e: 3b01 subs r3, #1 + ae90: 4413 add r3, r2 + _lv_blend_fill(clip, &fill_area, color, NULL, LV_DRAW_MASK_RES_FULL_COVER, opa, blend_mode); + ae92: 2601 movs r6, #1 + fill_area.x2 = area_outer.x1 + dsc->outline_width - 1; + ae94: f8ad 3064 strh.w r3, [sp, #100] ; 0x64 + _lv_blend_fill(clip, &fill_area, color, NULL, LV_DRAW_MASK_RES_FULL_COVER, opa, blend_mode); + ae98: 9b05 ldr r3, [sp, #20] + ae9a: 9301 str r3, [sp, #4] + ae9c: 463a mov r2, r7 + ae9e: 2300 movs r3, #0 + aea0: a918 add r1, sp, #96 ; 0x60 + aea2: 4640 mov r0, r8 + aea4: f8cd b008 str.w fp, [sp, #8] + aea8: 9600 str r6, [sp, #0] + aeaa: 47a8 blx r5 + fill_area.x1 = area_outer.x2 - dsc->outline_width + 1; + aeac: f9bd 2054 ldrsh.w r2, [sp, #84] ; 0x54 + aeb0: f8ba 1018 ldrh.w r1, [sl, #24] + fill_area.x2 = area_outer.x2; + aeb4: f8ad 2064 strh.w r2, [sp, #100] ; 0x64 + fill_area.x1 = area_outer.x2 - dsc->outline_width + 1; + aeb8: 1993 adds r3, r2, r6 + aeba: 1a5b subs r3, r3, r1 + aebc: f8ad 3060 strh.w r3, [sp, #96] ; 0x60 + _lv_blend_fill(clip, &fill_area, color, NULL, LV_DRAW_MASK_RES_FULL_COVER, opa, blend_mode); + aec0: 9b05 ldr r3, [sp, #20] + aec2: f8cd b008 str.w fp, [sp, #8] + aec6: e9cd 6300 strd r6, r3, [sp] + aeca: 463a mov r2, r7 + aecc: 2300 movs r3, #0 + aece: a918 add r1, sp, #96 ; 0x60 + aed0: 4640 mov r0, r8 + aed2: 47a8 blx r5 + lv_draw_mask_remove_id(mask_rin_id); + aed4: 4d6c ldr r5, [pc, #432] ; (b088 ) + aed6: ee18 0a90 vmov r0, s17 + aeda: 47a8 blx r5 + lv_draw_mask_remove_id(mask_rout_id); + aedc: ee19 0a10 vmov r0, s18 + aee0: 47a8 blx r5 + _lv_mem_buf_release(mask_buf); + aee2: 4b6a ldr r3, [pc, #424] ; (b08c ) + aee4: 4620 mov r0, r4 + aee6: 4798 blx r3 +} + aee8: b02d add sp, #180 ; 0xb4 + aeea: ecbd 8b04 vpop {d8-d9} + aeee: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + _lv_memcpy(mask_buf, sh_buf_tmp, w); + aef2: 4629 mov r1, r5 + aef4: 4b66 ldr r3, [pc, #408] ; (b090 ) + mask_res = lv_draw_mask_apply(mask_buf, fa.x1, fa.y1, w); + aef6: 4c67 ldr r4, [pc, #412] ; (b094 ) + _lv_memcpy(mask_buf, sh_buf_tmp, w); + aef8: 4632 mov r2, r6 + aefa: ee18 0a10 vmov r0, s16 + aefe: 4798 blx r3 + mask_res = lv_draw_mask_apply(mask_buf, fa.x1, fa.y1, w); + af00: f9bd 207a ldrsh.w r2, [sp, #122] ; 0x7a + af04: f9bd 1078 ldrsh.w r1, [sp, #120] ; 0x78 + af08: 4633 mov r3, r6 + af0a: ee18 0a10 vmov r0, s16 + af0e: 47a0 blx r4 + _lv_blend_fill(clip, &fa, dsc->shadow_color, mask_buf, + af10: f89a 3029 ldrb.w r3, [sl, #41] ; 0x29 + af14: 9302 str r3, [sp, #8] + if(mask_res == LV_DRAW_MASK_RES_FULL_COVER) mask_res = LV_DRAW_MASK_RES_CHANGED; + af16: 2801 cmp r0, #1 + _lv_blend_fill(clip, &fa, dsc->shadow_color, mask_buf, + af18: 9b08 ldr r3, [sp, #32] + af1a: 4c5a ldr r4, [pc, #360] ; (b084 ) + if(mask_res == LV_DRAW_MASK_RES_FULL_COVER) mask_res = LV_DRAW_MASK_RES_CHANGED; + af1c: bf08 it eq + af1e: 2002 moveq r0, #2 + _lv_blend_fill(clip, &fa, dsc->shadow_color, mask_buf, + af20: e9cd 0300 strd r0, r3, [sp] + af24: a91e add r1, sp, #120 ; 0x78 + af26: ee18 3a10 vmov r3, s16 + af2a: f8ba 201e ldrh.w r2, [sl, #30] + af2e: 4640 mov r0, r8 + af30: 47a0 blx r4 + fa.y1++; + af32: f8bd 307a ldrh.w r3, [sp, #122] ; 0x7a + af36: 3301 adds r3, #1 + af38: f8ad 307a strh.w r3, [sp, #122] ; 0x7a + fa.y2++; + af3c: f8bd 307e ldrh.w r3, [sp, #126] ; 0x7e + af40: 3301 adds r3, #1 + af42: b21b sxth r3, r3 + sh_buf_tmp += corner_size; + af44: 444d add r5, r9 + for(y = 0; y < h; y++) { + af46: 3701 adds r7, #1 + af48: f7ff ba2e b.w a3a8 + _lv_memcpy(mask_buf, sh_buf_tmp, w); + af4c: 4629 mov r1, r5 + af4e: 4b50 ldr r3, [pc, #320] ; (b090 ) + mask_res = lv_draw_mask_apply(mask_buf, fa.x1, fa.y1, w); + af50: 4c50 ldr r4, [pc, #320] ; (b094 ) + _lv_memcpy(mask_buf, sh_buf_tmp, w); + af52: 4632 mov r2, r6 + af54: ee18 0a10 vmov r0, s16 + af58: 4798 blx r3 + mask_res = lv_draw_mask_apply(mask_buf, fa.x1, fa.y1, w); + af5a: f9bd 207a ldrsh.w r2, [sp, #122] ; 0x7a + af5e: f9bd 1078 ldrsh.w r1, [sp, #120] ; 0x78 + af62: 4633 mov r3, r6 + af64: ee18 0a10 vmov r0, s16 + af68: 47a0 blx r4 + _lv_blend_fill(clip, &fa, dsc->shadow_color, mask_buf, + af6a: f89a 3029 ldrb.w r3, [sl, #41] ; 0x29 + af6e: 9302 str r3, [sp, #8] + if(mask_res == LV_DRAW_MASK_RES_FULL_COVER) mask_res = LV_DRAW_MASK_RES_CHANGED; + af70: 2801 cmp r0, #1 + _lv_blend_fill(clip, &fa, dsc->shadow_color, mask_buf, + af72: 9b08 ldr r3, [sp, #32] + af74: 4c43 ldr r4, [pc, #268] ; (b084 ) + if(mask_res == LV_DRAW_MASK_RES_FULL_COVER) mask_res = LV_DRAW_MASK_RES_CHANGED; + af76: bf08 it eq + af78: 2002 moveq r0, #2 + _lv_blend_fill(clip, &fa, dsc->shadow_color, mask_buf, + af7a: e9cd 0300 strd r0, r3, [sp] + af7e: a91e add r1, sp, #120 ; 0x78 + af80: ee18 3a10 vmov r3, s16 + af84: f8ba 201e ldrh.w r2, [sl, #30] + af88: 4640 mov r0, r8 + af8a: 47a0 blx r4 + fa.y1--; + af8c: f8bd 307a ldrh.w r3, [sp, #122] ; 0x7a + af90: 3b01 subs r3, #1 + af92: f8ad 307a strh.w r3, [sp, #122] ; 0x7a + fa.y2--; + af96: f8bd 307e ldrh.w r3, [sp, #126] ; 0x7e + af9a: 3b01 subs r3, #1 + af9c: f8ad 307e strh.w r3, [sp, #126] ; 0x7e + sh_buf_tmp += corner_size; + afa0: 444d add r5, r9 + for(y = 0; y < h; y++) { + afa2: 3701 adds r7, #1 + afa4: f7ff ba55 b.w a452 + _lv_memcpy(mask_buf, sh_buf_tmp, w); + afa8: 4b39 ldr r3, [pc, #228] ; (b090 ) + afaa: ee18 0a10 vmov r0, s16 + afae: 462a mov r2, r5 + afb0: 4631 mov r1, r6 + afb2: 4798 blx r3 + if(simple_mode) { + afb4: 9b07 ldr r3, [sp, #28] + afb6: b953 cbnz r3, afce + mask_res = lv_draw_mask_apply(mask_buf, fa.x1, fa.y1, w); + afb8: f9bd 207a ldrsh.w r2, [sp, #122] ; 0x7a + afbc: f9bd 1078 ldrsh.w r1, [sp, #120] ; 0x78 + afc0: 4c34 ldr r4, [pc, #208] ; (b094 ) + afc2: ee18 0a10 vmov r0, s16 + afc6: 462b mov r3, r5 + afc8: 47a0 blx r4 + if(mask_res == LV_DRAW_MASK_RES_FULL_COVER) mask_res = LV_DRAW_MASK_RES_CHANGED; + afca: 2801 cmp r0, #1 + afcc: d100 bne.n afd0 + afce: 2002 movs r0, #2 + _lv_blend_fill(clip, &fa, + afd0: f89a 3029 ldrb.w r3, [sl, #41] ; 0x29 + afd4: 9302 str r3, [sp, #8] + afd6: f89a 3028 ldrb.w r3, [sl, #40] ; 0x28 + afda: 4c2a ldr r4, [pc, #168] ; (b084 ) + afdc: e9cd 0300 strd r0, r3, [sp] + afe0: a91e add r1, sp, #120 ; 0x78 + afe2: ee18 3a10 vmov r3, s16 + afe6: f8ba 201e ldrh.w r2, [sl, #30] + afea: 4640 mov r0, r8 + afec: 47a0 blx r4 + fa.y1++; + afee: f8bd 307a ldrh.w r3, [sp, #122] ; 0x7a + aff2: 3301 adds r3, #1 + aff4: f8ad 307a strh.w r3, [sp, #122] ; 0x7a + fa.y2++; + aff8: f8bd 307e ldrh.w r3, [sp, #126] ; 0x7e + affc: 3301 adds r3, #1 + affe: b21b sxth r3, r3 + for(y = 0; y < h; y++) { + b000: 3701 adds r7, #1 + b002: f7ff ba6f b.w a4e4 + lv_opa_t opa_tmp = sh_buf_tmp[0]; + b006: 7833 ldrb r3, [r6, #0] + if(opa_tmp != LV_OPA_COVER || opa != LV_OPA_COVER) opa_tmp = (opa * opa_tmp) >> 8; + b008: 9a08 ldr r2, [sp, #32] + b00a: ea02 0103 and.w r1, r2, r3 + b00e: 29ff cmp r1, #255 ; 0xff + b010: bf1c itt ne + b012: fb12 f303 smulbbne r3, r2, r3 + b016: f3c3 2107 ubfxne r1, r3, #8, #8 + _lv_memset(mask_buf, opa_tmp, w); + b01a: ee18 0a10 vmov r0, s16 + b01e: 4b1e ldr r3, [pc, #120] ; (b098 ) + b020: 462a mov r2, r5 + b022: 4798 blx r3 + if(simple_mode) { + b024: 9b07 ldr r3, [sp, #28] + b026: b953 cbnz r3, b03e + mask_res = lv_draw_mask_apply(mask_buf, fa.x1, fa.y1, w); + b028: f9bd 207a ldrsh.w r2, [sp, #122] ; 0x7a + b02c: f9bd 1078 ldrsh.w r1, [sp, #120] ; 0x78 + b030: 4c18 ldr r4, [pc, #96] ; (b094 ) + b032: ee18 0a10 vmov r0, s16 + b036: 462b mov r3, r5 + b038: 47a0 blx r4 + if(mask_res == LV_DRAW_MASK_RES_FULL_COVER) mask_res = LV_DRAW_MASK_RES_CHANGED; + b03a: 2801 cmp r0, #1 + b03c: d100 bne.n b040 + b03e: 2002 movs r0, #2 + _lv_blend_fill(clip, &fa, dsc->shadow_color, mask_buf, + b040: f89a 3029 ldrb.w r3, [sl, #41] ; 0x29 + b044: 9302 str r3, [sp, #8] + b046: 23ff movs r3, #255 ; 0xff + b048: e9cd 0300 strd r0, r3, [sp] + b04c: 4c0d ldr r4, [pc, #52] ; (b084 ) + b04e: f8ba 201e ldrh.w r2, [sl, #30] + b052: ee18 3a10 vmov r3, s16 + b056: a91e add r1, sp, #120 ; 0x78 + b058: 4640 mov r0, r8 + b05a: 47a0 blx r4 + fa.y1++; + b05c: f8bd 307a ldrh.w r3, [sp, #122] ; 0x7a + b060: 3301 adds r3, #1 + b062: f8ad 307a strh.w r3, [sp, #122] ; 0x7a + fa.y2++; + b066: f8bd 307e ldrh.w r3, [sp, #126] ; 0x7e + b06a: 3301 adds r3, #1 + b06c: b21b sxth r3, r3 + sh_buf_tmp += corner_size; + b06e: 444e add r6, r9 + for(y = 0; y < h; y++) { + b070: 3701 adds r7, #1 + b072: f7ff ba80 b.w a576 + b076: bf00 nop + b078: 00009915 .word 0x00009915 + b07c: 00009711 .word 0x00009711 + b080: 0000eeb5 .word 0x0000eeb5 + b084: 000061f1 .word 0x000061f1 + b088: 000097a1 .word 0x000097a1 + b08c: 0000eb69 .word 0x0000eb69 + b090: 0000ec31 .word 0x0000ec31 + b094: 00009761 .word 0x00009761 + b098: 0000efb9 .word 0x0000efb9 + lv_opa_t opa_tmp = sh_buf_tmp[0]; + b09c: 7833 ldrb r3, [r6, #0] + if(opa_tmp != LV_OPA_COVER || opa != LV_OPA_COVER) opa_tmp = (opa * opa_tmp) >> 8; + b09e: 9a08 ldr r2, [sp, #32] + b0a0: ea02 0103 and.w r1, r2, r3 + b0a4: 29ff cmp r1, #255 ; 0xff + b0a6: bf1c itt ne + b0a8: fb12 f303 smulbbne r3, r2, r3 + b0ac: f3c3 2107 ubfxne r1, r3, #8, #8 + _lv_memset(mask_buf, opa_tmp, w); + b0b0: ee18 0a10 vmov r0, s16 + b0b4: 4bb5 ldr r3, [pc, #724] ; (b38c ) + b0b6: 462a mov r2, r5 + b0b8: 4798 blx r3 + if(simple_mode) { + b0ba: 9b07 ldr r3, [sp, #28] + b0bc: b953 cbnz r3, b0d4 + mask_res = lv_draw_mask_apply(mask_buf, fa.x1, fa.y1, w); + b0be: f9bd 207a ldrsh.w r2, [sp, #122] ; 0x7a + b0c2: f9bd 1078 ldrsh.w r1, [sp, #120] ; 0x78 + b0c6: 4cb2 ldr r4, [pc, #712] ; (b390 ) + b0c8: ee18 0a10 vmov r0, s16 + b0cc: 462b mov r3, r5 + b0ce: 47a0 blx r4 + if(mask_res == LV_DRAW_MASK_RES_FULL_COVER) mask_res = LV_DRAW_MASK_RES_CHANGED; + b0d0: 2801 cmp r0, #1 + b0d2: d100 bne.n b0d6 + b0d4: 2002 movs r0, #2 + _lv_blend_fill(clip, &fa, dsc->shadow_color, mask_buf, + b0d6: f89a 3029 ldrb.w r3, [sl, #41] ; 0x29 + b0da: 9302 str r3, [sp, #8] + b0dc: 23ff movs r3, #255 ; 0xff + b0de: e9cd 0300 strd r0, r3, [sp] + b0e2: 4cac ldr r4, [pc, #688] ; (b394 ) + b0e4: f8ba 201e ldrh.w r2, [sl, #30] + b0e8: ee18 3a10 vmov r3, s16 + b0ec: a91e add r1, sp, #120 ; 0x78 + b0ee: 4640 mov r0, r8 + b0f0: 47a0 blx r4 + fa.y1--; + b0f2: f8bd 307a ldrh.w r3, [sp, #122] ; 0x7a + b0f6: 3b01 subs r3, #1 + b0f8: f8ad 307a strh.w r3, [sp, #122] ; 0x7a + fa.y2--; + b0fc: f8bd 307e ldrh.w r3, [sp, #126] ; 0x7e + b100: 3b01 subs r3, #1 + b102: f8ad 307e strh.w r3, [sp, #126] ; 0x7e + sh_buf_tmp += corner_size; + b106: 444e add r6, r9 + for(y = 0; y < h; y++) { + b108: 3701 adds r7, #1 + b10a: f7ff ba81 b.w a610 + _lv_memset(mask_buf, dsc->shadow_opa, w); + b10e: f89a 1028 ldrb.w r1, [sl, #40] ; 0x28 + mask_res = lv_draw_mask_apply(mask_buf, fa.x1, fa.y1, w); + b112: 4c9f ldr r4, [pc, #636] ; (b390 ) + _lv_memset(mask_buf, dsc->shadow_opa, w); + b114: ee18 0a10 vmov r0, s16 + b118: 4632 mov r2, r6 + b11a: 47c8 blx r9 + mask_res = lv_draw_mask_apply(mask_buf, fa.x1, fa.y1, w); + b11c: f9bd 207a ldrsh.w r2, [sp, #122] ; 0x7a + b120: f9bd 1078 ldrsh.w r1, [sp, #120] ; 0x78 + b124: 4633 mov r3, r6 + b126: ee18 0a10 vmov r0, s16 + b12a: 47a0 blx r4 + _lv_blend_fill(clip, &fa, dsc->shadow_color, mask_buf, + b12c: f89a 3029 ldrb.w r3, [sl, #41] ; 0x29 + b130: 9302 str r3, [sp, #8] + if(mask_res == LV_DRAW_MASK_RES_FULL_COVER) mask_res = LV_DRAW_MASK_RES_CHANGED; + b132: 2801 cmp r0, #1 + b134: bf08 it eq + b136: 2002 moveq r0, #2 + _lv_blend_fill(clip, &fa, dsc->shadow_color, mask_buf, + b138: 23ff movs r3, #255 ; 0xff + b13a: e9cd 0300 strd r0, r3, [sp] + b13e: 4c95 ldr r4, [pc, #596] ; (b394 ) + b140: f8ba 201e ldrh.w r2, [sl, #30] + b144: ee18 3a10 vmov r3, s16 + b148: a91e add r1, sp, #120 ; 0x78 + b14a: 4640 mov r0, r8 + b14c: 47a0 blx r4 + fa.y1++; + b14e: f8bd 307a ldrh.w r3, [sp, #122] ; 0x7a + b152: 3301 adds r3, #1 + b154: f8ad 307a strh.w r3, [sp, #122] ; 0x7a + fa.y2++; + b158: f8bd 307e ldrh.w r3, [sp, #126] ; 0x7e + b15c: 3301 adds r3, #1 + b15e: b21b sxth r3, r3 + for(y = 0; y < h; y++) { + b160: 3501 adds r5, #1 + b162: f7ff ba93 b.w a68c + if(other_mask_cnt) simple_mode = false; + b166: 2300 movs r3, #0 + b168: f7ff bb13 b.w a792 + if(rout > 0) { + b16c: 2c00 cmp r4, #0 + b16e: f340 80b0 ble.w b2d2 + lv_draw_mask_radius_init(&mask_rout_param, &coords_bg, rout, false); + b172: 2300 movs r3, #0 + b174: 4622 mov r2, r4 + b176: a916 add r1, sp, #88 ; 0x58 + b178: a825 add r0, sp, #148 ; 0x94 + b17a: 4f87 ldr r7, [pc, #540] ; (b398 ) + b17c: 47b8 blx r7 + mask_rout_id = lv_draw_mask_add(&mask_rout_param, NULL); + b17e: 4b87 ldr r3, [pc, #540] ; (b39c ) + b180: 2100 movs r1, #0 + b182: a825 add r0, sp, #148 ; 0x94 + b184: 4798 blx r3 + b186: 900b str r0, [sp, #44] ; 0x2c + lv_color_t grad_color = dsc->bg_color; + b188: f8ba 3002 ldrh.w r3, [sl, #2] + b18c: ee08 3a10 vmov s16, r3 + if(dsc->bg_grad_dir == LV_GRAD_DIR_HOR && dsc->bg_color.full != dsc->bg_grad_color.full) { + b190: f89a 3006 ldrb.w r3, [sl, #6] + b194: 2b02 cmp r3, #2 + b196: f040 80a9 bne.w b2ec + b19a: f8ba 2004 ldrh.w r2, [sl, #4] + b19e: f8ba 3002 ldrh.w r3, [sl, #2] + b1a2: 429a cmp r2, r3 + b1a4: f000 80a2 beq.w b2ec + grad_map = _lv_mem_buf_get(coords_w * sizeof(lv_color_t)); + b1a8: 4b7d ldr r3, [pc, #500] ; (b3a0 ) + b1aa: 0070 lsls r0, r6, #1 + b1ac: 4798 blx r3 + for(i = 0; i < coords_w; i++) { + b1ae: 2700 movs r7, #0 + grad_map = _lv_mem_buf_get(coords_w * sizeof(lv_color_t)); + b1b0: 9006 str r0, [sp, #24] + for(i = 0; i < coords_w; i++) { + b1b2: 42be cmp r6, r7 + b1b4: 4b7b ldr r3, [pc, #492] ; (b3a4 ) + b1b6: f300 8090 bgt.w b2da + b1ba: f9bd 205c ldrsh.w r2, [sp, #92] ; 0x5c + b1be: f9bd 1058 ldrsh.w r1, [sp, #88] ; 0x58 + fill_area.x2 = coords_bg.x2; + b1c2: f8ad 206c strh.w r2, [sp, #108] ; 0x6c + b1c6: 1c53 adds r3, r2, #1 + b1c8: 1a5b subs r3, r3, r1 + if(lv_area_get_width(&coords_bg) - 2 * rout > SPLIT_LIMIT) split = true; + b1ca: b21b sxth r3, r3 + b1cc: eba3 0344 sub.w r3, r3, r4, lsl #1 + b1d0: 930a str r3, [sp, #40] ; 0x28 + fill_area.y1 = disp_area->y1 + draw_area.y1; + b1d2: 9b05 ldr r3, [sp, #20] + b1d4: f9bd 2062 ldrsh.w r2, [sp, #98] ; 0x62 + b1d8: 8a5b ldrh r3, [r3, #18] + fill_area.x1 = coords_bg.x1; + b1da: f8ad 1068 strh.w r1, [sp, #104] ; 0x68 + fill_area.y1 = disp_area->y1 + draw_area.y1; + b1de: 4413 add r3, r2 + b1e0: b21b sxth r3, r3 + b1e2: f8ad 306a strh.w r3, [sp, #106] ; 0x6a + for(h = draw_area.y1; h <= draw_area.y2; h++) { + b1e6: 9207 str r2, [sp, #28] + b1e8: 9a07 ldr r2, [sp, #28] + fill_area.y2 = fill_area.y1; + b1ea: f8ad 306e strh.w r3, [sp, #110] ; 0x6e + for(h = draw_area.y1; h <= draw_area.y2; h++) { + b1ee: f9bd 3066 ldrsh.w r3, [sp, #102] ; 0x66 + b1f2: 429a cmp r2, r3 + b1f4: dd7d ble.n b2f2 + if(dsc->bg_grad_dir == LV_GRAD_DIR_NONE && other_mask_cnt == 0 && split) { + b1f6: f89a 3006 ldrb.w r3, [sl, #6] + b1fa: 9a0c ldr r2, [sp, #48] ; 0x30 + b1fc: 431a orrs r2, r3 + b1fe: f012 03ff ands.w r3, r2, #255 ; 0xff + b202: d15d bne.n b2c0 + b204: 9a0a ldr r2, [sp, #40] ; 0x28 + b206: 2a32 cmp r2, #50 ; 0x32 + b208: dd5a ble.n b2c0 + fill_area.x1 = coords_bg.x1 + rout; + b20a: f8bd 2058 ldrh.w r2, [sp, #88] ; 0x58 + b20e: fa12 f284 uxtah r2, r2, r4 + b212: f8ad 2068 strh.w r2, [sp, #104] ; 0x68 + fill_area.x2 = coords_bg.x2 - rout; + b216: f8bd 205c ldrh.w r2, [sp, #92] ; 0x5c + fill_area.x1 = coords_bg.x1 + rout; + b21a: b2a6 uxth r6, r4 + fill_area.x2 = coords_bg.x2 - rout; + b21c: 1b92 subs r2, r2, r6 + b21e: f8ad 206c strh.w r2, [sp, #108] ; 0x6c + fill_area.y1 = coords_bg.y1; + b222: f9bd 205a ldrsh.w r2, [sp, #90] ; 0x5a + b226: f8ad 206a strh.w r2, [sp, #106] ; 0x6a + fill_area.y2 = coords_bg.y1 + rout; + b22a: 4432 add r2, r6 + b22c: f8ad 206e strh.w r2, [sp, #110] ; 0x6e + _lv_blend_fill(clip, &fill_area, + b230: f89a 200d ldrb.w r2, [sl, #13] + b234: 4c57 ldr r4, [pc, #348] ; (b394 ) + b236: e9cd 9201 strd r9, r2, [sp, #4] + b23a: 2201 movs r2, #1 + b23c: 9200 str r2, [sp, #0] + b23e: f8ba 2002 ldrh.w r2, [sl, #2] + b242: a91a add r1, sp, #104 ; 0x68 + b244: 4640 mov r0, r8 + b246: 47a0 blx r4 + fill_area.y1 = coords_bg.y2 - rout; + b248: f9bd 105e ldrsh.w r1, [sp, #94] ; 0x5e + if(fill_area.y1 <= fill_area.y2) fill_area.y1 = fill_area.y2 + 1; /*Avoid overdrawing the last line*/ + b24c: f9bd 306e ldrsh.w r3, [sp, #110] ; 0x6e + _lv_blend_fill(clip, &fill_area, + b250: 4c50 ldr r4, [pc, #320] ; (b394 ) + fill_area.y2 = coords_bg.y2; + b252: f8ad 106e strh.w r1, [sp, #110] ; 0x6e + fill_area.y1 = coords_bg.y2 - rout; + b256: 1b8a subs r2, r1, r6 + b258: b212 sxth r2, r2 + if(fill_area.y1 <= fill_area.y2) fill_area.y1 = fill_area.y2 + 1; /*Avoid overdrawing the last line*/ + b25a: 429a cmp r2, r3 + b25c: bfd8 it le + b25e: 3301 addle r3, #1 + fill_area.y1 = coords_bg.y2 - rout; + b260: f8ad 206a strh.w r2, [sp, #106] ; 0x6a + if(fill_area.y1 <= fill_area.y2) fill_area.y1 = fill_area.y2 + 1; /*Avoid overdrawing the last line*/ + b264: bfd8 it le + b266: f8ad 306a strhle.w r3, [sp, #106] ; 0x6a + _lv_blend_fill(clip, &fill_area, + b26a: f89a 300d ldrb.w r3, [sl, #13] + b26e: e9cd 9301 strd r9, r3, [sp, #4] + b272: 2701 movs r7, #1 + b274: 9700 str r7, [sp, #0] + b276: f8ba 2002 ldrh.w r2, [sl, #2] + b27a: 2300 movs r3, #0 + b27c: a91a add r1, sp, #104 ; 0x68 + b27e: 4640 mov r0, r8 + b280: 47a0 blx r4 + fill_area.x1 = coords_bg.x1; + b282: f8bd 3058 ldrh.w r3, [sp, #88] ; 0x58 + b286: f8ad 3068 strh.w r3, [sp, #104] ; 0x68 + fill_area.x2 = coords_bg.x2; + b28a: f8bd 305c ldrh.w r3, [sp, #92] ; 0x5c + b28e: f8ad 306c strh.w r3, [sp, #108] ; 0x6c + fill_area.y1 = coords_bg.y1 + rout + 1; + b292: f8bd 305a ldrh.w r3, [sp, #90] ; 0x5a + b296: 443b add r3, r7 + b298: 4433 add r3, r6 + b29a: f8ad 306a strh.w r3, [sp, #106] ; 0x6a + fill_area.y2 = coords_bg.y2 - rout - 1; + b29e: f8bd 305e ldrh.w r3, [sp, #94] ; 0x5e + b2a2: 3b01 subs r3, #1 + b2a4: 1b9b subs r3, r3, r6 + b2a6: f8ad 306e strh.w r3, [sp, #110] ; 0x6e + _lv_blend_fill(clip, &fill_area, + b2aa: f89a 300d ldrb.w r3, [sl, #13] + b2ae: 9700 str r7, [sp, #0] + b2b0: e9cd 9301 strd r9, r3, [sp, #4] + b2b4: a91a add r1, sp, #104 ; 0x68 + b2b6: f8ba 2002 ldrh.w r2, [sl, #2] + b2ba: 2300 movs r3, #0 + b2bc: 4640 mov r0, r8 + b2be: 47a0 blx r4 + if(grad_map) _lv_mem_buf_release(grad_map); + b2c0: 9b06 ldr r3, [sp, #24] + b2c2: 2b00 cmp r3, #0 + b2c4: f43f aa98 beq.w a7f8 + b2c8: 4618 mov r0, r3 + b2ca: 4b37 ldr r3, [pc, #220] ; (b3a8 ) + b2cc: 4798 blx r3 + b2ce: f7ff ba93 b.w a7f8 + int16_t mask_rout_id = LV_MASK_ID_INV; + b2d2: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + b2d6: 930b str r3, [sp, #44] ; 0x2c + b2d8: e756 b.n b188 + grad_map[i] = grad_get(dsc, coords_w, i); + b2da: b23a sxth r2, r7 + b2dc: 4631 mov r1, r6 + b2de: 4650 mov r0, sl + b2e0: 4798 blx r3 + b2e2: 9b06 ldr r3, [sp, #24] + b2e4: f823 0017 strh.w r0, [r3, r7, lsl #1] + for(i = 0; i < coords_w; i++) { + b2e8: 3701 adds r7, #1 + b2ea: e762 b.n b1b2 + lv_color_t * grad_map = NULL; + b2ec: 2300 movs r3, #0 + b2ee: 9306 str r3, [sp, #24] + b2f0: e763 b.n b1ba + int32_t y = h + vdb->area.y1; + b2f2: 9b05 ldr r3, [sp, #20] + b2f4: f9b3 7012 ldrsh.w r7, [r3, #18] + b2f8: 9b07 ldr r3, [sp, #28] + b2fa: 441f add r7, r3 + if(y > coords_bg.y1 + rout + 1 && + b2fc: f9bd 305a ldrsh.w r3, [sp, #90] ; 0x5a + b300: 4423 add r3, r4 + b302: 3301 adds r3, #1 + b304: 429f cmp r7, r3 + b306: dd08 ble.n b31a + y < coords_bg.y2 - rout - 1) { + b308: f9bd 305e ldrsh.w r3, [sp, #94] ; 0x5e + b30c: 1b1b subs r3, r3, r4 + b30e: 3b01 subs r3, #1 + if(y > coords_bg.y1 + rout + 1 && + b310: 429f cmp r7, r3 + b312: da02 bge.n b31a + if(simple_mode == false) { + b314: 9b08 ldr r3, [sp, #32] + b316: 2b00 cmp r3, #0 + b318: d136 bne.n b388 + _lv_memset_ff(mask_buf, draw_area_w); + b31a: ee18 1a90 vmov r1, s17 + b31e: 4b23 ldr r3, [pc, #140] ; (b3ac ) + mask_res = lv_draw_mask_apply(mask_buf, vdb->area.x1 + draw_area.x1, vdb->area.y1 + h, draw_area_w); + b320: 4e1b ldr r6, [pc, #108] ; (b390 ) + _lv_memset_ff(mask_buf, draw_area_w); + b322: 4628 mov r0, r5 + b324: 4798 blx r3 + mask_res = lv_draw_mask_apply(mask_buf, vdb->area.x1 + draw_area.x1, vdb->area.y1 + h, draw_area_w); + b326: 9b05 ldr r3, [sp, #20] + b328: 8a5a ldrh r2, [r3, #18] + b32a: 9b07 ldr r3, [sp, #28] + b32c: 441a add r2, r3 + b32e: 9b05 ldr r3, [sp, #20] + b330: 8a19 ldrh r1, [r3, #16] + b332: f8bd 3060 ldrh.w r3, [sp, #96] ; 0x60 + b336: 4419 add r1, r3 + b338: b212 sxth r2, r2 + b33a: ee18 3a90 vmov r3, s17 + b33e: b209 sxth r1, r1 + b340: 4628 mov r0, r5 + b342: 47b0 blx r6 + b344: 4606 mov r6, r0 + if(dsc->bg_grad_dir == LV_GRAD_DIR_VER && dsc->bg_color.full != dsc->bg_grad_color.full) { + b346: f89a 3006 ldrb.w r3, [sl, #6] + b34a: 9309 str r3, [sp, #36] ; 0x24 + b34c: 2b01 cmp r3, #1 + b34e: d12f bne.n b3b0 + b350: f8ba 2002 ldrh.w r2, [sl, #2] + b354: f8ba 3004 ldrh.w r3, [sl, #4] + b358: 429a cmp r2, r3 + b35a: d00d beq.n b378 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + b35c: f8bd 105e ldrh.w r1, [sp, #94] ; 0x5e + b360: f8bd 305a ldrh.w r3, [sp, #90] ; 0x5a + b364: 3101 adds r1, #1 + grad_color = grad_get(dsc, lv_area_get_height(&coords_bg), y - coords_bg.y1); + b366: 1afa subs r2, r7, r3 + b368: 1ac9 subs r1, r1, r3 + b36a: b212 sxth r2, r2 + b36c: 4b0d ldr r3, [pc, #52] ; (b3a4 ) + b36e: b209 sxth r1, r1 + b370: 4650 mov r0, sl + b372: 4798 blx r3 + b374: ee08 0a10 vmov s16, r0 + if(simple_mode && split && + b378: 9b08 ldr r3, [sp, #32] + b37a: 2b00 cmp r3, #0 + b37c: f000 80a3 beq.w b4c6 + b380: 9b0a ldr r3, [sp, #40] ; 0x28 + b382: 2b32 cmp r3, #50 ; 0x32 + b384: dc1c bgt.n b3c0 + b386: e09e b.n b4c6 + mask_res = LV_DRAW_MASK_RES_FULL_COVER; + b388: 2601 movs r6, #1 + b38a: e7dc b.n b346 + b38c: 0000efb9 .word 0x0000efb9 + b390: 00009761 .word 0x00009761 + b394: 000061f1 .word 0x000061f1 + b398: 00009915 .word 0x00009915 + b39c: 00009711 .word 0x00009711 + b3a0: 0000eeb5 .word 0x0000eeb5 + b3a4: 00009971 .word 0x00009971 + b3a8: 0000eb69 .word 0x0000eb69 + b3ac: 0000f075 .word 0x0000f075 + if(simple_mode && split && + b3b0: 9b08 ldr r3, [sp, #32] + b3b2: 2b00 cmp r3, #0 + b3b4: f000 84a2 beq.w bcfc + b3b8: 9b0a ldr r3, [sp, #40] ; 0x28 + b3ba: 2b32 cmp r3, #50 ; 0x32 + b3bc: f340 849e ble.w bcfc + (y < coords_bg.y1 + rout + 1 || + b3c0: f9bd 305a ldrsh.w r3, [sp, #90] ; 0x5a + b3c4: 4423 add r3, r4 + if(simple_mode && split && + b3c6: 429f cmp r7, r3 + b3c8: dd04 ble.n b3d4 + y > coords_bg.y2 - rout - 1)) { + b3ca: f9bd 305e ldrsh.w r3, [sp, #94] ; 0x5e + b3ce: 1b1b subs r3, r3, r4 + (y < coords_bg.y1 + rout + 1 || + b3d0: 429f cmp r7, r3 + b3d2: db5a blt.n b48a + fill_area2.x1 = coords_bg.x1; + b3d4: f9bd 3058 ldrsh.w r3, [sp, #88] ; 0x58 + b3d8: f8ad 3078 strh.w r3, [sp, #120] ; 0x78 + fill_area2.x2 = coords_bg.x1 + rout - 1; + b3dc: 3b01 subs r3, #1 + b3de: fa13 f384 uxtah r3, r3, r4 + b3e2: f8ad 307c strh.w r3, [sp, #124] ; 0x7c + fill_area2.y1 = fill_area.y1; + b3e6: f8bd 306a ldrh.w r3, [sp, #106] ; 0x6a + b3ea: f8ad 307a strh.w r3, [sp, #122] ; 0x7a + fill_area2.y2 = fill_area.y2; + b3ee: f8bd 306e ldrh.w r3, [sp, #110] ; 0x6e + b3f2: f8ad 307e strh.w r3, [sp, #126] ; 0x7e + _lv_blend_fill(clip, &fill_area2, + b3f6: f89a 300d ldrb.w r3, [sl, #13] + b3fa: 4f9e ldr r7, [pc, #632] ; (b674 ) + b3fc: 9600 str r6, [sp, #0] + fill_area2.x2 = coords_bg.x1 + rout - 1; + b3fe: b2a2 uxth r2, r4 + _lv_blend_fill(clip, &fill_area2, + b400: e9cd 9301 strd r9, r3, [sp, #4] + fill_area2.x2 = coords_bg.x1 + rout - 1; + b404: 9209 str r2, [sp, #36] ; 0x24 + _lv_blend_fill(clip, &fill_area2, + b406: 462b mov r3, r5 + b408: ee18 2a10 vmov r2, s16 + b40c: a91e add r1, sp, #120 ; 0x78 + b40e: 4640 mov r0, r8 + b410: 47b8 blx r7 + if(dsc->bg_grad_dir == LV_GRAD_DIR_VER) { + b412: f89a 2006 ldrb.w r2, [sl, #6] + b416: 2a01 cmp r2, #1 + b418: d115 bne.n b446 + fill_area2.x1 = coords_bg.x1 + rout; + b41a: 9909 ldr r1, [sp, #36] ; 0x24 + b41c: f8bd 3058 ldrh.w r3, [sp, #88] ; 0x58 + b420: 440b add r3, r1 + b422: f8ad 3078 strh.w r3, [sp, #120] ; 0x78 + fill_area2.x2 = coords_bg.x2 - rout; + b426: f8bd 305c ldrh.w r3, [sp, #92] ; 0x5c + b42a: 1a5b subs r3, r3, r1 + b42c: f8ad 307c strh.w r3, [sp, #124] ; 0x7c + _lv_blend_fill(clip, &fill_area2, + b430: f89a 300d ldrb.w r3, [sl, #13] + b434: 9200 str r2, [sp, #0] + b436: e9cd 9301 strd r9, r3, [sp, #4] + b43a: ee18 2a10 vmov r2, s16 + b43e: 2300 movs r3, #0 + b440: a91e add r1, sp, #120 ; 0x78 + b442: 4640 mov r0, r8 + b444: 47b8 blx r7 + fill_area2.x1 = coords_bg.x2 - rout + 1; + b446: f9bd 305c ldrsh.w r3, [sp, #92] ; 0x5c + b44a: 9909 ldr r1, [sp, #36] ; 0x24 + fill_area2.x2 = coords_bg.x2; + b44c: f8ad 307c strh.w r3, [sp, #124] ; 0x7c + fill_area2.x1 = coords_bg.x2 - rout + 1; + b450: 1c5a adds r2, r3, #1 + b452: 1a52 subs r2, r2, r1 + b454: f8ad 2078 strh.w r2, [sp, #120] ; 0x78 + int32_t mask_ofs = (coords_bg.x2 - rout + 1) - (vdb->area.x1 + draw_area.x1); + b458: 9a05 ldr r2, [sp, #20] + b45a: f9bd 1060 ldrsh.w r1, [sp, #96] ; 0x60 + b45e: f9b2 2010 ldrsh.w r2, [r2, #16] + b462: 1b1b subs r3, r3, r4 + b464: 440a add r2, r1 + b466: 3301 adds r3, #1 + b468: 1a9b subs r3, r3, r2 + _lv_blend_fill(clip, &fill_area2, + b46a: f89a 200d ldrb.w r2, [sl, #13] + b46e: 9600 str r6, [sp, #0] + b470: e9cd 9201 strd r9, r2, [sp, #4] + b474: ee18 2a10 vmov r2, s16 + b478: 2b00 cmp r3, #0 + b47a: bfac ite ge + b47c: 18eb addge r3, r5, r3 + b47e: 1c2b addlt r3, r5, #0 + b480: a91e add r1, sp, #120 ; 0x78 + _lv_blend_fill(clip, &fill_area, + b482: 4e7c ldr r6, [pc, #496] ; (b674 ) + b484: 4640 mov r0, r8 + b486: 47b0 blx r6 + b488: e00d b.n b4a6 + if(dsc->bg_grad_dir == LV_GRAD_DIR_HOR) { + b48a: 9b09 ldr r3, [sp, #36] ; 0x24 + b48c: 2b02 cmp r3, #2 + b48e: d116 bne.n b4be + _lv_blend_map(clip, &fill_area, grad_map, mask_buf, mask_res, opa, dsc->bg_blend_mode); + b490: f89a 300d ldrb.w r3, [sl, #13] + b494: 9a06 ldr r2, [sp, #24] + b496: 9600 str r6, [sp, #0] + b498: e9cd 9301 strd r9, r3, [sp, #4] + b49c: 4e76 ldr r6, [pc, #472] ; (b678 ) + b49e: 462b mov r3, r5 + b4a0: a91a add r1, sp, #104 ; 0x68 + b4a2: 4640 mov r0, r8 + b4a4: 47b0 blx r6 + fill_area.y1++; + b4a6: f8bd 306a ldrh.w r3, [sp, #106] ; 0x6a + for(h = draw_area.y1; h <= draw_area.y2; h++) { + b4aa: 9a07 ldr r2, [sp, #28] + fill_area.y1++; + b4ac: 3301 adds r3, #1 + b4ae: f8ad 306a strh.w r3, [sp, #106] ; 0x6a + fill_area.y2++; + b4b2: f8bd 306e ldrh.w r3, [sp, #110] ; 0x6e + b4b6: 3301 adds r3, #1 + b4b8: b21b sxth r3, r3 + for(h = draw_area.y1; h <= draw_area.y2; h++) { + b4ba: 3201 adds r2, #1 + b4bc: e693 b.n b1e6 + else if(dsc->bg_grad_dir == LV_GRAD_DIR_VER) { + b4be: 9b09 ldr r3, [sp, #36] ; 0x24 + b4c0: 2b01 cmp r3, #1 + b4c2: f040 841f bne.w bd04 + _lv_blend_fill(clip, &fill_area, + b4c6: f89a 300d ldrb.w r3, [sl, #13] + b4ca: 9600 str r6, [sp, #0] + b4cc: e9cd 9301 strd r9, r3, [sp, #4] + b4d0: ee18 2a10 vmov r2, s16 + b4d4: 462b mov r3, r5 + b4d6: a91a add r1, sp, #104 ; 0x68 + b4d8: e7d3 b.n b482 + img_h = header.h; + b4da: f8bd 3096 ldrh.w r3, [sp, #150] ; 0x96 + img_w = header.w; + b4de: 9d25 ldr r5, [sp, #148] ; 0x94 + img_h = header.h; + b4e0: f3c3 174a ubfx r7, r3, #5, #11 + lv_draw_img_dsc_init(&img_dsc); + b4e4: a81a add r0, sp, #104 ; 0x68 + b4e6: 4b65 ldr r3, [pc, #404] ; (b67c ) + b4e8: 4798 blx r3 + img_dsc.opa = dsc->pattern_opa; + b4ea: f89a 3036 ldrb.w r3, [sl, #54] ; 0x36 + b4ee: f88d 3068 strb.w r3, [sp, #104] ; 0x68 + img_dsc.recolor_opa = dsc->pattern_recolor_opa; + b4f2: f89a 3037 ldrb.w r3, [sl, #55] ; 0x37 + b4f6: f88d 3072 strb.w r3, [sp, #114] ; 0x72 + img_dsc.recolor = dsc->pattern_recolor; + b4fa: f8ba 3034 ldrh.w r3, [sl, #52] ; 0x34 + b4fe: f8ad 3074 strh.w r3, [sp, #116] ; 0x74 + img_w = header.w; + b502: f3c5 258a ubfx r5, r5, #10, #11 + coords_tmp.y2 = coords_tmp.y1 + img_h - 1; + b506: b2bb uxth r3, r7 + b508: f103 39ff add.w r9, r3, #4294967295 ; 0xffffffff + b50c: 9305 str r3, [sp, #20] + if(dsc->pattern_repeat) { + b50e: f89a 3038 ldrb.w r3, [sl, #56] ; 0x38 + lv_draw_mask_radius_init(&radius_mask_param, coords, dsc->radius, false); + b512: f9ba 2000 ldrsh.w r2, [sl] + if(dsc->pattern_repeat) { + b516: 07db lsls r3, r3, #31 + b518: fa1f f989 uxth.w r9, r9 + b51c: f140 80c6 bpl.w b6ac + lv_draw_mask_radius_init(&radius_mask_param, coords, dsc->radius, false); + b520: 4c57 ldr r4, [pc, #348] ; (b680 ) + b522: 2300 movs r3, #0 + b524: 4659 mov r1, fp + b526: a825 add r0, sp, #148 ; 0x94 + b528: 47a0 blx r4 + int16_t radius_mask_id = lv_draw_mask_add(&radius_mask_param, NULL); + b52a: 4b56 ldr r3, [pc, #344] ; (b684 ) + b52c: 2100 movs r1, #0 + b52e: a825 add r0, sp, #148 ; 0x94 + b530: 4798 blx r3 + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + b532: f8bb 4004 ldrh.w r4, [fp, #4] + b536: f8bb 3000 ldrh.w r3, [fp] + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + b53a: f8bb 2006 ldrh.w r2, [fp, #6] + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + b53e: 3401 adds r4, #1 + b540: 1ae4 subs r4, r4, r3 + int32_t ofs_x = (lv_area_get_width(coords) - (lv_area_get_width(coords) / img_w) * img_w) / 2; + b542: b224 sxth r4, r4 + b544: fb94 f3f5 sdiv r3, r4, r5 + b548: fb05 4413 mls r4, r5, r3, r4 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + b54c: f8bb 3002 ldrh.w r3, [fp, #2] + b550: 3201 adds r2, #1 + b552: 1ad2 subs r2, r2, r3 + int32_t ofs_y = (lv_area_get_height(coords) - (lv_area_get_height(coords) / img_h) * img_h) / 2; + b554: b212 sxth r2, r2 + b556: fb92 f1f7 sdiv r1, r2, r7 + b55a: fb07 2211 mls r2, r7, r1, r2 + b55e: eb02 72d2 add.w r2, r2, r2, lsr #31 + coords_tmp.y1 = coords->y1 - ofs_y; + b562: eba3 0362 sub.w r3, r3, r2, asr #1 + b566: b29b uxth r3, r3 + int32_t ofs_x = (lv_area_get_width(coords) - (lv_area_get_width(coords) / img_w) * img_w) / 2; + b568: eb04 74d4 add.w r4, r4, r4, lsr #31 + int16_t radius_mask_id = lv_draw_mask_add(&radius_mask_param, NULL); + b56c: ee08 0a10 vmov s16, r0 + coords_tmp.y1 = coords->y1 - ofs_y; + b570: f8ad 3062 strh.w r3, [sp, #98] ; 0x62 + int32_t ofs_x = (lv_area_get_width(coords) - (lv_area_get_width(coords) / img_w) * img_w) / 2; + b574: 1064 asrs r4, r4, #1 + coords_tmp.y2 = coords_tmp.y1 + img_h - 1; + b576: 444b add r3, r9 + for(; coords_tmp.y1 <= coords->y2; coords_tmp.y1 += img_h, coords_tmp.y2 += img_h) { + b578: b21b sxth r3, r3 + b57a: f9bd 2062 ldrsh.w r2, [sp, #98] ; 0x62 + coords_tmp.y2 = coords_tmp.y1 + img_h - 1; + b57e: f8ad 3066 strh.w r3, [sp, #102] ; 0x66 + for(; coords_tmp.y1 <= coords->y2; coords_tmp.y1 += img_h, coords_tmp.y2 += img_h) { + b582: f9bb 3006 ldrsh.w r3, [fp, #6] + b586: 429a cmp r2, r3 + b588: dd3a ble.n b600 + lv_draw_mask_remove_id(radius_mask_id); + b58a: ee18 0a10 vmov r0, s16 + lv_draw_mask_remove_id(radius_mask_id); + b58e: 4b3e ldr r3, [pc, #248] ; (b688 ) + b590: 4798 blx r3 + b592: f7ff b955 b.w a840 + else if(src_type == LV_IMG_SRC_SYMBOL) { + b596: 2802 cmp r0, #2 + b598: d121 bne.n b5de + lv_draw_label_dsc_init(&label_dsc); + b59a: 4b3c ldr r3, [pc, #240] ; (b68c ) + _lv_txt_get_size(&s, dsc->pattern_image, label_dsc.font, label_dsc.letter_space, label_dsc.line_space, LV_COORD_MAX, + b59c: 4c3c ldr r4, [pc, #240] ; (b690 ) + lv_draw_label_dsc_init(&label_dsc); + b59e: a81e add r0, sp, #120 ; 0x78 + b5a0: 4798 blx r3 + label_dsc.color = dsc->pattern_recolor; + b5a2: f8ba 3034 ldrh.w r3, [sl, #52] ; 0x34 + b5a6: f8ad 3078 strh.w r3, [sp, #120] ; 0x78 + label_dsc.opa = dsc->pattern_opa; + b5aa: f89a 3036 ldrb.w r3, [sl, #54] ; 0x36 + b5ae: f88d 3080 strb.w r3, [sp, #128] ; 0x80 + _lv_txt_get_size(&s, dsc->pattern_image, label_dsc.font, label_dsc.letter_space, label_dsc.line_space, LV_COORD_MAX, + b5b2: 2100 movs r1, #0 + b5b4: f647 4318 movw r3, #31768 ; 0x7c18 + label_dsc.font = dsc->pattern_font; + b5b8: f8da 2030 ldr.w r2, [sl, #48] ; 0x30 + b5bc: 921f str r2, [sp, #124] ; 0x7c + _lv_txt_get_size(&s, dsc->pattern_image, label_dsc.font, label_dsc.letter_space, label_dsc.line_space, LV_COORD_MAX, + b5be: e9cd 3101 strd r3, r1, [sp, #4] + b5c2: f9bd 3082 ldrsh.w r3, [sp, #130] ; 0x82 + b5c6: 9300 str r3, [sp, #0] + b5c8: f8da 102c ldr.w r1, [sl, #44] ; 0x2c + b5cc: f9bd 3084 ldrsh.w r3, [sp, #132] ; 0x84 + b5d0: a825 add r0, sp, #148 ; 0x94 + b5d2: 47a0 blx r4 + img_w = s.x; + b5d4: f9bd 5094 ldrsh.w r5, [sp, #148] ; 0x94 + img_h = s.y; + b5d8: f9bd 7096 ldrsh.w r7, [sp, #150] ; 0x96 + b5dc: e793 b.n b506 + LV_LOG_WARN("lv_img_design: image source type is unknown"); + b5de: 4b2d ldr r3, [pc, #180] ; (b694 ) + b5e0: 9300 str r3, [sp, #0] + b5e2: 492d ldr r1, [pc, #180] ; (b698 ) + b5e4: 4b2d ldr r3, [pc, #180] ; (b69c ) + b5e6: 4c2e ldr r4, [pc, #184] ; (b6a0 ) + b5e8: f240 52ae movw r2, #1454 ; 0x5ae + b5ec: 2002 movs r0, #2 + b5ee: 47a0 blx r4 + lv_draw_img(coords, clip, NULL, NULL); + b5f0: 2300 movs r3, #0 + b5f2: 4c2c ldr r4, [pc, #176] ; (b6a4 ) + b5f4: 461a mov r2, r3 + b5f6: 4641 mov r1, r8 + b5f8: 4658 mov r0, fp + b5fa: 47a0 blx r4 + return; + b5fc: f7ff b920 b.w a840 + coords_tmp.x1 = coords->x1 - ofs_x; + b600: f8bb 3000 ldrh.w r3, [fp] + coords_tmp.x2 = coords_tmp.x1 + img_w - 1; + b604: fa1f f985 uxth.w r9, r5 + coords_tmp.x1 = coords->x1 - ofs_x; + b608: 1b1b subs r3, r3, r4 + b60a: b29b uxth r3, r3 + coords_tmp.x2 = coords_tmp.x1 + img_w - 1; + b60c: f109 32ff add.w r2, r9, #4294967295 ; 0xffffffff + coords_tmp.x1 = coords->x1 - ofs_x; + b610: f8ad 3060 strh.w r3, [sp, #96] ; 0x60 + coords_tmp.x2 = coords_tmp.x1 + img_w - 1; + b614: 4413 add r3, r2 + for(; coords_tmp.x1 <= coords->x2; coords_tmp.x1 += img_w, coords_tmp.x2 += img_w) { + b616: b21b sxth r3, r3 + b618: f9bd 2060 ldrsh.w r2, [sp, #96] ; 0x60 + coords_tmp.x2 = coords_tmp.x1 + img_w - 1; + b61c: f8ad 3064 strh.w r3, [sp, #100] ; 0x64 + for(; coords_tmp.x1 <= coords->x2; coords_tmp.x1 += img_w, coords_tmp.x2 += img_w) { + b620: f9bb 3004 ldrsh.w r3, [fp, #4] + b624: 429a cmp r2, r3 + b626: dd09 ble.n b63c + for(; coords_tmp.y1 <= coords->y2; coords_tmp.y1 += img_h, coords_tmp.y2 += img_h) { + b628: f8bd 3062 ldrh.w r3, [sp, #98] ; 0x62 + b62c: 9a05 ldr r2, [sp, #20] + b62e: 4413 add r3, r2 + b630: f8ad 3062 strh.w r3, [sp, #98] ; 0x62 + b634: f8bd 3066 ldrh.w r3, [sp, #102] ; 0x66 + b638: 4413 add r3, r2 + b63a: e79d b.n b578 + if(src_type == LV_IMG_SRC_SYMBOL) lv_draw_label(&coords_tmp, clip, &label_dsc, dsc->pattern_image, NULL); + b63c: 2e02 cmp r6, #2 + b63e: f8da 202c ldr.w r2, [sl, #44] ; 0x2c + b642: d110 bne.n b666 + b644: 2300 movs r3, #0 + b646: 9300 str r3, [sp, #0] + b648: 4f17 ldr r7, [pc, #92] ; (b6a8 ) + b64a: 4613 mov r3, r2 + b64c: 4641 mov r1, r8 + b64e: aa1e add r2, sp, #120 ; 0x78 + b650: a818 add r0, sp, #96 ; 0x60 + b652: 47b8 blx r7 + for(; coords_tmp.x1 <= coords->x2; coords_tmp.x1 += img_w, coords_tmp.x2 += img_w) { + b654: f8bd 3060 ldrh.w r3, [sp, #96] ; 0x60 + b658: 444b add r3, r9 + b65a: f8ad 3060 strh.w r3, [sp, #96] ; 0x60 + b65e: f8bd 3064 ldrh.w r3, [sp, #100] ; 0x64 + b662: 444b add r3, r9 + b664: e7d7 b.n b616 + else lv_draw_img(&coords_tmp, clip, dsc->pattern_image, &img_dsc); + b666: 4f0f ldr r7, [pc, #60] ; (b6a4 ) + b668: ab1a add r3, sp, #104 ; 0x68 + b66a: 4641 mov r1, r8 + b66c: a818 add r0, sp, #96 ; 0x60 + b66e: 47b8 blx r7 + b670: e7f0 b.n b654 + b672: bf00 nop + b674: 000061f1 .word 0x000061f1 + b678: 000067fd .word 0x000067fd + b67c: 00007559 .word 0x00007559 + b680: 00009915 .word 0x00009915 + b684: 00009711 .word 0x00009711 + b688: 000097a1 .word 0x000097a1 + b68c: 00007845 .word 0x00007845 + b690: 0001019d .word 0x0001019d + b694: 0001fdc3 .word 0x0001fdc3 + b698: 0001fd6f .word 0x0001fd6f + b69c: 0001fdf2 .word 0x0001fdf2 + b6a0: 0000e8e9 .word 0x0000e8e9 + b6a4: 000075c1 .word 0x000075c1 + b6a8: 00007875 .word 0x00007875 + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + b6ac: f8bb 1004 ldrh.w r1, [fp, #4] + b6b0: f8bb 4000 ldrh.w r4, [fp] + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + b6b4: f8bb 3006 ldrh.w r3, [fp, #6] + b6b8: f8bb 0002 ldrh.w r0, [fp, #2] + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + b6bc: 3101 adds r1, #1 + b6be: 1b09 subs r1, r1, r4 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + b6c0: 3301 adds r3, #1 + b6c2: 1a1b subs r3, r3, r0 + int32_t obj_w = lv_area_get_width(coords); + b6c4: b209 sxth r1, r1 + coords_tmp.x1 = coords->x1 + (obj_w - img_w) / 2; + b6c6: 1b49 subs r1, r1, r5 + int32_t obj_h = lv_area_get_height(coords); + b6c8: b21b sxth r3, r3 + coords_tmp.x1 = coords->x1 + (obj_w - img_w) / 2; + b6ca: eb01 71d1 add.w r1, r1, r1, lsr #31 + coords_tmp.y1 = coords->y1 + (obj_h - img_h) / 2; + b6ce: 1bdb subs r3, r3, r7 + coords_tmp.x1 = coords->x1 + (obj_w - img_w) / 2; + b6d0: eb04 0461 add.w r4, r4, r1, asr #1 + coords_tmp.y1 = coords->y1 + (obj_h - img_h) / 2; + b6d4: eb03 71d3 add.w r1, r3, r3, lsr #31 + b6d8: eb00 0061 add.w r0, r0, r1, asr #1 + b6dc: b280 uxth r0, r0 + coords_tmp.x1 = coords->x1 + (obj_w - img_w) / 2; + b6de: b2a4 uxth r4, r4 + coords_tmp.x2 = coords_tmp.x1 + img_w - 1; + b6e0: 3d01 subs r5, #1 + coords_tmp.y2 = coords_tmp.y1 + img_h - 1; + b6e2: 4481 add r9, r0 + coords_tmp.x1 = coords->x1 + (obj_w - img_w) / 2; + b6e4: f8ad 4060 strh.w r4, [sp, #96] ; 0x60 + coords_tmp.y2 = coords_tmp.y1 + img_h - 1; + b6e8: fa1f f989 uxth.w r9, r9 + coords_tmp.x2 = coords_tmp.x1 + img_w - 1; + b6ec: 442c add r4, r5 + if(src_type == LV_IMG_SRC_SYMBOL) { + b6ee: 2e02 cmp r6, #2 + coords_tmp.y1 = coords->y1 + (obj_h - img_h) / 2; + b6f0: f8ad 0062 strh.w r0, [sp, #98] ; 0x62 + coords_tmp.x2 = coords_tmp.x1 + img_w - 1; + b6f4: f8ad 4064 strh.w r4, [sp, #100] ; 0x64 + coords_tmp.y2 = coords_tmp.y1 + img_h - 1; + b6f8: f8ad 9066 strh.w r9, [sp, #102] ; 0x66 + if(src_type == LV_IMG_SRC_SYMBOL) { + b6fc: d107 bne.n b70e + coords_tmp.y1 += y_corr; + b6fe: f003 0301 and.w r3, r3, #1 + b702: 4418 add r0, r3 + coords_tmp.y2 += y_corr; + b704: 4499 add r9, r3 + coords_tmp.y1 += y_corr; + b706: f8ad 0062 strh.w r0, [sp, #98] ; 0x62 + coords_tmp.y2 += y_corr; + b70a: f8ad 9066 strh.w r9, [sp, #102] ; 0x66 + if(_lv_area_is_in(&coords_tmp, coords, dsc->radius) == false) { + b70e: 4b94 ldr r3, [pc, #592] ; (b960 ) + b710: 4659 mov r1, fp + b712: a818 add r0, sp, #96 ; 0x60 + b714: 4798 blx r3 + b716: 4604 mov r4, r0 + b718: b9c8 cbnz r0, b74e + lv_draw_mask_radius_init(&radius_mask_param, coords, dsc->radius, false); + b71a: 4603 mov r3, r0 + b71c: f9ba 2000 ldrsh.w r2, [sl] + b720: 4d90 ldr r5, [pc, #576] ; (b964 ) + b722: 4659 mov r1, fp + b724: a825 add r0, sp, #148 ; 0x94 + b726: 47a8 blx r5 + radius_mask_id = lv_draw_mask_add(&radius_mask_param, NULL); + b728: 4621 mov r1, r4 + b72a: 4b8f ldr r3, [pc, #572] ; (b968 ) + b72c: a825 add r0, sp, #148 ; 0x94 + b72e: 4798 blx r3 + b730: 4604 mov r4, r0 + if(src_type == LV_IMG_SRC_SYMBOL) lv_draw_label(&coords_tmp, clip, &label_dsc, dsc->pattern_image, NULL); + b732: 2e02 cmp r6, #2 + b734: f8da 202c ldr.w r2, [sl, #44] ; 0x2c + b738: d10c bne.n b754 + b73a: 2300 movs r3, #0 + b73c: 9300 str r3, [sp, #0] + b73e: 4d8b ldr r5, [pc, #556] ; (b96c ) + b740: 4613 mov r3, r2 + b742: 4641 mov r1, r8 + b744: aa1e add r2, sp, #120 ; 0x78 + b746: a818 add r0, sp, #96 ; 0x60 + b748: 47a8 blx r5 + lv_draw_mask_remove_id(radius_mask_id); + b74a: 4620 mov r0, r4 + b74c: e71f b.n b58e + int16_t radius_mask_id = LV_MASK_ID_INV; + b74e: f04f 34ff mov.w r4, #4294967295 ; 0xffffffff + b752: e7ee b.n b732 + else lv_draw_img(&coords_tmp, clip, dsc->pattern_image, &img_dsc); + b754: 4d86 ldr r5, [pc, #536] ; (b970 ) + b756: ab1a add r3, sp, #104 ; 0x68 + b758: 4641 mov r1, r8 + b75a: a818 add r0, sp, #96 ; 0x60 + b75c: 47a8 blx r5 + b75e: e7f4 b.n b74a + if(other_mask_cnt) simple_mode = false; + b760: 2300 movs r3, #0 + b762: f7ff b8ba b.w a8da + int16_t mask_rout_id = LV_MASK_ID_INV; + b766: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + b76a: 930c str r3, [sp, #48] ; 0x30 + b76c: f7ff b8dc b.w a928 + _lv_memset_ff(mask_buf, draw_area_w); + b770: 4b80 ldr r3, [pc, #512] ; (b974 ) + mask_res = lv_draw_mask_apply(mask_buf, vdb->area.x1 + draw_area.x1, vdb->area.y1 + h, draw_area_w); + b772: 4f81 ldr r7, [pc, #516] ; (b978 ) + _lv_memset_ff(mask_buf, draw_area_w); + b774: 4649 mov r1, r9 + b776: 4620 mov r0, r4 + b778: 4798 blx r3 + mask_res = lv_draw_mask_apply(mask_buf, vdb->area.x1 + draw_area.x1, vdb->area.y1 + h, draw_area_w); + b77a: 9b06 ldr r3, [sp, #24] + b77c: 8a5a ldrh r2, [r3, #18] + b77e: 8a19 ldrh r1, [r3, #16] + b780: f8bd 3050 ldrh.w r3, [sp, #80] ; 0x50 + b784: 4432 add r2, r6 + b786: 4419 add r1, r3 + b788: b212 sxth r2, r2 + b78a: 464b mov r3, r9 + b78c: b209 sxth r1, r1 + b78e: 4620 mov r0, r4 + b790: 47b8 blx r7 + fill_area2.y1 = fill_area.y1; + b792: f8bd 3062 ldrh.w r3, [sp, #98] ; 0x62 + b796: f8ad 306a strh.w r3, [sp, #106] ; 0x6a + fill_area2.y2 = fill_area.y2; + b79a: f8bd 3066 ldrh.w r3, [sp, #102] ; 0x66 + b79e: f8ad 306e strh.w r3, [sp, #110] ; 0x6e + fill_area2.x1 = coords->x1; + b7a2: f9bb 3000 ldrsh.w r3, [fp] + b7a6: f8ad 3068 strh.w r3, [sp, #104] ; 0x68 + fill_area2.x2 = coords->x1 + rout - 1; + b7aa: 3b01 subs r3, #1 + b7ac: 442b add r3, r5 + b7ae: f8ad 306c strh.w r3, [sp, #108] ; 0x6c + _lv_blend_fill(clip, &fill_area2, color, mask_buf, mask_res, opa, blend_mode); + b7b2: 9b07 ldr r3, [sp, #28] + b7b4: 9302 str r3, [sp, #8] + b7b6: 9b05 ldr r3, [sp, #20] + mask_res = lv_draw_mask_apply(mask_buf, vdb->area.x1 + draw_area.x1, vdb->area.y1 + h, draw_area_w); + b7b8: 900b str r0, [sp, #44] ; 0x2c + _lv_blend_fill(clip, &fill_area2, color, mask_buf, mask_res, opa, blend_mode); + b7ba: ee18 2a10 vmov r2, s16 + b7be: 9301 str r3, [sp, #4] + b7c0: 9000 str r0, [sp, #0] + b7c2: 4623 mov r3, r4 + b7c4: a91a add r1, sp, #104 ; 0x68 + b7c6: 4f6d ldr r7, [pc, #436] ; (b97c ) + b7c8: 4640 mov r0, r8 + b7ca: 47b8 blx r7 + if(fill_area2.y2 < coords->y1 + dsc->border_width) { + b7cc: f9bb 3002 ldrsh.w r3, [fp, #2] + b7d0: f9ba 1010 ldrsh.w r1, [sl, #16] + b7d4: f9bd 206e ldrsh.w r2, [sp, #110] ; 0x6e + b7d8: 440b add r3, r1 + b7da: 429a cmp r2, r3 + b7dc: da15 bge.n b80a + fill_area2.x1 = coords->x1 + rout; + b7de: f8bb 3000 ldrh.w r3, [fp] + b7e2: 442b add r3, r5 + b7e4: f8ad 3068 strh.w r3, [sp, #104] ; 0x68 + fill_area2.x2 = coords->x2 - rout; + b7e8: f8bb 3004 ldrh.w r3, [fp, #4] + b7ec: 1b5b subs r3, r3, r5 + b7ee: f8ad 306c strh.w r3, [sp, #108] ; 0x6c + _lv_blend_fill(clip, &fill_area2, color, NULL, LV_DRAW_MASK_RES_FULL_COVER, opa, blend_mode); + b7f2: 9b07 ldr r3, [sp, #28] + b7f4: 9302 str r3, [sp, #8] + b7f6: 9b05 ldr r3, [sp, #20] + b7f8: 9301 str r3, [sp, #4] + b7fa: 2301 movs r3, #1 + b7fc: 9300 str r3, [sp, #0] + b7fe: ee18 2a10 vmov r2, s16 + b802: 2300 movs r3, #0 + b804: a91a add r1, sp, #104 ; 0x68 + b806: 4640 mov r0, r8 + b808: 47b8 blx r7 + fill_area2.x1 = coords->x2 - rout + 1; + b80a: f9bb 3004 ldrsh.w r3, [fp, #4] + fill_area2.x2 = coords->x2; + b80e: f8ad 306c strh.w r3, [sp, #108] ; 0x6c + fill_area2.x1 = coords->x2 - rout + 1; + b812: 1c5a adds r2, r3, #1 + b814: 1b52 subs r2, r2, r5 + b816: f8ad 2068 strh.w r2, [sp, #104] ; 0x68 + int32_t mask_ofs = (coords->x2 - rout + 1) - (vdb->area.x1 + draw_area.x1); + b81a: 9a09 ldr r2, [sp, #36] ; 0x24 + b81c: f9bd 1050 ldrsh.w r1, [sp, #80] ; 0x50 + _lv_blend_fill(clip, &fill_area2, color, mask_buf + mask_ofs, mask_res, opa, blend_mode); + b820: 4f56 ldr r7, [pc, #344] ; (b97c ) + int32_t mask_ofs = (coords->x2 - rout + 1) - (vdb->area.x1 + draw_area.x1); + b822: 1a9b subs r3, r3, r2 + b824: 9a06 ldr r2, [sp, #24] + b826: f9b2 2010 ldrsh.w r2, [r2, #16] + b82a: 3301 adds r3, #1 + b82c: 440a add r2, r1 + b82e: 1a9b subs r3, r3, r2 + _lv_blend_fill(clip, &fill_area2, color, mask_buf + mask_ofs, mask_res, opa, blend_mode); + b830: 9a07 ldr r2, [sp, #28] + b832: 9202 str r2, [sp, #8] + b834: 9a05 ldr r2, [sp, #20] + b836: 9201 str r2, [sp, #4] + b838: 9a0b ldr r2, [sp, #44] ; 0x2c + b83a: 9200 str r2, [sp, #0] + b83c: 2b00 cmp r3, #0 + b83e: bfac ite ge + b840: 18e3 addge r3, r4, r3 + b842: 1c23 addlt r3, r4, #0 + b844: ee18 2a10 vmov r2, s16 + b848: a91a add r1, sp, #104 ; 0x68 + b84a: 4640 mov r0, r8 + b84c: 47b8 blx r7 + fill_area.y1++; + b84e: f8bd 3062 ldrh.w r3, [sp, #98] ; 0x62 + b852: 3301 adds r3, #1 + b854: f8ad 3062 strh.w r3, [sp, #98] ; 0x62 + fill_area.y2++; + b858: f8bd 3066 ldrh.w r3, [sp, #102] ; 0x66 + b85c: 3301 adds r3, #1 + b85e: f8ad 3066 strh.w r3, [sp, #102] ; 0x66 + for(h = draw_area.y1; h <= upper_corner_end; h++) { + b862: 3601 adds r6, #1 + b864: f7ff b902 b.w aa6c + _lv_memset_ff(mask_buf, draw_area_w); + b868: 4b42 ldr r3, [pc, #264] ; (b974 ) + mask_res = lv_draw_mask_apply(mask_buf, vdb->area.x1 + draw_area.x1, vdb->area.y1 + h, draw_area_w); + b86a: 4f43 ldr r7, [pc, #268] ; (b978 ) + _lv_memset_ff(mask_buf, draw_area_w); + b86c: 4649 mov r1, r9 + b86e: 4620 mov r0, r4 + b870: 4798 blx r3 + mask_res = lv_draw_mask_apply(mask_buf, vdb->area.x1 + draw_area.x1, vdb->area.y1 + h, draw_area_w); + b872: 9b06 ldr r3, [sp, #24] + b874: 8a5a ldrh r2, [r3, #18] + b876: 8a19 ldrh r1, [r3, #16] + b878: f8bd 3050 ldrh.w r3, [sp, #80] ; 0x50 + b87c: 4432 add r2, r6 + b87e: 4419 add r1, r3 + b880: b212 sxth r2, r2 + b882: 464b mov r3, r9 + b884: b209 sxth r1, r1 + b886: 4620 mov r0, r4 + b888: 47b8 blx r7 + fill_area2.x1 = coords->x1; + b88a: f9bb 3000 ldrsh.w r3, [fp] + b88e: f8ad 3068 strh.w r3, [sp, #104] ; 0x68 + fill_area2.x2 = coords->x1 + rout - 1; + b892: 3b01 subs r3, #1 + b894: 442b add r3, r5 + b896: f8ad 306c strh.w r3, [sp, #108] ; 0x6c + fill_area2.y1 = fill_area.y1; + b89a: f8bd 3062 ldrh.w r3, [sp, #98] ; 0x62 + b89e: f8ad 306a strh.w r3, [sp, #106] ; 0x6a + fill_area2.y2 = fill_area.y2; + b8a2: f8bd 3066 ldrh.w r3, [sp, #102] ; 0x66 + b8a6: f8ad 306e strh.w r3, [sp, #110] ; 0x6e + _lv_blend_fill(clip, &fill_area2, color, mask_buf, mask_res, opa, blend_mode); + b8aa: 9b07 ldr r3, [sp, #28] + b8ac: 9302 str r3, [sp, #8] + b8ae: 9b05 ldr r3, [sp, #20] + mask_res = lv_draw_mask_apply(mask_buf, vdb->area.x1 + draw_area.x1, vdb->area.y1 + h, draw_area_w); + b8b0: 900a str r0, [sp, #40] ; 0x28 + _lv_blend_fill(clip, &fill_area2, color, mask_buf, mask_res, opa, blend_mode); + b8b2: ee18 2a10 vmov r2, s16 + b8b6: 9301 str r3, [sp, #4] + b8b8: 9000 str r0, [sp, #0] + b8ba: 4623 mov r3, r4 + b8bc: a91a add r1, sp, #104 ; 0x68 + b8be: 4f2f ldr r7, [pc, #188] ; (b97c ) + b8c0: 4640 mov r0, r8 + b8c2: 47b8 blx r7 + if(fill_area2.y2 > coords->y2 - dsc->border_width) { + b8c4: f9bb 3006 ldrsh.w r3, [fp, #6] + b8c8: f9ba 1010 ldrsh.w r1, [sl, #16] + b8cc: f9bd 206e ldrsh.w r2, [sp, #110] ; 0x6e + b8d0: 1a5b subs r3, r3, r1 + b8d2: 429a cmp r2, r3 + b8d4: dd15 ble.n b902 + fill_area2.x1 = coords->x1 + rout; + b8d6: f8bb 3000 ldrh.w r3, [fp] + b8da: 442b add r3, r5 + b8dc: f8ad 3068 strh.w r3, [sp, #104] ; 0x68 + fill_area2.x2 = coords->x2 - rout; + b8e0: f8bb 3004 ldrh.w r3, [fp, #4] + b8e4: 1b5b subs r3, r3, r5 + b8e6: f8ad 306c strh.w r3, [sp, #108] ; 0x6c + _lv_blend_fill(clip, &fill_area2, color, NULL, LV_DRAW_MASK_RES_FULL_COVER, opa, blend_mode); + b8ea: 9b07 ldr r3, [sp, #28] + b8ec: 9302 str r3, [sp, #8] + b8ee: 9b05 ldr r3, [sp, #20] + b8f0: 9301 str r3, [sp, #4] + b8f2: 2301 movs r3, #1 + b8f4: 9300 str r3, [sp, #0] + b8f6: ee18 2a10 vmov r2, s16 + b8fa: 2300 movs r3, #0 + b8fc: a91a add r1, sp, #104 ; 0x68 + b8fe: 4640 mov r0, r8 + b900: 47b8 blx r7 + fill_area2.x1 = coords->x2 - rout + 1; + b902: f9bb 3004 ldrsh.w r3, [fp, #4] + fill_area2.x2 = coords->x2; + b906: f8ad 306c strh.w r3, [sp, #108] ; 0x6c + fill_area2.x1 = coords->x2 - rout + 1; + b90a: 1c5a adds r2, r3, #1 + b90c: 1b52 subs r2, r2, r5 + b90e: f8ad 2068 strh.w r2, [sp, #104] ; 0x68 + int32_t mask_ofs = (coords->x2 - rout + 1) - (vdb->area.x1 + draw_area.x1); + b912: 9a09 ldr r2, [sp, #36] ; 0x24 + b914: f9bd 1050 ldrsh.w r1, [sp, #80] ; 0x50 + _lv_blend_fill(clip, &fill_area2, color, mask_buf + mask_ofs, mask_res, opa, blend_mode); + b918: 4f18 ldr r7, [pc, #96] ; (b97c ) + int32_t mask_ofs = (coords->x2 - rout + 1) - (vdb->area.x1 + draw_area.x1); + b91a: 1a9b subs r3, r3, r2 + b91c: 9a06 ldr r2, [sp, #24] + b91e: f9b2 2010 ldrsh.w r2, [r2, #16] + b922: 3301 adds r3, #1 + b924: 440a add r2, r1 + b926: 1a9b subs r3, r3, r2 + _lv_blend_fill(clip, &fill_area2, color, mask_buf + mask_ofs, mask_res, opa, blend_mode); + b928: 9a07 ldr r2, [sp, #28] + b92a: 9202 str r2, [sp, #8] + b92c: 9a05 ldr r2, [sp, #20] + b92e: 9201 str r2, [sp, #4] + b930: 9a0a ldr r2, [sp, #40] ; 0x28 + b932: 9200 str r2, [sp, #0] + b934: 2b00 cmp r3, #0 + b936: bfac ite ge + b938: 18e3 addge r3, r4, r3 + b93a: 1c23 addlt r3, r4, #0 + b93c: ee18 2a10 vmov r2, s16 + b940: a91a add r1, sp, #104 ; 0x68 + b942: 4640 mov r0, r8 + b944: 47b8 blx r7 + fill_area.y1++; + b946: f8bd 3062 ldrh.w r3, [sp, #98] ; 0x62 + b94a: 3301 adds r3, #1 + b94c: f8ad 3062 strh.w r3, [sp, #98] ; 0x62 + fill_area.y2++; + b950: f8bd 3066 ldrh.w r3, [sp, #102] ; 0x66 + b954: 3301 adds r3, #1 + b956: f8ad 3066 strh.w r3, [sp, #102] ; 0x66 + for(h = lower_corner_end; h <= draw_area.y2; h++) { + b95a: 3601 adds r6, #1 + b95c: f7ff b8a2 b.w aaa4 + b960: 0000e091 .word 0x0000e091 + b964: 00009915 .word 0x00009915 + b968: 00009711 .word 0x00009711 + b96c: 00007875 .word 0x00007875 + b970: 000075c1 .word 0x000075c1 + b974: 0000f075 .word 0x0000f075 + b978: 00009761 .word 0x00009761 + b97c: 000061f1 .word 0x000061f1 + fill_area.y1 = disp_area->y1 + draw_area.y1; + b980: f8ad 3062 strh.w r3, [sp, #98] ; 0x62 + fill_area.y2 = fill_area.y1; + b984: f8ad 3066 strh.w r3, [sp, #102] ; 0x66 + if(dsc->border_side == LV_BORDER_SIDE_LEFT) fill_area.x2 = coords->x1 + corner_size; + b988: f9ba 3012 ldrsh.w r3, [sl, #18] + fill_area.x1 = coords->x1; + b98c: f8ad 1060 strh.w r1, [sp, #96] ; 0x60 + if(dsc->border_side == LV_BORDER_SIDE_LEFT) fill_area.x2 = coords->x1 + corner_size; + b990: 2b04 cmp r3, #4 + fill_area.x2 = coords->x2; + b992: f8ad 2064 strh.w r2, [sp, #100] ; 0x64 + if(dsc->border_side == LV_BORDER_SIDE_LEFT) fill_area.x2 = coords->x1 + corner_size; + b996: d15e bne.n ba56 + b998: 9a08 ldr r2, [sp, #32] + b99a: 4411 add r1, r2 + b99c: f8ad 1064 strh.w r1, [sp, #100] ; 0x64 + volatile bool top_only = false; + b9a0: 2200 movs r2, #0 + if(dsc->border_side == LV_BORDER_SIDE_TOP) top_only = true; + b9a2: 2b02 cmp r3, #2 + volatile bool top_only = false; + b9a4: f88d 203e strb.w r2, [sp, #62] ; 0x3e + volatile bool bottom_only = false; + b9a8: f88d 203f strb.w r2, [sp, #63] ; 0x3f + if(dsc->border_side == LV_BORDER_SIDE_TOP) top_only = true; + b9ac: d15a bne.n ba64 + b9ae: 2301 movs r3, #1 + b9b0: f88d 303e strb.w r3, [sp, #62] ; 0x3e + volatile bool normal = !top_only && !bottom_only ? true : false; + b9b4: f89d 303e ldrb.w r3, [sp, #62] ; 0x3e + b9b8: 2b00 cmp r3, #0 + b9ba: d15d bne.n ba78 + b9bc: f89d 303f ldrb.w r3, [sp, #63] ; 0x3f + b9c0: f083 0301 eor.w r3, r3, #1 + b9c4: f003 0301 and.w r3, r3, #1 + _lv_blend_fill(clip, &fill_area, color, mask_buf, mask_res, opa, blend_mode); + b9c8: 4dad ldr r5, [pc, #692] ; (bc80 ) + volatile bool normal = !top_only && !bottom_only ? true : false; + b9ca: f88d 3040 strb.w r3, [sp, #64] ; 0x40 + for(h = draw_area.y1; h <= draw_area.y2; h++) { + b9ce: f9bd 3056 ldrsh.w r3, [sp, #86] ; 0x56 + b9d2: 429e cmp r6, r3 + b9d4: f73f a8a5 bgt.w ab22 + if(normal || + b9d8: f89d 3040 ldrb.w r3, [sp, #64] ; 0x40 + b9dc: b99b cbnz r3, ba06 + (top_only && fill_area.y1 <= coords->y1 + corner_size) || + b9de: f89d 303e ldrb.w r3, [sp, #62] ; 0x3e + b9e2: f9bd 2062 ldrsh.w r2, [sp, #98] ; 0x62 + if(normal || + b9e6: b12b cbz r3, b9f4 + (top_only && fill_area.y1 <= coords->y1 + corner_size) || + b9e8: f9bb 3002 ldrsh.w r3, [fp, #2] + b9ec: 9908 ldr r1, [sp, #32] + b9ee: 440b add r3, r1 + b9f0: 429a cmp r2, r3 + b9f2: dd08 ble.n ba06 + (bottom_only && fill_area.y1 >= coords->y2 - corner_size)) { + b9f4: f89d 303f ldrb.w r3, [sp, #63] ; 0x3f + (top_only && fill_area.y1 <= coords->y1 + corner_size) || + b9f8: b30b cbz r3, ba3e + (bottom_only && fill_area.y1 >= coords->y2 - corner_size)) { + b9fa: f9bb 3006 ldrsh.w r3, [fp, #6] + b9fe: 9908 ldr r1, [sp, #32] + ba00: 1a5b subs r3, r3, r1 + ba02: 429a cmp r2, r3 + ba04: db1b blt.n ba3e + _lv_memset_ff(mask_buf, draw_area_w); + ba06: 4b9f ldr r3, [pc, #636] ; (bc84 ) + mask_res = lv_draw_mask_apply(mask_buf, vdb->area.x1 + draw_area.x1, vdb->area.y1 + h, draw_area_w); + ba08: 4f9f ldr r7, [pc, #636] ; (bc88 ) + _lv_memset_ff(mask_buf, draw_area_w); + ba0a: 4649 mov r1, r9 + ba0c: 4620 mov r0, r4 + ba0e: 4798 blx r3 + mask_res = lv_draw_mask_apply(mask_buf, vdb->area.x1 + draw_area.x1, vdb->area.y1 + h, draw_area_w); + ba10: 9b06 ldr r3, [sp, #24] + ba12: 8a5a ldrh r2, [r3, #18] + ba14: 8a19 ldrh r1, [r3, #16] + ba16: f8bd 3050 ldrh.w r3, [sp, #80] ; 0x50 + ba1a: 4432 add r2, r6 + ba1c: 4419 add r1, r3 + ba1e: b212 sxth r2, r2 + ba20: 464b mov r3, r9 + ba22: b209 sxth r1, r1 + ba24: 4620 mov r0, r4 + ba26: 47b8 blx r7 + _lv_blend_fill(clip, &fill_area, color, mask_buf, mask_res, opa, blend_mode); + ba28: 9b07 ldr r3, [sp, #28] + ba2a: 9302 str r3, [sp, #8] + ba2c: 9b05 ldr r3, [sp, #20] + ba2e: ee18 2a10 vmov r2, s16 + ba32: e9cd 0300 strd r0, r3, [sp] + ba36: a918 add r1, sp, #96 ; 0x60 + ba38: 4623 mov r3, r4 + ba3a: 4640 mov r0, r8 + ba3c: 47a8 blx r5 + fill_area.y1++; + ba3e: f8bd 3062 ldrh.w r3, [sp, #98] ; 0x62 + ba42: 3301 adds r3, #1 + ba44: f8ad 3062 strh.w r3, [sp, #98] ; 0x62 + fill_area.y2++; + ba48: f8bd 3066 ldrh.w r3, [sp, #102] ; 0x66 + ba4c: 3301 adds r3, #1 + ba4e: f8ad 3066 strh.w r3, [sp, #102] ; 0x66 + for(h = draw_area.y1; h <= draw_area.y2; h++) { + ba52: 3601 adds r6, #1 + ba54: e7bb b.n b9ce + else if(dsc->border_side == LV_BORDER_SIDE_RIGHT) fill_area.x1 = coords->x2 - corner_size; + ba56: 2b08 cmp r3, #8 + ba58: bf02 ittt eq + ba5a: 9908 ldreq r1, [sp, #32] + ba5c: 1a52 subeq r2, r2, r1 + ba5e: f8ad 2060 strheq.w r2, [sp, #96] ; 0x60 + ba62: e79d b.n b9a0 + if(dsc->border_side == LV_BORDER_SIDE_BOTTOM) bottom_only = true; + ba64: 2b01 cmp r3, #1 + ba66: d004 beq.n ba72 + if(dsc->border_side == (LV_BORDER_SIDE_TOP | LV_BORDER_SIDE_BOTTOM)) { + ba68: 2b03 cmp r3, #3 + ba6a: d1a3 bne.n b9b4 + top_only = true; + ba6c: 2301 movs r3, #1 + ba6e: f88d 303e strb.w r3, [sp, #62] ; 0x3e + bottom_only = true; + ba72: f88d 303f strb.w r3, [sp, #63] ; 0x3f + ba76: e79d b.n b9b4 + volatile bool normal = !top_only && !bottom_only ? true : false; + ba78: 2300 movs r3, #0 + ba7a: e7a3 b.n b9c4 + _lv_memset_ff(mask_buf, draw_area_w); + ba7c: ee18 1a10 vmov r1, s16 + ba80: 4b80 ldr r3, [pc, #512] ; (bc84 ) + mask_res = lv_draw_mask_apply(mask_buf, vdb->area.x1 + draw_area.x1, vdb->area.y1 + h, draw_area_w); + ba82: 4d81 ldr r5, [pc, #516] ; (bc88 ) + _lv_memset_ff(mask_buf, draw_area_w); + ba84: 4620 mov r0, r4 + ba86: 4798 blx r3 + mask_res = lv_draw_mask_apply(mask_buf, vdb->area.x1 + draw_area.x1, vdb->area.y1 + h, draw_area_w); + ba88: 9b06 ldr r3, [sp, #24] + ba8a: 8a5a ldrh r2, [r3, #18] + ba8c: 8a19 ldrh r1, [r3, #16] + ba8e: f8bd 3058 ldrh.w r3, [sp, #88] ; 0x58 + ba92: 4432 add r2, r6 + ba94: 4419 add r1, r3 + ba96: b212 sxth r2, r2 + ba98: ee18 3a10 vmov r3, s16 + ba9c: b209 sxth r1, r1 + ba9e: 4620 mov r0, r4 + baa0: 47a8 blx r5 + fill_area2.y1 = fill_area.y1; + baa2: f8bd 3062 ldrh.w r3, [sp, #98] ; 0x62 + baa6: f8ad 306a strh.w r3, [sp, #106] ; 0x6a + fill_area2.y2 = fill_area.y2; + baaa: f8bd 3066 ldrh.w r3, [sp, #102] ; 0x66 + baae: f8ad 306e strh.w r3, [sp, #110] ; 0x6e + fill_area2.x1 = area_outer.x1; + bab2: f9bd 3050 ldrsh.w r3, [sp, #80] ; 0x50 + bab6: f8ad 3068 strh.w r3, [sp, #104] ; 0x68 + fill_area2.x2 = area_outer.x1 + rout - 1; + baba: 3b01 subs r3, #1 + babc: fa13 f389 uxtah r3, r3, r9 + bac0: fa1f f289 uxth.w r2, r9 + bac4: f8ad 306c strh.w r3, [sp, #108] ; 0x6c + _lv_blend_fill(clip, &fill_area2, color, mask_buf, mask_res, opa, blend_mode); + bac8: 9b05 ldr r3, [sp, #20] + mask_res = lv_draw_mask_apply(mask_buf, vdb->area.x1 + draw_area.x1, vdb->area.y1 + h, draw_area_w); + baca: 900a str r0, [sp, #40] ; 0x28 + fill_area2.x2 = area_outer.x1 + rout - 1; + bacc: 9209 str r2, [sp, #36] ; 0x24 + _lv_blend_fill(clip, &fill_area2, color, mask_buf, mask_res, opa, blend_mode); + bace: 9301 str r3, [sp, #4] + bad0: 9000 str r0, [sp, #0] + bad2: 4623 mov r3, r4 + bad4: 463a mov r2, r7 + bad6: a91a add r1, sp, #104 ; 0x68 + bad8: 4d69 ldr r5, [pc, #420] ; (bc80 ) + bada: f8cd b008 str.w fp, [sp, #8] + bade: 4640 mov r0, r8 + bae0: 47a8 blx r5 + if(fill_area2.y2 < area_outer.y1 + dsc->outline_width) { + bae2: f9bd 3052 ldrsh.w r3, [sp, #82] ; 0x52 + bae6: f9ba 1018 ldrsh.w r1, [sl, #24] + baea: f9bd 206e ldrsh.w r2, [sp, #110] ; 0x6e + baee: 440b add r3, r1 + baf0: 429a cmp r2, r3 + baf2: da15 bge.n bb20 + fill_area2.x1 = area_outer.x1 + rout; + baf4: 9a09 ldr r2, [sp, #36] ; 0x24 + baf6: f8bd 3050 ldrh.w r3, [sp, #80] ; 0x50 + _lv_blend_fill(clip, &fill_area2, color, NULL, LV_DRAW_MASK_RES_FULL_COVER, opa, blend_mode); + bafa: f8cd b008 str.w fp, [sp, #8] + fill_area2.x1 = area_outer.x1 + rout; + bafe: 4413 add r3, r2 + bb00: f8ad 3068 strh.w r3, [sp, #104] ; 0x68 + fill_area2.x2 = area_outer.x2 - rout; + bb04: f8bd 3054 ldrh.w r3, [sp, #84] ; 0x54 + bb08: 1a9b subs r3, r3, r2 + bb0a: f8ad 306c strh.w r3, [sp, #108] ; 0x6c + _lv_blend_fill(clip, &fill_area2, color, NULL, LV_DRAW_MASK_RES_FULL_COVER, opa, blend_mode); + bb0e: 9b05 ldr r3, [sp, #20] + bb10: 9301 str r3, [sp, #4] + bb12: 2301 movs r3, #1 + bb14: 9300 str r3, [sp, #0] + bb16: 463a mov r2, r7 + bb18: 2300 movs r3, #0 + bb1a: a91a add r1, sp, #104 ; 0x68 + bb1c: 4640 mov r0, r8 + bb1e: 47a8 blx r5 + fill_area2.x1 = area_outer.x2 - rout + 1; + bb20: f9bd 3054 ldrsh.w r3, [sp, #84] ; 0x54 + bb24: 9909 ldr r1, [sp, #36] ; 0x24 + fill_area2.x2 = area_outer.x2; + bb26: f8ad 306c strh.w r3, [sp, #108] ; 0x6c + fill_area2.x1 = area_outer.x2 - rout + 1; + bb2a: 1c5a adds r2, r3, #1 + bb2c: 1a52 subs r2, r2, r1 + bb2e: f8ad 2068 strh.w r2, [sp, #104] ; 0x68 + int32_t mask_ofs = (area_outer.x2 - rout + 1) - (vdb->area.x1 + draw_area.x1); + bb32: 9a06 ldr r2, [sp, #24] + bb34: f9bd 1058 ldrsh.w r1, [sp, #88] ; 0x58 + bb38: f9b2 2010 ldrsh.w r2, [r2, #16] + _lv_blend_fill(clip, &fill_area2, color, mask_buf + mask_ofs, mask_res, opa, blend_mode); + bb3c: 4d50 ldr r5, [pc, #320] ; (bc80 ) + bb3e: f8cd b008 str.w fp, [sp, #8] + int32_t mask_ofs = (area_outer.x2 - rout + 1) - (vdb->area.x1 + draw_area.x1); + bb42: eba3 0309 sub.w r3, r3, r9 + bb46: 440a add r2, r1 + bb48: 3301 adds r3, #1 + bb4a: 1a9b subs r3, r3, r2 + _lv_blend_fill(clip, &fill_area2, color, mask_buf + mask_ofs, mask_res, opa, blend_mode); + bb4c: 9a05 ldr r2, [sp, #20] + bb4e: 9201 str r2, [sp, #4] + bb50: 9a0a ldr r2, [sp, #40] ; 0x28 + bb52: 9200 str r2, [sp, #0] + bb54: 2b00 cmp r3, #0 + bb56: bfac ite ge + bb58: 18e3 addge r3, r4, r3 + bb5a: 1c23 addlt r3, r4, #0 + bb5c: 463a mov r2, r7 + bb5e: a91a add r1, sp, #104 ; 0x68 + bb60: 4640 mov r0, r8 + bb62: 47a8 blx r5 + fill_area.y1++; + bb64: f8bd 3062 ldrh.w r3, [sp, #98] ; 0x62 + bb68: 3301 adds r3, #1 + bb6a: f8ad 3062 strh.w r3, [sp, #98] ; 0x62 + fill_area.y2++; + bb6e: f8bd 3066 ldrh.w r3, [sp, #102] ; 0x66 + bb72: 3301 adds r3, #1 + bb74: f8ad 3066 strh.w r3, [sp, #102] ; 0x66 + for(h = draw_area.y1; h <= upper_corner_end; h++) { + bb78: 3601 adds r6, #1 + bb7a: f7ff b957 b.w ae2c + _lv_memset_ff(mask_buf, draw_area_w); + bb7e: ee18 1a10 vmov r1, s16 + bb82: 4b40 ldr r3, [pc, #256] ; (bc84 ) + mask_res = lv_draw_mask_apply(mask_buf, vdb->area.x1 + draw_area.x1, vdb->area.y1 + h, draw_area_w); + bb84: 4d40 ldr r5, [pc, #256] ; (bc88 ) + _lv_memset_ff(mask_buf, draw_area_w); + bb86: 4620 mov r0, r4 + bb88: 4798 blx r3 + mask_res = lv_draw_mask_apply(mask_buf, vdb->area.x1 + draw_area.x1, vdb->area.y1 + h, draw_area_w); + bb8a: 9b06 ldr r3, [sp, #24] + bb8c: 8a5a ldrh r2, [r3, #18] + bb8e: 8a19 ldrh r1, [r3, #16] + bb90: f8bd 3058 ldrh.w r3, [sp, #88] ; 0x58 + bb94: 4432 add r2, r6 + bb96: 4419 add r1, r3 + bb98: b212 sxth r2, r2 + bb9a: ee18 3a10 vmov r3, s16 + bb9e: b209 sxth r1, r1 + bba0: 4620 mov r0, r4 + bba2: 47a8 blx r5 + fill_area2.x1 = area_outer.x1; + bba4: f9bd 3050 ldrsh.w r3, [sp, #80] ; 0x50 + bba8: f8ad 3068 strh.w r3, [sp, #104] ; 0x68 + fill_area2.x2 = area_outer.x1 + rout - 1; + bbac: 3b01 subs r3, #1 + bbae: fa13 f389 uxtah r3, r3, r9 + bbb2: f8ad 306c strh.w r3, [sp, #108] ; 0x6c + fill_area2.y1 = fill_area.y1; + bbb6: f8bd 3062 ldrh.w r3, [sp, #98] ; 0x62 + bbba: f8ad 306a strh.w r3, [sp, #106] ; 0x6a + fill_area2.y2 = fill_area.y2; + bbbe: f8bd 3066 ldrh.w r3, [sp, #102] ; 0x66 + bbc2: f8ad 306e strh.w r3, [sp, #110] ; 0x6e + fill_area2.x2 = area_outer.x1 + rout - 1; + bbc6: fa1f f289 uxth.w r2, r9 + _lv_blend_fill(clip, &fill_area2, color, mask_buf, mask_res, opa, blend_mode); + bbca: 9b05 ldr r3, [sp, #20] + mask_res = lv_draw_mask_apply(mask_buf, vdb->area.x1 + draw_area.x1, vdb->area.y1 + h, draw_area_w); + bbcc: 9009 str r0, [sp, #36] ; 0x24 + fill_area2.x2 = area_outer.x1 + rout - 1; + bbce: 9208 str r2, [sp, #32] + _lv_blend_fill(clip, &fill_area2, color, mask_buf, mask_res, opa, blend_mode); + bbd0: 9301 str r3, [sp, #4] + bbd2: 9000 str r0, [sp, #0] + bbd4: 4623 mov r3, r4 + bbd6: 463a mov r2, r7 + bbd8: a91a add r1, sp, #104 ; 0x68 + bbda: 4d29 ldr r5, [pc, #164] ; (bc80 ) + bbdc: f8cd b008 str.w fp, [sp, #8] + bbe0: 4640 mov r0, r8 + bbe2: 47a8 blx r5 + if(fill_area2.y2 > area_outer.y2 - dsc->outline_width) { + bbe4: f9bd 3056 ldrsh.w r3, [sp, #86] ; 0x56 + bbe8: f9ba 1018 ldrsh.w r1, [sl, #24] + bbec: f9bd 206e ldrsh.w r2, [sp, #110] ; 0x6e + bbf0: 1a5b subs r3, r3, r1 + bbf2: 429a cmp r2, r3 + bbf4: dd15 ble.n bc22 + fill_area2.x1 = area_outer.x1 + rout; + bbf6: 9a08 ldr r2, [sp, #32] + bbf8: f8bd 3050 ldrh.w r3, [sp, #80] ; 0x50 + _lv_blend_fill(clip, &fill_area2, color, NULL, LV_DRAW_MASK_RES_FULL_COVER, opa, blend_mode); + bbfc: f8cd b008 str.w fp, [sp, #8] + fill_area2.x1 = area_outer.x1 + rout; + bc00: 4413 add r3, r2 + bc02: f8ad 3068 strh.w r3, [sp, #104] ; 0x68 + fill_area2.x2 = area_outer.x2 - rout; + bc06: f8bd 3054 ldrh.w r3, [sp, #84] ; 0x54 + bc0a: 1a9b subs r3, r3, r2 + bc0c: f8ad 306c strh.w r3, [sp, #108] ; 0x6c + _lv_blend_fill(clip, &fill_area2, color, NULL, LV_DRAW_MASK_RES_FULL_COVER, opa, blend_mode); + bc10: 9b05 ldr r3, [sp, #20] + bc12: 9301 str r3, [sp, #4] + bc14: 2301 movs r3, #1 + bc16: 9300 str r3, [sp, #0] + bc18: 463a mov r2, r7 + bc1a: 2300 movs r3, #0 + bc1c: a91a add r1, sp, #104 ; 0x68 + bc1e: 4640 mov r0, r8 + bc20: 47a8 blx r5 + fill_area2.x1 = area_outer.x2 - rout + 1; + bc22: f9bd 3054 ldrsh.w r3, [sp, #84] ; 0x54 + bc26: 9908 ldr r1, [sp, #32] + fill_area2.x2 = area_outer.x2; + bc28: f8ad 306c strh.w r3, [sp, #108] ; 0x6c + fill_area2.x1 = area_outer.x2 - rout + 1; + bc2c: 1c5a adds r2, r3, #1 + bc2e: 1a52 subs r2, r2, r1 + bc30: f8ad 2068 strh.w r2, [sp, #104] ; 0x68 + int32_t mask_ofs = (area_outer.x2 - rout + 1) - (vdb->area.x1 + draw_area.x1); + bc34: 9a06 ldr r2, [sp, #24] + bc36: f9bd 1058 ldrsh.w r1, [sp, #88] ; 0x58 + bc3a: f9b2 2010 ldrsh.w r2, [r2, #16] + _lv_blend_fill(clip, &fill_area2, color, mask_buf + mask_ofs, mask_res, opa, blend_mode); + bc3e: 4d10 ldr r5, [pc, #64] ; (bc80 ) + bc40: f8cd b008 str.w fp, [sp, #8] + int32_t mask_ofs = (area_outer.x2 - rout + 1) - (vdb->area.x1 + draw_area.x1); + bc44: eba3 0309 sub.w r3, r3, r9 + bc48: 440a add r2, r1 + bc4a: 3301 adds r3, #1 + bc4c: 1a9b subs r3, r3, r2 + _lv_blend_fill(clip, &fill_area2, color, mask_buf + mask_ofs, mask_res, opa, blend_mode); + bc4e: 9a05 ldr r2, [sp, #20] + bc50: 9201 str r2, [sp, #4] + bc52: 9a09 ldr r2, [sp, #36] ; 0x24 + bc54: 9200 str r2, [sp, #0] + bc56: 2b00 cmp r3, #0 + bc58: bfac ite ge + bc5a: 18e3 addge r3, r4, r3 + bc5c: 1c23 addlt r3, r4, #0 + bc5e: 463a mov r2, r7 + bc60: a91a add r1, sp, #104 ; 0x68 + bc62: 4640 mov r0, r8 + bc64: 47a8 blx r5 + fill_area.y1++; + bc66: f8bd 3062 ldrh.w r3, [sp, #98] ; 0x62 + bc6a: 3301 adds r3, #1 + bc6c: f8ad 3062 strh.w r3, [sp, #98] ; 0x62 + fill_area.y2++; + bc70: f8bd 3066 ldrh.w r3, [sp, #102] ; 0x66 + bc74: 3301 adds r3, #1 + bc76: f8ad 3066 strh.w r3, [sp, #102] ; 0x66 + for(h = lower_corner_end; h <= draw_area.y2; h++) { + bc7a: 3601 adds r6, #1 + bc7c: f7ff b8ed b.w ae5a + bc80: 000061f1 .word 0x000061f1 + bc84: 0000f075 .word 0x0000f075 + bc88: 00009761 .word 0x00009761 + _lv_memset_ff(mask_buf, draw_area_w); + bc8c: f8df 908c ldr.w r9, [pc, #140] ; bd1c + _lv_blend_fill(clip, &fill_area, color, mask_buf, mask_res, opa, blend_mode); + bc90: f8df a08c ldr.w sl, [pc, #140] ; bd20 + fill_area.x1 = area_outer.x1; + bc94: f8ad 0060 strh.w r0, [sp, #96] ; 0x60 + fill_area.x2 = area_outer.x2; + bc98: f8ad 1064 strh.w r1, [sp, #100] ; 0x64 + fill_area.y1 = disp_area->y1 + draw_area.y1; + bc9c: f8ad 3062 strh.w r3, [sp, #98] ; 0x62 + fill_area.y2 = fill_area.y1; + bca0: f8ad 3066 strh.w r3, [sp, #102] ; 0x66 + for(h = draw_area.y1; h <= draw_area.y2; h++) { + bca4: f9bd 305e ldrsh.w r3, [sp, #94] ; 0x5e + bca8: 429e cmp r6, r3 + bcaa: f73f a913 bgt.w aed4 + _lv_memset_ff(mask_buf, draw_area_w); + bcae: ee18 1a10 vmov r1, s16 + bcb2: 4620 mov r0, r4 + bcb4: 47c8 blx r9 + mask_res = lv_draw_mask_apply(mask_buf, vdb->area.x1 + draw_area.x1, vdb->area.y1 + h, draw_area_w); + bcb6: 9b06 ldr r3, [sp, #24] + bcb8: 4d17 ldr r5, [pc, #92] ; (bd18 ) + bcba: 8a5a ldrh r2, [r3, #18] + bcbc: 8a19 ldrh r1, [r3, #16] + bcbe: f8bd 3058 ldrh.w r3, [sp, #88] ; 0x58 + bcc2: 4432 add r2, r6 + bcc4: 4419 add r1, r3 + bcc6: b212 sxth r2, r2 + bcc8: ee18 3a10 vmov r3, s16 + bccc: b209 sxth r1, r1 + bcce: 4620 mov r0, r4 + bcd0: 47a8 blx r5 + _lv_blend_fill(clip, &fill_area, color, mask_buf, mask_res, opa, blend_mode); + bcd2: 9b05 ldr r3, [sp, #20] + bcd4: f8cd b008 str.w fp, [sp, #8] + bcd8: e9cd 0300 strd r0, r3, [sp] + bcdc: 463a mov r2, r7 + bcde: 4623 mov r3, r4 + bce0: a918 add r1, sp, #96 ; 0x60 + bce2: 4640 mov r0, r8 + bce4: 47d0 blx sl + fill_area.y1++; + bce6: f8bd 3062 ldrh.w r3, [sp, #98] ; 0x62 + bcea: 3301 adds r3, #1 + bcec: f8ad 3062 strh.w r3, [sp, #98] ; 0x62 + fill_area.y2++; + bcf0: f8bd 3066 ldrh.w r3, [sp, #102] ; 0x66 + bcf4: 3301 adds r3, #1 + bcf6: b21b sxth r3, r3 + for(h = draw_area.y1; h <= draw_area.y2; h++) { + bcf8: 3601 adds r6, #1 + bcfa: e7d1 b.n bca0 + if(dsc->bg_grad_dir == LV_GRAD_DIR_HOR) { + bcfc: 9b09 ldr r3, [sp, #36] ; 0x24 + bcfe: 2b02 cmp r3, #2 + bd00: f43f abc6 beq.w b490 + else if(other_mask_cnt != 0 || !split) { + bd04: 9b0d ldr r3, [sp, #52] ; 0x34 + bd06: 2b00 cmp r3, #0 + bd08: f47f abdd bne.w b4c6 + bd0c: 9b0a ldr r3, [sp, #40] ; 0x28 + bd0e: 2b32 cmp r3, #50 ; 0x32 + bd10: f73f abc9 bgt.w b4a6 + bd14: f7ff bbd7 b.w b4c6 + bd18: 00009761 .word 0x00009761 + bd1c: 0000f075 .word 0x0000f075 + bd20: 000061f1 .word 0x000061f1 + +0000bd24 : +{ + bd24: b5f0 push {r4, r5, r6, r7, lr} + LV_COLOR_SET_G(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_G(c1) * mix + LV_COLOR_GET_G(c2) * (255 - mix))); + bd26: f3c1 1345 ubfx r3, r1, #5, #6 + LV_COLOR_SET_R(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_R(c1) * mix + LV_COLOR_GET_R(c2) * (255 - mix))); + bd2a: f1c2 06ff rsb r6, r2, #255 ; 0xff + LV_COLOR_SET_G(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_G(c1) * mix + LV_COLOR_GET_G(c2) * (255 - mix))); + bd2e: f3c0 1445 ubfx r4, r0, #5, #6 + bd32: 4373 muls r3, r6 + bd34: fb04 3302 mla r3, r4, r2, r3 + LV_COLOR_SET_B(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_B(c1) * mix + LV_COLOR_GET_B(c2) * (255 - mix))); + bd38: f001 041f and.w r4, r1, #31 + bd3c: f000 071f and.w r7, r0, #31 + bd40: 4374 muls r4, r6 + LV_COLOR_SET_G(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_G(c1) * mix + LV_COLOR_GET_G(c2) * (255 - mix))); + bd42: f248 0581 movw r5, #32897 ; 0x8081 + LV_COLOR_SET_B(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_B(c1) * mix + LV_COLOR_GET_B(c2) * (255 - mix))); + bd46: fb07 4402 mla r4, r7, r2, r4 + LV_COLOR_SET_G(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_G(c1) * mix + LV_COLOR_GET_G(c2) * (255 - mix))); + bd4a: 436b muls r3, r5 + LV_COLOR_SET_B(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_B(c1) * mix + LV_COLOR_GET_B(c2) * (255 - mix))); + bd4c: 436c muls r4, r5 + return ret; + bd4e: f3c3 53c5 ubfx r3, r3, #23, #6 + bd52: f3c4 54c4 ubfx r4, r4, #23, #5 + bd56: ea44 1443 orr.w r4, r4, r3, lsl #5 + LV_COLOR_SET_R(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_R(c1) * mix + LV_COLOR_GET_R(c2) * (255 - mix))); + bd5a: f3c1 23c4 ubfx r3, r1, #11, #5 + bd5e: 4373 muls r3, r6 + bd60: f3c0 20c4 ubfx r0, r0, #11, #5 + bd64: fb00 3202 mla r2, r0, r2, r3 + bd68: fb05 f302 mul.w r3, r5, r2 + bd6c: 0ddb lsrs r3, r3, #23 +} + bd6e: ea44 20c3 orr.w r0, r4, r3, lsl #11 + bd72: bdf0 pop {r4, r5, r6, r7, pc} + +0000bd74 <_lv_memcpy_small.isra.0>: +LV_ATTRIBUTE_FAST_MEM static inline void * _lv_memcpy_small(void * dst, const void * src, size_t len) + bd74: 3901 subs r1, #1 + bd76: 4402 add r2, r0 + while(len) { + bd78: 4290 cmp r0, r2 + bd7a: d100 bne.n bd7e <_lv_memcpy_small.isra.0+0xa> + s8++; + len--; + } + + return dst; +} + bd7c: 4770 bx lr + *d8 = *s8; + bd7e: f811 3f01 ldrb.w r3, [r1, #1]! + bd82: f800 3b01 strb.w r3, [r0], #1 + len--; + bd86: e7f7 b.n bd78 <_lv_memcpy_small.isra.0+0x4> + +0000bd88 : + * Not used in other cases. + * @param safe true: check out of bounds + * @return color of the point + */ +lv_color_t lv_img_buf_get_px_color(lv_img_dsc_t * dsc, lv_coord_t x, lv_coord_t y, lv_color_t color) +{ + bd88: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} + lv_color_t p_color = LV_COLOR_BLACK; + uint8_t * buf_u8 = (uint8_t *)dsc->data; + bd8a: 6886 ldr r6, [r0, #8] +{ + bd8c: 4607 mov r7, r0 + + if(dsc->header.cf == LV_IMG_CF_TRUE_COLOR || dsc->header.cf == LV_IMG_CF_TRUE_COLOR_CHROMA_KEYED || + bd8e: 7800 ldrb r0, [r0, #0] +{ + bd90: 4615 mov r5, r2 + lv_color_t p_color = LV_COLOR_BLACK; + bd92: 2200 movs r2, #0 + bd94: f8ad 2004 strh.w r2, [sp, #4] + if(dsc->header.cf == LV_IMG_CF_TRUE_COLOR || dsc->header.cf == LV_IMG_CF_TRUE_COLOR_CHROMA_KEYED || + bd98: f000 021f and.w r2, r0, #31 + bd9c: 2a04 cmp r2, #4 +{ + bd9e: 460c mov r4, r1 + if(dsc->header.cf == LV_IMG_CF_TRUE_COLOR || dsc->header.cf == LV_IMG_CF_TRUE_COLOR_CHROMA_KEYED || + bda0: d009 beq.n bdb6 + bda2: 3a05 subs r2, #5 + bda4: 2a09 cmp r2, #9 + bda6: d81a bhi.n bdde + bda8: e8df f002 tbb [pc, r2] + bdac: 321d0505 .word 0x321d0505 + bdb0: 2f2f5843 .word 0x2f2f5843 + bdb4: 2f2f .short 0x2f2f + dsc->header.cf == LV_IMG_CF_TRUE_COLOR_ALPHA) { + uint8_t px_size = lv_img_cf_get_px_size(dsc->header.cf) >> 3; + bdb6: 4b2e ldr r3, [pc, #184] ; (be70 ) + bdb8: f000 001f and.w r0, r0, #31 + bdbc: 4798 blx r3 + uint32_t px = dsc->header.w * y * px_size + x * px_size; + bdbe: 683b ldr r3, [r7, #0] + uint8_t px_size = lv_img_cf_get_px_size(dsc->header.cf) >> 3; + bdc0: f3c0 00c7 ubfx r0, r0, #3, #8 + uint32_t px = dsc->header.w * y * px_size + x * px_size; + bdc4: f3c3 238a ubfx r3, r3, #10, #11 + bdc8: fb13 f305 smulbb r3, r3, r5 + bdcc: fb10 f104 smulbb r1, r0, r4 + bdd0: fb00 1103 mla r1, r0, r3, r1 + _lv_memcpy_small(&p_color, &buf_u8[px], sizeof(lv_color_t)); + bdd4: 2202 movs r2, #2 + bdd6: 4b27 ldr r3, [pc, #156] ; (be74 ) + bdd8: 4431 add r1, r6 + bdda: a801 add r0, sp, #4 + bddc: 4798 blx r3 + else if(dsc->header.cf == LV_IMG_CF_ALPHA_1BIT || dsc->header.cf == LV_IMG_CF_ALPHA_2BIT || + dsc->header.cf == LV_IMG_CF_ALPHA_4BIT || dsc->header.cf == LV_IMG_CF_ALPHA_8BIT) { + p_color = color; + } + return p_color; +} + bdde: f8bd 0004 ldrh.w r0, [sp, #4] + bde2: b003 add sp, #12 + bde4: bdf0 pop {r4, r5, r6, r7, pc} + uint32_t px = ((dsc->header.w + 7) >> 3) * y + x; + bde6: 683b ldr r3, [r7, #0] + bde8: f3c3 238a ubfx r3, r3, #10, #11 + bdec: 3307 adds r3, #7 + bdee: 10db asrs r3, r3, #3 + p_color.full = (buf_u8[px] & (1 << (7 - bit))) >> (7 - bit); + bdf0: fb05 6303 mla r3, r5, r3, r6 + bdf4: eb03 03e4 add.w r3, r3, r4, asr #3 + bdf8: f004 0207 and.w r2, r4, #7 + bdfc: 7a1b ldrb r3, [r3, #8] + bdfe: f1c2 0207 rsb r2, r2, #7 + be02: 2101 movs r1, #1 + p_color.full = (buf_u8[px] & (3 << (6 - bit))) >> (6 - bit); + be04: 4091 lsls r1, r2 + be06: 400b ands r3, r1 + be08: 4113 asrs r3, r2 + p_color = color; + be0a: f8ad 3004 strh.w r3, [sp, #4] + be0e: e7e6 b.n bdde + uint32_t px = ((dsc->header.w + 3) >> 2) * y + x; + be10: 683b ldr r3, [r7, #0] + be12: f3c3 238a ubfx r3, r3, #10, #11 + be16: 3303 adds r3, #3 + be18: 109b asrs r3, r3, #2 + p_color.full = (buf_u8[px] & (3 << (6 - bit))) >> (6 - bit); + be1a: fb05 6303 mla r3, r5, r3, r6 + uint8_t bit = (x & 0x3) * 2; + be1e: f004 0203 and.w r2, r4, #3 + p_color.full = (buf_u8[px] & (3 << (6 - bit))) >> (6 - bit); + be22: eb03 03a4 add.w r3, r3, r4, asr #2 + be26: 0052 lsls r2, r2, #1 + be28: 7c1b ldrb r3, [r3, #16] + be2a: f1c2 0206 rsb r2, r2, #6 + be2e: 2103 movs r1, #3 + be30: e7e8 b.n be04 + uint32_t px = ((dsc->header.w + 1) >> 1) * y + x; + be32: 683b ldr r3, [r7, #0] + be34: f3c3 238a ubfx r3, r3, #10, #11 + be38: 3301 adds r3, #1 + be3a: 105b asrs r3, r3, #1 + p_color.full = (buf_u8[px] & (0xF << (4 - bit))) >> (4 - bit); + be3c: fb05 6203 mla r2, r5, r3, r6 + be40: eb02 0264 add.w r2, r2, r4, asr #1 + uint8_t bit = (x & 0x1) * 4; + be44: f004 0101 and.w r1, r4, #1 + p_color.full = (buf_u8[px] & (0xF << (4 - bit))) >> (4 - bit); + be48: 0089 lsls r1, r1, #2 + be4a: f892 3040 ldrb.w r3, [r2, #64] ; 0x40 + be4e: f1c1 0104 rsb r1, r1, #4 + be52: 220f movs r2, #15 + be54: 408a lsls r2, r1 + be56: 4013 ands r3, r2 + be58: 410b asrs r3, r1 + be5a: e7d6 b.n be0a + uint32_t px = dsc->header.w * y + x; + be5c: 683b ldr r3, [r7, #0] + be5e: f3c3 238a ubfx r3, r3, #10, #11 + be62: fb15 4503 smlabb r5, r5, r3, r4 + p_color.full = buf_u8[px]; + be66: 442e add r6, r5 + be68: f896 3400 ldrb.w r3, [r6, #1024] ; 0x400 + be6c: e7cd b.n be0a + be6e: bf00 nop + be70: 00007581 .word 0x00007581 + be74: 0000bd75 .word 0x0000bd75 + +0000be78 : + * @param y x coordinate of the point to set + * @param safe true: check out of bounds + * @return alpha value of the point + */ +lv_opa_t lv_img_buf_get_px_alpha(lv_img_dsc_t * dsc, lv_coord_t x, lv_coord_t y) +{ + be78: b5f0 push {r4, r5, r6, r7, lr} + be7a: 460b mov r3, r1 + uint8_t * buf_u8 = (uint8_t *)dsc->data; + + if(dsc->header.cf == LV_IMG_CF_TRUE_COLOR_ALPHA) { + be7c: 7801 ldrb r1, [r0, #0] + uint8_t * buf_u8 = (uint8_t *)dsc->data; + be7e: 6885 ldr r5, [r0, #8] + if(dsc->header.cf == LV_IMG_CF_TRUE_COLOR_ALPHA) { + be80: f001 011f and.w r1, r1, #31 + be84: 2905 cmp r1, #5 +{ + be86: b085 sub sp, #20 + be88: 4604 mov r4, r0 + if(dsc->header.cf == LV_IMG_CF_TRUE_COLOR_ALPHA) { + be8a: d10a bne.n bea2 + uint32_t px = dsc->header.w * y * LV_IMG_PX_SIZE_ALPHA_BYTE + x * LV_IMG_PX_SIZE_ALPHA_BYTE; + be8c: 6801 ldr r1, [r0, #0] + be8e: f3c1 218a ubfx r1, r1, #10, #11 + be92: fb12 3201 smlabb r2, r2, r1, r3 + return buf_u8[px + LV_IMG_PX_SIZE_ALPHA_BYTE - 1]; + be96: eb02 0242 add.w r2, r2, r2, lsl #1 + be9a: 442a add r2, r5 + be9c: 7890 ldrb r0, [r2, #2] + uint32_t px = dsc->header.w * y + x; + return buf_u8[px]; + } + + return LV_OPA_COVER; +} + be9e: b005 add sp, #20 + bea0: bdf0 pop {r4, r5, r6, r7, pc} + else if(dsc->header.cf == LV_IMG_CF_ALPHA_1BIT) { + bea2: 390b subs r1, #11 + bea4: 2903 cmp r1, #3 + bea6: d856 bhi.n bf56 + bea8: e8df f001 tbb [pc, r1] + beac: 4e321902 .word 0x4e321902 + uint32_t px = ((dsc->header.w + 7) >> 3) * y + x; + beb0: 6821 ldr r1, [r4, #0] + beb2: f3c1 218a ubfx r1, r1, #10, #11 + beb6: 3107 adds r1, #7 + beb8: 10c9 asrs r1, r1, #3 + uint8_t px_opa = (buf_u8[px] & (1 << (7 - bit))) >> (7 - bit); + beba: f003 0007 and.w r0, r3, #7 + bebe: fb02 5201 mla r2, r2, r1, r5 + uint32_t px = ((dsc->header.w + 7) >> 3) * y + x; + bec2: 10db asrs r3, r3, #3 + uint8_t px_opa = (buf_u8[px] & (1 << (7 - bit))) >> (7 - bit); + bec4: f1c0 0007 rsb r0, r0, #7 + bec8: 5cd3 ldrb r3, [r2, r3] + beca: 2201 movs r2, #1 + becc: 4082 lsls r2, r0 + bece: 4013 ands r3, r2 + return px_opa ? LV_OPA_TRANSP : LV_OPA_COVER; + bed0: 4103 asrs r3, r0 + bed2: bf0c ite eq + bed4: f04f 30ff moveq.w r0, #4294967295 ; 0xffffffff + bed8: 2000 movne r0, #0 + beda: b2c0 uxtb r0, r0 + bedc: e7df b.n be9e + const uint8_t opa_table[4] = {0, 85, 170, 255}; /*Opacity mapping with bpp = 2*/ + bede: 491f ldr r1, [pc, #124] ; (bf5c ) + bee0: 9100 str r1, [sp, #0] + uint32_t px = ((dsc->header.w + 3) >> 2) * y + x; + bee2: 6821 ldr r1, [r4, #0] + bee4: f3c1 218a ubfx r1, r1, #10, #11 + bee8: 3103 adds r1, #3 + beea: 1089 asrs r1, r1, #2 + uint8_t bit = (x & 0x3) * 2; + beec: f003 0003 and.w r0, r3, #3 + uint8_t px_opa = (buf_u8[px] & (3 << (6 - bit))) >> (6 - bit); + bef0: fb02 5201 mla r2, r2, r1, r5 + uint32_t px = ((dsc->header.w + 3) >> 2) * y + x; + bef4: 109b asrs r3, r3, #2 + uint8_t px_opa = (buf_u8[px] & (3 << (6 - bit))) >> (6 - bit); + bef6: 0040 lsls r0, r0, #1 + bef8: 5cd3 ldrb r3, [r2, r3] + befa: f1c0 0006 rsb r0, r0, #6 + befe: 2203 movs r2, #3 + uint8_t px_opa = (buf_u8[px] & (0xF << (4 - bit))) >> (4 - bit); + bf00: 4082 lsls r2, r0 + bf02: 4013 ands r3, r2 + bf04: 4103 asrs r3, r0 + return opa_table[px_opa]; + bf06: 3310 adds r3, #16 + bf08: 446b add r3, sp + bf0a: f813 0c10 ldrb.w r0, [r3, #-16] + bf0e: e7c6 b.n be9e + const uint8_t opa_table[16] = {0, 17, 34, 51, /*Opacity mapping with bpp = 4*/ + bf10: 4e13 ldr r6, [pc, #76] ; (bf60 ) + bf12: 46ec mov ip, sp + bf14: f106 0e10 add.w lr, r6, #16 + bf18: 6830 ldr r0, [r6, #0] + bf1a: 6871 ldr r1, [r6, #4] + bf1c: 4667 mov r7, ip + bf1e: c703 stmia r7!, {r0, r1} + bf20: 3608 adds r6, #8 + bf22: 4576 cmp r6, lr + bf24: 46bc mov ip, r7 + bf26: d1f7 bne.n bf18 + uint32_t px = ((dsc->header.w + 1) >> 1) * y + x; + bf28: 6821 ldr r1, [r4, #0] + bf2a: f3c1 218a ubfx r1, r1, #10, #11 + bf2e: 3101 adds r1, #1 + bf30: 1049 asrs r1, r1, #1 + uint8_t bit = (x & 0x1) * 4; + bf32: f003 0001 and.w r0, r3, #1 + uint8_t px_opa = (buf_u8[px] & (0xF << (4 - bit))) >> (4 - bit); + bf36: fb02 5201 mla r2, r2, r1, r5 + uint32_t px = ((dsc->header.w + 1) >> 1) * y + x; + bf3a: 105b asrs r3, r3, #1 + uint8_t px_opa = (buf_u8[px] & (0xF << (4 - bit))) >> (4 - bit); + bf3c: 0080 lsls r0, r0, #2 + bf3e: 5cd3 ldrb r3, [r2, r3] + bf40: f1c0 0004 rsb r0, r0, #4 + bf44: 220f movs r2, #15 + bf46: e7db b.n bf00 + uint32_t px = dsc->header.w * y + x; + bf48: 6821 ldr r1, [r4, #0] + bf4a: f3c1 218a ubfx r1, r1, #10, #11 + bf4e: fb12 3201 smlabb r2, r2, r1, r3 + return buf_u8[px]; + bf52: 5ca8 ldrb r0, [r5, r2] + bf54: e7a3 b.n be9e + if(dsc->header.cf == LV_IMG_CF_TRUE_COLOR_ALPHA) { + bf56: 20ff movs r0, #255 ; 0xff + bf58: e7a1 b.n be9e + bf5a: bf00 nop + bf5c: ffaa5500 .word 0xffaa5500 + bf60: 0001fdff .word 0x0001fdff + +0000bf64 <_lv_img_buf_transform_init>: +/** + * Initialize a descriptor to tranform an image + * @param dsc pointer to an `lv_img_transform_dsc_t` variable whose `cfg` field is initialized + */ +void _lv_img_buf_transform_init(lv_img_transform_dsc_t * dsc) +{ + bf64: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} + dsc->tmp.pivot_x_256 = dsc->cfg.pivot_x * 256; + bf68: f9b0 3008 ldrsh.w r3, [r0, #8] + + int32_t angle_low = dsc->cfg.angle / 10; + int32_t angle_hight = angle_low + 1; + int32_t angle_rem = dsc->cfg.angle - (angle_low * 10); + + int32_t s1 = _lv_trigo_sin(-angle_low); + bf6c: f8df 80ec ldr.w r8, [pc, #236] ; c05c + dsc->tmp.pivot_x_256 = dsc->cfg.pivot_x * 256; + bf70: 021b lsls r3, r3, #8 + bf72: 6243 str r3, [r0, #36] ; 0x24 + dsc->tmp.pivot_y_256 = dsc->cfg.pivot_y * 256; + bf74: f9b0 300a ldrsh.w r3, [r0, #10] + bf78: 021b lsls r3, r3, #8 + int32_t angle_low = dsc->cfg.angle / 10; + bf7a: 260a movs r6, #10 + dsc->tmp.pivot_y_256 = dsc->cfg.pivot_y * 256; + bf7c: 6283 str r3, [r0, #40] ; 0x28 + int32_t angle_low = dsc->cfg.angle / 10; + bf7e: f9b0 300c ldrsh.w r3, [r0, #12] + bf82: fb93 f5f6 sdiv r5, r3, r6 + int32_t s1 = _lv_trigo_sin(-angle_low); + bf86: fa1f f985 uxth.w r9, r5 +{ + bf8a: 4604 mov r4, r0 + int32_t s1 = _lv_trigo_sin(-angle_low); + bf8c: f1c9 0000 rsb r0, r9, #0 + int32_t angle_rem = dsc->cfg.angle - (angle_low * 10); + bf90: f64f 77f6 movw r7, #65526 ; 0xfff6 + int32_t s1 = _lv_trigo_sin(-angle_low); + bf94: b200 sxth r0, r0 + int32_t angle_rem = dsc->cfg.angle - (angle_low * 10); + bf96: fb15 3707 smlabb r7, r5, r7, r3 + int32_t s1 = _lv_trigo_sin(-angle_low); + bf9a: 47c0 blx r8 + int32_t angle_hight = angle_low + 1; + bf9c: 3501 adds r5, #1 + int32_t s2 = _lv_trigo_sin(-angle_hight); + bf9e: b2ad uxth r5, r5 + int32_t s1 = _lv_trigo_sin(-angle_low); + bfa0: 4682 mov sl, r0 + int32_t s2 = _lv_trigo_sin(-angle_hight); + bfa2: 4268 negs r0, r5 + bfa4: b200 sxth r0, r0 + bfa6: 47c0 blx r8 + bfa8: 4683 mov fp, r0 + + int32_t c1 = _lv_trigo_sin(-angle_low + 90); + bfaa: f1c9 005a rsb r0, r9, #90 ; 0x5a + bfae: b200 sxth r0, r0 + bfb0: 47c0 blx r8 + int32_t c2 = _lv_trigo_sin(-angle_hight + 90); + bfb2: f1c5 055a rsb r5, r5, #90 ; 0x5a + int32_t c1 = _lv_trigo_sin(-angle_low + 90); + bfb6: 4681 mov r9, r0 + int32_t c2 = _lv_trigo_sin(-angle_hight + 90); + bfb8: b228 sxth r0, r5 + bfba: 47c0 blx r8 + + dsc->tmp.sinma = (s1 * (10 - angle_rem) + s2 * angle_rem) / 10; + bfbc: 1bf2 subs r2, r6, r7 + bfbe: fb07 f30b mul.w r3, r7, fp + bfc2: fb02 330a mla r3, r2, sl, r3 + bfc6: fb93 f3f6 sdiv r3, r3, r6 + bfca: 62e3 str r3, [r4, #44] ; 0x2c + dsc->tmp.cosma = (c1 * (10 - angle_rem) + c2 * angle_rem) / 10; + bfcc: fb07 f300 mul.w r3, r7, r0 + bfd0: fb02 3009 mla r0, r2, r9, r3 + + dsc->tmp.chroma_keyed = lv_img_cf_is_chroma_keyed(dsc->cfg.cf) ? 1 : 0; + bfd4: 4b1f ldr r3, [pc, #124] ; (c054 ) + dsc->tmp.cosma = (c1 * (10 - angle_rem) + c2 * angle_rem) / 10; + bfd6: fb90 f0f6 sdiv r0, r0, r6 + bfda: 6320 str r0, [r4, #48] ; 0x30 + dsc->tmp.chroma_keyed = lv_img_cf_is_chroma_keyed(dsc->cfg.cf) ? 1 : 0; + bfdc: 7ca0 ldrb r0, [r4, #18] + bfde: 4798 blx r3 + bfe0: f894 3034 ldrb.w r3, [r4, #52] ; 0x34 + bfe4: f360 0300 bfi r3, r0, #0, #1 + bfe8: f884 3034 strb.w r3, [r4, #52] ; 0x34 + dsc->tmp.has_alpha = lv_img_cf_has_alpha(dsc->cfg.cf) ? 1 : 0; + bfec: 7ca0 ldrb r0, [r4, #18] + bfee: 4b1a ldr r3, [pc, #104] ; (c058 ) + bff0: 4798 blx r3 + if(dsc->cfg.cf == LV_IMG_CF_TRUE_COLOR || dsc->cfg.cf == LV_IMG_CF_TRUE_COLOR_ALPHA || + bff2: 7ca3 ldrb r3, [r4, #18] + bff4: 1f19 subs r1, r3, #4 + bff6: 2902 cmp r1, #2 + bff8: bf8c ite hi + bffa: 2100 movhi r1, #0 + bffc: 2101 movls r1, #1 + dsc->tmp.has_alpha = lv_img_cf_has_alpha(dsc->cfg.cf) ? 1 : 0; + bffe: 0042 lsls r2, r0, #1 + c000: ea42 0281 orr.w r2, r2, r1, lsl #2 + c004: f894 1034 ldrb.w r1, [r4, #52] ; 0x34 + c008: f002 0206 and.w r2, r2, #6 + c00c: f021 0106 bic.w r1, r1, #6 + c010: 430a orrs r2, r1 + c012: f884 2034 strb.w r2, [r4, #52] ; 0x34 + } + else { + dsc->tmp.native_color = 0; + } + + dsc->tmp.img_dsc.data = dsc->cfg.src; + c016: 6822 ldr r2, [r4, #0] + c018: 6222 str r2, [r4, #32] + dsc->tmp.img_dsc.header.always_zero = 0; + dsc->tmp.img_dsc.header.cf = dsc->cfg.cf; + c01a: 88a2 ldrh r2, [r4, #4] + c01c: f003 031f and.w r3, r3, #31 + c020: f3c2 020a ubfx r2, r2, #0, #11 + c024: ea43 2382 orr.w r3, r3, r2, lsl #10 + c028: f9b4 2006 ldrsh.w r2, [r4, #6] + c02c: ea43 5342 orr.w r3, r3, r2, lsl #21 + c030: 69a2 ldr r2, [r4, #24] + c032: f402 7240 and.w r2, r2, #768 ; 0x300 + c036: 4313 orrs r3, r2 + c038: 61a3 str r3, [r4, #24] + dsc->tmp.img_dsc.header.w = dsc->cfg.src_w; + dsc->tmp.img_dsc.header.h = dsc->cfg.src_h; + + dsc->tmp.zoom_inv = (256 * 256) / dsc->cfg.zoom; + c03a: 89e2 ldrh r2, [r4, #14] + c03c: f44f 3380 mov.w r3, #65536 ; 0x10000 + c040: fbb3 f3f2 udiv r3, r3, r2 + c044: 86e3 strh r3, [r4, #54] ; 0x36 + + dsc->res.opa = LV_OPA_COVER; + c046: 23ff movs r3, #255 ; 0xff + c048: 75a3 strb r3, [r4, #22] + dsc->res.color = dsc->cfg.color; + c04a: 8a23 ldrh r3, [r4, #16] + c04c: 82a3 strh r3, [r4, #20] +} + c04e: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} + c052: bf00 nop + c054: 00007599 .word 0x00007599 + c058: 000075ad .word 0x000075ad + c05c: 0000e93d .word 0x0000e93d + +0000c060 <_lv_img_buf_get_transformed_area>: + * @param zoom zoom, (256 no zoom) + * @param pivot x,y pivot coordinates of rotation + */ +void _lv_img_buf_get_transformed_area(lv_area_t * res, lv_coord_t w, lv_coord_t h, int16_t angle, uint16_t zoom, + lv_point_t * pivot) +{ + c060: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + c064: b085 sub sp, #20 + c066: 4607 mov r7, r0 +#if LV_USE_IMG_TRANSFORM + int32_t angle_low = angle / 10; + int32_t angle_hight = angle_low + 1; + int32_t angle_rem = angle - (angle_low * 10); + + int32_t s1 = _lv_trigo_sin(angle_low); + c068: f8df b174 ldr.w fp, [pc, #372] ; c1e0 <_lv_img_buf_get_transformed_area+0x180> +{ + c06c: f8bd 8038 ldrh.w r8, [sp, #56] ; 0x38 + c070: 9102 str r1, [sp, #8] + int32_t angle_low = angle / 10; + c072: 260a movs r6, #10 + int32_t angle_rem = angle - (angle_low * 10); + c074: f64f 7af6 movw sl, #65526 ; 0xfff6 + int32_t angle_low = angle / 10; + c078: fb93 f9f6 sdiv r9, r3, r6 + int32_t s1 = _lv_trigo_sin(angle_low); + c07c: 4648 mov r0, r9 + int32_t angle_rem = angle - (angle_low * 10); + c07e: fb19 3a0a smlabb sl, r9, sl, r3 +{ + c082: 4614 mov r4, r2 + int32_t s1 = _lv_trigo_sin(angle_low); + c084: 47d8 blx fp + int32_t angle_hight = angle_low + 1; + c086: f109 0501 add.w r5, r9, #1 + int32_t s1 = _lv_trigo_sin(angle_low); + c08a: 9003 str r0, [sp, #12] + int32_t s2 = _lv_trigo_sin(angle_hight); + c08c: b228 sxth r0, r5 + c08e: 47d8 blx fp + c090: 4605 mov r5, r0 + + int32_t c1 = _lv_trigo_sin(angle_low + 90); + c092: f109 005a add.w r0, r9, #90 ; 0x5a + c096: b200 sxth r0, r0 + c098: 47d8 blx fp + c09a: 9001 str r0, [sp, #4] + int32_t c2 = _lv_trigo_sin(angle_hight + 90); + c09c: f109 005b add.w r0, r9, #91 ; 0x5b + c0a0: b200 sxth r0, r0 + c0a2: 47d8 blx fp + + int32_t sinma = (s1 * (10 - angle_rem) + s2 * angle_rem) / 10; + int32_t cosma = (c1 * (10 - angle_rem) + c2 * angle_rem) / 10; + c0a4: 9b01 ldr r3, [sp, #4] + int32_t sinma = (s1 * (10 - angle_rem) + s2 * angle_rem) / 10; + c0a6: 9903 ldr r1, [sp, #12] + c0a8: eba6 0c0a sub.w ip, r6, sl + int32_t cosma = (c1 * (10 - angle_rem) + c2 * angle_rem) / 10; + c0ac: fb0a f000 mul.w r0, sl, r0 + c0b0: fb0c 0003 mla r0, ip, r3, r0 + + lv_coord_t xt; + lv_coord_t yt; + + lv_area_t a; + a.x1 = ((-pivot->x) * zoom) >> 8; + c0b4: 9b0f ldr r3, [sp, #60] ; 0x3c + int32_t cosma = (c1 * (10 - angle_rem) + c2 * angle_rem) / 10; + c0b6: fb90 f0f6 sdiv r0, r0, r6 + int32_t sinma = (s1 * (10 - angle_rem) + s2 * angle_rem) / 10; + c0ba: fb0a f505 mul.w r5, sl, r5 + a.x1 = ((-pivot->x) * zoom) >> 8; + c0be: f9b3 e000 ldrsh.w lr, [r3] + int32_t sinma = (s1 * (10 - angle_rem) + s2 * angle_rem) / 10; + c0c2: fb0c 5501 mla r5, ip, r1, r5 + a.y1 = ((-pivot->y) * zoom) >> 8; + c0c6: f9b3 c002 ldrsh.w ip, [r3, #2] + int32_t sinma = (s1 * (10 - angle_rem) + s2 * angle_rem) / 10; + c0ca: fb95 f5f6 sdiv r5, r5, r6 + a.x1 = ((-pivot->x) * zoom) >> 8; + c0ce: f1ce 0300 rsb r3, lr, #0 + a.y1 = ((-pivot->y) * zoom) >> 8; + c0d2: f1cc 0200 rsb r2, ip, #0 + a.x1 = ((-pivot->x) * zoom) >> 8; + c0d6: fb08 f303 mul.w r3, r8, r3 + a.y1 = ((-pivot->y) * zoom) >> 8; + c0da: fb08 f202 mul.w r2, r8, r2 + a.x2 = ((w - pivot->x) * zoom) >> 8; + a.y2 = ((h - pivot->y) * zoom) >> 8; + + xt = a.x1; + yt = a.y1; + lt.x = ((cosma * xt - sinma * yt) >> LV_TRIGO_SHIFT) + pivot->x; + c0de: f343 230f sbfx r3, r3, #8, #16 + c0e2: f342 220f sbfx r2, r2, #8, #16 + c0e6: fb00 f903 mul.w r9, r0, r3 + c0ea: fb05 fa02 mul.w sl, r5, r2 + lt.y = ((sinma * xt + cosma * yt) >> LV_TRIGO_SHIFT) + pivot->y; + c0ee: 436b muls r3, r5 + c0f0: 4342 muls r2, r0 + c0f2: 1899 adds r1, r3, r2 + c0f4: 13c9 asrs r1, r1, #15 + c0f6: fa11 f18c uxtah r1, r1, ip + c0fa: b209 sxth r1, r1 + c0fc: 9101 str r1, [sp, #4] + a.x2 = ((w - pivot->x) * zoom) >> 8; + c0fe: 9902 ldr r1, [sp, #8] + c100: eba1 010e sub.w r1, r1, lr + c104: fb08 f101 mul.w r1, r8, r1 + + xt = a.x2; + yt = a.y1; + rt.x = ((cosma * xt - sinma * yt) >> LV_TRIGO_SHIFT) + pivot->x; + c108: f341 210f sbfx r1, r1, #8, #16 + a.y2 = ((h - pivot->y) * zoom) >> 8; + c10c: eba4 040c sub.w r4, r4, ip + rt.x = ((cosma * xt - sinma * yt) >> LV_TRIGO_SHIFT) + pivot->x; + c110: fb00 fb01 mul.w fp, r0, r1 + a.y2 = ((h - pivot->y) * zoom) >> 8; + c114: fb08 f404 mul.w r4, r8, r4 + lt.x = ((cosma * xt - sinma * yt) >> LV_TRIGO_SHIFT) + pivot->x; + c118: eba9 060a sub.w r6, r9, sl + rt.y = ((sinma * xt + cosma * yt) >> LV_TRIGO_SHIFT) + pivot->y; + + xt = a.x1; + yt = a.y2; + lb.x = ((cosma * xt - sinma * yt) >> LV_TRIGO_SHIFT) + pivot->x; + c11c: f344 240f sbfx r4, r4, #8, #16 + rt.x = ((cosma * xt - sinma * yt) >> LV_TRIGO_SHIFT) + pivot->x; + c120: ebab 0a0a sub.w sl, fp, sl + rt.y = ((sinma * xt + cosma * yt) >> LV_TRIGO_SHIFT) + pivot->y; + c124: 4369 muls r1, r5 + lt.x = ((cosma * xt - sinma * yt) >> LV_TRIGO_SHIFT) + pivot->x; + c126: 13f6 asrs r6, r6, #15 + lb.x = ((cosma * xt - sinma * yt) >> LV_TRIGO_SHIFT) + pivot->x; + c128: 4365 muls r5, r4 + rt.x = ((cosma * xt - sinma * yt) >> LV_TRIGO_SHIFT) + pivot->x; + c12a: ea4f 3aea mov.w sl, sl, asr #15 + lb.y = ((sinma * xt + cosma * yt) >> LV_TRIGO_SHIFT) + pivot->y; + c12e: 4344 muls r4, r0 + lt.x = ((cosma * xt - sinma * yt) >> LV_TRIGO_SHIFT) + pivot->x; + c130: fa16 f68e uxtah r6, r6, lr + rt.x = ((cosma * xt - sinma * yt) >> LV_TRIGO_SHIFT) + pivot->x; + c134: fa1a fa8e uxtah sl, sl, lr + lb.x = ((cosma * xt - sinma * yt) >> LV_TRIGO_SHIFT) + pivot->x; + c138: eba9 0905 sub.w r9, r9, r5 + lt.x = ((cosma * xt - sinma * yt) >> LV_TRIGO_SHIFT) + pivot->x; + c13c: b236 sxth r6, r6 + rt.x = ((cosma * xt - sinma * yt) >> LV_TRIGO_SHIFT) + pivot->x; + c13e: fa0f fa8a sxth.w sl, sl + rt.y = ((sinma * xt + cosma * yt) >> LV_TRIGO_SHIFT) + pivot->y; + c142: 440a add r2, r1 + lb.y = ((sinma * xt + cosma * yt) >> LV_TRIGO_SHIFT) + pivot->y; + c144: 4423 add r3, r4 + + xt = a.x2; + yt = a.y2; + rb.x = ((cosma * xt - sinma * yt) >> LV_TRIGO_SHIFT) + pivot->x; + rb.y = ((sinma * xt + cosma * yt) >> LV_TRIGO_SHIFT) + pivot->y; + c146: 4421 add r1, r4 + lb.x = ((cosma * xt - sinma * yt) >> LV_TRIGO_SHIFT) + pivot->x; + c148: ea4f 39e9 mov.w r9, r9, asr #15 + + res->x1 = LV_MATH_MIN4(lb.x, lt.x, rb.x, rt.x); + c14c: 4556 cmp r6, sl + lb.x = ((cosma * xt - sinma * yt) >> LV_TRIGO_SHIFT) + pivot->x; + c14e: fa19 f98e uxtah r9, r9, lr + rb.x = ((cosma * xt - sinma * yt) >> LV_TRIGO_SHIFT) + pivot->x; + c152: ebab 0b05 sub.w fp, fp, r5 + rb.y = ((sinma * xt + cosma * yt) >> LV_TRIGO_SHIFT) + pivot->y; + c156: ea4f 31e1 mov.w r1, r1, asr #15 + rt.y = ((sinma * xt + cosma * yt) >> LV_TRIGO_SHIFT) + pivot->y; + c15a: ea4f 32e2 mov.w r2, r2, asr #15 + lb.y = ((sinma * xt + cosma * yt) >> LV_TRIGO_SHIFT) + pivot->y; + c15e: ea4f 33e3 mov.w r3, r3, asr #15 + lb.x = ((cosma * xt - sinma * yt) >> LV_TRIGO_SHIFT) + pivot->x; + c162: fa0f f989 sxth.w r9, r9 + rt.y = ((sinma * xt + cosma * yt) >> LV_TRIGO_SHIFT) + pivot->y; + c166: fa12 f28c uxtah r2, r2, ip + lb.y = ((sinma * xt + cosma * yt) >> LV_TRIGO_SHIFT) + pivot->y; + c16a: fa13 f38c uxtah r3, r3, ip + rb.x = ((cosma * xt - sinma * yt) >> LV_TRIGO_SHIFT) + pivot->x; + c16e: ea4f 3beb mov.w fp, fp, asr #15 + rb.y = ((sinma * xt + cosma * yt) >> LV_TRIGO_SHIFT) + pivot->y; + c172: fa11 fc8c uxtah ip, r1, ip + res->x1 = LV_MATH_MIN4(lb.x, lt.x, rb.x, rt.x); + c176: 4631 mov r1, r6 + c178: bfa8 it ge + c17a: 4651 movge r1, sl + c17c: 4549 cmp r1, r9 + rb.x = ((cosma * xt - sinma * yt) >> LV_TRIGO_SHIFT) + pivot->x; + c17e: fa1b fe8e uxtah lr, fp, lr + c182: fa0f fe8e sxth.w lr, lr + res->x1 = LV_MATH_MIN4(lb.x, lt.x, rb.x, rt.x); + c186: bfa8 it ge + c188: 4649 movge r1, r9 + c18a: 4571 cmp r1, lr + c18c: bfa8 it ge + c18e: 4671 movge r1, lr + res->x2 = LV_MATH_MAX4(lb.x, lt.x, rb.x, rt.x); + c190: 4556 cmp r6, sl + c192: bfb8 it lt + c194: 4656 movlt r6, sl + c196: 454e cmp r6, r9 + c198: bfb8 it lt + c19a: 464e movlt r6, r9 + res->x1 = LV_MATH_MIN4(lb.x, lt.x, rb.x, rt.x); + c19c: 8039 strh r1, [r7, #0] + res->y1 = LV_MATH_MIN4(lb.y, lt.y, rb.y, rt.y); + c19e: 9901 ldr r1, [sp, #4] + rt.y = ((sinma * xt + cosma * yt) >> LV_TRIGO_SHIFT) + pivot->y; + c1a0: b212 sxth r2, r2 + res->x2 = LV_MATH_MAX4(lb.x, lt.x, rb.x, rt.x); + c1a2: 4576 cmp r6, lr + c1a4: bfb8 it lt + c1a6: 4676 movlt r6, lr + res->y1 = LV_MATH_MIN4(lb.y, lt.y, rb.y, rt.y); + c1a8: 4291 cmp r1, r2 + lb.y = ((sinma * xt + cosma * yt) >> LV_TRIGO_SHIFT) + pivot->y; + c1aa: b21b sxth r3, r3 + res->y1 = LV_MATH_MIN4(lb.y, lt.y, rb.y, rt.y); + c1ac: bfa8 it ge + c1ae: 4611 movge r1, r2 + c1b0: 4299 cmp r1, r3 + rb.y = ((sinma * xt + cosma * yt) >> LV_TRIGO_SHIFT) + pivot->y; + c1b2: fa0f fc8c sxth.w ip, ip + res->y1 = LV_MATH_MIN4(lb.y, lt.y, rb.y, rt.y); + c1b6: bfa8 it ge + c1b8: 4619 movge r1, r3 + c1ba: 4561 cmp r1, ip + c1bc: bfa8 it ge + c1be: 4661 movge r1, ip + c1c0: 8079 strh r1, [r7, #2] + res->y2 = LV_MATH_MAX4(lb.y, lt.y, rb.y, rt.y); + c1c2: 9901 ldr r1, [sp, #4] + res->x2 = LV_MATH_MAX4(lb.x, lt.x, rb.x, rt.x); + c1c4: 80be strh r6, [r7, #4] + res->y2 = LV_MATH_MAX4(lb.y, lt.y, rb.y, rt.y); + c1c6: 428a cmp r2, r1 + c1c8: bfb8 it lt + c1ca: 460a movlt r2, r1 + c1cc: 4293 cmp r3, r2 + c1ce: bfb8 it lt + c1d0: 4613 movlt r3, r2 + c1d2: 4563 cmp r3, ip + c1d4: bfb8 it lt + c1d6: 4663 movlt r3, ip + c1d8: 80fb strh r3, [r7, #6] + res->x1 = 0; + res->y1 = 0; + res->x2 = w; + res->y2 = h; +#endif +} + c1da: b005 add sp, #20 + c1dc: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + c1e0: 0000e93d .word 0x0000e93d + +0000c1e4 <_lv_img_buf_transform_anti_alias>: +/** + * Continue transformation by taking the neighbors into account + * @param dsc pointer to the transformation descriptor + */ +bool _lv_img_buf_transform_anti_alias(lv_img_transform_dsc_t * dsc) +{ + c1e4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + c1e8: f890 2038 ldrb.w r2, [r0, #56] ; 0x38 + const uint8_t * src_u8 = dsc->cfg.src; + c1ec: f8d0 8000 ldr.w r8, [r0] + + /*Get the fractional part of the source pixel*/ + int xs_fract = dsc->tmp.xs & 0xff; + c1f0: f9b0 5038 ldrsh.w r5, [r0, #56] ; 0x38 + int ys_fract = dsc->tmp.ys & 0xff; + c1f4: f9b0 603a ldrsh.w r6, [r0, #58] ; 0x3a + c1f8: f890 303a ldrb.w r3, [r0, #58] ; 0x3a + int32_t xn; /*x neightboor*/ + lv_opa_t xr; /*x mix ratio*/ + + if(xs_fract < 0x70) { + c1fc: 2a6f cmp r2, #111 ; 0x6f +{ + c1fe: b089 sub sp, #36 ; 0x24 + c200: 4604 mov r4, r0 + if(xs_fract < 0x70) { + c202: f200 8092 bhi.w c32a <_lv_img_buf_transform_anti_alias+0x146> + xn = - 1; + if(dsc->tmp.xs_int + xn < 0) xn = 0; + c206: f9b0 903c ldrsh.w r9, [r0, #60] ; 0x3c + c20a: f1b9 0f00 cmp.w r9, #0 + c20e: bfd4 ite le + c210: f04f 0900 movle.w r9, #0 + c214: f04f 0901 movgt.w r9, #1 + c218: f1c9 0900 rsb r9, r9, #0 + xr = xs_fract + 0x80; + c21c: 3d80 subs r5, #128 ; 0x80 + } + else if(xs_fract > 0x90) { + xn = 1; + if(dsc->tmp.xs_int + xn >= dsc->cfg.src_w) xn = 0; + xr = (0xFF - xs_fract) + 0x80; + c21e: b2ed uxtb r5, r5 + } + + int32_t yn; /*x neightboor*/ + lv_opa_t yr; /*x mix ratio*/ + + if(ys_fract < 0x70) { + c220: 2b6f cmp r3, #111 ; 0x6f + c222: f200 8097 bhi.w c354 <_lv_img_buf_transform_anti_alias+0x170> + yn = - 1; + if(dsc->tmp.ys_int + yn < 0) yn = 0; + c226: f9b4 703e ldrsh.w r7, [r4, #62] ; 0x3e + c22a: 2f00 cmp r7, #0 + c22c: bfd4 ite le + c22e: 2700 movle r7, #0 + c230: 2701 movgt r7, #1 + c232: 427f negs r7, r7 + + yr = ys_fract + 0x80; + c234: 3e80 subs r6, #128 ; 0x80 + } + else if(ys_fract > 0x90) { + yn = 1; + if(dsc->tmp.ys_int + yn >= dsc->cfg.src_h) yn = 0; + + yr = (0xFF - ys_fract) + 0x80; + c236: b2f6 uxtb r6, r6 + else { + yn = 0; + yr = 0xFF; + } + + lv_color_t c00 = dsc->res.color; + c238: 8aa3 ldrh r3, [r4, #20] + c23a: f8ad 300a strh.w r3, [sp, #10] + lv_color_t c01; + lv_color_t c10; + lv_color_t c11; + + lv_opa_t a00 = dsc->res.opa; + c23e: 7da3 ldrb r3, [r4, #22] + c240: 9301 str r3, [sp, #4] + lv_opa_t a10 = 0; + lv_opa_t a01 = 0; + lv_opa_t a11 = 0; + + if(dsc->tmp.native_color) { + c242: f894 3034 ldrb.w r3, [r4, #52] ; 0x34 + c246: 0758 lsls r0, r3, #29 + c248: f140 80a9 bpl.w c39e <_lv_img_buf_transform_anti_alias+0x1ba> + _lv_memcpy_small(&c01, &src_u8[dsc->tmp.pxi + dsc->tmp.px_size * xn], sizeof(lv_color_t)); + c24c: f894 3044 ldrb.w r3, [r4, #68] ; 0x44 + c250: 6c21 ldr r1, [r4, #64] ; 0x40 + c252: f8df a248 ldr.w sl, [pc, #584] ; c49c <_lv_img_buf_transform_anti_alias+0x2b8> + c256: fb09 1103 mla r1, r9, r3, r1 + c25a: 2202 movs r2, #2 + c25c: 4441 add r1, r8 + c25e: a805 add r0, sp, #20 + c260: 47d0 blx sl + _lv_memcpy_small(&c10, &src_u8[dsc->tmp.pxi + dsc->cfg.src_w * dsc->tmp.px_size * yn], sizeof(lv_color_t)); + c262: 88a2 ldrh r2, [r4, #4] + c264: f894 3044 ldrb.w r3, [r4, #68] ; 0x44 + c268: 6c21 ldr r1, [r4, #64] ; 0x40 + c26a: fb13 f302 smulbb r3, r3, r2 + c26e: fb07 1103 mla r1, r7, r3, r1 + c272: 2202 movs r2, #2 + c274: 4441 add r1, r8 + c276: a806 add r0, sp, #24 + c278: 47d0 blx sl + _lv_memcpy_small(&c11, &src_u8[dsc->tmp.pxi + dsc->cfg.src_w * dsc->tmp.px_size * yn + dsc->tmp.px_size * xn], + c27a: f894 2044 ldrb.w r2, [r4, #68] ; 0x44 + c27e: 88a3 ldrh r3, [r4, #4] + c280: 6c21 ldr r1, [r4, #64] ; 0x40 + c282: fb13 f302 smulbb r3, r3, r2 + c286: fb09 1102 mla r1, r9, r2, r1 + c28a: fb07 1103 mla r1, r7, r3, r1 + c28e: 4441 add r1, r8 + c290: 2202 movs r2, #2 + c292: a807 add r0, sp, #28 + c294: 47d0 blx sl + sizeof(lv_color_t)); + if(dsc->tmp.has_alpha) { + c296: f894 3034 ldrb.w r3, [r4, #52] ; 0x34 + c29a: 0799 lsls r1, r3, #30 + c29c: d46b bmi.n c376 <_lv_img_buf_transform_anti_alias+0x192> + lv_opa_t a11 = 0; + c29e: 2000 movs r0, #0 + lv_opa_t a01 = 0; + c2a0: 4607 mov r7, r0 + lv_opa_t a10 = 0; + c2a2: 4683 mov fp, r0 + } + } + + lv_opa_t xr0 = xr; + lv_opa_t xr1 = xr; + if(dsc->tmp.has_alpha) { + c2a4: f894 3034 ldrb.w r3, [r4, #52] ; 0x34 + c2a8: 079b lsls r3, r3, #30 + c2aa: f140 80c7 bpl.w c43c <_lv_img_buf_transform_anti_alias+0x258> + lv_opa_t a0 = (a00 * xr + (a10 * (255 - xr))) >> 8; + c2ae: 9a01 ldr r2, [sp, #4] + c2b0: f1c5 03ff rsb r3, r5, #255 ; 0xff + c2b4: fb12 f105 smulbb r1, r2, r5 + c2b8: fb03 110b mla r1, r3, fp, r1 + lv_opa_t a1 = (a01 * xr + (a11 * (255 - xr))) >> 8; + c2bc: 4343 muls r3, r0 + dsc->res.opa = (a0 * yr + (a1 * (255 - yr))) >> 8; + c2be: f3c1 2107 ubfx r1, r1, #8, #8 + lv_opa_t a1 = (a01 * xr + (a11 * (255 - xr))) >> 8; + c2c2: fb15 3307 smlabb r3, r5, r7, r3 + c2c6: f3c3 2307 ubfx r3, r3, #8, #8 + dsc->res.opa = (a0 * yr + (a1 * (255 - yr))) >> 8; + c2ca: f1c6 0cff rsb ip, r6, #255 ; 0xff + c2ce: fb06 f201 mul.w r2, r6, r1 + c2d2: fb03 220c mla r2, r3, ip, r2 + c2d6: 1212 asrs r2, r2, #8 + + if(a0 <= LV_OPA_MIN && a1 <= LV_OPA_MIN) return false; + c2d8: 2905 cmp r1, #5 + dsc->res.opa = (a0 * yr + (a1 * (255 - yr))) >> 8; + c2da: 75a2 strb r2, [r4, #22] + if(a0 <= LV_OPA_MIN && a1 <= LV_OPA_MIN) return false; + c2dc: f200 80aa bhi.w c434 <_lv_img_buf_transform_anti_alias+0x250> + c2e0: 2b05 cmp r3, #5 + c2e2: f240 80d4 bls.w c48e <_lv_img_buf_transform_anti_alias+0x2aa> + if(a0 <= LV_OPA_MIN) yr = LV_OPA_TRANSP; + c2e6: 2600 movs r6, #0 + if(a1 <= LV_OPA_MIN) yr = LV_OPA_COVER; + if(a00 <= LV_OPA_MIN) xr0 = LV_OPA_TRANSP; + c2e8: 9b01 ldr r3, [sp, #4] + c2ea: 2b05 cmp r3, #5 + c2ec: bf94 ite ls + c2ee: 2200 movls r2, #0 + c2f0: 462a movhi r2, r5 + if(a10 <= LV_OPA_MIN) xr0 = LV_OPA_COVER; + c2f2: f1bb 0f05 cmp.w fp, #5 + c2f6: bf98 it ls + c2f8: 22ff movls r2, #255 ; 0xff + if(a01 <= LV_OPA_MIN) xr1 = LV_OPA_TRANSP; + c2fa: 2f05 cmp r7, #5 + c2fc: bf98 it ls + c2fe: 2500 movls r5, #0 + if(a11 <= LV_OPA_MIN) xr1 = LV_OPA_COVER; + c300: 2805 cmp r0, #5 + c302: bf98 it ls + c304: 25ff movls r5, #255 ; 0xff + xr1 = xr; + dsc->res.opa = LV_OPA_COVER; + } + + lv_color_t c0; + if(xr0 == LV_OPA_TRANSP) c0 = c01; + c306: 2a00 cmp r2, #0 + c308: f040 809c bne.w c444 <_lv_img_buf_transform_anti_alias+0x260> + c30c: f8bd 7014 ldrh.w r7, [sp, #20] + else if(xr0 == LV_OPA_COVER) c0 = c00; + else c0 = lv_color_mix(c00, c01, xr0); + + lv_color_t c1; + if(xr1 == LV_OPA_TRANSP) c1 = c11; + c310: 2d00 cmp r5, #0 + c312: f040 80a4 bne.w c45e <_lv_img_buf_transform_anti_alias+0x27a> + c316: f8bd 101c ldrh.w r1, [sp, #28] + else if(xr1 == LV_OPA_COVER) c1 = c10; + else c1 = lv_color_mix(c10, c11, xr1); + + if(yr == LV_OPA_TRANSP) dsc->res.color = c1; + c31a: 2e00 cmp r6, #0 + c31c: f040 80ad bne.w c47a <_lv_img_buf_transform_anti_alias+0x296> + c320: 82a1 strh r1, [r4, #20] + else if(yr == LV_OPA_COVER) dsc->res.color = c0; + else dsc->res.color = lv_color_mix(c0, c1, yr); + + return true; + c322: 2001 movs r0, #1 +} + c324: b009 add sp, #36 ; 0x24 + c326: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + else if(xs_fract > 0x90) { + c32a: 2a90 cmp r2, #144 ; 0x90 + c32c: d90e bls.n c34c <_lv_img_buf_transform_anti_alias+0x168> + if(dsc->tmp.xs_int + xn >= dsc->cfg.src_w) xn = 0; + c32e: f9b0 903c ldrsh.w r9, [r0, #60] ; 0x3c + c332: f9b0 2004 ldrsh.w r2, [r0, #4] + c336: f109 0901 add.w r9, r9, #1 + c33a: 4591 cmp r9, r2 + c33c: bfac ite ge + c33e: f04f 0900 movge.w r9, #0 + c342: f04f 0901 movlt.w r9, #1 + xr = (0xFF - xs_fract) + 0x80; + c346: f1c5 057f rsb r5, r5, #127 ; 0x7f + c34a: e768 b.n c21e <_lv_img_buf_transform_anti_alias+0x3a> + xr = 0xFF; + c34c: 25ff movs r5, #255 ; 0xff + xn = 0; + c34e: f04f 0900 mov.w r9, #0 + c352: e765 b.n c220 <_lv_img_buf_transform_anti_alias+0x3c> + else if(ys_fract > 0x90) { + c354: 2b90 cmp r3, #144 ; 0x90 + c356: d90b bls.n c370 <_lv_img_buf_transform_anti_alias+0x18c> + if(dsc->tmp.ys_int + yn >= dsc->cfg.src_h) yn = 0; + c358: f9b4 703e ldrsh.w r7, [r4, #62] ; 0x3e + c35c: f9b4 3006 ldrsh.w r3, [r4, #6] + c360: 3701 adds r7, #1 + c362: 429f cmp r7, r3 + c364: bfac ite ge + c366: 2700 movge r7, #0 + c368: 2701 movlt r7, #1 + yr = (0xFF - ys_fract) + 0x80; + c36a: f1c6 067f rsb r6, r6, #127 ; 0x7f + c36e: e762 b.n c236 <_lv_img_buf_transform_anti_alias+0x52> + yr = 0xFF; + c370: 26ff movs r6, #255 ; 0xff + yn = 0; + c372: 2700 movs r7, #0 + c374: e760 b.n c238 <_lv_img_buf_transform_anti_alias+0x54> + a10 = src_u8[dsc->tmp.pxi + dsc->tmp.px_size * xn + dsc->tmp.px_size - 1]; + c376: 6c22 ldr r2, [r4, #64] ; 0x40 + c378: f894 1044 ldrb.w r1, [r4, #68] ; 0x44 + a01 = src_u8[dsc->tmp.pxi + dsc->cfg.src_w * dsc->tmp.px_size * yn + dsc->tmp.px_size - 1]; + c37c: 88a3 ldrh r3, [r4, #4] + c37e: 3a01 subs r2, #1 + c380: 440a add r2, r1 + a10 = src_u8[dsc->tmp.pxi + dsc->tmp.px_size * xn + dsc->tmp.px_size - 1]; + c382: fb09 2901 mla r9, r9, r1, r2 + a01 = src_u8[dsc->tmp.pxi + dsc->cfg.src_w * dsc->tmp.px_size * yn + dsc->tmp.px_size - 1]; + c386: fb13 f301 smulbb r3, r3, r1 + c38a: 437b muls r3, r7 + c38c: eb08 0103 add.w r1, r8, r3 + a10 = src_u8[dsc->tmp.pxi + dsc->tmp.px_size * xn + dsc->tmp.px_size - 1]; + c390: f818 b009 ldrb.w fp, [r8, r9] + a01 = src_u8[dsc->tmp.pxi + dsc->cfg.src_w * dsc->tmp.px_size * yn + dsc->tmp.px_size - 1]; + c394: 5c8f ldrb r7, [r1, r2] + a11 = src_u8[dsc->tmp.pxi + dsc->cfg.src_w * dsc->tmp.px_size * yn + dsc->tmp.px_size * xn + dsc->tmp.px_size - 1]; + c396: 44c8 add r8, r9 + c398: f818 0003 ldrb.w r0, [r8, r3] + c39c: e782 b.n c2a4 <_lv_img_buf_transform_anti_alias+0xc0> + c01 = lv_img_buf_get_px_color(&dsc->tmp.img_dsc, dsc->tmp.xs_int + xn, dsc->tmp.ys_int, dsc->cfg.color); + c39e: 8fa3 ldrh r3, [r4, #60] ; 0x3c + c3a0: f8df b0fc ldr.w fp, [pc, #252] ; c4a0 <_lv_img_buf_transform_anti_alias+0x2bc> + c3a4: f9b4 203e ldrsh.w r2, [r4, #62] ; 0x3e + c3a8: f104 0a18 add.w sl, r4, #24 + c3ac: fa13 f189 uxtah r1, r3, r9 + c3b0: b209 sxth r1, r1 + c3b2: 8a23 ldrh r3, [r4, #16] + c3b4: 4650 mov r0, sl + c3b6: 47d8 blx fp + c10 = lv_img_buf_get_px_color(&dsc->tmp.img_dsc, dsc->tmp.xs_int, dsc->tmp.ys_int + yn, dsc->cfg.color); + c3b8: 8fe3 ldrh r3, [r4, #62] ; 0x3e + c3ba: f9b4 103c ldrsh.w r1, [r4, #60] ; 0x3c + c01 = lv_img_buf_get_px_color(&dsc->tmp.img_dsc, dsc->tmp.xs_int + xn, dsc->tmp.ys_int, dsc->cfg.color); + c3be: f8ad 0014 strh.w r0, [sp, #20] + c10 = lv_img_buf_get_px_color(&dsc->tmp.img_dsc, dsc->tmp.xs_int, dsc->tmp.ys_int + yn, dsc->cfg.color); + c3c2: fa13 f287 uxtah r2, r3, r7 + c3c6: b212 sxth r2, r2 + c3c8: 8a23 ldrh r3, [r4, #16] + c3ca: 4650 mov r0, sl + c3cc: 47d8 blx fp + c11 = lv_img_buf_get_px_color(&dsc->tmp.img_dsc, dsc->tmp.xs_int + xn, dsc->tmp.ys_int + yn, dsc->cfg.color); + c3ce: 8fe2 ldrh r2, [r4, #62] ; 0x3e + c3d0: 8fa1 ldrh r1, [r4, #60] ; 0x3c + c3d2: 8a23 ldrh r3, [r4, #16] + c10 = lv_img_buf_get_px_color(&dsc->tmp.img_dsc, dsc->tmp.xs_int, dsc->tmp.ys_int + yn, dsc->cfg.color); + c3d4: f8ad 0018 strh.w r0, [sp, #24] + c01 = lv_img_buf_get_px_color(&dsc->tmp.img_dsc, dsc->tmp.xs_int + xn, dsc->tmp.ys_int, dsc->cfg.color); + c3d8: fa1f f889 uxth.w r8, r9 + c10 = lv_img_buf_get_px_color(&dsc->tmp.img_dsc, dsc->tmp.xs_int, dsc->tmp.ys_int + yn, dsc->cfg.color); + c3dc: fa1f f987 uxth.w r9, r7 + c11 = lv_img_buf_get_px_color(&dsc->tmp.img_dsc, dsc->tmp.xs_int + xn, dsc->tmp.ys_int + yn, dsc->cfg.color); + c3e0: 444a add r2, r9 + c3e2: 4441 add r1, r8 + c3e4: b212 sxth r2, r2 + c3e6: b209 sxth r1, r1 + c3e8: 4650 mov r0, sl + c3ea: 47d8 blx fp + if(dsc->tmp.has_alpha) { + c3ec: f894 3034 ldrb.w r3, [r4, #52] ; 0x34 + c11 = lv_img_buf_get_px_color(&dsc->tmp.img_dsc, dsc->tmp.xs_int + xn, dsc->tmp.ys_int + yn, dsc->cfg.color); + c3f0: f8ad 001c strh.w r0, [sp, #28] + if(dsc->tmp.has_alpha) { + c3f4: 079a lsls r2, r3, #30 + c3f6: f57f af52 bpl.w c29e <_lv_img_buf_transform_anti_alias+0xba> + a10 = lv_img_buf_get_px_alpha(&dsc->tmp.img_dsc, dsc->tmp.xs_int + xn, dsc->tmp.ys_int); + c3fa: f9b4 703c ldrsh.w r7, [r4, #60] ; 0x3c + c3fe: f9b4 203e ldrsh.w r2, [r4, #62] ; 0x3e + c402: 4b24 ldr r3, [pc, #144] ; (c494 <_lv_img_buf_transform_anti_alias+0x2b0>) + c404: 9203 str r2, [sp, #12] + c406: 44b8 add r8, r7 + c408: fa0f f888 sxth.w r8, r8 + c40c: 4641 mov r1, r8 + c40e: 4650 mov r0, sl + c410: 4798 blx r3 + a01 = lv_img_buf_get_px_alpha(&dsc->tmp.img_dsc, dsc->tmp.xs_int, dsc->tmp.ys_int + yn); + c412: 9a03 ldr r2, [sp, #12] + c414: 4b1f ldr r3, [pc, #124] ; (c494 <_lv_img_buf_transform_anti_alias+0x2b0>) + c416: 4491 add r9, r2 + c418: fa0f f289 sxth.w r2, r9 + c41c: 4639 mov r1, r7 + a10 = lv_img_buf_get_px_alpha(&dsc->tmp.img_dsc, dsc->tmp.xs_int + xn, dsc->tmp.ys_int); + c41e: 4683 mov fp, r0 + a01 = lv_img_buf_get_px_alpha(&dsc->tmp.img_dsc, dsc->tmp.xs_int, dsc->tmp.ys_int + yn); + c420: 4650 mov r0, sl + c422: 9203 str r2, [sp, #12] + c424: 4798 blx r3 + a11 = lv_img_buf_get_px_alpha(&dsc->tmp.img_dsc, dsc->tmp.xs_int + xn, dsc->tmp.ys_int + yn); + c426: 9a03 ldr r2, [sp, #12] + c428: 4b1a ldr r3, [pc, #104] ; (c494 <_lv_img_buf_transform_anti_alias+0x2b0>) + a01 = lv_img_buf_get_px_alpha(&dsc->tmp.img_dsc, dsc->tmp.xs_int, dsc->tmp.ys_int + yn); + c42a: 4607 mov r7, r0 + a11 = lv_img_buf_get_px_alpha(&dsc->tmp.img_dsc, dsc->tmp.xs_int + xn, dsc->tmp.ys_int + yn); + c42c: 4641 mov r1, r8 + c42e: 4650 mov r0, sl + c430: 4798 blx r3 + c432: e737 b.n c2a4 <_lv_img_buf_transform_anti_alias+0xc0> + if(a1 <= LV_OPA_MIN) yr = LV_OPA_COVER; + c434: 2b05 cmp r3, #5 + c436: bf98 it ls + c438: 26ff movls r6, #255 ; 0xff + c43a: e755 b.n c2e8 <_lv_img_buf_transform_anti_alias+0x104> + dsc->res.opa = LV_OPA_COVER; + c43c: 23ff movs r3, #255 ; 0xff + c43e: 75a3 strb r3, [r4, #22] + xr0 = xr; + c440: 462a mov r2, r5 + c442: e760 b.n c306 <_lv_img_buf_transform_anti_alias+0x122> + else if(xr0 == LV_OPA_COVER) c0 = c00; + c444: 2aff cmp r2, #255 ; 0xff + c446: d102 bne.n c44e <_lv_img_buf_transform_anti_alias+0x26a> + c448: f8bd 700a ldrh.w r7, [sp, #10] + c44c: e760 b.n c310 <_lv_img_buf_transform_anti_alias+0x12c> + else c0 = lv_color_mix(c00, c01, xr0); + c44e: f8bd 1014 ldrh.w r1, [sp, #20] + c452: f8bd 000a ldrh.w r0, [sp, #10] + c456: 4b10 ldr r3, [pc, #64] ; (c498 <_lv_img_buf_transform_anti_alias+0x2b4>) + c458: 4798 blx r3 + c45a: 4607 mov r7, r0 + c45c: e758 b.n c310 <_lv_img_buf_transform_anti_alias+0x12c> + else if(xr1 == LV_OPA_COVER) c1 = c10; + c45e: 2dff cmp r5, #255 ; 0xff + c460: d102 bne.n c468 <_lv_img_buf_transform_anti_alias+0x284> + c462: f8bd 1018 ldrh.w r1, [sp, #24] + c466: e758 b.n c31a <_lv_img_buf_transform_anti_alias+0x136> + else c1 = lv_color_mix(c10, c11, xr1); + c468: f8bd 101c ldrh.w r1, [sp, #28] + c46c: f8bd 0018 ldrh.w r0, [sp, #24] + c470: 4b09 ldr r3, [pc, #36] ; (c498 <_lv_img_buf_transform_anti_alias+0x2b4>) + c472: 462a mov r2, r5 + c474: 4798 blx r3 + c476: 4601 mov r1, r0 + c478: e74f b.n c31a <_lv_img_buf_transform_anti_alias+0x136> + else if(yr == LV_OPA_COVER) dsc->res.color = c0; + c47a: 2eff cmp r6, #255 ; 0xff + c47c: d101 bne.n c482 <_lv_img_buf_transform_anti_alias+0x29e> + c47e: 82a7 strh r7, [r4, #20] + c480: e74f b.n c322 <_lv_img_buf_transform_anti_alias+0x13e> + else dsc->res.color = lv_color_mix(c0, c1, yr); + c482: 4b05 ldr r3, [pc, #20] ; (c498 <_lv_img_buf_transform_anti_alias+0x2b4>) + c484: 4632 mov r2, r6 + c486: 4638 mov r0, r7 + c488: 4798 blx r3 + c48a: 82a0 strh r0, [r4, #20] + c48c: e749 b.n c322 <_lv_img_buf_transform_anti_alias+0x13e> + if(a0 <= LV_OPA_MIN && a1 <= LV_OPA_MIN) return false; + c48e: 2000 movs r0, #0 + c490: e748 b.n c324 <_lv_img_buf_transform_anti_alias+0x140> + c492: bf00 nop + c494: 0000be79 .word 0x0000be79 + c498: 0000bd25 .word 0x0000bd25 + c49c: 0000bd75 .word 0x0000bd75 + c4a0: 0000bd89 .word 0x0000bd89 + +0000c4a4 <_lv_img_cache_open>: + * @param src source of the image. Path to file or pointer to an `lv_img_dsc_t` variable + * @param style style of the image + * @return pointer to the cache entry or NULL if can open the image + */ +lv_img_cache_entry_t * _lv_img_cache_open(const void * src, lv_color_t color) +{ + c4a4: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} + if(entry_cnt == 0) { + c4a8: f8df 8190 ldr.w r8, [pc, #400] ; c63c <_lv_img_cache_open+0x198> + c4ac: f8b8 4000 ldrh.w r4, [r8] +{ + c4b0: 4605 mov r5, r0 + c4b2: 460e mov r6, r1 + if(entry_cnt == 0) { + c4b4: b95c cbnz r4, c4ce <_lv_img_cache_open+0x2a> + LV_LOG_WARN("lv_img_cache_open: the cache size is 0"); + c4b6: 4b52 ldr r3, [pc, #328] ; (c600 <_lv_img_cache_open+0x15c>) + c4b8: 9300 str r3, [sp, #0] + c4ba: 4952 ldr r1, [pc, #328] ; (c604 <_lv_img_cache_open+0x160>) + c4bc: 4b52 ldr r3, [pc, #328] ; (c608 <_lv_img_cache_open+0x164>) + c4be: 4d53 ldr r5, [pc, #332] ; (c60c <_lv_img_cache_open+0x168>) + c4c0: 2244 movs r2, #68 ; 0x44 + c4c2: 2002 movs r0, #2 + c4c4: 47a8 blx r5 + + if(cached_src->dec_dsc.time_to_open == 0) cached_src->dec_dsc.time_to_open = 1; + } + + return cached_src; +} + c4c6: 4620 mov r0, r4 + c4c8: b003 add sp, #12 + c4ca: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + lv_img_cache_entry_t * cache = LV_GC_ROOT(_lv_img_cache_array); + c4ce: 4b50 ldr r3, [pc, #320] ; (c610 <_lv_img_cache_open+0x16c>) + if(cache[i].life > INT32_MIN + LV_IMG_CACHE_AGING) { + c4d0: 4850 ldr r0, [pc, #320] ; (c614 <_lv_img_cache_open+0x170>) + lv_img_cache_entry_t * cache = LV_GC_ROOT(_lv_img_cache_array); + c4d2: 681f ldr r7, [r3, #0] + for(i = 0; i < entry_cnt; i++) { + c4d4: 2300 movs r3, #0 + c4d6: 463a mov r2, r7 + if(cache[i].life > INT32_MIN + LV_IMG_CACHE_AGING) { + c4d8: 6a11 ldr r1, [r2, #32] + for(i = 0; i < entry_cnt; i++) { + c4da: 3301 adds r3, #1 + if(cache[i].life > INT32_MIN + LV_IMG_CACHE_AGING) { + c4dc: 4281 cmp r1, r0 + cache[i].life -= LV_IMG_CACHE_AGING; + c4de: bfa8 it ge + c4e0: f101 31ff addge.w r1, r1, #4294967295 ; 0xffffffff + for(i = 0; i < entry_cnt; i++) { + c4e4: b29b uxth r3, r3 + cache[i].life -= LV_IMG_CACHE_AGING; + c4e6: bfa8 it ge + c4e8: 6211 strge r1, [r2, #32] + for(i = 0; i < entry_cnt; i++) { + c4ea: 429c cmp r4, r3 + c4ec: f102 0224 add.w r2, r2, #36 ; 0x24 + c4f0: d1f2 bne.n c4d8 <_lv_img_cache_open+0x34> + if(strcmp(cache[i].dec_dsc.src, src) == 0) match = true; + c4f2: f8df b14c ldr.w fp, [pc, #332] ; c640 <_lv_img_cache_open+0x19c> + c4f6: f04f 0a00 mov.w sl, #0 + lv_img_src_t src_type = lv_img_src_get_type(cache[i].dec_dsc.src); + c4fa: f04f 0924 mov.w r9, #36 ; 0x24 + for(i = 0; i < entry_cnt; i++) { + c4fe: f8b8 1000 ldrh.w r1, [r8] + c502: fa1f f28a uxth.w r2, sl + c506: 4291 cmp r1, r2 + c508: d839 bhi.n c57e <_lv_img_cache_open+0xda> + c50a: f107 0224 add.w r2, r7, #36 ; 0x24 + cached_src = &cache[0]; + c50e: 463c mov r4, r7 + for(i = 1; i < entry_cnt; i++) { + c510: 2301 movs r3, #1 + c512: 4299 cmp r1, r3 + c514: d856 bhi.n c5c4 <_lv_img_cache_open+0x120> + if(cached_src->dec_dsc.src) { + c516: 6863 ldr r3, [r4, #4] + c518: f8df 80f0 ldr.w r8, [pc, #240] ; c60c <_lv_img_cache_open+0x168> + c51c: 2b00 cmp r3, #0 + c51e: d05a beq.n c5d6 <_lv_img_cache_open+0x132> + lv_img_decoder_close(&cached_src->dec_dsc); + c520: 4b3d ldr r3, [pc, #244] ; (c618 <_lv_img_cache_open+0x174>) + c522: 4620 mov r0, r4 + c524: 4798 blx r3 + LV_LOG_INFO("image draw: cache miss, close and reuse an entry"); + c526: 4b3d ldr r3, [pc, #244] ; (c61c <_lv_img_cache_open+0x178>) + c528: 9300 str r3, [sp, #0] + c52a: 4b37 ldr r3, [pc, #220] ; (c608 <_lv_img_cache_open+0x164>) + c52c: 2277 movs r2, #119 ; 0x77 + LV_LOG_INFO("image draw: cache miss, cached to an empty entry"); + c52e: 4935 ldr r1, [pc, #212] ; (c604 <_lv_img_cache_open+0x160>) + c530: 2001 movs r0, #1 + c532: 47c0 blx r8 + t_start = lv_tick_get(); + c534: 4b3a ldr r3, [pc, #232] ; (c620 <_lv_img_cache_open+0x17c>) + c536: 4798 blx r3 + cached_src->dec_dsc.time_to_open = 0; + c538: f04f 0900 mov.w r9, #0 + lv_res_t open_res = lv_img_decoder_open(&cached_src->dec_dsc, src, color); + c53c: 4629 mov r1, r5 + c53e: 4b39 ldr r3, [pc, #228] ; (c624 <_lv_img_cache_open+0x180>) + cached_src->dec_dsc.time_to_open = 0; + c540: f8c4 9014 str.w r9, [r4, #20] + t_start = lv_tick_get(); + c544: 4607 mov r7, r0 + lv_res_t open_res = lv_img_decoder_open(&cached_src->dec_dsc, src, color); + c546: 4632 mov r2, r6 + c548: 4620 mov r0, r4 + c54a: 4798 blx r3 + if(open_res == LV_RES_INV) { + c54c: 4605 mov r5, r0 + c54e: 2800 cmp r0, #0 + c550: d146 bne.n c5e0 <_lv_img_cache_open+0x13c> + LV_LOG_WARN("Image draw cannot open the image resource"); + c552: 4b35 ldr r3, [pc, #212] ; (c628 <_lv_img_cache_open+0x184>) + c554: 492b ldr r1, [pc, #172] ; (c604 <_lv_img_cache_open+0x160>) + c556: 9300 str r3, [sp, #0] + c558: 2283 movs r2, #131 ; 0x83 + c55a: 4b2b ldr r3, [pc, #172] ; (c608 <_lv_img_cache_open+0x164>) + _lv_memset_00(&cached_src->dec_dsc, sizeof(lv_img_decoder_dsc_t)); + c55c: 4e33 ldr r6, [pc, #204] ; (c62c <_lv_img_cache_open+0x188>) + LV_LOG_WARN("Image draw cannot open the image resource"); + c55e: 2002 movs r0, #2 + c560: 47c0 blx r8 + lv_img_decoder_close(&cached_src->dec_dsc); + c562: 4b2d ldr r3, [pc, #180] ; (c618 <_lv_img_cache_open+0x174>) + c564: 4620 mov r0, r4 + c566: 4798 blx r3 + _lv_memset_00(&cached_src->dec_dsc, sizeof(lv_img_decoder_dsc_t)); + c568: 4620 mov r0, r4 + c56a: 2120 movs r1, #32 + c56c: 47b0 blx r6 + _lv_memset_00(cached_src, sizeof(lv_img_cache_entry_t)); + c56e: 4620 mov r0, r4 + c570: 2124 movs r1, #36 ; 0x24 + c572: 47b0 blx r6 + cached_src->life = INT32_MIN; /*Make the empty entry very "weak" to force its use */ + c574: f04f 4300 mov.w r3, #2147483648 ; 0x80000000 + c578: 6223 str r3, [r4, #32] + return NULL; + c57a: 462c mov r4, r5 + c57c: e7a3 b.n c4c6 <_lv_img_cache_open+0x22> + lv_img_src_t src_type = lv_img_src_get_type(cache[i].dec_dsc.src); + c57e: fa1f f48a uxth.w r4, sl + c582: fb09 7404 mla r4, r9, r4, r7 + c586: 4b2a ldr r3, [pc, #168] ; (c630 <_lv_img_cache_open+0x18c>) + c588: 6860 ldr r0, [r4, #4] + c58a: 4798 blx r3 + if(src_type == LV_IMG_SRC_VARIABLE) { + c58c: b980 cbnz r0, c5b0 <_lv_img_cache_open+0x10c> + if(cache[i].dec_dsc.src == src && cache[i].dec_dsc.color.full == color.full) match = true; + c58e: 6862 ldr r2, [r4, #4] + c590: 42aa cmp r2, r5 + c592: d114 bne.n c5be <_lv_img_cache_open+0x11a> + c594: 8921 ldrh r1, [r4, #8] + c596: b2b2 uxth r2, r6 + c598: 4291 cmp r1, r2 + c59a: d110 bne.n c5be <_lv_img_cache_open+0x11a> + cached_src->life += cached_src->dec_dsc.time_to_open * LV_IMG_CACHE_LIFE_GAIN; + c59c: 6a23 ldr r3, [r4, #32] + c59e: 6962 ldr r2, [r4, #20] + c5a0: 4413 add r3, r2 + c5a2: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 + c5a6: bfa8 it ge + c5a8: f44f 737a movge.w r3, #1000 ; 0x3e8 + c5ac: 6223 str r3, [r4, #32] + if(cached_src == NULL) { + c5ae: e78a b.n c4c6 <_lv_img_cache_open+0x22> + else if(src_type == LV_IMG_SRC_FILE) { + c5b0: 2801 cmp r0, #1 + c5b2: d104 bne.n c5be <_lv_img_cache_open+0x11a> + if(strcmp(cache[i].dec_dsc.src, src) == 0) match = true; + c5b4: 6860 ldr r0, [r4, #4] + c5b6: 4629 mov r1, r5 + c5b8: 47d8 blx fp + c5ba: 2800 cmp r0, #0 + c5bc: d0ee beq.n c59c <_lv_img_cache_open+0xf8> + for(i = 0; i < entry_cnt; i++) { + c5be: f10a 0a01 add.w sl, sl, #1 + c5c2: e79c b.n c4fe <_lv_img_cache_open+0x5a> + if(cache[i].life < cached_src->life) { + c5c4: 6a17 ldr r7, [r2, #32] + c5c6: 6a20 ldr r0, [r4, #32] + for(i = 1; i < entry_cnt; i++) { + c5c8: 3301 adds r3, #1 + if(cache[i].life < cached_src->life) { + c5ca: 4287 cmp r7, r0 + c5cc: bfb8 it lt + c5ce: 4614 movlt r4, r2 + for(i = 1; i < entry_cnt; i++) { + c5d0: b29b uxth r3, r3 + c5d2: 3224 adds r2, #36 ; 0x24 + c5d4: e79d b.n c512 <_lv_img_cache_open+0x6e> + LV_LOG_INFO("image draw: cache miss, cached to an empty entry"); + c5d6: 4b17 ldr r3, [pc, #92] ; (c634 <_lv_img_cache_open+0x190>) + c5d8: 9300 str r3, [sp, #0] + c5da: 227a movs r2, #122 ; 0x7a + c5dc: 4b0a ldr r3, [pc, #40] ; (c608 <_lv_img_cache_open+0x164>) + c5de: e7a6 b.n c52e <_lv_img_cache_open+0x8a> + if(cached_src->dec_dsc.time_to_open == 0) { + c5e0: 6963 ldr r3, [r4, #20] + cached_src->life = 0; + c5e2: f8c4 9020 str.w r9, [r4, #32] + if(cached_src->dec_dsc.time_to_open == 0) { + c5e6: 2b00 cmp r3, #0 + c5e8: f47f af6d bne.w c4c6 <_lv_img_cache_open+0x22> + cached_src->dec_dsc.time_to_open = lv_tick_elaps(t_start); + c5ec: 4b12 ldr r3, [pc, #72] ; (c638 <_lv_img_cache_open+0x194>) + c5ee: 4638 mov r0, r7 + c5f0: 4798 blx r3 + if(cached_src->dec_dsc.time_to_open == 0) cached_src->dec_dsc.time_to_open = 1; + c5f2: b108 cbz r0, c5f8 <_lv_img_cache_open+0x154> + cached_src->dec_dsc.time_to_open = lv_tick_elaps(t_start); + c5f4: 6160 str r0, [r4, #20] + c5f6: e766 b.n c4c6 <_lv_img_cache_open+0x22> + if(cached_src->dec_dsc.time_to_open == 0) cached_src->dec_dsc.time_to_open = 1; + c5f8: 2301 movs r3, #1 + c5fa: 6163 str r3, [r4, #20] + c5fc: e763 b.n c4c6 <_lv_img_cache_open+0x22> + c5fe: bf00 nop + c600: 0001fe5b .word 0x0001fe5b + c604: 0001fe26 .word 0x0001fe26 + c608: 0001ff0e .word 0x0001ff0e + c60c: 0000e8e9 .word 0x0000e8e9 + c610: 2000866c .word 0x2000866c + c614: 80000002 .word 0x80000002 + c618: 0000d04d .word 0x0000d04d + c61c: 0001fe82 .word 0x0001fe82 + c620: 0000da49 .word 0x0000da49 + c624: 0000cf7d .word 0x0000cf7d + c628: 0001fee4 .word 0x0001fee4 + c62c: 0000f019 .word 0x0000f019 + c630: 00007805 .word 0x00007805 + c634: 0001feb3 .word 0x0001feb3 + c638: 0000da5d .word 0x0000da5d + c63c: 200085d0 .word 0x200085d0 + c640: 00016315 .word 0x00016315 + +0000c644 : + * @param src an image source path to a file or pointer to an `lv_img_dsc_t` variable. + */ +void lv_img_cache_invalidate_src(const void * src) +{ + + lv_img_cache_entry_t * cache = LV_GC_ROOT(_lv_img_cache_array); + c644: 4b14 ldr r3, [pc, #80] ; (c698 ) +{ + c646: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr} + lv_img_cache_entry_t * cache = LV_GC_ROOT(_lv_img_cache_array); + c64a: 681f ldr r7, [r3, #0] + + uint16_t i; + for(i = 0; i < entry_cnt; i++) { + c64c: 4e13 ldr r6, [pc, #76] ; (c69c ) + if(cache[i].dec_dsc.src == src || src == NULL) { + if(cache[i].dec_dsc.src != NULL) { + lv_img_decoder_close(&cache[i].dec_dsc); + } + + _lv_memset_00(&cache[i].dec_dsc, sizeof(lv_img_decoder_dsc_t)); + c64e: 4d14 ldr r5, [pc, #80] ; (c6a0 ) + lv_img_decoder_close(&cache[i].dec_dsc); + c650: f8df 8050 ldr.w r8, [pc, #80] ; c6a4 +{ + c654: 4604 mov r4, r0 + for(i = 0; i < entry_cnt; i++) { + c656: f04f 0900 mov.w r9, #0 + c65a: 8832 ldrh r2, [r6, #0] + c65c: fa1f f389 uxth.w r3, r9 + c660: 429a cmp r2, r3 + c662: d802 bhi.n c66a + _lv_memset_00(&cache[i], sizeof(lv_img_cache_entry_t)); + } + } +} + c664: b003 add sp, #12 + c666: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + if(cache[i].dec_dsc.src == src || src == NULL) { + c66a: fa1f f389 uxth.w r3, r9 + c66e: 2224 movs r2, #36 ; 0x24 + c670: fb02 7003 mla r0, r2, r3, r7 + c674: 6843 ldr r3, [r0, #4] + c676: 42a3 cmp r3, r4 + c678: d000 beq.n c67c + c67a: b94c cbnz r4, c690 + if(cache[i].dec_dsc.src != NULL) { + c67c: b113 cbz r3, c684 + lv_img_decoder_close(&cache[i].dec_dsc); + c67e: 9001 str r0, [sp, #4] + c680: 47c0 blx r8 + c682: 9801 ldr r0, [sp, #4] + _lv_memset_00(&cache[i].dec_dsc, sizeof(lv_img_decoder_dsc_t)); + c684: 9001 str r0, [sp, #4] + c686: 2120 movs r1, #32 + c688: 47a8 blx r5 + _lv_memset_00(&cache[i], sizeof(lv_img_cache_entry_t)); + c68a: 9801 ldr r0, [sp, #4] + c68c: 2124 movs r1, #36 ; 0x24 + c68e: 47a8 blx r5 + for(i = 0; i < entry_cnt; i++) { + c690: f109 0901 add.w r9, r9, #1 + c694: e7e1 b.n c65a + c696: bf00 nop + c698: 2000866c .word 0x2000866c + c69c: 200085d0 .word 0x200085d0 + c6a0: 0000f019 .word 0x0000f019 + c6a4: 0000d04d .word 0x0000d04d + +0000c6a8 : +{ + c6a8: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr} + if(LV_GC_ROOT(_lv_img_cache_array) != NULL) { + c6ac: 4c1f ldr r4, [pc, #124] ; (c72c ) + c6ae: 6823 ldr r3, [r4, #0] +{ + c6b0: 4605 mov r5, r0 + if(LV_GC_ROOT(_lv_img_cache_array) != NULL) { + c6b2: b12b cbz r3, c6c0 + lv_img_cache_invalidate_src(NULL); + c6b4: 4b1e ldr r3, [pc, #120] ; (c730 ) + c6b6: 2000 movs r0, #0 + c6b8: 4798 blx r3 + lv_mem_free(LV_GC_ROOT(_lv_img_cache_array)); + c6ba: 6820 ldr r0, [r4, #0] + c6bc: 4b1d ldr r3, [pc, #116] ; (c734 ) + c6be: 4798 blx r3 + LV_GC_ROOT(_lv_img_cache_array) = lv_mem_alloc(sizeof(lv_img_cache_entry_t) * new_entry_cnt); + c6c0: 2724 movs r7, #36 ; 0x24 + c6c2: 4b1d ldr r3, [pc, #116] ; (c738 ) + c6c4: fb07 f005 mul.w r0, r7, r5 + c6c8: 4798 blx r3 + LV_ASSERT_MEM(LV_GC_ROOT(_lv_img_cache_array)); + c6ca: 4b1c ldr r3, [pc, #112] ; (c73c ) + LV_GC_ROOT(_lv_img_cache_array) = lv_mem_alloc(sizeof(lv_img_cache_entry_t) * new_entry_cnt); + c6cc: 6020 str r0, [r4, #0] + LV_ASSERT_MEM(LV_GC_ROOT(_lv_img_cache_array)); + c6ce: 4798 blx r3 + c6d0: 4606 mov r6, r0 + c6d2: b960 cbnz r0, c6ee + c6d4: 4b1a ldr r3, [pc, #104] ; (c740 ) + c6d6: 491b ldr r1, [pc, #108] ; (c744 ) + c6d8: 9300 str r3, [sp, #0] + c6da: 22a8 movs r2, #168 ; 0xa8 + c6dc: 2003 movs r0, #3 + c6de: 4d1a ldr r5, [pc, #104] ; (c748 ) + c6e0: 47a8 blx r5 + c6e2: 6822 ldr r2, [r4, #0] + c6e4: 4819 ldr r0, [pc, #100] ; (c74c ) + c6e6: 491a ldr r1, [pc, #104] ; (c750 ) + c6e8: 4633 mov r3, r6 + c6ea: 4788 blx r1 + c6ec: e7fe b.n c6ec + if(LV_GC_ROOT(_lv_img_cache_array) == NULL) { + c6ee: 6823 ldr r3, [r4, #0] + c6f0: f8df 8060 ldr.w r8, [pc, #96] ; c754 + c6f4: b923 cbnz r3, c700 + entry_cnt = 0; + c6f6: f8a8 3000 strh.w r3, [r8] +} + c6fa: b003 add sp, #12 + c6fc: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + _lv_memset_00(&LV_GC_ROOT(_lv_img_cache_array)[i].dec_dsc, sizeof(lv_img_decoder_dsc_t)); + c700: f8df 9054 ldr.w r9, [pc, #84] ; c758 + entry_cnt = new_entry_cnt; + c704: f8a8 5000 strh.w r5, [r8] + for(i = 0; i < entry_cnt; i++) { + c708: 2500 movs r5, #0 + c70a: f8b8 2000 ldrh.w r2, [r8] + c70e: b2ab uxth r3, r5 + c710: 429a cmp r2, r3 + c712: d9f2 bls.n c6fa + _lv_memset_00(&LV_GC_ROOT(_lv_img_cache_array)[i].dec_dsc, sizeof(lv_img_decoder_dsc_t)); + c714: 6820 ldr r0, [r4, #0] + c716: b2ae uxth r6, r5 + c718: 437e muls r6, r7 + c71a: 2120 movs r1, #32 + c71c: 4430 add r0, r6 + c71e: 47c8 blx r9 + _lv_memset_00(&LV_GC_ROOT(_lv_img_cache_array)[i], sizeof(lv_img_cache_entry_t)); + c720: 6820 ldr r0, [r4, #0] + c722: 2124 movs r1, #36 ; 0x24 + c724: 4430 add r0, r6 + c726: 47c8 blx r9 + for(i = 0; i < entry_cnt; i++) { + c728: 3501 adds r5, #1 + c72a: e7ee b.n c70a + c72c: 2000866c .word 0x2000866c + c730: 0000c645 .word 0x0000c645 + c734: 0000eae5 .word 0x0000eae5 + c738: 0000ea2d .word 0x0000ea2d + c73c: 000017e1 .word 0x000017e1 + c740: 0001ff21 .word 0x0001ff21 + c744: 0001fe26 .word 0x0001fe26 + c748: 0000e8e9 .word 0x0000e8e9 + c74c: 0001edbe .word 0x0001edbe + c750: 000017e9 .word 0x000017e9 + c754: 200085d0 .word 0x200085d0 + c758: 0000f019 .word 0x0000f019 + +0000c75c : + * @param src the image source: pointer to an `lv_img_dsc_t` variable, a file path or a symbol + * @param header store the image data here + * @return LV_RES_OK: the info is successfully stored in `header`; LV_RES_INV: unknown format or other error. + */ +lv_res_t lv_img_decoder_built_in_info(lv_img_decoder_t * decoder, const void * src, lv_img_header_t * header) +{ + c75c: b570 push {r4, r5, r6, lr} + (void)decoder; /*Unused*/ + + lv_img_src_t src_type = lv_img_src_get_type(src); + c75e: 4b2c ldr r3, [pc, #176] ; (c810 ) +{ + c760: b086 sub sp, #24 + lv_img_src_t src_type = lv_img_src_get_type(src); + c762: 4608 mov r0, r1 +{ + c764: 460e mov r6, r1 + c766: 4615 mov r5, r2 + lv_img_src_t src_type = lv_img_src_get_type(src); + c768: 4798 blx r3 + if(src_type == LV_IMG_SRC_VARIABLE) { + c76a: 4604 mov r4, r0 + c76c: b9d8 cbnz r0, c7a6 + lv_img_cf_t cf = ((lv_img_dsc_t *)src)->header.cf; + c76e: 7833 ldrb r3, [r6, #0] + c770: f3c3 0304 ubfx r3, r3, #0, #5 + if(cf < CF_BUILT_IN_FIRST || cf > CF_BUILT_IN_LAST) return LV_RES_INV; + c774: 3b04 subs r3, #4 + c776: b2db uxtb r3, r3 + c778: 2b0a cmp r3, #10 + c77a: d811 bhi.n c7a0 + + header->w = ((lv_img_dsc_t *)src)->header.w; + header->h = ((lv_img_dsc_t *)src)->header.h; + c77c: 8873 ldrh r3, [r6, #2] + c77e: 886a ldrh r2, [r5, #2] + lv_img_cf_t cf = ((lv_img_dsc_t *)src)->header.cf; + c780: 6831 ldr r1, [r6, #0] + header->h = ((lv_img_dsc_t *)src)->header.h; + c782: f3c3 134a ubfx r3, r3, #5, #11 + c786: f363 124f bfi r2, r3, #5, #11 + c78a: 806a strh r2, [r5, #2] + header->cf = ((lv_img_dsc_t *)src)->header.cf; + c78c: 682b ldr r3, [r5, #0] + c78e: 4a21 ldr r2, [pc, #132] ; (c814 ) + c790: f023 131f bic.w r3, r3, #2031647 ; 0x1f001f + c794: f423 437c bic.w r3, r3, #64512 ; 0xfc00 + c798: 400a ands r2, r1 + * function*/ + header->w = 1; + header->h = 1; + /* Symbols always have transparent parts. Important because of cover check in the design + * function. The actual value doesn't matter because lv_draw_label will draw it*/ + header->cf = LV_IMG_CF_ALPHA_1BIT; + c79a: 4313 orrs r3, r2 + c79c: 602b str r3, [r5, #0] + } + else { + LV_LOG_WARN("Image get info found unknown src type"); + return LV_RES_INV; + } + return LV_RES_OK; + c79e: 2401 movs r4, #1 +} + c7a0: 4620 mov r0, r4 + c7a2: b006 add sp, #24 + c7a4: bd70 pop {r4, r5, r6, pc} + else if(src_type == LV_IMG_SRC_FILE) { + c7a6: 2801 cmp r0, #1 + c7a8: d125 bne.n c7f6 + res = lv_fs_open(&file, src, LV_FS_MODE_RD); + c7aa: 4b1b ldr r3, [pc, #108] ; (c818 ) + c7ac: 2202 movs r2, #2 + c7ae: 4631 mov r1, r6 + c7b0: a804 add r0, sp, #16 + c7b2: 4798 blx r3 + if(res == LV_FS_RES_OK) { + c7b4: b9b8 cbnz r0, c7e6 + res = lv_fs_read(&file, header, sizeof(lv_img_header_t), &rn); + c7b6: 4e19 ldr r6, [pc, #100] ; (c81c ) + c7b8: ab03 add r3, sp, #12 + c7ba: 2204 movs r2, #4 + c7bc: 4629 mov r1, r5 + c7be: a804 add r0, sp, #16 + c7c0: 47b0 blx r6 + lv_fs_close(&file); + c7c2: 4b17 ldr r3, [pc, #92] ; (c820 ) + res = lv_fs_read(&file, header, sizeof(lv_img_header_t), &rn); + c7c4: 4606 mov r6, r0 + lv_fs_close(&file); + c7c6: a804 add r0, sp, #16 + c7c8: 4798 blx r3 + if(res != LV_FS_RES_OK || rn != sizeof(lv_img_header_t)) { + c7ca: b916 cbnz r6, c7d2 + c7cc: 9b03 ldr r3, [sp, #12] + c7ce: 2b04 cmp r3, #4 + c7d0: d009 beq.n c7e6 + LV_LOG_WARN("Image get info get read file header"); + c7d2: 4b14 ldr r3, [pc, #80] ; (c824 ) + c7d4: 9300 str r3, [sp, #0] + c7d6: 4b14 ldr r3, [pc, #80] ; (c828 ) + c7d8: f240 1221 movw r2, #289 ; 0x121 + LV_LOG_WARN("Image get info found unknown src type"); + c7dc: 4913 ldr r1, [pc, #76] ; (c82c ) + c7de: 4c14 ldr r4, [pc, #80] ; (c830 ) + c7e0: 2002 movs r0, #2 + c7e2: 47a0 blx r4 + c7e4: e005 b.n c7f2 + if(header->cf < CF_BUILT_IN_FIRST || header->cf > CF_BUILT_IN_LAST) return LV_RES_INV; + c7e6: 782b ldrb r3, [r5, #0] + c7e8: 331c adds r3, #28 + c7ea: f003 031f and.w r3, r3, #31 + c7ee: 2b0a cmp r3, #10 + c7f0: d9d6 bls.n c7a0 + return LV_RES_INV; + c7f2: 2400 movs r4, #0 + c7f4: e7d4 b.n c7a0 + else if(src_type == LV_IMG_SRC_SYMBOL) { + c7f6: 2802 cmp r0, #2 + c7f8: d104 bne.n c804 + header->cf = LV_IMG_CF_ALPHA_1BIT; + c7fa: 682b ldr r3, [r5, #0] + c7fc: f403 7278 and.w r2, r3, #992 ; 0x3e0 + c800: 4b0c ldr r3, [pc, #48] ; (c834 ) + c802: e7ca b.n c79a + LV_LOG_WARN("Image get info found unknown src type"); + c804: 4b0c ldr r3, [pc, #48] ; (c838 ) + c806: 9300 str r3, [sp, #0] + c808: f44f 729a mov.w r2, #308 ; 0x134 + c80c: 4b06 ldr r3, [pc, #24] ; (c828 ) + c80e: e7e5 b.n c7dc + c810: 00007805 .word 0x00007805 + c814: 001ffc1f .word 0x001ffc1f + c818: 0000e4a1 .word 0x0000e4a1 + c81c: 0000e419 .word 0x0000e419 + c820: 0000e3e9 .word 0x0000e3e9 + c824: 0001ff6e .word 0x0001ff6e + c828: 000200dc .word 0x000200dc + c82c: 0001ff37 .word 0x0001ff37 + c830: 0000e8e9 .word 0x0000e8e9 + c834: 0020040b .word 0x0020040b + c838: 0001ff92 .word 0x0001ff92 + +0000c83c : + * Close the pending decoding. Free resources etc. + * @param decoder pointer to the decoder the function associated with + * @param dsc pointer to decoder descriptor + */ +void lv_img_decoder_built_in_close(lv_img_decoder_t * decoder, lv_img_decoder_dsc_t * dsc) +{ + c83c: b570 push {r4, r5, r6, lr} + (void)decoder; /*Unused*/ + + lv_img_decoder_built_in_data_t * user_data = dsc->user_data; + c83e: 69cc ldr r4, [r1, #28] +{ + c840: 460d mov r5, r1 + if(user_data) { + c842: b184 cbz r4, c866 +#if LV_USE_FILESYSTEM + if(user_data->f) { + c844: 6820 ldr r0, [r4, #0] + c846: 4e08 ldr r6, [pc, #32] ; (c868 ) + c848: b118 cbz r0, c852 + lv_fs_close(user_data->f); + c84a: 4b08 ldr r3, [pc, #32] ; (c86c ) + c84c: 4798 blx r3 + lv_mem_free(user_data->f); + c84e: 6820 ldr r0, [r4, #0] + c850: 47b0 blx r6 + } +#endif + if(user_data->palette) lv_mem_free(user_data->palette); + c852: 6860 ldr r0, [r4, #4] + c854: b100 cbz r0, c858 + c856: 47b0 blx r6 + if(user_data->opa) lv_mem_free(user_data->opa); + c858: 68a0 ldr r0, [r4, #8] + c85a: b100 cbz r0, c85e + c85c: 47b0 blx r6 + + lv_mem_free(user_data); + c85e: 4620 mov r0, r4 + c860: 47b0 blx r6 + + dsc->user_data = NULL; + c862: 2300 movs r3, #0 + c864: 61eb str r3, [r5, #28] + } +} + c866: bd70 pop {r4, r5, r6, pc} + c868: 0000eae5 .word 0x0000eae5 + c86c: 0000e3e9 .word 0x0000e3e9 + +0000c870 : +{ + c870: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + if(dsc->header.cf == LV_IMG_CF_TRUE_COLOR || dsc->header.cf == LV_IMG_CF_TRUE_COLOR_ALPHA || + c874: 7b08 ldrb r0, [r1, #12] +{ + c876: b08d sub sp, #52 ; 0x34 + c878: 4698 mov r8, r3 + if(dsc->header.cf == LV_IMG_CF_TRUE_COLOR || dsc->header.cf == LV_IMG_CF_TRUE_COLOR_ALPHA || + c87a: f000 031e and.w r3, r0, #30 + c87e: 2b04 cmp r3, #4 +{ + c880: f9bd a058 ldrsh.w sl, [sp, #88] ; 0x58 + c884: 9e17 ldr r6, [sp, #92] ; 0x5c + c886: 460d mov r5, r1 + c888: 4614 mov r4, r2 + if(dsc->header.cf == LV_IMG_CF_TRUE_COLOR || dsc->header.cf == LV_IMG_CF_TRUE_COLOR_ALPHA || + c88a: d003 beq.n c894 + dsc->header.cf == LV_IMG_CF_TRUE_COLOR_CHROMA_KEYED) { + c88c: f000 031f and.w r3, r0, #31 + if(dsc->header.cf == LV_IMG_CF_TRUE_COLOR || dsc->header.cf == LV_IMG_CF_TRUE_COLOR_ALPHA || + c890: 2b06 cmp r3, #6 + c892: d13e bne.n c912 + if(dsc->src_type == LV_IMG_SRC_FILE) { + c894: f895 900a ldrb.w r9, [r5, #10] + c898: f1b9 0f01 cmp.w r9, #1 + c89c: d136 bne.n c90c + lv_coord_t len, uint8_t * buf) +{ +#if LV_USE_FILESYSTEM + lv_img_decoder_built_in_data_t * user_data = dsc->user_data; + lv_fs_res_t res; + uint8_t px_size = lv_img_cf_get_px_size(dsc->header.cf); + c89e: 4baf ldr r3, [pc, #700] ; (cb5c ) + lv_img_decoder_built_in_data_t * user_data = dsc->user_data; + c8a0: f8d5 b01c ldr.w fp, [r5, #28] + uint8_t px_size = lv_img_cf_get_px_size(dsc->header.cf); + c8a4: f000 001f and.w r0, r0, #31 + c8a8: 4798 blx r3 + + uint32_t pos = ((y * dsc->header.w + x) * px_size) >> 3; + c8aa: 68e9 ldr r1, [r5, #12] + pos += 4; /*Skip the header*/ + res = lv_fs_seek(user_data->f, pos); + c8ac: 4bac ldr r3, [pc, #688] ; (cb60 ) + uint32_t pos = ((y * dsc->header.w + x) * px_size) >> 3; + c8ae: f3c1 218a ubfx r1, r1, #10, #11 + c8b2: fb18 4101 smlabb r1, r8, r1, r4 + c8b6: 4341 muls r1, r0 + c8b8: 10c9 asrs r1, r1, #3 + uint8_t px_size = lv_img_cf_get_px_size(dsc->header.cf); + c8ba: 4607 mov r7, r0 + res = lv_fs_seek(user_data->f, pos); + c8bc: 3104 adds r1, #4 + c8be: f8db 0000 ldr.w r0, [fp] + c8c2: 4798 blx r3 + if(res != LV_FS_RES_OK) { + c8c4: b148 cbz r0, c8da + LV_LOG_WARN("Built-in image decoder seek failed"); + c8c6: 4ba7 ldr r3, [pc, #668] ; (cb64 ) + c8c8: 9300 str r3, [sp, #0] + c8ca: 4ba7 ldr r3, [pc, #668] ; (cb68 ) + c8cc: f240 222e movw r2, #558 ; 0x22e + LV_LOG_WARN("Built-in image decoder read not supports the color format"); + c8d0: 49a6 ldr r1, [pc, #664] ; (cb6c ) + c8d2: 4ca7 ldr r4, [pc, #668] ; (cb70 ) + c8d4: 2002 movs r0, #2 + c8d6: 47a0 blx r4 + return LV_RES_INV; + c8d8: e018 b.n c90c + return LV_RES_INV; + } + uint32_t btr = len * (px_size >> 3); + c8da: f3c7 07c7 ubfx r7, r7, #3, #8 + c8de: fb17 f70a smulbb r7, r7, sl + uint32_t br = 0; + c8e2: 9008 str r0, [sp, #32] + lv_fs_read(user_data->f, buf, btr, &br); + c8e4: ab08 add r3, sp, #32 + c8e6: f8db 0000 ldr.w r0, [fp] + c8ea: 4da2 ldr r5, [pc, #648] ; (cb74 ) + c8ec: 463a mov r2, r7 + c8ee: 4631 mov r1, r6 + c8f0: 47a8 blx r5 + if(res != LV_FS_RES_OK || btr != br) { + c8f2: 9b08 ldr r3, [sp, #32] + c8f4: 429f cmp r7, r3 + c8f6: f000 80db beq.w cab0 + LV_LOG_WARN("Built-in image decoder read failed"); + c8fa: 4b9f ldr r3, [pc, #636] ; (cb78 ) + c8fc: 9300 str r3, [sp, #0] + c8fe: 499b ldr r1, [pc, #620] ; (cb6c ) + c900: 4b99 ldr r3, [pc, #612] ; (cb68 ) + c902: 4d9b ldr r5, [pc, #620] ; (cb70 ) + c904: f240 2235 movw r2, #565 ; 0x235 + c908: 2002 movs r0, #2 + c90a: 47a8 blx r5 + lv_res_t res = LV_RES_INV; + c90c: f04f 0900 mov.w r9, #0 + c910: e0ce b.n cab0 + else if(dsc->header.cf == LV_IMG_CF_ALPHA_1BIT || dsc->header.cf == LV_IMG_CF_ALPHA_2BIT || + c912: f1a3 020b sub.w r2, r3, #11 + c916: 2a03 cmp r2, #3 + c918: f200 80ce bhi.w cab8 +static lv_res_t lv_img_decoder_built_in_line_alpha(lv_img_decoder_dsc_t * dsc, lv_coord_t x, lv_coord_t y, + lv_coord_t len, uint8_t * buf) +{ + +#if LV_IMG_CF_ALPHA + const lv_opa_t alpha1_opa_table[2] = {0, 255}; /*Opacity mapping with bpp = 1 (Just for compatibility)*/ + c91c: f44f 437f mov.w r3, #65280 ; 0xff00 + c920: f8ad 3018 strh.w r3, [sp, #24] + const lv_opa_t alpha2_opa_table[4] = {0, 85, 170, 255}; /*Opacity mapping with bpp = 2*/ + c924: f5a3 03ad sub.w r3, r3, #5668864 ; 0x568000 + c928: f5a3 5328 sub.w r3, r3, #10752 ; 0x2a00 + c92c: 9307 str r3, [sp, #28] + const lv_opa_t alpha4_opa_table[16] = {0, 17, 34, 51, /*Opacity mapping with bpp = 4*/ + c92e: 4b93 ldr r3, [pc, #588] ; (cb7c ) + c930: aa08 add r2, sp, #32 + c932: f103 0e10 add.w lr, r3, #16 + c936: 4617 mov r7, r2 + c938: 6818 ldr r0, [r3, #0] + c93a: 6859 ldr r1, [r3, #4] + c93c: 4694 mov ip, r2 + c93e: e8ac 0003 stmia.w ip!, {r0, r1} + c942: 3308 adds r3, #8 + c944: 4573 cmp r3, lr + c946: 4662 mov r2, ip + c948: d1f6 bne.n c938 + 68, 85, 102, 119, 136, 153, 170, 187, 204, 221, 238, 255 + }; + + /*Simply fill the buffer with the color. Later only the alpha value will be modified.*/ + lv_color_t bg_color = dsc->color; + c94a: 8929 ldrh r1, [r5, #8] + lv_coord_t i; + for(i = 0; i < len; i++) { + c94c: 4633 mov r3, r6 +#if LV_COLOR_DEPTH == 8 || LV_COLOR_DEPTH == 1 + buf[i * LV_IMG_PX_SIZE_ALPHA_BYTE] = bg_color.full; +#elif LV_COLOR_DEPTH == 16 + /*Because of Alpha byte 16 bit color can start on odd address which can cause crash*/ + buf[i * LV_IMG_PX_SIZE_ALPHA_BYTE] = bg_color.full & 0xFF; + buf[i * LV_IMG_PX_SIZE_ALPHA_BYTE + 1] = (bg_color.full >> 8) & 0xFF; + c94e: ea4f 2c11 mov.w ip, r1, lsr #8 + for(i = 0; i < len; i++) { + c952: 2200 movs r2, #0 + c954: b210 sxth r0, r2 + c956: 4582 cmp sl, r0 + c958: f103 0303 add.w r3, r3, #3 + c95c: dc14 bgt.n c988 +#error "Invalid LV_COLOR_DEPTH. Check it in lv_conf.h" +#endif + } + + const lv_opa_t * opa_table = NULL; + uint8_t px_size = lv_img_cf_get_px_size(dsc->header.cf); + c95e: 7b28 ldrb r0, [r5, #12] + c960: 4b7e ldr r3, [pc, #504] ; (cb5c ) + c962: f000 001f and.w r0, r0, #31 + c966: 4798 blx r3 + uint16_t mask = (1 << px_size) - 1; /*E.g. px_size = 2; mask = 0x03*/ + c968: 2301 movs r3, #1 + c96a: 4083 lsls r3, r0 + c96c: 3b01 subs r3, #1 + c96e: b29b uxth r3, r3 + c970: 9304 str r3, [sp, #16] + + lv_coord_t w = 0; + uint32_t ofs = 0; + int8_t pos = 0; + switch(dsc->header.cf) { + c972: 7b2b ldrb r3, [r5, #12] + c974: f003 031f and.w r3, r3, #31 + c978: 3b0b subs r3, #11 + uint8_t px_size = lv_img_cf_get_px_size(dsc->header.cf); + c97a: 4681 mov r9, r0 + switch(dsc->header.cf) { + c97c: 2b03 cmp r3, #3 + c97e: d85f bhi.n ca40 + c980: e8df f003 tbb [pc, r3] + c984: 55422e08 .word 0x55422e08 + buf[i * LV_IMG_PX_SIZE_ALPHA_BYTE] = bg_color.full & 0xFF; + c988: f803 1c03 strb.w r1, [r3, #-3] + buf[i * LV_IMG_PX_SIZE_ALPHA_BYTE + 1] = (bg_color.full >> 8) & 0xFF; + c98c: f803 cc02 strb.w ip, [r3, #-2] + for(i = 0; i < len; i++) { + c990: 3201 adds r2, #1 + c992: e7df b.n c954 + case LV_IMG_CF_ALPHA_1BIT: + w = (dsc->header.w >> 3); /*E.g. w = 20 -> w = 2 + 1*/ + c994: 68eb ldr r3, [r5, #12] + c996: f3c3 3247 ubfx r2, r3, #13, #8 + if(dsc->header.w & 0x7) w++; + c99a: f413 5fe0 tst.w r3, #7168 ; 0x1c00 + ofs += w * y + (x >> 3); /*First pixel*/ + c99e: ea4f 01e4 mov.w r1, r4, asr #3 + w = (dsc->header.w >> 3); /*E.g. w = 20 -> w = 2 + 1*/ + c9a2: bf0c ite eq + c9a4: fa0f fb82 sxtheq.w fp, r2 + if(dsc->header.w & 0x7) w++; + c9a8: f102 0b01 addne.w fp, r2, #1 + pos = 7 - (x & 0x7); + c9ac: 43e4 mvns r4, r4 + ofs += w * y + (x >> 3); /*First pixel*/ + c9ae: fb0b 1108 mla r1, fp, r8, r1 + pos = 7 - (x & 0x7); + c9b2: f004 0407 and.w r4, r4, #7 + opa_table = alpha1_opa_table; + c9b6: af06 add r7, sp, #24 + pos = 0; + break; + } + +#if LV_USE_FILESYSTEM + lv_img_decoder_built_in_data_t * user_data = dsc->user_data; + c9b8: 69eb ldr r3, [r5, #28] + c9ba: 9303 str r3, [sp, #12] + uint8_t * fs_buf = _lv_mem_buf_get(w); + c9bc: 4658 mov r0, fp + c9be: 4b70 ldr r3, [pc, #448] ; (cb80 ) + c9c0: 9105 str r1, [sp, #20] + c9c2: 4798 blx r3 +#endif + + const uint8_t * data_tmp = NULL; + if(dsc->src_type == LV_IMG_SRC_VARIABLE) { + c9c4: 7aab ldrb r3, [r5, #10] + c9c6: 9905 ldr r1, [sp, #20] + uint8_t * fs_buf = _lv_mem_buf_get(w); + c9c8: 4680 mov r8, r0 + if(dsc->src_type == LV_IMG_SRC_VARIABLE) { + c9ca: 2b00 cmp r3, #0 + c9cc: d13c bne.n ca48 + const lv_img_dsc_t * img_dsc = dsc->src; + + data_tmp = img_dsc->data + ofs; + c9ce: 686b ldr r3, [r5, #4] + c9d0: 689a ldr r2, [r3, #8] + c9d2: 440a add r2, r1 + buf[i * LV_IMG_PX_SIZE_ALPHA_BYTE + LV_IMG_PX_SIZE_ALPHA_BYTE - 1] = + dsc->header.cf == LV_IMG_CF_ALPHA_8BIT ? val_act : opa_table[val_act]; + + pos -= px_size; + if(pos < 0) { + pos = 8 - px_size; + c9d4: f1c9 0008 rsb r0, r9, #8 + data_tmp = fs_buf; + c9d8: 2100 movs r1, #0 + buf[i * LV_IMG_PX_SIZE_ALPHA_BYTE + LV_IMG_PX_SIZE_ALPHA_BYTE - 1] = + c9da: 3602 adds r6, #2 + pos = 8 - px_size; + c9dc: b240 sxtb r0, r0 + c9de: e05f b.n caa0 + w = (dsc->header.w >> 2); /*E.g. w = 13 -> w = 3 + 1 (bytes)*/ + c9e0: 68eb ldr r3, [r5, #12] + ofs += w * y + (x >> 2); /*First pixel*/ + c9e2: 10a1 asrs r1, r4, #2 + w = (dsc->header.w >> 2); /*E.g. w = 13 -> w = 3 + 1 (bytes)*/ + c9e4: f3c3 3208 ubfx r2, r3, #12, #9 + if(dsc->header.w & 0x3) w++; + c9e8: f413 6f40 tst.w r3, #3072 ; 0xc00 + pos = 6 - ((x & 0x3) * 2); + c9ec: ea6f 0404 mvn.w r4, r4 + w = (dsc->header.w >> 2); /*E.g. w = 13 -> w = 3 + 1 (bytes)*/ + c9f0: bf0c ite eq + c9f2: fa0f fb82 sxtheq.w fp, r2 + if(dsc->header.w & 0x3) w++; + c9f6: f102 0b01 addne.w fp, r2, #1 + pos = 6 - ((x & 0x3) * 2); + c9fa: f004 0403 and.w r4, r4, #3 + ofs += w * y + (x >> 2); /*First pixel*/ + c9fe: fb0b 1108 mla r1, fp, r8, r1 + pos = 6 - ((x & 0x3) * 2); + ca02: 0064 lsls r4, r4, #1 + opa_table = alpha2_opa_table; + ca04: af07 add r7, sp, #28 + break; + ca06: e7d7 b.n c9b8 + w = (dsc->header.w >> 1); /*E.g. w = 13 -> w = 6 + 1 (bytes)*/ + ca08: 68eb ldr r3, [r5, #12] + if(dsc->header.w & 0x1) w++; + ca0a: 0559 lsls r1, r3, #21 + w = (dsc->header.w >> 1); /*E.g. w = 13 -> w = 6 + 1 (bytes)*/ + ca0c: f3c3 22c9 ubfx r2, r3, #11, #10 + ofs += w * y + (x >> 1); /*First pixel*/ + ca10: ea4f 0164 mov.w r1, r4, asr #1 + pos = 4 - ((x & 0x1) * 4); + ca14: ea6f 0404 mvn.w r4, r4 + w = (dsc->header.w >> 1); /*E.g. w = 13 -> w = 6 + 1 (bytes)*/ + ca18: bf54 ite pl + ca1a: fa0f fb82 sxthpl.w fp, r2 + if(dsc->header.w & 0x1) w++; + ca1e: f102 0b01 addmi.w fp, r2, #1 + pos = 4 - ((x & 0x1) * 4); + ca22: f004 0401 and.w r4, r4, #1 + ofs += w * y + (x >> 1); /*First pixel*/ + ca26: fb0b 1108 mla r1, fp, r8, r1 + pos = 4 - ((x & 0x1) * 4); + ca2a: 00a4 lsls r4, r4, #2 + ca2c: e7c4 b.n c9b8 + w = dsc->header.w; /*E.g. x = 7 -> w = 7 (bytes)*/ + ca2e: 68ea ldr r2, [r5, #12] + ca30: f3c2 218a ubfx r1, r2, #10, #11 + ca34: 468b mov fp, r1 + ofs += w * y + x; /*First pixel*/ + ca36: fb18 4101 smlabb r1, r8, r1, r4 + pos = 0; + ca3a: 2400 movs r4, #0 + switch(dsc->header.cf) { + ca3c: 4627 mov r7, r4 + ca3e: e7bb b.n c9b8 + ca40: 2400 movs r4, #0 + ca42: 4621 mov r1, r4 + ca44: 46a3 mov fp, r4 + ca46: e7f9 b.n ca3c + lv_fs_seek(user_data->f, ofs + 4); /*+4 to skip the header*/ + ca48: 9b03 ldr r3, [sp, #12] + ca4a: 3104 adds r1, #4 + ca4c: 6818 ldr r0, [r3, #0] + ca4e: 4b44 ldr r3, [pc, #272] ; (cb60 ) + ca50: 4798 blx r3 + lv_fs_read(user_data->f, fs_buf, w, NULL); + ca52: 9803 ldr r0, [sp, #12] + ca54: 465a mov r2, fp + ca56: 6800 ldr r0, [r0, #0] + ca58: f8df b118 ldr.w fp, [pc, #280] ; cb74 + ca5c: 2300 movs r3, #0 + ca5e: 4641 mov r1, r8 + ca60: 47d8 blx fp + data_tmp = fs_buf; + ca62: 4642 mov r2, r8 + ca64: e7b6 b.n c9d4 + uint8_t val_act = (*data_tmp & (mask << pos)) >> pos; + ca66: 9b04 ldr r3, [sp, #16] + ca68: f892 e000 ldrb.w lr, [r2] + ca6c: fa03 fc04 lsl.w ip, r3, r4 + ca70: ea0e 030c and.w r3, lr, ip + dsc->header.cf == LV_IMG_CF_ALPHA_8BIT ? val_act : opa_table[val_act]; + ca74: f895 c00c ldrb.w ip, [r5, #12] + uint8_t val_act = (*data_tmp & (mask << pos)) >> pos; + ca78: 4123 asrs r3, r4 + buf[i * LV_IMG_PX_SIZE_ALPHA_BYTE + LV_IMG_PX_SIZE_ALPHA_BYTE - 1] = + ca7a: f00c 0c1f and.w ip, ip, #31 + ca7e: f1bc 0f0e cmp.w ip, #14 + pos -= px_size; + ca82: eba4 0409 sub.w r4, r4, r9 + buf[i * LV_IMG_PX_SIZE_ALPHA_BYTE + LV_IMG_PX_SIZE_ALPHA_BYTE - 1] = + ca86: eb01 0c41 add.w ip, r1, r1, lsl #1 + ca8a: bf14 ite ne + ca8c: 5cfb ldrbne r3, [r7, r3] + uint8_t val_act = (*data_tmp & (mask << pos)) >> pos; + ca8e: b2db uxtbeq r3, r3 + pos -= px_size; + ca90: b264 sxtb r4, r4 + if(pos < 0) { + ca92: 2c00 cmp r4, #0 + buf[i * LV_IMG_PX_SIZE_ALPHA_BYTE + LV_IMG_PX_SIZE_ALPHA_BYTE - 1] = + ca94: f806 300c strb.w r3, [r6, ip] + pos = 8 - px_size; + ca98: bfbc itt lt + ca9a: 4604 movlt r4, r0 + data_tmp++; + ca9c: 3201 addlt r2, #1 + for(i = 0; i < len; i++) { + ca9e: 3101 adds r1, #1 + caa0: b20b sxth r3, r1 + caa2: 459a cmp sl, r3 + caa4: dcdf bgt.n ca66 + pos = 8 - px_size; + data_tmp++; + } + } +#if LV_USE_FILESYSTEM + _lv_mem_buf_release(fs_buf); + caa6: 4b37 ldr r3, [pc, #220] ; (cb84 ) + caa8: 4640 mov r0, r8 + caaa: 4798 blx r3 + res = lv_img_decoder_built_in_line_indexed(dsc, x, y, len, buf); + caac: f04f 0901 mov.w r9, #1 +} + cab0: 4648 mov r0, r9 + cab2: b00d add sp, #52 ; 0x34 + cab4: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + else if(dsc->header.cf == LV_IMG_CF_INDEXED_1BIT || dsc->header.cf == LV_IMG_CF_INDEXED_2BIT || + cab8: 3b07 subs r3, #7 + caba: 2b03 cmp r3, #3 + cabc: f200 80b0 bhi.w cc20 + uint8_t px_size = lv_img_cf_get_px_size(dsc->header.cf); + cac0: 4b26 ldr r3, [pc, #152] ; (cb5c ) + cac2: f000 001f and.w r0, r0, #31 + cac6: 4798 blx r3 + uint16_t mask = (1 << px_size) - 1; /*E.g. px_size = 2; mask = 0x03*/ + cac8: 2701 movs r7, #1 + caca: 4087 lsls r7, r0 + cacc: 3f01 subs r7, #1 + cace: b2bb uxth r3, r7 + cad0: 9303 str r3, [sp, #12] + switch(dsc->header.cf) { + cad2: 7b2b ldrb r3, [r5, #12] + cad4: f003 031f and.w r3, r3, #31 + cad8: 3b07 subs r3, #7 + uint8_t px_size = lv_img_cf_get_px_size(dsc->header.cf); + cada: 4681 mov r9, r0 + switch(dsc->header.cf) { + cadc: 2b03 cmp r3, #3 + cade: d870 bhi.n cbc2 + cae0: e8df f003 tbb [pc, r3] + cae4: 65522702 .word 0x65522702 + w = (dsc->header.w >> 3); /*E.g. w = 20 -> w = 2 + 1*/ + cae8: 68eb ldr r3, [r5, #12] + caea: f3c3 3247 ubfx r2, r3, #13, #8 + if(dsc->header.w & 0x7) w++; + caee: f413 5fe0 tst.w r3, #7168 ; 0x1c00 + w = (dsc->header.w >> 3); /*E.g. w = 20 -> w = 2 + 1*/ + caf2: bf08 it eq + caf4: b217 sxtheq r7, r2 + ofs += w * y + (x >> 3); /*First pixel*/ + caf6: ea4f 03e4 mov.w r3, r4, asr #3 + if(dsc->header.w & 0x7) w++; + cafa: bf18 it ne + cafc: 1c57 addne r7, r2, #1 + ofs += w * y + (x >> 3); /*First pixel*/ + cafe: fb07 3308 mla r3, r7, r8, r3 + pos = 7 - (x & 0x7); + cb02: 43e4 mvns r4, r4 + ofs += 8; /*Skip the palette*/ + cb04: f103 0108 add.w r1, r3, #8 + pos = 7 - (x & 0x7); + cb08: f004 0407 and.w r4, r4, #7 + uint8_t * fs_buf = _lv_mem_buf_get(w); + cb0c: 4b1c ldr r3, [pc, #112] ; (cb80 ) + cb0e: 9104 str r1, [sp, #16] + cb10: 4638 mov r0, r7 + lv_img_decoder_built_in_data_t * user_data = dsc->user_data; + cb12: f8d5 b01c ldr.w fp, [r5, #28] + uint8_t * fs_buf = _lv_mem_buf_get(w); + cb16: 4798 blx r3 + if(dsc->src_type == LV_IMG_SRC_VARIABLE) { + cb18: 7aab ldrb r3, [r5, #10] + cb1a: 9904 ldr r1, [sp, #16] + uint8_t * fs_buf = _lv_mem_buf_get(w); + cb1c: 4680 mov r8, r0 + if(dsc->src_type == LV_IMG_SRC_VARIABLE) { + cb1e: 2b00 cmp r3, #0 + cb20: d153 bne.n cbca + data_tmp = img_dsc->data + ofs; + cb22: 686b ldr r3, [r5, #4] + cb24: 689b ldr r3, [r3, #8] + cb26: 440b add r3, r1 + pos = 8 - px_size; + cb28: f1c9 0508 rsb r5, r9, #8 + data_tmp = fs_buf; + cb2c: 2000 movs r0, #0 + pos = 8 - px_size; + cb2e: b26d sxtb r5, r5 + cb30: e072 b.n cc18 + w = (dsc->header.w >> 2); /*E.g. w = 13 -> w = 3 + 1 (bytes)*/ + cb32: 68eb ldr r3, [r5, #12] + cb34: f3c3 3208 ubfx r2, r3, #12, #9 + if(dsc->header.w & 0x3) w++; + cb38: f413 6f40 tst.w r3, #3072 ; 0xc00 + w = (dsc->header.w >> 2); /*E.g. w = 13 -> w = 3 + 1 (bytes)*/ + cb3c: bf08 it eq + cb3e: b217 sxtheq r7, r2 + ofs += w * y + (x >> 2); /*First pixel*/ + cb40: ea4f 03a4 mov.w r3, r4, asr #2 + if(dsc->header.w & 0x3) w++; + cb44: bf18 it ne + cb46: 1c57 addne r7, r2, #1 + pos = 6 - ((x & 0x3) * 2); + cb48: 43e4 mvns r4, r4 + ofs += w * y + (x >> 2); /*First pixel*/ + cb4a: fb07 3308 mla r3, r7, r8, r3 + pos = 6 - ((x & 0x3) * 2); + cb4e: f004 0403 and.w r4, r4, #3 + ofs += 16; /*Skip the palette*/ + cb52: f103 0110 add.w r1, r3, #16 + pos = 6 - ((x & 0x3) * 2); + cb56: 0064 lsls r4, r4, #1 + break; + cb58: e7d8 b.n cb0c + cb5a: bf00 nop + cb5c: 00007581 .word 0x00007581 + cb60: 0000e44f .word 0x0000e44f + cb64: 0001ffb8 .word 0x0001ffb8 + cb68: 000200f9 .word 0x000200f9 + cb6c: 0001ff37 .word 0x0001ff37 + cb70: 0000e8e9 .word 0x0000e8e9 + cb74: 0000e419 .word 0x0000e419 + cb78: 0001ffdb .word 0x0001ffdb + cb7c: 00020121 .word 0x00020121 + cb80: 0000eeb5 .word 0x0000eeb5 + cb84: 0000eb69 .word 0x0000eb69 + w = (dsc->header.w >> 1); /*E.g. w = 13 -> w = 6 + 1 (bytes)*/ + cb88: 68eb ldr r3, [r5, #12] + cb8a: f3c3 22c9 ubfx r2, r3, #11, #10 + if(dsc->header.w & 0x1) w++; + cb8e: 055b lsls r3, r3, #21 + w = (dsc->header.w >> 1); /*E.g. w = 13 -> w = 6 + 1 (bytes)*/ + cb90: bf58 it pl + cb92: b217 sxthpl r7, r2 + ofs += w * y + (x >> 1); /*First pixel*/ + cb94: ea4f 0364 mov.w r3, r4, asr #1 + if(dsc->header.w & 0x1) w++; + cb98: bf48 it mi + cb9a: 1c57 addmi r7, r2, #1 + pos = 4 - ((x & 0x1) * 4); + cb9c: 43e4 mvns r4, r4 + ofs += w * y + (x >> 1); /*First pixel*/ + cb9e: fb07 3308 mla r3, r7, r8, r3 + pos = 4 - ((x & 0x1) * 4); + cba2: f004 0401 and.w r4, r4, #1 + ofs += 64; /*Skip the palette*/ + cba6: f103 0140 add.w r1, r3, #64 ; 0x40 + pos = 4 - ((x & 0x1) * 4); + cbaa: 00a4 lsls r4, r4, #2 + cbac: e7ae b.n cb0c + w = dsc->header.w; /*E.g. x = 7 -> w = 7 (bytes)*/ + cbae: 68ef ldr r7, [r5, #12] + cbb0: f3c7 238a ubfx r3, r7, #10, #11 + ofs += w * y + x; /*First pixel*/ + cbb4: fb18 4803 smlabb r8, r8, r3, r4 + w = dsc->header.w; /*E.g. x = 7 -> w = 7 (bytes)*/ + cbb8: 461f mov r7, r3 + ofs += 1024; /*Skip the palette*/ + cbba: f508 6180 add.w r1, r8, #1024 ; 0x400 + pos = 0; + cbbe: 2400 movs r4, #0 + break; + cbc0: e7a4 b.n cb0c + switch(dsc->header.cf) { + cbc2: 2100 movs r1, #0 + cbc4: 460c mov r4, r1 + cbc6: 460f mov r7, r1 + cbc8: e7a0 b.n cb0c + lv_fs_seek(user_data->f, ofs + 4); /*+4 to skip the header*/ + cbca: 4b18 ldr r3, [pc, #96] ; (cc2c ) + cbcc: f8db 0000 ldr.w r0, [fp] + lv_fs_read(user_data->f, fs_buf, w, NULL); + cbd0: 4d17 ldr r5, [pc, #92] ; (cc30 ) + lv_fs_seek(user_data->f, ofs + 4); /*+4 to skip the header*/ + cbd2: 3104 adds r1, #4 + cbd4: 4798 blx r3 + lv_fs_read(user_data->f, fs_buf, w, NULL); + cbd6: 2300 movs r3, #0 + cbd8: f8db 0000 ldr.w r0, [fp] + cbdc: 463a mov r2, r7 + cbde: 4641 mov r1, r8 + cbe0: 47a8 blx r5 + data_tmp = fs_buf; + cbe2: 4643 mov r3, r8 + cbe4: e7a0 b.n cb28 + uint8_t val_act = (*data_tmp & (mask << pos)) >> pos; + cbe6: 9903 ldr r1, [sp, #12] + cbe8: 781a ldrb r2, [r3, #0] + cbea: 40a1 lsls r1, r4 + cbec: 400a ands r2, r1 + cbee: 4122 asrs r2, r4 + lv_color_t color = user_data->palette[val_act]; + cbf0: f8db 1004 ldr.w r1, [fp, #4] + cbf4: f831 1012 ldrh.w r1, [r1, r2, lsl #1] + buf[i * LV_IMG_PX_SIZE_ALPHA_BYTE] = color.full & 0xFF; + cbf8: 7031 strb r1, [r6, #0] + buf[i * LV_IMG_PX_SIZE_ALPHA_BYTE + 1] = (color.full >> 8) & 0xFF; + cbfa: 0a09 lsrs r1, r1, #8 + cbfc: 7071 strb r1, [r6, #1] + buf[i * LV_IMG_PX_SIZE_ALPHA_BYTE + LV_IMG_PX_SIZE_ALPHA_BYTE - 1] = user_data->opa[val_act]; + cbfe: f8db 1008 ldr.w r1, [fp, #8] + pos -= px_size; + cc02: eba4 0409 sub.w r4, r4, r9 + cc06: b264 sxtb r4, r4 + if(pos < 0) { + cc08: 2c00 cmp r4, #0 + buf[i * LV_IMG_PX_SIZE_ALPHA_BYTE + LV_IMG_PX_SIZE_ALPHA_BYTE - 1] = user_data->opa[val_act]; + cc0a: 5c8a ldrb r2, [r1, r2] + cc0c: 70b2 strb r2, [r6, #2] + pos = 8 - px_size; + cc0e: bfbc itt lt + cc10: 462c movlt r4, r5 + data_tmp++; + cc12: 3301 addlt r3, #1 + for(i = 0; i < len; i++) { + cc14: 3001 adds r0, #1 + cc16: 3603 adds r6, #3 + cc18: b202 sxth r2, r0 + cc1a: 4592 cmp sl, r2 + cc1c: dce3 bgt.n cbe6 + cc1e: e742 b.n caa6 + LV_LOG_WARN("Built-in image decoder read not supports the color format"); + cc20: 4b04 ldr r3, [pc, #16] ; (cc34 ) + cc22: 9300 str r3, [sp, #0] + cc24: f44f 72fe mov.w r2, #508 ; 0x1fc + cc28: 4b03 ldr r3, [pc, #12] ; (cc38 ) + cc2a: e651 b.n c8d0 + cc2c: 0000e44f .word 0x0000e44f + cc30: 0000e419 .word 0x0000e419 + cc34: 0001fffe .word 0x0001fffe + cc38: 00020131 .word 0x00020131 + +0000cc3c : +{ + cc3c: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} + cc40: 4606 mov r6, r0 + if(dsc->src_type == LV_IMG_SRC_FILE) { + cc42: 7a88 ldrb r0, [r1, #10] + cc44: 2801 cmp r0, #1 +{ + cc46: 460c mov r4, r1 + if(dsc->src_type == LV_IMG_SRC_FILE) { + cc48: d178 bne.n cd3c + if(strcmp(lv_fs_get_ext(dsc->src), "bin")) return LV_RES_INV; + cc4a: 6848 ldr r0, [r1, #4] + cc4c: 4b8b ldr r3, [pc, #556] ; (ce7c ) + cc4e: 4798 blx r3 + cc50: 498b ldr r1, [pc, #556] ; (ce80 ) + cc52: 4b8c ldr r3, [pc, #560] ; (ce84 ) + cc54: 4798 blx r3 + cc56: 2800 cmp r0, #0 + cc58: f040 80a9 bne.w cdae + lv_fs_res_t res = lv_fs_open(&f, dsc->src, LV_FS_MODE_RD); + cc5c: 6861 ldr r1, [r4, #4] + cc5e: 4b8a ldr r3, [pc, #552] ; (ce88 ) + cc60: 2202 movs r2, #2 + cc62: a802 add r0, sp, #8 + cc64: 4798 blx r3 + if(res != LV_FS_RES_OK) { + cc66: b138 cbz r0, cc78 + LV_LOG_WARN("Built-in image decoder can't open the file"); + cc68: 4b88 ldr r3, [pc, #544] ; (ce8c ) + cc6a: 9300 str r3, [sp, #0] + cc6c: 4b88 ldr r3, [pc, #544] ; (ce90 ) + cc6e: f44f 72a6 mov.w r2, #332 ; 0x14c + LV_LOG_WARN("Image decoder open: unknown color format") + cc72: 4988 ldr r1, [pc, #544] ; (ce94 ) + cc74: 2002 movs r0, #2 + cc76: e022 b.n ccbe + if(dsc->user_data == NULL) { + cc78: 69e3 ldr r3, [r4, #28] + cc7a: f8df 923c ldr.w r9, [pc, #572] ; ceb8 + cc7e: f8df 823c ldr.w r8, [pc, #572] ; cebc + cc82: bb13 cbnz r3, ccca + dsc->user_data = lv_mem_alloc(sizeof(lv_img_decoder_built_in_data_t)); + cc84: 200c movs r0, #12 + cc86: 47c8 blx r9 + cc88: 61e0 str r0, [r4, #28] + LV_ASSERT_MEM(dsc->user_data); + cc8a: 47c0 blx r8 + cc8c: 4605 mov r5, r0 + cc8e: b968 cbnz r0, ccac + cc90: 4b7f ldr r3, [pc, #508] ; (ce90 ) + cc92: 4980 ldr r1, [pc, #512] ; (ce94 ) + cc94: 9300 str r3, [sp, #0] + cc96: f240 1253 movw r2, #339 ; 0x153 + cc9a: 2003 movs r0, #3 + cc9c: 4e7e ldr r6, [pc, #504] ; (ce98 ) + cc9e: 47b0 blx r6 + cca0: 69e2 ldr r2, [r4, #28] + cca2: 487e ldr r0, [pc, #504] ; (ce9c ) + cca4: 497e ldr r1, [pc, #504] ; (cea0 ) + cca6: 462b mov r3, r5 + cca8: 4788 blx r1 + ccaa: e7fe b.n ccaa + if(dsc->user_data == NULL) { + ccac: 69e0 ldr r0, [r4, #28] + ccae: b948 cbnz r0, ccc4 + LV_LOG_ERROR("img_decoder_built_in_open: out of memory"); + ccb0: 4b7c ldr r3, [pc, #496] ; (cea4 ) + ccb2: 9300 str r3, [sp, #0] + ccb4: 4977 ldr r1, [pc, #476] ; (ce94 ) + ccb6: 4b76 ldr r3, [pc, #472] ; (ce90 ) + ccb8: f240 1255 movw r2, #341 ; 0x155 + ccbc: 2003 movs r0, #3 + LV_LOG_WARN("Image decoder open: unknown color format") + ccbe: 4c76 ldr r4, [pc, #472] ; (ce98 ) + ccc0: 47a0 blx r4 + ccc2: e074 b.n cdae + _lv_memset_00(dsc->user_data, sizeof(lv_img_decoder_built_in_data_t)); + ccc4: 4b78 ldr r3, [pc, #480] ; (cea8 ) + ccc6: 210c movs r1, #12 + ccc8: 4798 blx r3 + user_data->f = lv_mem_alloc(sizeof(f)); + ccca: 2008 movs r0, #8 + lv_img_decoder_built_in_data_t * user_data = dsc->user_data; + cccc: 69e7 ldr r7, [r4, #28] + user_data->f = lv_mem_alloc(sizeof(f)); + ccce: 47c8 blx r9 + ccd0: 6038 str r0, [r7, #0] + LV_ASSERT_MEM(user_data->f); + ccd2: 47c0 blx r8 + ccd4: 4605 mov r5, r0 + ccd6: b968 cbnz r0, ccf4 + ccd8: 4b6d ldr r3, [pc, #436] ; (ce90 ) + ccda: 496e ldr r1, [pc, #440] ; (ce94 ) + ccdc: 9300 str r3, [sp, #0] + ccde: f240 125d movw r2, #349 ; 0x15d + cce2: 2003 movs r0, #3 + cce4: 4c6c ldr r4, [pc, #432] ; (ce98 ) + cce6: 47a0 blx r4 + cce8: 683a ldr r2, [r7, #0] + ccea: 486c ldr r0, [pc, #432] ; (ce9c ) + ccec: 496c ldr r1, [pc, #432] ; (cea0 ) + ccee: 462b mov r3, r5 + ccf0: 4788 blx r1 + ccf2: e7fe b.n ccf2 + if(user_data->f == NULL) { + ccf4: 683b ldr r3, [r7, #0] + ccf6: b94b cbnz r3, cd0c + LV_LOG_ERROR("img_decoder_built_in_open: out of memory"); + ccf8: 4b6a ldr r3, [pc, #424] ; (cea4 ) + ccfa: 9300 str r3, [sp, #0] + ccfc: 4b64 ldr r3, [pc, #400] ; (ce90 ) + ccfe: f240 125f movw r2, #351 ; 0x15f + LV_LOG_ERROR("img_decoder_built_in_open: out of memory"); + cd02: 4964 ldr r1, [pc, #400] ; (ce94 ) + cd04: 4d64 ldr r5, [pc, #400] ; (ce98 ) + cd06: 2003 movs r0, #3 + cd08: 47a8 blx r5 + cd0a: e04c b.n cda6 + cd0c: aa02 add r2, sp, #8 + cd0e: f103 0108 add.w r1, r3, #8 + *d8 = *s8; + cd12: f812 0b01 ldrb.w r0, [r2], #1 + cd16: f803 0b01 strb.w r0, [r3], #1 + while(len) { + cd1a: 428b cmp r3, r1 + cd1c: d1f9 bne.n cd12 + lv_img_cf_t cf = dsc->header.cf; + cd1e: 7b23 ldrb r3, [r4, #12] + cd20: f003 001f and.w r0, r3, #31 + if(cf == LV_IMG_CF_TRUE_COLOR || cf == LV_IMG_CF_TRUE_COLOR_ALPHA || cf == LV_IMG_CF_TRUE_COLOR_CHROMA_KEYED) { + cd24: 1f02 subs r2, r0, #4 + cd26: 2a02 cmp r2, #2 + cd28: d811 bhi.n cd4e + if(dsc->src_type == LV_IMG_SRC_VARIABLE) { + cd2a: 7aa3 ldrb r3, [r4, #10] + cd2c: 2b00 cmp r3, #0 + cd2e: f040 8088 bne.w ce42 + dsc->img_data = ((lv_img_dsc_t *)dsc->src)->data; + cd32: 6863 ldr r3, [r4, #4] + cd34: 689b ldr r3, [r3, #8] + dsc->img_data = NULL; + cd36: 6123 str r3, [r4, #16] + return LV_RES_OK; + cd38: 2001 movs r0, #1 + cd3a: e005 b.n cd48 + else if(dsc->src_type == LV_IMG_SRC_VARIABLE) { + cd3c: 2800 cmp r0, #0 + cd3e: d1ee bne.n cd1e + if(((lv_img_dsc_t *)dsc->src)->data == NULL) { + cd40: 684a ldr r2, [r1, #4] + cd42: 6892 ldr r2, [r2, #8] + cd44: 2a00 cmp r2, #0 + cd46: d1ea bne.n cd1e +} + cd48: b004 add sp, #16 + cd4a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + else if(cf == LV_IMG_CF_INDEXED_1BIT || cf == LV_IMG_CF_INDEXED_2BIT || cf == LV_IMG_CF_INDEXED_4BIT || + cd4e: 1fc2 subs r2, r0, #7 + cd50: 2a03 cmp r2, #3 + cd52: f200 80d4 bhi.w cefe + uint8_t px_size = lv_img_cf_get_px_size(cf); + cd56: 4b55 ldr r3, [pc, #340] ; (ceac ) + cd58: f8df a15c ldr.w sl, [pc, #348] ; ceb8 + cd5c: f8df 915c ldr.w r9, [pc, #348] ; cebc + cd60: 4798 blx r3 + if(dsc->user_data == NULL) { + cd62: 69e3 ldr r3, [r4, #28] + uint8_t px_size = lv_img_cf_get_px_size(cf); + cd64: 4680 mov r8, r0 + if(dsc->user_data == NULL) { + cd66: bb43 cbnz r3, cdba + dsc->user_data = lv_mem_alloc(sizeof(lv_img_decoder_built_in_data_t)); + cd68: 200c movs r0, #12 + cd6a: 47d0 blx sl + cd6c: 61e0 str r0, [r4, #28] + LV_ASSERT_MEM(dsc->user_data); + cd6e: 47c8 blx r9 + cd70: 4605 mov r5, r0 + cd72: b968 cbnz r0, cd90 + cd74: 4b46 ldr r3, [pc, #280] ; (ce90 ) + cd76: 4947 ldr r1, [pc, #284] ; (ce94 ) + cd78: 9300 str r3, [sp, #0] + cd7a: f44f 72c6 mov.w r2, #396 ; 0x18c + cd7e: 2003 movs r0, #3 + cd80: 4e45 ldr r6, [pc, #276] ; (ce98 ) + cd82: 47b0 blx r6 + cd84: 69e2 ldr r2, [r4, #28] + cd86: 4845 ldr r0, [pc, #276] ; (ce9c ) + cd88: 4945 ldr r1, [pc, #276] ; (cea0 ) + cd8a: 462b mov r3, r5 + cd8c: 4788 blx r1 + cd8e: e7fe b.n cd8e + if(dsc->user_data == NULL) { + cd90: 69e5 ldr r5, [r4, #28] + cd92: b975 cbnz r5, cdb2 + LV_LOG_ERROR("img_decoder_built_in_open: out of memory"); + cd94: 4b43 ldr r3, [pc, #268] ; (cea4 ) + cd96: 9300 str r3, [sp, #0] + cd98: 493e ldr r1, [pc, #248] ; (ce94 ) + cd9a: 4b3d ldr r3, [pc, #244] ; (ce90 ) + cd9c: 4f3e ldr r7, [pc, #248] ; (ce98 ) + cd9e: f44f 72c7 mov.w r2, #398 ; 0x18e + cda2: 2003 movs r0, #3 + cda4: 47b8 blx r7 + lv_img_decoder_built_in_close(decoder, dsc); + cda6: 4b42 ldr r3, [pc, #264] ; (ceb0 ) + cda8: 4621 mov r1, r4 + cdaa: 4630 mov r0, r6 + cdac: 4798 blx r3 + return LV_RES_INV; + cdae: 2000 movs r0, #0 + cdb0: e7ca b.n cd48 + _lv_memset_00(dsc->user_data, sizeof(lv_img_decoder_built_in_data_t)); + cdb2: 4b3d ldr r3, [pc, #244] ; (cea8 ) + cdb4: 210c movs r1, #12 + cdb6: 4628 mov r0, r5 + cdb8: 4798 blx r3 + user_data->palette = lv_mem_alloc(palette_size * sizeof(lv_color_t)); + cdba: 2002 movs r0, #2 + cdbc: fa00 f008 lsl.w r0, r0, r8 + lv_img_decoder_built_in_data_t * user_data = dsc->user_data; + cdc0: 69e5 ldr r5, [r4, #28] + user_data->palette = lv_mem_alloc(palette_size * sizeof(lv_color_t)); + cdc2: 47d0 blx sl + cdc4: 6068 str r0, [r5, #4] + LV_ASSERT_MEM(user_data->palette); + cdc6: 47c8 blx r9 + cdc8: 4607 mov r7, r0 + cdca: b968 cbnz r0, cde8 + cdcc: 4b30 ldr r3, [pc, #192] ; (ce90 ) + cdce: 4931 ldr r1, [pc, #196] ; (ce94 ) + cdd0: 9300 str r3, [sp, #0] + cdd2: f240 1297 movw r2, #407 ; 0x197 + cdd6: 2003 movs r0, #3 + cdd8: 4c2f ldr r4, [pc, #188] ; (ce98 ) + cdda: 47a0 blx r4 + cddc: 686a ldr r2, [r5, #4] + cdde: 482f ldr r0, [pc, #188] ; (ce9c ) + cde0: 492f ldr r1, [pc, #188] ; (cea0 ) + cde2: 463b mov r3, r7 + cde4: 4788 blx r1 + cde6: e7fe b.n cde6 + uint32_t palette_size = 1 << px_size; + cde8: 2701 movs r7, #1 + cdea: fa07 f708 lsl.w r7, r7, r8 + user_data->opa = lv_mem_alloc(palette_size * sizeof(lv_opa_t)); + cdee: 4638 mov r0, r7 + cdf0: 47d0 blx sl + cdf2: 60a8 str r0, [r5, #8] + LV_ASSERT_MEM(user_data->opa); + cdf4: 47c8 blx r9 + cdf6: 4680 mov r8, r0 + cdf8: b968 cbnz r0, ce16 + cdfa: 4b25 ldr r3, [pc, #148] ; (ce90 ) + cdfc: 4925 ldr r1, [pc, #148] ; (ce94 ) + cdfe: 9300 str r3, [sp, #0] + ce00: f240 1299 movw r2, #409 ; 0x199 + ce04: 2003 movs r0, #3 + ce06: 4c24 ldr r4, [pc, #144] ; (ce98 ) + ce08: 47a0 blx r4 + ce0a: 68aa ldr r2, [r5, #8] + ce0c: 4823 ldr r0, [pc, #140] ; (ce9c ) + ce0e: 4924 ldr r1, [pc, #144] ; (cea0 ) + ce10: 4643 mov r3, r8 + ce12: 4788 blx r1 + ce14: e7fe b.n ce14 + if(user_data->palette == NULL || user_data->opa == NULL) { + ce16: 686b ldr r3, [r5, #4] + ce18: b10b cbz r3, ce1e + ce1a: 68ab ldr r3, [r5, #8] + ce1c: b92b cbnz r3, ce2a + LV_LOG_ERROR("img_decoder_built_in_open: out of memory"); + ce1e: 4b21 ldr r3, [pc, #132] ; (cea4 ) + ce20: 9300 str r3, [sp, #0] + ce22: f240 129b movw r2, #411 ; 0x19b + ce26: 4b1a ldr r3, [pc, #104] ; (ce90 ) + ce28: e76b b.n cd02 + if(dsc->src_type == LV_IMG_SRC_FILE) { + ce2a: 7aa3 ldrb r3, [r4, #10] + ce2c: 2b01 cmp r3, #1 + ce2e: d149 bne.n cec4 + lv_fs_seek(user_data->f, 4); /*Skip the header*/ + ce30: 6828 ldr r0, [r5, #0] + ce32: 4b20 ldr r3, [pc, #128] ; (ceb4 ) + lv_fs_read(user_data->f, &cur_color, sizeof(lv_color32_t), NULL); + ce34: f8df 8088 ldr.w r8, [pc, #136] ; cec0 + lv_fs_seek(user_data->f, 4); /*Skip the header*/ + ce38: 2104 movs r1, #4 + ce3a: 4798 blx r3 + for(i = 0; i < palette_size; i++) { + ce3c: 2600 movs r6, #0 + ce3e: 42be cmp r6, r7 + ce40: d101 bne.n ce46 + dsc->img_data = NULL; + ce42: 2300 movs r3, #0 + ce44: e777 b.n cd36 + lv_fs_read(user_data->f, &cur_color, sizeof(lv_color32_t), NULL); + ce46: 2300 movs r3, #0 + ce48: 2204 movs r2, #4 + ce4a: a902 add r1, sp, #8 + ce4c: 6828 ldr r0, [r5, #0] + ce4e: 47c0 blx r8 +#define LV_COLOR_MAKE(r8, g8, b8) ((lv_color_t){{b8, g8, r8, 0xff}}) /*Fix 0xff alpha*/ +#endif + +static inline lv_color_t lv_color_make(uint8_t r, uint8_t g, uint8_t b) +{ + return LV_COLOR_MAKE(r, g, b); + ce50: f89d 1009 ldrb.w r1, [sp, #9] + ce54: f89d 3008 ldrb.w r3, [sp, #8] + user_data->palette[i] = lv_color_make(cur_color.ch.red, cur_color.ch.green, cur_color.ch.blue); + ce58: 686a ldr r2, [r5, #4] + ce5a: 0889 lsrs r1, r1, #2 + ce5c: 08db lsrs r3, r3, #3 + ce5e: ea43 1341 orr.w r3, r3, r1, lsl #5 + ce62: f89d 100a ldrb.w r1, [sp, #10] + ce66: 08c9 lsrs r1, r1, #3 + ce68: ea43 23c1 orr.w r3, r3, r1, lsl #11 + ce6c: f822 3016 strh.w r3, [r2, r6, lsl #1] + user_data->opa[i] = cur_color.ch.alpha; + ce70: 68ab ldr r3, [r5, #8] + ce72: f89d 200b ldrb.w r2, [sp, #11] + ce76: 559a strb r2, [r3, r6] + for(i = 0; i < palette_size; i++) { + ce78: 3601 adds r6, #1 + ce7a: e7e0 b.n ce3e + ce7c: 0000e56d .word 0x0000e56d + ce80: 00020038 .word 0x00020038 + ce84: 00016315 .word 0x00016315 + ce88: 0000e4a1 .word 0x0000e4a1 + ce8c: 0002003c .word 0x0002003c + ce90: 00020153 .word 0x00020153 + ce94: 0001ff37 .word 0x0001ff37 + ce98: 0000e8e9 .word 0x0000e8e9 + ce9c: 0001edbe .word 0x0001edbe + cea0: 000017e9 .word 0x000017e9 + cea4: 00020067 .word 0x00020067 + cea8: 0000f019 .word 0x0000f019 + ceac: 00007581 .word 0x00007581 + ceb0: 0000c83d .word 0x0000c83d + ceb4: 0000e44f .word 0x0000e44f + ceb8: 0000ea2d .word 0x0000ea2d + cebc: 000017e1 .word 0x000017e1 + cec0: 0000e419 .word 0x0000e419 + lv_color32_t * palette_p = (lv_color32_t *)((lv_img_dsc_t *)dsc->src)->data; + cec4: 6863 ldr r3, [r4, #4] + cec6: 6899 ldr r1, [r3, #8] + for(i = 0; i < palette_size; i++) { + cec8: 2000 movs r0, #0 + ceca: 42b8 cmp r0, r7 + cecc: f101 0104 add.w r1, r1, #4 + ced0: d0b7 beq.n ce42 + ced2: f811 6c03 ldrb.w r6, [r1, #-3] + ced6: f811 3c04 ldrb.w r3, [r1, #-4] + user_data->palette[i] = lv_color_make(palette_p[i].ch.red, palette_p[i].ch.green, palette_p[i].ch.blue); + ceda: 686a ldr r2, [r5, #4] + cedc: 08b6 lsrs r6, r6, #2 + cede: 08db lsrs r3, r3, #3 + cee0: ea43 1346 orr.w r3, r3, r6, lsl #5 + cee4: f811 6c02 ldrb.w r6, [r1, #-2] + cee8: 08f6 lsrs r6, r6, #3 + ceea: ea43 23c6 orr.w r3, r3, r6, lsl #11 + ceee: f822 3010 strh.w r3, [r2, r0, lsl #1] + user_data->opa[i] = palette_p[i].ch.alpha; + cef2: 68ab ldr r3, [r5, #8] + cef4: f811 2c01 ldrb.w r2, [r1, #-1] + cef8: 541a strb r2, [r3, r0] + for(i = 0; i < palette_size; i++) { + cefa: 3001 adds r0, #1 + cefc: e7e5 b.n ceca + else if(cf == LV_IMG_CF_ALPHA_1BIT || cf == LV_IMG_CF_ALPHA_2BIT || cf == LV_IMG_CF_ALPHA_4BIT || + cefe: f1a0 030b sub.w r3, r0, #11 + cf02: 2b03 cmp r3, #3 + cf04: d99d bls.n ce42 + lv_img_decoder_built_in_close(decoder, dsc); + cf06: 4b05 ldr r3, [pc, #20] ; (cf1c ) + cf08: 4621 mov r1, r4 + cf0a: 4630 mov r0, r6 + cf0c: 4798 blx r3 + LV_LOG_WARN("Image decoder open: unknown color format") + cf0e: 4b04 ldr r3, [pc, #16] ; (cf20 ) + cf10: 9300 str r3, [sp, #0] + cf12: f240 12d3 movw r2, #467 ; 0x1d3 + cf16: 4b03 ldr r3, [pc, #12] ; (cf24 ) + cf18: e6ab b.n cc72 + cf1a: bf00 nop + cf1c: 0000c83d .word 0x0000c83d + cf20: 00020090 .word 0x00020090 + cf24: 00020153 .word 0x00020153 + +0000cf28 : +{ + cf28: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + header->always_zero = 0; + cf2c: 780b ldrb r3, [r1, #0] + _LV_LL_READ(LV_GC_ROOT(_lv_img_defoder_ll), d) { + cf2e: f8df 8044 ldr.w r8, [pc, #68] ; cf74 + cf32: f8df 9044 ldr.w r9, [pc, #68] ; cf78 + header->always_zero = 0; + cf36: f36f 1347 bfc r3, #5, #3 + cf3a: 700b strb r3, [r1, #0] +{ + cf3c: 4607 mov r7, r0 + _LV_LL_READ(LV_GC_ROOT(_lv_img_defoder_ll), d) { + cf3e: 4b0c ldr r3, [pc, #48] ; (cf70 ) + cf40: 480c ldr r0, [pc, #48] ; (cf74 ) +{ + cf42: 460e mov r6, r1 + _LV_LL_READ(LV_GC_ROOT(_lv_img_defoder_ll), d) { + cf44: 4798 blx r3 + lv_res_t res = LV_RES_INV; + cf46: 2400 movs r4, #0 + _LV_LL_READ(LV_GC_ROOT(_lv_img_defoder_ll), d) { + cf48: 4605 mov r5, r0 + cf4a: b915 cbnz r5, cf52 +} + cf4c: 4620 mov r0, r4 + cf4e: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + if(d->info_cb) { + cf52: 682c ldr r4, [r5, #0] + cf54: b134 cbz r4, cf64 + res = d->info_cb(d, src, header); + cf56: 4632 mov r2, r6 + cf58: 4639 mov r1, r7 + cf5a: 4628 mov r0, r5 + cf5c: 47a0 blx r4 + if(res == LV_RES_OK) break; + cf5e: 2801 cmp r0, #1 + res = d->info_cb(d, src, header); + cf60: 4604 mov r4, r0 + if(res == LV_RES_OK) break; + cf62: d0f3 beq.n cf4c + _LV_LL_READ(LV_GC_ROOT(_lv_img_defoder_ll), d) { + cf64: 4629 mov r1, r5 + cf66: 4640 mov r0, r8 + cf68: 47c8 blx r9 + cf6a: 4605 mov r5, r0 + cf6c: e7ed b.n cf4a + cf6e: bf00 nop + cf70: 0000e6a9 .word 0x0000e6a9 + cf74: 20008654 .word 0x20008654 + cf78: 0000e6b5 .word 0x0000e6b5 + +0000cf7c : +{ + cf7c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + dsc->src_type = lv_img_src_get_type(src); + cf80: 4b22 ldr r3, [pc, #136] ; (d00c ) + dsc->color = color; + cf82: 8102 strh r2, [r0, #8] +{ + cf84: 4604 mov r4, r0 + dsc->src_type = lv_img_src_get_type(src); + cf86: 4608 mov r0, r1 +{ + cf88: 460f mov r7, r1 + dsc->src_type = lv_img_src_get_type(src); + cf8a: 4798 blx r3 + dsc->user_data = NULL; + cf8c: 2300 movs r3, #0 + if(dsc->src_type == LV_IMG_SRC_FILE) { + cf8e: 2801 cmp r0, #1 + dsc->src_type = lv_img_src_get_type(src); + cf90: 72a0 strb r0, [r4, #10] + dsc->user_data = NULL; + cf92: 61e3 str r3, [r4, #28] + if(dsc->src_type == LV_IMG_SRC_FILE) { + cf94: d11d bne.n cfd2 + size_t fnlen = strlen(src); + cf96: 4b1e ldr r3, [pc, #120] ; (d010 ) + cf98: 4638 mov r0, r7 + cf9a: 4798 blx r3 + dsc->src = lv_mem_alloc(fnlen + 1); + cf9c: 4b1d ldr r3, [pc, #116] ; (d014 ) + cf9e: 3001 adds r0, #1 + cfa0: 4798 blx r3 +__ssp_bos_icheck3(memset, void *, int) +__ssp_bos_icheck2_restrict(stpcpy, char *, const char *) +#if __GNUC_PREREQ__(4,8) || defined(__clang__) +__ssp_bos_icheck3_restrict(stpncpy, char *, const char *) +#endif +__ssp_bos_icheck2_restrict(strcpy, char *, const char *) + cfa2: 4b1d ldr r3, [pc, #116] ; (d018 ) + cfa4: 6060 str r0, [r4, #4] + cfa6: 4639 mov r1, r7 + cfa8: 4798 blx r3 + _LV_LL_READ(LV_GC_ROOT(_lv_img_defoder_ll), d) { + cfaa: 481c ldr r0, [pc, #112] ; (d01c ) + cfac: 4b1c ldr r3, [pc, #112] ; (d020 ) + cfae: f8df 906c ldr.w r9, [pc, #108] ; d01c + cfb2: f8df a074 ldr.w sl, [pc, #116] ; d028 + cfb6: 4798 blx r3 + lv_res_t res = LV_RES_INV; + cfb8: 2600 movs r6, #0 + _LV_LL_READ(LV_GC_ROOT(_lv_img_defoder_ll), d) { + cfba: 4605 mov r5, r0 + res = d->info_cb(d, src, &dsc->header); + cfbc: f104 080c add.w r8, r4, #12 + _LV_LL_READ(LV_GC_ROOT(_lv_img_defoder_ll), d) { + cfc0: b94d cbnz r5, cfd6 + if(res == LV_RES_INV) { + cfc2: b91e cbnz r6, cfcc + _lv_memset_00(dsc, sizeof(lv_img_decoder_dsc_t)); + cfc4: 4b17 ldr r3, [pc, #92] ; (d024 ) + cfc6: 2120 movs r1, #32 + cfc8: 4620 mov r0, r4 + cfca: 4798 blx r3 +} + cfcc: 4630 mov r0, r6 + cfce: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + dsc->src = src; + cfd2: 6067 str r7, [r4, #4] + cfd4: e7e9 b.n cfaa + if(d->info_cb == NULL || d->open_cb == NULL) continue; + cfd6: 682b ldr r3, [r5, #0] + cfd8: b19b cbz r3, d002 + cfda: 686a ldr r2, [r5, #4] + cfdc: b18a cbz r2, d002 + res = d->info_cb(d, src, &dsc->header); + cfde: 4642 mov r2, r8 + cfe0: 4639 mov r1, r7 + cfe2: 4628 mov r0, r5 + cfe4: 4798 blx r3 + if(res != LV_RES_OK) continue; + cfe6: 2801 cmp r0, #1 + res = d->info_cb(d, src, &dsc->header); + cfe8: 4606 mov r6, r0 + if(res != LV_RES_OK) continue; + cfea: d10a bne.n d002 + dsc->error_msg = NULL; + cfec: 2300 movs r3, #0 + cfee: 61a3 str r3, [r4, #24] + dsc->img_data = NULL; + cff0: 6123 str r3, [r4, #16] + dsc->decoder = d; + cff2: 6025 str r5, [r4, #0] + res = d->open_cb(d, dsc); + cff4: 686b ldr r3, [r5, #4] + cff6: 4621 mov r1, r4 + cff8: 4628 mov r0, r5 + cffa: 4798 blx r3 + if(res == LV_RES_OK) break; + cffc: 2801 cmp r0, #1 + res = d->open_cb(d, dsc); + cffe: 4606 mov r6, r0 + if(res == LV_RES_OK) break; + d000: d0e4 beq.n cfcc + _LV_LL_READ(LV_GC_ROOT(_lv_img_defoder_ll), d) { + d002: 4629 mov r1, r5 + d004: 4648 mov r0, r9 + d006: 47d0 blx sl + d008: 4605 mov r5, r0 + d00a: e7d9 b.n cfc0 + d00c: 00007805 .word 0x00007805 + d010: 00016339 .word 0x00016339 + d014: 0000ea2d .word 0x0000ea2d + d018: 00016329 .word 0x00016329 + d01c: 20008654 .word 0x20008654 + d020: 0000e6a9 .word 0x0000e6a9 + d024: 0000f019 .word 0x0000f019 + d028: 0000e6b5 .word 0x0000e6b5 + +0000d02c : +{ + d02c: b573 push {r0, r1, r4, r5, r6, lr} + if(dsc->decoder->read_line_cb) res = dsc->decoder->read_line_cb(dsc->decoder, dsc, x, y, len, buf); + d02e: 6805 ldr r5, [r0, #0] + d030: 68ac ldr r4, [r5, #8] + d032: b14c cbz r4, d048 + d034: 9e06 ldr r6, [sp, #24] + d036: e9cd 3600 strd r3, r6, [sp] + d03a: 4613 mov r3, r2 + d03c: 460a mov r2, r1 + d03e: 4601 mov r1, r0 + d040: 4628 mov r0, r5 + d042: 47a0 blx r4 +} + d044: b002 add sp, #8 + d046: bd70 pop {r4, r5, r6, pc} + lv_res_t res = LV_RES_INV; + d048: 4620 mov r0, r4 + d04a: e7fb b.n d044 + +0000d04c : +{ + d04c: b510 push {r4, lr} + d04e: 4604 mov r4, r0 + if(dsc->decoder) { + d050: 6800 ldr r0, [r0, #0] + d052: b158 cbz r0, d06c + if(dsc->decoder->close_cb) dsc->decoder->close_cb(dsc->decoder, dsc); + d054: 68c3 ldr r3, [r0, #12] + d056: b10b cbz r3, d05c + d058: 4621 mov r1, r4 + d05a: 4798 blx r3 + if(dsc->src_type == LV_IMG_SRC_FILE) { + d05c: 7aa3 ldrb r3, [r4, #10] + d05e: 2b01 cmp r3, #1 + d060: d104 bne.n d06c + lv_mem_free(dsc->src); + d062: 4b03 ldr r3, [pc, #12] ; (d070 ) + d064: 6860 ldr r0, [r4, #4] + d066: 4798 blx r3 + dsc->src = NULL; + d068: 2300 movs r3, #0 + d06a: 6063 str r3, [r4, #4] +} + d06c: bd10 pop {r4, pc} + d06e: bf00 nop + d070: 0000eae5 .word 0x0000eae5 + +0000d074 : +{ + d074: b573 push {r0, r1, r4, r5, r6, lr} + decoder = _lv_ll_ins_head(&LV_GC_ROOT(_lv_img_defoder_ll)); + d076: 4b0e ldr r3, [pc, #56] ; (d0b0 ) + d078: 480e ldr r0, [pc, #56] ; (d0b4 ) + d07a: 4798 blx r3 + LV_ASSERT_MEM(decoder); + d07c: 4b0e ldr r3, [pc, #56] ; (d0b8 ) + decoder = _lv_ll_ins_head(&LV_GC_ROOT(_lv_img_defoder_ll)); + d07e: 4604 mov r4, r0 + LV_ASSERT_MEM(decoder); + d080: 4798 blx r3 + d082: 4605 mov r5, r0 + d084: b960 cbnz r0, d0a0 + d086: 4b0d ldr r3, [pc, #52] ; (d0bc ) + d088: 490d ldr r1, [pc, #52] ; (d0c0 ) + d08a: 9300 str r3, [sp, #0] + d08c: 22c9 movs r2, #201 ; 0xc9 + d08e: 2003 movs r0, #3 + d090: 4e0c ldr r6, [pc, #48] ; (d0c4 ) + d092: 47b0 blx r6 + d094: 480c ldr r0, [pc, #48] ; (d0c8 ) + d096: 490d ldr r1, [pc, #52] ; (d0cc ) + d098: 4622 mov r2, r4 + d09a: 462b mov r3, r5 + d09c: 4788 blx r1 + d09e: e7fe b.n d09e + if(decoder == NULL) return NULL; + d0a0: b11c cbz r4, d0aa + _lv_memset_00(decoder, sizeof(lv_img_decoder_t)); + d0a2: 4b0b ldr r3, [pc, #44] ; (d0d0 ) + d0a4: 2110 movs r1, #16 + d0a6: 4620 mov r0, r4 + d0a8: 4798 blx r3 +} + d0aa: 4620 mov r0, r4 + d0ac: b002 add sp, #8 + d0ae: bd70 pop {r4, r5, r6, pc} + d0b0: 0000e619 .word 0x0000e619 + d0b4: 20008654 .word 0x20008654 + d0b8: 000017e1 .word 0x000017e1 + d0bc: 00020170 .word 0x00020170 + d0c0: 0001ff37 .word 0x0001ff37 + d0c4: 0000e8e9 .word 0x0000e8e9 + d0c8: 0001edbe .word 0x0001edbe + d0cc: 000017e9 .word 0x000017e9 + d0d0: 0000f019 .word 0x0000f019 + +0000d0d4 <_lv_img_decoder_init>: +{ + d0d4: b537 push {r0, r1, r2, r4, r5, lr} + _lv_ll_init(&LV_GC_ROOT(_lv_img_defoder_ll), sizeof(lv_img_decoder_t)); + d0d6: 4b15 ldr r3, [pc, #84] ; (d12c <_lv_img_decoder_init+0x58>) + d0d8: 4815 ldr r0, [pc, #84] ; (d130 <_lv_img_decoder_init+0x5c>) + d0da: 2110 movs r1, #16 + d0dc: 4798 blx r3 + decoder = lv_img_decoder_create(); + d0de: 4b15 ldr r3, [pc, #84] ; (d134 <_lv_img_decoder_init+0x60>) + d0e0: 4798 blx r3 + if(decoder == NULL) { + d0e2: 4604 mov r4, r0 + d0e4: b9b8 cbnz r0, d116 <_lv_img_decoder_init+0x42> + LV_LOG_WARN("lv_img_decoder_init: out of memory"); + d0e6: 4a14 ldr r2, [pc, #80] ; (d138 <_lv_img_decoder_init+0x64>) + d0e8: 9200 str r2, [sp, #0] + d0ea: 2002 movs r0, #2 + d0ec: 2247 movs r2, #71 ; 0x47 + d0ee: 4b13 ldr r3, [pc, #76] ; (d13c <_lv_img_decoder_init+0x68>) + d0f0: 4913 ldr r1, [pc, #76] ; (d140 <_lv_img_decoder_init+0x6c>) + d0f2: 4d14 ldr r5, [pc, #80] ; (d144 <_lv_img_decoder_init+0x70>) + d0f4: 47a8 blx r5 + LV_ASSERT_MEM(decoder); + d0f6: 4a14 ldr r2, [pc, #80] ; (d148 <_lv_img_decoder_init+0x74>) + d0f8: 4620 mov r0, r4 + d0fa: 4790 blx r2 + d0fc: b998 cbnz r0, d126 <_lv_img_decoder_init+0x52> + d0fe: 4b0f ldr r3, [pc, #60] ; (d13c <_lv_img_decoder_init+0x68>) + d100: 490f ldr r1, [pc, #60] ; (d140 <_lv_img_decoder_init+0x6c>) + d102: 9300 str r3, [sp, #0] + d104: 2248 movs r2, #72 ; 0x48 + d106: 2003 movs r0, #3 + d108: 47a8 blx r5 + d10a: 4810 ldr r0, [pc, #64] ; (d14c <_lv_img_decoder_init+0x78>) + d10c: 4910 ldr r1, [pc, #64] ; (d150 <_lv_img_decoder_init+0x7c>) + d10e: 2200 movs r2, #0 + d110: 2300 movs r3, #0 + d112: 4788 blx r1 + d114: e7fe b.n d114 <_lv_img_decoder_init+0x40> + decoder->info_cb = info_cb; + d116: 4b0f ldr r3, [pc, #60] ; (d154 <_lv_img_decoder_init+0x80>) + d118: 6003 str r3, [r0, #0] + decoder->open_cb = open_cb; + d11a: 4b0f ldr r3, [pc, #60] ; (d158 <_lv_img_decoder_init+0x84>) + d11c: 6043 str r3, [r0, #4] + decoder->read_line_cb = read_line_cb; + d11e: 4b0f ldr r3, [pc, #60] ; (d15c <_lv_img_decoder_init+0x88>) + d120: 6083 str r3, [r0, #8] + decoder->close_cb = close_cb; + d122: 4b0f ldr r3, [pc, #60] ; (d160 <_lv_img_decoder_init+0x8c>) + d124: 60c3 str r3, [r0, #12] +} + d126: b003 add sp, #12 + d128: bd30 pop {r4, r5, pc} + d12a: bf00 nop + d12c: 0000e605 .word 0x0000e605 + d130: 20008654 .word 0x20008654 + d134: 0000d075 .word 0x0000d075 + d138: 000200b9 .word 0x000200b9 + d13c: 00020186 .word 0x00020186 + d140: 0001ff37 .word 0x0001ff37 + d144: 0000e8e9 .word 0x0000e8e9 + d148: 000017e1 .word 0x000017e1 + d14c: 0001edbe .word 0x0001edbe + d150: 000017e9 .word 0x000017e9 + d154: 0000c75d .word 0x0000c75d + d158: 0000cc3d .word 0x0000cc3d + d15c: 0000c871 .word 0x0000c871 + d160: 0000c83d .word 0x0000c83d + +0000d164 : + * @param letter an UNICODE character code + * @return pointer to the bitmap of the letter + */ +const uint8_t * lv_font_get_glyph_bitmap(const lv_font_t * font_p, uint32_t letter) +{ + return font_p->get_glyph_bitmap(font_p, letter); + d164: 6843 ldr r3, [r0, #4] + d166: 4718 bx r3 + +0000d168 : + * @return true: descriptor is successfully loaded into `dsc_out`. + * false: the letter was not found, no data is loaded to `dsc_out` + */ +bool lv_font_get_glyph_dsc(const lv_font_t * font_p, lv_font_glyph_dsc_t * dsc_out, uint32_t letter, + uint32_t letter_next) +{ + d168: b410 push {r4} + return font_p->get_glyph_dsc(font_p, dsc_out, letter, letter_next); + d16a: 6804 ldr r4, [r0, #0] + d16c: 46a4 mov ip, r4 +} + d16e: f85d 4b04 ldr.w r4, [sp], #4 + return font_p->get_glyph_dsc(font_p, dsc_out, letter, letter_next); + d172: 4760 bx ip + +0000d174 : + * @param letter an UNICODE letter + * @param letter_next the next letter after `letter`. Used for kerning + * @return the width of the glyph + */ +uint16_t lv_font_get_glyph_width(const lv_font_t * font, uint32_t letter, uint32_t letter_next) +{ + d174: b51f push {r0, r1, r2, r3, r4, lr} + d176: 4613 mov r3, r2 + lv_font_glyph_dsc_t g; + bool ret; + ret = lv_font_get_glyph_dsc(font, &g, letter, letter_next); + d178: 4c04 ldr r4, [pc, #16] ; (d18c ) + d17a: 460a mov r2, r1 + d17c: a901 add r1, sp, #4 + d17e: 47a0 blx r4 + if(ret) return g.adv_w; + d180: b108 cbz r0, d186 + d182: f8bd 0004 ldrh.w r0, [sp, #4] + else return 0; +} + d186: b004 add sp, #16 + d188: bd10 pop {r4, pc} + d18a: bf00 nop + d18c: 0000d169 .word 0x0000d169 + +0000d190 : +{ + const uint8_t * ref8_p = ref; + const uint8_t * element8_p = element; + + /*If the MSB is different it will matter. If not return the diff. of the LSB*/ + if(ref8_p[0] != element8_p[0]) return (int32_t)ref8_p[0] - element8_p[0]; + d190: 7803 ldrb r3, [r0, #0] + d192: 780a ldrb r2, [r1, #0] + d194: 4293 cmp r3, r2 + else return (int32_t) ref8_p[1] - element8_p[1]; + d196: bf09 itett eq + d198: 784b ldrbeq r3, [r1, #1] + if(ref8_p[0] != element8_p[0]) return (int32_t)ref8_p[0] - element8_p[0]; + d19a: 1a98 subne r0, r3, r2 + else return (int32_t) ref8_p[1] - element8_p[1]; + d19c: 7840 ldrbeq r0, [r0, #1] + d19e: 1ac0 subeq r0, r0, r3 + +} + d1a0: 4770 bx lr + +0000d1a2 : +{ + const uint16_t * ref16_p = ref; + const uint16_t * element16_p = element; + + /*If the MSB is different it will matter. If not return the diff. of the LSB*/ + if(ref16_p[0] != element16_p[0]) return (int32_t)ref16_p[0] - element16_p[0]; + d1a2: 8803 ldrh r3, [r0, #0] + d1a4: 880a ldrh r2, [r1, #0] + d1a6: 4293 cmp r3, r2 + else return (int32_t) ref16_p[1] - element16_p[1]; + d1a8: bf09 itett eq + d1aa: 884b ldrheq r3, [r1, #2] + if(ref16_p[0] != element16_p[0]) return (int32_t)ref16_p[0] - element16_p[0]; + d1ac: 1a98 subne r0, r3, r2 + else return (int32_t) ref16_p[1] - element16_p[1]; + d1ae: 8840 ldrheq r0, [r0, #2] + d1b0: 1ac0 subeq r0, r0, r3 +} + d1b2: 4770 bx lr + +0000d1b4 : + * @return the read bits + */ +static inline uint8_t get_bits(const uint8_t * in, uint32_t bit_pos, uint8_t len) +{ + uint8_t bit_mask; + switch(len) { + d1b4: 1e53 subs r3, r2, #1 +{ + d1b6: b530 push {r4, r5, lr} + switch(len) { + d1b8: 2b07 cmp r3, #7 + d1ba: d81f bhi.n d1fc + d1bc: e8df f003 tbb [pc, r3] + d1c0: 1a180423 .word 0x1a180423 + d1c4: 1c1e1e1e .word 0x1c1e1e1e + case 1: + bit_mask = 0x1; + break; + case 2: + bit_mask = 0x3; + d1c8: 2303 movs r3, #3 + break; + default: + bit_mask = (uint16_t)((uint16_t) 1 << len) - 1; + } + + uint32_t byte_pos = bit_pos >> 3; + d1ca: 08cd lsrs r5, r1, #3 + bit_pos = bit_pos & 0x7; + d1cc: f001 0107 and.w r1, r1, #7 + + if(bit_pos + len >= 8) { + d1d0: 440a add r2, r1 + d1d2: 2a07 cmp r2, #7 + uint16_t in16 = (in[byte_pos] << 8) + in[byte_pos + 1]; + d1d4: 5d44 ldrb r4, [r0, r5] + if(bit_pos + len >= 8) { + d1d6: d918 bls.n d20a + uint16_t in16 = (in[byte_pos] << 8) + in[byte_pos + 1]; + d1d8: 4428 add r0, r5 + return (in16 >> (16 - bit_pos - len)) & bit_mask; + d1da: f1c2 0210 rsb r2, r2, #16 + uint16_t in16 = (in[byte_pos] << 8) + in[byte_pos + 1]; + d1de: 7841 ldrb r1, [r0, #1] + d1e0: eb01 2104 add.w r1, r1, r4, lsl #8 + return (in16 >> (16 - bit_pos - len)) & bit_mask; + d1e4: b289 uxth r1, r1 + d1e6: fa41 f202 asr.w r2, r1, r2 + d1ea: ea03 0002 and.w r0, r3, r2 + } + else { + return (in[byte_pos] >> (8 - bit_pos - len)) & bit_mask; + } +} + d1ee: bd30 pop {r4, r5, pc} + bit_mask = 0x7; + d1f0: 2307 movs r3, #7 + break; + d1f2: e7ea b.n d1ca + bit_mask = 0xF; + d1f4: 230f movs r3, #15 + break; + d1f6: e7e8 b.n d1ca + bit_mask = 0xFF; + d1f8: 23ff movs r3, #255 ; 0xff + break; + d1fa: e7e6 b.n d1ca + bit_mask = (uint16_t)((uint16_t) 1 << len) - 1; + d1fc: 2301 movs r3, #1 + d1fe: 4093 lsls r3, r2 + d200: 3b01 subs r3, #1 + d202: b2db uxtb r3, r3 + d204: e7e1 b.n d1ca + switch(len) { + d206: 4613 mov r3, r2 + d208: e7df b.n d1ca + return (in[byte_pos] >> (8 - bit_pos - len)) & bit_mask; + d20a: f1c2 0208 rsb r2, r2, #8 + d20e: 4114 asrs r4, r2 + d210: ea03 0004 and.w r0, r3, r4 + d214: e7eb b.n d1ee + ... + +0000d218 : + * @param len length of bits to write from `val`. (Counted from the LSB). + * @note `len == 3` will be converted to `len = 4` and `val` will be upscaled too + */ +static inline void bits_write(uint8_t * out, uint32_t bit_pos, uint8_t val, uint8_t len) +{ + if(len == 3) { + d218: 2b03 cmp r3, #3 +{ + d21a: b530 push {r4, r5, lr} + if(len == 3) { + d21c: d104 bne.n d228 + len = 4; + switch(val) { + d21e: 2a07 cmp r2, #7 + d220: bf9c itt ls + d222: 4b0b ldrls r3, [pc, #44] ; (d250 ) + d224: 5c9a ldrbls r2, [r3, r2] + len = 4; + d226: 2304 movs r3, #4 + break; + } + } + + uint16_t byte_pos = bit_pos >> 3; + bit_pos = bit_pos & 0x7; + d228: f001 0507 and.w r5, r1, #7 + bit_pos = 8 - bit_pos - len; + + uint8_t bit_mask = (uint16_t)((uint16_t) 1 << len) - 1; + out[byte_pos] &= ((~bit_mask) << bit_pos); + d22c: f04f 34ff mov.w r4, #4294967295 ; 0xffffffff + d230: f3c1 01cf ubfx r1, r1, #3, #16 + d234: f1c5 0508 rsb r5, r5, #8 + bit_pos = 8 - bit_pos - len; + d238: 1aed subs r5, r5, r3 + out[byte_pos] &= ((~bit_mask) << bit_pos); + d23a: fa04 f303 lsl.w r3, r4, r3 + d23e: f063 03ff orn r3, r3, #255 ; 0xff + d242: 5c44 ldrb r4, [r0, r1] + d244: 40ab lsls r3, r5 + d246: 4023 ands r3, r4 + out[byte_pos] |= (val << bit_pos); + d248: 40aa lsls r2, r5 + d24a: 431a orrs r2, r3 + d24c: 5442 strb r2, [r0, r1] +} + d24e: bd30 pop {r4, r5, pc} + d250: 000201d3 .word 0x000201d3 + +0000d254 : +{ + d254: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} + } + else if(rle_state == RLE_STATE_COUNTER) { + ret = rle_prev_v; + rle_cnt--; + if(rle_cnt == 0) { + ret = get_bits(rle_in, rle_rdp, rle_bpp); + d258: 4c39 ldr r4, [pc, #228] ; (d340 ) + d25a: f8df a0e8 ldr.w sl, [pc, #232] ; d344 + d25e: f8d4 9000 ldr.w r9, [r4] + d262: 7927 ldrb r7, [r4, #4] + d264: 1843 adds r3, r0, r1 + d266: 4680 mov r8, r0 + d268: 9300 str r3, [sp, #0] + rle_state = RLE_STATE_COUNTER; + d26a: f04f 0b02 mov.w fp, #2 + for(i = 0; i < w; i++) { + d26e: 9b00 ldr r3, [sp, #0] + d270: 4543 cmp r3, r8 + d272: d102 bne.n d27a +} + d274: b003 add sp, #12 + d276: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + if(rle_state == RLE_STATE_SINGLE) { + d27a: 7963 ldrb r3, [r4, #5] + d27c: b9a3 cbnz r3, d2a8 + ret = get_bits(rle_in, rle_rdp, rle_bpp); + d27e: 68a6 ldr r6, [r4, #8] + d280: 9301 str r3, [sp, #4] + d282: 463a mov r2, r7 + d284: 4631 mov r1, r6 + d286: 4648 mov r0, r9 + d288: 47d0 blx sl + d28a: 4605 mov r5, r0 + if(rle_rdp != 0 && rle_prev_v == ret) { + d28c: b136 cbz r6, d29c + d28e: 7b22 ldrb r2, [r4, #12] + d290: 9b01 ldr r3, [sp, #4] + d292: 4282 cmp r2, r0 + rle_cnt = 0; + d294: bf02 ittt eq + d296: 7363 strbeq r3, [r4, #13] + rle_state = RLE_STATE_REPEATE; + d298: 2301 moveq r3, #1 + d29a: 7163 strbeq r3, [r4, #5] + rle_rdp += rle_bpp; + d29c: 443e add r6, r7 + rle_prev_v = ret; + d29e: 7325 strb r5, [r4, #12] + rle_rdp += rle_bpp; + d2a0: 60a6 str r6, [r4, #8] + out[i] = rle_next(); + d2a2: f808 5b01 strb.w r5, [r8], #1 + for(i = 0; i < w; i++) { + d2a6: e7e2 b.n d26e + else if(rle_state == RLE_STATE_REPEATE) { + d2a8: 2b01 cmp r3, #1 + d2aa: d131 bne.n d310 + v = get_bits(rle_in, rle_rdp, 1); + d2ac: 68a6 ldr r6, [r4, #8] + d2ae: 461a mov r2, r3 + d2b0: 4631 mov r1, r6 + d2b2: 4648 mov r0, r9 + d2b4: 47d0 blx sl + rle_cnt++; + d2b6: 7b63 ldrb r3, [r4, #13] + d2b8: 3301 adds r3, #1 + d2ba: b2db uxtb r3, r3 + rle_rdp += 1; + d2bc: 1c71 adds r1, r6, #1 + if(v == 1) { + d2be: 2801 cmp r0, #1 + rle_cnt++; + d2c0: 7363 strb r3, [r4, #13] + rle_rdp += 1; + d2c2: 60a1 str r1, [r4, #8] + if(v == 1) { + d2c4: d118 bne.n d2f8 + if(rle_cnt == 11) { + d2c6: 2b0b cmp r3, #11 + ret = rle_prev_v; + d2c8: 7b25 ldrb r5, [r4, #12] + if(rle_cnt == 11) { + d2ca: d1ea bne.n d2a2 + rle_cnt = get_bits(rle_in, rle_rdp, 6); + d2cc: 2206 movs r2, #6 + d2ce: 4648 mov r0, r9 + d2d0: 47d0 blx sl + rle_rdp += 6; + d2d2: 3607 adds r6, #7 + rle_cnt = get_bits(rle_in, rle_rdp, 6); + d2d4: 7360 strb r0, [r4, #13] + rle_rdp += 6; + d2d6: 60a6 str r6, [r4, #8] + if(rle_cnt != 0) { + d2d8: b110 cbz r0, d2e0 + rle_state = RLE_STATE_COUNTER; + d2da: f884 b005 strb.w fp, [r4, #5] + d2de: e7e0 b.n d2a2 + d2e0: 9001 str r0, [sp, #4] + ret = get_bits(rle_in, rle_rdp, rle_bpp); + d2e2: 4631 mov r1, r6 + d2e4: 463a mov r2, r7 + d2e6: 4648 mov r0, r9 + d2e8: 47d0 blx sl + rle_rdp += rle_bpp; + d2ea: 443e add r6, r7 + rle_state = RLE_STATE_SINGLE; + d2ec: 9b01 ldr r3, [sp, #4] + rle_prev_v = ret; + d2ee: 7320 strb r0, [r4, #12] + ret = get_bits(rle_in, rle_rdp, rle_bpp); + d2f0: 4605 mov r5, r0 + rle_rdp += rle_bpp; + d2f2: 60a6 str r6, [r4, #8] + rle_state = RLE_STATE_SINGLE; + d2f4: 7163 strb r3, [r4, #5] + d2f6: e7d4 b.n d2a2 + ret = get_bits(rle_in, rle_rdp, rle_bpp); + d2f8: 463a mov r2, r7 + d2fa: 4648 mov r0, r9 + d2fc: 9101 str r1, [sp, #4] + d2fe: 47d0 blx sl + rle_rdp += rle_bpp; + d300: 9901 ldr r1, [sp, #4] + rle_prev_v = ret; + d302: 7320 strb r0, [r4, #12] + rle_rdp += rle_bpp; + d304: 4439 add r1, r7 + ret = get_bits(rle_in, rle_rdp, rle_bpp); + d306: 4605 mov r5, r0 + rle_rdp += rle_bpp; + d308: 60a1 str r1, [r4, #8] + rle_state = RLE_STATE_SINGLE; + d30a: f04f 0300 mov.w r3, #0 + d30e: e7f1 b.n d2f4 + else if(rle_state == RLE_STATE_COUNTER) { + d310: 2b02 cmp r3, #2 + d312: d112 bne.n d33a + rle_cnt--; + d314: 7b66 ldrb r6, [r4, #13] + ret = rle_prev_v; + d316: 7b25 ldrb r5, [r4, #12] + rle_cnt--; + d318: 3e01 subs r6, #1 + d31a: b2f6 uxtb r6, r6 + d31c: 7366 strb r6, [r4, #13] + if(rle_cnt == 0) { + d31e: 2e00 cmp r6, #0 + d320: d1bf bne.n d2a2 + ret = get_bits(rle_in, rle_rdp, rle_bpp); + d322: 68a1 ldr r1, [r4, #8] + d324: 9101 str r1, [sp, #4] + d326: 463a mov r2, r7 + d328: 4648 mov r0, r9 + d32a: 47d0 blx sl + rle_prev_v = ret; + rle_rdp += rle_bpp; + d32c: 9901 ldr r1, [sp, #4] + rle_prev_v = ret; + d32e: 7320 strb r0, [r4, #12] + rle_rdp += rle_bpp; + d330: 4439 add r1, r7 + ret = get_bits(rle_in, rle_rdp, rle_bpp); + d332: 4605 mov r5, r0 + rle_rdp += rle_bpp; + d334: 60a1 str r1, [r4, #8] + rle_state = RLE_STATE_SINGLE; + d336: 7166 strb r6, [r4, #5] + d338: e7b3 b.n d2a2 + uint8_t ret = 0; + d33a: 2500 movs r5, #0 + d33c: e7b1 b.n d2a2 + d33e: bf00 nop + d340: 200085d4 .word 0x200085d4 + d344: 0000d1b5 .word 0x0000d1b5 + +0000d348 : + * @retval > 0 Reference is less than element. + * + */ +static int32_t unicode_list_compare(const void * ref, const void * element) +{ + return ((int32_t)(*(uint16_t *)ref)) - ((int32_t)(*(uint16_t *)element)); + d348: 8800 ldrh r0, [r0, #0] + d34a: 880b ldrh r3, [r1, #0] +} + d34c: 1ac0 subs r0, r0, r3 + d34e: 4770 bx lr + +0000d350 : +{ + d350: b5f0 push {r4, r5, r6, r7, lr} + if(letter == '\0') return 0; + d352: 460c mov r4, r1 +{ + d354: b085 sub sp, #20 + if(letter == '\0') return 0; + d356: b121 cbz r1, d362 + d358: 6905 ldr r5, [r0, #16] + if(letter == fdsc->last_letter) return fdsc->last_glyph_id; + d35a: 69ab ldr r3, [r5, #24] + d35c: 4299 cmp r1, r3 + d35e: d146 bne.n d3ee + d360: 69ec ldr r4, [r5, #28] +} + d362: 4620 mov r0, r4 + d364: b005 add sp, #20 + d366: bdf0 pop {r4, r5, r6, r7, pc} + uint32_t rcp = letter - fdsc->cmaps[i].range_start; + d368: 68aa ldr r2, [r5, #8] + d36a: fb00 f603 mul.w r6, r0, r3 + d36e: 1991 adds r1, r2, r6 + d370: 5992 ldr r2, [r2, r6] + if(rcp > fdsc->cmaps[i].range_length) continue; + d372: 888f ldrh r7, [r1, #4] + uint32_t rcp = letter - fdsc->cmaps[i].range_start; + d374: 1aa2 subs r2, r4, r2 + if(rcp > fdsc->cmaps[i].range_length) continue; + d376: 42ba cmp r2, r7 + uint32_t rcp = letter - fdsc->cmaps[i].range_start; + d378: 9203 str r2, [sp, #12] + if(rcp > fdsc->cmaps[i].range_length) continue; + d37a: f103 0301 add.w r3, r3, #1 + d37e: d838 bhi.n d3f2 + if(fdsc->cmaps[i].type == LV_FONT_FMT_TXT_CMAP_FORMAT0_TINY) { + d380: 7c8b ldrb r3, [r1, #18] + d382: b913 cbnz r3, d38a + glyph_id = fdsc->cmaps[i].glyph_id_start + rcp; + d384: 88cb ldrh r3, [r1, #6] + glyph_id = fdsc->cmaps[i].glyph_id_start + gid_ofs_16[ofs]; + d386: 4413 add r3, r2 + d388: e010 b.n d3ac + else if(fdsc->cmaps[i].type == LV_FONT_FMT_TXT_CMAP_FORMAT0_FULL) { + d38a: 2b01 cmp r3, #1 + d38c: d103 bne.n d396 + glyph_id = fdsc->cmaps[i].glyph_id_start + gid_ofs_8[rcp]; + d38e: 68cb ldr r3, [r1, #12] + d390: 5c9b ldrb r3, [r3, r2] + d392: 88ca ldrh r2, [r1, #6] + d394: e7f7 b.n d386 + else if(fdsc->cmaps[i].type == LV_FONT_FMT_TXT_CMAP_SPARSE_TINY) { + d396: 2b02 cmp r3, #2 + d398: d114 bne.n d3c4 + uint8_t * p = _lv_utils_bsearch(&rcp, fdsc->cmaps[i].unicode_list, fdsc->cmaps[i].list_length, + d39a: 481b ldr r0, [pc, #108] ; (d408 ) + d39c: 8a0a ldrh r2, [r1, #16] + d39e: 9000 str r0, [sp, #0] + d3a0: 6889 ldr r1, [r1, #8] + d3a2: 4f1a ldr r7, [pc, #104] ; (d40c ) + d3a4: a803 add r0, sp, #12 + d3a6: 47b8 blx r7 + if(p) { + d3a8: b920 cbnz r0, d3b4 + uint32_t glyph_id = 0; + d3aa: 2300 movs r3, #0 + fdsc->last_glyph_id = glyph_id; + d3ac: e9c5 4306 strd r4, r3, [r5, #24] + return glyph_id; + d3b0: 461c mov r4, r3 + d3b2: e7d6 b.n d362 + lv_uintptr_t ofs = (lv_uintptr_t)(p - (uint8_t *) fdsc->cmaps[i].unicode_list); + d3b4: 68ab ldr r3, [r5, #8] + d3b6: 4433 add r3, r6 + d3b8: 689a ldr r2, [r3, #8] + glyph_id = fdsc->cmaps[i].glyph_id_start + ofs; + d3ba: 88db ldrh r3, [r3, #6] + lv_uintptr_t ofs = (lv_uintptr_t)(p - (uint8_t *) fdsc->cmaps[i].unicode_list); + d3bc: 1a80 subs r0, r0, r2 + glyph_id = fdsc->cmaps[i].glyph_id_start + ofs; + d3be: eb03 0350 add.w r3, r3, r0, lsr #1 + d3c2: e7f3 b.n d3ac + else if(fdsc->cmaps[i].type == LV_FONT_FMT_TXT_CMAP_SPARSE_FULL) { + d3c4: 2b03 cmp r3, #3 + d3c6: d1f0 bne.n d3aa + uint8_t * p = _lv_utils_bsearch(&rcp, fdsc->cmaps[i].unicode_list, fdsc->cmaps[i].list_length, + d3c8: 4b0f ldr r3, [pc, #60] ; (d408 ) + d3ca: 8a0a ldrh r2, [r1, #16] + d3cc: 9300 str r3, [sp, #0] + d3ce: 6889 ldr r1, [r1, #8] + d3d0: 4f0e ldr r7, [pc, #56] ; (d40c ) + d3d2: 2302 movs r3, #2 + d3d4: a803 add r0, sp, #12 + d3d6: 47b8 blx r7 + if(p) { + d3d8: 2800 cmp r0, #0 + d3da: d0e6 beq.n d3aa + lv_uintptr_t ofs = (lv_uintptr_t)(p - (uint8_t *) fdsc->cmaps[i].unicode_list); + d3dc: 68aa ldr r2, [r5, #8] + d3de: 4432 add r2, r6 + d3e0: 6893 ldr r3, [r2, #8] + d3e2: 1ac0 subs r0, r0, r3 + ofs = ofs >> 1; /*The list stores `uint16_t` so the get the index divide by 2*/ + d3e4: 0840 lsrs r0, r0, #1 + glyph_id = fdsc->cmaps[i].glyph_id_start + gid_ofs_16[ofs]; + d3e6: 68d3 ldr r3, [r2, #12] + d3e8: 88d2 ldrh r2, [r2, #6] + d3ea: 5c1b ldrb r3, [r3, r0] + d3ec: e7cb b.n d386 + d3ee: 2300 movs r3, #0 + d3f0: 2014 movs r0, #20 + for(i = 0; i < fdsc->cmap_num; i++) { + d3f2: 8a6a ldrh r2, [r5, #18] + d3f4: b299 uxth r1, r3 + d3f6: f3c2 0209 ubfx r2, r2, #0, #10 + d3fa: 428a cmp r2, r1 + d3fc: d8b4 bhi.n d368 + fdsc->last_letter = letter; + d3fe: 61ac str r4, [r5, #24] + fdsc->last_glyph_id = 0; + d400: 2400 movs r4, #0 + d402: 61ec str r4, [r5, #28] + return 0; + d404: e7ad b.n d362 + d406: bf00 nop + d408: 0000d349 .word 0x0000d349 + d40c: 0001028d .word 0x0001028d + +0000d410 : +{ + d410: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + d414: ed2d 8b02 vpush {d8} + if(unicode_letter == '\t') unicode_letter = ' '; + d418: 2909 cmp r1, #9 + uint32_t gid = get_glyph_dsc_id(font, unicode_letter); + d41a: 4b68 ldr r3, [pc, #416] ; (d5bc ) + lv_font_fmt_txt_dsc_t * fdsc = (lv_font_fmt_txt_dsc_t *) font->dsc; + d41c: 6905 ldr r5, [r0, #16] +{ + d41e: b08b sub sp, #44 ; 0x2c + uint32_t gid = get_glyph_dsc_id(font, unicode_letter); + d420: bf08 it eq + d422: 2120 moveq r1, #32 + d424: 4798 blx r3 + if(!gid) return NULL; + d426: 4607 mov r7, r0 + d428: b928 cbnz r0, d436 + d42a: 2000 movs r0, #0 +} + d42c: b00b add sp, #44 ; 0x2c + d42e: ecbd 8b02 vpop {d8} + d432: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + if(fdsc->bitmap_format == LV_FONT_FMT_TXT_PLAIN) { + d436: 7d2b ldrb r3, [r5, #20] + const lv_font_fmt_txt_glyph_dsc_t * gdsc = &fdsc->glyph_dsc[gid]; + d438: f8d5 9004 ldr.w r9, [r5, #4] + if(fdsc->bitmap_format == LV_FONT_FMT_TXT_PLAIN) { + d43c: 079b lsls r3, r3, #30 + const lv_font_fmt_txt_glyph_dsc_t * gdsc = &fdsc->glyph_dsc[gid]; + d43e: eb09 08c0 add.w r8, r9, r0, lsl #3 + if(fdsc->bitmap_format == LV_FONT_FMT_TXT_PLAIN) { + d442: d109 bne.n d458 + if(gdsc) return &fdsc->glyph_bitmap[gdsc->bitmap_index]; + d444: f1b8 0f00 cmp.w r8, #0 + d448: d0ef beq.n d42a + d44a: f859 3030 ldr.w r3, [r9, r0, lsl #3] + d44e: 6828 ldr r0, [r5, #0] + d450: f3c3 0313 ubfx r3, r3, #0, #20 + d454: 4418 add r0, r3 + d456: e7e9 b.n d42c + uint32_t gsize = gdsc->box_w * gdsc->box_h; + d458: f898 4004 ldrb.w r4, [r8, #4] + d45c: f898 3005 ldrb.w r3, [r8, #5] + d460: fb14 f403 smulbb r4, r4, r3 + if(gsize == 0) return NULL; + d464: 2c00 cmp r4, #0 + d466: d0e0 beq.n d42a + switch(fdsc->bpp) { + d468: 7ceb ldrb r3, [r5, #19] + d46a: f3c3 0383 ubfx r3, r3, #2, #4 + d46e: 3b01 subs r3, #1 + d470: 2b03 cmp r3, #3 + d472: d805 bhi.n d480 + d474: e8df f003 tbb [pc, r3] + d478: 53535002 .word 0x53535002 + buf_size = (gsize + 7) >> 3; + d47c: 3407 adds r4, #7 + d47e: 08e4 lsrs r4, r4, #3 + if(_lv_mem_get_size(decompr_buf) < buf_size) { + d480: 4e4f ldr r6, [pc, #316] ; (d5c0 ) + d482: 4b50 ldr r3, [pc, #320] ; (d5c4 ) + d484: 6930 ldr r0, [r6, #16] + d486: 4798 blx r3 + d488: 42a0 cmp r0, r4 + d48a: d34b bcc.n d524 + decompress(&fdsc->glyph_bitmap[gdsc->bitmap_index], decompr_buf, gdsc->box_w, gdsc->box_h, (uint8_t)fdsc->bpp); + d48c: f859 2037 ldr.w r2, [r9, r7, lsl #3] + d490: 682b ldr r3, [r5, #0] + d492: 7ced ldrb r5, [r5, #19] + d494: f898 7004 ldrb.w r7, [r8, #4] + d498: f3c2 0213 ubfx r2, r2, #0, #20 + d49c: 4413 add r3, r2 + d49e: 6932 ldr r2, [r6, #16] + rle_in = in; + d4a0: 6033 str r3, [r6, #0] + decompress(&fdsc->glyph_bitmap[gdsc->bitmap_index], decompr_buf, gdsc->box_w, gdsc->box_h, (uint8_t)fdsc->bpp); + d4a2: ee08 2a10 vmov s16, r2 + d4a6: f898 2005 ldrb.w r2, [r8, #5] + d4aa: 9207 str r2, [sp, #28] + d4ac: f3c5 0283 ubfx r2, r5, #2, #4 + d4b0: 2a03 cmp r2, #3 + rle_state = RLE_STATE_SINGLE; + d4b2: f04f 0b00 mov.w fp, #0 + decompress(&fdsc->glyph_bitmap[gdsc->bitmap_index], decompr_buf, gdsc->box_w, gdsc->box_h, (uint8_t)fdsc->bpp); + d4b6: 4611 mov r1, r2 + rle_bpp = bpp; + d4b8: 7132 strb r2, [r6, #4] + d4ba: bf08 it eq + d4bc: 2104 moveq r1, #4 + rle_state = RLE_STATE_SINGLE; + d4be: f886 b005 strb.w fp, [r6, #5] + rle_rdp = 0; + d4c2: f8c6 b008 str.w fp, [r6, #8] + rle_prev_v = 0; + d4c6: f886 b00c strb.w fp, [r6, #12] + rle_cnt = 0; + d4ca: f886 b00d strb.w fp, [r6, #13] + uint8_t * line_buf1 = _lv_mem_buf_get(w); + d4ce: 4638 mov r0, r7 + d4d0: 4e3d ldr r6, [pc, #244] ; (d5c8 ) + decompress(&fdsc->glyph_bitmap[gdsc->bitmap_index], decompr_buf, gdsc->box_w, gdsc->box_h, (uint8_t)fdsc->bpp); + d4d2: 9203 str r2, [sp, #12] + if(bpp == 3) wr_size = 4; + d4d4: 9104 str r1, [sp, #16] + uint8_t * line_buf1 = _lv_mem_buf_get(w); + d4d6: 47b0 blx r6 + d4d8: 4604 mov r4, r0 + uint8_t * line_buf2 = _lv_mem_buf_get(w); + d4da: 4638 mov r0, r7 + d4dc: 47b0 blx r6 + decompress_line(line_buf1, w); + d4de: 4b3b ldr r3, [pc, #236] ; (d5cc ) + uint8_t * line_buf2 = _lv_mem_buf_get(w); + d4e0: 4606 mov r6, r0 + decompress_line(line_buf1, w); + d4e2: 4639 mov r1, r7 + d4e4: 4620 mov r0, r4 + d4e6: 4798 blx r3 + decompress(&fdsc->glyph_bitmap[gdsc->bitmap_index], decompr_buf, gdsc->box_w, gdsc->box_h, (uint8_t)fdsc->bpp); + d4e8: 46b9 mov r9, r7 + d4ea: 46a0 mov r8, r4 + d4ec: eb07 0a04 add.w sl, r7, r4 + for(x = 0; x < w; x++) { + d4f0: 45d0 cmp r8, sl + d4f2: d131 bne.n d558 + d4f4: 9b04 ldr r3, [sp, #16] + d4f6: fb17 f303 smulbb r3, r7, r3 + d4fa: 9306 str r3, [sp, #24] + d4fc: 469a mov sl, r3 + for(y = 1; y < h; y++) { + d4fe: f04f 0801 mov.w r8, #1 + d502: 9b07 ldr r3, [sp, #28] + d504: 4543 cmp r3, r8 + d506: dc32 bgt.n d56e + _lv_mem_buf_release(line_buf1); + d508: 4620 mov r0, r4 + d50a: 4c31 ldr r4, [pc, #196] ; (d5d0 ) + d50c: 47a0 blx r4 + _lv_mem_buf_release(line_buf2); + d50e: 4630 mov r0, r6 + d510: 47a0 blx r4 + return decompr_buf; + d512: 4b2b ldr r3, [pc, #172] ; (d5c0 ) + d514: 6918 ldr r0, [r3, #16] + d516: e789 b.n d42c + buf_size = (gsize + 3) >> 2; + d518: 3403 adds r4, #3 + d51a: 08a4 lsrs r4, r4, #2 + break; + d51c: e7b0 b.n d480 + buf_size = (gsize + 1) >> 1; + d51e: 3401 adds r4, #1 + d520: 0864 lsrs r4, r4, #1 + break; + d522: e7ad b.n d480 + decompr_buf = lv_mem_realloc(decompr_buf, buf_size); + d524: 4621 mov r1, r4 + d526: 4b2b ldr r3, [pc, #172] ; (d5d4 ) + d528: 6930 ldr r0, [r6, #16] + d52a: 4798 blx r3 + LV_ASSERT_MEM(decompr_buf); + d52c: 4b2a ldr r3, [pc, #168] ; (d5d8 ) + decompr_buf = lv_mem_realloc(decompr_buf, buf_size); + d52e: 6130 str r0, [r6, #16] + LV_ASSERT_MEM(decompr_buf); + d530: 4798 blx r3 + d532: 4604 mov r4, r0 + d534: b960 cbnz r0, d550 + d536: 4b29 ldr r3, [pc, #164] ; (d5dc ) + d538: 4929 ldr r1, [pc, #164] ; (d5e0 ) + d53a: 9300 str r3, [sp, #0] + d53c: 2272 movs r2, #114 ; 0x72 + d53e: 2003 movs r0, #3 + d540: 4d28 ldr r5, [pc, #160] ; (d5e4 ) + d542: 47a8 blx r5 + d544: 6932 ldr r2, [r6, #16] + d546: 4828 ldr r0, [pc, #160] ; (d5e8 ) + d548: 4928 ldr r1, [pc, #160] ; (d5ec ) + d54a: 4623 mov r3, r4 + d54c: 4788 blx r1 + d54e: e7fe b.n d54e + if(decompr_buf == NULL) return NULL; + d550: 6933 ldr r3, [r6, #16] + d552: 2b00 cmp r3, #0 + d554: d19a bne.n d48c + d556: e768 b.n d42a + bits_write(out, wrp, line_buf1[x], bpp); + d558: 9b03 ldr r3, [sp, #12] + d55a: f818 2b01 ldrb.w r2, [r8], #1 + d55e: 4d24 ldr r5, [pc, #144] ; (d5f0 ) + d560: 4659 mov r1, fp + d562: ee18 0a10 vmov r0, s16 + d566: 47a8 blx r5 + wrp += wr_size; + d568: 9b04 ldr r3, [sp, #16] + d56a: 449b add fp, r3 + for(x = 0; x < w; x++) { + d56c: e7c0 b.n d4f0 + decompress_line(line_buf2, w); + d56e: 4b17 ldr r3, [pc, #92] ; (d5cc ) + d570: 4649 mov r1, r9 + d572: 4630 mov r0, r6 + d574: 4798 blx r3 + for(x = 0; x < w; x++) { + d576: 1e63 subs r3, r4, #1 + d578: 9305 str r3, [sp, #20] + d57a: 19f3 adds r3, r6, r7 + d57c: 46b3 mov fp, r6 + d57e: 9308 str r3, [sp, #32] + d580: 4651 mov r1, sl + d582: 9b08 ldr r3, [sp, #32] + d584: 459b cmp fp, r3 + d586: d106 bne.n d596 + d588: 9b06 ldr r3, [sp, #24] + d58a: f108 0801 add.w r8, r8, #1 + d58e: 449a add sl, r3 + for(y = 1; y < h; y++) { + d590: fa0f f888 sxth.w r8, r8 + d594: e7b5 b.n d502 + line_buf1[x] = line_buf2[x] ^ line_buf1[x]; + d596: 9805 ldr r0, [sp, #20] + d598: f81b 2b01 ldrb.w r2, [fp], #1 + d59c: f810 3f01 ldrb.w r3, [r0, #1]! + d5a0: 9005 str r0, [sp, #20] + d5a2: 405a eors r2, r3 + d5a4: 7002 strb r2, [r0, #0] + bits_write(out, wrp, line_buf1[x], bpp); + d5a6: 9b03 ldr r3, [sp, #12] + d5a8: 4d11 ldr r5, [pc, #68] ; (d5f0 ) + d5aa: 9109 str r1, [sp, #36] ; 0x24 + d5ac: ee18 0a10 vmov r0, s16 + d5b0: 47a8 blx r5 + wrp += wr_size; + d5b2: 9b04 ldr r3, [sp, #16] + d5b4: 9909 ldr r1, [sp, #36] ; 0x24 + d5b6: 4419 add r1, r3 + for(x = 0; x < w; x++) { + d5b8: e7e3 b.n d582 + d5ba: bf00 nop + d5bc: 0000d351 .word 0x0000d351 + d5c0: 200085d4 .word 0x200085d4 + d5c4: 0000eb4d .word 0x0000eb4d + d5c8: 0000eeb5 .word 0x0000eeb5 + d5cc: 0000d255 .word 0x0000d255 + d5d0: 0000eb69 .word 0x0000eb69 + d5d4: 0000ee15 .word 0x0000ee15 + d5d8: 000017e1 .word 0x000017e1 + d5dc: 000201db .word 0x000201db + d5e0: 0002019b .word 0x0002019b + d5e4: 0000e8e9 .word 0x0000e8e9 + d5e8: 0001edbe .word 0x0001edbe + d5ec: 000017e9 .word 0x000017e9 + d5f0: 0000d219 .word 0x0000d219 + +0000d5f4 : + if(unicode_letter == '\t') { + d5f4: 2a09 cmp r2, #9 +{ + d5f6: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} + uint32_t gid = get_glyph_dsc_id(font, unicode_letter); + d5fa: f8df a13c ldr.w sl, [pc, #316] ; d738 + lv_font_fmt_txt_dsc_t * fdsc = (lv_font_fmt_txt_dsc_t *) font->dsc; + d5fe: 6907 ldr r7, [r0, #16] +{ + d600: 460c mov r4, r1 + d602: 4611 mov r1, r2 + unicode_letter = ' '; + d604: bf08 it eq + d606: 2120 moveq r1, #32 +{ + d608: 4680 mov r8, r0 + d60a: 4699 mov r9, r3 + is_tab = true; + d60c: bf0c ite eq + d60e: 2601 moveq r6, #1 + bool is_tab = false; + d610: 2600 movne r6, #0 + uint32_t gid = get_glyph_dsc_id(font, unicode_letter); + d612: 47d0 blx sl + if(!gid) return false; + d614: 4605 mov r5, r0 + d616: 2800 cmp r0, #0 + d618: f000 8086 beq.w d728 + if(fdsc->kern_dsc) { + d61c: 68fb ldr r3, [r7, #12] + d61e: bb3b cbnz r3, d670 + int8_t kvalue = 0; + d620: 2300 movs r3, #0 + const lv_font_fmt_txt_glyph_dsc_t * gdsc = &fdsc->glyph_dsc[gid]; + d622: 6879 ldr r1, [r7, #4] + int32_t kv = ((int32_t)((int32_t)kvalue * fdsc->kern_scale) >> 4); + d624: 8a3a ldrh r2, [r7, #16] + const lv_font_fmt_txt_glyph_dsc_t * gdsc = &fdsc->glyph_dsc[gid]; + d626: eb01 01c5 add.w r1, r1, r5, lsl #3 + int32_t kv = ((int32_t)((int32_t)kvalue * fdsc->kern_scale) >> 4); + d62a: 4353 muls r3, r2 + uint32_t adv_w = gdsc->adv_w; + d62c: 884a ldrh r2, [r1, #2] + d62e: f3c2 100b ubfx r0, r2, #4, #12 + int32_t kv = ((int32_t)((int32_t)kvalue * fdsc->kern_scale) >> 4); + d632: 111b asrs r3, r3, #4 + uint32_t adv_w = gdsc->adv_w; + d634: 4602 mov r2, r0 + if(is_tab) adv_w *= 2; + d636: b10e cbz r6, d63c + d638: b202 sxth r2, r0 + d63a: 0052 lsls r2, r2, #1 + adv_w = (adv_w + (1 << 3)) >> 4; + d63c: 3308 adds r3, #8 + d63e: 4413 add r3, r2 + d640: 091b lsrs r3, r3, #4 + dsc_out->adv_w = adv_w; + d642: 8023 strh r3, [r4, #0] + dsc_out->box_h = gdsc->box_h; + d644: 794b ldrb r3, [r1, #5] + d646: 80a3 strh r3, [r4, #4] + dsc_out->box_w = gdsc->box_w; + d648: 790b ldrb r3, [r1, #4] + d64a: 8063 strh r3, [r4, #2] + dsc_out->ofs_x = gdsc->ofs_x; + d64c: f991 2006 ldrsb.w r2, [r1, #6] + d650: 80e2 strh r2, [r4, #6] + dsc_out->ofs_y = gdsc->ofs_y; + d652: f991 2007 ldrsb.w r2, [r1, #7] + d656: 8122 strh r2, [r4, #8] + dsc_out->bpp = (uint8_t)fdsc->bpp; + d658: 7cfa ldrb r2, [r7, #19] + d65a: f3c2 0283 ubfx r2, r2, #2, #4 + d65e: 72a2 strb r2, [r4, #10] + if(is_tab) dsc_out->box_w = dsc_out->box_w * 2; + d660: 2e00 cmp r6, #0 + d662: d063 beq.n d72c + d664: 005b lsls r3, r3, #1 + d666: 8063 strh r3, [r4, #2] +} + d668: 4630 mov r0, r6 + d66a: b004 add sp, #16 + d66c: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + uint32_t gid_next = get_glyph_dsc_id(font, unicode_letter_next); + d670: 4649 mov r1, r9 + d672: 4640 mov r0, r8 + d674: 47d0 blx sl + if(gid_next) { + d676: 2800 cmp r0, #0 + d678: d0d2 beq.n d620 + kvalue = get_kern_value(font, gid, gid_next); + d67a: f8d8 2010 ldr.w r2, [r8, #16] + const lv_font_fmt_txt_kern_pair_t * kdsc = fdsc->kern_dsc; + d67e: f8d2 800c ldr.w r8, [r2, #12] + if(fdsc->kern_classes == 0) { + d682: 7cd2 ldrb r2, [r2, #19] + d684: 0653 lsls r3, r2, #25 + d686: d43a bmi.n d6fe + if(kdsc->glyph_ids_size == 0) { + d688: f898 200b ldrb.w r2, [r8, #11] + d68c: f012 0203 ands.w r2, r2, #3 + d690: d11b bne.n d6ca + const uint8_t * g_ids = kdsc->glyph_ids; + d692: f8d8 9000 ldr.w r9, [r8] + uint8_t * kid_p = _lv_utils_bsearch(&g_id_both, g_ids, kdsc->pair_cnt, 2, kern_pair_8_compare); + d696: f8d8 2008 ldr.w r2, [r8, #8] + d69a: f8df a0a0 ldr.w sl, [pc, #160] ; d73c + uint16_t g_id_both = (gid_right << 8) + gid_left; /*Create one number from the ids*/ + d69e: eb05 2300 add.w r3, r5, r0, lsl #8 + d6a2: f8ad 300c strh.w r3, [sp, #12] + uint8_t * kid_p = _lv_utils_bsearch(&g_id_both, g_ids, kdsc->pair_cnt, 2, kern_pair_8_compare); + d6a6: 4b22 ldr r3, [pc, #136] ; (d730 ) + d6a8: 9300 str r3, [sp, #0] + d6aa: f022 427f bic.w r2, r2, #4278190080 ; 0xff000000 + d6ae: 2302 movs r3, #2 + d6b0: 4649 mov r1, r9 + d6b2: a803 add r0, sp, #12 + d6b4: 47d0 blx sl + if(kid_p) { + d6b6: 4603 mov r3, r0 + d6b8: 2800 cmp r0, #0 + d6ba: d0b2 beq.n d622 + lv_uintptr_t ofs = (lv_uintptr_t)(kid_p - g_ids); + d6bc: eba0 0309 sub.w r3, r0, r9 + ofs = ofs >> 1; /*ofs is for pair, divide by 2 to refer as a single value*/ + d6c0: 085b lsrs r3, r3, #1 + value = kdsc->values[ofs]; + d6c2: f8d8 2004 ldr.w r2, [r8, #4] + d6c6: 56d3 ldrsb r3, [r2, r3] + d6c8: e7ab b.n d622 + else if(kdsc->glyph_ids_size == 1) { + d6ca: 2a01 cmp r2, #1 + d6cc: d1a8 bne.n d620 + const uint16_t * g_ids = kdsc->glyph_ids; + d6ce: f8d8 9000 ldr.w r9, [r8] + uint8_t * kid_p = _lv_utils_bsearch(&g_id_both, g_ids, kdsc->pair_cnt, 4, kern_pair_16_compare); + d6d2: f8d8 2008 ldr.w r2, [r8, #8] + d6d6: 4b17 ldr r3, [pc, #92] ; (d734 ) + d6d8: 9300 str r3, [sp, #0] + lv_uintptr_t g_id_both = (uint32_t)((uint32_t)gid_right << 8) + gid_left; /*Create one number from the ids*/ + d6da: eb05 2000 add.w r0, r5, r0, lsl #8 + d6de: 9003 str r0, [sp, #12] + uint8_t * kid_p = _lv_utils_bsearch(&g_id_both, g_ids, kdsc->pair_cnt, 4, kern_pair_16_compare); + d6e0: 2304 movs r3, #4 + d6e2: f8df a058 ldr.w sl, [pc, #88] ; d73c + d6e6: f022 427f bic.w r2, r2, #4278190080 ; 0xff000000 + d6ea: 4649 mov r1, r9 + d6ec: a803 add r0, sp, #12 + d6ee: 47d0 blx sl + if(kid_p) { + d6f0: 4603 mov r3, r0 + d6f2: 2800 cmp r0, #0 + d6f4: d095 beq.n d622 + lv_uintptr_t ofs = (lv_uintptr_t)(kid_p - (const uint8_t *)g_ids); + d6f6: eba0 0309 sub.w r3, r0, r9 + ofs = ofs >> 4; /*ofs is 4 byte pairs, divide by 4 to refer as a single value*/ + d6fa: 091b lsrs r3, r3, #4 + d6fc: e7e1 b.n d6c2 + uint8_t left_class = kdsc->left_class_mapping[gid_left]; + d6fe: f8d8 2004 ldr.w r2, [r8, #4] + uint8_t right_class = kdsc->right_class_mapping[gid_right]; + d702: f8d8 1008 ldr.w r1, [r8, #8] + uint8_t left_class = kdsc->left_class_mapping[gid_left]; + d706: 5d52 ldrb r2, [r2, r5] + uint8_t right_class = kdsc->right_class_mapping[gid_right]; + d708: 5c09 ldrb r1, [r1, r0] + if(left_class > 0 && right_class > 0) { + d70a: 2a00 cmp r2, #0 + d70c: d088 beq.n d620 + d70e: 2900 cmp r1, #0 + d710: d086 beq.n d620 + value = kdsc->class_pair_values[(left_class - 1) * kdsc->right_class_cnt + (right_class - 1)]; + d712: f8d8 3000 ldr.w r3, [r8] + d716: f898 000d ldrb.w r0, [r8, #13] + d71a: 3a01 subs r2, #1 + d71c: 440b add r3, r1 + d71e: fb00 3302 mla r3, r0, r2, r3 + d722: f913 3c01 ldrsb.w r3, [r3, #-1] + d726: e77c b.n d622 + if(!gid) return false; + d728: 4606 mov r6, r0 + d72a: e79d b.n d668 + return true; + d72c: 2601 movs r6, #1 + d72e: e79b b.n d668 + d730: 0000d191 .word 0x0000d191 + d734: 0000d1a3 .word 0x0000d1a3 + d738: 0000d351 .word 0x0000d351 + d73c: 0001028d .word 0x0001028d + +0000d740 <_lv_font_clean_up_fmt_txt>: +{ + d740: b510 push {r4, lr} + if(decompr_buf) { + d742: 4c04 ldr r4, [pc, #16] ; (d754 <_lv_font_clean_up_fmt_txt+0x14>) + d744: 6920 ldr r0, [r4, #16] + d746: b118 cbz r0, d750 <_lv_font_clean_up_fmt_txt+0x10> + lv_mem_free(decompr_buf); + d748: 4b03 ldr r3, [pc, #12] ; (d758 <_lv_font_clean_up_fmt_txt+0x18>) + d74a: 4798 blx r3 + decompr_buf = NULL; + d74c: 2300 movs r3, #0 + d74e: 6123 str r3, [r4, #16] +} + d750: bd10 pop {r4, pc} + d752: bf00 nop + d754: 200085d4 .word 0x200085d4 + d758: 0000eae5 .word 0x0000eae5 + +0000d75c : + * It is used to surly have known values in the fields ant not memory junk. + * After it you can set the fields. + * @param driver pointer to driver variable to initialize + */ +void lv_disp_drv_init(lv_disp_drv_t * driver) +{ + d75c: b510 push {r4, lr} + _lv_memset_00(driver, sizeof(lv_disp_drv_t)); + d75e: 4b0d ldr r3, [pc, #52] ; (d794 ) + d760: 212c movs r1, #44 ; 0x2c +{ + d762: 4604 mov r4, r0 + _lv_memset_00(driver, sizeof(lv_disp_drv_t)); + d764: 4798 blx r3 + + driver->flush_cb = NULL; + driver->hor_res = LV_HOR_RES_MAX; + d766: 4b0c ldr r3, [pc, #48] ; (d798 ) + driver->flush_cb = NULL; + d768: 2200 movs r2, #0 + driver->ver_res = LV_VER_RES_MAX; + driver->buffer = NULL; + d76a: e9c4 3200 strd r3, r2, [r4] + driver->rotated = 0; + driver->color_chroma_key = LV_COLOR_TRANSP; + driver->dpi = LV_DPI; + +#if LV_ANTIALIAS + driver->antialiasing = true; + d76e: 8923 ldrh r3, [r4, #8] + driver->flush_cb = NULL; + d770: 60e2 str r2, [r4, #12] + driver->antialiasing = true; + d772: f423 637f bic.w r3, r3, #4080 ; 0xff0 + d776: f023 030f bic.w r3, r3, #15 + d77a: f443 7302 orr.w r3, r3, #520 ; 0x208 + d77e: f043 0301 orr.w r3, r3, #1 + d782: 8123 strh r3, [r4, #8] + driver->color_chroma_key = LV_COLOR_TRANSP; + d784: f44f 63fc mov.w r3, #2016 ; 0x7e0 + driver->screen_transp = 1; +#endif + +#if LV_USE_GPU + driver->gpu_blend_cb = NULL; + driver->gpu_fill_cb = NULL; + d788: e9c4 2208 strd r2, r2, [r4, #32] + driver->color_chroma_key = LV_COLOR_TRANSP; + d78c: 8523 strh r3, [r4, #40] ; 0x28 + +#if LV_USE_USER_DATA + driver->user_data = NULL; +#endif + + driver->set_px_cb = NULL; + d78e: 6162 str r2, [r4, #20] +} + d790: bd10 pop {r4, pc} + d792: bf00 nop + d794: 0000f019 .word 0x0000f019 + d798: 011001e0 .word 0x011001e0 + +0000d79c : + * It lets LVGL to render next frame into the other buffer while previous is being + * sent. Set to `NULL` if unused. + * @param size_in_px_cnt size of the `buf1` and `buf2` in pixel count. + */ +void lv_disp_buf_init(lv_disp_buf_t * disp_buf, void * buf1, void * buf2, uint32_t size_in_px_cnt) +{ + d79c: b5f8 push {r3, r4, r5, r6, r7, lr} + d79e: 4604 mov r4, r0 + d7a0: 460d mov r5, r1 + d7a2: 4617 mov r7, r2 + d7a4: 461e mov r6, r3 + _lv_memset_00(disp_buf, sizeof(lv_disp_buf_t)); + d7a6: 2124 movs r1, #36 ; 0x24 + d7a8: 4b03 ldr r3, [pc, #12] ; (d7b8 ) + d7aa: 4798 blx r3 + + disp_buf->buf1 = buf1; + disp_buf->buf2 = buf2; + d7ac: e9c4 5700 strd r5, r7, [r4] + disp_buf->buf_act = disp_buf->buf1; + disp_buf->size = size_in_px_cnt; + d7b0: e9c4 5602 strd r5, r6, [r4, #8] +} + d7b4: bdf8 pop {r3, r4, r5, r6, r7, pc} + d7b6: bf00 nop + d7b8: 0000f019 .word 0x0000f019 + +0000d7bc : + * Automatically set the first display as active. + * @param driver pointer to an initialized 'lv_disp_drv_t' variable (can be local variable) + * @return pointer to the new display or NULL on error + */ +lv_disp_t * lv_disp_drv_register(lv_disp_drv_t * driver) +{ + d7bc: e92d 41f3 stmdb sp!, {r0, r1, r4, r5, r6, r7, r8, lr} + lv_disp_t * disp = _lv_ll_ins_head(&LV_GC_ROOT(_lv_disp_ll)); + d7c0: 4b3b ldr r3, [pc, #236] ; (d8b0 ) + d7c2: 4e3c ldr r6, [pc, #240] ; (d8b4 ) +{ + d7c4: 4605 mov r5, r0 + lv_disp_t * disp = _lv_ll_ins_head(&LV_GC_ROOT(_lv_disp_ll)); + d7c6: 483c ldr r0, [pc, #240] ; (d8b8 ) + d7c8: 4798 blx r3 + if(!disp) { + d7ca: 4604 mov r4, r0 + d7cc: b998 cbnz r0, d7f6 + LV_ASSERT_MEM(disp); + d7ce: 47b0 blx r6 + d7d0: b120 cbz r0, d7dc + return NULL; + d7d2: 2400 movs r4, #0 + disp_def = disp_def_tmp; /*Revert the default display*/ + + lv_task_ready(disp->refr_task); /*Be sure the screen will be refreshed immediately on start up*/ + + return disp; +} + d7d4: 4620 mov r0, r4 + d7d6: b002 add sp, #8 + d7d8: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + LV_ASSERT_MEM(disp); + d7dc: 4b37 ldr r3, [pc, #220] ; (d8bc ) + d7de: 4938 ldr r1, [pc, #224] ; (d8c0 ) + d7e0: 9300 str r3, [sp, #0] + d7e2: 227c movs r2, #124 ; 0x7c + d7e4: 2003 movs r0, #3 + d7e6: 4c37 ldr r4, [pc, #220] ; (d8c4 ) + d7e8: 47a0 blx r4 + d7ea: 4837 ldr r0, [pc, #220] ; (d8c8 ) + d7ec: 4937 ldr r1, [pc, #220] ; (d8cc ) + d7ee: 2200 movs r2, #0 + d7f0: 2300 movs r3, #0 + d7f2: 4788 blx r1 + d7f4: e7fe b.n d7f4 + _lv_memset_00(disp, sizeof(lv_disp_t)); + d7f6: 4b36 ldr r3, [pc, #216] ; (d8d0 ) + d7f8: f44f 71b8 mov.w r1, #368 ; 0x170 + d7fc: 4798 blx r3 + _lv_memcpy(&disp->driver, driver, sizeof(lv_disp_drv_t)); + d7fe: 4629 mov r1, r5 + d800: 4b34 ldr r3, [pc, #208] ; (d8d4 ) + if(disp_def == NULL) disp_def = disp; + d802: 4d35 ldr r5, [pc, #212] ; (d8d8 ) + _lv_memcpy(&disp->driver, driver, sizeof(lv_disp_drv_t)); + d804: 222c movs r2, #44 ; 0x2c + d806: 4620 mov r0, r4 + d808: 4798 blx r3 + _lv_ll_init(&disp->scr_ll, sizeof(lv_obj_t)); + d80a: 4b34 ldr r3, [pc, #208] ; (d8dc ) + d80c: 214c movs r1, #76 ; 0x4c + d80e: f104 0030 add.w r0, r4, #48 ; 0x30 + d812: 4798 blx r3 + disp->last_activity_time = 0; + d814: 2300 movs r3, #0 + d816: f8c4 316c str.w r3, [r4, #364] ; 0x16c + if(disp_def == NULL) disp_def = disp; + d81a: 682b ldr r3, [r5, #0] + d81c: b903 cbnz r3, d820 + d81e: 602c str r4, [r5, #0] + disp->refr_task = lv_task_create(_lv_disp_refr_task, LV_DISP_DEF_REFR_PERIOD, LV_REFR_TASK_PRIO, disp); + d820: 4623 mov r3, r4 + d822: 2203 movs r2, #3 + d824: 211e movs r1, #30 + d826: 482e ldr r0, [pc, #184] ; (d8e0 ) + d828: f8df 80cc ldr.w r8, [pc, #204] ; d8f8 + lv_disp_t * disp_def_tmp = disp_def; + d82c: 682f ldr r7, [r5, #0] + disp_def = disp; /*Temporarily change the default screen to create the default screens on the + d82e: 602c str r4, [r5, #0] + disp->refr_task = lv_task_create(_lv_disp_refr_task, LV_DISP_DEF_REFR_PERIOD, LV_REFR_TASK_PRIO, disp); + d830: 47c0 blx r8 + d832: 62e0 str r0, [r4, #44] ; 0x2c + LV_ASSERT_MEM(disp->refr_task); + d834: 47b0 blx r6 + d836: 4606 mov r6, r0 + d838: b960 cbnz r0, d854 + d83a: 4b20 ldr r3, [pc, #128] ; (d8bc ) + d83c: 4920 ldr r1, [pc, #128] ; (d8c0 ) + d83e: 9300 str r3, [sp, #0] + d840: 228d movs r2, #141 ; 0x8d + d842: 2003 movs r0, #3 + d844: 4d1f ldr r5, [pc, #124] ; (d8c4 ) + d846: 47a8 blx r5 + d848: 6ae2 ldr r2, [r4, #44] ; 0x2c + d84a: 481f ldr r0, [pc, #124] ; (d8c8 ) + d84c: 491f ldr r1, [pc, #124] ; (d8cc ) + d84e: 4633 mov r3, r6 + d850: 4788 blx r1 + d852: e7fe b.n d852 + if(disp->refr_task == NULL) return NULL; + d854: 6ae3 ldr r3, [r4, #44] ; 0x2c + d856: 2b00 cmp r3, #0 + d858: d0bb beq.n d7d2 + disp->inv_p = 0; + d85a: f8b4 3168 ldrh.w r3, [r4, #360] ; 0x168 + disp->act_scr = lv_obj_create(NULL, NULL); /*Create a default screen on the display*/ + d85e: 4e21 ldr r6, [pc, #132] ; (d8e4 ) + disp->inv_p = 0; + d860: f36f 0309 bfc r3, #0, #10 + disp->last_activity_time = 0; + d864: 2100 movs r1, #0 + disp->inv_p = 0; + d866: f8a4 3168 strh.w r3, [r4, #360] ; 0x168 + disp->last_activity_time = 0; + d86a: f8c4 116c str.w r1, [r4, #364] ; 0x16c + disp->act_scr = lv_obj_create(NULL, NULL); /*Create a default screen on the display*/ + d86e: 4608 mov r0, r1 + d870: 47b0 blx r6 + disp->top_layer = lv_obj_create(NULL, NULL); /*Create top layer on the display*/ + d872: 2100 movs r1, #0 + disp->act_scr = lv_obj_create(NULL, NULL); /*Create a default screen on the display*/ + d874: 63e0 str r0, [r4, #60] ; 0x3c + disp->top_layer = lv_obj_create(NULL, NULL); /*Create top layer on the display*/ + d876: 4608 mov r0, r1 + d878: 47b0 blx r6 + disp->sys_layer = lv_obj_create(NULL, NULL); /*Create sys layer on the display*/ + d87a: 2100 movs r1, #0 + disp->top_layer = lv_obj_create(NULL, NULL); /*Create top layer on the display*/ + d87c: 6420 str r0, [r4, #64] ; 0x40 + disp->sys_layer = lv_obj_create(NULL, NULL); /*Create sys layer on the display*/ + d87e: 4608 mov r0, r1 + d880: 47b0 blx r6 + lv_obj_reset_style_list(disp->top_layer, LV_OBJ_PART_MAIN); + d882: 4e19 ldr r6, [pc, #100] ; (d8e8 ) + disp->sys_layer = lv_obj_create(NULL, NULL); /*Create sys layer on the display*/ + d884: 6460 str r0, [r4, #68] ; 0x44 + lv_obj_reset_style_list(disp->top_layer, LV_OBJ_PART_MAIN); + d886: 2100 movs r1, #0 + d888: 6c20 ldr r0, [r4, #64] ; 0x40 + d88a: 47b0 blx r6 + lv_obj_reset_style_list(disp->sys_layer, LV_OBJ_PART_MAIN); + d88c: 6c60 ldr r0, [r4, #68] ; 0x44 + d88e: 2100 movs r1, #0 + d890: 47b0 blx r6 + lv_obj_set_click(disp->top_layer, false); + d892: 6c20 ldr r0, [r4, #64] ; 0x40 + d894: 4e15 ldr r6, [pc, #84] ; (d8ec ) + d896: 2100 movs r1, #0 + d898: 47b0 blx r6 + lv_obj_set_click(disp->sys_layer, false); + d89a: 6c60 ldr r0, [r4, #68] ; 0x44 + d89c: 2100 movs r1, #0 + d89e: 47b0 blx r6 + lv_obj_invalidate(disp->act_scr); + d8a0: 6be0 ldr r0, [r4, #60] ; 0x3c + d8a2: 4b13 ldr r3, [pc, #76] ; (d8f0 ) + d8a4: 4798 blx r3 + lv_task_ready(disp->refr_task); /*Be sure the screen will be refreshed immediately on start up*/ + d8a6: 6ae0 ldr r0, [r4, #44] ; 0x2c + d8a8: 4b12 ldr r3, [pc, #72] ; (d8f4 ) + disp_def = disp_def_tmp; /*Revert the default display*/ + d8aa: 602f str r7, [r5, #0] + lv_task_ready(disp->refr_task); /*Be sure the screen will be refreshed immediately on start up*/ + d8ac: 4798 blx r3 + return disp; + d8ae: e791 b.n d7d4 + d8b0: 0000e619 .word 0x0000e619 + d8b4: 000017e1 .word 0x000017e1 + d8b8: 2000860c .word 0x2000860c + d8bc: 00023ecf .word 0x00023ecf + d8c0: 00023e9c .word 0x00023e9c + d8c4: 0000e8e9 .word 0x0000e8e9 + d8c8: 0001edbe .word 0x0001edbe + d8cc: 000017e9 .word 0x000017e9 + d8d0: 0000f019 .word 0x0000f019 + d8d4: 0000ec31 .word 0x0000ec31 + d8d8: 200085e8 .word 0x200085e8 + d8dc: 0000e605 .word 0x0000e605 + d8e0: 00004ff5 .word 0x00004ff5 + d8e4: 000030e5 .word 0x000030e5 + d8e8: 00002e95 .word 0x00002e95 + d8ec: 00001e5d .word 0x00001e5d + d8f0: 00002785 .word 0x00002785 + d8f4: 0000fc41 .word 0x0000fc41 + d8f8: 0000fbd1 .word 0x0000fbd1 + +0000d8fc : + * @return pointer to the default display + */ +lv_disp_t * lv_disp_get_default(void) +{ + return disp_def; +} + d8fc: 4b01 ldr r3, [pc, #4] ; (d904 ) + d8fe: 6818 ldr r0, [r3, #0] + d900: 4770 bx lr + d902: bf00 nop + d904: 200085e8 .word 0x200085e8 + +0000d908 : + * @param disp pointer to a display (NULL to use the default display) + * @return the horizontal resolution of the display + */ +lv_coord_t lv_disp_get_hor_res(lv_disp_t * disp) +{ + if(disp == NULL) disp = lv_disp_get_default(); + d908: b910 cbnz r0, d910 + return disp_def; + d90a: 4b07 ldr r3, [pc, #28] ; (d928 ) + d90c: 6818 ldr r0, [r3, #0] + + if(disp == NULL) + d90e: b138 cbz r0, d920 + return LV_HOR_RES_MAX; + else + return disp->driver.rotated == 0 ? disp->driver.hor_res : disp->driver.ver_res; + d910: 7a03 ldrb r3, [r0, #8] + d912: 079b lsls r3, r3, #30 + d914: bf54 ite pl + d916: f9b0 0000 ldrshpl.w r0, [r0] + d91a: f9b0 0002 ldrshmi.w r0, [r0, #2] + d91e: 4770 bx lr + return LV_HOR_RES_MAX; + d920: f44f 70f0 mov.w r0, #480 ; 0x1e0 +} + d924: 4770 bx lr + d926: bf00 nop + d928: 200085e8 .word 0x200085e8 + +0000d92c : + * @param disp pointer to a display (NULL to use the default display) + * @return the vertical resolution of the display + */ +lv_coord_t lv_disp_get_ver_res(lv_disp_t * disp) +{ + if(disp == NULL) disp = lv_disp_get_default(); + d92c: b910 cbnz r0, d934 + return disp_def; + d92e: 4b07 ldr r3, [pc, #28] ; (d94c ) + d930: 6818 ldr r0, [r3, #0] + + if(disp == NULL) + d932: b138 cbz r0, d944 + return LV_VER_RES_MAX; + else + return disp->driver.rotated == 0 ? disp->driver.ver_res : disp->driver.hor_res; + d934: 7a03 ldrb r3, [r0, #8] + d936: 079b lsls r3, r3, #30 + d938: bf54 ite pl + d93a: f9b0 0002 ldrshpl.w r0, [r0, #2] + d93e: f9b0 0000 ldrshmi.w r0, [r0] + d942: 4770 bx lr + return LV_VER_RES_MAX; + d944: f44f 7088 mov.w r0, #272 ; 0x110 +} + d948: 4770 bx lr + d94a: bf00 nop + d94c: 200085e8 .word 0x200085e8 + +0000d950 : + * @param disp pointer to a display (NULL to use the default display) + * @return dpi of the display + */ +lv_coord_t lv_disp_get_dpi(lv_disp_t * disp) +{ + if(disp == NULL) disp = lv_disp_get_default(); + d950: b910 cbnz r0, d958 + return disp_def; + d952: 4b04 ldr r3, [pc, #16] ; (d964 ) + d954: 6818 ldr r0, [r3, #0] + if(disp == NULL) return LV_DPI; /*Do not return 0 because it might be a divider*/ + d956: b118 cbz r0, d960 + return disp->driver.dpi; + d958: 8900 ldrh r0, [r0, #8] + d95a: f3c0 0089 ubfx r0, r0, #2, #10 + d95e: 4770 bx lr + if(disp == NULL) return LV_DPI; /*Do not return 0 because it might be a divider*/ + d960: 2082 movs r0, #130 ; 0x82 +} + d962: 4770 bx lr + d964: 200085e8 .word 0x200085e8 + +0000d968 : + * Get the size category of the display based on it's hor. res. and dpi. + * @param disp pointer to a display (NULL to use the default display) + * @return LV_DISP_SIZE_SMALL/MEDIUM/LARGE/EXTRA_LARGE + */ +lv_disp_size_t lv_disp_get_size_category(lv_disp_t * disp) +{ + d968: b508 push {r3, lr} + if(disp == NULL) disp = lv_disp_get_default(); + d96a: 4601 mov r1, r0 + d96c: b910 cbnz r0, d974 + return disp_def; + d96e: 4b0f ldr r3, [pc, #60] ; (d9ac ) + d970: 6819 ldr r1, [r3, #0] + + uint32_t w; + if(disp == NULL) w = LV_HOR_RES_MAX; + d972: b199 cbz r1, d99c + else w = lv_disp_get_hor_res(disp); + d974: 4b0e ldr r3, [pc, #56] ; (d9b0 ) + d976: 4608 mov r0, r1 + d978: 4798 blx r3 + d97a: 4602 mov r2, r0 + + uint32_t dpi = lv_disp_get_dpi(disp); + d97c: 4b0d ldr r3, [pc, #52] ; (d9b4 ) + d97e: 4608 mov r0, r1 + d980: 4798 blx r3 + + w = w * 10 / dpi; + d982: 230a movs r3, #10 + d984: 435a muls r2, r3 + d986: fbb2 f0f0 udiv r0, r2, r0 + + if(w < LV_DISP_SMALL_LIMIT) return LV_DISP_SIZE_SMALL; + d98a: 281d cmp r0, #29 + d98c: d909 bls.n d9a2 + if(w < LV_DISP_MEDIUM_LIMIT) return LV_DISP_SIZE_MEDIUM; + d98e: 2831 cmp r0, #49 ; 0x31 + d990: d909 bls.n d9a6 + if(w < LV_DISP_LARGE_LIMIT) return LV_DISP_SIZE_LARGE; + else return LV_DISP_SIZE_EXTRA_LARGE; + d992: 2846 cmp r0, #70 ; 0x46 + d994: bf34 ite cc + d996: 2002 movcc r0, #2 + d998: 2003 movcs r0, #3 +} + d99a: bd08 pop {r3, pc} + if(disp == NULL) w = LV_HOR_RES_MAX; + d99c: f44f 72f0 mov.w r2, #480 ; 0x1e0 + d9a0: e7ec b.n d97c + if(w < LV_DISP_SMALL_LIMIT) return LV_DISP_SIZE_SMALL; + d9a2: 2000 movs r0, #0 + d9a4: e7f9 b.n d99a + if(w < LV_DISP_MEDIUM_LIMIT) return LV_DISP_SIZE_MEDIUM; + d9a6: 2001 movs r0, #1 + d9a8: e7f7 b.n d99a + d9aa: bf00 nop + d9ac: 200085e8 .word 0x200085e8 + d9b0: 0000d909 .word 0x0000d909 + d9b4: 0000d951 .word 0x0000d951 + +0000d9b8 : + if(disp_drv->screen_transp) { + _lv_memset_00(disp_drv->buffer->buf_act, disp_drv->buffer->size * sizeof(lv_color32_t)); + } +#endif + + disp_drv->buffer->flushing = 0; + d9b8: 6843 ldr r3, [r0, #4] + d9ba: 2200 movs r2, #0 + d9bc: 619a str r2, [r3, #24] + disp_drv->buffer->flushing_last = 0; + d9be: 61da str r2, [r3, #28] +} + d9c0: 4770 bx lr + ... + +0000d9c4 : + * @param disp pointer to the current display. NULL to initialize. + * @return the next display or NULL if no more. Give the first display when the parameter is NULL + */ +lv_disp_t * lv_disp_get_next(lv_disp_t * disp) +{ + if(disp == NULL) + d9c4: 4601 mov r1, r0 + return _lv_ll_get_head(&LV_GC_ROOT(_lv_disp_ll)); + d9c6: 4803 ldr r0, [pc, #12] ; (d9d4 ) + if(disp == NULL) + d9c8: b909 cbnz r1, d9ce + return _lv_ll_get_head(&LV_GC_ROOT(_lv_disp_ll)); + d9ca: 4b03 ldr r3, [pc, #12] ; (d9d8 ) + d9cc: 4718 bx r3 + else + return _lv_ll_get_next(&LV_GC_ROOT(_lv_disp_ll), disp); + d9ce: 4b03 ldr r3, [pc, #12] ; (d9dc ) + d9d0: 4718 bx r3 + d9d2: bf00 nop + d9d4: 2000860c .word 0x2000860c + d9d8: 0000e6a9 .word 0x0000e6a9 + d9dc: 0000e6b5 .word 0x0000e6b5 + +0000d9e0 : + * @return pointer to the internal buffers + */ +lv_disp_buf_t * lv_disp_get_buf(lv_disp_t * disp) +{ + return disp->driver.buffer; +} + d9e0: 6840 ldr r0, [r0, #4] + d9e2: 4770 bx lr + +0000d9e4 : + * @param disp pointer to to display to check + * @return true: double buffered; false: not double buffered + */ +bool lv_disp_is_double_buf(lv_disp_t * disp) +{ + if(disp->driver.buffer->buf1 && disp->driver.buffer->buf2) + d9e4: 6843 ldr r3, [r0, #4] + d9e6: 6818 ldr r0, [r3, #0] + d9e8: b118 cbz r0, d9f2 + d9ea: 6858 ldr r0, [r3, #4] + d9ec: 3800 subs r0, #0 + d9ee: bf18 it ne + d9f0: 2001 movne r0, #1 + return true; + else + return false; +} + d9f2: 4770 bx lr + +0000d9f4 : + * `size` is screen sized) + * @param disp pointer to to display to check + * @return true: double buffered; false: not double buffered + */ +bool lv_disp_is_true_double_buf(lv_disp_t * disp) +{ + d9f4: b508 push {r3, lr} + uint32_t scr_size = disp->driver.hor_res * disp->driver.ver_res; + + if(lv_disp_is_double_buf(disp) && disp->driver.buffer->size == scr_size) { + d9f6: 4b07 ldr r3, [pc, #28] ; (da14 ) +{ + d9f8: 4602 mov r2, r0 + if(lv_disp_is_double_buf(disp) && disp->driver.buffer->size == scr_size) { + d9fa: 4798 blx r3 + d9fc: b140 cbz r0, da10 + uint32_t scr_size = disp->driver.hor_res * disp->driver.ver_res; + d9fe: 8813 ldrh r3, [r2, #0] + da00: 8851 ldrh r1, [r2, #2] + if(lv_disp_is_double_buf(disp) && disp->driver.buffer->size == scr_size) { + da02: 6852 ldr r2, [r2, #4] + da04: 68d0 ldr r0, [r2, #12] + uint32_t scr_size = disp->driver.hor_res * disp->driver.ver_res; + da06: fb13 f301 smulbb r3, r3, r1 + if(lv_disp_is_double_buf(disp) && disp->driver.buffer->size == scr_size) { + da0a: 1a1b subs r3, r3, r0 + da0c: 4258 negs r0, r3 + da0e: 4158 adcs r0, r3 + return true; + } + else { + return false; + } +} + da10: bd08 pop {r3, pc} + da12: bf00 nop + da14: 0000d9e5 .word 0x0000d9e5 + +0000da18 : + * @return the next input devise or NULL if no more. Give the first input device when the parameter + * is NULL + */ +lv_indev_t * lv_indev_get_next(lv_indev_t * indev) +{ + if(indev == NULL) + da18: 4601 mov r1, r0 + return _lv_ll_get_head(&LV_GC_ROOT(_lv_indev_ll)); + da1a: 4803 ldr r0, [pc, #12] ; (da28 ) + if(indev == NULL) + da1c: b909 cbnz r1, da22 + return _lv_ll_get_head(&LV_GC_ROOT(_lv_indev_ll)); + da1e: 4b03 ldr r3, [pc, #12] ; (da2c ) + da20: 4718 bx r3 + else + return _lv_ll_get_next(&LV_GC_ROOT(_lv_indev_ll), indev); + da22: 4b03 ldr r3, [pc, #12] ; (da30 ) + da24: 4718 bx r3 + da26: bf00 nop + da28: 20008618 .word 0x20008618 + da2c: 0000e6a9 .word 0x0000e6a9 + da30: 0000e6b5 .word 0x0000e6b5 + +0000da34 : + * You have to call this function periodically + * @param tick_period the call period of this function in milliseconds + */ +LV_ATTRIBUTE_TICK_INC void lv_tick_inc(uint32_t tick_period) +{ + tick_irq_flag = 0; + da34: 4b03 ldr r3, [pc, #12] ; (da44 ) + da36: 2200 movs r2, #0 + da38: 701a strb r2, [r3, #0] + sys_time += tick_period; + da3a: 685a ldr r2, [r3, #4] + da3c: 4410 add r0, r2 + da3e: 6058 str r0, [r3, #4] +} + da40: 4770 bx lr + da42: bf00 nop + da44: 200085ec .word 0x200085ec + +0000da48 : +{ +#if LV_TICK_CUSTOM == 0 + uint32_t result; + do { + tick_irq_flag = 1; + result = sys_time; + da48: 4b03 ldr r3, [pc, #12] ; (da58 ) + da4a: 6858 ldr r0, [r3, #4] + tick_irq_flag = 1; + da4c: 2101 movs r1, #1 + da4e: 7019 strb r1, [r3, #0] + } while(!tick_irq_flag); /*'lv_tick_inc()' clears this flag which can be in an interrupt. + da50: 781a ldrb r2, [r3, #0] + da52: 2a00 cmp r2, #0 + da54: d0fb beq.n da4e + + return result; +#else + return LV_TICK_CUSTOM_SYS_TIME_EXPR; +#endif +} + da56: 4770 bx lr + da58: 200085ec .word 0x200085ec + +0000da5c : + * Get the elapsed milliseconds since a previous time stamp + * @param prev_tick a previous time stamp (return value of systick_get() ) + * @return the elapsed milliseconds since 'prev_tick' + */ +uint32_t lv_tick_elaps(uint32_t prev_tick) +{ + da5c: b510 push {r4, lr} + uint32_t act_time = lv_tick_get(); + da5e: 4b02 ldr r3, [pc, #8] ; (da68 ) +{ + da60: 4604 mov r4, r0 + uint32_t act_time = lv_tick_get(); + da62: 4798 blx r3 + prev_tick = UINT32_MAX - prev_tick + 1; + prev_tick += act_time; + } + + return prev_tick; +} + da64: 1b00 subs r0, r0, r4 + da66: bd10 pop {r4, pc} + da68: 0000da49 .word 0x0000da49 + +0000da6c : +{ + LV_UNUSED(path); + + /*Calculate the current step*/ + uint32_t step; + if(a->time == a->act_time) { + da6c: e9d1 2308 ldrd r2, r3, [r1, #32] + da70: 429a cmp r2, r3 + step = LV_ANIM_RESOLUTION; /*Use the last value if the time fully elapsed*/ + } + else { + step = ((int32_t)a->act_time * LV_ANIM_RESOLUTION) / a->time; + da72: bf1c itt ne + da74: 029b lslne r3, r3, #10 + da76: fb93 f3f2 sdivne r3, r3, r2 + } + + /* Get the new value which will be proportional to `step` + * and the `start` and `end` values*/ + int32_t new_value; + new_value = (int32_t)step * (a->end - a->start); + da7a: e9d1 0206 ldrd r0, r2, [r1, #24] + step = LV_ANIM_RESOLUTION; /*Use the last value if the time fully elapsed*/ + da7e: bf08 it eq + da80: f44f 6380 moveq.w r3, #1024 ; 0x400 + new_value = (int32_t)step * (a->end - a->start); + da84: 1a12 subs r2, r2, r0 + da86: 4353 muls r3, r2 + new_value = new_value >> LV_ANIM_RES_SHIFT; + new_value += a->start; + da88: eb00 20a3 add.w r0, r0, r3, asr #10 + + return (lv_anim_value_t)new_value; +} + da8c: b200 sxth r0, r0 + da8e: 4770 bx lr + +0000da90 : + } + + return anim_list_changed; +} +static void anim_mark_list_change(void) +{ + da90: b510 push {r4, lr} + anim_list_changed = true; + da92: 4c07 ldr r4, [pc, #28] ; (dab0 ) + if(_lv_ll_get_head(&LV_GC_ROOT(_lv_anim_ll)) == NULL) + da94: 4807 ldr r0, [pc, #28] ; (dab4 ) + anim_list_changed = true; + da96: 2301 movs r3, #1 + da98: 7023 strb r3, [r4, #0] + if(_lv_ll_get_head(&LV_GC_ROOT(_lv_anim_ll)) == NULL) + da9a: 4b07 ldr r3, [pc, #28] ; (dab8 ) + da9c: 4798 blx r3 + da9e: 4b07 ldr r3, [pc, #28] ; (dabc ) + daa0: 4601 mov r1, r0 + daa2: b918 cbnz r0, daac + lv_task_set_prio(_lv_anim_task, LV_TASK_PRIO_OFF); + else + lv_task_set_prio(_lv_anim_task, LV_ANIM_TASK_PRIO); + daa4: 6860 ldr r0, [r4, #4] +} + daa6: e8bd 4010 ldmia.w sp!, {r4, lr} + lv_task_set_prio(_lv_anim_task, LV_ANIM_TASK_PRIO); + daaa: 4718 bx r3 + daac: 2104 movs r1, #4 + daae: e7f9 b.n daa4 + dab0: 200085f4 .word 0x200085f4 + dab4: 2000863c .word 0x2000863c + dab8: 0000e6a9 .word 0x0000e6a9 + dabc: 0000fb6d .word 0x0000fb6d + +0000dac0 : +{ + dac0: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + _LV_LL_READ(LV_GC_ROOT(_lv_anim_ll), a) { + dac4: 484f ldr r0, [pc, #316] ; (dc04 ) + dac6: 4f50 ldr r7, [pc, #320] ; (dc08 ) + dac8: 4c4e ldr r4, [pc, #312] ; (dc04 ) + daca: 4d50 ldr r5, [pc, #320] ; (dc0c ) +{ + dacc: b090 sub sp, #64 ; 0x40 + _LV_LL_READ(LV_GC_ROOT(_lv_anim_ll), a) { + dace: 47b8 blx r7 + dad0: b9a0 cbnz r0, dafc + uint32_t elaps = lv_tick_elaps(last_task_run); + dad2: 4d4f ldr r5, [pc, #316] ; (dc10 ) + dad4: 4b4f ldr r3, [pc, #316] ; (dc14 ) + dad6: 68a8 ldr r0, [r5, #8] + a = _lv_ll_get_next(&LV_GC_ROOT(_lv_anim_ll), a); + dad8: f8df 8128 ldr.w r8, [pc, #296] ; dc04 + dadc: f8df 912c ldr.w r9, [pc, #300] ; dc0c + _lv_memcpy(&a_tmp, a, sizeof(lv_anim_t)); + dae0: f8df a148 ldr.w sl, [pc, #328] ; dc2c + uint32_t elaps = lv_tick_elaps(last_task_run); + dae4: 4798 blx r3 + dae6: 4606 mov r6, r0 + a = _lv_ll_get_head(&LV_GC_ROOT(_lv_anim_ll)); + dae8: 4846 ldr r0, [pc, #280] ; (dc04 ) + daea: 47b8 blx r7 + daec: 4604 mov r4, r0 + while(a != NULL) { + daee: b97c cbnz r4, db10 + last_task_run = lv_tick_get(); + daf0: 4b49 ldr r3, [pc, #292] ; (dc18 ) + daf2: 4798 blx r3 + daf4: 60a8 str r0, [r5, #8] +} + daf6: b010 add sp, #64 ; 0x40 + daf8: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + a->has_run = 0; + dafc: f890 303c ldrb.w r3, [r0, #60] ; 0x3c + db00: f36f 0341 bfc r3, #1, #1 + db04: f880 303c strb.w r3, [r0, #60] ; 0x3c + _LV_LL_READ(LV_GC_ROOT(_lv_anim_ll), a) { + db08: 4601 mov r1, r0 + db0a: 4620 mov r0, r4 + db0c: 47a8 blx r5 + db0e: e7df b.n dad0 + anim_list_changed = false; + db10: 2300 movs r3, #0 + db12: 702b strb r3, [r5, #0] + if(!a->has_run) { + db14: f894 303c ldrb.w r3, [r4, #60] ; 0x3c + db18: 079a lsls r2, r3, #30 + db1a: d46f bmi.n dbfc + a->has_run = 1; /*The list readying might be reseted so need to know which anim has run already*/ + db1c: f043 0302 orr.w r3, r3, #2 + db20: f884 303c strb.w r3, [r4, #60] ; 0x3c + int32_t new_act_time = a->act_time + elaps; + db24: 6a63 ldr r3, [r4, #36] ; 0x24 + if(a->act_time <= 0 && new_act_time >= 0) { + db26: 2b00 cmp r3, #0 + db28: dc05 bgt.n db36 + db2a: 42f3 cmn r3, r6 + db2c: d403 bmi.n db36 + if(a->start_cb) a->start_cb(a); + db2e: 68a3 ldr r3, [r4, #8] + db30: b10b cbz r3, db36 + db32: 4620 mov r0, r4 + db34: 4798 blx r3 + a->act_time += elaps; + db36: 6a63 ldr r3, [r4, #36] ; 0x24 + db38: 4433 add r3, r6 + if(a->act_time >= 0) { + db3a: 2b00 cmp r3, #0 + a->act_time += elaps; + db3c: 6263 str r3, [r4, #36] ; 0x24 + if(a->act_time >= 0) { + db3e: db2e blt.n db9e + if(a->act_time > a->time) a->act_time = a->time; + db40: 6a22 ldr r2, [r4, #32] + db42: 429a cmp r2, r3 + db44: bfd4 ite le + db46: 6262 strle r2, [r4, #36] ; 0x24 + db48: 6263 strgt r3, [r4, #36] ; 0x24 + if(a->path.cb) new_value = a->path.cb(&a->path, a); + db4a: 4620 mov r0, r4 + db4c: 4621 mov r1, r4 + db4e: f850 3f10 ldr.w r3, [r0, #16]! + db52: b353 cbz r3, dbaa + db54: 4798 blx r3 + if(a->exec_cb) a->exec_cb(a->var, new_value); + db56: 6863 ldr r3, [r4, #4] + db58: b113 cbz r3, db60 + db5a: b201 sxth r1, r0 + db5c: 6820 ldr r0, [r4, #0] + db5e: 4798 blx r3 + if(a->act_time >= a->time) { + db60: e9d4 3208 ldrd r3, r2, [r4, #32] + db64: 429a cmp r2, r3 + db66: db1a blt.n db9e + if(a->playback_now == 0 && a->repeat_cnt > 0 && a->repeat_cnt != LV_ANIM_REPEAT_INFINITE) { + db68: f894 303c ldrb.w r3, [r4, #60] ; 0x3c + db6c: 8ea2 ldrh r2, [r4, #52] ; 0x34 + db6e: 6ae1 ldr r1, [r4, #44] ; 0x2c + db70: f013 0301 ands.w r3, r3, #1 + db74: d122 bne.n dbbc + db76: b9da cbnz r2, dbb0 + if(a->repeat_cnt == 0 && ((a->playback_time == 0) || (a->playback_time && a->playback_now == 1))) { + db78: 2900 cmp r1, #0 + db7a: d13c bne.n dbf6 + _lv_memcpy(&a_tmp, a, sizeof(lv_anim_t)); + db7c: 2240 movs r2, #64 ; 0x40 + db7e: 4621 mov r1, r4 + db80: 4668 mov r0, sp + db82: 47d0 blx sl + _lv_ll_remove(&LV_GC_ROOT(_lv_anim_ll), a); + db84: 4621 mov r1, r4 + db86: 4b25 ldr r3, [pc, #148] ; (dc1c ) + db88: 4640 mov r0, r8 + db8a: 4798 blx r3 + lv_mem_free(a); + db8c: 4b24 ldr r3, [pc, #144] ; (dc20 ) + db8e: 4620 mov r0, r4 + db90: 4798 blx r3 + anim_mark_list_change(); + db92: 4b24 ldr r3, [pc, #144] ; (dc24 ) + db94: 4798 blx r3 + if(a_tmp.ready_cb != NULL) a_tmp.ready_cb(&a_tmp); + db96: 9b03 ldr r3, [sp, #12] + db98: b10b cbz r3, db9e + db9a: 4668 mov r0, sp + db9c: 4798 blx r3 + if(anim_list_changed) + db9e: 782b ldrb r3, [r5, #0] + dba0: b363 cbz r3, dbfc + a = _lv_ll_get_head(&LV_GC_ROOT(_lv_anim_ll)); + dba2: 4640 mov r0, r8 + dba4: 47b8 blx r7 + a = _lv_ll_get_next(&LV_GC_ROOT(_lv_anim_ll), a); + dba6: 4604 mov r4, r0 + dba8: e7a1 b.n daee + else new_value = lv_anim_path_linear(&a->path, a); + dbaa: 4b1f ldr r3, [pc, #124] ; (dc28 ) + dbac: 4798 blx r3 + dbae: e7d2 b.n db56 + if(a->playback_now == 0 && a->repeat_cnt > 0 && a->repeat_cnt != LV_ANIM_REPEAT_INFINITE) { + dbb0: f64f 70ff movw r0, #65535 ; 0xffff + dbb4: 4282 cmp r2, r0 + dbb6: d004 beq.n dbc2 + a->repeat_cnt--; + dbb8: 3a01 subs r2, #1 + dbba: 86a2 strh r2, [r4, #52] ; 0x34 + if(a->repeat_cnt == 0 && ((a->playback_time == 0) || (a->playback_time && a->playback_now == 1))) { + dbbc: 8ea2 ldrh r2, [r4, #52] ; 0x34 + dbbe: 2a00 cmp r2, #0 + dbc0: d0da beq.n db78 + a->act_time = -a->repeat_delay; /*Restart the animation*/ + dbc2: 6b22 ldr r2, [r4, #48] ; 0x30 + dbc4: 4252 negs r2, r2 + dbc6: 6262 str r2, [r4, #36] ; 0x24 + if(a->playback_time != 0) { + dbc8: 2900 cmp r1, #0 + dbca: d0e8 beq.n db9e + if(a->playback_now == 0) a->act_time = -a->playback_delay; + dbcc: b913 cbnz r3, dbd4 + dbce: 6aa2 ldr r2, [r4, #40] ; 0x28 + dbd0: 4252 negs r2, r2 + dbd2: 6262 str r2, [r4, #36] ; 0x24 + a->playback_now = a->playback_now == 0 ? 1 : 0; + dbd4: f083 0201 eor.w r2, r3, #1 + dbd8: f894 303c ldrb.w r3, [r4, #60] ; 0x3c + dbdc: f362 0300 bfi r3, r2, #0, #1 + a->start = a->end; + dbe0: e9d4 0206 ldrd r0, r2, [r4, #24] + a->playback_now = a->playback_now == 0 ? 1 : 0; + dbe4: f884 303c strb.w r3, [r4, #60] ; 0x3c + a->time = a->playback_now == 0 ? a->time_orig : a->playback_time; + dbe8: 07db lsls r3, r3, #31 + dbea: bf58 it pl + dbec: 6ba1 ldrpl r1, [r4, #56] ; 0x38 + dbee: 6221 str r1, [r4, #32] + a->end = tmp; + dbf0: e9c4 2006 strd r2, r0, [r4, #24] + a->time = a->playback_now == 0 ? a->time_orig : a->playback_time; + dbf4: e7d3 b.n db9e + if(a->repeat_cnt == 0 && ((a->playback_time == 0) || (a->playback_time && a->playback_now == 1))) { + dbf6: 2b00 cmp r3, #0 + dbf8: d0e3 beq.n dbc2 + dbfa: e7bf b.n db7c + a = _lv_ll_get_next(&LV_GC_ROOT(_lv_anim_ll), a); + dbfc: 4621 mov r1, r4 + dbfe: 4640 mov r0, r8 + dc00: 47c8 blx r9 + dc02: e7d0 b.n dba6 + dc04: 2000863c .word 0x2000863c + dc08: 0000e6a9 .word 0x0000e6a9 + dc0c: 0000e6b5 .word 0x0000e6b5 + dc10: 200085f4 .word 0x200085f4 + dc14: 0000da5d .word 0x0000da5d + dc18: 0000da49 .word 0x0000da49 + dc1c: 0000e76d .word 0x0000e76d + dc20: 0000eae5 .word 0x0000eae5 + dc24: 0000da91 .word 0x0000da91 + dc28: 0000da6d .word 0x0000da6d + dc2c: 0000ec31 .word 0x0000ec31 + +0000dc30 <_lv_anim_core_init>: +{ + dc30: b538 push {r3, r4, r5, lr} + _lv_ll_init(&LV_GC_ROOT(_lv_anim_ll), sizeof(lv_anim_t)); + dc32: 2140 movs r1, #64 ; 0x40 + dc34: 4809 ldr r0, [pc, #36] ; (dc5c <_lv_anim_core_init+0x2c>) + dc36: 4b0a ldr r3, [pc, #40] ; (dc60 <_lv_anim_core_init+0x30>) + last_task_run = lv_tick_get(); + dc38: 4c0a ldr r4, [pc, #40] ; (dc64 <_lv_anim_core_init+0x34>) + _lv_anim_task = lv_task_create(anim_task, LV_DISP_DEF_REFR_PERIOD, LV_ANIM_TASK_PRIO, NULL); + dc3a: 4d0b ldr r5, [pc, #44] ; (dc68 <_lv_anim_core_init+0x38>) + _lv_ll_init(&LV_GC_ROOT(_lv_anim_ll), sizeof(lv_anim_t)); + dc3c: 4798 blx r3 + last_task_run = lv_tick_get(); + dc3e: 4b0b ldr r3, [pc, #44] ; (dc6c <_lv_anim_core_init+0x3c>) + dc40: 4798 blx r3 + _lv_anim_task = lv_task_create(anim_task, LV_DISP_DEF_REFR_PERIOD, LV_ANIM_TASK_PRIO, NULL); + dc42: 2300 movs r3, #0 + last_task_run = lv_tick_get(); + dc44: 60a0 str r0, [r4, #8] + _lv_anim_task = lv_task_create(anim_task, LV_DISP_DEF_REFR_PERIOD, LV_ANIM_TASK_PRIO, NULL); + dc46: 2204 movs r2, #4 + dc48: 211e movs r1, #30 + dc4a: 4809 ldr r0, [pc, #36] ; (dc70 <_lv_anim_core_init+0x40>) + dc4c: 47a8 blx r5 + anim_mark_list_change(); /*Turn off the animation task*/ + dc4e: 4b09 ldr r3, [pc, #36] ; (dc74 <_lv_anim_core_init+0x44>) + _lv_anim_task = lv_task_create(anim_task, LV_DISP_DEF_REFR_PERIOD, LV_ANIM_TASK_PRIO, NULL); + dc50: 6060 str r0, [r4, #4] + anim_mark_list_change(); /*Turn off the animation task*/ + dc52: 4798 blx r3 + anim_list_changed = false; /*The list has not actaully changed*/ + dc54: 2300 movs r3, #0 + dc56: 7023 strb r3, [r4, #0] +} + dc58: bd38 pop {r3, r4, r5, pc} + dc5a: bf00 nop + dc5c: 2000863c .word 0x2000863c + dc60: 0000e605 .word 0x0000e605 + dc64: 200085f4 .word 0x200085f4 + dc68: 0000fbd1 .word 0x0000fbd1 + dc6c: 0000da49 .word 0x0000da49 + dc70: 0000dac1 .word 0x0000dac1 + dc74: 0000da91 .word 0x0000da91 + +0000dc78 : +{ + dc78: b510 push {r4, lr} + _lv_memset_00(a, sizeof(lv_anim_t)); + dc7a: 4b0b ldr r3, [pc, #44] ; (dca8 ) +{ + dc7c: 4604 mov r4, r0 + _lv_memset_00(a, sizeof(lv_anim_t)); + dc7e: 2140 movs r1, #64 ; 0x40 + dc80: 4798 blx r3 + a->time = 500; + dc82: f44f 73fa mov.w r3, #500 ; 0x1f4 + dc86: 6223 str r3, [r4, #32] + a->end = 100; + dc88: 2100 movs r1, #0 + dc8a: 2364 movs r3, #100 ; 0x64 + dc8c: e9c4 1306 strd r1, r3, [r4, #24] +{ + uint8_t * d8 = (uint8_t *)dst; + const uint8_t * s8 = (const uint8_t *)src; + + while(len) { + *d8 = *s8; + dc90: 4b06 ldr r3, [pc, #24] ; (dcac ) + dc92: 6123 str r3, [r4, #16] + a->repeat_cnt = 1; + dc94: 2301 movs r3, #1 + dc96: 86a3 strh r3, [r4, #52] ; 0x34 + a->early_apply = 1; + dc98: f894 3036 ldrb.w r3, [r4, #54] ; 0x36 + dc9c: f043 0301 orr.w r3, r3, #1 + dca0: f884 3036 strb.w r3, [r4, #54] ; 0x36 +} + dca4: bd10 pop {r4, pc} + dca6: bf00 nop + dca8: 0000f019 .word 0x0000f019 + dcac: 0000da6d .word 0x0000da6d + +0000dcb0 : +{ + dcb0: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} + a = _lv_ll_get_head(&LV_GC_ROOT(_lv_anim_ll)); + dcb4: 4b14 ldr r3, [pc, #80] ; (dd08 ) + a_next = _lv_ll_get_next(&LV_GC_ROOT(_lv_anim_ll), a); + dcb6: f8df 9054 ldr.w r9, [pc, #84] ; dd0c + dcba: f8df a05c ldr.w sl, [pc, #92] ; dd18 + _lv_ll_remove(&LV_GC_ROOT(_lv_anim_ll), a); + dcbe: f8df b05c ldr.w fp, [pc, #92] ; dd1c +{ + dcc2: 4606 mov r6, r0 + a = _lv_ll_get_head(&LV_GC_ROOT(_lv_anim_ll)); + dcc4: 4811 ldr r0, [pc, #68] ; (dd0c ) +{ + dcc6: 460d mov r5, r1 + a = _lv_ll_get_head(&LV_GC_ROOT(_lv_anim_ll)); + dcc8: 4798 blx r3 + bool del = false; + dcca: f04f 0800 mov.w r8, #0 + a = _lv_ll_get_head(&LV_GC_ROOT(_lv_anim_ll)); + dcce: 4604 mov r4, r0 + while(a != NULL) { + dcd0: b914 cbnz r4, dcd8 +} + dcd2: 4640 mov r0, r8 + dcd4: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} + a_next = _lv_ll_get_next(&LV_GC_ROOT(_lv_anim_ll), a); + dcd8: 4621 mov r1, r4 + dcda: 4648 mov r0, r9 + dcdc: 47d0 blx sl + if(a->var == var && (a->exec_cb == exec_cb || exec_cb == NULL)) { + dcde: 6823 ldr r3, [r4, #0] + dce0: 42b3 cmp r3, r6 + a_next = _lv_ll_get_next(&LV_GC_ROOT(_lv_anim_ll), a); + dce2: 4607 mov r7, r0 + if(a->var == var && (a->exec_cb == exec_cb || exec_cb == NULL)) { + dce4: d10d bne.n dd02 + dce6: 6863 ldr r3, [r4, #4] + dce8: 42ab cmp r3, r5 + dcea: d000 beq.n dcee + dcec: b94d cbnz r5, dd02 + _lv_ll_remove(&LV_GC_ROOT(_lv_anim_ll), a); + dcee: 4621 mov r1, r4 + dcf0: 4648 mov r0, r9 + dcf2: 47d8 blx fp + lv_mem_free(a); + dcf4: 4b06 ldr r3, [pc, #24] ; (dd10 ) + dcf6: 4620 mov r0, r4 + dcf8: 4798 blx r3 + anim_mark_list_change(); /*Read by `anim_task`. It need to know if a delete occurred in + dcfa: 4b06 ldr r3, [pc, #24] ; (dd14 ) + dcfc: 4798 blx r3 + del = true; + dcfe: f04f 0801 mov.w r8, #1 + dd02: 463c mov r4, r7 + dd04: e7e4 b.n dcd0 + dd06: bf00 nop + dd08: 0000e6a9 .word 0x0000e6a9 + dd0c: 2000863c .word 0x2000863c + dd10: 0000eae5 .word 0x0000eae5 + dd14: 0000da91 .word 0x0000da91 + dd18: 0000e6b5 .word 0x0000e6b5 + dd1c: 0000e76d .word 0x0000e76d + +0000dd20 : +{ + dd20: b573 push {r0, r1, r4, r5, r6, lr} + if(a->exec_cb != NULL) lv_anim_del(a->var, a->exec_cb); /*fp == NULL would delete all animations of var*/ + dd22: 6841 ldr r1, [r0, #4] +{ + dd24: 4605 mov r5, r0 + if(a->exec_cb != NULL) lv_anim_del(a->var, a->exec_cb); /*fp == NULL would delete all animations of var*/ + dd26: b111 cbz r1, dd2e + dd28: 6800 ldr r0, [r0, #0] + dd2a: 4b1d ldr r3, [pc, #116] ; (dda0 ) + dd2c: 4798 blx r3 + if(_lv_ll_is_empty(&LV_GC_ROOT(_lv_anim_ll))) { + dd2e: 481d ldr r0, [pc, #116] ; (dda4 ) + dd30: 4b1d ldr r3, [pc, #116] ; (dda8 ) + dd32: 4798 blx r3 + dd34: b120 cbz r0, dd40 + last_task_run = lv_tick_get() - 1; + dd36: 4b1d ldr r3, [pc, #116] ; (ddac ) + dd38: 4798 blx r3 + dd3a: 4b1d ldr r3, [pc, #116] ; (ddb0 ) + dd3c: 3801 subs r0, #1 + dd3e: 6098 str r0, [r3, #8] + lv_anim_t * new_anim = _lv_ll_ins_head(&LV_GC_ROOT(_lv_anim_ll)); + dd40: 4b1c ldr r3, [pc, #112] ; (ddb4 ) + dd42: 4818 ldr r0, [pc, #96] ; (dda4 ) + dd44: 4798 blx r3 + LV_ASSERT_MEM(new_anim); + dd46: 4b1c ldr r3, [pc, #112] ; (ddb8 ) + lv_anim_t * new_anim = _lv_ll_ins_head(&LV_GC_ROOT(_lv_anim_ll)); + dd48: 4604 mov r4, r0 + LV_ASSERT_MEM(new_anim); + dd4a: 4798 blx r3 + dd4c: 4606 mov r6, r0 + dd4e: b960 cbnz r0, dd6a + dd50: 4b1a ldr r3, [pc, #104] ; (ddbc ) + dd52: 491b ldr r1, [pc, #108] ; (ddc0 ) + dd54: 9300 str r3, [sp, #0] + dd56: 226a movs r2, #106 ; 0x6a + dd58: 2003 movs r0, #3 + dd5a: 4d1a ldr r5, [pc, #104] ; (ddc4 ) + dd5c: 47a8 blx r5 + dd5e: 481a ldr r0, [pc, #104] ; (ddc8 ) + dd60: 491a ldr r1, [pc, #104] ; (ddcc ) + dd62: 4622 mov r2, r4 + dd64: 4633 mov r3, r6 + dd66: 4788 blx r1 + dd68: e7fe b.n dd68 + if(new_anim == NULL) return; + dd6a: b1b4 cbz r4, dd9a + a->time_orig = a->time; + dd6c: 6a2b ldr r3, [r5, #32] + dd6e: 63ab str r3, [r5, #56] ; 0x38 + _lv_memcpy(new_anim, a, sizeof(lv_anim_t)); + dd70: 2240 movs r2, #64 ; 0x40 + dd72: 4b17 ldr r3, [pc, #92] ; (ddd0 ) + dd74: 4629 mov r1, r5 + dd76: 4620 mov r0, r4 + dd78: 4798 blx r3 + if(new_anim->early_apply) { + dd7a: f894 3036 ldrb.w r3, [r4, #54] ; 0x36 + dd7e: 07db lsls r3, r3, #31 + dd80: d506 bpl.n dd90 + if(new_anim->exec_cb && new_anim->var) new_anim->exec_cb(new_anim->var, new_anim->start); + dd82: 6863 ldr r3, [r4, #4] + dd84: b123 cbz r3, dd90 + dd86: 6820 ldr r0, [r4, #0] + dd88: b110 cbz r0, dd90 + dd8a: f9b4 1018 ldrsh.w r1, [r4, #24] + dd8e: 4798 blx r3 + anim_mark_list_change(); + dd90: 4b10 ldr r3, [pc, #64] ; (ddd4 ) +} + dd92: b002 add sp, #8 + dd94: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + anim_mark_list_change(); + dd98: 4718 bx r3 +} + dd9a: b002 add sp, #8 + dd9c: bd70 pop {r4, r5, r6, pc} + dd9e: bf00 nop + dda0: 0000dcb1 .word 0x0000dcb1 + dda4: 2000863c .word 0x2000863c + dda8: 0000e8d1 .word 0x0000e8d1 + ddac: 0000da49 .word 0x0000da49 + ddb0: 200085f4 .word 0x200085f4 + ddb4: 0000e619 .word 0x0000e619 + ddb8: 000017e1 .word 0x000017e1 + ddbc: 00023f14 .word 0x00023f14 + ddc0: 00023ee4 .word 0x00023ee4 + ddc4: 0000e8e9 .word 0x0000e8e9 + ddc8: 0001edbe .word 0x0001edbe + ddcc: 000017e9 .word 0x000017e9 + ddd0: 0000ec31 .word 0x0000ec31 + ddd4: 0000da91 .word 0x0000da91 + +0000ddd8 : +{ + ddd8: b5f8 push {r3, r4, r5, r6, r7, lr} + _LV_LL_READ(LV_GC_ROOT(_lv_anim_ll), a) { + ddda: 4b09 ldr r3, [pc, #36] ; (de00 ) + dddc: 4e09 ldr r6, [pc, #36] ; (de04 ) + ddde: 4f0a ldr r7, [pc, #40] ; (de08 ) +{ + dde0: 4604 mov r4, r0 + _LV_LL_READ(LV_GC_ROOT(_lv_anim_ll), a) { + dde2: 4808 ldr r0, [pc, #32] ; (de04 ) +{ + dde4: 460d mov r5, r1 + _LV_LL_READ(LV_GC_ROOT(_lv_anim_ll), a) { + dde6: 4798 blx r3 + dde8: b900 cbnz r0, ddec +} + ddea: bdf8 pop {r3, r4, r5, r6, r7, pc} + if(a->var == var && a->exec_cb == exec_cb) { + ddec: 6803 ldr r3, [r0, #0] + ddee: 42a3 cmp r3, r4 + ddf0: d102 bne.n ddf8 + ddf2: 6843 ldr r3, [r0, #4] + ddf4: 42ab cmp r3, r5 + ddf6: d0f8 beq.n ddea + _LV_LL_READ(LV_GC_ROOT(_lv_anim_ll), a) { + ddf8: 4601 mov r1, r0 + ddfa: 4630 mov r0, r6 + ddfc: 47b8 blx r7 + ddfe: e7f3 b.n dde8 + de00: 0000e6a9 .word 0x0000e6a9 + de04: 2000863c .word 0x2000863c + de08: 0000e6b5 .word 0x0000e6b5 + +0000de0c : + int32_t d = LV_MATH_ABS((int32_t)start - end); + de0c: 1a8a subs r2, r1, r2 + de0e: 2a00 cmp r2, #0 + de10: bfb8 it lt + de12: 4252 neglt r2, r2 + uint32_t time = (int32_t)((int32_t)(d * 1000) / speed); + de14: f44f 737a mov.w r3, #1000 ; 0x3e8 + de18: 435a muls r2, r3 + de1a: fbb2 f0f0 udiv r0, r2, r0 + return time; + de1e: 2801 cmp r0, #1 + de20: bf38 it cc + de22: 2001 movcc r0, #1 + de24: f64f 73ff movw r3, #65535 ; 0xffff + de28: 4298 cmp r0, r3 + de2a: bf28 it cs + de2c: 4618 movcs r0, r3 +} + de2e: b280 uxth r0, r0 + de30: 4770 bx lr + +0000de32 : + +/********************** + * STATIC FUNCTIONS + **********************/ + +static bool lv_point_within_circle(const lv_area_t * area, const lv_point_t * p) + de32: b530 push {r4, r5, lr} +{ + lv_coord_t r = (area->x2 - area->x1) / 2; + de34: f9b0 3004 ldrsh.w r3, [r0, #4] + de38: f9b0 5000 ldrsh.w r5, [r0] + lv_coord_t cx = area->x1 + r; + lv_coord_t cy = area->y1 + r; + + /*Simplify the code by moving everything to (0, 0) */ + lv_coord_t px = p->x - cx; + lv_coord_t py = p->y - cy; + de3c: 8840 ldrh r0, [r0, #2] + lv_coord_t r = (area->x2 - area->x1) / 2; + de3e: 1b5b subs r3, r3, r5 + de40: eb03 73d3 add.w r3, r3, r3, lsr #31 + lv_coord_t py = p->y - cy; + de44: 1a12 subs r2, r2, r0 + lv_coord_t r = (area->x2 - area->x1) / 2; + de46: 105c asrs r4, r3, #1 + lv_coord_t cx = area->x1 + r; + de48: f3c3 034f ubfx r3, r3, #1, #16 + lv_coord_t px = p->x - cx; + de4c: 1b49 subs r1, r1, r5 + lv_coord_t py = p->y - cy; + de4e: 1ad2 subs r2, r2, r3 + lv_coord_t px = p->x - cx; + de50: 1ac9 subs r1, r1, r3 + + int32_t r_sqrd = r * r; + int32_t dist = (px * px) + (py * py); + de52: fb12 f202 smulbb r2, r2, r2 + int32_t r_sqrd = r * r; + de56: 4364 muls r4, r4 + int32_t dist = (px * px) + (py * py); + de58: fb11 2101 smlabb r1, r1, r1, r2 + + if(dist <= r_sqrd) + return true; + else + return false; +} + de5c: 428c cmp r4, r1 + de5e: bfb4 ite lt + de60: 2000 movlt r0, #0 + de62: 2001 movge r0, #1 + de64: bd30 pop {r4, r5, pc} + +0000de66 : + area_p->y2 = area_p->y1 + h - 1; + de66: 8843 ldrh r3, [r0, #2] + de68: 3901 subs r1, #1 + de6a: 4419 add r1, r3 + de6c: 80c1 strh r1, [r0, #6] +} + de6e: 4770 bx lr + +0000de70 : + size = (uint32_t)(area_p->x2 - area_p->x1 + 1) * (area_p->y2 - area_p->y1 + 1); + de70: f9b0 3000 ldrsh.w r3, [r0] + de74: f9b0 2004 ldrsh.w r2, [r0, #4] + de78: f9b0 1002 ldrsh.w r1, [r0, #2] + de7c: 1ad2 subs r2, r2, r3 + de7e: f9b0 3006 ldrsh.w r3, [r0, #6] + de82: 1a58 subs r0, r3, r1 + de84: 3001 adds r0, #1 +} + de86: fb02 0000 mla r0, r2, r0, r0 + de8a: 4770 bx lr + +0000de8c <_lv_area_intersect>: + res_p->x1 = LV_MATH_MAX(a1_p->x1, a2_p->x1); + de8c: f9b1 3000 ldrsh.w r3, [r1] +{ + de90: b570 push {r4, r5, r6, lr} + res_p->x1 = LV_MATH_MAX(a1_p->x1, a2_p->x1); + de92: f9b2 5000 ldrsh.w r5, [r2] + res_p->y1 = LV_MATH_MAX(a1_p->y1, a2_p->y1); + de96: f9b1 4002 ldrsh.w r4, [r1, #2] + res_p->x2 = LV_MATH_MIN(a1_p->x2, a2_p->x2); + de9a: f9b1 6004 ldrsh.w r6, [r1, #4] + res_p->y2 = LV_MATH_MIN(a1_p->y2, a2_p->y2); + de9e: f9b1 1006 ldrsh.w r1, [r1, #6] + res_p->x1 = LV_MATH_MAX(a1_p->x1, a2_p->x1); + dea2: 429d cmp r5, r3 + dea4: bfb8 it lt + dea6: 461d movlt r5, r3 + res_p->y1 = LV_MATH_MAX(a1_p->y1, a2_p->y1); + dea8: f9b2 3002 ldrsh.w r3, [r2, #2] + res_p->x1 = LV_MATH_MAX(a1_p->x1, a2_p->x1); + deac: 8005 strh r5, [r0, #0] + res_p->y1 = LV_MATH_MAX(a1_p->y1, a2_p->y1); + deae: 42a3 cmp r3, r4 + deb0: bfb8 it lt + deb2: 4623 movlt r3, r4 + res_p->x2 = LV_MATH_MIN(a1_p->x2, a2_p->x2); + deb4: f9b2 4004 ldrsh.w r4, [r2, #4] + res_p->y2 = LV_MATH_MIN(a1_p->y2, a2_p->y2); + deb8: f9b2 2006 ldrsh.w r2, [r2, #6] + res_p->y1 = LV_MATH_MAX(a1_p->y1, a2_p->y1); + debc: 8043 strh r3, [r0, #2] + res_p->x2 = LV_MATH_MIN(a1_p->x2, a2_p->x2); + debe: 42b4 cmp r4, r6 + dec0: bfa8 it ge + dec2: 4634 movge r4, r6 + res_p->y2 = LV_MATH_MIN(a1_p->y2, a2_p->y2); + dec4: 428a cmp r2, r1 + dec6: bfa8 it ge + dec8: 460a movge r2, r1 + if((res_p->x1 > res_p->x2) || (res_p->y1 > res_p->y2)) { + deca: 42a5 cmp r5, r4 + res_p->x2 = LV_MATH_MIN(a1_p->x2, a2_p->x2); + decc: 8084 strh r4, [r0, #4] + res_p->y2 = LV_MATH_MIN(a1_p->y2, a2_p->y2); + dece: 80c2 strh r2, [r0, #6] + if((res_p->x1 > res_p->x2) || (res_p->y1 > res_p->y2)) { + ded0: dc04 bgt.n dedc <_lv_area_intersect+0x50> + ded2: 4293 cmp r3, r2 + ded4: bfcc ite gt + ded6: 2000 movgt r0, #0 + ded8: 2001 movle r0, #1 +} + deda: bd70 pop {r4, r5, r6, pc} + union_ok = false; + dedc: 2000 movs r0, #0 + dede: e7fc b.n deda <_lv_area_intersect+0x4e> + +0000dee0 <_lv_area_join>: + a_res_p->x1 = LV_MATH_MIN(a1_p->x1, a2_p->x1); + dee0: f9b2 3000 ldrsh.w r3, [r2] +{ + dee4: b510 push {r4, lr} + a_res_p->x1 = LV_MATH_MIN(a1_p->x1, a2_p->x1); + dee6: f9b1 4000 ldrsh.w r4, [r1] + deea: 42a3 cmp r3, r4 + deec: bfa8 it ge + deee: 4623 movge r3, r4 + def0: 8003 strh r3, [r0, #0] + a_res_p->y1 = LV_MATH_MIN(a1_p->y1, a2_p->y1); + def2: f9b1 4002 ldrsh.w r4, [r1, #2] + def6: f9b2 3002 ldrsh.w r3, [r2, #2] + defa: 42a3 cmp r3, r4 + defc: bfa8 it ge + defe: 4623 movge r3, r4 + df00: 8043 strh r3, [r0, #2] + a_res_p->x2 = LV_MATH_MAX(a1_p->x2, a2_p->x2); + df02: f9b1 4004 ldrsh.w r4, [r1, #4] + df06: f9b2 3004 ldrsh.w r3, [r2, #4] + df0a: 42a3 cmp r3, r4 + df0c: bfb8 it lt + df0e: 4623 movlt r3, r4 + df10: 8083 strh r3, [r0, #4] + a_res_p->y2 = LV_MATH_MAX(a1_p->y2, a2_p->y2); + df12: f9b2 3006 ldrsh.w r3, [r2, #6] + df16: f9b1 2006 ldrsh.w r2, [r1, #6] + df1a: 4293 cmp r3, r2 + df1c: bfb8 it lt + df1e: 4613 movlt r3, r2 + df20: 80c3 strh r3, [r0, #6] +} + df22: bd10 pop {r4, pc} + +0000df24 <_lv_area_is_point_on>: +{ + df24: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + if((p_p->x >= a_p->x1 && p_p->x <= a_p->x2) && ((p_p->y >= a_p->y1 && p_p->y <= a_p->y2))) { + df28: f9b1 9000 ldrsh.w r9, [r1] + df2c: f9b0 4000 ldrsh.w r4, [r0] + df30: 45a1 cmp r9, r4 +{ + df32: b087 sub sp, #28 + df34: 4688 mov r8, r1 + if((p_p->x >= a_p->x1 && p_p->x <= a_p->x2) && ((p_p->y >= a_p->y1 && p_p->y <= a_p->y2))) { + df36: f2c0 8088 blt.w e04a <_lv_area_is_point_on+0x126> + df3a: f9b0 3004 ldrsh.w r3, [r0, #4] + df3e: 9301 str r3, [sp, #4] + df40: 4599 cmp r9, r3 + df42: f300 8082 bgt.w e04a <_lv_area_is_point_on+0x126> + df46: f9b1 a002 ldrsh.w sl, [r1, #2] + df4a: f9b0 b002 ldrsh.w fp, [r0, #2] + df4e: 45da cmp sl, fp + df50: db7b blt.n e04a <_lv_area_is_point_on+0x126> + df52: f9b0 3006 ldrsh.w r3, [r0, #6] + df56: 459a cmp sl, r3 + df58: dc77 bgt.n e04a <_lv_area_is_point_on+0x126> + if(radius <= 0) { + df5a: 2a00 cmp r2, #0 + df5c: dc03 bgt.n df66 <_lv_area_is_point_on+0x42> + return true; + df5e: 2001 movs r0, #1 +} + df60: b007 add sp, #28 + df62: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + * @param area_p pointer to an area + * @return the width of the area (if x1 == x2 -> width = 1) + */ +static inline lv_coord_t lv_area_get_width(const lv_area_t * area_p) +{ + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + df66: f8bd 0004 ldrh.w r0, [sp, #4] + df6a: 9002 str r0, [sp, #8] + df6c: b2a7 uxth r7, r4 + df6e: 3001 adds r0, #1 + df70: 1bc0 subs r0, r0, r7 + * @param area_p pointer to an area + * @return the height of the area (if y1 == y2 -> height = 1) + */ +static inline lv_coord_t lv_area_get_height(const lv_area_t * area_p) +{ + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + df72: b29e uxth r6, r3 + corner_area.x1 = a_p->x1; + df74: f8ad 4010 strh.w r4, [sp, #16] + lv_coord_t w = lv_area_get_width(a_p) / 2; + df78: f3c0 34c0 ubfx r4, r0, #15, #1 + df7c: fa1f fc8b uxth.w ip, fp + df80: fa04 f080 sxtah r0, r4, r0 + df84: 1c74 adds r4, r6, #1 + df86: eba4 040c sub.w r4, r4, ip + lv_coord_t h = lv_area_get_height(a_p) / 2; + df8a: f3c4 35c0 ubfx r5, r4, #15, #1 + df8e: fa05 f584 sxtah r5, r5, r4 + lv_coord_t max_radius = LV_MATH_MIN(w, h); + df92: 1040 asrs r0, r0, #1 + df94: 106d asrs r5, r5, #1 + corner_area.x2 = a_p->x1 + radius; + df96: 42a8 cmp r0, r5 + df98: bfa8 it ge + df9a: 4628 movge r0, r5 + df9c: 4290 cmp r0, r2 + df9e: bfa8 it ge + dfa0: 4610 movge r0, r2 + corner_area.y2 = a_p->y1 + radius; + dfa2: fa1c f480 uxtah r4, ip, r0 + corner_area.x2 = a_p->x1 + radius; + dfa6: fa17 f780 uxtah r7, r7, r0 + if(_lv_area_is_point_on(&corner_area, p_p, 0)) { + dfaa: 2200 movs r2, #0 + corner_area.x2 = a_p->x1 + radius; + dfac: b285 uxth r5, r0 + dfae: b2bf uxth r7, r7 + corner_area.y2 = a_p->y1 + radius; + dfb0: b224 sxth r4, r4 + if(_lv_area_is_point_on(&corner_area, p_p, 0)) { + dfb2: a804 add r0, sp, #16 + dfb4: 9303 str r3, [sp, #12] + corner_area.x2 = a_p->x1 + radius; + dfb6: f8ad 7014 strh.w r7, [sp, #20] + corner_area.y1 = a_p->y1; + dfba: f8ad b012 strh.w fp, [sp, #18] + corner_area.y2 = a_p->y1 + radius; + dfbe: f8ad 4016 strh.w r4, [sp, #22] + if(_lv_area_is_point_on(&corner_area, p_p, 0)) { + dfc2: f7ff ffaf bl df24 <_lv_area_is_point_on> + dfc6: 9b03 ldr r3, [sp, #12] + dfc8: 4602 mov r2, r0 + dfca: b140 cbz r0, dfde <_lv_area_is_point_on+0xba> + corner_area.x2 += radius; + dfcc: 443d add r5, r7 + dfce: f8ad 5014 strh.w r5, [sp, #20] + return lv_point_within_circle(&corner_area, p_p); + dfd2: 4b1f ldr r3, [pc, #124] ; (e050 <_lv_area_is_point_on+0x12c>) + dfd4: 4652 mov r2, sl + dfd6: 4649 mov r1, r9 + dfd8: a804 add r0, sp, #16 + dfda: 4798 blx r3 + dfdc: e7c0 b.n df60 <_lv_area_is_point_on+0x3c> + corner_area.y1 = a_p->y2 - radius; + dfde: 1b76 subs r6, r6, r5 + dfe0: b2b6 uxth r6, r6 + if(_lv_area_is_point_on(&corner_area, p_p, 0)) { + dfe2: 4641 mov r1, r8 + dfe4: a804 add r0, sp, #16 + corner_area.y1 = a_p->y2 - radius; + dfe6: f8ad 6012 strh.w r6, [sp, #18] + corner_area.y2 = a_p->y2; + dfea: f8ad 3016 strh.w r3, [sp, #22] + if(_lv_area_is_point_on(&corner_area, p_p, 0)) { + dfee: f7ff ff99 bl df24 <_lv_area_is_point_on> + dff2: 4602 mov r2, r0 + dff4: b130 cbz r0, e004 <_lv_area_is_point_on+0xe0> + corner_area.x2 += radius; + dff6: 442f add r7, r5 + corner_area.y1 -= radius; + dff8: 1b75 subs r5, r6, r5 + corner_area.x2 += radius; + dffa: f8ad 7014 strh.w r7, [sp, #20] + corner_area.y1 -= radius; + dffe: f8ad 5012 strh.w r5, [sp, #18] + return lv_point_within_circle(&corner_area, p_p); + e002: e7e6 b.n dfd2 <_lv_area_is_point_on+0xae> + corner_area.x1 = a_p->x2 - radius; + e004: 9b02 ldr r3, [sp, #8] + e006: 1b5f subs r7, r3, r5 + e008: b2bf uxth r7, r7 + corner_area.x2 = a_p->x2; + e00a: 9b01 ldr r3, [sp, #4] + corner_area.x1 = a_p->x2 - radius; + e00c: f8ad 7010 strh.w r7, [sp, #16] + if(_lv_area_is_point_on(&corner_area, p_p, 0)) { + e010: 4641 mov r1, r8 + e012: a804 add r0, sp, #16 + corner_area.x2 = a_p->x2; + e014: f8ad 3014 strh.w r3, [sp, #20] + if(_lv_area_is_point_on(&corner_area, p_p, 0)) { + e018: f7ff ff84 bl df24 <_lv_area_is_point_on> + e01c: 4602 mov r2, r0 + e01e: b130 cbz r0, e02e <_lv_area_is_point_on+0x10a> + corner_area.x1 -= radius; + e020: 1b7f subs r7, r7, r5 + corner_area.y1 -= radius; + e022: 1b76 subs r6, r6, r5 + corner_area.x1 -= radius; + e024: f8ad 7010 strh.w r7, [sp, #16] + corner_area.y1 -= radius; + e028: f8ad 6012 strh.w r6, [sp, #18] + return lv_point_within_circle(&corner_area, p_p); + e02c: e7d1 b.n dfd2 <_lv_area_is_point_on+0xae> + if(_lv_area_is_point_on(&corner_area, p_p, 0)) { + e02e: 4641 mov r1, r8 + e030: a804 add r0, sp, #16 + corner_area.y1 = a_p->y1; + e032: f8ad b012 strh.w fp, [sp, #18] + corner_area.y2 = a_p->y1 + radius; + e036: f8ad 4016 strh.w r4, [sp, #22] + if(_lv_area_is_point_on(&corner_area, p_p, 0)) { + e03a: f7ff ff73 bl df24 <_lv_area_is_point_on> + e03e: 2800 cmp r0, #0 + e040: d08d beq.n df5e <_lv_area_is_point_on+0x3a> + corner_area.x1 -= radius; + e042: 1b7f subs r7, r7, r5 + e044: f8ad 7010 strh.w r7, [sp, #16] + e048: e7c3 b.n dfd2 <_lv_area_is_point_on+0xae> + return false; + e04a: 2000 movs r0, #0 + e04c: e788 b.n df60 <_lv_area_is_point_on+0x3c> + e04e: bf00 nop + e050: 0000de33 .word 0x0000de33 + +0000e054 <_lv_area_is_on>: + if((a1_p->x1 <= a2_p->x2) && (a1_p->x2 >= a2_p->x1) && (a1_p->y1 <= a2_p->y2) && (a1_p->y2 >= a2_p->y1)) { + e054: f9b0 2000 ldrsh.w r2, [r0] + e058: f9b1 3004 ldrsh.w r3, [r1, #4] + e05c: 429a cmp r2, r3 + e05e: dc14 bgt.n e08a <_lv_area_is_on+0x36> + e060: f9b0 2004 ldrsh.w r2, [r0, #4] + e064: f9b1 3000 ldrsh.w r3, [r1] + e068: 429a cmp r2, r3 + e06a: db0e blt.n e08a <_lv_area_is_on+0x36> + e06c: f9b0 2002 ldrsh.w r2, [r0, #2] + e070: f9b1 3006 ldrsh.w r3, [r1, #6] + e074: 429a cmp r2, r3 + e076: dc08 bgt.n e08a <_lv_area_is_on+0x36> + e078: f9b0 0006 ldrsh.w r0, [r0, #6] + e07c: f9b1 3002 ldrsh.w r3, [r1, #2] + e080: 4298 cmp r0, r3 + e082: bfb4 ite lt + e084: 2000 movlt r0, #0 + e086: 2001 movge r0, #1 + e088: 4770 bx lr + return false; + e08a: 2000 movs r0, #0 +} + e08c: 4770 bx lr + ... + +0000e090 <_lv_area_is_in>: +{ + e090: e92d 41ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, lr} + if(ain_p->x1 >= aholder_p->x1 && ain_p->y1 >= aholder_p->y1 && ain_p->x2 <= aholder_p->x2 && + e094: f9b0 7000 ldrsh.w r7, [r0] + e098: f9b1 3000 ldrsh.w r3, [r1] + e09c: 42bb cmp r3, r7 +{ + e09e: 4605 mov r5, r0 + e0a0: 460c mov r4, r1 + if(ain_p->x1 >= aholder_p->x1 && ain_p->y1 >= aholder_p->y1 && ain_p->x2 <= aholder_p->x2 && + e0a2: dc24 bgt.n e0ee <_lv_area_is_in+0x5e> + e0a4: f9b0 1002 ldrsh.w r1, [r0, #2] + e0a8: f9b4 3002 ldrsh.w r3, [r4, #2] + e0ac: 4299 cmp r1, r3 + e0ae: db1e blt.n e0ee <_lv_area_is_in+0x5e> + e0b0: f9b0 1004 ldrsh.w r1, [r0, #4] + e0b4: f9b4 3004 ldrsh.w r3, [r4, #4] + e0b8: 4299 cmp r1, r3 + e0ba: dc18 bgt.n e0ee <_lv_area_is_in+0x5e> + e0bc: f9b0 3006 ldrsh.w r3, [r0, #6] + e0c0: f9b4 1006 ldrsh.w r1, [r4, #6] + e0c4: 428b cmp r3, r1 + e0c6: bfcc ite gt + e0c8: 2000 movgt r0, #0 + e0ca: 2001 movle r0, #1 + if(radius == 0) return is_in; + e0cc: b162 cbz r2, e0e8 <_lv_area_is_in+0x58> + p.y = ain_p->y1; + e0ce: 886b ldrh r3, [r5, #2] + if(_lv_area_is_point_on(aholder_p, &p, radius) == false) return false; + e0d0: 4e16 ldr r6, [pc, #88] ; (e12c <_lv_area_is_in+0x9c>) + e0d2: 9201 str r2, [sp, #4] + e0d4: a903 add r1, sp, #12 + e0d6: 4620 mov r0, r4 + p.x = ain_p->x1; + e0d8: f8ad 700c strh.w r7, [sp, #12] + p.y = ain_p->y1; + e0dc: f8ad 300e strh.w r3, [sp, #14] + if(_lv_area_is_point_on(aholder_p, &p, radius) == false) return false; + e0e0: 47b0 blx r6 + e0e2: 9a01 ldr r2, [sp, #4] + e0e4: b928 cbnz r0, e0f2 <_lv_area_is_in+0x62> + e0e6: 2000 movs r0, #0 +} + e0e8: b004 add sp, #16 + e0ea: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + bool is_in = false; + e0ee: 2000 movs r0, #0 + e0f0: e7ec b.n e0cc <_lv_area_is_in+0x3c> + p.x = ain_p->x2; + e0f2: f9b5 8004 ldrsh.w r8, [r5, #4] + e0f6: f8ad 800c strh.w r8, [sp, #12] + if(_lv_area_is_point_on(aholder_p, &p, radius) == false) return false; + e0fa: a903 add r1, sp, #12 + e0fc: 4620 mov r0, r4 + e0fe: 9201 str r2, [sp, #4] + e100: 47b0 blx r6 + e102: 2800 cmp r0, #0 + e104: d0ef beq.n e0e6 <_lv_area_is_in+0x56> + p.y = ain_p->y2; + e106: 88eb ldrh r3, [r5, #6] + if(_lv_area_is_point_on(aholder_p, &p, radius) == false) return false; + e108: 9a01 ldr r2, [sp, #4] + p.x = ain_p->x1; + e10a: f8ad 700c strh.w r7, [sp, #12] + if(_lv_area_is_point_on(aholder_p, &p, radius) == false) return false; + e10e: a903 add r1, sp, #12 + e110: 4620 mov r0, r4 + p.y = ain_p->y2; + e112: f8ad 300e strh.w r3, [sp, #14] + if(_lv_area_is_point_on(aholder_p, &p, radius) == false) return false; + e116: 47b0 blx r6 + e118: 2800 cmp r0, #0 + e11a: d0e4 beq.n e0e6 <_lv_area_is_in+0x56> + if(_lv_area_is_point_on(aholder_p, &p, radius) == false) return false; + e11c: 9a01 ldr r2, [sp, #4] + p.x = ain_p->x2; + e11e: f8ad 800c strh.w r8, [sp, #12] + if(_lv_area_is_point_on(aholder_p, &p, radius) == false) return false; + e122: a903 add r1, sp, #12 + e124: 4620 mov r0, r4 + e126: 47b0 blx r6 + e128: e7de b.n e0e8 <_lv_area_is_in+0x58> + e12a: bf00 nop + e12c: 0000df25 .word 0x0000df25 + +0000e130 <_lv_area_align>: +{ + e130: b5f0 push {r4, r5, r6, r7, lr} + e132: 8844 ldrh r4, [r0, #2] + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + e134: 8805 ldrh r5, [r0, #0] + switch(align) { + e136: 2a14 cmp r2, #20 + e138: d83f bhi.n e1ba <_lv_area_align+0x8a> + e13a: e8df f012 tbh [pc, r2, lsl #1] + e13e: 0015 .short 0x0015 + e140: 0045003b .word 0x0045003b + e144: 0061005a .word 0x0061005a + e148: 007c0069 .word 0x007c0069 + e14c: 00850083 .word 0x00850083 + e150: 0093008c .word 0x0093008c + e154: 00ad00a6 .word 0x00ad00a6 + e158: 00c600b3 .word 0x00c600b3 + e15c: 00d200cd .word 0x00d200cd + e160: 00dc00d7 .word 0x00dc00d7 + e164: 00e200df .word 0x00e200df + e168: 8882 ldrh r2, [r0, #4] + e16a: 880f ldrh r7, [r1, #0] + e16c: 3201 adds r2, #1 + e16e: 1b52 subs r2, r2, r5 + res->x = lv_area_get_width(base) / 2 - lv_area_get_width(to_align) / 2; + e170: f3c2 36c0 ubfx r6, r2, #15, #1 + e174: fa06 f682 sxtah r6, r6, r2 + e178: 888a ldrh r2, [r1, #4] + e17a: 3201 adds r2, #1 + e17c: 1bd2 subs r2, r2, r7 + e17e: f3c2 37c0 ubfx r7, r2, #15, #1 + e182: fa07 f282 sxtah r2, r7, r2 + e186: 1052 asrs r2, r2, #1 + e188: ebc2 0266 rsb r2, r2, r6, asr #1 + res->x = lv_area_get_width(base); + e18c: 801a strh r2, [r3, #0] + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + e18e: 88c2 ldrh r2, [r0, #6] + e190: 3201 adds r2, #1 + e192: 1b12 subs r2, r2, r4 + res->y = lv_area_get_height(base) / 2 - lv_area_get_height(to_align) / 2; + e194: f3c2 30c0 ubfx r0, r2, #15, #1 + e198: fa00 f082 sxtah r0, r0, r2 + e19c: 88ca ldrh r2, [r1, #6] + e19e: 8849 ldrh r1, [r1, #2] + e1a0: 3201 adds r2, #1 + e1a2: 1a52 subs r2, r2, r1 + e1a4: f3c2 31c0 ubfx r1, r2, #15, #1 + e1a8: fa01 f282 sxtah r2, r1, r2 + e1ac: 1052 asrs r2, r2, #1 + e1ae: ebc2 0260 rsb r2, r2, r0, asr #1 + e1b2: e001 b.n e1b8 <_lv_area_align+0x88> + res->x = 0; + e1b4: 2200 movs r2, #0 + e1b6: 801a strh r2, [r3, #0] + res->y = lv_area_get_height(base) - lv_area_get_height(to_align); + e1b8: 805a strh r2, [r3, #2] + res->x += base->x1; + e1ba: 881a ldrh r2, [r3, #0] + e1bc: 4415 add r5, r2 + res->y += base->y1; + e1be: 885a ldrh r2, [r3, #2] + res->x += base->x1; + e1c0: 801d strh r5, [r3, #0] + res->y += base->y1; + e1c2: 4414 add r4, r2 + e1c4: 805c strh r4, [r3, #2] +} + e1c6: bdf0 pop {r4, r5, r6, r7, pc} + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + e1c8: 8882 ldrh r2, [r0, #4] + e1ca: 3201 adds r2, #1 + e1cc: 1b52 subs r2, r2, r5 + res->x = lv_area_get_width(base) / 2 - lv_area_get_width(to_align) / 2; + e1ce: f3c2 30c0 ubfx r0, r2, #15, #1 + e1d2: fa00 f082 sxtah r0, r0, r2 + e1d6: 888a ldrh r2, [r1, #4] + e1d8: 8809 ldrh r1, [r1, #0] + e1da: 3201 adds r2, #1 + e1dc: 1a52 subs r2, r2, r1 + e1de: f3c2 31c0 ubfx r1, r2, #15, #1 + e1e2: fa01 f282 sxtah r2, r1, r2 + e1e6: 1052 asrs r2, r2, #1 + e1e8: ebc2 0260 rsb r2, r2, r0, asr #1 + res->x = lv_area_get_width(base); + e1ec: 801a strh r2, [r3, #0] + res->y = 0; + e1ee: 2200 movs r2, #0 + e1f0: e7e2 b.n e1b8 <_lv_area_align+0x88> + res->x = lv_area_get_width(base) - lv_area_get_width(to_align); + e1f2: 880a ldrh r2, [r1, #0] + e1f4: 8889 ldrh r1, [r1, #4] + e1f6: 1a52 subs r2, r2, r1 + e1f8: 8881 ldrh r1, [r0, #4] + e1fa: 440a add r2, r1 + e1fc: 1b52 subs r2, r2, r5 + e1fe: e7f5 b.n e1ec <_lv_area_align+0xbc> + res->x = 0; + e200: 2200 movs r2, #0 + res->x = lv_area_get_width(base); + e202: 801a strh r2, [r3, #0] + res->y = lv_area_get_height(base) - lv_area_get_height(to_align); + e204: 884a ldrh r2, [r1, #2] + e206: 88c9 ldrh r1, [r1, #6] + e208: 1a52 subs r2, r2, r1 + e20a: 88c1 ldrh r1, [r0, #6] + e20c: 440a add r2, r1 + e20e: e047 b.n e2a0 <_lv_area_align+0x170> + e210: 8882 ldrh r2, [r0, #4] + e212: 880f ldrh r7, [r1, #0] + e214: 3201 adds r2, #1 + e216: 1b52 subs r2, r2, r5 + res->x = lv_area_get_width(base) / 2 - lv_area_get_width(to_align) / 2; + e218: f3c2 36c0 ubfx r6, r2, #15, #1 + e21c: fa06 f682 sxtah r6, r6, r2 + e220: 888a ldrh r2, [r1, #4] + e222: 3201 adds r2, #1 + e224: 1bd2 subs r2, r2, r7 + e226: f3c2 37c0 ubfx r7, r2, #15, #1 + e22a: fa07 f282 sxtah r2, r7, r2 + e22e: 1052 asrs r2, r2, #1 + e230: ebc2 0266 rsb r2, r2, r6, asr #1 + e234: e7e5 b.n e202 <_lv_area_align+0xd2> + res->x = lv_area_get_width(base) - lv_area_get_width(to_align); + e236: 888e ldrh r6, [r1, #4] + e238: 880a ldrh r2, [r1, #0] + e23a: 1b92 subs r2, r2, r6 + e23c: 8886 ldrh r6, [r0, #4] + e23e: 4432 add r2, r6 + e240: 1b52 subs r2, r2, r5 + e242: e7de b.n e202 <_lv_area_align+0xd2> + res->x = 0; + e244: 2200 movs r2, #0 + e246: e7a1 b.n e18c <_lv_area_align+0x5c> + res->x = lv_area_get_width(base) - lv_area_get_width(to_align); + e248: 888e ldrh r6, [r1, #4] + e24a: 880a ldrh r2, [r1, #0] + e24c: 1b92 subs r2, r2, r6 + e24e: 8886 ldrh r6, [r0, #4] + e250: 4432 add r2, r6 + e252: 1b52 subs r2, r2, r5 + e254: e79a b.n e18c <_lv_area_align+0x5c> + res->x = 0; + e256: 2200 movs r2, #0 + res->x = lv_area_get_width(base) - lv_area_get_width(to_align); + e258: 801a strh r2, [r3, #0] + res->y = -lv_area_get_height(to_align); + e25a: 884a ldrh r2, [r1, #2] + e25c: 88c9 ldrh r1, [r1, #6] + e25e: 3a01 subs r2, #1 + e260: 1a52 subs r2, r2, r1 + e262: e7a9 b.n e1b8 <_lv_area_align+0x88> + e264: 8882 ldrh r2, [r0, #4] + e266: 880e ldrh r6, [r1, #0] + e268: 3201 adds r2, #1 + e26a: 1b52 subs r2, r2, r5 + res->x = lv_area_get_width(base) / 2 - lv_area_get_width(to_align) / 2; + e26c: f3c2 30c0 ubfx r0, r2, #15, #1 + e270: fa00 f082 sxtah r0, r0, r2 + e274: 888a ldrh r2, [r1, #4] + e276: 3201 adds r2, #1 + e278: 1b92 subs r2, r2, r6 + e27a: f3c2 36c0 ubfx r6, r2, #15, #1 + e27e: fa06 f282 sxtah r2, r6, r2 + e282: 1052 asrs r2, r2, #1 + e284: ebc2 0260 rsb r2, r2, r0, asr #1 + e288: e7e6 b.n e258 <_lv_area_align+0x128> + res->x = lv_area_get_width(base) - lv_area_get_width(to_align); + e28a: 880a ldrh r2, [r1, #0] + e28c: 888e ldrh r6, [r1, #4] + e28e: 8880 ldrh r0, [r0, #4] + e290: 1b92 subs r2, r2, r6 + e292: 4402 add r2, r0 + e294: 1b52 subs r2, r2, r5 + e296: e7df b.n e258 <_lv_area_align+0x128> + res->x = 0; + e298: 2200 movs r2, #0 + res->x = lv_area_get_width(base) - lv_area_get_width(to_align); + e29a: 801a strh r2, [r3, #0] + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + e29c: 88c2 ldrh r2, [r0, #6] + e29e: 3201 adds r2, #1 + res->y = lv_area_get_height(base) - lv_area_get_height(to_align); + e2a0: 1b12 subs r2, r2, r4 + e2a2: e789 b.n e1b8 <_lv_area_align+0x88> + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + e2a4: 8882 ldrh r2, [r0, #4] + e2a6: 3201 adds r2, #1 + e2a8: 1b52 subs r2, r2, r5 + res->x = lv_area_get_width(base) / 2 - lv_area_get_width(to_align) / 2; + e2aa: f3c2 36c0 ubfx r6, r2, #15, #1 + e2ae: fa06 f682 sxtah r6, r6, r2 + e2b2: 888a ldrh r2, [r1, #4] + e2b4: 8809 ldrh r1, [r1, #0] + e2b6: 3201 adds r2, #1 + e2b8: 1a52 subs r2, r2, r1 + e2ba: f3c2 31c0 ubfx r1, r2, #15, #1 + e2be: fa01 f282 sxtah r2, r1, r2 + e2c2: 1052 asrs r2, r2, #1 + e2c4: ebc2 0266 rsb r2, r2, r6, asr #1 + e2c8: e7e7 b.n e29a <_lv_area_align+0x16a> + res->x = lv_area_get_width(base) - lv_area_get_width(to_align); + e2ca: 880a ldrh r2, [r1, #0] + e2cc: 8889 ldrh r1, [r1, #4] + e2ce: 1a52 subs r2, r2, r1 + e2d0: 8881 ldrh r1, [r0, #4] + e2d2: 440a add r2, r1 + e2d4: 1b52 subs r2, r2, r5 + e2d6: e7e0 b.n e29a <_lv_area_align+0x16a> + res->x = -lv_area_get_width(to_align); + e2d8: 880a ldrh r2, [r1, #0] + e2da: 8889 ldrh r1, [r1, #4] + e2dc: 3a01 subs r2, #1 + e2de: 1a52 subs r2, r2, r1 + e2e0: e784 b.n e1ec <_lv_area_align+0xbc> + res->x = -lv_area_get_width(to_align); + e2e2: 880a ldrh r2, [r1, #0] + e2e4: 888e ldrh r6, [r1, #4] + e2e6: 3a01 subs r2, #1 + e2e8: 1b92 subs r2, r2, r6 + e2ea: e74f b.n e18c <_lv_area_align+0x5c> + res->x = -lv_area_get_width(to_align); + e2ec: 880a ldrh r2, [r1, #0] + e2ee: 888e ldrh r6, [r1, #4] + e2f0: 3a01 subs r2, #1 + e2f2: 1b92 subs r2, r2, r6 + e2f4: e785 b.n e202 <_lv_area_align+0xd2> + e2f6: 8882 ldrh r2, [r0, #4] + e2f8: 3201 adds r2, #1 + e2fa: e77f b.n e1fc <_lv_area_align+0xcc> + e2fc: 8882 ldrh r2, [r0, #4] + e2fe: 3201 adds r2, #1 + e300: e7a7 b.n e252 <_lv_area_align+0x122> + e302: 8882 ldrh r2, [r0, #4] + e304: 3201 adds r2, #1 + e306: e79b b.n e240 <_lv_area_align+0x110> + +0000e308 : + +LV_ATTRIBUTE_FAST_MEM void lv_color_fill(lv_color_t * buf, lv_color_t color, uint32_t px_num) +{ +#if LV_COLOR_DEPTH == 16 + uintptr_t buf_int = (uintptr_t) buf; + if(buf_int & 0x3) { + e308: 0783 lsls r3, r0, #30 +{ + e30a: b510 push {r4, lr} + e30c: b28c uxth r4, r1 + *buf = color; + e30e: bf1c itt ne + e310: f820 1b02 strhne.w r1, [r0], #2 + buf++; + px_num--; + e314: f102 32ff addne.w r2, r2, #4294967295 ; 0xffffffff + } + + uint32_t c32 = color.full + (color.full << 16); + e318: eb04 4304 add.w r3, r4, r4, lsl #16 + uint32_t * buf32 = (uint32_t *)buf; + + while(px_num > 16) { + e31c: 2a10 cmp r2, #16 + e31e: 4601 mov r1, r0 + e320: f100 0020 add.w r0, r0, #32 + e324: d804 bhi.n e330 + e326: eb01 0242 add.w r2, r1, r2, lsl #1 + px_num -= 16; + } + + buf = (lv_color_t *)buf32; + + while(px_num) { + e32a: 428a cmp r2, r1 + e32c: d10a bne.n e344 + *buf = color; + buf++; + px_num --; + } +#endif +} + e32e: bd10 pop {r4, pc} + *buf32 = c32; + e330: e940 3308 strd r3, r3, [r0, #-32] + *buf32 = c32; + e334: e940 3306 strd r3, r3, [r0, #-24] + *buf32 = c32; + e338: e940 3304 strd r3, r3, [r0, #-16] + *buf32 = c32; + e33c: e940 3302 strd r3, r3, [r0, #-8] + px_num -= 16; + e340: 3a10 subs r2, #16 + e342: e7eb b.n e31c + *buf = color; + e344: f821 4b02 strh.w r4, [r1], #2 + px_num --; + e348: e7ef b.n e32a + +0000e34a : + + +lv_color_t lv_color_lighten(lv_color_t c, lv_opa_t lvl) +{ + e34a: b530 push {r4, r5, lr} +LV_ATTRIBUTE_FAST_MEM static inline lv_color_t lv_color_mix(lv_color_t c1, lv_color_t c2, uint8_t mix) +{ + lv_color_t ret; +#if LV_COLOR_DEPTH != 1 + /*LV_COLOR_DEPTH == 8, 16 or 32*/ + LV_COLOR_SET_R(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_R(c1) * mix + LV_COLOR_GET_R(c2) * (255 - mix))); + e34c: f1c1 04ff rsb r4, r1, #255 ; 0xff + LV_COLOR_SET_G(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_G(c1) * mix + LV_COLOR_GET_G(c2) * (255 - mix))); + e350: f3c0 1545 ubfx r5, r0, #5, #6 + e354: 4365 muls r5, r4 + e356: 233f movs r3, #63 ; 0x3f + LV_COLOR_SET_R(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_R(c1) * mix + LV_COLOR_GET_R(c2) * (255 - mix))); + e358: ebc1 1241 rsb r2, r1, r1, lsl #5 + LV_COLOR_SET_G(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_G(c1) * mix + LV_COLOR_GET_G(c2) * (255 - mix))); + e35c: fb13 5101 smlabb r1, r3, r1, r5 + LV_COLOR_SET_B(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_B(c1) * mix + LV_COLOR_GET_B(c2) * (255 - mix))); + e360: f000 031f and.w r3, r0, #31 + LV_COLOR_SET_G(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_G(c1) * mix + LV_COLOR_GET_G(c2) * (255 - mix))); + e364: f248 0581 movw r5, #32897 ; 0x8081 + LV_COLOR_SET_B(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_B(c1) * mix + LV_COLOR_GET_B(c2) * (255 - mix))); + e368: fb04 2303 mla r3, r4, r3, r2 + LV_COLOR_SET_R(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_R(c1) * mix + LV_COLOR_GET_R(c2) * (255 - mix))); + e36c: f3c0 20c4 ubfx r0, r0, #11, #5 + LV_COLOR_SET_G(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_G(c1) * mix + LV_COLOR_GET_G(c2) * (255 - mix))); + e370: 4369 muls r1, r5 + LV_COLOR_SET_B(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_B(c1) * mix + LV_COLOR_GET_B(c2) * (255 - mix))); + e372: 436b muls r3, r5 + LV_COLOR_SET_R(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_R(c1) * mix + LV_COLOR_GET_R(c2) * (255 - mix))); + e374: fb04 2000 mla r0, r4, r0, r2 + e378: f3c1 51c5 ubfx r1, r1, #23, #6 + e37c: 4368 muls r0, r5 + e37e: f3c3 53c4 ubfx r3, r3, #23, #5 + e382: ea43 1341 orr.w r3, r3, r1, lsl #5 + e386: 0dc0 lsrs r0, r0, #23 + return lv_color_mix(LV_COLOR_WHITE, c, lvl); +} + e388: ea43 20c0 orr.w r0, r3, r0, lsl #11 + e38c: bd30 pop {r4, r5, pc} + +0000e38e : + e38e: f1c1 01ff rsb r1, r1, #255 ; 0xff + + +lv_color_t lv_color_darken(lv_color_t c, lv_opa_t lvl) +{ + e392: b510 push {r4, lr} + LV_COLOR_SET_G(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_G(c1) * mix + LV_COLOR_GET_G(c2) * (255 - mix))); + e394: f3c0 1245 ubfx r2, r0, #5, #6 + LV_COLOR_SET_B(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_B(c1) * mix + LV_COLOR_GET_B(c2) * (255 - mix))); + e398: f000 031f and.w r3, r0, #31 + LV_COLOR_SET_G(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_G(c1) * mix + LV_COLOR_GET_G(c2) * (255 - mix))); + e39c: f248 0481 movw r4, #32897 ; 0x8081 + e3a0: 434a muls r2, r1 + LV_COLOR_SET_B(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_B(c1) * mix + LV_COLOR_GET_B(c2) * (255 - mix))); + e3a2: 434b muls r3, r1 + LV_COLOR_SET_R(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_R(c1) * mix + LV_COLOR_GET_R(c2) * (255 - mix))); + e3a4: f3c0 20c4 ubfx r0, r0, #11, #5 + LV_COLOR_SET_G(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_G(c1) * mix + LV_COLOR_GET_G(c2) * (255 - mix))); + e3a8: 4362 muls r2, r4 + LV_COLOR_SET_B(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_B(c1) * mix + LV_COLOR_GET_B(c2) * (255 - mix))); + e3aa: 4363 muls r3, r4 + LV_COLOR_SET_R(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_R(c1) * mix + LV_COLOR_GET_R(c2) * (255 - mix))); + e3ac: 4348 muls r0, r1 + LV_COLOR_SET_G(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_G(c1) * mix + LV_COLOR_GET_G(c2) * (255 - mix))); + e3ae: 0dd2 lsrs r2, r2, #23 + LV_COLOR_SET_R(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_R(c1) * mix + LV_COLOR_GET_R(c2) * (255 - mix))); + e3b0: 4360 muls r0, r4 + LV_COLOR_SET_B(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_B(c1) * mix + LV_COLOR_GET_B(c2) * (255 - mix))); + e3b2: 0ddb lsrs r3, r3, #23 + e3b4: ea43 1342 orr.w r3, r3, r2, lsl #5 + LV_COLOR_SET_R(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_R(c1) * mix + LV_COLOR_GET_R(c2) * (255 - mix))); + e3b8: 0dc0 lsrs r0, r0, #23 + return lv_color_mix(LV_COLOR_BLACK, c, lvl); +} + e3ba: ea43 20c0 orr.w r0, r3, r0, lsl #11 + e3be: bd10 pop {r4, pc} + +0000e3c0 : +static const char * lv_fs_get_real_path(const char * path) +{ + /* Example path: "S:/folder/file.txt" + * Leave the letter and the : / \ characters*/ + + path++; /*Ignore the driver letter*/ + e3c0: 1c43 adds r3, r0, #1 + e3c2: 4618 mov r0, r3 + + while(*path != '\0') { + e3c4: f813 2b01 ldrb.w r2, [r3], #1 + e3c8: b12a cbz r2, e3d6 + if(*path == ':' || *path == '\\' || *path == '/') { + e3ca: 2a3a cmp r2, #58 ; 0x3a + e3cc: d0f9 beq.n e3c2 + e3ce: 2a5c cmp r2, #92 ; 0x5c + e3d0: d0f7 beq.n e3c2 + e3d2: 2a2f cmp r2, #47 ; 0x2f + e3d4: d0f5 beq.n e3c2 + break; + } + } + + return path; +} + e3d6: 4770 bx lr + +0000e3d8 <_lv_fs_init>: + _lv_ll_init(&LV_GC_ROOT(_lv_drv_ll), sizeof(lv_fs_drv_t)); + e3d8: 4801 ldr r0, [pc, #4] ; (e3e0 <_lv_fs_init+0x8>) + e3da: 4b02 ldr r3, [pc, #8] ; (e3e4 <_lv_fs_init+0xc>) + e3dc: 2144 movs r1, #68 ; 0x44 + e3de: 4718 bx r3 + e3e0: 20008624 .word 0x20008624 + e3e4: 0000e605 .word 0x0000e605 + +0000e3e8 : +{ + e3e8: b538 push {r3, r4, r5, lr} + e3ea: 4604 mov r4, r0 + if(file_p->drv == NULL) { + e3ec: 6840 ldr r0, [r0, #4] + e3ee: b160 cbz r0, e40a + if(file_p->drv->close_cb == NULL) { + e3f0: 6903 ldr r3, [r0, #16] + e3f2: b163 cbz r3, e40e + lv_fs_res_t res = file_p->drv->close_cb(file_p->drv, file_p->file_d); + e3f4: 6821 ldr r1, [r4, #0] + e3f6: 4798 blx r3 + lv_mem_free(file_p->file_d); /*Clean up*/ + e3f8: 4b06 ldr r3, [pc, #24] ; (e414 ) + lv_fs_res_t res = file_p->drv->close_cb(file_p->drv, file_p->file_d); + e3fa: 4605 mov r5, r0 + lv_mem_free(file_p->file_d); /*Clean up*/ + e3fc: 6820 ldr r0, [r4, #0] + e3fe: 4798 blx r3 + file_p->file_d = NULL; + e400: 2300 movs r3, #0 + file_p->drv = NULL; + e402: e9c4 3300 strd r3, r3, [r4] +} + e406: 4628 mov r0, r5 + e408: bd38 pop {r3, r4, r5, pc} + return LV_FS_RES_INV_PARAM; + e40a: 250b movs r5, #11 + e40c: e7fb b.n e406 + return LV_FS_RES_NOT_IMP; + e40e: 2509 movs r5, #9 + e410: e7f9 b.n e406 + e412: bf00 nop + e414: 0000eae5 .word 0x0000eae5 + +0000e418 : +{ + e418: b57f push {r0, r1, r2, r3, r4, r5, r6, lr} + e41a: 4605 mov r5, r0 + if(br != NULL) *br = 0; + e41c: 461c mov r4, r3 + e41e: b10b cbz r3, e424 + e420: 2300 movs r3, #0 + e422: 6023 str r3, [r4, #0] + if(file_p->drv == NULL) return LV_FS_RES_INV_PARAM; + e424: 6868 ldr r0, [r5, #4] + e426: b170 cbz r0, e446 + if(file_p->drv->read_cb == NULL) return LV_FS_RES_NOT_IMP; + e428: 6986 ldr r6, [r0, #24] + e42a: b176 cbz r6, e44a + uint32_t br_tmp = 0; + e42c: 2300 movs r3, #0 + e42e: 9303 str r3, [sp, #12] + lv_fs_res_t res = file_p->drv->read_cb(file_p->drv, file_p->file_d, buf, btr, &br_tmp); + e430: ab03 add r3, sp, #12 + e432: 9300 str r3, [sp, #0] + e434: 4613 mov r3, r2 + e436: 460a mov r2, r1 + e438: 6829 ldr r1, [r5, #0] + e43a: 47b0 blx r6 + if(br != NULL) *br = br_tmp; + e43c: b10c cbz r4, e442 + e43e: 9b03 ldr r3, [sp, #12] + e440: 6023 str r3, [r4, #0] +} + e442: b004 add sp, #16 + e444: bd70 pop {r4, r5, r6, pc} + if(file_p->drv == NULL) return LV_FS_RES_INV_PARAM; + e446: 200b movs r0, #11 + e448: e7fb b.n e442 + if(file_p->drv->read_cb == NULL) return LV_FS_RES_NOT_IMP; + e44a: 2009 movs r0, #9 + e44c: e7f9 b.n e442 + +0000e44e : + if(file_p->drv == NULL) { + e44e: 6843 ldr r3, [r0, #4] +{ + e450: b410 push {r4} + e452: 460a mov r2, r1 + if(file_p->drv == NULL) { + e454: b13b cbz r3, e466 + if(file_p->drv->seek_cb == NULL) { + e456: 6a1c ldr r4, [r3, #32] + e458: b14c cbz r4, e46e + lv_fs_res_t res = file_p->drv->seek_cb(file_p->drv, file_p->file_d, pos); + e45a: 6801 ldr r1, [r0, #0] + e45c: 4618 mov r0, r3 + e45e: 4623 mov r3, r4 +} + e460: f85d 4b04 ldr.w r4, [sp], #4 + lv_fs_res_t res = file_p->drv->seek_cb(file_p->drv, file_p->file_d, pos); + e464: 4718 bx r3 + return LV_FS_RES_INV_PARAM; + e466: 200b movs r0, #11 +} + e468: f85d 4b04 ldr.w r4, [sp], #4 + e46c: 4770 bx lr + return LV_FS_RES_NOT_IMP; + e46e: 2009 movs r0, #9 + e470: e7fa b.n e468 + ... + +0000e474 : +{ + e474: b570 push {r4, r5, r6, lr} + _LV_LL_READ(LV_GC_ROOT(_lv_drv_ll), drv) { + e476: 4b07 ldr r3, [pc, #28] ; (e494 ) + e478: 4d07 ldr r5, [pc, #28] ; (e498 ) + e47a: 4e08 ldr r6, [pc, #32] ; (e49c ) +{ + e47c: 4604 mov r4, r0 + _LV_LL_READ(LV_GC_ROOT(_lv_drv_ll), drv) { + e47e: 4806 ldr r0, [pc, #24] ; (e498 ) + e480: 4798 blx r3 + e482: b900 cbnz r0, e486 +} + e484: bd70 pop {r4, r5, r6, pc} + if(drv->letter == letter) { + e486: 7803 ldrb r3, [r0, #0] + e488: 42a3 cmp r3, r4 + e48a: d0fb beq.n e484 + _LV_LL_READ(LV_GC_ROOT(_lv_drv_ll), drv) { + e48c: 4601 mov r1, r0 + e48e: 4628 mov r0, r5 + e490: 47b0 blx r6 + e492: e7f6 b.n e482 + e494: 0000e6a9 .word 0x0000e6a9 + e498: 20008624 .word 0x20008624 + e49c: 0000e6b5 .word 0x0000e6b5 + +0000e4a0 : + file_p->drv = NULL; + e4a0: 2300 movs r3, #0 +{ + e4a2: e92d 41f3 stmdb sp!, {r0, r1, r4, r5, r6, r7, r8, lr} + file_p->file_d = NULL; + e4a6: e9c0 3300 strd r3, r3, [r0] +{ + e4aa: 4604 mov r4, r0 + e4ac: 4617 mov r7, r2 + if(path == NULL) return LV_FS_RES_INV_PARAM; + e4ae: 460e mov r6, r1 + e4b0: 2900 cmp r1, #0 + e4b2: d043 beq.n e53c + file_p->drv = lv_fs_get_drv(letter); + e4b4: 7808 ldrb r0, [r1, #0] + e4b6: 4b23 ldr r3, [pc, #140] ; (e544 ) + e4b8: 4798 blx r3 + e4ba: 6060 str r0, [r4, #4] + if(file_p->drv == NULL) { + e4bc: b928 cbnz r0, e4ca + file_p->file_d = NULL; + e4be: 6020 str r0, [r4, #0] + return LV_FS_RES_NOT_EX; + e4c0: 2503 movs r5, #3 +} + e4c2: 4628 mov r0, r5 + e4c4: b002 add sp, #8 + e4c6: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + if(file_p->drv->ready_cb != NULL) { + e4ca: 6883 ldr r3, [r0, #8] + e4cc: b12b cbz r3, e4da + if(file_p->drv->ready_cb(file_p->drv) == false) { + e4ce: 4798 blx r3 + e4d0: b918 cbnz r0, e4da + file_p->file_d = NULL; + e4d2: e9c4 0000 strd r0, r0, [r4] + return LV_FS_RES_HW_ERR; + e4d6: 2501 movs r5, #1 + e4d8: e7f3 b.n e4c2 + file_p->file_d = lv_mem_alloc(file_p->drv->file_size); + e4da: 6863 ldr r3, [r4, #4] + e4dc: 8858 ldrh r0, [r3, #2] + e4de: 4b1a ldr r3, [pc, #104] ; (e548 ) + e4e0: 4798 blx r3 + LV_ASSERT_MEM(file_p->file_d); + e4e2: 4b1a ldr r3, [pc, #104] ; (e54c ) + file_p->file_d = lv_mem_alloc(file_p->drv->file_size); + e4e4: 6020 str r0, [r4, #0] + LV_ASSERT_MEM(file_p->file_d); + e4e6: 4798 blx r3 + e4e8: 4605 mov r5, r0 + e4ea: b960 cbnz r0, e506 + e4ec: 4b18 ldr r3, [pc, #96] ; (e550 ) + e4ee: 4919 ldr r1, [pc, #100] ; (e554 ) + e4f0: 9300 str r3, [sp, #0] + e4f2: 226f movs r2, #111 ; 0x6f + e4f4: 2003 movs r0, #3 + e4f6: 4e18 ldr r6, [pc, #96] ; (e558 ) + e4f8: 47b0 blx r6 + e4fa: 6822 ldr r2, [r4, #0] + e4fc: 4817 ldr r0, [pc, #92] ; (e55c ) + e4fe: 4918 ldr r1, [pc, #96] ; (e560 ) + e500: 462b mov r3, r5 + e502: 4788 blx r1 + e504: e7fe b.n e504 + if(file_p->file_d == NULL) { + e506: 6821 ldr r1, [r4, #0] + e508: b911 cbnz r1, e510 + file_p->drv = NULL; + e50a: 6061 str r1, [r4, #4] + return LV_FS_RES_OUT_OF_MEM; /* Out of memory */ + e50c: 250a movs r5, #10 + e50e: e7d8 b.n e4c2 + if(file_p->drv->open_cb == NULL) { + e510: f8d4 8004 ldr.w r8, [r4, #4] + e514: f8d8 500c ldr.w r5, [r8, #12] + e518: b195 cbz r5, e540 + const char * real_path = lv_fs_get_real_path(path); + e51a: 4b12 ldr r3, [pc, #72] ; (e564 ) + e51c: 4630 mov r0, r6 + e51e: 4798 blx r3 + lv_fs_res_t res = file_p->drv->open_cb(file_p->drv, file_p->file_d, real_path, mode); + e520: 463b mov r3, r7 + const char * real_path = lv_fs_get_real_path(path); + e522: 4602 mov r2, r0 + lv_fs_res_t res = file_p->drv->open_cb(file_p->drv, file_p->file_d, real_path, mode); + e524: 4640 mov r0, r8 + e526: 47a8 blx r5 + if(res != LV_FS_RES_OK) { + e528: 4605 mov r5, r0 + e52a: 2800 cmp r0, #0 + e52c: d0c9 beq.n e4c2 + lv_mem_free(file_p->file_d); + e52e: 4b0e ldr r3, [pc, #56] ; (e568 ) + e530: 6820 ldr r0, [r4, #0] + e532: 4798 blx r3 + file_p->file_d = NULL; + e534: 2300 movs r3, #0 + file_p->drv = NULL; + e536: e9c4 3300 strd r3, r3, [r4] + e53a: e7c2 b.n e4c2 + if(path == NULL) return LV_FS_RES_INV_PARAM; + e53c: 250b movs r5, #11 + e53e: e7c0 b.n e4c2 + return LV_FS_RES_NOT_IMP; + e540: 2509 movs r5, #9 + e542: e7be b.n e4c2 + e544: 0000e475 .word 0x0000e475 + e548: 0000ea2d .word 0x0000ea2d + e54c: 000017e1 .word 0x000017e1 + e550: 00023f6d .word 0x00023f6d + e554: 00023f2c .word 0x00023f2c + e558: 0000e8e9 .word 0x0000e8e9 + e55c: 0001edbe .word 0x0001edbe + e560: 000017e9 .word 0x000017e9 + e564: 0000e3c1 .word 0x0000e3c1 + e568: 0000eae5 .word 0x0000eae5 + +0000e56c : +{ + e56c: b510 push {r4, lr} + for(i = strlen(fn); i > 0; i--) { + e56e: 4b09 ldr r3, [pc, #36] ; (e594 ) +{ + e570: 4604 mov r4, r0 + for(i = strlen(fn); i > 0; i--) { + e572: 4798 blx r3 + e574: b908 cbnz r0, e57a + return ""; /*No extension if a '\' or '/' found*/ + e576: 4808 ldr r0, [pc, #32] ; (e598 ) + e578: e004 b.n e584 + if(fn[i] == '.') { + e57a: 5c23 ldrb r3, [r4, r0] + e57c: 2b2e cmp r3, #46 ; 0x2e + e57e: d102 bne.n e586 + return &fn[i + 1]; + e580: 3001 adds r0, #1 + e582: 4420 add r0, r4 +} + e584: bd10 pop {r4, pc} + else if(fn[i] == '/' || fn[i] == '\\') { + e586: 2b2f cmp r3, #47 ; 0x2f + e588: d0f5 beq.n e576 + e58a: 2b5c cmp r3, #92 ; 0x5c + e58c: d0f3 beq.n e576 + for(i = strlen(fn); i > 0; i--) { + e58e: 3801 subs r0, #1 + e590: e7f0 b.n e574 + e592: bf00 nop + e594: 00016339 .word 0x00016339 + e598: 0001f7d8 .word 0x0001f7d8 + +0000e59c <_lv_memcpy_small.constprop.0.isra.0>: + while(len) { + e59c: 3901 subs r1, #1 + e59e: 1d03 adds r3, r0, #4 + *d8 = *s8; + e5a0: f811 2f01 ldrb.w r2, [r1, #1]! + e5a4: f800 2b01 strb.w r2, [r0], #1 + while(len) { + e5a8: 4298 cmp r0, r3 + e5aa: d1f9 bne.n e5a0 <_lv_memcpy_small.constprop.0.isra.0+0x4> + s8++; + len--; + } + + return dst; +} + e5ac: 4770 bx lr + ... + +0000e5b0 : + * @param ll_p pointer to linked list + * @param act pointer to a node which prev. node pointer should be set + * @param prev pointer to a node which should be the previous node before 'act' + */ +static void node_set_prev(lv_ll_t * ll_p, lv_ll_node_t * act, lv_ll_node_t * prev) +{ + e5b0: b507 push {r0, r1, r2, lr} + e5b2: 9201 str r2, [sp, #4] + if(act == NULL) return; /*Can't set the prev node of `NULL`*/ + e5b4: b129 cbz r1, e5c2 + + uint32_t node_p_size = sizeof(lv_ll_node_t *); + if(prev) + _lv_memcpy_small(act + LL_PREV_P_OFFSET(ll_p), &prev, node_p_size); + e5b6: 6800 ldr r0, [r0, #0] + e5b8: 4408 add r0, r1 + if(prev) + e5ba: b12a cbz r2, e5c8 + _lv_memcpy_small(act + LL_PREV_P_OFFSET(ll_p), &prev, node_p_size); + e5bc: 4b04 ldr r3, [pc, #16] ; (e5d0 ) + e5be: a901 add r1, sp, #4 + e5c0: 4798 blx r3 + else + _lv_memset_00(act + LL_PREV_P_OFFSET(ll_p), node_p_size); +} + e5c2: b003 add sp, #12 + e5c4: f85d fb04 ldr.w pc, [sp], #4 + _lv_memset_00(act + LL_PREV_P_OFFSET(ll_p), node_p_size); + e5c8: 4b02 ldr r3, [pc, #8] ; (e5d4 ) + e5ca: 2104 movs r1, #4 + e5cc: 4798 blx r3 + e5ce: e7f8 b.n e5c2 + e5d0: 0000e59d .word 0x0000e59d + e5d4: 0000f019 .word 0x0000f019 + +0000e5d8 : + * @param ll_p pointer to linked list + * @param act pointer to a node which next node pointer should be set + * @param next pointer to a node which should be the next node before 'act' + */ +static void node_set_next(lv_ll_t * ll_p, lv_ll_node_t * act, lv_ll_node_t * next) +{ + e5d8: b507 push {r0, r1, r2, lr} + e5da: 9201 str r2, [sp, #4] + if(act == NULL) return; /*Can't set the next node of `NULL`*/ + e5dc: b131 cbz r1, e5ec + + uint32_t node_p_size = sizeof(lv_ll_node_t *); + if(next) + _lv_memcpy_small(act + LL_NEXT_P_OFFSET(ll_p), &next, node_p_size); + e5de: 6803 ldr r3, [r0, #0] + e5e0: 3304 adds r3, #4 + e5e2: 18c8 adds r0, r1, r3 + if(next) + e5e4: b12a cbz r2, e5f2 + _lv_memcpy_small(act + LL_NEXT_P_OFFSET(ll_p), &next, node_p_size); + e5e6: 4b05 ldr r3, [pc, #20] ; (e5fc ) + e5e8: a901 add r1, sp, #4 + e5ea: 4798 blx r3 + else + _lv_memset_00(act + LL_NEXT_P_OFFSET(ll_p), node_p_size); +} + e5ec: b003 add sp, #12 + e5ee: f85d fb04 ldr.w pc, [sp], #4 + _lv_memset_00(act + LL_NEXT_P_OFFSET(ll_p), node_p_size); + e5f2: 4b03 ldr r3, [pc, #12] ; (e600 ) + e5f4: 2104 movs r1, #4 + e5f6: 4798 blx r3 + e5f8: e7f8 b.n e5ec + e5fa: bf00 nop + e5fc: 0000e59d .word 0x0000e59d + e600: 0000f019 .word 0x0000f019 + +0000e604 <_lv_ll_init>: + ll_p->head = NULL; + e604: 2300 movs r3, #0 + ll_p->tail = NULL; + e606: e9c0 3301 strd r3, r3, [r0, #4] + if(node_size & 0x3) { + e60a: 078b lsls r3, r1, #30 + node_size = node_size & (~0x3); + e60c: bf1c itt ne + e60e: f021 0103 bicne.w r1, r1, #3 + node_size += 4; + e612: 3104 addne r1, #4 + ll_p->n_size = node_size; + e614: 6001 str r1, [r0, #0] +} + e616: 4770 bx lr + +0000e618 <_lv_ll_ins_head>: +{ + e618: b570 push {r4, r5, r6, lr} + e61a: 4604 mov r4, r0 + n_new = lv_mem_alloc(ll_p->n_size + LL_NODE_META_SIZE); + e61c: 6800 ldr r0, [r0, #0] + e61e: 4b0d ldr r3, [pc, #52] ; (e654 <_lv_ll_ins_head+0x3c>) + e620: 3008 adds r0, #8 + e622: 4798 blx r3 + if(n_new != NULL) { + e624: 4605 mov r5, r0 + e626: b190 cbz r0, e64e <_lv_ll_ins_head+0x36> + node_set_prev(ll_p, n_new, NULL); /*No prev. before the new head*/ + e628: 4601 mov r1, r0 + e62a: 2200 movs r2, #0 + e62c: 4620 mov r0, r4 + e62e: 4e0a ldr r6, [pc, #40] ; (e658 <_lv_ll_ins_head+0x40>) + e630: 47b0 blx r6 + node_set_next(ll_p, n_new, ll_p->head); /*After new comes the old head*/ + e632: 4629 mov r1, r5 + e634: 6862 ldr r2, [r4, #4] + e636: 4b09 ldr r3, [pc, #36] ; (e65c <_lv_ll_ins_head+0x44>) + e638: 4620 mov r0, r4 + e63a: 4798 blx r3 + if(ll_p->head != NULL) { /*If there is old head then before it goes the new*/ + e63c: 6861 ldr r1, [r4, #4] + e63e: b111 cbz r1, e646 <_lv_ll_ins_head+0x2e> + node_set_prev(ll_p, ll_p->head, n_new); + e640: 462a mov r2, r5 + e642: 4620 mov r0, r4 + e644: 47b0 blx r6 + if(ll_p->tail == NULL) { /*If there is no tail (1. node) set the tail too*/ + e646: 68a3 ldr r3, [r4, #8] + ll_p->head = n_new; /*Set the new head in the dsc.*/ + e648: 6065 str r5, [r4, #4] + if(ll_p->tail == NULL) { /*If there is no tail (1. node) set the tail too*/ + e64a: b903 cbnz r3, e64e <_lv_ll_ins_head+0x36> + ll_p->tail = n_new; + e64c: 60a5 str r5, [r4, #8] +} + e64e: 4628 mov r0, r5 + e650: bd70 pop {r4, r5, r6, pc} + e652: bf00 nop + e654: 0000ea2d .word 0x0000ea2d + e658: 0000e5b1 .word 0x0000e5b1 + e65c: 0000e5d9 .word 0x0000e5d9 + +0000e660 <_lv_ll_ins_tail>: +{ + e660: b570 push {r4, r5, r6, lr} + e662: 4604 mov r4, r0 + n_new = lv_mem_alloc(ll_p->n_size + LL_NODE_META_SIZE); + e664: 6800 ldr r0, [r0, #0] + e666: 4b0d ldr r3, [pc, #52] ; (e69c <_lv_ll_ins_tail+0x3c>) + e668: 3008 adds r0, #8 + e66a: 4798 blx r3 + if(n_new != NULL) { + e66c: 4605 mov r5, r0 + e66e: b190 cbz r0, e696 <_lv_ll_ins_tail+0x36> + node_set_next(ll_p, n_new, NULL); /*No next after the new tail*/ + e670: 4601 mov r1, r0 + e672: 2200 movs r2, #0 + e674: 4620 mov r0, r4 + e676: 4e0a ldr r6, [pc, #40] ; (e6a0 <_lv_ll_ins_tail+0x40>) + e678: 47b0 blx r6 + node_set_prev(ll_p, n_new, ll_p->tail); /*The prev. before new is tho old tail*/ + e67a: 4629 mov r1, r5 + e67c: 68a2 ldr r2, [r4, #8] + e67e: 4b09 ldr r3, [pc, #36] ; (e6a4 <_lv_ll_ins_tail+0x44>) + e680: 4620 mov r0, r4 + e682: 4798 blx r3 + if(ll_p->tail != NULL) { /*If there is old tail then the new comes after it*/ + e684: 68a1 ldr r1, [r4, #8] + e686: b111 cbz r1, e68e <_lv_ll_ins_tail+0x2e> + node_set_next(ll_p, ll_p->tail, n_new); + e688: 462a mov r2, r5 + e68a: 4620 mov r0, r4 + e68c: 47b0 blx r6 + if(ll_p->head == NULL) { /*If there is no head (1. node) set the head too*/ + e68e: 6863 ldr r3, [r4, #4] + ll_p->tail = n_new; /*Set the new tail in the dsc.*/ + e690: 60a5 str r5, [r4, #8] + if(ll_p->head == NULL) { /*If there is no head (1. node) set the head too*/ + e692: b903 cbnz r3, e696 <_lv_ll_ins_tail+0x36> + ll_p->head = n_new; + e694: 6065 str r5, [r4, #4] +} + e696: 4628 mov r0, r5 + e698: bd70 pop {r4, r5, r6, pc} + e69a: bf00 nop + e69c: 0000ea2d .word 0x0000ea2d + e6a0: 0000e5d9 .word 0x0000e5d9 + e6a4: 0000e5b1 .word 0x0000e5b1 + +0000e6a8 <_lv_ll_get_head>: + if(ll_p != NULL) { + e6a8: b100 cbz r0, e6ac <_lv_ll_get_head+0x4> + head = ll_p->head; + e6aa: 6840 ldr r0, [r0, #4] +} + e6ac: 4770 bx lr + +0000e6ae <_lv_ll_get_tail>: + if(ll_p != NULL) { + e6ae: b100 cbz r0, e6b2 <_lv_ll_get_tail+0x4> + tail = ll_p->tail; + e6b0: 6880 ldr r0, [r0, #8] +} + e6b2: 4770 bx lr + +0000e6b4 <_lv_ll_get_next>: +{ + e6b4: b507 push {r0, r1, r2, lr} + void * next = NULL; + e6b6: 2300 movs r3, #0 + e6b8: 9301 str r3, [sp, #4] + if(ll_p != NULL) { + e6ba: b128 cbz r0, e6c8 <_lv_ll_get_next+0x14> + _lv_memcpy_small(&next, n_act_d + LL_NEXT_P_OFFSET(ll_p), sizeof(void *)); + e6bc: 6803 ldr r3, [r0, #0] + e6be: 3304 adds r3, #4 + e6c0: 4419 add r1, r3 + e6c2: a801 add r0, sp, #4 + e6c4: 4b02 ldr r3, [pc, #8] ; (e6d0 <_lv_ll_get_next+0x1c>) + e6c6: 4798 blx r3 +} + e6c8: 9801 ldr r0, [sp, #4] + e6ca: b003 add sp, #12 + e6cc: f85d fb04 ldr.w pc, [sp], #4 + e6d0: 0000e59d .word 0x0000e59d + +0000e6d4 <_lv_ll_get_prev>: +{ + e6d4: b507 push {r0, r1, r2, lr} + void * prev = NULL; + e6d6: 2300 movs r3, #0 + e6d8: 9301 str r3, [sp, #4] + if(ll_p != NULL) { + e6da: b120 cbz r0, e6e6 <_lv_ll_get_prev+0x12> + _lv_memcpy_small(&prev, n_act_d + LL_PREV_P_OFFSET(ll_p), sizeof(void *)); + e6dc: 6803 ldr r3, [r0, #0] + e6de: a801 add r0, sp, #4 + e6e0: 4419 add r1, r3 + e6e2: 4b03 ldr r3, [pc, #12] ; (e6f0 <_lv_ll_get_prev+0x1c>) + e6e4: 4798 blx r3 +} + e6e6: 9801 ldr r0, [sp, #4] + e6e8: b003 add sp, #12 + e6ea: f85d fb04 ldr.w pc, [sp], #4 + e6ee: bf00 nop + e6f0: 0000e59d .word 0x0000e59d + +0000e6f4 <_lv_ll_ins_prev>: +{ + e6f4: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + e6f8: 460e mov r6, r1 + if(NULL == ll_p || NULL == n_act) return NULL; + e6fa: 4604 mov r4, r0 + e6fc: b340 cbz r0, e750 <_lv_ll_ins_prev+0x5c> + e6fe: b349 cbz r1, e754 <_lv_ll_ins_prev+0x60> + if(_lv_ll_get_head(ll_p) == n_act) { + e700: 6843 ldr r3, [r0, #4] + e702: 4299 cmp r1, r3 + e704: d103 bne.n e70e <_lv_ll_ins_prev+0x1a> +} + e706: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} + n_new = _lv_ll_ins_head(ll_p); + e70a: 4b13 ldr r3, [pc, #76] ; (e758 <_lv_ll_ins_prev+0x64>) + e70c: 4718 bx r3 + n_new = lv_mem_alloc(ll_p->n_size + LL_NODE_META_SIZE); + e70e: 6800 ldr r0, [r0, #0] + e710: 4b12 ldr r3, [pc, #72] ; (e75c <_lv_ll_ins_prev+0x68>) + e712: 3008 adds r0, #8 + e714: 4798 blx r3 + if(n_new == NULL) return NULL; + e716: 4605 mov r5, r0 + e718: b1b8 cbz r0, e74a <_lv_ll_ins_prev+0x56> + n_prev = _lv_ll_get_prev(ll_p, n_act); + e71a: 4b11 ldr r3, [pc, #68] ; (e760 <_lv_ll_ins_prev+0x6c>) + node_set_next(ll_p, n_prev, n_new); + e71c: f8df 8048 ldr.w r8, [pc, #72] ; e768 <_lv_ll_ins_prev+0x74> + n_prev = _lv_ll_get_prev(ll_p, n_act); + e720: 4631 mov r1, r6 + e722: 4620 mov r0, r4 + e724: 4798 blx r3 + node_set_next(ll_p, n_prev, n_new); + e726: 462a mov r2, r5 + n_prev = _lv_ll_get_prev(ll_p, n_act); + e728: 4607 mov r7, r0 + node_set_next(ll_p, n_prev, n_new); + e72a: 4601 mov r1, r0 + e72c: 4620 mov r0, r4 + e72e: 47c0 blx r8 + node_set_prev(ll_p, n_new, n_prev); + e730: 463a mov r2, r7 + e732: 4629 mov r1, r5 + e734: 4f0b ldr r7, [pc, #44] ; (e764 <_lv_ll_ins_prev+0x70>) + e736: 4620 mov r0, r4 + e738: 47b8 blx r7 + node_set_prev(ll_p, n_act, n_new); + e73a: 462a mov r2, r5 + e73c: 4631 mov r1, r6 + e73e: 4620 mov r0, r4 + e740: 47b8 blx r7 + node_set_next(ll_p, n_new, n_act); + e742: 4632 mov r2, r6 + e744: 4629 mov r1, r5 + e746: 4620 mov r0, r4 + e748: 47c0 blx r8 +} + e74a: 4628 mov r0, r5 + e74c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + if(NULL == ll_p || NULL == n_act) return NULL; + e750: 4605 mov r5, r0 + e752: e7fa b.n e74a <_lv_ll_ins_prev+0x56> + e754: 460d mov r5, r1 + e756: e7f8 b.n e74a <_lv_ll_ins_prev+0x56> + e758: 0000e619 .word 0x0000e619 + e75c: 0000ea2d .word 0x0000ea2d + e760: 0000e6d5 .word 0x0000e6d5 + e764: 0000e5b1 .word 0x0000e5b1 + e768: 0000e5d9 .word 0x0000e5d9 + +0000e76c <_lv_ll_remove>: +{ + e76c: b570 push {r4, r5, r6, lr} + e76e: 460d mov r5, r1 + if(ll_p != NULL) { + e770: 4604 mov r4, r0 + e772: b1f8 cbz r0, e7b4 <_lv_ll_remove+0x48> + if(_lv_ll_get_head(ll_p) == node_p) { + e774: 6843 ldr r3, [r0, #4] + e776: 4299 cmp r1, r3 + e778: d10c bne.n e794 <_lv_ll_remove+0x28> + ll_p->head = _lv_ll_get_next(ll_p, node_p); + e77a: 4629 mov r1, r5 + e77c: 4b17 ldr r3, [pc, #92] ; (e7dc <_lv_ll_remove+0x70>) + e77e: 4620 mov r0, r4 + e780: 4798 blx r3 + e782: 4601 mov r1, r0 + e784: 6060 str r0, [r4, #4] + if(ll_p->head == NULL) { + e786: b908 cbnz r0, e78c <_lv_ll_remove+0x20> + ll_p->tail = NULL; + e788: 60a0 str r0, [r4, #8] +} + e78a: bd70 pop {r4, r5, r6, pc} + node_set_prev(ll_p, ll_p->head, NULL); + e78c: 2200 movs r2, #0 + node_set_prev(ll_p, n_next, n_prev); + e78e: 4b14 ldr r3, [pc, #80] ; (e7e0 <_lv_ll_remove+0x74>) + e790: 4620 mov r0, r4 + e792: e00c b.n e7ae <_lv_ll_remove+0x42> + else if(_lv_ll_get_tail(ll_p) == node_p) { + e794: 6883 ldr r3, [r0, #8] + e796: 4299 cmp r1, r3 + e798: d10e bne.n e7b8 <_lv_ll_remove+0x4c> + ll_p->tail = _lv_ll_get_prev(ll_p, node_p); + e79a: 4b12 ldr r3, [pc, #72] ; (e7e4 <_lv_ll_remove+0x78>) + e79c: 4798 blx r3 + e79e: 4601 mov r1, r0 + e7a0: 60a0 str r0, [r4, #8] + if(ll_p->tail == NULL) { + e7a2: b908 cbnz r0, e7a8 <_lv_ll_remove+0x3c> + ll_p->head = NULL; + e7a4: 6060 str r0, [r4, #4] + e7a6: e7f0 b.n e78a <_lv_ll_remove+0x1e> + node_set_next(ll_p, ll_p->tail, NULL); + e7a8: 4b0f ldr r3, [pc, #60] ; (e7e8 <_lv_ll_remove+0x7c>) + e7aa: 2200 movs r2, #0 + e7ac: 4620 mov r0, r4 +} + e7ae: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + node_set_prev(ll_p, n_next, n_prev); + e7b2: 4718 bx r3 + if(_lv_ll_get_head(ll_p) == node_p) { + e7b4: 2900 cmp r1, #0 + e7b6: d0e0 beq.n e77a <_lv_ll_remove+0xe> + lv_ll_node_t * n_prev = _lv_ll_get_prev(ll_p, node_p); + e7b8: 4629 mov r1, r5 + e7ba: 4b0a ldr r3, [pc, #40] ; (e7e4 <_lv_ll_remove+0x78>) + e7bc: 4620 mov r0, r4 + e7be: 4798 blx r3 + lv_ll_node_t * n_next = _lv_ll_get_next(ll_p, node_p); + e7c0: 4629 mov r1, r5 + lv_ll_node_t * n_prev = _lv_ll_get_prev(ll_p, node_p); + e7c2: 4606 mov r6, r0 + lv_ll_node_t * n_next = _lv_ll_get_next(ll_p, node_p); + e7c4: 4b05 ldr r3, [pc, #20] ; (e7dc <_lv_ll_remove+0x70>) + e7c6: 4620 mov r0, r4 + e7c8: 4798 blx r3 + node_set_next(ll_p, n_prev, n_next); + e7ca: 4631 mov r1, r6 + e7cc: 4602 mov r2, r0 + lv_ll_node_t * n_next = _lv_ll_get_next(ll_p, node_p); + e7ce: 4605 mov r5, r0 + node_set_next(ll_p, n_prev, n_next); + e7d0: 4b05 ldr r3, [pc, #20] ; (e7e8 <_lv_ll_remove+0x7c>) + e7d2: 4620 mov r0, r4 + e7d4: 4798 blx r3 + node_set_prev(ll_p, n_next, n_prev); + e7d6: 4632 mov r2, r6 + e7d8: 4629 mov r1, r5 + e7da: e7d8 b.n e78e <_lv_ll_remove+0x22> + e7dc: 0000e6b5 .word 0x0000e6b5 + e7e0: 0000e5b1 .word 0x0000e5b1 + e7e4: 0000e6d5 .word 0x0000e6d5 + e7e8: 0000e5d9 .word 0x0000e5d9 + +0000e7ec <_lv_ll_chg_list>: +{ + e7ec: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + e7f0: 460c mov r4, r1 + e7f2: 461e mov r6, r3 + _lv_ll_remove(ll_ori_p, node); + e7f4: 4611 mov r1, r2 + e7f6: 4b16 ldr r3, [pc, #88] ; (e850 <_lv_ll_chg_list+0x64>) + e7f8: f8df 805c ldr.w r8, [pc, #92] ; e858 <_lv_ll_chg_list+0x6c> + e7fc: 4f15 ldr r7, [pc, #84] ; (e854 <_lv_ll_chg_list+0x68>) +{ + e7fe: 4615 mov r5, r2 + _lv_ll_remove(ll_ori_p, node); + e800: 4798 blx r3 + if(head) { + e802: b196 cbz r6, e82a <_lv_ll_chg_list+0x3e> + node_set_prev(ll_new_p, node, NULL); + e804: 2200 movs r2, #0 + e806: 4629 mov r1, r5 + e808: 4620 mov r0, r4 + e80a: 47c0 blx r8 + node_set_next(ll_new_p, node, ll_new_p->head); + e80c: 4629 mov r1, r5 + e80e: 6862 ldr r2, [r4, #4] + e810: 4620 mov r0, r4 + e812: 47b8 blx r7 + if(ll_new_p->head != NULL) { /*If there is old head then before it goes the new*/ + e814: 6861 ldr r1, [r4, #4] + e816: b111 cbz r1, e81e <_lv_ll_chg_list+0x32> + node_set_prev(ll_new_p, ll_new_p->head, node); + e818: 462a mov r2, r5 + e81a: 4620 mov r0, r4 + e81c: 47c0 blx r8 + if(ll_new_p->tail == NULL) { /*If there is no tail (first node) set the tail too*/ + e81e: 68a3 ldr r3, [r4, #8] + ll_new_p->head = node; /*Set the new head in the dsc.*/ + e820: 6065 str r5, [r4, #4] + if(ll_new_p->tail == NULL) { /*If there is no tail (first node) set the tail too*/ + e822: b903 cbnz r3, e826 <_lv_ll_chg_list+0x3a> + ll_new_p->tail = node; + e824: 60a5 str r5, [r4, #8] +} + e826: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + node_set_prev(ll_new_p, node, ll_new_p->tail); + e82a: 68a2 ldr r2, [r4, #8] + e82c: 4629 mov r1, r5 + e82e: 4620 mov r0, r4 + e830: 47c0 blx r8 + node_set_next(ll_new_p, node, NULL); + e832: 4629 mov r1, r5 + e834: 4632 mov r2, r6 + e836: 4620 mov r0, r4 + e838: 47b8 blx r7 + if(ll_new_p->tail != NULL) { /*If there is old tail then after it goes the new*/ + e83a: 68a1 ldr r1, [r4, #8] + e83c: b111 cbz r1, e844 <_lv_ll_chg_list+0x58> + node_set_next(ll_new_p, ll_new_p->tail, node); + e83e: 462a mov r2, r5 + e840: 4620 mov r0, r4 + e842: 47b8 blx r7 + if(ll_new_p->head == NULL) { /*If there is no head (first node) set the head too*/ + e844: 6863 ldr r3, [r4, #4] + ll_new_p->tail = node; /*Set the new tail in the dsc.*/ + e846: 60a5 str r5, [r4, #8] + if(ll_new_p->head == NULL) { /*If there is no head (first node) set the head too*/ + e848: 2b00 cmp r3, #0 + e84a: d1ec bne.n e826 <_lv_ll_chg_list+0x3a> + ll_new_p->head = node; + e84c: 6065 str r5, [r4, #4] +} + e84e: e7ea b.n e826 <_lv_ll_chg_list+0x3a> + e850: 0000e76d .word 0x0000e76d + e854: 0000e5d9 .word 0x0000e5d9 + e858: 0000e5b1 .word 0x0000e5b1 + +0000e85c <_lv_ll_move_before>: + if(n_act == n_after) return; /*Can't move before itself*/ + e85c: 4291 cmp r1, r2 +{ + e85e: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + e862: 4604 mov r4, r0 + e864: 460d mov r5, r1 + e866: 4617 mov r7, r2 + if(n_act == n_after) return; /*Can't move before itself*/ + e868: d022 beq.n e8b0 <_lv_ll_move_before+0x54> + if(n_after != NULL) + e86a: b31a cbz r2, e8b4 <_lv_ll_move_before+0x58> + n_before = _lv_ll_get_prev(ll_p, n_after); + e86c: 4b14 ldr r3, [pc, #80] ; (e8c0 <_lv_ll_move_before+0x64>) + e86e: 4611 mov r1, r2 + e870: 4798 blx r3 + e872: 4606 mov r6, r0 + if(n_act == n_before) return; /*Already before `n_after`*/ + e874: 42ae cmp r6, r5 + e876: d01b beq.n e8b0 <_lv_ll_move_before+0x54> + _lv_ll_remove(ll_p, n_act); + e878: 4b12 ldr r3, [pc, #72] ; (e8c4 <_lv_ll_move_before+0x68>) + node_set_next(ll_p, n_before, n_act); + e87a: f8df 804c ldr.w r8, [pc, #76] ; e8c8 <_lv_ll_move_before+0x6c> + node_set_prev(ll_p, n_act, n_before); + e87e: f8df 904c ldr.w r9, [pc, #76] ; e8cc <_lv_ll_move_before+0x70> + _lv_ll_remove(ll_p, n_act); + e882: 4629 mov r1, r5 + e884: 4620 mov r0, r4 + e886: 4798 blx r3 + node_set_next(ll_p, n_before, n_act); + e888: 462a mov r2, r5 + e88a: 4631 mov r1, r6 + e88c: 4620 mov r0, r4 + e88e: 47c0 blx r8 + node_set_prev(ll_p, n_act, n_before); + e890: 4632 mov r2, r6 + e892: 4629 mov r1, r5 + e894: 4620 mov r0, r4 + e896: 47c8 blx r9 + node_set_prev(ll_p, n_after, n_act); + e898: 462a mov r2, r5 + e89a: 4639 mov r1, r7 + e89c: 4620 mov r0, r4 + e89e: 47c8 blx r9 + node_set_next(ll_p, n_act, n_after); + e8a0: 463a mov r2, r7 + e8a2: 4629 mov r1, r5 + e8a4: 4620 mov r0, r4 + e8a6: 47c0 blx r8 + if(n_after == NULL) ll_p->tail = n_act; + e8a8: b907 cbnz r7, e8ac <_lv_ll_move_before+0x50> + e8aa: 60a5 str r5, [r4, #8] + if(n_before == NULL) ll_p->head = n_act; + e8ac: b906 cbnz r6, e8b0 <_lv_ll_move_before+0x54> + e8ae: 6065 str r5, [r4, #4] +} + e8b0: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + if(ll_p != NULL) { + e8b4: b108 cbz r0, e8ba <_lv_ll_move_before+0x5e> + tail = ll_p->tail; + e8b6: 6886 ldr r6, [r0, #8] + e8b8: e7dc b.n e874 <_lv_ll_move_before+0x18> + void * tail = NULL; + e8ba: 4606 mov r6, r0 + e8bc: e7da b.n e874 <_lv_ll_move_before+0x18> + e8be: bf00 nop + e8c0: 0000e6d5 .word 0x0000e6d5 + e8c4: 0000e76d .word 0x0000e76d + e8c8: 0000e5d9 .word 0x0000e5d9 + e8cc: 0000e5b1 .word 0x0000e5b1 + +0000e8d0 <_lv_ll_is_empty>: + if(ll_p == NULL) return true; + e8d0: b130 cbz r0, e8e0 <_lv_ll_is_empty+0x10> + if(ll_p->head == NULL && ll_p->tail == NULL) return true; + e8d2: 6843 ldr r3, [r0, #4] + e8d4: b933 cbnz r3, e8e4 <_lv_ll_is_empty+0x14> + e8d6: 6880 ldr r0, [r0, #8] + e8d8: fab0 f080 clz r0, r0 + e8dc: 0940 lsrs r0, r0, #5 + e8de: 4770 bx lr + if(ll_p == NULL) return true; + e8e0: 2001 movs r0, #1 + e8e2: 4770 bx lr + return false; + e8e4: 2000 movs r0, #0 +} + e8e6: 4770 bx lr + +0000e8e8 <_lv_log_add>: + * @param func name of the function when the log added + * @param format printf-like format string + * @param ... parameters for `format` + */ +void _lv_log_add(lv_log_level_t level, const char * file, int line, const char * func, const char * format, ...) +{ + e8e8: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} + e8ec: 461f mov r7, r3 + if(level >= _LV_LOG_LEVEL_NUM) return; /*Invalid level*/ + + if(level >= LV_LOG_LEVEL) { + e8ee: 1e43 subs r3, r0, #1 + e8f0: b2db uxtb r3, r3 + e8f2: 2b04 cmp r3, #4 +{ + e8f4: b0c5 sub sp, #276 ; 0x114 + e8f6: 4604 mov r4, r0 + e8f8: 460d mov r5, r1 + e8fa: 4616 mov r6, r2 + if(level >= LV_LOG_LEVEL) { + e8fc: d817 bhi.n e92e <_lv_log_add+0x46> + va_list args; + va_start(args, format); + e8fe: ab4d add r3, sp, #308 ; 0x134 + char buf[256]; + lv_vsnprintf(buf, sizeof(buf), format, args); + e900: f10d 0910 add.w r9, sp, #16 + e904: f8df 8030 ldr.w r8, [pc, #48] ; e938 <_lv_log_add+0x50> + va_start(args, format); + e908: 9303 str r3, [sp, #12] + lv_vsnprintf(buf, sizeof(buf), format, args); + e90a: 9a4c ldr r2, [sp, #304] ; 0x130 + e90c: f44f 7180 mov.w r1, #256 ; 0x100 + e910: 4648 mov r0, r9 + e912: 47c0 blx r8 + } + + static const char * lvl_prefix[] = {"Trace", "Info", "Warn", "Error", "User"}; + printf("%s: %s \t(%s #%d %s())\n", lvl_prefix[level], buf, &file[p], line, func); +#else + if(custom_print_cb) custom_print_cb(level, file, line, func, buf); + e914: 4b07 ldr r3, [pc, #28] ; (e934 <_lv_log_add+0x4c>) + e916: f8d3 8000 ldr.w r8, [r3] + e91a: f1b8 0f00 cmp.w r8, #0 + e91e: d006 beq.n e92e <_lv_log_add+0x46> + e920: f8cd 9000 str.w r9, [sp] + e924: 463b mov r3, r7 + e926: 4632 mov r2, r6 + e928: 4629 mov r1, r5 + e92a: 4620 mov r0, r4 + e92c: 47c0 blx r8 +#endif + } +} + e92e: b045 add sp, #276 ; 0x114 + e930: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + e934: 20008784 .word 0x20008784 + e938: 0000f821 .word 0x0000f821 + +0000e93c <_lv_trigo_sin>: + * @return sinus of 'angle'. sin(-90) = -32767, sin(90) = 32767 + */ +LV_ATTRIBUTE_FAST_MEM int16_t _lv_trigo_sin(int16_t angle) +{ + int16_t ret = 0; + angle = angle % 360; + e93c: f44f 73b4 mov.w r3, #360 ; 0x168 + e940: fb90 f2f3 sdiv r2, r0, r3 + e944: fb02 0013 mls r0, r2, r3, r0 + e948: b200 sxth r0, r0 + + if(angle < 0) angle = 360 + angle; + e94a: 2800 cmp r0, #0 + e94c: bfbc itt lt + e94e: 18c0 addlt r0, r0, r3 + e950: b200 sxthlt r0, r0 + + if(angle < 90) { + e952: 2859 cmp r0, #89 ; 0x59 + e954: 4b0e ldr r3, [pc, #56] ; (e990 <_lv_trigo_sin+0x54>) + e956: dc02 bgt.n e95e <_lv_trigo_sin+0x22> + ret = sin0_90_table[angle]; + } + else if(angle >= 90 && angle < 180) { + angle = 180 - angle; + ret = sin0_90_table[angle]; + e958: f933 0010 ldrsh.w r0, [r3, r0, lsl #1] + e95c: 4770 bx lr + else if(angle >= 90 && angle < 180) { + e95e: b280 uxth r0, r0 + e960: f1a0 025a sub.w r2, r0, #90 ; 0x5a + e964: 2a59 cmp r2, #89 ; 0x59 + e966: d803 bhi.n e970 <_lv_trigo_sin+0x34> + angle = 180 - angle; + e968: f1c0 00b4 rsb r0, r0, #180 ; 0xb4 + ret = sin0_90_table[angle]; + e96c: b280 uxth r0, r0 + e96e: e7f3 b.n e958 <_lv_trigo_sin+0x1c> + } + else if(angle >= 180 && angle < 270) { + e970: f1a0 02b4 sub.w r2, r0, #180 ; 0xb4 + e974: b292 uxth r2, r2 + e976: 2a59 cmp r2, #89 ; 0x59 + angle = angle - 180; + ret = -sin0_90_table[angle]; + } + else { /*angle >=270*/ + angle = 360 - angle; + e978: bf85 ittet hi + e97a: f5c0 70b4 rsbhi r0, r0, #360 ; 0x168 + ret = -sin0_90_table[angle]; + e97e: b280 uxthhi r0, r0 + ret = -sin0_90_table[angle]; + e980: f833 0012 ldrhls.w r0, [r3, r2, lsl #1] + ret = -sin0_90_table[angle]; + e984: f833 0010 ldrhhi.w r0, [r3, r0, lsl #1] + e988: 4240 negs r0, r0 + e98a: b200 sxth r0, r0 + } + + return ret; +} + e98c: 4770 bx lr + e98e: bf00 nop + e990: 00023f88 .word 0x00023f88 + +0000e994 <_lv_sqrt>: + * If root < 16: mask = 0x80 + * If root < 256: mask = 0x800 + * Else: mask = 0x8000 + */ +LV_ATTRIBUTE_FAST_MEM void _lv_sqrt(uint32_t x, lv_sqrt_res_t * q, uint32_t mask) +{ + e994: b530 push {r4, r5, lr} + x = x << 8; /*To get 4 bit precision. (sqrt(256) = 16 = 4 bit)*/ + e996: 0200 lsls r0, r0, #8 + + uint32_t root = 0; + e998: 2300 movs r3, #0 + uint32_t trial; + // http://ww1.microchip.com/...en/AppNotes/91040a.pdf + do { + trial = root + mask; + e99a: 18d4 adds r4, r2, r3 + if((uint32_t)trial * trial <= x) root = trial; + e99c: fb04 f504 mul.w r5, r4, r4 + e9a0: 42a8 cmp r0, r5 + e9a2: bf28 it cs + e9a4: 4623 movcs r3, r4 + mask = mask >> 1; + } while(mask); + e9a6: 0852 lsrs r2, r2, #1 + e9a8: d1f7 bne.n e99a <_lv_sqrt+0x6> + + q->i = (uint32_t) root >> 4; + e9aa: 091a lsrs r2, r3, #4 + q->f = (uint32_t)(root & 0xf) << 4; + e9ac: 011b lsls r3, r3, #4 + e9ae: b2db uxtb r3, r3 + q->i = (uint32_t) root >> 4; + e9b0: 800a strh r2, [r1, #0] + q->f = (uint32_t)(root & 0xf) << 4; + e9b2: 804b strh r3, [r1, #2] +} + e9b4: bd30 pop {r4, r5, pc} + ... + +0000e9b8 : +static lv_mem_ent_t * ent_get_next(lv_mem_ent_t * act_e) +{ + lv_mem_ent_t * next_e = NULL; + + if(act_e == NULL) { /*NULL means: get the first entry*/ + next_e = (lv_mem_ent_t *)work_mem; + e9b8: 4a07 ldr r2, [pc, #28] ; (e9d8 ) +{ + e9ba: 4603 mov r3, r0 + next_e = (lv_mem_ent_t *)work_mem; + e9bc: 6810 ldr r0, [r2, #0] + if(act_e == NULL) { /*NULL means: get the first entry*/ + e9be: b153 cbz r3, e9d6 + } + else { /*Get the next entry */ + uint8_t * data = &act_e->first_data; + next_e = (lv_mem_ent_t *)&data[act_e->header.s.d_size]; + e9c0: f853 2b04 ldr.w r2, [r3], #4 + e9c4: eb03 0352 add.w r3, r3, r2, lsr #1 + + if(&next_e->first_data >= &work_mem[LV_MEM_SIZE]) next_e = NULL; + e9c8: 1d19 adds r1, r3, #4 + e9ca: f500 4280 add.w r2, r0, #16384 ; 0x4000 + e9ce: 4291 cmp r1, r2 + e9d0: bf34 ite cc + e9d2: 4618 movcc r0, r3 + e9d4: 2000 movcs r0, #0 + } + + return next_e; +} + e9d6: 4770 bx lr + e9d8: 20008788 .word 0x20008788 + +0000e9dc : + size = size & (~0x7); + size += 8; + } +#else + /*Round the size up to 4*/ + if(size & 0x3) { + e9dc: 078b lsls r3, r1, #30 + size = size & (~0x3); + e9de: bf18 it ne + e9e0: f021 0103 bicne.w r1, r1, #3 + size += 4; + } +#endif + + /*Don't let empty space only for a header without data*/ + if(e->header.s.d_size == size + sizeof(lv_mem_header_t)) { + e9e4: 6802 ldr r2, [r0, #0] + size += 4; + e9e6: bf18 it ne + e9e8: 3104 addne r1, #4 +{ + e9ea: b510 push {r4, lr} + if(e->header.s.d_size == size + sizeof(lv_mem_header_t)) { + e9ec: 1d0c adds r4, r1, #4 + e9ee: ebb4 0f52 cmp.w r4, r2, lsr #1 + e9f2: f3c2 035e ubfx r3, r2, #1, #31 + e9f6: d00b beq.n ea10 + size = e->header.s.d_size; + } + + /* Create the new entry after the current if there is space for it */ + if(e->header.s.d_size != size) { + e9f8: 428b cmp r3, r1 + e9fa: d004 beq.n ea06 + uint8_t * e_data = &e->first_data; + lv_mem_ent_t * after_new_e = (lv_mem_ent_t *)&e_data[size]; + after_new_e->header.s.used = 0; + after_new_e->header.s.d_size = (uint32_t)e->header.s.d_size - size - sizeof(lv_mem_header_t); + e9fc: 3b04 subs r3, #4 + after_new_e->header.s.used = 0; + e9fe: 1842 adds r2, r0, r1 + after_new_e->header.s.d_size = (uint32_t)e->header.s.d_size - size - sizeof(lv_mem_header_t); + ea00: 1a5b subs r3, r3, r1 + after_new_e->header.s.used = 0; + ea02: 005b lsls r3, r3, #1 + ea04: 6053 str r3, [r2, #4] + } + + /* Set the new size for the original entry */ + e->header.s.d_size = (uint32_t)size; + ea06: 6803 ldr r3, [r0, #0] + ea08: f361 035f bfi r3, r1, #1, #31 + ea0c: 6003 str r3, [r0, #0] +} + ea0e: bd10 pop {r4, pc} + ea10: 4619 mov r1, r3 + ea12: e7f8 b.n ea06 + +0000ea14 <_lv_mem_init>: + work_mem = (uint8_t *)work_mem_int; + ea14: 4a03 ldr r2, [pc, #12] ; (ea24 <_lv_mem_init+0x10>) + ea16: 4b04 ldr r3, [pc, #16] ; (ea28 <_lv_mem_init+0x14>) + ea18: 6013 str r3, [r2, #0] + full->header.s.used = 0; + ea1a: f647 72f8 movw r2, #32760 ; 0x7ff8 + ea1e: 601a str r2, [r3, #0] +} + ea20: 4770 bx lr + ea22: bf00 nop + ea24: 20008788 .word 0x20008788 + ea28: 20008794 .word 0x20008794 + +0000ea2c : +{ + ea2c: b573 push {r0, r1, r4, r5, r6, lr} + if(size == 0) { + ea2e: 4605 mov r5, r0 + ea30: b1e8 cbz r0, ea6e + if(size & 0x3) { + ea32: 0782 lsls r2, r0, #30 + size = size & (~0x3); + ea34: bf18 it ne + ea36: f020 0503 bicne.w r5, r0, #3 + e = ent_get_next(e); + ea3a: 4e12 ldr r6, [pc, #72] ; (ea84 ) + size += 4; + ea3c: bf18 it ne + ea3e: 3504 addne r5, #4 + lv_mem_ent_t * e = NULL; + ea40: 2400 movs r4, #0 + e = ent_get_next(e); + ea42: 4620 mov r0, r4 + ea44: 47b0 blx r6 + if(e != NULL) { + ea46: 4604 mov r4, r0 + ea48: b198 cbz r0, ea72 + if(e->header.s.used == 0 && e->header.s.d_size >= size) { + ea4a: 7803 ldrb r3, [r0, #0] + ea4c: 07db lsls r3, r3, #31 + ea4e: d4f8 bmi.n ea42 + ea50: 6803 ldr r3, [r0, #0] + ea52: ebb5 0f53 cmp.w r5, r3, lsr #1 + ea56: d8f4 bhi.n ea42 + ent_trunc(e, size); + ea58: 4b0b ldr r3, [pc, #44] ; (ea88 ) + ea5a: 4629 mov r1, r5 + ea5c: 4798 blx r3 + e->header.s.used = 1; + ea5e: 7803 ldrb r3, [r0, #0] + ea60: f043 0301 orr.w r3, r3, #1 + ea64: f804 3b04 strb.w r3, [r4], #4 +} + ea68: 4620 mov r0, r4 + ea6a: b002 add sp, #8 + ea6c: bd70 pop {r4, r5, r6, pc} + return &zero_mem; + ea6e: 4c07 ldr r4, [pc, #28] ; (ea8c ) + ea70: e7fa b.n ea68 + if(alloc == NULL) LV_LOG_WARN("Couldn't allocate memory"); + ea72: 4b07 ldr r3, [pc, #28] ; (ea90 ) + ea74: 9300 str r3, [sp, #0] + ea76: 4907 ldr r1, [pc, #28] ; (ea94 ) + ea78: 4b07 ldr r3, [pc, #28] ; (ea98 ) + ea7a: 4d08 ldr r5, [pc, #32] ; (ea9c ) + ea7c: 22d1 movs r2, #209 ; 0xd1 + ea7e: 2002 movs r0, #2 + ea80: 47a8 blx r5 + ea82: e7f1 b.n ea68 + ea84: 0000e9b9 .word 0x0000e9b9 + ea88: 0000e9dd .word 0x0000e9dd + ea8c: 2000878c .word 0x2000878c + ea90: 0002406d .word 0x0002406d + ea94: 0002403e .word 0x0002403e + ea98: 00024152 .word 0x00024152 + ea9c: 0000e8e9 .word 0x0000e8e9 + +0000eaa0 : +{ + eaa0: b538 push {r3, r4, r5, lr} + next_e = (lv_mem_ent_t *)work_mem; + eaa2: 4b0e ldr r3, [pc, #56] ; (eadc ) + e_free = ent_get_next(e_free); + eaa4: 4d0e ldr r5, [pc, #56] ; (eae0 ) + next_e = (lv_mem_ent_t *)work_mem; + eaa6: 681c ldr r4, [r3, #0] + while(e_free != NULL) { + eaa8: b904 cbnz r4, eaac +} + eaaa: bd38 pop {r3, r4, r5, pc} + e_free = ent_get_next(e_free); + eaac: 4620 mov r0, r4 + eaae: 47a8 blx r5 + if(e_free->header.s.used != 0) { + eab0: 7823 ldrb r3, [r4, #0] + eab2: 07da lsls r2, r3, #31 + eab4: d50f bpl.n ead6 +{ + eab6: 4604 mov r4, r0 + eab8: e7f6 b.n eaa8 + if(e_next->header.s.used == 0) { + eaba: 7803 ldrb r3, [r0, #0] + eabc: 07db lsls r3, r3, #31 + eabe: d4fa bmi.n eab6 + e_free->header.s.d_size += e_next->header.s.d_size + sizeof(e_next->header); + eac0: 6823 ldr r3, [r4, #0] + eac2: 6801 ldr r1, [r0, #0] + eac4: f3c3 025e ubfx r2, r3, #1, #31 + eac8: 3204 adds r2, #4 + eaca: eb02 0251 add.w r2, r2, r1, lsr #1 + eace: f362 035f bfi r3, r2, #1, #31 + ead2: 6023 str r3, [r4, #0] + e_next = ent_get_next(e_next); + ead4: 47a8 blx r5 + while(e_next != NULL) { + ead6: 2800 cmp r0, #0 + ead8: d1ef bne.n eaba + eada: e7e6 b.n eaaa + eadc: 20008788 .word 0x20008788 + eae0: 0000e9b9 .word 0x0000e9b9 + +0000eae4 : + if(data == &zero_mem) return; + eae4: 4a16 ldr r2, [pc, #88] ; (eb40 ) + eae6: 1d13 adds r3, r2, #4 + eae8: 4298 cmp r0, r3 +{ + eaea: b570 push {r4, r5, r6, lr} + eaec: 4604 mov r4, r0 + if(data == &zero_mem) return; + eaee: d010 beq.n eb12 + if(data == NULL) return; + eaf0: b178 cbz r0, eb12 + e->header.s.used = 0; + eaf2: f810 3c04 ldrb.w r3, [r0, #-4] + eaf6: f36f 0300 bfc r3, #0, #1 + eafa: f800 3c04 strb.w r3, [r0, #-4] + full_defrag_cnt++; + eafe: 8913 ldrh r3, [r2, #8] + eb00: 3301 adds r3, #1 + eb02: b29b uxth r3, r3 + if(full_defrag_cnt < LV_MEM_FULL_DEFRAG_CNT) { + eb04: 2b0f cmp r3, #15 + full_defrag_cnt++; + eb06: 8113 strh r3, [r2, #8] + if(full_defrag_cnt < LV_MEM_FULL_DEFRAG_CNT) { + eb08: d814 bhi.n eb34 + e_next = ent_get_next(e); + eb0a: 4d0e ldr r5, [pc, #56] ; (eb44 ) + eb0c: 3804 subs r0, #4 + e_next = ent_get_next(e_next); + eb0e: 47a8 blx r5 + while(e_next != NULL) { + eb10: b900 cbnz r0, eb14 +} + eb12: bd70 pop {r4, r5, r6, pc} + if(e_next->header.s.used == 0) { + eb14: 7803 ldrb r3, [r0, #0] + eb16: 07db lsls r3, r3, #31 + eb18: d4fb bmi.n eb12 + e->header.s.d_size += e_next->header.s.d_size + sizeof(e->header); + eb1a: f854 3c04 ldr.w r3, [r4, #-4] + eb1e: 6801 ldr r1, [r0, #0] + eb20: f3c3 025e ubfx r2, r3, #1, #31 + eb24: 3204 adds r2, #4 + eb26: eb02 0251 add.w r2, r2, r1, lsr #1 + eb2a: f362 035f bfi r3, r2, #1, #31 + eb2e: f844 3c04 str.w r3, [r4, #-4] + eb32: e7ec b.n eb0e + full_defrag_cnt = 0; + eb34: 2300 movs r3, #0 + eb36: 8113 strh r3, [r2, #8] +} + eb38: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + lv_mem_defrag(); + eb3c: 4b02 ldr r3, [pc, #8] ; (eb48 ) + eb3e: 4718 bx r3 + eb40: 20008788 .word 0x20008788 + eb44: 0000e9b9 .word 0x0000e9b9 + eb48: 0000eaa1 .word 0x0000eaa1 + +0000eb4c <_lv_mem_get_size>: + if(data == NULL) return 0; + eb4c: b140 cbz r0, eb60 <_lv_mem_get_size+0x14> + if(data == &zero_mem) return 0; + eb4e: 4b05 ldr r3, [pc, #20] ; (eb64 <_lv_mem_get_size+0x18>) + eb50: 4298 cmp r0, r3 + eb52: d004 beq.n eb5e <_lv_mem_get_size+0x12> + return e->header.s.d_size; + eb54: f850 0c04 ldr.w r0, [r0, #-4] + eb58: f3c0 005e ubfx r0, r0, #1, #31 + eb5c: 4770 bx lr + if(data == NULL) return 0; + eb5e: 2000 movs r0, #0 +} + eb60: 4770 bx lr + eb62: bf00 nop + eb64: 2000878c .word 0x2000878c + +0000eb68 <_lv_mem_buf_release>: + if(mem_buf_small[i].p == p) { + eb68: 4b16 ldr r3, [pc, #88] ; (ebc4 <_lv_mem_buf_release+0x5c>) + eb6a: 681a ldr r2, [r3, #0] + eb6c: 4290 cmp r0, r2 +{ + eb6e: b513 push {r0, r1, r4, lr} + if(mem_buf_small[i].p == p) { + eb70: d00b beq.n eb8a <_lv_mem_buf_release+0x22> + eb72: 689a ldr r2, [r3, #8] + eb74: 4290 cmp r0, r2 + eb76: d10a bne.n eb8e <_lv_mem_buf_release+0x26> + eb78: 2201 movs r2, #1 + mem_buf_small[i].used = 0; + eb7a: eb03 03c2 add.w r3, r3, r2, lsl #3 + eb7e: 799a ldrb r2, [r3, #6] + eb80: f36f 0200 bfc r2, #0, #1 + eb84: 719a strb r2, [r3, #6] +} + eb86: b002 add sp, #8 + eb88: bd10 pop {r4, pc} + if(mem_buf_small[i].p == p) { + eb8a: 2200 movs r2, #0 + eb8c: e7f5 b.n eb7a <_lv_mem_buf_release+0x12> + if(LV_GC_ROOT(_lv_mem_buf[i]).p == p) { + eb8e: 4a0e ldr r2, [pc, #56] ; (ebc8 <_lv_mem_buf_release+0x60>) + if(mem_buf_small[i].p == p) { + eb90: 2300 movs r3, #0 + if(LV_GC_ROOT(_lv_mem_buf[i]).p == p) { + eb92: f852 4033 ldr.w r4, [r2, r3, lsl #3] + eb96: 4284 cmp r4, r0 + eb98: eb02 01c3 add.w r1, r2, r3, lsl #3 + eb9c: d104 bne.n eba8 <_lv_mem_buf_release+0x40> + LV_GC_ROOT(_lv_mem_buf[i]).used = 0; + eb9e: 798b ldrb r3, [r1, #6] + eba0: f36f 0300 bfc r3, #0, #1 + eba4: 718b strb r3, [r1, #6] + return; + eba6: e7ee b.n eb86 <_lv_mem_buf_release+0x1e> + for(i = 0; i < LV_MEM_BUF_MAX_NUM; i++) { + eba8: 3301 adds r3, #1 + ebaa: 2b10 cmp r3, #16 + ebac: d1f1 bne.n eb92 <_lv_mem_buf_release+0x2a> + LV_LOG_ERROR("lv_mem_buf_release: p is not a known buffer") + ebae: 4b07 ldr r3, [pc, #28] ; (ebcc <_lv_mem_buf_release+0x64>) + ebb0: 9300 str r3, [sp, #0] + ebb2: 4907 ldr r1, [pc, #28] ; (ebd0 <_lv_mem_buf_release+0x68>) + ebb4: 4b07 ldr r3, [pc, #28] ; (ebd4 <_lv_mem_buf_release+0x6c>) + ebb6: 4c08 ldr r4, [pc, #32] ; (ebd8 <_lv_mem_buf_release+0x70>) + ebb8: f240 2232 movw r2, #562 ; 0x232 + ebbc: 2003 movs r0, #3 + ebbe: 47a0 blx r4 + ebc0: e7e1 b.n eb86 <_lv_mem_buf_release+0x1e> + ebc2: bf00 nop + ebc4: 20000044 .word 0x20000044 + ebc8: 20008674 .word 0x20008674 + ebcc: 00024086 .word 0x00024086 + ebd0: 0002403e .word 0x0002403e + ebd4: 0002415f .word 0x0002415f + ebd8: 0000e8e9 .word 0x0000e8e9 + +0000ebdc <_lv_mem_buf_free_all>: + mem_buf_small[i].used = 0; + ebdc: 4b11 ldr r3, [pc, #68] ; (ec24 <_lv_mem_buf_free_all+0x48>) + ebde: 799a ldrb r2, [r3, #6] + ebe0: f36f 0200 bfc r2, #0, #1 +{ + ebe4: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + mem_buf_small[i].used = 0; + ebe8: 719a strb r2, [r3, #6] + ebea: 7b9a ldrb r2, [r3, #14] + ebec: 4c0e ldr r4, [pc, #56] ; (ec28 <_lv_mem_buf_free_all+0x4c>) + lv_mem_free(LV_GC_ROOT(_lv_mem_buf[i]).p); + ebee: f8df 803c ldr.w r8, [pc, #60] ; ec2c <_lv_mem_buf_free_all+0x50> + mem_buf_small[i].used = 0; + ebf2: f36f 0200 bfc r2, #0, #1 + ebf6: 2500 movs r5, #0 + ebf8: 739a strb r2, [r3, #14] + for(i = 0; i < LV_MEM_BUF_MAX_NUM; i++) { + ebfa: 4627 mov r7, r4 + LV_GC_ROOT(_lv_mem_buf[i]).p = NULL; + ebfc: 462e mov r6, r5 + if(LV_GC_ROOT(_lv_mem_buf[i]).p) { + ebfe: 6820 ldr r0, [r4, #0] + ec00: b140 cbz r0, ec14 <_lv_mem_buf_free_all+0x38> + lv_mem_free(LV_GC_ROOT(_lv_mem_buf[i]).p); + ec02: 47c0 blx r8 + LV_GC_ROOT(_lv_mem_buf[i]).used = 0; + ec04: eb07 03c5 add.w r3, r7, r5, lsl #3 + LV_GC_ROOT(_lv_mem_buf[i]).p = NULL; + ec08: 6026 str r6, [r4, #0] + LV_GC_ROOT(_lv_mem_buf[i]).used = 0; + ec0a: 799a ldrb r2, [r3, #6] + ec0c: f366 0200 bfi r2, r6, #0, #1 + ec10: 719a strb r2, [r3, #6] + LV_GC_ROOT(_lv_mem_buf[i]).size = 0; + ec12: 80a6 strh r6, [r4, #4] + for(i = 0; i < LV_MEM_BUF_MAX_NUM; i++) { + ec14: 3501 adds r5, #1 + ec16: 2d10 cmp r5, #16 + ec18: f104 0408 add.w r4, r4, #8 + ec1c: d1ef bne.n ebfe <_lv_mem_buf_free_all+0x22> +} + ec1e: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + ec22: bf00 nop + ec24: 20000044 .word 0x20000044 + ec28: 20008674 .word 0x20008674 + ec2c: 0000eae5 .word 0x0000eae5 + +0000ec30 <_lv_memcpy>: +{ + ec30: b570 push {r4, r5, r6, lr} + lv_uintptr_t d_align = (lv_uintptr_t)d8 & ALIGN_MASK; + ec32: f000 0503 and.w r5, r0, #3 + lv_uintptr_t s_align = (lv_uintptr_t)s8 & ALIGN_MASK; + ec36: f001 0603 and.w r6, r1, #3 + if(s_align != d_align) { + ec3a: 42b5 cmp r5, r6 + lv_uintptr_t d_align = (lv_uintptr_t)d8 & ALIGN_MASK; + ec3c: 4604 mov r4, r0 + lv_uintptr_t s_align = (lv_uintptr_t)s8 & ALIGN_MASK; + ec3e: 460b mov r3, r1 + if(s_align != d_align) { + ec40: f040 8098 bne.w ed74 <_lv_memcpy+0x144> + if(d_align) { + ec44: 2d00 cmp r5, #0 + ec46: f040 80a8 bne.w ed9a <_lv_memcpy+0x16a> + uint8_t * d8 = dst; + ec4a: 4605 mov r5, r0 + ec4c: 462b mov r3, r5 + while(len > 32) { + ec4e: 2a20 cmp r2, #32 + ec50: 461c mov r4, r3 + ec52: f101 0520 add.w r5, r1, #32 + ec56: f103 0320 add.w r3, r3, #32 + ec5a: f200 80b0 bhi.w edbe <_lv_memcpy+0x18e> + while(len > 4) { + ec5e: 2a04 cmp r2, #4 + ec60: 460e mov r6, r1 + ec62: f240 809f bls.w eda4 <_lv_memcpy+0x174> + COPY32; + ec66: f851 3b04 ldr.w r3, [r1], #4 + ec6a: f844 3b04 str.w r3, [r4], #4 + len -= 4; + ec6e: 3a04 subs r2, #4 + ec70: e7f5 b.n ec5e <_lv_memcpy+0x2e> + REPEAT8(COPY8); + ec72: f813 1c20 ldrb.w r1, [r3, #-32] + ec76: f804 1c20 strb.w r1, [r4, #-32] + ec7a: f813 1c1f ldrb.w r1, [r3, #-31] + ec7e: f804 1c1f strb.w r1, [r4, #-31] + ec82: f813 1c1e ldrb.w r1, [r3, #-30] + ec86: f804 1c1e strb.w r1, [r4, #-30] + ec8a: f813 1c1d ldrb.w r1, [r3, #-29] + ec8e: f804 1c1d strb.w r1, [r4, #-29] + ec92: f813 1c1c ldrb.w r1, [r3, #-28] + ec96: f804 1c1c strb.w r1, [r4, #-28] + ec9a: f813 1c1b ldrb.w r1, [r3, #-27] + ec9e: f804 1c1b strb.w r1, [r4, #-27] + eca2: f813 1c1a ldrb.w r1, [r3, #-26] + eca6: f804 1c1a strb.w r1, [r4, #-26] + ecaa: f813 1c19 ldrb.w r1, [r3, #-25] + ecae: f804 1c19 strb.w r1, [r4, #-25] + REPEAT8(COPY8); + ecb2: f813 1c18 ldrb.w r1, [r3, #-24] + ecb6: f804 1c18 strb.w r1, [r4, #-24] + ecba: f813 1c17 ldrb.w r1, [r3, #-23] + ecbe: f804 1c17 strb.w r1, [r4, #-23] + ecc2: f813 1c16 ldrb.w r1, [r3, #-22] + ecc6: f804 1c16 strb.w r1, [r4, #-22] + ecca: f813 1c15 ldrb.w r1, [r3, #-21] + ecce: f804 1c15 strb.w r1, [r4, #-21] + ecd2: f813 1c14 ldrb.w r1, [r3, #-20] + ecd6: f804 1c14 strb.w r1, [r4, #-20] + ecda: f813 1c13 ldrb.w r1, [r3, #-19] + ecde: f804 1c13 strb.w r1, [r4, #-19] + ece2: f813 1c12 ldrb.w r1, [r3, #-18] + ece6: f804 1c12 strb.w r1, [r4, #-18] + ecea: f813 1c11 ldrb.w r1, [r3, #-17] + ecee: f804 1c11 strb.w r1, [r4, #-17] + REPEAT8(COPY8); + ecf2: f813 1c10 ldrb.w r1, [r3, #-16] + ecf6: f804 1c10 strb.w r1, [r4, #-16] + ecfa: f813 1c0f ldrb.w r1, [r3, #-15] + ecfe: f804 1c0f strb.w r1, [r4, #-15] + ed02: f813 1c0e ldrb.w r1, [r3, #-14] + ed06: f804 1c0e strb.w r1, [r4, #-14] + ed0a: f813 1c0d ldrb.w r1, [r3, #-13] + ed0e: f804 1c0d strb.w r1, [r4, #-13] + ed12: f813 1c0c ldrb.w r1, [r3, #-12] + ed16: f804 1c0c strb.w r1, [r4, #-12] + ed1a: f813 1c0b ldrb.w r1, [r3, #-11] + ed1e: f804 1c0b strb.w r1, [r4, #-11] + ed22: f813 1c0a ldrb.w r1, [r3, #-10] + ed26: f804 1c0a strb.w r1, [r4, #-10] + ed2a: f813 1c09 ldrb.w r1, [r3, #-9] + ed2e: f804 1c09 strb.w r1, [r4, #-9] + REPEAT8(COPY8); + ed32: f813 1c08 ldrb.w r1, [r3, #-8] + ed36: f804 1c08 strb.w r1, [r4, #-8] + ed3a: f813 1c07 ldrb.w r1, [r3, #-7] + ed3e: f804 1c07 strb.w r1, [r4, #-7] + ed42: f813 1c06 ldrb.w r1, [r3, #-6] + ed46: f804 1c06 strb.w r1, [r4, #-6] + ed4a: f813 1c05 ldrb.w r1, [r3, #-5] + ed4e: f804 1c05 strb.w r1, [r4, #-5] + ed52: f813 1c04 ldrb.w r1, [r3, #-4] + ed56: f804 1c04 strb.w r1, [r4, #-4] + ed5a: f813 1c03 ldrb.w r1, [r3, #-3] + ed5e: f804 1c03 strb.w r1, [r4, #-3] + ed62: f813 1c02 ldrb.w r1, [r3, #-2] + ed66: f804 1c02 strb.w r1, [r4, #-2] + ed6a: f813 1c01 ldrb.w r1, [r3, #-1] + ed6e: f804 1c01 strb.w r1, [r4, #-1] + len -= 32; + ed72: 3a20 subs r2, #32 + while(len > 32) { + ed74: 2a20 cmp r2, #32 + ed76: 461d mov r5, r3 + ed78: 4621 mov r1, r4 + ed7a: f103 0320 add.w r3, r3, #32 + ed7e: f104 0420 add.w r4, r4, #32 + ed82: f63f af76 bhi.w ec72 <_lv_memcpy+0x42> + ed86: 1e6b subs r3, r5, #1 + ed88: 440a add r2, r1 + while(len) { + ed8a: 4291 cmp r1, r2 + ed8c: d100 bne.n ed90 <_lv_memcpy+0x160> +} + ed8e: bd70 pop {r4, r5, r6, pc} + COPY8 + ed90: f813 4f01 ldrb.w r4, [r3, #1]! + ed94: f801 4b01 strb.w r4, [r1], #1 + len--; + ed98: e7f7 b.n ed8a <_lv_memcpy+0x15a> + d_align = ALIGN_MASK + 1 - d_align; + ed9a: f1c5 0504 rsb r5, r5, #4 + ed9e: 4405 add r5, r0 + eda0: 461e mov r6, r3 + while(d_align && len) { + eda2: b912 cbnz r2, edaa <_lv_memcpy+0x17a> + eda4: 1e73 subs r3, r6, #1 + eda6: 4422 add r2, r4 + eda8: e030 b.n ee0c <_lv_memcpy+0x1dc> + COPY8; + edaa: f813 1b01 ldrb.w r1, [r3], #1 + edae: f804 1b01 strb.w r1, [r4], #1 + while(d_align && len) { + edb2: 42ac cmp r4, r5 + COPY8; + edb4: 4619 mov r1, r3 + len--; + edb6: f102 32ff add.w r2, r2, #4294967295 ; 0xffffffff + while(d_align && len) { + edba: d1f1 bne.n eda0 <_lv_memcpy+0x170> + edbc: e746 b.n ec4c <_lv_memcpy+0x1c> + REPEAT8(COPY32) + edbe: f855 1c20 ldr.w r1, [r5, #-32] + edc2: f843 1c20 str.w r1, [r3, #-32] + edc6: f855 1c1c ldr.w r1, [r5, #-28] + edca: f843 1c1c str.w r1, [r3, #-28] + edce: f855 1c18 ldr.w r1, [r5, #-24] + edd2: f843 1c18 str.w r1, [r3, #-24] + edd6: f855 1c14 ldr.w r1, [r5, #-20] + edda: f843 1c14 str.w r1, [r3, #-20] + edde: f855 1c10 ldr.w r1, [r5, #-16] + ede2: f843 1c10 str.w r1, [r3, #-16] + ede6: f855 1c0c ldr.w r1, [r5, #-12] + edea: f843 1c0c str.w r1, [r3, #-12] + edee: f855 1c08 ldr.w r1, [r5, #-8] + edf2: f843 1c08 str.w r1, [r3, #-8] + edf6: f855 1c04 ldr.w r1, [r5, #-4] + edfa: f843 1c04 str.w r1, [r3, #-4] + len -= 32; + edfe: 3a20 subs r2, #32 + ee00: 4629 mov r1, r5 + ee02: e724 b.n ec4e <_lv_memcpy+0x1e> + COPY8 + ee04: f813 1f01 ldrb.w r1, [r3, #1]! + ee08: f804 1b01 strb.w r1, [r4], #1 + while(len) { + ee0c: 4294 cmp r4, r2 + ee0e: d1f9 bne.n ee04 <_lv_memcpy+0x1d4> + ee10: e7bd b.n ed8e <_lv_memcpy+0x15e> + ... + +0000ee14 : + if(new_size & 0x3) { + ee14: 078b lsls r3, r1, #30 +{ + ee16: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} + ee18: 460d mov r5, r1 + new_size = new_size & (~0x3); + ee1a: bf18 it ne + ee1c: f021 0503 bicne.w r5, r1, #3 +{ + ee20: 4604 mov r4, r0 + new_size += 4; + ee22: bf18 it ne + ee24: 3504 addne r5, #4 + if(data_p != NULL) { + ee26: b128 cbz r0, ee34 + if(e->header.s.used == 0) { + ee28: f810 3c04 ldrb.w r3, [r0, #-4] + data_p = NULL; + ee2c: f013 0f01 tst.w r3, #1 + ee30: bf08 it eq + ee32: 2400 moveq r4, #0 + uint32_t old_size = _lv_mem_get_size(data_p); + ee34: 4b16 ldr r3, [pc, #88] ; (ee90 ) + ee36: 4620 mov r0, r4 + ee38: 4798 blx r3 + if(old_size == new_size) return data_p; /*Also avoid reallocating the same memory*/ + ee3a: 4285 cmp r5, r0 + uint32_t old_size = _lv_mem_get_size(data_p); + ee3c: 4607 mov r7, r0 + if(old_size == new_size) return data_p; /*Also avoid reallocating the same memory*/ + ee3e: d004 beq.n ee4a + if(new_size < old_size) { + ee40: d205 bcs.n ee4e + ent_trunc(e, new_size); + ee42: 4b14 ldr r3, [pc, #80] ; (ee94 ) + ee44: 4629 mov r1, r5 + ee46: 1f20 subs r0, r4, #4 + ee48: 4798 blx r3 + return &e->first_data; + ee4a: 4626 mov r6, r4 + ee4c: e00d b.n ee6a + new_p = lv_mem_alloc(new_size); + ee4e: 4b12 ldr r3, [pc, #72] ; (ee98 ) + ee50: 4628 mov r0, r5 + ee52: 4798 blx r3 + if(new_p == NULL) { + ee54: 4606 mov r6, r0 + ee56: b958 cbnz r0, ee70 + LV_LOG_WARN("Couldn't allocate memory"); + ee58: 4b10 ldr r3, [pc, #64] ; (ee9c ) + ee5a: 9300 str r3, [sp, #0] + ee5c: 4910 ldr r1, [pc, #64] ; (eea0 ) + ee5e: 4b11 ldr r3, [pc, #68] ; (eea4 ) + ee60: 4c11 ldr r4, [pc, #68] ; (eea8 ) + ee62: f240 123f movw r2, #319 ; 0x13f + ee66: 2002 movs r0, #2 + ee68: 47a0 blx r4 +} + ee6a: 4630 mov r0, r6 + ee6c: b003 add sp, #12 + ee6e: bdf0 pop {r4, r5, r6, r7, pc} + if(data_p != NULL) { + ee70: 2c00 cmp r4, #0 + ee72: d0fa beq.n ee6a + if(old_size != 0) { + ee74: 2f00 cmp r7, #0 + ee76: d0f8 beq.n ee6a + _lv_memcpy(new_p, data_p, LV_MATH_MIN(new_size, old_size)); + ee78: 42bd cmp r5, r7 + ee7a: 462a mov r2, r5 + ee7c: 4b0b ldr r3, [pc, #44] ; (eeac ) + ee7e: bf28 it cs + ee80: 463a movcs r2, r7 + ee82: 4621 mov r1, r4 + ee84: 4798 blx r3 + lv_mem_free(data_p); + ee86: 4b0a ldr r3, [pc, #40] ; (eeb0 ) + ee88: 4620 mov r0, r4 + ee8a: 4798 blx r3 + ee8c: e7ed b.n ee6a + ee8e: bf00 nop + ee90: 0000eb4d .word 0x0000eb4d + ee94: 0000e9dd .word 0x0000e9dd + ee98: 0000ea2d .word 0x0000ea2d + ee9c: 0002406d .word 0x0002406d + eea0: 0002403e .word 0x0002403e + eea4: 00024173 .word 0x00024173 + eea8: 0000e8e9 .word 0x0000e8e9 + eeac: 0000ec31 .word 0x0000ec31 + eeb0: 0000eae5 .word 0x0000eae5 + +0000eeb4 <_lv_mem_buf_get>: +{ + eeb4: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} + if(size == 0) return NULL; + eeb6: b190 cbz r0, eede <_lv_mem_buf_get+0x2a> + if(size <= MEM_BUF_SMALL_SIZE) { + eeb8: 2810 cmp r0, #16 + eeba: d812 bhi.n eee2 <_lv_mem_buf_get+0x2e> + if(mem_buf_small[i].used == 0) { + eebc: 4a36 ldr r2, [pc, #216] ; (ef98 <_lv_mem_buf_get+0xe4>) + eebe: 7993 ldrb r3, [r2, #6] + eec0: f013 0301 ands.w r3, r3, #1 + eec4: d003 beq.n eece <_lv_mem_buf_get+0x1a> + eec6: 7b93 ldrb r3, [r2, #14] + eec8: 07de lsls r6, r3, #31 + eeca: d40a bmi.n eee2 <_lv_mem_buf_get+0x2e> + eecc: 2301 movs r3, #1 + mem_buf_small[i].used = 1; + eece: eb02 00c3 add.w r0, r2, r3, lsl #3 + eed2: 7981 ldrb r1, [r0, #6] + eed4: f041 0101 orr.w r1, r1, #1 + eed8: 7181 strb r1, [r0, #6] + return mem_buf_small[i].p; + eeda: f852 0033 ldr.w r0, [r2, r3, lsl #3] +} + eede: b003 add sp, #12 + eee0: bdf0 pop {r4, r5, r6, r7, pc} + if(LV_GC_ROOT(_lv_mem_buf[i]).used == 0 && LV_GC_ROOT(_lv_mem_buf[i]).size >= size) { + eee2: 4c2e ldr r4, [pc, #184] ; (ef9c <_lv_mem_buf_get+0xe8>) + if(mem_buf_small[i].used == 0) { + eee4: 2300 movs r3, #0 + eee6: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + if(LV_GC_ROOT(_lv_mem_buf[i]).used == 0 && LV_GC_ROOT(_lv_mem_buf[i]).size >= size) { + eeea: 1d27 adds r7, r4, #4 + eeec: eb04 06c3 add.w r6, r4, r3, lsl #3 + eef0: 79b5 ldrb r5, [r6, #6] + eef2: 4629 mov r1, r5 + eef4: 07ed lsls r5, r5, #31 + eef6: d413 bmi.n ef20 <_lv_mem_buf_get+0x6c> + eef8: f837 5033 ldrh.w r5, [r7, r3, lsl #3] + eefc: 4285 cmp r5, r0 + eefe: d30f bcc.n ef20 <_lv_mem_buf_get+0x6c> + if(LV_GC_ROOT(_lv_mem_buf[i]).size == size) { + ef00: d105 bne.n ef0e <_lv_mem_buf_get+0x5a> + LV_GC_ROOT(_lv_mem_buf[i]).used = 1; + ef02: f041 0101 orr.w r1, r1, #1 + return LV_GC_ROOT(_lv_mem_buf[i]).p; + ef06: f854 0033 ldr.w r0, [r4, r3, lsl #3] + LV_GC_ROOT(_lv_mem_buf[i]).used = 1; + ef0a: 71b1 strb r1, [r6, #6] + return LV_GC_ROOT(_lv_mem_buf[i]).p; + ef0c: e7e7 b.n eede <_lv_mem_buf_get+0x2a> + else if(i_guess < 0) { + ef0e: 1c56 adds r6, r2, #1 + ef10: d101 bne.n ef16 <_lv_mem_buf_get+0x62> + i_guess = i; + ef12: b25a sxtb r2, r3 + ef14: e004 b.n ef20 <_lv_mem_buf_get+0x6c> + else if(LV_GC_ROOT(_lv_mem_buf[i]).size < LV_GC_ROOT(_lv_mem_buf[i_guess]).size) { + ef16: eb04 01c2 add.w r1, r4, r2, lsl #3 + ef1a: 8889 ldrh r1, [r1, #4] + ef1c: 42a9 cmp r1, r5 + ef1e: d8f8 bhi.n ef12 <_lv_mem_buf_get+0x5e> + for(i = 0; i < LV_MEM_BUF_MAX_NUM; i++) { + ef20: 3301 adds r3, #1 + ef22: 2b10 cmp r3, #16 + ef24: d1e2 bne.n eeec <_lv_mem_buf_get+0x38> + if(i_guess >= 0) { + ef26: 1c55 adds r5, r2, #1 + ef28: d008 beq.n ef3c <_lv_mem_buf_get+0x88> + LV_GC_ROOT(_lv_mem_buf[i_guess]).used = 1; + ef2a: eb04 01c2 add.w r1, r4, r2, lsl #3 + return LV_GC_ROOT(_lv_mem_buf[i_guess]).p; + ef2e: f854 0032 ldr.w r0, [r4, r2, lsl #3] + LV_GC_ROOT(_lv_mem_buf[i_guess]).used = 1; + ef32: 798b ldrb r3, [r1, #6] + ef34: f043 0301 orr.w r3, r3, #1 + ef38: 718b strb r3, [r1, #6] + return LV_GC_ROOT(_lv_mem_buf[i_guess]).p; + ef3a: e7d0 b.n eede <_lv_mem_buf_get+0x2a> + ef3c: 2500 movs r5, #0 + if(LV_GC_ROOT(_lv_mem_buf[i]).used == 0) { + ef3e: eb04 03c5 add.w r3, r4, r5, lsl #3 + ef42: 7999 ldrb r1, [r3, #6] + ef44: 460a mov r2, r1 + ef46: 07c9 lsls r1, r1, #31 + ef48: d417 bmi.n ef7a <_lv_mem_buf_get+0xc6> + LV_GC_ROOT(_lv_mem_buf[i]).used = 1; + ef4a: f042 0201 orr.w r2, r2, #1 + LV_GC_ROOT(_lv_mem_buf[i]).size = size; + ef4e: 8098 strh r0, [r3, #4] + LV_GC_ROOT(_lv_mem_buf[i]).used = 1; + ef50: 719a strb r2, [r3, #6] + LV_GC_ROOT(_lv_mem_buf[i]).p = lv_mem_realloc(LV_GC_ROOT(_lv_mem_buf[i]).p, size); + ef52: 4601 mov r1, r0 + ef54: 4b12 ldr r3, [pc, #72] ; (efa0 <_lv_mem_buf_get+0xec>) + ef56: f854 0035 ldr.w r0, [r4, r5, lsl #3] + ef5a: 4798 blx r3 + ef5c: f844 0035 str.w r0, [r4, r5, lsl #3] + if(LV_GC_ROOT(_lv_mem_buf[i]).p == NULL) { + ef60: b940 cbnz r0, ef74 <_lv_mem_buf_get+0xc0> + LV_LOG_ERROR("lv_mem_buf_get: Out of memory, can't allocate a new buffer (increase your LV_MEM_SIZE/heap size)") + ef62: 4b10 ldr r3, [pc, #64] ; (efa4 <_lv_mem_buf_get+0xf0>) + ef64: 9300 str r3, [sp, #0] + ef66: 4910 ldr r1, [pc, #64] ; (efa8 <_lv_mem_buf_get+0xf4>) + ef68: 4b10 ldr r3, [pc, #64] ; (efac <_lv_mem_buf_get+0xf8>) + ef6a: 4e11 ldr r6, [pc, #68] ; (efb0 <_lv_mem_buf_get+0xfc>) + ef6c: f44f 7204 mov.w r2, #528 ; 0x210 + ef70: 2003 movs r0, #3 + ef72: 47b0 blx r6 + return LV_GC_ROOT(_lv_mem_buf[i]).p; + ef74: f854 0035 ldr.w r0, [r4, r5, lsl #3] + ef78: e7b1 b.n eede <_lv_mem_buf_get+0x2a> + for(i = 0; i < LV_MEM_BUF_MAX_NUM; i++) { + ef7a: 3501 adds r5, #1 + ef7c: 2d10 cmp r5, #16 + ef7e: d1de bne.n ef3e <_lv_mem_buf_get+0x8a> + LV_LOG_ERROR("lv_mem_buf_get: no free buffer. Increase LV_DRAW_BUF_MAX_NUM."); + ef80: 4b0c ldr r3, [pc, #48] ; (efb4 <_lv_mem_buf_get+0x100>) + ef82: 9300 str r3, [sp, #0] + ef84: 2003 movs r0, #3 + ef86: 4b09 ldr r3, [pc, #36] ; (efac <_lv_mem_buf_get+0xf8>) + ef88: 4907 ldr r1, [pc, #28] ; (efa8 <_lv_mem_buf_get+0xf4>) + ef8a: 4c09 ldr r4, [pc, #36] ; (efb0 <_lv_mem_buf_get+0xfc>) + ef8c: f240 2216 movw r2, #534 ; 0x216 + ef90: 47a0 blx r4 + return NULL; + ef92: 2000 movs r0, #0 + ef94: e7a3 b.n eede <_lv_mem_buf_get+0x2a> + ef96: bf00 nop + ef98: 20000044 .word 0x20000044 + ef9c: 20008674 .word 0x20008674 + efa0: 0000ee15 .word 0x0000ee15 + efa4: 000240b2 .word 0x000240b2 + efa8: 0002403e .word 0x0002403e + efac: 00024182 .word 0x00024182 + efb0: 0000e8e9 .word 0x0000e8e9 + efb4: 00024114 .word 0x00024114 + +0000efb8 <_lv_memset>: + if(d_align) { + efb8: f010 0303 ands.w r3, r0, #3 +{ + efbc: b410 push {r4} + if(d_align) { + efbe: d009 beq.n efd4 <_lv_memset+0x1c> + d_align = ALIGN_MASK + 1 - d_align; + efc0: f1c3 0304 rsb r3, r3, #4 + efc4: 4403 add r3, r0 + while(d_align && len) { + efc6: b12a cbz r2, efd4 <_lv_memset+0x1c> + *d8 = v; + efc8: f800 1b01 strb.w r1, [r0], #1 + while(d_align && len) { + efcc: 4298 cmp r0, r3 + len--; + efce: f102 32ff add.w r2, r2, #4294967295 ; 0xffffffff + while(d_align && len) { + efd2: d1f8 bne.n efc6 <_lv_memset+0xe> + uint32_t v32 = v + (v << 8) + (v << 16) + (v << 24); + efd4: eb01 2401 add.w r4, r1, r1, lsl #8 + efd8: eb04 4401 add.w r4, r4, r1, lsl #16 + efdc: eb04 6401 add.w r4, r4, r1, lsl #24 + while(len > 32) { + efe0: 4603 mov r3, r0 + efe2: 2a20 cmp r2, #32 + efe4: 4618 mov r0, r3 + efe6: f103 0320 add.w r3, r3, #32 + efea: d805 bhi.n eff8 <_lv_memset+0x40> + while(len > 4) { + efec: 2a04 cmp r2, #4 + efee: d80d bhi.n f00c <_lv_memset+0x54> + *d8 = v; + eff0: 4b08 ldr r3, [pc, #32] ; (f014 <_lv_memset+0x5c>) +} + eff2: f85d 4b04 ldr.w r4, [sp], #4 + *d8 = v; + eff6: 4718 bx r3 + SET32(v32); + eff8: e943 4408 strd r4, r4, [r3, #-32] + SET32(v32); + effc: e943 4406 strd r4, r4, [r3, #-24] + SET32(v32); + f000: e943 4404 strd r4, r4, [r3, #-16] + SET32(v32); + f004: e943 4402 strd r4, r4, [r3, #-8] + len -= 32; + f008: 3a20 subs r2, #32 + f00a: e7ea b.n efe2 <_lv_memset+0x2a> + SET32(v32); + f00c: f840 4b04 str.w r4, [r0], #4 + len -= 4; + f010: 3a04 subs r2, #4 + f012: e7eb b.n efec <_lv_memset+0x34> + f014: 00016305 .word 0x00016305 + +0000f018 <_lv_memset_00>: + if(d_align) { + f018: f010 0303 ands.w r3, r0, #3 +{ + f01c: 460a mov r2, r1 + if(d_align) { + f01e: d10d bne.n f03c <_lv_memset_00+0x24> + f020: 4603 mov r3, r0 + SET32(0); + f022: 2100 movs r1, #0 + while(len > 32) { + f024: 2a20 cmp r2, #32 + f026: 4618 mov r0, r3 + f028: f103 0320 add.w r3, r3, #32 + f02c: d815 bhi.n f05a <_lv_memset_00+0x42> + SET32(0); + f02e: 2300 movs r3, #0 + while(len > 4) { + f030: 2a04 cmp r2, #4 + f032: d908 bls.n f046 <_lv_memset_00+0x2e> + SET32(0); + f034: f840 3b04 str.w r3, [r0], #4 + len -= 4; + f038: 3a04 subs r2, #4 + f03a: e7f9 b.n f030 <_lv_memset_00+0x18> + d_align = ALIGN_MASK + 1 - d_align; + f03c: f1c3 0304 rsb r3, r3, #4 + f040: 4403 add r3, r0 + *d8 = 0x00; + f042: 2100 movs r1, #0 + while(d_align && len) { + f044: b912 cbnz r2, f04c <_lv_memset_00+0x34> + *d8 = 0; + f046: 4b0a ldr r3, [pc, #40] ; (f070 <_lv_memset_00+0x58>) + f048: 2100 movs r1, #0 + f04a: 4718 bx r3 + *d8 = 0x00; + f04c: f800 1b01 strb.w r1, [r0], #1 + while(d_align && len) { + f050: 4283 cmp r3, r0 + len--; + f052: f102 32ff add.w r2, r2, #4294967295 ; 0xffffffff + while(d_align && len) { + f056: d1f5 bne.n f044 <_lv_memset_00+0x2c> + f058: e7e2 b.n f020 <_lv_memset_00+0x8> + SET32(0); + f05a: e943 1108 strd r1, r1, [r3, #-32] + SET32(0); + f05e: e943 1106 strd r1, r1, [r3, #-24] + SET32(0); + f062: e943 1104 strd r1, r1, [r3, #-16] + SET32(0); + f066: e943 1102 strd r1, r1, [r3, #-8] + len -= 32; + f06a: 3a20 subs r2, #32 + f06c: e7da b.n f024 <_lv_memset_00+0xc> + f06e: bf00 nop + f070: 00016305 .word 0x00016305 + +0000f074 <_lv_memset_ff>: + if(d_align) { + f074: f010 0303 ands.w r3, r0, #3 +{ + f078: 460a mov r2, r1 + if(d_align) { + f07a: d10f bne.n f09c <_lv_memset_ff+0x28> + f07c: 4603 mov r3, r0 + SET32(0xFFFFFFFF); + f07e: f04f 31ff mov.w r1, #4294967295 ; 0xffffffff + while(len > 32) { + f082: 2a20 cmp r2, #32 + f084: 4618 mov r0, r3 + f086: f103 0320 add.w r3, r3, #32 + f08a: d816 bhi.n f0ba <_lv_memset_ff+0x46> + SET32(0xFFFFFFFF); + f08c: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + while(len > 4) { + f090: 2a04 cmp r2, #4 + f092: d908 bls.n f0a6 <_lv_memset_ff+0x32> + SET32(0xFFFFFFFF); + f094: f840 3b04 str.w r3, [r0], #4 + len -= 4; + f098: 3a04 subs r2, #4 + f09a: e7f9 b.n f090 <_lv_memset_ff+0x1c> + d_align = ALIGN_MASK + 1 - d_align; + f09c: f1c3 0304 rsb r3, r3, #4 + f0a0: 4403 add r3, r0 + *d8 = 0xFF; + f0a2: 21ff movs r1, #255 ; 0xff + while(d_align && len) { + f0a4: b912 cbnz r2, f0ac <_lv_memset_ff+0x38> + *d8 = 0xFF; + f0a6: 4b0a ldr r3, [pc, #40] ; (f0d0 <_lv_memset_ff+0x5c>) + f0a8: 21ff movs r1, #255 ; 0xff + f0aa: 4718 bx r3 + *d8 = 0xFF; + f0ac: f800 1b01 strb.w r1, [r0], #1 + while(d_align && len) { + f0b0: 4283 cmp r3, r0 + len--; + f0b2: f102 32ff add.w r2, r2, #4294967295 ; 0xffffffff + while(d_align && len) { + f0b6: d1f5 bne.n f0a4 <_lv_memset_ff+0x30> + f0b8: e7e0 b.n f07c <_lv_memset_ff+0x8> + SET32(0xFFFFFFFF); + f0ba: e943 1108 strd r1, r1, [r3, #-32] + SET32(0xFFFFFFFF); + f0be: e943 1106 strd r1, r1, [r3, #-24] + SET32(0xFFFFFFFF); + f0c2: e943 1104 strd r1, r1, [r3, #-16] + SET32(0xFFFFFFFF); + f0c6: e943 1102 strd r1, r1, [r3, #-8] + len -= 32; + f0ca: 3a20 subs r2, #32 + f0cc: e7d9 b.n f082 <_lv_memset_ff+0xe> + f0ce: bf00 nop + f0d0: 00016305 .word 0x00016305 + +0000f0d4 <_out_buffer>: + + +// internal buffer output +static inline void _out_buffer(char character, void * buffer, size_t idx, size_t maxlen) +{ + if(idx < maxlen) { + f0d4: 429a cmp r2, r3 + ((char *)buffer)[idx] = character; + f0d6: bf38 it cc + f0d8: 5488 strbcc r0, [r1, r2] + } +} + f0da: 4770 bx lr + +0000f0dc <_out_null>: +{ + (void)character; + (void)buffer; + (void)idx; + (void)maxlen; +} + f0dc: 4770 bx lr + +0000f0de <_ntoa_format>: + + +// internal itoa format +static size_t _ntoa_format(out_fct_type out, char * buffer, size_t idx, size_t maxlen, char * buf, size_t len, + bool negative, unsigned int base, unsigned int prec, unsigned int width, unsigned int flags) +{ + f0de: e92d 4ff7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, sl, fp, lr} + f0e2: 4617 mov r7, r2 + f0e4: e9dd 6211 ldrd r6, r2, [sp, #68] ; 0x44 + // pad leading zeros + if(!(flags & FLAGS_LEFT)) { + f0e8: f012 0a02 ands.w sl, r2, #2 +{ + f0ec: 4680 mov r8, r0 + f0ee: e9dd 540c ldrd r5, r4, [sp, #48] ; 0x30 + f0f2: e9dd 0c0f ldrd r0, ip, [sp, #60] ; 0x3c + f0f6: f89d e038 ldrb.w lr, [sp, #56] ; 0x38 + if(!(flags & FLAGS_LEFT)) { + f0fa: d11f bne.n f13c <_ntoa_format+0x5e> + if(width && (flags & FLAGS_ZEROPAD) && (negative || (flags & (FLAGS_PLUS | FLAGS_SPACE)))) { + f0fc: f002 0901 and.w r9, r2, #1 + f100: b14e cbz r6, f116 <_ntoa_format+0x38> + f102: f1b9 0f00 cmp.w r9, #0 + f106: d006 beq.n f116 <_ntoa_format+0x38> + f108: f1be 0f00 cmp.w lr, #0 + f10c: d102 bne.n f114 <_ntoa_format+0x36> + f10e: f012 0f0c tst.w r2, #12 + f112: d000 beq.n f116 <_ntoa_format+0x38> + width--; + f114: 3e01 subs r6, #1 + } + while((len < prec) && (len < PRINTF_NTOA_BUFFER_SIZE)) { + buf[len++] = '0'; + f116: f04f 0b30 mov.w fp, #48 ; 0x30 + f11a: e002 b.n f122 <_ntoa_format+0x44> + f11c: f805 b004 strb.w fp, [r5, r4] + f120: 3401 adds r4, #1 + while((len < prec) && (len < PRINTF_NTOA_BUFFER_SIZE)) { + f122: 45a4 cmp ip, r4 + f124: d901 bls.n f12a <_ntoa_format+0x4c> + f126: 2c20 cmp r4, #32 + f128: d1f8 bne.n f11c <_ntoa_format+0x3e> + } + while((flags & FLAGS_ZEROPAD) && (len < width) && (len < PRINTF_NTOA_BUFFER_SIZE)) { + buf[len++] = '0'; + f12a: f04f 0b30 mov.w fp, #48 ; 0x30 + while((flags & FLAGS_ZEROPAD) && (len < width) && (len < PRINTF_NTOA_BUFFER_SIZE)) { + f12e: f1b9 0f00 cmp.w r9, #0 + f132: d003 beq.n f13c <_ntoa_format+0x5e> + f134: 42a6 cmp r6, r4 + f136: d901 bls.n f13c <_ntoa_format+0x5e> + f138: 2c20 cmp r4, #32 + f13a: d137 bne.n f1ac <_ntoa_format+0xce> + } + } + + // handle hash + if(flags & FLAGS_HASH) { + f13c: f012 0f10 tst.w r2, #16 + f140: d019 beq.n f176 <_ntoa_format+0x98> + if(!(flags & FLAGS_PRECISION) && len && ((len == prec) || (len == width))) { + f142: f412 6f80 tst.w r2, #1024 ; 0x400 + f146: d136 bne.n f1b6 <_ntoa_format+0xd8> + f148: b3ac cbz r4, f1b6 <_ntoa_format+0xd8> + f14a: 4564 cmp r4, ip + f14c: d001 beq.n f152 <_ntoa_format+0x74> + f14e: 42b4 cmp r4, r6 + f150: d131 bne.n f1b6 <_ntoa_format+0xd8> + len--; + if(len && (base == 16U)) { + f152: f1b4 0c01 subs.w ip, r4, #1 + f156: d02d beq.n f1b4 <_ntoa_format+0xd6> + f158: 2810 cmp r0, #16 + f15a: d16a bne.n f232 <_ntoa_format+0x154> + len--; + f15c: 3c02 subs r4, #2 + } + } + if((base == 16U) && !(flags & FLAGS_UPPERCASE) && (len < PRINTF_NTOA_BUFFER_SIZE)) { + f15e: 0690 lsls r0, r2, #26 + f160: d431 bmi.n f1c6 <_ntoa_format+0xe8> + f162: 2c1f cmp r4, #31 + f164: d80f bhi.n f186 <_ntoa_format+0xa8> + buf[len++] = 'x'; + f166: 2078 movs r0, #120 ; 0x78 + } + else if((base == 16U) && (flags & FLAGS_UPPERCASE) && (len < PRINTF_NTOA_BUFFER_SIZE)) { + buf[len++] = 'X'; + } + else if((base == 2U) && (len < PRINTF_NTOA_BUFFER_SIZE)) { + buf[len++] = 'b'; + f168: 5528 strb r0, [r5, r4] + f16a: 3401 adds r4, #1 + } + if(len < PRINTF_NTOA_BUFFER_SIZE) { + f16c: 2c1f cmp r4, #31 + f16e: d80a bhi.n f186 <_ntoa_format+0xa8> + buf[len++] = '0'; + f170: 2030 movs r0, #48 ; 0x30 + f172: 5528 strb r0, [r5, r4] + f174: 3401 adds r4, #1 + } + } + + if(len < PRINTF_NTOA_BUFFER_SIZE) { + f176: 2c20 cmp r4, #32 + f178: d005 beq.n f186 <_ntoa_format+0xa8> + if(negative) { + f17a: f1be 0f00 cmp.w lr, #0 + f17e: d026 beq.n f1ce <_ntoa_format+0xf0> + buf[len++] = '-'; + f180: 202d movs r0, #45 ; 0x2d + } + else if(flags & FLAGS_PLUS) { + buf[len++] = '+'; // ignore the space if the '+' exists + } + else if(flags & FLAGS_SPACE) { + buf[len++] = ' '; + f182: 5528 strb r0, [r5, r4] + f184: 3401 adds r4, #1 + if(!(flags & FLAGS_LEFT) && !(flags & FLAGS_ZEROPAD)) { + f186: 0792 lsls r2, r2, #30 + f188: d03b beq.n f202 <_ntoa_format+0x124> + f18a: 463a mov r2, r7 + f18c: 4425 add r5, r4 + f18e: 4414 add r4, r2 + while(len) { + f190: 42a2 cmp r2, r4 + f192: d13a bne.n f20a <_ntoa_format+0x12c> + if(flags & FLAGS_LEFT) { + f194: f1ba 0f00 cmp.w sl, #0 + f198: d004 beq.n f1a4 <_ntoa_format+0xc6> + f19a: 1bd5 subs r5, r2, r7 + while(idx - start_idx < width) { + f19c: 42b5 cmp r5, r6 + f19e: eb05 0407 add.w r4, r5, r7 + f1a2: d33d bcc.n f220 <_ntoa_format+0x142> + } + } + + return _out_rev(out, buffer, idx, maxlen, buf, len, width, flags); +} + f1a4: 4620 mov r0, r4 + f1a6: b003 add sp, #12 + f1a8: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + buf[len++] = '0'; + f1ac: f805 b004 strb.w fp, [r5, r4] + f1b0: 3401 adds r4, #1 + f1b2: e7bc b.n f12e <_ntoa_format+0x50> + f1b4: 4664 mov r4, ip + if((base == 16U) && !(flags & FLAGS_UPPERCASE) && (len < PRINTF_NTOA_BUFFER_SIZE)) { + f1b6: 2810 cmp r0, #16 + f1b8: d0d1 beq.n f15e <_ntoa_format+0x80> + else if((base == 2U) && (len < PRINTF_NTOA_BUFFER_SIZE)) { + f1ba: 2802 cmp r0, #2 + f1bc: d1d6 bne.n f16c <_ntoa_format+0x8e> + f1be: 2c1f cmp r4, #31 + f1c0: d8e1 bhi.n f186 <_ntoa_format+0xa8> + buf[len++] = 'b'; + f1c2: 2062 movs r0, #98 ; 0x62 + f1c4: e7d0 b.n f168 <_ntoa_format+0x8a> + else if((base == 16U) && (flags & FLAGS_UPPERCASE) && (len < PRINTF_NTOA_BUFFER_SIZE)) { + f1c6: 2c1f cmp r4, #31 + f1c8: d8dd bhi.n f186 <_ntoa_format+0xa8> + buf[len++] = 'X'; + f1ca: 2058 movs r0, #88 ; 0x58 + f1cc: e7cc b.n f168 <_ntoa_format+0x8a> + else if(flags & FLAGS_PLUS) { + f1ce: 0750 lsls r0, r2, #29 + f1d0: d501 bpl.n f1d6 <_ntoa_format+0xf8> + buf[len++] = '+'; // ignore the space if the '+' exists + f1d2: 202b movs r0, #43 ; 0x2b + f1d4: e7d5 b.n f182 <_ntoa_format+0xa4> + else if(flags & FLAGS_SPACE) { + f1d6: 0710 lsls r0, r2, #28 + f1d8: d5d5 bpl.n f186 <_ntoa_format+0xa8> + buf[len++] = ' '; + f1da: 2020 movs r0, #32 + f1dc: e7d1 b.n f182 <_ntoa_format+0xa4> + out(' ', buffer, idx++, maxlen); + f1de: 2020 movs r0, #32 + f1e0: e9cd 1300 strd r1, r3, [sp] + f1e4: 47c0 blx r8 + for(i = len; i < width; i++) { + f1e6: e9dd 1300 ldrd r1, r3, [sp] + f1ea: f109 0901 add.w r9, r9, #1 + f1ee: 454e cmp r6, r9 + f1f0: eb0b 0209 add.w r2, fp, r9 + f1f4: d8f3 bhi.n f1de <_ntoa_format+0x100> + f1f6: 1b32 subs r2, r6, r4 + f1f8: 42b4 cmp r4, r6 + f1fa: bf88 it hi + f1fc: 2200 movhi r2, #0 + f1fe: 443a add r2, r7 + f200: e7c4 b.n f18c <_ntoa_format+0xae> + f202: 46a1 mov r9, r4 + f204: eba7 0b04 sub.w fp, r7, r4 + f208: e7f1 b.n f1ee <_ntoa_format+0x110> + out(buf[--len], buffer, idx++, maxlen); + f20a: f102 0901 add.w r9, r2, #1 + f20e: f815 0d01 ldrb.w r0, [r5, #-1]! + f212: e9cd 1300 strd r1, r3, [sp] + f216: 47c0 blx r8 + f218: e9dd 1300 ldrd r1, r3, [sp] + f21c: 464a mov r2, r9 + f21e: e7b7 b.n f190 <_ntoa_format+0xb2> + out(' ', buffer, idx++, maxlen); + f220: 4622 mov r2, r4 + f222: 2020 movs r0, #32 + f224: 9301 str r3, [sp, #4] + f226: 9100 str r1, [sp, #0] + f228: 3501 adds r5, #1 + f22a: 47c0 blx r8 + f22c: e9dd 1300 ldrd r1, r3, [sp] + f230: e7b4 b.n f19c <_ntoa_format+0xbe> + else if((base == 2U) && (len < PRINTF_NTOA_BUFFER_SIZE)) { + f232: 2802 cmp r0, #2 + f234: 4664 mov r4, ip + f236: d199 bne.n f16c <_ntoa_format+0x8e> + f238: e7c3 b.n f1c2 <_ntoa_format+0xe4> + ... + +0000f23c <_ntoa_long>: + + +// internal itoa for 'long' type +static size_t _ntoa_long(out_fct_type out, char * buffer, size_t idx, size_t maxlen, unsigned long value, bool negative, + unsigned long base, unsigned int prec, unsigned int width, unsigned int flags) +{ + f23c: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} + f240: b091 sub sp, #68 ; 0x44 + f242: 9d18 ldr r5, [sp, #96] ; 0x60 + f244: 9e1a ldr r6, [sp, #104] ; 0x68 + f246: 9f1d ldr r7, [sp, #116] ; 0x74 + char buf[PRINTF_NTOA_BUFFER_SIZE]; + size_t len = 0U; + + // no hash for 0 values + if(!value) { + f248: b90d cbnz r5, f24e <_ntoa_long+0x12> + flags &= ~FLAGS_HASH; + f24a: f027 0710 bic.w r7, r7, #16 + } + + // write if precision != 0 and value is != 0 + if(!(flags & FLAGS_PRECISION) || value) { + f24e: 057c lsls r4, r7, #21 + f250: d500 bpl.n f254 <_ntoa_long+0x18> + f252: b315 cbz r5, f29a <_ntoa_long+0x5e> + f254: f017 0f20 tst.w r7, #32 + f258: bf14 ite ne + f25a: f04f 0e41 movne.w lr, #65 ; 0x41 + f25e: f04f 0e61 moveq.w lr, #97 ; 0x61 + do { + const char digit = (char)(value % base); + buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10; + f262: 46ac mov ip, r5 + f264: f10d 0820 add.w r8, sp, #32 + f268: 2500 movs r5, #0 + f26a: f1ae 0e0a sub.w lr, lr, #10 + const char digit = (char)(value % base); + f26e: fbbc f9f6 udiv r9, ip, r6 + f272: fb06 c919 mls r9, r6, r9, ip + f276: fa5f f489 uxtb.w r4, r9 + buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10; + f27a: f1b9 0f09 cmp.w r9, #9 + f27e: bf94 ite ls + f280: 3430 addls r4, #48 ; 0x30 + f282: 4474 addhi r4, lr + f284: b2e4 uxtb r4, r4 + value /= base; + } while(value && (len < PRINTF_NTOA_BUFFER_SIZE)); + f286: 45b4 cmp ip, r6 + buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10; + f288: f808 4b01 strb.w r4, [r8], #1 + value /= base; + f28c: fbbc f4f6 udiv r4, ip, r6 + buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10; + f290: f105 0501 add.w r5, r5, #1 + } while(value && (len < PRINTF_NTOA_BUFFER_SIZE)); + f294: d301 bcc.n f29a <_ntoa_long+0x5e> + f296: 2d20 cmp r5, #32 + f298: d110 bne.n f2bc <_ntoa_long+0x80> + } + + return _ntoa_format(out, buffer, idx, maxlen, buf, len, negative, (unsigned int)base, prec, width, flags); + f29a: 9c1c ldr r4, [sp, #112] ; 0x70 + f29c: 9405 str r4, [sp, #20] + f29e: 9c1b ldr r4, [sp, #108] ; 0x6c + f2a0: 9706 str r7, [sp, #24] + f2a2: e9cd 6403 strd r6, r4, [sp, #12] + f2a6: f89d 4064 ldrb.w r4, [sp, #100] ; 0x64 + f2aa: e9cd 5401 strd r5, r4, [sp, #4] + f2ae: ac08 add r4, sp, #32 + f2b0: 9400 str r4, [sp, #0] + f2b2: 4c03 ldr r4, [pc, #12] ; (f2c0 <_ntoa_long+0x84>) + f2b4: 47a0 blx r4 +} + f2b6: b011 add sp, #68 ; 0x44 + f2b8: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + value /= base; + f2bc: 46a4 mov ip, r4 + f2be: e7d6 b.n f26e <_ntoa_long+0x32> + f2c0: 0000f0df .word 0x0000f0df + +0000f2c4 <_ntoa_long_long>: + +// internal itoa for 'long long' type +#if defined(PRINTF_SUPPORT_LONG_LONG) +static size_t _ntoa_long_long(out_fct_type out, char * buffer, size_t idx, size_t maxlen, unsigned long long value, + bool negative, unsigned long long base, unsigned int prec, unsigned int width, unsigned int flags) +{ + f2c4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + f2c8: ed2d 8b04 vpush {d8-d9} + f2cc: b093 sub sp, #76 ; 0x4c + f2ce: e9dd 6420 ldrd r6, r4, [sp, #128] ; 0x80 + f2d2: 469a mov sl, r3 + char buf[PRINTF_NTOA_BUFFER_SIZE]; + size_t len = 0U; + + // no hash for 0 values + if(!value) { + f2d4: ea56 0304 orrs.w r3, r6, r4 + flags &= ~FLAGS_HASH; + f2d8: bf02 ittt eq + f2da: 9b28 ldreq r3, [sp, #160] ; 0xa0 + f2dc: f023 0310 biceq.w r3, r3, #16 + f2e0: 9328 streq r3, [sp, #160] ; 0xa0 + } + + // write if precision != 0 and value is != 0 + if(!(flags & FLAGS_PRECISION) || value) { + f2e2: 9b28 ldr r3, [sp, #160] ; 0xa0 + f2e4: 055b lsls r3, r3, #21 +{ + f2e6: e9dd b924 ldrd fp, r9, [sp, #144] ; 0x90 + f2ea: ee08 0a10 vmov s16, r0 + f2ee: ee08 1a90 vmov s17, r1 + f2f2: ee09 2a10 vmov s18, r2 + if(!(flags & FLAGS_PRECISION) || value) { + f2f6: d502 bpl.n f2fe <_ntoa_long_long+0x3a> + f2f8: ea56 0304 orrs.w r3, r6, r4 + f2fc: d03f beq.n f37e <_ntoa_long_long+0xba> + f2fe: 9b28 ldr r3, [sp, #160] ; 0xa0 + f300: f013 0f20 tst.w r3, #32 + f304: bf14 ite ne + f306: 2341 movne r3, #65 ; 0x41 + f308: 2361 moveq r3, #97 ; 0x61 + do { + const char digit = (char)(value % base); + buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10; + f30a: 3b0a subs r3, #10 + f30c: f10d 0828 add.w r8, sp, #40 ; 0x28 + f310: 2500 movs r5, #0 + f312: 9309 str r3, [sp, #36] ; 0x24 + const char digit = (char)(value % base); + f314: 4621 mov r1, r4 + f316: 4f1b ldr r7, [pc, #108] ; (f384 <_ntoa_long_long+0xc0>) + f318: 465a mov r2, fp + f31a: 464b mov r3, r9 + f31c: 4630 mov r0, r6 + f31e: 47b8 blx r7 + f320: b2d2 uxtb r2, r2 + buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10; + f322: 2a09 cmp r2, #9 + f324: bf8a itet hi + f326: 9b09 ldrhi r3, [sp, #36] ; 0x24 + f328: 3230 addls r2, #48 ; 0x30 + f32a: 18d2 addhi r2, r2, r3 + value /= base; + } while(value && (len < PRINTF_NTOA_BUFFER_SIZE)); + f32c: 455e cmp r6, fp + buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10; + f32e: b2d2 uxtb r2, r2 + } while(value && (len < PRINTF_NTOA_BUFFER_SIZE)); + f330: eb74 0409 sbcs.w r4, r4, r9 + buf[len++] = digit < 10 ? '0' + digit : (flags & FLAGS_UPPERCASE ? 'A' : 'a') + digit - 10; + f334: f808 2b01 strb.w r2, [r8], #1 + f338: f105 0501 add.w r5, r5, #1 + } while(value && (len < PRINTF_NTOA_BUFFER_SIZE)); + f33c: d301 bcc.n f342 <_ntoa_long_long+0x7e> + f33e: 2d20 cmp r5, #32 + f340: d11a bne.n f378 <_ntoa_long_long+0xb4> + } + + return _ntoa_format(out, buffer, idx, maxlen, buf, len, negative, (unsigned int)base, prec, width, flags); + f342: 9b28 ldr r3, [sp, #160] ; 0xa0 + f344: 9306 str r3, [sp, #24] + f346: 9b27 ldr r3, [sp, #156] ; 0x9c + f348: 9305 str r3, [sp, #20] + f34a: 9b26 ldr r3, [sp, #152] ; 0x98 + f34c: 4c0e ldr r4, [pc, #56] ; (f388 <_ntoa_long_long+0xc4>) + f34e: e9cd b303 strd fp, r3, [sp, #12] + f352: f89d 3088 ldrb.w r3, [sp, #136] ; 0x88 + f356: e9cd 5301 strd r5, r3, [sp, #4] + f35a: ab0a add r3, sp, #40 ; 0x28 + f35c: 9300 str r3, [sp, #0] + f35e: ee19 2a10 vmov r2, s18 + f362: ee18 1a90 vmov r1, s17 + f366: ee18 0a10 vmov r0, s16 + f36a: 4653 mov r3, sl + f36c: 47a0 blx r4 +} + f36e: b013 add sp, #76 ; 0x4c + f370: ecbd 8b04 vpop {d8-d9} + f374: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + value /= base; + f378: 4606 mov r6, r0 + f37a: 460c mov r4, r1 + f37c: e7ca b.n f314 <_ntoa_long_long+0x50> + size_t len = 0U; + f37e: 2500 movs r5, #0 + f380: e7df b.n f342 <_ntoa_long_long+0x7e> + f382: bf00 nop + f384: 00015f41 .word 0x00015f41 + f388: 0000f0df .word 0x0000f0df + +0000f38c <_vsnprintf.constprop.0>: +#endif // PRINTF_SUPPORT_EXPONENTIAL +#endif // PRINTF_SUPPORT_FLOAT + + +// internal vsnprintf +static int _vsnprintf(out_fct_type out, char * buffer, const size_t maxlen, const char * format, va_list va) + f38c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + f390: 4617 mov r7, r2 + f392: 461e mov r6, r3 + unsigned int flags, width, precision, n; + size_t idx = 0U; + + if(!buffer) { + // use null output function + out = _out_null; + f394: 4aac ldr r2, [pc, #688] ; (f648 <_vsnprintf.constprop.0+0x2bc>) + f396: 4bad ldr r3, [pc, #692] ; (f64c <_vsnprintf.constprop.0+0x2c0>) +static int _vsnprintf(out_fct_type out, char * buffer, const size_t maxlen, const char * format, va_list va) + f398: 4689 mov r9, r1 + out = _out_null; + f39a: 1e01 subs r1, r0, #0 +static int _vsnprintf(out_fct_type out, char * buffer, const size_t maxlen, const char * format, va_list va) + f39c: b091 sub sp, #68 ; 0x44 + out = _out_null; + f39e: bf14 ite ne + f3a0: 4693 movne fp, r2 + f3a2: 469b moveq fp, r3 + out('%', buffer, idx++, maxlen); + format++; + break; + + default : + out(*format, buffer, idx++, maxlen); + f3a4: 2500 movs r5, #0 + while(*format) { + f3a6: 7838 ldrb r0, [r7, #0] + f3a8: b958 cbnz r0, f3c2 <_vsnprintf.constprop.0+0x36> + break; + } + } + + // termination + out((char)0, buffer, idx < maxlen ? idx : maxlen - 1U, maxlen); + f3aa: 454d cmp r5, r9 + f3ac: bf2c ite cs + f3ae: f109 32ff addcs.w r2, r9, #4294967295 ; 0xffffffff + f3b2: 462a movcc r2, r5 + f3b4: 464b mov r3, r9 + f3b6: 2000 movs r0, #0 + f3b8: 47d8 blx fp + + // return written chars without terminating \0 + return (int)idx; +} + f3ba: 4628 mov r0, r5 + f3bc: b011 add sp, #68 ; 0x44 + f3be: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + if(*format != '%') { + f3c2: 2825 cmp r0, #37 ; 0x25 + format++; + f3c4: f107 0701 add.w r7, r7, #1 + if(*format != '%') { + f3c8: d006 beq.n f3d8 <_vsnprintf.constprop.0+0x4c> + out(*format, buffer, idx++, maxlen); + f3ca: 1c6c adds r4, r5, #1 + f3cc: 464b mov r3, r9 + f3ce: 462a mov r2, r5 + f3d0: 910a str r1, [sp, #40] ; 0x28 + out(*format, buffer, idx++, maxlen); + f3d2: 47d8 blx fp + f3d4: 4625 mov r5, r4 + f3d6: e0d2 b.n f57e <_vsnprintf.constprop.0+0x1f2> + flags = 0U; + f3d8: 2300 movs r3, #0 + f3da: e006 b.n f3ea <_vsnprintf.constprop.0+0x5e> + switch(*format) { + f3dc: 2a2d cmp r2, #45 ; 0x2d + f3de: d016 beq.n f40e <_vsnprintf.constprop.0+0x82> + f3e0: 2a30 cmp r2, #48 ; 0x30 + f3e2: d10c bne.n f3fe <_vsnprintf.constprop.0+0x72> + flags |= FLAGS_ZEROPAD; + f3e4: f043 0301 orr.w r3, r3, #1 + format++; + f3e8: 4607 mov r7, r0 + switch(*format) { + f3ea: 4638 mov r0, r7 + f3ec: f810 2b01 ldrb.w r2, [r0], #1 + f3f0: 2a2b cmp r2, #43 ; 0x2b + f3f2: d00f beq.n f414 <_vsnprintf.constprop.0+0x88> + f3f4: d8f2 bhi.n f3dc <_vsnprintf.constprop.0+0x50> + f3f6: 2a20 cmp r2, #32 + f3f8: d00f beq.n f41a <_vsnprintf.constprop.0+0x8e> + f3fa: 2a23 cmp r2, #35 ; 0x23 + f3fc: d010 beq.n f420 <_vsnprintf.constprop.0+0x94> + if(_is_digit(*format)) { + f3fe: f1a2 0430 sub.w r4, r2, #48 ; 0x30 + f402: 2c09 cmp r4, #9 + f404: d82c bhi.n f460 <_vsnprintf.constprop.0+0xd4> + unsigned int i = 0U; + f406: f04f 0800 mov.w r8, #0 + i = i * 10U + (unsigned int)(*((*str)++) - '0'); + f40a: 240a movs r4, #10 + f40c: e010 b.n f430 <_vsnprintf.constprop.0+0xa4> + flags |= FLAGS_LEFT; + f40e: f043 0302 orr.w r3, r3, #2 + } while(n); + f412: e7e9 b.n f3e8 <_vsnprintf.constprop.0+0x5c> + flags |= FLAGS_PLUS; + f414: f043 0304 orr.w r3, r3, #4 + } while(n); + f418: e7e6 b.n f3e8 <_vsnprintf.constprop.0+0x5c> + flags |= FLAGS_SPACE; + f41a: f043 0308 orr.w r3, r3, #8 + } while(n); + f41e: e7e3 b.n f3e8 <_vsnprintf.constprop.0+0x5c> + flags |= FLAGS_HASH; + f420: f043 0310 orr.w r3, r3, #16 + } while(n); + f424: e7e0 b.n f3e8 <_vsnprintf.constprop.0+0x5c> + i = i * 10U + (unsigned int)(*((*str)++) - '0'); + f426: fb04 2208 mla r2, r4, r8, r2 + f42a: f1a2 0830 sub.w r8, r2, #48 ; 0x30 + f42e: 4607 mov r7, r0 + while(_is_digit(**str)) { + f430: 4638 mov r0, r7 + f432: f810 2b01 ldrb.w r2, [r0], #1 + f436: f1a2 0c30 sub.w ip, r2, #48 ; 0x30 + f43a: f1bc 0f09 cmp.w ip, #9 + f43e: d9f2 bls.n f426 <_vsnprintf.constprop.0+0x9a> + if(*format == '.') { + f440: 783a ldrb r2, [r7, #0] + f442: 2a2e cmp r2, #46 ; 0x2e + f444: d15a bne.n f4fc <_vsnprintf.constprop.0+0x170> + if(_is_digit(*format)) { + f446: 7878 ldrb r0, [r7, #1] + f448: f1a0 0430 sub.w r4, r0, #48 ; 0x30 + f44c: 2c09 cmp r4, #9 + format++; + f44e: f107 0201 add.w r2, r7, #1 + flags |= FLAGS_PRECISION; + f452: f443 6380 orr.w r3, r3, #1024 ; 0x400 + if(_is_digit(*format)) { + f456: d848 bhi.n f4ea <_vsnprintf.constprop.0+0x15e> + unsigned int i = 0U; + f458: 2400 movs r4, #0 + i = i * 10U + (unsigned int)(*((*str)++) - '0'); + f45a: f04f 0e0a mov.w lr, #10 + f45e: e014 b.n f48a <_vsnprintf.constprop.0+0xfe> + else if(*format == '*') { + f460: 2a2a cmp r2, #42 ; 0x2a + f462: d10a bne.n f47a <_vsnprintf.constprop.0+0xee> + const int w = va_arg(va, int); + f464: f856 8b04 ldr.w r8, [r6], #4 + if(w < 0) { + f468: f1b8 0f00 cmp.w r8, #0 + flags |= FLAGS_LEFT; // reverse padding + f46c: bfbc itt lt + f46e: f043 0302 orrlt.w r3, r3, #2 + width = (unsigned int) - w; + f472: f1c8 0800 rsblt r8, r8, #0 + const int w = va_arg(va, int); + f476: 4607 mov r7, r0 + f478: e7e2 b.n f440 <_vsnprintf.constprop.0+0xb4> + width = 0U; + f47a: f04f 0800 mov.w r8, #0 + f47e: e7df b.n f440 <_vsnprintf.constprop.0+0xb4> + i = i * 10U + (unsigned int)(*((*str)++) - '0'); + f480: fb0e 0004 mla r0, lr, r4, r0 + f484: f1a0 0430 sub.w r4, r0, #48 ; 0x30 + f488: 463a mov r2, r7 + while(_is_digit(**str)) { + f48a: 4617 mov r7, r2 + f48c: f817 0b01 ldrb.w r0, [r7], #1 + f490: f1a0 0c30 sub.w ip, r0, #48 ; 0x30 + f494: f1bc 0f09 cmp.w ip, #9 + f498: d9f2 bls.n f480 <_vsnprintf.constprop.0+0xf4> + f49a: 4617 mov r7, r2 + switch(*format) { + f49c: 463a mov r2, r7 + f49e: f812 0b01 ldrb.w r0, [r2], #1 + f4a2: 286c cmp r0, #108 ; 0x6c + f4a4: d033 beq.n f50e <_vsnprintf.constprop.0+0x182> + f4a6: d82b bhi.n f500 <_vsnprintf.constprop.0+0x174> + f4a8: 2868 cmp r0, #104 ; 0x68 + f4aa: d037 beq.n f51c <_vsnprintf.constprop.0+0x190> + f4ac: 286a cmp r0, #106 ; 0x6a + f4ae: d03f beq.n f530 <_vsnprintf.constprop.0+0x1a4> + switch(*format) { + f4b0: f817 eb01 ldrb.w lr, [r7], #1 + f4b4: f1be 0f78 cmp.w lr, #120 ; 0x78 + f4b8: d811 bhi.n f4de <_vsnprintf.constprop.0+0x152> + f4ba: f1be 0f63 cmp.w lr, #99 ; 0x63 + f4be: d83a bhi.n f536 <_vsnprintf.constprop.0+0x1aa> + f4c0: f1be 0f62 cmp.w lr, #98 ; 0x62 + f4c4: f000 80a2 beq.w f60c <_vsnprintf.constprop.0+0x280> + f4c8: f1be 0f63 cmp.w lr, #99 ; 0x63 + f4cc: f000 80fc beq.w f6c8 <_vsnprintf.constprop.0+0x33c> + f4d0: f1be 0f25 cmp.w lr, #37 ; 0x25 + f4d4: d003 beq.n f4de <_vsnprintf.constprop.0+0x152> + f4d6: f1be 0f58 cmp.w lr, #88 ; 0x58 + f4da: f000 8093 beq.w f604 <_vsnprintf.constprop.0+0x278> + out(*format, buffer, idx++, maxlen); + f4de: 1c6c adds r4, r5, #1 + f4e0: 464b mov r3, r9 + f4e2: 462a mov r2, r5 + f4e4: 910a str r1, [sp, #40] ; 0x28 + f4e6: 4670 mov r0, lr + f4e8: e773 b.n f3d2 <_vsnprintf.constprop.0+0x46> + else if(*format == '*') { + f4ea: 282a cmp r0, #42 ; 0x2a + f4ec: d105 bne.n f4fa <_vsnprintf.constprop.0+0x16e> + precision = prec > 0 ? (unsigned int)prec : 0U; + f4ee: f856 4b04 ldr.w r4, [r6], #4 + format++; + f4f2: 3702 adds r7, #2 + precision = prec > 0 ? (unsigned int)prec : 0U; + f4f4: ea24 74e4 bic.w r4, r4, r4, asr #31 + format++; + f4f8: e7d0 b.n f49c <_vsnprintf.constprop.0+0x110> + format++; + f4fa: 4617 mov r7, r2 + precision = 0U; + f4fc: 2400 movs r4, #0 + f4fe: e7cd b.n f49c <_vsnprintf.constprop.0+0x110> + switch(*format) { + f500: 2874 cmp r0, #116 ; 0x74 + f502: d001 beq.n f508 <_vsnprintf.constprop.0+0x17c> + f504: 287a cmp r0, #122 ; 0x7a + f506: d1d3 bne.n f4b0 <_vsnprintf.constprop.0+0x124> + flags |= (sizeof(size_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG); + f508: f443 7380 orr.w r3, r3, #256 ; 0x100 + f50c: e00b b.n f526 <_vsnprintf.constprop.0+0x19a> + if(*format == 'l') { + f50e: 7878 ldrb r0, [r7, #1] + f510: 286c cmp r0, #108 ; 0x6c + f512: d1f9 bne.n f508 <_vsnprintf.constprop.0+0x17c> + flags |= FLAGS_LONG_LONG; + f514: f443 7340 orr.w r3, r3, #768 ; 0x300 + format++; + f518: 3702 adds r7, #2 + f51a: e7c9 b.n f4b0 <_vsnprintf.constprop.0+0x124> + if(*format == 'h') { + f51c: 7878 ldrb r0, [r7, #1] + f51e: 2868 cmp r0, #104 ; 0x68 + f520: d003 beq.n f52a <_vsnprintf.constprop.0+0x19e> + flags |= FLAGS_SHORT; + f522: f043 0380 orr.w r3, r3, #128 ; 0x80 + format++; + f526: 4617 mov r7, r2 + break; + f528: e7c2 b.n f4b0 <_vsnprintf.constprop.0+0x124> + flags |= FLAGS_CHAR; + f52a: f043 03c0 orr.w r3, r3, #192 ; 0xc0 + f52e: e7f3 b.n f518 <_vsnprintf.constprop.0+0x18c> + flags |= (sizeof(intmax_t) == sizeof(long) ? FLAGS_LONG : FLAGS_LONG_LONG); + f530: f443 7300 orr.w r3, r3, #512 ; 0x200 + break; + f534: e7f7 b.n f526 <_vsnprintf.constprop.0+0x19a> + f536: f1ae 0c64 sub.w ip, lr, #100 ; 0x64 + f53a: 4845 ldr r0, [pc, #276] ; (f650 <_vsnprintf.constprop.0+0x2c4>) + f53c: fa5f fc8c uxtb.w ip, ip + f540: 2201 movs r2, #1 + f542: fa02 f20c lsl.w r2, r2, ip + f546: 4002 ands r2, r0 + f548: d11b bne.n f582 <_vsnprintf.constprop.0+0x1f6> + f54a: f1be 0f73 cmp.w lr, #115 ; 0x73 + f54e: f000 80fb beq.w f748 <_vsnprintf.constprop.0+0x3bc> + f552: f1be 0f70 cmp.w lr, #112 ; 0x70 + f556: d1c2 bne.n f4de <_vsnprintf.constprop.0+0x152> + flags |= FLAGS_ZEROPAD | FLAGS_UPPERCASE; + f558: f043 0321 orr.w r3, r3, #33 ; 0x21 + idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned long)((uintptr_t)va_arg(va, void *)), false, 16U, precision, width, + f55c: 9305 str r3, [sp, #20] + f55e: 2308 movs r3, #8 + f560: e9cd 4303 strd r4, r3, [sp, #12] + f564: 2310 movs r3, #16 + f566: e9cd 2301 strd r2, r3, [sp, #4] + f56a: f856 3b04 ldr.w r3, [r6], #4 + f56e: 9300 str r3, [sp, #0] + f570: 462a mov r2, r5 + f572: 4c38 ldr r4, [pc, #224] ; (f654 <_vsnprintf.constprop.0+0x2c8>) + f574: 910a str r1, [sp, #40] ; 0x28 + f576: 464b mov r3, r9 + f578: 4658 mov r0, fp + f57a: 47a0 blx r4 + f57c: 4605 mov r5, r0 + out(*format, buffer, idx++, maxlen); + f57e: 990a ldr r1, [sp, #40] ; 0x28 + break; + f580: e711 b.n f3a6 <_vsnprintf.constprop.0+0x1a> + if(*format == 'x' || *format == 'X') { + f582: f1be 0f78 cmp.w lr, #120 ; 0x78 + f586: d03f beq.n f608 <_vsnprintf.constprop.0+0x27c> + f588: f1be 0f6f cmp.w lr, #111 ; 0x6f + f58c: f000 8144 beq.w f818 <_vsnprintf.constprop.0+0x48c> + if((*format != 'i') && (*format != 'd')) { + f590: f1be 0f69 cmp.w lr, #105 ; 0x69 + flags &= ~FLAGS_HASH; // no hash for dec format + f594: f023 0310 bic.w r3, r3, #16 + base = 10U; + f598: f04f 020a mov.w r2, #10 + if((*format != 'i') && (*format != 'd')) { + f59c: d002 beq.n f5a4 <_vsnprintf.constprop.0+0x218> + f59e: f1be 0f64 cmp.w lr, #100 ; 0x64 + f5a2: d134 bne.n f60e <_vsnprintf.constprop.0+0x282> + if(flags & FLAGS_PRECISION) { + f5a4: 0558 lsls r0, r3, #21 + flags &= ~FLAGS_ZEROPAD; + f5a6: bf48 it mi + f5a8: f023 0301 bicmi.w r3, r3, #1 + if((*format == 'i') || (*format == 'd')) { + f5ac: f1be 0f69 cmp.w lr, #105 ; 0x69 + if(flags & FLAGS_LONG_LONG) { + f5b0: f403 7c00 and.w ip, r3, #512 ; 0x200 + if((*format == 'i') || (*format == 'd')) { + f5b4: d002 beq.n f5bc <_vsnprintf.constprop.0+0x230> + f5b6: f1be 0f64 cmp.w lr, #100 ; 0x64 + f5ba: d14f bne.n f65c <_vsnprintf.constprop.0+0x2d0> + if(flags & FLAGS_LONG_LONG) { + f5bc: f1bc 0f00 cmp.w ip, #0 + f5c0: d028 beq.n f614 <_vsnprintf.constprop.0+0x288> + const long long value = va_arg(va, long long); + f5c2: 3607 adds r6, #7 + f5c4: f026 0607 bic.w r6, r6, #7 + f5c8: 46b2 mov sl, r6 + f5ca: 6876 ldr r6, [r6, #4] + f5cc: f85a 0b08 ldr.w r0, [sl], #8 + idx = _ntoa_long_long(out, buffer, idx, maxlen, (unsigned long long)(value > 0 ? value : 0 - value), value < 0, base, + f5d0: 9406 str r4, [sp, #24] + f5d2: e9cd 8307 strd r8, r3, [sp, #28] + f5d6: 2300 movs r3, #0 + f5d8: 9305 str r3, [sp, #20] + f5da: 0ff3 lsrs r3, r6, #31 + f5dc: 2e00 cmp r6, #0 + f5de: 9302 str r3, [sp, #8] + f5e0: 9204 str r2, [sp, #16] + f5e2: 4603 mov r3, r0 + f5e4: da02 bge.n f5ec <_vsnprintf.constprop.0+0x260> + f5e6: 4243 negs r3, r0 + f5e8: eb66 0646 sbc.w r6, r6, r6, lsl #1 + f5ec: e9cd 3600 strd r3, r6, [sp] + idx = _ntoa_long_long(out, buffer, idx, maxlen, va_arg(va, unsigned long long), false, base, precision, width, flags); + f5f0: 4c19 ldr r4, [pc, #100] ; (f658 <_vsnprintf.constprop.0+0x2cc>) + f5f2: 910a str r1, [sp, #40] ; 0x28 + f5f4: 464b mov r3, r9 + f5f6: 462a mov r2, r5 + f5f8: 4658 mov r0, fp + f5fa: 47a0 blx r4 + idx = _ntoa_long(out, buffer, idx, maxlen, value, false, base, precision, width, flags); + f5fc: 990a ldr r1, [sp, #40] ; 0x28 + f5fe: 4605 mov r5, r0 + break; + f600: 4656 mov r6, sl + f602: e6d0 b.n f3a6 <_vsnprintf.constprop.0+0x1a> + flags |= FLAGS_UPPERCASE; + f604: f043 0320 orr.w r3, r3, #32 + base = 16U; + f608: 2210 movs r2, #16 + f60a: e000 b.n f60e <_vsnprintf.constprop.0+0x282> + switch(*format) { + f60c: 2202 movs r2, #2 + flags &= ~(FLAGS_PLUS | FLAGS_SPACE); + f60e: f023 030c bic.w r3, r3, #12 + f612: e7c7 b.n f5a4 <_vsnprintf.constprop.0+0x218> + else if(flags & FLAGS_LONG) { + f614: 05d8 lsls r0, r3, #23 + idx = _ntoa_long(out, buffer, idx, maxlen, va_arg(va, unsigned long), false, base, precision, width, flags); + f616: f106 0a04 add.w sl, r6, #4 + else if(flags & FLAGS_LONG) { + f61a: d501 bpl.n f620 <_vsnprintf.constprop.0+0x294> + int) : va_arg(va, int); + f61c: 6830 ldr r0, [r6, #0] + f61e: e002 b.n f626 <_vsnprintf.constprop.0+0x29a> + const int value = (flags & FLAGS_CHAR) ? (char)va_arg(va, int) : (flags & FLAGS_SHORT) ? (short int)va_arg(va, + f620: 0658 lsls r0, r3, #25 + f622: d50c bpl.n f63e <_vsnprintf.constprop.0+0x2b2> + f624: 7830 ldrb r0, [r6, #0] + idx = _ntoa_long(out, buffer, idx, maxlen, (unsigned int)(value > 0 ? value : 0 - value), value < 0, base, precision, + f626: e9cd 2402 strd r2, r4, [sp, #8] + f62a: e9cd 8304 strd r8, r3, [sp, #16] + f62e: 2800 cmp r0, #0 + f630: ea4f 73d0 mov.w r3, r0, lsr #31 + f634: 9301 str r3, [sp, #4] + f636: bfb8 it lt + f638: 4240 neglt r0, r0 + idx = _ntoa_long(out, buffer, idx, maxlen, value, false, base, precision, width, flags); + f63a: 9000 str r0, [sp, #0] + f63c: e02d b.n f69a <_vsnprintf.constprop.0+0x30e> + int) : va_arg(va, int); + f63e: 0618 lsls r0, r3, #24 + f640: d5ec bpl.n f61c <_vsnprintf.constprop.0+0x290> + f642: f9b6 0000 ldrsh.w r0, [r6] + f646: e7ee b.n f626 <_vsnprintf.constprop.0+0x29a> + f648: 0000f0d5 .word 0x0000f0d5 + f64c: 0000f0dd .word 0x0000f0dd + f650: 00120821 .word 0x00120821 + f654: 0000f23d .word 0x0000f23d + f658: 0000f2c5 .word 0x0000f2c5 + if(flags & FLAGS_LONG_LONG) { + f65c: f1bc 0f00 cmp.w ip, #0 + f660: d00f beq.n f682 <_vsnprintf.constprop.0+0x2f6> + idx = _ntoa_long_long(out, buffer, idx, maxlen, va_arg(va, unsigned long long), false, base, precision, width, flags); + f662: e9cd 8307 strd r8, r3, [sp, #28] + f666: 2300 movs r3, #0 + f668: e9cd 2304 strd r2, r3, [sp, #16] + f66c: f106 0a07 add.w sl, r6, #7 + f670: f02a 0a07 bic.w sl, sl, #7 + f674: 9406 str r4, [sp, #24] + f676: 9302 str r3, [sp, #8] + f678: e8fa 2302 ldrd r2, r3, [sl], #8 + f67c: e9cd 2300 strd r2, r3, [sp] + f680: e7b6 b.n f5f0 <_vsnprintf.constprop.0+0x264> + else if(flags & FLAGS_LONG) { + f682: 05d8 lsls r0, r3, #23 + idx = _ntoa_long(out, buffer, idx, maxlen, va_arg(va, unsigned long), false, base, precision, width, flags); + f684: f106 0a04 add.w sl, r6, #4 + else if(flags & FLAGS_LONG) { + f688: d50e bpl.n f6a8 <_vsnprintf.constprop.0+0x31c> + idx = _ntoa_long(out, buffer, idx, maxlen, va_arg(va, unsigned long), false, base, precision, width, flags); + f68a: e9cd 8304 strd r8, r3, [sp, #16] + f68e: e9cd 2402 strd r2, r4, [sp, #8] + f692: f8cd c004 str.w ip, [sp, #4] + f696: 6833 ldr r3, [r6, #0] + f698: 9300 str r3, [sp, #0] + idx = _ntoa_long(out, buffer, idx, maxlen, value, false, base, precision, width, flags); + f69a: 4c60 ldr r4, [pc, #384] ; (f81c <_vsnprintf.constprop.0+0x490>) + f69c: 910a str r1, [sp, #40] ; 0x28 + f69e: 464b mov r3, r9 + f6a0: 462a mov r2, r5 + f6a2: 4658 mov r0, fp + f6a4: 47a0 blx r4 + f6a6: e7a9 b.n f5fc <_vsnprintf.constprop.0+0x270> + unsigned int) : (flags & FLAGS_SHORT) ? (unsigned short int)va_arg(va, unsigned int) : va_arg(va, unsigned int); + f6a8: 0658 lsls r0, r3, #25 + f6aa: d507 bpl.n f6bc <_vsnprintf.constprop.0+0x330> + f6ac: 7830 ldrb r0, [r6, #0] + idx = _ntoa_long(out, buffer, idx, maxlen, value, false, base, precision, width, flags); + f6ae: e9cd 8304 strd r8, r3, [sp, #16] + f6b2: 2300 movs r3, #0 + f6b4: e9cd 2402 strd r2, r4, [sp, #8] + f6b8: 9301 str r3, [sp, #4] + f6ba: e7be b.n f63a <_vsnprintf.constprop.0+0x2ae> + f6bc: 6830 ldr r0, [r6, #0] + unsigned int) : (flags & FLAGS_SHORT) ? (unsigned short int)va_arg(va, unsigned int) : va_arg(va, unsigned int); + f6be: f013 0f80 tst.w r3, #128 ; 0x80 + f6c2: bf18 it ne + f6c4: b280 uxthne r0, r0 + f6c6: e7f2 b.n f6ae <_vsnprintf.constprop.0+0x322> + if(!(flags & FLAGS_LEFT)) { + f6c8: f013 0402 ands.w r4, r3, #2 + f6cc: d026 beq.n f71c <_vsnprintf.constprop.0+0x390> + unsigned int l = 1U; + f6ce: f04f 0a01 mov.w sl, #1 + out((char)va_arg(va, int), buffer, idx++, maxlen); + f6d2: 1c6b adds r3, r5, #1 + f6d4: 930a str r3, [sp, #40] ; 0x28 + f6d6: 910b str r1, [sp, #44] ; 0x2c + f6d8: f816 0b04 ldrb.w r0, [r6], #4 + f6dc: 464b mov r3, r9 + f6de: 462a mov r2, r5 + f6e0: 47d8 blx fp + if(flags & FLAGS_LEFT) { + f6e2: 990b ldr r1, [sp, #44] ; 0x2c + f6e4: b374 cbz r4, f744 <_vsnprintf.constprop.0+0x3b8> + out((char)va_arg(va, int), buffer, idx++, maxlen); + f6e6: 9a0a ldr r2, [sp, #40] ; 0x28 + f6e8: 4654 mov r4, sl + f6ea: e021 b.n f730 <_vsnprintf.constprop.0+0x3a4> + out(' ', buffer, idx++, maxlen); + f6ec: 910a str r1, [sp, #40] ; 0x28 + f6ee: 464b mov r3, r9 + f6f0: 2020 movs r0, #32 + f6f2: 47d8 blx fp + f6f4: 990a ldr r1, [sp, #40] ; 0x28 + f6f6: eb05 020a add.w r2, r5, sl + while(l++ < width) { + f6fa: f10a 0a01 add.w sl, sl, #1 + f6fe: 45c2 cmp sl, r8 + f700: d3f4 bcc.n f6ec <_vsnprintf.constprop.0+0x360> + f702: f1b8 0f00 cmp.w r8, #0 + f706: f108 33ff add.w r3, r8, #4294967295 ; 0xffffffff + f70a: bf08 it eq + f70c: 2300 moveq r3, #0 + f70e: f108 0a01 add.w sl, r8, #1 + f712: 441d add r5, r3 + f714: bf08 it eq + f716: f04f 0a02 moveq.w sl, #2 + f71a: e7da b.n f6d2 <_vsnprintf.constprop.0+0x346> + f71c: 46a2 mov sl, r4 + f71e: e7ea b.n f6f6 <_vsnprintf.constprop.0+0x36a> + out(' ', buffer, idx++, maxlen); + f720: 910b str r1, [sp, #44] ; 0x2c + f722: 464b mov r3, r9 + f724: 2020 movs r0, #32 + f726: 1c55 adds r5, r2, #1 + f728: 47d8 blx fp + f72a: 990b ldr r1, [sp, #44] ; 0x2c + f72c: 3401 adds r4, #1 + f72e: 462a mov r2, r5 + while(l++ < width) { + f730: 4544 cmp r4, r8 + f732: d3f5 bcc.n f720 <_vsnprintf.constprop.0+0x394> + f734: 9a0a ldr r2, [sp, #40] ; 0x28 + f736: eba8 030a sub.w r3, r8, sl + f73a: 45d0 cmp r8, sl + f73c: bf38 it cc + f73e: 2300 movcc r3, #0 + f740: 441a add r2, r3 + f742: 920a str r2, [sp, #40] ; 0x28 + break; + f744: 9d0a ldr r5, [sp, #40] ; 0x28 + f746: e62e b.n f3a6 <_vsnprintf.constprop.0+0x1a> + const char * p = va_arg(va, char *); + f748: 4632 mov r2, r6 + unsigned int l = _strnlen_s(p, precision ? precision : (size_t) -1); + f74a: 2c00 cmp r4, #0 + const char * p = va_arg(va, char *); + f74c: f852 6b04 ldr.w r6, [r2], #4 + f750: 920a str r2, [sp, #40] ; 0x28 + unsigned int l = _strnlen_s(p, precision ? precision : (size_t) -1); + f752: bf14 ite ne + f754: 4620 movne r0, r4 + f756: f04f 30ff moveq.w r0, #4294967295 ; 0xffffffff + f75a: 4430 add r0, r6 + f75c: 4632 mov r2, r6 + for(s = str; *s && maxsize--; ++s); + f75e: f892 c000 ldrb.w ip, [r2] + f762: f1bc 0f00 cmp.w ip, #0 + f766: d001 beq.n f76c <_vsnprintf.constprop.0+0x3e0> + f768: 4290 cmp r0, r2 + f76a: d111 bne.n f790 <_vsnprintf.constprop.0+0x404> + return (unsigned int)(s - str); + f76c: eba2 0a06 sub.w sl, r2, r6 + if(flags & FLAGS_PRECISION) { + f770: f413 6280 ands.w r2, r3, #1024 ; 0x400 + f774: 920b str r2, [sp, #44] ; 0x2c + f776: d002 beq.n f77e <_vsnprintf.constprop.0+0x3f2> + l = (l < precision ? l : precision); + f778: 45a2 cmp sl, r4 + f77a: bf28 it cs + f77c: 46a2 movcs sl, r4 + if(!(flags & FLAGS_LEFT)) { + f77e: f013 0302 ands.w r3, r3, #2 + f782: 930c str r3, [sp, #48] ; 0x30 + f784: d11c bne.n f7c0 <_vsnprintf.constprop.0+0x434> + f786: ebaa 0305 sub.w r3, sl, r5 + f78a: 462a mov r2, r5 + f78c: 930e str r3, [sp, #56] ; 0x38 + f78e: e009 b.n f7a4 <_vsnprintf.constprop.0+0x418> + for(s = str; *s && maxsize--; ++s); + f790: 3201 adds r2, #1 + f792: e7e4 b.n f75e <_vsnprintf.constprop.0+0x3d2> + out(' ', buffer, idx++, maxlen); + f794: 1c53 adds r3, r2, #1 + f796: 930d str r3, [sp, #52] ; 0x34 + f798: 910f str r1, [sp, #60] ; 0x3c + f79a: 464b mov r3, r9 + f79c: 2020 movs r0, #32 + f79e: 47d8 blx fp + f7a0: 9a0d ldr r2, [sp, #52] ; 0x34 + f7a2: 990f ldr r1, [sp, #60] ; 0x3c + while(l++ < width) { + f7a4: 9b0e ldr r3, [sp, #56] ; 0x38 + f7a6: 18d3 adds r3, r2, r3 + f7a8: 4543 cmp r3, r8 + f7aa: d3f3 bcc.n f794 <_vsnprintf.constprop.0+0x408> + f7ac: eba8 030a sub.w r3, r8, sl + f7b0: 45d0 cmp r8, sl + f7b2: bf38 it cc + f7b4: 2300 movcc r3, #0 + f7b6: f10a 0201 add.w r2, sl, #1 + f7ba: 441d add r5, r3 + f7bc: eb03 0a02 add.w sl, r3, r2 + f7c0: 1bab subs r3, r5, r6 + f7c2: 930d str r3, [sp, #52] ; 0x34 + f7c4: e005 b.n f7d2 <_vsnprintf.constprop.0+0x446> + f7c6: 461c mov r4, r3 + out(*(p++), buffer, idx++, maxlen); + f7c8: 910e str r1, [sp, #56] ; 0x38 + f7ca: 464b mov r3, r9 + f7cc: 462a mov r2, r5 + f7ce: 47d8 blx fp + f7d0: 990e ldr r1, [sp, #56] ; 0x38 + f7d2: 9b0d ldr r3, [sp, #52] ; 0x34 + f7d4: 199d adds r5, r3, r6 + while((*p != 0) && (!(flags & FLAGS_PRECISION) || precision--)) { + f7d6: f816 0b01 ldrb.w r0, [r6], #1 + f7da: b128 cbz r0, f7e8 <_vsnprintf.constprop.0+0x45c> + f7dc: 9b0b ldr r3, [sp, #44] ; 0x2c + f7de: 2b00 cmp r3, #0 + f7e0: d0f2 beq.n f7c8 <_vsnprintf.constprop.0+0x43c> + f7e2: 1e63 subs r3, r4, #1 + f7e4: 2c00 cmp r4, #0 + f7e6: d1ee bne.n f7c6 <_vsnprintf.constprop.0+0x43a> + if(flags & FLAGS_LEFT) { + f7e8: 9b0c ldr r3, [sp, #48] ; 0x30 + f7ea: b19b cbz r3, f814 <_vsnprintf.constprop.0+0x488> + f7ec: 462a mov r2, r5 + f7ee: ebaa 0405 sub.w r4, sl, r5 + f7f2: e006 b.n f802 <_vsnprintf.constprop.0+0x476> + out(' ', buffer, idx++, maxlen); + f7f4: 910b str r1, [sp, #44] ; 0x2c + f7f6: 464b mov r3, r9 + f7f8: 2020 movs r0, #32 + f7fa: 1c56 adds r6, r2, #1 + f7fc: 47d8 blx fp + f7fe: 990b ldr r1, [sp, #44] ; 0x2c + f800: 4632 mov r2, r6 + while(l++ < width) { + f802: 18a3 adds r3, r4, r2 + f804: 4598 cmp r8, r3 + f806: d8f5 bhi.n f7f4 <_vsnprintf.constprop.0+0x468> + f808: eba8 030a sub.w r3, r8, sl + f80c: 45d0 cmp r8, sl + f80e: bf38 it cc + f810: 2300 movcc r3, #0 + f812: 441d add r5, r3 + const char * p = va_arg(va, char *); + f814: 9e0a ldr r6, [sp, #40] ; 0x28 + break; + f816: e5c6 b.n f3a6 <_vsnprintf.constprop.0+0x1a> + if(*format == 'x' || *format == 'X') { + f818: 2208 movs r2, #8 + f81a: e6f8 b.n f60e <_vsnprintf.constprop.0+0x282> + f81c: 0000f23d .word 0x0000f23d + +0000f820 : + va_end(va); + return ret; +} + +int lv_vsnprintf(char * buffer, size_t count, const char * format, va_list va) +{ + f820: b410 push {r4} + return _vsnprintf(_out_buffer, buffer, count, format, va); + f822: 4c02 ldr r4, [pc, #8] ; (f82c ) + f824: 46a4 mov ip, r4 +} + f826: f85d 4b04 ldr.w r4, [sp], #4 + return _vsnprintf(_out_buffer, buffer, count, format, va); + f82a: 4760 bx ip + f82c: 0000f38d .word 0x0000f38d + +0000f830 <_lv_task_core_init>: + +/** + * Init the lv_task module + */ +void _lv_task_core_init(void) +{ + f830: b508 push {r3, lr} + _lv_ll_init(&LV_GC_ROOT(_lv_task_ll), sizeof(lv_task_t)); + f832: 4805 ldr r0, [pc, #20] ; (f848 <_lv_task_core_init+0x18>) + f834: 4b05 ldr r3, [pc, #20] ; (f84c <_lv_task_core_init+0x1c>) + f836: 2118 movs r1, #24 + f838: 4798 blx r3 + + task_list_changed = false; + f83a: 4b05 ldr r3, [pc, #20] ; (f850 <_lv_task_core_init+0x20>) + f83c: 2200 movs r2, #0 + f83e: 701a strb r2, [r3, #0] + * Enable or disable the whole lv_task handling + * @param en: true: lv_task handling is running, false: lv_task handling is suspended + */ +void lv_task_enable(bool en) +{ + lv_task_run = en; + f840: 2201 movs r2, #1 + f842: 705a strb r2, [r3, #1] +} + f844: bd08 pop {r3, pc} + f846: bf00 nop + f848: 20008600 .word 0x20008600 + f84c: 0000e605 .word 0x0000e605 + f850: 2000c7b4 .word 0x2000c7b4 + +0000f854 : +{ + f854: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} + tmp = _lv_ll_get_head(&LV_GC_ROOT(_lv_task_ll)); + f856: 4b36 ldr r3, [pc, #216] ; (f930 ) + f858: 4836 ldr r0, [pc, #216] ; (f934 ) + f85a: 4798 blx r3 + if(NULL == tmp) { + f85c: 4605 mov r5, r0 + f85e: b1e0 cbz r0, f89a + tmp = _lv_ll_get_next(&LV_GC_ROOT(_lv_task_ll), tmp); + f860: 4e34 ldr r6, [pc, #208] ; (f934 ) + f862: 4c35 ldr r4, [pc, #212] ; (f938 ) + if(tmp->prio <= DEF_PRIO) { + f864: 7d2b ldrb r3, [r5, #20] + f866: f003 0307 and.w r3, r3, #7 + f86a: 2b03 cmp r3, #3 + new_task = _lv_ll_ins_prev(&LV_GC_ROOT(_lv_task_ll), tmp); + f86c: 4629 mov r1, r5 + if(tmp->prio <= DEF_PRIO) { + f86e: d82e bhi.n f8ce + new_task = _lv_ll_ins_prev(&LV_GC_ROOT(_lv_task_ll), tmp); + f870: 4b32 ldr r3, [pc, #200] ; (f93c ) + f872: 4830 ldr r0, [pc, #192] ; (f934 ) + f874: 4798 blx r3 + LV_ASSERT_MEM(new_task); + f876: 4b32 ldr r3, [pc, #200] ; (f940 ) + new_task = _lv_ll_ins_prev(&LV_GC_ROOT(_lv_task_ll), tmp); + f878: 4604 mov r4, r0 + LV_ASSERT_MEM(new_task); + f87a: 4798 blx r3 + f87c: 4605 mov r5, r0 + f87e: bb08 cbnz r0, f8c4 + f880: 4b30 ldr r3, [pc, #192] ; (f944 ) + f882: 4931 ldr r1, [pc, #196] ; (f948 ) + f884: 9300 str r3, [sp, #0] + f886: 22db movs r2, #219 ; 0xdb + f888: 2003 movs r0, #3 + f88a: 4e30 ldr r6, [pc, #192] ; (f94c ) + f88c: 47b0 blx r6 + f88e: 4830 ldr r0, [pc, #192] ; (f950 ) + f890: 4930 ldr r1, [pc, #192] ; (f954 ) + f892: 4622 mov r2, r4 + f894: 462b mov r3, r5 + f896: 4788 blx r1 + f898: e7fe b.n f898 + new_task = _lv_ll_ins_head(&LV_GC_ROOT(_lv_task_ll)); + f89a: 4b2f ldr r3, [pc, #188] ; (f958 ) + f89c: 4825 ldr r0, [pc, #148] ; (f934 ) + f89e: 4798 blx r3 + LV_ASSERT_MEM(new_task); + f8a0: 4b27 ldr r3, [pc, #156] ; (f940 ) + new_task = _lv_ll_ins_head(&LV_GC_ROOT(_lv_task_ll)); + f8a2: 4604 mov r4, r0 + LV_ASSERT_MEM(new_task); + f8a4: 4798 blx r3 + f8a6: 4605 mov r5, r0 + f8a8: b960 cbnz r0, f8c4 + f8aa: 4b26 ldr r3, [pc, #152] ; (f944 ) + f8ac: 4926 ldr r1, [pc, #152] ; (f948 ) + f8ae: 9300 str r3, [sp, #0] + f8b0: 22d3 movs r2, #211 ; 0xd3 + f8b2: 2003 movs r0, #3 + f8b4: 4e25 ldr r6, [pc, #148] ; (f94c ) + f8b6: 47b0 blx r6 + f8b8: 4825 ldr r0, [pc, #148] ; (f950 ) + f8ba: 4926 ldr r1, [pc, #152] ; (f954 ) + f8bc: 4622 mov r2, r4 + f8be: 462b mov r3, r5 + f8c0: 4788 blx r1 + f8c2: e7fe b.n f8c2 + if(new_task == NULL) return NULL; + f8c4: b9ec cbnz r4, f902 + f8c6: 2400 movs r4, #0 +} + f8c8: 4620 mov r0, r4 + f8ca: b003 add sp, #12 + f8cc: bdf0 pop {r4, r5, r6, r7, pc} + tmp = _lv_ll_get_next(&LV_GC_ROOT(_lv_task_ll), tmp); + f8ce: 4630 mov r0, r6 + f8d0: 47a0 blx r4 + } while(tmp != NULL); + f8d2: 4605 mov r5, r0 + f8d4: 2800 cmp r0, #0 + f8d6: d1c5 bne.n f864 + new_task = _lv_ll_ins_tail(&LV_GC_ROOT(_lv_task_ll)); + f8d8: 4b20 ldr r3, [pc, #128] ; (f95c ) + f8da: 4816 ldr r0, [pc, #88] ; (f934 ) + f8dc: 4798 blx r3 + LV_ASSERT_MEM(new_task); + f8de: 4b18 ldr r3, [pc, #96] ; (f940 ) + new_task = _lv_ll_ins_tail(&LV_GC_ROOT(_lv_task_ll)); + f8e0: 4604 mov r4, r0 + LV_ASSERT_MEM(new_task); + f8e2: 4798 blx r3 + f8e4: 2800 cmp r0, #0 + f8e6: d1ed bne.n f8c4 + f8e8: 4b16 ldr r3, [pc, #88] ; (f944 ) + f8ea: 4917 ldr r1, [pc, #92] ; (f948 ) + f8ec: 9300 str r3, [sp, #0] + f8ee: 22e5 movs r2, #229 ; 0xe5 + f8f0: 2003 movs r0, #3 + f8f2: 4e16 ldr r6, [pc, #88] ; (f94c ) + f8f4: 47b0 blx r6 + f8f6: 4816 ldr r0, [pc, #88] ; (f950 ) + f8f8: 4916 ldr r1, [pc, #88] ; (f954 ) + f8fa: 4622 mov r2, r4 + f8fc: 462b mov r3, r5 + f8fe: 4788 blx r1 + f900: e7fe b.n f900 + new_task->period = DEF_PERIOD; + f902: f44f 73fa mov.w r3, #500 ; 0x1f4 + f906: 6023 str r3, [r4, #0] + new_task->prio = DEF_PRIO; + f908: 7d23 ldrb r3, [r4, #20] + task_list_changed = true; + f90a: 4d15 ldr r5, [pc, #84] ; (f960 ) + new_task->prio = DEF_PRIO; + f90c: 2203 movs r2, #3 + f90e: f362 0302 bfi r3, r2, #0, #3 + new_task->task_cb = NULL; + f912: 2700 movs r7, #0 + new_task->prio = DEF_PRIO; + f914: 7523 strb r3, [r4, #20] + new_task->repeat_count = -1; + f916: f04f 33ff mov.w r3, #4294967295 ; 0xffffffff + task_list_changed = true; + f91a: 2601 movs r6, #1 + new_task->repeat_count = -1; + f91c: 6123 str r3, [r4, #16] + new_task->task_cb = NULL; + f91e: 60a7 str r7, [r4, #8] + new_task->last_run = lv_tick_get(); + f920: 4b10 ldr r3, [pc, #64] ; (f964 ) + task_list_changed = true; + f922: 702e strb r6, [r5, #0] + new_task->last_run = lv_tick_get(); + f924: 4798 blx r3 + new_task->user_data = NULL; + f926: 60e7 str r7, [r4, #12] + new_task->last_run = lv_tick_get(); + f928: 6060 str r0, [r4, #4] + task_created = true; + f92a: 70ae strb r6, [r5, #2] + return new_task; + f92c: e7cc b.n f8c8 + f92e: bf00 nop + f930: 0000e6a9 .word 0x0000e6a9 + f934: 20008600 .word 0x20008600 + f938: 0000e6b5 .word 0x0000e6b5 + f93c: 0000e6f5 .word 0x0000e6f5 + f940: 000017e1 .word 0x000017e1 + f944: 000241c2 .word 0x000241c2 + f948: 00024192 .word 0x00024192 + f94c: 0000e8e9 .word 0x0000e8e9 + f950: 0001edbe .word 0x0001edbe + f954: 000017e9 .word 0x000017e9 + f958: 0000e619 .word 0x0000e619 + f95c: 0000e661 .word 0x0000e661 + f960: 2000c7b4 .word 0x2000c7b4 + f964: 0000da49 .word 0x0000da49 + +0000f968 : +{ + f968: b570 push {r4, r5, r6, lr} + _lv_ll_remove(&LV_GC_ROOT(_lv_task_ll), task); + f96a: 4601 mov r1, r0 +{ + f96c: 4604 mov r4, r0 + _lv_ll_remove(&LV_GC_ROOT(_lv_task_ll), task); + f96e: 4b07 ldr r3, [pc, #28] ; (f98c ) + f970: 4807 ldr r0, [pc, #28] ; (f990 ) + task_list_changed = true; + f972: 4d08 ldr r5, [pc, #32] ; (f994 ) + _lv_ll_remove(&LV_GC_ROOT(_lv_task_ll), task); + f974: 4798 blx r3 + task_list_changed = true; + f976: 2601 movs r6, #1 + lv_mem_free(task); + f978: 4b07 ldr r3, [pc, #28] ; (f998 ) + task_list_changed = true; + f97a: 702e strb r6, [r5, #0] + lv_mem_free(task); + f97c: 4620 mov r0, r4 + f97e: 4798 blx r3 + if(LV_GC_ROOT(_lv_task_act) == task) task_deleted = true; /*The active task was deleted*/ + f980: 4b06 ldr r3, [pc, #24] ; (f99c ) + f982: 681b ldr r3, [r3, #0] + f984: 42a3 cmp r3, r4 + f986: bf08 it eq + f988: 70ee strbeq r6, [r5, #3] +} + f98a: bd70 pop {r4, r5, r6, pc} + f98c: 0000e76d .word 0x0000e76d + f990: 20008600 .word 0x20008600 + f994: 2000c7b4 .word 0x2000c7b4 + f998: 0000eae5 .word 0x0000eae5 + f99c: 20008670 .word 0x20008670 + +0000f9a0 : + * Execute task if its the priority is appropriate + * @param task pointer to lv_task + * @return true: execute, false: not executed + */ +static bool lv_task_exec(lv_task_t * task) +{ + f9a0: b538 push {r3, r4, r5, lr} + * @return the time remaining, or 0 if it needs to be run again + */ +static uint32_t lv_task_time_remaining(lv_task_t * task) +{ + /*Check if at least 'period' time elapsed*/ + uint32_t elp = lv_tick_elaps(task->last_run); + f9a2: 4b12 ldr r3, [pc, #72] ; (f9ec ) +{ + f9a4: 4604 mov r4, r0 + uint32_t elp = lv_tick_elaps(task->last_run); + f9a6: 6840 ldr r0, [r0, #4] + f9a8: 4798 blx r3 + if(lv_task_time_remaining(task) == 0) { + f9aa: 6823 ldr r3, [r4, #0] + f9ac: 4298 cmp r0, r3 + f9ae: d31b bcc.n f9e8 + task->last_run = lv_tick_get(); + f9b0: 4b0f ldr r3, [pc, #60] ; (f9f0 ) + task_deleted = false; + f9b2: 4d10 ldr r5, [pc, #64] ; (f9f4 ) + task->last_run = lv_tick_get(); + f9b4: 4798 blx r3 + task_deleted = false; + f9b6: 2300 movs r3, #0 + f9b8: 70eb strb r3, [r5, #3] + task_created = false; + f9ba: 70ab strb r3, [r5, #2] + if(task->task_cb) task->task_cb(task); + f9bc: 68a3 ldr r3, [r4, #8] + task->last_run = lv_tick_get(); + f9be: 6060 str r0, [r4, #4] + if(task->task_cb) task->task_cb(task); + f9c0: b943 cbnz r3, f9d4 + if(task->repeat_count > 0) { + f9c2: 6923 ldr r3, [r4, #16] + f9c4: 2b00 cmp r3, #0 + f9c6: dc0c bgt.n f9e2 + if(task->repeat_count == 0) { + f9c8: 6923 ldr r3, [r4, #16] + f9ca: b943 cbnz r3, f9de + lv_task_del(task); + f9cc: 4b0a ldr r3, [pc, #40] ; (f9f8 ) + f9ce: 4620 mov r0, r4 + f9d0: 4798 blx r3 + f9d2: e004 b.n f9de + if(task->task_cb) task->task_cb(task); + f9d4: 4620 mov r0, r4 + f9d6: 4798 blx r3 + if(task_deleted == false) { /*The task might be deleted by itself as well*/ + f9d8: 78eb ldrb r3, [r5, #3] + f9da: 2b00 cmp r3, #0 + f9dc: d0f1 beq.n f9c2 + lv_task_del(task); + f9de: 2001 movs r0, #1 +} + f9e0: bd38 pop {r3, r4, r5, pc} + task->repeat_count--; + f9e2: 3b01 subs r3, #1 + f9e4: 6123 str r3, [r4, #16] + f9e6: e7ef b.n f9c8 + bool exec = false; + f9e8: 2000 movs r0, #0 + f9ea: e7f9 b.n f9e0 + f9ec: 0000da5d .word 0x0000da5d + f9f0: 0000da49 .word 0x0000da49 + f9f4: 2000c7b4 .word 0x2000c7b4 + f9f8: 0000f969 .word 0x0000f969 + +0000f9fc : +{ + f9fc: e92d 4ff8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, lr} + if(already_running) return 1; + fa00: f8df b15c ldr.w fp, [pc, #348] ; fb60 + fa04: f89b 4004 ldrb.w r4, [fp, #4] + fa08: 2001 movs r0, #1 + fa0a: b934 cbnz r4, fa1a + if(lv_task_run == false) { + fa0c: f89b 2001 ldrb.w r2, [fp, #1] + already_running = true; + fa10: f88b 0004 strb.w r0, [fp, #4] + if(lv_task_run == false) { + fa14: b91a cbnz r2, fa1e + already_running = false; /*Release mutex*/ + fa16: f88b 2004 strb.w r2, [fp, #4] +} + fa1a: e8bd 8ff8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, sl, fp, pc} + handler_start = lv_tick_get(); + fa1e: f8df 8144 ldr.w r8, [pc, #324] ; fb64 + LV_GC_ROOT(_lv_task_act) = _lv_ll_get_head(&LV_GC_ROOT(_lv_task_ll)); + fa22: f8df a138 ldr.w sl, [pc, #312] ; fb5c + fa26: f8df 9140 ldr.w r9, [pc, #320] ; fb68 + handler_start = lv_tick_get(); + fa2a: 47c0 blx r8 + fa2c: f8cb 0008 str.w r0, [fp, #8] + task_deleted = false; + fa30: 2200 movs r2, #0 + LV_GC_ROOT(_lv_task_act) = _lv_ll_get_head(&LV_GC_ROOT(_lv_task_ll)); + fa32: 4650 mov r0, sl + task_deleted = false; + fa34: f88b 2003 strb.w r2, [fp, #3] + task_created = false; + fa38: f88b 2002 strb.w r2, [fp, #2] + LV_GC_ROOT(_lv_task_act) = _lv_ll_get_head(&LV_GC_ROOT(_lv_task_ll)); + fa3c: 47c8 blx r9 + fa3e: 4d43 ldr r5, [pc, #268] ; (fb4c ) + if(lv_task_exec(LV_GC_ROOT(_lv_task_act))) { + fa40: 4f43 ldr r7, [pc, #268] ; (fb50 ) + LV_GC_ROOT(_lv_task_act) = _lv_ll_get_head(&LV_GC_ROOT(_lv_task_ll)); + fa42: 6028 str r0, [r5, #0] + while(LV_GC_ROOT(_lv_task_act)) { + fa44: 6829 ldr r1, [r5, #0] + fa46: b189 cbz r1, fa6c + next = _lv_ll_get_next(&LV_GC_ROOT(_lv_task_ll), LV_GC_ROOT(_lv_task_act)); + fa48: 4b42 ldr r3, [pc, #264] ; (fb54 ) + fa4a: 4650 mov r0, sl + fa4c: 4798 blx r3 + fa4e: 4606 mov r6, r0 + if(((lv_task_t *)LV_GC_ROOT(_lv_task_act))->prio == LV_TASK_PRIO_OFF) { + fa50: 6828 ldr r0, [r5, #0] + fa52: 7d02 ldrb r2, [r0, #20] + fa54: f012 0107 ands.w r1, r2, #7 + fa58: d008 beq.n fa6c + if(LV_GC_ROOT(_lv_task_act) == task_interrupter) { + fa5a: 42a0 cmp r0, r4 + fa5c: d050 beq.n fb00 + if(((lv_task_t *)LV_GC_ROOT(_lv_task_act))->prio == LV_TASK_PRIO_HIGHEST) { + fa5e: 2905 cmp r1, #5 + fa60: d139 bne.n fad6 + lv_task_exec(LV_GC_ROOT(_lv_task_act)); + fa62: 47b8 blx r7 + if(task_created || task_deleted) { + fa64: f89b 2002 ldrb.w r2, [fp, #2] + fa68: 2a00 cmp r2, #0 + fa6a: d062 beq.n fb32 + busy_time += lv_tick_elaps(handler_start); + fa6c: 4c3a ldr r4, [pc, #232] ; (fb58 ) + fa6e: f8db 0008 ldr.w r0, [fp, #8] + fa72: 47a0 blx r4 + fa74: f8db 200c ldr.w r2, [fp, #12] + fa78: 4410 add r0, r2 + fa7a: f8cb 000c str.w r0, [fp, #12] + uint32_t idle_period_time = lv_tick_elaps(idle_period_start); + fa7e: f8db 0014 ldr.w r0, [fp, #20] + fa82: 47a0 blx r4 + if(idle_period_time >= IDLE_MEAS_PERIOD) { + fa84: f5b0 7ffa cmp.w r0, #500 ; 0x1f4 + fa88: d316 bcc.n fab8 + idle_last = (uint32_t)((uint32_t)busy_time * 100) / IDLE_MEAS_PERIOD; /*Calculate the busy percentage*/ + fa8a: f8db 200c ldr.w r2, [fp, #12] + fa8e: 2164 movs r1, #100 ; 0x64 + fa90: 434a muls r2, r1 + fa92: f44f 71fa mov.w r1, #500 ; 0x1f4 + fa96: fbb2 f2f1 udiv r2, r2, r1 + fa9a: b2d2 uxtb r2, r2 + idle_last = idle_last > 100 ? 0 : 100 - idle_last; /*But we need idle time*/ + fa9c: 2a64 cmp r2, #100 ; 0x64 + fa9e: bf9a itte ls + faa0: f1c2 0264 rsbls r2, r2, #100 ; 0x64 + faa4: b2d2 uxtbls r2, r2 + faa6: 2200 movhi r2, #0 + faa8: f88b 2010 strb.w r2, [fp, #16] + busy_time = 0; + faac: 2200 movs r2, #0 + faae: f8cb 200c str.w r2, [fp, #12] + idle_period_start = lv_tick_get(); + fab2: 47c0 blx r8 + fab4: f8cb 0014 str.w r0, [fp, #20] + time_till_next = LV_NO_TASK_READY; + fab8: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + next = _lv_ll_get_head(&LV_GC_ROOT(_lv_task_ll)); + fabc: 4827 ldr r0, [pc, #156] ; (fb5c ) + time_till_next = LV_NO_TASK_READY; + fabe: f8cb 2018 str.w r2, [fp, #24] + next = _lv_ll_get_head(&LV_GC_ROOT(_lv_task_ll)); + fac2: 47c8 blx r9 + next = _lv_ll_get_next(&LV_GC_ROOT(_lv_task_ll), next); /*Find the next task*/ + fac4: 4e25 ldr r6, [pc, #148] ; (fb5c ) + fac6: 4f23 ldr r7, [pc, #140] ; (fb54 ) + next = _lv_ll_get_head(&LV_GC_ROOT(_lv_task_ll)); + fac8: 4605 mov r5, r0 + while(next) { + faca: b9e5 cbnz r5, fb06 + return time_till_next; + facc: f8db 0018 ldr.w r0, [fp, #24] + already_running = false; /*Release the mutex*/ + fad0: f88b 5004 strb.w r5, [fp, #4] + return time_till_next; + fad4: e7a1 b.n fa1a + else if(task_interrupter) { + fad6: b134 cbz r4, fae6 + if(((lv_task_t *)LV_GC_ROOT(_lv_task_act))->prio > task_interrupter->prio) { + fad8: 7d21 ldrb r1, [r4, #20] + fada: f002 0207 and.w r2, r2, #7 + fade: f001 0107 and.w r1, r1, #7 + fae2: 428a cmp r2, r1 + fae4: d9be bls.n fa64 + if(lv_task_exec(LV_GC_ROOT(_lv_task_act))) { + fae6: 47b8 blx r7 + fae8: 2800 cmp r0, #0 + faea: d0bb beq.n fa64 + if(!task_created && !task_deleted) { + faec: f89b 2002 ldrb.w r2, [fp, #2] + faf0: 2a00 cmp r2, #0 + faf2: d1bb bne.n fa6c + faf4: f89b 2003 ldrb.w r2, [fp, #3] + faf8: 2a00 cmp r2, #0 + fafa: d1b7 bne.n fa6c + task_interrupter = LV_GC_ROOT(_lv_task_act); /*Check all tasks again from the highest priority */ + fafc: 682c ldr r4, [r5, #0] + } while(!end_flag); + fafe: e797 b.n fa30 + task_interrupter = NULL; /*From this point only task after the interrupter comes, so + fb00: 2400 movs r4, #0 + LV_GC_ROOT(_lv_task_act) = next; + fb02: 602e str r6, [r5, #0] + fb04: e79e b.n fa44 + if(next->prio != LV_TASK_PRIO_OFF) { + fb06: 7d2a ldrb r2, [r5, #20] + fb08: 0753 lsls r3, r2, #29 + fb0a: d00d beq.n fb28 + uint32_t elp = lv_tick_elaps(task->last_run); + fb0c: 6868 ldr r0, [r5, #4] + fb0e: 47a0 blx r4 + if(elp >= task->period) + fb10: 682a ldr r2, [r5, #0] + fb12: 4290 cmp r0, r2 + return 0; + return task->period - elp; + fb14: bf38 it cc + fb16: 1a10 subcc r0, r2, r0 + if(delay < time_till_next) + fb18: f8db 2018 ldr.w r2, [fp, #24] + return 0; + fb1c: bf28 it cs + fb1e: 2000 movcs r0, #0 + if(delay < time_till_next) + fb20: 4282 cmp r2, r0 + time_till_next = delay; + fb22: bf88 it hi + fb24: f8cb 0018 strhi.w r0, [fp, #24] + next = _lv_ll_get_next(&LV_GC_ROOT(_lv_task_ll), next); /*Find the next task*/ + fb28: 4629 mov r1, r5 + fb2a: 4630 mov r0, r6 + fb2c: 47b8 blx r7 + fb2e: 4605 mov r5, r0 + fb30: e7cb b.n faca + if(task_created || task_deleted) { + fb32: f89b 2003 ldrb.w r2, [fp, #3] + fb36: 2a00 cmp r2, #0 + fb38: d198 bne.n fa6c + if(task_list_changed) { + fb3a: f89b 1000 ldrb.w r1, [fp] + fb3e: 2900 cmp r1, #0 + fb40: d0df beq.n fb02 + task_list_changed = false; + fb42: f88b 2000 strb.w r2, [fp] + task_interrupter = NULL; + fb46: 4614 mov r4, r2 + fb48: e772 b.n fa30 + fb4a: bf00 nop + fb4c: 20008670 .word 0x20008670 + fb50: 0000f9a1 .word 0x0000f9a1 + fb54: 0000e6b5 .word 0x0000e6b5 + fb58: 0000da5d .word 0x0000da5d + fb5c: 20008600 .word 0x20008600 + fb60: 2000c7b4 .word 0x2000c7b4 + fb64: 0000da49 .word 0x0000da49 + fb68: 0000e6a9 .word 0x0000e6a9 + +0000fb6c : +{ + fb6c: b5f8 push {r3, r4, r5, r6, r7, lr} + if(task->prio == prio) return; + fb6e: 7d03 ldrb r3, [r0, #20] + fb70: f003 0307 and.w r3, r3, #7 + fb74: 428b cmp r3, r1 +{ + fb76: 4604 mov r4, r0 + fb78: 460d mov r5, r1 + if(task->prio == prio) return; + fb7a: d018 beq.n fbae + _LV_LL_READ(LV_GC_ROOT(_lv_task_ll), i) { + fb7c: 480f ldr r0, [pc, #60] ; (fbbc ) + fb7e: 4b10 ldr r3, [pc, #64] ; (fbc0 ) + fb80: 4e0e ldr r6, [pc, #56] ; (fbbc ) + fb82: 4f10 ldr r7, [pc, #64] ; (fbc4 ) + fb84: 4798 blx r3 + fb86: 4602 mov r2, r0 + fb88: b132 cbz r2, fb98 + if(i->prio <= prio) { + fb8a: 7d13 ldrb r3, [r2, #20] + fb8c: f003 0307 and.w r3, r3, #7 + fb90: 429d cmp r5, r3 + fb92: db0d blt.n fbb0 + if(i != task) _lv_ll_move_before(&LV_GC_ROOT(_lv_task_ll), task, i); + fb94: 42a2 cmp r2, r4 + fb96: d003 beq.n fba0 + _lv_ll_move_before(&LV_GC_ROOT(_lv_task_ll), task, NULL); + fb98: 4808 ldr r0, [pc, #32] ; (fbbc ) + fb9a: 4b0b ldr r3, [pc, #44] ; (fbc8 ) + fb9c: 4621 mov r1, r4 + fb9e: 4798 blx r3 + task_list_changed = true; + fba0: 4b0a ldr r3, [pc, #40] ; (fbcc ) + fba2: 2201 movs r2, #1 + fba4: 701a strb r2, [r3, #0] + task->prio = prio; + fba6: 7d23 ldrb r3, [r4, #20] + fba8: f365 0302 bfi r3, r5, #0, #3 + fbac: 7523 strb r3, [r4, #20] +} + fbae: bdf8 pop {r3, r4, r5, r6, r7, pc} + _LV_LL_READ(LV_GC_ROOT(_lv_task_ll), i) { + fbb0: 4611 mov r1, r2 + fbb2: 4630 mov r0, r6 + fbb4: 47b8 blx r7 + fbb6: 4602 mov r2, r0 + fbb8: e7e6 b.n fb88 + fbba: bf00 nop + fbbc: 20008600 .word 0x20008600 + fbc0: 0000e6a9 .word 0x0000e6a9 + fbc4: 0000e6b5 .word 0x0000e6b5 + fbc8: 0000e85d .word 0x0000e85d + fbcc: 2000c7b4 .word 0x2000c7b4 + +0000fbd0 : +{ + fbd0: e92d 41ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, lr} + fbd4: 461e mov r6, r3 + lv_task_t * new_task = lv_task_create_basic(); + fbd6: 4b12 ldr r3, [pc, #72] ; (fc20 ) +{ + fbd8: 9203 str r2, [sp, #12] + fbda: 460f mov r7, r1 + fbdc: 4680 mov r8, r0 + lv_task_t * new_task = lv_task_create_basic(); + fbde: 4798 blx r3 + LV_ASSERT_MEM(new_task); + fbe0: 4b10 ldr r3, [pc, #64] ; (fc24 ) + lv_task_t * new_task = lv_task_create_basic(); + fbe2: 4604 mov r4, r0 + LV_ASSERT_MEM(new_task); + fbe4: 4798 blx r3 + fbe6: 9903 ldr r1, [sp, #12] + fbe8: 4605 mov r5, r0 + fbea: b968 cbnz r0, fc08 + fbec: 4b0e ldr r3, [pc, #56] ; (fc28 ) + fbee: 490f ldr r1, [pc, #60] ; (fc2c ) + fbf0: 9300 str r3, [sp, #0] + fbf2: f44f 7283 mov.w r2, #262 ; 0x106 + fbf6: 2003 movs r0, #3 + fbf8: 4e0d ldr r6, [pc, #52] ; (fc30 ) + fbfa: 47b0 blx r6 + fbfc: 480d ldr r0, [pc, #52] ; (fc34 ) + fbfe: 490e ldr r1, [pc, #56] ; (fc38 ) + fc00: 4622 mov r2, r4 + fc02: 462b mov r3, r5 + fc04: 4788 blx r1 + fc06: e7fe b.n fc06 + if(new_task == NULL) return NULL; + fc08: b134 cbz r4, fc18 + lv_task_set_prio(new_task, prio); + fc0a: 4b0c ldr r3, [pc, #48] ; (fc3c ) + task->task_cb = task_cb; + fc0c: f8c4 8008 str.w r8, [r4, #8] + task->period = period; + fc10: 6027 str r7, [r4, #0] + lv_task_set_prio(new_task, prio); + fc12: 4620 mov r0, r4 + fc14: 4798 blx r3 + new_task->user_data = user_data; + fc16: 60e6 str r6, [r4, #12] +} + fc18: 4620 mov r0, r4 + fc1a: b004 add sp, #16 + fc1c: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + fc20: 0000f855 .word 0x0000f855 + fc24: 000017e1 .word 0x000017e1 + fc28: 000241d7 .word 0x000241d7 + fc2c: 00024192 .word 0x00024192 + fc30: 0000e8e9 .word 0x0000e8e9 + fc34: 0001edbe .word 0x0001edbe + fc38: 000017e9 .word 0x000017e9 + fc3c: 0000fb6d .word 0x0000fb6d + +0000fc40 : +{ + fc40: b510 push {r4, lr} + task->last_run = lv_tick_get() - task->period - 1; + fc42: 4b04 ldr r3, [pc, #16] ; (fc54 ) +{ + fc44: 4604 mov r4, r0 + task->last_run = lv_tick_get() - task->period - 1; + fc46: 4798 blx r3 + fc48: 6823 ldr r3, [r4, #0] + fc4a: 1ac3 subs r3, r0, r3 + fc4c: 3b01 subs r3, #1 + fc4e: 6063 str r3, [r4, #4] +} + fc50: bd10 pop {r4, pc} + fc52: bf00 nop + fc54: 0000da49 .word 0x0000da49 + +0000fc58 : + * @param str pointer to a character in a string + * @return length of the UTF-8 character (1,2,3 or 4). O on invalid code + */ +static uint8_t lv_txt_utf8_size(const char * str) +{ + if((str[0] & 0x80) == 0) + fc58: f990 2000 ldrsb.w r2, [r0] + fc5c: 7803 ldrb r3, [r0, #0] + fc5e: 2a00 cmp r2, #0 + fc60: da0f bge.n fc82 + return 1; + else if((str[0] & 0xE0) == 0xC0) + fc62: f003 02e0 and.w r2, r3, #224 ; 0xe0 + fc66: 2ac0 cmp r2, #192 ; 0xc0 + fc68: d00d beq.n fc86 + return 2; + else if((str[0] & 0xF0) == 0xE0) + fc6a: f003 02f0 and.w r2, r3, #240 ; 0xf0 + fc6e: 2ae0 cmp r2, #224 ; 0xe0 + fc70: d00b beq.n fc8a + return 3; + else if((str[0] & 0xF8) == 0xF0) + fc72: f003 00f8 and.w r0, r3, #248 ; 0xf8 + fc76: f1a0 03f0 sub.w r3, r0, #240 ; 0xf0 + fc7a: 4258 negs r0, r3 + fc7c: 4158 adcs r0, r3 + fc7e: 0080 lsls r0, r0, #2 + fc80: 4770 bx lr + return 1; + fc82: 2001 movs r0, #1 + fc84: 4770 bx lr + return 2; + fc86: 2002 movs r0, #2 + fc88: 4770 bx lr + return 3; + fc8a: 2003 movs r0, #3 + return 4; + return 0; /*If the char was invalid tell it's 1 byte long*/ +} + fc8c: 4770 bx lr + +0000fc8e : + * After call it will point to the next UTF-8 char in 'txt'. + * NULL to use txt[0] as index + * @return the decoded Unicode character or 0 on invalid UTF-8 code + */ +static uint32_t lv_txt_utf8_next(const char * txt, uint32_t * i) +{ + fc8e: b573 push {r0, r1, r4, r5, r6, lr} + * */ + + uint32_t result = 0; + + /*Dummy 'i' pointer is required*/ + uint32_t i_tmp = 0; + fc90: 2300 movs r3, #0 + fc92: 9301 str r3, [sp, #4] + if(i == NULL) i = &i_tmp; + fc94: b901 cbnz r1, fc98 + fc96: a901 add r1, sp, #4 + + /*Normal ASCII*/ + if((txt[*i] & 0x80) == 0) { + fc98: 680a ldr r2, [r1, #0] + fc9a: 5685 ldrsb r5, [r0, r2] + fc9c: 5c83 ldrb r3, [r0, r2] + fc9e: 2d00 cmp r5, #0 + result = txt[*i]; + (*i)++; + fca0: f102 0401 add.w r4, r2, #1 + if((txt[*i] & 0x80) == 0) { + fca4: db03 blt.n fcae + result = txt[*i]; + fca6: 4618 mov r0, r3 + (*i)++; + fca8: 600c str r4, [r1, #0] + else { + (*i)++; /*Not UTF-8 char. Go the next.*/ + } + } + return result; +} + fcaa: b002 add sp, #8 + fcac: bd70 pop {r4, r5, r6, pc} + if((txt[*i] & 0xE0) == 0xC0) { + fcae: f003 05e0 and.w r5, r3, #224 ; 0xe0 + fcb2: 2dc0 cmp r5, #192 ; 0xc0 + fcb4: d110 bne.n fcd8 + (*i)++; + fcb6: 600c str r4, [r1, #0] + if((txt[*i] & 0xC0) != 0x80) return 0; /*Invalid UTF-8 code*/ + fcb8: 5d00 ldrb r0, [r0, r4] + fcba: f000 04c0 and.w r4, r0, #192 ; 0xc0 + fcbe: 2c80 cmp r4, #128 ; 0x80 + fcc0: d001 beq.n fcc6 + uint32_t result = 0; + fcc2: 2000 movs r0, #0 + fcc4: e7f1 b.n fcaa + result = (uint32_t)(txt[*i] & 0x1F) << 6; + fcc6: 019b lsls r3, r3, #6 + fcc8: f403 63f8 and.w r3, r3, #1984 ; 0x7c0 + result += (txt[*i] & 0x3F); + fccc: f000 003f and.w r0, r0, #63 ; 0x3f + fcd0: 4418 add r0, r3 + (*i)++; + fcd2: 3202 adds r2, #2 + (*i)++; + fcd4: 600a str r2, [r1, #0] + fcd6: e7e8 b.n fcaa + else if((txt[*i] & 0xF0) == 0xE0) { + fcd8: f003 05f0 and.w r5, r3, #240 ; 0xf0 + fcdc: 2de0 cmp r5, #224 ; 0xe0 + fcde: d117 bne.n fd10 + (*i)++; + fce0: 600c str r4, [r1, #0] + if((txt[*i] & 0xC0) != 0x80) return 0; /*Invalid UTF-8 code*/ + fce2: 5d04 ldrb r4, [r0, r4] + fce4: f004 05c0 and.w r5, r4, #192 ; 0xc0 + fce8: 2d80 cmp r5, #128 ; 0x80 + fcea: d1ea bne.n fcc2 + (*i)++; + fcec: 1c95 adds r5, r2, #2 + fcee: 600d str r5, [r1, #0] + if((txt[*i] & 0xC0) != 0x80) return 0; /*Invalid UTF-8 code*/ + fcf0: 5d45 ldrb r5, [r0, r5] + fcf2: f005 00c0 and.w r0, r5, #192 ; 0xc0 + fcf6: 2880 cmp r0, #128 ; 0x80 + fcf8: d1e3 bne.n fcc2 + result = (uint32_t)(txt[*i] & 0x0F) << 12; + fcfa: 0318 lsls r0, r3, #12 + fcfc: b280 uxth r0, r0 + result += (txt[*i] & 0x3F); + fcfe: f005 053f and.w r5, r5, #63 ; 0x3f + result += (uint32_t)(txt[*i] & 0x3F) << 6; + fd02: 01a4 lsls r4, r4, #6 + fd04: 4428 add r0, r5 + fd06: f404 647c and.w r4, r4, #4032 ; 0xfc0 + result += (txt[*i] & 0x3F); + fd0a: 4420 add r0, r4 + (*i)++; + fd0c: 3203 adds r2, #3 + fd0e: e7e1 b.n fcd4 + else if((txt[*i] & 0xF8) == 0xF0) { + fd10: f003 05f8 and.w r5, r3, #248 ; 0xf8 + fd14: 2df0 cmp r5, #240 ; 0xf0 + (*i)++; + fd16: 600c str r4, [r1, #0] + else if((txt[*i] & 0xF8) == 0xF0) { + fd18: d1d3 bne.n fcc2 + if((txt[*i] & 0xC0) != 0x80) return 0; /*Invalid UTF-8 code*/ + fd1a: 5d04 ldrb r4, [r0, r4] + fd1c: f004 05c0 and.w r5, r4, #192 ; 0xc0 + fd20: 2d80 cmp r5, #128 ; 0x80 + fd22: d1ce bne.n fcc2 + (*i)++; + fd24: 1c95 adds r5, r2, #2 + fd26: 600d str r5, [r1, #0] + if((txt[*i] & 0xC0) != 0x80) return 0; /*Invalid UTF-8 code*/ + fd28: 5d45 ldrb r5, [r0, r5] + fd2a: f005 06c0 and.w r6, r5, #192 ; 0xc0 + fd2e: 2e80 cmp r6, #128 ; 0x80 + fd30: d1c7 bne.n fcc2 + (*i)++; + fd32: 1cd6 adds r6, r2, #3 + fd34: 600e str r6, [r1, #0] + if((txt[*i] & 0xC0) != 0x80) return 0; /*Invalid UTF-8 code*/ + fd36: 5d80 ldrb r0, [r0, r6] + fd38: f000 06c0 and.w r6, r0, #192 ; 0xc0 + fd3c: 2e80 cmp r6, #128 ; 0x80 + fd3e: d1c0 bne.n fcc2 + result = (uint32_t)(txt[*i] & 0x07) << 18; + fd40: 049b lsls r3, r3, #18 + result += (uint32_t)(txt[*i] & 0x3F) << 12; + fd42: 0324 lsls r4, r4, #12 + result += (uint32_t)(txt[*i] & 0x3F) << 6; + fd44: 01ad lsls r5, r5, #6 + result += txt[*i] & 0x3F; + fd46: f000 003f and.w r0, r0, #63 ; 0x3f + result = (uint32_t)(txt[*i] & 0x07) << 18; + fd4a: f403 13e0 and.w r3, r3, #1835008 ; 0x1c0000 + result += (uint32_t)(txt[*i] & 0x3F) << 12; + fd4e: f404 347c and.w r4, r4, #258048 ; 0x3f000 + result += (uint32_t)(txt[*i] & 0x3F) << 6; + fd52: f405 657c and.w r5, r5, #4032 ; 0xfc0 + result += (uint32_t)(txt[*i] & 0x3F) << 12; + fd56: 431c orrs r4, r3 + result += txt[*i] & 0x3F; + fd58: 4405 add r5, r0 + fd5a: 1928 adds r0, r5, r4 + (*i)++; + fd5c: 3204 adds r2, #4 + fd5e: e7b9 b.n fcd4 + +0000fd60 : +{ + uint8_t c_size; + uint8_t cnt = 0; + + /*Try to find a !0 long UTF-8 char by stepping one character back*/ + (*i)--; + fd60: 680b ldr r3, [r1, #0] +{ + fd62: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} + (*i)--; + fd64: 3b01 subs r3, #1 + do { + if(cnt >= 4) return 0; /*No UTF-8 char found before the initial*/ + + c_size = _lv_txt_encoded_size(&txt[*i]); + fd66: 4f0d ldr r7, [pc, #52] ; (fd9c ) + (*i)--; + fd68: 600b str r3, [r1, #0] +{ + fd6a: 4606 mov r6, r0 + fd6c: 460c mov r4, r1 + (*i)--; + fd6e: 2504 movs r5, #4 + c_size = _lv_txt_encoded_size(&txt[*i]); + fd70: 6820 ldr r0, [r4, #0] + fd72: 683b ldr r3, [r7, #0] + fd74: 4430 add r0, r6 + fd76: 4798 blx r3 + if(c_size == 0) { + fd78: 6823 ldr r3, [r4, #0] + fd7a: b948 cbnz r0, fd90 + if(*i != 0) + fd7c: b12b cbz r3, fd8a + if(cnt >= 4) return 0; /*No UTF-8 char found before the initial*/ + fd7e: 3d01 subs r5, #1 + (*i)--; + fd80: 3b01 subs r3, #1 + if(cnt >= 4) return 0; /*No UTF-8 char found before the initial*/ + fd82: f015 05ff ands.w r5, r5, #255 ; 0xff + (*i)--; + fd86: 6023 str r3, [r4, #0] + if(cnt >= 4) return 0; /*No UTF-8 char found before the initial*/ + fd88: d1f2 bne.n fd70 + fd8a: 2000 movs r0, #0 + + uint32_t i_tmp = *i; + uint32_t letter = _lv_txt_encoded_next(txt, &i_tmp); /*Character found, get it*/ + + return letter; +} + fd8c: b003 add sp, #12 + fd8e: bdf0 pop {r4, r5, r6, r7, pc} + uint32_t i_tmp = *i; + fd90: 9301 str r3, [sp, #4] + uint32_t letter = _lv_txt_encoded_next(txt, &i_tmp); /*Character found, get it*/ + fd92: a901 add r1, sp, #4 + fd94: 687b ldr r3, [r7, #4] + fd96: 4630 mov r0, r6 + fd98: 4798 blx r3 + return letter; + fd9a: e7f7 b.n fd8c + fd9c: 20000054 .word 0x20000054 + +0000fda0 : + * @param txt a '\0' terminated UTF-8 string + * @param utf8_id character index + * @return byte index of the 'utf8_id'th letter + */ +static uint32_t lv_txt_utf8_get_byte_id(const char * txt, uint32_t utf8_id) +{ + fda0: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + uint32_t i; + uint32_t byte_cnt = 0; + fda4: 2400 movs r4, #0 + for(i = 0; i < utf8_id; i++) { + uint8_t c_size = _lv_txt_encoded_size(&txt[byte_cnt]); + fda6: f8df 8028 ldr.w r8, [pc, #40] ; fdd0 +{ + fdaa: 4607 mov r7, r0 + fdac: 460d mov r5, r1 + for(i = 0; i < utf8_id; i++) { + fdae: 4626 mov r6, r4 + fdb0: 42ae cmp r6, r5 + fdb2: d102 bne.n fdba + byte_cnt += c_size > 0 ? c_size : 1; + } + + return byte_cnt; +} + fdb4: 4620 mov r0, r4 + fdb6: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + uint8_t c_size = _lv_txt_encoded_size(&txt[byte_cnt]); + fdba: 1938 adds r0, r7, r4 + fdbc: f8d8 3000 ldr.w r3, [r8] + fdc0: 4798 blx r3 + byte_cnt += c_size > 0 ? c_size : 1; + fdc2: 2801 cmp r0, #1 + fdc4: bf38 it cc + fdc6: 2001 movcc r0, #1 + fdc8: fa54 f480 uxtab r4, r4, r0 + for(i = 0; i < utf8_id; i++) { + fdcc: 3601 adds r6, #1 + fdce: e7ef b.n fdb0 + fdd0: 20000054 .word 0x20000054 + +0000fdd4 : + * @param txt a '\0' terminated UTF-8 string + * @param byte_id byte index + * @return character index of the letter at 'byte_id'th position + */ +static uint32_t lv_txt_utf8_get_char_id(const char * txt, uint32_t byte_id) +{ + fdd4: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} + uint32_t i = 0; + fdd6: 2400 movs r4, #0 + uint32_t char_cnt = 0; + + while(i < byte_id) { + _lv_txt_encoded_next(txt, &i); /*'i' points to the next letter so use the prev. value*/ + fdd8: 4f07 ldr r7, [pc, #28] ; (fdf8 ) + uint32_t i = 0; + fdda: 9401 str r4, [sp, #4] +{ + fddc: 4606 mov r6, r0 + fdde: 460d mov r5, r1 + while(i < byte_id) { + fde0: 9b01 ldr r3, [sp, #4] + fde2: 42ab cmp r3, r5 + fde4: d302 bcc.n fdec + char_cnt++; + } + + return char_cnt; +} + fde6: 4620 mov r0, r4 + fde8: b003 add sp, #12 + fdea: bdf0 pop {r4, r5, r6, r7, pc} + _lv_txt_encoded_next(txt, &i); /*'i' points to the next letter so use the prev. value*/ + fdec: 687b ldr r3, [r7, #4] + fdee: a901 add r1, sp, #4 + fdf0: 4630 mov r0, r6 + fdf2: 4798 blx r3 + char_cnt++; + fdf4: 3401 adds r4, #1 + fdf6: e7f3 b.n fde0 + fdf8: 20000054 .word 0x20000054 + +0000fdfc : + * E.g.: "ÁBC" is 3 characters (but 4 bytes) + * @param txt a '\0' terminated char string + * @return number of characters + */ +static uint32_t lv_txt_utf8_get_length(const char * txt) +{ + fdfc: b573 push {r0, r1, r4, r5, r6, lr} + uint32_t len = 0; + uint32_t i = 0; + fdfe: 2400 movs r4, #0 + + while(txt[i] != '\0') { + _lv_txt_encoded_next(txt, &i); + fe00: 4e07 ldr r6, [pc, #28] ; (fe20 ) + uint32_t i = 0; + fe02: 9401 str r4, [sp, #4] +{ + fe04: 4605 mov r5, r0 + while(txt[i] != '\0') { + fe06: 9b01 ldr r3, [sp, #4] + fe08: 5ceb ldrb r3, [r5, r3] + fe0a: b913 cbnz r3, fe12 + len++; + } + + return len; +} + fe0c: 4620 mov r0, r4 + fe0e: b002 add sp, #8 + fe10: bd70 pop {r4, r5, r6, pc} + _lv_txt_encoded_next(txt, &i); + fe12: 6873 ldr r3, [r6, #4] + fe14: a901 add r1, sp, #4 + fe16: 4628 mov r0, r5 + fe18: 4798 blx r3 + len++; + fe1a: 3401 adds r4, #1 + fe1c: e7f3 b.n fe06 + fe1e: bf00 nop + fe20: 20000054 .word 0x20000054 + +0000fe24 : + if(letter_uni < 128) return letter_uni; + fe24: 287f cmp r0, #127 ; 0x7f +{ + fe26: b082 sub sp, #8 + if(letter_uni < 128) return letter_uni; + fe28: d911 bls.n fe4e + if(letter_uni < 0x0800) { + fe2a: f5b0 6f00 cmp.w r0, #2048 ; 0x800 + fe2e: d210 bcs.n fe52 + bytes[0] = ((letter_uni >> 6) & 0x1F) | 0xC0; + fe30: 0983 lsrs r3, r0, #6 + fe32: f063 033f orn r3, r3, #63 ; 0x3f + bytes[1] = ((letter_uni >> 0) & 0x3F) | 0x80; + fe36: f000 003f and.w r0, r0, #63 ; 0x3f + bytes[0] = ((letter_uni >> 6) & 0x1F) | 0xC0; + fe3a: f88d 3004 strb.w r3, [sp, #4] + bytes[1] = ((letter_uni >> 0) & 0x3F) | 0x80; + fe3e: f060 007f orn r0, r0, #127 ; 0x7f + bytes[2] = 0; + fe42: 2300 movs r3, #0 + bytes[1] = ((letter_uni >> 0) & 0x3F) | 0x80; + fe44: f88d 0005 strb.w r0, [sp, #5] + bytes[2] = 0; + fe48: f8ad 3006 strh.w r3, [sp, #6] + return *res_p; + fe4c: 9801 ldr r0, [sp, #4] +} + fe4e: b002 add sp, #8 + fe50: 4770 bx lr + else if(letter_uni < 0x010000) { + fe52: f5b0 3f80 cmp.w r0, #65536 ; 0x10000 + fe56: d214 bcs.n fe82 + bytes[0] = ((letter_uni >> 12) & 0x0F) | 0xE0; + fe58: 0b03 lsrs r3, r0, #12 + fe5a: f063 031f orn r3, r3, #31 + fe5e: f88d 3004 strb.w r3, [sp, #4] + bytes[1] = ((letter_uni >> 6) & 0x3F) | 0x80; + fe62: f3c0 1385 ubfx r3, r0, #6, #6 + fe66: f063 037f orn r3, r3, #127 ; 0x7f + bytes[2] = ((letter_uni >> 0) & 0x3F) | 0x80; + fe6a: f000 003f and.w r0, r0, #63 ; 0x3f + bytes[1] = ((letter_uni >> 6) & 0x3F) | 0x80; + fe6e: f88d 3005 strb.w r3, [sp, #5] + bytes[2] = ((letter_uni >> 0) & 0x3F) | 0x80; + fe72: f060 007f orn r0, r0, #127 ; 0x7f + bytes[3] = 0; + fe76: 2300 movs r3, #0 + bytes[2] = ((letter_uni >> 0) & 0x3F) | 0x80; + fe78: f88d 0006 strb.w r0, [sp, #6] + bytes[3] = 0; + fe7c: f88d 3007 strb.w r3, [sp, #7] + fe80: e7e4 b.n fe4c + else if(letter_uni < 0x110000) { + fe82: f5b0 1f88 cmp.w r0, #1114112 ; 0x110000 + fe86: d2e1 bcs.n fe4c + bytes[0] = ((letter_uni >> 18) & 0x07) | 0xF0; + fe88: 0c83 lsrs r3, r0, #18 + fe8a: f063 030f orn r3, r3, #15 + fe8e: f88d 3004 strb.w r3, [sp, #4] + bytes[1] = ((letter_uni >> 12) & 0x3F) | 0x80; + fe92: f3c0 3305 ubfx r3, r0, #12, #6 + fe96: f063 037f orn r3, r3, #127 ; 0x7f + fe9a: f88d 3005 strb.w r3, [sp, #5] + bytes[2] = ((letter_uni >> 6) & 0x3F) | 0x80; + fe9e: f3c0 1385 ubfx r3, r0, #6, #6 + bytes[3] = ((letter_uni >> 0) & 0x3F) | 0x80; + fea2: f000 003f and.w r0, r0, #63 ; 0x3f + bytes[2] = ((letter_uni >> 6) & 0x3F) | 0x80; + fea6: f063 037f orn r3, r3, #127 ; 0x7f + bytes[3] = ((letter_uni >> 0) & 0x3F) | 0x80; + feaa: f060 007f orn r0, r0, #127 ; 0x7f + bytes[2] = ((letter_uni >> 6) & 0x3F) | 0x80; + feae: f88d 3006 strb.w r3, [sp, #6] + bytes[3] = ((letter_uni >> 0) & 0x3F) | 0x80; + feb2: f88d 0007 strb.w r0, [sp, #7] + feb6: e7c9 b.n fe4c + +0000feb8 : + if((c & 0x80) != 0) { + feb8: 0603 lsls r3, r0, #24 + feba: d512 bpl.n fee2 + swapped = (c8[0] << 24) + (c8[1] << 16) + (c8[2] << 8) + (c8[3]); + febc: f3c0 2207 ubfx r2, r0, #8, #8 + fec0: 0603 lsls r3, r0, #24 + fec2: eb03 4302 add.w r3, r3, r2, lsl #16 + fec6: f3c0 4207 ubfx r2, r0, #16, #8 + feca: eb03 2302 add.w r3, r3, r2, lsl #8 + fece: eb03 6010 add.w r0, r3, r0, lsr #24 + fed2: 2304 movs r3, #4 + if((swapped & 0xFF) == 0) + fed4: b2c2 uxtb r2, r0 + fed6: b902 cbnz r2, feda + swapped = (swapped >> 8); /*Ignore leading zeros (they were in the end originally)*/ + fed8: 0a00 lsrs r0, r0, #8 + for(i = 0; i < 4; i++) { + feda: 3b01 subs r3, #1 + fedc: f013 03ff ands.w r3, r3, #255 ; 0xff + fee0: d1f8 bne.n fed4 +} + fee2: 4770 bx lr + +0000fee4 <_lv_txt_is_cmd>: + if(c == (uint32_t)LV_TXT_COLOR_CMD[0]) { + fee4: 2923 cmp r1, #35 ; 0x23 + fee6: d116 bne.n ff16 <_lv_txt_is_cmd+0x32> + if(*state == LV_TXT_CMD_STATE_WAIT) { /*Start char*/ + fee8: 7802 ldrb r2, [r0, #0] + feea: b95a cbnz r2, ff04 <_lv_txt_is_cmd+0x20> + *state = LV_TXT_CMD_STATE_PAR; + feec: 2301 movs r3, #1 + *state = LV_TXT_CMD_STATE_WAIT; + feee: 7003 strb r3, [r0, #0] + if(*state == LV_TXT_CMD_STATE_PAR) { + fef0: 7802 ldrb r2, [r0, #0] + fef2: 2a01 cmp r2, #1 + fef4: d104 bne.n ff00 <_lv_txt_is_cmd+0x1c> + if(c == ' ') { + fef6: 2920 cmp r1, #32 + *state = LV_TXT_CMD_STATE_IN; /*After the parameter the text is in the command*/ + fef8: bf04 itt eq + fefa: 2302 moveq r3, #2 + fefc: 7003 strbeq r3, [r0, #0] + ret = true; + fefe: 4613 mov r3, r2 +} + ff00: 4618 mov r0, r3 + ff02: 4770 bx lr + else if(*state == LV_TXT_CMD_STATE_PAR) { + ff04: 2a01 cmp r2, #1 + ff06: f04f 0300 mov.w r3, #0 + ff0a: d0f0 beq.n feee <_lv_txt_is_cmd+0xa> + else if(*state == LV_TXT_CMD_STATE_IN) { + ff0c: 2a02 cmp r2, #2 + ff0e: d1ef bne.n fef0 <_lv_txt_is_cmd+0xc> + *state = LV_TXT_CMD_STATE_WAIT; + ff10: 7003 strb r3, [r0, #0] + ret = true; + ff12: 2301 movs r3, #1 + ff14: e7ec b.n fef0 <_lv_txt_is_cmd+0xc> + bool ret = false; + ff16: 2300 movs r3, #0 + ff18: e7ea b.n fef0 <_lv_txt_is_cmd+0xc> + ... + +0000ff1c <_lv_txt_get_width>: +{ + ff1c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ff20: 4688 mov r8, r1 + ff22: b085 sub sp, #20 + ff24: 4617 mov r7, r2 + ff26: 461e mov r6, r3 + if(txt == NULL) return 0; + ff28: 4605 mov r5, r0 + ff2a: 2400 movs r4, #0 + ff2c: 2800 cmp r0, #0 + ff2e: d03e beq.n ffae <_lv_txt_get_width+0x92> + if(font == NULL) return 0; + ff30: 2a00 cmp r2, #0 + ff32: d03e beq.n ffb2 <_lv_txt_get_width+0x96> + uint32_t i = 0; + ff34: 9403 str r4, [sp, #12] + lv_txt_cmd_state_t cmd_state = LV_TXT_CMD_STATE_WAIT; + ff36: f88d 400b strb.w r4, [sp, #11] + if(length != 0) { + ff3a: 2900 cmp r1, #0 + ff3c: d035 beq.n ffaa <_lv_txt_get_width+0x8e> + if((flag & LV_TXT_FLAG_RECOLOR) != 0) { + ff3e: f89d 9038 ldrb.w r9, [sp, #56] ; 0x38 + uint32_t letter = _lv_txt_encoded_next(txt, &i); + ff42: f8df a07c ldr.w sl, [pc, #124] ; ffc0 <_lv_txt_get_width+0xa4> + if((flag & LV_TXT_FLAG_RECOLOR) != 0) { + ff46: f009 0901 and.w r9, r9, #1 + uint32_t letter = _lv_txt_encoded_next(txt, &i); + ff4a: f8da 3004 ldr.w r3, [sl, #4] + ff4e: a903 add r1, sp, #12 + ff50: 4628 mov r0, r5 + ff52: 4798 blx r3 + ff54: 4683 mov fp, r0 + uint32_t letter_next = _lv_txt_encoded_next(&txt[i], NULL); + ff56: 9803 ldr r0, [sp, #12] + ff58: f8da 2004 ldr.w r2, [sl, #4] + ff5c: 2100 movs r1, #0 + ff5e: 4428 add r0, r5 + ff60: 4790 blx r2 + ff62: 4602 mov r2, r0 + if((flag & LV_TXT_FLAG_RECOLOR) != 0) { + ff64: f1b9 0f00 cmp.w r9, #0 + ff68: d111 bne.n ff8e <_lv_txt_get_width+0x72> + lv_coord_t char_width = lv_font_get_glyph_width(font, letter, letter_next); + ff6a: 4b13 ldr r3, [pc, #76] ; (ffb8 <_lv_txt_get_width+0x9c>) + ff6c: 4659 mov r1, fp + ff6e: 4638 mov r0, r7 + ff70: 4798 blx r3 + if(char_width > 0) { + ff72: b203 sxth r3, r0 + ff74: 2b00 cmp r3, #0 + ff76: dc14 bgt.n ffa2 <_lv_txt_get_width+0x86> + while(i < length) { + ff78: 9b03 ldr r3, [sp, #12] + ff7a: 4598 cmp r8, r3 + ff7c: d8e5 bhi.n ff4a <_lv_txt_get_width+0x2e> + if(width > 0) { + ff7e: 2c00 cmp r4, #0 + ff80: dd01 ble.n ff86 <_lv_txt_get_width+0x6a> + width -= letter_space; /*Trim the last letter space. Important if the text is center + ff82: 1ba6 subs r6, r4, r6 + ff84: b234 sxth r4, r6 +} + ff86: 4620 mov r0, r4 + ff88: b005 add sp, #20 + ff8a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + ff8e: 9001 str r0, [sp, #4] + if(_lv_txt_is_cmd(&cmd_state, letter) != false) { + ff90: 4b0a ldr r3, [pc, #40] ; (ffbc <_lv_txt_get_width+0xa0>) + ff92: 4659 mov r1, fp + ff94: f10d 000b add.w r0, sp, #11 + ff98: 4798 blx r3 + ff9a: 9a01 ldr r2, [sp, #4] + ff9c: 2800 cmp r0, #0 + ff9e: d0e4 beq.n ff6a <_lv_txt_get_width+0x4e> + ffa0: e7ea b.n ff78 <_lv_txt_get_width+0x5c> + width += letter_space; + ffa2: 4434 add r4, r6 + ffa4: 4420 add r0, r4 + ffa6: b204 sxth r4, r0 + ffa8: e7e6 b.n ff78 <_lv_txt_get_width+0x5c> + lv_coord_t width = 0; + ffaa: 460c mov r4, r1 + ffac: e7eb b.n ff86 <_lv_txt_get_width+0x6a> + if(txt == NULL) return 0; + ffae: 4604 mov r4, r0 + ffb0: e7e9 b.n ff86 <_lv_txt_get_width+0x6a> + ffb2: 4614 mov r4, r2 + ffb4: e7e7 b.n ff86 <_lv_txt_get_width+0x6a> + ffb6: bf00 nop + ffb8: 0000d175 .word 0x0000d175 + ffbc: 0000fee5 .word 0x0000fee5 + ffc0: 20000054 .word 0x20000054 + +0000ffc4 <_lv_txt_get_next_line>: +{ + ffc4: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + ffc8: b08f sub sp, #60 ; 0x3c + ffca: 4699 mov r9, r3 + ffcc: f89d 3060 ldrb.w r3, [sp, #96] ; 0x60 + ffd0: 9102 str r1, [sp, #8] + ffd2: 9204 str r2, [sp, #16] + ffd4: 9303 str r3, [sp, #12] + if(txt == NULL) return 0; + ffd6: 4607 mov r7, r0 + ffd8: b198 cbz r0, 10002 <_lv_txt_get_next_line+0x3e> + if(font == NULL) return 0; + ffda: 2900 cmp r1, #0 + ffdc: f000 80d2 beq.w 10184 <_lv_txt_get_next_line+0x1c0> + if((flag & LV_TXT_FLAG_EXPAND) || (flag & LV_TXT_FLAG_FIT)) { + ffe0: 9b03 ldr r3, [sp, #12] + ffe2: f013 0312 ands.w r3, r3, #18 + ffe6: d00f beq.n 10008 <_lv_txt_get_next_line+0x44> + for(i = 0; txt[i] != '\n' && txt[i] != '\r' && txt[i] != '\0'; i++) { + ffe8: 2000 movs r0, #0 + ffea: e000 b.n ffee <_lv_txt_get_next_line+0x2a> + ffec: 3001 adds r0, #1 + ffee: 5c3b ldrb r3, [r7, r0] + fff0: 2b0a cmp r3, #10 + fff2: f000 80c9 beq.w 10188 <_lv_txt_get_next_line+0x1c4> + fff6: 2b0d cmp r3, #13 + fff8: f000 80c6 beq.w 10188 <_lv_txt_get_next_line+0x1c4> + fffc: 2b00 cmp r3, #0 + fffe: d1f5 bne.n ffec <_lv_txt_get_next_line+0x28> + return i; + 10000: b280 uxth r0, r0 +} + 10002: b00f add sp, #60 ; 0x3c + 10004: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + if(flag & LV_TXT_FLAG_EXPAND) max_width = LV_COORD_MAX; + 10008: 9a03 ldr r2, [sp, #12] + lv_txt_cmd_state_t cmd_state = LV_TXT_CMD_STATE_WAIT; + 1000a: f88d 302b strb.w r3, [sp, #43] ; 0x2b + if(flag & LV_TXT_FLAG_EXPAND) max_width = LV_COORD_MAX; + 1000e: f012 0202 ands.w r2, r2, #2 + 10012: 9205 str r2, [sp, #20] + 10014: f647 4218 movw r2, #31768 ; 0x7c18 + 10018: bf18 it ne + 1001a: 4691 movne r9, r2 + uint32_t i = 0; /* Iterating index into txt */ + 1001c: 930b str r3, [sp, #44] ; 0x2c + while(txt[i] != '\0' && max_width > 0) { + 1001e: 9b0b ldr r3, [sp, #44] ; 0x2c + 10020: 9300 str r3, [sp, #0] + 10022: eb07 0b03 add.w fp, r7, r3 + 10026: 5cfb ldrb r3, [r7, r3] + 10028: 2b00 cmp r3, #0 + 1002a: f000 808e beq.w 1014a <_lv_txt_get_next_line+0x186> + 1002e: f1b9 0f00 cmp.w r9, #0 + 10032: f340 808a ble.w 1014a <_lv_txt_get_next_line+0x186> + if(flag & LV_TXT_FLAG_EXPAND) max_width = LV_COORD_MAX; + 10036: 9a05 ldr r2, [sp, #20] + 10038: f647 4318 movw r3, #31768 ; 0x7c18 + 1003c: 2a00 cmp r2, #0 + 1003e: bf08 it eq + 10040: 464b moveq r3, r9 + 10042: 9307 str r3, [sp, #28] + letter = _lv_txt_encoded_next(txt, &i_next); + 10044: 4b51 ldr r3, [pc, #324] ; (1018c <_lv_txt_get_next_line+0x1c8>) + uint32_t i = 0, i_next = 0, i_next_next = 0; /* Iterating index into txt */ + 10046: 2500 movs r5, #0 + letter = _lv_txt_encoded_next(txt, &i_next); + 10048: 685b ldr r3, [r3, #4] + uint32_t i = 0, i_next = 0, i_next_next = 0; /* Iterating index into txt */ + 1004a: e9cd 550c strd r5, r5, [sp, #48] ; 0x30 + letter = _lv_txt_encoded_next(txt, &i_next); + 1004e: a90c add r1, sp, #48 ; 0x30 + 10050: 4658 mov r0, fp + 10052: 4798 blx r3 + i_next_next = i_next; + 10054: 9b0c ldr r3, [sp, #48] ; 0x30 + 10056: 930d str r3, [sp, #52] ; 0x34 + if((flag & LV_TXT_FLAG_RECOLOR) != 0) { + 10058: 9b03 ldr r3, [sp, #12] + uint32_t word_len = 0; /* Number of characters in the transversed word */ + 1005a: 9501 str r5, [sp, #4] + if((flag & LV_TXT_FLAG_RECOLOR) != 0) { + 1005c: f003 0301 and.w r3, r3, #1 + letter = _lv_txt_encoded_next(txt, &i_next); + 10060: 4680 mov r8, r0 + uint32_t break_index = NO_BREAK_FOUND; /* only used for "long" words */ + 10062: f04f 3aff mov.w sl, #4294967295 ; 0xffffffff + lv_coord_t cur_w = 0; /* Pixel Width of transversed string */ + 10066: 462e mov r6, r5 + uint32_t letter_next = 0; /* Letter at i_next */ + 10068: 462a mov r2, r5 + uint32_t i = 0, i_next = 0, i_next_next = 0; /* Iterating index into txt */ + 1006a: 462c mov r4, r5 + if((flag & LV_TXT_FLAG_RECOLOR) != 0) { + 1006c: 9308 str r3, [sp, #32] + while(txt[i] != '\0') { + 1006e: f81b 3004 ldrb.w r3, [fp, r4] + 10072: b943 cbnz r3, 10086 <_lv_txt_get_next_line+0xc2> + if(break_index == NO_BREAK_FOUND) { + 10074: f1ba 3fff cmp.w sl, #4294967295 ; 0xffffffff + 10078: d052 beq.n 10120 <_lv_txt_get_next_line+0x15c> + if(force) return break_index; + 1007a: 9b00 ldr r3, [sp, #0] + 1007c: 2b00 cmp r3, #0 + 1007e: d16e bne.n 1015e <_lv_txt_get_next_line+0x19a> + 10080: fa1f f48a uxth.w r4, sl + 10084: e055 b.n 10132 <_lv_txt_get_next_line+0x16e> + letter_next = _lv_txt_encoded_next(txt, &i_next_next); + 10086: 4b41 ldr r3, [pc, #260] ; (1018c <_lv_txt_get_next_line+0x1c8>) + 10088: a90d add r1, sp, #52 ; 0x34 + 1008a: 685b ldr r3, [r3, #4] + 1008c: 4658 mov r0, fp + 1008e: 4798 blx r3 + word_len++; + 10090: 9b01 ldr r3, [sp, #4] + 10092: 3301 adds r3, #1 + 10094: 9306 str r3, [sp, #24] + if((flag & LV_TXT_FLAG_RECOLOR) != 0) { + 10096: 9b08 ldr r3, [sp, #32] + letter_next = _lv_txt_encoded_next(txt, &i_next_next); + 10098: 4602 mov r2, r0 + if((flag & LV_TXT_FLAG_RECOLOR) != 0) { + 1009a: b173 cbz r3, 100ba <_lv_txt_get_next_line+0xf6> + 1009c: 9009 str r0, [sp, #36] ; 0x24 + if(_lv_txt_is_cmd(cmd_state, letter) != false) { + 1009e: 4b3c ldr r3, [pc, #240] ; (10190 <_lv_txt_get_next_line+0x1cc>) + 100a0: 4641 mov r1, r8 + 100a2: f10d 002b add.w r0, sp, #43 ; 0x2b + 100a6: 4798 blx r3 + 100a8: 9a09 ldr r2, [sp, #36] ; 0x24 + 100aa: b130 cbz r0, 100ba <_lv_txt_get_next_line+0xf6> + i_next = i_next_next; + 100ac: e9dd 430c ldrd r4, r3, [sp, #48] ; 0x30 + 100b0: 930c str r3, [sp, #48] ; 0x30 + 100b2: 9b06 ldr r3, [sp, #24] + 100b4: 9301 str r3, [sp, #4] + letter_next = _lv_txt_encoded_next(txt, &i_next_next); + 100b6: 4690 mov r8, r2 + 100b8: e7d9 b.n 1006e <_lv_txt_get_next_line+0xaa> + letter_w = lv_font_get_glyph_width(font, letter, letter_next); + 100ba: 4b36 ldr r3, [pc, #216] ; (10194 <_lv_txt_get_next_line+0x1d0>) + 100bc: 9802 ldr r0, [sp, #8] + 100be: 9209 str r2, [sp, #36] ; 0x24 + 100c0: 4641 mov r1, r8 + 100c2: 4798 blx r3 + cur_w += letter_w; + 100c4: 4406 add r6, r0 + if(letter_w > 0) { + 100c6: b200 sxth r0, r0 + 100c8: 2800 cmp r0, #0 + cur_w += letter_space; + 100ca: bfc8 it gt + 100cc: 9b04 ldrgt r3, [sp, #16] + if(letter_w > 0) { + 100ce: 9a09 ldr r2, [sp, #36] ; 0x24 + cur_w += letter_w; + 100d0: b2b6 uxth r6, r6 + cur_w += letter_space; + 100d2: bfc4 itt gt + 100d4: 18f6 addgt r6, r6, r3 + 100d6: b2b6 uxthgt r6, r6 + if(break_index == NO_BREAK_FOUND && (cur_w - letter_space) > max_width) { + 100d8: f1ba 3fff cmp.w sl, #4294967295 ; 0xffffffff + 100dc: b236 sxth r6, r6 + 100de: d105 bne.n 100ec <_lv_txt_get_next_line+0x128> + 100e0: 9b04 ldr r3, [sp, #16] + 100e2: 9907 ldr r1, [sp, #28] + 100e4: 1af3 subs r3, r6, r3 + 100e6: 428b cmp r3, r1 + 100e8: bfc8 it gt + 100ea: 46a2 movgt sl, r4 + if(letter == '\n' || letter == '\r' || is_break_char(letter)) { + 100ec: f1b8 0f0a cmp.w r8, #10 + 100f0: d010 beq.n 10114 <_lv_txt_get_next_line+0x150> + 100f2: f1b8 0f0d cmp.w r8, #13 + 100f6: d00d beq.n 10114 <_lv_txt_get_next_line+0x150> +{ + uint8_t i; + bool ret = false; + + /*Compare the letter to TXT_BREAK_CHARS*/ + for(i = 0; LV_TXT_BREAK_CHARS[i] != '\0'; i++) { + 100f8: 4827 ldr r0, [pc, #156] ; (10198 <_lv_txt_get_next_line+0x1d4>) + 100fa: 2300 movs r3, #0 + 100fc: b2d9 uxtb r1, r3 + 100fe: 5c41 ldrb r1, [r0, r1] + 10100: b921 cbnz r1, 1010c <_lv_txt_get_next_line+0x148> + if(word_w_ptr != NULL && break_index == NO_BREAK_FOUND) *word_w_ptr = cur_w; + 10102: f1ba 3fff cmp.w sl, #4294967295 ; 0xffffffff + 10106: bf08 it eq + 10108: 4635 moveq r5, r6 + 1010a: e7cf b.n 100ac <_lv_txt_get_next_line+0xe8> + if(letter == (uint32_t)LV_TXT_BREAK_CHARS[i]) { + 1010c: 4588 cmp r8, r1 + 1010e: f103 0301 add.w r3, r3, #1 + 10112: d1f3 bne.n 100fc <_lv_txt_get_next_line+0x138> + if(i == 0 && break_index == NO_BREAK_FOUND && word_w_ptr != NULL) *word_w_ptr = cur_w; + 10114: 2c00 cmp r4, #0 + 10116: d1ad bne.n 10074 <_lv_txt_get_next_line+0xb0> + 10118: f1ba 3fff cmp.w sl, #4294967295 ; 0xffffffff + 1011c: d1ad bne.n 1007a <_lv_txt_get_next_line+0xb6> + 1011e: 4635 mov r5, r6 + if(word_len == 0 || (letter == '\r' && letter_next == '\n')) i = i_next; + 10120: 9b01 ldr r3, [sp, #4] + 10122: b123 cbz r3, 1012e <_lv_txt_get_next_line+0x16a> + 10124: f1b8 0f0d cmp.w r8, #13 + 10128: d102 bne.n 10130 <_lv_txt_get_next_line+0x16c> + 1012a: 2a0a cmp r2, #10 + 1012c: d100 bne.n 10130 <_lv_txt_get_next_line+0x16c> + 1012e: 9c0c ldr r4, [sp, #48] ; 0x30 + return i; + 10130: b2a4 uxth r4, r4 + max_width -= word_w; + 10132: eba9 0505 sub.w r5, r9, r5 + if(i == 0) _lv_txt_encoded_next(txt, &i); // prevent inf loops + 10136: 9b0b ldr r3, [sp, #44] ; 0x2c + max_width -= word_w; + 10138: fa0f f985 sxth.w r9, r5 + if(advance == 0) { + 1013c: b994 cbnz r4, 10164 <_lv_txt_get_next_line+0x1a0> + if(i == 0) _lv_txt_encoded_next(txt, &i); // prevent inf loops + 1013e: b95b cbnz r3, 10158 <_lv_txt_get_next_line+0x194> + 10140: 4b12 ldr r3, [pc, #72] ; (1018c <_lv_txt_get_next_line+0x1c8>) + 10142: a90b add r1, sp, #44 ; 0x2c + 10144: 685b ldr r3, [r3, #4] + 10146: 4638 mov r0, r7 + 10148: 4798 blx r3 + if(i == 0) { + 1014a: 9b0b ldr r3, [sp, #44] ; 0x2c + 1014c: b923 cbnz r3, 10158 <_lv_txt_get_next_line+0x194> + _lv_txt_encoded_next(txt, &i); + 1014e: 4b0f ldr r3, [pc, #60] ; (1018c <_lv_txt_get_next_line+0x1c8>) + 10150: a90b add r1, sp, #44 ; 0x2c + 10152: 685b ldr r3, [r3, #4] + 10154: 4638 mov r0, r7 + 10156: 4798 blx r3 + return i; + 10158: f8bd 002c ldrh.w r0, [sp, #44] ; 0x2c + 1015c: e751 b.n 10002 <_lv_txt_get_next_line+0x3e> + if(word_w_ptr != NULL) *word_w_ptr = 0; /* Return no word */ + 1015e: 2500 movs r5, #0 + return 0; + 10160: 462c mov r4, r5 + 10162: e7e6 b.n 10132 <_lv_txt_get_next_line+0x16e> + i += advance; + 10164: 441c add r4, r3 + if(txt[0] == '\n' || txt[0] == '\r') break; + 10166: 783b ldrb r3, [r7, #0] + i += advance; + 10168: 940b str r4, [sp, #44] ; 0x2c + if(txt[0] == '\n' || txt[0] == '\r') break; + 1016a: 2b0a cmp r3, #10 + 1016c: d0ed beq.n 1014a <_lv_txt_get_next_line+0x186> + 1016e: 2b0d cmp r3, #13 + 10170: d0eb beq.n 1014a <_lv_txt_get_next_line+0x186> + if(txt[i] == '\n' || txt[i] == '\r') { + 10172: 5d3b ldrb r3, [r7, r4] + 10174: 2b0a cmp r3, #10 + 10176: d002 beq.n 1017e <_lv_txt_get_next_line+0x1ba> + 10178: 2b0d cmp r3, #13 + 1017a: f47f af50 bne.w 1001e <_lv_txt_get_next_line+0x5a> + i++; /* Include the following newline in the current line */ + 1017e: 3401 adds r4, #1 + 10180: 940b str r4, [sp, #44] ; 0x2c + break; + 10182: e7e2 b.n 1014a <_lv_txt_get_next_line+0x186> + if(txt == NULL) return 0; + 10184: 9802 ldr r0, [sp, #8] + 10186: e73c b.n 10002 <_lv_txt_get_next_line+0x3e> + if(txt[i] != '\0') i++; /*To go beyond `\n`*/ + 10188: 3001 adds r0, #1 + 1018a: e739 b.n 10000 <_lv_txt_get_next_line+0x3c> + 1018c: 20000054 .word 0x20000054 + 10190: 0000fee5 .word 0x0000fee5 + 10194: 0000d175 .word 0x0000d175 + 10198: 000241e6 .word 0x000241e6 + +0001019c <_lv_txt_get_size>: +{ + 1019c: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 101a0: b089 sub sp, #36 ; 0x24 + size_res->x = 0; + 101a2: 2500 movs r5, #0 +{ + 101a4: 4698 mov r8, r3 + 101a6: f89d 3050 ldrb.w r3, [sp, #80] ; 0x50 + 101aa: f9bd b048 ldrsh.w fp, [sp, #72] ; 0x48 + 101ae: f9bd a04c ldrsh.w sl, [sp, #76] ; 0x4c + 101b2: 9304 str r3, [sp, #16] + 101b4: 4604 mov r4, r0 + 101b6: 4616 mov r6, r2 + size_res->x = 0; + 101b8: 8005 strh r5, [r0, #0] + size_res->y = 0; + 101ba: 8045 strh r5, [r0, #2] + if(text == NULL) return; + 101bc: 9103 str r1, [sp, #12] + 101be: b329 cbz r1, 1020c <_lv_txt_get_size+0x70> + if(font == NULL) return; + 101c0: b322 cbz r2, 1020c <_lv_txt_get_size+0x70> + if(flag & LV_TXT_FLAG_EXPAND) max_width = LV_COORD_MAX; + 101c2: 9b04 ldr r3, [sp, #16] + 101c4: f013 0f02 tst.w r3, #2 + 101c8: f647 4318 movw r3, #31768 ; 0x7c18 + 101cc: bf18 it ne + 101ce: 469a movne sl, r3 + * @param font_p pointer to a font + * @return the height of a font + */ +static inline lv_coord_t lv_font_get_line_height(const lv_font_t * font_p) +{ + return font_p->line_height; + 101d0: f9b2 3008 ldrsh.w r3, [r2, #8] + 101d4: 9306 str r3, [sp, #24] + uint16_t letter_height = lv_font_get_line_height(font); + 101d6: 8913 ldrh r3, [r2, #8] + 101d8: 9305 str r3, [sp, #20] + if((unsigned long)size_res->y + (unsigned long)letter_height + (unsigned long)line_space > LV_MAX_OF(lv_coord_t)) { + 101da: 445b add r3, fp + 101dc: 9307 str r3, [sp, #28] + while(text[line_start] != '\0') { + 101de: 9b03 ldr r3, [sp, #12] + 101e0: eb03 0905 add.w r9, r3, r5 + 101e4: 5d5b ldrb r3, [r3, r5] + 101e6: b9a3 cbnz r3, 10212 <_lv_txt_get_size+0x76> + if((line_start != 0) && (text[line_start - 1] == '\n' || text[line_start - 1] == '\r')) { + 101e8: b155 cbz r5, 10200 <_lv_txt_get_size+0x64> + 101ea: f819 3c01 ldrb.w r3, [r9, #-1] + 101ee: 2b0a cmp r3, #10 + 101f0: d001 beq.n 101f6 <_lv_txt_get_size+0x5a> + 101f2: 2b0d cmp r3, #13 + 101f4: d104 bne.n 10200 <_lv_txt_get_size+0x64> + size_res->y += letter_height + line_space; + 101f6: 9b05 ldr r3, [sp, #20] + 101f8: 8862 ldrh r2, [r4, #2] + 101fa: 445b add r3, fp + 101fc: 4413 add r3, r2 + 101fe: 8063 strh r3, [r4, #2] + if(size_res->y == 0) + 10200: f9b4 3002 ldrsh.w r3, [r4, #2] + 10204: 2b00 cmp r3, #0 + 10206: d131 bne.n 1026c <_lv_txt_get_size+0xd0> + size_res->y = letter_height; + 10208: 9b06 ldr r3, [sp, #24] + size_res->y -= line_space; + 1020a: 8063 strh r3, [r4, #2] +} + 1020c: b009 add sp, #36 ; 0x24 + 1020e: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + new_line_start += _lv_txt_get_next_line(&text[line_start], font, letter_space, max_width, flag); + 10212: 9b04 ldr r3, [sp, #16] + 10214: 9300 str r3, [sp, #0] + 10216: 4642 mov r2, r8 + 10218: 4653 mov r3, sl + 1021a: 4631 mov r1, r6 + 1021c: 4f15 ldr r7, [pc, #84] ; (10274 <_lv_txt_get_size+0xd8>) + 1021e: 4648 mov r0, r9 + 10220: 47b8 blx r7 + if((unsigned long)size_res->y + (unsigned long)letter_height + (unsigned long)line_space > LV_MAX_OF(lv_coord_t)) { + 10222: f9b4 3002 ldrsh.w r3, [r4, #2] + 10226: 9a07 ldr r2, [sp, #28] + 10228: 4413 add r3, r2 + 1022a: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + new_line_start += _lv_txt_get_next_line(&text[line_start], font, letter_space, max_width, flag); + 1022e: 4601 mov r1, r0 + 10230: 4405 add r5, r0 + if((unsigned long)size_res->y + (unsigned long)letter_height + (unsigned long)line_space > LV_MAX_OF(lv_coord_t)) { + 10232: d30b bcc.n 1024c <_lv_txt_get_size+0xb0> + LV_LOG_WARN("lv_txt_get_size: integer overflow while calculating text height"); + 10234: 4b10 ldr r3, [pc, #64] ; (10278 <_lv_txt_get_size+0xdc>) + 10236: 4c11 ldr r4, [pc, #68] ; (1027c <_lv_txt_get_size+0xe0>) + 10238: 9312 str r3, [sp, #72] ; 0x48 + 1023a: 4911 ldr r1, [pc, #68] ; (10280 <_lv_txt_get_size+0xe4>) + 1023c: 4b11 ldr r3, [pc, #68] ; (10284 <_lv_txt_get_size+0xe8>) + 1023e: 2271 movs r2, #113 ; 0x71 + 10240: 2002 movs r0, #2 + 10242: 46a4 mov ip, r4 +} + 10244: b009 add sp, #36 ; 0x24 + 10246: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + LV_LOG_WARN("lv_txt_get_size: integer overflow while calculating text height"); + 1024a: 4760 bx ip + size_res->y += line_space; + 1024c: 8063 strh r3, [r4, #2] + lv_coord_t act_line_length = _lv_txt_get_width(&text[line_start], new_line_start - line_start, font, letter_space, + 1024e: 9b04 ldr r3, [sp, #16] + 10250: 9300 str r3, [sp, #0] + 10252: 4648 mov r0, r9 + 10254: 4643 mov r3, r8 + 10256: f8df 9030 ldr.w r9, [pc, #48] ; 10288 <_lv_txt_get_size+0xec> + 1025a: 4632 mov r2, r6 + 1025c: 47c8 blx r9 + size_res->x = LV_MATH_MAX(act_line_length, size_res->x); + 1025e: f9b4 3000 ldrsh.w r3, [r4] + 10262: 4298 cmp r0, r3 + 10264: bfb8 it lt + 10266: 4618 movlt r0, r3 + 10268: 8020 strh r0, [r4, #0] + line_start = new_line_start; + 1026a: e7b8 b.n 101de <_lv_txt_get_size+0x42> + size_res->y -= line_space; + 1026c: eba3 030b sub.w r3, r3, fp + 10270: e7cb b.n 1020a <_lv_txt_get_size+0x6e> + 10272: bf00 nop + 10274: 0000ffc5 .word 0x0000ffc5 + 10278: 0002421d .word 0x0002421d + 1027c: 0000e8e9 .word 0x0000e8e9 + 10280: 000241ee .word 0x000241ee + 10284: 0002425d .word 0x0002425d + 10288: 0000ff1d .word 0x0000ff1d + +0001028c <_lv_utils_bsearch>: + * + * @return a pointer to a matching item, or NULL if none exists. + */ +void * _lv_utils_bsearch(const void * key, const void * base, uint32_t n, uint32_t size, + int32_t (*cmp)(const void * pRef, const void * pElement)) +{ + 1028c: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 10290: 9d08 ldr r5, [sp, #32] + 10292: 4680 mov r8, r0 + 10294: 460f mov r7, r1 + 10296: 4614 mov r4, r2 + 10298: 4699 mov r9, r3 + const char * middle; + int32_t c; + + for(middle = base; n != 0;) { + 1029a: b90c cbnz r4, 102a0 <_lv_utils_bsearch+0x14> + } + else { + return (char *)middle; + } + } + return NULL; + 1029c: 4626 mov r6, r4 + 1029e: e012 b.n 102c6 <_lv_utils_bsearch+0x3a> + middle += (n / 2) * size; + 102a0: ea4f 0a54 mov.w sl, r4, lsr #1 + 102a4: fb09 760a mla r6, r9, sl, r7 + if((c = (*cmp)(key, middle)) > 0) { + 102a8: 4631 mov r1, r6 + 102aa: 4640 mov r0, r8 + 102ac: 47a8 blx r5 + 102ae: 2800 cmp r0, #0 + 102b0: dd08 ble.n 102c4 <_lv_utils_bsearch+0x38> + n = (n / 2) - ((n & 1) == 0); + 102b2: 43e4 mvns r4, r4 + 102b4: f004 0401 and.w r4, r4, #1 + 102b8: ebaa 0a04 sub.w sl, sl, r4 + base = (middle += size); + 102bc: eb06 0709 add.w r7, r6, r9 +{ + 102c0: 4654 mov r4, sl + 102c2: e7ea b.n 1029a <_lv_utils_bsearch+0xe> + else if(c < 0) { + 102c4: d1fc bne.n 102c0 <_lv_utils_bsearch+0x34> +} + 102c6: 4630 mov r0, r6 + 102c8: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + +000102cc : + * From now, all the created objects will use styles from this theme by default + * @param th pointer to theme (return value of: 'lv_theme_init_xxx()') + */ +void lv_theme_set_act(lv_theme_t * th) +{ + act_theme = th; + 102cc: 4b01 ldr r3, [pc, #4] ; (102d4 ) + 102ce: 6018 str r0, [r3, #0] +} + 102d0: 4770 bx lr + 102d2: bf00 nop + 102d4: 2000c7d0 .word 0x2000c7d0 + +000102d8 : + * Get the normal font of the theme + * @return pointer to the font + */ +const lv_font_t * lv_theme_get_font_normal(void) +{ + return act_theme->font_normal; + 102d8: 4b01 ldr r3, [pc, #4] ; (102e0 ) + 102da: 681b ldr r3, [r3, #0] +} + 102dc: 68d8 ldr r0, [r3, #12] + 102de: 4770 bx lr + 102e0: 2000c7d0 .word 0x2000c7d0 + +000102e4 : + return act_theme->flags; +} + +void lv_theme_apply(lv_obj_t * obj, lv_theme_style_t name) +{ + act_theme->apply_xcb(obj, name); + 102e4: 4b01 ldr r3, [pc, #4] ; (102ec ) + 102e6: 681b ldr r3, [r3, #0] + 102e8: 681b ldr r3, [r3, #0] + 102ea: 4718 bx r3 + 102ec: 2000c7d0 .word 0x2000c7d0 + +000102f0 : + return lv_color_make((uint8_t)((c >> 16) & 0xFF), (uint8_t)((c >> 8) & 0xFF), (uint8_t)(c & 0xFF)); +} + +static inline lv_color_t lv_color_hex3(uint32_t c) +{ + return lv_color_make((uint8_t)(((c >> 4) & 0xF0) | ((c >> 8) & 0xF)), (uint8_t)((c & 0xF0) | ((c & 0xF0) >> 4)), + 102f0: f3c0 1303 ubfx r3, r0, #4, #4 +{ + 102f4: b510 push {r4, lr} + return lv_color_make((uint8_t)(((c >> 4) & 0xF0) | ((c >> 8) & 0xF)), (uint8_t)((c & 0xF0) | ((c & 0xF0) >> 4)), + 102f6: f000 01f0 and.w r1, r0, #240 ; 0xf0 + 102fa: b2c4 uxtb r4, r0 + 102fc: f3c0 1207 ubfx r2, r0, #4, #8 + return LV_COLOR_MAKE(r, g, b); + 10300: 4319 orrs r1, r3 + (uint8_t)((c & 0xF) | ((c & 0xF) << 4))); + 10302: f000 030f and.w r3, r0, #15 + return lv_color_make((uint8_t)(((c >> 4) & 0xF0) | ((c >> 8) & 0xF)), (uint8_t)((c & 0xF0) | ((c & 0xF0) >> 4)), + 10306: ea43 1304 orr.w r3, r3, r4, lsl #4 + 1030a: f022 020f bic.w r2, r2, #15 + 1030e: 0889 lsrs r1, r1, #2 + 10310: ea42 2010 orr.w r0, r2, r0, lsr #8 + 10314: f3c3 03c4 ubfx r3, r3, #3, #5 + 10318: ea43 1341 orr.w r3, r3, r1, lsl #5 + 1031c: f3c0 00c4 ubfx r0, r0, #3, #5 +} + 10320: ea43 20c0 orr.w r0, r3, r0, lsl #11 + 10324: bd10 pop {r4, pc} + ... + +00010328 : + +static void theme_apply(lv_obj_t * obj, lv_theme_style_t name) +{ + lv_style_list_t * list; + + switch(name) { + 10328: 3901 subs r1, #1 +{ + 1032a: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 1032e: 4604 mov r4, r0 + switch(name) { + 10330: 2927 cmp r1, #39 ; 0x27 + 10332: d834 bhi.n 1039e + 10334: e8df f011 tbh [pc, r1, lsl #1] + 10338: 00390028 .word 0x00390028 + 1033c: 008200bb .word 0x008200bb + 10340: 004f0044 .word 0x004f0044 + 10344: 00b70347 .word 0x00b70347 + 10348: 0256010f .word 0x0256010f + 1034c: 036f0039 .word 0x036f0039 + 10350: 03950220 .word 0x03950220 + 10354: 00b700b7 .word 0x00b700b7 + 10358: 00b70071 .word 0x00b70071 + 1035c: 00b70151 .word 0x00b70151 + 10360: 021501f7 .word 0x021501f7 + 10364: 012a0385 .word 0x012a0385 + 10368: 01ef013b .word 0x01ef013b + 1036c: 01d30166 .word 0x01d30166 + 10370: 031b00eb .word 0x031b00eb + 10374: 00d70337 .word 0x00d70337 + 10378: 02840098 .word 0x02840098 + 1037c: 01b9018e .word 0x01b9018e + 10380: 01c702f0 .word 0x01c702f0 + 10384: 02e502be .word 0x02e502be + case LV_THEME_NONE: + break; + + case LV_THEME_SCR: + lv_obj_clean_style_list(obj, LV_OBJ_PART_MAIN); + 10388: 4b99 ldr r3, [pc, #612] ; (105f0 ) + 1038a: 2100 movs r1, #0 + 1038c: 4798 blx r3 + list = lv_obj_get_style_list(obj, LV_OBJ_PART_MAIN); + 1038e: 4b99 ldr r3, [pc, #612] ; (105f4 ) + 10390: 2100 movs r1, #0 + 10392: 4620 mov r0, r4 + 10394: 4798 blx r3 + _lv_style_list_add_style(list, &styles->scr); + 10396: 4b98 ldr r3, [pc, #608] ; (105f8 ) + 10398: 6819 ldr r1, [r3, #0] + break; + case LV_THEME_OBJ: + lv_obj_clean_style_list(obj, LV_OBJ_PART_MAIN); + list = lv_obj_get_style_list(obj, LV_OBJ_PART_MAIN); + _lv_style_list_add_style(list, &styles->bg); + 1039a: 4b98 ldr r3, [pc, #608] ; (105fc ) + 1039c: 4798 blx r3 +#endif + default: + break; + } + + lv_obj_refresh_style(obj, LV_STYLE_PROP_ALL); + 1039e: 4620 mov r0, r4 + 103a0: 4b97 ldr r3, [pc, #604] ; (10600 ) +} + 103a2: e8bd 47f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + lv_obj_refresh_style(obj, LV_STYLE_PROP_ALL); + 103a6: 21ff movs r1, #255 ; 0xff + 103a8: 4718 bx r3 + lv_obj_clean_style_list(obj, LV_OBJ_PART_MAIN); + 103aa: 4b91 ldr r3, [pc, #580] ; (105f0 ) + 103ac: 2100 movs r1, #0 + 103ae: 4798 blx r3 + list = lv_obj_get_style_list(obj, LV_OBJ_PART_MAIN); + 103b0: 4b90 ldr r3, [pc, #576] ; (105f4 ) + 103b2: 2100 movs r1, #0 + 103b4: 4620 mov r0, r4 + 103b6: 4798 blx r3 + _lv_style_list_add_style(list, &styles->bg); + 103b8: 4b8f ldr r3, [pc, #572] ; (105f8 ) + 103ba: 6819 ldr r1, [r3, #0] + 103bc: 3104 adds r1, #4 + 103be: e7ec b.n 1039a + lv_obj_clean_style_list(obj, LV_BTN_PART_MAIN); + 103c0: 4b8b ldr r3, [pc, #556] ; (105f0 ) + 103c2: 2100 movs r1, #0 + 103c4: 4798 blx r3 + list = lv_obj_get_style_list(obj, LV_BTN_PART_MAIN); + 103c6: 4b8b ldr r3, [pc, #556] ; (105f4 ) + 103c8: 2100 movs r1, #0 + 103ca: 4620 mov r0, r4 + 103cc: 4798 blx r3 + _lv_style_list_add_style(list, &styles->btn); + 103ce: 4b8a ldr r3, [pc, #552] ; (105f8 ) + 103d0: 6819 ldr r1, [r3, #0] + 103d2: 3110 adds r1, #16 + 103d4: e7e1 b.n 1039a + _lv_style_list_add_style(list, &styles->bg); + 103d6: 4e88 ldr r6, [pc, #544] ; (105f8 ) + lv_obj_clean_style_list(obj, LV_BTNMATRIX_PART_BG); + 103d8: f8df 9214 ldr.w r9, [pc, #532] ; 105f0 + list = lv_obj_get_style_list(obj, LV_BTNMATRIX_PART_BG); + 103dc: f8df 8214 ldr.w r8, [pc, #532] ; 105f4 + _lv_style_list_add_style(list, &styles->bg); + 103e0: 4d86 ldr r5, [pc, #536] ; (105fc ) + lv_obj_clean_style_list(obj, LV_BTNMATRIX_PART_BG); + 103e2: 2100 movs r1, #0 + 103e4: 47c8 blx r9 + list = lv_obj_get_style_list(obj, LV_BTNMATRIX_PART_BG); + 103e6: 2100 movs r1, #0 + 103e8: 4620 mov r0, r4 + 103ea: 47c0 blx r8 + _lv_style_list_add_style(list, &styles->bg); + 103ec: 6831 ldr r1, [r6, #0] + 103ee: 3104 adds r1, #4 + list = lv_obj_get_style_list(obj, LV_BTNMATRIX_PART_BG); + 103f0: 4607 mov r7, r0 + _lv_style_list_add_style(list, &styles->bg); + 103f2: 47a8 blx r5 + _lv_style_list_add_style(list, &styles->pad_small); + 103f4: 6831 ldr r1, [r6, #0] + 103f6: 3118 adds r1, #24 + _lv_style_list_add_style(list, &styles->kb_bg); + 103f8: 4638 mov r0, r7 + 103fa: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_KEYBOARD_PART_BTN); + 103fc: 2101 movs r1, #1 + 103fe: 4620 mov r0, r4 + 10400: 47c8 blx r9 + list = lv_obj_get_style_list(obj, LV_KEYBOARD_PART_BTN); + 10402: 2101 movs r1, #1 + 10404: 4620 mov r0, r4 + 10406: 47c0 blx r8 + _lv_style_list_add_style(list, &styles->bg); + 10408: 6831 ldr r1, [r6, #0] + 1040a: 3104 adds r1, #4 + list = lv_obj_get_style_list(obj, LV_KEYBOARD_PART_BTN); + 1040c: 4607 mov r7, r0 + _lv_style_list_add_style(list, &styles->bg); + 1040e: 47a8 blx r5 + _lv_style_list_add_style(list, &styles->bg_click); + 10410: 6831 ldr r1, [r6, #0] + 10412: 4638 mov r0, r7 + 10414: 3108 adds r1, #8 + _lv_style_list_add_style(list, &styles->gauge_needle); + 10416: 47a8 blx r5 + break; + 10418: e7c1 b.n 1039e + lv_obj_clean_style_list(obj, LV_KEYBOARD_PART_BG); + 1041a: 2100 movs r1, #0 + 1041c: f8df 91d0 ldr.w r9, [pc, #464] ; 105f0 + list = lv_obj_get_style_list(obj, LV_KEYBOARD_PART_BG); + 10420: f8df 81d0 ldr.w r8, [pc, #464] ; 105f4 + _lv_style_list_add_style(list, &styles->scr); + 10424: 4e74 ldr r6, [pc, #464] ; (105f8 ) + 10426: 4d75 ldr r5, [pc, #468] ; (105fc ) + lv_obj_clean_style_list(obj, LV_KEYBOARD_PART_BG); + 10428: 47c8 blx r9 + list = lv_obj_get_style_list(obj, LV_KEYBOARD_PART_BG); + 1042a: 2100 movs r1, #0 + 1042c: 4620 mov r0, r4 + 1042e: 47c0 blx r8 + _lv_style_list_add_style(list, &styles->scr); + 10430: 6831 ldr r1, [r6, #0] + list = lv_obj_get_style_list(obj, LV_KEYBOARD_PART_BG); + 10432: 4607 mov r7, r0 + _lv_style_list_add_style(list, &styles->scr); + 10434: 47a8 blx r5 + _lv_style_list_add_style(list, &styles->kb_bg); + 10436: 6831 ldr r1, [r6, #0] + 10438: 3168 adds r1, #104 ; 0x68 + 1043a: e7dd b.n 103f8 + lv_obj_clean_style_list(obj, LV_BAR_PART_BG); + 1043c: f8df 81b0 ldr.w r8, [pc, #432] ; 105f0 + _lv_style_list_add_style(list, &styles->bar_bg); + 10440: 4e6d ldr r6, [pc, #436] ; (105f8 ) + list = lv_obj_get_style_list(obj, LV_BAR_PART_BG); + 10442: 4f6c ldr r7, [pc, #432] ; (105f4 ) + _lv_style_list_add_style(list, &styles->bar_bg); + 10444: 4d6d ldr r5, [pc, #436] ; (105fc ) + lv_obj_clean_style_list(obj, LV_BAR_PART_BG); + 10446: 2100 movs r1, #0 + 10448: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_BAR_PART_BG); + 1044a: 2100 movs r1, #0 + 1044c: 4620 mov r0, r4 + 1044e: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->bar_bg); + 10450: 6831 ldr r1, [r6, #0] + 10452: 3124 adds r1, #36 ; 0x24 + 10454: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_BAR_PART_INDIC); + 10456: 2101 movs r1, #1 + 10458: 4620 mov r0, r4 + 1045a: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_BAR_PART_INDIC); + 1045c: 2101 movs r1, #1 + 1045e: 4620 mov r0, r4 + 10460: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->bar_indic); + 10462: 6831 ldr r1, [r6, #0] + 10464: 3128 adds r1, #40 ; 0x28 + 10466: e7d6 b.n 10416 + lv_obj_clean_style_list(obj, LV_SWITCH_PART_BG); + 10468: f8df 8184 ldr.w r8, [pc, #388] ; 105f0 + _lv_style_list_add_style(list, &styles->bar_bg); + 1046c: 4e62 ldr r6, [pc, #392] ; (105f8 ) + list = lv_obj_get_style_list(obj, LV_SWITCH_PART_BG); + 1046e: 4f61 ldr r7, [pc, #388] ; (105f4 ) + _lv_style_list_add_style(list, &styles->bar_bg); + 10470: 4d62 ldr r5, [pc, #392] ; (105fc ) + lv_obj_clean_style_list(obj, LV_SWITCH_PART_BG); + 10472: 2100 movs r1, #0 + 10474: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_SWITCH_PART_BG); + 10476: 2100 movs r1, #0 + 10478: 4620 mov r0, r4 + 1047a: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->bar_bg); + 1047c: 6831 ldr r1, [r6, #0] + 1047e: 3124 adds r1, #36 ; 0x24 + 10480: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_SWITCH_PART_INDIC); + 10482: 2101 movs r1, #1 + 10484: 4620 mov r0, r4 + 10486: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_SWITCH_PART_INDIC); + 10488: 2101 movs r1, #1 + 1048a: 4620 mov r0, r4 + 1048c: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->bar_indic); + 1048e: 6831 ldr r1, [r6, #0] + 10490: 3128 adds r1, #40 ; 0x28 + 10492: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_SWITCH_PART_KNOB); + 10494: 2102 movs r1, #2 + 10496: 4620 mov r0, r4 + 10498: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_SWITCH_PART_KNOB); + 1049a: 2102 movs r1, #2 + 1049c: 4620 mov r0, r4 + 1049e: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->sw_knob); + 104a0: 6831 ldr r1, [r6, #0] + 104a2: 319c adds r1, #156 ; 0x9c + 104a4: e7b7 b.n 10416 + lv_obj_clean_style_list(obj, LV_CANVAS_PART_MAIN); + 104a6: 4b52 ldr r3, [pc, #328] ; (105f0 ) + 104a8: 2100 movs r1, #0 + 104aa: 4798 blx r3 + break; + 104ac: e777 b.n 1039e + lv_obj_clean_style_list(obj, LV_ARC_PART_BG); + 104ae: f8df 9140 ldr.w r9, [pc, #320] ; 105f0 + _lv_style_list_add_style(list, &styles->bg); + 104b2: 4e51 ldr r6, [pc, #324] ; (105f8 ) + list = lv_obj_get_style_list(obj, LV_ARC_PART_BG); + 104b4: f8df 813c ldr.w r8, [pc, #316] ; 105f4 + _lv_style_list_add_style(list, &styles->bg); + 104b8: 4d50 ldr r5, [pc, #320] ; (105fc ) + lv_obj_clean_style_list(obj, LV_ARC_PART_BG); + 104ba: 2100 movs r1, #0 + 104bc: 47c8 blx r9 + list = lv_obj_get_style_list(obj, LV_ARC_PART_BG); + 104be: 2100 movs r1, #0 + 104c0: 4620 mov r0, r4 + 104c2: 47c0 blx r8 + _lv_style_list_add_style(list, &styles->bg); + 104c4: 6831 ldr r1, [r6, #0] + 104c6: 3104 adds r1, #4 + list = lv_obj_get_style_list(obj, LV_ARC_PART_BG); + 104c8: 4607 mov r7, r0 + _lv_style_list_add_style(list, &styles->bg); + 104ca: 47a8 blx r5 + _lv_style_list_add_style(list, &styles->arc_bg); + 104cc: 6831 ldr r1, [r6, #0] + 104ce: 4638 mov r0, r7 + 104d0: 3120 adds r1, #32 + 104d2: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_ARC_PART_INDIC); + 104d4: 2101 movs r1, #1 + 104d6: 4620 mov r0, r4 + 104d8: 47c8 blx r9 + list = lv_obj_get_style_list(obj, LV_ARC_PART_INDIC); + 104da: 2101 movs r1, #1 + 104dc: 4620 mov r0, r4 + 104de: 47c0 blx r8 + _lv_style_list_add_style(list, &styles->arc_indic); + 104e0: 6831 ldr r1, [r6, #0] + 104e2: 311c adds r1, #28 + 104e4: e797 b.n 10416 + lv_obj_clean_style_list(obj, LV_SPINNER_PART_BG); + 104e6: f8df 8108 ldr.w r8, [pc, #264] ; 105f0 + _lv_style_list_add_style(list, &styles->arc_bg); + 104ea: 4e43 ldr r6, [pc, #268] ; (105f8 ) + list = lv_obj_get_style_list(obj, LV_SPINNER_PART_BG); + 104ec: 4f41 ldr r7, [pc, #260] ; (105f4 ) + _lv_style_list_add_style(list, &styles->arc_bg); + 104ee: 4d43 ldr r5, [pc, #268] ; (105fc ) + lv_obj_clean_style_list(obj, LV_SPINNER_PART_BG); + 104f0: 2100 movs r1, #0 + 104f2: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_SPINNER_PART_BG); + 104f4: 2100 movs r1, #0 + 104f6: 4620 mov r0, r4 + 104f8: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->arc_bg); + 104fa: 6831 ldr r1, [r6, #0] + 104fc: 3120 adds r1, #32 + 104fe: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_SPINNER_PART_INDIC); + 10500: 4620 mov r0, r4 + 10502: 2101 movs r1, #1 + 10504: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_SPINNER_PART_INDIC); + 10506: 2101 movs r1, #1 + 10508: 4620 mov r0, r4 + 1050a: 47b8 blx r7 + 1050c: e7e8 b.n 104e0 + _lv_style_list_add_style(list, &styles->bar_bg); + 1050e: 4e3a ldr r6, [pc, #232] ; (105f8 ) + lv_obj_clean_style_list(obj, LV_SLIDER_PART_BG); + 10510: f8df 80dc ldr.w r8, [pc, #220] ; 105f0 + list = lv_obj_get_style_list(obj, LV_SLIDER_PART_BG); + 10514: 4f37 ldr r7, [pc, #220] ; (105f4 ) + _lv_style_list_add_style(list, &styles->bar_bg); + 10516: 4d39 ldr r5, [pc, #228] ; (105fc ) + lv_obj_clean_style_list(obj, LV_SLIDER_PART_BG); + 10518: 2100 movs r1, #0 + 1051a: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_SLIDER_PART_BG); + 1051c: 2100 movs r1, #0 + 1051e: 4620 mov r0, r4 + 10520: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->bar_bg); + 10522: 6831 ldr r1, [r6, #0] + 10524: 3124 adds r1, #36 ; 0x24 + list = lv_obj_get_style_list(obj, LV_SLIDER_PART_BG); + 10526: 4681 mov r9, r0 + _lv_style_list_add_style(list, &styles->bar_bg); + 10528: 47a8 blx r5 + _lv_style_list_add_style(list, &styles->slider_bg); + 1052a: 6831 ldr r1, [r6, #0] + 1052c: 4648 mov r0, r9 + 1052e: 3194 adds r1, #148 ; 0x94 + 10530: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_SLIDER_PART_INDIC); + 10532: 2101 movs r1, #1 + 10534: 4620 mov r0, r4 + 10536: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_SLIDER_PART_INDIC); + 10538: 2101 movs r1, #1 + 1053a: 4620 mov r0, r4 + 1053c: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->bar_indic); + 1053e: 6831 ldr r1, [r6, #0] + 10540: 3128 adds r1, #40 ; 0x28 + 10542: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_SLIDER_PART_KNOB); + 10544: 2102 movs r1, #2 + 10546: 4620 mov r0, r4 + 10548: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_SLIDER_PART_KNOB); + 1054a: 2102 movs r1, #2 + 1054c: 4620 mov r0, r4 + 1054e: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->slider_knob); + 10550: 6831 ldr r1, [r6, #0] + 10552: 3190 adds r1, #144 ; 0x90 + 10554: e75f b.n 10416 + _lv_style_list_add_style(list, &styles->cb_bg); + 10556: 4f28 ldr r7, [pc, #160] ; (105f8 ) + lv_obj_clean_style_list(obj, LV_CHECKBOX_PART_BG); + 10558: f8df 8094 ldr.w r8, [pc, #148] ; 105f0 + list = lv_obj_get_style_list(obj, LV_CHECKBOX_PART_BG); + 1055c: 4e25 ldr r6, [pc, #148] ; (105f4 ) + _lv_style_list_add_style(list, &styles->cb_bg); + 1055e: 4d27 ldr r5, [pc, #156] ; (105fc ) + lv_obj_clean_style_list(obj, LV_CHECKBOX_PART_BG); + 10560: 2100 movs r1, #0 + 10562: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_CHECKBOX_PART_BG); + 10564: 2100 movs r1, #0 + 10566: 4620 mov r0, r4 + 10568: 47b0 blx r6 + _lv_style_list_add_style(list, &styles->cb_bg); + 1056a: 6839 ldr r1, [r7, #0] + 1056c: 314c adds r1, #76 ; 0x4c + 1056e: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_CHECKBOX_PART_BULLET); + 10570: 2140 movs r1, #64 ; 0x40 + 10572: 4620 mov r0, r4 + 10574: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_CHECKBOX_PART_BULLET); + 10576: 2140 movs r1, #64 ; 0x40 + 10578: 4620 mov r0, r4 + 1057a: 47b0 blx r6 + _lv_style_list_add_style(list, &styles->btn); + 1057c: 6839 ldr r1, [r7, #0] + 1057e: 3110 adds r1, #16 + list = lv_obj_get_style_list(obj, LV_CHECKBOX_PART_BULLET); + 10580: 4606 mov r6, r0 + _lv_style_list_add_style(list, &styles->btn); + 10582: 47a8 blx r5 + _lv_style_list_add_style(list, &styles->cb_bullet); + 10584: 6839 ldr r1, [r7, #0] + 10586: 4630 mov r0, r6 + 10588: 3150 adds r1, #80 ; 0x50 + 1058a: e744 b.n 10416 + lv_obj_clean_style_list(obj, LV_MSGBOX_PART_BG); + 1058c: 4b18 ldr r3, [pc, #96] ; (105f0 ) + _lv_style_list_add_style(list, &styles->bg); + 1058e: 4f1a ldr r7, [pc, #104] ; (105f8 ) + 10590: 4e1a ldr r6, [pc, #104] ; (105fc ) + lv_obj_clean_style_list(obj, LV_MSGBOX_PART_BG); + 10592: 2100 movs r1, #0 + 10594: 4798 blx r3 + list = lv_obj_get_style_list(obj, LV_MSGBOX_PART_BG); + 10596: 4b17 ldr r3, [pc, #92] ; (105f4 ) + 10598: 2100 movs r1, #0 + 1059a: 4620 mov r0, r4 + 1059c: 4798 blx r3 + _lv_style_list_add_style(list, &styles->bg); + 1059e: 6839 ldr r1, [r7, #0] + 105a0: 3104 adds r1, #4 + list = lv_obj_get_style_list(obj, LV_MSGBOX_PART_BG); + 105a2: 4605 mov r5, r0 + _lv_style_list_add_style(list, &styles->bg); + 105a4: 47b0 blx r6 + _lv_style_list_add_style(list, &styles->mbox_bg); + 105a6: 6839 ldr r1, [r7, #0] + 105a8: 317c adds r1, #124 ; 0x7c + _lv_style_list_add_style(list, &styles->lmeter); + 105aa: 4628 mov r0, r5 + 105ac: e07b b.n 106a6 + lv_obj_clean_style_list(obj, LV_MSGBOX_PART_BTN_BG); + 105ae: f8df 8040 ldr.w r8, [pc, #64] ; 105f0 + _lv_style_list_add_style(list, &styles->pad_small); + 105b2: 4e11 ldr r6, [pc, #68] ; (105f8 ) + list = lv_obj_get_style_list(obj, LV_MSGBOX_PART_BTN_BG); + 105b4: 4f0f ldr r7, [pc, #60] ; (105f4 ) + _lv_style_list_add_style(list, &styles->pad_small); + 105b6: 4d11 ldr r5, [pc, #68] ; (105fc ) + lv_obj_clean_style_list(obj, LV_MSGBOX_PART_BTN_BG); + 105b8: 2140 movs r1, #64 ; 0x40 + 105ba: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_MSGBOX_PART_BTN_BG); + 105bc: 2140 movs r1, #64 ; 0x40 + 105be: 4620 mov r0, r4 + 105c0: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->pad_small); + 105c2: 6831 ldr r1, [r6, #0] + 105c4: 3118 adds r1, #24 + 105c6: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_MSGBOX_PART_BTN); + 105c8: 2141 movs r1, #65 ; 0x41 + 105ca: 4620 mov r0, r4 + 105cc: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_MSGBOX_PART_BTN); + 105ce: 2141 movs r1, #65 ; 0x41 + 105d0: 4620 mov r0, r4 + 105d2: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->btn); + 105d4: 6831 ldr r1, [r6, #0] + 105d6: 3110 adds r1, #16 + 105d8: e71d b.n 10416 + lv_obj_clean_style_list(obj, LV_LED_PART_MAIN); + 105da: 4b05 ldr r3, [pc, #20] ; (105f0 ) + 105dc: 2100 movs r1, #0 + 105de: 4798 blx r3 + list = lv_obj_get_style_list(obj, LV_LED_PART_MAIN); + 105e0: 4b04 ldr r3, [pc, #16] ; (105f4 ) + 105e2: 2100 movs r1, #0 + 105e4: 4620 mov r0, r4 + 105e6: 4798 blx r3 + _lv_style_list_add_style(list, &styles->led); + 105e8: 4b03 ldr r3, [pc, #12] ; (105f8 ) + 105ea: 6819 ldr r1, [r3, #0] + 105ec: 316c adds r1, #108 ; 0x6c + 105ee: e6d4 b.n 1039a + 105f0: 00002549 .word 0x00002549 + 105f4: 0000248d .word 0x0000248d + 105f8: 2000c7d4 .word 0x2000c7d4 + 105fc: 00005619 .word 0x00005619 + 10600: 00002d91 .word 0x00002d91 + lv_obj_clean_style_list(obj, LV_PAGE_PART_BG); + 10604: f8df 82a8 ldr.w r8, [pc, #680] ; 108b0 + _lv_style_list_add_style(list, &styles->bg); + 10608: 4ea6 ldr r6, [pc, #664] ; (108a4 ) + list = lv_obj_get_style_list(obj, LV_PAGE_PART_BG); + 1060a: 4fa7 ldr r7, [pc, #668] ; (108a8 ) + _lv_style_list_add_style(list, &styles->bg); + 1060c: 4da7 ldr r5, [pc, #668] ; (108ac ) + lv_obj_clean_style_list(obj, LV_PAGE_PART_BG); + 1060e: 2100 movs r1, #0 + 10610: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_PAGE_PART_BG); + 10612: 2100 movs r1, #0 + 10614: 4620 mov r0, r4 + 10616: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->bg); + 10618: 6831 ldr r1, [r6, #0] + 1061a: 3104 adds r1, #4 + 1061c: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_PAGE_PART_SCROLLABLE); + 1061e: 2140 movs r1, #64 ; 0x40 + 10620: 4620 mov r0, r4 + 10622: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_PAGE_PART_SCROLLABLE); + 10624: 2140 movs r1, #64 ; 0x40 + 10626: 4620 mov r0, r4 + 10628: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->pad_inner); + 1062a: 6831 ldr r1, [r6, #0] + 1062c: 3114 adds r1, #20 + _lv_style_list_add_style(list, &styles->scr); + 1062e: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_TILEVIEW_PART_SCROLLBAR); + 10630: 2101 movs r1, #1 + 10632: 4620 mov r0, r4 + 10634: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_TILEVIEW_PART_SCROLLBAR); + 10636: 2101 movs r1, #1 + 10638: 4620 mov r0, r4 + 1063a: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->sb); + 1063c: 6831 ldr r1, [r6, #0] + 1063e: 3180 adds r1, #128 ; 0x80 + 10640: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_TILEVIEW_PART_EDGE_FLASH); + 10642: 2102 movs r1, #2 + 10644: 4620 mov r0, r4 + 10646: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_TILEVIEW_PART_EDGE_FLASH); + 10648: 2102 movs r1, #2 + 1064a: 4620 mov r0, r4 + 1064c: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->edge_flash); + 1064e: 6831 ldr r1, [r6, #0] + 10650: 3184 adds r1, #132 ; 0x84 + 10652: e6e0 b.n 10416 + lv_obj_clean_style_list(obj, LV_TABVIEW_PART_BG); + 10654: 4d96 ldr r5, [pc, #600] ; (108b0 ) + _lv_style_list_add_style(list, &styles->scr); + 10656: 4f93 ldr r7, [pc, #588] ; (108a4 ) + list = lv_obj_get_style_list(obj, LV_TABVIEW_PART_BG); + 10658: f8df 824c ldr.w r8, [pc, #588] ; 108a8 + _lv_style_list_add_style(list, &styles->scr); + 1065c: 4e93 ldr r6, [pc, #588] ; (108ac ) + lv_obj_clean_style_list(obj, LV_TABVIEW_PART_BG); + 1065e: 2100 movs r1, #0 + 10660: 47a8 blx r5 + list = lv_obj_get_style_list(obj, LV_TABVIEW_PART_BG); + 10662: 2100 movs r1, #0 + 10664: 4620 mov r0, r4 + 10666: 47c0 blx r8 + _lv_style_list_add_style(list, &styles->scr); + 10668: 6839 ldr r1, [r7, #0] + 1066a: 47b0 blx r6 + lv_obj_clean_style_list(obj, LV_TABVIEW_PART_BG_SCRLLABLE); + 1066c: 2140 movs r1, #64 ; 0x40 + 1066e: 4620 mov r0, r4 + 10670: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_TABVIEW_PART_TAB_BG); + 10672: 2141 movs r1, #65 ; 0x41 + 10674: 4620 mov r0, r4 + 10676: 47a8 blx r5 + list = lv_obj_get_style_list(obj, LV_TABVIEW_PART_TAB_BG); + 10678: 2141 movs r1, #65 ; 0x41 + 1067a: 4620 mov r0, r4 + 1067c: 47c0 blx r8 + _lv_style_list_add_style(list, &styles->tabview_btns_bg); + 1067e: 6839 ldr r1, [r7, #0] + 10680: 31a8 adds r1, #168 ; 0xa8 + 10682: 47b0 blx r6 + lv_obj_clean_style_list(obj, LV_TABVIEW_PART_INDIC); + 10684: 2143 movs r1, #67 ; 0x43 + 10686: 4620 mov r0, r4 + 10688: 47a8 blx r5 + list = lv_obj_get_style_list(obj, LV_TABVIEW_PART_INDIC); + 1068a: 2143 movs r1, #67 ; 0x43 + 1068c: 4620 mov r0, r4 + 1068e: 47c0 blx r8 + _lv_style_list_add_style(list, &styles->tabview_indic); + 10690: 6839 ldr r1, [r7, #0] + 10692: 31ac adds r1, #172 ; 0xac + 10694: 47b0 blx r6 + lv_obj_clean_style_list(obj, LV_TABVIEW_PART_TAB_BTN); + 10696: 2142 movs r1, #66 ; 0x42 + 10698: 4620 mov r0, r4 + 1069a: 47a8 blx r5 + list = lv_obj_get_style_list(obj, LV_TABVIEW_PART_TAB_BTN); + 1069c: 2142 movs r1, #66 ; 0x42 + 1069e: 4620 mov r0, r4 + 106a0: 47c0 blx r8 + _lv_style_list_add_style(list, &styles->tabview_btns); + 106a2: 6839 ldr r1, [r7, #0] + 106a4: 31a4 adds r1, #164 ; 0xa4 + _lv_style_list_add_style(list, &styles->lmeter); + 106a6: 47b0 blx r6 + break; + 106a8: e679 b.n 1039e + lv_obj_clean_style_list(obj, LV_PAGE_PART_BG); + 106aa: 4d81 ldr r5, [pc, #516] ; (108b0 ) + 106ac: 2100 movs r1, #0 + 106ae: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_PAGE_PART_SCROLLABLE); + 106b0: 2140 movs r1, #64 ; 0x40 + 106b2: 4620 mov r0, r4 + 106b4: 47a8 blx r5 + list = lv_obj_get_style_list(obj, LV_PAGE_PART_SCROLLABLE); + 106b6: 4b7c ldr r3, [pc, #496] ; (108a8 ) + 106b8: 2140 movs r1, #64 ; 0x40 + 106ba: 4620 mov r0, r4 + 106bc: 4798 blx r3 + _lv_style_list_add_style(list, &styles->tabview_page_scrl); + 106be: 4b79 ldr r3, [pc, #484] ; (108a4 ) + 106c0: 6819 ldr r1, [r3, #0] + 106c2: 31b0 adds r1, #176 ; 0xb0 + 106c4: e669 b.n 1039a + lv_obj_clean_style_list(obj, LV_TILEVIEW_PART_BG); + 106c6: 2100 movs r1, #0 + 106c8: f8df 81e4 ldr.w r8, [pc, #484] ; 108b0 + _lv_style_list_add_style(list, &styles->scr); + 106cc: 4e75 ldr r6, [pc, #468] ; (108a4 ) + list = lv_obj_get_style_list(obj, LV_TILEVIEW_PART_BG); + 106ce: 4f76 ldr r7, [pc, #472] ; (108a8 ) + _lv_style_list_add_style(list, &styles->scr); + 106d0: 4d76 ldr r5, [pc, #472] ; (108ac ) + lv_obj_clean_style_list(obj, LV_TILEVIEW_PART_BG); + 106d2: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_TILEVIEW_PART_BG); + 106d4: 2100 movs r1, #0 + 106d6: 4620 mov r0, r4 + 106d8: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->scr); + 106da: 6831 ldr r1, [r6, #0] + 106dc: e7a7 b.n 1062e + _lv_style_list_add_style(list, &styles->bg); + 106de: 4e71 ldr r6, [pc, #452] ; (108a4 ) + lv_obj_clean_style_list(obj, LV_ROLLER_PART_BG); + 106e0: f8df 91cc ldr.w r9, [pc, #460] ; 108b0 + list = lv_obj_get_style_list(obj, LV_ROLLER_PART_BG); + 106e4: f8df 81c0 ldr.w r8, [pc, #448] ; 108a8 + _lv_style_list_add_style(list, &styles->bg); + 106e8: 4d70 ldr r5, [pc, #448] ; (108ac ) + lv_obj_clean_style_list(obj, LV_ROLLER_PART_BG); + 106ea: 2100 movs r1, #0 + 106ec: 47c8 blx r9 + list = lv_obj_get_style_list(obj, LV_ROLLER_PART_BG); + 106ee: 2100 movs r1, #0 + 106f0: 4620 mov r0, r4 + 106f2: 47c0 blx r8 + _lv_style_list_add_style(list, &styles->bg); + 106f4: 6831 ldr r1, [r6, #0] + 106f6: 3104 adds r1, #4 + list = lv_obj_get_style_list(obj, LV_ROLLER_PART_BG); + 106f8: 4607 mov r7, r0 + _lv_style_list_add_style(list, &styles->bg); + 106fa: 47a8 blx r5 + _lv_style_list_add_style(list, &styles->roller_bg); + 106fc: 6831 ldr r1, [r6, #0] + 106fe: 4638 mov r0, r7 + 10700: 3188 adds r1, #136 ; 0x88 + 10702: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_ROLLER_PART_SELECTED); + 10704: 2103 movs r1, #3 + 10706: 4620 mov r0, r4 + 10708: 47c8 blx r9 + list = lv_obj_get_style_list(obj, LV_ROLLER_PART_SELECTED); + 1070a: 2103 movs r1, #3 + 1070c: 4620 mov r0, r4 + 1070e: 47c0 blx r8 + _lv_style_list_add_style(list, &styles->roller_sel); + 10710: 6831 ldr r1, [r6, #0] + 10712: 318c adds r1, #140 ; 0x8c + 10714: e67f b.n 10416 + lv_obj_clean_style_list(obj, LV_OBJMASK_PART_MAIN); + 10716: 4b66 ldr r3, [pc, #408] ; (108b0 ) + 10718: 2100 movs r1, #0 + 1071a: 4798 blx r3 + list = lv_obj_get_style_list(obj, LV_OBJMASK_PART_MAIN); + 1071c: 4b62 ldr r3, [pc, #392] ; (108a8 ) + 1071e: 2100 movs r1, #0 + 10720: 4620 mov r0, r4 + 10722: 4798 blx r3 + break; + 10724: e63b b.n 1039e + lv_obj_clean_style_list(obj, LV_LIST_PART_BG); + 10726: 4f62 ldr r7, [pc, #392] ; (108b0 ) + _lv_style_list_add_style(list, &styles->bg); + 10728: 4e5e ldr r6, [pc, #376] ; (108a4 ) + list = lv_obj_get_style_list(obj, LV_LIST_PART_BG); + 1072a: f8df 917c ldr.w r9, [pc, #380] ; 108a8 + _lv_style_list_add_style(list, &styles->bg); + 1072e: 4d5f ldr r5, [pc, #380] ; (108ac ) + lv_obj_clean_style_list(obj, LV_LIST_PART_BG); + 10730: 2100 movs r1, #0 + 10732: 47b8 blx r7 + list = lv_obj_get_style_list(obj, LV_LIST_PART_BG); + 10734: 2100 movs r1, #0 + 10736: 4620 mov r0, r4 + 10738: 47c8 blx r9 + _lv_style_list_add_style(list, &styles->bg); + 1073a: 6831 ldr r1, [r6, #0] + 1073c: 3104 adds r1, #4 + list = lv_obj_get_style_list(obj, LV_LIST_PART_BG); + 1073e: 4680 mov r8, r0 + _lv_style_list_add_style(list, &styles->bg); + 10740: 47a8 blx r5 + _lv_style_list_add_style(list, &styles->list_bg); + 10742: 6831 ldr r1, [r6, #0] + 10744: 4640 mov r0, r8 + 10746: 3174 adds r1, #116 ; 0x74 + 10748: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_LIST_PART_SCROLLABLE); + 1074a: 2140 movs r1, #64 ; 0x40 + 1074c: 4620 mov r0, r4 + 1074e: 47b8 blx r7 + lv_obj_clean_style_list(obj, LV_LIST_PART_SCROLLBAR); + 10750: 2101 movs r1, #1 + 10752: 4620 mov r0, r4 + 10754: 47b8 blx r7 + list = lv_obj_get_style_list(obj, LV_LIST_PART_SCROLLBAR); + 10756: 2101 movs r1, #1 + 10758: 4620 mov r0, r4 + 1075a: 47c8 blx r9 + _lv_style_list_add_style(list, &styles->sb); + 1075c: 6831 ldr r1, [r6, #0] + 1075e: 3180 adds r1, #128 ; 0x80 + 10760: e659 b.n 10416 + lv_obj_clean_style_list(obj, LV_BTN_PART_MAIN); + 10762: 4b53 ldr r3, [pc, #332] ; (108b0 ) + 10764: 2100 movs r1, #0 + 10766: 4798 blx r3 + list = lv_obj_get_style_list(obj, LV_BTN_PART_MAIN); + 10768: 4b4f ldr r3, [pc, #316] ; (108a8 ) + 1076a: 2100 movs r1, #0 + 1076c: 4620 mov r0, r4 + 1076e: 4798 blx r3 + _lv_style_list_add_style(list, &styles->list_btn); + 10770: 4b4c ldr r3, [pc, #304] ; (108a4 ) + 10772: 6819 ldr r1, [r3, #0] + 10774: 3178 adds r1, #120 ; 0x78 + 10776: e610 b.n 1039a + _lv_style_list_add_style(list, &styles->bg); + 10778: 4e4a ldr r6, [pc, #296] ; (108a4 ) + lv_obj_clean_style_list(obj, LV_DROPDOWN_PART_MAIN); + 1077a: f8df 8134 ldr.w r8, [pc, #308] ; 108b0 + list = lv_obj_get_style_list(obj, LV_DROPDOWN_PART_MAIN); + 1077e: 4f4a ldr r7, [pc, #296] ; (108a8 ) + _lv_style_list_add_style(list, &styles->bg); + 10780: 4d4a ldr r5, [pc, #296] ; (108ac ) + lv_obj_clean_style_list(obj, LV_DROPDOWN_PART_MAIN); + 10782: 2100 movs r1, #0 + 10784: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_DROPDOWN_PART_MAIN); + 10786: 2100 movs r1, #0 + 10788: 4620 mov r0, r4 + 1078a: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->bg); + 1078c: 6831 ldr r1, [r6, #0] + 1078e: 3104 adds r1, #4 + list = lv_obj_get_style_list(obj, LV_DROPDOWN_PART_MAIN); + 10790: 4681 mov r9, r0 + _lv_style_list_add_style(list, &styles->bg); + 10792: 47a8 blx r5 + _lv_style_list_add_style(list, &styles->bg_click); + 10794: 6831 ldr r1, [r6, #0] + 10796: 4648 mov r0, r9 + 10798: 3108 adds r1, #8 + 1079a: 47a8 blx r5 + _lv_style_list_add_style(list, &styles->pad_small); + 1079c: 6831 ldr r1, [r6, #0] + 1079e: 4648 mov r0, r9 + 107a0: 3118 adds r1, #24 + 107a2: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_DROPDOWN_PART_LIST); + 107a4: 2140 movs r1, #64 ; 0x40 + 107a6: 4620 mov r0, r4 + 107a8: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_DROPDOWN_PART_LIST); + 107aa: 2140 movs r1, #64 ; 0x40 + 107ac: 4620 mov r0, r4 + 107ae: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->bg); + 107b0: 6831 ldr r1, [r6, #0] + 107b2: 3104 adds r1, #4 + list = lv_obj_get_style_list(obj, LV_DROPDOWN_PART_LIST); + 107b4: 4681 mov r9, r0 + _lv_style_list_add_style(list, &styles->bg); + 107b6: 47a8 blx r5 + _lv_style_list_add_style(list, &styles->ddlist_page); + 107b8: 6831 ldr r1, [r6, #0] + 107ba: 4648 mov r0, r9 + 107bc: 3154 adds r1, #84 ; 0x54 + 107be: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_DROPDOWN_PART_SCROLLBAR); + 107c0: 2141 movs r1, #65 ; 0x41 + 107c2: 4620 mov r0, r4 + 107c4: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_DROPDOWN_PART_SCROLLBAR); + 107c6: 2141 movs r1, #65 ; 0x41 + 107c8: 4620 mov r0, r4 + 107ca: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->sb); + 107cc: 6831 ldr r1, [r6, #0] + 107ce: 3180 adds r1, #128 ; 0x80 + 107d0: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_DROPDOWN_PART_SELECTED); + 107d2: 2142 movs r1, #66 ; 0x42 + 107d4: 4620 mov r0, r4 + 107d6: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_DROPDOWN_PART_SELECTED); + 107d8: 2142 movs r1, #66 ; 0x42 + 107da: 4620 mov r0, r4 + 107dc: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->ddlist_sel); + 107de: 6831 ldr r1, [r6, #0] + 107e0: 3158 adds r1, #88 ; 0x58 + 107e2: e618 b.n 10416 + _lv_style_list_add_style(list, &styles->bg); + 107e4: 4e2f ldr r6, [pc, #188] ; (108a4 ) + lv_obj_clean_style_list(obj, LV_CHART_PART_BG); + 107e6: f8df 90c8 ldr.w r9, [pc, #200] ; 108b0 + list = lv_obj_get_style_list(obj, LV_CHART_PART_BG); + 107ea: f8df 80bc ldr.w r8, [pc, #188] ; 108a8 + _lv_style_list_add_style(list, &styles->bg); + 107ee: 4d2f ldr r5, [pc, #188] ; (108ac ) + lv_obj_clean_style_list(obj, LV_CHART_PART_BG); + 107f0: 2100 movs r1, #0 + 107f2: 47c8 blx r9 + list = lv_obj_get_style_list(obj, LV_CHART_PART_BG); + 107f4: 2100 movs r1, #0 + 107f6: 4620 mov r0, r4 + 107f8: 47c0 blx r8 + _lv_style_list_add_style(list, &styles->bg); + 107fa: 6831 ldr r1, [r6, #0] + 107fc: 3104 adds r1, #4 + list = lv_obj_get_style_list(obj, LV_CHART_PART_BG); + 107fe: 4607 mov r7, r0 + _lv_style_list_add_style(list, &styles->bg); + 10800: 47a8 blx r5 + _lv_style_list_add_style(list, &styles->chart_bg); + 10802: 6831 ldr r1, [r6, #0] + 10804: 4638 mov r0, r7 + 10806: 3140 adds r1, #64 ; 0x40 + 10808: 47a8 blx r5 + _lv_style_list_add_style(list, &styles->pad_small); + 1080a: 6831 ldr r1, [r6, #0] + 1080c: 4638 mov r0, r7 + 1080e: 3118 adds r1, #24 + 10810: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_CHART_PART_SERIES_BG); + 10812: 2101 movs r1, #1 + 10814: 4620 mov r0, r4 + 10816: 47c8 blx r9 + list = lv_obj_get_style_list(obj, LV_CHART_PART_SERIES_BG); + 10818: 2101 movs r1, #1 + 1081a: 4620 mov r0, r4 + 1081c: 47c0 blx r8 + _lv_style_list_add_style(list, &styles->pad_small); + 1081e: 6831 ldr r1, [r6, #0] + 10820: 3118 adds r1, #24 + list = lv_obj_get_style_list(obj, LV_CHART_PART_SERIES_BG); + 10822: 4607 mov r7, r0 + _lv_style_list_add_style(list, &styles->pad_small); + 10824: 47a8 blx r5 + _lv_style_list_add_style(list, &styles->chart_series_bg); + 10826: 6831 ldr r1, [r6, #0] + 10828: 4638 mov r0, r7 + 1082a: 3144 adds r1, #68 ; 0x44 + 1082c: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_CHART_PART_SERIES); + 1082e: 2102 movs r1, #2 + 10830: 4620 mov r0, r4 + 10832: 47c8 blx r9 + list = lv_obj_get_style_list(obj, LV_CHART_PART_SERIES); + 10834: 2102 movs r1, #2 + 10836: 4620 mov r0, r4 + 10838: 47c0 blx r8 + _lv_style_list_add_style(list, &styles->chart_series); + 1083a: 6831 ldr r1, [r6, #0] + 1083c: 3148 adds r1, #72 ; 0x48 + 1083e: e5ea b.n 10416 + lv_obj_clean_style_list(obj, LV_TABLE_PART_BG); + 10840: f8df 806c ldr.w r8, [pc, #108] ; 108b0 + _lv_style_list_add_style(list, &styles->bg); + 10844: 4e17 ldr r6, [pc, #92] ; (108a4 ) + list = lv_obj_get_style_list(obj, LV_TABLE_PART_BG); + 10846: 4f18 ldr r7, [pc, #96] ; (108a8 ) + _lv_style_list_add_style(list, &styles->bg); + 10848: 4d18 ldr r5, [pc, #96] ; (108ac ) + lv_obj_clean_style_list(obj, LV_TABLE_PART_BG); + 1084a: 2100 movs r1, #0 + 1084c: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_TABLE_PART_BG); + 1084e: 2100 movs r1, #0 + 10850: 4620 mov r0, r4 + 10852: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->bg); + 10854: 6831 ldr r1, [r6, #0] + 10856: 3104 adds r1, #4 + 10858: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_TABLE_PART_CELL1); + 1085a: 2101 movs r1, #1 + 1085c: 4620 mov r0, r4 + 1085e: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_TABLE_PART_CELL1); + 10860: 2101 movs r1, #1 + 10862: 4620 mov r0, r4 + 10864: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->table_cell); + 10866: 6831 ldr r1, [r6, #0] + 10868: 31a0 adds r1, #160 ; 0xa0 + 1086a: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_TABLE_PART_CELL2); + 1086c: 2102 movs r1, #2 + 1086e: 4620 mov r0, r4 + 10870: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_TABLE_PART_CELL2); + 10872: 2102 movs r1, #2 + 10874: 4620 mov r0, r4 + 10876: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->table_cell); + 10878: 6831 ldr r1, [r6, #0] + 1087a: 31a0 adds r1, #160 ; 0xa0 + 1087c: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_TABLE_PART_CELL3); + 1087e: 2103 movs r1, #3 + 10880: 4620 mov r0, r4 + 10882: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_TABLE_PART_CELL3); + 10884: 2103 movs r1, #3 + 10886: 4620 mov r0, r4 + 10888: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->table_cell); + 1088a: 6831 ldr r1, [r6, #0] + 1088c: 31a0 adds r1, #160 ; 0xa0 + 1088e: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_TABLE_PART_CELL4); + 10890: 2104 movs r1, #4 + 10892: 4620 mov r0, r4 + 10894: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_TABLE_PART_CELL4); + 10896: 2104 movs r1, #4 + 10898: 4620 mov r0, r4 + 1089a: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->table_cell); + 1089c: 6831 ldr r1, [r6, #0] + 1089e: 31a0 adds r1, #160 ; 0xa0 + 108a0: e5b9 b.n 10416 + 108a2: bf00 nop + 108a4: 2000c7d4 .word 0x2000c7d4 + 108a8: 0000248d .word 0x0000248d + 108ac: 00005619 .word 0x00005619 + 108b0: 00002549 .word 0x00002549 + lv_obj_clean_style_list(obj, LV_WIN_PART_BG); + 108b4: f8df 8200 ldr.w r8, [pc, #512] ; 10ab8 + _lv_style_list_add_style(list, &styles->scr); + 108b8: 4e7c ldr r6, [pc, #496] ; (10aac ) + list = lv_obj_get_style_list(obj, LV_WIN_PART_BG); + 108ba: 4f7d ldr r7, [pc, #500] ; (10ab0 ) + _lv_style_list_add_style(list, &styles->scr); + 108bc: 4d7d ldr r5, [pc, #500] ; (10ab4 ) + lv_obj_clean_style_list(obj, LV_WIN_PART_BG); + 108be: 2100 movs r1, #0 + 108c0: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_WIN_PART_BG); + 108c2: 2100 movs r1, #0 + 108c4: 4620 mov r0, r4 + 108c6: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->scr); + 108c8: 6831 ldr r1, [r6, #0] + 108ca: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_WIN_PART_SCROLLBAR); + 108cc: 2142 movs r1, #66 ; 0x42 + 108ce: 4620 mov r0, r4 + 108d0: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_WIN_PART_SCROLLBAR); + 108d2: 2142 movs r1, #66 ; 0x42 + 108d4: 4620 mov r0, r4 + 108d6: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->sb); + 108d8: 6831 ldr r1, [r6, #0] + 108da: 3180 adds r1, #128 ; 0x80 + 108dc: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_WIN_PART_CONTENT_SCROLLABLE); + 108de: 2141 movs r1, #65 ; 0x41 + 108e0: 4620 mov r0, r4 + 108e2: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_WIN_PART_CONTENT_SCROLLABLE); + 108e4: 2141 movs r1, #65 ; 0x41 + 108e6: 4620 mov r0, r4 + 108e8: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->tabview_page_scrl); + 108ea: 6831 ldr r1, [r6, #0] + 108ec: 31b0 adds r1, #176 ; 0xb0 + 108ee: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_WIN_PART_HEADER); + 108f0: 2140 movs r1, #64 ; 0x40 + 108f2: 4620 mov r0, r4 + 108f4: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_WIN_PART_HEADER); + 108f6: 2140 movs r1, #64 ; 0x40 + 108f8: 4620 mov r0, r4 + 108fa: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->tabview_btns_bg); + 108fc: 6831 ldr r1, [r6, #0] + 108fe: 31a8 adds r1, #168 ; 0xa8 + 10900: e589 b.n 10416 + lv_obj_clean_style_list(obj, LV_BTN_PART_MAIN); + 10902: 4b6d ldr r3, [pc, #436] ; (10ab8 ) + 10904: 2100 movs r1, #0 + 10906: 4798 blx r3 + list = lv_obj_get_style_list(obj, LV_BTN_PART_MAIN); + 10908: 4b69 ldr r3, [pc, #420] ; (10ab0 ) + 1090a: 2100 movs r1, #0 + 1090c: 4620 mov r0, r4 + 1090e: 4798 blx r3 + _lv_style_list_add_style(list, &styles->tabview_btns); + 10910: 4b66 ldr r3, [pc, #408] ; (10aac ) + 10912: 6819 ldr r1, [r3, #0] + 10914: 31a4 adds r1, #164 ; 0xa4 + 10916: e540 b.n 1039a + lv_obj_clean_style_list(obj, LV_TEXTAREA_PART_BG); + 10918: f8df 819c ldr.w r8, [pc, #412] ; 10ab8 + _lv_style_list_add_style(list, &styles->bg); + 1091c: 4e63 ldr r6, [pc, #396] ; (10aac ) + list = lv_obj_get_style_list(obj, LV_TEXTAREA_PART_BG); + 1091e: 4f64 ldr r7, [pc, #400] ; (10ab0 ) + _lv_style_list_add_style(list, &styles->bg); + 10920: 4d64 ldr r5, [pc, #400] ; (10ab4 ) + lv_obj_clean_style_list(obj, LV_TEXTAREA_PART_BG); + 10922: 2100 movs r1, #0 + 10924: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_TEXTAREA_PART_BG); + 10926: 2100 movs r1, #0 + 10928: 4620 mov r0, r4 + 1092a: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->bg); + 1092c: 6831 ldr r1, [r6, #0] + 1092e: 3104 adds r1, #4 + list = lv_obj_get_style_list(obj, LV_TEXTAREA_PART_BG); + 10930: 4681 mov r9, r0 + _lv_style_list_add_style(list, &styles->bg); + 10932: 47a8 blx r5 + _lv_style_list_add_style(list, &styles->pad_small); + 10934: 6831 ldr r1, [r6, #0] + 10936: 4648 mov r0, r9 + 10938: 3118 adds r1, #24 + 1093a: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_TEXTAREA_PART_PLACEHOLDER); + 1093c: 4620 mov r0, r4 + 1093e: 2104 movs r1, #4 + 10940: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_TEXTAREA_PART_PLACEHOLDER); + 10942: 2104 movs r1, #4 + 10944: 4620 mov r0, r4 + 10946: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->ta_placeholder); + 10948: 6831 ldr r1, [r6, #0] + 1094a: 31b8 adds r1, #184 ; 0xb8 + 1094c: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_TEXTAREA_PART_CURSOR); + 1094e: 4620 mov r0, r4 + 10950: 2103 movs r1, #3 + 10952: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_TEXTAREA_PART_CURSOR); + 10954: 2103 movs r1, #3 + 10956: 4620 mov r0, r4 + 10958: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->ta_cursor); + 1095a: 6831 ldr r1, [r6, #0] + 1095c: 31b4 adds r1, #180 ; 0xb4 + 1095e: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_TEXTAREA_PART_SCROLLBAR); + 10960: 4620 mov r0, r4 + 10962: 2101 movs r1, #1 + 10964: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_TEXTAREA_PART_SCROLLBAR); + 10966: 2101 movs r1, #1 + 10968: 4620 mov r0, r4 + 1096a: 47b8 blx r7 + 1096c: e6f6 b.n 1075c + _lv_style_list_add_style(list, &styles->bg); + 1096e: 4e4f ldr r6, [pc, #316] ; (10aac ) + lv_obj_clean_style_list(obj, LV_SPINBOX_PART_BG); + 10970: f8df 9144 ldr.w r9, [pc, #324] ; 10ab8 + list = lv_obj_get_style_list(obj, LV_SPINBOX_PART_BG); + 10974: f8df 8138 ldr.w r8, [pc, #312] ; 10ab0 + _lv_style_list_add_style(list, &styles->bg); + 10978: 4d4e ldr r5, [pc, #312] ; (10ab4 ) + lv_obj_clean_style_list(obj, LV_SPINBOX_PART_BG); + 1097a: 2100 movs r1, #0 + 1097c: 47c8 blx r9 + list = lv_obj_get_style_list(obj, LV_SPINBOX_PART_BG); + 1097e: 2100 movs r1, #0 + 10980: 4620 mov r0, r4 + 10982: 47c0 blx r8 + _lv_style_list_add_style(list, &styles->bg); + 10984: 6831 ldr r1, [r6, #0] + 10986: 3104 adds r1, #4 + list = lv_obj_get_style_list(obj, LV_SPINBOX_PART_BG); + 10988: 4607 mov r7, r0 + _lv_style_list_add_style(list, &styles->bg); + 1098a: 47a8 blx r5 + _lv_style_list_add_style(list, &styles->pad_small); + 1098c: 6831 ldr r1, [r6, #0] + 1098e: 4638 mov r0, r7 + 10990: 3118 adds r1, #24 + 10992: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_SPINBOX_PART_CURSOR); + 10994: 2103 movs r1, #3 + 10996: 4620 mov r0, r4 + 10998: 47c8 blx r9 + list = lv_obj_get_style_list(obj, LV_SPINBOX_PART_CURSOR); + 1099a: 2103 movs r1, #3 + 1099c: 4620 mov r0, r4 + 1099e: 47c0 blx r8 + _lv_style_list_add_style(list, &styles->spinbox_cursor); + 109a0: 6831 ldr r1, [r6, #0] + 109a2: 3198 adds r1, #152 ; 0x98 + 109a4: e537 b.n 10416 + lv_obj_clean_style_list(obj, LV_BTN_PART_MAIN); + 109a6: 4b44 ldr r3, [pc, #272] ; (10ab8 ) + _lv_style_list_add_style(list, &styles->bg); + 109a8: 4f40 ldr r7, [pc, #256] ; (10aac ) + 109aa: 4e42 ldr r6, [pc, #264] ; (10ab4 ) + lv_obj_clean_style_list(obj, LV_BTN_PART_MAIN); + 109ac: 2100 movs r1, #0 + 109ae: 4798 blx r3 + list = lv_obj_get_style_list(obj, LV_BTN_PART_MAIN); + 109b0: 4b3f ldr r3, [pc, #252] ; (10ab0 ) + 109b2: 2100 movs r1, #0 + 109b4: 4620 mov r0, r4 + 109b6: 4798 blx r3 + _lv_style_list_add_style(list, &styles->bg); + 109b8: 6839 ldr r1, [r7, #0] + 109ba: 3104 adds r1, #4 + list = lv_obj_get_style_list(obj, LV_BTN_PART_MAIN); + 109bc: 4605 mov r5, r0 + _lv_style_list_add_style(list, &styles->bg); + 109be: 47b0 blx r6 + _lv_style_list_add_style(list, &styles->bg_click); + 109c0: 6839 ldr r1, [r7, #0] + 109c2: 3108 adds r1, #8 + 109c4: e5f1 b.n 105aa + lv_obj_clean_style_list(obj, LV_CALENDAR_PART_BG); + 109c6: f8df 80f0 ldr.w r8, [pc, #240] ; 10ab8 + _lv_style_list_add_style(list, &styles->bg); + 109ca: 4e38 ldr r6, [pc, #224] ; (10aac ) + list = lv_obj_get_style_list(obj, LV_CALENDAR_PART_BG); + 109cc: 4f38 ldr r7, [pc, #224] ; (10ab0 ) + _lv_style_list_add_style(list, &styles->bg); + 109ce: 4d39 ldr r5, [pc, #228] ; (10ab4 ) + lv_obj_clean_style_list(obj, LV_CALENDAR_PART_BG); + 109d0: 2100 movs r1, #0 + 109d2: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_CALENDAR_PART_BG); + 109d4: 2100 movs r1, #0 + 109d6: 4620 mov r0, r4 + 109d8: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->bg); + 109da: 6831 ldr r1, [r6, #0] + 109dc: 3104 adds r1, #4 + 109de: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_CALENDAR_PART_DATE); + 109e0: 2103 movs r1, #3 + 109e2: 4620 mov r0, r4 + 109e4: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_CALENDAR_PART_DATE); + 109e6: 2103 movs r1, #3 + 109e8: 4620 mov r0, r4 + 109ea: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->calendar_date_nums); + 109ec: 6831 ldr r1, [r6, #0] + 109ee: 312c adds r1, #44 ; 0x2c + 109f0: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_CALENDAR_PART_HEADER); + 109f2: 2101 movs r1, #1 + 109f4: 4620 mov r0, r4 + 109f6: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_CALENDAR_PART_HEADER); + 109f8: 2101 movs r1, #1 + 109fa: 4620 mov r0, r4 + 109fc: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->calendar_header); + 109fe: 6831 ldr r1, [r6, #0] + 10a00: 3130 adds r1, #48 ; 0x30 + 10a02: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_CALENDAR_PART_DAY_NAMES); + 10a04: 2102 movs r1, #2 + 10a06: 4620 mov r0, r4 + 10a08: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_CALENDAR_PART_DAY_NAMES); + 10a0a: 2102 movs r1, #2 + 10a0c: 4620 mov r0, r4 + 10a0e: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->calendar_daynames); + 10a10: 6831 ldr r1, [r6, #0] + 10a12: 3134 adds r1, #52 ; 0x34 + 10a14: e4ff b.n 10416 + lv_obj_clean_style_list(obj, LV_CPICKER_PART_MAIN); + 10a16: f8df 80a0 ldr.w r8, [pc, #160] ; 10ab8 + _lv_style_list_add_style(list, &styles->cpicker_bg); + 10a1a: 4e24 ldr r6, [pc, #144] ; (10aac ) + list = lv_obj_get_style_list(obj, LV_CPICKER_PART_MAIN); + 10a1c: 4f24 ldr r7, [pc, #144] ; (10ab0 ) + _lv_style_list_add_style(list, &styles->cpicker_bg); + 10a1e: 4d25 ldr r5, [pc, #148] ; (10ab4 ) + lv_obj_clean_style_list(obj, LV_CPICKER_PART_MAIN); + 10a20: 2100 movs r1, #0 + 10a22: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_CPICKER_PART_MAIN); + 10a24: 2100 movs r1, #0 + 10a26: 4620 mov r0, r4 + 10a28: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->cpicker_bg); + 10a2a: 6831 ldr r1, [r6, #0] + 10a2c: 3138 adds r1, #56 ; 0x38 + 10a2e: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_CPICKER_PART_KNOB); + 10a30: 2101 movs r1, #1 + 10a32: 4620 mov r0, r4 + 10a34: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_CPICKER_PART_KNOB); + 10a36: 2101 movs r1, #1 + 10a38: 4620 mov r0, r4 + 10a3a: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->cpicker_indic); + 10a3c: 6831 ldr r1, [r6, #0] + 10a3e: 313c adds r1, #60 ; 0x3c + 10a40: e4e9 b.n 10416 + lv_obj_clean_style_list(obj, LV_LINEMETER_PART_MAIN); + 10a42: 4b1d ldr r3, [pc, #116] ; (10ab8 ) + _lv_style_list_add_style(list, &styles->bg); + 10a44: 4f19 ldr r7, [pc, #100] ; (10aac ) + 10a46: 4e1b ldr r6, [pc, #108] ; (10ab4 ) + lv_obj_clean_style_list(obj, LV_LINEMETER_PART_MAIN); + 10a48: 2100 movs r1, #0 + 10a4a: 4798 blx r3 + list = lv_obj_get_style_list(obj, LV_LINEMETER_PART_MAIN); + 10a4c: 4b18 ldr r3, [pc, #96] ; (10ab0 ) + 10a4e: 2100 movs r1, #0 + 10a50: 4620 mov r0, r4 + 10a52: 4798 blx r3 + _lv_style_list_add_style(list, &styles->bg); + 10a54: 6839 ldr r1, [r7, #0] + 10a56: 3104 adds r1, #4 + list = lv_obj_get_style_list(obj, LV_LINEMETER_PART_MAIN); + 10a58: 4605 mov r5, r0 + _lv_style_list_add_style(list, &styles->bg); + 10a5a: 47b0 blx r6 + _lv_style_list_add_style(list, &styles->lmeter); + 10a5c: 6839 ldr r1, [r7, #0] + 10a5e: 3170 adds r1, #112 ; 0x70 + 10a60: e5a3 b.n 105aa + _lv_style_list_add_style(list, &styles->bg); + 10a62: 4e12 ldr r6, [pc, #72] ; (10aac ) + lv_obj_clean_style_list(obj, LV_GAUGE_PART_MAIN); + 10a64: f8df 8050 ldr.w r8, [pc, #80] ; 10ab8 + list = lv_obj_get_style_list(obj, LV_GAUGE_PART_MAIN); + 10a68: 4f11 ldr r7, [pc, #68] ; (10ab0 ) + _lv_style_list_add_style(list, &styles->bg); + 10a6a: 4d12 ldr r5, [pc, #72] ; (10ab4 ) + lv_obj_clean_style_list(obj, LV_GAUGE_PART_MAIN); + 10a6c: 2100 movs r1, #0 + 10a6e: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_GAUGE_PART_MAIN); + 10a70: 2100 movs r1, #0 + 10a72: 4620 mov r0, r4 + 10a74: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->bg); + 10a76: 6831 ldr r1, [r6, #0] + 10a78: 3104 adds r1, #4 + list = lv_obj_get_style_list(obj, LV_GAUGE_PART_MAIN); + 10a7a: 4681 mov r9, r0 + _lv_style_list_add_style(list, &styles->bg); + 10a7c: 47a8 blx r5 + _lv_style_list_add_style(list, &styles->gauge_main); + 10a7e: 6831 ldr r1, [r6, #0] + 10a80: 4648 mov r0, r9 + 10a82: 315c adds r1, #92 ; 0x5c + 10a84: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_GAUGE_PART_MAJOR); + 10a86: 2101 movs r1, #1 + 10a88: 4620 mov r0, r4 + 10a8a: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_GAUGE_PART_MAJOR); + 10a8c: 2101 movs r1, #1 + 10a8e: 4620 mov r0, r4 + 10a90: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->gauge_strong); + 10a92: 6831 ldr r1, [r6, #0] + 10a94: 3160 adds r1, #96 ; 0x60 + 10a96: 47a8 blx r5 + lv_obj_clean_style_list(obj, LV_GAUGE_PART_NEEDLE); + 10a98: 2102 movs r1, #2 + 10a9a: 4620 mov r0, r4 + 10a9c: 47c0 blx r8 + list = lv_obj_get_style_list(obj, LV_GAUGE_PART_NEEDLE); + 10a9e: 2102 movs r1, #2 + 10aa0: 4620 mov r0, r4 + 10aa2: 47b8 blx r7 + _lv_style_list_add_style(list, &styles->gauge_needle); + 10aa4: 6831 ldr r1, [r6, #0] + 10aa6: 3164 adds r1, #100 ; 0x64 + 10aa8: e4b5 b.n 10416 + 10aaa: bf00 nop + 10aac: 2000c7d4 .word 0x2000c7d4 + 10ab0: 0000248d .word 0x0000248d + 10ab4: 00005619 .word 0x00005619 + 10ab8: 00002549 .word 0x00002549 + +00010abc : + * STATIC FUNCTIONS + **********************/ + +static void style_init_reset(lv_style_t * style) +{ + if(inited) lv_style_reset(style); + 10abc: 4b03 ldr r3, [pc, #12] ; (10acc ) + 10abe: 791b ldrb r3, [r3, #4] + 10ac0: b10b cbz r3, 10ac6 + 10ac2: 4b03 ldr r3, [pc, #12] ; (10ad0 ) + else lv_style_init(style); + 10ac4: 4718 bx r3 + 10ac6: 4b03 ldr r3, [pc, #12] ; (10ad4 ) + 10ac8: e7fc b.n 10ac4 + 10aca: bf00 nop + 10acc: 2000c7d4 .word 0x2000c7d4 + 10ad0: 00005795 .word 0x00005795 + 10ad4: 00005531 .word 0x00005531 + +00010ad8 : +{ + 10ad8: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + style_init_reset(&styles->sw_knob); + 10adc: 4d3a ldr r5, [pc, #232] ; (10bc8 ) + 10ade: 4b3b ldr r3, [pc, #236] ; (10bcc ) + 10ae0: 6828 ldr r0, [r5, #0] +#define _LV_OBJ_STYLE_SET_GET_DECLARE(prop_name, func_name, value_type, style_type, scalar) \ + _OBJ_GET_STYLE_##scalar(prop_name, func_name, value_type, style_type) \ + _OBJ_SET_STYLE_LOCAL_##scalar(prop_name, func_name, value_type, style_type) \ + _OBJ_SET_STYLE_##scalar(prop_name, func_name, value_type, style_type) + +_LV_OBJ_STYLE_SET_GET_DECLARE(RADIUS, radius, lv_style_int_t, _int, scalar) + 10ae2: 4e3b ldr r6, [pc, #236] ; (10bd0 ) + lv_style_set_pad_top(&styles->sw_knob, LV_STATE_DEFAULT, - LV_DPX(4)); + 10ae4: 4c3b ldr r4, [pc, #236] ; (10bd4 ) + style_init_reset(&styles->sw_knob); + 10ae6: 309c adds r0, #156 ; 0x9c + 10ae8: 4798 blx r3 + lv_style_set_bg_opa(&styles->sw_knob, LV_STATE_DEFAULT, LV_OPA_COVER); + 10aea: 6828 ldr r0, [r5, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_MAIN_STOP, bg_main_stop, lv_style_int_t, _int, scalar) +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_GRAD_STOP, bg_grad_stop, lv_style_int_t, _int, scalar) +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_GRAD_DIR, bg_grad_dir, lv_grad_dir_t, _int, scalar) +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_COLOR, bg_color, lv_color_t, _color, nonscalar) +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_GRAD_COLOR, bg_grad_color, lv_color_t, _color, nonscalar) +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_OPA, bg_opa, lv_opa_t, _opa, scalar) + 10aec: 4b3a ldr r3, [pc, #232] ; (10bd8 ) + 10aee: 22ff movs r2, #255 ; 0xff + 10af0: 212c movs r1, #44 ; 0x2c + 10af2: 309c adds r0, #156 ; 0x9c + 10af4: 4798 blx r3 + lv_style_set_bg_color(&styles->sw_knob, LV_STATE_DEFAULT, LV_COLOR_WHITE); + 10af6: 6828 ldr r0, [r5, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_COLOR, bg_color, lv_color_t, _color, nonscalar) + 10af8: 4b38 ldr r3, [pc, #224] ; (10bdc ) + 10afa: 2129 movs r1, #41 ; 0x29 + 10afc: 881a ldrh r2, [r3, #0] + 10afe: 4b38 ldr r3, [pc, #224] ; (10be0 ) + 10b00: 309c adds r0, #156 ; 0x9c + 10b02: 4798 blx r3 + lv_style_set_radius(&styles->sw_knob, LV_STATE_DEFAULT, LV_RADIUS_CIRCLE); + 10b04: 6828 ldr r0, [r5, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(RADIUS, radius, lv_style_int_t, _int, scalar) + 10b06: f647 72ff movw r2, #32767 ; 0x7fff + 10b0a: 2101 movs r1, #1 + 10b0c: 309c adds r0, #156 ; 0x9c + 10b0e: 47b0 blx r6 + lv_style_set_pad_top(&styles->sw_knob, LV_STATE_DEFAULT, - LV_DPX(4)); + 10b10: 2000 movs r0, #0 + 10b12: 682f ldr r7, [r5, #0] + 10b14: 47a0 blx r4 + 10b16: 283b cmp r0, #59 ; 0x3b + 10b18: f107 079c add.w r7, r7, #156 ; 0x9c + 10b1c: dd47 ble.n 10bae + 10b1e: 2000 movs r0, #0 + 10b20: 47a0 blx r4 + 10b22: f06f 0327 mvn.w r3, #39 ; 0x27 + 10b26: f100 0214 add.w r2, r0, #20 + 10b2a: fb92 f2f3 sdiv r2, r2, r3 + 10b2e: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_TOP, pad_top, lv_style_int_t, _int, scalar) + 10b30: 4638 mov r0, r7 + 10b32: 2110 movs r1, #16 + 10b34: 47b0 blx r6 + lv_style_set_pad_bottom(&styles->sw_knob, LV_STATE_DEFAULT, - LV_DPX(4)); + 10b36: 2000 movs r0, #0 + 10b38: 682f ldr r7, [r5, #0] + 10b3a: 47a0 blx r4 + 10b3c: 283b cmp r0, #59 ; 0x3b + 10b3e: f107 079c add.w r7, r7, #156 ; 0x9c + 10b42: dd37 ble.n 10bb4 + 10b44: 2000 movs r0, #0 + 10b46: 47a0 blx r4 + 10b48: f06f 0327 mvn.w r3, #39 ; 0x27 + 10b4c: f100 0214 add.w r2, r0, #20 + 10b50: fb92 f2f3 sdiv r2, r2, r3 + 10b54: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_BOTTOM, pad_bottom, lv_style_int_t, _int, scalar) + 10b56: 4638 mov r0, r7 + 10b58: 2111 movs r1, #17 + 10b5a: 47b0 blx r6 + lv_style_set_pad_left(&styles->sw_knob, LV_STATE_DEFAULT, - LV_DPX(4)); + 10b5c: 2000 movs r0, #0 + 10b5e: 682f ldr r7, [r5, #0] + 10b60: 47a0 blx r4 + 10b62: 283b cmp r0, #59 ; 0x3b + 10b64: f107 079c add.w r7, r7, #156 ; 0x9c + 10b68: dd27 ble.n 10bba + 10b6a: 2000 movs r0, #0 + 10b6c: 47a0 blx r4 + 10b6e: f06f 0327 mvn.w r3, #39 ; 0x27 + 10b72: f100 0214 add.w r2, r0, #20 + 10b76: fb92 f2f3 sdiv r2, r2, r3 + 10b7a: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_LEFT, pad_left, lv_style_int_t, _int, scalar) + 10b7c: 2112 movs r1, #18 + 10b7e: 4638 mov r0, r7 + 10b80: 47b0 blx r6 + lv_style_set_pad_right(&styles->sw_knob, LV_STATE_DEFAULT, - LV_DPX(4)); + 10b82: 2000 movs r0, #0 + 10b84: 682d ldr r5, [r5, #0] + 10b86: 47a0 blx r4 + 10b88: 283b cmp r0, #59 ; 0x3b + 10b8a: f105 059c add.w r5, r5, #156 ; 0x9c + 10b8e: dd17 ble.n 10bc0 + 10b90: 2000 movs r0, #0 + 10b92: 47a0 blx r4 + 10b94: f06f 0327 mvn.w r3, #39 ; 0x27 + 10b98: f100 0214 add.w r2, r0, #20 + 10b9c: fb92 f2f3 sdiv r2, r2, r3 + 10ba0: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_RIGHT, pad_right, lv_style_int_t, _int, scalar) + 10ba2: 4628 mov r0, r5 + 10ba4: 4633 mov r3, r6 + 10ba6: 2113 movs r1, #19 +} + 10ba8: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} + 10bac: 4718 bx r3 + lv_style_set_pad_top(&styles->sw_knob, LV_STATE_DEFAULT, - LV_DPX(4)); + 10bae: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 10bb2: e7bd b.n 10b30 + lv_style_set_pad_bottom(&styles->sw_knob, LV_STATE_DEFAULT, - LV_DPX(4)); + 10bb4: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 10bb8: e7cd b.n 10b56 + lv_style_set_pad_left(&styles->sw_knob, LV_STATE_DEFAULT, - LV_DPX(4)); + 10bba: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 10bbe: e7dd b.n 10b7c + lv_style_set_pad_right(&styles->sw_knob, LV_STATE_DEFAULT, - LV_DPX(4)); + 10bc0: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff + 10bc4: e7ed b.n 10ba2 + 10bc6: bf00 nop + 10bc8: 2000c7d4 .word 0x2000c7d4 + 10bcc: 00010abd .word 0x00010abd + 10bd0: 00005879 .word 0x00005879 + 10bd4: 0000d951 .word 0x0000d951 + 10bd8: 00005a19 .word 0x00005a19 + 10bdc: 00024272 .word 0x00024272 + 10be0: 00005949 .word 0x00005949 + +00010be4 : +{ + 10be4: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + style_init_reset(&styles->lmeter); + 10be8: 4d6b ldr r5, [pc, #428] ; (10d98 ) + 10bea: 4b6c ldr r3, [pc, #432] ; (10d9c ) + 10bec: 6828 ldr r0, [r5, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(RADIUS, radius, lv_style_int_t, _int, scalar) + 10bee: 4e6c ldr r6, [pc, #432] ; (10da0 ) + lv_style_set_pad_left(&styles->lmeter, LV_STATE_DEFAULT, LV_DPX(20)); + 10bf0: 4c6c ldr r4, [pc, #432] ; (10da4 ) + style_init_reset(&styles->lmeter); + 10bf2: 3070 adds r0, #112 ; 0x70 + 10bf4: 4798 blx r3 + lv_style_set_radius(&styles->lmeter, LV_STATE_DEFAULT, LV_RADIUS_CIRCLE); + 10bf6: 6828 ldr r0, [r5, #0] + 10bf8: f647 72ff movw r2, #32767 ; 0x7fff + 10bfc: 2101 movs r1, #1 + 10bfe: 3070 adds r0, #112 ; 0x70 + 10c00: 47b0 blx r6 + lv_style_set_pad_left(&styles->lmeter, LV_STATE_DEFAULT, LV_DPX(20)); + 10c02: 2000 movs r0, #0 + 10c04: 682f ldr r7, [r5, #0] + 10c06: 47a0 blx r4 + 10c08: eb00 0080 add.w r0, r0, r0, lsl #2 + 10c0c: 0080 lsls r0, r0, #2 + 10c0e: 28ef cmp r0, #239 ; 0xef + 10c10: f107 0770 add.w r7, r7, #112 ; 0x70 + 10c14: f340 80b2 ble.w 10d7c + 10c18: 2000 movs r0, #0 + 10c1a: 47a0 blx r4 + 10c1c: 2314 movs r3, #20 + 10c1e: 2250 movs r2, #80 ; 0x50 + 10c20: fb00 2203 mla r2, r0, r3, r2 + 10c24: 23a0 movs r3, #160 ; 0xa0 + 10c26: fb92 f2f3 sdiv r2, r2, r3 + 10c2a: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_LEFT, pad_left, lv_style_int_t, _int, scalar) + 10c2c: 4638 mov r0, r7 + 10c2e: 2112 movs r1, #18 + 10c30: 47b0 blx r6 + lv_style_set_pad_right(&styles->lmeter, LV_STATE_DEFAULT, LV_DPX(20)); + 10c32: 2000 movs r0, #0 + 10c34: 682f ldr r7, [r5, #0] + 10c36: 47a0 blx r4 + 10c38: eb00 0080 add.w r0, r0, r0, lsl #2 + 10c3c: 0080 lsls r0, r0, #2 + 10c3e: 28ef cmp r0, #239 ; 0xef + 10c40: f107 0770 add.w r7, r7, #112 ; 0x70 + 10c44: f340 809c ble.w 10d80 + 10c48: 2000 movs r0, #0 + 10c4a: 47a0 blx r4 + 10c4c: 2314 movs r3, #20 + 10c4e: 2250 movs r2, #80 ; 0x50 + 10c50: fb00 2203 mla r2, r0, r3, r2 + 10c54: 23a0 movs r3, #160 ; 0xa0 + 10c56: fb92 f2f3 sdiv r2, r2, r3 + 10c5a: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_RIGHT, pad_right, lv_style_int_t, _int, scalar) + 10c5c: 4638 mov r0, r7 + 10c5e: 2113 movs r1, #19 + 10c60: 47b0 blx r6 + lv_style_set_pad_top(&styles->lmeter, LV_STATE_DEFAULT, LV_DPX(20)); + 10c62: 2000 movs r0, #0 + 10c64: 682f ldr r7, [r5, #0] + 10c66: 47a0 blx r4 + 10c68: eb00 0080 add.w r0, r0, r0, lsl #2 + 10c6c: 0080 lsls r0, r0, #2 + 10c6e: 28ef cmp r0, #239 ; 0xef + 10c70: f107 0770 add.w r7, r7, #112 ; 0x70 + 10c74: f340 8086 ble.w 10d84 + 10c78: 2000 movs r0, #0 + 10c7a: 47a0 blx r4 + 10c7c: 2314 movs r3, #20 + 10c7e: 2250 movs r2, #80 ; 0x50 + 10c80: fb00 2203 mla r2, r0, r3, r2 + 10c84: 23a0 movs r3, #160 ; 0xa0 + 10c86: fb92 f2f3 sdiv r2, r2, r3 + 10c8a: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_TOP, pad_top, lv_style_int_t, _int, scalar) + 10c8c: 4638 mov r0, r7 + 10c8e: 2110 movs r1, #16 + 10c90: 47b0 blx r6 + lv_style_set_pad_inner(&styles->lmeter, LV_STATE_DEFAULT, LV_DPX(30)); + 10c92: 2000 movs r0, #0 + 10c94: 682f ldr r7, [r5, #0] + 10c96: 47a0 blx r4 + 10c98: ebc0 1000 rsb r0, r0, r0, lsl #4 + 10c9c: 0040 lsls r0, r0, #1 + 10c9e: 28ef cmp r0, #239 ; 0xef + 10ca0: f107 0770 add.w r7, r7, #112 ; 0x70 + 10ca4: dd70 ble.n 10d88 + 10ca6: 2000 movs r0, #0 + 10ca8: 47a0 blx r4 + 10caa: 231e movs r3, #30 + 10cac: 2250 movs r2, #80 ; 0x50 + 10cae: fb00 2203 mla r2, r0, r3, r2 + 10cb2: 23a0 movs r3, #160 ; 0xa0 + 10cb4: fb92 f2f3 sdiv r2, r2, r3 + 10cb8: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_INNER, pad_inner, lv_style_int_t, _int, scalar) + 10cba: 4638 mov r0, r7 + 10cbc: 2114 movs r1, #20 + 10cbe: 47b0 blx r6 + lv_style_set_scale_width(&styles->lmeter, LV_STATE_DEFAULT, LV_DPX(25)); + 10cc0: 2000 movs r0, #0 + 10cc2: 682f ldr r7, [r5, #0] + 10cc4: 47a0 blx r4 + 10cc6: eb00 0080 add.w r0, r0, r0, lsl #2 + 10cca: eb00 0080 add.w r0, r0, r0, lsl #2 + 10cce: 28ef cmp r0, #239 ; 0xef + 10cd0: f107 0770 add.w r7, r7, #112 ; 0x70 + 10cd4: dd5a ble.n 10d8c + 10cd6: 2000 movs r0, #0 + 10cd8: 47a0 blx r4 + 10cda: 2319 movs r3, #25 + 10cdc: 2250 movs r2, #80 ; 0x50 + 10cde: fb00 2203 mla r2, r0, r3, r2 + 10ce2: 23a0 movs r3, #160 ; 0xa0 + 10ce4: fb92 f2f3 sdiv r2, r2, r3 + 10ce8: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSITION_PATH, transition_path, lv_anim_path_t *, _ptr, scalar) +#else +/*For compatibility*/ +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSITION_PATH, transition_path, const void *, _ptr, scalar) +#endif +_LV_OBJ_STYLE_SET_GET_DECLARE(SCALE_WIDTH, scale_width, lv_style_int_t, _int, scalar) + 10cea: 4638 mov r0, r7 + 10cec: 21c0 movs r1, #192 ; 0xc0 + 10cee: 47b0 blx r6 + lv_style_set_line_color(&styles->lmeter, LV_STATE_DEFAULT, theme.color_primary); + 10cf0: 6828 ldr r0, [r5, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(LINE_COLOR, line_color, lv_color_t, _color, nonscalar) + 10cf2: 4f2d ldr r7, [pc, #180] ; (10da8 ) + 10cf4: 89aa ldrh r2, [r5, #12] + 10cf6: 2199 movs r1, #153 ; 0x99 + 10cf8: 3070 adds r0, #112 ; 0x70 + 10cfa: 47b8 blx r7 + lv_style_set_scale_grad_color(&styles->lmeter, LV_STATE_DEFAULT, theme.color_primary); + 10cfc: 6828 ldr r0, [r5, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(SCALE_BORDER_WIDTH, scale_border_width, lv_style_int_t, _int, scalar) +_LV_OBJ_STYLE_SET_GET_DECLARE(SCALE_END_BORDER_WIDTH, scale_end_border_width, lv_style_int_t, _int, scalar) +_LV_OBJ_STYLE_SET_GET_DECLARE(SCALE_END_LINE_WIDTH, scale_end_line_width, lv_style_int_t, _int, scalar) +_LV_OBJ_STYLE_SET_GET_DECLARE(SCALE_GRAD_COLOR, scale_grad_color, lv_color_t, _color, nonscalar) + 10cfe: 89aa ldrh r2, [r5, #12] + 10d00: 21c9 movs r1, #201 ; 0xc9 + 10d02: 3070 adds r0, #112 ; 0x70 + 10d04: 47b8 blx r7 + lv_style_set_scale_end_color(&styles->lmeter, LV_STATE_DEFAULT, lv_color_hex3(0x888)); + 10d06: 6828 ldr r0, [r5, #0] + 10d08: 4b28 ldr r3, [pc, #160] ; (10dac ) + 10d0a: f100 0870 add.w r8, r0, #112 ; 0x70 + 10d0e: f640 0088 movw r0, #2184 ; 0x888 + 10d12: 4798 blx r3 +_LV_OBJ_STYLE_SET_GET_DECLARE(SCALE_END_COLOR, scale_end_color, lv_color_t, _color, nonscalar) + 10d14: 21ca movs r1, #202 ; 0xca + 10d16: 4602 mov r2, r0 + 10d18: 4640 mov r0, r8 + 10d1a: 47b8 blx r7 + lv_style_set_line_width(&styles->lmeter, LV_STATE_DEFAULT, LV_DPX(10)); + 10d1c: 2000 movs r0, #0 + 10d1e: 682f ldr r7, [r5, #0] + 10d20: 47a0 blx r4 + 10d22: eb00 0080 add.w r0, r0, r0, lsl #2 + 10d26: 0040 lsls r0, r0, #1 + 10d28: 28ef cmp r0, #239 ; 0xef + 10d2a: f107 0770 add.w r7, r7, #112 ; 0x70 + 10d2e: dd2f ble.n 10d90 + 10d30: 2000 movs r0, #0 + 10d32: 47a0 blx r4 + 10d34: 230a movs r3, #10 + 10d36: 2250 movs r2, #80 ; 0x50 + 10d38: fb00 2203 mla r2, r0, r3, r2 + 10d3c: 23a0 movs r3, #160 ; 0xa0 + 10d3e: fb92 f2f3 sdiv r2, r2, r3 + 10d42: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(LINE_WIDTH, line_width, lv_style_int_t, _int, scalar) + 10d44: 2190 movs r1, #144 ; 0x90 + 10d46: 4638 mov r0, r7 + 10d48: 47b0 blx r6 + lv_style_set_scale_end_line_width(&styles->lmeter, LV_STATE_DEFAULT, LV_DPX(7)); + 10d4a: 2000 movs r0, #0 + 10d4c: 682d ldr r5, [r5, #0] + 10d4e: 47a0 blx r4 + 10d50: ebc0 00c0 rsb r0, r0, r0, lsl #3 + 10d54: 28ef cmp r0, #239 ; 0xef + 10d56: f105 0570 add.w r5, r5, #112 ; 0x70 + 10d5a: dd1b ble.n 10d94 + 10d5c: 2000 movs r0, #0 + 10d5e: 47a0 blx r4 + 10d60: 2307 movs r3, #7 + 10d62: 2250 movs r2, #80 ; 0x50 + 10d64: fb00 2203 mla r2, r0, r3, r2 + 10d68: 23a0 movs r3, #160 ; 0xa0 + 10d6a: fb92 f2f3 sdiv r2, r2, r3 + 10d6e: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(SCALE_END_LINE_WIDTH, scale_end_line_width, lv_style_int_t, _int, scalar) + 10d70: 4628 mov r0, r5 + 10d72: 4633 mov r3, r6 + 10d74: 21c3 movs r1, #195 ; 0xc3 +} + 10d76: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} + 10d7a: 4718 bx r3 + lv_style_set_pad_left(&styles->lmeter, LV_STATE_DEFAULT, LV_DPX(20)); + 10d7c: 2201 movs r2, #1 + 10d7e: e755 b.n 10c2c + lv_style_set_pad_right(&styles->lmeter, LV_STATE_DEFAULT, LV_DPX(20)); + 10d80: 2201 movs r2, #1 + 10d82: e76b b.n 10c5c + lv_style_set_pad_top(&styles->lmeter, LV_STATE_DEFAULT, LV_DPX(20)); + 10d84: 2201 movs r2, #1 + 10d86: e781 b.n 10c8c + lv_style_set_pad_inner(&styles->lmeter, LV_STATE_DEFAULT, LV_DPX(30)); + 10d88: 2201 movs r2, #1 + 10d8a: e796 b.n 10cba + lv_style_set_scale_width(&styles->lmeter, LV_STATE_DEFAULT, LV_DPX(25)); + 10d8c: 2201 movs r2, #1 + 10d8e: e7ac b.n 10cea + lv_style_set_line_width(&styles->lmeter, LV_STATE_DEFAULT, LV_DPX(10)); + 10d90: 2201 movs r2, #1 + 10d92: e7d7 b.n 10d44 + lv_style_set_scale_end_line_width(&styles->lmeter, LV_STATE_DEFAULT, LV_DPX(7)); + 10d94: 2201 movs r2, #1 + 10d96: e7eb b.n 10d70 + 10d98: 2000c7d4 .word 0x2000c7d4 + 10d9c: 00010abd .word 0x00010abd + 10da0: 00005879 .word 0x00005879 + 10da4: 0000d951 .word 0x0000d951 + 10da8: 00005949 .word 0x00005949 + 10dac: 000102f1 .word 0x000102f1 + +00010db0 : +{ + 10db0: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + style_init_reset(&styles->led); + 10db4: 4c32 ldr r4, [pc, #200] ; (10e80 ) + 10db6: 4b33 ldr r3, [pc, #204] ; (10e84 ) + 10db8: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_OPA, bg_opa, lv_opa_t, _opa, scalar) + 10dba: 4f33 ldr r7, [pc, #204] ; (10e88 ) +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_COLOR, bg_color, lv_color_t, _color, nonscalar) + 10dbc: 4e33 ldr r6, [pc, #204] ; (10e8c ) +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_WIDTH, border_width, lv_style_int_t, _int, scalar) + 10dbe: 4d34 ldr r5, [pc, #208] ; (10e90 ) + 10dc0: 306c adds r0, #108 ; 0x6c + 10dc2: 4798 blx r3 + lv_style_set_bg_opa(&styles->led, LV_STATE_DEFAULT, LV_OPA_COVER); + 10dc4: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_OPA, bg_opa, lv_opa_t, _opa, scalar) + 10dc6: 22ff movs r2, #255 ; 0xff + 10dc8: 212c movs r1, #44 ; 0x2c + 10dca: 306c adds r0, #108 ; 0x6c + 10dcc: 47b8 blx r7 + lv_style_set_bg_color(&styles->led, LV_STATE_DEFAULT, theme.color_primary); + 10dce: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_COLOR, bg_color, lv_color_t, _color, nonscalar) + 10dd0: 89a2 ldrh r2, [r4, #12] + 10dd2: 2129 movs r1, #41 ; 0x29 + 10dd4: 306c adds r0, #108 ; 0x6c + 10dd6: 47b0 blx r6 + lv_style_set_border_width(&styles->led, LV_STATE_DEFAULT, 2); + 10dd8: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_WIDTH, border_width, lv_style_int_t, _int, scalar) + 10dda: 2202 movs r2, #2 + 10ddc: 2130 movs r1, #48 ; 0x30 + 10dde: 306c adds r0, #108 ; 0x6c + 10de0: 47a8 blx r5 + lv_style_set_border_opa(&styles->led, LV_STATE_DEFAULT, LV_OPA_50); + 10de2: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_OPA, border_opa, lv_opa_t, _opa, scalar) + 10de4: 227f movs r2, #127 ; 0x7f + 10de6: 213c movs r1, #60 ; 0x3c + 10de8: 306c adds r0, #108 ; 0x6c + 10dea: 47b8 blx r7 + lv_style_set_border_color(&styles->led, LV_STATE_DEFAULT, lv_color_lighten(theme.color_primary, LV_OPA_30)); + 10dec: 6820 ldr r0, [r4, #0] + 10dee: 4b29 ldr r3, [pc, #164] ; (10e94 ) + 10df0: f100 076c add.w r7, r0, #108 ; 0x6c + 10df4: 214c movs r1, #76 ; 0x4c + 10df6: 89a0 ldrh r0, [r4, #12] + 10df8: 4798 blx r3 +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_COLOR, border_color, lv_color_t, _color, nonscalar) + 10dfa: 2139 movs r1, #57 ; 0x39 + 10dfc: 4602 mov r2, r0 + 10dfe: 4638 mov r0, r7 + 10e00: 47b0 blx r6 + lv_style_set_radius(&styles->led, LV_STATE_DEFAULT, LV_RADIUS_CIRCLE); + 10e02: 6820 ldr r0, [r4, #0] + lv_style_set_shadow_width(&styles->led, LV_STATE_DEFAULT, LV_DPX(15)); + 10e04: 4f24 ldr r7, [pc, #144] ; (10e98 ) +_LV_OBJ_STYLE_SET_GET_DECLARE(RADIUS, radius, lv_style_int_t, _int, scalar) + 10e06: f647 72ff movw r2, #32767 ; 0x7fff + 10e0a: 2101 movs r1, #1 + 10e0c: 306c adds r0, #108 ; 0x6c + 10e0e: 47a8 blx r5 + 10e10: 6823 ldr r3, [r4, #0] + 10e12: 2000 movs r0, #0 + 10e14: f103 086c add.w r8, r3, #108 ; 0x6c + 10e18: 47b8 blx r7 + 10e1a: ebc0 1000 rsb r0, r0, r0, lsl #4 + 10e1e: 28ef cmp r0, #239 ; 0xef + 10e20: dd2a ble.n 10e78 + 10e22: 2000 movs r0, #0 + 10e24: 47b8 blx r7 + 10e26: 230f movs r3, #15 + 10e28: 2250 movs r2, #80 ; 0x50 + 10e2a: fb00 2203 mla r2, r0, r3, r2 + 10e2e: 23a0 movs r3, #160 ; 0xa0 + 10e30: fb92 f2f3 sdiv r2, r2, r3 + 10e34: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(SHADOW_WIDTH, shadow_width, lv_style_int_t, _int, scalar) + 10e36: 2150 movs r1, #80 ; 0x50 + 10e38: 4640 mov r0, r8 + 10e3a: 47a8 blx r5 + lv_style_set_shadow_color(&styles->led, LV_STATE_DEFAULT, theme.color_primary); + 10e3c: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(SHADOW_COLOR, shadow_color, lv_color_t, _color, nonscalar) + 10e3e: 89a2 ldrh r2, [r4, #12] + 10e40: 2159 movs r1, #89 ; 0x59 + 10e42: 306c adds r0, #108 ; 0x6c + 10e44: 47b0 blx r6 + lv_style_set_shadow_spread(&styles->led, LV_STATE_DEFAULT, LV_DPX(5)); + 10e46: 2000 movs r0, #0 + 10e48: 6824 ldr r4, [r4, #0] + 10e4a: 47b8 blx r7 + 10e4c: eb00 0080 add.w r0, r0, r0, lsl #2 + 10e50: 28ef cmp r0, #239 ; 0xef + 10e52: f104 046c add.w r4, r4, #108 ; 0x6c + 10e56: dd11 ble.n 10e7c + 10e58: 2000 movs r0, #0 + 10e5a: 47b8 blx r7 + 10e5c: 2305 movs r3, #5 + 10e5e: 2250 movs r2, #80 ; 0x50 + 10e60: fb00 2203 mla r2, r0, r3, r2 + 10e64: 23a0 movs r3, #160 ; 0xa0 + 10e66: fb92 f2f3 sdiv r2, r2, r3 + 10e6a: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(SHADOW_SPREAD, shadow_spread, lv_style_int_t, _int, scalar) + 10e6c: 4620 mov r0, r4 + 10e6e: 462b mov r3, r5 + 10e70: 2153 movs r1, #83 ; 0x53 +} + 10e72: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} + 10e76: 4718 bx r3 + lv_style_set_shadow_width(&styles->led, LV_STATE_DEFAULT, LV_DPX(15)); + 10e78: 2201 movs r2, #1 + 10e7a: e7dc b.n 10e36 + lv_style_set_shadow_spread(&styles->led, LV_STATE_DEFAULT, LV_DPX(5)); + 10e7c: 2201 movs r2, #1 + 10e7e: e7f5 b.n 10e6c + 10e80: 2000c7d4 .word 0x2000c7d4 + 10e84: 00010abd .word 0x00010abd + 10e88: 00005a19 .word 0x00005a19 + 10e8c: 00005949 .word 0x00005949 + 10e90: 00005879 .word 0x00005879 + 10e94: 0000e34b .word 0x0000e34b + 10e98: 0000d951 .word 0x0000d951 + +00010e9c : + return LV_COLOR_MAKE(r, g, b); + 10e9c: f3c0 2285 ubfx r2, r0, #10, #6 + 10ea0: f3c0 03c4 ubfx r3, r0, #3, #5 + 10ea4: ea43 1342 orr.w r3, r3, r2, lsl #5 + 10ea8: f3c0 40c4 ubfx r0, r0, #19, #5 +} + 10eac: ea43 20c0 orr.w r0, r3, r0, lsl #11 + 10eb0: 4770 bx lr + ... + +00010eb4 : +{ + 10eb4: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + style_init_reset(&styles->bar_bg); + 10eb8: 4c43 ldr r4, [pc, #268] ; (10fc8 ) + 10eba: f8df 9134 ldr.w r9, [pc, #308] ; 10ff0 + 10ebe: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(RADIUS, radius, lv_style_int_t, _int, scalar) + 10ec0: 4e42 ldr r6, [pc, #264] ; (10fcc ) +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_OPA, bg_opa, lv_opa_t, _opa, scalar) + 10ec2: 4f43 ldr r7, [pc, #268] ; (10fd0 ) + 10ec4: f8df 812c ldr.w r8, [pc, #300] ; 10ff4 + 10ec8: 3024 adds r0, #36 ; 0x24 + 10eca: 47c8 blx r9 + lv_style_set_radius(&styles->bar_bg, LV_STATE_DEFAULT, LV_RADIUS_CIRCLE); + 10ecc: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(RADIUS, radius, lv_style_int_t, _int, scalar) + 10ece: f647 72ff movw r2, #32767 ; 0x7fff + 10ed2: 2101 movs r1, #1 + 10ed4: 3024 adds r0, #36 ; 0x24 + 10ed6: 47b0 blx r6 + lv_style_set_bg_opa(&styles->bar_bg, LV_STATE_DEFAULT, LV_OPA_COVER); + 10ed8: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_OPA, bg_opa, lv_opa_t, _opa, scalar) + 10eda: 22ff movs r2, #255 ; 0xff + 10edc: 3024 adds r0, #36 ; 0x24 + 10ede: 212c movs r1, #44 ; 0x2c + 10ee0: 47b8 blx r7 + lv_style_set_bg_color(&styles->bar_bg, LV_STATE_DEFAULT, COLOR_BG_SEC); + 10ee2: 6a23 ldr r3, [r4, #32] + 10ee4: 6825 ldr r5, [r4, #0] + 10ee6: f013 0f02 tst.w r3, #2 + 10eea: bf14 ite ne + 10eec: 4839 ldrne r0, [pc, #228] ; (10fd4 ) + 10eee: 483a ldreq r0, [pc, #232] ; (10fd8 ) + 10ef0: 47c0 blx r8 + 10ef2: 3524 adds r5, #36 ; 0x24 +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_COLOR, bg_color, lv_color_t, _color, nonscalar) + 10ef4: 4602 mov r2, r0 + 10ef6: 2129 movs r1, #41 ; 0x29 + 10ef8: 4628 mov r0, r5 + 10efa: 4d38 ldr r5, [pc, #224] ; (10fdc ) + 10efc: 47a8 blx r5 + lv_style_set_value_color(&styles->bar_bg, LV_STATE_DEFAULT, IS_LIGHT ? lv_color_hex(0x31404f) : LV_COLOR_WHITE); + 10efe: 6823 ldr r3, [r4, #0] + 10f00: f103 0a24 add.w sl, r3, #36 ; 0x24 + 10f04: 6a23 ldr r3, [r4, #32] + 10f06: 079a lsls r2, r3, #30 + 10f08: d558 bpl.n 10fbc + 10f0a: 4835 ldr r0, [pc, #212] ; (10fe0 ) + 10f0c: 47c0 blx r8 + 10f0e: 4602 mov r2, r0 +_LV_OBJ_STYLE_SET_GET_DECLARE(VALUE_COLOR, value_color, lv_color_t, _color, nonscalar) + 10f10: 2179 movs r1, #121 ; 0x79 + 10f12: 4650 mov r0, sl + 10f14: 47a8 blx r5 + lv_style_set_outline_color(&styles->bar_bg, LV_STATE_DEFAULT, theme.color_primary); + 10f16: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(OUTLINE_COLOR, outline_color, lv_color_t, _color, nonscalar) + 10f18: 89a2 ldrh r2, [r4, #12] + 10f1a: 2149 movs r1, #73 ; 0x49 + 10f1c: 3024 adds r0, #36 ; 0x24 + 10f1e: 47a8 blx r5 + lv_style_set_outline_color(&styles->bar_bg, LV_STATE_EDITED, theme.color_secondary); + 10f20: 6820 ldr r0, [r4, #0] + 10f22: 89e2 ldrh r2, [r4, #14] + 10f24: f240 4149 movw r1, #1097 ; 0x449 + 10f28: 3024 adds r0, #36 ; 0x24 + 10f2a: 47a8 blx r5 + lv_style_set_outline_opa(&styles->bar_bg, LV_STATE_DEFAULT, LV_OPA_TRANSP); + 10f2c: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(OUTLINE_OPA, outline_opa, lv_opa_t, _opa, scalar) + 10f2e: 2200 movs r2, #0 + 10f30: 214c movs r1, #76 ; 0x4c + 10f32: 3024 adds r0, #36 ; 0x24 + 10f34: 47b8 blx r7 + lv_style_set_outline_opa(&styles->bar_bg, LV_STATE_FOCUSED, LV_OPA_50); + 10f36: 6820 ldr r0, [r4, #0] + 10f38: 227f movs r2, #127 ; 0x7f + 10f3a: f44f 7113 mov.w r1, #588 ; 0x24c + 10f3e: 3024 adds r0, #36 ; 0x24 + 10f40: 47b8 blx r7 + lv_style_set_outline_width(&styles->bar_bg, LV_STATE_DEFAULT, 3); + 10f42: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(OUTLINE_WIDTH, outline_width, lv_style_int_t, _int, scalar) + 10f44: 2203 movs r2, #3 + 10f46: 2140 movs r1, #64 ; 0x40 + 10f48: 3024 adds r0, #36 ; 0x24 + 10f4a: 47b0 blx r6 + lv_style_set_transition_time(&styles->bar_bg, LV_STATE_DEFAULT, TRANSITION_TIME); + 10f4c: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSITION_TIME, transition_time, lv_style_int_t, _int, scalar) + 10f4e: 2296 movs r2, #150 ; 0x96 + 10f50: 21b0 movs r1, #176 ; 0xb0 + 10f52: 3024 adds r0, #36 ; 0x24 + 10f54: 47b0 blx r6 + lv_style_set_transition_prop_6(&styles->bar_bg, LV_STATE_DEFAULT, LV_STYLE_OUTLINE_OPA); + 10f56: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSITION_PROP_6, transition_prop_6, lv_style_int_t, _int, scalar) + 10f58: 224c movs r2, #76 ; 0x4c + 10f5a: 21b7 movs r1, #183 ; 0xb7 + 10f5c: 3024 adds r0, #36 ; 0x24 + 10f5e: 47b0 blx r6 + style_init_reset(&styles->bar_indic); + 10f60: 6820 ldr r0, [r4, #0] + 10f62: 3028 adds r0, #40 ; 0x28 + 10f64: 47c8 blx r9 + lv_style_set_bg_opa(&styles->bar_indic, LV_STATE_DEFAULT, LV_OPA_COVER); + 10f66: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_OPA, bg_opa, lv_opa_t, _opa, scalar) + 10f68: 22ff movs r2, #255 ; 0xff + 10f6a: 212c movs r1, #44 ; 0x2c + 10f6c: 3028 adds r0, #40 ; 0x28 + 10f6e: 47b8 blx r7 + lv_style_set_radius(&styles->bar_indic, LV_STATE_DEFAULT, LV_RADIUS_CIRCLE); + 10f70: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(RADIUS, radius, lv_style_int_t, _int, scalar) + 10f72: f647 72ff movw r2, #32767 ; 0x7fff + 10f76: 2101 movs r1, #1 + 10f78: 3028 adds r0, #40 ; 0x28 + 10f7a: 47b0 blx r6 + lv_style_set_bg_color(&styles->bar_indic, LV_STATE_DEFAULT, theme.color_primary); + 10f7c: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_COLOR, bg_color, lv_color_t, _color, nonscalar) + 10f7e: 89a2 ldrh r2, [r4, #12] + 10f80: 2129 movs r1, #41 ; 0x29 + 10f82: 3028 adds r0, #40 ; 0x28 + 10f84: 47a8 blx r5 + lv_style_set_bg_color(&styles->bar_indic, LV_STATE_DISABLED, lv_color_hex3(0x888)); + 10f86: 6820 ldr r0, [r4, #0] + 10f88: 4b16 ldr r3, [pc, #88] ; (10fe4 ) + 10f8a: f100 0628 add.w r6, r0, #40 ; 0x28 + 10f8e: f640 0088 movw r0, #2184 ; 0x888 + 10f92: 4798 blx r3 + 10f94: f242 0129 movw r1, #8233 ; 0x2029 + 10f98: 4602 mov r2, r0 + 10f9a: 4630 mov r0, r6 + 10f9c: 47a8 blx r5 + lv_style_set_value_color(&styles->bar_indic, LV_STATE_DEFAULT, IS_LIGHT ? lv_color_hex(0x41404f) : LV_COLOR_WHITE); + 10f9e: 6a23 ldr r3, [r4, #32] + 10fa0: 6820 ldr r0, [r4, #0] + 10fa2: 079b lsls r3, r3, #30 + 10fa4: f100 0628 add.w r6, r0, #40 ; 0x28 + 10fa8: d50b bpl.n 10fc2 + 10faa: 480f ldr r0, [pc, #60] ; (10fe8 ) + 10fac: 47c0 blx r8 + 10fae: 4602 mov r2, r0 +_LV_OBJ_STYLE_SET_GET_DECLARE(VALUE_COLOR, value_color, lv_color_t, _color, nonscalar) + 10fb0: 4630 mov r0, r6 + 10fb2: 462b mov r3, r5 + 10fb4: 2179 movs r1, #121 ; 0x79 +} + 10fb6: e8bd 47f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 10fba: 4718 bx r3 + lv_style_set_value_color(&styles->bar_bg, LV_STATE_DEFAULT, IS_LIGHT ? lv_color_hex(0x31404f) : LV_COLOR_WHITE); + 10fbc: 4b0b ldr r3, [pc, #44] ; (10fec ) + 10fbe: 881a ldrh r2, [r3, #0] + 10fc0: e7a6 b.n 10f10 + lv_style_set_value_color(&styles->bar_indic, LV_STATE_DEFAULT, IS_LIGHT ? lv_color_hex(0x41404f) : LV_COLOR_WHITE); + 10fc2: 4b0a ldr r3, [pc, #40] ; (10fec ) + 10fc4: 881a ldrh r2, [r3, #0] + 10fc6: e7f3 b.n 10fb0 + 10fc8: 2000c7d4 .word 0x2000c7d4 + 10fcc: 00005879 .word 0x00005879 + 10fd0: 00005a19 .word 0x00005a19 + 10fd4: 00d4d7d9 .word 0x00d4d7d9 + 10fd8: 0045494d .word 0x0045494d + 10fdc: 00005949 .word 0x00005949 + 10fe0: 0031404f .word 0x0031404f + 10fe4: 000102f1 .word 0x000102f1 + 10fe8: 0041404f .word 0x0041404f + 10fec: 00024272 .word 0x00024272 + 10ff0: 00010abd .word 0x00010abd + 10ff4: 00010e9d .word 0x00010e9d + +00010ff8 : +{ + 10ff8: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + style_init_reset(&styles->slider_knob); + 10ffc: 4c7d ldr r4, [pc, #500] ; (111f4 ) + 10ffe: 4f7e ldr r7, [pc, #504] ; (111f8 ) + 11000: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_COLOR, bg_color, lv_color_t, _color, nonscalar) + 11002: 4d7e ldr r5, [pc, #504] ; (111fc ) + 11004: 3090 adds r0, #144 ; 0x90 + 11006: 47b8 blx r7 + lv_style_set_bg_opa(&styles->slider_knob, LV_STATE_DEFAULT, LV_OPA_COVER); + 11008: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_OPA, bg_opa, lv_opa_t, _opa, scalar) + 1100a: 4b7d ldr r3, [pc, #500] ; (11200 ) + 1100c: 22ff movs r2, #255 ; 0xff + 1100e: 212c movs r1, #44 ; 0x2c + 11010: 3090 adds r0, #144 ; 0x90 + 11012: 4798 blx r3 + lv_style_set_bg_color(&styles->slider_knob, LV_STATE_DEFAULT, IS_LIGHT ? theme.color_primary : LV_COLOR_WHITE); + 11014: 6a23 ldr r3, [r4, #32] + 11016: 6820 ldr r0, [r4, #0] + 11018: 079a lsls r2, r3, #30 + 1101a: bf56 itet pl + 1101c: 4b79 ldrpl r3, [pc, #484] ; (11204 ) + 1101e: 89a2 ldrhmi r2, [r4, #12] + 11020: 881a ldrhpl r2, [r3, #0] + 11022: 3090 adds r0, #144 ; 0x90 +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_COLOR, bg_color, lv_color_t, _color, nonscalar) + 11024: 2129 movs r1, #41 ; 0x29 + 11026: 47a8 blx r5 + lv_style_set_value_color(&styles->slider_knob, LV_STATE_DEFAULT, IS_LIGHT ? lv_color_hex(0x31404f) : LV_COLOR_WHITE); + 11028: 6a23 ldr r3, [r4, #32] + 1102a: 6826 ldr r6, [r4, #0] + 1102c: 079b lsls r3, r3, #30 + 1102e: f106 0690 add.w r6, r6, #144 ; 0x90 + 11032: f140 80cc bpl.w 111ce + 11036: 4874 ldr r0, [pc, #464] ; (11208 ) + 11038: 4b74 ldr r3, [pc, #464] ; (1120c ) + 1103a: 4798 blx r3 + 1103c: 4602 mov r2, r0 +_LV_OBJ_STYLE_SET_GET_DECLARE(VALUE_COLOR, value_color, lv_color_t, _color, nonscalar) + 1103e: 4630 mov r0, r6 + 11040: 2179 movs r1, #121 ; 0x79 + 11042: 47a8 blx r5 + lv_style_set_radius(&styles->slider_knob, LV_STATE_DEFAULT, LV_RADIUS_CIRCLE); + 11044: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(RADIUS, radius, lv_style_int_t, _int, scalar) + 11046: 4e72 ldr r6, [pc, #456] ; (11210 ) + lv_style_set_pad_left(&styles->slider_knob, LV_STATE_DEFAULT, LV_DPX(7)); + 11048: 4d72 ldr r5, [pc, #456] ; (11214 ) + 1104a: f647 72ff movw r2, #32767 ; 0x7fff + 1104e: 2101 movs r1, #1 + 11050: 3090 adds r0, #144 ; 0x90 + 11052: 47b0 blx r6 + 11054: 6823 ldr r3, [r4, #0] + 11056: 2000 movs r0, #0 + 11058: f103 0890 add.w r8, r3, #144 ; 0x90 + 1105c: 47a8 blx r5 + 1105e: ebc0 00c0 rsb r0, r0, r0, lsl #3 + 11062: 28ef cmp r0, #239 ; 0xef + 11064: f340 80b6 ble.w 111d4 + 11068: 2000 movs r0, #0 + 1106a: 47a8 blx r5 + 1106c: 2307 movs r3, #7 + 1106e: 2250 movs r2, #80 ; 0x50 + 11070: fb00 2203 mla r2, r0, r3, r2 + 11074: 23a0 movs r3, #160 ; 0xa0 + 11076: fb92 f2f3 sdiv r2, r2, r3 + 1107a: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_LEFT, pad_left, lv_style_int_t, _int, scalar) + 1107c: 4640 mov r0, r8 + 1107e: 2112 movs r1, #18 + 11080: 47b0 blx r6 + lv_style_set_pad_right(&styles->slider_knob, LV_STATE_DEFAULT, LV_DPX(7)); + 11082: 6823 ldr r3, [r4, #0] + 11084: 2000 movs r0, #0 + 11086: f103 0890 add.w r8, r3, #144 ; 0x90 + 1108a: 47a8 blx r5 + 1108c: ebc0 00c0 rsb r0, r0, r0, lsl #3 + 11090: 28ef cmp r0, #239 ; 0xef + 11092: f340 80a1 ble.w 111d8 + 11096: 2000 movs r0, #0 + 11098: 47a8 blx r5 + 1109a: 2307 movs r3, #7 + 1109c: 2250 movs r2, #80 ; 0x50 + 1109e: fb00 2203 mla r2, r0, r3, r2 + 110a2: 23a0 movs r3, #160 ; 0xa0 + 110a4: fb92 f2f3 sdiv r2, r2, r3 + 110a8: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_RIGHT, pad_right, lv_style_int_t, _int, scalar) + 110aa: 4640 mov r0, r8 + 110ac: 2113 movs r1, #19 + 110ae: 47b0 blx r6 + lv_style_set_pad_top(&styles->slider_knob, LV_STATE_DEFAULT, LV_DPX(7)); + 110b0: 6823 ldr r3, [r4, #0] + 110b2: 2000 movs r0, #0 + 110b4: f103 0890 add.w r8, r3, #144 ; 0x90 + 110b8: 47a8 blx r5 + 110ba: ebc0 00c0 rsb r0, r0, r0, lsl #3 + 110be: 28ef cmp r0, #239 ; 0xef + 110c0: f340 808c ble.w 111dc + 110c4: 2000 movs r0, #0 + 110c6: 47a8 blx r5 + 110c8: 2307 movs r3, #7 + 110ca: 2250 movs r2, #80 ; 0x50 + 110cc: fb00 2203 mla r2, r0, r3, r2 + 110d0: 23a0 movs r3, #160 ; 0xa0 + 110d2: fb92 f2f3 sdiv r2, r2, r3 + 110d6: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_TOP, pad_top, lv_style_int_t, _int, scalar) + 110d8: 4640 mov r0, r8 + 110da: 2110 movs r1, #16 + 110dc: 47b0 blx r6 + lv_style_set_pad_bottom(&styles->slider_knob, LV_STATE_DEFAULT, LV_DPX(7)); + 110de: 6823 ldr r3, [r4, #0] + 110e0: 2000 movs r0, #0 + 110e2: f103 0890 add.w r8, r3, #144 ; 0x90 + 110e6: 47a8 blx r5 + 110e8: ebc0 00c0 rsb r0, r0, r0, lsl #3 + 110ec: 28ef cmp r0, #239 ; 0xef + 110ee: dd77 ble.n 111e0 + 110f0: 2000 movs r0, #0 + 110f2: 47a8 blx r5 + 110f4: 2307 movs r3, #7 + 110f6: 2250 movs r2, #80 ; 0x50 + 110f8: fb00 2203 mla r2, r0, r3, r2 + 110fc: 23a0 movs r3, #160 ; 0xa0 + 110fe: fb92 f2f3 sdiv r2, r2, r3 + 11102: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_BOTTOM, pad_bottom, lv_style_int_t, _int, scalar) + 11104: 2111 movs r1, #17 + 11106: 4640 mov r0, r8 + 11108: 47b0 blx r6 + style_init_reset(&styles->slider_bg); + 1110a: 6820 ldr r0, [r4, #0] + 1110c: 3094 adds r0, #148 ; 0x94 + 1110e: 47b8 blx r7 + lv_style_set_margin_left(&styles->slider_bg, LV_STATE_DEFAULT, LV_DPX(10)); + 11110: 2000 movs r0, #0 + 11112: 6827 ldr r7, [r4, #0] + 11114: 47a8 blx r5 + 11116: eb00 0080 add.w r0, r0, r0, lsl #2 + 1111a: 0040 lsls r0, r0, #1 + 1111c: 28ef cmp r0, #239 ; 0xef + 1111e: f107 0794 add.w r7, r7, #148 ; 0x94 + 11122: dd5f ble.n 111e4 + 11124: 2000 movs r0, #0 + 11126: 47a8 blx r5 + 11128: 230a movs r3, #10 + 1112a: 2250 movs r2, #80 ; 0x50 + 1112c: fb00 2203 mla r2, r0, r3, r2 + 11130: 23a0 movs r3, #160 ; 0xa0 + 11132: fb92 f2f3 sdiv r2, r2, r3 + 11136: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(MARGIN_LEFT, margin_left, lv_style_int_t, _int, scalar) + 11138: 4638 mov r0, r7 + 1113a: 2117 movs r1, #23 + 1113c: 47b0 blx r6 + lv_style_set_margin_right(&styles->slider_bg, LV_STATE_DEFAULT, LV_DPX(10)); + 1113e: 2000 movs r0, #0 + 11140: 6827 ldr r7, [r4, #0] + 11142: 47a8 blx r5 + 11144: eb00 0080 add.w r0, r0, r0, lsl #2 + 11148: 0040 lsls r0, r0, #1 + 1114a: 28ef cmp r0, #239 ; 0xef + 1114c: f107 0794 add.w r7, r7, #148 ; 0x94 + 11150: dd4a ble.n 111e8 + 11152: 2000 movs r0, #0 + 11154: 47a8 blx r5 + 11156: 230a movs r3, #10 + 11158: 2250 movs r2, #80 ; 0x50 + 1115a: fb00 2203 mla r2, r0, r3, r2 + 1115e: 23a0 movs r3, #160 ; 0xa0 + 11160: fb92 f2f3 sdiv r2, r2, r3 + 11164: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(MARGIN_RIGHT, margin_right, lv_style_int_t, _int, scalar) + 11166: 4638 mov r0, r7 + 11168: 2118 movs r1, #24 + 1116a: 47b0 blx r6 + lv_style_set_margin_top(&styles->slider_bg, LV_STATE_DEFAULT, LV_DPX(10)); + 1116c: 2000 movs r0, #0 + 1116e: 6827 ldr r7, [r4, #0] + 11170: 47a8 blx r5 + 11172: eb00 0080 add.w r0, r0, r0, lsl #2 + 11176: 0040 lsls r0, r0, #1 + 11178: 28ef cmp r0, #239 ; 0xef + 1117a: f107 0794 add.w r7, r7, #148 ; 0x94 + 1117e: dd35 ble.n 111ec + 11180: 2000 movs r0, #0 + 11182: 47a8 blx r5 + 11184: 230a movs r3, #10 + 11186: 2250 movs r2, #80 ; 0x50 + 11188: fb00 2203 mla r2, r0, r3, r2 + 1118c: 23a0 movs r3, #160 ; 0xa0 + 1118e: fb92 f2f3 sdiv r2, r2, r3 + 11192: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(MARGIN_TOP, margin_top, lv_style_int_t, _int, scalar) + 11194: 2115 movs r1, #21 + 11196: 4638 mov r0, r7 + 11198: 47b0 blx r6 + lv_style_set_margin_bottom(&styles->slider_bg, LV_STATE_DEFAULT, LV_DPX(10)); + 1119a: 2000 movs r0, #0 + 1119c: 6824 ldr r4, [r4, #0] + 1119e: 47a8 blx r5 + 111a0: eb00 0080 add.w r0, r0, r0, lsl #2 + 111a4: 0040 lsls r0, r0, #1 + 111a6: 28ef cmp r0, #239 ; 0xef + 111a8: f104 0494 add.w r4, r4, #148 ; 0x94 + 111ac: dd20 ble.n 111f0 + 111ae: 2000 movs r0, #0 + 111b0: 47a8 blx r5 + 111b2: 230a movs r3, #10 + 111b4: 2250 movs r2, #80 ; 0x50 + 111b6: fb00 2203 mla r2, r0, r3, r2 + 111ba: 23a0 movs r3, #160 ; 0xa0 + 111bc: fb92 f2f3 sdiv r2, r2, r3 + 111c0: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(MARGIN_BOTTOM, margin_bottom, lv_style_int_t, _int, scalar) + 111c2: 4620 mov r0, r4 + 111c4: 4633 mov r3, r6 + 111c6: 2116 movs r1, #22 +} + 111c8: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} + 111cc: 4718 bx r3 + lv_style_set_value_color(&styles->slider_knob, LV_STATE_DEFAULT, IS_LIGHT ? lv_color_hex(0x31404f) : LV_COLOR_WHITE); + 111ce: 4b0d ldr r3, [pc, #52] ; (11204 ) + 111d0: 881a ldrh r2, [r3, #0] + 111d2: e734 b.n 1103e + lv_style_set_pad_left(&styles->slider_knob, LV_STATE_DEFAULT, LV_DPX(7)); + 111d4: 2201 movs r2, #1 + 111d6: e751 b.n 1107c + lv_style_set_pad_right(&styles->slider_knob, LV_STATE_DEFAULT, LV_DPX(7)); + 111d8: 2201 movs r2, #1 + 111da: e766 b.n 110aa + lv_style_set_pad_top(&styles->slider_knob, LV_STATE_DEFAULT, LV_DPX(7)); + 111dc: 2201 movs r2, #1 + 111de: e77b b.n 110d8 + lv_style_set_pad_bottom(&styles->slider_knob, LV_STATE_DEFAULT, LV_DPX(7)); + 111e0: 2201 movs r2, #1 + 111e2: e78f b.n 11104 + lv_style_set_margin_left(&styles->slider_bg, LV_STATE_DEFAULT, LV_DPX(10)); + 111e4: 2201 movs r2, #1 + 111e6: e7a7 b.n 11138 + lv_style_set_margin_right(&styles->slider_bg, LV_STATE_DEFAULT, LV_DPX(10)); + 111e8: 2201 movs r2, #1 + 111ea: e7bc b.n 11166 + lv_style_set_margin_top(&styles->slider_bg, LV_STATE_DEFAULT, LV_DPX(10)); + 111ec: 2201 movs r2, #1 + 111ee: e7d1 b.n 11194 + lv_style_set_margin_bottom(&styles->slider_bg, LV_STATE_DEFAULT, LV_DPX(10)); + 111f0: 2201 movs r2, #1 + 111f2: e7e6 b.n 111c2 + 111f4: 2000c7d4 .word 0x2000c7d4 + 111f8: 00010abd .word 0x00010abd + 111fc: 00005949 .word 0x00005949 + 11200: 00005a19 .word 0x00005a19 + 11204: 00024272 .word 0x00024272 + 11208: 0031404f .word 0x0031404f + 1120c: 00010e9d .word 0x00010e9d + 11210: 00005879 .word 0x00005879 + 11214: 0000d951 .word 0x0000d951 + +00011218 : +{ + 11218: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + style_init_reset(&styles->gauge_main); + 1121c: 4cb6 ldr r4, [pc, #728] ; (114f8 ) + 1121e: f8df 82f4 ldr.w r8, [pc, #756] ; 11514 + 11222: 6820 ldr r0, [r4, #0] + lv_style_set_line_color(&styles->gauge_main, LV_STATE_DEFAULT, lv_color_hex3(0x888)); + 11224: f8df 92f0 ldr.w r9, [pc, #752] ; 11518 +_LV_OBJ_STYLE_SET_GET_DECLARE(LINE_COLOR, line_color, lv_color_t, _color, nonscalar) + 11228: 4fb4 ldr r7, [pc, #720] ; (114fc ) + style_init_reset(&styles->gauge_main); + 1122a: 305c adds r0, #92 ; 0x5c + 1122c: 47c0 blx r8 + lv_style_set_line_color(&styles->gauge_main, LV_STATE_DEFAULT, lv_color_hex3(0x888)); + 1122e: 6820 ldr r0, [r4, #0] + 11230: f100 055c add.w r5, r0, #92 ; 0x5c + 11234: f640 0088 movw r0, #2184 ; 0x888 + 11238: 47c8 blx r9 + 1123a: 2199 movs r1, #153 ; 0x99 + 1123c: 4602 mov r2, r0 + 1123e: 4628 mov r0, r5 + 11240: 47b8 blx r7 + lv_style_set_scale_grad_color(&styles->gauge_main, LV_STATE_DEFAULT, lv_color_hex3(0x888)); + 11242: 6820 ldr r0, [r4, #0] + 11244: f100 055c add.w r5, r0, #92 ; 0x5c + 11248: f640 0088 movw r0, #2184 ; 0x888 + 1124c: 47c8 blx r9 +_LV_OBJ_STYLE_SET_GET_DECLARE(SCALE_GRAD_COLOR, scale_grad_color, lv_color_t, _color, nonscalar) + 1124e: 21c9 movs r1, #201 ; 0xc9 + 11250: 4602 mov r2, r0 + 11252: 4628 mov r0, r5 + 11254: 47b8 blx r7 + lv_style_set_scale_end_color(&styles->gauge_main, LV_STATE_DEFAULT, theme.color_primary); + 11256: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(SCALE_END_COLOR, scale_end_color, lv_color_t, _color, nonscalar) + 11258: 89a2 ldrh r2, [r4, #12] + lv_style_set_line_width(&styles->gauge_main, LV_STATE_DEFAULT, LV_DPX(5)); + 1125a: 4da9 ldr r5, [pc, #676] ; (11500 ) + 1125c: 21ca movs r1, #202 ; 0xca + 1125e: 305c adds r0, #92 ; 0x5c + 11260: 47b8 blx r7 + 11262: 2000 movs r0, #0 + 11264: 6826 ldr r6, [r4, #0] + 11266: 47a8 blx r5 + 11268: eb00 0080 add.w r0, r0, r0, lsl #2 + 1126c: 28ef cmp r0, #239 ; 0xef + 1126e: f106 065c add.w r6, r6, #92 ; 0x5c + 11272: f340 818d ble.w 11590 + 11276: 2000 movs r0, #0 + 11278: 47a8 blx r5 + 1127a: 2305 movs r3, #5 + 1127c: 2250 movs r2, #80 ; 0x50 + 1127e: fb00 2203 mla r2, r0, r3, r2 + 11282: 23a0 movs r3, #160 ; 0xa0 + 11284: fb92 f2f3 sdiv r2, r2, r3 + 11288: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(LINE_WIDTH, line_width, lv_style_int_t, _int, scalar) + 1128a: 4630 mov r0, r6 + 1128c: 2190 movs r1, #144 ; 0x90 + 1128e: 4e9d ldr r6, [pc, #628] ; (11504 ) + 11290: 47b0 blx r6 + lv_style_set_scale_end_line_width(&styles->gauge_main, LV_STATE_DEFAULT, LV_DPX(4)); + 11292: 6823 ldr r3, [r4, #0] + 11294: 2000 movs r0, #0 + 11296: f103 0a5c add.w sl, r3, #92 ; 0x5c + 1129a: 47a8 blx r5 + 1129c: 283b cmp r0, #59 ; 0x3b + 1129e: f340 8179 ble.w 11594 + 112a2: 2000 movs r0, #0 + 112a4: 47a8 blx r5 + 112a6: 2328 movs r3, #40 ; 0x28 + 112a8: f100 0214 add.w r2, r0, #20 + 112ac: fb92 f2f3 sdiv r2, r2, r3 + 112b0: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(SCALE_END_LINE_WIDTH, scale_end_line_width, lv_style_int_t, _int, scalar) + 112b2: 4650 mov r0, sl + 112b4: 21c3 movs r1, #195 ; 0xc3 + 112b6: 47b0 blx r6 + lv_style_set_scale_end_border_width(&styles->gauge_main, LV_STATE_DEFAULT, LV_DPX(8)); + 112b8: 6823 ldr r3, [r4, #0] + 112ba: 2000 movs r0, #0 + 112bc: f103 0a5c add.w sl, r3, #92 ; 0x5c + 112c0: 47a8 blx r5 + 112c2: 281d cmp r0, #29 + 112c4: f340 8168 ble.w 11598 + 112c8: 2000 movs r0, #0 + 112ca: 47a8 blx r5 + 112cc: 2314 movs r3, #20 + 112ce: f100 020a add.w r2, r0, #10 + 112d2: fb92 f2f3 sdiv r2, r2, r3 + 112d6: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(SCALE_END_BORDER_WIDTH, scale_end_border_width, lv_style_int_t, _int, scalar) + 112d8: 4650 mov r0, sl + 112da: 21c2 movs r1, #194 ; 0xc2 + 112dc: 47b0 blx r6 + lv_style_set_pad_left(&styles->gauge_main, LV_STATE_DEFAULT, LV_DPX(20)); + 112de: 6823 ldr r3, [r4, #0] + 112e0: 2000 movs r0, #0 + 112e2: f103 0a5c add.w sl, r3, #92 ; 0x5c + 112e6: 47a8 blx r5 + 112e8: eb00 0080 add.w r0, r0, r0, lsl #2 + 112ec: 0080 lsls r0, r0, #2 + 112ee: 28ef cmp r0, #239 ; 0xef + 112f0: f340 8154 ble.w 1159c + 112f4: 2000 movs r0, #0 + 112f6: 47a8 blx r5 + 112f8: 2314 movs r3, #20 + 112fa: 2250 movs r2, #80 ; 0x50 + 112fc: fb00 2203 mla r2, r0, r3, r2 + 11300: 23a0 movs r3, #160 ; 0xa0 + 11302: fb92 f2f3 sdiv r2, r2, r3 + 11306: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_LEFT, pad_left, lv_style_int_t, _int, scalar) + 11308: 4650 mov r0, sl + 1130a: 2112 movs r1, #18 + 1130c: 47b0 blx r6 + lv_style_set_pad_right(&styles->gauge_main, LV_STATE_DEFAULT, LV_DPX(20)); + 1130e: 6823 ldr r3, [r4, #0] + 11310: 2000 movs r0, #0 + 11312: f103 0a5c add.w sl, r3, #92 ; 0x5c + 11316: 47a8 blx r5 + 11318: eb00 0080 add.w r0, r0, r0, lsl #2 + 1131c: 0080 lsls r0, r0, #2 + 1131e: 28ef cmp r0, #239 ; 0xef + 11320: f340 813e ble.w 115a0 + 11324: 2000 movs r0, #0 + 11326: 47a8 blx r5 + 11328: 2314 movs r3, #20 + 1132a: 2250 movs r2, #80 ; 0x50 + 1132c: fb00 2203 mla r2, r0, r3, r2 + 11330: 23a0 movs r3, #160 ; 0xa0 + 11332: fb92 f2f3 sdiv r2, r2, r3 + 11336: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_RIGHT, pad_right, lv_style_int_t, _int, scalar) + 11338: 4650 mov r0, sl + 1133a: 2113 movs r1, #19 + 1133c: 47b0 blx r6 + lv_style_set_pad_top(&styles->gauge_main, LV_STATE_DEFAULT, LV_DPX(20)); + 1133e: 6823 ldr r3, [r4, #0] + 11340: 2000 movs r0, #0 + 11342: f103 0a5c add.w sl, r3, #92 ; 0x5c + 11346: 47a8 blx r5 + 11348: eb00 0080 add.w r0, r0, r0, lsl #2 + 1134c: 0080 lsls r0, r0, #2 + 1134e: 28ef cmp r0, #239 ; 0xef + 11350: f340 8128 ble.w 115a4 + 11354: 2000 movs r0, #0 + 11356: 47a8 blx r5 + 11358: 2314 movs r3, #20 + 1135a: 2250 movs r2, #80 ; 0x50 + 1135c: fb00 2203 mla r2, r0, r3, r2 + 11360: 23a0 movs r3, #160 ; 0xa0 + 11362: fb92 f2f3 sdiv r2, r2, r3 + 11366: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_TOP, pad_top, lv_style_int_t, _int, scalar) + 11368: 4650 mov r0, sl + 1136a: 2110 movs r1, #16 + 1136c: 47b0 blx r6 + lv_style_set_pad_inner(&styles->gauge_main, LV_STATE_DEFAULT, LV_DPX(20)); + 1136e: 6823 ldr r3, [r4, #0] + 11370: 2000 movs r0, #0 + 11372: f103 0a5c add.w sl, r3, #92 ; 0x5c + 11376: 47a8 blx r5 + 11378: eb00 0080 add.w r0, r0, r0, lsl #2 + 1137c: 0080 lsls r0, r0, #2 + 1137e: 28ef cmp r0, #239 ; 0xef + 11380: f340 8112 ble.w 115a8 + 11384: 2000 movs r0, #0 + 11386: 47a8 blx r5 + 11388: 2314 movs r3, #20 + 1138a: 2250 movs r2, #80 ; 0x50 + 1138c: fb00 2203 mla r2, r0, r3, r2 + 11390: 23a0 movs r3, #160 ; 0xa0 + 11392: fb92 f2f3 sdiv r2, r2, r3 + 11396: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_INNER, pad_inner, lv_style_int_t, _int, scalar) + 11398: 4650 mov r0, sl + 1139a: 2114 movs r1, #20 + 1139c: 47b0 blx r6 + lv_style_set_scale_width(&styles->gauge_main, LV_STATE_DEFAULT, LV_DPX(15)); + 1139e: 6823 ldr r3, [r4, #0] + 113a0: 2000 movs r0, #0 + 113a2: f103 0a5c add.w sl, r3, #92 ; 0x5c + 113a6: 47a8 blx r5 + 113a8: ebc0 1000 rsb r0, r0, r0, lsl #4 + 113ac: 28ef cmp r0, #239 ; 0xef + 113ae: f340 80fd ble.w 115ac + 113b2: 2000 movs r0, #0 + 113b4: 47a8 blx r5 + 113b6: 230f movs r3, #15 + 113b8: 2250 movs r2, #80 ; 0x50 + 113ba: fb00 2203 mla r2, r0, r3, r2 + 113be: 23a0 movs r3, #160 ; 0xa0 + 113c0: fb92 f2f3 sdiv r2, r2, r3 + 113c4: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(SCALE_WIDTH, scale_width, lv_style_int_t, _int, scalar) + 113c6: 4650 mov r0, sl + 113c8: 21c0 movs r1, #192 ; 0xc0 + 113ca: 47b0 blx r6 + lv_style_set_radius(&styles->gauge_main, LV_STATE_DEFAULT, LV_RADIUS_CIRCLE); + 113cc: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(RADIUS, radius, lv_style_int_t, _int, scalar) + 113ce: f647 72ff movw r2, #32767 ; 0x7fff + 113d2: 2101 movs r1, #1 + 113d4: 305c adds r0, #92 ; 0x5c + 113d6: 47b0 blx r6 + style_init_reset(&styles->gauge_strong); + 113d8: 6820 ldr r0, [r4, #0] + 113da: 3060 adds r0, #96 ; 0x60 + 113dc: 47c0 blx r8 + lv_style_set_line_color(&styles->gauge_strong, LV_STATE_DEFAULT, lv_color_hex3(0x888)); + 113de: 6820 ldr r0, [r4, #0] + 113e0: f100 0a60 add.w sl, r0, #96 ; 0x60 + 113e4: f640 0088 movw r0, #2184 ; 0x888 + 113e8: 47c8 blx r9 +_LV_OBJ_STYLE_SET_GET_DECLARE(LINE_COLOR, line_color, lv_color_t, _color, nonscalar) + 113ea: 2199 movs r1, #153 ; 0x99 + 113ec: 4602 mov r2, r0 + 113ee: 4650 mov r0, sl + 113f0: 47b8 blx r7 + lv_style_set_scale_grad_color(&styles->gauge_strong, LV_STATE_DEFAULT, lv_color_hex3(0x888)); + 113f2: 6820 ldr r0, [r4, #0] + 113f4: f100 0a60 add.w sl, r0, #96 ; 0x60 + 113f8: f640 0088 movw r0, #2184 ; 0x888 + 113fc: 47c8 blx r9 +_LV_OBJ_STYLE_SET_GET_DECLARE(SCALE_GRAD_COLOR, scale_grad_color, lv_color_t, _color, nonscalar) + 113fe: 21c9 movs r1, #201 ; 0xc9 + 11400: 4602 mov r2, r0 + 11402: 4650 mov r0, sl + 11404: 47b8 blx r7 + lv_style_set_scale_end_color(&styles->gauge_strong, LV_STATE_DEFAULT, theme.color_primary); + 11406: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(SCALE_END_COLOR, scale_end_color, lv_color_t, _color, nonscalar) + 11408: 89a2 ldrh r2, [r4, #12] + 1140a: 21ca movs r1, #202 ; 0xca + 1140c: 3060 adds r0, #96 ; 0x60 + 1140e: 47b8 blx r7 + lv_style_set_line_width(&styles->gauge_strong, LV_STATE_DEFAULT, LV_DPX(8)); + 11410: 6823 ldr r3, [r4, #0] + 11412: 2000 movs r0, #0 + 11414: f103 0960 add.w r9, r3, #96 ; 0x60 + 11418: 47a8 blx r5 + 1141a: 281d cmp r0, #29 + 1141c: f340 80c8 ble.w 115b0 + 11420: 2000 movs r0, #0 + 11422: 47a8 blx r5 + 11424: 2314 movs r3, #20 + 11426: f100 020a add.w r2, r0, #10 + 1142a: fb92 f2f3 sdiv r2, r2, r3 + 1142e: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(LINE_WIDTH, line_width, lv_style_int_t, _int, scalar) + 11430: 4648 mov r0, r9 + 11432: 2190 movs r1, #144 ; 0x90 + 11434: 47b0 blx r6 + lv_style_set_scale_end_line_width(&styles->gauge_strong, LV_STATE_DEFAULT, LV_DPX(8)); + 11436: 6823 ldr r3, [r4, #0] + 11438: 2000 movs r0, #0 + 1143a: f103 0960 add.w r9, r3, #96 ; 0x60 + 1143e: 47a8 blx r5 + 11440: 281d cmp r0, #29 + 11442: f340 80b7 ble.w 115b4 + 11446: 2000 movs r0, #0 + 11448: 47a8 blx r5 + 1144a: 2314 movs r3, #20 + 1144c: f100 020a add.w r2, r0, #10 + 11450: fb92 f2f3 sdiv r2, r2, r3 + 11454: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(SCALE_END_LINE_WIDTH, scale_end_line_width, lv_style_int_t, _int, scalar) + 11456: 4648 mov r0, r9 + 11458: 21c3 movs r1, #195 ; 0xc3 + 1145a: 47b0 blx r6 + lv_style_set_scale_width(&styles->gauge_strong, LV_STATE_DEFAULT, LV_DPX(25)); + 1145c: 6823 ldr r3, [r4, #0] + 1145e: 2000 movs r0, #0 + 11460: f103 0960 add.w r9, r3, #96 ; 0x60 + 11464: 47a8 blx r5 + 11466: eb00 0080 add.w r0, r0, r0, lsl #2 + 1146a: eb00 0080 add.w r0, r0, r0, lsl #2 + 1146e: 28ef cmp r0, #239 ; 0xef + 11470: f340 80a2 ble.w 115b8 + 11474: 2000 movs r0, #0 + 11476: 47a8 blx r5 + 11478: 2319 movs r3, #25 + 1147a: 2250 movs r2, #80 ; 0x50 + 1147c: fb00 2203 mla r2, r0, r3, r2 + 11480: 23a0 movs r3, #160 ; 0xa0 + 11482: fb92 f2f3 sdiv r2, r2, r3 + 11486: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(SCALE_WIDTH, scale_width, lv_style_int_t, _int, scalar) + 11488: 21c0 movs r1, #192 ; 0xc0 + 1148a: 4648 mov r0, r9 + 1148c: 47b0 blx r6 + style_init_reset(&styles->gauge_needle); + 1148e: 6820 ldr r0, [r4, #0] + 11490: 3064 adds r0, #100 ; 0x64 + 11492: 47c0 blx r8 + lv_style_set_line_color(&styles->gauge_needle, LV_STATE_DEFAULT, IS_LIGHT ? lv_color_hex(0x464b5b) : LV_COLOR_WHITE); + 11494: 6823 ldr r3, [r4, #0] + 11496: f103 0864 add.w r8, r3, #100 ; 0x64 + 1149a: 6a23 ldr r3, [r4, #32] + 1149c: 079a lsls r2, r3, #30 + 1149e: f140 808d bpl.w 115bc + 114a2: 4819 ldr r0, [pc, #100] ; (11508 ) + 114a4: 4b19 ldr r3, [pc, #100] ; (1150c ) + 114a6: 4798 blx r3 + 114a8: 4602 mov r2, r0 +_LV_OBJ_STYLE_SET_GET_DECLARE(LINE_COLOR, line_color, lv_color_t, _color, nonscalar) + 114aa: 4640 mov r0, r8 + 114ac: 2199 movs r1, #153 ; 0x99 + 114ae: 47b8 blx r7 + lv_style_set_line_width(&styles->gauge_needle, LV_STATE_DEFAULT, LV_DPX(8)); + 114b0: 6823 ldr r3, [r4, #0] + 114b2: 2000 movs r0, #0 + 114b4: f103 0864 add.w r8, r3, #100 ; 0x64 + 114b8: 47a8 blx r5 + 114ba: 281d cmp r0, #29 + 114bc: f340 8081 ble.w 115c2 + 114c0: 2000 movs r0, #0 + 114c2: 47a8 blx r5 + 114c4: 2314 movs r3, #20 + 114c6: f100 020a add.w r2, r0, #10 + 114ca: fb92 f2f3 sdiv r2, r2, r3 + 114ce: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(LINE_WIDTH, line_width, lv_style_int_t, _int, scalar) + 114d0: 4640 mov r0, r8 + 114d2: 2190 movs r1, #144 ; 0x90 + 114d4: 47b0 blx r6 + lv_style_set_bg_opa(&styles->gauge_needle, LV_STATE_DEFAULT, LV_OPA_COVER); + 114d6: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_OPA, bg_opa, lv_opa_t, _opa, scalar) + 114d8: 4b0d ldr r3, [pc, #52] ; (11510 ) + 114da: 22ff movs r2, #255 ; 0xff + 114dc: 212c movs r1, #44 ; 0x2c + 114de: 3064 adds r0, #100 ; 0x64 + 114e0: 4798 blx r3 + lv_style_set_bg_color(&styles->gauge_needle, LV_STATE_DEFAULT, IS_LIGHT ? lv_color_hex(0x464b5b) : LV_COLOR_WHITE); + 114e2: 6823 ldr r3, [r4, #0] + 114e4: f103 0864 add.w r8, r3, #100 ; 0x64 + 114e8: 6a23 ldr r3, [r4, #32] + 114ea: 079b lsls r3, r3, #30 + 114ec: d56b bpl.n 115c6 + 114ee: 4806 ldr r0, [pc, #24] ; (11508 ) + 114f0: 4b06 ldr r3, [pc, #24] ; (1150c ) + 114f2: 4798 blx r3 + 114f4: 4602 mov r2, r0 + 114f6: e011 b.n 1151c + 114f8: 2000c7d4 .word 0x2000c7d4 + 114fc: 00005949 .word 0x00005949 + 11500: 0000d951 .word 0x0000d951 + 11504: 00005879 .word 0x00005879 + 11508: 00464b5b .word 0x00464b5b + 1150c: 00010e9d .word 0x00010e9d + 11510: 00005a19 .word 0x00005a19 + 11514: 00010abd .word 0x00010abd + 11518: 000102f1 .word 0x000102f1 +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_COLOR, bg_color, lv_color_t, _color, nonscalar) + 1151c: 2129 movs r1, #41 ; 0x29 + 1151e: 4640 mov r0, r8 + 11520: 47b8 blx r7 + lv_style_set_radius(&styles->gauge_needle, LV_STATE_DEFAULT, LV_RADIUS_CIRCLE); + 11522: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(RADIUS, radius, lv_style_int_t, _int, scalar) + 11524: f647 72ff movw r2, #32767 ; 0x7fff + 11528: 2101 movs r1, #1 + 1152a: 3064 adds r0, #100 ; 0x64 + 1152c: 47b0 blx r6 + lv_style_set_size(&styles->gauge_needle, LV_STATE_DEFAULT, LV_DPX(30)); + 1152e: 2000 movs r0, #0 + 11530: 6827 ldr r7, [r4, #0] + 11532: 47a8 blx r5 + 11534: ebc0 1000 rsb r0, r0, r0, lsl #4 + 11538: 0040 lsls r0, r0, #1 + 1153a: 28ef cmp r0, #239 ; 0xef + 1153c: f107 0764 add.w r7, r7, #100 ; 0x64 + 11540: dd44 ble.n 115cc + 11542: 2000 movs r0, #0 + 11544: 47a8 blx r5 + 11546: 231e movs r3, #30 + 11548: 2250 movs r2, #80 ; 0x50 + 1154a: fb00 2203 mla r2, r0, r3, r2 + 1154e: 23a0 movs r3, #160 ; 0xa0 + 11550: fb92 f2f3 sdiv r2, r2, r3 + 11554: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(SIZE, size, lv_style_int_t, _int, scalar) + 11556: 2103 movs r1, #3 + 11558: 4638 mov r0, r7 + 1155a: 47b0 blx r6 + lv_style_set_pad_inner(&styles->gauge_needle, LV_STATE_DEFAULT, LV_DPX(10)); + 1155c: 2000 movs r0, #0 + 1155e: 6824 ldr r4, [r4, #0] + 11560: 47a8 blx r5 + 11562: eb00 0080 add.w r0, r0, r0, lsl #2 + 11566: 0040 lsls r0, r0, #1 + 11568: 28ef cmp r0, #239 ; 0xef + 1156a: f104 0464 add.w r4, r4, #100 ; 0x64 + 1156e: dd2f ble.n 115d0 + 11570: 2000 movs r0, #0 + 11572: 47a8 blx r5 + 11574: 230a movs r3, #10 + 11576: 2250 movs r2, #80 ; 0x50 + 11578: fb00 2203 mla r2, r0, r3, r2 + 1157c: 23a0 movs r3, #160 ; 0xa0 + 1157e: fb92 f2f3 sdiv r2, r2, r3 + 11582: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_INNER, pad_inner, lv_style_int_t, _int, scalar) + 11584: 4620 mov r0, r4 + 11586: 4633 mov r3, r6 + 11588: 2114 movs r1, #20 +} + 1158a: e8bd 47f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 1158e: 4718 bx r3 + lv_style_set_line_width(&styles->gauge_main, LV_STATE_DEFAULT, LV_DPX(5)); + 11590: 2201 movs r2, #1 + 11592: e67a b.n 1128a + lv_style_set_scale_end_line_width(&styles->gauge_main, LV_STATE_DEFAULT, LV_DPX(4)); + 11594: 2201 movs r2, #1 + 11596: e68c b.n 112b2 + lv_style_set_scale_end_border_width(&styles->gauge_main, LV_STATE_DEFAULT, LV_DPX(8)); + 11598: 2201 movs r2, #1 + 1159a: e69d b.n 112d8 + lv_style_set_pad_left(&styles->gauge_main, LV_STATE_DEFAULT, LV_DPX(20)); + 1159c: 2201 movs r2, #1 + 1159e: e6b3 b.n 11308 + lv_style_set_pad_right(&styles->gauge_main, LV_STATE_DEFAULT, LV_DPX(20)); + 115a0: 2201 movs r2, #1 + 115a2: e6c9 b.n 11338 + lv_style_set_pad_top(&styles->gauge_main, LV_STATE_DEFAULT, LV_DPX(20)); + 115a4: 2201 movs r2, #1 + 115a6: e6df b.n 11368 + lv_style_set_pad_inner(&styles->gauge_main, LV_STATE_DEFAULT, LV_DPX(20)); + 115a8: 2201 movs r2, #1 + 115aa: e6f5 b.n 11398 + lv_style_set_scale_width(&styles->gauge_main, LV_STATE_DEFAULT, LV_DPX(15)); + 115ac: 2201 movs r2, #1 + 115ae: e70a b.n 113c6 + lv_style_set_line_width(&styles->gauge_strong, LV_STATE_DEFAULT, LV_DPX(8)); + 115b0: 2201 movs r2, #1 + 115b2: e73d b.n 11430 + lv_style_set_scale_end_line_width(&styles->gauge_strong, LV_STATE_DEFAULT, LV_DPX(8)); + 115b4: 2201 movs r2, #1 + 115b6: e74e b.n 11456 + lv_style_set_scale_width(&styles->gauge_strong, LV_STATE_DEFAULT, LV_DPX(25)); + 115b8: 2201 movs r2, #1 + 115ba: e765 b.n 11488 + lv_style_set_line_color(&styles->gauge_needle, LV_STATE_DEFAULT, IS_LIGHT ? lv_color_hex(0x464b5b) : LV_COLOR_WHITE); + 115bc: 4b05 ldr r3, [pc, #20] ; (115d4 ) + 115be: 881a ldrh r2, [r3, #0] + 115c0: e773 b.n 114aa + lv_style_set_line_width(&styles->gauge_needle, LV_STATE_DEFAULT, LV_DPX(8)); + 115c2: 2201 movs r2, #1 + 115c4: e784 b.n 114d0 + lv_style_set_bg_color(&styles->gauge_needle, LV_STATE_DEFAULT, IS_LIGHT ? lv_color_hex(0x464b5b) : LV_COLOR_WHITE); + 115c6: 4b03 ldr r3, [pc, #12] ; (115d4 ) + 115c8: 881a ldrh r2, [r3, #0] + 115ca: e7a7 b.n 1151c + lv_style_set_size(&styles->gauge_needle, LV_STATE_DEFAULT, LV_DPX(30)); + 115cc: 2201 movs r2, #1 + 115ce: e7c2 b.n 11556 + lv_style_set_pad_inner(&styles->gauge_needle, LV_STATE_DEFAULT, LV_DPX(10)); + 115d0: 2201 movs r2, #1 + 115d2: e7d7 b.n 11584 + 115d4: 00024272 .word 0x00024272 + +000115d8 : +{ + 115d8: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + style_init_reset(&styles->chart_bg); + 115dc: 4d68 ldr r5, [pc, #416] ; (11780 ) + 115de: 4f69 ldr r7, [pc, #420] ; (11784 ) + 115e0: 6828 ldr r0, [r5, #0] + 115e2: f8df 91bc ldr.w r9, [pc, #444] ; 117a0 + 115e6: 3040 adds r0, #64 ; 0x40 + 115e8: 47b8 blx r7 + lv_style_set_text_color(&styles->chart_bg, LV_STATE_DEFAULT, IS_LIGHT ? COLOR_BG_TEXT_DIS : lv_color_hex(0xa1adbd)); + 115ea: 6a2b ldr r3, [r5, #32] + 115ec: 682c ldr r4, [r5, #0] + 115ee: f013 0f02 tst.w r3, #2 + 115f2: f104 0440 add.w r4, r4, #64 ; 0x40 + 115f6: f000 80b1 beq.w 1175c + 115fa: 4b63 ldr r3, [pc, #396] ; (11788 ) + 115fc: f640 20aa movw r0, #2730 ; 0xaaa + 11600: 4798 blx r3 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_COLOR, text_color, lv_color_t, _color, nonscalar) + 11602: 4602 mov r2, r0 + 11604: f248 0189 movw r1, #32905 ; 0x8089 + 11608: 4620 mov r0, r4 + 1160a: f8df 8198 ldr.w r8, [pc, #408] ; 117a4 + lv_style_set_line_width(&styles->chart_series_bg, LV_STATE_DEFAULT, LV_DPX(1)); + 1160e: 4c5f ldr r4, [pc, #380] ; (1178c ) + 11610: 47c0 blx r8 + style_init_reset(&styles->chart_series_bg); + 11612: 6828 ldr r0, [r5, #0] + 11614: 3044 adds r0, #68 ; 0x44 + 11616: 47b8 blx r7 + lv_style_set_line_width(&styles->chart_series_bg, LV_STATE_DEFAULT, LV_DPX(1)); + 11618: 2000 movs r0, #0 + 1161a: 682e ldr r6, [r5, #0] + 1161c: 47a0 blx r4 + 1161e: 28ef cmp r0, #239 ; 0xef + 11620: f106 0644 add.w r6, r6, #68 ; 0x44 + 11624: f340 809d ble.w 11762 + 11628: 2000 movs r0, #0 + 1162a: 47a0 blx r4 + 1162c: 23a0 movs r3, #160 ; 0xa0 + 1162e: f100 0250 add.w r2, r0, #80 ; 0x50 + 11632: fb92 f2f3 sdiv r2, r2, r3 + 11636: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(LINE_WIDTH, line_width, lv_style_int_t, _int, scalar) + 11638: 4630 mov r0, r6 + 1163a: 2190 movs r1, #144 ; 0x90 + 1163c: 4e54 ldr r6, [pc, #336] ; (11790 ) + 1163e: 47b0 blx r6 + lv_style_set_line_dash_width(&styles->chart_series_bg, LV_STATE_DEFAULT, LV_DPX(10)); + 11640: 682b ldr r3, [r5, #0] + 11642: 2000 movs r0, #0 + 11644: f103 0a44 add.w sl, r3, #68 ; 0x44 + 11648: 47a0 blx r4 + 1164a: eb00 0080 add.w r0, r0, r0, lsl #2 + 1164e: 0040 lsls r0, r0, #1 + 11650: 28ef cmp r0, #239 ; 0xef + 11652: f340 8088 ble.w 11766 + 11656: 2000 movs r0, #0 + 11658: 47a0 blx r4 + 1165a: 230a movs r3, #10 + 1165c: 2250 movs r2, #80 ; 0x50 + 1165e: fb00 2203 mla r2, r0, r3, r2 + 11662: 23a0 movs r3, #160 ; 0xa0 + 11664: fb92 f2f3 sdiv r2, r2, r3 + 11668: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(LINE_DASH_WIDTH, line_dash_width, lv_style_int_t, _int, scalar) + 1166a: 4650 mov r0, sl + 1166c: 2192 movs r1, #146 ; 0x92 + 1166e: 47b0 blx r6 + lv_style_set_line_dash_gap(&styles->chart_series_bg, LV_STATE_DEFAULT, LV_DPX(10)); + 11670: 682b ldr r3, [r5, #0] + 11672: 2000 movs r0, #0 + 11674: f103 0a44 add.w sl, r3, #68 ; 0x44 + 11678: 47a0 blx r4 + 1167a: eb00 0080 add.w r0, r0, r0, lsl #2 + 1167e: 0040 lsls r0, r0, #1 + 11680: 28ef cmp r0, #239 ; 0xef + 11682: dd72 ble.n 1176a + 11684: 2000 movs r0, #0 + 11686: 47a0 blx r4 + 11688: 230a movs r3, #10 + 1168a: 2250 movs r2, #80 ; 0x50 + 1168c: fb00 2203 mla r2, r0, r3, r2 + 11690: 23a0 movs r3, #160 ; 0xa0 + 11692: fb92 f2f3 sdiv r2, r2, r3 + 11696: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(LINE_DASH_GAP, line_dash_gap, lv_style_int_t, _int, scalar) + 11698: 4650 mov r0, sl + 1169a: 2193 movs r1, #147 ; 0x93 + 1169c: 47b0 blx r6 + lv_style_set_line_color(&styles->chart_series_bg, LV_STATE_DEFAULT, COLOR_BG_BORDER); + 1169e: 682b ldr r3, [r5, #0] + 116a0: f103 0a44 add.w sl, r3, #68 ; 0x44 + 116a4: 6a2b ldr r3, [r5, #32] + 116a6: 079b lsls r3, r3, #30 + 116a8: bf4c ite mi + 116aa: 483a ldrmi r0, [pc, #232] ; (11794 ) + 116ac: 483a ldrpl r0, [pc, #232] ; (11798 ) + 116ae: 47c8 blx r9 +_LV_OBJ_STYLE_SET_GET_DECLARE(LINE_COLOR, line_color, lv_color_t, _color, nonscalar) + 116b0: 2199 movs r1, #153 ; 0x99 + 116b2: 4602 mov r2, r0 + 116b4: 4650 mov r0, sl + 116b6: 47c0 blx r8 + style_init_reset(&styles->chart_series); + 116b8: 6828 ldr r0, [r5, #0] + 116ba: 3048 adds r0, #72 ; 0x48 + 116bc: 47b8 blx r7 + lv_style_set_line_width(&styles->chart_series, LV_STATE_DEFAULT, LV_DPX(3)); + 116be: 2000 movs r0, #0 + 116c0: 682f ldr r7, [r5, #0] + 116c2: 47a0 blx r4 + 116c4: eb00 0040 add.w r0, r0, r0, lsl #1 + 116c8: 28ef cmp r0, #239 ; 0xef + 116ca: f107 0748 add.w r7, r7, #72 ; 0x48 + 116ce: dd4e ble.n 1176e + 116d0: 2000 movs r0, #0 + 116d2: 47a0 blx r4 + 116d4: 2303 movs r3, #3 + 116d6: 2250 movs r2, #80 ; 0x50 + 116d8: fb00 2203 mla r2, r0, r3, r2 + 116dc: 23a0 movs r3, #160 ; 0xa0 + 116de: fb92 f2f3 sdiv r2, r2, r3 + 116e2: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(LINE_WIDTH, line_width, lv_style_int_t, _int, scalar) + 116e4: 4638 mov r0, r7 + 116e6: 2190 movs r1, #144 ; 0x90 + 116e8: 47b0 blx r6 + lv_style_set_size(&styles->chart_series, LV_STATE_DEFAULT, LV_DPX(4)); + 116ea: 2000 movs r0, #0 + 116ec: 682f ldr r7, [r5, #0] + 116ee: 47a0 blx r4 + 116f0: 283b cmp r0, #59 ; 0x3b + 116f2: f107 0748 add.w r7, r7, #72 ; 0x48 + 116f6: dd3c ble.n 11772 + 116f8: 2000 movs r0, #0 + 116fa: 47a0 blx r4 + 116fc: 2328 movs r3, #40 ; 0x28 + 116fe: f100 0214 add.w r2, r0, #20 + 11702: fb92 f2f3 sdiv r2, r2, r3 + 11706: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(SIZE, size, lv_style_int_t, _int, scalar) + 11708: 4638 mov r0, r7 + 1170a: 2103 movs r1, #3 + 1170c: 47b0 blx r6 + lv_style_set_pad_inner(&styles->chart_series, LV_STATE_DEFAULT, LV_DPX(2)); /*Space between columns*/ + 1170e: 2000 movs r0, #0 + 11710: 682f ldr r7, [r5, #0] + 11712: 47a0 blx r4 + 11714: 2877 cmp r0, #119 ; 0x77 + 11716: f107 0748 add.w r7, r7, #72 ; 0x48 + 1171a: dd2c ble.n 11776 + 1171c: 2000 movs r0, #0 + 1171e: 47a0 blx r4 + 11720: 2350 movs r3, #80 ; 0x50 + 11722: f100 0228 add.w r2, r0, #40 ; 0x28 + 11726: fb92 f2f3 sdiv r2, r2, r3 + 1172a: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_INNER, pad_inner, lv_style_int_t, _int, scalar) + 1172c: 2114 movs r1, #20 + 1172e: 4638 mov r0, r7 + 11730: 47b0 blx r6 + lv_style_set_radius(&styles->chart_series, LV_STATE_DEFAULT, LV_DPX(1)); + 11732: 2000 movs r0, #0 + 11734: 682d ldr r5, [r5, #0] + 11736: 47a0 blx r4 + 11738: 28ef cmp r0, #239 ; 0xef + 1173a: f105 0548 add.w r5, r5, #72 ; 0x48 + 1173e: dd1c ble.n 1177a + 11740: 2000 movs r0, #0 + 11742: 47a0 blx r4 + 11744: 23a0 movs r3, #160 ; 0xa0 + 11746: f100 0250 add.w r2, r0, #80 ; 0x50 + 1174a: fb92 f2f3 sdiv r2, r2, r3 + 1174e: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(RADIUS, radius, lv_style_int_t, _int, scalar) + 11750: 4628 mov r0, r5 + 11752: 4633 mov r3, r6 + 11754: 2101 movs r1, #1 +} + 11756: e8bd 47f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 1175a: 4718 bx r3 + lv_style_set_text_color(&styles->chart_bg, LV_STATE_DEFAULT, IS_LIGHT ? COLOR_BG_TEXT_DIS : lv_color_hex(0xa1adbd)); + 1175c: 480f ldr r0, [pc, #60] ; (1179c ) + 1175e: 47c8 blx r9 + 11760: e74f b.n 11602 + lv_style_set_line_width(&styles->chart_series_bg, LV_STATE_DEFAULT, LV_DPX(1)); + 11762: 2201 movs r2, #1 + 11764: e768 b.n 11638 + lv_style_set_line_dash_width(&styles->chart_series_bg, LV_STATE_DEFAULT, LV_DPX(10)); + 11766: 2201 movs r2, #1 + 11768: e77f b.n 1166a + lv_style_set_line_dash_gap(&styles->chart_series_bg, LV_STATE_DEFAULT, LV_DPX(10)); + 1176a: 2201 movs r2, #1 + 1176c: e794 b.n 11698 + lv_style_set_line_width(&styles->chart_series, LV_STATE_DEFAULT, LV_DPX(3)); + 1176e: 2201 movs r2, #1 + 11770: e7b8 b.n 116e4 + lv_style_set_size(&styles->chart_series, LV_STATE_DEFAULT, LV_DPX(4)); + 11772: 2201 movs r2, #1 + 11774: e7c8 b.n 11708 + lv_style_set_pad_inner(&styles->chart_series, LV_STATE_DEFAULT, LV_DPX(2)); /*Space between columns*/ + 11776: 2201 movs r2, #1 + 11778: e7d8 b.n 1172c + lv_style_set_radius(&styles->chart_series, LV_STATE_DEFAULT, LV_DPX(1)); + 1177a: 2201 movs r2, #1 + 1177c: e7e8 b.n 11750 + 1177e: bf00 nop + 11780: 2000c7d4 .word 0x2000c7d4 + 11784: 00010abd .word 0x00010abd + 11788: 000102f1 .word 0x000102f1 + 1178c: 0000d951 .word 0x0000d951 + 11790: 00005879 .word 0x00005879 + 11794: 00d6dde3 .word 0x00d6dde3 + 11798: 00808a97 .word 0x00808a97 + 1179c: 00a1adbd .word 0x00a1adbd + 117a0: 00010e9d .word 0x00010e9d + 117a4: 00005949 .word 0x00005949 + +000117a8 : +{ + 117a8: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 117ac: ed2d 8b02 vpush {d8} + style_init_reset(&styles->scr); + 117b0: 4ca1 ldr r4, [pc, #644] ; (11a38 ) + 117b2: 4fa2 ldr r7, [pc, #648] ; (11a3c ) + 117b4: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_OPA, bg_opa, lv_opa_t, _opa, scalar) + 117b6: 4da2 ldr r5, [pc, #648] ; (11a40 ) +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_FONT, text_font, const lv_font_t *, _ptr, scalar) + 117b8: f8df a2b0 ldr.w sl, [pc, #688] ; 11a6c +{ + 117bc: b083 sub sp, #12 + style_init_reset(&styles->scr); + 117be: 47b8 blx r7 +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_OPA, bg_opa, lv_opa_t, _opa, scalar) + 117c0: 6820 ldr r0, [r4, #0] + 117c2: 22ff movs r2, #255 ; 0xff + 117c4: 212c movs r1, #44 ; 0x2c + 117c6: 47a8 blx r5 + lv_style_set_bg_color(&styles->scr, LV_STATE_DEFAULT, COLOR_SCR); + 117c8: 6a23 ldr r3, [r4, #32] + 117ca: 6826 ldr r6, [r4, #0] + 117cc: f013 0f02 tst.w r3, #2 + 117d0: bf14 ite ne + 117d2: 489c ldrne r0, [pc, #624] ; (11a44 ) + 117d4: 489c ldreq r0, [pc, #624] ; (11a48 ) + 117d6: 46ab mov fp, r5 + 117d8: 4d9c ldr r5, [pc, #624] ; (11a4c ) + 117da: 47a8 blx r5 +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_COLOR, bg_color, lv_color_t, _color, nonscalar) + 117dc: 46b9 mov r9, r7 + 117de: 4602 mov r2, r0 + 117e0: 4f9b ldr r7, [pc, #620] ; (11a50 ) + 117e2: 4630 mov r0, r6 + 117e4: 2129 movs r1, #41 ; 0x29 + 117e6: 47b8 blx r7 + lv_style_set_text_color(&styles->scr, LV_STATE_DEFAULT, COLOR_SCR_TEXT); + 117e8: 6a23 ldr r3, [r4, #32] + 117ea: 6826 ldr r6, [r4, #0] + 117ec: 0798 lsls r0, r3, #30 + 117ee: bf4c ite mi + 117f0: 4898 ldrmi r0, [pc, #608] ; (11a54 ) + 117f2: 4899 ldrpl r0, [pc, #612] ; (11a58 ) + 117f4: 47a8 blx r5 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_COLOR, text_color, lv_color_t, _color, nonscalar) + 117f6: f248 0189 movw r1, #32905 ; 0x8089 + 117fa: 4602 mov r2, r0 + 117fc: 4630 mov r0, r6 + 117fe: 47b8 blx r7 + lv_style_set_value_color(&styles->scr, LV_STATE_DEFAULT, COLOR_SCR_TEXT); + 11800: 6a23 ldr r3, [r4, #32] + 11802: 6826 ldr r6, [r4, #0] + 11804: 0799 lsls r1, r3, #30 + 11806: bf4c ite mi + 11808: 4892 ldrmi r0, [pc, #584] ; (11a54 ) + 1180a: 4893 ldrpl r0, [pc, #588] ; (11a58 ) + 1180c: 47a8 blx r5 +_LV_OBJ_STYLE_SET_GET_DECLARE(VALUE_COLOR, value_color, lv_color_t, _color, nonscalar) + 1180e: 2179 movs r1, #121 ; 0x79 + 11810: 4602 mov r2, r0 + 11812: 4630 mov r0, r6 + 11814: 47b8 blx r7 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_FONT, text_font, const lv_font_t *, _ptr, scalar) + 11816: 6962 ldr r2, [r4, #20] + 11818: 6820 ldr r0, [r4, #0] + lv_style_set_radius(&styles->bg, LV_STATE_DEFAULT, LV_DPX(8)); + 1181a: 4e90 ldr r6, [pc, #576] ; (11a5c ) + 1181c: f248 018e movw r1, #32910 ; 0x808e + 11820: 47d0 blx sl +_LV_OBJ_STYLE_SET_GET_DECLARE(VALUE_FONT, value_font, const lv_font_t *, _ptr, scalar) + 11822: 6962 ldr r2, [r4, #20] + 11824: 6820 ldr r0, [r4, #0] + 11826: 217e movs r1, #126 ; 0x7e + 11828: 47d0 blx sl + style_init_reset(&styles->bg); + 1182a: 6820 ldr r0, [r4, #0] + 1182c: 3004 adds r0, #4 + 1182e: 47c8 blx r9 + lv_style_set_radius(&styles->bg, LV_STATE_DEFAULT, LV_DPX(8)); + 11830: 6823 ldr r3, [r4, #0] + 11832: 2000 movs r0, #0 + 11834: f103 0804 add.w r8, r3, #4 + 11838: 47b0 blx r6 + 1183a: 281d cmp r0, #29 + 1183c: f340 8568 ble.w 12310 + 11840: 2000 movs r0, #0 + 11842: 47b0 blx r6 + 11844: 2314 movs r3, #20 + 11846: f100 020a add.w r2, r0, #10 + 1184a: fb92 f2f3 sdiv r2, r2, r3 + 1184e: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(RADIUS, radius, lv_style_int_t, _int, scalar) + 11850: 4640 mov r0, r8 + 11852: 2101 movs r1, #1 + 11854: f8df 8218 ldr.w r8, [pc, #536] ; 11a70 + 11858: 47c0 blx r8 + lv_style_set_bg_opa(&styles->bg, LV_STATE_DEFAULT, LV_OPA_COVER); + 1185a: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_OPA, bg_opa, lv_opa_t, _opa, scalar) + 1185c: 22ff movs r2, #255 ; 0xff + 1185e: 3004 adds r0, #4 + 11860: 212c movs r1, #44 ; 0x2c + 11862: 47d8 blx fp + lv_style_set_bg_color(&styles->bg, LV_STATE_DEFAULT, COLOR_BG); + 11864: 6823 ldr r3, [r4, #0] + 11866: f103 0b04 add.w fp, r3, #4 + 1186a: 6a23 ldr r3, [r4, #32] + 1186c: 079a lsls r2, r3, #30 + 1186e: bf54 ite pl + 11870: 487b ldrpl r0, [pc, #492] ; (11a60 ) + 11872: f06f 407f mvnmi.w r0, #4278190080 ; 0xff000000 + 11876: 47a8 blx r5 +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_COLOR, bg_color, lv_color_t, _color, nonscalar) + 11878: 2129 movs r1, #41 ; 0x29 + 1187a: 4602 mov r2, r0 + 1187c: 4658 mov r0, fp + 1187e: 47b8 blx r7 + lv_style_set_border_color(&styles->bg, LV_STATE_DEFAULT, COLOR_BG_BORDER); + 11880: 6823 ldr r3, [r4, #0] + 11882: f103 0b04 add.w fp, r3, #4 + 11886: 6a23 ldr r3, [r4, #32] + 11888: 079b lsls r3, r3, #30 + 1188a: bf4c ite mi + 1188c: 4875 ldrmi r0, [pc, #468] ; (11a64 ) + 1188e: 4876 ldrpl r0, [pc, #472] ; (11a68 ) + 11890: 47a8 blx r5 +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_COLOR, border_color, lv_color_t, _color, nonscalar) + 11892: 2139 movs r1, #57 ; 0x39 + 11894: 4602 mov r2, r0 + 11896: 4658 mov r0, fp + 11898: 47b8 blx r7 + lv_style_set_border_color(&styles->bg, LV_STATE_FOCUSED, theme.color_primary); + 1189a: 6820 ldr r0, [r4, #0] + 1189c: 89a2 ldrh r2, [r4, #12] + 1189e: f240 2139 movw r1, #569 ; 0x239 + 118a2: 3004 adds r0, #4 + 118a4: 47b8 blx r7 + lv_style_set_border_color(&styles->bg, LV_STATE_EDITED, theme.color_secondary); + 118a6: 6820 ldr r0, [r4, #0] + 118a8: 89e2 ldrh r2, [r4, #14] + 118aa: f240 4139 movw r1, #1081 ; 0x439 + 118ae: 3004 adds r0, #4 + 118b0: 47b8 blx r7 + lv_style_set_border_width(&styles->bg, LV_STATE_DEFAULT, BORDER_WIDTH); + 118b2: 6823 ldr r3, [r4, #0] + 118b4: 2000 movs r0, #0 + 118b6: f103 0b04 add.w fp, r3, #4 + 118ba: 47b0 blx r6 + 118bc: 2877 cmp r0, #119 ; 0x77 + 118be: f340 852a ble.w 12316 + 118c2: 2000 movs r0, #0 + 118c4: 47b0 blx r6 + 118c6: 2350 movs r3, #80 ; 0x50 + 118c8: f100 0228 add.w r2, r0, #40 ; 0x28 + 118cc: fb92 f2f3 sdiv r2, r2, r3 + 118d0: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_WIDTH, border_width, lv_style_int_t, _int, scalar) + 118d2: 4658 mov r0, fp + 118d4: 2130 movs r1, #48 ; 0x30 + 118d6: 47c0 blx r8 + lv_style_set_border_post(&styles->bg, LV_STATE_DEFAULT, true); + 118d8: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_POST, border_post, bool, _int, scalar) + 118da: 2201 movs r2, #1 + 118dc: 2133 movs r1, #51 ; 0x33 + 118de: 3004 adds r0, #4 + 118e0: 47c0 blx r8 + lv_style_set_text_font(&styles->bg, LV_STATE_DEFAULT, theme.font_normal); + 118e2: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_FONT, text_font, const lv_font_t *, _ptr, scalar) + 118e4: 6962 ldr r2, [r4, #20] + 118e6: 3004 adds r0, #4 + 118e8: f248 018e movw r1, #32910 ; 0x808e + 118ec: 47d0 blx sl + lv_style_set_text_color(&styles->bg, LV_STATE_DEFAULT, COLOR_BG_TEXT); + 118ee: 6823 ldr r3, [r4, #0] + 118f0: f103 0b04 add.w fp, r3, #4 + 118f4: 6a23 ldr r3, [r4, #32] + 118f6: 0798 lsls r0, r3, #30 + 118f8: bf4c ite mi + 118fa: 4856 ldrmi r0, [pc, #344] ; (11a54 ) + 118fc: f06f 407f mvnpl.w r0, #4278190080 ; 0xff000000 + 11900: 47a8 blx r5 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_COLOR, text_color, lv_color_t, _color, nonscalar) + 11902: f248 0189 movw r1, #32905 ; 0x8089 + 11906: 4602 mov r2, r0 + 11908: 4658 mov r0, fp + 1190a: 47b8 blx r7 + lv_style_set_value_font(&styles->bg, LV_STATE_DEFAULT, theme.font_normal); + 1190c: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(VALUE_FONT, value_font, const lv_font_t *, _ptr, scalar) + 1190e: 6962 ldr r2, [r4, #20] + 11910: 3004 adds r0, #4 + 11912: 217e movs r1, #126 ; 0x7e + 11914: 47d0 blx sl + lv_style_set_value_color(&styles->bg, LV_STATE_DEFAULT, COLOR_BG_TEXT); + 11916: 6823 ldr r3, [r4, #0] + 11918: f103 0a04 add.w sl, r3, #4 + 1191c: 6a23 ldr r3, [r4, #32] + 1191e: 0799 lsls r1, r3, #30 + 11920: bf4c ite mi + 11922: 484c ldrmi r0, [pc, #304] ; (11a54 ) + 11924: f06f 407f mvnpl.w r0, #4278190080 ; 0xff000000 + 11928: 47a8 blx r5 +_LV_OBJ_STYLE_SET_GET_DECLARE(VALUE_COLOR, value_color, lv_color_t, _color, nonscalar) + 1192a: 2179 movs r1, #121 ; 0x79 + 1192c: 4602 mov r2, r0 + 1192e: 4650 mov r0, sl + 11930: 47b8 blx r7 + lv_style_set_image_recolor(&styles->bg, LV_STATE_DEFAULT, COLOR_BG_TEXT); + 11932: 6823 ldr r3, [r4, #0] + 11934: f103 0a04 add.w sl, r3, #4 + 11938: 6a23 ldr r3, [r4, #32] + 1193a: 079a lsls r2, r3, #30 + 1193c: bf4c ite mi + 1193e: 4845 ldrmi r0, [pc, #276] ; (11a54 ) + 11940: f06f 407f mvnpl.w r0, #4278190080 ; 0xff000000 + 11944: 47a8 blx r5 +_LV_OBJ_STYLE_SET_GET_DECLARE(IMAGE_RECOLOR, image_recolor, lv_color_t, _color, nonscalar) + 11946: f248 01a9 movw r1, #32937 ; 0x80a9 + 1194a: 4602 mov r2, r0 + 1194c: 4650 mov r0, sl + 1194e: 47b8 blx r7 + lv_style_set_line_color(&styles->bg, LV_STATE_DEFAULT, COLOR_BG_TEXT); + 11950: 6823 ldr r3, [r4, #0] + 11952: f103 0a04 add.w sl, r3, #4 + 11956: 6a23 ldr r3, [r4, #32] + 11958: 079b lsls r3, r3, #30 + 1195a: bf4c ite mi + 1195c: 483d ldrmi r0, [pc, #244] ; (11a54 ) + 1195e: f06f 407f mvnpl.w r0, #4278190080 ; 0xff000000 + 11962: 47a8 blx r5 +_LV_OBJ_STYLE_SET_GET_DECLARE(LINE_COLOR, line_color, lv_color_t, _color, nonscalar) + 11964: 2199 movs r1, #153 ; 0x99 + 11966: 4602 mov r2, r0 + 11968: 4650 mov r0, sl + 1196a: 47b8 blx r7 + lv_style_set_line_width(&styles->bg, LV_STATE_DEFAULT, 1); + 1196c: 6820 ldr r0, [r4, #0] + lv_style_set_pad_left(&styles->bg, LV_STATE_DEFAULT, PAD_DEF + BORDER_WIDTH); + 1196e: f8df a104 ldr.w sl, [pc, #260] ; 11a74 +_LV_OBJ_STYLE_SET_GET_DECLARE(LINE_WIDTH, line_width, lv_style_int_t, _int, scalar) + 11972: 2201 movs r2, #1 + 11974: 2190 movs r1, #144 ; 0x90 + 11976: 3004 adds r0, #4 + 11978: 47c0 blx r8 + 1197a: 6823 ldr r3, [r4, #0] + 1197c: 2000 movs r0, #0 + 1197e: 3304 adds r3, #4 + 11980: ee08 3a10 vmov s16, r3 + 11984: 47d0 blx sl + 11986: 2801 cmp r0, #1 + 11988: f04f 0000 mov.w r0, #0 + 1198c: f200 84d3 bhi.w 12336 + 11990: 47b0 blx r6 + 11992: ebc0 1000 rsb r0, r0, r0, lsl #4 + 11996: 28ef cmp r0, #239 ; 0xef + 11998: f300 84c0 bgt.w 1231c + 1199c: f04f 0b01 mov.w fp, #1 + 119a0: 2000 movs r0, #0 + 119a2: 47b0 blx r6 + 119a4: 2877 cmp r0, #119 ; 0x77 + 119a6: f340 84d1 ble.w 1234c + 119aa: 2000 movs r0, #0 + 119ac: 47b0 blx r6 + 119ae: 2350 movs r3, #80 ; 0x50 + 119b0: 3028 adds r0, #40 ; 0x28 + 119b2: fb90 f0f3 sdiv r0, r0, r3 + 119b6: b280 uxth r0, r0 + 119b8: eb0b 0200 add.w r2, fp, r0 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_LEFT, pad_left, lv_style_int_t, _int, scalar) + 119bc: b212 sxth r2, r2 + 119be: ee18 0a10 vmov r0, s16 + 119c2: 2112 movs r1, #18 + 119c4: 47c0 blx r8 + lv_style_set_pad_right(&styles->bg, LV_STATE_DEFAULT, PAD_DEF + BORDER_WIDTH); + 119c6: 6823 ldr r3, [r4, #0] + 119c8: 2000 movs r0, #0 + 119ca: 3304 adds r3, #4 + 119cc: ee08 3a10 vmov s16, r3 + 119d0: 47d0 blx sl + 119d2: 2801 cmp r0, #1 + 119d4: f04f 0000 mov.w r0, #0 + 119d8: f200 84c8 bhi.w 1236c + 119dc: 47b0 blx r6 + 119de: ebc0 1000 rsb r0, r0, r0, lsl #4 + 119e2: 28ef cmp r0, #239 ; 0xef + 119e4: f300 84b5 bgt.w 12352 + 119e8: f04f 0b01 mov.w fp, #1 + 119ec: 2000 movs r0, #0 + 119ee: 47b0 blx r6 + 119f0: 2877 cmp r0, #119 ; 0x77 + 119f2: f340 84c6 ble.w 12382 + 119f6: 2000 movs r0, #0 + 119f8: 47b0 blx r6 + 119fa: 2350 movs r3, #80 ; 0x50 + 119fc: 3028 adds r0, #40 ; 0x28 + 119fe: fb90 f0f3 sdiv r0, r0, r3 + 11a02: b280 uxth r0, r0 + 11a04: eb0b 0200 add.w r2, fp, r0 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_RIGHT, pad_right, lv_style_int_t, _int, scalar) + 11a08: b212 sxth r2, r2 + 11a0a: ee18 0a10 vmov r0, s16 + 11a0e: 2113 movs r1, #19 + 11a10: 47c0 blx r8 + lv_style_set_pad_top(&styles->bg, LV_STATE_DEFAULT, PAD_DEF + BORDER_WIDTH); + 11a12: 6823 ldr r3, [r4, #0] + 11a14: 2000 movs r0, #0 + 11a16: 3304 adds r3, #4 + 11a18: ee08 3a10 vmov s16, r3 + 11a1c: 47d0 blx sl + 11a1e: 2801 cmp r0, #1 + 11a20: f04f 0000 mov.w r0, #0 + 11a24: f200 84bd bhi.w 123a2 + 11a28: 47b0 blx r6 + 11a2a: ebc0 1000 rsb r0, r0, r0, lsl #4 + 11a2e: 28ef cmp r0, #239 ; 0xef + 11a30: f300 84aa bgt.w 12388 + 11a34: e020 b.n 11a78 + 11a36: bf00 nop + 11a38: 2000c7d4 .word 0x2000c7d4 + 11a3c: 00010abd .word 0x00010abd + 11a40: 00005a19 .word 0x00005a19 + 11a44: 00eaeff3 .word 0x00eaeff3 + 11a48: 00444b5a .word 0x00444b5a + 11a4c: 00010e9d .word 0x00010e9d + 11a50: 00005949 .word 0x00005949 + 11a54: 003b3e42 .word 0x003b3e42 + 11a58: 00e7e9ec .word 0x00e7e9ec + 11a5c: 0000d951 .word 0x0000d951 + 11a60: 00586273 .word 0x00586273 + 11a64: 00d6dde3 .word 0x00d6dde3 + 11a68: 00808a97 .word 0x00808a97 + 11a6c: 00005aed .word 0x00005aed + 11a70: 00005879 .word 0x00005879 + 11a74: 0000d969 .word 0x0000d969 + 11a78: f04f 0b01 mov.w fp, #1 + 11a7c: 2000 movs r0, #0 + 11a7e: 47b0 blx r6 + 11a80: 2877 cmp r0, #119 ; 0x77 + 11a82: f340 8499 ble.w 123b8 + 11a86: 2000 movs r0, #0 + 11a88: 47b0 blx r6 + 11a8a: 2350 movs r3, #80 ; 0x50 + 11a8c: 3028 adds r0, #40 ; 0x28 + 11a8e: fb90 f0f3 sdiv r0, r0, r3 + 11a92: b280 uxth r0, r0 + 11a94: eb0b 0200 add.w r2, fp, r0 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_TOP, pad_top, lv_style_int_t, _int, scalar) + 11a98: b212 sxth r2, r2 + 11a9a: ee18 0a10 vmov r0, s16 + 11a9e: 2110 movs r1, #16 + 11aa0: 47c0 blx r8 + lv_style_set_pad_bottom(&styles->bg, LV_STATE_DEFAULT, PAD_DEF + BORDER_WIDTH); + 11aa2: 6823 ldr r3, [r4, #0] + 11aa4: 2000 movs r0, #0 + 11aa6: 3304 adds r3, #4 + 11aa8: ee08 3a10 vmov s16, r3 + 11aac: 47d0 blx sl + 11aae: 2801 cmp r0, #1 + 11ab0: f04f 0000 mov.w r0, #0 + 11ab4: f200 8490 bhi.w 123d8 + 11ab8: 47b0 blx r6 + 11aba: ebc0 1000 rsb r0, r0, r0, lsl #4 + 11abe: 28ef cmp r0, #239 ; 0xef + 11ac0: f300 847d bgt.w 123be + 11ac4: f04f 0b01 mov.w fp, #1 + 11ac8: 2000 movs r0, #0 + 11aca: 47b0 blx r6 + 11acc: 2877 cmp r0, #119 ; 0x77 + 11ace: f340 848e ble.w 123ee + 11ad2: 2000 movs r0, #0 + 11ad4: 47b0 blx r6 + 11ad6: 2350 movs r3, #80 ; 0x50 + 11ad8: 3028 adds r0, #40 ; 0x28 + 11ada: fb90 f0f3 sdiv r0, r0, r3 + 11ade: b280 uxth r0, r0 + 11ae0: eb0b 0200 add.w r2, fp, r0 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_BOTTOM, pad_bottom, lv_style_int_t, _int, scalar) + 11ae4: b212 sxth r2, r2 + 11ae6: ee18 0a10 vmov r0, s16 + 11aea: 2111 movs r1, #17 + 11aec: 47c0 blx r8 + lv_style_set_pad_inner(&styles->bg, LV_STATE_DEFAULT, PAD_DEF); + 11aee: 6823 ldr r3, [r4, #0] + 11af0: 2000 movs r0, #0 + 11af2: f103 0b04 add.w fp, r3, #4 + 11af6: 47d0 blx sl + 11af8: 2801 cmp r0, #1 + 11afa: f04f 0000 mov.w r0, #0 + 11afe: f200 8485 bhi.w 1240c + 11b02: 47b0 blx r6 + 11b04: ebc0 1000 rsb r0, r0, r0, lsl #4 + 11b08: 28ef cmp r0, #239 ; 0xef + 11b0a: f300 8473 bgt.w 123f4 + 11b0e: 2201 movs r2, #1 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_INNER, pad_inner, lv_style_int_t, _int, scalar) + 11b10: 2114 movs r1, #20 + 11b12: 4658 mov r0, fp + 11b14: 47c0 blx r8 + lv_style_set_transition_time(&styles->bg, LV_STATE_DEFAULT, TRANSITION_TIME); + 11b16: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSITION_TIME, transition_time, lv_style_int_t, _int, scalar) + 11b18: 2296 movs r2, #150 ; 0x96 + 11b1a: 21b0 movs r1, #176 ; 0xb0 + 11b1c: 3004 adds r0, #4 + 11b1e: 47c0 blx r8 + lv_style_set_transition_prop_6(&styles->bg, LV_STATE_DEFAULT, LV_STYLE_BORDER_COLOR); + 11b20: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSITION_PROP_6, transition_prop_6, lv_style_int_t, _int, scalar) + 11b22: 2239 movs r2, #57 ; 0x39 + 11b24: 21b7 movs r1, #183 ; 0xb7 + 11b26: 3004 adds r0, #4 + 11b28: 47c0 blx r8 + style_init_reset(&styles->bg_sec); + 11b2a: 6820 ldr r0, [r4, #0] + 11b2c: 300c adds r0, #12 + 11b2e: 47c8 blx r9 + lv_style_copy(&styles->bg_sec, &styles->bg); + 11b30: 6820 ldr r0, [r4, #0] + 11b32: 4bac ldr r3, [pc, #688] ; (11de4 ) + 11b34: 1d01 adds r1, r0, #4 + 11b36: 300c adds r0, #12 + 11b38: 4798 blx r3 + lv_style_set_bg_color(&styles->bg_sec, LV_STATE_DEFAULT, COLOR_BG_SEC); + 11b3a: 6a23 ldr r3, [r4, #32] + 11b3c: 6826 ldr r6, [r4, #0] + 11b3e: 0798 lsls r0, r3, #30 + 11b40: bf4c ite mi + 11b42: 48a9 ldrmi r0, [pc, #676] ; (11de8 ) + 11b44: 48a9 ldrpl r0, [pc, #676] ; (11dec ) + 11b46: 47a8 blx r5 + 11b48: 360c adds r6, #12 +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_COLOR, bg_color, lv_color_t, _color, nonscalar) + 11b4a: 4602 mov r2, r0 + 11b4c: 2129 movs r1, #41 ; 0x29 + 11b4e: 4630 mov r0, r6 + 11b50: 47b8 blx r7 + lv_style_set_border_color(&styles->bg_sec, LV_STATE_DEFAULT, COLOR_BG_SEC_BORDER); + 11b52: 6a23 ldr r3, [r4, #32] + 11b54: 6826 ldr r6, [r4, #0] + 11b56: 0799 lsls r1, r3, #30 + 11b58: bf4c ite mi + 11b5a: 48a5 ldrmi r0, [pc, #660] ; (11df0 ) + 11b5c: 48a5 ldrpl r0, [pc, #660] ; (11df4 ) + 11b5e: 47a8 blx r5 + 11b60: 360c adds r6, #12 +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_COLOR, border_color, lv_color_t, _color, nonscalar) + 11b62: 4602 mov r2, r0 + 11b64: 2139 movs r1, #57 ; 0x39 + 11b66: 4630 mov r0, r6 + 11b68: 47b8 blx r7 + lv_style_set_text_color(&styles->bg_sec, LV_STATE_DEFAULT, COLOR_BG_SEC_TEXT); + 11b6a: 6a23 ldr r3, [r4, #32] + 11b6c: 6826 ldr r6, [r4, #0] + 11b6e: 079a lsls r2, r3, #30 + 11b70: bf4c ite mi + 11b72: 48a1 ldrmi r0, [pc, #644] ; (11df8 ) + 11b74: 48a1 ldrpl r0, [pc, #644] ; (11dfc ) + 11b76: 47a8 blx r5 + 11b78: 360c adds r6, #12 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_COLOR, text_color, lv_color_t, _color, nonscalar) + 11b7a: 4602 mov r2, r0 + 11b7c: f248 0189 movw r1, #32905 ; 0x8089 + 11b80: 4630 mov r0, r6 + 11b82: 47b8 blx r7 + lv_style_set_value_color(&styles->bg_sec, LV_STATE_DEFAULT, COLOR_BG_SEC_TEXT); + 11b84: 6a23 ldr r3, [r4, #32] + 11b86: 6826 ldr r6, [r4, #0] + 11b88: 079b lsls r3, r3, #30 + 11b8a: bf4c ite mi + 11b8c: 489a ldrmi r0, [pc, #616] ; (11df8 ) + 11b8e: 489b ldrpl r0, [pc, #620] ; (11dfc ) + 11b90: 47a8 blx r5 + 11b92: 360c adds r6, #12 +_LV_OBJ_STYLE_SET_GET_DECLARE(VALUE_COLOR, value_color, lv_color_t, _color, nonscalar) + 11b94: 4602 mov r2, r0 + 11b96: 2179 movs r1, #121 ; 0x79 + 11b98: 4630 mov r0, r6 + 11b9a: 47b8 blx r7 + lv_style_set_image_recolor(&styles->bg_sec, LV_STATE_DEFAULT, COLOR_BG_SEC_TEXT); + 11b9c: 6a23 ldr r3, [r4, #32] + 11b9e: 6826 ldr r6, [r4, #0] + 11ba0: 0798 lsls r0, r3, #30 + 11ba2: bf4c ite mi + 11ba4: 4894 ldrmi r0, [pc, #592] ; (11df8 ) + 11ba6: 4895 ldrpl r0, [pc, #596] ; (11dfc ) + 11ba8: 47a8 blx r5 + 11baa: 360c adds r6, #12 +_LV_OBJ_STYLE_SET_GET_DECLARE(IMAGE_RECOLOR, image_recolor, lv_color_t, _color, nonscalar) + 11bac: 4602 mov r2, r0 + 11bae: f248 01a9 movw r1, #32937 ; 0x80a9 + 11bb2: 4630 mov r0, r6 + 11bb4: 47b8 blx r7 + lv_style_set_line_color(&styles->bg_sec, LV_STATE_DEFAULT, COLOR_BG_SEC_TEXT); + 11bb6: 6a23 ldr r3, [r4, #32] + 11bb8: 6826 ldr r6, [r4, #0] + 11bba: 0799 lsls r1, r3, #30 + 11bbc: bf4c ite mi + 11bbe: 488e ldrmi r0, [pc, #568] ; (11df8 ) + 11bc0: 488e ldrpl r0, [pc, #568] ; (11dfc ) + 11bc2: 47a8 blx r5 + 11bc4: 360c adds r6, #12 +_LV_OBJ_STYLE_SET_GET_DECLARE(LINE_COLOR, line_color, lv_color_t, _color, nonscalar) + 11bc6: 4602 mov r2, r0 + 11bc8: 2199 movs r1, #153 ; 0x99 + 11bca: 4630 mov r0, r6 + 11bcc: 47b8 blx r7 + style_init_reset(&styles->bg_click); + 11bce: 6820 ldr r0, [r4, #0] + 11bd0: 3008 adds r0, #8 + 11bd2: 47c8 blx r9 + lv_style_set_bg_color(&styles->bg_click, LV_STATE_PRESSED, COLOR_BG_PR); + 11bd4: 6a23 ldr r3, [r4, #32] + 11bd6: 6826 ldr r6, [r4, #0] + lv_style_set_bg_color(&styles->bg_click, LV_STATE_PRESSED | LV_STATE_CHECKED, COLOR_BG_PR_CHK); + 11bd8: f8df 9250 ldr.w r9, [pc, #592] ; 11e2c + lv_style_set_bg_color(&styles->bg_click, LV_STATE_PRESSED, COLOR_BG_PR); + 11bdc: 079a lsls r2, r3, #30 + 11bde: bf4c ite mi + 11be0: 4887 ldrmi r0, [pc, #540] ; (11e00 ) + 11be2: 4888 ldrpl r0, [pc, #544] ; (11e04 ) + 11be4: 47a8 blx r5 + 11be6: 3608 adds r6, #8 +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_COLOR, bg_color, lv_color_t, _color, nonscalar) + 11be8: 4602 mov r2, r0 + 11bea: f241 0129 movw r1, #4137 ; 0x1029 + 11bee: 4630 mov r0, r6 + 11bf0: 47b8 blx r7 + lv_style_set_bg_color(&styles->bg_click, LV_STATE_CHECKED, COLOR_BG_CHK); + 11bf2: 6820 ldr r0, [r4, #0] + 11bf4: 89a2 ldrh r2, [r4, #12] + 11bf6: f240 1129 movw r1, #297 ; 0x129 + 11bfa: 3008 adds r0, #8 + 11bfc: 47b8 blx r7 + lv_style_set_bg_color(&styles->bg_click, LV_STATE_PRESSED | LV_STATE_CHECKED, COLOR_BG_PR_CHK); + 11bfe: 6820 ldr r0, [r4, #0] + 11c00: 2133 movs r1, #51 ; 0x33 + 11c02: f100 0608 add.w r6, r0, #8 + 11c06: 89a0 ldrh r0, [r4, #12] + 11c08: 47c8 blx r9 + 11c0a: f241 1129 movw r1, #4393 ; 0x1129 + 11c0e: 4602 mov r2, r0 + 11c10: 4630 mov r0, r6 + 11c12: 47b8 blx r7 + lv_style_set_bg_color(&styles->bg_click, LV_STATE_DISABLED, COLOR_BG_DIS); + 11c14: 6a23 ldr r3, [r4, #32] + 11c16: 6826 ldr r6, [r4, #0] + 11c18: 079b lsls r3, r3, #30 + 11c1a: bf54 ite pl + 11c1c: 487a ldrpl r0, [pc, #488] ; (11e08 ) + 11c1e: f06f 407f mvnmi.w r0, #4278190080 ; 0xff000000 + 11c22: 47a8 blx r5 + 11c24: 3608 adds r6, #8 + 11c26: 4602 mov r2, r0 + 11c28: f242 0129 movw r1, #8233 ; 0x2029 + 11c2c: 4630 mov r0, r6 + 11c2e: 47b8 blx r7 + lv_style_set_border_width(&styles->bg_click, LV_STATE_CHECKED, 0); + 11c30: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_WIDTH, border_width, lv_style_int_t, _int, scalar) + 11c32: 2200 movs r2, #0 + 11c34: f44f 7198 mov.w r1, #304 ; 0x130 + 11c38: 3008 adds r0, #8 + 11c3a: 47c0 blx r8 + lv_style_set_border_color(&styles->bg_click, LV_STATE_FOCUSED | LV_STATE_PRESSED, lv_color_darken(theme.color_primary, + 11c3c: 6820 ldr r0, [r4, #0] + 11c3e: f8df 81f0 ldr.w r8, [pc, #496] ; 11e30 + 11c42: f100 0608 add.w r6, r0, #8 + 11c46: 2133 movs r1, #51 ; 0x33 + 11c48: 89a0 ldrh r0, [r4, #12] + 11c4a: 47c8 blx r9 +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_COLOR, border_color, lv_color_t, _color, nonscalar) + 11c4c: f241 2139 movw r1, #4665 ; 0x1239 + 11c50: 4602 mov r2, r0 + 11c52: 4630 mov r0, r6 + 11c54: 47b8 blx r7 + lv_style_set_border_color(&styles->bg_click, LV_STATE_PRESSED, COLOR_BG_BORDER_PR); + 11c56: 6a23 ldr r3, [r4, #32] + 11c58: 6826 ldr r6, [r4, #0] + 11c5a: f013 0f02 tst.w r3, #2 + 11c5e: f106 0608 add.w r6, r6, #8 + 11c62: f000 83de beq.w 12422 + 11c66: f640 40cc movw r0, #3276 ; 0xccc + 11c6a: 47c0 blx r8 + 11c6c: 4602 mov r2, r0 + 11c6e: f241 0139 movw r1, #4153 ; 0x1039 + 11c72: 4630 mov r0, r6 + 11c74: 47b8 blx r7 + lv_style_set_border_color(&styles->bg_click, LV_STATE_CHECKED, COLOR_BG_BORDER_CHK); + 11c76: 6a23 ldr r3, [r4, #32] + 11c78: 6826 ldr r6, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_OPA, bg_opa, lv_opa_t, _opa, scalar) + 11c7a: f8df b1b8 ldr.w fp, [pc, #440] ; 11e34 + 11c7e: 0798 lsls r0, r3, #30 + 11c80: bf4c ite mi + 11c82: 4862 ldrmi r0, [pc, #392] ; (11e0c ) + 11c84: 4862 ldrpl r0, [pc, #392] ; (11e10 ) + 11c86: 47a8 blx r5 + 11c88: 3608 adds r6, #8 +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_COLOR, border_color, lv_color_t, _color, nonscalar) + 11c8a: 4602 mov r2, r0 + 11c8c: f240 1139 movw r1, #313 ; 0x139 + 11c90: 4630 mov r0, r6 + 11c92: 47b8 blx r7 + lv_style_set_border_color(&styles->bg_click, LV_STATE_PRESSED | LV_STATE_CHECKED, COLOR_BG_BORDER_CHK_PR); + 11c94: 6a23 ldr r3, [r4, #32] + 11c96: 4d5f ldr r5, [pc, #380] ; (11e14 ) + 11c98: 6826 ldr r6, [r4, #0] + lv_style_set_border_color(&styles->bg_click, LV_STATE_DISABLED, COLOR_BG_BORDER_DIS); + 11c9a: 4c5f ldr r4, [pc, #380] ; (11e18 ) + lv_style_set_border_color(&styles->bg_click, LV_STATE_PRESSED | LV_STATE_CHECKED, COLOR_BG_BORDER_CHK_PR); + 11c9c: f013 0f02 tst.w r3, #2 + 11ca0: bf14 ite ne + 11ca2: 485a ldrne r0, [pc, #360] ; (11e0c ) + 11ca4: 485a ldreq r0, [pc, #360] ; (11e10 ) + 11ca6: 47a8 blx r5 + 11ca8: 3608 adds r6, #8 + 11caa: 4602 mov r2, r0 + 11cac: f241 1139 movw r1, #4409 ; 0x1139 + 11cb0: 4630 mov r0, r6 + 11cb2: 47b8 blx r7 + lv_style_set_border_color(&styles->bg_click, LV_STATE_DISABLED, COLOR_BG_BORDER_DIS); + 11cb4: 6a23 ldr r3, [r4, #32] + 11cb6: 6826 ldr r6, [r4, #0] + 11cb8: 0799 lsls r1, r3, #30 + 11cba: bf4c ite mi + 11cbc: 4857 ldrmi r0, [pc, #348] ; (11e1c ) + 11cbe: 4854 ldrpl r0, [pc, #336] ; (11e10 ) + 11cc0: 47a8 blx r5 + 11cc2: 3608 adds r6, #8 + 11cc4: 4602 mov r2, r0 + 11cc6: f242 0139 movw r1, #8249 ; 0x2039 + 11cca: 4630 mov r0, r6 + 11ccc: 4e54 ldr r6, [pc, #336] ; (11e20 ) + 11cce: 47b0 blx r6 + lv_style_set_text_color(&styles->bg_click, LV_STATE_PRESSED, COLOR_BG_TEXT_PR); + 11cd0: 6a23 ldr r3, [r4, #32] + 11cd2: 6827 ldr r7, [r4, #0] + 11cd4: 079a lsls r2, r3, #30 + 11cd6: bf4c ite mi + 11cd8: 484c ldrmi r0, [pc, #304] ; (11e0c ) + 11cda: f06f 407f mvnpl.w r0, #4278190080 ; 0xff000000 + 11cde: 47a8 blx r5 + 11ce0: 3708 adds r7, #8 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_COLOR, text_color, lv_color_t, _color, nonscalar) + 11ce2: 4602 mov r2, r0 + 11ce4: f249 0189 movw r1, #37001 ; 0x9089 + 11ce8: 4638 mov r0, r7 + 11cea: 47b0 blx r6 + lv_style_set_text_color(&styles->bg_click, LV_STATE_CHECKED, COLOR_BG_TEXT_CHK); + 11cec: 6820 ldr r0, [r4, #0] + 11cee: f100 0708 add.w r7, r0, #8 + 11cf2: f06f 407f mvn.w r0, #4278190080 ; 0xff000000 + 11cf6: 47a8 blx r5 + 11cf8: f248 1189 movw r1, #33161 ; 0x8189 + 11cfc: 4602 mov r2, r0 + 11cfe: 4638 mov r0, r7 + 11d00: 47b0 blx r6 + lv_style_set_text_color(&styles->bg_click, LV_STATE_PRESSED | LV_STATE_CHECKED, COLOR_BG_TEXT_CHK_PR); + 11d02: 6820 ldr r0, [r4, #0] + 11d04: f100 0708 add.w r7, r0, #8 + 11d08: f06f 407f mvn.w r0, #4278190080 ; 0xff000000 + 11d0c: 47a8 blx r5 + 11d0e: f249 1189 movw r1, #37257 ; 0x9189 + 11d12: 4602 mov r2, r0 + 11d14: 4638 mov r0, r7 + 11d16: 47b0 blx r6 + lv_style_set_text_color(&styles->bg_click, LV_STATE_DISABLED, COLOR_BG_TEXT_DIS); + 11d18: 6a23 ldr r3, [r4, #32] + 11d1a: 6827 ldr r7, [r4, #0] + 11d1c: 079b lsls r3, r3, #30 + 11d1e: bf4c ite mi + 11d20: f640 20aa movwmi r0, #2730 ; 0xaaa + 11d24: f640 1099 movwpl r0, #2457 ; 0x999 + 11d28: 47c0 blx r8 + 11d2a: 3708 adds r7, #8 + 11d2c: 4602 mov r2, r0 + 11d2e: f24a 0189 movw r1, #41097 ; 0xa089 + 11d32: 4638 mov r0, r7 + 11d34: 47b0 blx r6 + lv_style_set_image_recolor(&styles->bg_click, LV_STATE_PRESSED, COLOR_BG_TEXT_PR); + 11d36: 6a23 ldr r3, [r4, #32] + 11d38: 6827 ldr r7, [r4, #0] + 11d3a: 0798 lsls r0, r3, #30 + 11d3c: bf4c ite mi + 11d3e: 4833 ldrmi r0, [pc, #204] ; (11e0c ) + 11d40: f06f 407f mvnpl.w r0, #4278190080 ; 0xff000000 + 11d44: 47a8 blx r5 + 11d46: 3708 adds r7, #8 +_LV_OBJ_STYLE_SET_GET_DECLARE(IMAGE_RECOLOR, image_recolor, lv_color_t, _color, nonscalar) + 11d48: 4602 mov r2, r0 + 11d4a: f249 01a9 movw r1, #37033 ; 0x90a9 + 11d4e: 4638 mov r0, r7 + 11d50: 47b0 blx r6 + lv_style_set_image_recolor(&styles->bg_click, LV_STATE_CHECKED, COLOR_BG_TEXT_CHK); + 11d52: 6820 ldr r0, [r4, #0] + 11d54: f100 0708 add.w r7, r0, #8 + 11d58: f06f 407f mvn.w r0, #4278190080 ; 0xff000000 + 11d5c: 47a8 blx r5 + 11d5e: f248 11a9 movw r1, #33193 ; 0x81a9 + 11d62: 4602 mov r2, r0 + 11d64: 4638 mov r0, r7 + 11d66: 47b0 blx r6 + lv_style_set_image_recolor(&styles->bg_click, LV_STATE_PRESSED | LV_STATE_CHECKED, COLOR_BG_TEXT_CHK_PR); + 11d68: 6820 ldr r0, [r4, #0] + 11d6a: f100 0708 add.w r7, r0, #8 + 11d6e: f06f 407f mvn.w r0, #4278190080 ; 0xff000000 + 11d72: 47a8 blx r5 + 11d74: f249 11a9 movw r1, #37289 ; 0x91a9 + 11d78: 4602 mov r2, r0 + 11d7a: 4638 mov r0, r7 + 11d7c: 47b0 blx r6 + lv_style_set_image_recolor(&styles->bg_click, LV_STATE_DISABLED, COLOR_BG_TEXT_DIS); + 11d7e: 6a23 ldr r3, [r4, #32] + 11d80: 6827 ldr r7, [r4, #0] + 11d82: 0799 lsls r1, r3, #30 + 11d84: bf4c ite mi + 11d86: f640 20aa movwmi r0, #2730 ; 0xaaa + 11d8a: f640 1099 movwpl r0, #2457 ; 0x999 + 11d8e: 47c0 blx r8 + 11d90: 3708 adds r7, #8 + 11d92: 4602 mov r2, r0 + 11d94: f24a 01a9 movw r1, #41129 ; 0xa0a9 + 11d98: 4638 mov r0, r7 + 11d9a: 47b0 blx r6 + lv_style_set_transition_prop_5(&styles->bg_click, LV_STATE_DEFAULT, LV_STYLE_BG_COLOR); + 11d9c: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSITION_PROP_5, transition_prop_5, lv_style_int_t, _int, scalar) + 11d9e: 4f21 ldr r7, [pc, #132] ; (11e24 ) + 11da0: 2229 movs r2, #41 ; 0x29 + 11da2: 21b6 movs r1, #182 ; 0xb6 + 11da4: 3008 adds r0, #8 + 11da6: 47b8 blx r7 + style_init_reset(&styles->btn); + 11da8: 6820 ldr r0, [r4, #0] + 11daa: 4b1f ldr r3, [pc, #124] ; (11e28 ) + 11dac: 3010 adds r0, #16 + 11dae: 4798 blx r3 + lv_style_set_radius(&styles->btn, LV_STATE_DEFAULT, LV_RADIUS_CIRCLE); + 11db0: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(RADIUS, radius, lv_style_int_t, _int, scalar) + 11db2: f647 72ff movw r2, #32767 ; 0x7fff + 11db6: 2101 movs r1, #1 + 11db8: 3010 adds r0, #16 + 11dba: 47b8 blx r7 + lv_style_set_bg_opa(&styles->btn, LV_STATE_DEFAULT, LV_OPA_COVER); + 11dbc: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_OPA, bg_opa, lv_opa_t, _opa, scalar) + 11dbe: 22ff movs r2, #255 ; 0xff + 11dc0: 3010 adds r0, #16 + 11dc2: 212c movs r1, #44 ; 0x2c + 11dc4: 47d8 blx fp + lv_style_set_bg_color(&styles->btn, LV_STATE_DEFAULT, COLOR_BTN); + 11dc6: 6823 ldr r3, [r4, #0] + 11dc8: f8cd b004 str.w fp, [sp, #4] + 11dcc: f103 0a10 add.w sl, r3, #16 + 11dd0: 6a23 ldr r3, [r4, #32] + 11dd2: f013 0f02 tst.w r3, #2 + 11dd6: bf0c ite eq + 11dd8: 480b ldreq r0, [pc, #44] ; (11e08 ) + 11dda: f06f 407f mvnne.w r0, #4278190080 ; 0xff000000 + 11dde: 47a8 blx r5 +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_COLOR, bg_color, lv_color_t, _color, nonscalar) + 11de0: 2129 movs r1, #41 ; 0x29 + 11de2: e029 b.n 11e38 + 11de4: 000057d9 .word 0x000057d9 + 11de8: 00d4d7d9 .word 0x00d4d7d9 + 11dec: 0045494d .word 0x0045494d + 11df0: 00dfe7ed .word 0x00dfe7ed + 11df4: 00404040 .word 0x00404040 + 11df8: 0031404f .word 0x0031404f + 11dfc: 00a5a8ad .word 0x00a5a8ad + 11e00: 00eeeeee .word 0x00eeeeee + 11e04: 00494f57 .word 0x00494f57 + 11e08: 00586273 .word 0x00586273 + 11e0c: 003b3e42 .word 0x003b3e42 + 11e10: 005f656e .word 0x005f656e + 11e14: 00010e9d .word 0x00010e9d + 11e18: 2000c7d4 .word 0x2000c7d4 + 11e1c: 00d6dde3 .word 0x00d6dde3 + 11e20: 00005949 .word 0x00005949 + 11e24: 00005879 .word 0x00005879 + 11e28: 00010abd .word 0x00010abd + 11e2c: 0000e38f .word 0x0000e38f + 11e30: 000102f1 .word 0x000102f1 + 11e34: 00005a19 .word 0x00005a19 + 11e38: 4602 mov r2, r0 + 11e3a: 4650 mov r0, sl + 11e3c: 47b0 blx r6 + lv_style_set_bg_color(&styles->btn, LV_STATE_PRESSED, COLOR_BTN_PR); + 11e3e: 6823 ldr r3, [r4, #0] + 11e40: f103 0a10 add.w sl, r3, #16 + 11e44: 6a23 ldr r3, [r4, #32] + 11e46: 079a lsls r2, r3, #30 + 11e48: f140 82ee bpl.w 12428 + 11e4c: f06f 407f mvn.w r0, #4278190080 ; 0xff000000 + 11e50: 47a8 blx r5 + LV_COLOR_SET_R(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_R(c1) * mix + LV_COLOR_GET_R(c2) * (255 - mix))); + 11e52: 7b61 ldrb r1, [r4, #13] + LV_COLOR_SET_G(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_G(c1) * mix + LV_COLOR_GET_G(c2) * (255 - mix))); + 11e54: f8b4 c00c ldrh.w ip, [r4, #12] + LV_COLOR_SET_R(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_R(c1) * mix + LV_COLOR_GET_R(c2) * (255 - mix))); + 11e58: f04f 0be6 mov.w fp, #230 ; 0xe6 + 11e5c: f3c0 22c4 ubfx r2, r0, #11, #5 + 11e60: 2319 movs r3, #25 + 11e62: fb0b f202 mul.w r2, fp, r2 + 11e66: 08c9 lsrs r1, r1, #3 + 11e68: fb13 2101 smlabb r1, r3, r1, r2 + LV_COLOR_SET_G(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_G(c1) * mix + LV_COLOR_GET_G(c2) * (255 - mix))); + 11e6c: f3c0 1245 ubfx r2, r0, #5, #6 + 11e70: fb0b f202 mul.w r2, fp, r2 + 11e74: f3cc 1c45 ubfx ip, ip, #5, #6 + 11e78: fb13 2c0c smlabb ip, r3, ip, r2 + LV_COLOR_SET_B(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_B(c1) * mix + LV_COLOR_GET_B(c2) * (255 - mix))); + 11e7c: 7b22 ldrb r2, [r4, #12] + 11e7e: f000 001f and.w r0, r0, #31 + LV_COLOR_SET_R(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_R(c1) * mix + LV_COLOR_GET_R(c2) * (255 - mix))); + 11e82: f248 0e81 movw lr, #32897 ; 0x8081 + LV_COLOR_SET_B(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_B(c1) * mix + LV_COLOR_GET_B(c2) * (255 - mix))); + 11e86: f002 021f and.w r2, r2, #31 + 11e8a: fb0b f000 mul.w r0, fp, r0 + LV_COLOR_SET_R(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_R(c1) * mix + LV_COLOR_GET_R(c2) * (255 - mix))); + 11e8e: fb0e f101 mul.w r1, lr, r1 + LV_COLOR_SET_G(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_G(c1) * mix + LV_COLOR_GET_G(c2) * (255 - mix))); + 11e92: fb0e fc0c mul.w ip, lr, ip + LV_COLOR_SET_B(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_B(c1) * mix + LV_COLOR_GET_B(c2) * (255 - mix))); + 11e96: fb13 0202 smlabb r2, r3, r2, r0 + LV_COLOR_SET_R(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_R(c1) * mix + LV_COLOR_GET_R(c2) * (255 - mix))); + 11e9a: f3c1 51c4 ubfx r1, r1, #23, #5 + LV_COLOR_SET_G(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_G(c1) * mix + LV_COLOR_GET_G(c2) * (255 - mix))); + 11e9e: f3cc 5cc5 ubfx ip, ip, #23, #6 + LV_COLOR_SET_B(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_B(c1) * mix + LV_COLOR_GET_B(c2) * (255 - mix))); + 11ea2: fb0e f202 mul.w r2, lr, r2 + 11ea6: f3c2 52c4 ubfx r2, r2, #23, #5 + 11eaa: ea42 124c orr.w r2, r2, ip, lsl #5 + 11eae: ea42 22c1 orr.w r2, r2, r1, lsl #11 + 11eb2: 4650 mov r0, sl + 11eb4: f241 0129 movw r1, #4137 ; 0x1029 + 11eb8: 47b0 blx r6 + lv_style_set_bg_color(&styles->btn, LV_STATE_CHECKED, COLOR_BTN_CHK); + 11eba: 6820 ldr r0, [r4, #0] + 11ebc: 89a2 ldrh r2, [r4, #12] + 11ebe: f240 1129 movw r1, #297 ; 0x129 + 11ec2: 3010 adds r0, #16 + 11ec4: 47b0 blx r6 + lv_style_set_bg_color(&styles->btn, LV_STATE_CHECKED | LV_STATE_PRESSED, COLOR_BTN_CHK_PR); + 11ec6: 6820 ldr r0, [r4, #0] + 11ec8: 214c movs r1, #76 ; 0x4c + 11eca: f100 0a10 add.w sl, r0, #16 + 11ece: 89a0 ldrh r0, [r4, #12] + 11ed0: 47c8 blx r9 + 11ed2: f241 1129 movw r1, #4393 ; 0x1129 + 11ed6: 4602 mov r2, r0 + 11ed8: 4650 mov r0, sl + 11eda: 47b0 blx r6 + lv_style_set_bg_color(&styles->btn, LV_STATE_DISABLED, COLOR_BTN); + 11edc: 6823 ldr r3, [r4, #0] + 11ede: f103 0910 add.w r9, r3, #16 + 11ee2: 6a23 ldr r3, [r4, #32] + 11ee4: 079b lsls r3, r3, #30 + 11ee6: bf54 ite pl + 11ee8: 48b2 ldrpl r0, [pc, #712] ; (121b4 ) + 11eea: f06f 407f mvnmi.w r0, #4278190080 ; 0xff000000 + 11eee: 47a8 blx r5 + 11ef0: f242 0129 movw r1, #8233 ; 0x2029 + 11ef4: 4602 mov r2, r0 + 11ef6: 4648 mov r0, r9 + 11ef8: 47b0 blx r6 + lv_style_set_bg_color(&styles->btn, LV_STATE_DISABLED | LV_STATE_CHECKED, COLOR_BTN_DIS); + 11efa: 6823 ldr r3, [r4, #0] + 11efc: f103 0910 add.w r9, r3, #16 + 11f00: 6a23 ldr r3, [r4, #32] + 11f02: 0798 lsls r0, r3, #30 + 11f04: bf4c ite mi + 11f06: f640 40cc movwmi r0, #3276 ; 0xccc + 11f0a: f640 0088 movwpl r0, #2184 ; 0x888 + 11f0e: 47c0 blx r8 + 11f10: f242 1129 movw r1, #8489 ; 0x2129 + 11f14: 4602 mov r2, r0 + 11f16: 4648 mov r0, r9 + 11f18: 47b0 blx r6 + lv_style_set_border_color(&styles->btn, LV_STATE_DEFAULT, COLOR_BTN_BORDER); + 11f1a: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_COLOR, border_color, lv_color_t, _color, nonscalar) + 11f1c: 89a2 ldrh r2, [r4, #12] + 11f1e: 2139 movs r1, #57 ; 0x39 + 11f20: 3010 adds r0, #16 + 11f22: 47b0 blx r6 + lv_style_set_border_color(&styles->btn, LV_STATE_PRESSED, COLOR_BTN_BORDER_PR); + 11f24: 6820 ldr r0, [r4, #0] + 11f26: 89a2 ldrh r2, [r4, #12] + 11f28: f241 0139 movw r1, #4153 ; 0x1039 + 11f2c: 3010 adds r0, #16 + 11f2e: 47b0 blx r6 + lv_style_set_border_color(&styles->btn, LV_STATE_DISABLED, COLOR_BTN_BORDER_INA); + 11f30: 6823 ldr r3, [r4, #0] + 11f32: f103 0910 add.w r9, r3, #16 + 11f36: 6a23 ldr r3, [r4, #32] + 11f38: 0799 lsls r1, r3, #30 + 11f3a: f140 82a0 bpl.w 1247e + 11f3e: f640 0088 movw r0, #2184 ; 0x888 + 11f42: 47c0 blx r8 + 11f44: 4602 mov r2, r0 + 11f46: f242 0139 movw r1, #8249 ; 0x2039 + 11f4a: 4648 mov r0, r9 + 11f4c: 47b0 blx r6 + lv_style_set_border_width(&styles->btn, LV_STATE_DEFAULT, BORDER_WIDTH); + 11f4e: 6823 ldr r3, [r4, #0] + 11f50: f8df 8270 ldr.w r8, [pc, #624] ; 121c4 + 11f54: 2000 movs r0, #0 + 11f56: f103 0910 add.w r9, r3, #16 + 11f5a: 47c0 blx r8 + 11f5c: 2877 cmp r0, #119 ; 0x77 + 11f5e: f340 8291 ble.w 12484 + 11f62: 2000 movs r0, #0 + 11f64: 47c0 blx r8 + 11f66: 2350 movs r3, #80 ; 0x50 + 11f68: f100 0228 add.w r2, r0, #40 ; 0x28 + 11f6c: fb92 f2f3 sdiv r2, r2, r3 + 11f70: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_WIDTH, border_width, lv_style_int_t, _int, scalar) + 11f72: 4648 mov r0, r9 + 11f74: 2130 movs r1, #48 ; 0x30 + 11f76: f8df 9250 ldr.w r9, [pc, #592] ; 121c8 + 11f7a: 47c8 blx r9 + lv_style_set_border_opa(&styles->btn, LV_STATE_CHECKED, LV_OPA_TRANSP); + 11f7c: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_OPA, border_opa, lv_opa_t, _opa, scalar) + 11f7e: 4b8e ldr r3, [pc, #568] ; (121b8 ) + 11f80: 2200 movs r2, #0 + 11f82: 3010 adds r0, #16 + 11f84: f44f 719e mov.w r1, #316 ; 0x13c + 11f88: 4798 blx r3 + lv_style_set_text_color(&styles->btn, LV_STATE_DEFAULT, IS_LIGHT ? lv_color_hex(0x31404f) : lv_color_hex(0xffffff)); + 11f8a: 6823 ldr r3, [r4, #0] + 11f8c: f103 0a10 add.w sl, r3, #16 + 11f90: 6a23 ldr r3, [r4, #32] + 11f92: 079a lsls r2, r3, #30 + 11f94: bf4c ite mi + 11f96: 4889 ldrmi r0, [pc, #548] ; (121bc ) + 11f98: f06f 407f mvnpl.w r0, #4278190080 ; 0xff000000 + 11f9c: 47a8 blx r5 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_COLOR, text_color, lv_color_t, _color, nonscalar) + 11f9e: f248 0189 movw r1, #32905 ; 0x8089 + 11fa2: 4602 mov r2, r0 + 11fa4: 4650 mov r0, sl + 11fa6: 47b0 blx r6 + lv_style_set_text_color(&styles->btn, LV_STATE_PRESSED, IS_LIGHT ? lv_color_hex(0x31404f) : lv_color_hex(0xffffff)); + 11fa8: 6823 ldr r3, [r4, #0] + 11faa: f103 0a10 add.w sl, r3, #16 + 11fae: 6a23 ldr r3, [r4, #32] + 11fb0: 079b lsls r3, r3, #30 + 11fb2: bf4c ite mi + 11fb4: 4881 ldrmi r0, [pc, #516] ; (121bc ) + 11fb6: f06f 407f mvnpl.w r0, #4278190080 ; 0xff000000 + 11fba: 47a8 blx r5 + 11fbc: f249 0189 movw r1, #37001 ; 0x9089 + 11fc0: 4602 mov r2, r0 + 11fc2: 4650 mov r0, sl + 11fc4: 47b0 blx r6 + lv_style_set_text_color(&styles->btn, LV_STATE_CHECKED, lv_color_hex(0xffffff)); + 11fc6: 6820 ldr r0, [r4, #0] + 11fc8: f100 0a10 add.w sl, r0, #16 + 11fcc: f06f 407f mvn.w r0, #4278190080 ; 0xff000000 + 11fd0: 47a8 blx r5 + 11fd2: f248 1189 movw r1, #33161 ; 0x8189 + 11fd6: 4602 mov r2, r0 + 11fd8: 4650 mov r0, sl + 11fda: 47b0 blx r6 + lv_style_set_text_color(&styles->btn, LV_STATE_CHECKED | LV_STATE_PRESSED, lv_color_hex(0xffffff)); + 11fdc: 6820 ldr r0, [r4, #0] + 11fde: f100 0a10 add.w sl, r0, #16 + 11fe2: f06f 407f mvn.w r0, #4278190080 ; 0xff000000 + 11fe6: 47a8 blx r5 + 11fe8: f249 1189 movw r1, #37257 ; 0x9189 + 11fec: 4602 mov r2, r0 + 11fee: 4650 mov r0, sl + 11ff0: 47b0 blx r6 + lv_style_set_text_color(&styles->btn, LV_STATE_DISABLED, IS_LIGHT ? lv_color_hex(0x888888) : lv_color_hex(0x888888)); + 11ff2: 6820 ldr r0, [r4, #0] + 11ff4: f100 0a10 add.w sl, r0, #16 + 11ff8: 4871 ldr r0, [pc, #452] ; (121c0 ) + 11ffa: 47a8 blx r5 + 11ffc: f24a 0189 movw r1, #41097 ; 0xa089 + 12000: 4602 mov r2, r0 + 12002: 4650 mov r0, sl + 12004: 47b0 blx r6 + lv_style_set_image_recolor(&styles->btn, LV_STATE_DEFAULT, IS_LIGHT ? lv_color_hex(0x31404f) : lv_color_hex(0xffffff)); + 12006: 6823 ldr r3, [r4, #0] + 12008: f103 0a10 add.w sl, r3, #16 + 1200c: 6a23 ldr r3, [r4, #32] + 1200e: 0798 lsls r0, r3, #30 + 12010: bf4c ite mi + 12012: 486a ldrmi r0, [pc, #424] ; (121bc ) + 12014: f06f 407f mvnpl.w r0, #4278190080 ; 0xff000000 + 12018: 47a8 blx r5 +_LV_OBJ_STYLE_SET_GET_DECLARE(IMAGE_RECOLOR, image_recolor, lv_color_t, _color, nonscalar) + 1201a: f248 01a9 movw r1, #32937 ; 0x80a9 + 1201e: 4602 mov r2, r0 + 12020: 4650 mov r0, sl + 12022: 47b0 blx r6 + lv_style_set_image_recolor(&styles->btn, LV_STATE_PRESSED, IS_LIGHT ? lv_color_hex(0x31404f) : lv_color_hex(0xffffff)); + 12024: 6823 ldr r3, [r4, #0] + 12026: f103 0a10 add.w sl, r3, #16 + 1202a: 6a23 ldr r3, [r4, #32] + 1202c: 0799 lsls r1, r3, #30 + 1202e: bf4c ite mi + 12030: 4862 ldrmi r0, [pc, #392] ; (121bc ) + 12032: f06f 407f mvnpl.w r0, #4278190080 ; 0xff000000 + 12036: 47a8 blx r5 + 12038: f249 01a9 movw r1, #37033 ; 0x90a9 + 1203c: 4602 mov r2, r0 + 1203e: 4650 mov r0, sl + 12040: 47b0 blx r6 + lv_style_set_image_recolor(&styles->btn, LV_STATE_PRESSED, lv_color_hex(0xffffff)); + 12042: 6820 ldr r0, [r4, #0] + 12044: f100 0a10 add.w sl, r0, #16 + 12048: f06f 407f mvn.w r0, #4278190080 ; 0xff000000 + 1204c: 47a8 blx r5 + 1204e: f249 01a9 movw r1, #37033 ; 0x90a9 + 12052: 4602 mov r2, r0 + 12054: 4650 mov r0, sl + 12056: 47b0 blx r6 + lv_style_set_image_recolor(&styles->btn, LV_STATE_CHECKED | LV_STATE_PRESSED, lv_color_hex(0xffffff)); + 12058: 6820 ldr r0, [r4, #0] + 1205a: f100 0a10 add.w sl, r0, #16 + 1205e: f06f 407f mvn.w r0, #4278190080 ; 0xff000000 + 12062: 47a8 blx r5 + 12064: f249 11a9 movw r1, #37289 ; 0x91a9 + 12068: 4602 mov r2, r0 + 1206a: 4650 mov r0, sl + 1206c: 47b0 blx r6 + lv_style_set_image_recolor(&styles->btn, LV_STATE_DISABLED, IS_LIGHT ? lv_color_hex(0x888888) : lv_color_hex(0x888888)); + 1206e: 6820 ldr r0, [r4, #0] + 12070: f100 0a10 add.w sl, r0, #16 + 12074: 4852 ldr r0, [pc, #328] ; (121c0 ) + 12076: 47a8 blx r5 + 12078: f24a 01a9 movw r1, #41129 ; 0xa0a9 + 1207c: 4602 mov r2, r0 + 1207e: 4650 mov r0, sl + 12080: 47b0 blx r6 + lv_style_set_value_color(&styles->btn, LV_STATE_DEFAULT, IS_LIGHT ? lv_color_hex(0x31404f) : lv_color_hex(0xffffff)); + 12082: 6823 ldr r3, [r4, #0] + 12084: f103 0a10 add.w sl, r3, #16 + 12088: 6a23 ldr r3, [r4, #32] + 1208a: 079a lsls r2, r3, #30 + 1208c: bf4c ite mi + 1208e: 484b ldrmi r0, [pc, #300] ; (121bc ) + 12090: f06f 407f mvnpl.w r0, #4278190080 ; 0xff000000 + 12094: 47a8 blx r5 +_LV_OBJ_STYLE_SET_GET_DECLARE(VALUE_COLOR, value_color, lv_color_t, _color, nonscalar) + 12096: 2179 movs r1, #121 ; 0x79 + 12098: 4602 mov r2, r0 + 1209a: 4650 mov r0, sl + 1209c: 47b0 blx r6 + lv_style_set_value_color(&styles->btn, LV_STATE_PRESSED, IS_LIGHT ? lv_color_hex(0x31404f) : lv_color_hex(0xffffff)); + 1209e: 6823 ldr r3, [r4, #0] + 120a0: f103 0a10 add.w sl, r3, #16 + 120a4: 6a23 ldr r3, [r4, #32] + 120a6: 079b lsls r3, r3, #30 + 120a8: bf4c ite mi + 120aa: 4844 ldrmi r0, [pc, #272] ; (121bc ) + 120ac: f06f 407f mvnpl.w r0, #4278190080 ; 0xff000000 + 120b0: 47a8 blx r5 + 120b2: f241 0179 movw r1, #4217 ; 0x1079 + 120b6: 4602 mov r2, r0 + 120b8: 4650 mov r0, sl + 120ba: 47b0 blx r6 + lv_style_set_value_color(&styles->btn, LV_STATE_CHECKED, lv_color_hex(0xffffff)); + 120bc: 6820 ldr r0, [r4, #0] + 120be: f100 0a10 add.w sl, r0, #16 + 120c2: f06f 407f mvn.w r0, #4278190080 ; 0xff000000 + 120c6: 47a8 blx r5 + 120c8: f240 1179 movw r1, #377 ; 0x179 + 120cc: 4602 mov r2, r0 + 120ce: 4650 mov r0, sl + 120d0: 47b0 blx r6 + lv_style_set_value_color(&styles->btn, LV_STATE_CHECKED | LV_STATE_PRESSED, lv_color_hex(0xffffff)); + 120d2: 6820 ldr r0, [r4, #0] + 120d4: f100 0a10 add.w sl, r0, #16 + 120d8: f06f 407f mvn.w r0, #4278190080 ; 0xff000000 + 120dc: 47a8 blx r5 + 120de: f241 1179 movw r1, #4473 ; 0x1179 + 120e2: 4602 mov r2, r0 + 120e4: 4650 mov r0, sl + 120e6: 47b0 blx r6 + lv_style_set_value_color(&styles->btn, LV_STATE_DISABLED, IS_LIGHT ? lv_color_hex(0x888888) : lv_color_hex(0x888888)); + 120e8: 6820 ldr r0, [r4, #0] + 120ea: f100 0a10 add.w sl, r0, #16 + 120ee: 4834 ldr r0, [pc, #208] ; (121c0 ) + 120f0: 47a8 blx r5 + 120f2: f242 0179 movw r1, #8313 ; 0x2079 + 120f6: 4602 mov r2, r0 + 120f8: 4650 mov r0, sl + 120fa: 47b0 blx r6 + lv_style_set_pad_left(&styles->btn, LV_STATE_DEFAULT, LV_DPX(40)); + 120fc: 2000 movs r0, #0 + 120fe: 6825 ldr r5, [r4, #0] + 12100: 47c0 blx r8 + 12102: eb00 0080 add.w r0, r0, r0, lsl #2 + 12106: 00c0 lsls r0, r0, #3 + 12108: 28ef cmp r0, #239 ; 0xef + 1210a: f105 0510 add.w r5, r5, #16 + 1210e: f340 81bb ble.w 12488 + 12112: 2000 movs r0, #0 + 12114: 47c0 blx r8 + 12116: 2328 movs r3, #40 ; 0x28 + 12118: 2250 movs r2, #80 ; 0x50 + 1211a: fb00 2203 mla r2, r0, r3, r2 + 1211e: 23a0 movs r3, #160 ; 0xa0 + 12120: fb92 f2f3 sdiv r2, r2, r3 + 12124: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_LEFT, pad_left, lv_style_int_t, _int, scalar) + 12126: 4628 mov r0, r5 + 12128: 2112 movs r1, #18 + 1212a: 47c8 blx r9 + lv_style_set_pad_right(&styles->btn, LV_STATE_DEFAULT, LV_DPX(40)); + 1212c: 2000 movs r0, #0 + 1212e: 6825 ldr r5, [r4, #0] + 12130: 47c0 blx r8 + 12132: eb00 0080 add.w r0, r0, r0, lsl #2 + 12136: 00c0 lsls r0, r0, #3 + 12138: 28ef cmp r0, #239 ; 0xef + 1213a: f105 0510 add.w r5, r5, #16 + 1213e: f340 81a5 ble.w 1248c + 12142: 2000 movs r0, #0 + 12144: 47c0 blx r8 + 12146: 2328 movs r3, #40 ; 0x28 + 12148: 2250 movs r2, #80 ; 0x50 + 1214a: fb00 2203 mla r2, r0, r3, r2 + 1214e: 23a0 movs r3, #160 ; 0xa0 + 12150: fb92 f2f3 sdiv r2, r2, r3 + 12154: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_RIGHT, pad_right, lv_style_int_t, _int, scalar) + 12156: 4628 mov r0, r5 + 12158: 2113 movs r1, #19 + 1215a: 47c8 blx r9 + lv_style_set_pad_top(&styles->btn, LV_STATE_DEFAULT, LV_DPX(15)); + 1215c: 2000 movs r0, #0 + 1215e: 6825 ldr r5, [r4, #0] + 12160: 47c0 blx r8 + 12162: ebc0 1000 rsb r0, r0, r0, lsl #4 + 12166: 28ef cmp r0, #239 ; 0xef + 12168: f105 0510 add.w r5, r5, #16 + 1216c: f340 8190 ble.w 12490 + 12170: 2000 movs r0, #0 + 12172: 47c0 blx r8 + 12174: 230f movs r3, #15 + 12176: 2250 movs r2, #80 ; 0x50 + 12178: fb00 2203 mla r2, r0, r3, r2 + 1217c: 23a0 movs r3, #160 ; 0xa0 + 1217e: fb92 f2f3 sdiv r2, r2, r3 + 12182: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_TOP, pad_top, lv_style_int_t, _int, scalar) + 12184: 4628 mov r0, r5 + 12186: 2110 movs r1, #16 + 12188: 47c8 blx r9 + lv_style_set_pad_bottom(&styles->btn, LV_STATE_DEFAULT, LV_DPX(15)); + 1218a: 2000 movs r0, #0 + 1218c: 6825 ldr r5, [r4, #0] + 1218e: 47c0 blx r8 + 12190: ebc0 1000 rsb r0, r0, r0, lsl #4 + 12194: 28ef cmp r0, #239 ; 0xef + 12196: f105 0510 add.w r5, r5, #16 + 1219a: f340 817b ble.w 12494 + 1219e: 2000 movs r0, #0 + 121a0: 47c0 blx r8 + 121a2: 230f movs r3, #15 + 121a4: 2250 movs r2, #80 ; 0x50 + 121a6: fb00 2203 mla r2, r0, r3, r2 + 121aa: 23a0 movs r3, #160 ; 0xa0 + 121ac: fb92 f2f3 sdiv r2, r2, r3 + 121b0: b212 sxth r2, r2 + 121b2: e00b b.n 121cc + 121b4: 00586273 .word 0x00586273 + 121b8: 00005a19 .word 0x00005a19 + 121bc: 0031404f .word 0x0031404f + 121c0: 00888888 .word 0x00888888 + 121c4: 0000d951 .word 0x0000d951 + 121c8: 00005879 .word 0x00005879 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_BOTTOM, pad_bottom, lv_style_int_t, _int, scalar) + 121cc: 4628 mov r0, r5 + 121ce: 2111 movs r1, #17 + 121d0: 47c8 blx r9 + lv_style_set_pad_inner(&styles->btn, LV_STATE_DEFAULT, LV_DPX(20)); + 121d2: 2000 movs r0, #0 + 121d4: 6825 ldr r5, [r4, #0] + 121d6: 47c0 blx r8 + 121d8: eb00 0080 add.w r0, r0, r0, lsl #2 + 121dc: 0080 lsls r0, r0, #2 + 121de: 28ef cmp r0, #239 ; 0xef + 121e0: f105 0510 add.w r5, r5, #16 + 121e4: f340 8158 ble.w 12498 + 121e8: 2000 movs r0, #0 + 121ea: 47c0 blx r8 + 121ec: 2314 movs r3, #20 + 121ee: 2250 movs r2, #80 ; 0x50 + 121f0: fb00 2203 mla r2, r0, r3, r2 + 121f4: 23a0 movs r3, #160 ; 0xa0 + 121f6: fb92 f2f3 sdiv r2, r2, r3 + 121fa: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_INNER, pad_inner, lv_style_int_t, _int, scalar) + 121fc: 4628 mov r0, r5 + 121fe: 2114 movs r1, #20 + 12200: 47b8 blx r7 + lv_style_set_outline_width(&styles->btn, LV_STATE_DEFAULT, 3); + 12202: 6820 ldr r0, [r4, #0] + style_init_reset(&styles->pad_inner); + 12204: 4dbb ldr r5, [pc, #748] ; (124f4 ) +_LV_OBJ_STYLE_SET_GET_DECLARE(OUTLINE_WIDTH, outline_width, lv_style_int_t, _int, scalar) + 12206: 2203 movs r2, #3 + 12208: 2140 movs r1, #64 ; 0x40 + 1220a: 3010 adds r0, #16 + 1220c: 47b8 blx r7 + lv_style_set_outline_opa(&styles->btn, LV_STATE_DEFAULT, LV_OPA_0); + 1220e: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(OUTLINE_OPA, outline_opa, lv_opa_t, _opa, scalar) + 12210: 9b01 ldr r3, [sp, #4] + 12212: 2200 movs r2, #0 + 12214: 214c movs r1, #76 ; 0x4c + 12216: 3010 adds r0, #16 + 12218: 4798 blx r3 + lv_style_set_outline_opa(&styles->btn, LV_STATE_FOCUSED, LV_OPA_50); + 1221a: 6820 ldr r0, [r4, #0] + 1221c: 9b01 ldr r3, [sp, #4] + 1221e: 227f movs r2, #127 ; 0x7f + 12220: f44f 7113 mov.w r1, #588 ; 0x24c + 12224: 3010 adds r0, #16 + 12226: 4798 blx r3 + lv_style_set_outline_color(&styles->btn, LV_STATE_DEFAULT, theme.color_primary); + 12228: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(OUTLINE_COLOR, outline_color, lv_color_t, _color, nonscalar) + 1222a: 89a2 ldrh r2, [r4, #12] + 1222c: 2149 movs r1, #73 ; 0x49 + 1222e: 3010 adds r0, #16 + 12230: 47b0 blx r6 + lv_style_set_outline_color(&styles->btn, LV_STATE_EDITED, theme.color_secondary); + 12232: 6820 ldr r0, [r4, #0] + 12234: 89e2 ldrh r2, [r4, #14] + 12236: f240 4149 movw r1, #1097 ; 0x449 + 1223a: 3010 adds r0, #16 + 1223c: 47b0 blx r6 + lv_style_set_transition_time(&styles->btn, LV_STATE_DEFAULT, TRANSITION_TIME); + 1223e: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSITION_TIME, transition_time, lv_style_int_t, _int, scalar) + 12240: 2296 movs r2, #150 ; 0x96 + 12242: 21b0 movs r1, #176 ; 0xb0 + 12244: 3010 adds r0, #16 + 12246: 47b8 blx r7 + lv_style_set_transition_prop_4(&styles->btn, LV_STATE_DEFAULT, LV_STYLE_BORDER_OPA); + 12248: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSITION_PROP_4, transition_prop_4, lv_style_int_t, _int, scalar) + 1224a: 223c movs r2, #60 ; 0x3c + 1224c: 21b5 movs r1, #181 ; 0xb5 + 1224e: 3010 adds r0, #16 + 12250: 47b8 blx r7 + lv_style_set_transition_prop_5(&styles->btn, LV_STATE_DEFAULT, LV_STYLE_BG_COLOR); + 12252: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSITION_PROP_5, transition_prop_5, lv_style_int_t, _int, scalar) + 12254: 2229 movs r2, #41 ; 0x29 + 12256: 21b6 movs r1, #182 ; 0xb6 + 12258: 3010 adds r0, #16 + 1225a: 47b8 blx r7 + lv_style_set_transition_prop_6(&styles->btn, LV_STATE_DEFAULT, LV_STYLE_OUTLINE_OPA); + 1225c: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSITION_PROP_6, transition_prop_6, lv_style_int_t, _int, scalar) + 1225e: 224c movs r2, #76 ; 0x4c + 12260: 21b7 movs r1, #183 ; 0xb7 + 12262: 3010 adds r0, #16 + 12264: 47b8 blx r7 + lv_style_set_transition_delay(&styles->btn, LV_STATE_DEFAULT, TRANSITION_TIME); + 12266: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSITION_DELAY, transition_delay, lv_style_int_t, _int, scalar) + 12268: 2296 movs r2, #150 ; 0x96 + 1226a: 21b1 movs r1, #177 ; 0xb1 + 1226c: 3010 adds r0, #16 + 1226e: 47b8 blx r7 + lv_style_set_transition_delay(&styles->btn, LV_STATE_PRESSED, 0); + 12270: 6820 ldr r0, [r4, #0] + 12272: 2200 movs r2, #0 + 12274: f241 01b1 movw r1, #4273 ; 0x10b1 + 12278: 3010 adds r0, #16 + 1227a: 47b8 blx r7 + style_init_reset(&styles->pad_inner); + 1227c: 6820 ldr r0, [r4, #0] + lv_disp_get_size_category(NULL) <= LV_DISP_MEDIUM_LIMIT ? LV_DPX(20) : LV_DPX(40)); + 1227e: 4f9e ldr r7, [pc, #632] ; (124f8 ) + style_init_reset(&styles->pad_inner); + 12280: 3014 adds r0, #20 + 12282: 47a8 blx r5 + lv_disp_get_size_category(NULL) <= LV_DISP_MEDIUM_LIMIT ? LV_DPX(20) : LV_DPX(40)); + 12284: 2000 movs r0, #0 + lv_style_set_pad_inner(&styles->pad_inner, LV_STATE_DEFAULT, + 12286: 6826 ldr r6, [r4, #0] + lv_disp_get_size_category(NULL) <= LV_DISP_MEDIUM_LIMIT ? LV_DPX(20) : LV_DPX(40)); + 12288: 47b8 blx r7 + lv_style_set_pad_inner(&styles->pad_inner, LV_STATE_DEFAULT, + 1228a: 2832 cmp r0, #50 ; 0x32 + 1228c: f106 0614 add.w r6, r6, #20 + lv_disp_get_size_category(NULL) <= LV_DISP_MEDIUM_LIMIT ? LV_DPX(20) : LV_DPX(40)); + 12290: f04f 0000 mov.w r0, #0 + lv_style_set_pad_inner(&styles->pad_inner, LV_STATE_DEFAULT, + 12294: f200 810d bhi.w 124b2 + lv_disp_get_size_category(NULL) <= LV_DISP_MEDIUM_LIMIT ? LV_DPX(20) : LV_DPX(40)); + 12298: 47c0 blx r8 + 1229a: eb00 0080 add.w r0, r0, r0, lsl #2 + 1229e: 0080 lsls r0, r0, #2 + lv_style_set_pad_inner(&styles->pad_inner, LV_STATE_DEFAULT, + 122a0: 28ef cmp r0, #239 ; 0xef + 122a2: f300 80fb bgt.w 1249c + 122a6: 2201 movs r2, #1 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_INNER, pad_inner, lv_style_int_t, _int, scalar) + 122a8: 2114 movs r1, #20 + 122aa: 4630 mov r0, r6 + 122ac: 47c8 blx r9 + style_init_reset(&styles->pad_small); + 122ae: 6820 ldr r0, [r4, #0] + 122b0: 3018 adds r0, #24 + 122b2: 47a8 blx r5 + lv_style_int_t pad_small_value = lv_disp_get_size_category(NULL) <= LV_DISP_MEDIUM_LIMIT ? LV_DPX(10) : LV_DPX(20); + 122b4: 2000 movs r0, #0 + 122b6: 47b8 blx r7 + 122b8: 2832 cmp r0, #50 ; 0x32 + 122ba: f04f 0000 mov.w r0, #0 + 122be: f200 810e bhi.w 124de + 122c2: 47c0 blx r8 + 122c4: eb00 0080 add.w r0, r0, r0, lsl #2 + 122c8: 0040 lsls r0, r0, #1 + 122ca: 28ef cmp r0, #239 ; 0xef + 122cc: f300 80fc bgt.w 124c8 + 122d0: 2201 movs r2, #1 + lv_style_set_pad_left(&styles->pad_small, LV_STATE_DEFAULT, pad_small_value); + 122d2: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_LEFT, pad_left, lv_style_int_t, _int, scalar) + 122d4: 9201 str r2, [sp, #4] + 122d6: 2112 movs r1, #18 + 122d8: 3018 adds r0, #24 + 122da: 47c8 blx r9 + lv_style_set_pad_right(&styles->pad_small, LV_STATE_DEFAULT, pad_small_value); + 122dc: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_RIGHT, pad_right, lv_style_int_t, _int, scalar) + 122de: 9a01 ldr r2, [sp, #4] + 122e0: 2113 movs r1, #19 + 122e2: 3018 adds r0, #24 + 122e4: 47c8 blx r9 + lv_style_set_pad_top(&styles->pad_small, LV_STATE_DEFAULT, pad_small_value); + 122e6: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_TOP, pad_top, lv_style_int_t, _int, scalar) + 122e8: 9a01 ldr r2, [sp, #4] + 122ea: 2110 movs r1, #16 + 122ec: 3018 adds r0, #24 + 122ee: 47c8 blx r9 + lv_style_set_pad_bottom(&styles->pad_small, LV_STATE_DEFAULT, pad_small_value); + 122f0: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_BOTTOM, pad_bottom, lv_style_int_t, _int, scalar) + 122f2: 9a01 ldr r2, [sp, #4] + 122f4: 2111 movs r1, #17 + 122f6: 3018 adds r0, #24 + 122f8: 47c8 blx r9 + lv_style_set_pad_inner(&styles->pad_small, LV_STATE_DEFAULT, pad_small_value); + 122fa: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_INNER, pad_inner, lv_style_int_t, _int, scalar) + 122fc: 9a01 ldr r2, [sp, #4] + 122fe: 2114 movs r1, #20 + 12300: 3018 adds r0, #24 + 12302: 464b mov r3, r9 +} + 12304: b003 add sp, #12 + 12306: ecbd 8b02 vpop {d8} + 1230a: e8bd 4ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 1230e: 4718 bx r3 + lv_style_set_radius(&styles->bg, LV_STATE_DEFAULT, LV_DPX(8)); + 12310: 2201 movs r2, #1 + 12312: f7ff ba9d b.w 11850 + lv_style_set_border_width(&styles->bg, LV_STATE_DEFAULT, BORDER_WIDTH); + 12316: 2201 movs r2, #1 + 12318: f7ff badb b.w 118d2 + lv_style_set_pad_left(&styles->bg, LV_STATE_DEFAULT, PAD_DEF + BORDER_WIDTH); + 1231c: 2000 movs r0, #0 + 1231e: 47b0 blx r6 + 12320: 230f movs r3, #15 + 12322: 2250 movs r2, #80 ; 0x50 + 12324: fb00 2203 mla r2, r0, r3, r2 + 12328: 23a0 movs r3, #160 ; 0xa0 + 1232a: fb92 f2f3 sdiv r2, r2, r3 + 1232e: fa1f fb82 uxth.w fp, r2 + 12332: f7ff bb35 b.w 119a0 + 12336: 47b0 blx r6 + 12338: ebc0 1000 rsb r0, r0, r0, lsl #4 + 1233c: 0040 lsls r0, r0, #1 + 1233e: 28ef cmp r0, #239 ; 0xef + 12340: f77f ab2c ble.w 1199c + 12344: 2000 movs r0, #0 + 12346: 47b0 blx r6 + 12348: 231e movs r3, #30 + 1234a: e7ea b.n 12322 + 1234c: 2001 movs r0, #1 + 1234e: f7ff bb33 b.w 119b8 + lv_style_set_pad_right(&styles->bg, LV_STATE_DEFAULT, PAD_DEF + BORDER_WIDTH); + 12352: 2000 movs r0, #0 + 12354: 47b0 blx r6 + 12356: 230f movs r3, #15 + 12358: 2250 movs r2, #80 ; 0x50 + 1235a: fb00 2203 mla r2, r0, r3, r2 + 1235e: 23a0 movs r3, #160 ; 0xa0 + 12360: fb92 f2f3 sdiv r2, r2, r3 + 12364: fa1f fb82 uxth.w fp, r2 + 12368: f7ff bb40 b.w 119ec + 1236c: 47b0 blx r6 + 1236e: ebc0 1000 rsb r0, r0, r0, lsl #4 + 12372: 0040 lsls r0, r0, #1 + 12374: 28ef cmp r0, #239 ; 0xef + 12376: f77f ab37 ble.w 119e8 + 1237a: 2000 movs r0, #0 + 1237c: 47b0 blx r6 + 1237e: 231e movs r3, #30 + 12380: e7ea b.n 12358 + 12382: 2001 movs r0, #1 + 12384: f7ff bb3e b.w 11a04 + lv_style_set_pad_top(&styles->bg, LV_STATE_DEFAULT, PAD_DEF + BORDER_WIDTH); + 12388: 2000 movs r0, #0 + 1238a: 47b0 blx r6 + 1238c: 230f movs r3, #15 + 1238e: 2250 movs r2, #80 ; 0x50 + 12390: fb00 2203 mla r2, r0, r3, r2 + 12394: 23a0 movs r3, #160 ; 0xa0 + 12396: fb92 f2f3 sdiv r2, r2, r3 + 1239a: fa1f fb82 uxth.w fp, r2 + 1239e: f7ff bb6d b.w 11a7c + 123a2: 47b0 blx r6 + 123a4: ebc0 1000 rsb r0, r0, r0, lsl #4 + 123a8: 0040 lsls r0, r0, #1 + 123aa: 28ef cmp r0, #239 ; 0xef + 123ac: f77f ab64 ble.w 11a78 + 123b0: 2000 movs r0, #0 + 123b2: 47b0 blx r6 + 123b4: 231e movs r3, #30 + 123b6: e7ea b.n 1238e + 123b8: 2001 movs r0, #1 + 123ba: f7ff bb6b b.w 11a94 + lv_style_set_pad_bottom(&styles->bg, LV_STATE_DEFAULT, PAD_DEF + BORDER_WIDTH); + 123be: 2000 movs r0, #0 + 123c0: 47b0 blx r6 + 123c2: 230f movs r3, #15 + 123c4: 2250 movs r2, #80 ; 0x50 + 123c6: fb00 2203 mla r2, r0, r3, r2 + 123ca: 23a0 movs r3, #160 ; 0xa0 + 123cc: fb92 f2f3 sdiv r2, r2, r3 + 123d0: fa1f fb82 uxth.w fp, r2 + 123d4: f7ff bb78 b.w 11ac8 + 123d8: 47b0 blx r6 + 123da: ebc0 1000 rsb r0, r0, r0, lsl #4 + 123de: 0040 lsls r0, r0, #1 + 123e0: 28ef cmp r0, #239 ; 0xef + 123e2: f77f ab6f ble.w 11ac4 + 123e6: 2000 movs r0, #0 + 123e8: 47b0 blx r6 + 123ea: 231e movs r3, #30 + 123ec: e7ea b.n 123c4 + 123ee: 2001 movs r0, #1 + 123f0: f7ff bb76 b.w 11ae0 + lv_style_set_pad_inner(&styles->bg, LV_STATE_DEFAULT, PAD_DEF); + 123f4: 2000 movs r0, #0 + 123f6: 47b0 blx r6 + 123f8: 230f movs r3, #15 + 123fa: 2250 movs r2, #80 ; 0x50 + 123fc: fb00 2203 mla r2, r0, r3, r2 + 12400: 23a0 movs r3, #160 ; 0xa0 + 12402: fb92 f2f3 sdiv r2, r2, r3 + 12406: b212 sxth r2, r2 + 12408: f7ff bb82 b.w 11b10 + 1240c: 47b0 blx r6 + 1240e: ebc0 1000 rsb r0, r0, r0, lsl #4 + 12412: 0040 lsls r0, r0, #1 + 12414: 28ef cmp r0, #239 ; 0xef + 12416: f77f ab7a ble.w 11b0e + 1241a: 2000 movs r0, #0 + 1241c: 47b0 blx r6 + 1241e: 231e movs r3, #30 + 12420: e7eb b.n 123fa + lv_style_set_border_color(&styles->bg_click, LV_STATE_PRESSED, COLOR_BG_BORDER_PR); + 12422: 4836 ldr r0, [pc, #216] ; (124fc ) + 12424: 47a8 blx r5 + 12426: e421 b.n 11c6c + lv_style_set_bg_color(&styles->btn, LV_STATE_PRESSED, COLOR_BTN_PR); + 12428: 4835 ldr r0, [pc, #212] ; (12500 ) + 1242a: 47a8 blx r5 + LV_COLOR_SET_G(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_G(c1) * mix + LV_COLOR_GET_G(c2) * (255 - mix))); + 1242c: 89a2 ldrh r2, [r4, #12] + LV_COLOR_SET_R(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_R(c1) * mix + LV_COLOR_GET_R(c2) * (255 - mix))); + 1242e: 7b63 ldrb r3, [r4, #13] + 12430: f04f 0bb3 mov.w fp, #179 ; 0xb3 + LV_COLOR_SET_G(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_G(c1) * mix + LV_COLOR_GET_G(c2) * (255 - mix))); + 12434: f3c0 1c45 ubfx ip, r0, #5, #6 + LV_COLOR_SET_R(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_R(c1) * mix + LV_COLOR_GET_R(c2) * (255 - mix))); + 12438: f04f 0e4c mov.w lr, #76 ; 0x4c + LV_COLOR_SET_G(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_G(c1) * mix + LV_COLOR_GET_G(c2) * (255 - mix))); + 1243c: f3c2 1245 ubfx r2, r2, #5, #6 + 12440: fb0b fc0c mul.w ip, fp, ip + LV_COLOR_SET_R(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_R(c1) * mix + LV_COLOR_GET_R(c2) * (255 - mix))); + 12444: f3c0 21c4 ubfx r1, r0, #11, #5 + LV_COLOR_SET_G(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_G(c1) * mix + LV_COLOR_GET_G(c2) * (255 - mix))); + 12448: fb0e cc02 mla ip, lr, r2, ip + LV_COLOR_SET_B(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_B(c1) * mix + LV_COLOR_GET_B(c2) * (255 - mix))); + 1244c: 7b22 ldrb r2, [r4, #12] + LV_COLOR_SET_R(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_R(c1) * mix + LV_COLOR_GET_R(c2) * (255 - mix))); + 1244e: 08db lsrs r3, r3, #3 + 12450: fb0b f101 mul.w r1, fp, r1 + LV_COLOR_SET_B(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_B(c1) * mix + LV_COLOR_GET_B(c2) * (255 - mix))); + 12454: f000 001f and.w r0, r0, #31 + LV_COLOR_SET_R(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_R(c1) * mix + LV_COLOR_GET_R(c2) * (255 - mix))); + 12458: fb0e 1103 mla r1, lr, r3, r1 + LV_COLOR_SET_B(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_B(c1) * mix + LV_COLOR_GET_B(c2) * (255 - mix))); + 1245c: f002 021f and.w r2, r2, #31 + LV_COLOR_SET_R(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_R(c1) * mix + LV_COLOR_GET_R(c2) * (255 - mix))); + 12460: f248 0381 movw r3, #32897 ; 0x8081 + LV_COLOR_SET_B(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_B(c1) * mix + LV_COLOR_GET_B(c2) * (255 - mix))); + 12464: fb0b f000 mul.w r0, fp, r0 + LV_COLOR_SET_R(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_R(c1) * mix + LV_COLOR_GET_R(c2) * (255 - mix))); + 12468: 4359 muls r1, r3 + LV_COLOR_SET_G(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_G(c1) * mix + LV_COLOR_GET_G(c2) * (255 - mix))); + 1246a: fb03 fc0c mul.w ip, r3, ip + LV_COLOR_SET_B(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_B(c1) * mix + LV_COLOR_GET_B(c2) * (255 - mix))); + 1246e: fb0e 0202 mla r2, lr, r2, r0 + LV_COLOR_SET_R(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_R(c1) * mix + LV_COLOR_GET_R(c2) * (255 - mix))); + 12472: f3c1 51c4 ubfx r1, r1, #23, #5 + LV_COLOR_SET_G(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_G(c1) * mix + LV_COLOR_GET_G(c2) * (255 - mix))); + 12476: f3cc 5cc5 ubfx ip, ip, #23, #6 + LV_COLOR_SET_B(ret, LV_MATH_UDIV255((uint16_t) LV_COLOR_GET_B(c1) * mix + LV_COLOR_GET_B(c2) * (255 - mix))); + 1247a: 435a muls r2, r3 + 1247c: e513 b.n 11ea6 + lv_style_set_border_color(&styles->btn, LV_STATE_DISABLED, COLOR_BTN_BORDER_INA); + 1247e: 4821 ldr r0, [pc, #132] ; (12504 ) + 12480: 47a8 blx r5 + 12482: e55f b.n 11f44 + lv_style_set_border_width(&styles->btn, LV_STATE_DEFAULT, BORDER_WIDTH); + 12484: 2201 movs r2, #1 + 12486: e574 b.n 11f72 + lv_style_set_pad_left(&styles->btn, LV_STATE_DEFAULT, LV_DPX(40)); + 12488: 2201 movs r2, #1 + 1248a: e64c b.n 12126 + lv_style_set_pad_right(&styles->btn, LV_STATE_DEFAULT, LV_DPX(40)); + 1248c: 2201 movs r2, #1 + 1248e: e662 b.n 12156 + lv_style_set_pad_top(&styles->btn, LV_STATE_DEFAULT, LV_DPX(15)); + 12490: 2201 movs r2, #1 + 12492: e677 b.n 12184 + lv_style_set_pad_bottom(&styles->btn, LV_STATE_DEFAULT, LV_DPX(15)); + 12494: 2201 movs r2, #1 + 12496: e699 b.n 121cc + lv_style_set_pad_inner(&styles->btn, LV_STATE_DEFAULT, LV_DPX(20)); + 12498: 2201 movs r2, #1 + 1249a: e6af b.n 121fc + lv_disp_get_size_category(NULL) <= LV_DISP_MEDIUM_LIMIT ? LV_DPX(20) : LV_DPX(40)); + 1249c: 2000 movs r0, #0 + 1249e: 47c0 blx r8 + 124a0: 2314 movs r3, #20 + 124a2: 2250 movs r2, #80 ; 0x50 + 124a4: fb00 2203 mla r2, r0, r3, r2 + 124a8: 23a0 movs r3, #160 ; 0xa0 + 124aa: fb92 f2f3 sdiv r2, r2, r3 + lv_style_set_pad_inner(&styles->pad_inner, LV_STATE_DEFAULT, + 124ae: b212 sxth r2, r2 + 124b0: e6fa b.n 122a8 + lv_disp_get_size_category(NULL) <= LV_DISP_MEDIUM_LIMIT ? LV_DPX(20) : LV_DPX(40)); + 124b2: 47c0 blx r8 + 124b4: eb00 0080 add.w r0, r0, r0, lsl #2 + 124b8: 00c0 lsls r0, r0, #3 + lv_style_set_pad_inner(&styles->pad_inner, LV_STATE_DEFAULT, + 124ba: 28ef cmp r0, #239 ; 0xef + 124bc: f77f aef3 ble.w 122a6 + lv_disp_get_size_category(NULL) <= LV_DISP_MEDIUM_LIMIT ? LV_DPX(20) : LV_DPX(40)); + 124c0: 2000 movs r0, #0 + 124c2: 47c0 blx r8 + 124c4: 2328 movs r3, #40 ; 0x28 + 124c6: e7ec b.n 124a2 + lv_style_int_t pad_small_value = lv_disp_get_size_category(NULL) <= LV_DISP_MEDIUM_LIMIT ? LV_DPX(10) : LV_DPX(20); + 124c8: 2000 movs r0, #0 + 124ca: 47c0 blx r8 + 124cc: 230a movs r3, #10 + 124ce: 2250 movs r2, #80 ; 0x50 + 124d0: fb00 2203 mla r2, r0, r3, r2 + 124d4: 23a0 movs r3, #160 ; 0xa0 + 124d6: fb92 f2f3 sdiv r2, r2, r3 + 124da: b212 sxth r2, r2 + 124dc: e6f9 b.n 122d2 + 124de: 47c0 blx r8 + 124e0: eb00 0080 add.w r0, r0, r0, lsl #2 + 124e4: 0080 lsls r0, r0, #2 + 124e6: 28ef cmp r0, #239 ; 0xef + 124e8: f77f aef2 ble.w 122d0 + 124ec: 2000 movs r0, #0 + 124ee: 47c0 blx r8 + 124f0: 2314 movs r3, #20 + 124f2: e7ec b.n 124ce + 124f4: 00010abd .word 0x00010abd + 124f8: 0000d969 .word 0x0000d969 + 124fc: 005f656e .word 0x005f656e + 12500: 00586273 .word 0x00586273 + 12504: 00404040 .word 0x00404040 + +00012508 : +{ + 12508: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + if(!inited) { + 1250c: 4cb4 ldr r4, [pc, #720] ; (127e0 ) +{ + 1250e: ed2d 8b02 vpush {d8} + 12512: 461e mov r6, r3 + if(!inited) { + 12514: 7923 ldrb r3, [r4, #4] +{ + 12516: b083 sub sp, #12 + 12518: 4680 mov r8, r0 + 1251a: 460f mov r7, r1 + 1251c: 4615 mov r5, r2 + if(!inited) { + 1251e: b92b cbnz r3, 1252c + LV_GC_ROOT(_lv_theme_material_styles) = lv_mem_alloc(sizeof(theme_styles_t)); + 12520: 4bb0 ldr r3, [pc, #704] ; (127e4 ) + 12522: 20bc movs r0, #188 ; 0xbc + 12524: 4798 blx r3 + 12526: 4bb0 ldr r3, [pc, #704] ; (127e8 ) + styles = (theme_styles_t *)LV_GC_ROOT(_lv_theme_material_styles); + 12528: 6020 str r0, [r4, #0] + LV_GC_ROOT(_lv_theme_material_styles) = lv_mem_alloc(sizeof(theme_styles_t)); + 1252a: 6018 str r0, [r3, #0] + theme.font_normal = font_normal; + 1252c: 9b0e ldr r3, [sp, #56] ; 0x38 + 1252e: 6163 str r3, [r4, #20] + theme.font_subtitle = font_subtitle; + 12530: 9b0f ldr r3, [sp, #60] ; 0x3c + 12532: 61a3 str r3, [r4, #24] + theme.font_title = font_title; + 12534: 9b10 ldr r3, [sp, #64] ; 0x40 + theme.color_primary = color_primary; + 12536: f8a4 800c strh.w r8, [r4, #12] + theme.flags = flags; + 1253a: e9c4 3507 strd r3, r5, [r4, #28] + basic_init(); + 1253e: 4bab ldr r3, [pc, #684] ; (127ec ) + theme.color_secondary = color_secondary; + 12540: 81e7 strh r7, [r4, #14] + theme.font_small = font_small; + 12542: 6126 str r6, [r4, #16] + basic_init(); + 12544: 4798 blx r3 + bar_init(); + 12546: 4baa ldr r3, [pc, #680] ; (127f0 ) + style_init_reset(&styles->arc_indic); + 12548: f8df 82dc ldr.w r8, [pc, #732] ; 12828 +_LV_OBJ_STYLE_SET_GET_DECLARE(LINE_COLOR, line_color, lv_color_t, _color, nonscalar) + 1254c: 4fa9 ldr r7, [pc, #676] ; (127f4 ) + lv_style_set_line_width(&styles->arc_indic, LV_STATE_DEFAULT, LV_DPX(25)); + 1254e: 4daa ldr r5, [pc, #680] ; (127f8 ) + bar_init(); + 12550: 4798 blx r3 + led_init(); + 12552: 4baa ldr r3, [pc, #680] ; (127fc ) + 12554: 4798 blx r3 + slider_init(); + 12556: 4baa ldr r3, [pc, #680] ; (12800 ) + 12558: 4798 blx r3 + switch_init(); + 1255a: 4baa ldr r3, [pc, #680] ; (12804 ) + 1255c: 4798 blx r3 + linemeter_init(); + 1255e: 4baa ldr r3, [pc, #680] ; (12808 ) + 12560: 4798 blx r3 + gauge_init(); + 12562: 4baa ldr r3, [pc, #680] ; (1280c ) + 12564: 4798 blx r3 + style_init_reset(&styles->arc_indic); + 12566: 6820 ldr r0, [r4, #0] + 12568: 301c adds r0, #28 + 1256a: 47c0 blx r8 + lv_style_set_line_color(&styles->arc_indic, LV_STATE_DEFAULT, theme.color_primary); + 1256c: 6820 ldr r0, [r4, #0] + 1256e: 89a2 ldrh r2, [r4, #12] + 12570: 2199 movs r1, #153 ; 0x99 + 12572: 301c adds r0, #28 + 12574: 47b8 blx r7 + lv_style_set_line_width(&styles->arc_indic, LV_STATE_DEFAULT, LV_DPX(25)); + 12576: 2000 movs r0, #0 + 12578: 6826 ldr r6, [r4, #0] + 1257a: 47a8 blx r5 + 1257c: eb00 0080 add.w r0, r0, r0, lsl #2 + 12580: eb00 0080 add.w r0, r0, r0, lsl #2 + 12584: 28ef cmp r0, #239 ; 0xef + 12586: f106 061c add.w r6, r6, #28 + 1258a: f341 8256 ble.w 13a3a + 1258e: 2000 movs r0, #0 + 12590: 47a8 blx r5 + 12592: 2319 movs r3, #25 + 12594: 2250 movs r2, #80 ; 0x50 + 12596: fb00 2203 mla r2, r0, r3, r2 + 1259a: 23a0 movs r3, #160 ; 0xa0 + 1259c: fb92 f2f3 sdiv r2, r2, r3 + 125a0: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(LINE_WIDTH, line_width, lv_style_int_t, _int, scalar) + 125a2: 4630 mov r0, r6 + 125a4: 2190 movs r1, #144 ; 0x90 + 125a6: 4e9a ldr r6, [pc, #616] ; (12810 ) + 125a8: f8df a280 ldr.w sl, [pc, #640] ; 1282c + 125ac: 47b0 blx r6 + lv_style_set_line_rounded(&styles->arc_indic, LV_STATE_DEFAULT, true); + 125ae: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(LINE_ROUNDED, line_rounded, bool, _int, scalar) + 125b0: 2201 movs r2, #1 + 125b2: 2194 movs r1, #148 ; 0x94 + 125b4: 301c adds r0, #28 + 125b6: 47b0 blx r6 + style_init_reset(&styles->arc_bg); + 125b8: 6820 ldr r0, [r4, #0] + 125ba: 3020 adds r0, #32 + 125bc: 47c0 blx r8 + lv_style_set_line_color(&styles->arc_bg, LV_STATE_DEFAULT, COLOR_BG_SEC); + 125be: 6823 ldr r3, [r4, #0] + 125c0: f103 0920 add.w r9, r3, #32 + 125c4: 6a23 ldr r3, [r4, #32] + 125c6: f013 0f02 tst.w r3, #2 + 125ca: bf14 ite ne + 125cc: 4891 ldrne r0, [pc, #580] ; (12814 ) + 125ce: 4892 ldreq r0, [pc, #584] ; (12818 ) + 125d0: 47d0 blx sl +_LV_OBJ_STYLE_SET_GET_DECLARE(LINE_COLOR, line_color, lv_color_t, _color, nonscalar) + 125d2: 2199 movs r1, #153 ; 0x99 + 125d4: 4602 mov r2, r0 + 125d6: 4648 mov r0, r9 + 125d8: 47b8 blx r7 + lv_style_set_line_width(&styles->arc_bg, LV_STATE_DEFAULT, LV_DPX(25)); + 125da: 6823 ldr r3, [r4, #0] + 125dc: 2000 movs r0, #0 + 125de: f103 0920 add.w r9, r3, #32 + 125e2: 47a8 blx r5 + 125e4: eb00 0080 add.w r0, r0, r0, lsl #2 + 125e8: eb00 0080 add.w r0, r0, r0, lsl #2 + 125ec: 28ef cmp r0, #239 ; 0xef + 125ee: f341 8227 ble.w 13a40 + 125f2: 2000 movs r0, #0 + 125f4: 47a8 blx r5 + 125f6: 2319 movs r3, #25 + 125f8: 2250 movs r2, #80 ; 0x50 + 125fa: fb00 2203 mla r2, r0, r3, r2 + 125fe: 23a0 movs r3, #160 ; 0xa0 + 12600: fb92 f2f3 sdiv r2, r2, r3 + 12604: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(LINE_WIDTH, line_width, lv_style_int_t, _int, scalar) + 12606: 4648 mov r0, r9 + 12608: 2190 movs r1, #144 ; 0x90 + 1260a: 47b0 blx r6 + lv_style_set_line_rounded(&styles->arc_bg, LV_STATE_DEFAULT, true); + 1260c: 6820 ldr r0, [r4, #0] + lv_style_set_pad_top(&styles->calendar_header, LV_STATE_DEFAULT, PAD_DEF); + 1260e: f8df 9220 ldr.w r9, [pc, #544] ; 12830 +_LV_OBJ_STYLE_SET_GET_DECLARE(LINE_ROUNDED, line_rounded, bool, _int, scalar) + 12612: 2201 movs r2, #1 + 12614: 2194 movs r1, #148 ; 0x94 + 12616: 3020 adds r0, #32 + 12618: 47b0 blx r6 + chart_init(); + 1261a: 4b80 ldr r3, [pc, #512] ; (1281c ) + 1261c: 4798 blx r3 + style_init_reset(&styles->calendar_header); + 1261e: 6820 ldr r0, [r4, #0] + 12620: 3030 adds r0, #48 ; 0x30 + 12622: 47c0 blx r8 + lv_style_set_pad_top(&styles->calendar_header, LV_STATE_DEFAULT, PAD_DEF); + 12624: 6823 ldr r3, [r4, #0] + 12626: 2000 movs r0, #0 + 12628: f103 0b30 add.w fp, r3, #48 ; 0x30 + 1262c: 47c8 blx r9 + 1262e: 2801 cmp r0, #1 + 12630: f04f 0000 mov.w r0, #0 + 12634: f201 8213 bhi.w 13a5e + 12638: 47a8 blx r5 + 1263a: ebc0 1000 rsb r0, r0, r0, lsl #4 + 1263e: 28ef cmp r0, #239 ; 0xef + 12640: f301 8201 bgt.w 13a46 + 12644: 2201 movs r2, #1 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_TOP, pad_top, lv_style_int_t, _int, scalar) + 12646: 4658 mov r0, fp + 12648: 2110 movs r1, #16 + 1264a: 47b0 blx r6 + lv_style_set_pad_left(&styles->calendar_header, LV_STATE_DEFAULT, PAD_DEF); + 1264c: 6823 ldr r3, [r4, #0] + 1264e: 2000 movs r0, #0 + 12650: f103 0b30 add.w fp, r3, #48 ; 0x30 + 12654: 47c8 blx r9 + 12656: 2801 cmp r0, #1 + 12658: f04f 0000 mov.w r0, #0 + 1265c: f201 8216 bhi.w 13a8c + 12660: 47a8 blx r5 + 12662: ebc0 1000 rsb r0, r0, r0, lsl #4 + 12666: 28ef cmp r0, #239 ; 0xef + 12668: f301 8204 bgt.w 13a74 + 1266c: 2201 movs r2, #1 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_LEFT, pad_left, lv_style_int_t, _int, scalar) + 1266e: 4658 mov r0, fp + 12670: 2112 movs r1, #18 + 12672: 47b0 blx r6 + lv_style_set_pad_right(&styles->calendar_header, LV_STATE_DEFAULT, PAD_DEF); + 12674: 6823 ldr r3, [r4, #0] + 12676: 2000 movs r0, #0 + 12678: f103 0b30 add.w fp, r3, #48 ; 0x30 + 1267c: 47c8 blx r9 + 1267e: 2801 cmp r0, #1 + 12680: f04f 0000 mov.w r0, #0 + 12684: f201 8219 bhi.w 13aba + 12688: 47a8 blx r5 + 1268a: ebc0 1000 rsb r0, r0, r0, lsl #4 + 1268e: 28ef cmp r0, #239 ; 0xef + 12690: f301 8207 bgt.w 13aa2 + 12694: 2201 movs r2, #1 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_RIGHT, pad_right, lv_style_int_t, _int, scalar) + 12696: 4658 mov r0, fp + 12698: 2113 movs r1, #19 + 1269a: 47b0 blx r6 + lv_style_set_pad_bottom(&styles->calendar_header, LV_STATE_DEFAULT, PAD_DEF); + 1269c: 6823 ldr r3, [r4, #0] + 1269e: 2000 movs r0, #0 + 126a0: f103 0b30 add.w fp, r3, #48 ; 0x30 + 126a4: 47c8 blx r9 + 126a6: 2801 cmp r0, #1 + 126a8: f04f 0000 mov.w r0, #0 + 126ac: f201 821c bhi.w 13ae8 + 126b0: 47a8 blx r5 + 126b2: ebc0 1000 rsb r0, r0, r0, lsl #4 + 126b6: 28ef cmp r0, #239 ; 0xef + 126b8: f301 820a bgt.w 13ad0 + 126bc: 2201 movs r2, #1 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_BOTTOM, pad_bottom, lv_style_int_t, _int, scalar) + 126be: 4658 mov r0, fp + 126c0: 2111 movs r1, #17 + 126c2: 47b0 blx r6 + lv_style_set_text_color(&styles->calendar_header, LV_STATE_PRESSED, IS_LIGHT ? lv_color_hex(0x888888) : LV_COLOR_WHITE); + 126c4: 6a22 ldr r2, [r4, #32] + 126c6: 6823 ldr r3, [r4, #0] + 126c8: f8df b168 ldr.w fp, [pc, #360] ; 12834 + 126cc: f012 0f02 tst.w r2, #2 + 126d0: f103 0330 add.w r3, r3, #48 ; 0x30 + 126d4: f001 8213 beq.w 13afe + 126d8: 4851 ldr r0, [pc, #324] ; (12820 ) + 126da: 9301 str r3, [sp, #4] + 126dc: 47d0 blx sl + 126de: 9b01 ldr r3, [sp, #4] + 126e0: 4602 mov r2, r0 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_COLOR, text_color, lv_color_t, _color, nonscalar) + 126e2: 4618 mov r0, r3 + 126e4: f249 0189 movw r1, #37001 ; 0x9089 + 126e8: 47b8 blx r7 + style_init_reset(&styles->calendar_daynames); + 126ea: 6820 ldr r0, [r4, #0] + 126ec: 3034 adds r0, #52 ; 0x34 + 126ee: 47c0 blx r8 + lv_style_set_text_color(&styles->calendar_daynames, LV_STATE_DEFAULT, IS_LIGHT ? lv_color_hex(0x31404f) : lv_color_hex3(0xeee)); + 126f0: 6823 ldr r3, [r4, #0] + 126f2: 3334 adds r3, #52 ; 0x34 + 126f4: ee07 3a90 vmov s15, r3 + 126f8: 6a23 ldr r3, [r4, #32] + 126fa: 0798 lsls r0, r3, #30 + 126fc: f141 8203 bpl.w 13b06 + 12700: 4848 ldr r0, [pc, #288] ; (12824 ) + 12702: 47d0 blx sl + 12704: 4602 mov r2, r0 + 12706: f248 0189 movw r1, #32905 ; 0x8089 + 1270a: ee17 0a90 vmov r0, s15 + 1270e: 47b8 blx r7 + lv_style_set_pad_left(&styles->calendar_daynames, LV_STATE_DEFAULT, PAD_DEF); + 12710: 6823 ldr r3, [r4, #0] + 12712: 2000 movs r0, #0 + 12714: 3334 adds r3, #52 ; 0x34 + 12716: ee08 3a10 vmov s16, r3 + 1271a: 47c8 blx r9 + 1271c: 2801 cmp r0, #1 + 1271e: f04f 0000 mov.w r0, #0 + 12722: f201 8202 bhi.w 13b2a + 12726: 47a8 blx r5 + 12728: ebc0 1000 rsb r0, r0, r0, lsl #4 + 1272c: 28ef cmp r0, #239 ; 0xef + 1272e: f301 81f0 bgt.w 13b12 + 12732: 2201 movs r2, #1 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_LEFT, pad_left, lv_style_int_t, _int, scalar) + 12734: ee18 0a10 vmov r0, s16 + 12738: 2112 movs r1, #18 + 1273a: 47b0 blx r6 + lv_style_set_pad_right(&styles->calendar_daynames, LV_STATE_DEFAULT, PAD_DEF); + 1273c: 6823 ldr r3, [r4, #0] + 1273e: 2000 movs r0, #0 + 12740: 3334 adds r3, #52 ; 0x34 + 12742: ee08 3a10 vmov s16, r3 + 12746: 47c8 blx r9 + 12748: 2801 cmp r0, #1 + 1274a: f04f 0000 mov.w r0, #0 + 1274e: f201 8203 bhi.w 13b58 + 12752: 47a8 blx r5 + 12754: ebc0 1000 rsb r0, r0, r0, lsl #4 + 12758: 28ef cmp r0, #239 ; 0xef + 1275a: f301 81f1 bgt.w 13b40 + 1275e: 2201 movs r2, #1 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_RIGHT, pad_right, lv_style_int_t, _int, scalar) + 12760: ee18 0a10 vmov r0, s16 + 12764: 2113 movs r1, #19 + 12766: 47b0 blx r6 + lv_style_set_pad_bottom(&styles->calendar_daynames, LV_STATE_DEFAULT, PAD_DEF); + 12768: 6823 ldr r3, [r4, #0] + 1276a: 2000 movs r0, #0 + 1276c: 3334 adds r3, #52 ; 0x34 + 1276e: ee08 3a10 vmov s16, r3 + 12772: 47c8 blx r9 + 12774: 2801 cmp r0, #1 + 12776: f04f 0000 mov.w r0, #0 + 1277a: f201 8204 bhi.w 13b86 + 1277e: 47a8 blx r5 + 12780: ebc0 1000 rsb r0, r0, r0, lsl #4 + 12784: 28ef cmp r0, #239 ; 0xef + 12786: f301 81f2 bgt.w 13b6e + 1278a: 2201 movs r2, #1 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_BOTTOM, pad_bottom, lv_style_int_t, _int, scalar) + 1278c: ee18 0a10 vmov r0, s16 + 12790: 2111 movs r1, #17 + 12792: 47b0 blx r6 + style_init_reset(&styles->calendar_date_nums); + 12794: 6820 ldr r0, [r4, #0] + 12796: 302c adds r0, #44 ; 0x2c + 12798: 47c0 blx r8 + lv_style_set_radius(&styles->calendar_date_nums, LV_STATE_DEFAULT, LV_DPX(4)); + 1279a: 6823 ldr r3, [r4, #0] + 1279c: 2000 movs r0, #0 + 1279e: 332c adds r3, #44 ; 0x2c + 127a0: ee08 3a10 vmov s16, r3 + 127a4: 47a8 blx r5 + 127a6: 283b cmp r0, #59 ; 0x3b + 127a8: f341 81f8 ble.w 13b9c + 127ac: 2000 movs r0, #0 + 127ae: 47a8 blx r5 + 127b0: 2328 movs r3, #40 ; 0x28 + 127b2: f100 0214 add.w r2, r0, #20 + 127b6: fb92 f2f3 sdiv r2, r2, r3 + 127ba: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(RADIUS, radius, lv_style_int_t, _int, scalar) + 127bc: 2101 movs r1, #1 + 127be: ee18 0a10 vmov r0, s16 + 127c2: 47b0 blx r6 + lv_style_set_text_color(&styles->calendar_date_nums, LV_STATE_CHECKED, IS_LIGHT ? lv_color_hex(0x31404f) : LV_COLOR_WHITE); + 127c4: 6a22 ldr r2, [r4, #32] + 127c6: 6823 ldr r3, [r4, #0] + 127c8: 0791 lsls r1, r2, #30 + 127ca: f103 032c add.w r3, r3, #44 ; 0x2c + 127ce: f141 81e8 bpl.w 13ba2 + 127d2: 4814 ldr r0, [pc, #80] ; (12824 ) + 127d4: 9301 str r3, [sp, #4] + 127d6: 47d0 blx sl + 127d8: 9b01 ldr r3, [sp, #4] + 127da: 4602 mov r2, r0 + 127dc: e02c b.n 12838 + 127de: bf00 nop + 127e0: 2000c7d4 .word 0x2000c7d4 + 127e4: 0000ea2d .word 0x0000ea2d + 127e8: 20008774 .word 0x20008774 + 127ec: 000117a9 .word 0x000117a9 + 127f0: 00010eb5 .word 0x00010eb5 + 127f4: 00005949 .word 0x00005949 + 127f8: 0000d951 .word 0x0000d951 + 127fc: 00010db1 .word 0x00010db1 + 12800: 00010ff9 .word 0x00010ff9 + 12804: 00010ad9 .word 0x00010ad9 + 12808: 00010be5 .word 0x00010be5 + 1280c: 00011219 .word 0x00011219 + 12810: 00005879 .word 0x00005879 + 12814: 00d4d7d9 .word 0x00d4d7d9 + 12818: 0045494d .word 0x0045494d + 1281c: 000115d9 .word 0x000115d9 + 12820: 00888888 .word 0x00888888 + 12824: 0031404f .word 0x0031404f + 12828: 00010abd .word 0x00010abd + 1282c: 00010e9d .word 0x00010e9d + 12830: 0000d969 .word 0x0000d969 + 12834: 00024272 .word 0x00024272 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_COLOR, text_color, lv_color_t, _color, nonscalar) + 12838: 4618 mov r0, r3 + 1283a: f248 1189 movw r1, #33161 ; 0x8189 + 1283e: 47b8 blx r7 + lv_style_set_bg_opa(&styles->calendar_date_nums, LV_STATE_CHECKED, IS_LIGHT ? LV_OPA_20 : LV_OPA_40); + 12840: 6a23 ldr r3, [r4, #32] + 12842: 6820 ldr r0, [r4, #0] + 12844: f013 0f02 tst.w r3, #2 +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_OPA, bg_opa, lv_opa_t, _opa, scalar) + 12848: bf14 ite ne + 1284a: 2233 movne r2, #51 ; 0x33 + 1284c: 2266 moveq r2, #102 ; 0x66 + 1284e: 4bc0 ldr r3, [pc, #768] ; (12b50 ) + 12850: f44f 7196 mov.w r1, #300 ; 0x12c + 12854: 302c adds r0, #44 ; 0x2c + 12856: 4798 blx r3 + lv_style_set_bg_opa(&styles->calendar_date_nums, LV_STATE_PRESSED, LV_OPA_20); + 12858: 6820 ldr r0, [r4, #0] + 1285a: 4bbd ldr r3, [pc, #756] ; (12b50 ) + 1285c: 2233 movs r2, #51 ; 0x33 + 1285e: f241 012c movw r1, #4140 ; 0x102c + 12862: 302c adds r0, #44 ; 0x2c + 12864: 4798 blx r3 + lv_style_set_bg_opa(&styles->calendar_date_nums, LV_STATE_FOCUSED, LV_OPA_COVER); + 12866: 6820 ldr r0, [r4, #0] + 12868: 4bb9 ldr r3, [pc, #740] ; (12b50 ) + 1286a: 22ff movs r2, #255 ; 0xff + 1286c: f44f 710b mov.w r1, #556 ; 0x22c + 12870: 302c adds r0, #44 ; 0x2c + 12872: 4798 blx r3 + lv_style_set_text_color(&styles->calendar_date_nums, LV_STATE_FOCUSED, LV_COLOR_WHITE); + 12874: f8bb 3000 ldrh.w r3, [fp] + 12878: 6820 ldr r0, [r4, #0] + 1287a: f8ad 3004 strh.w r3, [sp, #4] +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_COLOR, text_color, lv_color_t, _color, nonscalar) + 1287e: b29a uxth r2, r3 + 12880: f248 2189 movw r1, #33417 ; 0x8289 + 12884: 302c adds r0, #44 ; 0x2c + 12886: 47b8 blx r7 + lv_style_set_bg_color(&styles->calendar_date_nums, LV_STATE_FOCUSED, theme.color_primary); + 12888: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_COLOR, bg_color, lv_color_t, _color, nonscalar) + 1288a: 89a2 ldrh r2, [r4, #12] + 1288c: f240 2129 movw r1, #553 ; 0x229 + 12890: 302c adds r0, #44 ; 0x2c + 12892: 47b8 blx r7 + lv_style_set_bg_color(&styles->calendar_date_nums, LV_STATE_DEFAULT, IS_LIGHT ? lv_color_hex(0x666666) : LV_COLOR_WHITE); + 12894: 6a22 ldr r2, [r4, #32] + 12896: 6823 ldr r3, [r4, #0] + 12898: 0792 lsls r2, r2, #30 + 1289a: f103 032c add.w r3, r3, #44 ; 0x2c + 1289e: f141 8184 bpl.w 13baa + 128a2: 48ac ldr r0, [pc, #688] ; (12b54 ) + 128a4: 9301 str r3, [sp, #4] + 128a6: 47d0 blx sl + 128a8: 9b01 ldr r3, [sp, #4] + 128aa: 4602 mov r2, r0 + 128ac: 4618 mov r0, r3 + 128ae: 2129 movs r1, #41 ; 0x29 + 128b0: 47b8 blx r7 + lv_style_set_bg_color(&styles->calendar_date_nums, LV_STATE_CHECKED, theme.color_primary); + 128b2: 6820 ldr r0, [r4, #0] + 128b4: 89a2 ldrh r2, [r4, #12] + 128b6: f240 1129 movw r1, #297 ; 0x129 + 128ba: 302c adds r0, #44 ; 0x2c + 128bc: 47b8 blx r7 + lv_style_set_border_width(&styles->calendar_date_nums, LV_STATE_CHECKED, 2); + 128be: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_WIDTH, border_width, lv_style_int_t, _int, scalar) + 128c0: 2202 movs r2, #2 + 128c2: f44f 7198 mov.w r1, #304 ; 0x130 + 128c6: 302c adds r0, #44 ; 0x2c + 128c8: 47b0 blx r6 + lv_style_set_border_side(&styles->calendar_date_nums, LV_STATE_CHECKED, LV_BORDER_SIDE_LEFT); + 128ca: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_SIDE, border_side, lv_border_side_t, _int, scalar) + 128cc: 2204 movs r2, #4 + 128ce: f240 1131 movw r1, #305 ; 0x131 + 128d2: 302c adds r0, #44 ; 0x2c + 128d4: 47b0 blx r6 + lv_style_set_border_color(&styles->calendar_date_nums, LV_STATE_CHECKED, theme.color_primary); + 128d6: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_COLOR, border_color, lv_color_t, _color, nonscalar) + 128d8: 89a2 ldrh r2, [r4, #12] + 128da: f240 1139 movw r1, #313 ; 0x139 + 128de: 302c adds r0, #44 ; 0x2c + 128e0: 47b8 blx r7 + lv_style_set_pad_inner(&styles->calendar_date_nums, LV_STATE_DEFAULT, LV_DPX(3)); + 128e2: 6823 ldr r3, [r4, #0] + 128e4: 2000 movs r0, #0 + 128e6: 332c adds r3, #44 ; 0x2c + 128e8: ee08 3a10 vmov s16, r3 + 128ec: 47a8 blx r5 + 128ee: eb00 0040 add.w r0, r0, r0, lsl #1 + 128f2: 28ef cmp r0, #239 ; 0xef + 128f4: f341 815d ble.w 13bb2 + 128f8: 2000 movs r0, #0 + 128fa: 47a8 blx r5 + 128fc: 2303 movs r3, #3 + 128fe: 2250 movs r2, #80 ; 0x50 + 12900: fb00 2203 mla r2, r0, r3, r2 + 12904: 23a0 movs r3, #160 ; 0xa0 + 12906: fb92 f2f3 sdiv r2, r2, r3 + 1290a: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_INNER, pad_inner, lv_style_int_t, _int, scalar) + 1290c: ee18 0a10 vmov r0, s16 + 12910: 2114 movs r1, #20 + 12912: 47b0 blx r6 + lv_style_set_pad_left(&styles->calendar_date_nums, LV_STATE_DEFAULT, PAD_DEF); + 12914: 6823 ldr r3, [r4, #0] + 12916: 2000 movs r0, #0 + 12918: 332c adds r3, #44 ; 0x2c + 1291a: ee08 3a10 vmov s16, r3 + 1291e: 47c8 blx r9 + 12920: 2801 cmp r0, #1 + 12922: f04f 0000 mov.w r0, #0 + 12926: f201 8153 bhi.w 13bd0 + 1292a: 47a8 blx r5 + 1292c: ebc0 1000 rsb r0, r0, r0, lsl #4 + 12930: 28ef cmp r0, #239 ; 0xef + 12932: f301 8141 bgt.w 13bb8 + 12936: 2201 movs r2, #1 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_LEFT, pad_left, lv_style_int_t, _int, scalar) + 12938: ee18 0a10 vmov r0, s16 + 1293c: 2112 movs r1, #18 + 1293e: 47b0 blx r6 + lv_style_set_pad_right(&styles->calendar_date_nums, LV_STATE_DEFAULT, PAD_DEF); + 12940: 6823 ldr r3, [r4, #0] + 12942: 2000 movs r0, #0 + 12944: 332c adds r3, #44 ; 0x2c + 12946: ee08 3a10 vmov s16, r3 + 1294a: 47c8 blx r9 + 1294c: 2801 cmp r0, #1 + 1294e: f04f 0000 mov.w r0, #0 + 12952: f201 8154 bhi.w 13bfe + 12956: 47a8 blx r5 + 12958: ebc0 1000 rsb r0, r0, r0, lsl #4 + 1295c: 28ef cmp r0, #239 ; 0xef + 1295e: f301 8142 bgt.w 13be6 + 12962: 2201 movs r2, #1 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_RIGHT, pad_right, lv_style_int_t, _int, scalar) + 12964: ee18 0a10 vmov r0, s16 + 12968: 2113 movs r1, #19 + 1296a: 47b0 blx r6 + lv_style_set_pad_bottom(&styles->calendar_date_nums, LV_STATE_DEFAULT, PAD_DEF); + 1296c: 6823 ldr r3, [r4, #0] + 1296e: 2000 movs r0, #0 + 12970: 332c adds r3, #44 ; 0x2c + 12972: ee08 3a10 vmov s16, r3 + 12976: 47c8 blx r9 + 12978: 2801 cmp r0, #1 + 1297a: f04f 0000 mov.w r0, #0 + 1297e: f201 8155 bhi.w 13c2c + 12982: 47a8 blx r5 + 12984: ebc0 1000 rsb r0, r0, r0, lsl #4 + 12988: 28ef cmp r0, #239 ; 0xef + 1298a: f301 8143 bgt.w 13c14 + 1298e: 2201 movs r2, #1 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_BOTTOM, pad_bottom, lv_style_int_t, _int, scalar) + 12990: 2111 movs r1, #17 + 12992: ee18 0a10 vmov r0, s16 + 12996: 47b0 blx r6 + style_init_reset(&styles->cpicker_bg); + 12998: 6820 ldr r0, [r4, #0] + 1299a: 3038 adds r0, #56 ; 0x38 + 1299c: 47c0 blx r8 + lv_style_set_scale_width(&styles->cpicker_bg, LV_STATE_DEFAULT, LV_DPX(30)); + 1299e: 6823 ldr r3, [r4, #0] + 129a0: 2000 movs r0, #0 + 129a2: f103 0938 add.w r9, r3, #56 ; 0x38 + 129a6: 47a8 blx r5 + 129a8: ebc0 1000 rsb r0, r0, r0, lsl #4 + 129ac: 0040 lsls r0, r0, #1 + 129ae: 28ef cmp r0, #239 ; 0xef + 129b0: f341 8147 ble.w 13c42 + 129b4: 2000 movs r0, #0 + 129b6: 47a8 blx r5 + 129b8: 231e movs r3, #30 + 129ba: 2250 movs r2, #80 ; 0x50 + 129bc: fb00 2203 mla r2, r0, r3, r2 + 129c0: 23a0 movs r3, #160 ; 0xa0 + 129c2: fb92 f2f3 sdiv r2, r2, r3 + 129c6: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(SCALE_WIDTH, scale_width, lv_style_int_t, _int, scalar) + 129c8: 4648 mov r0, r9 + 129ca: 21c0 movs r1, #192 ; 0xc0 + 129cc: 47b0 blx r6 + lv_style_set_bg_opa(&styles->cpicker_bg, LV_STATE_DEFAULT, LV_OPA_COVER); + 129ce: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_OPA, bg_opa, lv_opa_t, _opa, scalar) + 129d0: 4b5f ldr r3, [pc, #380] ; (12b50 ) + 129d2: 3038 adds r0, #56 ; 0x38 + 129d4: 22ff movs r2, #255 ; 0xff + 129d6: 212c movs r1, #44 ; 0x2c + 129d8: 4798 blx r3 + lv_style_set_bg_color(&styles->cpicker_bg, LV_STATE_DEFAULT, COLOR_SCR); + 129da: 6823 ldr r3, [r4, #0] + 129dc: f103 0938 add.w r9, r3, #56 ; 0x38 + 129e0: 6a23 ldr r3, [r4, #32] + 129e2: 079b lsls r3, r3, #30 + 129e4: bf4c ite mi + 129e6: 485c ldrmi r0, [pc, #368] ; (12b58 ) + 129e8: 485c ldrpl r0, [pc, #368] ; (12b5c ) + 129ea: 47d0 blx sl +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_COLOR, bg_color, lv_color_t, _color, nonscalar) + 129ec: 2129 movs r1, #41 ; 0x29 + 129ee: 4602 mov r2, r0 + 129f0: 4648 mov r0, r9 + 129f2: 47b8 blx r7 + lv_style_set_pad_inner(&styles->cpicker_bg, LV_STATE_DEFAULT, LV_DPX(20)); + 129f4: 6823 ldr r3, [r4, #0] + 129f6: 2000 movs r0, #0 + 129f8: f103 0938 add.w r9, r3, #56 ; 0x38 + 129fc: 47a8 blx r5 + 129fe: eb00 0080 add.w r0, r0, r0, lsl #2 + 12a02: 0080 lsls r0, r0, #2 + 12a04: 28ef cmp r0, #239 ; 0xef + 12a06: f341 811f ble.w 13c48 + 12a0a: 2000 movs r0, #0 + 12a0c: 47a8 blx r5 + 12a0e: 2314 movs r3, #20 + 12a10: 2250 movs r2, #80 ; 0x50 + 12a12: fb00 2203 mla r2, r0, r3, r2 + 12a16: 23a0 movs r3, #160 ; 0xa0 + 12a18: fb92 f2f3 sdiv r2, r2, r3 + 12a1c: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_INNER, pad_inner, lv_style_int_t, _int, scalar) + 12a1e: 4648 mov r0, r9 + 12a20: 2114 movs r1, #20 + 12a22: 47b0 blx r6 + lv_style_set_radius(&styles->cpicker_bg, LV_STATE_DEFAULT, LV_RADIUS_CIRCLE); + 12a24: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_OPA, bg_opa, lv_opa_t, _opa, scalar) + 12a26: f8df 9128 ldr.w r9, [pc, #296] ; 12b50 +_LV_OBJ_STYLE_SET_GET_DECLARE(RADIUS, radius, lv_style_int_t, _int, scalar) + 12a2a: f647 72ff movw r2, #32767 ; 0x7fff + 12a2e: 2101 movs r1, #1 + 12a30: 3038 adds r0, #56 ; 0x38 + 12a32: 47b0 blx r6 + style_init_reset(&styles->cpicker_indic); + 12a34: 6820 ldr r0, [r4, #0] + 12a36: 303c adds r0, #60 ; 0x3c + 12a38: 47c0 blx r8 + lv_style_set_radius(&styles->cpicker_indic, LV_STATE_DEFAULT, LV_RADIUS_CIRCLE); + 12a3a: 6820 ldr r0, [r4, #0] + 12a3c: f647 72ff movw r2, #32767 ; 0x7fff + 12a40: 2101 movs r1, #1 + 12a42: 303c adds r0, #60 ; 0x3c + 12a44: 47b0 blx r6 + lv_style_set_bg_color(&styles->cpicker_indic, LV_STATE_DEFAULT, LV_COLOR_WHITE); + 12a46: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_COLOR, bg_color, lv_color_t, _color, nonscalar) + 12a48: f8bb 2000 ldrh.w r2, [fp] + 12a4c: 2129 movs r1, #41 ; 0x29 + 12a4e: 303c adds r0, #60 ; 0x3c + 12a50: 47b8 blx r7 + lv_style_set_bg_opa(&styles->cpicker_indic, LV_STATE_DEFAULT, LV_OPA_COVER); + 12a52: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_OPA, bg_opa, lv_opa_t, _opa, scalar) + 12a54: 22ff movs r2, #255 ; 0xff + 12a56: 212c movs r1, #44 ; 0x2c + 12a58: 303c adds r0, #60 ; 0x3c + 12a5a: 47c8 blx r9 + lv_style_set_border_width(&styles->cpicker_indic, LV_STATE_DEFAULT, 2); + 12a5c: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_WIDTH, border_width, lv_style_int_t, _int, scalar) + 12a5e: 2202 movs r2, #2 + 12a60: 2130 movs r1, #48 ; 0x30 + 12a62: 303c adds r0, #60 ; 0x3c + 12a64: 47b0 blx r6 + lv_style_set_border_color(&styles->cpicker_indic, LV_STATE_DEFAULT, LV_COLOR_GRAY); + 12a66: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_COLOR, border_color, lv_color_t, _color, nonscalar) + 12a68: f8bb 2002 ldrh.w r2, [fp, #2] + 12a6c: 2139 movs r1, #57 ; 0x39 + 12a6e: 303c adds r0, #60 ; 0x3c + 12a70: 47b8 blx r7 + lv_style_set_border_color(&styles->cpicker_indic, LV_STATE_FOCUSED, theme.color_primary); + 12a72: 6820 ldr r0, [r4, #0] + 12a74: 89a2 ldrh r2, [r4, #12] + 12a76: f240 2139 movw r1, #569 ; 0x239 + 12a7a: 303c adds r0, #60 ; 0x3c + 12a7c: 47b8 blx r7 + lv_style_set_border_color(&styles->cpicker_indic, LV_STATE_EDITED, theme.color_secondary); + 12a7e: 6820 ldr r0, [r4, #0] + 12a80: 89e2 ldrh r2, [r4, #14] + 12a82: f240 4139 movw r1, #1081 ; 0x439 + 12a86: 303c adds r0, #60 ; 0x3c + 12a88: 47b8 blx r7 + lv_style_set_pad_left(&styles->cpicker_indic, LV_STATE_DEFAULT, LV_DPX(13)); + 12a8a: 6823 ldr r3, [r4, #0] + 12a8c: 2000 movs r0, #0 + 12a8e: f103 0a3c add.w sl, r3, #60 ; 0x3c + 12a92: 47a8 blx r5 + 12a94: eb00 0340 add.w r3, r0, r0, lsl #1 + 12a98: eb00 0083 add.w r0, r0, r3, lsl #2 + 12a9c: 28ef cmp r0, #239 ; 0xef + 12a9e: f341 80d6 ble.w 13c4e + 12aa2: 2000 movs r0, #0 + 12aa4: 47a8 blx r5 + 12aa6: 230d movs r3, #13 + 12aa8: 2250 movs r2, #80 ; 0x50 + 12aaa: fb00 2203 mla r2, r0, r3, r2 + 12aae: 23a0 movs r3, #160 ; 0xa0 + 12ab0: fb92 f2f3 sdiv r2, r2, r3 + 12ab4: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_LEFT, pad_left, lv_style_int_t, _int, scalar) + 12ab6: 4650 mov r0, sl + 12ab8: 2112 movs r1, #18 + 12aba: 47b0 blx r6 + lv_style_set_pad_right(&styles->cpicker_indic, LV_STATE_DEFAULT, LV_DPX(13)); + 12abc: 6823 ldr r3, [r4, #0] + 12abe: 2000 movs r0, #0 + 12ac0: f103 0a3c add.w sl, r3, #60 ; 0x3c + 12ac4: 47a8 blx r5 + 12ac6: eb00 0340 add.w r3, r0, r0, lsl #1 + 12aca: eb00 0083 add.w r0, r0, r3, lsl #2 + 12ace: 28ef cmp r0, #239 ; 0xef + 12ad0: f341 80c0 ble.w 13c54 + 12ad4: 2000 movs r0, #0 + 12ad6: 47a8 blx r5 + 12ad8: 230d movs r3, #13 + 12ada: 2250 movs r2, #80 ; 0x50 + 12adc: fb00 2203 mla r2, r0, r3, r2 + 12ae0: 23a0 movs r3, #160 ; 0xa0 + 12ae2: fb92 f2f3 sdiv r2, r2, r3 + 12ae6: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_RIGHT, pad_right, lv_style_int_t, _int, scalar) + 12ae8: 4650 mov r0, sl + 12aea: 2113 movs r1, #19 + 12aec: 47b0 blx r6 + lv_style_set_pad_top(&styles->cpicker_indic, LV_STATE_DEFAULT, LV_DPX(13)); + 12aee: 6823 ldr r3, [r4, #0] + 12af0: 2000 movs r0, #0 + 12af2: f103 0a3c add.w sl, r3, #60 ; 0x3c + 12af6: 47a8 blx r5 + 12af8: eb00 0340 add.w r3, r0, r0, lsl #1 + 12afc: eb00 0083 add.w r0, r0, r3, lsl #2 + 12b00: 28ef cmp r0, #239 ; 0xef + 12b02: f341 80aa ble.w 13c5a + 12b06: 2000 movs r0, #0 + 12b08: 47a8 blx r5 + 12b0a: 230d movs r3, #13 + 12b0c: 2250 movs r2, #80 ; 0x50 + 12b0e: fb00 2203 mla r2, r0, r3, r2 + 12b12: 23a0 movs r3, #160 ; 0xa0 + 12b14: fb92 f2f3 sdiv r2, r2, r3 + 12b18: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_TOP, pad_top, lv_style_int_t, _int, scalar) + 12b1a: 4650 mov r0, sl + 12b1c: 2110 movs r1, #16 + 12b1e: 47b0 blx r6 + lv_style_set_pad_bottom(&styles->cpicker_indic, LV_STATE_DEFAULT, LV_DPX(13)); + 12b20: 6823 ldr r3, [r4, #0] + 12b22: 2000 movs r0, #0 + 12b24: f103 0a3c add.w sl, r3, #60 ; 0x3c + 12b28: 47a8 blx r5 + 12b2a: eb00 0340 add.w r3, r0, r0, lsl #1 + 12b2e: eb00 0083 add.w r0, r0, r3, lsl #2 + 12b32: 28ef cmp r0, #239 ; 0xef + 12b34: f341 8094 ble.w 13c60 + 12b38: 2000 movs r0, #0 + 12b3a: 47a8 blx r5 + 12b3c: 230d movs r3, #13 + 12b3e: 2250 movs r2, #80 ; 0x50 + 12b40: fb00 2203 mla r2, r0, r3, r2 + 12b44: 23a0 movs r3, #160 ; 0xa0 + 12b46: fb92 f2f3 sdiv r2, r2, r3 + 12b4a: b212 sxth r2, r2 + 12b4c: e008 b.n 12b60 + 12b4e: bf00 nop + 12b50: 00005a19 .word 0x00005a19 + 12b54: 00666666 .word 0x00666666 + 12b58: 00eaeff3 .word 0x00eaeff3 + 12b5c: 00444b5a .word 0x00444b5a +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_BOTTOM, pad_bottom, lv_style_int_t, _int, scalar) + 12b60: 2111 movs r1, #17 + 12b62: 4650 mov r0, sl + 12b64: 47b0 blx r6 + style_init_reset(&styles->cb_bg); + 12b66: 6820 ldr r0, [r4, #0] + 12b68: 304c adds r0, #76 ; 0x4c + 12b6a: 47c0 blx r8 + lv_style_set_radius(&styles->cb_bg, LV_STATE_DEFAULT, LV_DPX(4)); + 12b6c: 6823 ldr r3, [r4, #0] + 12b6e: 2000 movs r0, #0 + 12b70: f103 084c add.w r8, r3, #76 ; 0x4c + 12b74: 47a8 blx r5 + 12b76: 283b cmp r0, #59 ; 0x3b + 12b78: f341 8075 ble.w 13c66 + 12b7c: 2000 movs r0, #0 + 12b7e: 47a8 blx r5 + 12b80: 2328 movs r3, #40 ; 0x28 + 12b82: f100 0214 add.w r2, r0, #20 + 12b86: fb92 f2f3 sdiv r2, r2, r3 + 12b8a: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(RADIUS, radius, lv_style_int_t, _int, scalar) + 12b8c: 4640 mov r0, r8 + 12b8e: 2101 movs r1, #1 + 12b90: 47b0 blx r6 + lv_style_set_pad_inner(&styles->cb_bg, LV_STATE_DEFAULT, LV_DPX(10)); + 12b92: 6823 ldr r3, [r4, #0] + 12b94: 2000 movs r0, #0 + 12b96: f103 084c add.w r8, r3, #76 ; 0x4c + 12b9a: 47a8 blx r5 + 12b9c: eb00 0080 add.w r0, r0, r0, lsl #2 + 12ba0: 0040 lsls r0, r0, #1 + 12ba2: 28ef cmp r0, #239 ; 0xef + 12ba4: f341 8062 ble.w 13c6c + 12ba8: 2000 movs r0, #0 + 12baa: 47a8 blx r5 + 12bac: 230a movs r3, #10 + 12bae: 2250 movs r2, #80 ; 0x50 + 12bb0: fb00 2203 mla r2, r0, r3, r2 + 12bb4: 23a0 movs r3, #160 ; 0xa0 + 12bb6: fb92 f2f3 sdiv r2, r2, r3 + 12bba: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_INNER, pad_inner, lv_style_int_t, _int, scalar) + 12bbc: 2114 movs r1, #20 + 12bbe: 4640 mov r0, r8 + 12bc0: 47b0 blx r6 + lv_style_set_outline_color(&styles->cb_bg, LV_STATE_DEFAULT, theme.color_primary); + 12bc2: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(OUTLINE_COLOR, outline_color, lv_color_t, _color, nonscalar) + 12bc4: 89a2 ldrh r2, [r4, #12] + 12bc6: 2149 movs r1, #73 ; 0x49 + 12bc8: 304c adds r0, #76 ; 0x4c + 12bca: 47b8 blx r7 + lv_style_set_outline_opa(&styles->cb_bg, LV_STATE_DEFAULT, LV_OPA_TRANSP); + 12bcc: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(OUTLINE_OPA, outline_opa, lv_opa_t, _opa, scalar) + 12bce: 214c movs r1, #76 ; 0x4c + 12bd0: 4408 add r0, r1 + 12bd2: 2200 movs r2, #0 + 12bd4: 47c8 blx r9 + lv_style_set_outline_opa(&styles->cb_bg, LV_STATE_FOCUSED, LV_OPA_50); + 12bd6: 6820 ldr r0, [r4, #0] + 12bd8: 227f movs r2, #127 ; 0x7f + 12bda: f44f 7113 mov.w r1, #588 ; 0x24c + 12bde: 304c adds r0, #76 ; 0x4c + 12be0: 47c8 blx r9 + lv_style_set_outline_width(&styles->cb_bg, LV_STATE_DEFAULT, LV_DPX(3)); + 12be2: 2000 movs r0, #0 + 12be4: 6824 ldr r4, [r4, #0] + 12be6: 47a8 blx r5 + 12be8: eb00 0040 add.w r0, r0, r0, lsl #1 + 12bec: 28ef cmp r0, #239 ; 0xef + 12bee: f104 044c add.w r4, r4, #76 ; 0x4c + 12bf2: f341 803e ble.w 13c72 + 12bf6: 2000 movs r0, #0 + 12bf8: 47a8 blx r5 + 12bfa: 2303 movs r3, #3 + 12bfc: 2250 movs r2, #80 ; 0x50 + 12bfe: fb00 2203 mla r2, r0, r3, r2 + 12c02: 23a0 movs r3, #160 ; 0xa0 + 12c04: fb92 f2f3 sdiv r2, r2, r3 + 12c08: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(OUTLINE_WIDTH, outline_width, lv_style_int_t, _int, scalar) + 12c0a: 4620 mov r0, r4 + 12c0c: 2140 movs r1, #64 ; 0x40 + lv_style_set_outline_pad(&styles->cb_bg, LV_STATE_DEFAULT, LV_DPX(10)); + 12c0e: 4cbf ldr r4, [pc, #764] ; (12f0c ) + 12c10: 47b0 blx r6 + 12c12: 2000 movs r0, #0 + 12c14: 6827 ldr r7, [r4, #0] + 12c16: 47a8 blx r5 + 12c18: eb00 0080 add.w r0, r0, r0, lsl #2 + 12c1c: 0040 lsls r0, r0, #1 + 12c1e: 28ef cmp r0, #239 ; 0xef + 12c20: f107 074c add.w r7, r7, #76 ; 0x4c + 12c24: f341 8028 ble.w 13c78 + 12c28: 2000 movs r0, #0 + 12c2a: 47a8 blx r5 + 12c2c: 230a movs r3, #10 + 12c2e: 2250 movs r2, #80 ; 0x50 + 12c30: fb00 2203 mla r2, r0, r3, r2 + 12c34: 23a0 movs r3, #160 ; 0xa0 + 12c36: fb92 f2f3 sdiv r2, r2, r3 + 12c3a: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(OUTLINE_PAD, outline_pad, lv_style_int_t, _int, scalar) + 12c3c: 2141 movs r1, #65 ; 0x41 + 12c3e: 4638 mov r0, r7 + 12c40: 47b0 blx r6 + lv_style_set_transition_time(&styles->cb_bg, LV_STATE_DEFAULT, TRANSITION_TIME); + 12c42: 6820 ldr r0, [r4, #0] + lv_style_set_radius(&styles->cb_bullet, LV_STATE_DEFAULT, LV_DPX(4)); + 12c44: f8df 82e4 ldr.w r8, [pc, #740] ; 12f2c +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSITION_TIME, transition_time, lv_style_int_t, _int, scalar) + 12c48: 2296 movs r2, #150 ; 0x96 + 12c4a: 21b0 movs r1, #176 ; 0xb0 + 12c4c: 304c adds r0, #76 ; 0x4c + 12c4e: 47b0 blx r6 + lv_style_set_transition_prop_6(&styles->cb_bg, LV_STATE_DEFAULT, LV_STYLE_OUTLINE_OPA); + 12c50: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSITION_PROP_6, transition_prop_6, lv_style_int_t, _int, scalar) + 12c52: 224c movs r2, #76 ; 0x4c + 12c54: 4410 add r0, r2 + 12c56: 21b7 movs r1, #183 ; 0xb7 + 12c58: 47b0 blx r6 + style_init_reset(&styles->cb_bullet); + 12c5a: 6820 ldr r0, [r4, #0] + 12c5c: 4eac ldr r6, [pc, #688] ; (12f10 ) + 12c5e: 3050 adds r0, #80 ; 0x50 + 12c60: 47b0 blx r6 + lv_style_set_outline_opa(&styles->cb_bullet, LV_STATE_FOCUSED, LV_OPA_TRANSP); + 12c62: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(OUTLINE_OPA, outline_opa, lv_opa_t, _opa, scalar) + 12c64: 2200 movs r2, #0 + 12c66: f44f 7113 mov.w r1, #588 ; 0x24c + 12c6a: 3050 adds r0, #80 ; 0x50 + 12c6c: 47c8 blx r9 + lv_style_set_radius(&styles->cb_bullet, LV_STATE_DEFAULT, LV_DPX(4)); + 12c6e: 2000 movs r0, #0 + 12c70: 6825 ldr r5, [r4, #0] + 12c72: 47c0 blx r8 + 12c74: 283b cmp r0, #59 ; 0x3b + 12c76: f105 0550 add.w r5, r5, #80 ; 0x50 + 12c7a: 46b2 mov sl, r6 + 12c7c: f341 8012 ble.w 13ca4 + 12c80: 2000 movs r0, #0 + 12c82: 47c0 blx r8 + 12c84: 2328 movs r3, #40 ; 0x28 + 12c86: f100 0214 add.w r2, r0, #20 + 12c8a: fb92 f2f3 sdiv r2, r2, r3 + 12c8e: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(RADIUS, radius, lv_style_int_t, _int, scalar) + 12c90: 4628 mov r0, r5 + 12c92: 2101 movs r1, #1 + 12c94: 4d9f ldr r5, [pc, #636] ; (12f14 ) +_LV_OBJ_STYLE_SET_GET_DECLARE(PATTERN_IMAGE, pattern_image, const void *, _ptr, scalar) + 12c96: 4fa0 ldr r7, [pc, #640] ; (12f18 ) +_LV_OBJ_STYLE_SET_GET_DECLARE(PATTERN_RECOLOR, pattern_recolor, lv_color_t, _color, nonscalar) + 12c98: 4ea0 ldr r6, [pc, #640] ; (12f1c ) +_LV_OBJ_STYLE_SET_GET_DECLARE(RADIUS, radius, lv_style_int_t, _int, scalar) + 12c9a: 47a8 blx r5 + lv_style_set_pattern_image(&styles->cb_bullet, LV_STATE_CHECKED, LV_SYMBOL_OK); + 12c9c: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(PATTERN_IMAGE, pattern_image, const void *, _ptr, scalar) + 12c9e: 4aa0 ldr r2, [pc, #640] ; (12f20 ) + 12ca0: f44f 71b7 mov.w r1, #366 ; 0x16e + 12ca4: 3050 adds r0, #80 ; 0x50 + 12ca6: 47b8 blx r7 + lv_style_set_pattern_recolor(&styles->cb_bullet, LV_STATE_CHECKED, LV_COLOR_WHITE); + 12ca8: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(PATTERN_RECOLOR, pattern_recolor, lv_color_t, _color, nonscalar) + 12caa: f8bb 2000 ldrh.w r2, [fp] + 12cae: f240 1169 movw r1, #361 ; 0x169 + 12cb2: 3050 adds r0, #80 ; 0x50 + 12cb4: 47b0 blx r6 + lv_style_set_text_font(&styles->cb_bullet, LV_STATE_CHECKED, theme.font_small); + 12cb6: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_FONT, text_font, const lv_font_t *, _ptr, scalar) + 12cb8: 6922 ldr r2, [r4, #16] + 12cba: f248 118e movw r1, #33166 ; 0x818e + 12cbe: 3050 adds r0, #80 ; 0x50 + 12cc0: 47b8 blx r7 + lv_style_set_pad_left(&styles->cb_bullet, LV_STATE_DEFAULT, LV_DPX(3)); + 12cc2: 2000 movs r0, #0 + 12cc4: 6827 ldr r7, [r4, #0] + 12cc6: 47c0 blx r8 + 12cc8: eb00 0040 add.w r0, r0, r0, lsl #1 + 12ccc: 28ef cmp r0, #239 ; 0xef + 12cce: f107 0750 add.w r7, r7, #80 ; 0x50 + 12cd2: f340 87ea ble.w 13caa + 12cd6: 2000 movs r0, #0 + 12cd8: 47c0 blx r8 + 12cda: 2303 movs r3, #3 + 12cdc: 2250 movs r2, #80 ; 0x50 + 12cde: fb00 2203 mla r2, r0, r3, r2 + 12ce2: 23a0 movs r3, #160 ; 0xa0 + 12ce4: fb92 f2f3 sdiv r2, r2, r3 + 12ce8: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_LEFT, pad_left, lv_style_int_t, _int, scalar) + 12cea: 4638 mov r0, r7 + 12cec: 2112 movs r1, #18 + 12cee: 47a8 blx r5 + lv_style_set_pad_right(&styles->cb_bullet, LV_STATE_DEFAULT, LV_DPX(3)); + 12cf0: 2000 movs r0, #0 + 12cf2: 6827 ldr r7, [r4, #0] + 12cf4: 47c0 blx r8 + 12cf6: eb00 0040 add.w r0, r0, r0, lsl #1 + 12cfa: 28ef cmp r0, #239 ; 0xef + 12cfc: f107 0750 add.w r7, r7, #80 ; 0x50 + 12d00: f340 87d6 ble.w 13cb0 + 12d04: 2000 movs r0, #0 + 12d06: 47c0 blx r8 + 12d08: 2303 movs r3, #3 + 12d0a: 2250 movs r2, #80 ; 0x50 + 12d0c: fb00 2203 mla r2, r0, r3, r2 + 12d10: 23a0 movs r3, #160 ; 0xa0 + 12d12: fb92 f2f3 sdiv r2, r2, r3 + 12d16: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_RIGHT, pad_right, lv_style_int_t, _int, scalar) + 12d18: 4638 mov r0, r7 + 12d1a: 2113 movs r1, #19 + 12d1c: 47a8 blx r5 + lv_style_set_pad_top(&styles->cb_bullet, LV_STATE_DEFAULT, LV_DPX(3)); + 12d1e: 2000 movs r0, #0 + 12d20: 6827 ldr r7, [r4, #0] + 12d22: 47c0 blx r8 + 12d24: eb00 0040 add.w r0, r0, r0, lsl #1 + 12d28: 28ef cmp r0, #239 ; 0xef + 12d2a: f107 0750 add.w r7, r7, #80 ; 0x50 + 12d2e: f340 87c2 ble.w 13cb6 + 12d32: 2000 movs r0, #0 + 12d34: 47c0 blx r8 + 12d36: 2303 movs r3, #3 + 12d38: 2250 movs r2, #80 ; 0x50 + 12d3a: fb00 2203 mla r2, r0, r3, r2 + 12d3e: 23a0 movs r3, #160 ; 0xa0 + 12d40: fb92 f2f3 sdiv r2, r2, r3 + 12d44: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_TOP, pad_top, lv_style_int_t, _int, scalar) + 12d46: 4638 mov r0, r7 + 12d48: 2110 movs r1, #16 + 12d4a: 47a8 blx r5 + lv_style_set_pad_bottom(&styles->cb_bullet, LV_STATE_DEFAULT, LV_DPX(3)); + 12d4c: 2000 movs r0, #0 + 12d4e: 6827 ldr r7, [r4, #0] + 12d50: 47c0 blx r8 + 12d52: eb00 0040 add.w r0, r0, r0, lsl #1 + 12d56: 28ef cmp r0, #239 ; 0xef + 12d58: f107 0750 add.w r7, r7, #80 ; 0x50 + 12d5c: f340 87ae ble.w 13cbc + 12d60: 2000 movs r0, #0 + 12d62: 47c0 blx r8 + 12d64: 2303 movs r3, #3 + 12d66: 2250 movs r2, #80 ; 0x50 + 12d68: fb00 2203 mla r2, r0, r3, r2 + 12d6c: 23a0 movs r3, #160 ; 0xa0 + 12d6e: fb92 f2f3 sdiv r2, r2, r3 + 12d72: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_BOTTOM, pad_bottom, lv_style_int_t, _int, scalar) + 12d74: 2111 movs r1, #17 + 12d76: 4638 mov r0, r7 + 12d78: 47a8 blx r5 + style_init_reset(&styles->kb_bg); + 12d7a: 6820 ldr r0, [r4, #0] + 12d7c: 3068 adds r0, #104 ; 0x68 + 12d7e: 47d0 blx sl + lv_style_set_radius(&styles->kb_bg, LV_STATE_DEFAULT, 0); + 12d80: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(RADIUS, radius, lv_style_int_t, _int, scalar) + 12d82: 2200 movs r2, #0 + 12d84: 2101 movs r1, #1 + 12d86: 3068 adds r0, #104 ; 0x68 + 12d88: 47a8 blx r5 + lv_style_set_border_width(&styles->kb_bg, LV_STATE_DEFAULT, LV_DPX(4)); + 12d8a: 2000 movs r0, #0 + 12d8c: 6827 ldr r7, [r4, #0] + 12d8e: 47c0 blx r8 + 12d90: 283b cmp r0, #59 ; 0x3b + 12d92: f107 0768 add.w r7, r7, #104 ; 0x68 + 12d96: f340 8794 ble.w 13cc2 + 12d9a: 2000 movs r0, #0 + 12d9c: 47c0 blx r8 + 12d9e: 2328 movs r3, #40 ; 0x28 + 12da0: f100 0214 add.w r2, r0, #20 + 12da4: fb92 f2f3 sdiv r2, r2, r3 + 12da8: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_WIDTH, border_width, lv_style_int_t, _int, scalar) + 12daa: 4638 mov r0, r7 + 12dac: 2130 movs r1, #48 ; 0x30 + 12dae: 47a8 blx r5 + lv_style_set_border_side(&styles->kb_bg, LV_STATE_DEFAULT, LV_BORDER_SIDE_TOP); + 12db0: 6820 ldr r0, [r4, #0] + 12db2: 4f5c ldr r7, [pc, #368] ; (12f24 ) +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_SIDE, border_side, lv_border_side_t, _int, scalar) + 12db4: 3068 adds r0, #104 ; 0x68 + 12db6: 2202 movs r2, #2 + 12db8: 2131 movs r1, #49 ; 0x31 + 12dba: 47a8 blx r5 + lv_style_set_border_color(&styles->kb_bg, LV_STATE_DEFAULT, IS_LIGHT ? COLOR_BG_TEXT : LV_COLOR_BLACK); + 12dbc: 6a20 ldr r0, [r4, #32] + 12dbe: 6823 ldr r3, [r4, #0] + 12dc0: f010 0002 ands.w r0, r0, #2 + 12dc4: f103 0b68 add.w fp, r3, #104 ; 0x68 + 12dc8: f000 877e beq.w 13cc8 + 12dcc: 4856 ldr r0, [pc, #344] ; (12f28 ) + 12dce: 47b8 blx r7 + 12dd0: f000 021f and.w r2, r0, #31 + 12dd4: f3c0 1345 ubfx r3, r0, #5, #6 + 12dd8: f3c0 20c4 ubfx r0, r0, #11, #5 +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_COLOR, border_color, lv_color_t, _color, nonscalar) + 12ddc: ea42 1243 orr.w r2, r2, r3, lsl #5 + 12de0: ea42 22c0 orr.w r2, r2, r0, lsl #11 + 12de4: 2139 movs r1, #57 ; 0x39 + 12de6: 4658 mov r0, fp + 12de8: 47b0 blx r6 + lv_style_set_border_color(&styles->kb_bg, LV_STATE_EDITED, theme.color_secondary); + 12dea: 6820 ldr r0, [r4, #0] + 12dec: 89e2 ldrh r2, [r4, #14] + 12dee: f240 4139 movw r1, #1081 ; 0x439 + 12df2: 3068 adds r0, #104 ; 0x68 + 12df4: 47b0 blx r6 + lv_style_set_pad_left(&styles->kb_bg, LV_STATE_DEFAULT, LV_DPX(5)); + 12df6: 6823 ldr r3, [r4, #0] + 12df8: 2000 movs r0, #0 + 12dfa: f103 0b68 add.w fp, r3, #104 ; 0x68 + 12dfe: 47c0 blx r8 + 12e00: eb00 0080 add.w r0, r0, r0, lsl #2 + 12e04: 28ef cmp r0, #239 ; 0xef + 12e06: f340 8763 ble.w 13cd0 + 12e0a: 2000 movs r0, #0 + 12e0c: 47c0 blx r8 + 12e0e: 2305 movs r3, #5 + 12e10: 2250 movs r2, #80 ; 0x50 + 12e12: fb00 2203 mla r2, r0, r3, r2 + 12e16: 23a0 movs r3, #160 ; 0xa0 + 12e18: fb92 f2f3 sdiv r2, r2, r3 + 12e1c: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_LEFT, pad_left, lv_style_int_t, _int, scalar) + 12e1e: 4658 mov r0, fp + 12e20: 2112 movs r1, #18 + 12e22: 47a8 blx r5 + lv_style_set_pad_right(&styles->kb_bg, LV_STATE_DEFAULT, LV_DPX(5)); + 12e24: 6823 ldr r3, [r4, #0] + 12e26: 2000 movs r0, #0 + 12e28: f103 0b68 add.w fp, r3, #104 ; 0x68 + 12e2c: 47c0 blx r8 + 12e2e: eb00 0080 add.w r0, r0, r0, lsl #2 + 12e32: 28ef cmp r0, #239 ; 0xef + 12e34: f340 874f ble.w 13cd6 + 12e38: 2000 movs r0, #0 + 12e3a: 47c0 blx r8 + 12e3c: 2305 movs r3, #5 + 12e3e: 2250 movs r2, #80 ; 0x50 + 12e40: fb00 2203 mla r2, r0, r3, r2 + 12e44: 23a0 movs r3, #160 ; 0xa0 + 12e46: fb92 f2f3 sdiv r2, r2, r3 + 12e4a: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_RIGHT, pad_right, lv_style_int_t, _int, scalar) + 12e4c: 4658 mov r0, fp + 12e4e: 2113 movs r1, #19 + 12e50: 47a8 blx r5 + lv_style_set_pad_top(&styles->kb_bg, LV_STATE_DEFAULT, LV_DPX(5)); + 12e52: 6823 ldr r3, [r4, #0] + 12e54: 2000 movs r0, #0 + 12e56: f103 0b68 add.w fp, r3, #104 ; 0x68 + 12e5a: 47c0 blx r8 + 12e5c: eb00 0080 add.w r0, r0, r0, lsl #2 + 12e60: 28ef cmp r0, #239 ; 0xef + 12e62: f340 873b ble.w 13cdc + 12e66: 2000 movs r0, #0 + 12e68: 47c0 blx r8 + 12e6a: 2305 movs r3, #5 + 12e6c: 2250 movs r2, #80 ; 0x50 + 12e6e: fb00 2203 mla r2, r0, r3, r2 + 12e72: 23a0 movs r3, #160 ; 0xa0 + 12e74: fb92 f2f3 sdiv r2, r2, r3 + 12e78: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_TOP, pad_top, lv_style_int_t, _int, scalar) + 12e7a: 4658 mov r0, fp + 12e7c: 2110 movs r1, #16 + 12e7e: 47a8 blx r5 + lv_style_set_pad_bottom(&styles->kb_bg, LV_STATE_DEFAULT, LV_DPX(5)); + 12e80: 6823 ldr r3, [r4, #0] + 12e82: 2000 movs r0, #0 + 12e84: f103 0b68 add.w fp, r3, #104 ; 0x68 + 12e88: 47c0 blx r8 + 12e8a: eb00 0080 add.w r0, r0, r0, lsl #2 + 12e8e: 28ef cmp r0, #239 ; 0xef + 12e90: f340 8727 ble.w 13ce2 + 12e94: 2000 movs r0, #0 + 12e96: 47c0 blx r8 + 12e98: 2305 movs r3, #5 + 12e9a: 2250 movs r2, #80 ; 0x50 + 12e9c: fb00 2203 mla r2, r0, r3, r2 + 12ea0: 23a0 movs r3, #160 ; 0xa0 + 12ea2: fb92 f2f3 sdiv r2, r2, r3 + 12ea6: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_BOTTOM, pad_bottom, lv_style_int_t, _int, scalar) + 12ea8: 4658 mov r0, fp + 12eaa: 2111 movs r1, #17 + 12eac: 47a8 blx r5 + lv_style_set_pad_inner(&styles->kb_bg, LV_STATE_DEFAULT, LV_DPX(3)); + 12eae: 6823 ldr r3, [r4, #0] + 12eb0: 2000 movs r0, #0 + 12eb2: f103 0b68 add.w fp, r3, #104 ; 0x68 + 12eb6: 47c0 blx r8 + 12eb8: eb00 0040 add.w r0, r0, r0, lsl #1 + 12ebc: 28ef cmp r0, #239 ; 0xef + 12ebe: f340 8713 ble.w 13ce8 + 12ec2: 2000 movs r0, #0 + 12ec4: 47c0 blx r8 + 12ec6: 2303 movs r3, #3 + 12ec8: 2250 movs r2, #80 ; 0x50 + 12eca: fb00 2203 mla r2, r0, r3, r2 + 12ece: 23a0 movs r3, #160 ; 0xa0 + 12ed0: fb92 f2f3 sdiv r2, r2, r3 + 12ed4: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_INNER, pad_inner, lv_style_int_t, _int, scalar) + 12ed6: 2114 movs r1, #20 + 12ed8: 4658 mov r0, fp + 12eda: 47a8 blx r5 + style_init_reset(&styles->mbox_bg); + 12edc: 6820 ldr r0, [r4, #0] + 12ede: 307c adds r0, #124 ; 0x7c + 12ee0: 47d0 blx sl + lv_style_set_shadow_width(&styles->mbox_bg, LV_STATE_DEFAULT, LV_DPX(50)); + 12ee2: 6823 ldr r3, [r4, #0] + 12ee4: 2000 movs r0, #0 + 12ee6: f103 0b7c add.w fp, r3, #124 ; 0x7c + 12eea: 47c0 blx r8 + 12eec: 2332 movs r3, #50 ; 0x32 + 12eee: 4358 muls r0, r3 + 12ef0: 28ef cmp r0, #239 ; 0xef + 12ef2: f340 86fc ble.w 13cee + 12ef6: 2000 movs r0, #0 + 12ef8: 47c0 blx r8 + 12efa: 2332 movs r3, #50 ; 0x32 + 12efc: 2250 movs r2, #80 ; 0x50 + 12efe: fb00 2203 mla r2, r0, r3, r2 + 12f02: 23a0 movs r3, #160 ; 0xa0 + 12f04: fb92 f2f3 sdiv r2, r2, r3 + 12f08: b212 sxth r2, r2 + 12f0a: e011 b.n 12f30 + 12f0c: 2000c7d4 .word 0x2000c7d4 + 12f10: 00010abd .word 0x00010abd + 12f14: 00005879 .word 0x00005879 + 12f18: 00005aed .word 0x00005aed + 12f1c: 00005949 .word 0x00005949 + 12f20: 0002426e .word 0x0002426e + 12f24: 00010e9d .word 0x00010e9d + 12f28: 003b3e42 .word 0x003b3e42 + 12f2c: 0000d951 .word 0x0000d951 +_LV_OBJ_STYLE_SET_GET_DECLARE(SHADOW_WIDTH, shadow_width, lv_style_int_t, _int, scalar) + 12f30: 4658 mov r0, fp + 12f32: 2150 movs r1, #80 ; 0x50 + 12f34: 47a8 blx r5 + lv_style_set_shadow_color(&styles->mbox_bg, LV_STATE_DEFAULT, IS_LIGHT ? LV_COLOR_SILVER : lv_color_hex3(0x999)); + 12f36: 6823 ldr r3, [r4, #0] + 12f38: f103 0b7c add.w fp, r3, #124 ; 0x7c + 12f3c: 6a23 ldr r3, [r4, #32] + 12f3e: 0798 lsls r0, r3, #30 + 12f40: f140 86d8 bpl.w 13cf4 + 12f44: 4bb6 ldr r3, [pc, #728] ; (13220 ) + 12f46: 889a ldrh r2, [r3, #4] +_LV_OBJ_STYLE_SET_GET_DECLARE(SHADOW_COLOR, shadow_color, lv_color_t, _color, nonscalar) + 12f48: 2159 movs r1, #89 ; 0x59 + 12f4a: 4658 mov r0, fp + 12f4c: 47b0 blx r6 + style_init_reset(&styles->sb); + 12f4e: 6820 ldr r0, [r4, #0] + 12f50: 3080 adds r0, #128 ; 0x80 + 12f52: 47d0 blx sl + lv_style_set_bg_opa(&styles->sb, LV_STATE_DEFAULT, LV_OPA_COVER); + 12f54: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_OPA, bg_opa, lv_opa_t, _opa, scalar) + 12f56: 22ff movs r2, #255 ; 0xff + 12f58: 3080 adds r0, #128 ; 0x80 + 12f5a: 212c movs r1, #44 ; 0x2c + 12f5c: 47c8 blx r9 + lv_style_set_bg_color(&styles->sb, LV_STATE_DEFAULT, (IS_LIGHT ? lv_color_hex(0xcccfd1) : lv_color_hex(0x777f85))); + 12f5e: 6823 ldr r3, [r4, #0] + 12f60: f103 0b80 add.w fp, r3, #128 ; 0x80 + 12f64: 6a23 ldr r3, [r4, #32] + 12f66: 0799 lsls r1, r3, #30 + 12f68: bf4c ite mi + 12f6a: 48ae ldrmi r0, [pc, #696] ; (13224 ) + 12f6c: 48ae ldrpl r0, [pc, #696] ; (13228 ) + 12f6e: 47b8 blx r7 +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_COLOR, bg_color, lv_color_t, _color, nonscalar) + 12f70: 2129 movs r1, #41 ; 0x29 + 12f72: 4602 mov r2, r0 + 12f74: 4658 mov r0, fp + 12f76: 47b0 blx r6 + lv_style_set_radius(&styles->sb, LV_STATE_DEFAULT, LV_RADIUS_CIRCLE); + 12f78: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(RADIUS, radius, lv_style_int_t, _int, scalar) + 12f7a: f647 72ff movw r2, #32767 ; 0x7fff + 12f7e: 2101 movs r1, #1 + 12f80: 3080 adds r0, #128 ; 0x80 + 12f82: 47a8 blx r5 + lv_style_set_size(&styles->sb, LV_STATE_DEFAULT, LV_DPX(7)); + 12f84: 6823 ldr r3, [r4, #0] + 12f86: 2000 movs r0, #0 + 12f88: f103 0b80 add.w fp, r3, #128 ; 0x80 + 12f8c: 47c0 blx r8 + 12f8e: ebc0 00c0 rsb r0, r0, r0, lsl #3 + 12f92: 28ef cmp r0, #239 ; 0xef + 12f94: f340 86b5 ble.w 13d02 + 12f98: 2000 movs r0, #0 + 12f9a: 47c0 blx r8 + 12f9c: 2307 movs r3, #7 + 12f9e: 2250 movs r2, #80 ; 0x50 + 12fa0: fb00 2203 mla r2, r0, r3, r2 + 12fa4: 23a0 movs r3, #160 ; 0xa0 + 12fa6: fb92 f2f3 sdiv r2, r2, r3 + 12faa: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(SIZE, size, lv_style_int_t, _int, scalar) + 12fac: 4658 mov r0, fp + 12fae: 2103 movs r1, #3 + 12fb0: 47a8 blx r5 + lv_style_set_pad_right(&styles->sb, LV_STATE_DEFAULT, LV_DPX(7)); + 12fb2: 6823 ldr r3, [r4, #0] + 12fb4: 2000 movs r0, #0 + 12fb6: f103 0b80 add.w fp, r3, #128 ; 0x80 + 12fba: 47c0 blx r8 + 12fbc: ebc0 00c0 rsb r0, r0, r0, lsl #3 + 12fc0: 28ef cmp r0, #239 ; 0xef + 12fc2: f340 86a1 ble.w 13d08 + 12fc6: 2000 movs r0, #0 + 12fc8: 47c0 blx r8 + 12fca: 2307 movs r3, #7 + 12fcc: 2250 movs r2, #80 ; 0x50 + 12fce: fb00 2203 mla r2, r0, r3, r2 + 12fd2: 23a0 movs r3, #160 ; 0xa0 + 12fd4: fb92 f2f3 sdiv r2, r2, r3 + 12fd8: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_RIGHT, pad_right, lv_style_int_t, _int, scalar) + 12fda: 4658 mov r0, fp + 12fdc: 2113 movs r1, #19 + 12fde: 47a8 blx r5 + lv_style_set_pad_bottom(&styles->sb, LV_STATE_DEFAULT, LV_DPX(7)); + 12fe0: 6823 ldr r3, [r4, #0] + 12fe2: 2000 movs r0, #0 + 12fe4: f103 0b80 add.w fp, r3, #128 ; 0x80 + 12fe8: 47c0 blx r8 + 12fea: ebc0 00c0 rsb r0, r0, r0, lsl #3 + 12fee: 28ef cmp r0, #239 ; 0xef + 12ff0: f340 868d ble.w 13d0e + 12ff4: 2000 movs r0, #0 + 12ff6: 47c0 blx r8 + 12ff8: 2307 movs r3, #7 + 12ffa: 2250 movs r2, #80 ; 0x50 + 12ffc: fb00 2203 mla r2, r0, r3, r2 + 13000: 23a0 movs r3, #160 ; 0xa0 + 13002: fb92 f2f3 sdiv r2, r2, r3 + 13006: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_BOTTOM, pad_bottom, lv_style_int_t, _int, scalar) + 13008: 2111 movs r1, #17 + 1300a: 4658 mov r0, fp + 1300c: 47a8 blx r5 + style_init_reset(&styles->edge_flash); + 1300e: 6820 ldr r0, [r4, #0] + 13010: 3084 adds r0, #132 ; 0x84 + 13012: 47d0 blx sl + lv_style_set_bg_opa(&styles->edge_flash, LV_STATE_DEFAULT, LV_OPA_COVER); + 13014: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_OPA, bg_opa, lv_opa_t, _opa, scalar) + 13016: 22ff movs r2, #255 ; 0xff + 13018: 212c movs r1, #44 ; 0x2c + 1301a: 3084 adds r0, #132 ; 0x84 + 1301c: 47c8 blx r9 + lv_style_set_bg_color(&styles->edge_flash, LV_STATE_DEFAULT, lv_color_hex3(0x888)); + 1301e: 6823 ldr r3, [r4, #0] + 13020: f640 0088 movw r0, #2184 ; 0x888 + 13024: f103 0b84 add.w fp, r3, #132 ; 0x84 + 13028: 4b80 ldr r3, [pc, #512] ; (1322c ) + 1302a: 4798 blx r3 +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_COLOR, bg_color, lv_color_t, _color, nonscalar) + 1302c: 2129 movs r1, #41 ; 0x29 + 1302e: 4602 mov r2, r0 + 13030: 4658 mov r0, fp + 13032: 47b0 blx r6 + style_init_reset(&styles->ta_cursor); + 13034: 6820 ldr r0, [r4, #0] + 13036: 30b4 adds r0, #180 ; 0xb4 + 13038: 47d0 blx sl + lv_style_set_border_color(&styles->ta_cursor, LV_STATE_DEFAULT, COLOR_BG_SEC_TEXT); + 1303a: 6823 ldr r3, [r4, #0] + 1303c: f103 0bb4 add.w fp, r3, #180 ; 0xb4 + 13040: 6a23 ldr r3, [r4, #32] + 13042: 079a lsls r2, r3, #30 + 13044: bf4c ite mi + 13046: 487a ldrmi r0, [pc, #488] ; (13230 ) + 13048: 487a ldrpl r0, [pc, #488] ; (13234 ) + 1304a: 47b8 blx r7 +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_COLOR, border_color, lv_color_t, _color, nonscalar) + 1304c: 2139 movs r1, #57 ; 0x39 + 1304e: 4602 mov r2, r0 + 13050: 4658 mov r0, fp + 13052: 47b0 blx r6 + lv_style_set_border_width(&styles->ta_cursor, LV_STATE_DEFAULT, LV_DPX(2)); + 13054: 6823 ldr r3, [r4, #0] + 13056: 2000 movs r0, #0 + 13058: f103 0bb4 add.w fp, r3, #180 ; 0xb4 + 1305c: 47c0 blx r8 + 1305e: 2877 cmp r0, #119 ; 0x77 + 13060: f340 8658 ble.w 13d14 + 13064: 2000 movs r0, #0 + 13066: 47c0 blx r8 + 13068: 2350 movs r3, #80 ; 0x50 + 1306a: f100 0228 add.w r2, r0, #40 ; 0x28 + 1306e: fb92 f2f3 sdiv r2, r2, r3 + 13072: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_WIDTH, border_width, lv_style_int_t, _int, scalar) + 13074: 4658 mov r0, fp + 13076: 2130 movs r1, #48 ; 0x30 + 13078: 47a8 blx r5 + lv_style_set_pad_left(&styles->ta_cursor, LV_STATE_DEFAULT, LV_DPX(1)); + 1307a: 6823 ldr r3, [r4, #0] + 1307c: 2000 movs r0, #0 + 1307e: f103 0bb4 add.w fp, r3, #180 ; 0xb4 + 13082: 47c0 blx r8 + 13084: 28ef cmp r0, #239 ; 0xef + 13086: f340 8648 ble.w 13d1a + 1308a: 2000 movs r0, #0 + 1308c: 47c0 blx r8 + 1308e: 23a0 movs r3, #160 ; 0xa0 + 13090: f100 0250 add.w r2, r0, #80 ; 0x50 + 13094: fb92 f2f3 sdiv r2, r2, r3 + 13098: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_LEFT, pad_left, lv_style_int_t, _int, scalar) + 1309a: 4658 mov r0, fp + 1309c: 2112 movs r1, #18 + 1309e: 47a8 blx r5 + lv_style_set_border_side(&styles->ta_cursor, LV_STATE_DEFAULT, LV_BORDER_SIDE_LEFT); + 130a0: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_SIDE, border_side, lv_border_side_t, _int, scalar) + 130a2: 2204 movs r2, #4 + 130a4: 2131 movs r1, #49 ; 0x31 + 130a6: 30b4 adds r0, #180 ; 0xb4 + 130a8: 47a8 blx r5 + style_init_reset(&styles->ta_placeholder); + 130aa: 6820 ldr r0, [r4, #0] + 130ac: 30b8 adds r0, #184 ; 0xb8 + 130ae: 47d0 blx sl + lv_style_set_text_color(&styles->ta_placeholder, LV_STATE_DEFAULT, IS_LIGHT ? COLOR_BG_TEXT_DIS : lv_color_hex(0xa1adbd)); + 130b0: 6823 ldr r3, [r4, #0] + 130b2: f103 0bb8 add.w fp, r3, #184 ; 0xb8 + 130b6: 6a23 ldr r3, [r4, #32] + 130b8: 079b lsls r3, r3, #30 + 130ba: f140 8631 bpl.w 13d20 + 130be: 4b5b ldr r3, [pc, #364] ; (1322c ) + 130c0: f640 20aa movw r0, #2730 ; 0xaaa + 130c4: 4798 blx r3 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_COLOR, text_color, lv_color_t, _color, nonscalar) + 130c6: 4602 mov r2, r0 + 130c8: f248 0189 movw r1, #32905 ; 0x8089 + 130cc: 4658 mov r0, fp + 130ce: 47b0 blx r6 + style_init_reset(&styles->spinbox_cursor); + 130d0: 6820 ldr r0, [r4, #0] + 130d2: 3098 adds r0, #152 ; 0x98 + 130d4: 47d0 blx sl + lv_style_set_bg_opa(&styles->spinbox_cursor, LV_STATE_DEFAULT, LV_OPA_COVER); + 130d6: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_OPA, bg_opa, lv_opa_t, _opa, scalar) + 130d8: 22ff movs r2, #255 ; 0xff + 130da: 212c movs r1, #44 ; 0x2c + 130dc: 3098 adds r0, #152 ; 0x98 + 130de: 47c8 blx r9 + lv_style_set_bg_color(&styles->spinbox_cursor, LV_STATE_DEFAULT, theme.color_primary); + 130e0: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_COLOR, bg_color, lv_color_t, _color, nonscalar) + 130e2: 89a2 ldrh r2, [r4, #12] + 130e4: 2129 movs r1, #41 ; 0x29 + 130e6: 3098 adds r0, #152 ; 0x98 + 130e8: 47b0 blx r6 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_COLOR, text_color, lv_color_t, _color, nonscalar) + 130ea: 4b4d ldr r3, [pc, #308] ; (13220 ) + lv_style_set_text_color(&styles->spinbox_cursor, LV_STATE_DEFAULT, LV_COLOR_WHITE); + 130ec: 6820 ldr r0, [r4, #0] + 130ee: 881a ldrh r2, [r3, #0] + 130f0: f248 0189 movw r1, #32905 ; 0x8089 + 130f4: 3098 adds r0, #152 ; 0x98 + 130f6: 47b0 blx r6 + lv_style_set_pad_top(&styles->spinbox_cursor, LV_STATE_DEFAULT, LV_DPX(100)); + 130f8: 6823 ldr r3, [r4, #0] + 130fa: 2000 movs r0, #0 + 130fc: f103 0998 add.w r9, r3, #152 ; 0x98 + 13100: 47c0 blx r8 + 13102: f04f 0b64 mov.w fp, #100 ; 0x64 + 13106: fb00 f00b mul.w r0, r0, fp + 1310a: 28ef cmp r0, #239 ; 0xef + 1310c: f340 860c ble.w 13d28 + 13110: 2000 movs r0, #0 + 13112: 47c0 blx r8 + 13114: 2250 movs r2, #80 ; 0x50 + 13116: fb00 220b mla r2, r0, fp, r2 + 1311a: 23a0 movs r3, #160 ; 0xa0 + 1311c: fb92 f2f3 sdiv r2, r2, r3 + 13120: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_TOP, pad_top, lv_style_int_t, _int, scalar) + 13122: 4648 mov r0, r9 + 13124: 2110 movs r1, #16 + 13126: 47a8 blx r5 + lv_style_set_pad_bottom(&styles->spinbox_cursor, LV_STATE_DEFAULT, LV_DPX(100)); + 13128: 6823 ldr r3, [r4, #0] + 1312a: 2000 movs r0, #0 + 1312c: f103 0998 add.w r9, r3, #152 ; 0x98 + 13130: 47c0 blx r8 + 13132: f04f 0b64 mov.w fp, #100 ; 0x64 + 13136: fb00 f00b mul.w r0, r0, fp + 1313a: 28ef cmp r0, #239 ; 0xef + 1313c: f340 85f7 ble.w 13d2e + 13140: 2000 movs r0, #0 + 13142: 47c0 blx r8 + 13144: 2250 movs r2, #80 ; 0x50 + 13146: fb00 220b mla r2, r0, fp, r2 + 1314a: 23a0 movs r3, #160 ; 0xa0 + 1314c: fb92 f2f3 sdiv r2, r2, r3 + 13150: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_BOTTOM, pad_bottom, lv_style_int_t, _int, scalar) + 13152: 2111 movs r1, #17 + 13154: 4648 mov r0, r9 + 13156: 47a8 blx r5 + style_init_reset(&styles->list_bg); + 13158: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_OPA, bg_opa, lv_opa_t, _opa, scalar) + 1315a: f8df 90ec ldr.w r9, [pc, #236] ; 13248 + 1315e: 3074 adds r0, #116 ; 0x74 + 13160: 47d0 blx sl + lv_style_set_clip_corner(&styles->list_bg, LV_STATE_DEFAULT, true); + 13162: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(CLIP_CORNER, clip_corner, bool, _int, scalar) + 13164: 2201 movs r2, #1 + 13166: 2102 movs r1, #2 + 13168: 3074 adds r0, #116 ; 0x74 + 1316a: 47a8 blx r5 + lv_style_set_pad_left(&styles->list_bg, LV_STATE_DEFAULT, 0); + 1316c: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_LEFT, pad_left, lv_style_int_t, _int, scalar) + 1316e: 2200 movs r2, #0 + 13170: 2112 movs r1, #18 + 13172: 3074 adds r0, #116 ; 0x74 + 13174: 47a8 blx r5 + lv_style_set_pad_right(&styles->list_bg, LV_STATE_DEFAULT, 0); + 13176: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_RIGHT, pad_right, lv_style_int_t, _int, scalar) + 13178: 2200 movs r2, #0 + 1317a: 2113 movs r1, #19 + 1317c: 3074 adds r0, #116 ; 0x74 + 1317e: 47a8 blx r5 + lv_style_set_pad_top(&styles->list_bg, LV_STATE_DEFAULT, 0); + 13180: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_TOP, pad_top, lv_style_int_t, _int, scalar) + 13182: 2200 movs r2, #0 + 13184: 2110 movs r1, #16 + 13186: 3074 adds r0, #116 ; 0x74 + 13188: 47a8 blx r5 + lv_style_set_pad_bottom(&styles->list_bg, LV_STATE_DEFAULT, 0); + 1318a: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_BOTTOM, pad_bottom, lv_style_int_t, _int, scalar) + 1318c: 2200 movs r2, #0 + 1318e: 2111 movs r1, #17 + 13190: 3074 adds r0, #116 ; 0x74 + 13192: 47a8 blx r5 + lv_style_set_pad_inner(&styles->list_bg, LV_STATE_DEFAULT, 0); + 13194: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_INNER, pad_inner, lv_style_int_t, _int, scalar) + 13196: 2200 movs r2, #0 + 13198: 2114 movs r1, #20 + 1319a: 3074 adds r0, #116 ; 0x74 + 1319c: 47a8 blx r5 + style_init_reset(&styles->list_btn); + 1319e: 6820 ldr r0, [r4, #0] + 131a0: 3078 adds r0, #120 ; 0x78 + 131a2: 47d0 blx sl + lv_style_set_bg_opa(&styles->list_btn, LV_STATE_DEFAULT, LV_OPA_COVER); + 131a4: 6820 ldr r0, [r4, #0] + 131a6: f8df a084 ldr.w sl, [pc, #132] ; 1322c +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_OPA, bg_opa, lv_opa_t, _opa, scalar) + 131aa: 3078 adds r0, #120 ; 0x78 + 131ac: 22ff movs r2, #255 ; 0xff + 131ae: 212c movs r1, #44 ; 0x2c + 131b0: 47c8 blx r9 + lv_style_set_bg_color(&styles->list_btn, LV_STATE_DEFAULT, COLOR_BG); + 131b2: 6823 ldr r3, [r4, #0] + 131b4: f103 0878 add.w r8, r3, #120 ; 0x78 + 131b8: 6a23 ldr r3, [r4, #32] + 131ba: 0798 lsls r0, r3, #30 + 131bc: bf54 ite pl + 131be: 481e ldrpl r0, [pc, #120] ; (13238 ) + 131c0: f06f 407f mvnmi.w r0, #4278190080 ; 0xff000000 + 131c4: 47b8 blx r7 +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_COLOR, bg_color, lv_color_t, _color, nonscalar) + 131c6: 2129 movs r1, #41 ; 0x29 + 131c8: 4602 mov r2, r0 + 131ca: 4640 mov r0, r8 + 131cc: 47b0 blx r6 + lv_style_set_bg_color(&styles->list_btn, LV_STATE_PRESSED, COLOR_BG_PR); + 131ce: 6823 ldr r3, [r4, #0] + 131d0: f103 0878 add.w r8, r3, #120 ; 0x78 + 131d4: 6a23 ldr r3, [r4, #32] + 131d6: 0799 lsls r1, r3, #30 + 131d8: bf4c ite mi + 131da: 4818 ldrmi r0, [pc, #96] ; (1323c ) + 131dc: 4818 ldrpl r0, [pc, #96] ; (13240 ) + 131de: 47b8 blx r7 + 131e0: f241 0129 movw r1, #4137 ; 0x1029 + 131e4: 4602 mov r2, r0 + 131e6: 4640 mov r0, r8 + 131e8: 47b0 blx r6 + lv_style_set_bg_color(&styles->list_btn, LV_STATE_DISABLED, COLOR_BG_DIS); + 131ea: 6823 ldr r3, [r4, #0] + 131ec: f103 0878 add.w r8, r3, #120 ; 0x78 + 131f0: 6a23 ldr r3, [r4, #32] + 131f2: 079a lsls r2, r3, #30 + 131f4: bf54 ite pl + 131f6: 4810 ldrpl r0, [pc, #64] ; (13238 ) + 131f8: f06f 407f mvnmi.w r0, #4278190080 ; 0xff000000 + 131fc: 47b8 blx r7 + 131fe: f242 0129 movw r1, #8233 ; 0x2029 + 13202: 4602 mov r2, r0 + 13204: 4640 mov r0, r8 + 13206: 47b0 blx r6 + lv_style_set_bg_color(&styles->list_btn, LV_STATE_CHECKED, COLOR_BG_CHK); + 13208: 6820 ldr r0, [r4, #0] + 1320a: 89a2 ldrh r2, [r4, #12] + 1320c: f240 1129 movw r1, #297 ; 0x129 + 13210: 3078 adds r0, #120 ; 0x78 + 13212: 47b0 blx r6 + lv_style_set_bg_color(&styles->list_btn, LV_STATE_CHECKED | LV_STATE_PRESSED, COLOR_BG_PR_CHK); + 13214: 6820 ldr r0, [r4, #0] + 13216: 4b0b ldr r3, [pc, #44] ; (13244 ) + 13218: f100 0878 add.w r8, r0, #120 ; 0x78 + 1321c: e016 b.n 1324c + 1321e: bf00 nop + 13220: 00024272 .word 0x00024272 + 13224: 00cccfd1 .word 0x00cccfd1 + 13228: 00777f85 .word 0x00777f85 + 1322c: 000102f1 .word 0x000102f1 + 13230: 0031404f .word 0x0031404f + 13234: 00a5a8ad .word 0x00a5a8ad + 13238: 00586273 .word 0x00586273 + 1323c: 00eeeeee .word 0x00eeeeee + 13240: 00494f57 .word 0x00494f57 + 13244: 0000e38f .word 0x0000e38f + 13248: 00005a19 .word 0x00005a19 + 1324c: 2133 movs r1, #51 ; 0x33 + 1324e: 89a0 ldrh r0, [r4, #12] + 13250: 4798 blx r3 + 13252: f241 1129 movw r1, #4393 ; 0x1129 + 13256: 4602 mov r2, r0 + 13258: 4640 mov r0, r8 + 1325a: 47b0 blx r6 + lv_style_set_text_color(&styles->list_btn, LV_STATE_DEFAULT, COLOR_BG_TEXT); + 1325c: 6823 ldr r3, [r4, #0] + 1325e: f103 0878 add.w r8, r3, #120 ; 0x78 + 13262: 6a23 ldr r3, [r4, #32] + 13264: 079b lsls r3, r3, #30 + 13266: bf4c ite mi + 13268: 48ba ldrmi r0, [pc, #744] ; (13554 ) + 1326a: f06f 407f mvnpl.w r0, #4278190080 ; 0xff000000 + 1326e: 47b8 blx r7 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_COLOR, text_color, lv_color_t, _color, nonscalar) + 13270: f248 0189 movw r1, #32905 ; 0x8089 + 13274: 4602 mov r2, r0 + 13276: 4640 mov r0, r8 + 13278: 47b0 blx r6 + lv_style_set_text_color(&styles->list_btn, LV_STATE_CHECKED, COLOR_BG_TEXT_CHK); + 1327a: 6820 ldr r0, [r4, #0] + 1327c: f100 0878 add.w r8, r0, #120 ; 0x78 + 13280: f06f 407f mvn.w r0, #4278190080 ; 0xff000000 + 13284: 47b8 blx r7 + 13286: f248 1189 movw r1, #33161 ; 0x8189 + 1328a: 4602 mov r2, r0 + 1328c: 4640 mov r0, r8 + 1328e: 47b0 blx r6 + lv_style_set_text_color(&styles->list_btn, LV_STATE_DISABLED, COLOR_BG_TEXT_DIS); + 13290: 6823 ldr r3, [r4, #0] + 13292: f103 0878 add.w r8, r3, #120 ; 0x78 + 13296: 6a23 ldr r3, [r4, #32] + 13298: f013 0f02 tst.w r3, #2 + 1329c: bf14 ite ne + 1329e: f640 20aa movwne r0, #2730 ; 0xaaa + 132a2: f640 1099 movweq r0, #2457 ; 0x999 + 132a6: 47d0 blx sl + 132a8: f24a 0189 movw r1, #41097 ; 0xa089 + 132ac: 4602 mov r2, r0 + 132ae: 4640 mov r0, r8 + 132b0: 47b0 blx r6 + lv_style_set_image_recolor(&styles->list_btn, LV_STATE_DEFAULT, COLOR_BG_TEXT); + 132b2: 6823 ldr r3, [r4, #0] + 132b4: f103 0878 add.w r8, r3, #120 ; 0x78 + 132b8: 6a23 ldr r3, [r4, #32] + lv_style_set_image_recolor(&styles->list_btn, LV_STATE_CHECKED, COLOR_BG_TEXT_CHK); + 132ba: 4ca7 ldr r4, [pc, #668] ; (13558 ) + lv_style_set_image_recolor(&styles->list_btn, LV_STATE_DEFAULT, COLOR_BG_TEXT); + 132bc: 0798 lsls r0, r3, #30 + 132be: bf4c ite mi + 132c0: 48a4 ldrmi r0, [pc, #656] ; (13554 ) + 132c2: f06f 407f mvnpl.w r0, #4278190080 ; 0xff000000 + 132c6: 47b8 blx r7 +_LV_OBJ_STYLE_SET_GET_DECLARE(IMAGE_RECOLOR, image_recolor, lv_color_t, _color, nonscalar) + 132c8: f248 01a9 movw r1, #32937 ; 0x80a9 + 132cc: 4602 mov r2, r0 + 132ce: 4640 mov r0, r8 + 132d0: 47b0 blx r6 + lv_style_set_image_recolor(&styles->list_btn, LV_STATE_CHECKED, COLOR_BG_TEXT_CHK); + 132d2: 6820 ldr r0, [r4, #0] + 132d4: f100 0878 add.w r8, r0, #120 ; 0x78 + 132d8: f06f 407f mvn.w r0, #4278190080 ; 0xff000000 + 132dc: 47b8 blx r7 + 132de: f248 11a9 movw r1, #33193 ; 0x81a9 + 132e2: 4602 mov r2, r0 + 132e4: 4640 mov r0, r8 + 132e6: 47b0 blx r6 + lv_style_set_image_recolor(&styles->list_btn, LV_STATE_DISABLED, COLOR_BG_TEXT_DIS); + 132e8: 6823 ldr r3, [r4, #0] + 132ea: f103 0878 add.w r8, r3, #120 ; 0x78 + 132ee: 6a23 ldr r3, [r4, #32] + 132f0: 0799 lsls r1, r3, #30 + 132f2: bf4c ite mi + 132f4: f640 20aa movwmi r0, #2730 ; 0xaaa + 132f8: f640 1099 movwpl r0, #2457 ; 0x999 + 132fc: 47d0 blx sl + 132fe: f24a 01a9 movw r1, #41129 ; 0xa0a9 + 13302: 4602 mov r2, r0 + 13304: 4640 mov r0, r8 + 13306: 47b0 blx r6 + lv_style_set_border_side(&styles->list_btn, LV_STATE_DEFAULT, LV_BORDER_SIDE_BOTTOM); + 13308: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_WIDTH, border_width, lv_style_int_t, _int, scalar) + 1330a: 4e94 ldr r6, [pc, #592] ; (1355c ) + lv_style_set_pad_left(&styles->list_btn, LV_STATE_DEFAULT, PAD_DEF); + 1330c: f8df 8268 ldr.w r8, [pc, #616] ; 13578 +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_SIDE, border_side, lv_border_side_t, _int, scalar) + 13310: 2201 movs r2, #1 + 13312: 3078 adds r0, #120 ; 0x78 + 13314: 2131 movs r1, #49 ; 0x31 + 13316: 47a8 blx r5 + lv_style_set_border_color(&styles->list_btn, LV_STATE_DEFAULT, COLOR_BG_BORDER); + 13318: 6a23 ldr r3, [r4, #32] + 1331a: 6825 ldr r5, [r4, #0] + 1331c: 079a lsls r2, r3, #30 + 1331e: bf4c ite mi + 13320: 488f ldrmi r0, [pc, #572] ; (13560 ) + 13322: 4890 ldrpl r0, [pc, #576] ; (13564 ) + 13324: 47b8 blx r7 + 13326: 3578 adds r5, #120 ; 0x78 +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_COLOR, border_color, lv_color_t, _color, nonscalar) + 13328: 4602 mov r2, r0 + 1332a: 4f8f ldr r7, [pc, #572] ; (13568 ) + 1332c: 4628 mov r0, r5 + 1332e: 2139 movs r1, #57 ; 0x39 + 13330: 47b8 blx r7 + lv_style_set_border_color(&styles->list_btn, LV_STATE_FOCUSED, theme.color_primary); + 13332: 6820 ldr r0, [r4, #0] + 13334: 89a2 ldrh r2, [r4, #12] + 13336: 4d8d ldr r5, [pc, #564] ; (1356c ) + 13338: f240 2139 movw r1, #569 ; 0x239 + 1333c: 3078 adds r0, #120 ; 0x78 + 1333e: 47b8 blx r7 + lv_style_set_border_width(&styles->list_btn, LV_STATE_DEFAULT, 1); + 13340: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_WIDTH, border_width, lv_style_int_t, _int, scalar) + 13342: 2201 movs r2, #1 + 13344: 2130 movs r1, #48 ; 0x30 + 13346: 3078 adds r0, #120 ; 0x78 + 13348: 47b0 blx r6 + lv_style_set_pad_left(&styles->list_btn, LV_STATE_DEFAULT, PAD_DEF); + 1334a: 6823 ldr r3, [r4, #0] + 1334c: 2000 movs r0, #0 + 1334e: f103 0b78 add.w fp, r3, #120 ; 0x78 + 13352: 47c0 blx r8 + 13354: 2801 cmp r0, #1 + 13356: f04f 0000 mov.w r0, #0 + 1335a: f200 84f7 bhi.w 13d4c + 1335e: 47a8 blx r5 + 13360: ebc0 1000 rsb r0, r0, r0, lsl #4 + 13364: 28ef cmp r0, #239 ; 0xef + 13366: f300 84e5 bgt.w 13d34 + 1336a: 2201 movs r2, #1 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_LEFT, pad_left, lv_style_int_t, _int, scalar) + 1336c: 4658 mov r0, fp + 1336e: 2112 movs r1, #18 + 13370: 47b0 blx r6 + lv_style_set_pad_right(&styles->list_btn, LV_STATE_DEFAULT, PAD_DEF); + 13372: 6823 ldr r3, [r4, #0] + 13374: 2000 movs r0, #0 + 13376: f103 0b78 add.w fp, r3, #120 ; 0x78 + 1337a: 47c0 blx r8 + 1337c: 2801 cmp r0, #1 + 1337e: f04f 0000 mov.w r0, #0 + 13382: f200 84fa bhi.w 13d7a + 13386: 47a8 blx r5 + 13388: ebc0 1000 rsb r0, r0, r0, lsl #4 + 1338c: 28ef cmp r0, #239 ; 0xef + 1338e: f300 84e8 bgt.w 13d62 + 13392: 2201 movs r2, #1 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_RIGHT, pad_right, lv_style_int_t, _int, scalar) + 13394: 4658 mov r0, fp + 13396: 2113 movs r1, #19 + 13398: 47b0 blx r6 + lv_style_set_pad_top(&styles->list_btn, LV_STATE_DEFAULT, PAD_DEF); + 1339a: 6823 ldr r3, [r4, #0] + 1339c: 2000 movs r0, #0 + 1339e: f103 0b78 add.w fp, r3, #120 ; 0x78 + 133a2: 47c0 blx r8 + 133a4: 2801 cmp r0, #1 + 133a6: f04f 0000 mov.w r0, #0 + 133aa: f200 84fd bhi.w 13da8 + 133ae: 47a8 blx r5 + 133b0: ebc0 1000 rsb r0, r0, r0, lsl #4 + 133b4: 28ef cmp r0, #239 ; 0xef + 133b6: f300 84eb bgt.w 13d90 + 133ba: 2201 movs r2, #1 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_TOP, pad_top, lv_style_int_t, _int, scalar) + 133bc: 4658 mov r0, fp + 133be: 2110 movs r1, #16 + 133c0: 47b0 blx r6 + lv_style_set_pad_bottom(&styles->list_btn, LV_STATE_DEFAULT, PAD_DEF); + 133c2: 6823 ldr r3, [r4, #0] + 133c4: 2000 movs r0, #0 + 133c6: f103 0b78 add.w fp, r3, #120 ; 0x78 + 133ca: 47c0 blx r8 + 133cc: 2801 cmp r0, #1 + 133ce: f04f 0000 mov.w r0, #0 + 133d2: f200 8500 bhi.w 13dd6 + 133d6: 47a8 blx r5 + 133d8: ebc0 1000 rsb r0, r0, r0, lsl #4 + 133dc: 28ef cmp r0, #239 ; 0xef + 133de: f300 84ee bgt.w 13dbe + 133e2: 2201 movs r2, #1 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_BOTTOM, pad_bottom, lv_style_int_t, _int, scalar) + 133e4: 4658 mov r0, fp + 133e6: 2111 movs r1, #17 + 133e8: 47b0 blx r6 + lv_style_set_pad_inner(&styles->list_btn, LV_STATE_DEFAULT, PAD_DEF); + 133ea: 6823 ldr r3, [r4, #0] + 133ec: 2000 movs r0, #0 + 133ee: f103 0b78 add.w fp, r3, #120 ; 0x78 + 133f2: 47c0 blx r8 + 133f4: 2801 cmp r0, #1 + 133f6: f04f 0000 mov.w r0, #0 + 133fa: f200 8503 bhi.w 13e04 + 133fe: 47a8 blx r5 + 13400: ebc0 1000 rsb r0, r0, r0, lsl #4 + 13404: 28ef cmp r0, #239 ; 0xef + 13406: f300 84f1 bgt.w 13dec + 1340a: 2201 movs r2, #1 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_INNER, pad_inner, lv_style_int_t, _int, scalar) + 1340c: 4658 mov r0, fp + 1340e: 2114 movs r1, #20 + 13410: 47b0 blx r6 + lv_style_set_transform_width(&styles->list_btn, LV_STATE_DEFAULT, - PAD_DEF); + 13412: 6823 ldr r3, [r4, #0] + 13414: 2000 movs r0, #0 + 13416: f103 0b78 add.w fp, r3, #120 ; 0x78 + 1341a: 47c0 blx r8 + 1341c: 2801 cmp r0, #1 + 1341e: f04f 0000 mov.w r0, #0 + 13422: f200 8507 bhi.w 13e34 + 13426: 47a8 blx r5 + 13428: ebc0 1000 rsb r0, r0, r0, lsl #4 + 1342c: 28ef cmp r0, #239 ; 0xef + 1342e: f300 84f4 bgt.w 13e1a + 13432: f04f 32ff mov.w r2, #4294967295 ; 0xffffffff +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSFORM_WIDTH, transform_width, lv_style_int_t, _int, scalar) + 13436: 4658 mov r0, fp + 13438: 2104 movs r1, #4 + 1343a: 47b0 blx r6 + lv_style_set_transform_width(&styles->list_btn, LV_STATE_PRESSED, 0); + 1343c: 6820 ldr r0, [r4, #0] + style_init_reset(&styles->ddlist_page); + 1343e: f8df b13c ldr.w fp, [pc, #316] ; 1357c + 13442: 2200 movs r2, #0 + 13444: f241 0104 movw r1, #4100 ; 0x1004 + 13448: 3078 adds r0, #120 ; 0x78 + 1344a: 47b0 blx r6 + lv_style_set_transform_width(&styles->list_btn, LV_STATE_CHECKED, 0); + 1344c: 6820 ldr r0, [r4, #0] + 1344e: 2200 movs r2, #0 + 13450: f44f 7182 mov.w r1, #260 ; 0x104 + 13454: 3078 adds r0, #120 ; 0x78 + 13456: 47b0 blx r6 + lv_style_set_transform_width(&styles->list_btn, LV_STATE_DISABLED, 0); + 13458: 6820 ldr r0, [r4, #0] + 1345a: 2200 movs r2, #0 + 1345c: f242 0104 movw r1, #8196 ; 0x2004 + 13460: 3078 adds r0, #120 ; 0x78 + 13462: 47b0 blx r6 + lv_style_set_transition_time(&styles->list_btn, LV_STATE_DEFAULT, TRANSITION_TIME); + 13464: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSITION_TIME, transition_time, lv_style_int_t, _int, scalar) + 13466: 2296 movs r2, #150 ; 0x96 + 13468: 21b0 movs r1, #176 ; 0xb0 + 1346a: 3078 adds r0, #120 ; 0x78 + 1346c: 47b0 blx r6 + lv_style_set_transition_prop_6(&styles->list_btn, LV_STATE_DEFAULT, LV_STYLE_BG_COLOR); + 1346e: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSITION_PROP_6, transition_prop_6, lv_style_int_t, _int, scalar) + 13470: 2229 movs r2, #41 ; 0x29 + 13472: 21b7 movs r1, #183 ; 0xb7 + 13474: 3078 adds r0, #120 ; 0x78 + 13476: 47b0 blx r6 + lv_style_set_transition_prop_5(&styles->list_btn, LV_STATE_DEFAULT, LV_STYLE_TRANSFORM_WIDTH); + 13478: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSITION_PROP_5, transition_prop_5, lv_style_int_t, _int, scalar) + 1347a: 2204 movs r2, #4 + 1347c: 21b6 movs r1, #182 ; 0xb6 + 1347e: 3078 adds r0, #120 ; 0x78 + 13480: 47b0 blx r6 + style_init_reset(&styles->ddlist_page); + 13482: 6820 ldr r0, [r4, #0] + 13484: 3054 adds r0, #84 ; 0x54 + 13486: 47d8 blx fp + lv_style_set_text_line_space(&styles->ddlist_page, LV_STATE_DEFAULT, LV_DPX(20)); + 13488: 6823 ldr r3, [r4, #0] + 1348a: 2000 movs r0, #0 + 1348c: f103 0854 add.w r8, r3, #84 ; 0x54 + 13490: 47a8 blx r5 + 13492: eb00 0080 add.w r0, r0, r0, lsl #2 + 13496: 0080 lsls r0, r0, #2 + 13498: 28ef cmp r0, #239 ; 0xef + 1349a: f8cd b004 str.w fp, [sp, #4] + 1349e: f340 84d4 ble.w 13e4a + 134a2: 2000 movs r0, #0 + 134a4: 47a8 blx r5 + 134a6: 2314 movs r3, #20 + 134a8: 2250 movs r2, #80 ; 0x50 + 134aa: fb00 2203 mla r2, r0, r3, r2 + 134ae: 23a0 movs r3, #160 ; 0xa0 + 134b0: fb92 f2f3 sdiv r2, r2, r3 + 134b4: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_LINE_SPACE, text_line_space, lv_style_int_t, _int, scalar) + 134b6: 4640 mov r0, r8 + 134b8: f248 0181 movw r1, #32897 ; 0x8081 + 134bc: 47b0 blx r6 + lv_style_set_clip_corner(&styles->ddlist_page, LV_STATE_DEFAULT, true); + 134be: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(CLIP_CORNER, clip_corner, bool, _int, scalar) + 134c0: 2201 movs r2, #1 + 134c2: 2102 movs r1, #2 + 134c4: 3054 adds r0, #84 ; 0x54 + 134c6: 47b0 blx r6 + style_init_reset(&styles->ddlist_sel); + 134c8: 6820 ldr r0, [r4, #0] + 134ca: 9b01 ldr r3, [sp, #4] + 134cc: 3058 adds r0, #88 ; 0x58 + 134ce: 4798 blx r3 + lv_style_set_bg_opa(&styles->ddlist_sel, LV_STATE_DEFAULT, LV_OPA_COVER); + 134d0: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_OPA, bg_opa, lv_opa_t, _opa, scalar) + 134d2: 22ff movs r2, #255 ; 0xff + 134d4: 212c movs r1, #44 ; 0x2c + 134d6: 3058 adds r0, #88 ; 0x58 + 134d8: 47c8 blx r9 + lv_style_set_bg_color(&styles->ddlist_sel, LV_STATE_DEFAULT, theme.color_primary); + 134da: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_COLOR, bg_color, lv_color_t, _color, nonscalar) + 134dc: 89a2 ldrh r2, [r4, #12] + 134de: 2129 movs r1, #41 ; 0x29 + 134e0: 3058 adds r0, #88 ; 0x58 + 134e2: 47b8 blx r7 + lv_style_set_text_color(&styles->ddlist_sel, LV_STATE_DEFAULT, IS_LIGHT ? lv_color_hex3(0xfff) : lv_color_hex3(0xfff)); + 134e4: 6823 ldr r3, [r4, #0] + 134e6: f640 70ff movw r0, #4095 ; 0xfff + 134ea: f103 0858 add.w r8, r3, #88 ; 0x58 + 134ee: 47d0 blx sl +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_COLOR, text_color, lv_color_t, _color, nonscalar) + 134f0: f248 0189 movw r1, #32905 ; 0x8089 + 134f4: 4602 mov r2, r0 + 134f6: 4640 mov r0, r8 + 134f8: 47b8 blx r7 + lv_style_set_bg_color(&styles->ddlist_sel, LV_STATE_PRESSED, COLOR_BG_PR); + 134fa: 6823 ldr r3, [r4, #0] + 134fc: f8df 8080 ldr.w r8, [pc, #128] ; 13580 + 13500: f103 0b58 add.w fp, r3, #88 ; 0x58 + 13504: 6a23 ldr r3, [r4, #32] + 13506: f013 0f02 tst.w r3, #2 + 1350a: bf14 ite ne + 1350c: 4818 ldrne r0, [pc, #96] ; (13570 ) + 1350e: 4819 ldreq r0, [pc, #100] ; (13574 ) + 13510: 47c0 blx r8 +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_COLOR, bg_color, lv_color_t, _color, nonscalar) + 13512: f241 0129 movw r1, #4137 ; 0x1029 + 13516: 4602 mov r2, r0 + 13518: 4658 mov r0, fp + 1351a: 47b8 blx r7 + lv_style_set_text_color(&styles->ddlist_sel, LV_STATE_PRESSED, COLOR_BG_TEXT_PR); + 1351c: 6823 ldr r3, [r4, #0] + 1351e: f103 0b58 add.w fp, r3, #88 ; 0x58 + 13522: 6a23 ldr r3, [r4, #32] + 13524: 079b lsls r3, r3, #30 + 13526: bf4c ite mi + 13528: 480a ldrmi r0, [pc, #40] ; (13554 ) + 1352a: f06f 407f mvnpl.w r0, #4278190080 ; 0xff000000 + 1352e: 47c0 blx r8 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_COLOR, text_color, lv_color_t, _color, nonscalar) + 13530: f249 0189 movw r1, #37001 ; 0x9089 + 13534: 4602 mov r2, r0 + 13536: 4658 mov r0, fp + 13538: 47b8 blx r7 + style_init_reset(&styles->roller_bg); + 1353a: 6820 ldr r0, [r4, #0] + 1353c: 9b01 ldr r3, [sp, #4] + 1353e: 3088 adds r0, #136 ; 0x88 + 13540: 4798 blx r3 + lv_style_set_text_line_space(&styles->roller_bg, LV_STATE_DEFAULT, LV_DPX(25)); + 13542: 6823 ldr r3, [r4, #0] + 13544: 2000 movs r0, #0 + 13546: f103 0888 add.w r8, r3, #136 ; 0x88 + 1354a: 47a8 blx r5 + 1354c: eb00 0080 add.w r0, r0, r0, lsl #2 + 13550: e018 b.n 13584 + 13552: bf00 nop + 13554: 003b3e42 .word 0x003b3e42 + 13558: 2000c7d4 .word 0x2000c7d4 + 1355c: 00005879 .word 0x00005879 + 13560: 00d6dde3 .word 0x00d6dde3 + 13564: 00808a97 .word 0x00808a97 + 13568: 00005949 .word 0x00005949 + 1356c: 0000d951 .word 0x0000d951 + 13570: 00eeeeee .word 0x00eeeeee + 13574: 00494f57 .word 0x00494f57 + 13578: 0000d969 .word 0x0000d969 + 1357c: 00010abd .word 0x00010abd + 13580: 00010e9d .word 0x00010e9d + 13584: eb00 0080 add.w r0, r0, r0, lsl #2 + 13588: 28ef cmp r0, #239 ; 0xef + 1358a: f340 8461 ble.w 13e50 + 1358e: 2000 movs r0, #0 + 13590: 47a8 blx r5 + 13592: 2319 movs r3, #25 + 13594: 2250 movs r2, #80 ; 0x50 + 13596: fb00 2203 mla r2, r0, r3, r2 + 1359a: 23a0 movs r3, #160 ; 0xa0 + 1359c: fb92 f2f3 sdiv r2, r2, r3 + 135a0: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_LINE_SPACE, text_line_space, lv_style_int_t, _int, scalar) + 135a2: f248 0181 movw r1, #32897 ; 0x8081 + 135a6: 4640 mov r0, r8 + 135a8: 47b0 blx r6 + style_init_reset(&styles->roller_sel); + 135aa: 6820 ldr r0, [r4, #0] + 135ac: f8df 8308 ldr.w r8, [pc, #776] ; 138b8 + 135b0: 308c adds r0, #140 ; 0x8c + 135b2: 47c0 blx r8 + lv_style_set_bg_opa(&styles->roller_sel, LV_STATE_DEFAULT, LV_OPA_COVER); + 135b4: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_OPA, bg_opa, lv_opa_t, _opa, scalar) + 135b6: 22ff movs r2, #255 ; 0xff + 135b8: 212c movs r1, #44 ; 0x2c + 135ba: 308c adds r0, #140 ; 0x8c + 135bc: 47c8 blx r9 + lv_style_set_bg_color(&styles->roller_sel, LV_STATE_DEFAULT, theme.color_primary); + 135be: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_COLOR, bg_color, lv_color_t, _color, nonscalar) + 135c0: 89a2 ldrh r2, [r4, #12] + 135c2: 2129 movs r1, #41 ; 0x29 + 135c4: 308c adds r0, #140 ; 0x8c + 135c6: 47b8 blx r7 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_COLOR, text_color, lv_color_t, _color, nonscalar) + 135c8: 4bb4 ldr r3, [pc, #720] ; (1389c ) + lv_style_set_text_color(&styles->roller_sel, LV_STATE_DEFAULT, LV_COLOR_WHITE); + 135ca: 6820 ldr r0, [r4, #0] + 135cc: 881a ldrh r2, [r3, #0] + 135ce: f248 0189 movw r1, #32905 ; 0x8089 + 135d2: 308c adds r0, #140 ; 0x8c + 135d4: 47b8 blx r7 + style_init_reset(&styles->tabview_btns_bg); + 135d6: 6820 ldr r0, [r4, #0] + 135d8: 30a8 adds r0, #168 ; 0xa8 + 135da: 47c0 blx r8 + lv_style_set_bg_opa(&styles->tabview_btns_bg, LV_STATE_DEFAULT, LV_OPA_COVER); + 135dc: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_OPA, bg_opa, lv_opa_t, _opa, scalar) + 135de: 22ff movs r2, #255 ; 0xff + 135e0: 30a8 adds r0, #168 ; 0xa8 + 135e2: 212c movs r1, #44 ; 0x2c + 135e4: 47c8 blx r9 + lv_style_set_bg_color(&styles->tabview_btns_bg, LV_STATE_DEFAULT, COLOR_BG); + 135e6: 6823 ldr r3, [r4, #0] + 135e8: f8cd 8004 str.w r8, [sp, #4] + 135ec: f103 0ba8 add.w fp, r3, #168 ; 0xa8 + 135f0: 6a23 ldr r3, [r4, #32] + 135f2: f8df 82c8 ldr.w r8, [pc, #712] ; 138bc + 135f6: f013 0f02 tst.w r3, #2 + 135fa: bf0c ite eq + 135fc: 48a8 ldreq r0, [pc, #672] ; (138a0 ) + 135fe: f06f 407f mvnne.w r0, #4278190080 ; 0xff000000 + 13602: 47c0 blx r8 +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_COLOR, bg_color, lv_color_t, _color, nonscalar) + 13604: 2129 movs r1, #41 ; 0x29 + 13606: 4602 mov r2, r0 + 13608: 4658 mov r0, fp + 1360a: 47b8 blx r7 + lv_style_set_border_color(&styles->tabview_btns_bg, LV_STATE_DEFAULT, + 1360c: 6823 ldr r3, [r4, #0] + 1360e: f103 0ba8 add.w fp, r3, #168 ; 0xa8 + IS_LIGHT ? lv_color_hex(0xe4eaf0) : lv_color_hex(0x3b3e42)); + 13612: 6a23 ldr r3, [r4, #32] + lv_style_set_border_color(&styles->tabview_btns_bg, LV_STATE_DEFAULT, + 13614: 0798 lsls r0, r3, #30 + IS_LIGHT ? lv_color_hex(0xe4eaf0) : lv_color_hex(0x3b3e42)); + 13616: bf4c ite mi + 13618: 48a2 ldrmi r0, [pc, #648] ; (138a4 ) + 1361a: 48a3 ldrpl r0, [pc, #652] ; (138a8 ) + 1361c: 47c0 blx r8 +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_COLOR, border_color, lv_color_t, _color, nonscalar) + 1361e: 2139 movs r1, #57 ; 0x39 + 13620: 4602 mov r2, r0 + 13622: 4658 mov r0, fp + 13624: 47b8 blx r7 + lv_style_set_border_width(&styles->tabview_btns_bg, LV_STATE_DEFAULT, LV_DPX(5)); + 13626: 6823 ldr r3, [r4, #0] + 13628: 2000 movs r0, #0 + 1362a: f103 0ba8 add.w fp, r3, #168 ; 0xa8 + 1362e: 47a8 blx r5 + 13630: eb00 0080 add.w r0, r0, r0, lsl #2 + 13634: 28ef cmp r0, #239 ; 0xef + 13636: f340 840e ble.w 13e56 + 1363a: 2000 movs r0, #0 + 1363c: 47a8 blx r5 + 1363e: 2305 movs r3, #5 + 13640: 2250 movs r2, #80 ; 0x50 + 13642: fb00 2203 mla r2, r0, r3, r2 + 13646: 23a0 movs r3, #160 ; 0xa0 + 13648: fb92 f2f3 sdiv r2, r2, r3 + 1364c: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_WIDTH, border_width, lv_style_int_t, _int, scalar) + 1364e: 4658 mov r0, fp + 13650: 2130 movs r1, #48 ; 0x30 + 13652: 47b0 blx r6 + lv_style_set_border_side(&styles->tabview_btns_bg, LV_STATE_DEFAULT, LV_BORDER_SIDE_BOTTOM); + 13654: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_SIDE, border_side, lv_border_side_t, _int, scalar) + 13656: 2201 movs r2, #1 + 13658: 30a8 adds r0, #168 ; 0xa8 + 1365a: 2131 movs r1, #49 ; 0x31 + 1365c: 47b0 blx r6 + lv_style_set_text_color(&styles->tabview_btns_bg, LV_STATE_DEFAULT, COLOR_SCR_TEXT); + 1365e: 6823 ldr r3, [r4, #0] + 13660: f103 0ba8 add.w fp, r3, #168 ; 0xa8 + 13664: 6a23 ldr r3, [r4, #32] + 13666: 0799 lsls r1, r3, #30 + 13668: bf4c ite mi + 1366a: 488f ldrmi r0, [pc, #572] ; (138a8 ) + 1366c: 488f ldrpl r0, [pc, #572] ; (138ac ) + 1366e: 47c0 blx r8 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_COLOR, text_color, lv_color_t, _color, nonscalar) + 13670: f248 0189 movw r1, #32905 ; 0x8089 + 13674: 4602 mov r2, r0 + 13676: 4658 mov r0, fp + 13678: 47b8 blx r7 + lv_style_set_text_font(&styles->tabview_btns_bg, LV_STATE_DEFAULT, theme.font_normal); + 1367a: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_FONT, text_font, const lv_font_t *, _ptr, scalar) + 1367c: 6962 ldr r2, [r4, #20] + 1367e: 4b8c ldr r3, [pc, #560] ; (138b0 ) + 13680: f248 018e movw r1, #32910 ; 0x808e + 13684: 30a8 adds r0, #168 ; 0xa8 + 13686: 4798 blx r3 + lv_style_set_image_recolor(&styles->tabview_btns_bg, LV_STATE_DEFAULT, lv_color_hex(0x979a9f)); + 13688: 6823 ldr r3, [r4, #0] + 1368a: 488a ldr r0, [pc, #552] ; (138b4 ) + 1368c: f103 0ba8 add.w fp, r3, #168 ; 0xa8 + 13690: 47c0 blx r8 +_LV_OBJ_STYLE_SET_GET_DECLARE(IMAGE_RECOLOR, image_recolor, lv_color_t, _color, nonscalar) + 13692: f248 01a9 movw r1, #32937 ; 0x80a9 + 13696: 4602 mov r2, r0 + 13698: 4658 mov r0, fp + 1369a: 47b8 blx r7 + lv_style_set_pad_top(&styles->tabview_btns_bg, LV_STATE_DEFAULT, LV_DPX(7)); + 1369c: 6823 ldr r3, [r4, #0] + 1369e: 2000 movs r0, #0 + 136a0: f103 0ba8 add.w fp, r3, #168 ; 0xa8 + 136a4: 47a8 blx r5 + 136a6: ebc0 00c0 rsb r0, r0, r0, lsl #3 + 136aa: 28ef cmp r0, #239 ; 0xef + 136ac: f340 83d6 ble.w 13e5c + 136b0: 2000 movs r0, #0 + 136b2: 47a8 blx r5 + 136b4: 2307 movs r3, #7 + 136b6: 2250 movs r2, #80 ; 0x50 + 136b8: fb00 2203 mla r2, r0, r3, r2 + 136bc: 23a0 movs r3, #160 ; 0xa0 + 136be: fb92 f2f3 sdiv r2, r2, r3 + 136c2: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_TOP, pad_top, lv_style_int_t, _int, scalar) + 136c4: 4658 mov r0, fp + 136c6: 2110 movs r1, #16 + 136c8: 47b0 blx r6 + lv_style_set_pad_left(&styles->tabview_btns_bg, LV_STATE_DEFAULT, LV_DPX(7)); + 136ca: 6823 ldr r3, [r4, #0] + 136cc: 2000 movs r0, #0 + 136ce: f103 0ba8 add.w fp, r3, #168 ; 0xa8 + 136d2: 47a8 blx r5 + 136d4: ebc0 00c0 rsb r0, r0, r0, lsl #3 + 136d8: 28ef cmp r0, #239 ; 0xef + 136da: f340 83c1 ble.w 13e60 + 136de: 2000 movs r0, #0 + 136e0: 47a8 blx r5 + 136e2: 2307 movs r3, #7 + 136e4: 2250 movs r2, #80 ; 0x50 + 136e6: fb00 2203 mla r2, r0, r3, r2 + 136ea: 23a0 movs r3, #160 ; 0xa0 + 136ec: fb92 f2f3 sdiv r2, r2, r3 + 136f0: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_LEFT, pad_left, lv_style_int_t, _int, scalar) + 136f2: 4658 mov r0, fp + 136f4: 2112 movs r1, #18 + 136f6: 47b0 blx r6 + lv_style_set_pad_right(&styles->tabview_btns_bg, LV_STATE_DEFAULT, LV_DPX(7)); + 136f8: 6823 ldr r3, [r4, #0] + 136fa: 2000 movs r0, #0 + 136fc: f103 0ba8 add.w fp, r3, #168 ; 0xa8 + 13700: 47a8 blx r5 + 13702: ebc0 00c0 rsb r0, r0, r0, lsl #3 + 13706: 28ef cmp r0, #239 ; 0xef + 13708: f340 83ac ble.w 13e64 + 1370c: 2000 movs r0, #0 + 1370e: 47a8 blx r5 + 13710: 2307 movs r3, #7 + 13712: 2250 movs r2, #80 ; 0x50 + 13714: fb00 2203 mla r2, r0, r3, r2 + 13718: 23a0 movs r3, #160 ; 0xa0 + 1371a: fb92 f2f3 sdiv r2, r2, r3 + 1371e: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_RIGHT, pad_right, lv_style_int_t, _int, scalar) + 13720: 2113 movs r1, #19 + 13722: 4658 mov r0, fp + 13724: 47b0 blx r6 + style_init_reset(&styles->tabview_btns); + 13726: 6820 ldr r0, [r4, #0] + 13728: 9b01 ldr r3, [sp, #4] + 1372a: 30a4 adds r0, #164 ; 0xa4 + 1372c: 4798 blx r3 + lv_style_set_bg_opa(&styles->tabview_btns, LV_STATE_PRESSED, LV_OPA_50); + 1372e: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_OPA, bg_opa, lv_opa_t, _opa, scalar) + 13730: 227f movs r2, #127 ; 0x7f + 13732: f241 012c movw r1, #4140 ; 0x102c + 13736: 30a4 adds r0, #164 ; 0xa4 + 13738: 47c8 blx r9 + lv_style_set_bg_color(&styles->tabview_btns, LV_STATE_PRESSED, lv_color_hex3(0x888)); + 1373a: 6823 ldr r3, [r4, #0] + 1373c: f640 0088 movw r0, #2184 ; 0x888 + 13740: f103 0ba4 add.w fp, r3, #164 ; 0xa4 + 13744: 47d0 blx sl +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_COLOR, bg_color, lv_color_t, _color, nonscalar) + 13746: f241 0129 movw r1, #4137 ; 0x1029 + 1374a: 4602 mov r2, r0 + 1374c: 4658 mov r0, fp + 1374e: 47b8 blx r7 + lv_style_set_text_color(&styles->tabview_btns, LV_STATE_CHECKED, COLOR_SCR_TEXT); + 13750: 6823 ldr r3, [r4, #0] + 13752: f103 0aa4 add.w sl, r3, #164 ; 0xa4 + 13756: 6a23 ldr r3, [r4, #32] + 13758: 079a lsls r2, r3, #30 + 1375a: bf4c ite mi + 1375c: 4852 ldrmi r0, [pc, #328] ; (138a8 ) + 1375e: 4853 ldrpl r0, [pc, #332] ; (138ac ) + 13760: 47c0 blx r8 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_COLOR, text_color, lv_color_t, _color, nonscalar) + 13762: f248 1189 movw r1, #33161 ; 0x8189 + 13766: 4602 mov r2, r0 + 13768: 4650 mov r0, sl + 1376a: 47b8 blx r7 + lv_style_set_pad_top(&styles->tabview_btns, LV_STATE_DEFAULT, LV_DPX(20)); + 1376c: 6823 ldr r3, [r4, #0] + 1376e: 2000 movs r0, #0 + 13770: f103 0aa4 add.w sl, r3, #164 ; 0xa4 + 13774: 47a8 blx r5 + 13776: eb00 0080 add.w r0, r0, r0, lsl #2 + 1377a: 0080 lsls r0, r0, #2 + 1377c: 28ef cmp r0, #239 ; 0xef + 1377e: f340 8373 ble.w 13e68 + 13782: 2000 movs r0, #0 + 13784: 47a8 blx r5 + 13786: 2314 movs r3, #20 + 13788: 2250 movs r2, #80 ; 0x50 + 1378a: fb00 2203 mla r2, r0, r3, r2 + 1378e: 23a0 movs r3, #160 ; 0xa0 + 13790: fb92 f2f3 sdiv r2, r2, r3 + 13794: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_TOP, pad_top, lv_style_int_t, _int, scalar) + 13796: 4650 mov r0, sl + 13798: 2110 movs r1, #16 + 1379a: 47b0 blx r6 + lv_style_set_pad_bottom(&styles->tabview_btns, LV_STATE_DEFAULT, LV_DPX(20)); + 1379c: 6823 ldr r3, [r4, #0] + 1379e: 2000 movs r0, #0 + 137a0: f103 0aa4 add.w sl, r3, #164 ; 0xa4 + 137a4: 47a8 blx r5 + 137a6: eb00 0080 add.w r0, r0, r0, lsl #2 + 137aa: 0080 lsls r0, r0, #2 + 137ac: 28ef cmp r0, #239 ; 0xef + 137ae: f340 835d ble.w 13e6c + 137b2: 2000 movs r0, #0 + 137b4: 47a8 blx r5 + 137b6: 2314 movs r3, #20 + 137b8: 2250 movs r2, #80 ; 0x50 + 137ba: fb00 2203 mla r2, r0, r3, r2 + 137be: 23a0 movs r3, #160 ; 0xa0 + 137c0: fb92 f2f3 sdiv r2, r2, r3 + 137c4: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_BOTTOM, pad_bottom, lv_style_int_t, _int, scalar) + 137c6: 2111 movs r1, #17 + 137c8: 4650 mov r0, sl + 137ca: 47b0 blx r6 + lv_style_set_text_color(&styles->tabview_btns, LV_STATE_FOCUSED, theme.color_primary); + 137cc: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_COLOR, text_color, lv_color_t, _color, nonscalar) + 137ce: 89a2 ldrh r2, [r4, #12] + 137d0: f248 2189 movw r1, #33417 ; 0x8289 + 137d4: 30a4 adds r0, #164 ; 0xa4 + 137d6: 47b8 blx r7 + lv_style_set_text_color(&styles->tabview_btns, LV_STATE_EDITED, theme.color_secondary); + 137d8: 6820 ldr r0, [r4, #0] + 137da: 89e2 ldrh r2, [r4, #14] + 137dc: f248 4189 movw r1, #33929 ; 0x8489 + 137e0: 30a4 adds r0, #164 ; 0xa4 + 137e2: 47b8 blx r7 + style_init_reset(&styles->tabview_indic); + 137e4: 6820 ldr r0, [r4, #0] + 137e6: 9b01 ldr r3, [sp, #4] + 137e8: 30ac adds r0, #172 ; 0xac + 137ea: 4798 blx r3 + lv_style_set_bg_opa(&styles->tabview_indic, LV_STATE_DEFAULT, LV_OPA_COVER); + 137ec: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_OPA, bg_opa, lv_opa_t, _opa, scalar) + 137ee: 22ff movs r2, #255 ; 0xff + 137f0: 212c movs r1, #44 ; 0x2c + 137f2: 30ac adds r0, #172 ; 0xac + 137f4: 47c8 blx r9 + lv_style_set_bg_color(&styles->tabview_indic, LV_STATE_DEFAULT, theme.color_primary); + 137f6: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BG_COLOR, bg_color, lv_color_t, _color, nonscalar) + 137f8: 89a2 ldrh r2, [r4, #12] + 137fa: 2129 movs r1, #41 ; 0x29 + 137fc: 30ac adds r0, #172 ; 0xac + 137fe: 47b8 blx r7 + lv_style_set_bg_color(&styles->tabview_indic, LV_STATE_EDITED, theme.color_secondary); + 13800: 6820 ldr r0, [r4, #0] + 13802: 89e2 ldrh r2, [r4, #14] + 13804: f240 4129 movw r1, #1065 ; 0x429 + 13808: 30ac adds r0, #172 ; 0xac + 1380a: 47b8 blx r7 + lv_style_set_size(&styles->tabview_indic, LV_STATE_DEFAULT, LV_DPX(5)); + 1380c: 6823 ldr r3, [r4, #0] + 1380e: 2000 movs r0, #0 + 13810: f103 09ac add.w r9, r3, #172 ; 0xac + 13814: 47a8 blx r5 + 13816: eb00 0080 add.w r0, r0, r0, lsl #2 + 1381a: 28ef cmp r0, #239 ; 0xef + 1381c: f340 8328 ble.w 13e70 + 13820: 2000 movs r0, #0 + 13822: 47a8 blx r5 + 13824: 2305 movs r3, #5 + 13826: 2250 movs r2, #80 ; 0x50 + 13828: fb00 2203 mla r2, r0, r3, r2 + 1382c: 23a0 movs r3, #160 ; 0xa0 + 1382e: fb92 f2f3 sdiv r2, r2, r3 + 13832: b212 sxth r2, r2 +_LV_OBJ_STYLE_SET_GET_DECLARE(SIZE, size, lv_style_int_t, _int, scalar) + 13834: 4648 mov r0, r9 + 13836: 2103 movs r1, #3 + 13838: 47b0 blx r6 + lv_style_set_radius(&styles->tabview_indic, LV_STATE_DEFAULT, LV_RADIUS_CIRCLE); + 1383a: 6820 ldr r0, [r4, #0] + lv_style_set_pad_top(&styles->tabview_page_scrl, LV_STATE_DEFAULT, PAD_DEF); + 1383c: f8df 9080 ldr.w r9, [pc, #128] ; 138c0 +_LV_OBJ_STYLE_SET_GET_DECLARE(RADIUS, radius, lv_style_int_t, _int, scalar) + 13840: f647 72ff movw r2, #32767 ; 0x7fff + 13844: 2101 movs r1, #1 + 13846: 30ac adds r0, #172 ; 0xac + 13848: 47b0 blx r6 + style_init_reset(&styles->tabview_page_scrl); + 1384a: 6820 ldr r0, [r4, #0] + 1384c: 9b01 ldr r3, [sp, #4] + 1384e: 30b0 adds r0, #176 ; 0xb0 + 13850: 4798 blx r3 + lv_style_set_pad_top(&styles->tabview_page_scrl, LV_STATE_DEFAULT, PAD_DEF); + 13852: 6823 ldr r3, [r4, #0] + 13854: 2000 movs r0, #0 + 13856: f103 0ab0 add.w sl, r3, #176 ; 0xb0 + 1385a: 47c8 blx r9 + 1385c: 2801 cmp r0, #1 + 1385e: f04f 0000 mov.w r0, #0 + 13862: f200 8312 bhi.w 13e8a + 13866: 47a8 blx r5 + 13868: ebc0 1000 rsb r0, r0, r0, lsl #4 + 1386c: 28ef cmp r0, #239 ; 0xef + 1386e: f300 8301 bgt.w 13e74 + 13872: 2201 movs r2, #1 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_TOP, pad_top, lv_style_int_t, _int, scalar) + 13874: 4650 mov r0, sl + 13876: 2110 movs r1, #16 + 13878: 47b0 blx r6 + lv_style_set_pad_bottom(&styles->tabview_page_scrl, LV_STATE_DEFAULT, PAD_DEF); + 1387a: 6823 ldr r3, [r4, #0] + 1387c: 2000 movs r0, #0 + 1387e: f103 0ab0 add.w sl, r3, #176 ; 0xb0 + 13882: 47c8 blx r9 + 13884: 2801 cmp r0, #1 + 13886: f04f 0000 mov.w r0, #0 + 1388a: f200 8314 bhi.w 13eb6 + 1388e: 47a8 blx r5 + 13890: ebc0 1000 rsb r0, r0, r0, lsl #4 + 13894: 28ef cmp r0, #239 ; 0xef + 13896: f300 8303 bgt.w 13ea0 + 1389a: e013 b.n 138c4 + 1389c: 00024272 .word 0x00024272 + 138a0: 00586273 .word 0x00586273 + 138a4: 00e4eaf0 .word 0x00e4eaf0 + 138a8: 003b3e42 .word 0x003b3e42 + 138ac: 00e7e9ec .word 0x00e7e9ec + 138b0: 00005aed .word 0x00005aed + 138b4: 00979a9f .word 0x00979a9f + 138b8: 00010abd .word 0x00010abd + 138bc: 00010e9d .word 0x00010e9d + 138c0: 0000d969 .word 0x0000d969 + 138c4: 2201 movs r2, #1 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_BOTTOM, pad_bottom, lv_style_int_t, _int, scalar) + 138c6: 4650 mov r0, sl + 138c8: 2111 movs r1, #17 + 138ca: 47b0 blx r6 + lv_style_set_pad_left(&styles->tabview_page_scrl, LV_STATE_DEFAULT, PAD_DEF); + 138cc: 6823 ldr r3, [r4, #0] + 138ce: 2000 movs r0, #0 + 138d0: f103 0ab0 add.w sl, r3, #176 ; 0xb0 + 138d4: 47c8 blx r9 + 138d6: 2801 cmp r0, #1 + 138d8: f04f 0000 mov.w r0, #0 + 138dc: f200 8301 bhi.w 13ee2 + 138e0: 47a8 blx r5 + 138e2: ebc0 1000 rsb r0, r0, r0, lsl #4 + 138e6: 28ef cmp r0, #239 ; 0xef + 138e8: f300 82f0 bgt.w 13ecc + 138ec: 2201 movs r2, #1 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_LEFT, pad_left, lv_style_int_t, _int, scalar) + 138ee: 4650 mov r0, sl + 138f0: 2112 movs r1, #18 + 138f2: 47b0 blx r6 + lv_style_set_pad_right(&styles->tabview_page_scrl, LV_STATE_DEFAULT, PAD_DEF); + 138f4: 6823 ldr r3, [r4, #0] + 138f6: 2000 movs r0, #0 + 138f8: f103 0ab0 add.w sl, r3, #176 ; 0xb0 + 138fc: 47c8 blx r9 + 138fe: 2801 cmp r0, #1 + 13900: f04f 0000 mov.w r0, #0 + 13904: f200 8303 bhi.w 13f0e + 13908: 47a8 blx r5 + 1390a: ebc0 1000 rsb r0, r0, r0, lsl #4 + 1390e: 28ef cmp r0, #239 ; 0xef + 13910: f300 82f2 bgt.w 13ef8 + 13914: 2201 movs r2, #1 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_RIGHT, pad_right, lv_style_int_t, _int, scalar) + 13916: 4650 mov r0, sl + 13918: 2113 movs r1, #19 + 1391a: 47b0 blx r6 + lv_style_set_pad_inner(&styles->tabview_page_scrl, LV_STATE_DEFAULT, PAD_DEF); + 1391c: 6823 ldr r3, [r4, #0] + 1391e: 2000 movs r0, #0 + 13920: f103 0ab0 add.w sl, r3, #176 ; 0xb0 + 13924: 47c8 blx r9 + 13926: 2801 cmp r0, #1 + 13928: f04f 0000 mov.w r0, #0 + 1392c: f200 8305 bhi.w 13f3a + 13930: 47a8 blx r5 + 13932: ebc0 1000 rsb r0, r0, r0, lsl #4 + 13936: 28ef cmp r0, #239 ; 0xef + 13938: f300 82f4 bgt.w 13f24 + 1393c: 2201 movs r2, #1 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_INNER, pad_inner, lv_style_int_t, _int, scalar) + 1393e: 2114 movs r1, #20 + 13940: 4650 mov r0, sl + 13942: 47b0 blx r6 + style_init_reset(&styles->table_cell); + 13944: 6820 ldr r0, [r4, #0] + 13946: 9b01 ldr r3, [sp, #4] + 13948: 30a0 adds r0, #160 ; 0xa0 + 1394a: 4798 blx r3 + lv_style_set_border_color(&styles->table_cell, LV_STATE_DEFAULT, COLOR_BG_BORDER); + 1394c: 6823 ldr r3, [r4, #0] + 1394e: f103 0aa0 add.w sl, r3, #160 ; 0xa0 + 13952: 6a23 ldr r3, [r4, #32] + 13954: 079b lsls r3, r3, #30 + 13956: bf4c ite mi + 13958: 48c9 ldrmi r0, [pc, #804] ; (13c80 ) + 1395a: 48ca ldrpl r0, [pc, #808] ; (13c84 ) + 1395c: 47c0 blx r8 +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_COLOR, border_color, lv_color_t, _color, nonscalar) + 1395e: 2139 movs r1, #57 ; 0x39 + 13960: 4602 mov r2, r0 + 13962: 4650 mov r0, sl + 13964: 47b8 blx r7 + lv_style_set_border_width(&styles->table_cell, LV_STATE_DEFAULT, 1); + 13966: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_WIDTH, border_width, lv_style_int_t, _int, scalar) + 13968: 2201 movs r2, #1 + 1396a: 2130 movs r1, #48 ; 0x30 + 1396c: 30a0 adds r0, #160 ; 0xa0 + 1396e: 47b0 blx r6 + lv_style_set_border_side(&styles->table_cell, LV_STATE_DEFAULT, LV_BORDER_SIDE_TOP | LV_BORDER_SIDE_BOTTOM); + 13970: 6820 ldr r0, [r4, #0] +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_SIDE, border_side, lv_border_side_t, _int, scalar) + 13972: 2203 movs r2, #3 + 13974: 2131 movs r1, #49 ; 0x31 + 13976: 30a0 adds r0, #160 ; 0xa0 + 13978: 47b0 blx r6 + lv_style_set_pad_left(&styles->table_cell, LV_STATE_DEFAULT, PAD_DEF); + 1397a: 2000 movs r0, #0 + 1397c: 6827 ldr r7, [r4, #0] + 1397e: 47c8 blx r9 + 13980: 2801 cmp r0, #1 + 13982: f107 07a0 add.w r7, r7, #160 ; 0xa0 + 13986: f04f 0000 mov.w r0, #0 + 1398a: f200 82ec bhi.w 13f66 + 1398e: 47a8 blx r5 + 13990: ebc0 1000 rsb r0, r0, r0, lsl #4 + 13994: 28ef cmp r0, #239 ; 0xef + 13996: f300 82db bgt.w 13f50 + 1399a: 2201 movs r2, #1 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_LEFT, pad_left, lv_style_int_t, _int, scalar) + 1399c: 2112 movs r1, #18 + 1399e: 4638 mov r0, r7 + 139a0: 47b0 blx r6 + lv_style_set_pad_right(&styles->table_cell, LV_STATE_DEFAULT, PAD_DEF); + 139a2: 2000 movs r0, #0 + 139a4: 6824 ldr r4, [r4, #0] + 139a6: 47c8 blx r9 + 139a8: 2801 cmp r0, #1 + 139aa: f104 04a0 add.w r4, r4, #160 ; 0xa0 + 139ae: f04f 0000 mov.w r0, #0 + 139b2: f200 82ee bhi.w 13f92 + 139b6: 47a8 blx r5 + 139b8: ebc0 1000 rsb r0, r0, r0, lsl #4 + 139bc: 28ef cmp r0, #239 ; 0xef + 139be: f300 82dd bgt.w 13f7c + 139c2: 2201 movs r2, #1 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_RIGHT, pad_right, lv_style_int_t, _int, scalar) + 139c4: 4620 mov r0, r4 + 139c6: 2113 movs r1, #19 + lv_style_set_pad_top(&styles->table_cell, LV_STATE_DEFAULT, PAD_DEF); + 139c8: 4caf ldr r4, [pc, #700] ; (13c88 ) + 139ca: 47b0 blx r6 + 139cc: 2000 movs r0, #0 + 139ce: 6827 ldr r7, [r4, #0] + 139d0: 47c8 blx r9 + 139d2: 2801 cmp r0, #1 + 139d4: f107 07a0 add.w r7, r7, #160 ; 0xa0 + 139d8: f04f 0000 mov.w r0, #0 + 139dc: f200 82ef bhi.w 13fbe + 139e0: 47a8 blx r5 + 139e2: ebc0 1000 rsb r0, r0, r0, lsl #4 + 139e6: 28ef cmp r0, #239 ; 0xef + 139e8: f300 82de bgt.w 13fa8 + 139ec: 2201 movs r2, #1 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_TOP, pad_top, lv_style_int_t, _int, scalar) + 139ee: 2110 movs r1, #16 + 139f0: 4638 mov r0, r7 + 139f2: 47b0 blx r6 + lv_style_set_pad_bottom(&styles->table_cell, LV_STATE_DEFAULT, PAD_DEF); + 139f4: 2000 movs r0, #0 + 139f6: 6825 ldr r5, [r4, #0] + 139f8: 4ea4 ldr r6, [pc, #656] ; (13c8c ) + 139fa: 47c8 blx r9 + 139fc: 2801 cmp r0, #1 + 139fe: f105 05a0 add.w r5, r5, #160 ; 0xa0 + 13a02: f04f 0000 mov.w r0, #0 + 13a06: f200 82f0 bhi.w 13fea + 13a0a: 47b0 blx r6 + 13a0c: ebc0 1000 rsb r0, r0, r0, lsl #4 + 13a10: 28ef cmp r0, #239 ; 0xef + 13a12: f300 82df bgt.w 13fd4 + 13a16: 2201 movs r2, #1 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_BOTTOM, pad_bottom, lv_style_int_t, _int, scalar) + 13a18: 2111 movs r1, #17 + 13a1a: 4628 mov r0, r5 + 13a1c: 4b9c ldr r3, [pc, #624] ; (13c90 ) + 13a1e: 4798 blx r3 + theme.apply_xcb = theme_apply; + 13a20: 4b9c ldr r3, [pc, #624] ; (13c94 ) + 13a22: 60a3 str r3, [r4, #8] + inited = true; + 13a24: 2301 movs r3, #1 + 13a26: 7123 strb r3, [r4, #4] + lv_obj_report_style_mod(NULL); + 13a28: 2000 movs r0, #0 + 13a2a: 4b9b ldr r3, [pc, #620] ; (13c98 ) + 13a2c: 4798 blx r3 +} + 13a2e: 489b ldr r0, [pc, #620] ; (13c9c ) + 13a30: b003 add sp, #12 + 13a32: ecbd 8b02 vpop {d8} + 13a36: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + lv_style_set_line_width(&styles->arc_indic, LV_STATE_DEFAULT, LV_DPX(25)); + 13a3a: 2201 movs r2, #1 + 13a3c: f7fe bdb1 b.w 125a2 + lv_style_set_line_width(&styles->arc_bg, LV_STATE_DEFAULT, LV_DPX(25)); + 13a40: 2201 movs r2, #1 + 13a42: f7fe bde0 b.w 12606 + lv_style_set_pad_top(&styles->calendar_header, LV_STATE_DEFAULT, PAD_DEF); + 13a46: 2000 movs r0, #0 + 13a48: 47a8 blx r5 + 13a4a: 230f movs r3, #15 + 13a4c: 2250 movs r2, #80 ; 0x50 + 13a4e: fb00 2203 mla r2, r0, r3, r2 + 13a52: 23a0 movs r3, #160 ; 0xa0 + 13a54: fb92 f2f3 sdiv r2, r2, r3 + 13a58: b212 sxth r2, r2 + 13a5a: f7fe bdf4 b.w 12646 + 13a5e: 47a8 blx r5 + 13a60: ebc0 1000 rsb r0, r0, r0, lsl #4 + 13a64: 0040 lsls r0, r0, #1 + 13a66: 28ef cmp r0, #239 ; 0xef + 13a68: f77e adec ble.w 12644 + 13a6c: 2000 movs r0, #0 + 13a6e: 47a8 blx r5 + 13a70: 231e movs r3, #30 + 13a72: e7eb b.n 13a4c + lv_style_set_pad_left(&styles->calendar_header, LV_STATE_DEFAULT, PAD_DEF); + 13a74: 2000 movs r0, #0 + 13a76: 47a8 blx r5 + 13a78: 230f movs r3, #15 + 13a7a: 2250 movs r2, #80 ; 0x50 + 13a7c: fb00 2203 mla r2, r0, r3, r2 + 13a80: 23a0 movs r3, #160 ; 0xa0 + 13a82: fb92 f2f3 sdiv r2, r2, r3 + 13a86: b212 sxth r2, r2 + 13a88: f7fe bdf1 b.w 1266e + 13a8c: 47a8 blx r5 + 13a8e: ebc0 1000 rsb r0, r0, r0, lsl #4 + 13a92: 0040 lsls r0, r0, #1 + 13a94: 28ef cmp r0, #239 ; 0xef + 13a96: f77e ade9 ble.w 1266c + 13a9a: 2000 movs r0, #0 + 13a9c: 47a8 blx r5 + 13a9e: 231e movs r3, #30 + 13aa0: e7eb b.n 13a7a + lv_style_set_pad_right(&styles->calendar_header, LV_STATE_DEFAULT, PAD_DEF); + 13aa2: 2000 movs r0, #0 + 13aa4: 47a8 blx r5 + 13aa6: 230f movs r3, #15 + 13aa8: 2250 movs r2, #80 ; 0x50 + 13aaa: fb00 2203 mla r2, r0, r3, r2 + 13aae: 23a0 movs r3, #160 ; 0xa0 + 13ab0: fb92 f2f3 sdiv r2, r2, r3 + 13ab4: b212 sxth r2, r2 + 13ab6: f7fe bdee b.w 12696 + 13aba: 47a8 blx r5 + 13abc: ebc0 1000 rsb r0, r0, r0, lsl #4 + 13ac0: 0040 lsls r0, r0, #1 + 13ac2: 28ef cmp r0, #239 ; 0xef + 13ac4: f77e ade6 ble.w 12694 + 13ac8: 2000 movs r0, #0 + 13aca: 47a8 blx r5 + 13acc: 231e movs r3, #30 + 13ace: e7eb b.n 13aa8 + lv_style_set_pad_bottom(&styles->calendar_header, LV_STATE_DEFAULT, PAD_DEF); + 13ad0: 2000 movs r0, #0 + 13ad2: 47a8 blx r5 + 13ad4: 230f movs r3, #15 + 13ad6: 2250 movs r2, #80 ; 0x50 + 13ad8: fb00 2203 mla r2, r0, r3, r2 + 13adc: 23a0 movs r3, #160 ; 0xa0 + 13ade: fb92 f2f3 sdiv r2, r2, r3 + 13ae2: b212 sxth r2, r2 + 13ae4: f7fe bdeb b.w 126be + 13ae8: 47a8 blx r5 + 13aea: ebc0 1000 rsb r0, r0, r0, lsl #4 + 13aee: 0040 lsls r0, r0, #1 + 13af0: 28ef cmp r0, #239 ; 0xef + 13af2: f77e ade3 ble.w 126bc + 13af6: 2000 movs r0, #0 + 13af8: 47a8 blx r5 + 13afa: 231e movs r3, #30 + 13afc: e7eb b.n 13ad6 + lv_style_set_text_color(&styles->calendar_header, LV_STATE_PRESSED, IS_LIGHT ? lv_color_hex(0x888888) : LV_COLOR_WHITE); + 13afe: f8bb 2000 ldrh.w r2, [fp] + 13b02: f7fe bdee b.w 126e2 + lv_style_set_text_color(&styles->calendar_daynames, LV_STATE_DEFAULT, IS_LIGHT ? lv_color_hex(0x31404f) : lv_color_hex3(0xeee)); + 13b06: 4b66 ldr r3, [pc, #408] ; (13ca0 ) + 13b08: f640 60ee movw r0, #3822 ; 0xeee + 13b0c: 4798 blx r3 + 13b0e: f7fe bdf9 b.w 12704 + lv_style_set_pad_left(&styles->calendar_daynames, LV_STATE_DEFAULT, PAD_DEF); + 13b12: 2000 movs r0, #0 + 13b14: 47a8 blx r5 + 13b16: 230f movs r3, #15 + 13b18: 2250 movs r2, #80 ; 0x50 + 13b1a: fb00 2203 mla r2, r0, r3, r2 + 13b1e: 23a0 movs r3, #160 ; 0xa0 + 13b20: fb92 f2f3 sdiv r2, r2, r3 + 13b24: b212 sxth r2, r2 + 13b26: f7fe be05 b.w 12734 + 13b2a: 47a8 blx r5 + 13b2c: ebc0 1000 rsb r0, r0, r0, lsl #4 + 13b30: 0040 lsls r0, r0, #1 + 13b32: 28ef cmp r0, #239 ; 0xef + 13b34: f77e adfd ble.w 12732 + 13b38: 2000 movs r0, #0 + 13b3a: 47a8 blx r5 + 13b3c: 231e movs r3, #30 + 13b3e: e7eb b.n 13b18 + lv_style_set_pad_right(&styles->calendar_daynames, LV_STATE_DEFAULT, PAD_DEF); + 13b40: 2000 movs r0, #0 + 13b42: 47a8 blx r5 + 13b44: 230f movs r3, #15 + 13b46: 2250 movs r2, #80 ; 0x50 + 13b48: fb00 2203 mla r2, r0, r3, r2 + 13b4c: 23a0 movs r3, #160 ; 0xa0 + 13b4e: fb92 f2f3 sdiv r2, r2, r3 + 13b52: b212 sxth r2, r2 + 13b54: f7fe be04 b.w 12760 + 13b58: 47a8 blx r5 + 13b5a: ebc0 1000 rsb r0, r0, r0, lsl #4 + 13b5e: 0040 lsls r0, r0, #1 + 13b60: 28ef cmp r0, #239 ; 0xef + 13b62: f77e adfc ble.w 1275e + 13b66: 2000 movs r0, #0 + 13b68: 47a8 blx r5 + 13b6a: 231e movs r3, #30 + 13b6c: e7eb b.n 13b46 + lv_style_set_pad_bottom(&styles->calendar_daynames, LV_STATE_DEFAULT, PAD_DEF); + 13b6e: 2000 movs r0, #0 + 13b70: 47a8 blx r5 + 13b72: 230f movs r3, #15 + 13b74: 2250 movs r2, #80 ; 0x50 + 13b76: fb00 2203 mla r2, r0, r3, r2 + 13b7a: 23a0 movs r3, #160 ; 0xa0 + 13b7c: fb92 f2f3 sdiv r2, r2, r3 + 13b80: b212 sxth r2, r2 + 13b82: f7fe be03 b.w 1278c + 13b86: 47a8 blx r5 + 13b88: ebc0 1000 rsb r0, r0, r0, lsl #4 + 13b8c: 0040 lsls r0, r0, #1 + 13b8e: 28ef cmp r0, #239 ; 0xef + 13b90: f77e adfb ble.w 1278a + 13b94: 2000 movs r0, #0 + 13b96: 47a8 blx r5 + 13b98: 231e movs r3, #30 + 13b9a: e7eb b.n 13b74 + lv_style_set_radius(&styles->calendar_date_nums, LV_STATE_DEFAULT, LV_DPX(4)); + 13b9c: 2201 movs r2, #1 + 13b9e: f7fe be0d b.w 127bc + lv_style_set_text_color(&styles->calendar_date_nums, LV_STATE_CHECKED, IS_LIGHT ? lv_color_hex(0x31404f) : LV_COLOR_WHITE); + 13ba2: f8bb 2000 ldrh.w r2, [fp] + 13ba6: f7fe be47 b.w 12838 + lv_style_set_bg_color(&styles->calendar_date_nums, LV_STATE_DEFAULT, IS_LIGHT ? lv_color_hex(0x666666) : LV_COLOR_WHITE); + 13baa: f8bd 2004 ldrh.w r2, [sp, #4] + 13bae: f7fe be7d b.w 128ac + lv_style_set_pad_inner(&styles->calendar_date_nums, LV_STATE_DEFAULT, LV_DPX(3)); + 13bb2: 2201 movs r2, #1 + 13bb4: f7fe beaa b.w 1290c + lv_style_set_pad_left(&styles->calendar_date_nums, LV_STATE_DEFAULT, PAD_DEF); + 13bb8: 2000 movs r0, #0 + 13bba: 47a8 blx r5 + 13bbc: 230f movs r3, #15 + 13bbe: 2250 movs r2, #80 ; 0x50 + 13bc0: fb00 2203 mla r2, r0, r3, r2 + 13bc4: 23a0 movs r3, #160 ; 0xa0 + 13bc6: fb92 f2f3 sdiv r2, r2, r3 + 13bca: b212 sxth r2, r2 + 13bcc: f7fe beb4 b.w 12938 + 13bd0: 47a8 blx r5 + 13bd2: ebc0 1000 rsb r0, r0, r0, lsl #4 + 13bd6: 0040 lsls r0, r0, #1 + 13bd8: 28ef cmp r0, #239 ; 0xef + 13bda: f77e aeac ble.w 12936 + 13bde: 2000 movs r0, #0 + 13be0: 47a8 blx r5 + 13be2: 231e movs r3, #30 + 13be4: e7eb b.n 13bbe + lv_style_set_pad_right(&styles->calendar_date_nums, LV_STATE_DEFAULT, PAD_DEF); + 13be6: 2000 movs r0, #0 + 13be8: 47a8 blx r5 + 13bea: 230f movs r3, #15 + 13bec: 2250 movs r2, #80 ; 0x50 + 13bee: fb00 2203 mla r2, r0, r3, r2 + 13bf2: 23a0 movs r3, #160 ; 0xa0 + 13bf4: fb92 f2f3 sdiv r2, r2, r3 + 13bf8: b212 sxth r2, r2 + 13bfa: f7fe beb3 b.w 12964 + 13bfe: 47a8 blx r5 + 13c00: ebc0 1000 rsb r0, r0, r0, lsl #4 + 13c04: 0040 lsls r0, r0, #1 + 13c06: 28ef cmp r0, #239 ; 0xef + 13c08: f77e aeab ble.w 12962 + 13c0c: 2000 movs r0, #0 + 13c0e: 47a8 blx r5 + 13c10: 231e movs r3, #30 + 13c12: e7eb b.n 13bec + lv_style_set_pad_bottom(&styles->calendar_date_nums, LV_STATE_DEFAULT, PAD_DEF); + 13c14: 2000 movs r0, #0 + 13c16: 47a8 blx r5 + 13c18: 230f movs r3, #15 + 13c1a: 2250 movs r2, #80 ; 0x50 + 13c1c: fb00 2203 mla r2, r0, r3, r2 + 13c20: 23a0 movs r3, #160 ; 0xa0 + 13c22: fb92 f2f3 sdiv r2, r2, r3 + 13c26: b212 sxth r2, r2 + 13c28: f7fe beb2 b.w 12990 + 13c2c: 47a8 blx r5 + 13c2e: ebc0 1000 rsb r0, r0, r0, lsl #4 + 13c32: 0040 lsls r0, r0, #1 + 13c34: 28ef cmp r0, #239 ; 0xef + 13c36: f77e aeaa ble.w 1298e + 13c3a: 2000 movs r0, #0 + 13c3c: 47a8 blx r5 + 13c3e: 231e movs r3, #30 + 13c40: e7eb b.n 13c1a + lv_style_set_scale_width(&styles->cpicker_bg, LV_STATE_DEFAULT, LV_DPX(30)); + 13c42: 2201 movs r2, #1 + 13c44: f7fe bec0 b.w 129c8 + lv_style_set_pad_inner(&styles->cpicker_bg, LV_STATE_DEFAULT, LV_DPX(20)); + 13c48: 2201 movs r2, #1 + 13c4a: f7fe bee8 b.w 12a1e + lv_style_set_pad_left(&styles->cpicker_indic, LV_STATE_DEFAULT, LV_DPX(13)); + 13c4e: 2201 movs r2, #1 + 13c50: f7fe bf31 b.w 12ab6 + lv_style_set_pad_right(&styles->cpicker_indic, LV_STATE_DEFAULT, LV_DPX(13)); + 13c54: 2201 movs r2, #1 + 13c56: f7fe bf47 b.w 12ae8 + lv_style_set_pad_top(&styles->cpicker_indic, LV_STATE_DEFAULT, LV_DPX(13)); + 13c5a: 2201 movs r2, #1 + 13c5c: f7fe bf5d b.w 12b1a + lv_style_set_pad_bottom(&styles->cpicker_indic, LV_STATE_DEFAULT, LV_DPX(13)); + 13c60: 2201 movs r2, #1 + 13c62: f7fe bf7d b.w 12b60 + lv_style_set_radius(&styles->cb_bg, LV_STATE_DEFAULT, LV_DPX(4)); + 13c66: 2201 movs r2, #1 + 13c68: f7fe bf90 b.w 12b8c + lv_style_set_pad_inner(&styles->cb_bg, LV_STATE_DEFAULT, LV_DPX(10)); + 13c6c: 2201 movs r2, #1 + 13c6e: f7fe bfa5 b.w 12bbc + lv_style_set_outline_width(&styles->cb_bg, LV_STATE_DEFAULT, LV_DPX(3)); + 13c72: 2201 movs r2, #1 + 13c74: f7fe bfc9 b.w 12c0a + lv_style_set_outline_pad(&styles->cb_bg, LV_STATE_DEFAULT, LV_DPX(10)); + 13c78: 2201 movs r2, #1 + 13c7a: f7fe bfdf b.w 12c3c + 13c7e: bf00 nop + 13c80: 00d6dde3 .word 0x00d6dde3 + 13c84: 00808a97 .word 0x00808a97 + 13c88: 2000c7d4 .word 0x2000c7d4 + 13c8c: 0000d951 .word 0x0000d951 + 13c90: 00005879 .word 0x00005879 + 13c94: 00010329 .word 0x00010329 + 13c98: 00002f39 .word 0x00002f39 + 13c9c: 2000c7dc .word 0x2000c7dc + 13ca0: 000102f1 .word 0x000102f1 + lv_style_set_radius(&styles->cb_bullet, LV_STATE_DEFAULT, LV_DPX(4)); + 13ca4: 2201 movs r2, #1 + 13ca6: f7fe bff3 b.w 12c90 + lv_style_set_pad_left(&styles->cb_bullet, LV_STATE_DEFAULT, LV_DPX(3)); + 13caa: 2201 movs r2, #1 + 13cac: f7ff b81d b.w 12cea + lv_style_set_pad_right(&styles->cb_bullet, LV_STATE_DEFAULT, LV_DPX(3)); + 13cb0: 2201 movs r2, #1 + 13cb2: f7ff b831 b.w 12d18 + lv_style_set_pad_top(&styles->cb_bullet, LV_STATE_DEFAULT, LV_DPX(3)); + 13cb6: 2201 movs r2, #1 + 13cb8: f7ff b845 b.w 12d46 + lv_style_set_pad_bottom(&styles->cb_bullet, LV_STATE_DEFAULT, LV_DPX(3)); + 13cbc: 2201 movs r2, #1 + 13cbe: f7ff b859 b.w 12d74 + lv_style_set_border_width(&styles->kb_bg, LV_STATE_DEFAULT, LV_DPX(4)); + 13cc2: 2201 movs r2, #1 + 13cc4: f7ff b871 b.w 12daa + lv_style_set_border_color(&styles->kb_bg, LV_STATE_DEFAULT, IS_LIGHT ? COLOR_BG_TEXT : LV_COLOR_BLACK); + 13cc8: 4603 mov r3, r0 + 13cca: 4602 mov r2, r0 + 13ccc: f7ff b886 b.w 12ddc + lv_style_set_pad_left(&styles->kb_bg, LV_STATE_DEFAULT, LV_DPX(5)); + 13cd0: 2201 movs r2, #1 + 13cd2: f7ff b8a4 b.w 12e1e + lv_style_set_pad_right(&styles->kb_bg, LV_STATE_DEFAULT, LV_DPX(5)); + 13cd6: 2201 movs r2, #1 + 13cd8: f7ff b8b8 b.w 12e4c + lv_style_set_pad_top(&styles->kb_bg, LV_STATE_DEFAULT, LV_DPX(5)); + 13cdc: 2201 movs r2, #1 + 13cde: f7ff b8cc b.w 12e7a + lv_style_set_pad_bottom(&styles->kb_bg, LV_STATE_DEFAULT, LV_DPX(5)); + 13ce2: 2201 movs r2, #1 + 13ce4: f7ff b8e0 b.w 12ea8 + lv_style_set_pad_inner(&styles->kb_bg, LV_STATE_DEFAULT, LV_DPX(3)); + 13ce8: 2201 movs r2, #1 + 13cea: f7ff b8f4 b.w 12ed6 + lv_style_set_shadow_width(&styles->mbox_bg, LV_STATE_DEFAULT, LV_DPX(50)); + 13cee: 2201 movs r2, #1 + 13cf0: f7ff b91e b.w 12f30 + lv_style_set_shadow_color(&styles->mbox_bg, LV_STATE_DEFAULT, IS_LIGHT ? LV_COLOR_SILVER : lv_color_hex3(0x999)); + 13cf4: 4bc2 ldr r3, [pc, #776] ; (14000 ) + 13cf6: f640 1099 movw r0, #2457 ; 0x999 + 13cfa: 4798 blx r3 + 13cfc: 4602 mov r2, r0 + 13cfe: f7ff b923 b.w 12f48 + lv_style_set_size(&styles->sb, LV_STATE_DEFAULT, LV_DPX(7)); + 13d02: 2201 movs r2, #1 + 13d04: f7ff b952 b.w 12fac + lv_style_set_pad_right(&styles->sb, LV_STATE_DEFAULT, LV_DPX(7)); + 13d08: 2201 movs r2, #1 + 13d0a: f7ff b966 b.w 12fda + lv_style_set_pad_bottom(&styles->sb, LV_STATE_DEFAULT, LV_DPX(7)); + 13d0e: 2201 movs r2, #1 + 13d10: f7ff b97a b.w 13008 + lv_style_set_border_width(&styles->ta_cursor, LV_STATE_DEFAULT, LV_DPX(2)); + 13d14: 2201 movs r2, #1 + 13d16: f7ff b9ad b.w 13074 + lv_style_set_pad_left(&styles->ta_cursor, LV_STATE_DEFAULT, LV_DPX(1)); + 13d1a: 2201 movs r2, #1 + 13d1c: f7ff b9bd b.w 1309a + lv_style_set_text_color(&styles->ta_placeholder, LV_STATE_DEFAULT, IS_LIGHT ? COLOR_BG_TEXT_DIS : lv_color_hex(0xa1adbd)); + 13d20: 48b8 ldr r0, [pc, #736] ; (14004 ) + 13d22: 47b8 blx r7 + 13d24: f7ff b9cf b.w 130c6 + lv_style_set_pad_top(&styles->spinbox_cursor, LV_STATE_DEFAULT, LV_DPX(100)); + 13d28: 2201 movs r2, #1 + 13d2a: f7ff b9fa b.w 13122 + lv_style_set_pad_bottom(&styles->spinbox_cursor, LV_STATE_DEFAULT, LV_DPX(100)); + 13d2e: 2201 movs r2, #1 + 13d30: f7ff ba0f b.w 13152 + lv_style_set_pad_left(&styles->list_btn, LV_STATE_DEFAULT, PAD_DEF); + 13d34: 2000 movs r0, #0 + 13d36: 47a8 blx r5 + 13d38: 230f movs r3, #15 + 13d3a: 2250 movs r2, #80 ; 0x50 + 13d3c: fb00 2203 mla r2, r0, r3, r2 + 13d40: 23a0 movs r3, #160 ; 0xa0 + 13d42: fb92 f2f3 sdiv r2, r2, r3 + 13d46: b212 sxth r2, r2 + 13d48: f7ff bb10 b.w 1336c + 13d4c: 47a8 blx r5 + 13d4e: ebc0 1000 rsb r0, r0, r0, lsl #4 + 13d52: 0040 lsls r0, r0, #1 + 13d54: 28ef cmp r0, #239 ; 0xef + 13d56: f77f ab08 ble.w 1336a + 13d5a: 2000 movs r0, #0 + 13d5c: 47a8 blx r5 + 13d5e: 231e movs r3, #30 + 13d60: e7eb b.n 13d3a + lv_style_set_pad_right(&styles->list_btn, LV_STATE_DEFAULT, PAD_DEF); + 13d62: 2000 movs r0, #0 + 13d64: 47a8 blx r5 + 13d66: 230f movs r3, #15 + 13d68: 2250 movs r2, #80 ; 0x50 + 13d6a: fb00 2203 mla r2, r0, r3, r2 + 13d6e: 23a0 movs r3, #160 ; 0xa0 + 13d70: fb92 f2f3 sdiv r2, r2, r3 + 13d74: b212 sxth r2, r2 + 13d76: f7ff bb0d b.w 13394 + 13d7a: 47a8 blx r5 + 13d7c: ebc0 1000 rsb r0, r0, r0, lsl #4 + 13d80: 0040 lsls r0, r0, #1 + 13d82: 28ef cmp r0, #239 ; 0xef + 13d84: f77f ab05 ble.w 13392 + 13d88: 2000 movs r0, #0 + 13d8a: 47a8 blx r5 + 13d8c: 231e movs r3, #30 + 13d8e: e7eb b.n 13d68 + lv_style_set_pad_top(&styles->list_btn, LV_STATE_DEFAULT, PAD_DEF); + 13d90: 2000 movs r0, #0 + 13d92: 47a8 blx r5 + 13d94: 230f movs r3, #15 + 13d96: 2250 movs r2, #80 ; 0x50 + 13d98: fb00 2203 mla r2, r0, r3, r2 + 13d9c: 23a0 movs r3, #160 ; 0xa0 + 13d9e: fb92 f2f3 sdiv r2, r2, r3 + 13da2: b212 sxth r2, r2 + 13da4: f7ff bb0a b.w 133bc + 13da8: 47a8 blx r5 + 13daa: ebc0 1000 rsb r0, r0, r0, lsl #4 + 13dae: 0040 lsls r0, r0, #1 + 13db0: 28ef cmp r0, #239 ; 0xef + 13db2: f77f ab02 ble.w 133ba + 13db6: 2000 movs r0, #0 + 13db8: 47a8 blx r5 + 13dba: 231e movs r3, #30 + 13dbc: e7eb b.n 13d96 + lv_style_set_pad_bottom(&styles->list_btn, LV_STATE_DEFAULT, PAD_DEF); + 13dbe: 2000 movs r0, #0 + 13dc0: 47a8 blx r5 + 13dc2: 230f movs r3, #15 + 13dc4: 2250 movs r2, #80 ; 0x50 + 13dc6: fb00 2203 mla r2, r0, r3, r2 + 13dca: 23a0 movs r3, #160 ; 0xa0 + 13dcc: fb92 f2f3 sdiv r2, r2, r3 + 13dd0: b212 sxth r2, r2 + 13dd2: f7ff bb07 b.w 133e4 + 13dd6: 47a8 blx r5 + 13dd8: ebc0 1000 rsb r0, r0, r0, lsl #4 + 13ddc: 0040 lsls r0, r0, #1 + 13dde: 28ef cmp r0, #239 ; 0xef + 13de0: f77f aaff ble.w 133e2 + 13de4: 2000 movs r0, #0 + 13de6: 47a8 blx r5 + 13de8: 231e movs r3, #30 + 13dea: e7eb b.n 13dc4 + lv_style_set_pad_inner(&styles->list_btn, LV_STATE_DEFAULT, PAD_DEF); + 13dec: 2000 movs r0, #0 + 13dee: 47a8 blx r5 + 13df0: 230f movs r3, #15 + 13df2: 2250 movs r2, #80 ; 0x50 + 13df4: fb00 2203 mla r2, r0, r3, r2 + 13df8: 23a0 movs r3, #160 ; 0xa0 + 13dfa: fb92 f2f3 sdiv r2, r2, r3 + 13dfe: b212 sxth r2, r2 + 13e00: f7ff bb04 b.w 1340c + 13e04: 47a8 blx r5 + 13e06: ebc0 1000 rsb r0, r0, r0, lsl #4 + 13e0a: 0040 lsls r0, r0, #1 + 13e0c: 28ef cmp r0, #239 ; 0xef + 13e0e: f77f aafc ble.w 1340a + 13e12: 2000 movs r0, #0 + 13e14: 47a8 blx r5 + 13e16: 231e movs r3, #30 + 13e18: e7eb b.n 13df2 + lv_style_set_transform_width(&styles->list_btn, LV_STATE_DEFAULT, - PAD_DEF); + 13e1a: 2000 movs r0, #0 + 13e1c: 47a8 blx r5 + 13e1e: 230f movs r3, #15 + 13e20: 2250 movs r2, #80 ; 0x50 + 13e22: fb00 2203 mla r2, r0, r3, r2 + 13e26: f06f 039f mvn.w r3, #159 ; 0x9f + 13e2a: fb92 f2f3 sdiv r2, r2, r3 + 13e2e: b212 sxth r2, r2 + 13e30: f7ff bb01 b.w 13436 + 13e34: 47a8 blx r5 + 13e36: ebc0 1000 rsb r0, r0, r0, lsl #4 + 13e3a: 0040 lsls r0, r0, #1 + 13e3c: 28ef cmp r0, #239 ; 0xef + 13e3e: f77f aaf8 ble.w 13432 + 13e42: 2000 movs r0, #0 + 13e44: 47a8 blx r5 + 13e46: 231e movs r3, #30 + 13e48: e7ea b.n 13e20 + lv_style_set_text_line_space(&styles->ddlist_page, LV_STATE_DEFAULT, LV_DPX(20)); + 13e4a: 2201 movs r2, #1 + 13e4c: f7ff bb33 b.w 134b6 + lv_style_set_text_line_space(&styles->roller_bg, LV_STATE_DEFAULT, LV_DPX(25)); + 13e50: 2201 movs r2, #1 + 13e52: f7ff bba6 b.w 135a2 + lv_style_set_border_width(&styles->tabview_btns_bg, LV_STATE_DEFAULT, LV_DPX(5)); + 13e56: 2201 movs r2, #1 + 13e58: f7ff bbf9 b.w 1364e + lv_style_set_pad_top(&styles->tabview_btns_bg, LV_STATE_DEFAULT, LV_DPX(7)); + 13e5c: 2201 movs r2, #1 + 13e5e: e431 b.n 136c4 + lv_style_set_pad_left(&styles->tabview_btns_bg, LV_STATE_DEFAULT, LV_DPX(7)); + 13e60: 2201 movs r2, #1 + 13e62: e446 b.n 136f2 + lv_style_set_pad_right(&styles->tabview_btns_bg, LV_STATE_DEFAULT, LV_DPX(7)); + 13e64: 2201 movs r2, #1 + 13e66: e45b b.n 13720 + lv_style_set_pad_top(&styles->tabview_btns, LV_STATE_DEFAULT, LV_DPX(20)); + 13e68: 2201 movs r2, #1 + 13e6a: e494 b.n 13796 + lv_style_set_pad_bottom(&styles->tabview_btns, LV_STATE_DEFAULT, LV_DPX(20)); + 13e6c: 2201 movs r2, #1 + 13e6e: e4aa b.n 137c6 + lv_style_set_size(&styles->tabview_indic, LV_STATE_DEFAULT, LV_DPX(5)); + 13e70: 2201 movs r2, #1 + 13e72: e4df b.n 13834 + lv_style_set_pad_top(&styles->tabview_page_scrl, LV_STATE_DEFAULT, PAD_DEF); + 13e74: 2000 movs r0, #0 + 13e76: 47a8 blx r5 + 13e78: 230f movs r3, #15 + 13e7a: 2250 movs r2, #80 ; 0x50 + 13e7c: fb00 2203 mla r2, r0, r3, r2 + 13e80: 23a0 movs r3, #160 ; 0xa0 + 13e82: fb92 f2f3 sdiv r2, r2, r3 + 13e86: b212 sxth r2, r2 + 13e88: e4f4 b.n 13874 + 13e8a: 47a8 blx r5 + 13e8c: ebc0 1000 rsb r0, r0, r0, lsl #4 + 13e90: 0040 lsls r0, r0, #1 + 13e92: 28ef cmp r0, #239 ; 0xef + 13e94: f77f aced ble.w 13872 + 13e98: 2000 movs r0, #0 + 13e9a: 47a8 blx r5 + 13e9c: 231e movs r3, #30 + 13e9e: e7ec b.n 13e7a + lv_style_set_pad_bottom(&styles->tabview_page_scrl, LV_STATE_DEFAULT, PAD_DEF); + 13ea0: 2000 movs r0, #0 + 13ea2: 47a8 blx r5 + 13ea4: 230f movs r3, #15 + 13ea6: 2250 movs r2, #80 ; 0x50 + 13ea8: fb00 2203 mla r2, r0, r3, r2 + 13eac: 23a0 movs r3, #160 ; 0xa0 + 13eae: fb92 f2f3 sdiv r2, r2, r3 + 13eb2: b212 sxth r2, r2 + 13eb4: e507 b.n 138c6 + 13eb6: 47a8 blx r5 + 13eb8: ebc0 1000 rsb r0, r0, r0, lsl #4 + 13ebc: 0040 lsls r0, r0, #1 + 13ebe: 28ef cmp r0, #239 ; 0xef + 13ec0: f77f ad00 ble.w 138c4 + 13ec4: 2000 movs r0, #0 + 13ec6: 47a8 blx r5 + 13ec8: 231e movs r3, #30 + 13eca: e7ec b.n 13ea6 + lv_style_set_pad_left(&styles->tabview_page_scrl, LV_STATE_DEFAULT, PAD_DEF); + 13ecc: 2000 movs r0, #0 + 13ece: 47a8 blx r5 + 13ed0: 230f movs r3, #15 + 13ed2: 2250 movs r2, #80 ; 0x50 + 13ed4: fb00 2203 mla r2, r0, r3, r2 + 13ed8: 23a0 movs r3, #160 ; 0xa0 + 13eda: fb92 f2f3 sdiv r2, r2, r3 + 13ede: b212 sxth r2, r2 + 13ee0: e505 b.n 138ee + 13ee2: 47a8 blx r5 + 13ee4: ebc0 1000 rsb r0, r0, r0, lsl #4 + 13ee8: 0040 lsls r0, r0, #1 + 13eea: 28ef cmp r0, #239 ; 0xef + 13eec: f77f acfe ble.w 138ec + 13ef0: 2000 movs r0, #0 + 13ef2: 47a8 blx r5 + 13ef4: 231e movs r3, #30 + 13ef6: e7ec b.n 13ed2 + lv_style_set_pad_right(&styles->tabview_page_scrl, LV_STATE_DEFAULT, PAD_DEF); + 13ef8: 2000 movs r0, #0 + 13efa: 47a8 blx r5 + 13efc: 230f movs r3, #15 + 13efe: 2250 movs r2, #80 ; 0x50 + 13f00: fb00 2203 mla r2, r0, r3, r2 + 13f04: 23a0 movs r3, #160 ; 0xa0 + 13f06: fb92 f2f3 sdiv r2, r2, r3 + 13f0a: b212 sxth r2, r2 + 13f0c: e503 b.n 13916 + 13f0e: 47a8 blx r5 + 13f10: ebc0 1000 rsb r0, r0, r0, lsl #4 + 13f14: 0040 lsls r0, r0, #1 + 13f16: 28ef cmp r0, #239 ; 0xef + 13f18: f77f acfc ble.w 13914 + 13f1c: 2000 movs r0, #0 + 13f1e: 47a8 blx r5 + 13f20: 231e movs r3, #30 + 13f22: e7ec b.n 13efe + lv_style_set_pad_inner(&styles->tabview_page_scrl, LV_STATE_DEFAULT, PAD_DEF); + 13f24: 2000 movs r0, #0 + 13f26: 47a8 blx r5 + 13f28: 230f movs r3, #15 + 13f2a: 2250 movs r2, #80 ; 0x50 + 13f2c: fb00 2203 mla r2, r0, r3, r2 + 13f30: 23a0 movs r3, #160 ; 0xa0 + 13f32: fb92 f2f3 sdiv r2, r2, r3 + 13f36: b212 sxth r2, r2 + 13f38: e501 b.n 1393e + 13f3a: 47a8 blx r5 + 13f3c: ebc0 1000 rsb r0, r0, r0, lsl #4 + 13f40: 0040 lsls r0, r0, #1 + 13f42: 28ef cmp r0, #239 ; 0xef + 13f44: f77f acfa ble.w 1393c + 13f48: 2000 movs r0, #0 + 13f4a: 47a8 blx r5 + 13f4c: 231e movs r3, #30 + 13f4e: e7ec b.n 13f2a + lv_style_set_pad_left(&styles->table_cell, LV_STATE_DEFAULT, PAD_DEF); + 13f50: 2000 movs r0, #0 + 13f52: 47a8 blx r5 + 13f54: 230f movs r3, #15 + 13f56: 2250 movs r2, #80 ; 0x50 + 13f58: fb00 2203 mla r2, r0, r3, r2 + 13f5c: 23a0 movs r3, #160 ; 0xa0 + 13f5e: fb92 f2f3 sdiv r2, r2, r3 + 13f62: b212 sxth r2, r2 + 13f64: e51a b.n 1399c + 13f66: 47a8 blx r5 + 13f68: ebc0 1000 rsb r0, r0, r0, lsl #4 + 13f6c: 0040 lsls r0, r0, #1 + 13f6e: 28ef cmp r0, #239 ; 0xef + 13f70: f77f ad13 ble.w 1399a + 13f74: 2000 movs r0, #0 + 13f76: 47a8 blx r5 + 13f78: 231e movs r3, #30 + 13f7a: e7ec b.n 13f56 + lv_style_set_pad_right(&styles->table_cell, LV_STATE_DEFAULT, PAD_DEF); + 13f7c: 2000 movs r0, #0 + 13f7e: 47a8 blx r5 + 13f80: 230f movs r3, #15 + 13f82: 2250 movs r2, #80 ; 0x50 + 13f84: fb00 2203 mla r2, r0, r3, r2 + 13f88: 23a0 movs r3, #160 ; 0xa0 + 13f8a: fb92 f2f3 sdiv r2, r2, r3 + 13f8e: b212 sxth r2, r2 + 13f90: e518 b.n 139c4 + 13f92: 47a8 blx r5 + 13f94: ebc0 1000 rsb r0, r0, r0, lsl #4 + 13f98: 0040 lsls r0, r0, #1 + 13f9a: 28ef cmp r0, #239 ; 0xef + 13f9c: f77f ad11 ble.w 139c2 + 13fa0: 2000 movs r0, #0 + 13fa2: 47a8 blx r5 + 13fa4: 231e movs r3, #30 + 13fa6: e7ec b.n 13f82 + lv_style_set_pad_top(&styles->table_cell, LV_STATE_DEFAULT, PAD_DEF); + 13fa8: 2000 movs r0, #0 + 13faa: 47a8 blx r5 + 13fac: 230f movs r3, #15 + 13fae: 2250 movs r2, #80 ; 0x50 + 13fb0: fb00 2203 mla r2, r0, r3, r2 + 13fb4: 23a0 movs r3, #160 ; 0xa0 + 13fb6: fb92 f2f3 sdiv r2, r2, r3 + 13fba: b212 sxth r2, r2 + 13fbc: e517 b.n 139ee + 13fbe: 47a8 blx r5 + 13fc0: ebc0 1000 rsb r0, r0, r0, lsl #4 + 13fc4: 0040 lsls r0, r0, #1 + 13fc6: 28ef cmp r0, #239 ; 0xef + 13fc8: f77f ad10 ble.w 139ec + 13fcc: 2000 movs r0, #0 + 13fce: 47a8 blx r5 + 13fd0: 231e movs r3, #30 + 13fd2: e7ec b.n 13fae + lv_style_set_pad_bottom(&styles->table_cell, LV_STATE_DEFAULT, PAD_DEF); + 13fd4: 2000 movs r0, #0 + 13fd6: 47b0 blx r6 + 13fd8: 230f movs r3, #15 + 13fda: 2250 movs r2, #80 ; 0x50 + 13fdc: fb00 2203 mla r2, r0, r3, r2 + 13fe0: 23a0 movs r3, #160 ; 0xa0 + 13fe2: fb92 f2f3 sdiv r2, r2, r3 + 13fe6: b212 sxth r2, r2 + 13fe8: e516 b.n 13a18 + 13fea: 47b0 blx r6 + 13fec: ebc0 1000 rsb r0, r0, r0, lsl #4 + 13ff0: 0040 lsls r0, r0, #1 + 13ff2: 28ef cmp r0, #239 ; 0xef + 13ff4: f77f ad0f ble.w 13a16 + 13ff8: 2000 movs r0, #0 + 13ffa: 47b0 blx r6 + 13ffc: 231e movs r3, #30 + 13ffe: e7ec b.n 13fda + 14000: 000102f1 .word 0x000102f1 + 14004: 00a1adbd .word 0x00a1adbd + +00014008 : + * LV_DESIGN_DRAW: draw the object (always return 'true') + * LV_DESIGN_DRAW_POST: drawing after every children are drawn + * @param return an element of `lv_design_res_t` + */ +static lv_design_res_t lv_img_design(lv_obj_t * img, const lv_area_t * clip_area, lv_design_mode_t mode) +{ + 14008: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + lv_img_ext_t * ext = lv_obj_get_ext_attr(img); + 1400c: 4ba4 ldr r3, [pc, #656] ; (142a0 ) +{ + 1400e: b0a7 sub sp, #156 ; 0x9c + 14010: 4616 mov r6, r2 + 14012: 4604 mov r4, r0 + 14014: 460f mov r7, r1 + lv_img_ext_t * ext = lv_obj_get_ext_attr(img); + 14016: 4798 blx r3 + + if(mode == LV_DESIGN_COVER_CHK) { + 14018: 2e02 cmp r6, #2 + lv_img_ext_t * ext = lv_obj_get_ext_attr(img); + 1401a: 4605 mov r5, r0 + if(mode == LV_DESIGN_COVER_CHK) { + 1401c: d163 bne.n 140e6 + _OBJ_GET_STYLE_##scalar(prop_name, func_name, value_type, style_type) \ + _OBJ_SET_STYLE_LOCAL_##scalar(prop_name, func_name, value_type, style_type) \ + _OBJ_SET_STYLE_##scalar(prop_name, func_name, value_type, style_type) + +_LV_OBJ_STYLE_SET_GET_DECLARE(RADIUS, radius, lv_style_int_t, _int, scalar) +_LV_OBJ_STYLE_SET_GET_DECLARE(CLIP_CORNER, clip_corner, bool, _int, scalar) + 1401e: f8df 82b4 ldr.w r8, [pc, #692] ; 142d4 + 14022: 4632 mov r2, r6 + 14024: 2100 movs r1, #0 + 14026: 4620 mov r0, r4 + 14028: 47c0 blx r8 + + if(lv_obj_get_style_clip_corner(img, LV_IMG_PART_MAIN)) return LV_DESIGN_RES_MASKED; + 1402a: 2800 cmp r0, #0 + 1402c: f040 81ff bne.w 1442e + + if(ext->src_type == LV_IMG_SRC_UNKNOWN || ext->src_type == LV_IMG_SRC_SYMBOL) return LV_DESIGN_RES_NOT_COVER; + 14030: 7d2b ldrb r3, [r5, #20] + 14032: 0799 lsls r1, r3, #30 + 14034: d42a bmi.n 1408c + + /*Non true color format might have "holes"*/ + if(ext->cf != LV_IMG_CF_TRUE_COLOR && ext->cf != LV_IMG_CF_RAW) return LV_DESIGN_RES_NOT_COVER; + 14036: f003 03f8 and.w r3, r3, #248 ; 0xf8 + 1403a: 2b20 cmp r3, #32 + 1403c: d001 beq.n 14042 + 1403e: 2b08 cmp r3, #8 + 14040: d124 bne.n 1408c +_LV_OBJ_STYLE_SET_GET_DECLARE(SIZE, size, lv_style_int_t, _int, scalar) +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSFORM_WIDTH, transform_width, lv_style_int_t, _int, scalar) +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSFORM_HEIGHT, transform_height, lv_style_int_t, _int, scalar) +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSFORM_ANGLE, transform_angle, lv_style_int_t, _int, scalar) + 14042: 2206 movs r2, #6 + 14044: 2100 movs r1, #0 + 14046: 4620 mov r0, r4 + 14048: 47c0 blx r8 + + int32_t angle_final = lv_obj_get_style_transform_angle(img, LV_IMG_PART_MAIN); + angle_final += ext->angle; + 1404a: 89ab ldrh r3, [r5, #12] + + if(angle_final == 0) return LV_DESIGN_RES_NOT_COVER; + 1404c: 42c3 cmn r3, r0 + 1404e: d01d beq.n 1408c +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSFORM_ZOOM, transform_zoom, lv_style_int_t, _int, scalar) + 14050: 2207 movs r2, #7 + 14052: 2100 movs r1, #0 + 14054: 4620 mov r0, r4 + 14056: 47c0 blx r8 + + int32_t zoom_final = lv_obj_get_style_transform_zoom(img, LV_IMG_PART_MAIN); + zoom_final = (zoom_final * ext->zoom) >> 8; + 14058: f8b5 8012 ldrh.w r8, [r5, #18] + 1405c: f8df 9278 ldr.w r9, [pc, #632] ; 142d8 + 14060: fb00 f808 mul.w r8, r0, r8 + 14064: ea4f 2828 mov.w r8, r8, asr #8 + + if(zoom_final != LV_IMG_ZOOM_NONE) { + 14068: f5b8 7f80 cmp.w r8, #256 ; 0x100 + 1406c: d012 beq.n 14094 + if(_lv_area_is_in(clip_area, &img->coords, 0) == false) return LV_DESIGN_RES_NOT_COVER; + 1406e: 2200 movs r2, #0 + 14070: f104 0110 add.w r1, r4, #16 + a.x1 += img->coords.x1; + a.y1 += img->coords.y1; + a.x2 += img->coords.x1; + a.y2 += img->coords.y1; + + if(_lv_area_is_in(clip_area, &a, 0) == false) return LV_DESIGN_RES_NOT_COVER; + 14074: 4638 mov r0, r7 + 14076: 47c8 blx r9 + 14078: b140 cbz r0, 1408c +_LV_OBJ_STYLE_SET_GET_DECLARE(LINE_ROUNDED, line_rounded, bool, _int, scalar) +_LV_OBJ_STYLE_SET_GET_DECLARE(LINE_COLOR, line_color, lv_color_t, _color, nonscalar) +_LV_OBJ_STYLE_SET_GET_DECLARE(LINE_OPA, line_opa, lv_opa_t, _opa, scalar) +_LV_OBJ_STYLE_SET_GET_DECLARE(IMAGE_BLEND_MODE, image_blend_mode, lv_blend_mode_t, _int, scalar) +_LV_OBJ_STYLE_SET_GET_DECLARE(IMAGE_RECOLOR, image_recolor, lv_color_t, _color, nonscalar) +_LV_OBJ_STYLE_SET_GET_DECLARE(IMAGE_OPA, image_opa, lv_opa_t, _opa, scalar) + 1407a: 4b8a ldr r3, [pc, #552] ; (142a4 ) + 1407c: f248 02ac movw r2, #32940 ; 0x80ac + 14080: 2100 movs r1, #0 + 14082: 4620 mov r0, r4 + 14084: 4798 blx r3 + } + + if(lv_obj_get_style_image_opa(img, LV_IMG_PART_MAIN) != LV_OPA_COVER) return LV_DESIGN_RES_NOT_COVER; + + return LV_DESIGN_RES_COVER; + 14086: 28ff cmp r0, #255 ; 0xff + 14088: bf08 it eq + 1408a: 2601 moveq r6, #1 + lv_draw_rect(&img->coords, clip_area, &draw_dsc); + } + } + + return LV_DESIGN_RES_OK; +} + 1408c: 4630 mov r0, r6 + 1408e: b027 add sp, #156 ; 0x9c + 14090: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + _lv_img_buf_get_transformed_area(&a, lv_obj_get_width(img), lv_obj_get_height(img), 0, zoom_final, &ext->pivot); + 14094: 4b84 ldr r3, [pc, #528] ; (142a8 ) + 14096: 4620 mov r0, r4 + 14098: 4798 blx r3 + 1409a: 4b84 ldr r3, [pc, #528] ; (142ac ) + 1409c: 9003 str r0, [sp, #12] + 1409e: 4620 mov r0, r4 + 140a0: 4798 blx r3 + 140a2: 350e adds r5, #14 + 140a4: 4602 mov r2, r0 + 140a6: e9cd 8500 strd r8, r5, [sp] + 140aa: 9903 ldr r1, [sp, #12] + 140ac: 4d80 ldr r5, [pc, #512] ; (142b0 ) + 140ae: 2300 movs r3, #0 + 140b0: a811 add r0, sp, #68 ; 0x44 + 140b2: 47a8 blx r5 + a.x1 += img->coords.x1; + 140b4: 8a22 ldrh r2, [r4, #16] + 140b6: f8bd 3044 ldrh.w r3, [sp, #68] ; 0x44 + a.y1 += img->coords.y1; + 140ba: f8bd 1046 ldrh.w r1, [sp, #70] ; 0x46 + a.x1 += img->coords.x1; + 140be: 4413 add r3, r2 + 140c0: f8ad 3044 strh.w r3, [sp, #68] ; 0x44 + a.y1 += img->coords.y1; + 140c4: 8a63 ldrh r3, [r4, #18] + 140c6: 4419 add r1, r3 + 140c8: f8ad 1046 strh.w r1, [sp, #70] ; 0x46 + a.x2 += img->coords.x1; + 140cc: f8bd 1048 ldrh.w r1, [sp, #72] ; 0x48 + 140d0: 440a add r2, r1 + 140d2: f8ad 2048 strh.w r2, [sp, #72] ; 0x48 + a.y2 += img->coords.y1; + 140d6: f8bd 204a ldrh.w r2, [sp, #74] ; 0x4a + 140da: 4413 add r3, r2 + 140dc: f8ad 304a strh.w r3, [sp, #74] ; 0x4a + if(_lv_area_is_in(clip_area, &a, 0) == false) return LV_DESIGN_RES_NOT_COVER; + 140e0: 2200 movs r2, #0 + 140e2: a911 add r1, sp, #68 ; 0x44 + 140e4: e7c6 b.n 14074 + else if(mode == LV_DESIGN_DRAW_MAIN) { + 140e6: 2e00 cmp r6, #0 + 140e8: f040 8176 bne.w 143d8 + if(ext->h == 0 || ext->w == 0) return true; + 140ec: f9b0 300a ldrsh.w r3, [r0, #10] + 140f0: 2b00 cmp r3, #0 + 140f2: f000 816f beq.w 143d4 + 140f6: f9b0 3008 ldrsh.w r3, [r0, #8] + 140fa: 2b00 cmp r3, #0 + 140fc: f000 816a beq.w 143d4 + lv_obj_get_coords(img, &img_coords); + 14100: a904 add r1, sp, #16 + 14102: 4b6c ldr r3, [pc, #432] ; (142b4 ) +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_POST, border_post, bool, _int, scalar) + 14104: f8df 91cc ldr.w r9, [pc, #460] ; 142d4 + 14108: 4620 mov r0, r4 + 1410a: 4798 blx r3 + lv_draw_rect_dsc_init(&bg_dsc); + 1410c: 4b6a ldr r3, [pc, #424] ; (142b8 ) + 1410e: a811 add r0, sp, #68 ; 0x44 + 14110: 4798 blx r3 + lv_obj_init_draw_rect_dsc(img, LV_IMG_PART_MAIN, &bg_dsc); + 14112: aa11 add r2, sp, #68 ; 0x44 + 14114: 4631 mov r1, r6 + 14116: 4620 mov r0, r4 + 14118: 4b68 ldr r3, [pc, #416] ; (142bc ) + 1411a: 4798 blx r3 + 1411c: 2233 movs r2, #51 ; 0x33 + 1411e: 4631 mov r1, r6 + 14120: 4620 mov r0, r4 + 14122: 47c8 blx r9 + if(lv_obj_get_style_border_post(img, LV_OBJ_PART_MAIN)) { + 14124: b108 cbz r0, 1412a + bg_dsc.border_opa = LV_OPA_TRANSP; + 14126: f88d 6058 strb.w r6, [sp, #88] ; 0x58 +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSFORM_ZOOM, transform_zoom, lv_style_int_t, _int, scalar) + 1412a: 2207 movs r2, #7 + 1412c: 2100 movs r1, #0 + 1412e: 4620 mov r0, r4 + 14130: 47c8 blx r9 + zoom_final = (zoom_final * ext->zoom) >> 8; + 14132: f8b5 8012 ldrh.w r8, [r5, #18] + 14136: fb00 f008 mul.w r0, r0, r8 + if(zoom_final == 0) return LV_DESIGN_RES_OK; + 1413a: ea5f 2820 movs.w r8, r0, asr #8 + 1413e: d0a5 beq.n 1408c +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSFORM_ANGLE, transform_angle, lv_style_int_t, _int, scalar) + 14140: 2206 movs r2, #6 + 14142: 2100 movs r1, #0 + 14144: 4620 mov r0, r4 + 14146: 47c8 blx r9 + * @param area_p pointer to an area + * @return the height of the area (if y1 == y2 -> height = 1) + */ +static inline lv_coord_t lv_area_get_height(const lv_area_t * area_p) +{ + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + 14148: f8bd 2016 ldrh.w r2, [sp, #22] + 1414c: f8bd 3012 ldrh.w r3, [sp, #18] + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + 14150: f8bd 1014 ldrh.w r1, [sp, #20] + angle_final += ext->angle; + 14154: f8b5 a00c ldrh.w sl, [r5, #12] + _lv_img_buf_get_transformed_area(&bg_coords, lv_area_get_width(&img_coords), lv_area_get_height(&img_coords), + 14158: f8df b154 ldr.w fp, [pc, #340] ; 142b0 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + 1415c: 3201 adds r2, #1 + 1415e: 1ad2 subs r2, r2, r3 + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + 14160: f8bd 3010 ldrh.w r3, [sp, #16] + 14164: 3101 adds r1, #1 + angle_final += ext->angle; + 14166: 4482 add sl, r0 + 14168: 1ac9 subs r1, r1, r3 + _lv_img_buf_get_transformed_area(&bg_coords, lv_area_get_width(&img_coords), lv_area_get_height(&img_coords), + 1416a: fa1f f888 uxth.w r8, r8 + 1416e: f105 030e add.w r3, r5, #14 + 14172: e9cd 8300 strd r8, r3, [sp] + 14176: b212 sxth r2, r2 + 14178: fa0f f38a sxth.w r3, sl + 1417c: b209 sxth r1, r1 + 1417e: a806 add r0, sp, #24 + 14180: 47d8 blx fp + bg_coords.x1 += img_coords.x1; + 14182: f8bd 2010 ldrh.w r2, [sp, #16] + 14186: f8bd 3018 ldrh.w r3, [sp, #24] + bg_coords.y1 += img_coords.y1; + 1418a: f8bd 101a ldrh.w r1, [sp, #26] + bg_coords.x1 += img_coords.x1; + 1418e: 4413 add r3, r2 + 14190: f8ad 3018 strh.w r3, [sp, #24] + bg_coords.y1 += img_coords.y1; + 14194: f8bd 3012 ldrh.w r3, [sp, #18] + 14198: 4419 add r1, r3 + 1419a: f8ad 101a strh.w r1, [sp, #26] + bg_coords.x2 += img_coords.x1; + 1419e: f8bd 101c ldrh.w r1, [sp, #28] + 141a2: 440a add r2, r1 + 141a4: f8ad 201c strh.w r2, [sp, #28] + bg_coords.y2 += img_coords.y1; + 141a8: f8bd 201e ldrh.w r2, [sp, #30] +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_LEFT, pad_left, lv_style_int_t, _int, scalar) + 141ac: 2100 movs r1, #0 + 141ae: 4413 add r3, r2 + 141b0: 4620 mov r0, r4 + 141b2: 2212 movs r2, #18 + 141b4: f8ad 301e strh.w r3, [sp, #30] + 141b8: 47c8 blx r9 + bg_coords.x1 -= lv_obj_get_style_pad_left(img, LV_IMG_PART_MAIN); + 141ba: f8bd 3018 ldrh.w r3, [sp, #24] + 141be: 1a18 subs r0, r3, r0 + 141c0: f8ad 0018 strh.w r0, [sp, #24] +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_RIGHT, pad_right, lv_style_int_t, _int, scalar) + 141c4: 2213 movs r2, #19 + 141c6: 2100 movs r1, #0 + 141c8: 4620 mov r0, r4 + 141ca: 47c8 blx r9 + bg_coords.x2 += lv_obj_get_style_pad_right(img, LV_IMG_PART_MAIN); + 141cc: f8bd 301c ldrh.w r3, [sp, #28] + 141d0: 4418 add r0, r3 + 141d2: f8ad 001c strh.w r0, [sp, #28] +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_TOP, pad_top, lv_style_int_t, _int, scalar) + 141d6: 2210 movs r2, #16 + 141d8: 2100 movs r1, #0 + 141da: 4620 mov r0, r4 + 141dc: 47c8 blx r9 + bg_coords.y1 -= lv_obj_get_style_pad_top(img, LV_IMG_PART_MAIN); + 141de: f8bd 301a ldrh.w r3, [sp, #26] + 141e2: 1a18 subs r0, r3, r0 + 141e4: f8ad 001a strh.w r0, [sp, #26] +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_BOTTOM, pad_bottom, lv_style_int_t, _int, scalar) + 141e8: 2211 movs r2, #17 + 141ea: 2100 movs r1, #0 + 141ec: 4620 mov r0, r4 + 141ee: 47c8 blx r9 + bg_coords.y2 += lv_obj_get_style_pad_bottom(img, LV_IMG_PART_MAIN); + 141f0: f8bd 301e ldrh.w r3, [sp, #30] + 141f4: 4418 add r0, r3 + 141f6: f8ad 001e strh.w r0, [sp, #30] + lv_draw_rect(&bg_coords, clip_area, &bg_dsc); + 141fa: aa11 add r2, sp, #68 ; 0x44 + 141fc: 4639 mov r1, r7 + 141fe: a806 add r0, sp, #24 + 14200: 4b2f ldr r3, [pc, #188] ; (142c0 ) + 14202: 4798 blx r3 +_LV_OBJ_STYLE_SET_GET_DECLARE(CLIP_CORNER, clip_corner, bool, _int, scalar) + 14204: 2202 movs r2, #2 + 14206: 2100 movs r1, #0 + 14208: 4620 mov r0, r4 + 1420a: 47c8 blx r9 + if(lv_obj_get_style_clip_corner(img, LV_OBJ_PART_MAIN)) { + 1420c: b198 cbz r0, 14236 + lv_draw_mask_radius_param_t * mp = _lv_mem_buf_get(sizeof(lv_draw_mask_radius_param_t)); + 1420e: 4b2d ldr r3, [pc, #180] ; (142c4 ) + 14210: 201c movs r0, #28 + 14212: 4798 blx r3 +_LV_OBJ_STYLE_SET_GET_DECLARE(RADIUS, radius, lv_style_int_t, _int, scalar) + 14214: 2201 movs r2, #1 + 14216: 4683 mov fp, r0 + 14218: 2100 movs r1, #0 + 1421a: 4620 mov r0, r4 + 1421c: 47c8 blx r9 + lv_draw_mask_radius_init(mp, &bg_coords, r, false); + 1421e: 2300 movs r3, #0 + 14220: 4602 mov r2, r0 + 14222: a906 add r1, sp, #24 + 14224: 4658 mov r0, fp + 14226: f8df 90b4 ldr.w r9, [pc, #180] ; 142dc + 1422a: 47c8 blx r9 + lv_draw_mask_add(mp, img + 8); + 1422c: 4b26 ldr r3, [pc, #152] ; (142c8 ) + 1422e: f504 7118 add.w r1, r4, #608 ; 0x260 + 14232: 4658 mov r0, fp + 14234: 4798 blx r3 + if(ext->src_type == LV_IMG_SRC_FILE || ext->src_type == LV_IMG_SRC_VARIABLE) { + 14236: 7d2b ldrb r3, [r5, #20] + 14238: 079a lsls r2, r3, #30 + 1423a: f100 809d bmi.w 14378 + img_coords.x1 += ext->offset.x; + 1423e: f8bd 2010 ldrh.w r2, [sp, #16] + 14242: 88ab ldrh r3, [r5, #4] + if(img_coords.x1 > img->coords.x1) img_coords.x1 -= ext->w; + 14244: f9b4 c010 ldrsh.w ip, [r4, #16] + img_coords.y1 += ext->offset.y; + 14248: 88e9 ldrh r1, [r5, #6] + img_coords.x1 += ext->offset.x; + 1424a: 441a add r2, r3 + 1424c: b290 uxth r0, r2 + 1424e: b212 sxth r2, r2 + if(img_coords.x1 > img->coords.x1) img_coords.x1 -= ext->w; + 14250: 4594 cmp ip, r2 + img_coords.x1 += ext->offset.x; + 14252: f8ad 2010 strh.w r2, [sp, #16] + if(img_coords.x1 > img->coords.x1) img_coords.x1 -= ext->w; + 14256: bfb8 it lt + 14258: 892a ldrhlt r2, [r5, #8] + img_coords.y1 += ext->offset.y; + 1425a: f8bd 3012 ldrh.w r3, [sp, #18] + if(img_coords.x1 > img->coords.x1) img_coords.x1 -= ext->w; + 1425e: bfbc itt lt + 14260: 1a82 sublt r2, r0, r2 + 14262: f8ad 2010 strhlt.w r2, [sp, #16] + img_coords.y1 += ext->offset.y; + 14266: 440b add r3, r1 + if(img_coords.y1 > img->coords.y1) img_coords.y1 -= ext->h; + 14268: f9b4 2012 ldrsh.w r2, [r4, #18] + img_coords.y1 += ext->offset.y; + 1426c: b299 uxth r1, r3 + 1426e: b21b sxth r3, r3 + if(img_coords.y1 > img->coords.y1) img_coords.y1 -= ext->h; + 14270: 429a cmp r2, r3 + img_coords.y1 += ext->offset.y; + 14272: f8ad 3012 strh.w r3, [sp, #18] + if(img_coords.y1 > img->coords.y1) img_coords.y1 -= ext->h; + 14276: bfbe ittt lt + 14278: 896b ldrhlt r3, [r5, #10] + 1427a: 1acb sublt r3, r1, r3 + 1427c: f8ad 3012 strhlt.w r3, [sp, #18] + lv_draw_img_dsc_init(&img_dsc); + 14280: a80a add r0, sp, #40 ; 0x28 + 14282: 4b12 ldr r3, [pc, #72] ; (142cc ) + 14284: 4798 blx r3 + lv_obj_init_draw_img_dsc(img, LV_IMG_PART_MAIN, &img_dsc); + 14286: 4b12 ldr r3, [pc, #72] ; (142d0 ) + 14288: aa0a add r2, sp, #40 ; 0x28 + 1428a: 2100 movs r1, #0 + 1428c: 4620 mov r0, r4 + 1428e: 4798 blx r3 + img_dsc.zoom = zoom_final; + 14290: f8ad 8030 strh.w r8, [sp, #48] ; 0x30 + if(img_dsc.zoom == 0) return LV_DESIGN_RES_OK; + 14294: f1b8 0f00 cmp.w r8, #0 + 14298: d122 bne.n 142e0 + return LV_DESIGN_RES_OK; + 1429a: 2600 movs r6, #0 + 1429c: e6f6 b.n 1408c + 1429e: bf00 nop + 142a0: 00003fa9 .word 0x00003fa9 + 142a4: 00003839 .word 0x00003839 + 142a8: 000023ed .word 0x000023ed + 142ac: 0000243d .word 0x0000243d + 142b0: 0000c061 .word 0x0000c061 + 142b4: 000022d5 .word 0x000022d5 + 142b8: 00009ba1 .word 0x00009ba1 + 142bc: 000042a9 .word 0x000042a9 + 142c0: 00009bed .word 0x00009bed + 142c4: 0000eeb5 .word 0x0000eeb5 + 142c8: 00009711 .word 0x00009711 + 142cc: 00007559 .word 0x00007559 + 142d0: 0000489d .word 0x0000489d + 142d4: 00003711 .word 0x00003711 + 142d8: 0000e091 .word 0x0000e091 + 142dc: 00009915 .word 0x00009915 + img_dsc.pivot.x = ext->pivot.x; + 142e0: 89eb ldrh r3, [r5, #14] + 142e2: f8ad 302c strh.w r3, [sp, #44] ; 0x2c + img_dsc.pivot.y = ext->pivot.y; + 142e6: 8a2b ldrh r3, [r5, #16] + 142e8: f8ad 302e strh.w r3, [sp, #46] ; 0x2e + img_dsc.antialias = ext->antialias; + 142ec: 7d6b ldrb r3, [r5, #21] + 142ee: f89d 2037 ldrb.w r2, [sp, #55] ; 0x37 + lv_draw_img(&cords_tmp, clip_area, ext->src, &img_dsc); + 142f2: 4c50 ldr r4, [pc, #320] ; (14434 ) + img_dsc.angle = angle_final; + 142f4: f8ad a02a strh.w sl, [sp, #42] ; 0x2a + img_dsc.antialias = ext->antialias; + 142f8: f3c3 0300 ubfx r3, r3, #0, #1 + 142fc: f363 0200 bfi r2, r3, #0, #1 + 14300: f88d 2037 strb.w r2, [sp, #55] ; 0x37 + cords_tmp.y1 = img_coords.y1; + 14304: f9bd 3012 ldrsh.w r3, [sp, #18] + cords_tmp.y2 = img_coords.y1 + ext->h - 1; + 14308: 896a ldrh r2, [r5, #10] + cords_tmp.y1 = img_coords.y1; + 1430a: f8ad 3022 strh.w r3, [sp, #34] ; 0x22 + cords_tmp.y2 = img_coords.y1 + ext->h - 1; + 1430e: 3b01 subs r3, #1 + 14310: 4413 add r3, r2 + 14312: b21b sxth r3, r3 + for(; cords_tmp.y1 <= img_coords.y2; cords_tmp.y1 += ext->h, cords_tmp.y2 += ext->h) { + 14314: f9bd 2022 ldrsh.w r2, [sp, #34] ; 0x22 + cords_tmp.y2 = img_coords.y1 + ext->h - 1; + 14318: f8ad 3026 strh.w r3, [sp, #38] ; 0x26 + for(; cords_tmp.y1 <= img_coords.y2; cords_tmp.y1 += ext->h, cords_tmp.y2 += ext->h) { + 1431c: f9bd 3016 ldrsh.w r3, [sp, #22] + 14320: 429a cmp r2, r3 + 14322: f73f aeb3 bgt.w 1408c + cords_tmp.x1 = img_coords.x1; + 14326: f9bd 3010 ldrsh.w r3, [sp, #16] + cords_tmp.x2 = img_coords.x1 + ext->w - 1; + 1432a: 892a ldrh r2, [r5, #8] + cords_tmp.x1 = img_coords.x1; + 1432c: f8ad 3020 strh.w r3, [sp, #32] + cords_tmp.x2 = img_coords.x1 + ext->w - 1; + 14330: 3b01 subs r3, #1 + for(; cords_tmp.x1 <= img_coords.x2; cords_tmp.x1 += ext->w, cords_tmp.x2 += ext->w) { + 14332: 4413 add r3, r2 + 14334: b21b sxth r3, r3 + 14336: f9bd 2020 ldrsh.w r2, [sp, #32] + cords_tmp.x2 = img_coords.x1 + ext->w - 1; + 1433a: f8ad 3024 strh.w r3, [sp, #36] ; 0x24 + for(; cords_tmp.x1 <= img_coords.x2; cords_tmp.x1 += ext->w, cords_tmp.x2 += ext->w) { + 1433e: f9bd 3014 ldrsh.w r3, [sp, #20] + 14342: 429a cmp r2, r3 + 14344: dd0a ble.n 1435c + for(; cords_tmp.y1 <= img_coords.y2; cords_tmp.y1 += ext->h, cords_tmp.y2 += ext->h) { + 14346: 896b ldrh r3, [r5, #10] + 14348: f8bd 2022 ldrh.w r2, [sp, #34] ; 0x22 + 1434c: 441a add r2, r3 + 1434e: f8ad 2022 strh.w r2, [sp, #34] ; 0x22 + 14352: f8bd 2026 ldrh.w r2, [sp, #38] ; 0x26 + 14356: 4413 add r3, r2 + 14358: b21b sxth r3, r3 + 1435a: e7db b.n 14314 + lv_draw_img(&cords_tmp, clip_area, ext->src, &img_dsc); + 1435c: 682a ldr r2, [r5, #0] + 1435e: ab0a add r3, sp, #40 ; 0x28 + 14360: 4639 mov r1, r7 + 14362: a808 add r0, sp, #32 + 14364: 47a0 blx r4 + for(; cords_tmp.x1 <= img_coords.x2; cords_tmp.x1 += ext->w, cords_tmp.x2 += ext->w) { + 14366: f8bd 2020 ldrh.w r2, [sp, #32] + 1436a: 892b ldrh r3, [r5, #8] + 1436c: 441a add r2, r3 + 1436e: f8ad 2020 strh.w r2, [sp, #32] + 14372: f8bd 2024 ldrh.w r2, [sp, #36] ; 0x24 + 14376: e7dc b.n 14332 + else if(ext->src_type == LV_IMG_SRC_SYMBOL) { + 14378: f003 0303 and.w r3, r3, #3 + 1437c: 2b02 cmp r3, #2 + 1437e: d118 bne.n 143b2 + lv_draw_label_dsc_init(&label_dsc); + 14380: a80a add r0, sp, #40 ; 0x28 + 14382: 4b2d ldr r3, [pc, #180] ; (14438 ) + 14384: 4798 blx r3 + lv_obj_init_draw_label_dsc(img, LV_IMG_PART_MAIN, &label_dsc); + 14386: aa0a add r2, sp, #40 ; 0x28 + 14388: 4620 mov r0, r4 + 1438a: 4b2c ldr r3, [pc, #176] ; (1443c ) + 1438c: 2100 movs r1, #0 + 1438e: 4798 blx r3 +_LV_OBJ_STYLE_SET_GET_DECLARE(IMAGE_RECOLOR, image_recolor, lv_color_t, _color, nonscalar) + 14390: 4b2b ldr r3, [pc, #172] ; (14440 ) + 14392: f248 02a9 movw r2, #32937 ; 0x80a9 + 14396: 2100 movs r1, #0 + 14398: 4620 mov r0, r4 + 1439a: 4798 blx r3 + lv_draw_label(&img_coords, clip_area, &label_dsc, ext->src, NULL); + 1439c: 2300 movs r3, #0 + 1439e: 9300 str r3, [sp, #0] + label_dsc.color = lv_obj_get_style_image_recolor(img, LV_IMG_PART_MAIN); + 143a0: f8ad 0028 strh.w r0, [sp, #40] ; 0x28 + lv_draw_label(&img_coords, clip_area, &label_dsc, ext->src, NULL); + 143a4: 682b ldr r3, [r5, #0] + 143a6: 4c27 ldr r4, [pc, #156] ; (14444 ) + 143a8: aa0a add r2, sp, #40 ; 0x28 + 143aa: 4639 mov r1, r7 + 143ac: a804 add r0, sp, #16 + 143ae: 47a0 blx r4 + 143b0: e66c b.n 1408c + LV_LOG_WARN("lv_img_design: image source type is unknown"); + 143b2: 4b25 ldr r3, [pc, #148] ; (14448 ) + 143b4: 9300 str r3, [sp, #0] + 143b6: 4925 ldr r1, [pc, #148] ; (1444c ) + 143b8: 4b25 ldr r3, [pc, #148] ; (14450 ) + 143ba: 4d26 ldr r5, [pc, #152] ; (14454 ) + 143bc: f240 22bb movw r2, #699 ; 0x2bb + 143c0: 2002 movs r0, #2 + 143c2: 47a8 blx r5 + lv_draw_img(&img->coords, clip_area, NULL, NULL); + 143c4: 2300 movs r3, #0 + 143c6: f104 0010 add.w r0, r4, #16 + 143ca: 461a mov r2, r3 + 143cc: 4c19 ldr r4, [pc, #100] ; (14434 ) + 143ce: 4639 mov r1, r7 + 143d0: 47a0 blx r4 + 143d2: e65b b.n 1408c + if(ext->h == 0 || ext->w == 0) return true; + 143d4: 2601 movs r6, #1 + 143d6: e659 b.n 1408c + else if(mode == LV_DESIGN_DRAW_POST) { + 143d8: 2e01 cmp r6, #1 + 143da: f47f af5e bne.w 1429a +_LV_OBJ_STYLE_SET_GET_DECLARE(CLIP_CORNER, clip_corner, bool, _int, scalar) + 143de: 4d1e ldr r5, [pc, #120] ; (14458 ) + 143e0: 2202 movs r2, #2 + 143e2: 2100 movs r1, #0 + 143e4: 4620 mov r0, r4 + 143e6: 47a8 blx r5 + if(lv_obj_get_style_clip_corner(img, LV_OBJ_PART_MAIN)) { + 143e8: b128 cbz r0, 143f6 + lv_draw_mask_radius_param_t * param = lv_draw_mask_remove_custom(img + 8); + 143ea: 4b1c ldr r3, [pc, #112] ; (1445c ) + 143ec: f504 7018 add.w r0, r4, #608 ; 0x260 + 143f0: 4798 blx r3 + _lv_mem_buf_release(param); + 143f2: 4b1b ldr r3, [pc, #108] ; (14460 ) + 143f4: 4798 blx r3 + lv_draw_rect_dsc_init(&draw_dsc); + 143f6: a811 add r0, sp, #68 ; 0x44 + 143f8: 4b1a ldr r3, [pc, #104] ; (14464 ) + 143fa: 4798 blx r3 +_LV_OBJ_STYLE_SET_GET_DECLARE(BORDER_POST, border_post, bool, _int, scalar) + 143fc: 2233 movs r2, #51 ; 0x33 + 143fe: 2100 movs r1, #0 + 14400: 4620 mov r0, r4 + 14402: 47a8 blx r5 + if(lv_obj_get_style_border_post(img, LV_OBJ_PART_MAIN)) { + 14404: 2800 cmp r0, #0 + 14406: f43f af48 beq.w 1429a + draw_dsc.bg_opa = LV_OPA_TRANSP; + 1440a: 2100 movs r1, #0 + 1440c: f88d 1050 strb.w r1, [sp, #80] ; 0x50 + draw_dsc.pattern_opa = LV_OPA_TRANSP; + 14410: f88d 107a strb.w r1, [sp, #122] ; 0x7a + draw_dsc.shadow_opa = LV_OPA_TRANSP; + 14414: f88d 106c strb.w r1, [sp, #108] ; 0x6c + lv_obj_init_draw_rect_dsc(img, LV_OBJ_PART_MAIN, &draw_dsc); + 14418: aa11 add r2, sp, #68 ; 0x44 + 1441a: 4620 mov r0, r4 + 1441c: 4b12 ldr r3, [pc, #72] ; (14468 ) + 1441e: 4798 blx r3 + lv_draw_rect(&img->coords, clip_area, &draw_dsc); + 14420: 4b12 ldr r3, [pc, #72] ; (1446c ) + 14422: aa11 add r2, sp, #68 ; 0x44 + 14424: 4639 mov r1, r7 + 14426: f104 0010 add.w r0, r4, #16 + 1442a: 4798 blx r3 + 1442c: e735 b.n 1429a + if(lv_obj_get_style_clip_corner(img, LV_IMG_PART_MAIN)) return LV_DESIGN_RES_MASKED; + 1442e: 2603 movs r6, #3 + 14430: e62c b.n 1408c + 14432: bf00 nop + 14434: 000075c1 .word 0x000075c1 + 14438: 00007845 .word 0x00007845 + 1443c: 000047e5 .word 0x000047e5 + 14440: 000037b5 .word 0x000037b5 + 14444: 00007875 .word 0x00007875 + 14448: 0001fdc3 .word 0x0001fdc3 + 1444c: 00024278 .word 0x00024278 + 14450: 00024331 .word 0x00024331 + 14454: 0000e8e9 .word 0x0000e8e9 + 14458: 00003711 .word 0x00003711 + 1445c: 000097c9 .word 0x000097c9 + 14460: 0000eb69 .word 0x0000eb69 + 14464: 00009ba1 .word 0x00009ba1 + 14468: 000042a9 .word 0x000042a9 + 1446c: 00009bed .word 0x00009bed + +00014470 : +{ + 14470: b573 push {r0, r1, r4, r5, r6, lr} + LV_ASSERT_OBJ(img, LV_OBJX_NAME); + 14472: 4b0d ldr r3, [pc, #52] ; (144a8 ) +{ + 14474: 4604 mov r4, r0 + LV_ASSERT_OBJ(img, LV_OBJX_NAME); + 14476: 4798 blx r3 + 14478: 4605 mov r5, r0 + 1447a: b968 cbnz r0, 14498 + 1447c: 4b0b ldr r3, [pc, #44] ; (144ac ) + 1447e: 490c ldr r1, [pc, #48] ; (144b0 ) + 14480: 9300 str r3, [sp, #0] + 14482: f44f 72e7 mov.w r2, #462 ; 0x1ce + 14486: 2003 movs r0, #3 + 14488: 4e0a ldr r6, [pc, #40] ; (144b4 ) + 1448a: 47b0 blx r6 + 1448c: 480a ldr r0, [pc, #40] ; (144b8 ) + 1448e: 490b ldr r1, [pc, #44] ; (144bc ) + 14490: 4622 mov r2, r4 + 14492: 462b mov r3, r5 + 14494: 4788 blx r1 + 14496: e7fe b.n 14496 + lv_img_ext_t * ext = lv_obj_get_ext_attr(img); + 14498: 4b09 ldr r3, [pc, #36] ; (144c0 ) + 1449a: 4620 mov r0, r4 + 1449c: 4798 blx r3 + return ext->auto_size == 0 ? false : true; + 1449e: 7d00 ldrb r0, [r0, #20] +} + 144a0: f3c0 0080 ubfx r0, r0, #2, #1 + 144a4: b002 add sp, #8 + 144a6: bd70 pop {r4, r5, r6, pc} + 144a8: 000017e1 .word 0x000017e1 + 144ac: 000243a0 .word 0x000243a0 + 144b0: 00024278 .word 0x00024278 + 144b4: 0000e8e9 .word 0x0000e8e9 + 144b8: 0001eebf .word 0x0001eebf + 144bc: 000017e9 .word 0x000017e9 + 144c0: 00003fa9 .word 0x00003fa9 + +000144c4 : +{ + 144c4: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + LV_ASSERT_OBJ(img, LV_OBJX_NAME); + 144c8: f8df a244 ldr.w sl, [pc, #580] ; 14710 +{ + 144cc: b088 sub sp, #32 + 144ce: 4606 mov r6, r0 + 144d0: 460f mov r7, r1 + LV_ASSERT_OBJ(img, LV_OBJX_NAME); + 144d2: 47d0 blx sl + 144d4: 4604 mov r4, r0 + 144d6: b960 cbnz r0, 144f2 + 144d8: 4b77 ldr r3, [pc, #476] ; (146b8 ) + 144da: 4978 ldr r1, [pc, #480] ; (146bc ) + 144dc: 9300 str r3, [sp, #0] + 144de: 228f movs r2, #143 ; 0x8f + 144e0: 2003 movs r0, #3 + 144e2: 4d77 ldr r5, [pc, #476] ; (146c0 ) + 144e4: 47a8 blx r5 + 144e6: 4877 ldr r0, [pc, #476] ; (146c4 ) + 144e8: 4977 ldr r1, [pc, #476] ; (146c8 ) + 144ea: 4632 mov r2, r6 + 144ec: 4623 mov r3, r4 + 144ee: 4788 blx r1 + 144f0: e7fe b.n 144f0 + lv_img_src_t src_type = lv_img_src_get_type(src_img); + 144f2: 4b76 ldr r3, [pc, #472] ; (146cc ) + 144f4: 4638 mov r0, r7 + 144f6: 4798 blx r3 + lv_img_ext_t * ext = lv_obj_get_ext_attr(img); + 144f8: 4b75 ldr r3, [pc, #468] ; (146d0 ) + lv_img_src_t src_type = lv_img_src_get_type(src_img); + 144fa: 4605 mov r5, r0 + lv_img_ext_t * ext = lv_obj_get_ext_attr(img); + 144fc: 4630 mov r0, r6 + 144fe: 4798 blx r3 + switch(src_type) { + 14500: 2d02 cmp r5, #2 + lv_img_ext_t * ext = lv_obj_get_ext_attr(img); + 14502: 4604 mov r4, r0 + switch(src_type) { + 14504: d923 bls.n 1454e + LV_LOG_WARN("lv_img_set_src: unknown type"); + 14506: 4b73 ldr r3, [pc, #460] ; (146d4 ) + 14508: 9300 str r3, [sp, #0] + 1450a: 496c ldr r1, [pc, #432] ; (146bc ) + 1450c: 4b6a ldr r3, [pc, #424] ; (146b8 ) + 1450e: f8df 81b0 ldr.w r8, [pc, #432] ; 146c0 + 14512: 22a0 movs r2, #160 ; 0xa0 + 14514: 2002 movs r0, #2 + 14516: 47c0 blx r8 + if(src_type == LV_IMG_SRC_UNKNOWN) { + 14518: 2d03 cmp r5, #3 + 1451a: d118 bne.n 1454e + LV_LOG_WARN("lv_img_set_src: unknown image type"); + 1451c: 4b6e ldr r3, [pc, #440] ; (146d8 ) + 1451e: 9300 str r3, [sp, #0] + 14520: 4966 ldr r1, [pc, #408] ; (146bc ) + 14522: 4b65 ldr r3, [pc, #404] ; (146b8 ) + 14524: 22a6 movs r2, #166 ; 0xa6 + 14526: 2002 movs r0, #2 + 14528: 47c0 blx r8 + if(ext->src_type == LV_IMG_SRC_SYMBOL || ext->src_type == LV_IMG_SRC_FILE) { + 1452a: 7d23 ldrb r3, [r4, #20] + 1452c: f003 0303 and.w r3, r3, #3 + 14530: 3b01 subs r3, #1 + 14532: 2b01 cmp r3, #1 + 14534: d802 bhi.n 1453c + lv_mem_free(ext->src); + 14536: 6820 ldr r0, [r4, #0] + 14538: 4b68 ldr r3, [pc, #416] ; (146dc ) + 1453a: 4798 blx r3 + ext->src = NULL; + 1453c: 2300 movs r3, #0 + 1453e: 6023 str r3, [r4, #0] + ext->src_type = LV_IMG_SRC_UNKNOWN; + 14540: 7d23 ldrb r3, [r4, #20] + 14542: f043 0303 orr.w r3, r3, #3 + 14546: 7523 strb r3, [r4, #20] +} + 14548: b008 add sp, #32 + 1454a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + lv_img_decoder_get_info(src_img, &header); + 1454e: 4b64 ldr r3, [pc, #400] ; (146e0 ) + 14550: a906 add r1, sp, #24 + 14552: 4638 mov r0, r7 + 14554: 4798 blx r3 + if(src_type == LV_IMG_SRC_VARIABLE) { + 14556: 2d00 cmp r5, #0 + 14558: d146 bne.n 145e8 + LV_LOG_INFO("lv_img_set_src: `LV_IMG_SRC_VARIABLE` type found"); + 1455a: 4b62 ldr r3, [pc, #392] ; (146e4 ) + 1455c: 9300 str r3, [sp, #0] + 1455e: 4957 ldr r1, [pc, #348] ; (146bc ) + 14560: 4b55 ldr r3, [pc, #340] ; (146b8 ) + 14562: f8df 815c ldr.w r8, [pc, #348] ; 146c0 + 14566: 22b4 movs r2, #180 ; 0xb4 + 14568: 2001 movs r0, #1 + 1456a: 47c0 blx r8 + if(ext->src_type == LV_IMG_SRC_FILE || ext->src_type == LV_IMG_SRC_SYMBOL) { + 1456c: 7d23 ldrb r3, [r4, #20] + 1456e: f003 0303 and.w r3, r3, #3 + 14572: 3b01 subs r3, #1 + 14574: 2b01 cmp r3, #1 + 14576: d802 bhi.n 1457e + lv_mem_free(ext->src); + 14578: 6820 ldr r0, [r4, #0] + 1457a: 4b58 ldr r3, [pc, #352] ; (146dc ) + 1457c: 4798 blx r3 + ext->src = src_img; + 1457e: 6027 str r7, [r4, #0] + ext->w = header.w; + 14580: 9a06 ldr r2, [sp, #24] + 14582: f3c2 238a ubfx r3, r2, #10, #11 + 14586: 8123 strh r3, [r4, #8] + ext->h = header.h; + 14588: f8bd 301a ldrh.w r3, [sp, #26] + 1458c: f3c3 114a ubfx r1, r3, #5, #11 + 14590: 8161 strh r1, [r4, #10] + ext->cf = header.cf; + 14592: f89d 1018 ldrb.w r1, [sp, #24] + ext->src_type = src_type; + 14596: f005 0503 and.w r5, r5, #3 + ext->cf = header.cf; + 1459a: f3c1 0104 ubfx r1, r1, #0, #5 + ext->src_type = src_type; + 1459e: ea45 05c1 orr.w r5, r5, r1, lsl #3 + 145a2: 7d21 ldrb r1, [r4, #20] + 145a4: f001 0104 and.w r1, r1, #4 + ext->pivot.y = header.h / 2; + 145a8: f3c3 1389 ubfx r3, r3, #6, #10 + ext->src_type = src_type; + 145ac: 430d orrs r5, r1 + ext->pivot.x = header.w / 2; + 145ae: f3c2 22c9 ubfx r2, r2, #11, #10 + ext->pivot.y = header.h / 2; + 145b2: 8223 strh r3, [r4, #16] + ext->src_type = src_type; + 145b4: 7525 strb r5, [r4, #20] + if(lv_img_get_auto_size(img) != false) { + 145b6: 4b4c ldr r3, [pc, #304] ; (146e8 ) + ext->pivot.x = header.w / 2; + 145b8: 81e2 strh r2, [r4, #14] + if(lv_img_get_auto_size(img) != false) { + 145ba: 4630 mov r0, r6 + 145bc: 4798 blx r3 + 145be: b130 cbz r0, 145ce + lv_obj_set_size(img, ext->w, ext->h); + 145c0: f9b4 200a ldrsh.w r2, [r4, #10] + 145c4: f9b4 1008 ldrsh.w r1, [r4, #8] + 145c8: 4b48 ldr r3, [pc, #288] ; (146ec ) + 145ca: 4630 mov r0, r6 + 145cc: 4798 blx r3 + if(ext->angle || ext->zoom != LV_IMG_ZOOM_NONE) lv_obj_refresh_ext_draw_pad(img); + 145ce: 89a3 ldrh r3, [r4, #12] + 145d0: b91b cbnz r3, 145da + 145d2: 8a63 ldrh r3, [r4, #18] + 145d4: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 145d8: d002 beq.n 145e0 + 145da: 4b45 ldr r3, [pc, #276] ; (146f0 ) + 145dc: 4630 mov r0, r6 + 145de: 4798 blx r3 + lv_obj_invalidate(img); + 145e0: 4b44 ldr r3, [pc, #272] ; (146f4 ) + 145e2: 4630 mov r0, r6 + 145e4: 4798 blx r3 + 145e6: e7af b.n 14548 + else if(src_type == LV_IMG_SRC_FILE || src_type == LV_IMG_SRC_SYMBOL) { + 145e8: 1e6b subs r3, r5, #1 + 145ea: b2db uxtb r3, r3 + 145ec: 2b01 cmp r3, #1 + 145ee: d831 bhi.n 14654 + if(ext->src != src_img) { + 145f0: f8d4 9000 ldr.w r9, [r4] + 145f4: 454f cmp r7, r9 + 145f6: d02d beq.n 14654 + if(ext->src_type == LV_IMG_SRC_FILE || ext->src_type == LV_IMG_SRC_SYMBOL) { + 145f8: 7d23 ldrb r3, [r4, #20] + 145fa: f003 0303 and.w r3, r3, #3 + 145fe: 3b01 subs r3, #1 + const void * old_src = NULL; + 14600: 2b01 cmp r3, #1 + char * new_str = lv_mem_alloc(strlen(src_img) + 1); + 14602: 4638 mov r0, r7 + 14604: 4b3c ldr r3, [pc, #240] ; (146f8 ) + const void * old_src = NULL; + 14606: bf88 it hi + 14608: f04f 0900 movhi.w r9, #0 + char * new_str = lv_mem_alloc(strlen(src_img) + 1); + 1460c: 4798 blx r3 + 1460e: 4b3b ldr r3, [pc, #236] ; (146fc ) + 14610: 3001 adds r0, #1 + 14612: 4798 blx r3 + 14614: 4680 mov r8, r0 + LV_ASSERT_MEM(new_str); + 14616: 47d0 blx sl + 14618: 4682 mov sl, r0 + 1461a: b960 cbnz r0, 14636 + 1461c: 4b26 ldr r3, [pc, #152] ; (146b8 ) + 1461e: 4927 ldr r1, [pc, #156] ; (146bc ) + 14620: 9300 str r3, [sp, #0] + 14622: 22c7 movs r2, #199 ; 0xc7 + 14624: 2003 movs r0, #3 + 14626: 4c26 ldr r4, [pc, #152] ; (146c0 ) + 14628: 47a0 blx r4 + 1462a: 4835 ldr r0, [pc, #212] ; (14700 ) + 1462c: 4926 ldr r1, [pc, #152] ; (146c8 ) + 1462e: 4642 mov r2, r8 + 14630: 4653 mov r3, sl + 14632: 4788 blx r1 + 14634: e7fe b.n 14634 + if(new_str == NULL) return; + 14636: f1b8 0f00 cmp.w r8, #0 + 1463a: d085 beq.n 14548 + 1463c: 4b31 ldr r3, [pc, #196] ; (14704 ) + 1463e: 4639 mov r1, r7 + 14640: 4640 mov r0, r8 + 14642: 4798 blx r3 + ext->src = new_str; + 14644: f8c4 8000 str.w r8, [r4] + if(old_src) lv_mem_free(old_src); + 14648: f1b9 0f00 cmp.w r9, #0 + 1464c: d002 beq.n 14654 + 1464e: 4b23 ldr r3, [pc, #140] ; (146dc ) + 14650: 4648 mov r0, r9 + 14652: 4798 blx r3 + if(src_type == LV_IMG_SRC_SYMBOL) { + 14654: 2d02 cmp r5, #2 + 14656: d193 bne.n 14580 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_FONT, text_font, const lv_font_t *, _ptr, scalar) + 14658: 4b2b ldr r3, [pc, #172] ; (14708 ) +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_LETTER_SPACE, text_letter_space, lv_style_int_t, _int, scalar) + 1465a: f8df 90b8 ldr.w r9, [pc, #184] ; 14714 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_FONT, text_font, const lv_font_t *, _ptr, scalar) + 1465e: f248 028e movw r2, #32910 ; 0x808e + 14662: 2100 movs r1, #0 + 14664: 4630 mov r0, r6 + 14666: 4798 blx r3 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_LETTER_SPACE, text_letter_space, lv_style_int_t, _int, scalar) + 14668: f248 0280 movw r2, #32896 ; 0x8080 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_FONT, text_font, const lv_font_t *, _ptr, scalar) + 1466c: 4680 mov r8, r0 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_LETTER_SPACE, text_letter_space, lv_style_int_t, _int, scalar) + 1466e: 2100 movs r1, #0 + 14670: 4630 mov r0, r6 + 14672: 47c8 blx r9 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_LINE_SPACE, text_line_space, lv_style_int_t, _int, scalar) + 14674: f248 0281 movw r2, #32897 ; 0x8081 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_LETTER_SPACE, text_letter_space, lv_style_int_t, _int, scalar) + 14678: 9005 str r0, [sp, #20] +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_LINE_SPACE, text_line_space, lv_style_int_t, _int, scalar) + 1467a: 2100 movs r1, #0 + 1467c: 4630 mov r0, r6 + 1467e: 47c8 blx r9 + _lv_txt_get_size(&size, src_img, font, letter_space, line_space, + 14680: f647 4218 movw r2, #31768 ; 0x7c18 + 14684: 2300 movs r3, #0 + 14686: e9cd 2301 strd r2, r3, [sp, #4] + 1468a: 9000 str r0, [sp, #0] + 1468c: 9b05 ldr r3, [sp, #20] + 1468e: 4642 mov r2, r8 + 14690: 4639 mov r1, r7 + 14692: a807 add r0, sp, #28 + 14694: 4f1d ldr r7, [pc, #116] ; (1470c ) + 14696: 47b8 blx r7 + header.w = size.x; + 14698: f8bd 201c ldrh.w r2, [sp, #28] + 1469c: f9bd 301e ldrsh.w r3, [sp, #30] + 146a0: f3c2 020a ubfx r2, r2, #0, #11 + 146a4: 055b lsls r3, r3, #21 + 146a6: ea43 2382 orr.w r3, r3, r2, lsl #10 + 146aa: 9a06 ldr r2, [sp, #24] + 146ac: f3c2 0209 ubfx r2, r2, #0, #10 + 146b0: 4313 orrs r3, r2 + 146b2: 9306 str r3, [sp, #24] + 146b4: e764 b.n 14580 + 146b6: bf00 nop + 146b8: 000243b5 .word 0x000243b5 + 146bc: 00024278 .word 0x00024278 + 146c0: 0000e8e9 .word 0x0000e8e9 + 146c4: 0001eebf .word 0x0001eebf + 146c8: 000017e9 .word 0x000017e9 + 146cc: 00007805 .word 0x00007805 + 146d0: 00003fa9 .word 0x00003fa9 + 146d4: 000242aa .word 0x000242aa + 146d8: 000242c7 .word 0x000242c7 + 146dc: 0000eae5 .word 0x0000eae5 + 146e0: 0000cf29 .word 0x0000cf29 + 146e4: 000242ea .word 0x000242ea + 146e8: 00014471 .word 0x00014471 + 146ec: 000034e1 .word 0x000034e1 + 146f0: 000020d1 .word 0x000020d1 + 146f4: 00002785 .word 0x00002785 + 146f8: 00016339 .word 0x00016339 + 146fc: 0000ea2d .word 0x0000ea2d + 14700: 0001edbe .word 0x0001edbe + 14704: 00016329 .word 0x00016329 + 14708: 000038c9 .word 0x000038c9 + 1470c: 0001019d .word 0x0001019d + 14710: 000017e1 .word 0x000017e1 + 14714: 00003711 .word 0x00003711 + +00014718 : +{ + 14718: e92d 41f3 stmdb sp!, {r0, r1, r4, r5, r6, r7, r8, lr} + lv_obj_t * img = lv_obj_create(par, copy); + 1471c: 4b53 ldr r3, [pc, #332] ; (1486c ) + LV_ASSERT_MEM(img); + 1471e: f8df 81a8 ldr.w r8, [pc, #424] ; 148c8 +{ + 14722: 460e mov r6, r1 + 14724: 4607 mov r7, r0 + lv_obj_t * img = lv_obj_create(par, copy); + 14726: 4798 blx r3 + 14728: 4605 mov r5, r0 + LV_ASSERT_MEM(img); + 1472a: 47c0 blx r8 + 1472c: 4604 mov r4, r0 + 1472e: b960 cbnz r0, 1474a + 14730: 4b4f ldr r3, [pc, #316] ; (14870 ) + 14732: 4950 ldr r1, [pc, #320] ; (14874 ) + 14734: 9300 str r3, [sp, #0] + 14736: 2242 movs r2, #66 ; 0x42 + 14738: 2003 movs r0, #3 + 1473a: 4e4f ldr r6, [pc, #316] ; (14878 ) + 1473c: 47b0 blx r6 + 1473e: 484f ldr r0, [pc, #316] ; (1487c ) + 14740: 494f ldr r1, [pc, #316] ; (14880 ) + 14742: 462a mov r2, r5 + 14744: 4623 mov r3, r4 + 14746: 4788 blx r1 + 14748: e7fe b.n 14748 + if(img == NULL) return NULL; + 1474a: b315 cbz r5, 14792 + if(ancestor_signal == NULL) ancestor_signal = lv_obj_get_signal_cb(img); + 1474c: 4c4d ldr r4, [pc, #308] ; (14884 ) + 1474e: 6823 ldr r3, [r4, #0] + 14750: b91b cbnz r3, 1475a + 14752: 4b4d ldr r3, [pc, #308] ; (14888 ) + 14754: 4628 mov r0, r5 + 14756: 4798 blx r3 + 14758: 6020 str r0, [r4, #0] + lv_img_ext_t * ext = lv_obj_allocate_ext_attr(img, sizeof(lv_img_ext_t)); + 1475a: 4b4c ldr r3, [pc, #304] ; (1488c ) + 1475c: 2118 movs r1, #24 + 1475e: 4628 mov r0, r5 + 14760: 4798 blx r3 + 14762: 4604 mov r4, r0 + LV_ASSERT_MEM(ext); + 14764: 47c0 blx r8 + 14766: 4680 mov r8, r0 + 14768: b960 cbnz r0, 14784 + 1476a: 4b41 ldr r3, [pc, #260] ; (14870 ) + 1476c: 4941 ldr r1, [pc, #260] ; (14874 ) + 1476e: 9300 str r3, [sp, #0] + 14770: 2249 movs r2, #73 ; 0x49 + 14772: 2003 movs r0, #3 + 14774: 4d40 ldr r5, [pc, #256] ; (14878 ) + 14776: 47a8 blx r5 + 14778: 4840 ldr r0, [pc, #256] ; (1487c ) + 1477a: 4941 ldr r1, [pc, #260] ; (14880 ) + 1477c: 4622 mov r2, r4 + 1477e: 4643 mov r3, r8 + 14780: 4788 blx r1 + 14782: e7fe b.n 14782 + if(ext == NULL) { + 14784: f04f 0800 mov.w r8, #0 + 14788: b93c cbnz r4, 1479a + lv_obj_del(img); + 1478a: 4628 mov r0, r5 + 1478c: 4b40 ldr r3, [pc, #256] ; (14890 ) + 1478e: 4798 blx r3 + return NULL; + 14790: 4625 mov r5, r4 +} + 14792: 4628 mov r0, r5 + 14794: b002 add sp, #8 + 14796: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + ext->src_type = LV_IMG_SRC_UNKNOWN; + 1479a: 7d23 ldrb r3, [r4, #20] + ext->src = NULL; + 1479c: f8c4 8000 str.w r8, [r4] + ext->src_type = LV_IMG_SRC_UNKNOWN; + 147a0: f003 0304 and.w r3, r3, #4 + 147a4: f043 0303 orr.w r3, r3, #3 + 147a8: 7523 strb r3, [r4, #20] + ext->w = lv_obj_get_width(img); + 147aa: 4628 mov r0, r5 + 147ac: 4b39 ldr r3, [pc, #228] ; (14894 ) + 147ae: 4798 blx r3 + ext->h = lv_obj_get_height(img); + 147b0: 4b39 ldr r3, [pc, #228] ; (14898 ) + ext->w = lv_obj_get_width(img); + 147b2: 8120 strh r0, [r4, #8] + ext->h = lv_obj_get_height(img); + 147b4: 4628 mov r0, r5 + 147b6: 4798 blx r3 + ext->pivot.y = 0; + 147b8: f04f 7380 mov.w r3, #16777216 ; 0x1000000 + 147bc: 6123 str r3, [r4, #16] + ext->auto_size = 1; + 147be: 8aa3 ldrh r3, [r4, #20] + lv_obj_set_signal_cb(img, lv_img_signal); + 147c0: 4936 ldr r1, [pc, #216] ; (1489c ) + ext->h = lv_obj_get_height(img); + 147c2: 8160 strh r0, [r4, #10] + ext->auto_size = 1; + 147c4: f443 7382 orr.w r3, r3, #260 ; 0x104 + 147c8: 82a3 strh r3, [r4, #20] + lv_obj_set_signal_cb(img, lv_img_signal); + 147ca: 4628 mov r0, r5 + 147cc: 4b34 ldr r3, [pc, #208] ; (148a0 ) + ext->offset.x = 0; + 147ce: f8c4 8004 str.w r8, [r4, #4] + ext->angle = 0; + 147d2: f8c4 800c str.w r8, [r4, #12] + lv_obj_set_signal_cb(img, lv_img_signal); + 147d6: 4798 blx r3 + lv_obj_set_design_cb(img, lv_img_design); + 147d8: 4932 ldr r1, [pc, #200] ; (148a4 ) + 147da: 4b33 ldr r3, [pc, #204] ; (148a8 ) + 147dc: 4628 mov r0, r5 + 147de: 4798 blx r3 + if(copy == NULL) { + 147e0: b9e6 cbnz r6, 1481c + lv_theme_apply(img, LV_THEME_IMAGE); + 147e2: 4b32 ldr r3, [pc, #200] ; (148ac ) + 147e4: 210f movs r1, #15 + 147e6: 4628 mov r0, r5 + 147e8: 4798 blx r3 + lv_obj_set_click(img, false); + 147ea: 4b31 ldr r3, [pc, #196] ; (148b0 ) + 147ec: 4631 mov r1, r6 + 147ee: 4628 mov r0, r5 + 147f0: 4798 blx r3 + lv_obj_set_adv_hittest(img, true); /*Images have fast hit-testing*/ + 147f2: 4b30 ldr r3, [pc, #192] ; (148b4 ) + 147f4: 2101 movs r1, #1 + 147f6: 4628 mov r0, r5 + 147f8: 4798 blx r3 + if(par != NULL) { + 147fa: 7d23 ldrb r3, [r4, #20] + 147fc: b15f cbz r7, 14816 + ext->auto_size = 1; + 147fe: f043 0304 orr.w r3, r3, #4 + ext->auto_size = 0; + 14802: 7523 strb r3, [r4, #20] + LV_LOG_INFO("image created"); + 14804: 4b2c ldr r3, [pc, #176] ; (148b8 ) + 14806: 9300 str r3, [sp, #0] + 14808: 491a ldr r1, [pc, #104] ; (14874 ) + 1480a: 4b19 ldr r3, [pc, #100] ; (14870 ) + 1480c: 4c1a ldr r4, [pc, #104] ; (14878 ) + 1480e: 227f movs r2, #127 ; 0x7f + 14810: 2001 movs r0, #1 + 14812: 47a0 blx r4 + return img; + 14814: e7bd b.n 14792 + ext->auto_size = 0; + 14816: f367 0382 bfi r3, r7, #2, #1 + 1481a: e7f2 b.n 14802 + lv_img_ext_t * copy_ext = lv_obj_get_ext_attr(copy); + 1481c: 4b27 ldr r3, [pc, #156] ; (148bc ) + 1481e: 4630 mov r0, r6 + 14820: 4798 blx r3 + ext->auto_size = copy_ext->auto_size; + 14822: 7d03 ldrb r3, [r0, #20] + 14824: 7d22 ldrb r2, [r4, #20] + 14826: f3c3 0380 ubfx r3, r3, #2, #1 + 1482a: f363 0282 bfi r2, r3, #2, #1 + 1482e: 7522 strb r2, [r4, #20] + ext->zoom = copy_ext->zoom; + 14830: 8a43 ldrh r3, [r0, #18] + 14832: 8263 strh r3, [r4, #18] + ext->angle = copy_ext->angle; + 14834: 8983 ldrh r3, [r0, #12] + ext->antialias = copy_ext->antialias; + 14836: 7d42 ldrb r2, [r0, #21] + ext->angle = copy_ext->angle; + 14838: 81a3 strh r3, [r4, #12] + ext->antialias = copy_ext->antialias; + 1483a: 7d63 ldrb r3, [r4, #21] + 1483c: f362 0300 bfi r3, r2, #0, #1 + 14840: 7563 strb r3, [r4, #21] + ext->offset.x = copy_ext->offset.x; + 14842: f9b0 3004 ldrsh.w r3, [r0, #4] + 14846: 80a3 strh r3, [r4, #4] + ext->offset.y = copy_ext->offset.y; + 14848: f9b0 3006 ldrsh.w r3, [r0, #6] + 1484c: 80e3 strh r3, [r4, #6] + ext->pivot.x = copy_ext->pivot.x; + 1484e: f9b0 300e ldrsh.w r3, [r0, #14] + 14852: 81e3 strh r3, [r4, #14] + ext->pivot.y = copy_ext->pivot.y; + 14854: f9b0 3010 ldrsh.w r3, [r0, #16] + lv_img_set_src(img, copy_ext->src); + 14858: 6801 ldr r1, [r0, #0] + ext->pivot.y = copy_ext->pivot.y; + 1485a: 8223 strh r3, [r4, #16] + lv_img_set_src(img, copy_ext->src); + 1485c: 4628 mov r0, r5 + 1485e: 4b18 ldr r3, [pc, #96] ; (148c0 ) + 14860: 4798 blx r3 + lv_obj_refresh_style(img, LV_STYLE_PROP_ALL); + 14862: 4b18 ldr r3, [pc, #96] ; (148c4 ) + 14864: 21ff movs r1, #255 ; 0xff + 14866: 4628 mov r0, r5 + 14868: 4798 blx r3 + 1486a: e7cb b.n 14804 + 1486c: 000030e5 .word 0x000030e5 + 14870: 000243c4 .word 0x000243c4 + 14874: 00024278 .word 0x00024278 + 14878: 0000e8e9 .word 0x0000e8e9 + 1487c: 0001edbe .word 0x0001edbe + 14880: 000017e9 .word 0x000017e9 + 14884: 2000c7f8 .word 0x2000c7f8 + 14888: 00003f61 .word 0x00003f61 + 1488c: 00002079 .word 0x00002079 + 14890: 00004161 .word 0x00004161 + 14894: 000023ed .word 0x000023ed + 14898: 0000243d .word 0x0000243d + 1489c: 000148cd .word 0x000148cd + 148a0: 00001fdd .word 0x00001fdd + 148a4: 00014009 .word 0x00014009 + 148a8: 00002031 .word 0x00002031 + 148ac: 000102e5 .word 0x000102e5 + 148b0: 00001e5d .word 0x00001e5d + 148b4: 00001e09 .word 0x00001e09 + 148b8: 0002431c .word 0x0002431c + 148bc: 00003fa9 .word 0x00003fa9 + 148c0: 000144c5 .word 0x000144c5 + 148c4: 00002d91 .word 0x00002d91 + 148c8: 000017e1 .word 0x000017e1 + +000148cc : + * @param sign a signal type from lv_signal_t enum + * @param param pointer to a signal specific variable + * @return LV_RES_OK: the object is not deleted in the function; LV_RES_INV: the object is deleted + */ +static lv_res_t lv_img_signal(lv_obj_t * img, lv_signal_t sign, void * param) +{ + 148cc: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} + lv_res_t res; + if(sign == LV_SIGNAL_GET_STYLE) { + 148d0: 2908 cmp r1, #8 +{ + 148d2: b085 sub sp, #20 + 148d4: 4604 mov r4, r0 + 148d6: 4689 mov r9, r1 + 148d8: 4616 mov r6, r2 + if(sign == LV_SIGNAL_GET_STYLE) { + 148da: d110 bne.n 148fe + + +static lv_style_list_t * lv_img_get_style(lv_obj_t * img, uint8_t type) +{ + lv_style_list_t * style_dsc_p; + switch(type) { + 148dc: 7813 ldrb r3, [r2, #0] + 148de: b13b cbz r3, 148f0 + info->result = lv_img_get_style(img, info->part); + 148e0: 2300 movs r3, #0 + 148e2: 6053 str r3, [r2, #4] + else return ancestor_signal(img, sign, param); + 148e4: 4b83 ldr r3, [pc, #524] ; (14af4 ) + 148e6: 681b ldr r3, [r3, #0] +} + 148e8: b005 add sp, #20 + 148ea: e8bd 43f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, lr} + else return ancestor_signal(img, sign, param); + 148ee: 4718 bx r3 + case LV_IMG_PART_MAIN: + style_dsc_p = &img->style_list; + 148f0: 3428 adds r4, #40 ; 0x28 + info->result = lv_img_get_style(img, info->part); + 148f2: 6054 str r4, [r2, #4] + if(info->result != NULL) return LV_RES_OK; + 148f4: 2701 movs r7, #1 +} + 148f6: 4638 mov r0, r7 + 148f8: b005 add sp, #20 + 148fa: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + res = ancestor_signal(img, sign, param); + 148fe: 4b7d ldr r3, [pc, #500] ; (14af4 ) + 14900: 681b ldr r3, [r3, #0] + 14902: 4798 blx r3 + if(res != LV_RES_OK) return res; + 14904: 2801 cmp r0, #1 + res = ancestor_signal(img, sign, param); + 14906: 4607 mov r7, r0 + if(res != LV_RES_OK) return res; + 14908: d1f5 bne.n 148f6 + if(sign == LV_SIGNAL_GET_TYPE) return lv_obj_handle_get_type_signal(param, LV_OBJX_NAME); + 1490a: f1b9 0f07 cmp.w r9, #7 + 1490e: d106 bne.n 1491e + 14910: 4979 ldr r1, [pc, #484] ; (14af8 ) + 14912: 4b7a ldr r3, [pc, #488] ; (14afc ) + 14914: 4630 mov r0, r6 +} + 14916: b005 add sp, #20 + 14918: e8bd 43f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, lr} + if(sign == LV_SIGNAL_GET_TYPE) return lv_obj_handle_get_type_signal(param, LV_OBJX_NAME); + 1491c: 4718 bx r3 + lv_img_ext_t * ext = lv_obj_get_ext_attr(img); + 1491e: 4b78 ldr r3, [pc, #480] ; (14b00 ) + 14920: 4620 mov r0, r4 + 14922: 4798 blx r3 + 14924: 4605 mov r5, r0 + if(sign == LV_SIGNAL_CLEANUP) { + 14926: f1b9 0f00 cmp.w r9, #0 + 1492a: d10f bne.n 1494c + if(ext->src_type == LV_IMG_SRC_FILE || ext->src_type == LV_IMG_SRC_SYMBOL) { + 1492c: 7d03 ldrb r3, [r0, #20] + 1492e: f003 0303 and.w r3, r3, #3 + 14932: 3b01 subs r3, #1 + 14934: 2b01 cmp r3, #1 + 14936: d8de bhi.n 148f6 + lv_mem_free(ext->src); + 14938: 4b72 ldr r3, [pc, #456] ; (14b04 ) + 1493a: 6800 ldr r0, [r0, #0] + 1493c: 4798 blx r3 + ext->src_type = LV_IMG_SRC_UNKNOWN; + 1493e: 7d2b ldrb r3, [r5, #20] + ext->src = NULL; + 14940: f8c5 9000 str.w r9, [r5] + ext->src_type = LV_IMG_SRC_UNKNOWN; + 14944: f043 0303 orr.w r3, r3, #3 + 14948: 752b strb r3, [r5, #20] + 1494a: e7d4 b.n 148f6 + else if(sign == LV_SIGNAL_STYLE_CHG) { + 1494c: f1b9 0f04 cmp.w r9, #4 + 14950: d109 bne.n 14966 + if(ext->src_type == LV_IMG_SRC_SYMBOL) { + 14952: 7d03 ldrb r3, [r0, #20] + 14954: f003 0303 and.w r3, r3, #3 + 14958: 2b02 cmp r3, #2 + 1495a: d1cc bne.n 148f6 + lv_img_set_src(img, ext->src); + 1495c: 6801 ldr r1, [r0, #0] + 1495e: 4b6a ldr r3, [pc, #424] ; (14b08 ) + 14960: 4620 mov r0, r4 + 14962: 4798 blx r3 + 14964: e7c7 b.n 148f6 + else if(sign == LV_SIGNAL_REFR_EXT_DRAW_PAD) { + 14966: f1b9 0f06 cmp.w r9, #6 + 1496a: d16e bne.n 14a4a +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSFORM_ZOOM, transform_zoom, lv_style_int_t, _int, scalar) + 1496c: 4e67 ldr r6, [pc, #412] ; (14b0c ) + 1496e: 2207 movs r2, #7 + 14970: 2100 movs r1, #0 + 14972: 4620 mov r0, r4 + 14974: 47b0 blx r6 + transf_zoom = (transf_zoom * ext->zoom) >> 8; + 14976: f8b5 8012 ldrh.w r8, [r5, #18] +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSFORM_ANGLE, transform_angle, lv_style_int_t, _int, scalar) + 1497a: 464a mov r2, r9 + 1497c: fb00 f808 mul.w r8, r0, r8 + 14980: 2100 movs r1, #0 + 14982: 4620 mov r0, r4 + 14984: 47b0 blx r6 + transf_angle += ext->angle; + 14986: 89ab ldrh r3, [r5, #12] + 14988: 4418 add r0, r3 + 1498a: b203 sxth r3, r0 + transf_zoom = (transf_zoom * ext->zoom) >> 8; + 1498c: ea4f 2828 mov.w r8, r8, asr #8 + if(transf_angle || transf_zoom != LV_IMG_ZOOM_NONE) { + 14990: b923 cbnz r3, 1499c + 14992: fa0f f288 sxth.w r2, r8 + 14996: f5b2 7f80 cmp.w r2, #256 ; 0x100 + 1499a: d031 beq.n 14a00 + _lv_img_buf_get_transformed_area(&a, ext->w, ext->h, transf_angle, transf_zoom, &ext->pivot); + 1499c: f105 000e add.w r0, r5, #14 + 149a0: f9b5 200a ldrsh.w r2, [r5, #10] + 149a4: f9b5 1008 ldrsh.w r1, [r5, #8] + 149a8: 9001 str r0, [sp, #4] + 149aa: fa1f f088 uxth.w r0, r8 + 149ae: 9000 str r0, [sp, #0] + 149b0: f8df 8164 ldr.w r8, [pc, #356] ; 14b18 + 149b4: a802 add r0, sp, #8 + 149b6: 47c0 blx r8 + img->ext_draw_pad = LV_MATH_MAX(img->ext_draw_pad, pad_ori - a.x1); + 149b8: f9b4 1032 ldrsh.w r1, [r4, #50] ; 0x32 + 149bc: f9bd 3008 ldrsh.w r3, [sp, #8] + img->ext_draw_pad = LV_MATH_MAX(img->ext_draw_pad, pad_ori - a.y1); + 149c0: f9bd 200a ldrsh.w r2, [sp, #10] + img->ext_draw_pad = LV_MATH_MAX(img->ext_draw_pad, pad_ori + a.x2 - ext->w); + 149c4: f9b5 0008 ldrsh.w r0, [r5, #8] + img->ext_draw_pad = LV_MATH_MAX(img->ext_draw_pad, pad_ori - a.x1); + 149c8: 1acb subs r3, r1, r3 + 149ca: 428b cmp r3, r1 + 149cc: bfb8 it lt + 149ce: 460b movlt r3, r1 + img->ext_draw_pad = LV_MATH_MAX(img->ext_draw_pad, pad_ori - a.y1); + 149d0: 1a8a subs r2, r1, r2 + 149d2: b21b sxth r3, r3 + 149d4: 4293 cmp r3, r2 + 149d6: bfb8 it lt + 149d8: 4613 movlt r3, r2 + img->ext_draw_pad = LV_MATH_MAX(img->ext_draw_pad, pad_ori + a.x2 - ext->w); + 149da: f9bd 200c ldrsh.w r2, [sp, #12] + 149de: 440a add r2, r1 + 149e0: b21b sxth r3, r3 + 149e2: 1a12 subs r2, r2, r0 + 149e4: 4293 cmp r3, r2 + 149e6: bfb8 it lt + 149e8: 4613 movlt r3, r2 + img->ext_draw_pad = LV_MATH_MAX(img->ext_draw_pad, pad_ori + a.y2 - ext->h); + 149ea: f9bd 200e ldrsh.w r2, [sp, #14] + 149ee: 440a add r2, r1 + 149f0: f9b5 100a ldrsh.w r1, [r5, #10] + 149f4: b21b sxth r3, r3 + 149f6: 1a52 subs r2, r2, r1 + 149f8: 4293 cmp r3, r2 + 149fa: bfb8 it lt + 149fc: 4613 movlt r3, r2 + 149fe: 8663 strh r3, [r4, #50] ; 0x32 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_LEFT, pad_left, lv_style_int_t, _int, scalar) + 14a00: 2212 movs r2, #18 + 14a02: 2100 movs r1, #0 + 14a04: 4620 mov r0, r4 + 14a06: 47b0 blx r6 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_RIGHT, pad_right, lv_style_int_t, _int, scalar) + 14a08: 2213 movs r2, #19 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_LEFT, pad_left, lv_style_int_t, _int, scalar) + 14a0a: 4681 mov r9, r0 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_RIGHT, pad_right, lv_style_int_t, _int, scalar) + 14a0c: 2100 movs r1, #0 + 14a0e: 4620 mov r0, r4 + 14a10: 47b0 blx r6 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_TOP, pad_top, lv_style_int_t, _int, scalar) + 14a12: 2210 movs r2, #16 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_RIGHT, pad_right, lv_style_int_t, _int, scalar) + 14a14: 4605 mov r5, r0 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_TOP, pad_top, lv_style_int_t, _int, scalar) + 14a16: 2100 movs r1, #0 + 14a18: 4620 mov r0, r4 + 14a1a: 47b0 blx r6 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_BOTTOM, pad_bottom, lv_style_int_t, _int, scalar) + 14a1c: 2211 movs r2, #17 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_TOP, pad_top, lv_style_int_t, _int, scalar) + 14a1e: 4680 mov r8, r0 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_BOTTOM, pad_bottom, lv_style_int_t, _int, scalar) + 14a20: 2100 movs r1, #0 + 14a22: 4620 mov r0, r4 + 14a24: 47b0 blx r6 + img->ext_draw_pad = LV_MATH_MAX(img->ext_draw_pad, right); + 14a26: 454d cmp r5, r9 + 14a28: f9b4 3032 ldrsh.w r3, [r4, #50] ; 0x32 + 14a2c: bfb8 it lt + 14a2e: 464d movlt r5, r9 + 14a30: b22d sxth r5, r5 + img->ext_draw_pad = LV_MATH_MAX(img->ext_draw_pad, top); + 14a32: 42ab cmp r3, r5 + 14a34: bfb8 it lt + 14a36: 462b movlt r3, r5 + 14a38: 4543 cmp r3, r8 + 14a3a: bfb8 it lt + 14a3c: 4643 movlt r3, r8 + img->ext_draw_pad = LV_MATH_MAX(img->ext_draw_pad, bottom); + 14a3e: b21b sxth r3, r3 + 14a40: 4298 cmp r0, r3 + 14a42: bfb8 it lt + 14a44: 4618 movlt r0, r3 + 14a46: 8660 strh r0, [r4, #50] ; 0x32 + 14a48: e755 b.n 148f6 + else if(sign == LV_SIGNAL_HIT_TEST) { + 14a4a: f1b9 0f0a cmp.w r9, #10 + 14a4e: f47f af52 bne.w 148f6 + if(ext->zoom != 256 && ext->angle == 0) { + 14a52: f8b0 c012 ldrh.w ip, [r0, #18] + 14a56: f5bc 7f80 cmp.w ip, #256 ; 0x100 + 14a5a: d045 beq.n 14ae8 + 14a5c: 8983 ldrh r3, [r0, #12] + 14a5e: 2b00 cmp r3, #0 + 14a60: d142 bne.n 14ae8 + 14a62: 8aa5 ldrh r5, [r4, #20] + 14a64: 8a23 ldrh r3, [r4, #16] + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + 14a66: 8a62 ldrh r2, [r4, #18] +{ + uint8_t * d8 = (uint8_t *)dst; + const uint8_t * s8 = (const uint8_t *)src; + + while(len) { + *d8 = *s8; + 14a68: 6920 ldr r0, [r4, #16] + 14a6a: 6961 ldr r1, [r4, #20] + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + 14a6c: 3501 adds r5, #1 + 14a6e: 1aed subs r5, r5, r3 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + 14a70: 8ae3 ldrh r3, [r4, #22] + 14a72: 3301 adds r3, #1 + lv_coord_t scaled_width = (origin_width * ext->zoom + 255) / 256; + 14a74: b22d sxth r5, r5 + 14a76: 1a9b subs r3, r3, r2 + 14a78: aa02 add r2, sp, #8 + 14a7a: c203 stmia r2!, {r0, r1} + 14a7c: fb0c f205 mul.w r2, ip, r5 + 14a80: 32ff adds r2, #255 ; 0xff + 14a82: bf48 it mi + 14a84: 32ff addmi r2, #255 ; 0xff + lv_coord_t width_offset = (origin_width - scaled_width) / 2; + 14a86: f342 220f sbfx r2, r2, #8, #16 + 14a8a: 1aad subs r5, r5, r2 + 14a8c: eb05 75d5 add.w r5, r5, r5, lsr #31 + coords.x1 += width_offset; + 14a90: f8bd 2008 ldrh.w r2, [sp, #8] + info->result = _lv_area_is_point_on(&coords, info->point, 0); + 14a94: 6831 ldr r1, [r6, #0] + coords.x1 += width_offset; + 14a96: f3c5 054f ubfx r5, r5, #1, #16 + 14a9a: 442a add r2, r5 + 14a9c: f8ad 2008 strh.w r2, [sp, #8] + coords.x2 -= width_offset; + 14aa0: f8bd 200c ldrh.w r2, [sp, #12] + lv_coord_t scaled_height = (origin_height * ext->zoom + 255) / 256; + 14aa4: b21b sxth r3, r3 + 14aa6: fb03 fc0c mul.w ip, r3, ip + coords.x2 -= width_offset; + 14aaa: 1b52 subs r2, r2, r5 + 14aac: f8ad 200c strh.w r2, [sp, #12] + lv_coord_t scaled_height = (origin_height * ext->zoom + 255) / 256; + 14ab0: f11c 02ff adds.w r2, ip, #255 ; 0xff + 14ab4: bf48 it mi + 14ab6: f50c 72ff addmi.w r2, ip, #510 ; 0x1fe + lv_coord_t height_offset = (origin_height - scaled_height) / 2; + 14aba: f342 220f sbfx r2, r2, #8, #16 + 14abe: 1a9b subs r3, r3, r2 + 14ac0: eb03 73d3 add.w r3, r3, r3, lsr #31 + coords.y1 += height_offset; + 14ac4: f8bd 200a ldrh.w r2, [sp, #10] + 14ac8: f3c3 034f ubfx r3, r3, #1, #16 + 14acc: 441a add r2, r3 + 14ace: f8ad 200a strh.w r2, [sp, #10] + coords.y2 -= height_offset; + 14ad2: f8bd 200e ldrh.w r2, [sp, #14] + 14ad6: 1ad3 subs r3, r2, r3 + 14ad8: f8ad 300e strh.w r3, [sp, #14] + info->result = _lv_area_is_point_on(&coords, info->point, 0); + 14adc: 2200 movs r2, #0 + 14ade: 4b0c ldr r3, [pc, #48] ; (14b10 ) + 14ae0: a802 add r0, sp, #8 + 14ae2: 4798 blx r3 + info->result = lv_obj_is_point_on_coords(img, info->point); + 14ae4: 7130 strb r0, [r6, #4] + 14ae6: e706 b.n 148f6 + 14ae8: 6831 ldr r1, [r6, #0] + 14aea: 4b0a ldr r3, [pc, #40] ; (14b14 ) + 14aec: 4620 mov r0, r4 + 14aee: 4798 blx r3 + 14af0: e7f8 b.n 14ae4 + 14af2: bf00 nop + 14af4: 2000c7f8 .word 0x2000c7f8 + 14af8: 0002432a .word 0x0002432a + 14afc: 0000428d .word 0x0000428d + 14b00: 00003fa9 .word 0x00003fa9 + 14b04: 0000eae5 .word 0x0000eae5 + 14b08: 000144c5 .word 0x000144c5 + 14b0c: 00003711 .word 0x00003711 + 14b10: 0000df25 .word 0x0000df25 + 14b14: 00004251 .word 0x00004251 + 14b18: 0000c061 .word 0x0000c061 + +00014b1c : + * Free the dot_tmp_ptr field if it was previously allocated. + * Always clears the field + * @param label pointer to label object. + */ +static void lv_label_dot_tmp_free(lv_obj_t * label) +{ + 14b1c: b510 push {r4, lr} + lv_label_ext_t * ext = lv_obj_get_ext_attr(label); + 14b1e: 4b08 ldr r3, [pc, #32] ; (14b40 ) + 14b20: 4798 blx r3 + if(ext->dot_tmp_alloc && ext->dot.tmp_ptr) { + 14b22: 7c43 ldrb r3, [r0, #17] + 14b24: 07db lsls r3, r3, #31 + lv_label_ext_t * ext = lv_obj_get_ext_attr(label); + 14b26: 4604 mov r4, r0 + if(ext->dot_tmp_alloc && ext->dot.tmp_ptr) { + 14b28: d503 bpl.n 14b32 + 14b2a: 6840 ldr r0, [r0, #4] + 14b2c: b108 cbz r0, 14b32 + lv_mem_free(ext->dot.tmp_ptr); + 14b2e: 4b05 ldr r3, [pc, #20] ; (14b44 ) + 14b30: 4798 blx r3 + } + ext->dot_tmp_alloc = false; + 14b32: 7c63 ldrb r3, [r4, #17] + 14b34: f36f 0300 bfc r3, #0, #1 + 14b38: 7463 strb r3, [r4, #17] + ext->dot.tmp_ptr = NULL; + 14b3a: 2300 movs r3, #0 + 14b3c: 6063 str r3, [r4, #4] +} + 14b3e: bd10 pop {r4, pc} + 14b40: 00003fa9 .word 0x00003fa9 + 14b44: 0000eae5 .word 0x0000eae5 + +00014b48 : +{ + 14b48: b5f8 push {r3, r4, r5, r6, r7, lr} + lv_label_ext_t * ext = lv_obj_get_ext_attr(label); + 14b4a: 4e1a ldr r6, [pc, #104] ; (14bb4 ) +{ + 14b4c: 4605 mov r5, r0 + lv_label_ext_t * ext = lv_obj_get_ext_attr(label); + 14b4e: 47b0 blx r6 + if(ext->long_mode != LV_LABEL_LONG_DOT) return; + 14b50: 7c03 ldrb r3, [r0, #16] + 14b52: f003 0307 and.w r3, r3, #7 + 14b56: 2b02 cmp r3, #2 + lv_label_ext_t * ext = lv_obj_get_ext_attr(label); + 14b58: 4604 mov r4, r0 + if(ext->long_mode != LV_LABEL_LONG_DOT) return; + 14b5a: d128 bne.n 14bae + if(ext->dot_end == LV_LABEL_DOT_END_INV) return; + 14b5c: 8901 ldrh r1, [r0, #8] + 14b5e: f64f 73ff movw r3, #65535 ; 0xffff + 14b62: 4299 cmp r1, r3 + 14b64: d023 beq.n 14bae + uint32_t byte_i = _lv_txt_encoded_get_byte_id(ext->text, letter_i); + 14b66: 4b14 ldr r3, [pc, #80] ; (14bb8 ) + 14b68: 6800 ldr r0, [r0, #0] + 14b6a: 681b ldr r3, [r3, #0] + 14b6c: 3903 subs r1, #3 + 14b6e: 4798 blx r3 + 14b70: 4607 mov r7, r0 + lv_label_ext_t * ext = lv_obj_get_ext_attr(label); + 14b72: 4628 mov r0, r5 + 14b74: 47b0 blx r6 + if(ext->dot_tmp_alloc) { + 14b76: 7c42 ldrb r2, [r0, #17] + 14b78: 07d2 lsls r2, r2, #31 + lv_label_ext_t * ext = lv_obj_get_ext_attr(label); + 14b7a: 4603 mov r3, r0 + return ext->dot.tmp_ptr; + 14b7c: bf4c ite mi + 14b7e: 6843 ldrmi r3, [r0, #4] + return ext->dot.tmp; + 14b80: 3304 addpl r3, #4 + while(ext->text[byte_i + i] != '\0') { + 14b82: 2200 movs r2, #0 + 14b84: fa57 f182 uxtab r1, r7, r2 + 14b88: 6826 ldr r6, [r4, #0] + 14b8a: b2d0 uxtb r0, r2 + 14b8c: f816 e001 ldrb.w lr, [r6, r1] + ext->text[byte_i + i] = dot_tmp[i]; + 14b90: 5c18 ldrb r0, [r3, r0] + while(ext->text[byte_i + i] != '\0') { + 14b92: eb06 0c01 add.w ip, r6, r1 + 14b96: 3201 adds r2, #1 + 14b98: f1be 0f00 cmp.w lr, #0 + 14b9c: d108 bne.n 14bb0 + lv_label_dot_tmp_free(label); + 14b9e: 4b07 ldr r3, [pc, #28] ; (14bbc ) + ext->text[byte_i + i] = dot_tmp[i]; + 14ba0: f88c 0000 strb.w r0, [ip] + lv_label_dot_tmp_free(label); + 14ba4: 4628 mov r0, r5 + 14ba6: 4798 blx r3 + ext->dot_end = LV_LABEL_DOT_END_INV; + 14ba8: f64f 73ff movw r3, #65535 ; 0xffff + 14bac: 8123 strh r3, [r4, #8] +} + 14bae: bdf8 pop {r3, r4, r5, r6, r7, pc} + ext->text[byte_i + i] = dot_tmp[i]; + 14bb0: 5470 strb r0, [r6, r1] + i++; + 14bb2: e7e7 b.n 14b84 + 14bb4: 00003fa9 .word 0x00003fa9 + 14bb8: 2000005c .word 0x2000005c + 14bbc: 00014b1d .word 0x00014b1d + +00014bc0 : +{ + 14bc0: b570 push {r4, r5, r6, lr} + lv_label_ext_t * ext = lv_obj_get_ext_attr(label); + 14bc2: 4b05 ldr r3, [pc, #20] ; (14bd8 ) +{ + 14bc4: 4604 mov r4, r0 + 14bc6: 460d mov r5, r1 + lv_label_ext_t * ext = lv_obj_get_ext_attr(label); + 14bc8: 4798 blx r3 + lv_obj_invalidate(label); + 14bca: 4b04 ldr r3, [pc, #16] ; (14bdc ) + ext->offset.y = y; + 14bcc: 81c5 strh r5, [r0, #14] + lv_obj_invalidate(label); + 14bce: 4620 mov r0, r4 +} + 14bd0: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + lv_obj_invalidate(label); + 14bd4: 4718 bx r3 + 14bd6: bf00 nop + 14bd8: 00003fa9 .word 0x00003fa9 + 14bdc: 00002785 .word 0x00002785 + +00014be0 : +{ + 14be0: b570 push {r4, r5, r6, lr} + lv_label_ext_t * ext = lv_obj_get_ext_attr(label); + 14be2: 4b05 ldr r3, [pc, #20] ; (14bf8 ) +{ + 14be4: 4604 mov r4, r0 + 14be6: 460d mov r5, r1 + lv_label_ext_t * ext = lv_obj_get_ext_attr(label); + 14be8: 4798 blx r3 + lv_obj_invalidate(label); + 14bea: 4b04 ldr r3, [pc, #16] ; (14bfc ) + ext->offset.x = x; + 14bec: 8185 strh r5, [r0, #12] + lv_obj_invalidate(label); + 14bee: 4620 mov r0, r4 +} + 14bf0: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + lv_obj_invalidate(label); + 14bf4: 4718 bx r3 + 14bf6: bf00 nop + 14bf8: 00003fa9 .word 0x00003fa9 + 14bfc: 00002785 .word 0x00002785 + +00014c00 : +{ + 14c00: b57f push {r0, r1, r2, r3, r4, r5, r6, lr} + lv_label_ext_t * ext = lv_obj_get_ext_attr(label); + 14c02: 4b1a ldr r3, [pc, #104] ; (14c6c ) +{ + 14c04: 9103 str r1, [sp, #12] + 14c06: 4616 mov r6, r2 + 14c08: 4604 mov r4, r0 + lv_label_ext_t * ext = lv_obj_get_ext_attr(label); + 14c0a: 4798 blx r3 + lv_label_dot_tmp_free(label); /* Deallocate any existing space */ + 14c0c: 4b18 ldr r3, [pc, #96] ; (14c70 ) + lv_label_ext_t * ext = lv_obj_get_ext_attr(label); + 14c0e: 4605 mov r5, r0 + lv_label_dot_tmp_free(label); /* Deallocate any existing space */ + 14c10: 4620 mov r0, r4 + 14c12: 4798 blx r3 + if(len > sizeof(char *)) { + 14c14: 2e04 cmp r6, #4 + 14c16: 9903 ldr r1, [sp, #12] + 14c18: d91e bls.n 14c58 + ext->dot.tmp_ptr = lv_mem_alloc(len + 1); + 14c1a: 4b16 ldr r3, [pc, #88] ; (14c74 ) + 14c1c: 1c70 adds r0, r6, #1 + 14c1e: 4798 blx r3 + if(ext->dot.tmp_ptr == NULL) { + 14c20: 9903 ldr r1, [sp, #12] + ext->dot.tmp_ptr = lv_mem_alloc(len + 1); + 14c22: 6068 str r0, [r5, #4] + 14c24: 4604 mov r4, r0 + if(ext->dot.tmp_ptr == NULL) { + 14c26: b958 cbnz r0, 14c40 + LV_LOG_ERROR("Failed to allocate memory for dot_tmp_ptr"); + 14c28: 4b13 ldr r3, [pc, #76] ; (14c78 ) + 14c2a: 9300 str r3, [sp, #0] + 14c2c: 2003 movs r0, #3 + 14c2e: 4b13 ldr r3, [pc, #76] ; (14c7c ) + 14c30: 4913 ldr r1, [pc, #76] ; (14c80 ) + 14c32: 4d14 ldr r5, [pc, #80] ; (14c84 ) + 14c34: f240 52b5 movw r2, #1461 ; 0x5b5 + 14c38: 47a8 blx r5 + return false; + 14c3a: 4620 mov r0, r4 +} + 14c3c: b004 add sp, #16 + 14c3e: bd70 pop {r4, r5, r6, pc} + _lv_memcpy(ext->dot.tmp_ptr, data, len); + 14c40: 4b11 ldr r3, [pc, #68] ; (14c88 ) + 14c42: 4632 mov r2, r6 + 14c44: 4798 blx r3 + ext->dot.tmp_ptr[len] = '\0'; + 14c46: 686b ldr r3, [r5, #4] + 14c48: 2200 movs r2, #0 + 14c4a: 559a strb r2, [r3, r6] + ext->dot_tmp_alloc = true; + 14c4c: 7c6b ldrb r3, [r5, #17] + 14c4e: f043 0301 orr.w r3, r3, #1 + 14c52: 746b strb r3, [r5, #17] + return true; + 14c54: 2001 movs r0, #1 + 14c56: e7f1 b.n 14c3c + ext->dot_tmp_alloc = false; + 14c58: 7c6b ldrb r3, [r5, #17] + 14c5a: f36f 0300 bfc r3, #0, #1 + 14c5e: 746b strb r3, [r5, #17] + _lv_memcpy(ext->dot.tmp, data, len); + 14c60: 4632 mov r2, r6 + 14c62: 4b09 ldr r3, [pc, #36] ; (14c88 ) + 14c64: 1d28 adds r0, r5, #4 + 14c66: 4798 blx r3 + 14c68: e7f4 b.n 14c54 + 14c6a: bf00 nop + 14c6c: 00003fa9 .word 0x00003fa9 + 14c70: 00014b1d .word 0x00014b1d + 14c74: 0000ea2d .word 0x0000ea2d + 14c78: 00024475 .word 0x00024475 + 14c7c: 000244bb .word 0x000244bb + 14c80: 00024441 .word 0x00024441 + 14c84: 0000e8e9 .word 0x0000e8e9 + 14c88: 0000ec31 .word 0x0000ec31 + +00014c8c : + +static void get_txt_coords(const lv_obj_t * label, lv_area_t * area) +{ + 14c8c: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + lv_obj_get_coords(label, area); + 14c90: 4b13 ldr r3, [pc, #76] ; (14ce0 ) +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_LEFT, pad_left, lv_style_int_t, _int, scalar) + 14c92: f8df 8050 ldr.w r8, [pc, #80] ; 14ce4 +{ + 14c96: 4605 mov r5, r0 + 14c98: 460c mov r4, r1 + lv_obj_get_coords(label, area); + 14c9a: 4798 blx r3 + 14c9c: 2212 movs r2, #18 + 14c9e: 2100 movs r1, #0 + 14ca0: 4628 mov r0, r5 + 14ca2: 47c0 blx r8 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_RIGHT, pad_right, lv_style_int_t, _int, scalar) + 14ca4: 2213 movs r2, #19 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_LEFT, pad_left, lv_style_int_t, _int, scalar) + 14ca6: 4607 mov r7, r0 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_RIGHT, pad_right, lv_style_int_t, _int, scalar) + 14ca8: 2100 movs r1, #0 + 14caa: 4628 mov r0, r5 + 14cac: 47c0 blx r8 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_TOP, pad_top, lv_style_int_t, _int, scalar) + 14cae: 2210 movs r2, #16 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_RIGHT, pad_right, lv_style_int_t, _int, scalar) + 14cb0: 4681 mov r9, r0 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_TOP, pad_top, lv_style_int_t, _int, scalar) + 14cb2: 2100 movs r1, #0 + 14cb4: 4628 mov r0, r5 + 14cb6: 47c0 blx r8 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_BOTTOM, pad_bottom, lv_style_int_t, _int, scalar) + 14cb8: 2211 movs r2, #17 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_TOP, pad_top, lv_style_int_t, _int, scalar) + 14cba: 4606 mov r6, r0 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_BOTTOM, pad_bottom, lv_style_int_t, _int, scalar) + 14cbc: 2100 movs r1, #0 + 14cbe: 4628 mov r0, r5 + 14cc0: 47c0 blx r8 + + lv_coord_t left = lv_obj_get_style_pad_left(label, LV_LABEL_PART_MAIN); + lv_coord_t right = lv_obj_get_style_pad_right(label, LV_LABEL_PART_MAIN); + lv_coord_t top = lv_obj_get_style_pad_top(label, LV_LABEL_PART_MAIN); + lv_coord_t bottom = lv_obj_get_style_pad_bottom(label, LV_LABEL_PART_MAIN); + area->x1 += left; + 14cc2: 8823 ldrh r3, [r4, #0] + 14cc4: 441f add r7, r3 + area->x2 -= right; + 14cc6: 88a3 ldrh r3, [r4, #4] + area->x1 += left; + 14cc8: 8027 strh r7, [r4, #0] + area->x2 -= right; + 14cca: eba3 0309 sub.w r3, r3, r9 + 14cce: 80a3 strh r3, [r4, #4] + area->y1 += top; + 14cd0: 8863 ldrh r3, [r4, #2] + 14cd2: 441e add r6, r3 + area->y2 -= bottom; + 14cd4: 88e3 ldrh r3, [r4, #6] + area->y1 += top; + 14cd6: 8066 strh r6, [r4, #2] + area->y2 -= bottom; + 14cd8: 1a18 subs r0, r3, r0 + 14cda: 80e0 strh r0, [r4, #6] +} + 14cdc: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + 14ce0: 000022d5 .word 0x000022d5 + 14ce4: 00003711 .word 0x00003711 + +00014ce8 : +{ + 14ce8: b573 push {r0, r1, r4, r5, r6, lr} + LV_ASSERT_OBJ(label, LV_OBJX_NAME); + 14cea: 4b13 ldr r3, [pc, #76] ; (14d38 ) +{ + 14cec: 4604 mov r4, r0 + 14cee: 460d mov r5, r1 + LV_ASSERT_OBJ(label, LV_OBJX_NAME); + 14cf0: 4798 blx r3 + 14cf2: 4606 mov r6, r0 + 14cf4: b968 cbnz r0, 14d12 + 14cf6: 4b11 ldr r3, [pc, #68] ; (14d3c ) + 14cf8: 4911 ldr r1, [pc, #68] ; (14d40 ) + 14cfa: 9300 str r3, [sp, #0] + 14cfc: f44f 72c4 mov.w r2, #392 ; 0x188 + 14d00: 2003 movs r0, #3 + 14d02: 4d10 ldr r5, [pc, #64] ; (14d44 ) + 14d04: 47a8 blx r5 + 14d06: 4810 ldr r0, [pc, #64] ; (14d48 ) + 14d08: 4910 ldr r1, [pc, #64] ; (14d4c ) + 14d0a: 4622 mov r2, r4 + 14d0c: 4633 mov r3, r6 + 14d0e: 4788 blx r1 + 14d10: e7fe b.n 14d10 + lv_label_ext_t * ext = lv_obj_get_ext_attr(label); + 14d12: 4b0f ldr r3, [pc, #60] ; (14d50 ) + 14d14: 4620 mov r0, r4 + 14d16: 4798 blx r3 + if(ext->align == align) return; + 14d18: 7c03 ldrb r3, [r0, #16] + 14d1a: f3c3 1201 ubfx r2, r3, #4, #2 + 14d1e: 42aa cmp r2, r5 + 14d20: d008 beq.n 14d34 + ext->align = align; + 14d22: f365 1305 bfi r3, r5, #4, #2 + 14d26: 7403 strb r3, [r0, #16] + lv_obj_invalidate(label); /*Enough to invalidate because alignment is only drawing related + 14d28: 4b0a ldr r3, [pc, #40] ; (14d54 ) + 14d2a: 4620 mov r0, r4 +} + 14d2c: b002 add sp, #8 + 14d2e: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + lv_obj_invalidate(label); /*Enough to invalidate because alignment is only drawing related + 14d32: 4718 bx r3 +} + 14d34: b002 add sp, #8 + 14d36: bd70 pop {r4, r5, r6, pc} + 14d38: 000017e1 .word 0x000017e1 + 14d3c: 000244d0 .word 0x000244d0 + 14d40: 00024441 .word 0x00024441 + 14d44: 0000e8e9 .word 0x0000e8e9 + 14d48: 0001eebf .word 0x0001eebf + 14d4c: 000017e9 .word 0x000017e9 + 14d50: 00003fa9 .word 0x00003fa9 + 14d54: 00002785 .word 0x00002785 + +00014d58 : +{ + 14d58: b573 push {r0, r1, r4, r5, r6, lr} + LV_ASSERT_OBJ(label, LV_OBJX_NAME); + 14d5a: 4b0c ldr r3, [pc, #48] ; (14d8c ) +{ + 14d5c: 4604 mov r4, r0 + LV_ASSERT_OBJ(label, LV_OBJX_NAME); + 14d5e: 4798 blx r3 + 14d60: 4605 mov r5, r0 + 14d62: b968 cbnz r0, 14d80 + 14d64: 4b0a ldr r3, [pc, #40] ; (14d90 ) + 14d66: 490b ldr r1, [pc, #44] ; (14d94 ) + 14d68: 9300 str r3, [sp, #0] + 14d6a: f44f 72f2 mov.w r2, #484 ; 0x1e4 + 14d6e: 2003 movs r0, #3 + 14d70: 4e09 ldr r6, [pc, #36] ; (14d98 ) + 14d72: 47b0 blx r6 + 14d74: 4809 ldr r0, [pc, #36] ; (14d9c ) + 14d76: 490a ldr r1, [pc, #40] ; (14da0 ) + 14d78: 4622 mov r2, r4 + 14d7a: 462b mov r3, r5 + 14d7c: 4788 blx r1 + 14d7e: e7fe b.n 14d7e + lv_label_ext_t * ext = lv_obj_get_ext_attr(label); + 14d80: 4b08 ldr r3, [pc, #32] ; (14da4 ) + 14d82: 4620 mov r0, r4 + 14d84: 4798 blx r3 +} + 14d86: 6800 ldr r0, [r0, #0] + 14d88: b002 add sp, #8 + 14d8a: bd70 pop {r4, r5, r6, pc} + 14d8c: 000017e1 .word 0x000017e1 + 14d90: 00024519 .word 0x00024519 + 14d94: 00024441 .word 0x00024441 + 14d98: 0000e8e9 .word 0x0000e8e9 + 14d9c: 0001eebf .word 0x0001eebf + 14da0: 000017e9 .word 0x000017e9 + 14da4: 00003fa9 .word 0x00003fa9 + +00014da8 : +{ + 14da8: b573 push {r0, r1, r4, r5, r6, lr} + LV_ASSERT_OBJ(label, LV_OBJX_NAME); + 14daa: 4b0d ldr r3, [pc, #52] ; (14de0 ) +{ + 14dac: 4604 mov r4, r0 + LV_ASSERT_OBJ(label, LV_OBJX_NAME); + 14dae: 4798 blx r3 + 14db0: 4605 mov r5, r0 + 14db2: b968 cbnz r0, 14dd0 + 14db4: 4b0b ldr r3, [pc, #44] ; (14de4 ) + 14db6: 490c ldr r1, [pc, #48] ; (14de8 ) + 14db8: 9300 str r3, [sp, #0] + 14dba: f44f 72f9 mov.w r2, #498 ; 0x1f2 + 14dbe: 2003 movs r0, #3 + 14dc0: 4e0a ldr r6, [pc, #40] ; (14dec ) + 14dc2: 47b0 blx r6 + 14dc4: 480a ldr r0, [pc, #40] ; (14df0 ) + 14dc6: 490b ldr r1, [pc, #44] ; (14df4 ) + 14dc8: 4622 mov r2, r4 + 14dca: 462b mov r3, r5 + 14dcc: 4788 blx r1 + 14dce: e7fe b.n 14dce + lv_label_ext_t * ext = lv_obj_get_ext_attr(label); + 14dd0: 4b09 ldr r3, [pc, #36] ; (14df8 ) + 14dd2: 4620 mov r0, r4 + 14dd4: 4798 blx r3 + return ext->long_mode; + 14dd6: 7c00 ldrb r0, [r0, #16] +} + 14dd8: f000 0007 and.w r0, r0, #7 + 14ddc: b002 add sp, #8 + 14dde: bd70 pop {r4, r5, r6, pc} + 14de0: 000017e1 .word 0x000017e1 + 14de4: 0002452b .word 0x0002452b + 14de8: 00024441 .word 0x00024441 + 14dec: 0000e8e9 .word 0x0000e8e9 + 14df0: 0001eebf .word 0x0001eebf + 14df4: 000017e9 .word 0x000017e9 + 14df8: 00003fa9 .word 0x00003fa9 + +00014dfc : +{ + 14dfc: b573 push {r0, r1, r4, r5, r6, lr} + LV_ASSERT_OBJ(label, LV_OBJX_NAME); + 14dfe: 4b0f ldr r3, [pc, #60] ; (14e3c ) +{ + 14e00: 4604 mov r4, r0 + LV_ASSERT_OBJ(label, LV_OBJX_NAME); + 14e02: 4798 blx r3 + 14e04: 4605 mov r5, r0 + 14e06: b968 cbnz r0, 14e24 + 14e08: 4b0d ldr r3, [pc, #52] ; (14e40 ) + 14e0a: 490e ldr r1, [pc, #56] ; (14e44 ) + 14e0c: 9300 str r3, [sp, #0] + 14e0e: f240 12ff movw r2, #511 ; 0x1ff + 14e12: 2003 movs r0, #3 + 14e14: 4e0c ldr r6, [pc, #48] ; (14e48 ) + 14e16: 47b0 blx r6 + 14e18: 480c ldr r0, [pc, #48] ; (14e4c ) + 14e1a: 490d ldr r1, [pc, #52] ; (14e50 ) + 14e1c: 4622 mov r2, r4 + 14e1e: 462b mov r3, r5 + 14e20: 4788 blx r1 + 14e22: e7fe b.n 14e22 + lv_label_ext_t * ext = lv_obj_get_ext_attr(label); + 14e24: 4b0b ldr r3, [pc, #44] ; (14e54 ) + 14e26: 4620 mov r0, r4 + 14e28: 4798 blx r3 + lv_label_align_t align = ext->align; + 14e2a: 7c00 ldrb r0, [r0, #16] + 14e2c: f3c0 1001 ubfx r0, r0, #4, #2 + align = LV_LABEL_ALIGN_LEFT; + 14e30: 2803 cmp r0, #3 +} + 14e32: bf08 it eq + 14e34: 2000 moveq r0, #0 + 14e36: b002 add sp, #8 + 14e38: bd70 pop {r4, r5, r6, pc} + 14e3a: bf00 nop + 14e3c: 000017e1 .word 0x000017e1 + 14e40: 00024542 .word 0x00024542 + 14e44: 00024441 .word 0x00024441 + 14e48: 0000e8e9 .word 0x0000e8e9 + 14e4c: 0001eebf .word 0x0001eebf + 14e50: 000017e9 .word 0x000017e9 + 14e54: 00003fa9 .word 0x00003fa9 + +00014e58 : +{ + 14e58: b573 push {r0, r1, r4, r5, r6, lr} + LV_ASSERT_OBJ(label, LV_OBJX_NAME); + 14e5a: 4b0d ldr r3, [pc, #52] ; (14e90 ) +{ + 14e5c: 4604 mov r4, r0 + LV_ASSERT_OBJ(label, LV_OBJX_NAME); + 14e5e: 4798 blx r3 + 14e60: 4605 mov r5, r0 + 14e62: b968 cbnz r0, 14e80 + 14e64: 4b0b ldr r3, [pc, #44] ; (14e94 ) + 14e66: 490c ldr r1, [pc, #48] ; (14e98 ) + 14e68: 9300 str r3, [sp, #0] + 14e6a: f240 221b movw r2, #539 ; 0x21b + 14e6e: 2003 movs r0, #3 + 14e70: 4e0a ldr r6, [pc, #40] ; (14e9c ) + 14e72: 47b0 blx r6 + 14e74: 480a ldr r0, [pc, #40] ; (14ea0 ) + 14e76: 490b ldr r1, [pc, #44] ; (14ea4 ) + 14e78: 4622 mov r2, r4 + 14e7a: 462b mov r3, r5 + 14e7c: 4788 blx r1 + 14e7e: e7fe b.n 14e7e + lv_label_ext_t * ext = lv_obj_get_ext_attr(label); + 14e80: 4b09 ldr r3, [pc, #36] ; (14ea8 ) + 14e82: 4620 mov r0, r4 + 14e84: 4798 blx r3 + return ext->recolor == 0 ? false : true; + 14e86: 7c00 ldrb r0, [r0, #16] +} + 14e88: f3c0 1080 ubfx r0, r0, #6, #1 + 14e8c: b002 add sp, #8 + 14e8e: bd70 pop {r4, r5, r6, pc} + 14e90: 000017e1 .word 0x000017e1 + 14e94: 00024555 .word 0x00024555 + 14e98: 00024441 .word 0x00024441 + 14e9c: 0000e8e9 .word 0x0000e8e9 + 14ea0: 0001eebf .word 0x0001eebf + 14ea4: 000017e9 .word 0x000017e9 + 14ea8: 00003fa9 .word 0x00003fa9 + +00014eac : +{ + 14eac: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 14eb0: ed2d 8b02 vpush {d8} + 14eb4: b08b sub sp, #44 ; 0x2c + LV_ASSERT_OBJ(label, LV_OBJX_NAME); + 14eb6: 4e93 ldr r6, [pc, #588] ; (15104 ) +{ + 14eb8: 9102 str r1, [sp, #8] + 14eba: 4604 mov r4, r0 + LV_ASSERT_OBJ(label, LV_OBJX_NAME); + 14ebc: 47b0 blx r6 + 14ebe: 4605 mov r5, r0 + 14ec0: b968 cbnz r0, 14ede + 14ec2: 4b91 ldr r3, [pc, #580] ; (15108 ) + 14ec4: 4991 ldr r1, [pc, #580] ; (1510c ) + 14ec6: 9300 str r3, [sp, #0] + 14ec8: f240 22a5 movw r2, #677 ; 0x2a5 + 14ecc: 2003 movs r0, #3 + 14ece: 4e90 ldr r6, [pc, #576] ; (15110 ) + 14ed0: 47b0 blx r6 + 14ed2: 4890 ldr r0, [pc, #576] ; (15114 ) + 14ed4: 4990 ldr r1, [pc, #576] ; (15118 ) + 14ed6: 4622 mov r2, r4 + 14ed8: 462b mov r3, r5 + 14eda: 4788 blx r1 + 14edc: e7fe b.n 14edc + LV_ASSERT_NULL(pos); + 14ede: 9802 ldr r0, [sp, #8] + 14ee0: 47b0 blx r6 + 14ee2: 4605 mov r5, r0 + 14ee4: b968 cbnz r0, 14f02 + 14ee6: 4b88 ldr r3, [pc, #544] ; (15108 ) + 14ee8: 4988 ldr r1, [pc, #544] ; (1510c ) + 14eea: 9300 str r3, [sp, #0] + 14eec: f240 22a6 movw r2, #678 ; 0x2a6 + 14ef0: 2003 movs r0, #3 + 14ef2: 4c87 ldr r4, [pc, #540] ; (15110 ) + 14ef4: 47a0 blx r4 + 14ef6: 9a02 ldr r2, [sp, #8] + 14ef8: 4886 ldr r0, [pc, #536] ; (15114 ) + 14efa: 4987 ldr r1, [pc, #540] ; (15118 ) + 14efc: 462b mov r3, r5 + 14efe: 4788 blx r1 + 14f00: e7fe b.n 14f00 + get_txt_coords(label, &txt_coords); + 14f02: a908 add r1, sp, #32 + 14f04: 4620 mov r0, r4 + 14f06: 4b85 ldr r3, [pc, #532] ; (1511c ) +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_LINE_SPACE, text_line_space, lv_style_int_t, _int, scalar) + 14f08: 4f85 ldr r7, [pc, #532] ; (15120 ) + 14f0a: 4798 blx r3 + const char * txt = lv_label_get_text(label); + 14f0c: 4b85 ldr r3, [pc, #532] ; (15124 ) + 14f0e: 4620 mov r0, r4 + 14f10: 4798 blx r3 + lv_label_ext_t * ext = lv_obj_get_ext_attr(label); + 14f12: 4b85 ldr r3, [pc, #532] ; (15128 ) + const char * txt = lv_label_get_text(label); + 14f14: 4680 mov r8, r0 + lv_label_ext_t * ext = lv_obj_get_ext_attr(label); + 14f16: 4620 mov r0, r4 + 14f18: 4798 blx r3 + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + 14f1a: f8bd 3024 ldrh.w r3, [sp, #36] ; 0x24 + 14f1e: f8bd 2020 ldrh.w r2, [sp, #32] + 14f22: 3301 adds r3, #1 + 14f24: 1a9b subs r3, r3, r2 + 14f26: b21b sxth r3, r3 + 14f28: 4606 mov r6, r0 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_FONT, text_font, const lv_font_t *, _ptr, scalar) + 14f2a: f248 028e movw r2, #32910 ; 0x808e + 14f2e: 2100 movs r1, #0 + 14f30: 4620 mov r0, r4 + 14f32: ee08 3a90 vmov s17, r3 + 14f36: 4b7d ldr r3, [pc, #500] ; (1512c ) + 14f38: 4798 blx r3 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_LINE_SPACE, text_line_space, lv_style_int_t, _int, scalar) + 14f3a: f248 0281 movw r2, #32897 ; 0x8081 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_FONT, text_font, const lv_font_t *, _ptr, scalar) + 14f3e: 4682 mov sl, r0 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_LINE_SPACE, text_line_space, lv_style_int_t, _int, scalar) + 14f40: 2100 movs r1, #0 + 14f42: 4620 mov r0, r4 + 14f44: 47b8 blx r7 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_LETTER_SPACE, text_letter_space, lv_style_int_t, _int, scalar) + 14f46: f248 0280 movw r2, #32896 ; 0x8080 + 14f4a: 2100 movs r1, #0 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_LINE_SPACE, text_line_space, lv_style_int_t, _int, scalar) + 14f4c: 4605 mov r5, r0 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_LETTER_SPACE, text_letter_space, lv_style_int_t, _int, scalar) + 14f4e: 4620 mov r0, r4 + 14f50: 47b8 blx r7 + * @param font_p pointer to a font + * @return the height of a font + */ +static inline lv_coord_t lv_font_get_line_height(const lv_font_t * font_p) +{ + return font_p->line_height; + 14f52: f9ba 3008 ldrsh.w r3, [sl, #8] + 14f56: 9303 str r3, [sp, #12] + if(ext->recolor != 0) flag |= LV_TXT_FLAG_RECOLOR; + 14f58: 7c33 ldrb r3, [r6, #16] + lv_txt_flag_t flag = LV_TXT_FLAG_NONE; + 14f5a: f3c3 1680 ubfx r6, r3, #6, #1 + if(ext->expand != 0) flag |= LV_TXT_FLAG_EXPAND; + 14f5e: 061a lsls r2, r3, #24 + 14f60: bf48 it mi + 14f62: f046 0602 orrmi.w r6, r6, #2 + 14f66: ee08 0a10 vmov s16, r0 + if(ext->long_mode == LV_LABEL_LONG_EXPAND) flag |= LV_TXT_FLAG_FIT; + 14f6a: 075b lsls r3, r3, #29 + lv_label_align_t align = lv_label_get_align(label); + 14f6c: 4620 mov r0, r4 + 14f6e: 4b70 ldr r3, [pc, #448] ; (15130 ) + if(ext->long_mode == LV_LABEL_LONG_EXPAND) flag |= LV_TXT_FLAG_FIT; + 14f70: bf08 it eq + 14f72: f046 0610 orreq.w r6, r6, #16 + lv_label_align_t align = lv_label_get_align(label); + 14f76: 4798 blx r3 + if(align == LV_LABEL_ALIGN_CENTER) flag |= LV_TXT_FLAG_CENTER; + 14f78: 2801 cmp r0, #1 + lv_label_align_t align = lv_label_get_align(label); + 14f7a: 4604 mov r4, r0 + if(align == LV_LABEL_ALIGN_CENTER) flag |= LV_TXT_FLAG_CENTER; + 14f7c: d108 bne.n 14f90 + 14f7e: f046 0604 orr.w r6, r6, #4 + y += letter_height + line_space; + 14f82: 9b03 ldr r3, [sp, #12] + new_line_start += _lv_txt_get_next_line(&txt[line_start], font, letter_space, max_w, flag); + 14f84: f04f 0b00 mov.w fp, #0 + y += letter_height + line_space; + 14f88: 442b add r3, r5 + new_line_start += _lv_txt_get_next_line(&txt[line_start], font, letter_space, max_w, flag); + 14f8a: 465f mov r7, fp + y += letter_height + line_space; + 14f8c: 9304 str r3, [sp, #16] + 14f8e: e059 b.n 15044 + if(align == LV_LABEL_ALIGN_RIGHT) flag |= LV_TXT_FLAG_RIGHT; + 14f90: 2802 cmp r0, #2 + 14f92: d1f6 bne.n 14f82 + 14f94: f046 0608 orr.w r6, r6, #8 + 14f98: e7f3 b.n 14f82 + new_line_start += _lv_txt_get_next_line(&txt[line_start], font, letter_space, max_w, flag); + 14f9a: ee18 3a90 vmov r3, s17 + 14f9e: ee18 2a10 vmov r2, s16 + 14fa2: 4d64 ldr r5, [pc, #400] ; (15134 ) + 14fa4: 9600 str r6, [sp, #0] + 14fa6: 4651 mov r1, sl + 14fa8: 4648 mov r0, r9 + 14faa: 47a8 blx r5 + if(pos->y <= y + letter_height) { + 14fac: 9b02 ldr r3, [sp, #8] + 14fae: f9b3 2002 ldrsh.w r2, [r3, #2] + 14fb2: 9b03 ldr r3, [sp, #12] + 14fb4: 445b add r3, fp + 14fb6: 429a cmp r2, r3 + new_line_start += _lv_txt_get_next_line(&txt[line_start], font, letter_space, max_w, flag); + 14fb8: eb00 0507 add.w r5, r0, r7 + if(pos->y <= y + letter_height) { + 14fbc: dc3d bgt.n 1503a + letter = _lv_txt_encoded_prev(txt, &tmp); + 14fbe: 4b5e ldr r3, [pc, #376] ; (15138 ) + uint32_t tmp = new_line_start; + 14fc0: 9507 str r5, [sp, #28] + letter = _lv_txt_encoded_prev(txt, &tmp); + 14fc2: 681b ldr r3, [r3, #0] + 14fc4: a907 add r1, sp, #28 + 14fc6: 4640 mov r0, r8 + 14fc8: 4798 blx r3 + if(letter != '\n' && txt[new_line_start] == '\0') new_line_start++; + 14fca: 280a cmp r0, #10 + 14fcc: d003 beq.n 14fd6 + 14fce: f818 3005 ldrb.w r3, [r8, r5] + 14fd2: b903 cbnz r3, 14fd6 + 14fd4: 3501 adds r5, #1 + if(align == LV_LABEL_ALIGN_CENTER) { + 14fd6: 2c01 cmp r4, #1 + 14fd8: d13c bne.n 15054 + line_w = _lv_txt_get_width(bidi_txt, new_line_start - line_start, font, letter_space, flag); + 14fda: 1be9 subs r1, r5, r7 + 14fdc: ee18 3a10 vmov r3, s16 + 14fe0: 4c56 ldr r4, [pc, #344] ; (1513c ) + 14fe2: 9600 str r6, [sp, #0] + 14fe4: 4652 mov r2, sl + 14fe6: b289 uxth r1, r1 + 14fe8: 4648 mov r0, r9 + 14fea: 47a0 blx r4 + 14fec: f8bd 3024 ldrh.w r3, [sp, #36] ; 0x24 + 14ff0: f8bd 2020 ldrh.w r2, [sp, #32] + 14ff4: 3301 adds r3, #1 + 14ff6: 1a9b subs r3, r3, r2 + x += lv_area_get_width(&txt_coords) / 2 - line_w / 2; + 14ff8: f3c3 32c0 ubfx r2, r3, #15, #1 + 14ffc: eb00 74d0 add.w r4, r0, r0, lsr #31 + 15000: fa02 f383 sxtah r3, r2, r3 + 15004: 1064 asrs r4, r4, #1 + 15006: ebc4 0463 rsb r4, r4, r3, asr #1 + x += lv_area_get_width(&txt_coords) - line_w; + 1500a: b224 sxth r4, r4 + lv_txt_cmd_state_t cmd_state = LV_TXT_CMD_STATE_WAIT; + 1500c: 2300 movs r3, #0 + 1500e: f88d 301b strb.w r3, [sp, #27] + uint32_t i = 0; + 15012: 9307 str r3, [sp, #28] + if(new_line_start > 0) { + 15014: 2d00 cmp r5, #0 + 15016: d16d bne.n 150f4 + logical_pos = _lv_txt_encoded_get_char_id(bidi_txt, i); + 15018: 4d49 ldr r5, [pc, #292] ; (15140 ) + 1501a: 9907 ldr r1, [sp, #28] + 1501c: 682b ldr r3, [r5, #0] + 1501e: 4648 mov r0, r9 + 15020: 4798 blx r3 + return logical_pos + _lv_txt_encoded_get_char_id(txt, line_start); + 15022: 682b ldr r3, [r5, #0] + logical_pos = _lv_txt_encoded_get_char_id(bidi_txt, i); + 15024: 4604 mov r4, r0 + return logical_pos + _lv_txt_encoded_get_char_id(txt, line_start); + 15026: 4639 mov r1, r7 + 15028: 4640 mov r0, r8 + 1502a: 4798 blx r3 + 1502c: 4420 add r0, r4 +} + 1502e: b280 uxth r0, r0 + 15030: b00b add sp, #44 ; 0x2c + 15032: ecbd 8b02 vpop {d8} + 15036: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + y += letter_height + line_space; + 1503a: 9b04 ldr r3, [sp, #16] + 1503c: 449b add fp, r3 + 1503e: fa0f fb8b sxth.w fp, fp + new_line_start += _lv_txt_get_next_line(&txt[line_start], font, letter_space, max_w, flag); + 15042: 462f mov r7, r5 + while(txt[line_start] != '\0') { + 15044: f818 3007 ldrb.w r3, [r8, r7] + 15048: eb08 0907 add.w r9, r8, r7 + 1504c: 2b00 cmp r3, #0 + 1504e: d1a4 bne.n 14f9a + 15050: 463d mov r5, r7 + 15052: e7c0 b.n 14fd6 + else if(align == LV_LABEL_ALIGN_RIGHT) { + 15054: 2c02 cmp r4, #2 + 15056: d110 bne.n 1507a + line_w = _lv_txt_get_width(bidi_txt, new_line_start - line_start, font, letter_space, flag); + 15058: 1be9 subs r1, r5, r7 + 1505a: ee18 3a10 vmov r3, s16 + 1505e: 4c37 ldr r4, [pc, #220] ; (1513c ) + 15060: 9600 str r6, [sp, #0] + 15062: 4652 mov r2, sl + 15064: b289 uxth r1, r1 + 15066: 4648 mov r0, r9 + 15068: 47a0 blx r4 + 1506a: f8bd 4024 ldrh.w r4, [sp, #36] ; 0x24 + 1506e: f8bd 3020 ldrh.w r3, [sp, #32] + 15072: 3401 adds r4, #1 + 15074: 1ae4 subs r4, r4, r3 + x += lv_area_get_width(&txt_coords) - line_w; + 15076: 1a24 subs r4, r4, r0 + 15078: e7c7 b.n 1500a + lv_coord_t x = 0; + 1507a: 2400 movs r4, #0 + 1507c: e7c6 b.n 1500c + if(_lv_txt_is_cmd(&cmd_state, bidi_txt[i]) != false) { + 1507e: 9b07 ldr r3, [sp, #28] + 15080: 9005 str r0, [sp, #20] + 15082: f819 1003 ldrb.w r1, [r9, r3] + 15086: 4b2f ldr r3, [pc, #188] ; (15144 ) + 15088: f10d 001b add.w r0, sp, #27 + 1508c: 4798 blx r3 + 1508e: 9a05 ldr r2, [sp, #20] + 15090: b198 cbz r0, 150ba + while(i + line_start < new_line_start) { + 15092: 9b07 ldr r3, [sp, #28] + 15094: 443b add r3, r7 + 15096: 429d cmp r5, r3 + 15098: d9be bls.n 15018 + uint32_t letter = _lv_txt_encoded_next(bidi_txt, &i); + 1509a: f8db 3000 ldr.w r3, [fp] + 1509e: a907 add r1, sp, #28 + 150a0: 4648 mov r0, r9 + 150a2: 4798 blx r3 + 150a4: 4606 mov r6, r0 + uint32_t letter_next = _lv_txt_encoded_next(&bidi_txt[i], NULL); + 150a6: 9807 ldr r0, [sp, #28] + 150a8: f8db 3000 ldr.w r3, [fp] + 150ac: 2100 movs r1, #0 + 150ae: 4448 add r0, r9 + 150b0: 4798 blx r3 + if((flag & LV_TXT_FLAG_RECOLOR) != 0) { + 150b2: 9b04 ldr r3, [sp, #16] + uint32_t letter_next = _lv_txt_encoded_next(&bidi_txt[i], NULL); + 150b4: 4602 mov r2, r0 + if((flag & LV_TXT_FLAG_RECOLOR) != 0) { + 150b6: 2b00 cmp r3, #0 + 150b8: d1e1 bne.n 1507e + x += lv_font_get_glyph_width(font, letter, letter_next); + 150ba: 4b23 ldr r3, [pc, #140] ; (15148 ) + 150bc: 4631 mov r1, r6 + 150be: 4650 mov r0, sl + 150c0: 4798 blx r3 + if(pos->x < x || i + line_start == new_line_start || txt[i + line_start] == '\0') { + 150c2: 9b02 ldr r3, [sp, #8] + x += lv_font_get_glyph_width(font, letter, letter_next); + 150c4: 4420 add r0, r4 + if(pos->x < x || i + line_start == new_line_start || txt[i + line_start] == '\0') { + 150c6: f9b3 3000 ldrsh.w r3, [r3] + x += lv_font_get_glyph_width(font, letter, letter_next); + 150ca: b284 uxth r4, r0 + if(pos->x < x || i + line_start == new_line_start || txt[i + line_start] == '\0') { + 150cc: b200 sxth r0, r0 + 150ce: 4283 cmp r3, r0 + 150d0: da02 bge.n 150d8 + i = i_act; + 150d2: 9b03 ldr r3, [sp, #12] + 150d4: 9307 str r3, [sp, #28] + break; + 150d6: e79f b.n 15018 + if(pos->x < x || i + line_start == new_line_start || txt[i + line_start] == '\0') { + 150d8: 9b07 ldr r3, [sp, #28] + 150da: 18fa adds r2, r7, r3 + 150dc: 4295 cmp r5, r2 + 150de: d0f8 beq.n 150d2 + 150e0: f818 2002 ldrb.w r2, [r8, r2] + 150e4: 2a00 cmp r2, #0 + 150e6: d0f4 beq.n 150d2 + x += letter_space; + 150e8: ee18 2a10 vmov r2, s16 + 150ec: 4414 add r4, r2 + 150ee: b224 sxth r4, r4 + i_act = i; + 150f0: 9303 str r3, [sp, #12] + 150f2: e7ce b.n 15092 + uint32_t i_act = i; + 150f4: 9303 str r3, [sp, #12] + if((flag & LV_TXT_FLAG_RECOLOR) != 0) { + 150f6: f006 0301 and.w r3, r6, #1 + uint32_t letter = _lv_txt_encoded_next(bidi_txt, &i); + 150fa: f8df b050 ldr.w fp, [pc, #80] ; 1514c + if((flag & LV_TXT_FLAG_RECOLOR) != 0) { + 150fe: 9304 str r3, [sp, #16] + 15100: e7c7 b.n 15092 + 15102: bf00 nop + 15104: 000017e1 .word 0x000017e1 + 15108: 0002459a .word 0x0002459a + 1510c: 00024441 .word 0x00024441 + 15110: 0000e8e9 .word 0x0000e8e9 + 15114: 0001eebf .word 0x0001eebf + 15118: 000017e9 .word 0x000017e9 + 1511c: 00014c8d .word 0x00014c8d + 15120: 00003711 .word 0x00003711 + 15124: 00014d59 .word 0x00014d59 + 15128: 00003fa9 .word 0x00003fa9 + 1512c: 000038c9 .word 0x000038c9 + 15130: 00014dfd .word 0x00014dfd + 15134: 0000ffc5 .word 0x0000ffc5 + 15138: 20000068 .word 0x20000068 + 1513c: 0000ff1d .word 0x0000ff1d + 15140: 20000064 .word 0x20000064 + 15144: 0000fee5 .word 0x0000fee5 + 15148: 0000d175 .word 0x0000d175 + 1514c: 20000058 .word 0x20000058 + +00015150 : +{ + 15150: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + lv_label_ext_t * ext = lv_obj_get_ext_attr(label); + 15154: 4b8d ldr r3, [pc, #564] ; (1538c ) +{ + 15156: b09b sub sp, #108 ; 0x6c + 15158: 4604 mov r4, r0 + lv_label_ext_t * ext = lv_obj_get_ext_attr(label); + 1515a: 4798 blx r3 + if(ext->text == NULL) return; + 1515c: 6803 ldr r3, [r0, #0] + lv_label_ext_t * ext = lv_obj_get_ext_attr(label); + 1515e: 4605 mov r5, r0 + if(ext->text == NULL) return; + 15160: 2b00 cmp r3, #0 + 15162: d062 beq.n 1522a + get_txt_coords(label, &txt_coords); + 15164: 4b8a ldr r3, [pc, #552] ; (15390 ) +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_LINE_SPACE, text_line_space, lv_style_int_t, _int, scalar) + 15166: f8df 8258 ldr.w r8, [pc, #600] ; 153c0 + 1516a: a908 add r1, sp, #32 + 1516c: 4620 mov r0, r4 + 1516e: 4798 blx r3 + 15170: f8bd a024 ldrh.w sl, [sp, #36] ; 0x24 + 15174: f8bd 3020 ldrh.w r3, [sp, #32] + 15178: f10a 0a01 add.w sl, sl, #1 + 1517c: ebaa 0a03 sub.w sl, sl, r3 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_FONT, text_font, const lv_font_t *, _ptr, scalar) + 15180: f248 028e movw r2, #32910 ; 0x808e + 15184: 4b83 ldr r3, [pc, #524] ; (15394 ) + 15186: 2100 movs r1, #0 + 15188: 4620 mov r0, r4 + 1518a: 4798 blx r3 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_LINE_SPACE, text_line_space, lv_style_int_t, _int, scalar) + 1518c: f248 0281 movw r2, #32897 ; 0x8081 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_FONT, text_font, const lv_font_t *, _ptr, scalar) + 15190: 4606 mov r6, r0 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_LINE_SPACE, text_line_space, lv_style_int_t, _int, scalar) + 15192: 2100 movs r1, #0 + 15194: 4620 mov r0, r4 + 15196: 47c0 blx r8 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_LETTER_SPACE, text_letter_space, lv_style_int_t, _int, scalar) + 15198: 2100 movs r1, #0 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_LINE_SPACE, text_line_space, lv_style_int_t, _int, scalar) + 1519a: 4607 mov r7, r0 +_LV_OBJ_STYLE_SET_GET_DECLARE(TEXT_LETTER_SPACE, text_letter_space, lv_style_int_t, _int, scalar) + 1519c: f248 0280 movw r2, #32896 ; 0x8080 + 151a0: 4620 mov r0, r4 + 151a2: 47c0 blx r8 + if(ext->recolor != 0) flag |= LV_TXT_FLAG_RECOLOR; + 151a4: 7c2a ldrb r2, [r5, #16] + _lv_txt_get_size(&size, ext->text, font, letter_space, line_space, max_w, flag); + 151a6: 9700 str r7, [sp, #0] + lv_txt_flag_t flag = LV_TXT_FLAG_NONE; + 151a8: f3c2 1380 ubfx r3, r2, #6, #1 + if(ext->expand != 0) flag |= LV_TXT_FLAG_EXPAND; + 151ac: 0611 lsls r1, r2, #24 + 151ae: bf48 it mi + 151b0: f043 0302 orrmi.w r3, r3, #2 + if(ext->long_mode == LV_LABEL_LONG_EXPAND) flag |= LV_TXT_FLAG_FIT; + 151b4: 0752 lsls r2, r2, #29 + 151b6: bf08 it eq + 151b8: f043 0310 orreq.w r3, r3, #16 + 151bc: fa0f fa8a sxth.w sl, sl + _lv_txt_get_size(&size, ext->text, font, letter_space, line_space, max_w, flag); + 151c0: e9cd a301 strd sl, r3, [sp, #4] + 151c4: 4681 mov r9, r0 + 151c6: 6829 ldr r1, [r5, #0] + 151c8: f8df a1f8 ldr.w sl, [pc, #504] ; 153c4 + 151cc: 4603 mov r3, r0 + 151ce: 4632 mov r2, r6 + 151d0: a806 add r0, sp, #24 + 151d2: 47d0 blx sl + if(ext->long_mode == LV_LABEL_LONG_EXPAND) { + 151d4: 7c29 ldrb r1, [r5, #16] + 151d6: f011 0107 ands.w r1, r1, #7 + 151da: d129 bne.n 15230 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_LEFT, pad_left, lv_style_int_t, _int, scalar) + 151dc: 2212 movs r2, #18 + 151de: 4620 mov r0, r4 + 151e0: 9105 str r1, [sp, #20] + 151e2: 47c0 blx r8 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_RIGHT, pad_right, lv_style_int_t, _int, scalar) + 151e4: 9905 ldr r1, [sp, #20] +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_LEFT, pad_left, lv_style_int_t, _int, scalar) + 151e6: 4605 mov r5, r0 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_RIGHT, pad_right, lv_style_int_t, _int, scalar) + 151e8: 2213 movs r2, #19 + 151ea: 4620 mov r0, r4 + 151ec: 47c0 blx r8 + size.x += lv_obj_get_style_pad_left(label, LV_LABEL_PART_MAIN) + lv_obj_get_style_pad_right(label, LV_LABEL_PART_MAIN); + 151ee: f8bd 3018 ldrh.w r3, [sp, #24] +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_TOP, pad_top, lv_style_int_t, _int, scalar) + 151f2: 9905 ldr r1, [sp, #20] + 151f4: 4428 add r0, r5 + 151f6: 4418 add r0, r3 + 151f8: f8ad 0018 strh.w r0, [sp, #24] + 151fc: 2210 movs r2, #16 + 151fe: 4620 mov r0, r4 + 15200: 47c0 blx r8 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_BOTTOM, pad_bottom, lv_style_int_t, _int, scalar) + 15202: 9905 ldr r1, [sp, #20] +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_TOP, pad_top, lv_style_int_t, _int, scalar) + 15204: 4605 mov r5, r0 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_BOTTOM, pad_bottom, lv_style_int_t, _int, scalar) + 15206: 2211 movs r2, #17 + 15208: 4620 mov r0, r4 + 1520a: 47c0 blx r8 + size.y += lv_obj_get_style_pad_top(label, LV_LABEL_PART_MAIN) + lv_obj_get_style_pad_bottom(label, LV_LABEL_PART_MAIN); + 1520c: f8bd 301a ldrh.w r3, [sp, #26] + lv_obj_set_size(label, size.x, size.y); + 15210: f9bd 1018 ldrsh.w r1, [sp, #24] + size.y += lv_obj_get_style_pad_top(label, LV_LABEL_PART_MAIN) + lv_obj_get_style_pad_bottom(label, LV_LABEL_PART_MAIN); + 15214: 182a adds r2, r5, r0 + 15216: 441a add r2, r3 + 15218: b212 sxth r2, r2 + lv_obj_set_size(label, size.x, size.y); + 1521a: 4b5f ldr r3, [pc, #380] ; (15398 ) + size.y += lv_obj_get_style_pad_top(label, LV_LABEL_PART_MAIN) + lv_obj_get_style_pad_bottom(label, LV_LABEL_PART_MAIN); + 1521c: f8ad 201a strh.w r2, [sp, #26] + lv_obj_set_size(label, size.x, size.y); + 15220: 4620 mov r0, r4 + 15222: 4798 blx r3 + lv_obj_invalidate(label); + 15224: 4b5d ldr r3, [pc, #372] ; (1539c ) + 15226: 4620 mov r0, r4 + 15228: 4798 blx r3 +} + 1522a: b01b add sp, #108 ; 0x6c + 1522c: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + else if(ext->long_mode == LV_LABEL_LONG_SROLL) { + 15230: 3901 subs r1, #1 + 15232: 2903 cmp r1, #3 + 15234: d8f6 bhi.n 15224 + 15236: e8df f011 tbh [pc, r1, lsl #1] + 1523a: 01c8 .short 0x01c8 + 1523c: 0004013c .word 0x0004013c + 15240: 00c7 .short 0x00c7 + lv_anim_init(&a); + 15242: 4b57 ldr r3, [pc, #348] ; (153a0 ) + 15244: a80a add r0, sp, #40 ; 0x28 + 15246: 4798 blx r3 + lv_anim_set_playback_delay(&a, (((lv_font_get_glyph_width(font, ' ', ' ') + letter_space) * 1000) / + 15248: 2220 movs r2, #32 + * @param a pointer to an initialized `lv_anim_t` variable + * @param cnt repeat count or `LV_ANIM_REPEAT_INFINITE` for infinite repetition. 0: to disable repetition. + */ +static inline void lv_anim_set_repeat_count(lv_anim_t * a, uint16_t cnt) +{ + a->repeat_cnt = cnt; + 1524a: f64f 73ff movw r3, #65535 ; 0xffff + 1524e: 4611 mov r1, r2 + 15250: f8ad 305c strh.w r3, [sp, #92] ; 0x5c + a->var = var; + 15254: 940a str r4, [sp, #40] ; 0x28 + 15256: 4b53 ldr r3, [pc, #332] ; (153a4 ) + 15258: 4630 mov r0, r6 + 1525a: 4798 blx r3 + 1525c: f44f 727a mov.w r2, #1000 ; 0x3e8 + 15260: eb00 0309 add.w r3, r0, r9 + ext->anim_speed) * + 15264: 896f ldrh r7, [r5, #10] + if(size.x > lv_area_get_width(&txt_coords)) { + 15266: f9bd 1018 ldrsh.w r1, [sp, #24] + lv_anim_set_playback_delay(&a, (((lv_font_get_glyph_width(font, ' ', ' ') + letter_space) * 1000) / + 1526a: 4353 muls r3, r2 + 1526c: fb93 f3f7 sdiv r3, r3, r7 + 15270: eb03 0343 add.w r3, r3, r3, lsl #1 + a->playback_delay = delay; + 15274: b29b uxth r3, r3 + 15276: 9314 str r3, [sp, #80] ; 0x50 + * @param a pointer to an initialized `lv_anim_t` variable + * @param delay delay in milliseconds before repeating the animation. + */ +static inline void lv_anim_set_repeat_delay(lv_anim_t * a, uint16_t delay) +{ + a->repeat_delay = delay; + 15278: 9316 str r3, [sp, #88] ; 0x58 + 1527a: f8bd 3024 ldrh.w r3, [sp, #36] ; 0x24 + 1527e: f8bd 2020 ldrh.w r2, [sp, #32] + 15282: 3301 adds r3, #1 + 15284: 1a9b subs r3, r3, r2 + 15286: b29a uxth r2, r3 + if(size.x > lv_area_get_width(&txt_coords)) { + 15288: b21b sxth r3, r3 + 1528a: 4299 cmp r1, r3 + 1528c: dd74 ble.n 15378 + lv_anim_set_values(&a, 0, lv_area_get_width(&txt_coords) - size.x); + 1528e: 1a52 subs r2, r2, r1 + a->exec_cb = exec_cb; + 15290: f8df 8124 ldr.w r8, [pc, #292] ; 153b8 + lv_anim_set_time(&a, lv_anim_speed_to_time(ext->anim_speed, a.start, a.end)); + 15294: 4b44 ldr r3, [pc, #272] ; (153a8 ) + 15296: f8cd 802c str.w r8, [sp, #44] ; 0x2c + a->start = start; + 1529a: 2100 movs r1, #0 + lv_anim_set_values(&a, 0, lv_area_get_width(&txt_coords) - size.x); + 1529c: b212 sxth r2, r2 + a->end = end; + 1529e: e9cd 1210 strd r1, r2, [sp, #64] ; 0x40 + lv_anim_set_time(&a, lv_anim_speed_to_time(ext->anim_speed, a.start, a.end)); + 152a2: 4638 mov r0, r7 + 152a4: 4798 blx r3 + lv_anim_t * anim_cur = lv_anim_get(label, (lv_anim_exec_xcb_t)lv_label_set_offset_x); + 152a6: 4b41 ldr r3, [pc, #260] ; (153ac ) + a->time = duration; + 152a8: 9012 str r0, [sp, #72] ; 0x48 + lv_anim_set_time(&a, lv_anim_speed_to_time(ext->anim_speed, a.start, a.end)); + 152aa: 9015 str r0, [sp, #84] ; 0x54 + lv_anim_t * anim_cur = lv_anim_get(label, (lv_anim_exec_xcb_t)lv_label_set_offset_x); + 152ac: 4641 mov r1, r8 + 152ae: 4620 mov r0, r4 + 152b0: 4798 blx r3 + if(anim_cur) { + 152b2: 2800 cmp r0, #0 + 152b4: d05e beq.n 15374 + act_time = anim_cur->act_time; + 152b6: 6a43 ldr r3, [r0, #36] ; 0x24 + playback_now = anim_cur->playback_now; + 152b8: f890 003c ldrb.w r0, [r0, #60] ; 0x3c + 152bc: f000 0001 and.w r0, r0, #1 + if(act_time < a.time) { + 152c0: 9a12 ldr r2, [sp, #72] ; 0x48 + 152c2: 429a cmp r2, r3 + 152c4: dd11 ble.n 152ea + a.act_time = act_time; /*To keep the old position*/ + 152c6: 9313 str r3, [sp, #76] ; 0x4c + a.early_apply = 0; + 152c8: f89d 305e ldrb.w r3, [sp, #94] ; 0x5e + 152cc: f36f 0300 bfc r3, #0, #1 + 152d0: f88d 305e strb.w r3, [sp, #94] ; 0x5e + if(playback_now) { + 152d4: b148 cbz r0, 152ea + a.playback_now = 1; + 152d6: f89d 3064 ldrb.w r3, [sp, #100] ; 0x64 + 152da: f043 0301 orr.w r3, r3, #1 + 152de: f88d 3064 strb.w r3, [sp, #100] ; 0x64 + a.start = a.end; + 152e2: e9dd 3210 ldrd r3, r2, [sp, #64] ; 0x40 + a.end = tmp; + 152e6: e9cd 2310 strd r2, r3, [sp, #64] ; 0x40 + lv_anim_start(&a); + 152ea: 4b31 ldr r3, [pc, #196] ; (153b0 ) + 152ec: a80a add r0, sp, #40 ; 0x28 + 152ee: 4798 blx r3 + hor_anim = true; + 152f0: 2701 movs r7, #1 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + 152f2: f8bd 3026 ldrh.w r3, [sp, #38] ; 0x26 + 152f6: f8bd 2022 ldrh.w r2, [sp, #34] ; 0x22 + if(size.y > lv_area_get_height(&txt_coords) && hor_anim == false) { + 152fa: f9bd 101a ldrsh.w r1, [sp, #26] + 152fe: 3301 adds r3, #1 + 15300: 1a9b subs r3, r3, r2 + 15302: b29a uxth r2, r3 + 15304: b21b sxth r3, r3 + 15306: 4299 cmp r1, r3 + 15308: f340 80cc ble.w 154a4 + 1530c: 2f00 cmp r7, #0 + 1530e: f040 80c9 bne.w 154a4 + lv_anim_set_values(&a, 0, lv_area_get_height(&txt_coords) - size.y - (lv_font_get_line_height(font))); + 15312: 8933 ldrh r3, [r6, #8] + a->exec_cb = exec_cb; + 15314: 4e27 ldr r6, [pc, #156] ; (153b4 ) + lv_anim_set_time(&a, lv_anim_speed_to_time(ext->anim_speed, a.start, a.end)); + 15316: 8968 ldrh r0, [r5, #10] + 15318: 960b str r6, [sp, #44] ; 0x2c + lv_anim_set_values(&a, 0, lv_area_get_height(&txt_coords) - size.y - (lv_font_get_line_height(font))); + 1531a: 1a52 subs r2, r2, r1 + 1531c: 1ad2 subs r2, r2, r3 + 1531e: b212 sxth r2, r2 + lv_anim_set_time(&a, lv_anim_speed_to_time(ext->anim_speed, a.start, a.end)); + 15320: 4b21 ldr r3, [pc, #132] ; (153a8 ) + 15322: 4639 mov r1, r7 + a->end = end; + 15324: e9cd 7210 strd r7, r2, [sp, #64] ; 0x40 + 15328: 4798 blx r3 + lv_anim_t * anim_cur = lv_anim_get(label, (lv_anim_exec_xcb_t)lv_label_set_offset_y); + 1532a: 4b20 ldr r3, [pc, #128] ; (153ac ) + a->time = duration; + 1532c: 9012 str r0, [sp, #72] ; 0x48 + lv_anim_set_time(&a, lv_anim_speed_to_time(ext->anim_speed, a.start, a.end)); + 1532e: 9015 str r0, [sp, #84] ; 0x54 + lv_anim_t * anim_cur = lv_anim_get(label, (lv_anim_exec_xcb_t)lv_label_set_offset_y); + 15330: 4631 mov r1, r6 + 15332: 4620 mov r0, r4 + 15334: 4798 blx r3 + if(anim_cur) { + 15336: b330 cbz r0, 15386 + playback_now = anim_cur->playback_now; + 15338: f890 703c ldrb.w r7, [r0, #60] ; 0x3c + act_time = anim_cur->act_time; + 1533c: 6a43 ldr r3, [r0, #36] ; 0x24 + playback_now = anim_cur->playback_now; + 1533e: f007 0701 and.w r7, r7, #1 + if(act_time < a.time) { + 15342: 9a12 ldr r2, [sp, #72] ; 0x48 + 15344: 429a cmp r2, r3 + 15346: dd11 ble.n 1536c + a.act_time = act_time; /*To keep the old position*/ + 15348: 9313 str r3, [sp, #76] ; 0x4c + a.early_apply = 0; + 1534a: f89d 305e ldrb.w r3, [sp, #94] ; 0x5e + 1534e: f36f 0300 bfc r3, #0, #1 + 15352: f88d 305e strb.w r3, [sp, #94] ; 0x5e + if(playback_now) { + 15356: b14f cbz r7, 1536c + a.playback_now = 1; + 15358: f89d 3064 ldrb.w r3, [sp, #100] ; 0x64 + 1535c: f043 0301 orr.w r3, r3, #1 + 15360: f88d 3064 strb.w r3, [sp, #100] ; 0x64 + a.start = a.end; + 15364: e9dd 3210 ldrd r3, r2, [sp, #64] ; 0x40 + a.end = tmp; + 15368: e9cd 2310 strd r2, r3, [sp, #64] ; 0x40 + lv_anim_start(&a); + 1536c: 4b10 ldr r3, [pc, #64] ; (153b0 ) + 1536e: a80a add r0, sp, #40 ; 0x28 + 15370: 4798 blx r3 + if(size.y > lv_area_get_height(&txt_coords) && hor_anim == false) { + 15372: e757 b.n 15224 + int32_t act_time = 0; + 15374: 4603 mov r3, r0 + 15376: e7a3 b.n 152c0 + lv_anim_del(label, (lv_anim_exec_xcb_t)lv_label_set_offset_x); + 15378: 490f ldr r1, [pc, #60] ; (153b8 ) + 1537a: 4b10 ldr r3, [pc, #64] ; (153bc ) + 1537c: 4620 mov r0, r4 + ext->offset.x = 0; + 1537e: 2700 movs r7, #0 + lv_anim_del(label, (lv_anim_exec_xcb_t)lv_label_set_offset_x); + 15380: 4798 blx r3 + ext->offset.x = 0; + 15382: 81af strh r7, [r5, #12] + 15384: e7b5 b.n 152f2 + int32_t act_time = 0; + 15386: 463b mov r3, r7 + 15388: e7db b.n 15342 + 1538a: bf00 nop + 1538c: 00003fa9 .word 0x00003fa9 + 15390: 00014c8d .word 0x00014c8d + 15394: 000038c9 .word 0x000038c9 + 15398: 000034e1 .word 0x000034e1 + 1539c: 00002785 .word 0x00002785 + 153a0: 0000dc79 .word 0x0000dc79 + 153a4: 0000d175 .word 0x0000d175 + 153a8: 0000de0d .word 0x0000de0d + 153ac: 0000ddd9 .word 0x0000ddd9 + 153b0: 0000dd21 .word 0x0000dd21 + 153b4: 00014bc1 .word 0x00014bc1 + 153b8: 00014be1 .word 0x00014be1 + 153bc: 0000dcb1 .word 0x0000dcb1 + 153c0: 00003711 .word 0x00003711 + 153c4: 0001019d .word 0x0001019d + lv_anim_init(&a); + 153c8: 4b8a ldr r3, [pc, #552] ; (155f4 ) + 153ca: a80a add r0, sp, #40 ; 0x28 + 153cc: 4798 blx r3 + a->repeat_cnt = cnt; + 153ce: f64f 73ff movw r3, #65535 ; 0xffff + 153d2: f8ad 305c strh.w r3, [sp, #92] ; 0x5c + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + 153d6: f8bd 3024 ldrh.w r3, [sp, #36] ; 0x24 + 153da: f8bd 2020 ldrh.w r2, [sp, #32] + a->var = var; + 153de: 940a str r4, [sp, #40] ; 0x28 + 153e0: 3301 adds r3, #1 + 153e2: 1a9b subs r3, r3, r2 + if(size.x > lv_area_get_width(&txt_coords)) { + 153e4: f9bd 2018 ldrsh.w r2, [sp, #24] + 153e8: b21b sxth r3, r3 + 153ea: 429a cmp r2, r3 + 153ec: dd53 ble.n 15496 + lv_anim_set_values(&a, 0, -size.x - lv_font_get_glyph_width(font, ' ', ' ') * LV_LABEL_WAIT_CHAR_COUNT); + 153ee: 2220 movs r2, #32 + 153f0: 4611 mov r1, r2 + 153f2: 4b81 ldr r3, [pc, #516] ; (155f8 ) + a->exec_cb = exec_cb; + 153f4: 4f81 ldr r7, [pc, #516] ; (155fc ) + 153f6: 4630 mov r0, r6 + 153f8: 4798 blx r3 + 153fa: ebc0 3380 rsb r3, r0, r0, lsl #14 + 153fe: eb00 0283 add.w r2, r0, r3, lsl #2 + 15402: f8bd 3018 ldrh.w r3, [sp, #24] + lv_anim_set_time(&a, lv_anim_speed_to_time(ext->anim_speed, a.start, a.end)); + 15406: 8968 ldrh r0, [r5, #10] + 15408: 970b str r7, [sp, #44] ; 0x2c + lv_anim_set_values(&a, 0, -size.x - lv_font_get_glyph_width(font, ' ', ' ') * LV_LABEL_WAIT_CHAR_COUNT); + 1540a: 1ad2 subs r2, r2, r3 + a->start = start; + 1540c: 2100 movs r1, #0 + 1540e: b212 sxth r2, r2 + a->end = end; + 15410: e9cd 1210 strd r1, r2, [sp, #64] ; 0x40 + lv_anim_set_time(&a, lv_anim_speed_to_time(ext->anim_speed, a.start, a.end)); + 15414: 4b7a ldr r3, [pc, #488] ; (15600 ) + 15416: 4798 blx r3 + lv_anim_t * anim_cur = lv_anim_get(label, (lv_anim_exec_xcb_t)lv_label_set_offset_x); + 15418: 4b7a ldr r3, [pc, #488] ; (15604 ) + a->time = duration; + 1541a: 9012 str r0, [sp, #72] ; 0x48 + 1541c: 4639 mov r1, r7 + 1541e: 4620 mov r0, r4 + 15420: 4798 blx r3 + int32_t act_time = anim_cur ? anim_cur->act_time : 0; + 15422: b100 cbz r0, 15426 + 15424: 6a40 ldr r0, [r0, #36] ; 0x24 + if(act_time < a.time) { + 15426: 9b12 ldr r3, [sp, #72] ; 0x48 + 15428: 4283 cmp r3, r0 + a.early_apply = 0; + 1542a: bfc1 itttt gt + 1542c: f89d 305e ldrbgt.w r3, [sp, #94] ; 0x5e + a.act_time = act_time; /*To keep the old position*/ + 15430: 9013 strgt r0, [sp, #76] ; 0x4c + a.early_apply = 0; + 15432: f36f 0300 bfcgt r3, #0, #1 + 15436: f88d 305e strbgt.w r3, [sp, #94] ; 0x5e + lv_anim_start(&a); + 1543a: a80a add r0, sp, #40 ; 0x28 + 1543c: 4b72 ldr r3, [pc, #456] ; (15608 ) + 1543e: 4798 blx r3 + hor_anim = true; + 15440: 2701 movs r7, #1 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + 15442: f8bd 3026 ldrh.w r3, [sp, #38] ; 0x26 + 15446: f8bd 1022 ldrh.w r1, [sp, #34] ; 0x22 + if(size.y > lv_area_get_height(&txt_coords) && hor_anim == false) { + 1544a: f9bd 201a ldrsh.w r2, [sp, #26] + 1544e: 3301 adds r3, #1 + 15450: 1a5b subs r3, r3, r1 + 15452: b21b sxth r3, r3 + 15454: 429a cmp r2, r3 + 15456: dd25 ble.n 154a4 + 15458: bb27 cbnz r7, 154a4 + lv_anim_set_values(&a, 0, -size.y - (lv_font_get_line_height(font))); + 1545a: 8933 ldrh r3, [r6, #8] + a->exec_cb = exec_cb; + 1545c: 4e6b ldr r6, [pc, #428] ; (1560c ) + lv_anim_set_time(&a, lv_anim_speed_to_time(ext->anim_speed, a.start, a.end)); + 1545e: 8968 ldrh r0, [r5, #10] + 15460: 960b str r6, [sp, #44] ; 0x2c + lv_anim_set_values(&a, 0, -size.y - (lv_font_get_line_height(font))); + 15462: 441a add r2, r3 + 15464: 4252 negs r2, r2 + 15466: b212 sxth r2, r2 + lv_anim_set_time(&a, lv_anim_speed_to_time(ext->anim_speed, a.start, a.end)); + 15468: 4b65 ldr r3, [pc, #404] ; (15600 ) + 1546a: 4639 mov r1, r7 + a->end = end; + 1546c: e9cd 7210 strd r7, r2, [sp, #64] ; 0x40 + 15470: 4798 blx r3 + lv_anim_t * anim_cur = lv_anim_get(label, (lv_anim_exec_xcb_t)lv_label_set_offset_y); + 15472: 4b64 ldr r3, [pc, #400] ; (15604 ) + a->time = duration; + 15474: 9012 str r0, [sp, #72] ; 0x48 + 15476: 4631 mov r1, r6 + 15478: 4620 mov r0, r4 + 1547a: 4798 blx r3 + int32_t act_time = anim_cur ? anim_cur->act_time : 0; + 1547c: b100 cbz r0, 15480 + 1547e: 6a47 ldr r7, [r0, #36] ; 0x24 + if(act_time < a.time) { + 15480: 9b12 ldr r3, [sp, #72] ; 0x48 + 15482: 42bb cmp r3, r7 + a.early_apply = 0; + 15484: bfc1 itttt gt + 15486: f89d 305e ldrbgt.w r3, [sp, #94] ; 0x5e + a.act_time = act_time; /*To keep the old position*/ + 1548a: 9713 strgt r7, [sp, #76] ; 0x4c + a.early_apply = 0; + 1548c: f36f 0300 bfcgt r3, #0, #1 + 15490: f88d 305e strbgt.w r3, [sp, #94] ; 0x5e + 15494: e76a b.n 1536c + lv_anim_del(label, (lv_anim_exec_xcb_t)lv_label_set_offset_x); + 15496: 4959 ldr r1, [pc, #356] ; (155fc ) + 15498: 4b5d ldr r3, [pc, #372] ; (15610 ) + 1549a: 4620 mov r0, r4 + ext->offset.x = 0; + 1549c: 2700 movs r7, #0 + lv_anim_del(label, (lv_anim_exec_xcb_t)lv_label_set_offset_x); + 1549e: 4798 blx r3 + ext->offset.x = 0; + 154a0: 81af strh r7, [r5, #12] + 154a2: e7ce b.n 15442 + lv_anim_del(label, (lv_anim_exec_xcb_t)lv_label_set_offset_y); + 154a4: 4b5a ldr r3, [pc, #360] ; (15610 ) + 154a6: 4959 ldr r1, [pc, #356] ; (1560c ) + 154a8: 4620 mov r0, r4 + 154aa: 4798 blx r3 + ext->offset.y = 0; + 154ac: 2300 movs r3, #0 + 154ae: 81eb strh r3, [r5, #14] + 154b0: e6b8 b.n 15224 + 154b2: f8bd 3026 ldrh.w r3, [sp, #38] ; 0x26 + 154b6: f8bd 2022 ldrh.w r2, [sp, #34] ; 0x22 + 154ba: 3301 adds r3, #1 + 154bc: 1a9b subs r3, r3, r2 + if(size.y <= lv_area_get_height(&txt_coords)) { /*No dots are required, the text is short enough*/ + 154be: f9bd 201a ldrsh.w r2, [sp, #26] + 154c2: b21b sxth r3, r3 + 154c4: 429a cmp r2, r3 + 154c6: dc03 bgt.n 154d0 + ext->dot_end = LV_LABEL_DOT_END_INV; + 154c8: f64f 73ff movw r3, #65535 ; 0xffff + 154cc: 812b strh r3, [r5, #8] + 154ce: e6a9 b.n 15224 + else if(_lv_txt_get_encoded_length(ext->text) <= LV_LABEL_DOT_NUM) { /*Don't turn to dots all the characters*/ + 154d0: 4b50 ldr r3, [pc, #320] ; (15614 ) + 154d2: 6828 ldr r0, [r5, #0] + 154d4: 681b ldr r3, [r3, #0] + 154d6: 4798 blx r3 + 154d8: 2803 cmp r0, #3 + 154da: d9f5 bls.n 154c8 + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + 154dc: f8bd 8024 ldrh.w r8, [sp, #36] ; 0x24 + 154e0: f8bd 3020 ldrh.w r3, [sp, #32] + (lv_font_get_glyph_width(font, '.', '.') + letter_space) * + 154e4: 222e movs r2, #46 ; 0x2e + 154e6: f108 0801 add.w r8, r8, #1 + 154ea: 4611 mov r1, r2 + 154ec: eba8 0803 sub.w r8, r8, r3 + 154f0: 4630 mov r0, r6 + 154f2: 4b41 ldr r3, [pc, #260] ; (155f8 ) + 154f4: 4798 blx r3 + 154f6: 4448 add r0, r9 + p.x = lv_area_get_width(&txt_coords) - + 154f8: ebc0 3380 rsb r3, r0, r0, lsl #14 + 154fc: eb00 0083 add.w r0, r0, r3, lsl #2 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + 15500: f8bd 3026 ldrh.w r3, [sp, #38] ; 0x26 + 15504: f8bd 2022 ldrh.w r2, [sp, #34] ; 0x22 + byte_id -= _lv_txt_encoded_size(&ext->text[byte_id]); + 15508: f8df 9124 ldr.w r9, [pc, #292] ; 15630 + 1550c: 3301 adds r3, #1 + 1550e: 1a9b subs r3, r3, r2 + (lv_font_get_line_height(font) + line_space); /*Round down to the last line*/ + 15510: f9b6 2008 ldrsh.w r2, [r6, #8] + 15514: b29b uxth r3, r3 + 15516: 443a add r2, r7 + p.y -= line_space; /*Trim the last line space*/ + 15518: 1bd9 subs r1, r3, r7 + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + 1551a: fa1f f888 uxth.w r8, r8 + p.y -= p.y % + 1551e: b21b sxth r3, r3 + p.x = lv_area_get_width(&txt_coords) - + 15520: 4480 add r8, r0 + p.y -= p.y % + 15522: fb93 f0f2 sdiv r0, r3, r2 + 15526: fb02 3310 mls r3, r2, r0, r3 + p.y -= line_space; /*Trim the last line space*/ + 1552a: 1acb subs r3, r1, r3 + 1552c: f8ad 301e strh.w r3, [sp, #30] + uint32_t letter_id = lv_label_get_letter_on(label, &p); + 15530: a907 add r1, sp, #28 + 15532: 4b39 ldr r3, [pc, #228] ; (15618 ) + p.x = lv_area_get_width(&txt_coords) - + 15534: f8ad 801c strh.w r8, [sp, #28] + uint32_t letter_id = lv_label_get_letter_on(label, &p); + 15538: 4620 mov r0, r4 + 1553a: 4798 blx r3 + size_t txt_len = strlen(ext->text); + 1553c: 682e ldr r6, [r5, #0] + 1553e: 4b37 ldr r3, [pc, #220] ; (1561c ) + uint32_t letter_id = lv_label_get_letter_on(label, &p); + 15540: 4607 mov r7, r0 + size_t txt_len = strlen(ext->text); + 15542: 4630 mov r0, r6 + 15544: 4798 blx r3 + uint32_t byte_id = _lv_txt_encoded_get_byte_id(ext->text, letter_id); + 15546: 4b36 ldr r3, [pc, #216] ; (15620 ) + size_t txt_len = strlen(ext->text); + 15548: 4680 mov r8, r0 + uint32_t byte_id = _lv_txt_encoded_get_byte_id(ext->text, letter_id); + 1554a: 681b ldr r3, [r3, #0] + 1554c: 4630 mov r0, r6 + 1554e: 4639 mov r1, r7 + 15550: 4798 blx r3 + 15552: 4606 mov r6, r0 + byte_id -= _lv_txt_encoded_size(&ext->text[byte_id]); + 15554: 6828 ldr r0, [r5, #0] + 15556: f8d9 3000 ldr.w r3, [r9] + uint32_t byte_id = _lv_txt_encoded_get_byte_id(ext->text, letter_id); + 1555a: 960a str r6, [sp, #40] ; 0x28 + while(byte_id + LV_LABEL_DOT_NUM > txt_len) { + 1555c: f106 0b03 add.w fp, r6, #3 + 15560: 45c3 cmp fp, r8 + byte_id -= _lv_txt_encoded_size(&ext->text[byte_id]); + 15562: 4430 add r0, r6 + while(byte_id + LV_LABEL_DOT_NUM > txt_len) { + 15564: d82c bhi.n 155c0 + 15566: f04f 0a04 mov.w sl, #4 + uint8_t len = 0; + 1556a: f04f 0800 mov.w r8, #0 + len += _lv_txt_encoded_size(&ext->text[byte_id]); + 1556e: 9a0a ldr r2, [sp, #40] ; 0x28 + 15570: 6828 ldr r0, [r5, #0] + 15572: f8d9 3000 ldr.w r3, [r9] + 15576: 4410 add r0, r2 + 15578: 4798 blx r3 + _lv_txt_encoded_next(ext->text, &byte_id); + 1557a: 4b2a ldr r3, [pc, #168] ; (15624 ) + len += _lv_txt_encoded_size(&ext->text[byte_id]); + 1557c: 4440 add r0, r8 + _lv_txt_encoded_next(ext->text, &byte_id); + 1557e: 681b ldr r3, [r3, #0] + len += _lv_txt_encoded_size(&ext->text[byte_id]); + 15580: fa5f f880 uxtb.w r8, r0 + _lv_txt_encoded_next(ext->text, &byte_id); + 15584: a90a add r1, sp, #40 ; 0x28 + 15586: 6828 ldr r0, [r5, #0] + 15588: 4798 blx r3 + for(i = 0; i <= LV_LABEL_DOT_NUM; i++) { + 1558a: f1ba 0a01 subs.w sl, sl, #1 + 1558e: d1ee bne.n 1556e + if(lv_label_set_dot_tmp(label, &ext->text[byte_id_ori], len)) { + 15590: 6829 ldr r1, [r5, #0] + 15592: 4b25 ldr r3, [pc, #148] ; (15628 ) + 15594: 4642 mov r2, r8 + 15596: 4431 add r1, r6 + 15598: 4620 mov r0, r4 + 1559a: 4798 blx r3 + 1559c: 2800 cmp r0, #0 + 1559e: f43f ae41 beq.w 15224 + ext->text[byte_id_ori + i] = '.'; + 155a2: 682b ldr r3, [r5, #0] + 155a4: 222e movs r2, #46 ; 0x2e + 155a6: 559a strb r2, [r3, r6] + 155a8: 682b ldr r3, [r5, #0] + 155aa: 4433 add r3, r6 + ext->dot_end = letter_id + LV_LABEL_DOT_NUM; + 155ac: 3703 adds r7, #3 + ext->text[byte_id_ori + i] = '.'; + 155ae: 705a strb r2, [r3, #1] + 155b0: 682b ldr r3, [r5, #0] + 155b2: 4433 add r3, r6 + 155b4: 709a strb r2, [r3, #2] + ext->text[byte_id_ori + LV_LABEL_DOT_NUM] = '\0'; + 155b6: 682b ldr r3, [r5, #0] + 155b8: f803 a00b strb.w sl, [r3, fp] + ext->dot_end = letter_id + LV_LABEL_DOT_NUM; + 155bc: 812f strh r7, [r5, #8] + 155be: e631 b.n 15224 + byte_id -= _lv_txt_encoded_size(&ext->text[byte_id]); + 155c0: 4798 blx r3 + 155c2: 9e0a ldr r6, [sp, #40] ; 0x28 + letter_id--; + 155c4: 3f01 subs r7, #1 + byte_id -= _lv_txt_encoded_size(&ext->text[byte_id]); + 155c6: 1a36 subs r6, r6, r0 + letter_id--; + 155c8: e7c4 b.n 15554 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_TOP, pad_top, lv_style_int_t, _int, scalar) + 155ca: 2210 movs r2, #16 + 155cc: 2100 movs r1, #0 + 155ce: 4620 mov r0, r4 + 155d0: 47c0 blx r8 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_BOTTOM, pad_bottom, lv_style_int_t, _int, scalar) + 155d2: 2211 movs r2, #17 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_TOP, pad_top, lv_style_int_t, _int, scalar) + 155d4: 4605 mov r5, r0 +_LV_OBJ_STYLE_SET_GET_DECLARE(PAD_BOTTOM, pad_bottom, lv_style_int_t, _int, scalar) + 155d6: 2100 movs r1, #0 + 155d8: 4620 mov r0, r4 + 155da: 47c0 blx r8 + size.y += lv_obj_get_style_pad_top(label, LV_LABEL_PART_MAIN) + lv_obj_get_style_pad_bottom(label, LV_LABEL_PART_MAIN); + 155dc: f8bd 301a ldrh.w r3, [sp, #26] + 155e0: 1829 adds r1, r5, r0 + 155e2: 4419 add r1, r3 + 155e4: b209 sxth r1, r1 + lv_obj_set_height(label, size.y); + 155e6: 4b11 ldr r3, [pc, #68] ; (1562c ) + size.y += lv_obj_get_style_pad_top(label, LV_LABEL_PART_MAIN) + lv_obj_get_style_pad_bottom(label, LV_LABEL_PART_MAIN); + 155e8: f8ad 101a strh.w r1, [sp, #26] + lv_obj_set_height(label, size.y); + 155ec: 4620 mov r0, r4 + 155ee: 4798 blx r3 + 155f0: e618 b.n 15224 + 155f2: bf00 nop + 155f4: 0000dc79 .word 0x0000dc79 + 155f8: 0000d175 .word 0x0000d175 + 155fc: 00014be1 .word 0x00014be1 + 15600: 0000de0d .word 0x0000de0d + 15604: 0000ddd9 .word 0x0000ddd9 + 15608: 0000dd21 .word 0x0000dd21 + 1560c: 00014bc1 .word 0x00014bc1 + 15610: 0000dcb1 .word 0x0000dcb1 + 15614: 20000060 .word 0x20000060 + 15618: 00014ead .word 0x00014ead + 1561c: 00016339 .word 0x00016339 + 15620: 2000005c .word 0x2000005c + 15624: 20000058 .word 0x20000058 + 15628: 00014c01 .word 0x00014c01 + 1562c: 000035f1 .word 0x000035f1 + 15630: 20000054 .word 0x20000054 + +00015634 : +{ + 15634: e92d 43f7 stmdb sp!, {r0, r1, r2, r4, r5, r6, r7, r8, r9, lr} + LV_ASSERT_OBJ(label, LV_OBJX_NAME); + 15638: 4f40 ldr r7, [pc, #256] ; (1573c ) +{ + 1563a: 4606 mov r6, r0 + 1563c: 460d mov r5, r1 + LV_ASSERT_OBJ(label, LV_OBJX_NAME); + 1563e: 47b8 blx r7 + 15640: 4604 mov r4, r0 + 15642: b960 cbnz r0, 1565e + 15644: 4b3e ldr r3, [pc, #248] ; (15740 ) + 15646: 493f ldr r1, [pc, #252] ; (15744 ) + 15648: 9300 str r3, [sp, #0] + 1564a: 22b8 movs r2, #184 ; 0xb8 + 1564c: 2003 movs r0, #3 + 1564e: 4d3e ldr r5, [pc, #248] ; (15748 ) + 15650: 47a8 blx r5 + 15652: 483e ldr r0, [pc, #248] ; (1574c ) + 15654: 493e ldr r1, [pc, #248] ; (15750 ) + 15656: 4632 mov r2, r6 + 15658: 4623 mov r3, r4 + 1565a: 4788 blx r1 + 1565c: e7fe b.n 1565c + lv_obj_invalidate(label); + 1565e: 4b3d ldr r3, [pc, #244] ; (15754 ) + 15660: 4630 mov r0, r6 + 15662: 4798 blx r3 + lv_label_ext_t * ext = lv_obj_get_ext_attr(label); + 15664: 4b3c ldr r3, [pc, #240] ; (15758 ) + 15666: 4630 mov r0, r6 + 15668: 4798 blx r3 + 1566a: 4604 mov r4, r0 + if(text == NULL) { + 1566c: b92d cbnz r5, 1567a + lv_label_refr_text(label); + 1566e: 4b3b ldr r3, [pc, #236] ; (1575c ) + 15670: 4630 mov r0, r6 +} + 15672: b003 add sp, #12 + 15674: e8bd 43f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, lr} + lv_label_refr_text(label); + 15678: 4718 bx r3 + LV_ASSERT_STR(text); + 1567a: 4628 mov r0, r5 + 1567c: 47b8 blx r7 + 1567e: 4680 mov r8, r0 + 15680: b960 cbnz r0, 1569c + 15682: 4b2f ldr r3, [pc, #188] ; (15740 ) + 15684: 492f ldr r1, [pc, #188] ; (15744 ) + 15686: 9300 str r3, [sp, #0] + 15688: 22c4 movs r2, #196 ; 0xc4 + 1568a: 2003 movs r0, #3 + 1568c: 4c2e ldr r4, [pc, #184] ; (15748 ) + 1568e: 47a0 blx r4 + 15690: 482e ldr r0, [pc, #184] ; (1574c ) + 15692: 492f ldr r1, [pc, #188] ; (15750 ) + 15694: 462a mov r2, r5 + 15696: 4643 mov r3, r8 + 15698: 4788 blx r1 + 1569a: e7fe b.n 1569a + if(ext->text == text && ext->static_txt == 0) { + 1569c: 6820 ldr r0, [r4, #0] + 1569e: f8df 90d4 ldr.w r9, [pc, #212] ; 15774 + 156a2: 4285 cmp r5, r0 + 156a4: d11f bne.n 156e6 + 156a6: 7c23 ldrb r3, [r4, #16] + 156a8: 071b lsls r3, r3, #28 + 156aa: d425 bmi.n 156f8 + ext->text = lv_mem_realloc(ext->text, strlen(ext->text) + 1); + 156ac: 4628 mov r0, r5 + 156ae: 47c8 blx r9 + 156b0: 4b2b ldr r3, [pc, #172] ; (15760 ) + 156b2: 1c41 adds r1, r0, #1 + 156b4: 4628 mov r0, r5 + 156b6: 4798 blx r3 + 156b8: 6020 str r0, [r4, #0] + LV_ASSERT_MEM(ext->text); + 156ba: 47b8 blx r7 + 156bc: 4605 mov r5, r0 + 156be: b960 cbnz r0, 156da + 156c0: 4b1f ldr r3, [pc, #124] ; (15740 ) + 156c2: 4920 ldr r1, [pc, #128] ; (15744 ) + 156c4: 9300 str r3, [sp, #0] + 156c6: 22d5 movs r2, #213 ; 0xd5 + 156c8: 2003 movs r0, #3 + 156ca: 4e1f ldr r6, [pc, #124] ; (15748 ) + 156cc: 47b0 blx r6 + 156ce: 6822 ldr r2, [r4, #0] + 156d0: 4824 ldr r0, [pc, #144] ; (15764 ) + 156d2: 491f ldr r1, [pc, #124] ; (15750 ) + 156d4: 462b mov r3, r5 + 156d6: 4788 blx r1 + 156d8: e7fe b.n 156d8 + if(ext->text == NULL) return; + 156da: 6823 ldr r3, [r4, #0] + 156dc: 2b00 cmp r3, #0 + 156de: d1c6 bne.n 1566e +} + 156e0: b003 add sp, #12 + 156e2: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + if(ext->text != NULL && ext->static_txt == 0) { + 156e6: b138 cbz r0, 156f8 + 156e8: 7c23 ldrb r3, [r4, #16] + 156ea: f013 0808 ands.w r8, r3, #8 + 156ee: d103 bne.n 156f8 + lv_mem_free(ext->text); + 156f0: 4b1d ldr r3, [pc, #116] ; (15768 ) + 156f2: 4798 blx r3 + ext->text = NULL; + 156f4: f8c4 8000 str.w r8, [r4] + size_t len = strlen(text) + 1; + 156f8: 4628 mov r0, r5 + 156fa: 47c8 blx r9 + ext->text = lv_mem_alloc(len); + 156fc: 4b1b ldr r3, [pc, #108] ; (1576c ) + 156fe: 3001 adds r0, #1 + 15700: 4798 blx r3 + 15702: 6020 str r0, [r4, #0] + LV_ASSERT_MEM(ext->text); + 15704: 47b8 blx r7 + 15706: 4607 mov r7, r0 + 15708: b960 cbnz r0, 15724 + 1570a: 4b0d ldr r3, [pc, #52] ; (15740 ) + 1570c: 490d ldr r1, [pc, #52] ; (15744 ) + 1570e: 9300 str r3, [sp, #0] + 15710: 22ee movs r2, #238 ; 0xee + 15712: 2003 movs r0, #3 + 15714: 4d0c ldr r5, [pc, #48] ; (15748 ) + 15716: 47a8 blx r5 + 15718: 6822 ldr r2, [r4, #0] + 1571a: 4812 ldr r0, [pc, #72] ; (15764 ) + 1571c: 490c ldr r1, [pc, #48] ; (15750 ) + 1571e: 463b mov r3, r7 + 15720: 4788 blx r1 + 15722: e7fe b.n 15722 + if(ext->text == NULL) return; + 15724: 6820 ldr r0, [r4, #0] + 15726: 2800 cmp r0, #0 + 15728: d0da beq.n 156e0 + 1572a: 4b11 ldr r3, [pc, #68] ; (15770 ) + 1572c: 4629 mov r1, r5 + 1572e: 4798 blx r3 + ext->static_txt = 0; + 15730: 7c23 ldrb r3, [r4, #16] + 15732: f36f 03c3 bfc r3, #3, #1 + 15736: 7423 strb r3, [r4, #16] + 15738: e799 b.n 1566e + 1573a: bf00 nop + 1573c: 000017e1 .word 0x000017e1 + 15740: 000245b1 .word 0x000245b1 + 15744: 00024441 .word 0x00024441 + 15748: 0000e8e9 .word 0x0000e8e9 + 1574c: 0001eebf .word 0x0001eebf + 15750: 000017e9 .word 0x000017e9 + 15754: 00002785 .word 0x00002785 + 15758: 00003fa9 .word 0x00003fa9 + 1575c: 00015151 .word 0x00015151 + 15760: 0000ee15 .word 0x0000ee15 + 15764: 0001edbe .word 0x0001edbe + 15768: 0000eae5 .word 0x0000eae5 + 1576c: 0000ea2d .word 0x0000ea2d + 15770: 00016329 .word 0x00016329 + 15774: 00016339 .word 0x00016339 + +00015778 : +{ + 15778: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} + LV_ASSERT_OBJ(label, LV_OBJX_NAME); + 1577a: 4b16 ldr r3, [pc, #88] ; (157d4 ) +{ + 1577c: 4605 mov r5, r0 + 1577e: 460e mov r6, r1 + LV_ASSERT_OBJ(label, LV_OBJX_NAME); + 15780: 4798 blx r3 + 15782: 4604 mov r4, r0 + 15784: b968 cbnz r0, 157a2 + 15786: 4b14 ldr r3, [pc, #80] ; (157d8 ) + 15788: 4914 ldr r1, [pc, #80] ; (157dc ) + 1578a: 9300 str r3, [sp, #0] + 1578c: f44f 72a6 mov.w r2, #332 ; 0x14c + 15790: 2003 movs r0, #3 + 15792: 4e13 ldr r6, [pc, #76] ; (157e0 ) + 15794: 47b0 blx r6 + 15796: 4813 ldr r0, [pc, #76] ; (157e4 ) + 15798: 4913 ldr r1, [pc, #76] ; (157e8 ) + 1579a: 462a mov r2, r5 + 1579c: 4623 mov r3, r4 + 1579e: 4788 blx r1 + 157a0: e7fe b.n 157a0 + lv_label_ext_t * ext = lv_obj_get_ext_attr(label); + 157a2: 4b12 ldr r3, [pc, #72] ; (157ec ) + 157a4: 4628 mov r0, r5 + 157a6: 4798 blx r3 + if(ext->static_txt == 0 && ext->text != NULL) { + 157a8: 7c03 ldrb r3, [r0, #16] + 157aa: f013 0708 ands.w r7, r3, #8 + lv_label_ext_t * ext = lv_obj_get_ext_attr(label); + 157ae: 4604 mov r4, r0 + if(ext->static_txt == 0 && ext->text != NULL) { + 157b0: d104 bne.n 157bc + 157b2: 6800 ldr r0, [r0, #0] + 157b4: b110 cbz r0, 157bc + lv_mem_free(ext->text); + 157b6: 4b0e ldr r3, [pc, #56] ; (157f0 ) + 157b8: 4798 blx r3 + ext->text = NULL; + 157ba: 6027 str r7, [r4, #0] + if(text != NULL) { + 157bc: b126 cbz r6, 157c8 + ext->static_txt = 1; + 157be: 7c23 ldrb r3, [r4, #16] + ext->text = (char *)text; + 157c0: 6026 str r6, [r4, #0] + ext->static_txt = 1; + 157c2: f043 0308 orr.w r3, r3, #8 + 157c6: 7423 strb r3, [r4, #16] + lv_label_refr_text(label); + 157c8: 4b0a ldr r3, [pc, #40] ; (157f4 ) + 157ca: 4628 mov r0, r5 +} + 157cc: b003 add sp, #12 + 157ce: e8bd 40f0 ldmia.w sp!, {r4, r5, r6, r7, lr} + lv_label_refr_text(label); + 157d2: 4718 bx r3 + 157d4: 000017e1 .word 0x000017e1 + 157d8: 000245d9 .word 0x000245d9 + 157dc: 00024441 .word 0x00024441 + 157e0: 0000e8e9 .word 0x0000e8e9 + 157e4: 0001eebf .word 0x0001eebf + 157e8: 000017e9 .word 0x000017e9 + 157ec: 00003fa9 .word 0x00003fa9 + 157f0: 0000eae5 .word 0x0000eae5 + 157f4: 00015151 .word 0x00015151 + +000157f8 : +{ + 157f8: b5f7 push {r0, r1, r2, r4, r5, r6, r7, lr} + LV_ASSERT_OBJ(label, LV_OBJX_NAME); + 157fa: 4b23 ldr r3, [pc, #140] ; (15888 ) +{ + 157fc: 4604 mov r4, r0 + 157fe: 460e mov r6, r1 + LV_ASSERT_OBJ(label, LV_OBJX_NAME); + 15800: 4798 blx r3 + 15802: 4605 mov r5, r0 + 15804: b968 cbnz r0, 15822 + 15806: 4b21 ldr r3, [pc, #132] ; (1588c ) + 15808: 4921 ldr r1, [pc, #132] ; (15890 ) + 1580a: 9300 str r3, [sp, #0] + 1580c: f240 1265 movw r2, #357 ; 0x165 + 15810: 2003 movs r0, #3 + 15812: 4e20 ldr r6, [pc, #128] ; (15894 ) + 15814: 47b0 blx r6 + 15816: 4820 ldr r0, [pc, #128] ; (15898 ) + 15818: 4920 ldr r1, [pc, #128] ; (1589c ) + 1581a: 4622 mov r2, r4 + 1581c: 462b mov r3, r5 + 1581e: 4788 blx r1 + 15820: e7fe b.n 15820 + lv_label_ext_t * ext = lv_obj_get_ext_attr(label); + 15822: 4b1f ldr r3, [pc, #124] ; (158a0 ) + lv_anim_del(label, (lv_anim_exec_xcb_t)lv_obj_set_x); + 15824: 4f1f ldr r7, [pc, #124] ; (158a4 ) + lv_label_ext_t * ext = lv_obj_get_ext_attr(label); + 15826: 4620 mov r0, r4 + 15828: 4798 blx r3 + lv_anim_del(label, (lv_anim_exec_xcb_t)lv_obj_set_x); + 1582a: 491f ldr r1, [pc, #124] ; (158a8 ) + lv_label_ext_t * ext = lv_obj_get_ext_attr(label); + 1582c: 4605 mov r5, r0 + lv_anim_del(label, (lv_anim_exec_xcb_t)lv_obj_set_x); + 1582e: 4620 mov r0, r4 + 15830: 47b8 blx r7 + lv_anim_del(label, (lv_anim_exec_xcb_t)lv_obj_set_y); + 15832: 491e ldr r1, [pc, #120] ; (158ac ) + 15834: 4620 mov r0, r4 + 15836: 47b8 blx r7 + lv_anim_del(label, (lv_anim_exec_xcb_t)lv_label_set_offset_x); + 15838: 491d ldr r1, [pc, #116] ; (158b0 ) + 1583a: 4620 mov r0, r4 + 1583c: 47b8 blx r7 + lv_anim_del(label, (lv_anim_exec_xcb_t)lv_label_set_offset_y); + 1583e: 491d ldr r1, [pc, #116] ; (158b4 ) + 15840: 4620 mov r0, r4 + 15842: 47b8 blx r7 + if(long_mode == LV_LABEL_LONG_SROLL || long_mode == LV_LABEL_LONG_SROLL_CIRC || long_mode == LV_LABEL_LONG_CROP) + 15844: 1ef2 subs r2, r6, #3 + ext->offset.x = 0; + 15846: 2300 movs r3, #0 + if(long_mode == LV_LABEL_LONG_SROLL || long_mode == LV_LABEL_LONG_SROLL_CIRC || long_mode == LV_LABEL_LONG_CROP) + 15848: 2a02 cmp r2, #2 + ext->offset.x = 0; + 1584a: 60eb str r3, [r5, #12] + 1584c: 7c2b ldrb r3, [r5, #16] + if(long_mode == LV_LABEL_LONG_SROLL || long_mode == LV_LABEL_LONG_SROLL_CIRC || long_mode == LV_LABEL_LONG_CROP) + 1584e: bf8c ite hi + 15850: 2200 movhi r2, #0 + 15852: 2201 movls r2, #1 + 15854: f362 13c7 bfi r3, r2, #7, #1 + 15858: 742b strb r3, [r5, #16] + if(ext->long_mode == LV_LABEL_LONG_DOT && ext->dot_end != LV_LABEL_DOT_END_INV) { + 1585a: f003 0307 and.w r3, r3, #7 + 1585e: 2b02 cmp r3, #2 + 15860: d107 bne.n 15872 + 15862: 892a ldrh r2, [r5, #8] + 15864: f64f 73ff movw r3, #65535 ; 0xffff + 15868: 429a cmp r2, r3 + 1586a: d002 beq.n 15872 + lv_label_revert_dots(label); + 1586c: 4b12 ldr r3, [pc, #72] ; (158b8 ) + 1586e: 4620 mov r0, r4 + 15870: 4798 blx r3 + ext->long_mode = long_mode; + 15872: 7c2b ldrb r3, [r5, #16] + 15874: f366 0302 bfi r3, r6, #0, #3 + 15878: 742b strb r3, [r5, #16] + lv_label_refr_text(label); + 1587a: 4b10 ldr r3, [pc, #64] ; (158bc ) + 1587c: 4620 mov r0, r4 +} + 1587e: b003 add sp, #12 + 15880: e8bd 40f0 ldmia.w sp!, {r4, r5, r6, r7, lr} + lv_label_refr_text(label); + 15884: 4718 bx r3 + 15886: bf00 nop + 15888: 000017e1 .word 0x000017e1 + 1588c: 000245f2 .word 0x000245f2 + 15890: 00024441 .word 0x00024441 + 15894: 0000e8e9 .word 0x0000e8e9 + 15898: 0001eebf .word 0x0001eebf + 1589c: 000017e9 .word 0x000017e9 + 158a0: 00003fa9 .word 0x00003fa9 + 158a4: 0000dcb1 .word 0x0000dcb1 + 158a8: 00002989 .word 0x00002989 + 158ac: 000029e9 .word 0x000029e9 + 158b0: 00014be1 .word 0x00014be1 + 158b4: 00014bc1 .word 0x00014bc1 + 158b8: 00014b49 .word 0x00014b49 + 158bc: 00015151 .word 0x00015151 + +000158c0 : +{ + 158c0: b573 push {r0, r1, r4, r5, r6, lr} + LV_ASSERT_OBJ(label, LV_OBJX_NAME); + 158c2: 4b13 ldr r3, [pc, #76] ; (15910 ) +{ + 158c4: 4604 mov r4, r0 + 158c6: 460d mov r5, r1 + LV_ASSERT_OBJ(label, LV_OBJX_NAME); + 158c8: 4798 blx r3 + 158ca: 4606 mov r6, r0 + 158cc: b968 cbnz r0, 158ea + 158ce: 4b11 ldr r3, [pc, #68] ; (15914 ) + 158d0: 4911 ldr r1, [pc, #68] ; (15918 ) + 158d2: 9300 str r3, [sp, #0] + 158d4: f44f 72cd mov.w r2, #410 ; 0x19a + 158d8: 2003 movs r0, #3 + 158da: 4d10 ldr r5, [pc, #64] ; (1591c ) + 158dc: 47a8 blx r5 + 158de: 4810 ldr r0, [pc, #64] ; (15920 ) + 158e0: 4910 ldr r1, [pc, #64] ; (15924 ) + 158e2: 4622 mov r2, r4 + 158e4: 4633 mov r3, r6 + 158e6: 4788 blx r1 + 158e8: e7fe b.n 158e8 + lv_label_ext_t * ext = lv_obj_get_ext_attr(label); + 158ea: 4b0f ldr r3, [pc, #60] ; (15928 ) + 158ec: 4620 mov r0, r4 + 158ee: 4798 blx r3 + if(ext->recolor == en) return; + 158f0: 7c03 ldrb r3, [r0, #16] + 158f2: f3c3 1280 ubfx r2, r3, #6, #1 + 158f6: 42aa cmp r2, r5 + 158f8: d008 beq.n 1590c + ext->recolor = en == false ? 0 : 1; + 158fa: f365 1386 bfi r3, r5, #6, #1 + 158fe: 7403 strb r3, [r0, #16] + lv_label_refr_text(label); /*Refresh the text because the potential colo codes in text needs to + 15900: 4b0a ldr r3, [pc, #40] ; (1592c ) + 15902: 4620 mov r0, r4 +} + 15904: b002 add sp, #8 + 15906: e8bd 4070 ldmia.w sp!, {r4, r5, r6, lr} + lv_label_refr_text(label); /*Refresh the text because the potential colo codes in text needs to + 1590a: 4718 bx r3 +} + 1590c: b002 add sp, #8 + 1590e: bd70 pop {r4, r5, r6, pc} + 15910: 000017e1 .word 0x000017e1 + 15914: 00024609 .word 0x00024609 + 15918: 00024441 .word 0x00024441 + 1591c: 0000e8e9 .word 0x0000e8e9 + 15920: 0001eebf .word 0x0001eebf + 15924: 000017e9 .word 0x000017e9 + 15928: 00003fa9 .word 0x00003fa9 + 1592c: 00015151 .word 0x00015151 + +00015930 : +{ + 15930: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} + lv_obj_t * new_label = lv_obj_create(par, copy); + 15934: 4b71 ldr r3, [pc, #452] ; (15afc ) + LV_ASSERT_MEM(new_label); + 15936: f8df 8248 ldr.w r8, [pc, #584] ; 15b80 +{ + 1593a: b085 sub sp, #20 + 1593c: 460f mov r7, r1 + lv_obj_t * new_label = lv_obj_create(par, copy); + 1593e: 4798 blx r3 + 15940: 4605 mov r5, r0 + LV_ASSERT_MEM(new_label); + 15942: 47c0 blx r8 + 15944: 4604 mov r4, r0 + 15946: b960 cbnz r0, 15962 + 15948: 4b6d ldr r3, [pc, #436] ; (15b00 ) + 1594a: 496e ldr r1, [pc, #440] ; (15b04 ) + 1594c: 9300 str r3, [sp, #0] + 1594e: 2254 movs r2, #84 ; 0x54 + 15950: 2003 movs r0, #3 + 15952: 4e6d ldr r6, [pc, #436] ; (15b08 ) + 15954: 47b0 blx r6 + 15956: 486d ldr r0, [pc, #436] ; (15b0c ) + 15958: 496d ldr r1, [pc, #436] ; (15b10 ) + 1595a: 462a mov r2, r5 + 1595c: 4623 mov r3, r4 + 1595e: 4788 blx r1 + 15960: e7fe b.n 15960 + if(new_label == NULL) return NULL; + 15962: b925 cbnz r5, 1596e + 15964: 2400 movs r4, #0 +} + 15966: 4620 mov r0, r4 + 15968: b005 add sp, #20 + 1596a: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + if(ancestor_signal == NULL) ancestor_signal = lv_obj_get_signal_cb(new_label); + 1596e: 4c69 ldr r4, [pc, #420] ; (15b14 ) + 15970: 6823 ldr r3, [r4, #0] + 15972: b91b cbnz r3, 1597c + 15974: 4b68 ldr r3, [pc, #416] ; (15b18 ) + 15976: 4628 mov r0, r5 + 15978: 4798 blx r3 + 1597a: 6020 str r0, [r4, #0] + lv_obj_allocate_ext_attr(new_label, sizeof(lv_label_ext_t)); + 1597c: 4b67 ldr r3, [pc, #412] ; (15b1c ) + lv_label_ext_t * ext = lv_obj_get_ext_attr(new_label); + 1597e: 4e68 ldr r6, [pc, #416] ; (15b20 ) + lv_obj_allocate_ext_attr(new_label, sizeof(lv_label_ext_t)); + 15980: 2114 movs r1, #20 + 15982: 4628 mov r0, r5 + 15984: 4798 blx r3 + lv_label_ext_t * ext = lv_obj_get_ext_attr(new_label); + 15986: 4628 mov r0, r5 + 15988: 47b0 blx r6 + 1598a: 4604 mov r4, r0 + LV_ASSERT_MEM(ext); + 1598c: 47c0 blx r8 + 1598e: 4681 mov r9, r0 + 15990: b960 cbnz r0, 159ac + 15992: 4b5b ldr r3, [pc, #364] ; (15b00 ) + 15994: 495b ldr r1, [pc, #364] ; (15b04 ) + 15996: 9300 str r3, [sp, #0] + 15998: 225d movs r2, #93 ; 0x5d + 1599a: 2003 movs r0, #3 + 1599c: 4d5a ldr r5, [pc, #360] ; (15b08 ) + 1599e: 47a8 blx r5 + 159a0: 485a ldr r0, [pc, #360] ; (15b0c ) + 159a2: 495b ldr r1, [pc, #364] ; (15b10 ) + 159a4: 4622 mov r2, r4 + 159a6: 464b mov r3, r9 + 159a8: 4788 blx r1 + 159aa: e7fe b.n 159aa + if(ext == NULL) { + 159ac: b91c cbnz r4, 159b6 + lv_obj_del(new_label); + 159ae: 4b5d ldr r3, [pc, #372] ; (15b24 ) + 159b0: 4628 mov r0, r5 + 159b2: 4798 blx r3 + return NULL; + 159b4: e7d7 b.n 15966 + ext->dot_end = LV_LABEL_DOT_END_INV; + 159b6: 4a5c ldr r2, [pc, #368] ; (15b28 ) + lv_obj_set_design_cb(new_label, lv_label_design); + 159b8: 495c ldr r1, [pc, #368] ; (15b2c ) + 159ba: f8df 91c8 ldr.w r9, [pc, #456] ; 15b84 + ext->text = NULL; + 159be: 2300 movs r3, #0 + ext->offset.x = 0; + 159c0: e9c4 2302 strd r2, r3, [r4, #8] + ext->dot.tmp_ptr = NULL; + 159c4: e9c4 3300 strd r3, r3, [r4] + ext->long_mode = LV_LABEL_LONG_EXPAND; + 159c8: 8a23 ldrh r3, [r4, #16] + 159ca: f423 73bf bic.w r3, r3, #382 ; 0x17e + 159ce: f023 0301 bic.w r3, r3, #1 + 159d2: f043 0330 orr.w r3, r3, #48 ; 0x30 + 159d6: 8223 strh r3, [r4, #16] + lv_obj_set_design_cb(new_label, lv_label_design); + 159d8: 4628 mov r0, r5 + 159da: 4b55 ldr r3, [pc, #340] ; (15b30 ) + 159dc: 4798 blx r3 + lv_obj_set_signal_cb(new_label, lv_label_signal); + 159de: 4955 ldr r1, [pc, #340] ; (15b34 ) + 159e0: 4b55 ldr r3, [pc, #340] ; (15b38 ) + 159e2: 4628 mov r0, r5 + 159e4: 4798 blx r3 + if(copy == NULL) { + 159e6: b9c7 cbnz r7, 15a1a + lv_theme_apply(new_label, LV_THEME_LABEL); + 159e8: 4b54 ldr r3, [pc, #336] ; (15b3c ) + 159ea: 2112 movs r1, #18 + 159ec: 4628 mov r0, r5 + 159ee: 4798 blx r3 + lv_obj_set_click(new_label, false); + 159f0: 4b53 ldr r3, [pc, #332] ; (15b40 ) + 159f2: 4639 mov r1, r7 + 159f4: 4628 mov r0, r5 + 159f6: 4798 blx r3 + lv_label_set_long_mode(new_label, LV_LABEL_LONG_EXPAND); + 159f8: 4639 mov r1, r7 + 159fa: 4628 mov r0, r5 + 159fc: 47c8 blx r9 + lv_label_set_text(new_label, "Text"); + 159fe: 4951 ldr r1, [pc, #324] ; (15b44 ) + 15a00: 4b51 ldr r3, [pc, #324] ; (15b48 ) + 15a02: 4628 mov r0, r5 + 15a04: 4798 blx r3 + LV_LOG_INFO("label created"); + 15a06: 4b51 ldr r3, [pc, #324] ; (15b4c ) + 15a08: 4c3f ldr r4, [pc, #252] ; (15b08 ) + 15a0a: 9300 str r3, [sp, #0] + 15a0c: 493d ldr r1, [pc, #244] ; (15b04 ) + 15a0e: 4b3c ldr r3, [pc, #240] ; (15b00 ) + 15a10: 22a8 movs r2, #168 ; 0xa8 + 15a12: 2001 movs r0, #1 + 15a14: 47a0 blx r4 + return new_label; + 15a16: 462c mov r4, r5 + 15a18: e7a5 b.n 15966 + lv_label_ext_t * copy_ext = lv_obj_get_ext_attr(copy); + 15a1a: 4638 mov r0, r7 + 15a1c: 47b0 blx r6 + lv_label_set_long_mode(new_label, lv_label_get_long_mode(copy)); + 15a1e: 4b4c ldr r3, [pc, #304] ; (15b50 ) + lv_label_ext_t * copy_ext = lv_obj_get_ext_attr(copy); + 15a20: 4606 mov r6, r0 + lv_label_set_long_mode(new_label, lv_label_get_long_mode(copy)); + 15a22: 4638 mov r0, r7 + 15a24: 4798 blx r3 + 15a26: 4601 mov r1, r0 + 15a28: 4628 mov r0, r5 + 15a2a: 47c8 blx r9 + lv_label_set_recolor(new_label, lv_label_get_recolor(copy)); + 15a2c: 4b49 ldr r3, [pc, #292] ; (15b54 ) + 15a2e: 4638 mov r0, r7 + 15a30: 4798 blx r3 + 15a32: 4b49 ldr r3, [pc, #292] ; (15b58 ) + 15a34: 4601 mov r1, r0 + 15a36: 4628 mov r0, r5 + 15a38: 4798 blx r3 + lv_label_set_align(new_label, lv_label_get_align(copy)); + 15a3a: 4b48 ldr r3, [pc, #288] ; (15b5c ) + 15a3c: 4638 mov r0, r7 + 15a3e: 4798 blx r3 + 15a40: 4b47 ldr r3, [pc, #284] ; (15b60 ) + 15a42: 4601 mov r1, r0 + 15a44: 4628 mov r0, r5 + 15a46: 4798 blx r3 + if(copy_ext->static_txt == 0) + 15a48: 7c33 ldrb r3, [r6, #16] + 15a4a: f013 0f08 tst.w r3, #8 + lv_label_set_text(new_label, lv_label_get_text(copy)); + 15a4e: 4638 mov r0, r7 + 15a50: 4b44 ldr r3, [pc, #272] ; (15b64 ) + if(copy_ext->static_txt == 0) + 15a52: d123 bne.n 15a9c + lv_label_set_text(new_label, lv_label_get_text(copy)); + 15a54: 4798 blx r3 + 15a56: 4b3c ldr r3, [pc, #240] ; (15b48 ) + 15a58: 4601 mov r1, r0 + 15a5a: 4628 mov r0, r5 + lv_label_set_text_static(new_label, lv_label_get_text(copy)); + 15a5c: 4798 blx r3 + if(copy_ext->long_mode == LV_LABEL_LONG_DOT) { + 15a5e: 7c33 ldrb r3, [r6, #16] + 15a60: f003 0307 and.w r3, r3, #7 + 15a64: 2b02 cmp r3, #2 + 15a66: d12b bne.n 15ac0 + ext->text = lv_mem_realloc(ext->text, _lv_mem_get_size(copy_ext->text)); + 15a68: 6830 ldr r0, [r6, #0] + 15a6a: f8df 911c ldr.w r9, [pc, #284] ; 15b88 + 15a6e: 6827 ldr r7, [r4, #0] + 15a70: 47c8 blx r9 + 15a72: 4b3d ldr r3, [pc, #244] ; (15b68 ) + 15a74: 4601 mov r1, r0 + 15a76: 4638 mov r0, r7 + 15a78: 4798 blx r3 + 15a7a: 6020 str r0, [r4, #0] + LV_ASSERT_MEM(ext->text); + 15a7c: 47c0 blx r8 + 15a7e: 4607 mov r7, r0 + 15a80: b988 cbnz r0, 15aa6 + 15a82: 4b1f ldr r3, [pc, #124] ; (15b00 ) + 15a84: 491f ldr r1, [pc, #124] ; (15b04 ) + 15a86: 9300 str r3, [sp, #0] + 15a88: 2295 movs r2, #149 ; 0x95 + 15a8a: 2003 movs r0, #3 + 15a8c: 4d1e ldr r5, [pc, #120] ; (15b08 ) + 15a8e: 47a8 blx r5 + 15a90: 6822 ldr r2, [r4, #0] + 15a92: 481e ldr r0, [pc, #120] ; (15b0c ) + 15a94: 491e ldr r1, [pc, #120] ; (15b10 ) + 15a96: 463b mov r3, r7 + 15a98: 4788 blx r1 + 15a9a: e7fe b.n 15a9a + lv_label_set_text_static(new_label, lv_label_get_text(copy)); + 15a9c: 4798 blx r3 + 15a9e: 4b33 ldr r3, [pc, #204] ; (15b6c ) + 15aa0: 4601 mov r1, r0 + 15aa2: 4628 mov r0, r5 + 15aa4: e7da b.n 15a5c + if(ext->text == NULL) return NULL; + 15aa6: 6827 ldr r7, [r4, #0] + 15aa8: 2f00 cmp r7, #0 + 15aaa: f43f af5b beq.w 15964 + _lv_memcpy(ext->text, copy_ext->text, _lv_mem_get_size(copy_ext->text)); + 15aae: 6831 ldr r1, [r6, #0] + 15ab0: 9103 str r1, [sp, #12] + 15ab2: 4608 mov r0, r1 + 15ab4: 47c8 blx r9 + 15ab6: 9903 ldr r1, [sp, #12] + 15ab8: 4b2d ldr r3, [pc, #180] ; (15b70 ) + 15aba: 4602 mov r2, r0 + 15abc: 4638 mov r0, r7 + 15abe: 4798 blx r3 + if(copy_ext->dot_tmp_alloc && copy_ext->dot.tmp_ptr) { + 15ac0: 7c73 ldrb r3, [r6, #17] + 15ac2: 07db lsls r3, r3, #31 + 15ac4: d514 bpl.n 15af0 + 15ac6: 6870 ldr r0, [r6, #4] + 15ac8: b190 cbz r0, 15af0 + uint16_t len = (uint16_t)strlen(copy_ext->dot.tmp_ptr); + 15aca: 4b2a ldr r3, [pc, #168] ; (15b74 ) + 15acc: 4798 blx r3 + lv_label_set_dot_tmp(new_label, ext->dot.tmp_ptr, len); + 15ace: 6861 ldr r1, [r4, #4] + 15ad0: 4b29 ldr r3, [pc, #164] ; (15b78 ) + 15ad2: b282 uxth r2, r0 + 15ad4: 4628 mov r0, r5 + 15ad6: 4798 blx r3 + ext->dot_tmp_alloc = copy_ext->dot_tmp_alloc; + 15ad8: 7c72 ldrb r2, [r6, #17] + 15ada: 7c63 ldrb r3, [r4, #17] + 15adc: f362 0300 bfi r3, r2, #0, #1 + 15ae0: 7463 strb r3, [r4, #17] + ext->dot_end = copy_ext->dot_end; + 15ae2: 8933 ldrh r3, [r6, #8] + 15ae4: 8123 strh r3, [r4, #8] + lv_obj_refresh_style(new_label, LV_STYLE_PROP_ALL); + 15ae6: 21ff movs r1, #255 ; 0xff + 15ae8: 4b24 ldr r3, [pc, #144] ; (15b7c ) + 15aea: 4628 mov r0, r5 + 15aec: 4798 blx r3 + 15aee: e78a b.n 15a06 + _lv_memcpy(ext->dot.tmp, copy_ext->dot.tmp, sizeof(ext->dot.tmp)); + 15af0: 2204 movs r2, #4 + 15af2: 4b1f ldr r3, [pc, #124] ; (15b70 ) + 15af4: 18b1 adds r1, r6, r2 + 15af6: 18a0 adds r0, r4, r2 + 15af8: 4798 blx r3 + 15afa: e7ed b.n 15ad8 + 15afc: 000030e5 .word 0x000030e5 + 15b00: 0002461e .word 0x0002461e + 15b04: 00024441 .word 0x00024441 + 15b08: 0000e8e9 .word 0x0000e8e9 + 15b0c: 0001edbe .word 0x0001edbe + 15b10: 000017e9 .word 0x000017e9 + 15b14: 2000c7fc .word 0x2000c7fc + 15b18: 00003f61 .word 0x00003f61 + 15b1c: 00002079 .word 0x00002079 + 15b20: 00003fa9 .word 0x00003fa9 + 15b24: 00004161 .word 0x00004161 + 15b28: 0019ffff .word 0x0019ffff + 15b2c: 00015ce9 .word 0x00015ce9 + 15b30: 00002031 .word 0x00002031 + 15b34: 00015b8d .word 0x00015b8d + 15b38: 00001fdd .word 0x00001fdd + 15b3c: 000102e5 .word 0x000102e5 + 15b40: 00001e5d .word 0x00001e5d + 15b44: 0002449f .word 0x0002449f + 15b48: 00015635 .word 0x00015635 + 15b4c: 000244a4 .word 0x000244a4 + 15b50: 00014da9 .word 0x00014da9 + 15b54: 00014e59 .word 0x00014e59 + 15b58: 000158c1 .word 0x000158c1 + 15b5c: 00014dfd .word 0x00014dfd + 15b60: 00014ce9 .word 0x00014ce9 + 15b64: 00014d59 .word 0x00014d59 + 15b68: 0000ee15 .word 0x0000ee15 + 15b6c: 00015779 .word 0x00015779 + 15b70: 0000ec31 .word 0x0000ec31 + 15b74: 00016339 .word 0x00016339 + 15b78: 00014c01 .word 0x00014c01 + 15b7c: 00002d91 .word 0x00002d91 + 15b80: 000017e1 .word 0x000017e1 + 15b84: 000157f9 .word 0x000157f9 + 15b88: 0000eb4d .word 0x0000eb4d + +00015b8c : + if(sign == LV_SIGNAL_GET_STYLE) { + 15b8c: 2908 cmp r1, #8 +{ + 15b8e: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 15b92: 4604 mov r4, r0 + 15b94: 460e mov r6, r1 + 15b96: 4615 mov r5, r2 + if(sign == LV_SIGNAL_GET_STYLE) { + 15b98: d10e bne.n 15bb8 + switch(type) { + 15b9a: 7813 ldrb r3, [r2, #0] + 15b9c: b133 cbz r3, 15bac + info->result = lv_label_get_style(label, info->part); + 15b9e: 2300 movs r3, #0 + 15ba0: 6053 str r3, [r2, #4] + else return ancestor_signal(label, sign, param); + 15ba2: 4b25 ldr r3, [pc, #148] ; (15c38 ) +} + 15ba4: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} + else return ancestor_signal(label, sign, param); + 15ba8: 681b ldr r3, [r3, #0] + 15baa: 4718 bx r3 + style_dsc_p = &label->style_list; + 15bac: 3428 adds r4, #40 ; 0x28 + info->result = lv_label_get_style(label, info->part); + 15bae: 6054 str r4, [r2, #4] + if(info->result != NULL) return LV_RES_OK; + 15bb0: 2701 movs r7, #1 +} + 15bb2: 4638 mov r0, r7 + 15bb4: e8bd 81f0 ldmia.w sp!, {r4, r5, r6, r7, r8, pc} + res = ancestor_signal(label, sign, param); + 15bb8: 4b1f ldr r3, [pc, #124] ; (15c38 ) + 15bba: 681b ldr r3, [r3, #0] + 15bbc: 4798 blx r3 + if(res != LV_RES_OK) return res; + 15bbe: 2801 cmp r0, #1 + res = ancestor_signal(label, sign, param); + 15bc0: 4607 mov r7, r0 + if(res != LV_RES_OK) return res; + 15bc2: d1f6 bne.n 15bb2 + if(sign == LV_SIGNAL_GET_TYPE) return lv_obj_handle_get_type_signal(param, LV_OBJX_NAME); + 15bc4: 2e07 cmp r6, #7 + 15bc6: d105 bne.n 15bd4 + 15bc8: 4628 mov r0, r5 + 15bca: 491c ldr r1, [pc, #112] ; (15c3c ) + 15bcc: 4b1c ldr r3, [pc, #112] ; (15c40 ) +} + 15bce: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} + if(sign == LV_SIGNAL_GET_TYPE) return lv_obj_handle_get_type_signal(param, LV_OBJX_NAME); + 15bd2: 4718 bx r3 + lv_label_ext_t * ext = lv_obj_get_ext_attr(label); + 15bd4: 4b1b ldr r3, [pc, #108] ; (15c44 ) + 15bd6: 4620 mov r0, r4 + 15bd8: 4798 blx r3 + 15bda: 4680 mov r8, r0 + if(sign == LV_SIGNAL_CLEANUP) { + 15bdc: b966 cbnz r6, 15bf8 + if(ext->static_txt == 0) { + 15bde: 7c03 ldrb r3, [r0, #16] + 15be0: f013 0508 ands.w r5, r3, #8 + 15be4: d104 bne.n 15bf0 + lv_mem_free(ext->text); + 15be6: 6800 ldr r0, [r0, #0] + 15be8: 4b17 ldr r3, [pc, #92] ; (15c48 ) + 15bea: 4798 blx r3 + ext->text = NULL; + 15bec: f8c8 5000 str.w r5, [r8] + lv_label_dot_tmp_free(label); + 15bf0: 4b16 ldr r3, [pc, #88] ; (15c4c ) + 15bf2: 4620 mov r0, r4 + lv_label_refr_text(label); + 15bf4: 4798 blx r3 + 15bf6: e7dc b.n 15bb2 + else if(sign == LV_SIGNAL_STYLE_CHG) { + 15bf8: 2e04 cmp r6, #4 + 15bfa: d105 bne.n 15c08 + lv_label_revert_dots(label); + 15bfc: 4b14 ldr r3, [pc, #80] ; (15c50 ) + 15bfe: 4620 mov r0, r4 + 15c00: 4798 blx r3 + lv_label_refr_text(label); + 15c02: 4b14 ldr r3, [pc, #80] ; (15c54 ) + 15c04: 4620 mov r0, r4 + 15c06: e7f5 b.n 15bf4 + else if(sign == LV_SIGNAL_COORD_CHG) { + 15c08: 2e02 cmp r6, #2 + 15c0a: d1d2 bne.n 15bb2 + 15c0c: 8a23 ldrh r3, [r4, #16] + 15c0e: 8aa2 ldrh r2, [r4, #20] + 15c10: 8829 ldrh r1, [r5, #0] + 15c12: 1ad2 subs r2, r2, r3 + 15c14: 88ab ldrh r3, [r5, #4] + 15c16: 1a5b subs r3, r3, r1 + if(lv_area_get_width(&label->coords) != lv_area_get_width(param) || + 15c18: b292 uxth r2, r2 + 15c1a: b29b uxth r3, r3 + 15c1c: 429a cmp r2, r3 + 15c1e: d1ed bne.n 15bfc + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + 15c20: 8a63 ldrh r3, [r4, #18] + 15c22: 8ae2 ldrh r2, [r4, #22] + 15c24: 8869 ldrh r1, [r5, #2] + 15c26: 1ad2 subs r2, r2, r3 + 15c28: 88eb ldrh r3, [r5, #6] + 15c2a: 1a5b subs r3, r3, r1 + 15c2c: b292 uxth r2, r2 + 15c2e: b29b uxth r3, r3 + 15c30: 429a cmp r2, r3 + 15c32: d1e3 bne.n 15bfc + 15c34: e7bd b.n 15bb2 + 15c36: bf00 nop + 15c38: 2000c7fc .word 0x2000c7fc + 15c3c: 000244b2 .word 0x000244b2 + 15c40: 0000428d .word 0x0000428d + 15c44: 00003fa9 .word 0x00003fa9 + 15c48: 0000eae5 .word 0x0000eae5 + 15c4c: 00014b1d .word 0x00014b1d + 15c50: 00014b49 .word 0x00014b49 + 15c54: 00015151 .word 0x00015151 + +00015c58 : +{ + 15c58: b573 push {r0, r1, r4, r5, r6, lr} + LV_ASSERT_OBJ(label, LV_OBJX_NAME); + 15c5a: 4b0b ldr r3, [pc, #44] ; (15c88 ) +{ + 15c5c: 4605 mov r5, r0 + LV_ASSERT_OBJ(label, LV_OBJX_NAME); + 15c5e: 4798 blx r3 + 15c60: 4604 mov r4, r0 + 15c62: b968 cbnz r0, 15c80 + 15c64: 4b09 ldr r3, [pc, #36] ; (15c8c ) + 15c66: 490a ldr r1, [pc, #40] ; (15c90 ) + 15c68: 9300 str r3, [sp, #0] + 15c6a: f240 321d movw r2, #797 ; 0x31d + 15c6e: 2003 movs r0, #3 + 15c70: 4e08 ldr r6, [pc, #32] ; (15c94 ) + 15c72: 47b0 blx r6 + 15c74: 4808 ldr r0, [pc, #32] ; (15c98 ) + 15c76: 4909 ldr r1, [pc, #36] ; (15c9c ) + 15c78: 462a mov r2, r5 + 15c7a: 4623 mov r3, r4 + 15c7c: 4788 blx r1 + 15c7e: e7fe b.n 15c7e +} + 15c80: f64f 70ff movw r0, #65535 ; 0xffff + 15c84: b002 add sp, #8 + 15c86: bd70 pop {r4, r5, r6, pc} + 15c88: 000017e1 .word 0x000017e1 + 15c8c: 00024646 .word 0x00024646 + 15c90: 00024441 .word 0x00024441 + 15c94: 0000e8e9 .word 0x0000e8e9 + 15c98: 0001eebf .word 0x0001eebf + 15c9c: 000017e9 .word 0x000017e9 + +00015ca0 : +{ + 15ca0: b573 push {r0, r1, r4, r5, r6, lr} + LV_ASSERT_OBJ(label, LV_OBJX_NAME); + 15ca2: 4b0b ldr r3, [pc, #44] ; (15cd0 ) +{ + 15ca4: 4605 mov r5, r0 + LV_ASSERT_OBJ(label, LV_OBJX_NAME); + 15ca6: 4798 blx r3 + 15ca8: 4604 mov r4, r0 + 15caa: b968 cbnz r0, 15cc8 + 15cac: 4b09 ldr r3, [pc, #36] ; (15cd4 ) + 15cae: 490a ldr r1, [pc, #40] ; (15cd8 ) + 15cb0: 9300 str r3, [sp, #0] + 15cb2: f44f 724c mov.w r2, #816 ; 0x330 + 15cb6: 2003 movs r0, #3 + 15cb8: 4e08 ldr r6, [pc, #32] ; (15cdc ) + 15cba: 47b0 blx r6 + 15cbc: 4808 ldr r0, [pc, #32] ; (15ce0 ) + 15cbe: 4909 ldr r1, [pc, #36] ; (15ce4 ) + 15cc0: 462a mov r2, r5 + 15cc2: 4623 mov r3, r4 + 15cc4: 4788 blx r1 + 15cc6: e7fe b.n 15cc6 +} + 15cc8: f64f 70ff movw r0, #65535 ; 0xffff + 15ccc: b002 add sp, #8 + 15cce: bd70 pop {r4, r5, r6, pc} + 15cd0: 000017e1 .word 0x000017e1 + 15cd4: 00024662 .word 0x00024662 + 15cd8: 00024441 .word 0x00024441 + 15cdc: 0000e8e9 .word 0x0000e8e9 + 15ce0: 0001eebf .word 0x0001eebf + 15ce4: 000017e9 .word 0x000017e9 + +00015ce8 : +{ + 15ce8: e92d 43f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, lr} + if(mode == LV_DESIGN_COVER_CHK) + 15cec: 2a02 cmp r2, #2 +{ + 15cee: b0a9 sub sp, #164 ; 0xa4 + 15cf0: 4605 mov r5, r0 + 15cf2: 4688 mov r8, r1 + 15cf4: 4617 mov r7, r2 + if(mode == LV_DESIGN_COVER_CHK) + 15cf6: f000 80fa beq.w 15eee + else if(mode == LV_DESIGN_DRAW_MAIN) { + 15cfa: 2a00 cmp r2, #0 + 15cfc: f040 8100 bne.w 15f00 + lv_label_ext_t * ext = lv_obj_get_ext_attr(label); + 15d00: 4b80 ldr r3, [pc, #512] ; (15f04 ) +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSFORM_WIDTH, transform_width, lv_style_int_t, _int, scalar) + 15d02: f8df 9238 ldr.w r9, [pc, #568] ; 15f3c + 15d06: 4798 blx r3 + 15d08: 2204 movs r2, #4 + 15d0a: 4639 mov r1, r7 + 15d0c: 4604 mov r4, r0 + 15d0e: 4628 mov r0, r5 + 15d10: 47c8 blx r9 +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSFORM_HEIGHT, transform_height, lv_style_int_t, _int, scalar) + 15d12: 2205 movs r2, #5 +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSFORM_WIDTH, transform_width, lv_style_int_t, _int, scalar) + 15d14: 4606 mov r6, r0 +_LV_OBJ_STYLE_SET_GET_DECLARE(TRANSFORM_HEIGHT, transform_height, lv_style_int_t, _int, scalar) + 15d16: 4639 mov r1, r7 + 15d18: 4628 mov r0, r5 + 15d1a: 47c8 blx r9 + 15d1c: 6969 ldr r1, [r5, #20] + 15d1e: 4603 mov r3, r0 + 15d20: 6928 ldr r0, [r5, #16] + 15d22: aa06 add r2, sp, #24 + 15d24: c203 stmia r2!, {r0, r1} + bg_coords.x1 -= w; + 15d26: f8bd 2018 ldrh.w r2, [sp, #24] + 15d2a: b2b0 uxth r0, r6 + 15d2c: 1a12 subs r2, r2, r0 + 15d2e: f8ad 2018 strh.w r2, [sp, #24] + bg_coords.x2 += w; + 15d32: f8bd 201c ldrh.w r2, [sp, #28] + 15d36: 4410 add r0, r2 + 15d38: f8ad 001c strh.w r0, [sp, #28] + bg_coords.y1 -= h; + 15d3c: b298 uxth r0, r3 + 15d3e: f8bd 301a ldrh.w r3, [sp, #26] + 15d42: 1a1b subs r3, r3, r0 + 15d44: f8ad 301a strh.w r3, [sp, #26] + bg_coords.y2 += h; + 15d48: f8bd 301e ldrh.w r3, [sp, #30] + 15d4c: 4418 add r0, r3 + 15d4e: f8ad 001e strh.w r0, [sp, #30] + lv_draw_rect_dsc_init(&draw_rect_dsc); + 15d52: 4b6d ldr r3, [pc, #436] ; (15f08 ) + 15d54: a813 add r0, sp, #76 ; 0x4c + 15d56: 4798 blx r3 + lv_obj_init_draw_rect_dsc(label, LV_LABEL_PART_MAIN, &draw_rect_dsc); + 15d58: 4b6c ldr r3, [pc, #432] ; (15f0c ) + 15d5a: aa13 add r2, sp, #76 ; 0x4c + 15d5c: 4639 mov r1, r7 + 15d5e: 4628 mov r0, r5 + 15d60: 4798 blx r3 + lv_draw_rect(&bg_coords, clip_area, &draw_rect_dsc); + 15d62: aa13 add r2, sp, #76 ; 0x4c + 15d64: 4b6a ldr r3, [pc, #424] ; (15f10 ) + 15d66: 4641 mov r1, r8 + 15d68: a806 add r0, sp, #24 + 15d6a: 4798 blx r3 + get_txt_coords(label, &txt_coords); + 15d6c: 4b69 ldr r3, [pc, #420] ; (15f14 ) + 15d6e: a908 add r1, sp, #32 + 15d70: 4628 mov r0, r5 + 15d72: 4798 blx r3 + bool is_common = _lv_area_intersect(&txt_clip, clip_area, &txt_coords); + 15d74: 4b68 ldr r3, [pc, #416] ; (15f18 ) + 15d76: aa08 add r2, sp, #32 + 15d78: 4641 mov r1, r8 + 15d7a: a80a add r0, sp, #40 ; 0x28 + 15d7c: 4798 blx r3 + if(!is_common) return LV_DESIGN_RES_OK; + 15d7e: 2800 cmp r0, #0 + 15d80: f000 80b5 beq.w 15eee + lv_label_align_t align = lv_label_get_align(label); + 15d84: 4b65 ldr r3, [pc, #404] ; (15f1c ) + 15d86: 4628 mov r0, r5 + 15d88: 4798 blx r3 + if(ext->recolor != 0) flag |= LV_TXT_FLAG_RECOLOR; + 15d8a: 7c23 ldrb r3, [r4, #16] + lv_txt_flag_t flag = LV_TXT_FLAG_NONE; + 15d8c: f3c3 1680 ubfx r6, r3, #6, #1 + if(ext->expand != 0) flag |= LV_TXT_FLAG_EXPAND; + 15d90: 061a lsls r2, r3, #24 + 15d92: bf48 it mi + 15d94: f046 0602 orrmi.w r6, r6, #2 + if(ext->long_mode == LV_LABEL_LONG_EXPAND) flag |= LV_TXT_FLAG_FIT; + 15d98: 075b lsls r3, r3, #29 + 15d9a: bf08 it eq + 15d9c: f046 0610 orreq.w r6, r6, #16 + if(align == LV_LABEL_ALIGN_CENTER) flag |= LV_TXT_FLAG_CENTER; + 15da0: 2801 cmp r0, #1 + 15da2: f040 80a8 bne.w 15ef6 + 15da6: f046 0604 orr.w r6, r6, #4 + lv_draw_label_dsc_init(&label_draw_dsc); + 15daa: 4b5d ldr r3, [pc, #372] ; (15f20 ) + 15dac: a80c add r0, sp, #48 ; 0x30 + 15dae: 4798 blx r3 + label_draw_dsc.sel_start = lv_label_get_text_sel_start(label); + 15db0: 4b5c ldr r3, [pc, #368] ; (15f24 ) + 15db2: 4628 mov r0, r5 + 15db4: 4798 blx r3 + label_draw_dsc.sel_end = lv_label_get_text_sel_end(label); + 15db6: 4b5c ldr r3, [pc, #368] ; (15f28 ) + label_draw_dsc.sel_start = lv_label_get_text_sel_start(label); + 15db8: f8ad 003e strh.w r0, [sp, #62] ; 0x3e + label_draw_dsc.sel_end = lv_label_get_text_sel_end(label); + 15dbc: 4628 mov r0, r5 + 15dbe: 4798 blx r3 + label_draw_dsc.ofs_x = ext->offset.x; + 15dc0: 89a3 ldrh r3, [r4, #12] + 15dc2: f8ad 3042 strh.w r3, [sp, #66] ; 0x42 + label_draw_dsc.ofs_y = ext->offset.y; + 15dc6: 89e3 ldrh r3, [r4, #14] + label_draw_dsc.sel_end = lv_label_get_text_sel_end(label); + 15dc8: f8ad 0040 strh.w r0, [sp, #64] ; 0x40 + label_draw_dsc.ofs_y = ext->offset.y; + 15dcc: f8ad 3044 strh.w r3, [sp, #68] ; 0x44 + lv_obj_init_draw_label_dsc(label, LV_LABEL_PART_MAIN, &label_draw_dsc); + 15dd0: aa0c add r2, sp, #48 ; 0x30 + 15dd2: 4b56 ldr r3, [pc, #344] ; (15f2c ) + label_draw_dsc.flag = flag; + 15dd4: f88d 6047 strb.w r6, [sp, #71] ; 0x47 + lv_obj_init_draw_label_dsc(label, LV_LABEL_PART_MAIN, &label_draw_dsc); + 15dd8: 2100 movs r1, #0 + 15dda: 4628 mov r0, r5 + 15ddc: 4798 blx r3 + if((ext->long_mode == LV_LABEL_LONG_SROLL || ext->long_mode == LV_LABEL_LONG_SROLL_CIRC) && + 15dde: 7c23 ldrb r3, [r4, #16] + 15de0: f003 0207 and.w r2, r3, #7 + 15de4: 3a03 subs r2, #3 + 15de6: 2a01 cmp r2, #1 + 15de8: d824 bhi.n 15e34 + (ext->align == LV_LABEL_ALIGN_CENTER || ext->align == LV_LABEL_ALIGN_RIGHT)) { + 15dea: f003 0330 and.w r3, r3, #48 ; 0x30 + if((ext->long_mode == LV_LABEL_LONG_SROLL || ext->long_mode == LV_LABEL_LONG_SROLL_CIRC) && + 15dee: 2b10 cmp r3, #16 + 15df0: d001 beq.n 15df6 + (ext->align == LV_LABEL_ALIGN_CENTER || ext->align == LV_LABEL_ALIGN_RIGHT)) { + 15df2: 2b20 cmp r3, #32 + 15df4: d11e bne.n 15e34 + _lv_txt_get_size(&size, ext->text, label_draw_dsc.font, label_draw_dsc.letter_space, label_draw_dsc.line_space, + 15df6: f647 4318 movw r3, #31768 ; 0x7c18 + 15dfa: 9301 str r3, [sp, #4] + 15dfc: f9bd 303a ldrsh.w r3, [sp, #58] ; 0x3a + 15e00: 9300 str r3, [sp, #0] + 15e02: 9602 str r6, [sp, #8] + 15e04: f9bd 303c ldrsh.w r3, [sp, #60] ; 0x3c + 15e08: 9a0d ldr r2, [sp, #52] ; 0x34 + 15e0a: 6821 ldr r1, [r4, #0] + 15e0c: 4d48 ldr r5, [pc, #288] ; (15f30 ) + 15e0e: a805 add r0, sp, #20 + 15e10: 47a8 blx r5 + return (lv_coord_t)(area_p->x2 - area_p->x1 + 1); + 15e12: f8bd 3024 ldrh.w r3, [sp, #36] ; 0x24 + 15e16: f8bd 2020 ldrh.w r2, [sp, #32] + 15e1a: 3301 adds r3, #1 + 15e1c: 1a9b subs r3, r3, r2 + if(size.x > lv_area_get_width(&txt_coords)) { + 15e1e: f9bd 2014 ldrsh.w r2, [sp, #20] + 15e22: b21b sxth r3, r3 + 15e24: 429a cmp r2, r3 + label_draw_dsc.flag &= ~LV_TXT_FLAG_CENTER; + 15e26: bfc2 ittt gt + 15e28: f89d 3047 ldrbgt.w r3, [sp, #71] ; 0x47 + 15e2c: f023 030c bicgt.w r3, r3, #12 + 15e30: f88d 3047 strbgt.w r3, [sp, #71] ; 0x47 + lv_draw_label(&txt_coords, &txt_clip, &label_draw_dsc, ext->text, hint); + 15e34: f04f 0900 mov.w r9, #0 + 15e38: f8cd 9000 str.w r9, [sp] + 15e3c: 6823 ldr r3, [r4, #0] + 15e3e: f8df 80f8 ldr.w r8, [pc, #248] ; 15f38 + 15e42: aa0c add r2, sp, #48 ; 0x30 + 15e44: a90a add r1, sp, #40 ; 0x28 + 15e46: a808 add r0, sp, #32 + 15e48: 47c0 blx r8 + if(ext->long_mode == LV_LABEL_LONG_SROLL_CIRC) { + 15e4a: 7c23 ldrb r3, [r4, #16] + 15e4c: f003 0307 and.w r3, r3, #7 + 15e50: 2b04 cmp r3, #4 + 15e52: d14c bne.n 15eee + _lv_txt_get_size(&size, ext->text, label_draw_dsc.font, label_draw_dsc.letter_space, label_draw_dsc.line_space, + 15e54: f647 4318 movw r3, #31768 ; 0x7c18 + 15e58: 9301 str r3, [sp, #4] + 15e5a: f9bd 303a ldrsh.w r3, [sp, #58] ; 0x3a + 15e5e: 9300 str r3, [sp, #0] + 15e60: 9602 str r6, [sp, #8] + 15e62: f9bd 303c ldrsh.w r3, [sp, #60] ; 0x3c + 15e66: 9a0d ldr r2, [sp, #52] ; 0x34 + 15e68: 6821 ldr r1, [r4, #0] + 15e6a: 4d31 ldr r5, [pc, #196] ; (15f30 ) + 15e6c: a805 add r0, sp, #20 + 15e6e: 47a8 blx r5 + 15e70: f8bd 2024 ldrh.w r2, [sp, #36] ; 0x24 + 15e74: f8bd 1020 ldrh.w r1, [sp, #32] + if(size.x > lv_area_get_width(&txt_coords)) { + 15e78: f9bd 3014 ldrsh.w r3, [sp, #20] + 15e7c: 3201 adds r2, #1 + 15e7e: 1a52 subs r2, r2, r1 + 15e80: b212 sxth r2, r2 + 15e82: 4293 cmp r3, r2 + 15e84: dd16 ble.n 15eb4 + label_draw_dsc.ofs_x = ext->offset.x + size.x + + 15e86: 89a2 ldrh r2, [r4, #12] + lv_font_get_glyph_width(label_draw_dsc.font, ' ', ' ') * LV_LABEL_WAIT_CHAR_COUNT; + 15e88: 980d ldr r0, [sp, #52] ; 0x34 + label_draw_dsc.ofs_x = ext->offset.x + size.x + + 15e8a: 4413 add r3, r2 + lv_font_get_glyph_width(label_draw_dsc.font, ' ', ' ') * LV_LABEL_WAIT_CHAR_COUNT; + 15e8c: 2220 movs r2, #32 + 15e8e: 4611 mov r1, r2 + label_draw_dsc.ofs_x = ext->offset.x + size.x + + 15e90: b29d uxth r5, r3 + lv_font_get_glyph_width(label_draw_dsc.font, ' ', ' ') * LV_LABEL_WAIT_CHAR_COUNT; + 15e92: 4b28 ldr r3, [pc, #160] ; (15f34 ) + 15e94: 4798 blx r3 + label_draw_dsc.ofs_y = ext->offset.y; + 15e96: 89e3 ldrh r3, [r4, #14] + lv_draw_label(&txt_coords, &txt_clip, &label_draw_dsc, ext->text, hint); + 15e98: f8cd 9000 str.w r9, [sp] + label_draw_dsc.ofs_x = ext->offset.x + size.x + + 15e9c: eb00 0040 add.w r0, r0, r0, lsl #1 + 15ea0: 4405 add r5, r0 + label_draw_dsc.ofs_y = ext->offset.y; + 15ea2: f8ad 3044 strh.w r3, [sp, #68] ; 0x44 + lv_draw_label(&txt_coords, &txt_clip, &label_draw_dsc, ext->text, hint); + 15ea6: aa0c add r2, sp, #48 ; 0x30 + 15ea8: 6823 ldr r3, [r4, #0] + label_draw_dsc.ofs_x = ext->offset.x + size.x + + 15eaa: f8ad 5042 strh.w r5, [sp, #66] ; 0x42 + lv_draw_label(&txt_coords, &txt_clip, &label_draw_dsc, ext->text, hint); + 15eae: a90a add r1, sp, #40 ; 0x28 + 15eb0: a808 add r0, sp, #32 + 15eb2: 47c0 blx r8 + return (lv_coord_t)(area_p->y2 - area_p->y1 + 1); + 15eb4: f8bd 3026 ldrh.w r3, [sp, #38] ; 0x26 + 15eb8: f8bd 1022 ldrh.w r1, [sp, #34] ; 0x22 + if(size.y > lv_area_get_height(&txt_coords)) { + 15ebc: f9bd 2016 ldrsh.w r2, [sp, #22] + 15ec0: 3301 adds r3, #1 + 15ec2: 1a5b subs r3, r3, r1 + 15ec4: b21b sxth r3, r3 + 15ec6: 429a cmp r2, r3 + 15ec8: dd11 ble.n 15eee + label_draw_dsc.ofs_x = ext->offset.x; + 15eca: 89a3 ldrh r3, [r4, #12] + 15ecc: f8ad 3042 strh.w r3, [sp, #66] ; 0x42 + 15ed0: 9b0d ldr r3, [sp, #52] ; 0x34 + label_draw_dsc.ofs_y = ext->offset.y + size.y + lv_font_get_line_height(label_draw_dsc.font); + 15ed2: 891b ldrh r3, [r3, #8] + 15ed4: 441a add r2, r3 + 15ed6: 89e3 ldrh r3, [r4, #14] + 15ed8: 441a add r2, r3 + lv_draw_label(&txt_coords, &txt_clip, &label_draw_dsc, ext->text, hint); + 15eda: 2300 movs r3, #0 + 15edc: 9300 str r3, [sp, #0] + 15ede: 6823 ldr r3, [r4, #0] + label_draw_dsc.ofs_y = ext->offset.y + size.y + lv_font_get_line_height(label_draw_dsc.font); + 15ee0: f8ad 2044 strh.w r2, [sp, #68] ; 0x44 + lv_draw_label(&txt_coords, &txt_clip, &label_draw_dsc, ext->text, hint); + 15ee4: 4c14 ldr r4, [pc, #80] ; (15f38 ) + 15ee6: aa0c add r2, sp, #48 ; 0x30 + 15ee8: a90a add r1, sp, #40 ; 0x28 + 15eea: a808 add r0, sp, #32 + 15eec: 47a0 blx r4 +} + 15eee: 4638 mov r0, r7 + 15ef0: b029 add sp, #164 ; 0xa4 + 15ef2: e8bd 83f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, pc} + if(align == LV_LABEL_ALIGN_RIGHT) flag |= LV_TXT_FLAG_RIGHT; + 15ef6: 2802 cmp r0, #2 + 15ef8: bf08 it eq + 15efa: f046 0608 orreq.w r6, r6, #8 + 15efe: e754 b.n 15daa + return LV_DESIGN_RES_OK; + 15f00: 2700 movs r7, #0 + 15f02: e7f4 b.n 15eee + 15f04: 00003fa9 .word 0x00003fa9 + 15f08: 00009ba1 .word 0x00009ba1 + 15f0c: 000042a9 .word 0x000042a9 + 15f10: 00009bed .word 0x00009bed + 15f14: 00014c8d .word 0x00014c8d + 15f18: 0000de8d .word 0x0000de8d + 15f1c: 00014dfd .word 0x00014dfd + 15f20: 00007845 .word 0x00007845 + 15f24: 00015c59 .word 0x00015c59 + 15f28: 00015ca1 .word 0x00015ca1 + 15f2c: 000047e5 .word 0x000047e5 + 15f30: 0001019d .word 0x0001019d + 15f34: 0000d175 .word 0x0000d175 + 15f38: 00007875 .word 0x00007875 + 15f3c: 00003711 .word 0x00003711 + +00015f40 <__aeabi_uldivmod>: + 15f40: b953 cbnz r3, 15f58 <__aeabi_uldivmod+0x18> + 15f42: b94a cbnz r2, 15f58 <__aeabi_uldivmod+0x18> + 15f44: 2900 cmp r1, #0 + 15f46: bf08 it eq + 15f48: 2800 cmpeq r0, #0 + 15f4a: bf1c itt ne + 15f4c: f04f 31ff movne.w r1, #4294967295 ; 0xffffffff + 15f50: f04f 30ff movne.w r0, #4294967295 ; 0xffffffff + 15f54: f000 b978 b.w 16248 <__aeabi_idiv0> + 15f58: f1ad 0c08 sub.w ip, sp, #8 + 15f5c: e96d ce04 strd ip, lr, [sp, #-16]! + 15f60: f000 f806 bl 15f70 <__udivmoddi4> + 15f64: f8dd e004 ldr.w lr, [sp, #4] + 15f68: e9dd 2302 ldrd r2, r3, [sp, #8] + 15f6c: b004 add sp, #16 + 15f6e: 4770 bx lr + +00015f70 <__udivmoddi4>: + 15f70: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 15f74: 9d08 ldr r5, [sp, #32] + 15f76: 460e mov r6, r1 + 15f78: 4604 mov r4, r0 + 15f7a: 460f mov r7, r1 + 15f7c: 2b00 cmp r3, #0 + 15f7e: d14a bne.n 16016 <__udivmoddi4+0xa6> + 15f80: 428a cmp r2, r1 + 15f82: 4694 mov ip, r2 + 15f84: d965 bls.n 16052 <__udivmoddi4+0xe2> + 15f86: fab2 f282 clz r2, r2 + 15f8a: b142 cbz r2, 15f9e <__udivmoddi4+0x2e> + 15f8c: f1c2 0320 rsb r3, r2, #32 + 15f90: 4097 lsls r7, r2 + 15f92: fa20 f303 lsr.w r3, r0, r3 + 15f96: fa0c fc02 lsl.w ip, ip, r2 + 15f9a: 431f orrs r7, r3 + 15f9c: 4094 lsls r4, r2 + 15f9e: ea4f 4e1c mov.w lr, ip, lsr #16 + 15fa2: fa1f f68c uxth.w r6, ip + 15fa6: fbb7 f1fe udiv r1, r7, lr + 15faa: 0c23 lsrs r3, r4, #16 + 15fac: fb0e 7711 mls r7, lr, r1, r7 + 15fb0: ea43 4307 orr.w r3, r3, r7, lsl #16 + 15fb4: fb01 f006 mul.w r0, r1, r6 + 15fb8: 4298 cmp r0, r3 + 15fba: d90a bls.n 15fd2 <__udivmoddi4+0x62> + 15fbc: eb1c 0303 adds.w r3, ip, r3 + 15fc0: f101 37ff add.w r7, r1, #4294967295 ; 0xffffffff + 15fc4: f080 8120 bcs.w 16208 <__udivmoddi4+0x298> + 15fc8: 4298 cmp r0, r3 + 15fca: f240 811d bls.w 16208 <__udivmoddi4+0x298> + 15fce: 3902 subs r1, #2 + 15fd0: 4463 add r3, ip + 15fd2: 1a1b subs r3, r3, r0 + 15fd4: b2a4 uxth r4, r4 + 15fd6: fbb3 f0fe udiv r0, r3, lr + 15fda: fb0e 3310 mls r3, lr, r0, r3 + 15fde: ea44 4403 orr.w r4, r4, r3, lsl #16 + 15fe2: fb00 f606 mul.w r6, r0, r6 + 15fe6: 42a6 cmp r6, r4 + 15fe8: d90a bls.n 16000 <__udivmoddi4+0x90> + 15fea: eb1c 0404 adds.w r4, ip, r4 + 15fee: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff + 15ff2: f080 810b bcs.w 1620c <__udivmoddi4+0x29c> + 15ff6: 42a6 cmp r6, r4 + 15ff8: f240 8108 bls.w 1620c <__udivmoddi4+0x29c> + 15ffc: 4464 add r4, ip + 15ffe: 3802 subs r0, #2 + 16000: ea40 4001 orr.w r0, r0, r1, lsl #16 + 16004: 1ba4 subs r4, r4, r6 + 16006: 2100 movs r1, #0 + 16008: b11d cbz r5, 16012 <__udivmoddi4+0xa2> + 1600a: 40d4 lsrs r4, r2 + 1600c: 2300 movs r3, #0 + 1600e: e9c5 4300 strd r4, r3, [r5] + 16012: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 16016: 428b cmp r3, r1 + 16018: d908 bls.n 1602c <__udivmoddi4+0xbc> + 1601a: 2d00 cmp r5, #0 + 1601c: f000 80f1 beq.w 16202 <__udivmoddi4+0x292> + 16020: 2100 movs r1, #0 + 16022: e9c5 0600 strd r0, r6, [r5] + 16026: 4608 mov r0, r1 + 16028: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 1602c: fab3 f183 clz r1, r3 + 16030: 2900 cmp r1, #0 + 16032: d14a bne.n 160ca <__udivmoddi4+0x15a> + 16034: 42b3 cmp r3, r6 + 16036: d302 bcc.n 1603e <__udivmoddi4+0xce> + 16038: 4282 cmp r2, r0 + 1603a: f200 8100 bhi.w 1623e <__udivmoddi4+0x2ce> + 1603e: 1a84 subs r4, r0, r2 + 16040: eb66 0203 sbc.w r2, r6, r3 + 16044: 2001 movs r0, #1 + 16046: 4617 mov r7, r2 + 16048: 2d00 cmp r5, #0 + 1604a: d0e2 beq.n 16012 <__udivmoddi4+0xa2> + 1604c: e9c5 4700 strd r4, r7, [r5] + 16050: e7df b.n 16012 <__udivmoddi4+0xa2> + 16052: b902 cbnz r2, 16056 <__udivmoddi4+0xe6> + 16054: deff udf #255 ; 0xff + 16056: fab2 f282 clz r2, r2 + 1605a: 2a00 cmp r2, #0 + 1605c: f040 8094 bne.w 16188 <__udivmoddi4+0x218> + 16060: eba1 030c sub.w r3, r1, ip + 16064: ea4f 471c mov.w r7, ip, lsr #16 + 16068: fa1f fe8c uxth.w lr, ip + 1606c: 2101 movs r1, #1 + 1606e: fbb3 f6f7 udiv r6, r3, r7 + 16072: fb07 3016 mls r0, r7, r6, r3 + 16076: 0c23 lsrs r3, r4, #16 + 16078: ea43 4300 orr.w r3, r3, r0, lsl #16 + 1607c: fb0e f006 mul.w r0, lr, r6 + 16080: 4298 cmp r0, r3 + 16082: d908 bls.n 16096 <__udivmoddi4+0x126> + 16084: eb1c 0303 adds.w r3, ip, r3 + 16088: f106 38ff add.w r8, r6, #4294967295 ; 0xffffffff + 1608c: d202 bcs.n 16094 <__udivmoddi4+0x124> + 1608e: 4298 cmp r0, r3 + 16090: f200 80d2 bhi.w 16238 <__udivmoddi4+0x2c8> + 16094: 4646 mov r6, r8 + 16096: 1a1b subs r3, r3, r0 + 16098: b2a4 uxth r4, r4 + 1609a: fbb3 f0f7 udiv r0, r3, r7 + 1609e: fb07 3310 mls r3, r7, r0, r3 + 160a2: ea44 4403 orr.w r4, r4, r3, lsl #16 + 160a6: fb0e fe00 mul.w lr, lr, r0 + 160aa: 45a6 cmp lr, r4 + 160ac: d908 bls.n 160c0 <__udivmoddi4+0x150> + 160ae: eb1c 0404 adds.w r4, ip, r4 + 160b2: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff + 160b6: d202 bcs.n 160be <__udivmoddi4+0x14e> + 160b8: 45a6 cmp lr, r4 + 160ba: f200 80ba bhi.w 16232 <__udivmoddi4+0x2c2> + 160be: 4618 mov r0, r3 + 160c0: eba4 040e sub.w r4, r4, lr + 160c4: ea40 4006 orr.w r0, r0, r6, lsl #16 + 160c8: e79e b.n 16008 <__udivmoddi4+0x98> + 160ca: f1c1 0720 rsb r7, r1, #32 + 160ce: 408b lsls r3, r1 + 160d0: fa22 fc07 lsr.w ip, r2, r7 + 160d4: ea4c 0c03 orr.w ip, ip, r3 + 160d8: fa06 fe01 lsl.w lr, r6, r1 + 160dc: fa20 f407 lsr.w r4, r0, r7 + 160e0: fa26 f307 lsr.w r3, r6, r7 + 160e4: ea44 040e orr.w r4, r4, lr + 160e8: fa00 f801 lsl.w r8, r0, r1 + 160ec: ea4f 401c mov.w r0, ip, lsr #16 + 160f0: ea4f 4914 mov.w r9, r4, lsr #16 + 160f4: fbb3 fef0 udiv lr, r3, r0 + 160f8: fa1f f68c uxth.w r6, ip + 160fc: fb00 331e mls r3, r0, lr, r3 + 16100: ea49 4303 orr.w r3, r9, r3, lsl #16 + 16104: fb0e f906 mul.w r9, lr, r6 + 16108: 4599 cmp r9, r3 + 1610a: fa02 f201 lsl.w r2, r2, r1 + 1610e: d90b bls.n 16128 <__udivmoddi4+0x1b8> + 16110: eb1c 0303 adds.w r3, ip, r3 + 16114: f10e 3aff add.w sl, lr, #4294967295 ; 0xffffffff + 16118: f080 8089 bcs.w 1622e <__udivmoddi4+0x2be> + 1611c: 4599 cmp r9, r3 + 1611e: f240 8086 bls.w 1622e <__udivmoddi4+0x2be> + 16122: f1ae 0e02 sub.w lr, lr, #2 + 16126: 4463 add r3, ip + 16128: eba3 0909 sub.w r9, r3, r9 + 1612c: b2a4 uxth r4, r4 + 1612e: fbb9 f3f0 udiv r3, r9, r0 + 16132: fb00 9913 mls r9, r0, r3, r9 + 16136: ea44 4409 orr.w r4, r4, r9, lsl #16 + 1613a: fb03 f606 mul.w r6, r3, r6 + 1613e: 42a6 cmp r6, r4 + 16140: d908 bls.n 16154 <__udivmoddi4+0x1e4> + 16142: eb1c 0404 adds.w r4, ip, r4 + 16146: f103 30ff add.w r0, r3, #4294967295 ; 0xffffffff + 1614a: d26c bcs.n 16226 <__udivmoddi4+0x2b6> + 1614c: 42a6 cmp r6, r4 + 1614e: d96a bls.n 16226 <__udivmoddi4+0x2b6> + 16150: 3b02 subs r3, #2 + 16152: 4464 add r4, ip + 16154: ea43 400e orr.w r0, r3, lr, lsl #16 + 16158: 1ba4 subs r4, r4, r6 + 1615a: fba0 e602 umull lr, r6, r0, r2 + 1615e: 42b4 cmp r4, r6 + 16160: 4673 mov r3, lr + 16162: 46b1 mov r9, r6 + 16164: d356 bcc.n 16214 <__udivmoddi4+0x2a4> + 16166: d053 beq.n 16210 <__udivmoddi4+0x2a0> + 16168: 2d00 cmp r5, #0 + 1616a: d06a beq.n 16242 <__udivmoddi4+0x2d2> + 1616c: ebb8 0203 subs.w r2, r8, r3 + 16170: eb64 0409 sbc.w r4, r4, r9 + 16174: fa22 f301 lsr.w r3, r2, r1 + 16178: fa04 f707 lsl.w r7, r4, r7 + 1617c: 431f orrs r7, r3 + 1617e: 40cc lsrs r4, r1 + 16180: e9c5 7400 strd r7, r4, [r5] + 16184: 2100 movs r1, #0 + 16186: e744 b.n 16012 <__udivmoddi4+0xa2> + 16188: f1c2 0120 rsb r1, r2, #32 + 1618c: fa20 f301 lsr.w r3, r0, r1 + 16190: fa0c fc02 lsl.w ip, ip, r2 + 16194: fa26 f101 lsr.w r1, r6, r1 + 16198: 4096 lsls r6, r2 + 1619a: 4333 orrs r3, r6 + 1619c: ea4f 471c mov.w r7, ip, lsr #16 + 161a0: fa1f fe8c uxth.w lr, ip + 161a4: fbb1 f0f7 udiv r0, r1, r7 + 161a8: fb07 1610 mls r6, r7, r0, r1 + 161ac: 0c19 lsrs r1, r3, #16 + 161ae: ea41 4106 orr.w r1, r1, r6, lsl #16 + 161b2: fb00 f60e mul.w r6, r0, lr + 161b6: 428e cmp r6, r1 + 161b8: fa04 f402 lsl.w r4, r4, r2 + 161bc: d908 bls.n 161d0 <__udivmoddi4+0x260> + 161be: eb1c 0101 adds.w r1, ip, r1 + 161c2: f100 38ff add.w r8, r0, #4294967295 ; 0xffffffff + 161c6: d230 bcs.n 1622a <__udivmoddi4+0x2ba> + 161c8: 428e cmp r6, r1 + 161ca: d92e bls.n 1622a <__udivmoddi4+0x2ba> + 161cc: 3802 subs r0, #2 + 161ce: 4461 add r1, ip + 161d0: 1b89 subs r1, r1, r6 + 161d2: b29b uxth r3, r3 + 161d4: fbb1 f6f7 udiv r6, r1, r7 + 161d8: fb07 1116 mls r1, r7, r6, r1 + 161dc: ea43 4301 orr.w r3, r3, r1, lsl #16 + 161e0: fb06 f10e mul.w r1, r6, lr + 161e4: 4299 cmp r1, r3 + 161e6: d908 bls.n 161fa <__udivmoddi4+0x28a> + 161e8: eb1c 0303 adds.w r3, ip, r3 + 161ec: f106 38ff add.w r8, r6, #4294967295 ; 0xffffffff + 161f0: d217 bcs.n 16222 <__udivmoddi4+0x2b2> + 161f2: 4299 cmp r1, r3 + 161f4: d915 bls.n 16222 <__udivmoddi4+0x2b2> + 161f6: 3e02 subs r6, #2 + 161f8: 4463 add r3, ip + 161fa: 1a5b subs r3, r3, r1 + 161fc: ea46 4100 orr.w r1, r6, r0, lsl #16 + 16200: e735 b.n 1606e <__udivmoddi4+0xfe> + 16202: 4629 mov r1, r5 + 16204: 4628 mov r0, r5 + 16206: e704 b.n 16012 <__udivmoddi4+0xa2> + 16208: 4639 mov r1, r7 + 1620a: e6e2 b.n 15fd2 <__udivmoddi4+0x62> + 1620c: 4618 mov r0, r3 + 1620e: e6f7 b.n 16000 <__udivmoddi4+0x90> + 16210: 45f0 cmp r8, lr + 16212: d2a9 bcs.n 16168 <__udivmoddi4+0x1f8> + 16214: ebbe 0302 subs.w r3, lr, r2 + 16218: eb66 060c sbc.w r6, r6, ip + 1621c: 3801 subs r0, #1 + 1621e: 46b1 mov r9, r6 + 16220: e7a2 b.n 16168 <__udivmoddi4+0x1f8> + 16222: 4646 mov r6, r8 + 16224: e7e9 b.n 161fa <__udivmoddi4+0x28a> + 16226: 4603 mov r3, r0 + 16228: e794 b.n 16154 <__udivmoddi4+0x1e4> + 1622a: 4640 mov r0, r8 + 1622c: e7d0 b.n 161d0 <__udivmoddi4+0x260> + 1622e: 46d6 mov lr, sl + 16230: e77a b.n 16128 <__udivmoddi4+0x1b8> + 16232: 4464 add r4, ip + 16234: 3802 subs r0, #2 + 16236: e743 b.n 160c0 <__udivmoddi4+0x150> + 16238: 3e02 subs r6, #2 + 1623a: 4463 add r3, ip + 1623c: e72b b.n 16096 <__udivmoddi4+0x126> + 1623e: 4608 mov r0, r1 + 16240: e702 b.n 16048 <__udivmoddi4+0xd8> + 16242: 4629 mov r1, r5 + 16244: e6e5 b.n 16012 <__udivmoddi4+0xa2> + 16246: bf00 nop + +00016248 <__aeabi_idiv0>: + 16248: 4770 bx lr + 1624a: bf00 nop + +0001624c <__libc_init_array>: + 1624c: b570 push {r4, r5, r6, lr} + 1624e: 4d0d ldr r5, [pc, #52] ; (16284 <__libc_init_array+0x38>) + 16250: 4c0d ldr r4, [pc, #52] ; (16288 <__libc_init_array+0x3c>) + 16252: 1b64 subs r4, r4, r5 + 16254: 10a4 asrs r4, r4, #2 + 16256: 2600 movs r6, #0 + 16258: 42a6 cmp r6, r4 + 1625a: d109 bne.n 16270 <__libc_init_array+0x24> + 1625c: 4d0b ldr r5, [pc, #44] ; (1628c <__libc_init_array+0x40>) + 1625e: 4c0c ldr r4, [pc, #48] ; (16290 <__libc_init_array+0x44>) + 16260: f00e fa2c bl 246bc <_init> + 16264: 1b64 subs r4, r4, r5 + 16266: 10a4 asrs r4, r4, #2 + 16268: 2600 movs r6, #0 + 1626a: 42a6 cmp r6, r4 + 1626c: d105 bne.n 1627a <__libc_init_array+0x2e> + 1626e: bd70 pop {r4, r5, r6, pc} + 16270: f855 3b04 ldr.w r3, [r5], #4 + 16274: 4798 blx r3 + 16276: 3601 adds r6, #1 + 16278: e7ee b.n 16258 <__libc_init_array+0xc> + 1627a: f855 3b04 ldr.w r3, [r5], #4 + 1627e: 4798 blx r3 + 16280: 3601 adds r6, #1 + 16282: e7f2 b.n 1626a <__libc_init_array+0x1e> + 16284: 000246c8 .word 0x000246c8 + 16288: 000246c8 .word 0x000246c8 + 1628c: 000246c8 .word 0x000246c8 + 16290: 000246cc .word 0x000246cc + +00016294 : + 16294: b510 push {r4, lr} + 16296: 3901 subs r1, #1 + 16298: 4402 add r2, r0 + 1629a: 4290 cmp r0, r2 + 1629c: d101 bne.n 162a2 + 1629e: 2000 movs r0, #0 + 162a0: e005 b.n 162ae + 162a2: 7803 ldrb r3, [r0, #0] + 162a4: f811 4f01 ldrb.w r4, [r1, #1]! + 162a8: 42a3 cmp r3, r4 + 162aa: d001 beq.n 162b0 + 162ac: 1b18 subs r0, r3, r4 + 162ae: bd10 pop {r4, pc} + 162b0: 3001 adds r0, #1 + 162b2: e7f2 b.n 1629a + +000162b4 : + 162b4: 440a add r2, r1 + 162b6: 4291 cmp r1, r2 + 162b8: f100 33ff add.w r3, r0, #4294967295 ; 0xffffffff + 162bc: d100 bne.n 162c0 + 162be: 4770 bx lr + 162c0: b510 push {r4, lr} + 162c2: f811 4b01 ldrb.w r4, [r1], #1 + 162c6: f803 4f01 strb.w r4, [r3, #1]! + 162ca: 4291 cmp r1, r2 + 162cc: d1f9 bne.n 162c2 + 162ce: bd10 pop {r4, pc} + +000162d0 : + 162d0: 4288 cmp r0, r1 + 162d2: b510 push {r4, lr} + 162d4: eb01 0402 add.w r4, r1, r2 + 162d8: d902 bls.n 162e0 + 162da: 4284 cmp r4, r0 + 162dc: 4623 mov r3, r4 + 162de: d807 bhi.n 162f0 + 162e0: 1e43 subs r3, r0, #1 + 162e2: 42a1 cmp r1, r4 + 162e4: d008 beq.n 162f8 + 162e6: f811 2b01 ldrb.w r2, [r1], #1 + 162ea: f803 2f01 strb.w r2, [r3, #1]! + 162ee: e7f8 b.n 162e2 + 162f0: 4402 add r2, r0 + 162f2: 4601 mov r1, r0 + 162f4: 428a cmp r2, r1 + 162f6: d100 bne.n 162fa + 162f8: bd10 pop {r4, pc} + 162fa: f813 4d01 ldrb.w r4, [r3, #-1]! + 162fe: f802 4d01 strb.w r4, [r2, #-1]! + 16302: e7f7 b.n 162f4 + +00016304 : + 16304: 4402 add r2, r0 + 16306: 4603 mov r3, r0 + 16308: 4293 cmp r3, r2 + 1630a: d100 bne.n 1630e + 1630c: 4770 bx lr + 1630e: f803 1b01 strb.w r1, [r3], #1 + 16312: e7f9 b.n 16308 + +00016314 : + 16314: f810 2b01 ldrb.w r2, [r0], #1 + 16318: f811 3b01 ldrb.w r3, [r1], #1 + 1631c: 2a01 cmp r2, #1 + 1631e: bf28 it cs + 16320: 429a cmpcs r2, r3 + 16322: d0f7 beq.n 16314 + 16324: 1ad0 subs r0, r2, r3 + 16326: 4770 bx lr + +00016328 : + 16328: 4603 mov r3, r0 + 1632a: f811 2b01 ldrb.w r2, [r1], #1 + 1632e: f803 2b01 strb.w r2, [r3], #1 + 16332: 2a00 cmp r2, #0 + 16334: d1f9 bne.n 1632a + 16336: 4770 bx lr + +00016338 : + 16338: 4603 mov r3, r0 + 1633a: f813 2b01 ldrb.w r2, [r3], #1 + 1633e: 2a00 cmp r2, #0 + 16340: d1fb bne.n 1633a + 16342: 1a18 subs r0, r3, r0 + 16344: 3801 subs r0, #1 + 16346: 4770 bx lr + 16348: 682f2e2e .word 0x682f2e2e + 1634c: 732f6c61 .word 0x732f6c61 + 16350: 682f6372 .word 0x682f6372 + 16354: 695f6c61 .word 0x695f6c61 + 16358: 00632e6f .word 0x00632e6f + 1635c: 682f2e2e .word 0x682f2e2e + 16360: 732f6c61 .word 0x732f6c61 + 16364: 682f6372 .word 0x682f6372 + 16368: 745f6c61 .word 0x745f6c61 + 1636c: 72656d69 .word 0x72656d69 + 16370: 632e .short 0x632e + 16372: 00 .byte 0x00 + 16373: 2e .byte 0x2e + 16374: 61682f2e .word 0x61682f2e + 16378: 74752f6c .word 0x74752f6c + 1637c: 2f736c69 .word 0x2f736c69 + 16380: 2f637273 .word 0x2f637273 + 16384: 6c697475 .word 0x6c697475 + 16388: 696c5f73 .word 0x696c5f73 + 1638c: 632e7473 .word 0x632e7473 + 16390: 00 .byte 0x00 + 16391: 2e .byte 0x2e + 16392: 2f2e .short 0x2f2e + 16394: 2f6c7068 .word 0x2f6c7068 + 16398: 63726573 .word 0x63726573 + 1639c: 682f6d6f .word 0x682f6d6f + 163a0: 735f6c70 .word 0x735f6c70 + 163a4: 6f637265 .word 0x6f637265 + 163a8: 00632e6d .word 0x00632e6d + 163ac: 40003000 .word 0x40003000 + 163b0: 40003400 .word 0x40003400 + 163b4: 41012000 .word 0x41012000 + 163b8: 41014000 .word 0x41014000 + 163bc: 43000000 .word 0x43000000 + 163c0: 43000400 .word 0x43000400 + 163c4: 43000800 .word 0x43000800 + 163c8: 43000c00 .word 0x43000c00 + +000163cc <_i2cms>: + 163cc: 00000003 00200014 00000100 000000ff ...... ......... + 163dc: 00d70000 07270400 ......'. + +000163e4 : + ... + 163f4: 2f2e2e00 2f6c6168 2f637273 5f6c6168 .../hal/src/hal_ + 16404: 72617375 73615f74 2e636e79 2e2e0063 usart_async.c... + 16414: 6c61682f 6974752f 732f736c 752f6372 /hal/utils/src/u + 16424: 736c6974 6e69725f 66756267 2e726566 tils_ringbuffer. + 16434: 2e2e0063 6c70682f 2f63742f 5f6c7068 c.../hpl/tc/hpl_ + 16444: 632e6374 00000000 40003800 40003c00 tc.c.....8.@.<.@ + 16454: 4101a000 4101c000 42001400 42001800 ...A...A...B...B + 16464: 43001400 43001800 ...C...C + +0001646c <_tcs>: + 1646c: 006b0000 00000308 00000000 00003a97 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00000000 .pp.....pJ.p.... + 1e5c8: 70707000 36364e4f 70703636 70707070 .pppON6666pppppp + 1e5d8: 70707070 00000070 70707000 70707070 ppppp....ppppppp + 1e5e8: 00707070 00000000 00000000 00000000 ppp............. + ... + 1e618: 00150000 00000000 00000000 00000000 ................ + 1e628: 70000000 48484870 4848fdfd 00007048 ...ppHHH..HHHp.. + ... + 1e644: 70000000 703b4f70 00000000 00000000 ...ppO;p........ + ... + 1e678: cb4a4800 00000000 70700000 36707070 .HJ.......ppppp6 + 1e688: 7070701f 70707070 70707070 00007070 .ppppppppppppp.. + 1e698: 00000000 70000000 00000000 00000000 .......p........ + ... + 1e6d0: 48700000 00000000 00000000 00000000 ..pH............ + 1e6e0: 00000000 48484870 4848fdfd 00007048 ....pHHH..HHHp.. + ... + 1e700: 364f1f70 00000070 00000000 00000000 p.O6p........... + ... + 1e730: fd480000 00000048 00000000 70707070 ..H.H.......pppp + 1e740: 70707070 70000070 70707070 00707070 ppppp..pppppppp. + ... + 1e79c: 48487070 48481515 00000070 00000000 ppHH..HHp....... + ... + 1e7b8: 4f4f7000 00000070 00000000 00000000 .pOOp........... + ... + 1e7e8: 48000000 00004848 00000000 70000000 ...HHH.........p + 1e7f8: 70707070 00000070 70707000 00000070 ppppp....pppp... + ... + 1e854: 48487000 48481515 00000070 00000000 .pHH..HHp....... + ... + 1e870: 4f1f0000 0000001f 00000000 00000000 ...O............ + ... + 1e8a0: 70000000 70484848 00000000 00000000 ...pHHHp........ + 1e8b0: 70000000 00000000 70000000 00000070 ...p.......pp... + ... + 1e90c: 48700000 48481515 00000070 00000000 ..pH..HHp....... + ... + 1e928: 36700000 00007036 00000000 00000000 ..p66p.......... + ... + 1e95c: 48484870 00000000 00000000 00000000 pHHH............ + ... + 1e9c4: 70000000 70481548 00000070 00000000 ...pH.Hpp....... + ... + 1e9e0: 70000000 00007036 00000000 00000000 ...p6p.......... + ... + 1ea0c: 2e000000 68732f2e 64657261 6968742f ...../shared/thi + 1ea1c: 61706472 2f797472 6c67766c 6372732f rdparty/lvgl/src + 1ea2c: 5f766c2f 65726f63 5f766c2f 75626564 /lv_core/lv_debu + 1ea3c: 00632e67 645f766c 67756265 6568635f g.c.lv_debug_che + 1ea4c: 735f6b63 203a7274 6f6e2061 53412d6e ck_str: a non-AS + 1ea5c: 20494943 72616863 73616820 70657220 CII char has rep + 1ea6c: 65746165 6f6d2064 74206572 206e6168 eated more than + 1ea7c: 445f564c 47554245 5254535f 58414d5f LV_DEBUG_STR_MAX + 1ea8c: 5045525f 20544145 656d6974 6c002973 _REPEAT times).l + 1ea9c: 65645f76 5f677562 63656863 74735f6b v_debug_check_st + 1eaac: 69203a72 6c61766e 63206469 20726168 r: invalid char + 1eabc: 74206e69 73206568 6e697274 3c282067 in the string (< + 1eacc: 20303120 756c6176 6c002965 65645f76 10 value).lv_de + 1eadc: 5f677562 63656863 74735f6b 73203a72 bug_check_str: s + 1eaec: 6e697274 73692067 6e6f6c20 20726567 tring is longer + 1eafc: 6e616874 5f564c20 55424544 54535f47 than LV_DEBUG_ST + 1eb0c: 414d5f52 454c5f58 4854474e R_MAX_LENGTH. + +0001eb19 <__func__.2>: + 1eb19: 645f766c 67756265 6568635f 735f6b63 lv_debug_check_s + 1eb29: tr. + +0001eb2c : + 1eb2c: 33323130 37363534 42413938 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69645f76 615f7073 67697373 63735f6e v_disp_assign_sc + 1ec3d: 6e656572 7274203a 6f742079 73736120 reen: try to ass + 1ec4d: 206e6769 6f6e2061 63732d6e 6e656572 ign a non-screen + 1ec5d: 6a626f20 00746365 645f766c 5f707369 object.lv_disp_ + 1ec6d: 5f746567 63616e69 65766974 6d69745f get_inactive_tim + 1ec7d: 6e203a65 6964206f 616c7073 65722079 e: no display re + 1ec8d: 74736967 64657265 5f766c00 70736964 gistered.lv_disp + 1ec9d: 6972745f 63615f67 69766974 203a7974 _trig_activity: + 1ecad: 64206f6e 6c707369 72207961 73696765 no display regis + 1ecbd: 65726574 766c0064 7369645f 65675f70 tered.lv_disp_ge + 1eccd: 65725f74 745f7266 3a6b7361 206f6e20 t_refr_task: no + 1ecdd: 70736964 2079616c 69676572 72657473 display register + 1eced: ed. + +0001ecf0 <__func__.6>: + 1ecf0: 645f766c 5f707369 5f746567 5f726373 lv_disp_get_scr_ + 1ed00: 00746361 act. + +0001ed04 <__func__.5>: + 1ed04: 645f766c 5f707369 5f746567 6579616c lv_disp_get_laye + 1ed14: 6f745f72 r_top. + +0001ed1a <__func__.4>: + 1ed1a: 645f766c 5f707369 5f746567 6579616c lv_disp_get_laye + 1ed2a: 79735f72 r_sys. + +0001ed30 <__func__.3>: + 1ed30: 645f766c 5f707369 69737361 735f6e67 lv_disp_assign_s + 1ed40: 65657263 creen. + +0001ed46 <__func__.2>: + 1ed46: 645f766c 5f707369 5f746567 63616e69 lv_disp_get_inac + 1ed56: 65766974 6d69745f tive_time. + +0001ed60 <__func__.1>: + 1ed60: 645f766c 5f707369 67697274 7463615f lv_disp_trig_act + 1ed70: 74697669 ivity. + +0001ed76 <__func__.0>: + 1ed76: 5f766c5f 70736964 7465675f 6665725f _lv_disp_get_ref + 1ed86: 61745f72 2e006b73 68732f2e 64657261 r_task.../shared + 1ed96: 6968742f 61706472 2f797472 6c67766c /thirdparty/lvgl + 1eda6: 6372732f 5f766c2f 65726f63 5f766c2f /src/lv_core/lv_ + 1edb6: 756f7267 00632e70 2074754f 6d20666f group.c.Out of m + 1edc6: 726f6d65 766c0079 6f72675f 615f7075 emory.lv_group_a + 1edd6: 6f5f6464 203a6a62 20656874 656a626f dd_obj: the obje + 1ede6: 69207463 6c612073 64616572 64612079 ct is already ad + 1edf6: 20646564 74206f74 20736968 756f7267 ded to this grou + 1ee06: 766c0070 6f72675f 615f7075 6f5f6464 p.lv_group_add_o + 1ee16: 203a6a62 69737361 6f206e67 63656a62 bj: assign objec + 1ee26: 6f742074 206e6120 6568746f 72672072 t to an other gr + 1ee36: 0070756f oup. + +0001ee3a <__func__.1>: + 1ee3a: 675f766c 70756f72 6572635f 00657461 lv_group_create. + +0001ee4a <__func__.0>: + 1ee4a: 675f766c 70756f72 6464615f 6a626f5f lv_group_add_obj + 1ee5a: 2f2e2e00 72616873 742f6465 64726968 .../shared/third + 1ee6a: 74726170 766c2f79 732f6c67 6c2f6372 party/lvgl/src/l + 1ee7a: 6f635f76 6c2f6572 626f5f76 00632e6a v_core/lv_obj.c. + 1ee8a: 695f766c 3a74696e 726c6120 79646165 lv_init: already + 1ee9a: 696e6920 00646574 695f766c 2074696e inited.lv_init + 1eeaa: 64616572 766c0079 6965645f 2074696e ready.lv_deinit + 1eeba: 656e6f64 4c554e00 6f70204c 65746e69 done.NULL pointe + 1eeca: 766c0072 7263735f 7465675f 7369645f r.lv_scr_get_dis + 1eeda: 73203a70 65657263 6f6e206e 6f662074 p: screen not fo + 1eeea: 00646e75 6f5f766c 735f6a62 625f7465 und.lv_obj_set_b + 1eefa: 5f657361 3a726964 766e6920 64696c61 ase_dir: invalid + 1ef0a: 73616220 69642065 766c0072 6a626f5f base dir.lv_obj + 1ef1a: 656c635f 735f6e61 656c7974 73696c5f _clean_style_lis + 1ef2a: 63203a74 74276e61 6e696620 74732064 t: can't find st + 1ef3a: 20656c79 68746977 61706020 00607472 yle with `part`. + 1ef4a: 6f5f766c 735f6a62 705f7465 203a736f lv_obj_set_pos: + 1ef5a: 20746f6e 6e616863 676e6967 736f7020 not changing pos + 1ef6a: 6f697469 666f206e 72637320 206e6565 ition of screen + 1ef7a: 656a626f 6c007463 626f5f76 64615f6a object.lv_obj_ad + 1ef8a: 74735f64 3a656c79 6e616320 66207427 d_style: can't f + 1ef9a: 20646e69 6c797473 69772065 60206874 ind style with ` + 1efaa: 65707974 766c0060 6a626f5f 6572635f type`.lv_obj_cre + 1efba: 3a657461 746f6e20 73696420 79616c70 ate: not display + 1efca: 65726320 64657461 206f7420 66206f73 created to so f + 1efda: 202e7261 70206f4e 6563616c 206f7420 ar. No place to + 1efea: 69737361 74206e67 6e206568 73207765 assign the new s + 1effa: 65657263 624f006e 7463656a 65726320 creen.Object cre + 1f00a: 20657461 64616572 61430079 2074276e ate ready.Can't + 1f01a: 20746573 20656874 65726170 6f20746e set the parent o + 1f02a: 20612066 65726373 43006e65 74276e61 f a screen.Can't + 1f03a: 74657320 72617020 20746e65 4e203d3d set parent == N + 1f04a: 204c4c55 61206f74 626f206e 7463656a ULL to an object + 1f05a: 5f766c00 006a626f .lv_obj. + +0001f062 <__func__.90>: + 1f062: 695f766c 0074696e lv_init. + +0001f06a <__func__.89>: + 1f06a: 645f766c 696e6965 lv_deinit. + +0001f074 <__func__.86>: + 1f074: 6f5f766c 645f6a62 615f6c65 636e7973 lv_obj_del_async + ... + +0001f085 <__func__.69>: + 1f085: 6f5f766c 735f6a62 615f7465 5f6f7475 lv_obj_set_auto_ + 1f095: 6c616572 006e6769 realign. + +0001f09d <__func__.68>: + 1f09d: 6f5f766c 735f6a62 655f7465 635f7478 lv_obj_set_ext_c + 1f0ad: 6b63696c 6572615f lick_area. + +0001f0b7 <__func__.62>: + 1f0b7: 6f5f766c 735f6a62 615f7465 685f7664 lv_obj_set_adv_h + 1f0c7: 65747469 ittest. + +0001f0ce <__func__.61>: + 1f0ce: 6f5f766c 735f6a62 635f7465 6b63696c lv_obj_set_click + ... + +0001f0df <__func__.60>: + 1f0df: 6f5f766c 735f6a62 745f7465 lv_obj_set_top. + +0001f0ee <__func__.59>: + 1f0ee: 6f5f766c 735f6a62 645f7465 00676172 lv_obj_set_drag. + +0001f0fe <__func__.58>: + 1f0fe: 6f5f766c 735f6a62 645f7465 5f676172 lv_obj_set_drag_ + 1f10e: 00726964 dir. + +0001f112 <__func__.57>: + 1f112: 6f5f766c 735f6a62 645f7465 5f676172 lv_obj_set_drag_ + 1f122: 6f726874 throw. + +0001f128 <__func__.56>: + 1f128: 6f5f766c 735f6a62 645f7465 5f676172 lv_obj_set_drag_ + 1f138: 65726170 parent. + +0001f13f <__func__.55>: + 1f13f: 6f5f766c 735f6a62 705f7465 6e657261 lv_obj_set_paren + 1f14f: 76655f74 00746e65 t_event. + +0001f157 <__func__.53>: + 1f157: 6f5f766c 615f6a62 705f6464 65746f72 lv_obj_add_prote + 1f167: ct. + +0001f16a <__func__.52>: + 1f16a: 6f5f766c 635f6a62 7261656c 6f72705f lv_obj_clear_pro + 1f17a: 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65672074 6d692074 20656761 can't get image + 1fdbe: 6f666e69 5f766c00 5f676d69 69736564 info.lv_img_desi + 1fdce: 203a6e67 67616d69 6f732065 65637275 gn: image source + 1fdde: 70797420 73692065 6b6e7520 6e776f6e type is unknown + 1fdee: ffff0000 .... + +0001fdf2 <__func__.0>: + 1fdf2: 77617264 7461705f 6e726574 22110000 draw_pattern..." + 1fe02: 66554433 aa998877 eeddccbb 3DUfw........ + +0001fe0f <__func__.0>: + 1fe0f: 695f766c 625f676d 735f6675 705f7465 lv_img_buf_set_p + 1fe1f: 74656c61 2e006574 68732f2e 64657261 alette.../shared + 1fe2f: 6968742f 61706472 2f797472 6c67766c /thirdparty/lvgl + 1fe3f: 6372732f 5f766c2f 77617264 5f766c2f /src/lv_draw/lv_ + 1fe4f: 5f676d69 68636163 00632e65 695f766c img_cache.c.lv_i + 1fe5f: 635f676d 65686361 65706f5f 74203a6e mg_cache_open: t + 1fe6f: 63206568 65686361 7a697320 73692065 he cache size is + 1fe7f: 69003020 6567616d 61726420 63203a77 0.image draw: c + 1fe8f: 65686361 73696d20 63202c73 65736f6c ache miss, close + 1fe9f: 646e6120 75657220 61206573 6e65206e and reuse an en + 1feaf: 00797274 67616d69 72642065 203a7761 try.image draw: + 1febf: 68636163 696d2065 202c7373 68636163 cache miss, cach + 1fecf: 74206465 6e61206f 706d6520 65207974 ed to an empty e + 1fedf: 7972746e 616d4900 64206567 20776172 ntry.Image draw + 1feef: 6e6e6163 6f20746f 206e6570 20656874 cannot open the + 1feff: 67616d69 65722065 72756f73 image resource. + +0001ff0e <__func__.1>: + 1ff0e: 5f766c5f 5f676d69 68636163 706f5f65 _lv_img_cache_op + 1ff1e: en. + +0001ff21 <__func__.0>: + 1ff21: 695f766c 635f676d 65686361 7465735f lv_img_cache_set + 1ff31: 7a69735f 2e2e0065 6168732f 2f646572 _size.../shared/ + 1ff41: 72696874 72617064 6c2f7974 2f6c6776 thirdparty/lvgl/ + 1ff51: 2f637273 645f766c 2f776172 695f766c src/lv_draw/lv_i + 1ff61: 645f676d 646f6365 632e7265 616d4900 mg_decoder.c.Ima + 1ff71: 67206567 69207465 206f666e 20746567 ge get info get + 1ff81: 64616572 6c696620 65682065 72656461 read file header + 1ff91: 616d4900 67206567 69207465 206f666e .Image get info + 1ffa1: 6e756f66 6e752064 776f6e6b 7273206e found unknown sr + 1ffb1: 79742063 42006570 746c6975 206e692d c type.Built-in + 1ffc1: 67616d69 65642065 65646f63 65732072 image decoder se + 1ffd1: 66206b65 656c6961 75420064 2d746c69 ek failed.Built- + 1ffe1: 69206e69 6567616d 63656420 7265646f in image decoder + 1fff1: 61657220 61662064 64656c69 69754200 read failed.Bui + 20001: 692d746c 6d69206e 20656761 6f636564 lt-in image deco + 20011: 20726564 64616572 746f6e20 70757320 der read not sup + 20021: 74726f70 68742073 6f632065 20726f6c ports the color + 20031: 6d726f66 62007461 42006e69 746c6975 format.bin.Built + 20041: 206e692d 67616d69 65642065 65646f63 -in image decode + 20051: 61632072 2074276e 6e65706f 65687420 r can't open the + 20061: 6c696620 6d690065 65645f67 65646f63 file.img_decode + 20071: 75625f72 5f746c69 6f5f6e69 3a6e6570 r_built_in_open: + 20081: 74756f20 20666f20 6f6d656d 49007972 out of memory.I + 20091: 6567616d 63656420 7265646f 65706f20 mage decoder ope + 200a1: 75203a6e 6f6e6b6e 63206e77 726f6c6f n: unknown color + 200b1: 726f6620 0074616d 695f766c 645f676d format.lv_img_d + 200c1: 646f6365 695f7265 3a74696e 74756f20 ecoder_init: out + 200d1: 20666f20 6f6d656d of memory. + +000200dc <__func__.3>: + 200dc: 695f766c 645f676d 646f6365 625f7265 lv_img_decoder_b + 200ec: 746c6975 5f6e695f 6f666e69 uilt_in_info. + +000200f9 <__func__.0>: + 200f9: 695f766c 645f676d 646f6365 625f7265 lv_img_decoder_b + 20109: 746c6975 5f6e695f 656e696c 7572745f uilt_in_line_tru + 20119: 6f635f65 00726f6c 33221100 77665544 e_color..."3DUfw + 20129: bbaa9988 ffeeddcc ........ + +00020131 <__func__.1>: + 20131: 695f766c 645f676d 646f6365 625f7265 lv_img_decoder_b + 20141: 746c6975 5f6e695f 64616572 6e696c5f uilt_in_read_lin + 20151: e. + +00020153 <__func__.2>: + 20153: 695f766c 645f676d 646f6365 625f7265 lv_img_decoder_b + 20163: 746c6975 5f6e695f 6e65706f uilt_in_open. + +00020170 <__func__.4>: + 20170: 695f766c 645f676d 646f6365 635f7265 lv_img_decoder_c + 20180: 74616572 reate. + +00020186 <__func__.5>: + 20186: 5f766c5f 5f676d69 6f636564 5f726564 _lv_img_decoder_ + 20196: 74696e69 2f2e2e00 72616873 742f6465 init.../shared/t + 201a6: 64726968 74726170 766c2f79 732f6c67 hirdparty/lvgl/s + 201b6: 6c2f6372 6f665f76 6c2f746e 6f665f76 rc/lv_font/lv_fo + 201c6: 665f746e 745f746d 632e7478 nt_fmt_txt.c. + +000201d3 : + 201d3: 06040200 0f0d0b09 ........ + +000201db <__func__.0>: + 201db: 665f766c 5f746e6f 5f746567 6d746962 lv_font_get_bitm + 201eb: 665f7061 745f746d 00007478 ap_fmt_txt... + +000201f8 : + 201f8: 00020208 00020e50 00020db5 0000313d ....P.......=1.. + +00020208 : + 20208: 00000100 00000000 00000100 00000003 ................ + 20218: 00000200 00000000 00000000 00000000 ................ + 20228: 00010000 00000000 00000000 00000000 ................ + 20238: 000c0100 0000fa07 f1f20000 04060c02 ................ + 20248: 010d02f6 0008030b 00000000 00000000 ................ + 20258: 020f0000 000000fe 00000000 00000000 ................ + 20268: f8000500 00000000 0504fb00 00fd0000 ................ + 20278: fd0003fe fbfffd00 00000000 fd0000fd ................ + 20288: fd0000fc 0000fb00 00000000 fd000000 ................ + 20298: 00fc00fd 00e100f9 0500fb00 fb000008 ................ + 202a8: 05080303 000005fc 000000f1 00000000 ................ + 202b8: 00000000 000000f7 00000000 00000000 ................ + 202c8: f9000000 f600f3fd 000000fe 000a0100 ................ + 202d8: 01fffef8 0000fc00 0000edfe 00000000 ................ + 202e8: 00000000 0afeec00 00000000 00000000 ................ + 202f8: 00000000 000000f6 00000000 08000000 ................ + 20308: 00000300 000000fb 00000000 00000000 ................ + 20318: 00000000 020a0000 00000001 00000000 ................ + ... + 20348: 000000f7 00000000 00000000 00000000 ................ + 20358: 00000000 02000000 fd080305 fd050000 ................ + 20368: 0702ddf8 00fd0105 00080009 00e80008 ................ + 20378: 080008fd 000305fd 00fd0100 0014fc00 ................ + 20388: 00080014 0804030b f7000000 00000000 ................ + 20398: 0200fe01 02fbfdfb 0000fd00 0000f600 ................ + ... + 203b0: 0000ef00 00000000 00000000 00000000 ................ + 203c0: 00f20100 000000f0 1900fe00 0303fdfd ................ + 203d0: 03fd00fe 00f20000 00000000 00000000 ................ + 203e0: 00e70000 00000003 00000000 00000000 ................ + 203f0: 0f00f000 00f70000 e7ef0008 0008fbef ................ + 20400: 0300ef00 00fc00fa 00000000 00000000 ................ + 20410: 07000000 0000e108 00000000 00000000 ................ + 20420: 000c0000 00000002 02020000 ff00fbfd ................ + 20430: 0000fdff 000000fe 00fe00fb fa00fbfa ................ + 20440: 00fbf8f8 00fb00fb fe000000 00030000 ................ + 20450: 0100fd02 03000000 000000fe ff0303fe ................ + 20460: fb000000 0000ff00 01000000 00fe0300 ................ + 20470: 00fc00fd 0800fe00 00fd0000 00000000 ................ + 20480: fefe01ff 00fd0000 000000fd 00000000 ................ + 20490: ffff0000 00fdfd00 00000000 fe000001 ................ + 204a0: fdfdfd00 00000000 00000000 0000fe00 ................ + 204b0: fdfe0000 f800fc00 0005f8fe 0503fb00 ................ + 204c0: fffa0007 f4ff00fd f202fe03 01000003 ................ + 204d0: fef200f3 f300feea 00070500 00000003 ................ + 204e0: fb000100 00f800fd 00fd0000 00fd0000 ................ + 204f0: 00000000 ff00ffff 000000fd 00000000 ................ + 20500: fe00fdfd 0000fefd 000000fd 00000000 ................ + 20510: 00000000 fd00fefe fb00fe00 fd000003 ................ + 20520: 00030301 00000000 0000fe00 02000000 ................ + 20530: 00fd0000 00fdfefd 00000000 00020000 ................ + 20540: 000000fe 00fcfd00 fe0800fb 0000f801 ................ + 20550: f5f3f307 fe0003fb fb00fbef fb04fb00 ................ + 20560: 00f900f0 02ff0100 000300fe f300f6f8 ................ + 20570: f8fafbfa fbfff9fd 010002f9 0000fd00 ................ + 20580: 03000200 00000000 00000000 fd000000 ................ + 20590: ff00ff00 fafc00fd f800fffa 00000000 ................ + 205a0: 00fe0000 01000000 000000fe 00000003 ................ + 205b0: 00000000 00000c00 00000000 00000002 ................ + 205c0: 000000fd 00000000 00000000 000300fb ................ + ... + 205dc: 000000fe 000000fb 00f8f300 f3fc0000 ................ + 205ec: 03fd0000 0000f900 00000000 00000000 ................ + 205fc: fb0000fc 00000000 00000000 00000000 ................ + 2060c: 00fb0003 03000000 fbfb0200 fdfdfd00 ................ + 2061c: 00000000 00f80000 fdfc00fd f8fafa00 ................ + 2062c: 00fb00fe 000000f8 00001400 fd000001 ................ + 2063c: f5000300 00000000 08fbe800 00f5fe08 ................ + 2064c: f300fc03 ee03fdff 040003fd f8f7fcf7 ................ + 2065c: f10000f5 00000f00 000000ff f9fdffff ................ + 2066c: 00e8fff8 00000000 00000000 00000001 ................ + ... + 20688: ff00fd00 0000fcfd 00fd00fb 00000000 ................ + ... + 206a0: 00ff0000 050000fb fa0003ff f9fffe03 ................ + 206b0: fdfd00fd fcfc00fe fffe0000 00fdfcfe ................ + 206c0: 0300fd00 00fa00fe 00fb0000 fcfc00fc ................ + 206d0: 00000003 00000000 0003fb00 fdfe00fc ................ + 206e0: fefefef8 fffdfeff 00000000 fefefd00 ................ + 206f0: 00000000 fe00fe03 fe000000 fdfefefd ................ + 20700: 0a0200fe 00f900ff fd0005fe 0004fdf5 ................ + 20710: 03fcf400 fe0002fc fc00f8fe fc000001 ................ + 20720: 03000000 00fbfb03 fdfcfdfc 01fc00fd ................ + 20730: 0008fcfb 00000000 00000000 00000003 ................ + ... + 20754: 000000fc 00000000 00000000 00000000 ................ + ... + 20780: 000000fe 00000000 00000000 00000000 ................ + ... + 2079c: fdfe0000 00000000 00000000 00000000 ................ + 207ac: fd0000fc fdfd0000 00000000 000000fd ................ + 207bc: 0000ff00 fe000000 00000000 00fb00fc ................ + 207cc: 00f80000 0105fa02 0000f4fe f600fdfa ................ + 207dc: 0000f9fa f6f6fdf5 00f900f4 00fd1102 ................ + 207ec: fdfffdfa f7fbf9fc 00fdfaf6 0100fe00 ................ + 207fc: feee0000 f7fa0608 00f80100 05fdfef3 ................ + 2080c: 0001fde8 f3fdef00 0000edfd 010f00ee ................ + 2081c: 0000fe00 feff0000 ef00fef6 00000000 ................ + 2082c: 00fe00f8 00f4f9ff f8fcff00 00fe00fd ................ + 2083c: f4000000 fef8f8fd fcfdfafc f8fefb00 ................ + 2084c: fbfd00fc 0100fbfd 00f8fe00 00fb0005 ................ + 2085c: 03000000 0afb0200 fdfdfd00 00000000 ................ + 2086c: 00f80000 fdfc00fd f8fafa00 02fb00fe ................ + 2087c: 0000000a 00001400 fd000001 00000300 ................ + 2088c: 00000000 00ff0000 00000000 0000fbfe ................ + 2089c: ff000000 fd000000 fb0000fd fb0000fd ................ + 208ac: 00ff0400 00000000 00000100 05040000 ................ + 208bc: f800fe02 f80800fc 0afbfbf8 feea0305 ................ + 208cc: fd00fd05 00f7fd03 fefd03fd 0000fef8 ................ + 208dc: f9000508 07fdf200 fd01f6fd 0afdf8f8 ................ + 208ec: 00fc0003 080200f9 faf6f7fa ed010008 ................ + 208fc: fefc03fe f7fa00fa 00fefcfc fdfbfa00 ................ + 2090c: fd060800 fcf200f2 fff1f700 f9f8fcf8 ................ + 2091c: fd000007 00fefb00 0400fbfd 000003f8 ................ + 2092c: fafd00f2 faf8fefc f800faf8 f8fbfafd ................ + 2093c: 010000fd f800fc0c fbfd00fd f6f9f9fa ................ + 2094c: 0005fbfd fdf300fc f7f80502 fd08f8fb ................ + 2095c: 05fbe801 00f7fcfa fdfdf5f8 f8fbfdfe ................ + 2096c: 080000ff 00effe07 f606faf1 f5f7fbef ................ + 2097c: 0005f8f3 fd000000 fd030000 05fb0205 ................ + 2098c: fff80000 0100ff00 0000fe01 00000000 ................ + 2099c: 000000fd 01080200 0000fd00 fefe0000 ................ + 209ac: 000000fd 00000201 00020000 000a00fe ................ + 209bc: fd010105 00000500 00000200 00000000 ................ + 209cc: 00000000 07000800 00000000 00000000 ................ + 209dc: 00000000 00f10000 080004fd 03190000 ................ + 209ec: 0303fbfb 00f301fe 00f10c00 00000000 ................ + 209fc: 00000000 0aef0000 00000024 00000000 ........$....... + 20a0c: 00000000 0000f100 00000000 00000000 ................ + ... + 20a2c: fb0000fc 000000fe 00000000 00000000 ................ + ... + 20a44: 00f900fe 00000100 fefb2103 03f90708 .........!...... + 20a54: 03030000 000000fd 00000000 00000000 ................ + 20a64: 000007df 00000000 00000000 00000000 ................ + 20a74: f9000000 f9000000 00000000 0000fffa ................ + 20a84: fd00fa00 0000f400 00000000 00000000 ................ + 20a94: 0000ef00 00010000 00000000 0000fd00 ................ + 20aa4: 00fc00fb 000000f9 00fd03fc fafdf900 ................ + 20ab4: 00f90000 00f400fd eb0000fd f7fdf6fb ................ + 20ac4: 00ef0000 0000fff9 00000000 fbfc0000 ................ + 20ad4: 0000fcfe 00fa0000 05fd03fa fefafe00 ................ + 20ae4: fd00fbfc f902feff 000000ff 00fcfee9 ................ + 20af4: f4fe00fa fe0000fe 000000fe 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.............s.. + 227b4: 00fdffff 00000000 df000000 ffff73ff .............s.. + 227c4: fffdffff ffffa5ff ffffffff ffffa5ff ................ + 227d4: dfffffff ffff73ff 00fdffff 00000000 .....s.......... + 227e4: 00b10a00 00000000 00fcbf00 00000000 ................ + 227f4: 00fbff0b 00000000 1bc0ffbf 0b0000a0 ................ + 22804: cf00fcff bf0000fb bf00c0ff ff0bb0ff ................ + 22814: 0c0000fc ffbffbff 000000c0 fbffffcf ................ + 22824: 00000000 b0ffff0c 00000000 00fbbf00 ................ + 22834: 00000000 00b00b00 03000000 03000000 ................ + 22844: 0010fc08 fcfff81c f5ff1c10 ff2cfcff ..............,. + 22854: ffff05f5 0500f5ff 00f5ffff fdff1d00 ................ + 22864: ff1c0010 1c10fcff fcfff9ff 05f5ff1c ................ + 22874: f5dffcff d1ff0500 040000a4 000000a1 ................ + 22884: 0000e04f 10020000 1003f16f d05f0000 O.......o....._. + 22894: d13ff16f f1ff0300 fd5ff16f 40ff0d00 o.?.....o._....@ + 228a4: ff09f16f 00f74f70 cf00f16f 00f09fe0 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.I.............. + 230dc: 04000000 0000f8ef 0070ff4e ff1c0000 ........N.p..... + 230ec: ff04e869 e30400f7 fffe9f00 40ffcf80 i..............@ + 230fc: 0570ff0d 8fe0ffff ff0dd0ff ff2d00f7 ..p...........-. + 2310c: d0ff8fe0 00fcff04 cff8af00 7f0030ff .............0.. + 2311c: 060040ff 00f7ffff f4ff0800 ff3e0000 .@............>. + 2312c: 000000a0 82c8ff4d 00f7bf01 5a000000 ....M..........Z + 2313c: 0810fcdf 0000a0ff 00000000 fd4e0000 ..............N. + ... + 23154: 0000c802 d22d0000 00000000 00000000 ......-......... + 23164: 0000fbbf 00000000 ffff0500 00000050 ............P... + 23174: 0d000000 00d0ffff 00000000 ffff7f00 ................ + 23184: 000000f7 ff010000 10ff8dd8 00000000 ................ + 23194: 0aa0ff0a 0000a0ff ff3f0000 f3ff0bb0 ..........?..... + 231a4: 00000000 0cc0ffcf 0000fcff ffff0500 ................ + 231b4: ffff0dd0 0e000050 9ff9ffff 00e0ffff ....P........... + 231c4: ffff8f00 ffff2ee2 ff0200f8 0990ffff ................ + 231d4: 10ffffff ffffff0a ffff3ee3 ff0fa0ff .........>...... + 231e4: ffffffff f0ffffff ffffff08 ffffffff ................ + 231f4: 000080ff 00000000 00000000 00000000 ................ + 23204: 000000d8 00000000 ffff80ff ff070070 ............p... + 23214: fffff8ff ff6f00f6 8e78fdff e8ff15ff ......o...x..... + 23224: 0200e2ff 20fe4fe5 000020fe 00f3ff13 .....O. . ...... + 23234: 00000052 0031ff3f 02000052 205ef4ef R...?.1.R.....^ + 23244: 8e7820fe e8ff51ff ffffe2ff ff6f00f6 . x..Q........o. + 23254: fffffdff ff070070 0000f8ff 00000000 ....p........... + 23264: 000080ff 00000000 000000d8 00000000 ................ + ... + 2327c: 01000000 000010dd ff1d0000 000000d1 ................ + 2328c: fdffdf01 1d000010 d1ff99ff f9df0100 ................ + 2329c: 10fd9f00 0090ff1d bfd1ff09 000000f9 ................ + 232ac: 905ffb9f 09000000 000000f5 00000000 .._............. + 232bc: 00000000 5f000000 00000090 f9bff509 ......._........ + 232cc: 9f000000 90ff1dfb d1ff0900 00f9df01 ................ + 232dc: 0010fd9f ff99ff1d 010000d1 10fdffdf ................ + 232ec: 1d000000 0000d1ff dd010000 00000010 ................ + ... + 2330c: 00d11d00 00000000 df010000 ffef10fd ................ + 2331c: 00d0ffff d1ffff1d ffffffaf cfcf00f0 ................ + 2332c: 0000fcfc 00f00f00 b6f11f6b 0f000000 ........k....... + 2333c: 0f0000f0 000000f0 00f00f00 00f00f00 ................ + 2334c: 0f000000 0f0000f0 000000f0 b6f11f6b ............k... + 2335c: 00f00f00 cfcf0000 0f00fcfc faffffff ................ + 2336c: d1ffff1d ffff0d00 df01feff 000010fd ................ + 2337c: 00000000 00d11d00 00000000 00000000 ................ + 2338c: ff8f0000 0000e2ff ffff0000 0020feff .............. . + 2339c: ffff0000 ffffffff fffff8ff ffffffff ................ + 233ac: ffffffff ffffffff ffffffff ffffffff ................ + 233bc: ffffffff ffffffff ffffffff ffffffff ................ + 233cc: ffffffff ffffffff ffffffff ffffffff ................ + 233dc: ffffffff ffffffff ff8fffff ffffffff ................ + 233ec: 0000f8ff 00b00b00 00000000 00fbbf00 ................ + 233fc: 00000000 b0ffff0b 00000000 fbffffbf ................ + 2340c: 0b000000 ffffffff 4f0000b0 ffffffff ...........O.... + 2341c: 000000f4 00ffff00 00000000 00ffff00 ................ + 2342c: 00000000 00ffff00 00000000 00ffff00 ................ + 2343c: 00000000 00ffff00 ffdf0000 0ffddff0 ................ + 2344c: fffffdff 9f0000f9 ffffffff ffffffff ................ + 2345c: ffffffff f0ffffff ffdfffe0 ffffffff ................ + 2346c: 0000fdff 00000000 00000000 00000000 ................ + 2347c: 0062ea0a 00000000 f0ffff02 00000000 ..b............. + 2348c: ffff9f00 00000000 ffff0f00 000000d0 ................ + 2349c: ffff0200 000000fb ef030000 000070ff .............p.. + 234ac: 04000000 0000f2ff 00000000 0000fbbf ................ + 234bc: 00000000 0030ff6f 00000200 0090ff4f ....o.0.....O... + 234cc: 00f38f02 00d0ff6f e4ffff0a 00d1ffbf ....o........... + 234dc: ffffef00 00d1ffff ffff0a00 0090ffff ................ + 234ec: ff6f0000 0030fbff ff020000 000072db ..o...0......r.. + 234fc: 08000000 000080ee ff086106 2d0080ff .........a.....- + 2350c: 33efd0ff ff2e00fe 3ff30ef3 f3ff2ee0 ...3.......?.... + 2351c: ffff8f00 00f3ff6e ffff8e00 0000f3ff ....n........... + 2352c: ffef0200 000000f3 ffff2e00 08000030 ............0... + 2353c: ffffffef ff080030 ffeff6ff 33ef0030 ....0.......0..3 + 2354c: ffef02fe 3ff30e30 ffef02e0 f8ff8f30 ....0..?....0... + 2355c: fddf0200 00e88e00 10660000 ffdf0000 ..........f..... + 2356c: 00200dff ffffff00 0000e20f 0fffffff .. ............. + 2357c: fff0dffd 0020ffff fffff0ff ffffffff ...... ......... + 2358c: fffffff0 f0ffffff ffffffff fff0ffff ................ + 2359c: ffffffff fffff0ff ffffffff fffffff0 ................ + 235ac: f0ffffff ffffffff fff0ffff ffffffff ................ + 235bc: ffdff0ff fffdffff 000000f9 ffff0000 ................ + 235cc: 00ffffff ffffdf00 0000fdff ffffff8f ................ + 235dc: ff00c2ff ffffffff 00ff20fe ff010000 ......... ...... + 235ec: 0000ffe2 fcff0000 000000ff ffffff00 ................ + 235fc: 00000000 ffffffff ffffffff ffffffff ................ + 2360c: ffffffff 11fbffff ffffffbf 1f00f1ff ................ + 2361c: ffffffff ff1f00f1 fbffffff ffffbf11 ................ + 2362c: ffffffff 8fffffff ffffffff df00f8ff ................ + 2363c: 0000fdff fcffff01 ff030000 0000f7ff ................ + 2364c: f2ffff06 ff080000 0000d0ff ffffff0a ................ + 2365c: ff0cd0ff a0ffffff ffffff0e ff0d20ff ............. .. + 2366c: 00f8ffff ff0a0000 000000e0 0050ff0e ..............P. + 2367c: fc2f0000 00000000 0000f35f a09f0000 ../....._....... + 2368c: 00000000 000010df 00d70000 04000000 ................ + 2369c: 000040ee 99ffdf00 0000fdff ff99ffff .@.............. + 236ac: ff0000ff ffffffff ffff0000 00000090 ................ + 236bc: 0dffff00 200dffff ff0fffff ffe20fff ....... ........ + 236cc: ffff0fff fffffd0f 20ffff0f 0fffff00 ........... .... + 236dc: ffffffff ff0fffff ffffffff ffff0fff ................ + 236ec: ffdfffff ffffff0f 0f0000ff ffffffff ................ + 236fc: ff0f0000 00ffffff ffff0d00 0000fdff ................ + 2370c: 0000cc00 02000000 000030ff ffbf0100 .........0...... + 2371c: 000020fc ffffff1e 9f0000e1 f8ffffff . .............. + 2372c: ffef0000 00fdffff ffffff00 0100ffff ................ + 2373c: ffffffff ff0300ff ffffffff ffff0830 ............0... + 2374c: 80ffffff ffffff1e cfe1ffff ffffffff ................ + 2375c: ffcffcff ffffffff 000000fc 00000000 ................ + 2376c: ff0e0000 000000e0 40ee0400 ff8f0000 ...........@.... + 2377c: ffffffff fff8ffff ffffffff ffffffff ................ + 2378c: 0ff000ff 000ff000 f000ffff 0ff0000f ................ + 2379c: ffffff00 ffffffff ffffffff 888008f8 ................ + 237ac: ff8f8008 8008f8ff 8f800888 ffffffff ................ + 237bc: ffffffff 00ffffff 000000f0 ffff000f ................ + 237cc: 0000f000 ff000f00 ffffffff ffffffff ................ + 237dc: ffff8fff ffffffff 0000f8ff 00000000 ................ + ... + 237f4: 70af0300 00000000 ffcf0400 000000f0 ...p............ + 23804: ffdf0600 0000a0ff ffef1700 0030ffff ..............0. + 23814: ffff1800 00fcffff ffff2a00 f4ffffff .........*...... + 23824: ffff0800 ffffffff ff0f00d0 ffffffff ................ + 23834: 080060ff ffffffff 0000feff 00000000 .`.............. + 23844: 00f7ffff 00000000 f1ffff00 00000000 ................ + 23854: ffff0000 00000080 ff000000 000010ff ................ + 23864: 00000000 0000faff 00000000 00f2ff00 ................ + 23874: 00000000 808f0000 00000000 00000000 ................ + 23884: 00000000 f0ffffdf ffff00d2 20fef0ff ............... + 23894: f0ffffff ffffe2ff fdfff0ff f2ffffff ................ + 238a4: ffff0000 ffffffff ffffffff ffffffff ................ + 238b4: ffffffff ffffffff ffffffff ffffffff ................ + 238c4: ffffffff ffffffff ffffffff ffffffff ................ + 238d4: ffffffff ffffffff ffffffff ffdfffff ................ + 238e4: fdffffff 00000000 00000000 00000000 ................ + 238f4: feef9c04 000040c9 ffef0700 feffffff .....@.......... + 23904: df040070 8aa8fcff 40fdffcf 00d5ff6f p..........@o... + 23914: 5d000000 f6cff6ff 00000000 fc6f0000 ...]..........o. + 23924: 5a00301a 00a5fddf 0000a103 ffffff4d .0.Z........M... + 23934: 0000d4ff feff0500 ffef8aa8 01000050 ............P... + 23944: 000070df 0010fd07 00120000 21000000 .p.............! + 23954: 00000000 e44e0000 00000000 00000000 ......N......... + 23964: 0000feef 00000000 feef0000 00000000 ................ + 23974: 00000000 0000e44e ff8f0000 ffffffff ....N........... + 23984: 80ffffff ffffffff ffffffff 00fff0ff ................ + 23994: 00000000 fd0f0000 ffff0fff ffffffff ................ + 239a4: 0fffff0f ffffffff ff00ffff ffff0fff ................ + 239b4: ffffffff 0fffff00 ffffffff ff0fffff ................ + 239c4: 000000ff 00000000 fffffd0f ffffffff ................ + 239d4: f0ffffff ffffff8f ffffffff ff8f80ff ................ + 239e4: ffffffff 80ffffff ffffffff ffffffff ................ + 239f4: 00fff0ff 00000000 fd0f0000 ffff0fff ................ + 23a04: 00f0ffff 0fffff0f ffffffff ff0000f0 ................ + 23a14: ffff0fff 00f0ffff 0fffff00 ffffffff ................ + 23a24: ff0f00f0 000000ff 00000000 fffffd0f ................ + 23a34: ffffffff f0ffffff ffffff8f ffffffff ................ + 23a44: ff8f80ff ffffffff 80ffffff ffffffff ................ + 23a54: ffffffff 00fff0ff 00000000 fd0f0000 ................ + 23a64: ffff0fff 000000ff 0fffff0f 00ffffff ................ + 23a74: ff000000 ffff0fff 000000ff 0fffff00 ................ + 23a84: 00ffffff ff0f0000 000000ff 00000000 ................ + 23a94: fffffd0f ffffffff f0ffffff ffffff8f ................ + 23aa4: ffffffff ff8f80ff ffffffff 80ffffff ................ + 23ab4: ffffffff ffffffff 00fff0ff 00000000 ................ + 23ac4: fd0f0000 f0ff0fff 00000000 0fffff0f ................ + 23ad4: 0000f0ff ff000000 f0ff0fff 00000000 ................ + 23ae4: 0fffff00 0000f0ff ff0f0000 000000ff ................ + 23af4: 00000000 fffffd0f ffffffff f0ffffff ................ + 23b04: ffffff8f ffffffff ff8f80ff ffffffff ................ + 23b14: 80ffffff ffffffff ffffffff 00fff0ff ................ + 23b24: 00000000 fd0f0000 000000ff 00000000 ................ + 23b34: 00ffff0f 00000000 ff000000 000000ff ................ + 23b44: 00000000 00ffff00 00000000 ff0f0000 ................ + 23b54: 000000ff 00000000 fffffd0f ffffffff ................ + 23b64: f0ffffff ffffff8f ffffffff 000080ff ................ + 23b74: 01000000 00000000 00000000 10fd0700 ................ + 23b84: 00000000 cf010000 0000f5ff 00000000 ................ + 23b94: fe29b900 00000010 3f000000 00000210 ..)........?.... + 23ba4: df030000 00900a80 70030000 77ffdf00 ...........p...w + 23bb4: 555555f7 0fd38f55 dfccfdff cdccccdc .UUUU........... + 23bc4: fe8fb0ff 00aa0010 404d0000 00104600 ..........M@.F.. + 23bd4: 3302f201 00000010 09000000 00f9cfb1 ...3............ + 23be4: 00000000 ff0a0000 000090ff 00000000 ................ + 23bf4: f9bf0000 00000000 00000000 00002201 .............".. + 23c04: df180000 020092fd ffeffbef faff0d30 ............0... + 23c14: 4fe0ff2e ff03faff fafa9ff5 cffa4f35 ...O........5O.. + 23c24: 0b3d8ac0 03fbeffd fffe8f12 ff06b0ff ..=............. + 23c34: d1ffffff efffff08 9f1011fd 59d1dfff ...............Y + 23c44: affd0b3b 1d38fad7 faff5ffb 0df7df01 ;.....8.._...... + 23c54: ff1dfaff fcef03f1 0050ffdf a3fedf18 ..........P..... + 23c64: 7f000000 0000f7ff ffffffef effeffff ................ + 23c74: ffffffff 0000feff 00000000 ffff0f00 ................ + 23c84: f0ffffff ffffff0f 0ff0ffff f9999ff9 ................ + 23c94: f80ff09f 8ff8888f 8ff80ff0 f08ff888 ................ + 23ca4: 888ff80f 0ff08ff8 f8888ff8 f80ff08f ................ + 23cb4: 8ff8888f 8ff80ff0 f08ff888 999ff90f ................ + 23cc4: 0ff09ff9 ffffffff ff08f0ff ffffffff ................ + 23cd4: 00000080 7f000000 000000a0 8f000000 ................ + 23ce4: 0000b0ff 0d000000 00a0ffff 8a000000 ................ + 23cf4: 00ffff1d 8f000000 70ff1dfa 8f000000 ...........p.... + 23d04: 801dfaff 8f000000 00faffff 8f000000 ................ + 23d14: 80ffffff 8f000000 80ffffff 8f000000 ................ + 23d24: 80ffffff 8f000000 80ffffff 6f000000 ...............o + 23d34: 80ffffff 0b000000 80ffffff 00000000 ................ + 23d44: 80ffffdf 00000000 80ffff0e 00000000 ................ + 23d54: 60dbde00 00000000 00000000 00000000 ...`............ + 23d64: 00000000 ffffff1b e4ffffff ffdf0100 ................ + 23d74: ffffffff 1d00feff effaffff ffffaffe ................ + 23d84: ffffdf01 0ae22ea0 ff1dffff 02e2ffff ................ + 23d94: ffff2e20 ffffffcf ef0220fe ffcfffff ........ ...... + 23da4: 20feffff ffffef02 ffffff1d 2e2002e2 ... .......... . + 23db4: df01ffff 2ea0ffff ffff0ae2 ffff1d00 ................ + 23dc4: affeeffa 0100ffff ffffffdf feffffff ................ + 23dd4: ff1b0000 ffffffff 0800e4ff e4ffffff ................ + 23de4: ffff8f00 f808feff ff400b0f 0b0ff88f ..........@..... + 23df4: f8ffff40 ff400b0f ffffffff ffffffff @.....@......... + 23e04: ffffffff ffffffff ffffffff ffffffff ................ + 23e14: ffffffff ffffffff ffffffff ffffffff ................ + 23e24: ffffffff ffffffff ffffffff ffefffff ................ + 23e34: feffffff ffffff4e 0000e4ff 00000000 ....N........... + 23e44: 00000100 00000000 00e00300 00001000 ................ + 23e54: 10ef0200 0000bf00 f17f0000 00f1cf00 ................ + 23e64: ff070000 77ffcf11 bf777777 ffffcff1 .......wwww..... + 23e74: ffffffff ffff17ff ffffffff ff07e0ff ................ + 23e84: 000000f1 06000000 000010ff 00000000 ................ + 23e94: 0000a005 00000000 732f2e2e 65726168 ........../share + 23ea4: 68742f64 70647269 79747261 67766c2f d/thirdparty/lvg + 23eb4: 72732f6c 766c2f63 6c61685f 5f766c2f l/src/lv_hal/lv_ + 23ec4: 5f6c6168 70736964 hal_disp.c. + +00023ecf <__func__.0>: + 23ecf: 645f766c 5f707369 5f767264 69676572 lv_disp_drv_regi + 23edf: 72657473 2f2e2e00 72616873 742f6465 ster.../shared/t + 23eef: 64726968 74726170 766c2f79 732f6c67 hirdparty/lvgl/s + 23eff: 6c2f6372 696d5f76 6c2f6373 6e615f76 rc/lv_misc/lv_an + 23f0f: 632e6d69 im.c. + +00023f14 <__func__.0>: + 23f14: 615f766c 5f6d696e 72617473 00000074 lv_anim_start... + +00023f24 : + 23f24: 0000da6d 00000000 732f2e2e 65726168 m........./share + 23f34: 68742f64 70647269 79747261 67766c2f d/thirdparty/lvg + 23f44: 72732f6c 766c2f63 73696d5f 766c2f63 l/src/lv_misc/lv + 23f54: 2e73665f _fs.c. + +00023f5a <__func__.0>: + 23f5a: 665f766c 72645f73 65725f76 74736967 lv_fs_drv_regist + 23f6a: er. + +00023f6d <__func__.2>: + 23f6d: 665f766c 706f5f73 lv_fs_open. + +00023f78 <__func__.1>: + 23f78: 665f766c 69645f73 706f5f72 00006e65 lv_fs_dir_open.. + +00023f88 : + 23f88: 023c0000 06b30478 0b2808ee 0f990d61 ..<.x.....(.a... + 23f98: 140611d0 186c163a 1ccb1a9d 21211ef7 ....:.l.......!! + 23fa8: 256c2348 29ac278e 2ddf2bc7 32032ff3 H#l%.'.).+.-./.2 + 23fb8: 36183410 3a1c381c 3e0e3c17 41ec3fff .4.6.8.:.<.>.?.A + 23fc8: 45b643d4 496a4793 4d084b3c 508d4ecd .C.E.GjI: + 24152: 6d5f766c 615f6d65 636f6c6c lv_mem_alloc. + +0002415f <__func__.0>: + 2415f: 5f766c5f 5f6d656d 5f667562 656c6572 _lv_mem_buf_rele + 2416f: 00657361 ase. + +00024173 <__func__.2>: + 24173: 6d5f766c 725f6d65 6c6c6165 lv_mem_realloc. + +00024182 <__func__.1>: + 24182: 5f766c5f 5f6d656d 5f667562 00746567 _lv_mem_buf_get. + 24192: 732f2e2e 65726168 68742f64 70647269 ../shared/thirdp + 241a2: 79747261 67766c2f 72732f6c 766c2f63 arty/lvgl/src/lv + 241b2: 73696d5f 766c2f63 7361745f 00632e6b _misc/lv_task.c. + +000241c2 <__func__.1>: + 241c2: 745f766c 5f6b7361 61657263 625f6574 lv_task_create_b + 241d2: 63697361 asic. + +000241d7 <__func__.0>: + 241d7: 745f766c 5f6b7361 61657263 20006574 lv_task_create. + 241e7: 3a3b2e2c 2e005f2d 68732f2e 64657261 ,.;:-_.../shared + 241f7: 6968742f 61706472 2f797472 6c67766c /thirdparty/lvgl + 24207: 6372732f 5f766c2f 6373696d 5f766c2f /src/lv_misc/lv_ + 24217: 2e747874 766c0063 7478745f 7465675f txt.c.lv_txt_get + 24227: 7a69735f 69203a65 6765746e 6f207265 _size: integer o + 24237: 66726576 20776f6c 6c696877 61632065 verflow while ca + 24247: 6c75636c 6e697461 65742067 68207478 lculating text h + 24257: 68676965 eight. + +0002425d <__func__.0>: + 2425d: 5f766c5f 5f747874 5f746567 657a6973 _lv_txt_get_size + 2426d: 8c80ef00 10ffff00 2ec61884 68732f2e ............./sh + 2427d: 64657261 6968742f 61706472 2f797472 ared/thirdparty/ + 2428d: 6c67766c 6372732f 5f766c2f 67646977 lvgl/src/lv_widg + 2429d: 2f737465 695f766c 632e676d 5f766c00 ets/lv_img.c.lv_ + 242ad: 5f676d69 5f746573 3a637273 6b6e7520 img_set_src: unk + 242bd: 6e776f6e 70797420 766c0065 676d695f nown type.lv_img + 242cd: 7465735f 6372735f 6e75203a 776f6e6b _set_src: unknow + 242dd: 6d69206e 20656761 65707974 5f766c00 n image type.lv_ + 242ed: 5f676d69 5f746573 3a637273 4c602020 img_set_src: `L + 242fd: 4d495f56 52535f47 41565f43 42414952 V_IMG_SRC_VARIAB + 2430d: 2060454c 65707974 756f6620 6900646e LE` type found.i + 2431d: 6567616d 65726320 64657461 5f766c00 mage created.lv_ + 2432d: 00676d69 img. + +00024331 <__func__.13>: + 24331: 695f766c 645f676d 67697365 lv_img_design. + +0002433f <__func__.11>: + 2433f: 695f766c 735f676d 615f7465 5f6f7475 lv_img_set_auto_ + 2434f: 657a6973 size. + +00024354 <__func__.10>: + 24354: 695f766c 735f676d 6f5f7465 65736666 lv_img_set_offse + 24364: 00785f74 t_x. + +00024368 <__func__.9>: + 24368: 695f766c 735f676d 6f5f7465 65736666 lv_img_set_offse + 24378: 00795f74 t_y. + +0002437c <__func__.8>: + 2437c: 695f766c 675f676d 735f7465 lv_img_get_src. + +0002438b <__func__.7>: + 2438b: 695f766c 675f676d 665f7465 5f656c69 lv_img_get_file_ + 2439b: 656d616e name. + +000243a0 <__func__.6>: + 243a0: 695f766c 675f676d 615f7465 5f6f7475 lv_img_get_auto_ + 243b0: 657a6973 size. + +000243b5 <__func__.12>: + 243b5: 695f766c 735f676d 735f7465 lv_img_set_src. + +000243c4 <__func__.14>: + 243c4: 695f766c 635f676d 74616572 lv_img_create. + +000243d2 <__func__.5>: + 243d2: 695f766c 675f676d 6f5f7465 65736666 lv_img_get_offse + 243e2: 00785f74 t_x. + +000243e6 <__func__.4>: + 243e6: 695f766c 675f676d 6f5f7465 65736666 lv_img_get_offse + 243f6: 00795f74 t_y. + +000243fa <__func__.3>: + 243fa: 695f766c 675f676d 705f7465 746f7669 lv_img_get_pivot + ... + +0002440b <__func__.2>: + 2440b: 695f766c 675f676d 615f7465 656c676e lv_img_get_angle + ... + +0002441c <__func__.1>: + 2441c: 695f766c 675f676d 7a5f7465 006d6f6f lv_img_get_zoom. + +0002442c <__func__.0>: + 2442c: 695f766c 675f676d 615f7465 6169746e lv_img_get_antia + 2443c: 7361696c 2f2e2e00 72616873 742f6465 lias.../shared/t + 2444c: 64726968 74726170 766c2f79 732f6c67 hirdparty/lvgl/s + 2445c: 6c2f6372 69775f76 74656764 766c2f73 rc/lv_widgets/lv + 2446c: 62616c5f 632e6c65 69614600 2064656c _label.c.Failed + 2447c: 61206f74 636f6c6c 20657461 6f6d656d to allocate memo + 2448c: 66207972 6420726f 745f746f 705f706d ry for dot_tmp_p + 2449c: 54007274 00747865 6562616c 7263206c tr.Text.label cr + 244ac: 65746165 766c0064 62616c5f eated.lv_label. + +000244bb <__func__.21>: + 244bb: 6c5f766c 6c656261 7465735f 746f645f lv_label_set_dot + 244cb: 706d745f _tmp. + +000244d0 <__func__.16>: + 244d0: 6c5f766c 6c656261 7465735f 696c615f lv_label_set_ali + 244e0: gn. + +000244e3 <__func__.13>: + 244e3: 6c5f766c 6c656261 7465735f 7865745f lv_label_set_tex + 244f3: 65735f74 74735f6c 00747261 t_sel_start. + +000244ff <__func__.12>: + 244ff: 6c5f766c 6c656261 7465735f 7865745f lv_label_set_tex + 2450f: 65735f74 6e655f6c t_sel_end. + +00024519 <__func__.11>: + 24519: 6c5f766c 6c656261 7465675f 7865745f lv_label_get_tex + 24529: t. + +0002452b <__func__.10>: + 2452b: 6c5f766c 6c656261 7465675f 6e6f6c5f lv_label_get_lon + 2453b: 6f6d5f67 g_mode. + +00024542 <__func__.9>: + 24542: 6c5f766c 6c656261 7465675f 696c615f lv_label_get_ali + 24552: gn. + +00024555 <__func__.8>: + 24555: 6c5f766c 6c656261 7465675f 6365725f lv_label_get_rec + 24565: 726f6c6f olor. + +0002456a <__func__.7>: + 2456a: 6c5f766c 6c656261 7465675f 696e615f lv_label_get_ani + 2457a: 70735f6d 00646565 m_speed. + +00024582 <__func__.6>: + 24582: 6c5f766c 6c656261 7465675f 74656c5f lv_label_get_let + 24592: 5f726574 00736f70 ter_pos. + +0002459a <__func__.5>: + 2459a: 6c5f766c 6c656261 7465675f 74656c5f lv_label_get_let + 245aa: 5f726574 ter_on. + +000245b1 <__func__.20>: + 245b1: 6c5f766c 6c656261 7465735f 7865745f lv_label_set_tex + 245c1: t. + +000245c3 <__func__.19>: + 245c3: 6c5f766c 6c656261 7465735f 7865745f lv_label_set_tex + 245d3: 6d665f74 t_fmt. + +000245d9 <__func__.18>: + 245d9: 6c5f766c 6c656261 7465735f 7865745f lv_label_set_tex + 245e9: 74735f74 63697461 t_static. + +000245f2 <__func__.17>: + 245f2: 6c5f766c 6c656261 7465735f 6e6f6c5f lv_label_set_lon + 24602: 6f6d5f67 g_mode. + +00024609 <__func__.15>: + 24609: 6c5f766c 6c656261 7465735f 6365725f lv_label_set_rec + 24619: 726f6c6f olor. + +0002461e <__func__.22>: + 2461e: 6c5f766c 6c656261 6572635f 00657461 lv_label_create. + +0002462e <__func__.14>: + 2462e: 6c5f766c 6c656261 7465735f 696e615f lv_label_set_ani + 2463e: 70735f6d 00646565 m_speed. + +00024646 <__func__.4>: + 24646: 6c5f766c 6c656261 7465675f 7865745f lv_label_get_tex + 24656: 65735f74 74735f6c 00747261 t_sel_start. + +00024662 <__func__.3>: + 24662: 6c5f766c 6c656261 7465675f 7865745f lv_label_get_tex + 24672: 65735f74 6e655f6c t_sel_end. + +0002467c <__func__.2>: + 2467c: 6c5f766c 6c656261 5f73695f 72616863 lv_label_is_char + 2468c: 646e755f 705f7265 _under_pos. + +00024697 <__func__.1>: + 24697: 6c5f766c 6c656261 736e695f 7865745f lv_label_ins_tex + 246a7: t. + +000246a9 <__func__.0>: + 246a9: 6c5f766c 6c656261 7475635f 7865745f lv_label_cut_tex + 246b9: t.. + +000246bc <_init>: + 246bc: b5f8 push {r3, r4, r5, r6, r7, lr} + 246be: bf00 nop + 246c0: bcf8 pop {r3, r4, r5, r6, r7} + 246c2: bc08 pop {r3} + 246c4: 469e mov lr, r3 + 246c6: 4770 bx lr + +000246c8 <__frame_dummy_init_array_entry>: + 246c8: 02cd 0000 .... + +000246cc <_fini>: + 246cc: b5f8 push {r3, r4, r5, r6, r7, lr} + 246ce: bf00 nop + 246d0: bcf8 pop {r3, r4, r5, r6, r7} + 246d2: bc08 pop {r3} + 246d4: 469e mov lr, r3 + 246d6: 4770 bx lr + +000246d8 <__do_global_dtors_aux_fini_array_entry>: + 246d8: 02a5 0000 .... diff --git a/software/firmware/oracle_same54n19a/gcc/AtmelStart.map b/software/firmware/oracle_same54n19a/gcc/AtmelStart.map new file mode 100644 index 00000000..63dd9049 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/AtmelStart.map @@ -0,0 +1,30898 @@ +Archive member included to satisfy reference by file (symbol) + +/usr/lib/gcc/arm-none-eabi/11.2.1/thumb/v7e-m/nofp/libgcc.a(_arm_muldf3.o) + hpl/sercom/hpl_sercom.o (__aeabi_dmul) +/usr/lib/gcc/arm-none-eabi/11.2.1/thumb/v7e-m/nofp/libgcc.a(_arm_addsubdf3.o) + hpl/sercom/hpl_sercom.o (__aeabi_dsub) +/usr/lib/gcc/arm-none-eabi/11.2.1/thumb/v7e-m/nofp/libgcc.a(_arm_muldivdf3.o) + hpl/sercom/hpl_sercom.o (__aeabi_ddiv) +/usr/lib/gcc/arm-none-eabi/11.2.1/thumb/v7e-m/nofp/libgcc.a(_arm_fixunsdfsi.o) + hpl/sercom/hpl_sercom.o (__aeabi_d2uiz) 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(exit) +/usr/lib/gcc/arm-none-eabi/11.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-fini.o) + /usr/lib/gcc/arm-none-eabi/11.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/crt0.o (__libc_fini_array) +/usr/lib/gcc/arm-none-eabi/11.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-impure.o) + /usr/lib/gcc/arm-none-eabi/11.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-exit.o) (_global_impure_ptr) +/usr/lib/gcc/arm-none-eabi/11.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-init.o) + /usr/lib/gcc/arm-none-eabi/11.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/crt0.o (__libc_init_array) +/usr/lib/gcc/arm-none-eabi/11.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-memcmp.o) + shared/thirdparty/lvgl/src/lv_core/lv_obj.o (memcmp) +/usr/lib/gcc/arm-none-eabi/11.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-memcpy-stub.o) + gcc/gcc/startup_same54.o (memcpy) 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shared/thirdparty/lvgl/src/lv_draw/lv_img_decoder.o (strcpy) +/usr/lib/gcc/arm-none-eabi/11.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-strcpy_chk.o) + shared/thirdparty/lvgl/src/lv_widgets/lv_calendar.o (__strcpy_chk) +/usr/lib/gcc/arm-none-eabi/11.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-strlen.o) + shared/thirdparty/lvgl/src/lv_core/lv_debug.o (strlen) +/usr/lib/gcc/arm-none-eabi/11.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-strncpy.o) + shared/thirdparty/lvgl/src/lv_widgets/lv_chart.o (strncpy) +/usr/lib/gcc/arm-none-eabi/11.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-__atexit.o) + /usr/lib/gcc/arm-none-eabi/11.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-atexit.o) (__register_exitproc) +/usr/lib/gcc/arm-none-eabi/11.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-__call_atexit.o) + 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/usr/lib/gcc/arm-none-eabi/11.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a +END GROUP +LOAD /usr/lib/gcc/arm-none-eabi/11.2.1/thumb/v7e-m/nofp/crtend.o +LOAD /usr/lib/gcc/arm-none-eabi/11.2.1/thumb/v7e-m/nofp/crtn.o + 0x000000000000c000 STACK_SIZE = DEFINED (STACK_SIZE)?STACK_SIZE:DEFINED (__stack_size__)?__stack_size__:0xc000 + +.text 0x0000000000000000 0x246dc + 0x0000000000000000 . = ALIGN (0x4) + 0x0000000000000000 _sfixed = . + *(.vectors .vectors.*) + .vectors 0x0000000000000000 0x264 gcc/gcc/startup_same54.o + 0x0000000000000000 exception_table + *(.text .text.* .gnu.linkonce.t.*) + .text 0x0000000000000264 0x88 /usr/lib/gcc/arm-none-eabi/11.2.1/thumb/v7e-m/nofp/crtbegin.o + .text.io_write + 0x00000000000002ec 0x30 hal/src/hal_io.o + 0x00000000000002ec io_write + .text._irq_set + 0x000000000000031c 0x18 hpl/core/hpl_core_m4.o + 0x000000000000031c _irq_set + .text._get_cycles_for_us + 0x0000000000000334 0xe hpl/core/hpl_core_m4.o + 0x0000000000000334 _get_cycles_for_us + .text._get_cycles_for_ms + 0x0000000000000342 0x14 hpl/core/hpl_core_m4.o + 0x0000000000000342 _get_cycles_for_ms + .text._delay_init + 0x0000000000000356 0x2 hpl/core/hpl_core_m4.o + 0x0000000000000356 _delay_init + .text._delay_cycles + 0x0000000000000358 0x8 hpl/core/hpl_core_m4.o + 0x0000000000000358 _delay_cycles + .text.timer_add_timer_task + 0x0000000000000360 0x4c hal/src/hal_timer.o + .text.timer_process_counted + 0x00000000000003ac 0x68 hal/src/hal_timer.o + .text.timer_init + 0x0000000000000414 0x38 hal/src/hal_timer.o + 0x0000000000000414 timer_init + .text.timer_start + 0x000000000000044c 0x3c hal/src/hal_timer.o + 0x000000000000044c timer_start + .text.timer_add_task + 0x0000000000000488 0xa8 hal/src/hal_timer.o + 0x0000000000000488 timer_add_task + .text.delay_init + 0x0000000000000530 0x10 hal/src/hal_delay.o + 0x0000000000000530 delay_init + .text.delay_us + 0x0000000000000540 0x24 hal/src/hal_delay.o + 0x0000000000000540 delay_us + .text.delay_ms + 0x0000000000000564 0x24 hal/src/hal_delay.o + 0x0000000000000564 delay_ms + .text._init_chip + 0x0000000000000588 0x44 hpl/core/hpl_init.o + 0x0000000000000588 _init_chip + .text.RAMECC_Handler + 0x00000000000005cc 0x38 hpl/ramecc/hpl_ramecc.o + 0x00000000000005cc RAMECC_Handler + .text.is_list_element + 0x0000000000000604 0xe hal/utils/src/utils_list.o + 0x0000000000000604 is_list_element + *fill* 0x0000000000000612 0x2 + .text.list_insert_as_head + 0x0000000000000614 0x2c hal/utils/src/utils_list.o + 0x0000000000000614 list_insert_as_head + .text.list_insert_after + 0x0000000000000640 0x8 hal/utils/src/utils_list.o + 0x0000000000000640 list_insert_after + .text.list_remove_head + 0x0000000000000648 0xc hal/utils/src/utils_list.o + 0x0000000000000648 list_remove_head + .text.assert 0x0000000000000654 0x6 hal/utils/src/utils_assert.o + 0x0000000000000654 assert + .text._oscctrl_init_sources + 0x000000000000065a 0x2 hpl/oscctrl/hpl_oscctrl.o + 0x000000000000065a _oscctrl_init_sources + .text._oscctrl_init_referenced_generators + 0x000000000000065c 0x3c hpl/oscctrl/hpl_oscctrl.o + 0x000000000000065c _oscctrl_init_referenced_generators + .text._mclk_init + 0x0000000000000698 0xc hpl/mclk/hpl_mclk.o + 0x0000000000000698 _mclk_init + .text.hri_sercomi2cm_wait_for_sync + 0x00000000000006a4 0x8 hpl/sercom/hpl_sercom.o + .text.hri_sercomi2cm_set_CTRLA_ENABLE_bit + 0x00000000000006ac 0x14 hpl/sercom/hpl_sercom.o + .text.hri_sercomi2cm_clear_CTRLA_ENABLE_bit + 0x00000000000006c0 0x14 hpl/sercom/hpl_sercom.o + .text.hri_sercomi2cm_write_CTRLA_reg + 0x00000000000006d4 0xc hpl/sercom/hpl_sercom.o + .text._sercom_get_hardware_index + 0x00000000000006e0 0x38 hpl/sercom/hpl_sercom.o + .text._sercom_get_irq_num + 0x0000000000000718 0x14 hpl/sercom/hpl_sercom.o + .text.__NVIC_EnableIRQ + 0x000000000000072c 0x18 hpl/sercom/hpl_sercom.o + .text.__NVIC_DisableIRQ + 0x0000000000000744 0x20 hpl/sercom/hpl_sercom.o + .text.__NVIC_ClearPendingIRQ + 0x0000000000000764 0x18 hpl/sercom/hpl_sercom.o + .text._usart_init + 0x000000000000077c 0x8c hpl/sercom/hpl_sercom.o + .text._usart_async_init + 0x0000000000000808 0x84 hpl/sercom/hpl_sercom.o + 0x0000000000000808 _usart_async_init + .text._usart_async_enable + 0x000000000000088c 0xc hpl/sercom/hpl_sercom.o + 0x000000000000088c _usart_async_enable + .text._usart_async_write_byte + 0x0000000000000898 0x6 hpl/sercom/hpl_sercom.o + 0x0000000000000898 _usart_async_write_byte + .text._usart_async_enable_byte_sent_irq + 0x000000000000089e 0x8 hpl/sercom/hpl_sercom.o + 0x000000000000089e _usart_async_enable_byte_sent_irq + .text._usart_async_enable_tx_done_irq + 0x00000000000008a6 0x8 hpl/sercom/hpl_sercom.o + 0x00000000000008a6 _usart_async_enable_tx_done_irq + *fill* 0x00000000000008ae 0x2 + .text.SERCOM0_0_Handler + 0x00000000000008b0 0x6c hpl/sercom/hpl_sercom.o + 0x00000000000008b0 SERCOM0_0_Handler + .text.SERCOM0_1_Handler + 0x000000000000091c 0x8 hpl/sercom/hpl_sercom.o + 0x000000000000091c SERCOM0_1_Handler + .text.SERCOM0_2_Handler + 0x0000000000000924 0x8 hpl/sercom/hpl_sercom.o + 0x0000000000000924 SERCOM0_2_Handler + .text.SERCOM0_3_Handler + 0x000000000000092c 0x8 hpl/sercom/hpl_sercom.o + 0x000000000000092c SERCOM0_3_Handler + .text._gclk_init_generators_by_fref + 0x0000000000000934 0x20 hpl/gclk/hpl_gclk.o + 0x0000000000000934 _gclk_init_generators_by_fref + .text.Dummy_Handler + 0x0000000000000954 0x2 gcc/gcc/startup_same54.o + 0x0000000000000954 EIC_5_Handler + 0x0000000000000954 SVCall_Handler + 0x0000000000000954 EIC_13_Handler + 0x0000000000000954 EVSYS_0_Handler + 0x0000000000000954 TCC1_3_Handler + 0x0000000000000954 DAC_3_Handler + 0x0000000000000954 TRNG_Handler + 0x0000000000000954 HardFault_Handler + 0x0000000000000954 TC2_Handler + 0x0000000000000954 PDEC_2_Handler + 0x0000000000000954 EIC_4_Handler + 0x0000000000000954 AC_Handler + 0x0000000000000954 SERCOM3_1_Handler + 0x0000000000000954 SysTick_Handler + 0x0000000000000954 TCC2_3_Handler + 0x0000000000000954 SERCOM3_2_Handler + 0x0000000000000954 PendSV_Handler + 0x0000000000000954 TC7_Handler + 0x0000000000000954 ADC1_1_Handler + 0x0000000000000954 EVSYS_3_Handler + 0x0000000000000954 PDEC_0_Handler + 0x0000000000000954 QSPI_Handler + 0x0000000000000954 NonMaskableInt_Handler + 0x0000000000000954 TCC0_0_Handler + 0x0000000000000954 EIC_3_Handler + 0x0000000000000954 MemManagement_Handler + 0x0000000000000954 DAC_2_Handler + 0x0000000000000954 RTC_Handler + 0x0000000000000954 UsageFault_Handler + 0x0000000000000954 SERCOM4_0_Handler + 0x0000000000000954 EIC_10_Handler + 0x0000000000000954 EIC_11_Handler + 0x0000000000000954 EIC_9_Handler + 0x0000000000000954 OSC32KCTRL_Handler + 0x0000000000000954 TCC2_1_Handler + 0x0000000000000954 SUPC_1_Handler + 0x0000000000000954 TCC0_5_Handler + 0x0000000000000954 TCC0_6_Handler + 0x0000000000000954 SERCOM6_2_Handler + 0x0000000000000954 EVSYS_1_Handler + 0x0000000000000954 TCC1_4_Handler + 0x0000000000000954 TC6_Handler + 0x0000000000000954 DMAC_0_Handler + 0x0000000000000954 WDT_Handler + 0x0000000000000954 CAN0_Handler + 0x0000000000000954 EIC_8_Handler + 0x0000000000000954 EIC_15_Handler + 0x0000000000000954 SERCOM6_0_Handler + 0x0000000000000954 SERCOM5_0_Handler + 0x0000000000000954 TC4_Handler + 0x0000000000000954 TC1_Handler + 0x0000000000000954 OSCCTRL_4_Handler + 0x0000000000000954 SERCOM4_3_Handler + 0x0000000000000954 EIC_12_Handler + 0x0000000000000954 DMAC_4_Handler + 0x0000000000000954 TCC4_2_Handler + 0x0000000000000954 PAC_Handler + 0x0000000000000954 TCC1_0_Handler + 0x0000000000000954 USB_0_Handler + 0x0000000000000954 OSCCTRL_0_Handler + 0x0000000000000954 EIC_0_Handler + 0x0000000000000954 OSCCTRL_3_Handler + 0x0000000000000954 SERCOM4_1_Handler + 0x0000000000000954 TC3_Handler + 0x0000000000000954 Dummy_Handler + 0x0000000000000954 TCC3_0_Handler + 0x0000000000000954 TCC2_2_Handler + 0x0000000000000954 SERCOM5_1_Handler + 0x0000000000000954 TCC1_1_Handler + 0x0000000000000954 DMAC_2_Handler + 0x0000000000000954 ADC0_0_Handler + 0x0000000000000954 OSCCTRL_2_Handler + 0x0000000000000954 ADC1_0_Handler + 0x0000000000000954 TCC1_2_Handler + 0x0000000000000954 SERCOM7_1_Handler + 0x0000000000000954 USB_1_Handler + 0x0000000000000954 PM_Handler + 0x0000000000000954 SERCOM6_3_Handler + 0x0000000000000954 SERCOM2_3_Handler + 0x0000000000000954 DAC_4_Handler + 0x0000000000000954 TCC3_2_Handler + 0x0000000000000954 SERCOM7_0_Handler + 0x0000000000000954 TCC0_2_Handler + 0x0000000000000954 DMAC_1_Handler + 0x0000000000000954 TCC4_0_Handler + 0x0000000000000954 SERCOM7_3_Handler + 0x0000000000000954 GMAC_Handler + 0x0000000000000954 SDHC1_Handler + 0x0000000000000954 USB_3_Handler + 0x0000000000000954 SERCOM7_2_Handler + 0x0000000000000954 CAN1_Handler + 0x0000000000000954 TCC2_0_Handler + 0x0000000000000954 PDEC_1_Handler + 0x0000000000000954 TCC4_1_Handler + 0x0000000000000954 SERCOM5_3_Handler + 0x0000000000000954 USB_2_Handler + 0x0000000000000954 SERCOM6_1_Handler + 0x0000000000000954 SDHC0_Handler + 0x0000000000000954 SERCOM1_1_Handler + 0x0000000000000954 I2S_Handler + 0x0000000000000954 EIC_2_Handler + 0x0000000000000954 PCC_Handler + 0x0000000000000954 DAC_0_Handler + 0x0000000000000954 TCC0_1_Handler + 0x0000000000000954 SERCOM1_3_Handler + 0x0000000000000954 EIC_6_Handler + 0x0000000000000954 OSCCTRL_1_Handler + 0x0000000000000954 SERCOM1_0_Handler + 0x0000000000000954 PUKCC_Handler + 0x0000000000000954 SERCOM2_1_Handler + 0x0000000000000954 SERCOM1_2_Handler + 0x0000000000000954 SERCOM3_0_Handler + 0x0000000000000954 EIC_1_Handler + 0x0000000000000954 SERCOM4_2_Handler + 0x0000000000000954 EVSYS_4_Handler + 0x0000000000000954 EIC_7_Handler + 0x0000000000000954 NVMCTRL_1_Handler + 0x0000000000000954 SERCOM5_2_Handler + 0x0000000000000954 SERCOM3_3_Handler + 0x0000000000000954 ADC0_1_Handler + 0x0000000000000954 SERCOM2_2_Handler + 0x0000000000000954 TCC3_1_Handler + 0x0000000000000954 EIC_14_Handler + 0x0000000000000954 DAC_1_Handler + 0x0000000000000954 NVMCTRL_0_Handler + 0x0000000000000954 MCLK_Handler + 0x0000000000000954 EVSYS_2_Handler + 0x0000000000000954 SUPC_0_Handler + 0x0000000000000954 BusFault_Handler + 0x0000000000000954 FREQM_Handler + 0x0000000000000954 TCC0_3_Handler + 0x0000000000000954 DMAC_3_Handler + 0x0000000000000954 DebugMonitor_Handler + 0x0000000000000954 TCC0_4_Handler + 0x0000000000000954 TC5_Handler + 0x0000000000000954 SERCOM2_0_Handler + 0x0000000000000954 AES_Handler + 0x0000000000000954 ICM_Handler + *fill* 0x0000000000000956 0x2 + .text.Reset_Handler + 0x0000000000000958 0x90 gcc/gcc/startup_same54.o + 0x0000000000000958 Reset_Handler + .text.startup.main + 0x00000000000009e8 0x14 main.o + 0x00000000000009e8 main + .text.oracle_init + 0x00000000000009fc 0x38 oracle.o + 0x00000000000009fc oracle_init + .text.oracle_service + 0x0000000000000a34 0x8 oracle.o + 0x0000000000000a34 oracle_service + .text._osc32kctrl_init_sources + 0x0000000000000a3c 0x20 hpl/osc32kctrl/hpl_osc32kctrl.o + 0x0000000000000a3c _osc32kctrl_init_sources + .text.usart_transmission_complete + 0x0000000000000a5c 0xe hal/src/hal_usart_async.o + .text.usart_error + 0x0000000000000a6a 0xe hal/src/hal_usart_async.o + .text.usart_fill_rx_buffer + 0x0000000000000a78 0x20 hal/src/hal_usart_async.o + .text.usart_async_write + 0x0000000000000a98 0x5c hal/src/hal_usart_async.o + .text.usart_process_byte_sent + 0x0000000000000af4 0x34 hal/src/hal_usart_async.o + .text.usart_async_read + 0x0000000000000b28 0x70 hal/src/hal_usart_async.o + .text.usart_async_init + 0x0000000000000b98 0x88 hal/src/hal_usart_async.o + 0x0000000000000b98 usart_async_init + .text.usart_async_enable + 0x0000000000000c20 0x2c hal/src/hal_usart_async.o + 0x0000000000000c20 usart_async_enable + .text.ringbuffer_init + 0x0000000000000c4c 0x3c hal/utils/src/utils_ringbuffer.o + 0x0000000000000c4c ringbuffer_init + .text.ringbuffer_get + 0x0000000000000c88 0x40 hal/utils/src/utils_ringbuffer.o + 0x0000000000000c88 ringbuffer_get + .text.ringbuffer_put + 0x0000000000000cc8 0x40 hal/utils/src/utils_ringbuffer.o + 0x0000000000000cc8 ringbuffer_put + .text.ringbuffer_num + 0x0000000000000d08 0x20 hal/utils/src/utils_ringbuffer.o + 0x0000000000000d08 ringbuffer_num + .text.hri_tc_wait_for_sync + 0x0000000000000d28 0x8 hpl/tc/hpl_tc.o + .text.get_tc_index + 0x0000000000000d30 0x50 hpl/tc/hpl_tc.o + .text._timer_init + 0x0000000000000d80 0x13c hpl/tc/hpl_tc.o + 0x0000000000000d80 _timer_init + .text._timer_start + 0x0000000000000ebc 0x14 hpl/tc/hpl_tc.o + 0x0000000000000ebc _timer_start + .text._timer_is_started + 0x0000000000000ed0 0x18 hpl/tc/hpl_tc.o + 0x0000000000000ed0 _timer_is_started + .text._tc_get_timer + 0x0000000000000ee8 0x4 hpl/tc/hpl_tc.o + 0x0000000000000ee8 _tc_get_timer + .text._timer_set_irq + 0x0000000000000eec 0x40 hpl/tc/hpl_tc.o + 0x0000000000000eec _timer_set_irq + .text.TC0_Handler + 0x0000000000000f2c 0x1c hpl/tc/hpl_tc.o + 0x0000000000000f2c TC0_Handler + .text.atomic_enter_critical + 0x0000000000000f48 0xe hal/src/hal_atomic.o + 0x0000000000000f48 atomic_enter_critical + .text.atomic_leave_critical + 0x0000000000000f56 0xc hal/src/hal_atomic.o + 0x0000000000000f56 atomic_leave_critical + *fill* 0x0000000000000f62 0x2 + .text.gpio_set_pin_direction + 0x0000000000000f64 0x78 shared/drivers/p_gpio.o + .text._gpio_set_pin_function + 0x0000000000000fdc 0x6c shared/drivers/p_gpio.o + .text.gpio_set_pin_pull_mode + 0x0000000000001048 0x80 shared/drivers/p_gpio.o + .text.p_gpio_set_port_data + 0x00000000000010c8 0x2c shared/drivers/p_gpio.o + 0x00000000000010c8 p_gpio_set_port_data + .text.p_gpio_parallel_write + 0x00000000000010f4 0x20 shared/drivers/p_gpio.o + 0x00000000000010f4 p_gpio_parallel_write + .text.p_gpio_parallel_write_arr + 0x0000000000001114 0x28 shared/drivers/p_gpio.o + 0x0000000000001114 p_gpio_parallel_write_arr + .text.p_gpio_set_port_group_config + 0x000000000000113c 0x68 shared/drivers/p_gpio.o + 0x000000000000113c p_gpio_set_port_group_config + .text.p_gpio_init + 0x00000000000011a4 0xc8 shared/drivers/p_gpio.o + 0x00000000000011a4 p_gpio_init + .text.p_i2c_init + 0x000000000000126c 0x2 shared/drivers/p_i2c.o + 0x000000000000126c p_i2c_init + *fill* 0x000000000000126e 0x2 + .text.TIMER_0_task1_cb + 0x0000000000001270 0x24 shared/drivers/p_tcc.o + .text.p_tcc_init + 0x0000000000001294 0x78 shared/drivers/p_tcc.o + 0x0000000000001294 p_tcc_init + .text.p_usart_init + 0x000000000000130c 0xac shared/drivers/p_usart.o + 0x000000000000130c p_usart_init + .text.p_screen_init + 0x00000000000013b8 0xac shared/devices/p_screen.o + 0x00000000000013b8 p_screen_init + .text.p_screen_service + 0x0000000000001464 0x8 shared/devices/p_screen.o + 0x0000000000001464 p_screen_service + .text.ssd1963_cmd + 0x000000000000146c 0x3c shared/devices/display/p_ssd1963.o + .text.ssd1963_data + 0x00000000000014a8 0x3c shared/devices/display/p_ssd1963.o + .text.ssd1963_init + 0x00000000000014e4 0x1a4 shared/devices/display/p_ssd1963.o + 0x00000000000014e4 ssd1963_init + .text.ssd1963_flush + 0x0000000000001688 0x158 shared/devices/display/p_ssd1963.o + 0x0000000000001688 ssd1963_flush + .text.lv_debug_check_null + 0x00000000000017e0 0x8 shared/thirdparty/lvgl/src/lv_core/lv_debug.o + 0x00000000000017e0 lv_debug_check_null + .text.lv_debug_log_error + 0x00000000000017e8 0x88 shared/thirdparty/lvgl/src/lv_core/lv_debug.o + 0x00000000000017e8 lv_debug_log_error + .text.lv_disp_get_scr_act + 0x0000000000001870 0x3c shared/thirdparty/lvgl/src/lv_core/lv_disp.o + 0x0000000000001870 lv_disp_get_scr_act + .text.lv_disp_get_layer_top + 0x00000000000018ac 0x3c shared/thirdparty/lvgl/src/lv_core/lv_disp.o + 0x00000000000018ac lv_disp_get_layer_top + .text.lv_disp_get_layer_sys + 0x00000000000018e8 0x3c shared/thirdparty/lvgl/src/lv_core/lv_disp.o + 0x00000000000018e8 lv_disp_get_layer_sys + .text.obj_to_foreground + 0x0000000000001924 0x30 shared/thirdparty/lvgl/src/lv_core/lv_group.o + .text.focus_next_core + 0x0000000000001954 0xe4 shared/thirdparty/lvgl/src/lv_core/lv_group.o + .text._lv_group_init + 0x0000000000001a38 0x10 shared/thirdparty/lvgl/src/lv_core/lv_group.o + 0x0000000000001a38 _lv_group_init + .text.lv_group_focus_next + 0x0000000000001a48 0x14 shared/thirdparty/lvgl/src/lv_core/lv_group.o + 0x0000000000001a48 lv_group_focus_next + .text.lv_group_focus_prev + 0x0000000000001a5c 0x14 shared/thirdparty/lvgl/src/lv_core/lv_group.o + 0x0000000000001a5c lv_group_focus_prev + .text.lv_group_refocus + 0x0000000000001a70 0x2c shared/thirdparty/lvgl/src/lv_core/lv_group.o + .text.lv_group_add_obj + 0x0000000000001a9c 0xd8 shared/thirdparty/lvgl/src/lv_core/lv_group.o + 0x0000000000001a9c lv_group_add_obj + .text.lv_group_remove_obj + 0x0000000000001b74 0x9c shared/thirdparty/lvgl/src/lv_core/lv_group.o + 0x0000000000001b74 lv_group_remove_obj + .text.lv_group_get_focused + 0x0000000000001c10 0xa shared/thirdparty/lvgl/src/lv_core/lv_group.o + 0x0000000000001c10 lv_group_get_focused + .text.lv_group_get_editing + 0x0000000000001c1a 0xa shared/thirdparty/lvgl/src/lv_core/lv_group.o + 0x0000000000001c1a lv_group_get_editing + .text.lv_indev_reset.part.0 + 0x0000000000001c24 0x3c shared/thirdparty/lvgl/src/lv_core/lv_indev.o + .text._lv_indev_init + 0x0000000000001c60 0xc shared/thirdparty/lvgl/src/lv_core/lv_indev.o + 0x0000000000001c60 _lv_indev_init + .text.lv_indev_get_act + 0x0000000000001c6c 0xc shared/thirdparty/lvgl/src/lv_core/lv_indev.o + 0x0000000000001c6c lv_indev_get_act + .text.lv_indev_reset + 0x0000000000001c78 0x3c shared/thirdparty/lvgl/src/lv_core/lv_indev.o + 0x0000000000001c78 lv_indev_reset + .text.lv_indev_get_obj_act + 0x0000000000001cb4 0xc shared/thirdparty/lvgl/src/lv_core/lv_indev.o + 0x0000000000001cb4 lv_indev_get_obj_act + .text.refresh_children_position + 0x0000000000001cc0 0x58 shared/thirdparty/lvgl/src/lv_core/lv_obj.o + .text.lv_area_copy + 0x0000000000001d18 0x14 shared/thirdparty/lvgl/src/lv_core/lv_obj.o + .text.lv_init 0x0000000000001d2c 0xdc shared/thirdparty/lvgl/src/lv_core/lv_obj.o + 0x0000000000001d2c lv_init + .text.lv_obj_set_adv_hittest + 0x0000000000001e08 0x54 shared/thirdparty/lvgl/src/lv_core/lv_obj.o + 0x0000000000001e08 lv_obj_set_adv_hittest + .text.lv_obj_set_click + 0x0000000000001e5c 0x54 shared/thirdparty/lvgl/src/lv_core/lv_obj.o + 0x0000000000001e5c lv_obj_set_click + .text.lv_event_send_func + 0x0000000000001eb0 0xc8 shared/thirdparty/lvgl/src/lv_core/lv_obj.o + 0x0000000000001eb0 lv_event_send_func + .text.lv_event_send + 0x0000000000001f78 0x64 shared/thirdparty/lvgl/src/lv_core/lv_obj.o + 0x0000000000001f78 lv_event_send + .text.lv_obj_set_signal_cb + 0x0000000000001fdc 0x48 shared/thirdparty/lvgl/src/lv_core/lv_obj.o + 0x0000000000001fdc lv_obj_set_signal_cb + .text.lv_signal_send + 0x0000000000002024 0xc shared/thirdparty/lvgl/src/lv_core/lv_obj.o + 0x0000000000002024 lv_signal_send + .text.lv_obj_set_design_cb + 0x0000000000002030 0x48 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*(SORT_BY_NAME(.fini_array.*)) + 0x00000000000246dc __fini_array_end = . + *crtbegin.o(.dtors) + *(EXCLUDE_FILE(*crtend.o) .dtors) + *(SORT_BY_NAME(.dtors.*)) + *crtend.o(.dtors) + 0x00000000000246dc . = ALIGN (0x4) + 0x00000000000246dc _efixed = . + [!provide] PROVIDE (__exidx_start = .) + +.vfp11_veneer 0x00000000000246dc 0x0 + .vfp11_veneer 0x00000000000246dc 0x0 linker stubs + +.v4_bx 0x00000000000246dc 0x0 + .v4_bx 0x00000000000246dc 0x0 linker stubs + +.iplt 0x00000000000246dc 0x0 + .iplt 0x00000000000246dc 0x0 /usr/lib/gcc/arm-none-eabi/11.2.1/thumb/v7e-m/nofp/crtbegin.o + +.ARM.exidx 0x00000000000246dc 0x8 + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + .ARM.exidx 0x00000000000246dc 0x8 /usr/lib/gcc/arm-none-eabi/11.2.1/thumb/v7e-m/nofp/libgcc.a(_udivmoddi4.o) + [!provide] PROVIDE (__exidx_end = .) + +.eh_frame 0x00000000000246e4 0x0 + .eh_frame 0x00000000000246e4 0x0 /usr/lib/gcc/arm-none-eabi/11.2.1/thumb/v7e-m/nofp/crtbegin.o + +.rel.dyn 0x00000000000246e4 0x0 + .rel.iplt 0x00000000000246e4 0x0 /usr/lib/gcc/arm-none-eabi/11.2.1/thumb/v7e-m/nofp/crtbegin.o + +.tm_clone_table + 0x00000000000246e4 0x0 + .tm_clone_table + 0x00000000000246e4 0x0 /usr/lib/gcc/arm-none-eabi/11.2.1/thumb/v7e-m/nofp/crtbegin.o + .tm_clone_table + 0x00000000000246e4 0x0 /usr/lib/gcc/arm-none-eabi/11.2.1/thumb/v7e-m/nofp/crtend.o + +.igot.plt 0x00000000000246e4 0x0 + .igot.plt 0x00000000000246e4 0x0 /usr/lib/gcc/arm-none-eabi/11.2.1/thumb/v7e-m/nofp/crtbegin.o + 0x00000000000246e4 . = ALIGN (0x4) + 0x00000000000246e4 _etext = . + +.relocate 0x0000000020000000 0x74 load address 0x00000000000246e4 + 0x0000000020000000 . = ALIGN (0x4) + 0x0000000020000000 _srelocate = . + *(.ramfunc .ramfunc.*) + *(.data .data.*) + .data 0x0000000020000000 0xc shared/drivers/p_usart.o + .data 0x000000002000000c 0x1 shared/devices/display/p_ssd1963.o + *fill* 0x000000002000000d 0x3 + .data 0x0000000020000010 0x34 shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_16.o + 0x0000000020000010 lv_font_montserrat_16 + .data 0x0000000020000044 0x10 shared/thirdparty/lvgl/src/lv_misc/lv_mem.o + .data 0x0000000020000054 0x20 shared/thirdparty/lvgl/src/lv_misc/lv_txt.o + 0x0000000020000054 _lv_txt_encoded_size + 0x0000000020000058 _lv_txt_encoded_next + 0x000000002000005c _lv_txt_encoded_get_byte_id + 0x0000000020000060 _lv_txt_get_encoded_length + 0x0000000020000064 _lv_txt_encoded_get_char_id + 0x0000000020000068 _lv_txt_encoded_prev + 0x000000002000006c _lv_txt_encoded_conv_wc + 0x0000000020000070 _lv_txt_unicode_to_encoded + 0x0000000020000074 . = ALIGN (0x4) + 0x0000000020000074 _erelocate = . + +.bkupram 0x0000000047000000 0x0 + 0x0000000047000000 . = ALIGN (0x8) + 0x0000000047000000 _sbkupram = . + *(.bkupram .bkupram.*) + 0x0000000047000000 . = ALIGN (0x8) + 0x0000000047000000 _ebkupram = . + +.qspi 0x0000000004000000 0x0 + 0x0000000004000000 . = ALIGN (0x8) + 0x0000000004000000 _sqspi = . + *(.qspi .qspi.*) + 0x0000000004000000 . = ALIGN (0x8) + 0x0000000004000000 _eqspi = . + +.bss 0x0000000020000078 0xc788 load address 0x0000000000024760 + 0x0000000020000078 . = ALIGN (0x4) + 0x0000000020000078 _sbss = . + 0x0000000020000078 _szero = . + *(.bss .bss.*) + .bss 0x0000000020000078 0x1c /usr/lib/gcc/arm-none-eabi/11.2.1/thumb/v7e-m/nofp/crtbegin.o + .bss 0x0000000020000094 0x4 hal/src/hal_delay.o + .bss 0x0000000020000098 0x10 hpl/ramecc/hpl_ramecc.o + 0x0000000020000098 device + .bss 0x00000000200000a8 0x4 hpl/sercom/hpl_sercom.o + .bss 0x00000000200000ac 0x4 hpl/tc/hpl_tc.o + .bss 0x00000000200000b0 0x38 shared/drivers/p_tcc.o + 0x00000000200000cc p_tcc_inst + .bss 0x00000000200000e8 0x60 shared/drivers/p_usart.o + 0x00000000200000f8 p_usart_debug_inst + .bss 0x0000000020000148 0x7fa4 shared/devices/p_screen.o + .bss 0x00000000200080ec 0x8 shared/thirdparty/lvgl/src/lv_core/lv_indev.o + .bss 0x00000000200080f4 0xc shared/thirdparty/lvgl/src/lv_core/lv_obj.o + .bss 0x0000000020008100 0x8 shared/thirdparty/lvgl/src/lv_core/lv_refr.o + .bss 0x0000000020008108 0x3c0 shared/thirdparty/lvgl/src/lv_draw/lv_draw_blend.o + .bss 0x00000000200084c8 0x108 shared/thirdparty/lvgl/src/lv_draw/lv_draw_label.o + .bss 0x00000000200085d0 0x2 shared/thirdparty/lvgl/src/lv_draw/lv_img_cache.o + *fill* 0x00000000200085d2 0x2 + .bss 0x00000000200085d4 0x14 shared/thirdparty/lvgl/src/lv_font/lv_font_fmt_txt.o + .bss 0x00000000200085e8 0x4 shared/thirdparty/lvgl/src/lv_hal/lv_hal_disp.o + .bss 0x00000000200085ec 0x8 shared/thirdparty/lvgl/src/lv_hal/lv_hal_tick.o + .bss 0x00000000200085f4 0xc shared/thirdparty/lvgl/src/lv_misc/lv_anim.o + .bss 0x0000000020008600 0x184 shared/thirdparty/lvgl/src/lv_misc/lv_gc.o + 0x0000000020008600 _lv_task_ll + 0x000000002000860c _lv_disp_ll + 0x0000000020008618 _lv_indev_ll + 0x0000000020008624 _lv_drv_ll + 0x0000000020008630 _lv_file_ll + 0x000000002000863c _lv_anim_ll + 0x0000000020008648 _lv_group_ll + 0x0000000020008654 _lv_img_defoder_ll + 0x0000000020008660 _lv_obj_style_trans_ll + 0x000000002000866c _lv_img_cache_array + 0x0000000020008670 _lv_task_act + 0x0000000020008674 _lv_mem_buf + 0x00000000200086f4 _lv_draw_mask_list + 0x0000000020008774 _lv_theme_material_styles + 0x0000000020008778 _lv_theme_template_styles + 0x000000002000877c _lv_theme_mono_styles + 0x0000000020008780 _lv_theme_empty_styles + .bss 0x0000000020008784 0x4 shared/thirdparty/lvgl/src/lv_misc/lv_log.o + .bss 0x0000000020008788 0x402c shared/thirdparty/lvgl/src/lv_misc/lv_mem.o + .bss 0x000000002000c7b4 0x1c shared/thirdparty/lvgl/src/lv_misc/lv_task.o + .bss 0x000000002000c7d0 0x4 shared/thirdparty/lvgl/src/lv_themes/lv_theme.o + .bss 0x000000002000c7d4 0x24 shared/thirdparty/lvgl/src/lv_themes/lv_theme_material.o + .bss 0x000000002000c7f8 0x4 shared/thirdparty/lvgl/src/lv_widgets/lv_img.o + .bss 0x000000002000c7fc 0x4 shared/thirdparty/lvgl/src/lv_widgets/lv_label.o + *(COMMON) + 0x000000002000c800 . = ALIGN (0x4) + 0x000000002000c800 _ebss = . + 0x000000002000c800 _ezero = . + +.stack 0x000000002000c800 0xc000 load address 0x0000000000030ee8 + 0x000000002000c800 . = ALIGN (0x8) + 0x000000002000c800 _sstack = . + 0x0000000020018800 . = (. + STACK_SIZE) + *fill* 0x000000002000c800 0xc000 + 0x0000000020018800 . = ALIGN (0x8) + 0x0000000020018800 _estack = . + 0x0000000020018800 . = ALIGN (0x4) + 0x0000000020018800 _end = . +OUTPUT(AtmelStart.elf elf32-littlearm) +LOAD linker stubs + +.ARM.attributes + 0x0000000000000000 0x2e + .ARM.attributes + 0x0000000000000000 0x1e /usr/lib/gcc/arm-none-eabi/11.2.1/thumb/v7e-m/nofp/crti.o + .ARM.attributes + 0x000000000000001e 0x2e /usr/lib/gcc/arm-none-eabi/11.2.1/thumb/v7e-m/nofp/crtbegin.o + .ARM.attributes + 0x000000000000004c 0x32 hal/src/hal_io.o + .ARM.attributes + 0x000000000000007e 0x32 hpl/core/hpl_core_m4.o + .ARM.attributes + 0x00000000000000b0 0x32 hal/src/hal_timer.o + .ARM.attributes + 0x00000000000000e2 0x32 hal/src/hal_delay.o + .ARM.attributes + 0x0000000000000114 0x32 hpl/core/hpl_init.o + .ARM.attributes + 0x0000000000000146 0x32 hpl/ramecc/hpl_ramecc.o + .ARM.attributes + 0x0000000000000178 0x32 hal/utils/src/utils_list.o + .ARM.attributes + 0x00000000000001aa 0x32 hal/utils/src/utils_assert.o + .ARM.attributes + 0x00000000000001dc 0x32 hpl/oscctrl/hpl_oscctrl.o + .ARM.attributes + 0x000000000000020e 0x32 hpl/mclk/hpl_mclk.o + .ARM.attributes + 0x0000000000000240 0x32 hpl/sercom/hpl_sercom.o + .ARM.attributes + 0x0000000000000272 0x32 hpl/gclk/hpl_gclk.o + .ARM.attributes + 0x00000000000002a4 0x32 gcc/gcc/startup_same54.o + .ARM.attributes + 0x00000000000002d6 0x32 main.o + .ARM.attributes + 0x0000000000000308 0x32 oracle.o + .ARM.attributes + 0x000000000000033a 0x32 hpl/osc32kctrl/hpl_osc32kctrl.o + .ARM.attributes + 0x000000000000036c 0x32 hal/src/hal_usart_async.o + .ARM.attributes + 0x000000000000039e 0x32 hal/utils/src/utils_ringbuffer.o + .ARM.attributes + 0x00000000000003d0 0x32 hpl/tc/hpl_tc.o + .ARM.attributes + 0x0000000000000402 0x32 hal/src/hal_atomic.o + .ARM.attributes + 0x0000000000000434 0x32 shared/drivers/p_gpio.o + .ARM.attributes + 0x0000000000000466 0x32 shared/drivers/p_i2c.o + .ARM.attributes + 0x0000000000000498 0x32 shared/drivers/p_tcc.o + .ARM.attributes + 0x00000000000004ca 0x32 shared/drivers/p_usart.o + .ARM.attributes + 0x00000000000004fc 0x32 shared/devices/p_screen.o + .ARM.attributes + 0x000000000000052e 0x32 shared/devices/display/p_ssd1963.o + .ARM.attributes + 0x0000000000000560 0x32 shared/thirdparty/lvgl/src/lv_core/lv_debug.o + .ARM.attributes + 0x0000000000000592 0x32 shared/thirdparty/lvgl/src/lv_core/lv_disp.o + .ARM.attributes + 0x00000000000005c4 0x32 shared/thirdparty/lvgl/src/lv_core/lv_group.o + .ARM.attributes + 0x00000000000005f6 0x32 shared/thirdparty/lvgl/src/lv_core/lv_indev.o + .ARM.attributes + 0x0000000000000628 0x32 shared/thirdparty/lvgl/src/lv_core/lv_obj.o + .ARM.attributes + 0x000000000000065a 0x32 shared/thirdparty/lvgl/src/lv_core/lv_refr.o + .ARM.attributes + 0x000000000000068c 0x32 shared/thirdparty/lvgl/src/lv_core/lv_style.o + .ARM.attributes + 0x00000000000006be 0x32 shared/thirdparty/lvgl/src/lv_draw/lv_draw_blend.o + .ARM.attributes + 0x00000000000006f0 0x32 shared/thirdparty/lvgl/src/lv_draw/lv_draw_img.o + .ARM.attributes + 0x0000000000000722 0x32 shared/thirdparty/lvgl/src/lv_draw/lv_draw_label.o + .ARM.attributes + 0x0000000000000754 0x32 shared/thirdparty/lvgl/src/lv_draw/lv_draw_line.o + .ARM.attributes + 0x0000000000000786 0x32 shared/thirdparty/lvgl/src/lv_draw/lv_draw_mask.o + .ARM.attributes + 0x00000000000007b8 0x32 shared/thirdparty/lvgl/src/lv_draw/lv_draw_rect.o + .ARM.attributes + 0x00000000000007ea 0x32 shared/thirdparty/lvgl/src/lv_draw/lv_img_buf.o + .ARM.attributes + 0x000000000000081c 0x32 shared/thirdparty/lvgl/src/lv_draw/lv_img_cache.o + .ARM.attributes + 0x000000000000084e 0x32 shared/thirdparty/lvgl/src/lv_draw/lv_img_decoder.o + .ARM.attributes + 0x0000000000000880 0x32 shared/thirdparty/lvgl/src/lv_font/lv_font.o + .ARM.attributes + 0x00000000000008b2 0x32 shared/thirdparty/lvgl/src/lv_font/lv_font_fmt_txt.o + .ARM.attributes + 0x00000000000008e4 0x32 shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_16.o + .ARM.attributes + 0x0000000000000916 0x32 shared/thirdparty/lvgl/src/lv_hal/lv_hal_disp.o + .ARM.attributes + 0x0000000000000948 0x32 shared/thirdparty/lvgl/src/lv_hal/lv_hal_indev.o + .ARM.attributes + 0x000000000000097a 0x32 shared/thirdparty/lvgl/src/lv_hal/lv_hal_tick.o + .ARM.attributes + 0x00000000000009ac 0x32 shared/thirdparty/lvgl/src/lv_misc/lv_anim.o + .ARM.attributes + 0x00000000000009de 0x32 shared/thirdparty/lvgl/src/lv_misc/lv_area.o + .ARM.attributes + 0x0000000000000a10 0x32 shared/thirdparty/lvgl/src/lv_misc/lv_color.o + .ARM.attributes + 0x0000000000000a42 0x32 shared/thirdparty/lvgl/src/lv_misc/lv_fs.o + .ARM.attributes + 0x0000000000000a74 0x32 shared/thirdparty/lvgl/src/lv_misc/lv_gc.o + .ARM.attributes + 0x0000000000000aa6 0x32 shared/thirdparty/lvgl/src/lv_misc/lv_ll.o + .ARM.attributes + 0x0000000000000ad8 0x32 shared/thirdparty/lvgl/src/lv_misc/lv_log.o + .ARM.attributes + 0x0000000000000b0a 0x32 shared/thirdparty/lvgl/src/lv_misc/lv_math.o + .ARM.attributes + 0x0000000000000b3c 0x32 shared/thirdparty/lvgl/src/lv_misc/lv_mem.o + .ARM.attributes + 0x0000000000000b6e 0x32 shared/thirdparty/lvgl/src/lv_misc/lv_printf.o + .ARM.attributes + 0x0000000000000ba0 0x32 shared/thirdparty/lvgl/src/lv_misc/lv_task.o + .ARM.attributes + 0x0000000000000bd2 0x32 shared/thirdparty/lvgl/src/lv_misc/lv_txt.o + .ARM.attributes + 0x0000000000000c04 0x32 shared/thirdparty/lvgl/src/lv_misc/lv_utils.o + .ARM.attributes + 0x0000000000000c36 0x32 shared/thirdparty/lvgl/src/lv_themes/lv_theme.o + .ARM.attributes + 0x0000000000000c68 0x32 shared/thirdparty/lvgl/src/lv_themes/lv_theme_material.o + .ARM.attributes + 0x0000000000000c9a 0x32 shared/thirdparty/lvgl/src/lv_widgets/lv_img.o + .ARM.attributes + 0x0000000000000ccc 0x32 shared/thirdparty/lvgl/src/lv_widgets/lv_label.o + .ARM.attributes + 0x0000000000000cfe 0x1e /usr/lib/gcc/arm-none-eabi/11.2.1/thumb/v7e-m/nofp/libgcc.a(_aeabi_uldivmod.o) + .ARM.attributes + 0x0000000000000d1c 0x2e /usr/lib/gcc/arm-none-eabi/11.2.1/thumb/v7e-m/nofp/libgcc.a(_udivmoddi4.o) + .ARM.attributes + 0x0000000000000d4a 0x1e /usr/lib/gcc/arm-none-eabi/11.2.1/thumb/v7e-m/nofp/libgcc.a(_dvmd_tls.o) + .ARM.attributes + 0x0000000000000d68 0x2e /usr/lib/gcc/arm-none-eabi/11.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-init.o) + .ARM.attributes + 0x0000000000000d96 0x2e /usr/lib/gcc/arm-none-eabi/11.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-memcmp.o) + .ARM.attributes + 0x0000000000000dc4 0x2e /usr/lib/gcc/arm-none-eabi/11.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-memcpy-stub.o) + .ARM.attributes + 0x0000000000000df2 0x2e /usr/lib/gcc/arm-none-eabi/11.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-memmove.o) + .ARM.attributes + 0x0000000000000e20 0x2e /usr/lib/gcc/arm-none-eabi/11.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-memset.o) + .ARM.attributes + 0x0000000000000e4e 0x1c /usr/lib/gcc/arm-none-eabi/11.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-strcmp.o) + .ARM.attributes + 0x0000000000000e6a 0x2e /usr/lib/gcc/arm-none-eabi/11.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-strcpy.o) + .ARM.attributes + 0x0000000000000e98 0x17 /usr/lib/gcc/arm-none-eabi/11.2.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp/libc_nano.a(lib_a-strlen.o) + .ARM.attributes + 0x0000000000000eaf 0x2e /usr/lib/gcc/arm-none-eabi/11.2.1/thumb/v7e-m/nofp/crtend.o + .ARM.attributes + 0x0000000000000edd 0x1e /usr/lib/gcc/arm-none-eabi/11.2.1/thumb/v7e-m/nofp/crtn.o + +.comment 0x0000000000000000 0x64 + .comment 0x0000000000000000 0x32 /usr/lib/gcc/arm-none-eabi/11.2.1/thumb/v7e-m/nofp/crtbegin.o + 0x33 (size before relaxing) + .comment 0x0000000000000032 0x33 hal/src/hal_io.o + .comment 0x0000000000000032 0x33 hpl/core/hpl_core_m4.o + .comment 0x0000000000000032 0x33 hal/src/hal_timer.o + .comment 0x0000000000000032 0x33 hal/src/hal_delay.o + .comment 0x0000000000000032 0x33 hpl/core/hpl_init.o + .comment 0x0000000000000032 0x33 hpl/ramecc/hpl_ramecc.o + .comment 0x0000000000000032 0x33 hal/utils/src/utils_list.o + .comment 0x0000000000000032 0x33 hal/utils/src/utils_assert.o + .comment 0x0000000000000032 0x33 hpl/oscctrl/hpl_oscctrl.o + .comment 0x0000000000000032 0x33 hpl/mclk/hpl_mclk.o + .comment 0x0000000000000032 0x33 hpl/sercom/hpl_sercom.o + .comment 0x0000000000000032 0x33 hpl/gclk/hpl_gclk.o + .comment 0x0000000000000032 0x33 gcc/gcc/startup_same54.o + .comment 0x0000000000000032 0x33 main.o + .comment 0x0000000000000032 0x33 oracle.o + .comment 0x0000000000000032 0x33 hpl/osc32kctrl/hpl_osc32kctrl.o + .comment 0x0000000000000032 0x33 hal/src/hal_usart_async.o + .comment 0x0000000000000032 0x33 hal/utils/src/utils_ringbuffer.o + .comment 0x0000000000000032 0x33 hpl/tc/hpl_tc.o + .comment 0x0000000000000032 0x33 hal/src/hal_atomic.o + .comment 0x0000000000000032 0x33 shared/drivers/p_gpio.o + .comment 0x0000000000000032 0x33 shared/drivers/p_i2c.o + .comment 0x0000000000000032 0x33 shared/drivers/p_tcc.o + .comment 0x0000000000000032 0x33 shared/drivers/p_usart.o + .comment 0x0000000000000032 0x33 shared/devices/p_screen.o + .comment 0x0000000000000032 0x33 shared/devices/display/p_ssd1963.o + .comment 0x0000000000000032 0x33 shared/thirdparty/lvgl/src/lv_core/lv_debug.o + .comment 0x0000000000000032 0x33 shared/thirdparty/lvgl/src/lv_core/lv_disp.o + .comment 0x0000000000000032 0x33 shared/thirdparty/lvgl/src/lv_core/lv_group.o + .comment 0x0000000000000032 0x33 shared/thirdparty/lvgl/src/lv_core/lv_indev.o + .comment 0x0000000000000032 0x33 shared/thirdparty/lvgl/src/lv_core/lv_obj.o + .comment 0x0000000000000032 0x33 shared/thirdparty/lvgl/src/lv_core/lv_refr.o + .comment 0x0000000000000032 0x33 shared/thirdparty/lvgl/src/lv_core/lv_style.o + .comment 0x0000000000000032 0x33 shared/thirdparty/lvgl/src/lv_draw/lv_draw_blend.o + .comment 0x0000000000000032 0x33 shared/thirdparty/lvgl/src/lv_draw/lv_draw_img.o + .comment 0x0000000000000032 0x33 shared/thirdparty/lvgl/src/lv_draw/lv_draw_label.o + .comment 0x0000000000000032 0x33 shared/thirdparty/lvgl/src/lv_draw/lv_draw_line.o + .comment 0x0000000000000032 0x33 shared/thirdparty/lvgl/src/lv_draw/lv_draw_mask.o + .comment 0x0000000000000032 0x33 shared/thirdparty/lvgl/src/lv_draw/lv_draw_rect.o + .comment 0x0000000000000032 0x33 shared/thirdparty/lvgl/src/lv_draw/lv_img_buf.o + .comment 0x0000000000000032 0x33 shared/thirdparty/lvgl/src/lv_draw/lv_img_cache.o + .comment 0x0000000000000032 0x33 shared/thirdparty/lvgl/src/lv_draw/lv_img_decoder.o + .comment 0x0000000000000032 0x33 shared/thirdparty/lvgl/src/lv_font/lv_font.o + .comment 0x0000000000000032 0x33 shared/thirdparty/lvgl/src/lv_font/lv_font_fmt_txt.o + .comment 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0x0000000000000000 0x75 + .debug_line_str + 0x0000000000000000 0x69 /usr/lib/gcc/arm-none-eabi/11.2.1/thumb/v7e-m/nofp/libgcc.a(_aeabi_uldivmod.o) + 0xd2 (size before relaxing) + .debug_line_str + 0x0000000000000069 0xc /usr/lib/gcc/arm-none-eabi/11.2.1/thumb/v7e-m/nofp/libgcc.a(_dvmd_tls.o) + 0xda (size before relaxing) diff --git a/software/firmware/oracle_same54n19a/gcc/Makefile b/software/firmware/oracle_same54n19a/gcc/Makefile new file mode 100644 index 00000000..7f09708e --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/Makefile @@ -0,0 +1,662 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +GDB=arm-none-eabi-gdb +ifdef SystemRoot + SHELL = cmd.exe + MK_DIR = mkdir +else + ifeq ($(shell uname), Linux) + MK_DIR = mkdir -p + endif + + ifeq ($(shell uname | cut -d _ -f 1), CYGWIN) + MK_DIR = mkdir -p + endif + + ifeq ($(shell uname | cut -d _ -f 1), MINGW32) + MK_DIR = mkdir -p + endif + + ifeq ($(shell uname | cut -d _ -f 1), MINGW64) + MK_DIR = mkdir -p + endif + + ifeq ($(shell uname | cut -d _ -f 1), DARWIN) + MK_DIR = mkdir -p + endif +endif + +print-% : ; @echo $* = $($*) +# List the subdirectories for creating object files +SUB_DIRS += \ + \ +hpl/pm \ +hpl/tc \ +hpl/osc32kctrl \ +hpl/ramecc \ +hpl/dmac \ +hal/src \ +gcc \ +hpl/mclk \ +hpl/eic \ +hpl/sercom \ +hpl/gclk \ +hpl/oscctrl \ +hal/utils/src \ +gcc/gcc \ +hpl/core \ +hpl/cmcc \ +shared/drivers \ +shared/devices \ +shared/devices/display \ +shared/thirdparty/lvgl/porting \ +shared/thirdparty/lvgl/src/lv_core \ +shared/thirdparty/lvgl/src/lv_draw \ +shared/thirdparty/lvgl/src/lv_font \ +shared/thirdparty/lvgl/src/lv_gpu \ +shared/thirdparty/lvgl/src/lv_hal \ +shared/thirdparty/lvgl/src/lv_misc \ +shared/thirdparty/lvgl/src/lv_themes \ +shared/thirdparty/lvgl/src/lv_widgets \ +shared/thirdparty/lvgl/tests \ +shared/thirdparty/lvgl/tests/lv_test_core \ +shared/thirdparty/lvgl/tests/lv_test_objx + +# List the object files +OBJS += \ +hal/src/hal_io.o \ +hpl/eic/hpl_eic.o \ +hpl/core/hpl_core_m4.o \ +hal/utils/src/utils_syscalls.o \ +hal/src/hal_timer.o \ +gcc/system_same54.o \ +hal/src/hal_i2c_m_sync.o \ +hal/src/hal_delay.o \ +hpl/pm/hpl_pm.o \ +hpl/core/hpl_init.o \ +hpl/ramecc/hpl_ramecc.o \ +hal/utils/src/utils_list.o \ +hal/utils/src/utils_assert.o \ +hpl/dmac/hpl_dmac.o \ +hpl/oscctrl/hpl_oscctrl.o \ +hpl/mclk/hpl_mclk.o \ +hpl/sercom/hpl_sercom.o \ +hpl/gclk/hpl_gclk.o \ +hal/src/hal_init.o \ +gcc/gcc/startup_same54.o \ +main.o \ +oracle.o \ +hpl/osc32kctrl/hpl_osc32kctrl.o \ +driver_init.o \ +hal/src/hal_usart_async.o \ +hal/src/hal_ext_irq.o \ +hal/utils/src/utils_ringbuffer.o \ +hal/src/hal_gpio.o \ +hal/utils/src/utils_event.o \ +hal/src/hal_sleep.o \ +hal/src/hal_cache.o \ +hpl/cmcc/hpl_cmcc.o \ +atmel_start.o \ +hpl/tc/hpl_tc.o \ +hal/src/hal_atomic.o \ +shared/drivers/p_gpio.o \ +shared/drivers/p_i2c.o \ +shared/drivers/p_tcc.o \ +shared/drivers/p_usart.o \ +shared/devices/p_screen.o \ +shared/devices/display/p_ssd1963.o \ +shared/thirdparty/lvgl/porting/lv_port_disp_template.o \ +shared/thirdparty/lvgl/porting/lv_port_fs_template.o \ +shared/thirdparty/lvgl/porting/lv_port_indev_template.o \ +shared/thirdparty/lvgl/src/lv_core/lv_debug.o \ +shared/thirdparty/lvgl/src/lv_core/lv_disp.o \ +shared/thirdparty/lvgl/src/lv_core/lv_group.o \ +shared/thirdparty/lvgl/src/lv_core/lv_indev.o \ +shared/thirdparty/lvgl/src/lv_core/lv_obj.o \ +shared/thirdparty/lvgl/src/lv_core/lv_refr.o \ +shared/thirdparty/lvgl/src/lv_core/lv_style.o \ +shared/thirdparty/lvgl/src/lv_draw/lv_draw_arc.o \ +shared/thirdparty/lvgl/src/lv_draw/lv_draw_blend.o \ +shared/thirdparty/lvgl/src/lv_draw/lv_draw_img.o \ +shared/thirdparty/lvgl/src/lv_draw/lv_draw_label.o \ +shared/thirdparty/lvgl/src/lv_draw/lv_draw_line.o \ +shared/thirdparty/lvgl/src/lv_draw/lv_draw_mask.o \ +shared/thirdparty/lvgl/src/lv_draw/lv_draw_rect.o \ +shared/thirdparty/lvgl/src/lv_draw/lv_draw_triangle.o \ +shared/thirdparty/lvgl/src/lv_draw/lv_img_buf.o \ +shared/thirdparty/lvgl/src/lv_draw/lv_img_cache.o \ +shared/thirdparty/lvgl/src/lv_draw/lv_img_decoder.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_dejavu_16_persian_hebrew.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_fmt_txt.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_12.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_12_subpx.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_14.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_16.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_18.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_20.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_22.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_24.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_26.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_28.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_28_compressed.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_30.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_32.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_34.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_36.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_38.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_40.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_42.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_44.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_46.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_48.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_simsun_16_cjk.o \ +shared/thirdparty/lvgl/src/lv_font/lv_font_unscii_8.o \ +shared/thirdparty/lvgl/src/lv_gpu/lv_gpu_stm32_dma2d.o \ +shared/thirdparty/lvgl/src/lv_hal/lv_hal_disp.o \ +shared/thirdparty/lvgl/src/lv_hal/lv_hal_indev.o \ +shared/thirdparty/lvgl/src/lv_hal/lv_hal_tick.o \ +shared/thirdparty/lvgl/src/lv_misc/lv_anim.o \ +shared/thirdparty/lvgl/src/lv_misc/lv_area.o \ +shared/thirdparty/lvgl/src/lv_misc/lv_async.o \ +shared/thirdparty/lvgl/src/lv_misc/lv_bidi.o \ +shared/thirdparty/lvgl/src/lv_misc/lv_color.o \ +shared/thirdparty/lvgl/src/lv_misc/lv_fs.o \ +shared/thirdparty/lvgl/src/lv_misc/lv_gc.o \ +shared/thirdparty/lvgl/src/lv_misc/lv_ll.o \ +shared/thirdparty/lvgl/src/lv_misc/lv_log.o \ +shared/thirdparty/lvgl/src/lv_misc/lv_math.o \ +shared/thirdparty/lvgl/src/lv_misc/lv_mem.o \ +shared/thirdparty/lvgl/src/lv_misc/lv_printf.o \ +shared/thirdparty/lvgl/src/lv_misc/lv_task.o \ +shared/thirdparty/lvgl/src/lv_misc/lv_templ.o \ +shared/thirdparty/lvgl/src/lv_misc/lv_txt.o \ +shared/thirdparty/lvgl/src/lv_misc/lv_txt_ap.o \ +shared/thirdparty/lvgl/src/lv_misc/lv_utils.o \ +shared/thirdparty/lvgl/src/lv_themes/lv_theme.o \ +shared/thirdparty/lvgl/src/lv_themes/lv_theme_empty.o \ +shared/thirdparty/lvgl/src/lv_themes/lv_theme_material.o \ +shared/thirdparty/lvgl/src/lv_themes/lv_theme_mono.o \ +shared/thirdparty/lvgl/src/lv_themes/lv_theme_template.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_arc.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_bar.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_btn.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_btnmatrix.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_calendar.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_canvas.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_chart.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_checkbox.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_cont.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_cpicker.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_dropdown.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_gauge.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_img.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_imgbtn.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_keyboard.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_label.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_led.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_line.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_linemeter.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_list.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_msgbox.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_objmask.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_objx_templ.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_page.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_roller.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_slider.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_spinbox.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_spinner.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_switch.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_table.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_tabview.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_textarea.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_tileview.o \ +shared/thirdparty/lvgl/src/lv_widgets/lv_win.o \ +shared/thirdparty/lvgl/tests/lv_test_assert.o \ +shared/thirdparty/lvgl/tests/lv_test_core/lv_test_core.o \ +shared/thirdparty/lvgl/tests/lv_test_core/lv_test_obj.o \ +shared/thirdparty/lvgl/tests/lv_test_core/lv_test_style.o \ +shared/thirdparty/lvgl/tests/lv_test_main.o \ +shared/thirdparty/lvgl/tests/lv_test_objx/lv_test_cont.o + +OBJS_AS_ARGS += \ +"hal/src/hal_io.o" \ +"hpl/eic/hpl_eic.o" \ +"hpl/core/hpl_core_m4.o" \ +"hal/utils/src/utils_syscalls.o" \ +"hal/src/hal_timer.o" \ +"gcc/system_same54.o" \ +"hal/src/hal_i2c_m_sync.o" \ +"hal/src/hal_delay.o" \ +"hpl/pm/hpl_pm.o" \ +"hpl/core/hpl_init.o" \ +"hpl/ramecc/hpl_ramecc.o" \ +"hal/utils/src/utils_list.o" \ +"hal/utils/src/utils_assert.o" \ +"hpl/dmac/hpl_dmac.o" \ +"hpl/oscctrl/hpl_oscctrl.o" \ +"hpl/mclk/hpl_mclk.o" \ +"hpl/sercom/hpl_sercom.o" \ +"hpl/gclk/hpl_gclk.o" \ +"hal/src/hal_init.o" \ +"gcc/gcc/startup_same54.o" \ +"main.o" \ +"oracle.o" \ +"hpl/osc32kctrl/hpl_osc32kctrl.o" \ +"driver_init.o" \ +"hal/src/hal_usart_async.o" \ +"hal/src/hal_ext_irq.o" \ +"hal/utils/src/utils_ringbuffer.o" \ +"hal/src/hal_gpio.o" \ +"hal/utils/src/utils_event.o" \ +"hal/src/hal_sleep.o" \ +"hal/src/hal_cache.o" \ +"hpl/cmcc/hpl_cmcc.o" \ +"atmel_start.o" \ +"hpl/tc/hpl_tc.o" \ +"hal/src/hal_atomic.o" \ +"shared/drivers/p_gpio.o" \ +"shared/drivers/p_i2c.o" \ +"shared/drivers/p_tcc.o" \ +"shared/drivers/p_usart.o" \ +"shared/devices/p_screen.o" \ +"shared/devices/display/p_ssd1963.o" \ +"shared/thirdparty/lvgl/porting/lv_port_disp_template.o" \ +"shared/thirdparty/lvgl/porting/lv_port_fs_template.o" \ +"shared/thirdparty/lvgl/porting/lv_port_indev_template.o" \ +"shared/thirdparty/lvgl/src/lv_core/lv_debug.o" \ +"shared/thirdparty/lvgl/src/lv_core/lv_disp.o" \ +"shared/thirdparty/lvgl/src/lv_core/lv_group.o" \ +"shared/thirdparty/lvgl/src/lv_core/lv_indev.o" \ +"shared/thirdparty/lvgl/src/lv_core/lv_obj.o" \ +"shared/thirdparty/lvgl/src/lv_core/lv_refr.o" \ +"shared/thirdparty/lvgl/src/lv_core/lv_style.o" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_draw_arc.o" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_draw_blend.o" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_draw_img.o" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_draw_label.o" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_draw_line.o" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_draw_mask.o" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_draw_rect.o" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_draw_triangle.o" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_img_buf.o" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_img_cache.o" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_img_decoder.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_dejavu_16_persian_hebrew.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_fmt_txt.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_12.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_12_subpx.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_14.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_16.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_18.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_20.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_22.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_24.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_26.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_28.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_28_compressed.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_30.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_32.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_34.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_36.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_38.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_40.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_42.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_44.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_46.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_48.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_simsun_16_cjk.o" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_unscii_8.o" \ +"shared/thirdparty/lvgl/src/lv_gpu/lv_gpu_stm32_dma2d.o" \ +"shared/thirdparty/lvgl/src/lv_hal/lv_hal_disp.o" \ +"shared/thirdparty/lvgl/src/lv_hal/lv_hal_indev.o" \ +"shared/thirdparty/lvgl/src/lv_hal/lv_hal_tick.o" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_anim.o" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_area.o" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_async.o" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_bidi.o" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_color.o" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_fs.o" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_gc.o" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_ll.o" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_log.o" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_math.o" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_mem.o" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_printf.o" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_task.o" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_templ.o" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_txt.o" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_txt_ap.o" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_utils.o" \ +"shared/thirdparty/lvgl/src/lv_themes/lv_theme.o" \ +"shared/thirdparty/lvgl/src/lv_themes/lv_theme_empty.o" \ +"shared/thirdparty/lvgl/src/lv_themes/lv_theme_material.o" \ +"shared/thirdparty/lvgl/src/lv_themes/lv_theme_mono.o" \ +"shared/thirdparty/lvgl/src/lv_themes/lv_theme_template.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_arc.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_bar.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_btn.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_btnmatrix.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_calendar.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_canvas.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_chart.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_checkbox.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_cont.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_cpicker.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_dropdown.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_gauge.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_img.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_imgbtn.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_keyboard.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_label.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_led.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_line.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_linemeter.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_list.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_msgbox.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_objmask.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_objx_templ.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_page.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_roller.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_slider.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_spinbox.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_spinner.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_switch.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_table.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_tabview.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_textarea.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_tileview.o" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_win.o" \ +"shared/thirdparty/lvgl/tests/lv_test_assert.o" \ +"shared/thirdparty/lvgl/tests/lv_test_core/lv_test_core.o" \ +"shared/thirdparty/lvgl/tests/lv_test_core/lv_test_obj.o" \ +"shared/thirdparty/lvgl/tests/lv_test_core/lv_test_style.o" \ +"shared/thirdparty/lvgl/tests/lv_test_main.o" \ +"shared/thirdparty/lvgl/tests/lv_test_objx/lv_test_cont.o" + +# List the directories containing header files +DIR_INCLUDES += \ +-I"../" \ +-I"../config" \ +-I"../hal/include" \ +-I"../hal/utils/include" \ +-I"../hpl/cmcc" \ +-I"../hpl/core" \ +-I"../hpl/dmac" \ +-I"../hpl/eic" \ +-I"../hpl/gclk" \ +-I"../hpl/mclk" \ +-I"../hpl/osc32kctrl" \ +-I"../hpl/oscctrl" \ +-I"../hpl/pm" \ +-I"../hpl/port" \ +-I"../hpl/ramecc" \ +-I"../hpl/sercom" \ +-I"../hpl/tc" \ +-I"../hri" \ +-I"../CMSIS/Core/Include" \ +-I"../include" \ +-I"../shared/thirdparty" \ +-I"../shared/thirdparty/lvgl" \ +-I"../shared/drivers" \ +-I"../shared/devices" \ +-I"../shared/devices/display" + +# List the dependency files +DEPS := $(OBJS:%.o=%.d) + +DEPS_AS_ARGS += \ +"hal/utils/src/utils_event.d" \ +"hal/src/hal_io.d" \ +"hpl/ramecc/hpl_ramecc.d" \ +"hpl/core/hpl_core_m4.d" \ +"hpl/eic/hpl_eic.d" \ +"hal/utils/src/utils_syscalls.d" \ +"hal/src/hal_i2c_m_sync.d" \ +"hal/src/hal_timer.d" \ +"hal/utils/src/utils_list.d" \ +"hpl/cmcc/hpl_cmcc.d" \ +"hpl/dmac/hpl_dmac.d" \ +"hal/utils/src/utils_assert.d" \ +"hal/src/hal_delay.d" \ +"hpl/core/hpl_init.d" \ +"hpl/pm/hpl_pm.d" \ +"hpl/gclk/hpl_gclk.d" \ +"hpl/sercom/hpl_sercom.d" \ +"gcc/gcc/startup_same54.d" \ +"hal/src/hal_init.d" \ +"hpl/mclk/hpl_mclk.d" \ +"driver_init.d" \ +"hal/src/hal_usart_async.d" \ +"hpl/osc32kctrl/hpl_osc32kctrl.d" \ +"main.d" \ +"hal/src/hal_cache.d" \ +"hal/src/hal_sleep.d" \ +"hal/utils/src/utils_ringbuffer.d" \ +"hal/src/hal_ext_irq.d" \ +"hal/src/hal_gpio.d" \ +"hal/src/hal_atomic.d" \ +"hpl/tc/hpl_tc.d" \ +"hpl/oscctrl/hpl_oscctrl.d" \ +"gcc/system_same54.d" \ +"atmel_start.d" \ +"shared/drivers/p_gpio.d" \ +"shared/drivers/p_i2c.d" \ +"shared/drivers/p_tcc.d" \ +"shared/drivers/p_usart.d" \ +"shared/devices/p_screen.d" \ +"shared/devices/display/p_ssd1963.d" \ +"shared/thirdparty/lvgl/porting/lv_port_disp_template.d" \ +"shared/thirdparty/lvgl/porting/lv_port_fs_template.d" \ +"shared/thirdparty/lvgl/porting/lv_port_indev_template.d" \ +"shared/thirdparty/lvgl/src/lv_core/lv_debug.d" \ +"shared/thirdparty/lvgl/src/lv_core/lv_disp.d" \ +"shared/thirdparty/lvgl/src/lv_core/lv_group.d" \ +"shared/thirdparty/lvgl/src/lv_core/lv_indev.d" \ +"shared/thirdparty/lvgl/src/lv_core/lv_obj.d" \ +"shared/thirdparty/lvgl/src/lv_core/lv_refr.d" \ +"shared/thirdparty/lvgl/src/lv_core/lv_style.d" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_draw_arc.d" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_draw_blend.d" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_draw_img.d" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_draw_label.d" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_draw_line.d" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_draw_mask.d" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_draw_rect.d" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_draw_triangle.d" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_img_buf.d" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_img_cache.d" \ +"shared/thirdparty/lvgl/src/lv_draw/lv_img_decoder.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_dejavu_16_persian_hebrew.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_fmt_txt.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_12.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_12_subpx.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_14.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_16.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_18.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_20.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_22.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_24.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_26.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_28.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_28_compressed.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_30.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_32.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_34.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_36.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_38.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_40.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_42.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_44.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_46.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_48.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_simsun_16_cjk.d" \ +"shared/thirdparty/lvgl/src/lv_font/lv_font_unscii_8.d" \ +"shared/thirdparty/lvgl/src/lv_gpu/lv_gpu_stm32_dma2d.d" \ +"shared/thirdparty/lvgl/src/lv_hal/lv_hal_disp.d" \ +"shared/thirdparty/lvgl/src/lv_hal/lv_hal_indev.d" \ +"shared/thirdparty/lvgl/src/lv_hal/lv_hal_tick.d" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_anim.d" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_area.d" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_async.d" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_bidi.d" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_color.d" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_fs.d" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_gc.d" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_ll.d" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_log.d" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_math.d" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_mem.d" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_printf.d" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_task.d" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_templ.d" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_txt.d" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_txt_ap.d" \ +"shared/thirdparty/lvgl/src/lv_misc/lv_utils.d" \ +"shared/thirdparty/lvgl/src/lv_themes/lv_theme.d" \ +"shared/thirdparty/lvgl/src/lv_themes/lv_theme_empty.d" \ +"shared/thirdparty/lvgl/src/lv_themes/lv_theme_material.d" \ +"shared/thirdparty/lvgl/src/lv_themes/lv_theme_mono.d" \ +"shared/thirdparty/lvgl/src/lv_themes/lv_theme_template.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_arc.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_bar.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_btn.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_btnmatrix.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_calendar.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_canvas.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_chart.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_checkbox.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_cont.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_cpicker.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_dropdown.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_gauge.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_img.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_imgbtn.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_keyboard.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_label.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_led.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_line.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_linemeter.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_list.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_msgbox.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_objmask.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_objx_templ.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_page.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_roller.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_slider.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_spinbox.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_spinner.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_switch.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_table.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_tabview.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_textarea.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_tileview.d" \ +"shared/thirdparty/lvgl/src/lv_widgets/lv_win.d" \ +"shared/thirdparty/lvgl/tests/lv_test_assert.d" \ +"shared/thirdparty/lvgl/tests/lv_test_core/lv_test_core.d" \ +"shared/thirdparty/lvgl/tests/lv_test_core/lv_test_obj.d" \ +"shared/thirdparty/lvgl/tests/lv_test_core/lv_test_style.d" \ +"shared/thirdparty/lvgl/tests/lv_test_main.d" \ +"shared/thirdparty/lvgl/tests/lv_test_objx/lv_test_cont.d" + +OUTPUT_FILE_NAME :=AtmelStart +QUOTE := " +OUTPUT_FILE_PATH +=$(OUTPUT_FILE_NAME).elf +OUTPUT_FILE_PATH_AS_ARGS +=$(OUTPUT_FILE_NAME).elf + +vpath %.c ../ +vpath %.s ../ +vpath %.S ../ + +# All Target +all: $(SUB_DIRS) $(OUTPUT_FILE_PATH) + +# Linker target + +$(OUTPUT_FILE_PATH): $(OBJS) + @echo Building target: $@ + @echo Invoking: ARM/GNU Linker + $(QUOTE)arm-none-eabi-gcc$(QUOTE) -o $(OUTPUT_FILE_NAME).elf $(OBJS_AS_ARGS) -Wl,--start-group -lm -Wl,--end-group -mthumb \ +-Wl,-Map="$(OUTPUT_FILE_NAME).map" --specs=nano.specs -Wl,--gc-sections -mcpu=cortex-m4 \ + \ +-T"../gcc/gcc/same54n19a_flash.ld" \ +-L"../gcc/gcc" + @echo Finished building target: $@ + + "arm-none-eabi-objcopy" -O binary "$(OUTPUT_FILE_NAME).elf" "$(OUTPUT_FILE_NAME).bin" + "arm-none-eabi-objcopy" -O ihex -R .eeprom -R .fuse -R .lock -R .signature \ + "$(OUTPUT_FILE_NAME).elf" "$(OUTPUT_FILE_NAME).hex" + "arm-none-eabi-objcopy" -j .eeprom --set-section-flags=.eeprom=alloc,load --change-section-lma \ + .eeprom=0 --no-change-warnings -O binary "$(OUTPUT_FILE_NAME).elf" \ + "$(OUTPUT_FILE_NAME).eep" || exit 0 + "arm-none-eabi-objdump" -h -S "$(OUTPUT_FILE_NAME).elf" > "$(OUTPUT_FILE_NAME).lss" + "arm-none-eabi-size" "$(OUTPUT_FILE_NAME).elf" + + + +# Compiler targets + + + + +%.o: %.c + @echo Building file: $< + @echo ARM/GNU C Compiler + $(QUOTE)arm-none-eabi-gcc$(QUOTE) -x c -mthumb -DDEBUG -DLV_CONF_INCLUDE_SIMPLE -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \ +-D__SAME54N19A__ -mcpu=cortex-m4 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 \ +$(DIR_INCLUDES) \ +-MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + +%.o: %.s + @echo Building file: $< + @echo ARM/GNU Assembler + $(QUOTE)arm-none-eabi-as$(QUOTE) -x c -mthumb -DDEBUG -DLV_CONF_INCLUDE_SIMPLE -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \ +-D__SAME54N19A__ -mcpu=cortex-m4 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 \ +$(DIR_INCLUDES) \ +-MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + +%.o: %.S + @echo Building file: $< + @echo ARM/GNU Preprocessing Assembler + $(QUOTE)arm-none-eabi-gcc$(QUOTE) -x c -mthumb -DDEBUG -DLV_CONF_INCLUDE_SIMPLE -Os -ffunction-sections -mlong-calls -g3 -Wall -c -std=gnu99 \ +-D__SAME54N19A__ -mcpu=cortex-m4 -mfloat-abi=softfp -mfpu=fpv4-sp-d16 \ +$(DIR_INCLUDES) \ +-MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<" + @echo Finished building: $< + +# Detect changes in the dependent files and recompile the respective object files. +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(DEPS)),) +-include $(DEPS) +endif +endif + +$(SUB_DIRS): + $(MK_DIR) "$@" + +clean: + rm -f $(OBJS_AS_ARGS) + rm -f $(OUTPUT_FILE_PATH) + rm -f $(DEPS) + rm -f $(DEPS_AS_ARGS) + rm -f $(OUTPUT_FILE_NAME).a $(OUTPUT_FILE_NAME).hex $(OUTPUT_FILE_NAME).bin \ + $(OUTPUT_FILE_NAME).lss $(OUTPUT_FILE_NAME).eep $(OUTPUT_FILE_NAME).map \ + $(OUTPUT_FILE_NAME).srec + +push:\ +all + @echo $(QUOTE)$(QUOTE) + @echo $(QUOTE)Uploading $(OUTPUT_FILE_NAME).elf...$(QUOTE) + @$(GDB) $(OUTPUT_FILE_NAME).elf -x $(QUOTE)../scripts/push.gdb$(QUOTE) >/dev/null + @echo $(QUOTE)$(QUOTE)$(OUTPUT_FILE_NAME).elf $(QUOTE) uploaded!$(QUOTE) + @$(QUOTE)$(SIZE)$(QUOTE) $(QUOTE)$(OUTPUT_FILE_NAME).elf$(QUOTE) + +debug:\ +all + @$(GDB) $(OUTPUT_FILE_NAME).elf -x $(QUOTE)../scripts/debug.gdb$(QUOTE) diff --git a/software/firmware/oracle_same54n19a/gcc/atmel_start.d b/software/firmware/oracle_same54n19a/gcc/atmel_start.d new file mode 100644 index 00000000..4f584ff5 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/atmel_start.d @@ -0,0 +1,288 @@ +atmel_start.d atmel_start.o: ../atmel_start.c ../atmel_start.h \ + ../driver_init.h ../atmel_start_pins.h ../hal/include/hal_gpio.h \ + ../hal/include/hpl_gpio.h ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h ../hpl/port/hpl_gpio_base.h \ + ../hal/utils/include/utils_assert.h ../config/hpl_port_config.h \ + ../hal/include/hal_delay.h ../hal/include/hpl_irq.h \ + ../hal/include/hpl_reset.h ../hal/include/hpl_sleep.h \ + ../hal/include/hal_init.h ../hal/include/hpl_init.h \ + ../hal/include/hal_io.h ../hal/include/hal_sleep.h \ + ../hal/include/hal_ext_irq.h ../hal/include/hpl_ext_irq.h \ + ../hal/include/hal_usart_async.h ../hal/include/hal_io.h \ + ../hal/include/hpl_usart_async.h ../hal/include/hpl_usart.h \ + ../hal/include/hpl_irq.h ../hal/utils/include/utils_ringbuffer.h \ + ../hal/utils/include/compiler.h ../hal/utils/include/utils_assert.h \ + ../hal/include/hal_i2c_m_sync.h ../hal/include/hpl_i2c_m_sync.h \ + ../hal/include/hal_timer.h ../hal/utils/include/utils_list.h \ + ../hal/include/hpl_timer.h ../hpl/tc/hpl_tc_base.h \ + ../hal/include/hpl_pwm.h +../atmel_start.h: +../driver_init.h: +../atmel_start_pins.h: +../hal/include/hal_gpio.h: +../hal/include/hpl_gpio.h: +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: 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"/storage/Shared/Projects/Embedded-Graphics-Learning/software/firmware/oracle_same54n19a/gcc", + "file": "../atmel_start.c" + }, + { + "arguments": [ + "arm-none-eabi-gcc", + "-c", + "-x", + "c", + "-mthumb", + "-DDEBUG", + "-DLV_CONF_INCLUDE_SIMPLE", + "-Os", + "-ffunction-sections", + "-mlong-calls", + "-g3", + "-Wall", + "-std=gnu99", + "-D__SAME54N19A__", + "-mcpu=cortex-m4", + "-mfloat-abi=softfp", + "-mfpu=fpv4-sp-d16", + "-I../", + "-I../config", + "-I../hal/include", + "-I../hal/utils/include", + "-I../hpl/cmcc", + "-I../hpl/core", + "-I../hpl/dmac", + "-I../hpl/eic", + "-I../hpl/gclk", + "-I../hpl/mclk", + "-I../hpl/osc32kctrl", + "-I../hpl/oscctrl", + "-I../hpl/pm", + "-I../hpl/port", + "-I../hpl/ramecc", + "-I../hpl/sercom", + "-I../hpl/tc", + "-I../hri", + "-I../CMSIS/Core/Include", + "-I../include", + "-I../shared/thirdparty", + "-I../shared/thirdparty/lvgl", + "-I../shared/drivers", + "-I../shared/devices", + "-I../shared/devices/display", + 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"-mlong-calls", + "-g3", + "-Wall", + "-std=gnu99", + "-D__SAME54N19A__", + "-mcpu=cortex-m4", + "-mfloat-abi=softfp", + "-mfpu=fpv4-sp-d16", + "-I../", + "-I../config", + "-I../hal/include", + "-I../hal/utils/include", + "-I../hpl/cmcc", + "-I../hpl/core", + "-I../hpl/dmac", + "-I../hpl/eic", + "-I../hpl/gclk", + "-I../hpl/mclk", + "-I../hpl/osc32kctrl", + "-I../hpl/oscctrl", + "-I../hpl/pm", + "-I../hpl/port", + "-I../hpl/ramecc", + "-I../hpl/sercom", + "-I../hpl/tc", + "-I../hri", + "-I../CMSIS/Core/Include", + "-I../include", + "-I../shared/thirdparty", + "-I../shared/thirdparty/lvgl", + "-I../shared/drivers", + "-I../shared/devices", + "-I../shared/devices/display", + "-MTshared/thirdparty/lvgl/src/lv_core/lv_indev.d", + "-MTshared/thirdparty/lvgl/src/lv_core/lv_indev.o", + "-o", + "shared/thirdparty/lvgl/src/lv_core/lv_indev.o", + "../shared/thirdparty/lvgl/src/lv_core/lv_indev.c" + ], + "directory": "/storage/Shared/Projects/Embedded-Graphics-Learning/software/firmware/oracle_same54n19a/gcc", + "file": "../shared/thirdparty/lvgl/src/lv_core/lv_indev.c" + }, + { + "arguments": [ + "arm-none-eabi-gcc", + "-c", + "-x", + "c", + "-mthumb", + "-DDEBUG", + "-DLV_CONF_INCLUDE_SIMPLE", + "-Os", + "-ffunction-sections", + "-mlong-calls", + "-g3", + "-Wall", + "-std=gnu99", + "-D__SAME54N19A__", + "-mcpu=cortex-m4", + "-mfloat-abi=softfp", + "-mfpu=fpv4-sp-d16", + "-I../", + "-I../config", + "-I../hal/include", + "-I../hal/utils/include", + "-I../hpl/cmcc", + "-I../hpl/core", + "-I../hpl/dmac", + "-I../hpl/eic", + "-I../hpl/gclk", + "-I../hpl/mclk", + "-I../hpl/osc32kctrl", + "-I../hpl/oscctrl", + "-I../hpl/pm", + "-I../hpl/port", + "-I../hpl/ramecc", + "-I../hpl/sercom", + "-I../hpl/tc", + "-I../hri", + "-I../CMSIS/Core/Include", + "-I../include", + "-I../shared/thirdparty", + "-I../shared/thirdparty/lvgl", + "-I../shared/drivers", + "-I../shared/devices", + "-I../shared/devices/display", + "-MTshared/thirdparty/lvgl/src/lv_widgets/lv_tileview.d", + "-MTshared/thirdparty/lvgl/src/lv_widgets/lv_tileview.o", + "-o", + "shared/thirdparty/lvgl/src/lv_widgets/lv_tileview.o", + "../shared/thirdparty/lvgl/src/lv_widgets/lv_tileview.c" + ], + "directory": "/storage/Shared/Projects/Embedded-Graphics-Learning/software/firmware/oracle_same54n19a/gcc", + "file": "../shared/thirdparty/lvgl/src/lv_widgets/lv_tileview.c" + } +] \ No newline at end of file diff --git a/software/firmware/oracle_same54n19a/gcc/driver_init.d b/software/firmware/oracle_same54n19a/gcc/driver_init.d new file mode 100644 index 00000000..a2809a2e --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/driver_init.d @@ -0,0 +1,290 @@ +driver_init.d driver_init.o: ../driver_init.c ../driver_init.h \ + ../atmel_start_pins.h ../hal/include/hal_gpio.h \ + ../hal/include/hpl_gpio.h ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h ../hpl/port/hpl_gpio_base.h \ + ../hal/utils/include/utils_assert.h ../config/hpl_port_config.h \ + ../hal/include/hal_delay.h ../hal/include/hpl_irq.h \ + ../hal/include/hpl_reset.h ../hal/include/hpl_sleep.h \ + ../hal/include/hal_init.h ../hal/include/hpl_init.h \ + ../hal/include/hal_io.h ../hal/include/hal_sleep.h \ + ../hal/include/hal_ext_irq.h ../hal/include/hpl_ext_irq.h \ + ../hal/include/hal_usart_async.h ../hal/include/hal_io.h \ + ../hal/include/hpl_usart_async.h ../hal/include/hpl_usart.h \ + ../hal/include/hpl_irq.h ../hal/utils/include/utils_ringbuffer.h \ + ../hal/utils/include/compiler.h ../hal/utils/include/utils_assert.h \ + ../hal/include/hal_i2c_m_sync.h ../hal/include/hpl_i2c_m_sync.h \ + ../hal/include/hal_timer.h ../hal/utils/include/utils_list.h \ + ../hal/include/hpl_timer.h ../hpl/tc/hpl_tc_base.h \ + ../hal/include/hpl_pwm.h ../config/peripheral_clk_config.h \ + ../hal/utils/include/utils.h +../driver_init.h: +../atmel_start_pins.h: +../hal/include/hal_gpio.h: +../hal/include/hpl_gpio.h: +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hal/include/hal_atomic.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: +../hpl/port/hpl_gpio_base.h: +../hal/utils/include/utils_assert.h: +../config/hpl_port_config.h: +../hal/include/hal_delay.h: +../hal/include/hpl_irq.h: +../hal/include/hpl_reset.h: +../hal/include/hpl_sleep.h: +../hal/include/hal_init.h: +../hal/include/hpl_init.h: +../hal/include/hal_io.h: +../hal/include/hal_sleep.h: +../hal/include/hal_ext_irq.h: +../hal/include/hpl_ext_irq.h: +../hal/include/hal_usart_async.h: +../hal/include/hal_io.h: +../hal/include/hpl_usart_async.h: +../hal/include/hpl_usart.h: +../hal/include/hpl_irq.h: +../hal/utils/include/utils_ringbuffer.h: +../hal/utils/include/compiler.h: +../hal/utils/include/utils_assert.h: +../hal/include/hal_i2c_m_sync.h: +../hal/include/hpl_i2c_m_sync.h: +../hal/include/hal_timer.h: +../hal/utils/include/utils_list.h: +../hal/include/hpl_timer.h: +../hpl/tc/hpl_tc_base.h: +../hal/include/hpl_pwm.h: +../config/peripheral_clk_config.h: +../hal/utils/include/utils.h: diff --git a/software/firmware/oracle_same54n19a/gcc/driver_init.o b/software/firmware/oracle_same54n19a/gcc/driver_init.o new file mode 100644 index 00000000..e88735bc Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/driver_init.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/gcc/gcc/startup_same54.d b/software/firmware/oracle_same54n19a/gcc/gcc/gcc/startup_same54.d new file mode 100644 index 00000000..8d7bd23b --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/gcc/gcc/startup_same54.d @@ -0,0 +1,176 @@ +gcc/gcc/startup_same54.d gcc/gcc/startup_same54.o: \ + ../gcc/gcc/startup_same54.c ../include/same54.h ../include/same54n19a.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h +../include/same54.h: +../include/same54n19a.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: diff --git a/software/firmware/oracle_same54n19a/gcc/gcc/gcc/startup_same54.o b/software/firmware/oracle_same54n19a/gcc/gcc/gcc/startup_same54.o new file mode 100644 index 00000000..e78871ef Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/gcc/gcc/startup_same54.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/gcc/same54n19a_flash.ld b/software/firmware/oracle_same54n19a/gcc/gcc/same54n19a_flash.ld new file mode 100644 index 00000000..33b8ed9c --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/gcc/same54n19a_flash.ld @@ -0,0 +1,163 @@ +/** + * \file + * + * \brief Linker script for running in internal FLASH on the SAME54N19A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > rom + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > rom + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/software/firmware/oracle_same54n19a/gcc/gcc/same54n19a_sram.ld b/software/firmware/oracle_same54n19a/gcc/gcc/same54n19a_sram.ld new file mode 100644 index 00000000..c770c7c6 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/gcc/same54n19a_sram.ld @@ -0,0 +1,162 @@ +/** + * \file + * + * \brief Linker script for running in internal SRAM on the SAME54N19A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +SEARCH_DIR(.) + +/* Memory Spaces Definitions */ +MEMORY +{ + ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00030000 + bkupram (rwx) : ORIGIN = 0x47000000, LENGTH = 0x00002000 + qspi (rwx) : ORIGIN = 0x04000000, LENGTH = 0x01000000 +} + +/* The stack size used by the application. NOTE: you need to adjust according to your application. */ +STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0xC000; + +/* Section Definitions */ +SECTIONS +{ + .text : + { + . = ALIGN(4); + _sfixed = .; + KEEP(*(.vectors .vectors.*)) + *(.text .text.* .gnu.linkonce.t.*) + *(.glue_7t) *(.glue_7) + *(.rodata .rodata* .gnu.linkonce.r.*) + *(.ARM.extab* .gnu.linkonce.armextab.*) + + /* Support C constructors, and C destructors in both user code + and the C library. This also provides support for C++ code. */ + . = ALIGN(4); + KEEP(*(.init)) + . = ALIGN(4); + __preinit_array_start = .; + KEEP (*(.preinit_array)) + __preinit_array_end = .; + + . = ALIGN(4); + __init_array_start = .; + KEEP (*(SORT(.init_array.*))) + KEEP (*(.init_array)) + __init_array_end = .; + + . = ALIGN(4); + KEEP (*crtbegin.o(.ctors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*crtend.o(.ctors)) + + . = ALIGN(4); + KEEP(*(.fini)) + + . = ALIGN(4); + __fini_array_start = .; + KEEP (*(.fini_array)) + KEEP (*(SORT(.fini_array.*))) + __fini_array_end = .; + + KEEP (*crtbegin.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*crtend.o(.dtors)) + + . = ALIGN(4); + _efixed = .; /* End of text section */ + } > ram + + /* .ARM.exidx is sorted, so has to go in its own output section. */ + PROVIDE_HIDDEN (__exidx_start = .); + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > ram + PROVIDE_HIDDEN (__exidx_end = .); + + . = ALIGN(4); + _etext = .; + + .relocate : AT (_etext) + { + . = ALIGN(4); + _srelocate = .; + *(.ramfunc .ramfunc.*); + *(.data .data.*); + . = ALIGN(4); + _erelocate = .; + } > ram + + .bkupram (NOLOAD): + { + . = ALIGN(8); + _sbkupram = .; + *(.bkupram .bkupram.*); + . = ALIGN(8); + _ebkupram = .; + } > bkupram + + .qspi (NOLOAD): + { + . = ALIGN(8); + _sqspi = .; + *(.qspi .qspi.*); + . = ALIGN(8); + _eqspi = .; + } > qspi + + /* .bss section which is used for uninitialized data */ + .bss (NOLOAD) : + { + . = ALIGN(4); + _sbss = . ; + _szero = .; + *(.bss .bss.*) + *(COMMON) + . = ALIGN(4); + _ebss = . ; + _ezero = .; + } > ram + + /* stack section */ + .stack (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + . = . + STACK_SIZE; + . = ALIGN(8); + _estack = .; + } > ram + + . = ALIGN(4); + _end = . ; +} diff --git a/software/firmware/oracle_same54n19a/gcc/gcc/startup_same54.c b/software/firmware/oracle_same54n19a/gcc/gcc/startup_same54.c new file mode 100644 index 00000000..097a1c4d --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/gcc/startup_same54.c @@ -0,0 +1,678 @@ +/** + * \file + * + * \brief gcc starttup file for SAME54 + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#include "same54.h" + +/* Initialize segments */ +extern uint32_t _sfixed; +extern uint32_t _efixed; +extern uint32_t _etext; +extern uint32_t _srelocate; +extern uint32_t _erelocate; +extern uint32_t _szero; +extern uint32_t _ezero; +extern uint32_t _sstack; +extern uint32_t _estack; + +/** \cond DOXYGEN_SHOULD_SKIP_THIS */ +int main(void); +/** \endcond */ + +void __libc_init_array(void); + +/* Default empty handler */ +void Dummy_Handler(void); + +/* Cortex-M4 core handlers */ +void NonMaskableInt_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void HardFault_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void MemManagement_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void BusFault_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void UsageFault_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void SVCall_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void DebugMonitor_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void PendSV_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void SysTick_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); + +/* Peripherals handlers */ +void PM_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void MCLK_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void OSCCTRL_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ +void OSCCTRL_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ +void OSCCTRL_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, + OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, + OSCCTRL_DFLLRDY */ +void OSCCTRL_3_Handler(void) __attribute__(( + weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ +void OSCCTRL_4_Handler(void) __attribute__(( + weak, alias("Dummy_Handler"))); /* OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ +void OSC32KCTRL_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void SUPC_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, + SUPC_BOD33RDY, SUPC_VCORERDY, SUPC_VREGRDY + */ +void SUPC_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SUPC_BOD12DET, SUPC_BOD33DET */ +void WDT_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void RTC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void EIC_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_0 */ +void EIC_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_1 */ +void EIC_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_2 */ +void EIC_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_3 */ +void EIC_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_4 */ +void EIC_5_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_5 */ +void EIC_6_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_6 */ +void EIC_7_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_7 */ +void EIC_8_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_8 */ +void EIC_9_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_9 */ +void EIC_10_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_10 */ +void EIC_11_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_11 */ +void EIC_12_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_12 */ +void EIC_13_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_13 */ +void EIC_14_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_14 */ +void EIC_15_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EIC_EXTINT_15 */ +void FREQM_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void NVMCTRL_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, + NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, + NVMCTRL_6, NVMCTRL_7 */ +void NVMCTRL_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ +void DMAC_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ +void DMAC_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ +void DMAC_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ +void DMAC_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ +void DMAC_4_Handler(void) + __attribute__((weak, + alias("Dummy_Handler"))); /* DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, DMAC_SUSP_14, + DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, DMAC_SUSP_18, DMAC_SUSP_19, + DMAC_SUSP_20, DMAC_SUSP_21, DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, + DMAC_SUSP_25, DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, + DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, DMAC_SUSP_6, + DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, DMAC_TCMPL_10, DMAC_TCMPL_11, + DMAC_TCMPL_12, DMAC_TCMPL_13, DMAC_TCMPL_14, DMAC_TCMPL_15, + DMAC_TCMPL_16, DMAC_TCMPL_17, DMAC_TCMPL_18, DMAC_TCMPL_19, + DMAC_TCMPL_20, DMAC_TCMPL_21, DMAC_TCMPL_22, DMAC_TCMPL_23, + DMAC_TCMPL_24, DMAC_TCMPL_25, DMAC_TCMPL_26, DMAC_TCMPL_27, + DMAC_TCMPL_28, DMAC_TCMPL_29, DMAC_TCMPL_30, DMAC_TCMPL_31, + DMAC_TCMPL_4, DMAC_TCMPL_5, DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, + DMAC_TCMPL_9, DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, + DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, DMAC_TERR_18, + DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, DMAC_TERR_22, DMAC_TERR_23, + DMAC_TERR_24, DMAC_TERR_25, DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, + DMAC_TERR_29, DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, + DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ +void EVSYS_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_0, EVSYS_OVR_0 */ +void EVSYS_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_1, EVSYS_OVR_1 */ +void EVSYS_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_2, EVSYS_OVR_2 */ +void EVSYS_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_3, EVSYS_OVR_3 */ +void EVSYS_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, + EVSYS_EVD_5, EVSYS_EVD_6, EVSYS_EVD_7, + EVSYS_EVD_8, EVSYS_EVD_9, EVSYS_OVR_10, + EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, + EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, + EVSYS_OVR_9 */ +void PAC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void RAMECC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void SERCOM0_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM0_0 */ +void SERCOM0_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM0_1 */ +void SERCOM0_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM0_2 */ +void SERCOM0_3_Handler(void) + __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ +void SERCOM1_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM1_0 */ +void SERCOM1_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM1_1 */ +void SERCOM1_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM1_2 */ +void SERCOM1_3_Handler(void) + __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ +void SERCOM2_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM2_0 */ +void SERCOM2_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM2_1 */ +void SERCOM2_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM2_2 */ +void SERCOM2_3_Handler(void) + __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ +void SERCOM3_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM3_0 */ +void SERCOM3_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM3_1 */ +void SERCOM3_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM3_2 */ +void SERCOM3_3_Handler(void) + __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ +#ifdef ID_SERCOM4 +void SERCOM4_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM4_0 */ +void SERCOM4_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM4_1 */ +void SERCOM4_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM4_2 */ +void SERCOM4_3_Handler(void) + __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ +#endif +#ifdef ID_SERCOM5 +void SERCOM5_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM5_0 */ +void SERCOM5_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM5_1 */ +void SERCOM5_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM5_2 */ +void SERCOM5_3_Handler(void) + __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ +#endif +#ifdef ID_SERCOM6 +void SERCOM6_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM6_0 */ +void SERCOM6_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM6_1 */ +void SERCOM6_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM6_2 */ +void SERCOM6_3_Handler(void) + __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */ +#endif +#ifdef ID_SERCOM7 +void SERCOM7_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM7_0 */ +void SERCOM7_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM7_1 */ +void SERCOM7_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM7_2 */ +void SERCOM7_3_Handler(void) + __attribute__((weak, alias("Dummy_Handler"))); /* SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */ +#endif +#ifdef ID_CAN0 +void CAN0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_CAN1 +void CAN1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_USB +void USB_0_Handler(void) + __attribute__((weak, + alias("Dummy_Handler"))); /* USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, + USB_MSOF, USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, + USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, USB_RXSTP_TXSTP_4, + USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, + USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, + USB_STALL0_STALL_3, USB_STALL0_STALL_4, USB_STALL0_STALL_5, + USB_STALL0_STALL_6, USB_STALL0_STALL_7, USB_STALL1_0, USB_STALL1_1, + USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, USB_STALL1_6, + USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, + USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, + USB_TRFAIL0_TRFAIL_5, USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, + USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, USB_TRFAIL1_PERR_2, + USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, + USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ +void USB_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* USB_SOF_HSOF */ +void USB_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, + USB_TRCPT0_3, USB_TRCPT0_4, USB_TRCPT0_5, + USB_TRCPT0_6, USB_TRCPT0_7 */ +void USB_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, + USB_TRCPT1_3, USB_TRCPT1_4, USB_TRCPT1_5, + USB_TRCPT1_6, USB_TRCPT1_7 */ +#endif +#ifdef ID_GMAC +void GMAC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +void TCC0_0_Handler(void) + __attribute__((weak, + alias("Dummy_Handler"))); /* TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, + TCC0_FAULTA_A, TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ +void TCC0_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_0 */ +void TCC0_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_1 */ +void TCC0_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_2 */ +void TCC0_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_3 */ +void TCC0_5_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_4 */ +void TCC0_6_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC0_MC_5 */ +void TCC1_0_Handler(void) + __attribute__((weak, + alias("Dummy_Handler"))); /* TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, + TCC1_FAULTA_A, TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ +void TCC1_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC1_MC_0 */ +void TCC1_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC1_MC_1 */ +void TCC1_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC1_MC_2 */ +void TCC1_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC1_MC_3 */ +void TCC2_0_Handler(void) + __attribute__((weak, + alias("Dummy_Handler"))); /* TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, + TCC2_FAULTA_A, TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ +void TCC2_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC2_MC_0 */ +void TCC2_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC2_MC_1 */ +void TCC2_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC2_MC_2 */ +#ifdef ID_TCC3 +void TCC3_0_Handler(void) + __attribute__((weak, + alias("Dummy_Handler"))); /* TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, + TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ +void TCC3_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC3_MC_0 */ +void TCC3_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC3_MC_1 */ +#endif +#ifdef ID_TCC4 +void TCC4_0_Handler(void) + __attribute__((weak, + alias("Dummy_Handler"))); /* TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, + TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ +void TCC4_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC4_MC_0 */ +void TCC4_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* TCC4_MC_1 */ +#endif +void TC0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TC1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TC2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TC3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#ifdef ID_TC4 +void TC4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_TC5 +void TC5_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_TC6 +void TC6_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_TC7 +void TC7_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +void PDEC_0_Handler(void) + __attribute__((weak, alias("Dummy_Handler"))); /* PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ +void PDEC_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* PDEC_MC_0 */ +void PDEC_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* PDEC_MC_1 */ +void ADC0_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* ADC0_OVERRUN, ADC0_WINMON */ +void ADC0_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* ADC0_RESRDY */ +void ADC1_0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* ADC1_OVERRUN, ADC1_WINMON */ +void ADC1_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* ADC1_RESRDY */ +void AC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void DAC_0_Handler(void) + __attribute__((weak, + alias("Dummy_Handler"))); /* DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ +void DAC_1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_0 */ +void DAC_2_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DAC_EMPTY_1 */ +void DAC_3_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_0 */ +void DAC_4_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); /* DAC_RESRDY_1 */ +#ifdef ID_I2S +void I2S_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +void PCC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void AES_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +void TRNG_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#ifdef ID_ICM +void ICM_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_PUKCC +void PUKCC_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +void QSPI_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#ifdef ID_SDHC0 +void SDHC0_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif +#ifdef ID_SDHC1 +void SDHC1_Handler(void) __attribute__((weak, alias("Dummy_Handler"))); +#endif + +/* Exception Table */ +__attribute__((section(".vectors"))) const DeviceVectors exception_table + = { + + /* Configure Initial Stack Pointer, using linker-generated symbols */ + .pvStack = (void *)(&_estack), + + .pfnReset_Handler = (void *)Reset_Handler, + .pfnNonMaskableInt_Handler = (void *)NonMaskableInt_Handler, + .pfnHardFault_Handler = (void *)HardFault_Handler, + .pfnMemManagement_Handler = (void *)MemManagement_Handler, + .pfnBusFault_Handler = (void *)BusFault_Handler, + .pfnUsageFault_Handler = (void *)UsageFault_Handler, + .pvReservedM9 = (void *)(0UL), /* Reserved */ + .pvReservedM8 = (void *)(0UL), /* Reserved */ + .pvReservedM7 = (void *)(0UL), /* Reserved */ + .pvReservedM6 = (void *)(0UL), /* Reserved */ + .pfnSVCall_Handler = (void *)SVCall_Handler, + .pfnDebugMonitor_Handler = (void *)DebugMonitor_Handler, + .pvReservedM3 = (void *)(0UL), /* Reserved */ + .pfnPendSV_Handler = (void *)PendSV_Handler, + .pfnSysTick_Handler = (void *)SysTick_Handler, + + /* Configurable interrupts */ + .pfnPM_Handler = (void *)PM_Handler, /* 0 Power Manager */ + .pfnMCLK_Handler = (void *)MCLK_Handler, /* 1 Main Clock */ + .pfnOSCCTRL_0_Handler = (void *)OSCCTRL_0_Handler, /* 2 OSCCTRL_XOSCFAIL_0, OSCCTRL_XOSCRDY_0 */ + .pfnOSCCTRL_1_Handler = (void *)OSCCTRL_1_Handler, /* 3 OSCCTRL_XOSCFAIL_1, OSCCTRL_XOSCRDY_1 */ + .pfnOSCCTRL_2_Handler + = (void *)OSCCTRL_2_Handler, /* 4 OSCCTRL_DFLLLOCKC, OSCCTRL_DFLLLOCKF, OSCCTRL_DFLLOOB, OSCCTRL_DFLLRCS, + OSCCTRL_DFLLRDY */ + .pfnOSCCTRL_3_Handler = (void *) + OSCCTRL_3_Handler, /* 5 OSCCTRL_DPLLLCKF_0, OSCCTRL_DPLLLCKR_0, OSCCTRL_DPLLLDRTO_0, OSCCTRL_DPLLLTO_0 */ + .pfnOSCCTRL_4_Handler = (void *) + OSCCTRL_4_Handler, /* 6 OSCCTRL_DPLLLCKF_1, OSCCTRL_DPLLLCKR_1, OSCCTRL_DPLLLDRTO_1, OSCCTRL_DPLLLTO_1 */ + .pfnOSC32KCTRL_Handler = (void *)OSC32KCTRL_Handler, /* 7 32kHz Oscillators Control */ + .pfnSUPC_0_Handler = (void *)SUPC_0_Handler, /* 8 SUPC_B12SRDY, SUPC_B33SRDY, SUPC_BOD12RDY, SUPC_BOD33RDY, + SUPC_VCORERDY, SUPC_VREGRDY */ + .pfnSUPC_1_Handler = (void *)SUPC_1_Handler, /* 9 SUPC_BOD12DET, SUPC_BOD33DET */ + .pfnWDT_Handler = (void *)WDT_Handler, /* 10 Watchdog Timer */ + .pfnRTC_Handler = (void *)RTC_Handler, /* 11 Real-Time Counter */ + .pfnEIC_0_Handler = (void *)EIC_0_Handler, /* 12 EIC_EXTINT_0 */ + .pfnEIC_1_Handler = (void *)EIC_1_Handler, /* 13 EIC_EXTINT_1 */ + .pfnEIC_2_Handler = (void *)EIC_2_Handler, /* 14 EIC_EXTINT_2 */ + .pfnEIC_3_Handler = (void *)EIC_3_Handler, /* 15 EIC_EXTINT_3 */ + .pfnEIC_4_Handler = (void *)EIC_4_Handler, /* 16 EIC_EXTINT_4 */ + .pfnEIC_5_Handler = (void *)EIC_5_Handler, /* 17 EIC_EXTINT_5 */ + .pfnEIC_6_Handler = (void *)EIC_6_Handler, /* 18 EIC_EXTINT_6 */ + .pfnEIC_7_Handler = (void *)EIC_7_Handler, /* 19 EIC_EXTINT_7 */ + .pfnEIC_8_Handler = (void *)EIC_8_Handler, /* 20 EIC_EXTINT_8 */ + .pfnEIC_9_Handler = (void *)EIC_9_Handler, /* 21 EIC_EXTINT_9 */ + .pfnEIC_10_Handler = (void *)EIC_10_Handler, /* 22 EIC_EXTINT_10 */ + .pfnEIC_11_Handler = (void *)EIC_11_Handler, /* 23 EIC_EXTINT_11 */ + .pfnEIC_12_Handler = (void *)EIC_12_Handler, /* 24 EIC_EXTINT_12 */ + .pfnEIC_13_Handler = (void *)EIC_13_Handler, /* 25 EIC_EXTINT_13 */ + .pfnEIC_14_Handler = (void *)EIC_14_Handler, /* 26 EIC_EXTINT_14 */ + .pfnEIC_15_Handler = (void *)EIC_15_Handler, /* 27 EIC_EXTINT_15 */ + .pfnFREQM_Handler = (void *)FREQM_Handler, /* 28 Frequency Meter */ + .pfnNVMCTRL_0_Handler = (void *) + NVMCTRL_0_Handler, /* 29 NVMCTRL_0, NVMCTRL_1, NVMCTRL_2, NVMCTRL_3, NVMCTRL_4, NVMCTRL_5, NVMCTRL_6, + NVMCTRL_7 */ + .pfnNVMCTRL_1_Handler = (void *)NVMCTRL_1_Handler, /* 30 NVMCTRL_10, NVMCTRL_8, NVMCTRL_9 */ + .pfnDMAC_0_Handler = (void *)DMAC_0_Handler, /* 31 DMAC_SUSP_0, DMAC_TCMPL_0, DMAC_TERR_0 */ + .pfnDMAC_1_Handler = (void *)DMAC_1_Handler, /* 32 DMAC_SUSP_1, DMAC_TCMPL_1, DMAC_TERR_1 */ + .pfnDMAC_2_Handler = (void *)DMAC_2_Handler, /* 33 DMAC_SUSP_2, DMAC_TCMPL_2, DMAC_TERR_2 */ + .pfnDMAC_3_Handler = (void *)DMAC_3_Handler, /* 34 DMAC_SUSP_3, DMAC_TCMPL_3, DMAC_TERR_3 */ + .pfnDMAC_4_Handler = (void *)DMAC_4_Handler, /* 35 DMAC_SUSP_10, DMAC_SUSP_11, DMAC_SUSP_12, DMAC_SUSP_13, + DMAC_SUSP_14, DMAC_SUSP_15, DMAC_SUSP_16, DMAC_SUSP_17, + DMAC_SUSP_18, DMAC_SUSP_19, DMAC_SUSP_20, DMAC_SUSP_21, + DMAC_SUSP_22, DMAC_SUSP_23, DMAC_SUSP_24, DMAC_SUSP_25, + DMAC_SUSP_26, DMAC_SUSP_27, DMAC_SUSP_28, DMAC_SUSP_29, + DMAC_SUSP_30, DMAC_SUSP_31, DMAC_SUSP_4, DMAC_SUSP_5, + DMAC_SUSP_6, DMAC_SUSP_7, DMAC_SUSP_8, DMAC_SUSP_9, + DMAC_TCMPL_10, DMAC_TCMPL_11, DMAC_TCMPL_12, DMAC_TCMPL_13, + DMAC_TCMPL_14, DMAC_TCMPL_15, DMAC_TCMPL_16, DMAC_TCMPL_17, + DMAC_TCMPL_18, DMAC_TCMPL_19, DMAC_TCMPL_20, DMAC_TCMPL_21, + DMAC_TCMPL_22, DMAC_TCMPL_23, DMAC_TCMPL_24, DMAC_TCMPL_25, + DMAC_TCMPL_26, DMAC_TCMPL_27, DMAC_TCMPL_28, DMAC_TCMPL_29, + DMAC_TCMPL_30, DMAC_TCMPL_31, DMAC_TCMPL_4, DMAC_TCMPL_5, + DMAC_TCMPL_6, DMAC_TCMPL_7, DMAC_TCMPL_8, DMAC_TCMPL_9, + DMAC_TERR_10, DMAC_TERR_11, DMAC_TERR_12, DMAC_TERR_13, + DMAC_TERR_14, DMAC_TERR_15, DMAC_TERR_16, DMAC_TERR_17, + DMAC_TERR_18, DMAC_TERR_19, DMAC_TERR_20, DMAC_TERR_21, + DMAC_TERR_22, DMAC_TERR_23, DMAC_TERR_24, DMAC_TERR_25, + DMAC_TERR_26, DMAC_TERR_27, DMAC_TERR_28, DMAC_TERR_29, + DMAC_TERR_30, DMAC_TERR_31, DMAC_TERR_4, DMAC_TERR_5, + DMAC_TERR_6, DMAC_TERR_7, DMAC_TERR_8, DMAC_TERR_9 */ + .pfnEVSYS_0_Handler = (void *)EVSYS_0_Handler, /* 36 EVSYS_EVD_0, EVSYS_OVR_0 */ + .pfnEVSYS_1_Handler = (void *)EVSYS_1_Handler, /* 37 EVSYS_EVD_1, EVSYS_OVR_1 */ + .pfnEVSYS_2_Handler = (void *)EVSYS_2_Handler, /* 38 EVSYS_EVD_2, EVSYS_OVR_2 */ + .pfnEVSYS_3_Handler = (void *)EVSYS_3_Handler, /* 39 EVSYS_EVD_3, EVSYS_OVR_3 */ + .pfnEVSYS_4_Handler = (void *)EVSYS_4_Handler, /* 40 EVSYS_EVD_10, EVSYS_EVD_11, EVSYS_EVD_4, EVSYS_EVD_5, + EVSYS_EVD_6, EVSYS_EVD_7, EVSYS_EVD_8, EVSYS_EVD_9, + EVSYS_OVR_10, EVSYS_OVR_11, EVSYS_OVR_4, EVSYS_OVR_5, + EVSYS_OVR_6, EVSYS_OVR_7, EVSYS_OVR_8, EVSYS_OVR_9 */ + .pfnPAC_Handler = (void *)PAC_Handler, /* 41 Peripheral Access Controller */ + .pvReserved42 = (void *)(0UL), /* 42 Reserved */ + .pvReserved43 = (void *)(0UL), /* 43 Reserved */ + .pvReserved44 = (void *)(0UL), /* 44 Reserved */ + .pfnRAMECC_Handler = (void *)RAMECC_Handler, /* 45 RAM ECC */ + .pfnSERCOM0_0_Handler = (void *)SERCOM0_0_Handler, /* 46 SERCOM0_0 */ + .pfnSERCOM0_1_Handler = (void *)SERCOM0_1_Handler, /* 47 SERCOM0_1 */ + .pfnSERCOM0_2_Handler = (void *)SERCOM0_2_Handler, /* 48 SERCOM0_2 */ + .pfnSERCOM0_3_Handler = (void *)SERCOM0_3_Handler, /* 49 SERCOM0_3, SERCOM0_4, SERCOM0_5, SERCOM0_6 */ + .pfnSERCOM1_0_Handler = (void *)SERCOM1_0_Handler, /* 50 SERCOM1_0 */ + .pfnSERCOM1_1_Handler = (void *)SERCOM1_1_Handler, /* 51 SERCOM1_1 */ + .pfnSERCOM1_2_Handler = (void *)SERCOM1_2_Handler, /* 52 SERCOM1_2 */ + .pfnSERCOM1_3_Handler = (void *)SERCOM1_3_Handler, /* 53 SERCOM1_3, SERCOM1_4, SERCOM1_5, SERCOM1_6 */ + .pfnSERCOM2_0_Handler = (void *)SERCOM2_0_Handler, /* 54 SERCOM2_0 */ + .pfnSERCOM2_1_Handler = (void *)SERCOM2_1_Handler, /* 55 SERCOM2_1 */ + .pfnSERCOM2_2_Handler = (void *)SERCOM2_2_Handler, /* 56 SERCOM2_2 */ + .pfnSERCOM2_3_Handler = (void *)SERCOM2_3_Handler, /* 57 SERCOM2_3, SERCOM2_4, SERCOM2_5, SERCOM2_6 */ + .pfnSERCOM3_0_Handler = (void *)SERCOM3_0_Handler, /* 58 SERCOM3_0 */ + .pfnSERCOM3_1_Handler = (void *)SERCOM3_1_Handler, /* 59 SERCOM3_1 */ + .pfnSERCOM3_2_Handler = (void *)SERCOM3_2_Handler, /* 60 SERCOM3_2 */ + .pfnSERCOM3_3_Handler = (void *)SERCOM3_3_Handler, /* 61 SERCOM3_3, SERCOM3_4, SERCOM3_5, SERCOM3_6 */ +#ifdef ID_SERCOM4 + .pfnSERCOM4_0_Handler = (void *)SERCOM4_0_Handler, /* 62 SERCOM4_0 */ + .pfnSERCOM4_1_Handler = (void *)SERCOM4_1_Handler, /* 63 SERCOM4_1 */ + .pfnSERCOM4_2_Handler = (void *)SERCOM4_2_Handler, /* 64 SERCOM4_2 */ + .pfnSERCOM4_3_Handler = (void *)SERCOM4_3_Handler, /* 65 SERCOM4_3, SERCOM4_4, SERCOM4_5, SERCOM4_6 */ +#else + .pvReserved62 = (void *)(0UL), /* 62 Reserved */ + .pvReserved63 = (void *)(0UL), /* 63 Reserved */ + .pvReserved64 = (void *)(0UL), /* 64 Reserved */ + .pvReserved65 = (void *)(0UL), /* 65 Reserved */ +#endif +#ifdef ID_SERCOM5 + .pfnSERCOM5_0_Handler = (void *)SERCOM5_0_Handler, /* 66 SERCOM5_0 */ + .pfnSERCOM5_1_Handler = (void *)SERCOM5_1_Handler, /* 67 SERCOM5_1 */ + .pfnSERCOM5_2_Handler = (void *)SERCOM5_2_Handler, /* 68 SERCOM5_2 */ + .pfnSERCOM5_3_Handler = (void *)SERCOM5_3_Handler, /* 69 SERCOM5_3, SERCOM5_4, SERCOM5_5, SERCOM5_6 */ +#else + .pvReserved66 = (void *)(0UL), /* 66 Reserved */ + .pvReserved67 = (void *)(0UL), /* 67 Reserved */ + .pvReserved68 = (void *)(0UL), /* 68 Reserved */ + .pvReserved69 = (void *)(0UL), /* 69 Reserved */ +#endif +#ifdef ID_SERCOM6 + .pfnSERCOM6_0_Handler = (void *)SERCOM6_0_Handler, /* 70 SERCOM6_0 */ + .pfnSERCOM6_1_Handler = (void *)SERCOM6_1_Handler, /* 71 SERCOM6_1 */ + .pfnSERCOM6_2_Handler = (void *)SERCOM6_2_Handler, /* 72 SERCOM6_2 */ + .pfnSERCOM6_3_Handler = (void *)SERCOM6_3_Handler, /* 73 SERCOM6_3, SERCOM6_4, SERCOM6_5, SERCOM6_6 */ +#else + .pvReserved70 = (void *)(0UL), /* 70 Reserved */ + .pvReserved71 = (void *)(0UL), /* 71 Reserved */ + .pvReserved72 = (void *)(0UL), /* 72 Reserved */ + .pvReserved73 = (void *)(0UL), /* 73 Reserved */ +#endif +#ifdef ID_SERCOM7 + .pfnSERCOM7_0_Handler = (void *)SERCOM7_0_Handler, /* 74 SERCOM7_0 */ + .pfnSERCOM7_1_Handler = (void *)SERCOM7_1_Handler, /* 75 SERCOM7_1 */ + .pfnSERCOM7_2_Handler = (void *)SERCOM7_2_Handler, /* 76 SERCOM7_2 */ + .pfnSERCOM7_3_Handler = (void *)SERCOM7_3_Handler, /* 77 SERCOM7_3, SERCOM7_4, SERCOM7_5, SERCOM7_6 */ +#else + .pvReserved74 = (void *)(0UL), /* 74 Reserved */ + .pvReserved75 = (void *)(0UL), /* 75 Reserved */ + .pvReserved76 = (void *)(0UL), /* 76 Reserved */ + .pvReserved77 = (void *)(0UL), /* 77 Reserved */ +#endif +#ifdef ID_CAN0 + .pfnCAN0_Handler = (void *)CAN0_Handler, /* 78 Control Area Network 0 */ +#else + .pvReserved78 = (void *)(0UL), /* 78 Reserved */ +#endif +#ifdef ID_CAN1 + .pfnCAN1_Handler = (void *)CAN1_Handler, /* 79 Control Area Network 1 */ +#else + .pvReserved79 = (void *)(0UL), /* 79 Reserved */ +#endif +#ifdef ID_USB + .pfnUSB_0_Handler = (void *) + USB_0_Handler, /* 80 USB_EORSM_DNRSM, USB_EORST_RST, USB_LPMSUSP_DDISC, USB_LPM_DCONN, USB_MSOF, + USB_RAMACER, USB_RXSTP_TXSTP_0, USB_RXSTP_TXSTP_1, USB_RXSTP_TXSTP_2, USB_RXSTP_TXSTP_3, + USB_RXSTP_TXSTP_4, USB_RXSTP_TXSTP_5, USB_RXSTP_TXSTP_6, USB_RXSTP_TXSTP_7, + USB_STALL0_STALL_0, USB_STALL0_STALL_1, USB_STALL0_STALL_2, USB_STALL0_STALL_3, + USB_STALL0_STALL_4, USB_STALL0_STALL_5, USB_STALL0_STALL_6, USB_STALL0_STALL_7, + USB_STALL1_0, USB_STALL1_1, USB_STALL1_2, USB_STALL1_3, USB_STALL1_4, USB_STALL1_5, + USB_STALL1_6, USB_STALL1_7, USB_SUSPEND, USB_TRFAIL0_TRFAIL_0, USB_TRFAIL0_TRFAIL_1, + USB_TRFAIL0_TRFAIL_2, USB_TRFAIL0_TRFAIL_3, USB_TRFAIL0_TRFAIL_4, USB_TRFAIL0_TRFAIL_5, + USB_TRFAIL0_TRFAIL_6, USB_TRFAIL0_TRFAIL_7, USB_TRFAIL1_PERR_0, USB_TRFAIL1_PERR_1, + USB_TRFAIL1_PERR_2, USB_TRFAIL1_PERR_3, USB_TRFAIL1_PERR_4, USB_TRFAIL1_PERR_5, + USB_TRFAIL1_PERR_6, USB_TRFAIL1_PERR_7, USB_UPRSM, USB_WAKEUP */ + .pfnUSB_1_Handler = (void *)USB_1_Handler, /* 81 USB_SOF_HSOF */ + .pfnUSB_2_Handler = (void *)USB_2_Handler, /* 82 USB_TRCPT0_0, USB_TRCPT0_1, USB_TRCPT0_2, USB_TRCPT0_3, + USB_TRCPT0_4, USB_TRCPT0_5, USB_TRCPT0_6, USB_TRCPT0_7 */ + .pfnUSB_3_Handler = (void *)USB_3_Handler, /* 83 USB_TRCPT1_0, USB_TRCPT1_1, USB_TRCPT1_2, USB_TRCPT1_3, + USB_TRCPT1_4, USB_TRCPT1_5, USB_TRCPT1_6, USB_TRCPT1_7 */ +#else + .pvReserved80 = (void *)(0UL), /* 80 Reserved */ + .pvReserved81 = (void *)(0UL), /* 81 Reserved */ + .pvReserved82 = (void *)(0UL), /* 82 Reserved */ + .pvReserved83 = (void *)(0UL), /* 83 Reserved */ +#endif +#ifdef ID_GMAC + .pfnGMAC_Handler = (void *)GMAC_Handler, /* 84 Ethernet MAC */ +#else + .pvReserved84 = (void *)(0UL), /* 84 Reserved */ +#endif + .pfnTCC0_0_Handler = (void *) + TCC0_0_Handler, /* 85 TCC0_CNT_A, TCC0_DFS_A, TCC0_ERR_A, TCC0_FAULT0_A, TCC0_FAULT1_A, TCC0_FAULTA_A, + TCC0_FAULTB_A, TCC0_OVF, TCC0_TRG, TCC0_UFS_A */ + .pfnTCC0_1_Handler = (void *)TCC0_1_Handler, /* 86 TCC0_MC_0 */ + .pfnTCC0_2_Handler = (void *)TCC0_2_Handler, /* 87 TCC0_MC_1 */ + .pfnTCC0_3_Handler = (void *)TCC0_3_Handler, /* 88 TCC0_MC_2 */ + .pfnTCC0_4_Handler = (void *)TCC0_4_Handler, /* 89 TCC0_MC_3 */ + .pfnTCC0_5_Handler = (void *)TCC0_5_Handler, /* 90 TCC0_MC_4 */ + .pfnTCC0_6_Handler = (void *)TCC0_6_Handler, /* 91 TCC0_MC_5 */ + .pfnTCC1_0_Handler = (void *) + TCC1_0_Handler, /* 92 TCC1_CNT_A, TCC1_DFS_A, TCC1_ERR_A, TCC1_FAULT0_A, TCC1_FAULT1_A, TCC1_FAULTA_A, + TCC1_FAULTB_A, TCC1_OVF, TCC1_TRG, TCC1_UFS_A */ + .pfnTCC1_1_Handler = (void *)TCC1_1_Handler, /* 93 TCC1_MC_0 */ + .pfnTCC1_2_Handler = (void *)TCC1_2_Handler, /* 94 TCC1_MC_1 */ + .pfnTCC1_3_Handler = (void *)TCC1_3_Handler, /* 95 TCC1_MC_2 */ + .pfnTCC1_4_Handler = (void *)TCC1_4_Handler, /* 96 TCC1_MC_3 */ + .pfnTCC2_0_Handler = (void *) + TCC2_0_Handler, /* 97 TCC2_CNT_A, TCC2_DFS_A, TCC2_ERR_A, TCC2_FAULT0_A, TCC2_FAULT1_A, TCC2_FAULTA_A, + TCC2_FAULTB_A, TCC2_OVF, TCC2_TRG, TCC2_UFS_A */ + .pfnTCC2_1_Handler = (void *)TCC2_1_Handler, /* 98 TCC2_MC_0 */ + .pfnTCC2_2_Handler = (void *)TCC2_2_Handler, /* 99 TCC2_MC_1 */ + .pfnTCC2_3_Handler = (void *)TCC2_3_Handler, /* 100 TCC2_MC_2 */ +#ifdef ID_TCC3 + .pfnTCC3_0_Handler + = (void *)TCC3_0_Handler, /* 101 TCC3_CNT_A, TCC3_DFS_A, TCC3_ERR_A, TCC3_FAULT0_A, TCC3_FAULT1_A, + TCC3_FAULTA_A, TCC3_FAULTB_A, TCC3_OVF, TCC3_TRG, TCC3_UFS_A */ + .pfnTCC3_1_Handler = (void *)TCC3_1_Handler, /* 102 TCC3_MC_0 */ + .pfnTCC3_2_Handler = (void *)TCC3_2_Handler, /* 103 TCC3_MC_1 */ +#else + .pvReserved101 = (void *)(0UL), /* 101 Reserved */ + .pvReserved102 = (void *)(0UL), /* 102 Reserved */ + .pvReserved103 = (void *)(0UL), /* 103 Reserved */ +#endif +#ifdef ID_TCC4 + .pfnTCC4_0_Handler + = (void *)TCC4_0_Handler, /* 104 TCC4_CNT_A, TCC4_DFS_A, TCC4_ERR_A, TCC4_FAULT0_A, TCC4_FAULT1_A, + TCC4_FAULTA_A, TCC4_FAULTB_A, TCC4_OVF, TCC4_TRG, TCC4_UFS_A */ + .pfnTCC4_1_Handler = (void *)TCC4_1_Handler, /* 105 TCC4_MC_0 */ + .pfnTCC4_2_Handler = (void *)TCC4_2_Handler, /* 106 TCC4_MC_1 */ +#else + .pvReserved104 = (void *)(0UL), /* 104 Reserved */ + .pvReserved105 = (void *)(0UL), /* 105 Reserved */ + .pvReserved106 = (void *)(0UL), /* 106 Reserved */ +#endif + .pfnTC0_Handler = (void *)TC0_Handler, /* 107 Basic Timer Counter 0 */ + .pfnTC1_Handler = (void *)TC1_Handler, /* 108 Basic Timer Counter 1 */ + .pfnTC2_Handler = (void *)TC2_Handler, /* 109 Basic Timer Counter 2 */ + .pfnTC3_Handler = (void *)TC3_Handler, /* 110 Basic Timer Counter 3 */ +#ifdef ID_TC4 + .pfnTC4_Handler = (void *)TC4_Handler, /* 111 Basic Timer Counter 4 */ +#else + .pvReserved111 = (void *)(0UL), /* 111 Reserved */ +#endif +#ifdef ID_TC5 + .pfnTC5_Handler = (void *)TC5_Handler, /* 112 Basic Timer Counter 5 */ +#else + .pvReserved112 = (void *)(0UL), /* 112 Reserved */ +#endif +#ifdef ID_TC6 + .pfnTC6_Handler = (void *)TC6_Handler, /* 113 Basic Timer Counter 6 */ +#else + .pvReserved113 = (void *)(0UL), /* 113 Reserved */ +#endif +#ifdef ID_TC7 + .pfnTC7_Handler = (void *)TC7_Handler, /* 114 Basic Timer Counter 7 */ +#else + .pvReserved114 = (void *)(0UL), /* 114 Reserved */ +#endif + .pfnPDEC_0_Handler = (void *)PDEC_0_Handler, /* 115 PDEC_DIR_A, PDEC_ERR_A, PDEC_OVF, PDEC_VLC_A */ + .pfnPDEC_1_Handler = (void *)PDEC_1_Handler, /* 116 PDEC_MC_0 */ + .pfnPDEC_2_Handler = (void *)PDEC_2_Handler, /* 117 PDEC_MC_1 */ + .pfnADC0_0_Handler = (void *)ADC0_0_Handler, /* 118 ADC0_OVERRUN, ADC0_WINMON */ + .pfnADC0_1_Handler = (void *)ADC0_1_Handler, /* 119 ADC0_RESRDY */ + .pfnADC1_0_Handler = (void *)ADC1_0_Handler, /* 120 ADC1_OVERRUN, ADC1_WINMON */ + .pfnADC1_1_Handler = (void *)ADC1_1_Handler, /* 121 ADC1_RESRDY */ + .pfnAC_Handler = (void *)AC_Handler, /* 122 Analog Comparators */ + .pfnDAC_0_Handler + = (void *)DAC_0_Handler, /* 123 DAC_OVERRUN_A_0, DAC_OVERRUN_A_1, DAC_UNDERRUN_A_0, DAC_UNDERRUN_A_1 */ + .pfnDAC_1_Handler = (void *)DAC_1_Handler, /* 124 DAC_EMPTY_0 */ + .pfnDAC_2_Handler = (void *)DAC_2_Handler, /* 125 DAC_EMPTY_1 */ + .pfnDAC_3_Handler = (void *)DAC_3_Handler, /* 126 DAC_RESRDY_0 */ + .pfnDAC_4_Handler = (void *)DAC_4_Handler, /* 127 DAC_RESRDY_1 */ +#ifdef ID_I2S + .pfnI2S_Handler = (void *)I2S_Handler, /* 128 Inter-IC Sound Interface */ +#else + .pvReserved128 = (void *)(0UL), /* 128 Reserved */ +#endif + .pfnPCC_Handler = (void *)PCC_Handler, /* 129 Parallel Capture Controller */ + .pfnAES_Handler = (void *)AES_Handler, /* 130 Advanced Encryption Standard */ + .pfnTRNG_Handler = (void *)TRNG_Handler, /* 131 True Random Generator */ +#ifdef ID_ICM + .pfnICM_Handler = (void *)ICM_Handler, /* 132 Integrity Check Monitor */ +#else + .pvReserved132 = (void *)(0UL), /* 132 Reserved */ +#endif +#ifdef ID_PUKCC + .pfnPUKCC_Handler = (void *)PUKCC_Handler, /* 133 PUblic-Key Cryptography Controller */ +#else + .pvReserved133 = (void *)(0UL), /* 133 Reserved */ +#endif + .pfnQSPI_Handler = (void *)QSPI_Handler, /* 134 Quad SPI interface */ +#ifdef ID_SDHC0 + .pfnSDHC0_Handler = (void *)SDHC0_Handler, /* 135 SD/MMC Host Controller 0 */ +#else + .pvReserved135 = (void *)(0UL), /* 135 Reserved */ +#endif +#ifdef ID_SDHC1 + .pfnSDHC1_Handler = (void *)SDHC1_Handler /* 136 SD/MMC Host Controller 1 */ +#else + .pvReserved136 = (void *)(0UL) /* 136 Reserved */ +#endif +}; + +/** + * \brief This is the code that gets called on processor reset. + * To initialize the device, and call the main() routine. + */ +void Reset_Handler(void) +{ + uint32_t *pSrc, *pDest; + + /* Initialize the relocate segment */ + pSrc = &_etext; + pDest = &_srelocate; + + if (pSrc != pDest) { + for (; pDest < &_erelocate;) { + *pDest++ = *pSrc++; + } + } + + /* Clear the zero segment */ + for (pDest = &_szero; pDest < &_ezero;) { + *pDest++ = 0; + } + + /* Set the vector table base address */ + pSrc = (uint32_t *)&_sfixed; + SCB->VTOR = ((uint32_t)pSrc & SCB_VTOR_TBLOFF_Msk); + +#if __FPU_USED + /* Enable FPU */ + SCB->CPACR |= (0xFu << 20); + __DSB(); + __ISB(); +#endif + + /* Initialize the C library */ + __libc_init_array(); + + /* Branch to main function */ + main(); + + /* Infinite loop */ + while (1) + ; +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Dummy_Handler(void) +{ + while (1) { + } +} diff --git a/software/firmware/oracle_same54n19a/gcc/gcc/system_same54.d b/software/firmware/oracle_same54n19a/gcc/gcc/system_same54.d new file mode 100644 index 00000000..d43d2158 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/gcc/system_same54.d @@ -0,0 +1,176 @@ +gcc/system_same54.d gcc/system_same54.o: ../gcc/system_same54.c \ + ../include/same54.h ../include/same54n19a.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h +../include/same54.h: +../include/same54n19a.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: diff --git a/software/firmware/oracle_same54n19a/gcc/gcc/system_same54.o b/software/firmware/oracle_same54n19a/gcc/gcc/system_same54.o new file mode 100644 index 00000000..be812805 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/gcc/system_same54.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/hal/src/hal_atomic.d b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_atomic.d new file mode 100644 index 00000000..7c2f9f77 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_atomic.d @@ -0,0 +1,239 @@ +hal/src/hal_atomic.d hal/src/hal_atomic.o: ../hal/src/hal_atomic.c \ + ../hal/include/hal_atomic.h ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hri/hri_adc_e54.h ../hri/hri_aes_e54.h \ + ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h ../hri/hri_cmcc_e54.h \ + ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h ../hri/hri_dsu_e54.h \ + ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h ../hri/hri_freqm_e54.h \ + ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h ../hri/hri_hmatrixb_e54.h \ + ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h ../hri/hri_mclk_e54.h \ + ../hri/hri_nvmctrl_e54.h ../hri/hri_osc32kctrl_e54.h \ + ../hri/hri_oscctrl_e54.h ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h \ + ../hri/hri_pdec_e54.h ../hri/hri_pm_e54.h ../hri/hri_port_e54.h \ + ../hri/hri_qspi_e54.h ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h \ + ../hri/hri_rtc_e54.h ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h \ + ../hri/hri_supc_e54.h ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h \ + ../hri/hri_trng_e54.h ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h +../hal/include/hal_atomic.h: +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: diff --git a/software/firmware/oracle_same54n19a/gcc/hal/src/hal_atomic.o b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_atomic.o new file mode 100644 index 00000000..b38f905c Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_atomic.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/hal/src/hal_cache.d b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_cache.d new file mode 100644 index 00000000..c9c6dbea --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_cache.d @@ -0,0 +1,241 @@ +hal/src/hal_cache.d hal/src/hal_cache.o: ../hal/src/hal_cache.c \ + ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h ../hal/include/hpl_cmcc.h +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hal/include/hal_atomic.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: +../hal/include/hpl_cmcc.h: diff --git a/software/firmware/oracle_same54n19a/gcc/hal/src/hal_cache.o b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_cache.o new file mode 100644 index 00000000..4fec8c9c Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_cache.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/hal/src/hal_delay.d b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_delay.d new file mode 100644 index 00000000..5020f511 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_delay.d @@ -0,0 +1,247 @@ +hal/src/hal_delay.d hal/src/hal_delay.o: ../hal/src/hal_delay.c \ + ../hal/include/hpl_irq.h ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h ../hal/include/hpl_reset.h \ + ../hal/include/hpl_sleep.h ../hal/include/hal_delay.h \ + ../hal/include/hpl_delay.h +../hal/include/hpl_irq.h: +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hal/include/hal_atomic.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: +../hal/include/hpl_reset.h: +../hal/include/hpl_sleep.h: +../hal/include/hal_delay.h: +../hal/include/hpl_delay.h: diff --git a/software/firmware/oracle_same54n19a/gcc/hal/src/hal_delay.o b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_delay.o new file mode 100644 index 00000000..366b946e Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_delay.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/hal/src/hal_ext_irq.d b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_ext_irq.d new file mode 100644 index 00000000..9675c336 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_ext_irq.d @@ -0,0 +1,243 @@ +hal/src/hal_ext_irq.d hal/src/hal_ext_irq.o: ../hal/src/hal_ext_irq.c \ + ../hal/include/hal_ext_irq.h ../hal/include/hpl_ext_irq.h \ + ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h +../hal/include/hal_ext_irq.h: +../hal/include/hpl_ext_irq.h: +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hal/include/hal_atomic.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: diff --git a/software/firmware/oracle_same54n19a/gcc/hal/src/hal_ext_irq.o b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_ext_irq.o new file mode 100644 index 00000000..55a9e4e4 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_ext_irq.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/hal/src/hal_gpio.d b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_gpio.d new file mode 100644 index 00000000..9a3d09c2 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_gpio.d @@ -0,0 +1,247 @@ +hal/src/hal_gpio.d hal/src/hal_gpio.o: ../hal/src/hal_gpio.c \ + ../hal/include/hal_gpio.h ../hal/include/hpl_gpio.h \ + ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h ../hpl/port/hpl_gpio_base.h \ + ../hal/utils/include/utils_assert.h ../config/hpl_port_config.h +../hal/include/hal_gpio.h: +../hal/include/hpl_gpio.h: +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hal/include/hal_atomic.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: +../hpl/port/hpl_gpio_base.h: +../hal/utils/include/utils_assert.h: +../config/hpl_port_config.h: diff --git a/software/firmware/oracle_same54n19a/gcc/hal/src/hal_gpio.o b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_gpio.o new file mode 100644 index 00000000..9f02e83a Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_gpio.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/hal/src/hal_i2c_m_sync.d b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_i2c_m_sync.d new file mode 100644 index 00000000..262c0a7e --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_i2c_m_sync.d @@ -0,0 +1,247 @@ +hal/src/hal_i2c_m_sync.d hal/src/hal_i2c_m_sync.o: \ + ../hal/src/hal_i2c_m_sync.c ../hal/include/hal_i2c_m_sync.h \ + ../hal/include/hpl_i2c_m_sync.h ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h ../hal/include/hal_io.h \ + ../hal/utils/include/utils.h ../hal/utils/include/utils_assert.h +../hal/include/hal_i2c_m_sync.h: +../hal/include/hpl_i2c_m_sync.h: +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hal/include/hal_atomic.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: +../hal/include/hal_io.h: +../hal/utils/include/utils.h: +../hal/utils/include/utils_assert.h: diff --git a/software/firmware/oracle_same54n19a/gcc/hal/src/hal_i2c_m_sync.o b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_i2c_m_sync.o new file mode 100644 index 00000000..1ff6d559 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_i2c_m_sync.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/hal/src/hal_init.d b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_init.d new file mode 100644 index 00000000..2af93a0c --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_init.d @@ -0,0 +1,243 @@ +hal/src/hal_init.d hal/src/hal_init.o: ../hal/src/hal_init.c \ + ../hal/include/hal_init.h ../hal/include/hpl_init.h \ + ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h +../hal/include/hal_init.h: +../hal/include/hpl_init.h: +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hal/include/hal_atomic.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: diff --git a/software/firmware/oracle_same54n19a/gcc/hal/src/hal_init.o b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_init.o new file mode 100644 index 00000000..564d7e3f Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_init.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/hal/src/hal_io.d b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_io.d new file mode 100644 index 00000000..10ecc6fb --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_io.d @@ -0,0 +1,242 @@ +hal/src/hal_io.d hal/src/hal_io.o: ../hal/src/hal_io.c \ + ../hal/include/hal_io.h ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h ../hal/utils/include/utils_assert.h +../hal/include/hal_io.h: +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hal/include/hal_atomic.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: +../hal/utils/include/utils_assert.h: diff --git a/software/firmware/oracle_same54n19a/gcc/hal/src/hal_io.o b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_io.o new file mode 100644 index 00000000..c2c63b82 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_io.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/hal/src/hal_sleep.d b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_sleep.d new file mode 100644 index 00000000..9eaa4e5f --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_sleep.d @@ -0,0 +1,243 @@ +hal/src/hal_sleep.d hal/src/hal_sleep.o: ../hal/src/hal_sleep.c \ + ../hal/include/hal_sleep.h ../hal/include/hpl_sleep.h \ + ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h +../hal/include/hal_sleep.h: +../hal/include/hpl_sleep.h: +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hal/include/hal_atomic.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: diff --git a/software/firmware/oracle_same54n19a/gcc/hal/src/hal_sleep.o b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_sleep.o new file mode 100644 index 00000000..9245b62b Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_sleep.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/hal/src/hal_timer.d b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_timer.d new file mode 100644 index 00000000..c181f198 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_timer.d @@ -0,0 +1,249 @@ +hal/src/hal_timer.d hal/src/hal_timer.o: ../hal/src/hal_timer.c \ + ../hal/include/hal_timer.h ../hal/utils/include/utils_list.h \ + ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h ../hal/include/hpl_timer.h \ + ../hal/include/hpl_irq.h ../hal/utils/include/utils_assert.h \ + ../hal/utils/include/utils.h +../hal/include/hal_timer.h: +../hal/utils/include/utils_list.h: +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hal/include/hal_atomic.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: +../hal/include/hpl_timer.h: +../hal/include/hpl_irq.h: +../hal/utils/include/utils_assert.h: +../hal/utils/include/utils.h: diff --git a/software/firmware/oracle_same54n19a/gcc/hal/src/hal_timer.o b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_timer.o new file mode 100644 index 00000000..c921bdc4 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_timer.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/hal/src/hal_usart_async.d b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_usart_async.d new file mode 100644 index 00000000..7b2f4bb2 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_usart_async.d @@ -0,0 +1,255 @@ +hal/src/hal_usart_async.d hal/src/hal_usart_async.o: \ + ../hal/src/hal_usart_async.c ../hal/include/hal_usart_async.h \ + ../hal/include/hal_io.h ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h ../hal/include/hpl_usart_async.h \ + ../hal/include/hpl_usart.h ../hal/include/hpl_irq.h \ + ../hal/utils/include/utils_ringbuffer.h ../hal/utils/include/compiler.h \ + ../hal/utils/include/utils_assert.h ../hal/utils/include/utils_assert.h \ + ../hal/utils/include/utils.h +../hal/include/hal_usart_async.h: +../hal/include/hal_io.h: +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hal/include/hal_atomic.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: +../hal/include/hpl_usart_async.h: +../hal/include/hpl_usart.h: +../hal/include/hpl_irq.h: +../hal/utils/include/utils_ringbuffer.h: +../hal/utils/include/compiler.h: +../hal/utils/include/utils_assert.h: +../hal/utils/include/utils_assert.h: +../hal/utils/include/utils.h: diff --git a/software/firmware/oracle_same54n19a/gcc/hal/src/hal_usart_async.o b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_usart_async.o new file mode 100644 index 00000000..2ad576fc Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/hal/src/hal_usart_async.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/hal/utils/src/utils_assert.d b/software/firmware/oracle_same54n19a/gcc/hal/utils/src/utils_assert.d new file mode 100644 index 00000000..300a0dfa --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/hal/utils/src/utils_assert.d @@ -0,0 +1,242 @@ +hal/utils/src/utils_assert.d hal/utils/src/utils_assert.o: \ + ../hal/utils/src/utils_assert.c ../hal/utils/include/utils_assert.h \ + ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h +../hal/utils/include/utils_assert.h: +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hal/include/hal_atomic.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: diff --git a/software/firmware/oracle_same54n19a/gcc/hal/utils/src/utils_assert.o b/software/firmware/oracle_same54n19a/gcc/hal/utils/src/utils_assert.o new file mode 100644 index 00000000..697a9745 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/hal/utils/src/utils_assert.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/hal/utils/src/utils_event.d b/software/firmware/oracle_same54n19a/gcc/hal/utils/src/utils_event.d new file mode 100644 index 00000000..ea00fb68 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/hal/utils/src/utils_event.d @@ -0,0 +1,280 @@ +hal/utils/src/utils_event.d hal/utils/src/utils_event.o: \ + ../hal/utils/src/utils_event.c ../hal/utils/include/utils_event.h \ + ../hal/utils/include/utils.h ../hal/utils/include/utils_list.h \ + ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h ../hal/utils/include/events.h \ + ../hal/utils/include/utils_assert.h /usr/arm-none-eabi/include/string.h \ + /usr/arm-none-eabi/include/_ansi.h /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h +../hal/utils/include/utils_event.h: +../hal/utils/include/utils.h: +../hal/utils/include/utils_list.h: +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hal/include/hal_atomic.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: +../hal/utils/include/events.h: +../hal/utils/include/utils_assert.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: diff --git a/software/firmware/oracle_same54n19a/gcc/hal/utils/src/utils_event.o b/software/firmware/oracle_same54n19a/gcc/hal/utils/src/utils_event.o new file mode 100644 index 00000000..c9839d36 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/hal/utils/src/utils_event.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/hal/utils/src/utils_list.d b/software/firmware/oracle_same54n19a/gcc/hal/utils/src/utils_list.d new file mode 100644 index 00000000..7ca31fd5 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/hal/utils/src/utils_list.d @@ -0,0 +1,243 @@ +hal/utils/src/utils_list.d hal/utils/src/utils_list.o: \ + ../hal/utils/src/utils_list.c ../hal/utils/include/utils_list.h \ + ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h ../hal/utils/include/utils_assert.h +../hal/utils/include/utils_list.h: +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hal/include/hal_atomic.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: +../hal/utils/include/utils_assert.h: diff --git a/software/firmware/oracle_same54n19a/gcc/hal/utils/src/utils_list.o b/software/firmware/oracle_same54n19a/gcc/hal/utils/src/utils_list.o new file mode 100644 index 00000000..aa87fd8a Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/hal/utils/src/utils_list.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/hal/utils/src/utils_ringbuffer.d b/software/firmware/oracle_same54n19a/gcc/hal/utils/src/utils_ringbuffer.d new file mode 100644 index 00000000..4a67f0fc --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/hal/utils/src/utils_ringbuffer.d @@ -0,0 +1,245 @@ +hal/utils/src/utils_ringbuffer.d hal/utils/src/utils_ringbuffer.o: \ + ../hal/utils/src/utils_ringbuffer.c \ + ../hal/utils/include/utils_ringbuffer.h ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h \ + ../hal/utils/include/compiler.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h ../hal/utils/include/utils_assert.h +../hal/utils/include/utils_ringbuffer.h: +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hal/include/hal_atomic.h: +../hal/utils/include/compiler.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: +../hal/utils/include/utils_assert.h: diff --git a/software/firmware/oracle_same54n19a/gcc/hal/utils/src/utils_ringbuffer.o b/software/firmware/oracle_same54n19a/gcc/hal/utils/src/utils_ringbuffer.o new file mode 100644 index 00000000..a4fe2109 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/hal/utils/src/utils_ringbuffer.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/hal/utils/src/utils_syscalls.d b/software/firmware/oracle_same54n19a/gcc/hal/utils/src/utils_syscalls.d new file mode 100644 index 00000000..eac24a2d --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/hal/utils/src/utils_syscalls.d @@ -0,0 +1,69 @@ +hal/utils/src/utils_syscalls.d hal/utils/src/utils_syscalls.o: \ + ../hal/utils/src/utils_syscalls.c /usr/arm-none-eabi/include/stdio.h \ + /usr/arm-none-eabi/include/_ansi.h /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/types.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/arm-none-eabi/include/machine/endian.h \ + /usr/arm-none-eabi/include/machine/_endian.h \ + /usr/arm-none-eabi/include/sys/select.h \ + /usr/arm-none-eabi/include/sys/_sigset.h \ + /usr/arm-none-eabi/include/sys/_timeval.h \ + /usr/arm-none-eabi/include/sys/timespec.h \ + /usr/arm-none-eabi/include/sys/_timespec.h \ + /usr/arm-none-eabi/include/sys/_pthreadtypes.h \ + /usr/arm-none-eabi/include/sys/sched.h \ + /usr/arm-none-eabi/include/machine/types.h \ + /usr/arm-none-eabi/include/sys/stdio.h \ + /usr/arm-none-eabi/include/ssp/stdio.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/stat.h /usr/arm-none-eabi/include/time.h \ + /usr/arm-none-eabi/include/machine/time.h \ + /usr/arm-none-eabi/include/sys/_locale.h +/usr/arm-none-eabi/include/stdio.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/types.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/arm-none-eabi/include/machine/endian.h: +/usr/arm-none-eabi/include/machine/_endian.h: +/usr/arm-none-eabi/include/sys/select.h: +/usr/arm-none-eabi/include/sys/_sigset.h: +/usr/arm-none-eabi/include/sys/_timeval.h: +/usr/arm-none-eabi/include/sys/timespec.h: +/usr/arm-none-eabi/include/sys/_timespec.h: +/usr/arm-none-eabi/include/sys/_pthreadtypes.h: +/usr/arm-none-eabi/include/sys/sched.h: +/usr/arm-none-eabi/include/machine/types.h: +/usr/arm-none-eabi/include/sys/stdio.h: +/usr/arm-none-eabi/include/ssp/stdio.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/stat.h: +/usr/arm-none-eabi/include/time.h: +/usr/arm-none-eabi/include/machine/time.h: +/usr/arm-none-eabi/include/sys/_locale.h: diff --git a/software/firmware/oracle_same54n19a/gcc/hal/utils/src/utils_syscalls.o b/software/firmware/oracle_same54n19a/gcc/hal/utils/src/utils_syscalls.o new file mode 100644 index 00000000..a18f0592 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/hal/utils/src/utils_syscalls.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/hpl/cmcc/hpl_cmcc.d b/software/firmware/oracle_same54n19a/gcc/hpl/cmcc/hpl_cmcc.d new file mode 100644 index 00000000..0c50ecd2 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/hpl/cmcc/hpl_cmcc.d @@ -0,0 +1,243 @@ +hpl/cmcc/hpl_cmcc.d hpl/cmcc/hpl_cmcc.o: ../hpl/cmcc/hpl_cmcc.c \ + ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h ../hal/include/hpl_cmcc.h \ + ../config/hpl_cmcc_config.h +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hal/include/hal_atomic.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: +../hal/include/hpl_cmcc.h: +../config/hpl_cmcc_config.h: diff --git a/software/firmware/oracle_same54n19a/gcc/hpl/cmcc/hpl_cmcc.o b/software/firmware/oracle_same54n19a/gcc/hpl/cmcc/hpl_cmcc.o new file mode 100644 index 00000000..c6542bc0 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/hpl/cmcc/hpl_cmcc.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/hpl/core/hpl_core_m4.d b/software/firmware/oracle_same54n19a/gcc/hpl/core/hpl_core_m4.d new file mode 100644 index 00000000..823ae532 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/hpl/core/hpl_core_m4.d @@ -0,0 +1,248 @@ +hpl/core/hpl_core_m4.d hpl/core/hpl_core_m4.o: ../hpl/core/hpl_core_m4.c \ + ../hal/include/hpl_core.h ../hpl/core/hpl_core_port.h \ + ../config/peripheral_clk_config.h ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h ../hal/include/hpl_irq.h \ + ../hal/utils/include/utils.h ../hal/utils/include/utils_assert.h +../hal/include/hpl_core.h: +../hpl/core/hpl_core_port.h: +../config/peripheral_clk_config.h: +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hal/include/hal_atomic.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: +../hal/include/hpl_irq.h: +../hal/utils/include/utils.h: +../hal/utils/include/utils_assert.h: diff --git a/software/firmware/oracle_same54n19a/gcc/hpl/core/hpl_core_m4.o b/software/firmware/oracle_same54n19a/gcc/hpl/core/hpl_core_m4.o new file mode 100644 index 00000000..bd379fac Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/hpl/core/hpl_core_m4.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/hpl/core/hpl_init.d b/software/firmware/oracle_same54n19a/gcc/hpl/core/hpl_init.d new file mode 100644 index 00000000..a5120d7e --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/hpl/core/hpl_init.d @@ -0,0 +1,260 @@ +hpl/core/hpl_init.d hpl/core/hpl_init.o: ../hpl/core/hpl_init.c \ + ../hal/include/hpl_gpio.h ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h ../hpl/port/hpl_gpio_base.h \ + ../hal/utils/include/utils_assert.h ../config/hpl_port_config.h \ + ../hal/include/hpl_init.h ../hpl/gclk/hpl_gclk_base.h \ + ../config/hpl_mclk_config.h ../config/peripheral_clk_config.h \ + ../hal/include/hpl_dma.h ../hal/include/hpl_irq.h \ + ../config/hpl_dmac_config.h ../config/hpl_cmcc_config.h \ + ../hal/include/hal_cache.h ../hal/include/hpl_cmcc.h +../hal/include/hpl_gpio.h: +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hal/include/hal_atomic.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: +../hpl/port/hpl_gpio_base.h: +../hal/utils/include/utils_assert.h: +../config/hpl_port_config.h: +../hal/include/hpl_init.h: +../hpl/gclk/hpl_gclk_base.h: +../config/hpl_mclk_config.h: +../config/peripheral_clk_config.h: +../hal/include/hpl_dma.h: +../hal/include/hpl_irq.h: +../config/hpl_dmac_config.h: +../config/hpl_cmcc_config.h: +../hal/include/hal_cache.h: +../hal/include/hpl_cmcc.h: diff --git a/software/firmware/oracle_same54n19a/gcc/hpl/core/hpl_init.o b/software/firmware/oracle_same54n19a/gcc/hpl/core/hpl_init.o new file mode 100644 index 00000000..0376e648 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/hpl/core/hpl_init.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/hpl/dmac/hpl_dmac.d b/software/firmware/oracle_same54n19a/gcc/hpl/dmac/hpl_dmac.d new file mode 100644 index 00000000..8bf5f1fc --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/hpl/dmac/hpl_dmac.d @@ -0,0 +1,250 @@ +hpl/dmac/hpl_dmac.d hpl/dmac/hpl_dmac.o: ../hpl/dmac/hpl_dmac.c \ + ../hal/include/hpl_dma.h ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h ../hal/include/hpl_irq.h \ + ../hal/utils/include/utils_assert.h ../hal/utils/include/utils.h \ + ../config/hpl_dmac_config.h ../hal/utils/include/utils_repeat_macro.h \ + ../hal/utils/include/utils_increment_macro.h +../hal/include/hpl_dma.h: +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hal/include/hal_atomic.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: +../hal/include/hpl_irq.h: +../hal/utils/include/utils_assert.h: +../hal/utils/include/utils.h: +../config/hpl_dmac_config.h: +../hal/utils/include/utils_repeat_macro.h: +../hal/utils/include/utils_increment_macro.h: diff --git a/software/firmware/oracle_same54n19a/gcc/hpl/dmac/hpl_dmac.o b/software/firmware/oracle_same54n19a/gcc/hpl/dmac/hpl_dmac.o new file mode 100644 index 00000000..6625ee67 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/hpl/dmac/hpl_dmac.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/hpl/eic/hpl_eic.d b/software/firmware/oracle_same54n19a/gcc/hpl/eic/hpl_eic.d new file mode 100644 index 00000000..55858efd --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/hpl/eic/hpl_eic.d @@ -0,0 +1,278 @@ +hpl/eic/hpl_eic.d hpl/eic/hpl_eic.o: ../hpl/eic/hpl_eic.c \ + ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h ../config/hpl_eic_config.h \ + ../hal/include/hpl_ext_irq.h /usr/arm-none-eabi/include/string.h \ + /usr/arm-none-eabi/include/_ansi.h /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h ../hal/utils/include/utils.h \ + ../hal/utils/include/utils_assert.h +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hal/include/hal_atomic.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: +../config/hpl_eic_config.h: +../hal/include/hpl_ext_irq.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../hal/utils/include/utils.h: +../hal/utils/include/utils_assert.h: diff --git a/software/firmware/oracle_same54n19a/gcc/hpl/eic/hpl_eic.o b/software/firmware/oracle_same54n19a/gcc/hpl/eic/hpl_eic.o new file mode 100644 index 00000000..d5cf3b45 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/hpl/eic/hpl_eic.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/hpl/gclk/hpl_gclk.d b/software/firmware/oracle_same54n19a/gcc/hpl/gclk/hpl_gclk.d new file mode 100644 index 00000000..342482b3 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/hpl/gclk/hpl_gclk.d @@ -0,0 +1,244 @@ +hpl/gclk/hpl_gclk.d hpl/gclk/hpl_gclk.o: ../hpl/gclk/hpl_gclk.c \ + ../config/hpl_gclk_config.h ../hal/include/hpl_init.h \ + ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h ../hal/utils/include/utils_assert.h +../config/hpl_gclk_config.h: +../hal/include/hpl_init.h: +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hal/include/hal_atomic.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: +../hal/utils/include/utils_assert.h: diff --git a/software/firmware/oracle_same54n19a/gcc/hpl/gclk/hpl_gclk.o b/software/firmware/oracle_same54n19a/gcc/hpl/gclk/hpl_gclk.o new file mode 100644 index 00000000..7e2cb55e Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/hpl/gclk/hpl_gclk.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/hpl/mclk/hpl_mclk.d b/software/firmware/oracle_same54n19a/gcc/hpl/mclk/hpl_mclk.d new file mode 100644 index 00000000..478e39ac --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/hpl/mclk/hpl_mclk.d @@ -0,0 +1,243 @@ +hpl/mclk/hpl_mclk.d hpl/mclk/hpl_mclk.o: ../hpl/mclk/hpl_mclk.c \ + ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h ../config/hpl_mclk_config.h \ + ../config/peripheral_clk_config.h +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hal/include/hal_atomic.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: +../config/hpl_mclk_config.h: +../config/peripheral_clk_config.h: diff --git a/software/firmware/oracle_same54n19a/gcc/hpl/mclk/hpl_mclk.o b/software/firmware/oracle_same54n19a/gcc/hpl/mclk/hpl_mclk.o new file mode 100644 index 00000000..d8614ca5 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/hpl/mclk/hpl_mclk.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/hpl/osc32kctrl/hpl_osc32kctrl.d b/software/firmware/oracle_same54n19a/gcc/hpl/osc32kctrl/hpl_osc32kctrl.d new file mode 100644 index 00000000..a7c6fab9 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/hpl/osc32kctrl/hpl_osc32kctrl.d @@ -0,0 +1,243 @@ +hpl/osc32kctrl/hpl_osc32kctrl.d hpl/osc32kctrl/hpl_osc32kctrl.o: \ + ../hpl/osc32kctrl/hpl_osc32kctrl.c ../hal/include/hpl_init.h \ + ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h ../config/hpl_osc32kctrl_config.h +../hal/include/hpl_init.h: +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hal/include/hal_atomic.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: +../config/hpl_osc32kctrl_config.h: diff --git a/software/firmware/oracle_same54n19a/gcc/hpl/osc32kctrl/hpl_osc32kctrl.o b/software/firmware/oracle_same54n19a/gcc/hpl/osc32kctrl/hpl_osc32kctrl.o new file mode 100644 index 00000000..7dc5bcbc Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/hpl/osc32kctrl/hpl_osc32kctrl.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/hpl/oscctrl/hpl_oscctrl.d b/software/firmware/oracle_same54n19a/gcc/hpl/oscctrl/hpl_oscctrl.d new file mode 100644 index 00000000..05b0f867 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/hpl/oscctrl/hpl_oscctrl.d @@ -0,0 +1,245 @@ +hpl/oscctrl/hpl_oscctrl.d hpl/oscctrl/hpl_oscctrl.o: \ + ../hpl/oscctrl/hpl_oscctrl.c ../hal/include/hpl_init.h \ + ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h ../config/hpl_oscctrl_config.h \ + ../config/hpl_gclk_config.h +../hal/include/hpl_init.h: +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hal/include/hal_atomic.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: +../config/hpl_oscctrl_config.h: +../config/hpl_gclk_config.h: diff --git a/software/firmware/oracle_same54n19a/gcc/hpl/oscctrl/hpl_oscctrl.o b/software/firmware/oracle_same54n19a/gcc/hpl/oscctrl/hpl_oscctrl.o new file mode 100644 index 00000000..0c73a485 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/hpl/oscctrl/hpl_oscctrl.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/hpl/pm/hpl_pm.d b/software/firmware/oracle_same54n19a/gcc/hpl/pm/hpl_pm.d new file mode 100644 index 00000000..0ee2996a --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/hpl/pm/hpl_pm.d @@ -0,0 +1,242 @@ +hpl/pm/hpl_pm.d hpl/pm/hpl_pm.o: ../hpl/pm/hpl_pm.c \ + ../hal/include/hpl_sleep.h ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h ../hal/include/hpl_init.h +../hal/include/hpl_sleep.h: +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hal/include/hal_atomic.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: +../hal/include/hpl_init.h: diff --git a/software/firmware/oracle_same54n19a/gcc/hpl/pm/hpl_pm.o b/software/firmware/oracle_same54n19a/gcc/hpl/pm/hpl_pm.o new file mode 100644 index 00000000..ec81e1f2 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/hpl/pm/hpl_pm.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/hpl/ramecc/hpl_ramecc.d b/software/firmware/oracle_same54n19a/gcc/hpl/ramecc/hpl_ramecc.d new file mode 100644 index 00000000..1d9008b7 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/hpl/ramecc/hpl_ramecc.d @@ -0,0 +1,246 @@ +hpl/ramecc/hpl_ramecc.d hpl/ramecc/hpl_ramecc.o: \ + ../hpl/ramecc/hpl_ramecc.c ../hal/utils/include/utils.h \ + ../hal/utils/include/utils_assert.h ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h ../hal/include/hpl_ramecc.h \ + ../hal/include/hpl_irq.h +../hal/utils/include/utils.h: +../hal/utils/include/utils_assert.h: +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hal/include/hal_atomic.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: +../hal/include/hpl_ramecc.h: +../hal/include/hpl_irq.h: diff --git a/software/firmware/oracle_same54n19a/gcc/hpl/ramecc/hpl_ramecc.o b/software/firmware/oracle_same54n19a/gcc/hpl/ramecc/hpl_ramecc.o new file mode 100644 index 00000000..c36d18ab Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/hpl/ramecc/hpl_ramecc.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/hpl/sercom/hpl_sercom.d b/software/firmware/oracle_same54n19a/gcc/hpl/sercom/hpl_sercom.d new file mode 100644 index 00000000..7c2eaee2 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/hpl/sercom/hpl_sercom.d @@ -0,0 +1,275 @@ +hpl/sercom/hpl_sercom.d hpl/sercom/hpl_sercom.o: \ + ../hpl/sercom/hpl_sercom.c ../hal/include/hpl_dma.h \ + ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h ../hal/include/hpl_irq.h \ + ../hal/include/hpl_i2c_m_async.h ../hal/include/hpl_i2c_m_sync.h \ + ../hal/include/hpl_irq.h ../hal/utils/include/utils.h \ + ../hal/include/hpl_i2c_m_sync.h ../hal/include/hpl_i2c_s_async.h \ + ../hal/include/hpl_i2c_s_sync.h ../config/hpl_sercom_config.h \ + ../config/peripheral_clk_config.h ../hal/include/hpl_spi_m_async.h \ + ../hal/include/hpl_spi.h ../hal/include/hpl_spi_async.h \ + ../hal/include/hpl_spi_m_sync.h ../hal/include/hpl_spi_sync.h \ + ../hal/include/hpl_spi_s_async.h ../hal/include/hpl_spi_s_sync.h \ + ../hal/include/hpl_usart_async.h ../hal/include/hpl_usart.h \ + ../hal/include/hpl_usart_sync.h ../hal/include/hpl_usart.h \ + ../hal/utils/include/utils_assert.h +../hal/include/hpl_dma.h: +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hal/include/hal_atomic.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: +../hal/include/hpl_irq.h: +../hal/include/hpl_i2c_m_async.h: +../hal/include/hpl_i2c_m_sync.h: +../hal/include/hpl_irq.h: +../hal/utils/include/utils.h: +../hal/include/hpl_i2c_m_sync.h: +../hal/include/hpl_i2c_s_async.h: +../hal/include/hpl_i2c_s_sync.h: +../config/hpl_sercom_config.h: +../config/peripheral_clk_config.h: +../hal/include/hpl_spi_m_async.h: +../hal/include/hpl_spi.h: +../hal/include/hpl_spi_async.h: +../hal/include/hpl_spi_m_sync.h: +../hal/include/hpl_spi_sync.h: +../hal/include/hpl_spi_s_async.h: +../hal/include/hpl_spi_s_sync.h: +../hal/include/hpl_usart_async.h: +../hal/include/hpl_usart.h: +../hal/include/hpl_usart_sync.h: +../hal/include/hpl_usart.h: +../hal/utils/include/utils_assert.h: diff --git a/software/firmware/oracle_same54n19a/gcc/hpl/sercom/hpl_sercom.o b/software/firmware/oracle_same54n19a/gcc/hpl/sercom/hpl_sercom.o new file mode 100644 index 00000000..9d9e5090 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/hpl/sercom/hpl_sercom.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/hpl/tc/hpl_tc.d b/software/firmware/oracle_same54n19a/gcc/hpl/tc/hpl_tc.d new file mode 100644 index 00000000..33550091 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/hpl/tc/hpl_tc.d @@ -0,0 +1,253 @@ +hpl/tc/hpl_tc.d hpl/tc/hpl_tc.o: ../hpl/tc/hpl_tc.c \ + ../hal/include/hpl_pwm.h ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h ../hal/include/hpl_irq.h \ + ../config/hpl_tc_config.h ../config/peripheral_clk_config.h \ + ../hal/include/hpl_timer.h ../hal/include/hpl_irq.h \ + ../hal/utils/include/utils.h ../hal/utils/include/utils_assert.h \ + ../hpl/tc/hpl_tc_base.h +../hal/include/hpl_pwm.h: +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hal/include/hal_atomic.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: +../hal/include/hpl_irq.h: +../config/hpl_tc_config.h: +../config/peripheral_clk_config.h: +../hal/include/hpl_timer.h: +../hal/include/hpl_irq.h: +../hal/utils/include/utils.h: +../hal/utils/include/utils_assert.h: +../hpl/tc/hpl_tc_base.h: diff --git a/software/firmware/oracle_same54n19a/gcc/hpl/tc/hpl_tc.o b/software/firmware/oracle_same54n19a/gcc/hpl/tc/hpl_tc.o new file mode 100644 index 00000000..2fd7b3ca Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/hpl/tc/hpl_tc.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/main.d b/software/firmware/oracle_same54n19a/gcc/main.d new file mode 100644 index 00000000..41e06cf4 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/main.d @@ -0,0 +1,361 @@ +main.d main.o: ../main.c ../include/oracle.h ../config/pc_board.h \ + ../hal/include/hal_gpio.h ../hal/include/hpl_gpio.h \ + ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h ../hpl/port/hpl_gpio_base.h \ + ../hal/utils/include/utils_assert.h ../config/hpl_port_config.h \ + ../config/pc_master.h ../hal/include/hal_delay.h \ + ../hal/include/hpl_irq.h ../hal/include/hpl_reset.h \ + ../hal/include/hpl_sleep.h ../hal/include/hal_init.h \ + ../hal/include/hpl_init.h ../hal/include/hal_io.h \ + ../hal/include/hal_sleep.h ../hal/include/hal_ext_irq.h \ + ../hal/include/hpl_ext_irq.h ../hal/include/hal_usart_async.h \ + ../hal/include/hal_io.h ../hal/include/hpl_usart_async.h \ + ../hal/include/hpl_usart.h ../hal/include/hpl_irq.h \ + ../hal/utils/include/utils_ringbuffer.h ../hal/utils/include/compiler.h \ + ../hal/utils/include/utils_assert.h ../hal/include/hal_i2c_m_sync.h \ + ../hal/include/hpl_i2c_m_sync.h ../hal/include/hal_timer.h \ + ../hal/utils/include/utils_list.h ../hal/include/hpl_timer.h \ + ../hpl/tc/hpl_tc_base.h ../hal/include/hpl_pwm.h \ + ../config/peripheral_clk_config.h ../hal/utils/include/utils.h \ + /usr/arm-none-eabi/include/stdio.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/types.h \ + /usr/arm-none-eabi/include/machine/endian.h \ + /usr/arm-none-eabi/include/machine/_endian.h \ + /usr/arm-none-eabi/include/sys/select.h \ + /usr/arm-none-eabi/include/sys/_sigset.h \ + /usr/arm-none-eabi/include/sys/_timeval.h \ + /usr/arm-none-eabi/include/sys/timespec.h \ + /usr/arm-none-eabi/include/sys/_timespec.h \ + /usr/arm-none-eabi/include/sys/_pthreadtypes.h \ + /usr/arm-none-eabi/include/sys/sched.h \ + /usr/arm-none-eabi/include/machine/types.h \ + /usr/arm-none-eabi/include/sys/stdio.h \ + /usr/arm-none-eabi/include/ssp/stdio.h \ + /usr/arm-none-eabi/include/ssp/ssp.h /usr/arm-none-eabi/include/stdlib.h \ + /usr/arm-none-eabi/include/machine/stdlib.h \ + /usr/arm-none-eabi/include/alloca.h \ + /usr/arm-none-eabi/include/ssp/stdlib.h \ + /usr/arm-none-eabi/include/string.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h +../include/oracle.h: +../config/pc_board.h: +../hal/include/hal_gpio.h: +../hal/include/hpl_gpio.h: +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hal/include/hal_atomic.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: +../hpl/port/hpl_gpio_base.h: +../hal/utils/include/utils_assert.h: +../config/hpl_port_config.h: +../config/pc_master.h: +../hal/include/hal_delay.h: +../hal/include/hpl_irq.h: +../hal/include/hpl_reset.h: +../hal/include/hpl_sleep.h: +../hal/include/hal_init.h: +../hal/include/hpl_init.h: +../hal/include/hal_io.h: +../hal/include/hal_sleep.h: +../hal/include/hal_ext_irq.h: +../hal/include/hpl_ext_irq.h: +../hal/include/hal_usart_async.h: +../hal/include/hal_io.h: +../hal/include/hpl_usart_async.h: +../hal/include/hpl_usart.h: +../hal/include/hpl_irq.h: +../hal/utils/include/utils_ringbuffer.h: +../hal/utils/include/compiler.h: +../hal/utils/include/utils_assert.h: +../hal/include/hal_i2c_m_sync.h: +../hal/include/hpl_i2c_m_sync.h: +../hal/include/hal_timer.h: +../hal/utils/include/utils_list.h: +../hal/include/hpl_timer.h: +../hpl/tc/hpl_tc_base.h: +../hal/include/hpl_pwm.h: +../config/peripheral_clk_config.h: +../hal/utils/include/utils.h: +/usr/arm-none-eabi/include/stdio.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/types.h: +/usr/arm-none-eabi/include/machine/endian.h: +/usr/arm-none-eabi/include/machine/_endian.h: +/usr/arm-none-eabi/include/sys/select.h: +/usr/arm-none-eabi/include/sys/_sigset.h: +/usr/arm-none-eabi/include/sys/_timeval.h: +/usr/arm-none-eabi/include/sys/timespec.h: +/usr/arm-none-eabi/include/sys/_timespec.h: +/usr/arm-none-eabi/include/sys/_pthreadtypes.h: +/usr/arm-none-eabi/include/sys/sched.h: +/usr/arm-none-eabi/include/machine/types.h: +/usr/arm-none-eabi/include/sys/stdio.h: +/usr/arm-none-eabi/include/ssp/stdio.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/stdlib.h: +/usr/arm-none-eabi/include/machine/stdlib.h: +/usr/arm-none-eabi/include/alloca.h: +/usr/arm-none-eabi/include/ssp/stdlib.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: diff --git a/software/firmware/oracle_same54n19a/gcc/main.o b/software/firmware/oracle_same54n19a/gcc/main.o new file mode 100644 index 00000000..50c6f38a Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/main.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/oracle.d b/software/firmware/oracle_same54n19a/gcc/oracle.d new file mode 100644 index 00000000..18d73351 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/oracle.d @@ -0,0 +1,676 @@ +oracle.d oracle.o: ../oracle.c ../include/oracle.h ../config/pc_board.h \ + ../hal/include/hal_gpio.h ../hal/include/hpl_gpio.h \ + ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h ../hpl/port/hpl_gpio_base.h \ + ../hal/utils/include/utils_assert.h ../config/hpl_port_config.h \ + ../config/pc_master.h ../hal/include/hal_delay.h \ + ../hal/include/hpl_irq.h ../hal/include/hpl_reset.h \ + ../hal/include/hpl_sleep.h ../hal/include/hal_init.h \ + ../hal/include/hpl_init.h ../hal/include/hal_io.h \ + ../hal/include/hal_sleep.h ../hal/include/hal_ext_irq.h \ + ../hal/include/hpl_ext_irq.h ../hal/include/hal_usart_async.h \ + ../hal/include/hal_io.h ../hal/include/hpl_usart_async.h \ + ../hal/include/hpl_usart.h ../hal/include/hpl_irq.h \ + ../hal/utils/include/utils_ringbuffer.h ../hal/utils/include/compiler.h \ + ../hal/utils/include/utils_assert.h ../hal/include/hal_i2c_m_sync.h \ + ../hal/include/hpl_i2c_m_sync.h ../hal/include/hal_timer.h \ + ../hal/utils/include/utils_list.h ../hal/include/hpl_timer.h \ + ../hpl/tc/hpl_tc_base.h ../hal/include/hpl_pwm.h \ + ../config/peripheral_clk_config.h ../hal/utils/include/utils.h \ + /usr/arm-none-eabi/include/stdio.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/types.h \ + /usr/arm-none-eabi/include/machine/endian.h \ + /usr/arm-none-eabi/include/machine/_endian.h \ + /usr/arm-none-eabi/include/sys/select.h \ + /usr/arm-none-eabi/include/sys/_sigset.h \ + /usr/arm-none-eabi/include/sys/_timeval.h \ + /usr/arm-none-eabi/include/sys/timespec.h \ + /usr/arm-none-eabi/include/sys/_timespec.h \ + /usr/arm-none-eabi/include/sys/_pthreadtypes.h \ + /usr/arm-none-eabi/include/sys/sched.h \ + /usr/arm-none-eabi/include/machine/types.h \ + /usr/arm-none-eabi/include/sys/stdio.h \ + /usr/arm-none-eabi/include/ssp/stdio.h \ + /usr/arm-none-eabi/include/ssp/ssp.h /usr/arm-none-eabi/include/stdlib.h \ + /usr/arm-none-eabi/include/machine/stdlib.h \ + /usr/arm-none-eabi/include/alloca.h \ + /usr/arm-none-eabi/include/ssp/stdlib.h \ + /usr/arm-none-eabi/include/string.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h ../shared/drivers/p_usart.h \ + ../shared/drivers/p_gpio.h ../shared/drivers/p_i2c.h \ + ../shared/drivers/p_tcc.h ../shared/thirdparty/lvgl/lvgl.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h \ + ../config/lv_conf.h ../shared/thirdparty/lvgl/src/lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_async.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_group.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_indev.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_core/lv_group.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_refr.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_disp.h \ + ../shared/thirdparty/lvgl/src/lv_themes/lv_theme.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_themes/lv_theme_empty.h \ + ../shared/thirdparty/lvgl/src/lv_themes/lv_theme_template.h \ + ../shared/thirdparty/lvgl/src/lv_themes/lv_theme_material.h \ + ../shared/thirdparty/lvgl/src/lv_themes/lv_theme_mono.h \ + ../shared/thirdparty/lvgl/src/lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_font/lv_font_fmt_txt.h \ + ../shared/thirdparty/lvgl/src/lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_printf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_btn.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_cont.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_imgbtn.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_btn.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_page.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_cont.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_list.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_page.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_chart.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_table.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_checkbox.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_cpicker.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_bar.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_slider.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_bar.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_led.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_btnmatrix.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_keyboard.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_btnmatrix.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_dropdown.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_page.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_roller.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_textarea.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_canvas.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_win.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_tabview.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_win.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_tileview.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_msgbox.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_objmask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_cont.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_gauge.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_linemeter.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_linemeter.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_switch.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_arc.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_spinner.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_arc.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_calendar.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_spinbox.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_textarea.h \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_img_cache.h \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_api_map.h \ + ../shared/thirdparty/lvgl/src/../lvgl.h \ + ../shared/devices/display/p_ssd1963.h ../shared/devices/p_screen.h +../include/oracle.h: +../config/pc_board.h: +../hal/include/hal_gpio.h: +../hal/include/hpl_gpio.h: +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hal/include/hal_atomic.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: +../hpl/port/hpl_gpio_base.h: +../hal/utils/include/utils_assert.h: +../config/hpl_port_config.h: +../config/pc_master.h: +../hal/include/hal_delay.h: +../hal/include/hpl_irq.h: +../hal/include/hpl_reset.h: +../hal/include/hpl_sleep.h: +../hal/include/hal_init.h: +../hal/include/hpl_init.h: +../hal/include/hal_io.h: +../hal/include/hal_sleep.h: +../hal/include/hal_ext_irq.h: +../hal/include/hpl_ext_irq.h: +../hal/include/hal_usart_async.h: +../hal/include/hal_io.h: +../hal/include/hpl_usart_async.h: +../hal/include/hpl_usart.h: +../hal/include/hpl_irq.h: +../hal/utils/include/utils_ringbuffer.h: +../hal/utils/include/compiler.h: +../hal/utils/include/utils_assert.h: +../hal/include/hal_i2c_m_sync.h: +../hal/include/hpl_i2c_m_sync.h: +../hal/include/hal_timer.h: +../hal/utils/include/utils_list.h: +../hal/include/hpl_timer.h: +../hpl/tc/hpl_tc_base.h: +../hal/include/hpl_pwm.h: +../config/peripheral_clk_config.h: +../hal/utils/include/utils.h: +/usr/arm-none-eabi/include/stdio.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/types.h: +/usr/arm-none-eabi/include/machine/endian.h: +/usr/arm-none-eabi/include/machine/_endian.h: +/usr/arm-none-eabi/include/sys/select.h: +/usr/arm-none-eabi/include/sys/_sigset.h: +/usr/arm-none-eabi/include/sys/_timeval.h: +/usr/arm-none-eabi/include/sys/timespec.h: +/usr/arm-none-eabi/include/sys/_timespec.h: +/usr/arm-none-eabi/include/sys/_pthreadtypes.h: +/usr/arm-none-eabi/include/sys/sched.h: +/usr/arm-none-eabi/include/machine/types.h: +/usr/arm-none-eabi/include/sys/stdio.h: +/usr/arm-none-eabi/include/ssp/stdio.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/stdlib.h: +/usr/arm-none-eabi/include/machine/stdlib.h: +/usr/arm-none-eabi/include/alloca.h: +/usr/arm-none-eabi/include/ssp/stdlib.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/drivers/p_usart.h: +../shared/drivers/p_gpio.h: +../shared/drivers/p_i2c.h: +../shared/drivers/p_tcc.h: +../shared/thirdparty/lvgl/lvgl.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h: +../config/lv_conf.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_async.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_core/lv_group.h: +../shared/thirdparty/lvgl/src/lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_core/lv_indev.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_core/lv_group.h: +../shared/thirdparty/lvgl/src/lv_core/lv_refr.h: +../shared/thirdparty/lvgl/src/lv_core/lv_disp.h: +../shared/thirdparty/lvgl/src/lv_themes/lv_theme.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_themes/lv_theme_empty.h: +../shared/thirdparty/lvgl/src/lv_themes/lv_theme_template.h: +../shared/thirdparty/lvgl/src/lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/src/lv_themes/lv_theme_mono.h: +../shared/thirdparty/lvgl/src/lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_font/lv_font_fmt_txt.h: +../shared/thirdparty/lvgl/src/lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_printf.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_btn.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_cont.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_indev.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_imgbtn.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_btn.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_page.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_cont.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_list.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_page.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_chart.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_table.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_checkbox.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_cpicker.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_bar.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_slider.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_bar.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_led.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_btnmatrix.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_keyboard.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_btnmatrix.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_dropdown.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_page.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_roller.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_textarea.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_canvas.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_win.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_tabview.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_win.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_tileview.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_msgbox.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_objmask.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_cont.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_gauge.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_linemeter.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_linemeter.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_switch.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_arc.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_spinner.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_arc.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_calendar.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_spinbox.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_textarea.h: +../shared/thirdparty/lvgl/src/lv_draw/lv_img_cache.h: +../shared/thirdparty/lvgl/src/lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_api_map.h: +../shared/thirdparty/lvgl/src/../lvgl.h: +../shared/devices/display/p_ssd1963.h: +../shared/devices/p_screen.h: diff --git a/software/firmware/oracle_same54n19a/gcc/oracle.o b/software/firmware/oracle_same54n19a/gcc/oracle.o new file mode 100644 index 00000000..0d6debc9 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/oracle.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/devices/display/p_ssd1963.d b/software/firmware/oracle_same54n19a/gcc/shared/devices/display/p_ssd1963.d new file mode 100644 index 00000000..52a09b70 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/devices/display/p_ssd1963.d @@ -0,0 +1,671 @@ +shared/devices/display/p_ssd1963.d shared/devices/display/p_ssd1963.o: \ + ../shared/devices/display/p_ssd1963.c \ + ../shared/devices/display/p_ssd1963.h ../include/oracle.h \ + ../config/pc_board.h ../hal/include/hal_gpio.h ../hal/include/hpl_gpio.h \ + ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h ../hpl/port/hpl_gpio_base.h \ + ../hal/utils/include/utils_assert.h ../config/hpl_port_config.h \ + ../config/pc_master.h ../hal/include/hal_delay.h \ + ../hal/include/hpl_irq.h ../hal/include/hpl_reset.h \ + ../hal/include/hpl_sleep.h ../hal/include/hal_init.h \ + ../hal/include/hpl_init.h ../hal/include/hal_io.h \ + ../hal/include/hal_sleep.h ../hal/include/hal_ext_irq.h \ + ../hal/include/hpl_ext_irq.h ../hal/include/hal_usart_async.h \ + ../hal/include/hal_io.h ../hal/include/hpl_usart_async.h \ + ../hal/include/hpl_usart.h ../hal/include/hpl_irq.h \ + ../hal/utils/include/utils_ringbuffer.h ../hal/utils/include/compiler.h \ + ../hal/utils/include/utils_assert.h ../hal/include/hal_i2c_m_sync.h \ + ../hal/include/hpl_i2c_m_sync.h ../hal/include/hal_timer.h \ + ../hal/utils/include/utils_list.h ../hal/include/hpl_timer.h \ + ../hpl/tc/hpl_tc_base.h ../hal/include/hpl_pwm.h \ + ../config/peripheral_clk_config.h ../hal/utils/include/utils.h \ + /usr/arm-none-eabi/include/stdio.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/types.h \ + /usr/arm-none-eabi/include/machine/endian.h \ + /usr/arm-none-eabi/include/machine/_endian.h \ + /usr/arm-none-eabi/include/sys/select.h \ + /usr/arm-none-eabi/include/sys/_sigset.h \ + /usr/arm-none-eabi/include/sys/_timeval.h \ + /usr/arm-none-eabi/include/sys/timespec.h \ + /usr/arm-none-eabi/include/sys/_timespec.h \ + /usr/arm-none-eabi/include/sys/_pthreadtypes.h \ + /usr/arm-none-eabi/include/sys/sched.h \ + /usr/arm-none-eabi/include/machine/types.h \ + /usr/arm-none-eabi/include/sys/stdio.h \ + /usr/arm-none-eabi/include/ssp/stdio.h \ + /usr/arm-none-eabi/include/ssp/ssp.h /usr/arm-none-eabi/include/stdlib.h \ + /usr/arm-none-eabi/include/machine/stdlib.h \ + /usr/arm-none-eabi/include/alloca.h \ + /usr/arm-none-eabi/include/ssp/stdlib.h \ + /usr/arm-none-eabi/include/string.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h ../shared/thirdparty/lvgl/lvgl.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h \ + ../config/lv_conf.h ../shared/thirdparty/lvgl/src/lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_async.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_group.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_indev.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_core/lv_group.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_refr.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_disp.h \ + ../shared/thirdparty/lvgl/src/lv_themes/lv_theme.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_themes/lv_theme_empty.h \ + ../shared/thirdparty/lvgl/src/lv_themes/lv_theme_template.h \ + ../shared/thirdparty/lvgl/src/lv_themes/lv_theme_material.h \ + ../shared/thirdparty/lvgl/src/lv_themes/lv_theme_mono.h \ + ../shared/thirdparty/lvgl/src/lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_font/lv_font_fmt_txt.h \ + ../shared/thirdparty/lvgl/src/lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_printf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_btn.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_cont.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_imgbtn.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_btn.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_page.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_cont.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_list.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_page.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_chart.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_table.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_checkbox.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_cpicker.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_bar.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_slider.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_bar.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_led.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_btnmatrix.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_keyboard.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_btnmatrix.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_dropdown.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_page.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_roller.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_textarea.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_canvas.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_win.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_tabview.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_win.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_tileview.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_msgbox.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_objmask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_cont.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_gauge.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_linemeter.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_linemeter.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_switch.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_arc.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_spinner.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_arc.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_calendar.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_spinbox.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_textarea.h \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_img_cache.h \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_api_map.h \ + ../shared/thirdparty/lvgl/src/../lvgl.h ../shared/drivers/p_gpio.h +../shared/devices/display/p_ssd1963.h: +../include/oracle.h: +../config/pc_board.h: +../hal/include/hal_gpio.h: +../hal/include/hpl_gpio.h: +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hal/include/hal_atomic.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: +../hpl/port/hpl_gpio_base.h: +../hal/utils/include/utils_assert.h: +../config/hpl_port_config.h: +../config/pc_master.h: +../hal/include/hal_delay.h: +../hal/include/hpl_irq.h: +../hal/include/hpl_reset.h: +../hal/include/hpl_sleep.h: +../hal/include/hal_init.h: +../hal/include/hpl_init.h: +../hal/include/hal_io.h: +../hal/include/hal_sleep.h: +../hal/include/hal_ext_irq.h: +../hal/include/hpl_ext_irq.h: +../hal/include/hal_usart_async.h: +../hal/include/hal_io.h: +../hal/include/hpl_usart_async.h: +../hal/include/hpl_usart.h: +../hal/include/hpl_irq.h: +../hal/utils/include/utils_ringbuffer.h: +../hal/utils/include/compiler.h: +../hal/utils/include/utils_assert.h: +../hal/include/hal_i2c_m_sync.h: +../hal/include/hpl_i2c_m_sync.h: +../hal/include/hal_timer.h: +../hal/utils/include/utils_list.h: +../hal/include/hpl_timer.h: +../hpl/tc/hpl_tc_base.h: +../hal/include/hpl_pwm.h: +../config/peripheral_clk_config.h: +../hal/utils/include/utils.h: +/usr/arm-none-eabi/include/stdio.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/types.h: +/usr/arm-none-eabi/include/machine/endian.h: +/usr/arm-none-eabi/include/machine/_endian.h: +/usr/arm-none-eabi/include/sys/select.h: +/usr/arm-none-eabi/include/sys/_sigset.h: +/usr/arm-none-eabi/include/sys/_timeval.h: +/usr/arm-none-eabi/include/sys/timespec.h: +/usr/arm-none-eabi/include/sys/_timespec.h: +/usr/arm-none-eabi/include/sys/_pthreadtypes.h: +/usr/arm-none-eabi/include/sys/sched.h: +/usr/arm-none-eabi/include/machine/types.h: +/usr/arm-none-eabi/include/sys/stdio.h: +/usr/arm-none-eabi/include/ssp/stdio.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/stdlib.h: +/usr/arm-none-eabi/include/machine/stdlib.h: +/usr/arm-none-eabi/include/alloca.h: +/usr/arm-none-eabi/include/ssp/stdlib.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/lvgl.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h: +../config/lv_conf.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_async.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_core/lv_group.h: +../shared/thirdparty/lvgl/src/lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_core/lv_indev.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_core/lv_group.h: +../shared/thirdparty/lvgl/src/lv_core/lv_refr.h: +../shared/thirdparty/lvgl/src/lv_core/lv_disp.h: +../shared/thirdparty/lvgl/src/lv_themes/lv_theme.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_themes/lv_theme_empty.h: +../shared/thirdparty/lvgl/src/lv_themes/lv_theme_template.h: +../shared/thirdparty/lvgl/src/lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/src/lv_themes/lv_theme_mono.h: +../shared/thirdparty/lvgl/src/lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_font/lv_font_fmt_txt.h: +../shared/thirdparty/lvgl/src/lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_printf.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_btn.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_cont.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_indev.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_imgbtn.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_btn.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_page.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_cont.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_list.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_page.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_chart.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_table.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_checkbox.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_cpicker.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_bar.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_slider.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_bar.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_led.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_btnmatrix.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_keyboard.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_btnmatrix.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_dropdown.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_page.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_roller.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_textarea.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_canvas.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_win.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_tabview.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_win.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_tileview.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_msgbox.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_objmask.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_cont.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_gauge.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_linemeter.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_linemeter.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_switch.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_arc.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_spinner.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_arc.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_calendar.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_spinbox.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_textarea.h: +../shared/thirdparty/lvgl/src/lv_draw/lv_img_cache.h: +../shared/thirdparty/lvgl/src/lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_api_map.h: +../shared/thirdparty/lvgl/src/../lvgl.h: +../shared/drivers/p_gpio.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/devices/display/p_ssd1963.o b/software/firmware/oracle_same54n19a/gcc/shared/devices/display/p_ssd1963.o new file mode 100644 index 00000000..928e85a7 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/devices/display/p_ssd1963.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/devices/p_screen.d b/software/firmware/oracle_same54n19a/gcc/shared/devices/p_screen.d new file mode 100644 index 00000000..6cefeb2f --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/devices/p_screen.d @@ -0,0 +1,672 @@ +shared/devices/p_screen.d shared/devices/p_screen.o: \ + ../shared/devices/p_screen.c ../shared/devices/p_screen.h \ + ../include/oracle.h ../config/pc_board.h ../hal/include/hal_gpio.h \ + ../hal/include/hpl_gpio.h ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h ../hpl/port/hpl_gpio_base.h \ + ../hal/utils/include/utils_assert.h ../config/hpl_port_config.h \ + ../config/pc_master.h ../hal/include/hal_delay.h \ + ../hal/include/hpl_irq.h ../hal/include/hpl_reset.h \ + ../hal/include/hpl_sleep.h ../hal/include/hal_init.h \ + ../hal/include/hpl_init.h ../hal/include/hal_io.h \ + ../hal/include/hal_sleep.h ../hal/include/hal_ext_irq.h \ + ../hal/include/hpl_ext_irq.h ../hal/include/hal_usart_async.h \ + ../hal/include/hal_io.h ../hal/include/hpl_usart_async.h \ + ../hal/include/hpl_usart.h ../hal/include/hpl_irq.h \ + ../hal/utils/include/utils_ringbuffer.h ../hal/utils/include/compiler.h \ + ../hal/utils/include/utils_assert.h ../hal/include/hal_i2c_m_sync.h \ + ../hal/include/hpl_i2c_m_sync.h ../hal/include/hal_timer.h \ + ../hal/utils/include/utils_list.h ../hal/include/hpl_timer.h \ + ../hpl/tc/hpl_tc_base.h ../hal/include/hpl_pwm.h \ + ../config/peripheral_clk_config.h ../hal/utils/include/utils.h \ + /usr/arm-none-eabi/include/stdio.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/types.h \ + /usr/arm-none-eabi/include/machine/endian.h \ + /usr/arm-none-eabi/include/machine/_endian.h \ + /usr/arm-none-eabi/include/sys/select.h \ + /usr/arm-none-eabi/include/sys/_sigset.h \ + /usr/arm-none-eabi/include/sys/_timeval.h \ + /usr/arm-none-eabi/include/sys/timespec.h \ + /usr/arm-none-eabi/include/sys/_timespec.h \ + /usr/arm-none-eabi/include/sys/_pthreadtypes.h \ + /usr/arm-none-eabi/include/sys/sched.h \ + /usr/arm-none-eabi/include/machine/types.h \ + /usr/arm-none-eabi/include/sys/stdio.h \ + /usr/arm-none-eabi/include/ssp/stdio.h \ + /usr/arm-none-eabi/include/ssp/ssp.h /usr/arm-none-eabi/include/stdlib.h \ + /usr/arm-none-eabi/include/machine/stdlib.h \ + /usr/arm-none-eabi/include/alloca.h \ + /usr/arm-none-eabi/include/ssp/stdlib.h \ + /usr/arm-none-eabi/include/string.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/devices/display/p_ssd1963.h ../shared/thirdparty/lvgl/lvgl.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h \ + ../config/lv_conf.h ../shared/thirdparty/lvgl/src/lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_async.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_group.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_indev.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_core/lv_group.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_refr.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_disp.h \ + ../shared/thirdparty/lvgl/src/lv_themes/lv_theme.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_themes/lv_theme_empty.h \ + ../shared/thirdparty/lvgl/src/lv_themes/lv_theme_template.h \ + ../shared/thirdparty/lvgl/src/lv_themes/lv_theme_material.h \ + ../shared/thirdparty/lvgl/src/lv_themes/lv_theme_mono.h \ + ../shared/thirdparty/lvgl/src/lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_font/lv_font_fmt_txt.h \ + ../shared/thirdparty/lvgl/src/lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_printf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_btn.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_cont.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_imgbtn.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_btn.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_page.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_cont.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_list.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_page.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_chart.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_table.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_checkbox.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_cpicker.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_bar.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_slider.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_bar.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_led.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_btnmatrix.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_keyboard.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_btnmatrix.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_dropdown.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_page.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_roller.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_textarea.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_canvas.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_win.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_tabview.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_win.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_tileview.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_msgbox.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_objmask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_cont.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_gauge.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_linemeter.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_linemeter.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_switch.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_arc.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_spinner.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_arc.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_calendar.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_spinbox.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_textarea.h \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_img_cache.h \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_api_map.h \ + ../shared/thirdparty/lvgl/src/../lvgl.h ../include/hornet.h +../shared/devices/p_screen.h: +../include/oracle.h: +../config/pc_board.h: +../hal/include/hal_gpio.h: +../hal/include/hpl_gpio.h: +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hal/include/hal_atomic.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: +../hpl/port/hpl_gpio_base.h: +../hal/utils/include/utils_assert.h: +../config/hpl_port_config.h: +../config/pc_master.h: +../hal/include/hal_delay.h: +../hal/include/hpl_irq.h: +../hal/include/hpl_reset.h: +../hal/include/hpl_sleep.h: +../hal/include/hal_init.h: +../hal/include/hpl_init.h: +../hal/include/hal_io.h: +../hal/include/hal_sleep.h: +../hal/include/hal_ext_irq.h: +../hal/include/hpl_ext_irq.h: +../hal/include/hal_usart_async.h: +../hal/include/hal_io.h: +../hal/include/hpl_usart_async.h: +../hal/include/hpl_usart.h: +../hal/include/hpl_irq.h: +../hal/utils/include/utils_ringbuffer.h: +../hal/utils/include/compiler.h: +../hal/utils/include/utils_assert.h: +../hal/include/hal_i2c_m_sync.h: +../hal/include/hpl_i2c_m_sync.h: +../hal/include/hal_timer.h: +../hal/utils/include/utils_list.h: +../hal/include/hpl_timer.h: +../hpl/tc/hpl_tc_base.h: +../hal/include/hpl_pwm.h: +../config/peripheral_clk_config.h: +../hal/utils/include/utils.h: +/usr/arm-none-eabi/include/stdio.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/types.h: +/usr/arm-none-eabi/include/machine/endian.h: +/usr/arm-none-eabi/include/machine/_endian.h: +/usr/arm-none-eabi/include/sys/select.h: +/usr/arm-none-eabi/include/sys/_sigset.h: +/usr/arm-none-eabi/include/sys/_timeval.h: +/usr/arm-none-eabi/include/sys/timespec.h: +/usr/arm-none-eabi/include/sys/_timespec.h: +/usr/arm-none-eabi/include/sys/_pthreadtypes.h: +/usr/arm-none-eabi/include/sys/sched.h: +/usr/arm-none-eabi/include/machine/types.h: +/usr/arm-none-eabi/include/sys/stdio.h: +/usr/arm-none-eabi/include/ssp/stdio.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/stdlib.h: +/usr/arm-none-eabi/include/machine/stdlib.h: +/usr/arm-none-eabi/include/alloca.h: +/usr/arm-none-eabi/include/ssp/stdlib.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/devices/display/p_ssd1963.h: +../shared/thirdparty/lvgl/lvgl.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h: +../config/lv_conf.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_async.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_core/lv_group.h: +../shared/thirdparty/lvgl/src/lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_core/lv_indev.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_core/lv_group.h: +../shared/thirdparty/lvgl/src/lv_core/lv_refr.h: +../shared/thirdparty/lvgl/src/lv_core/lv_disp.h: +../shared/thirdparty/lvgl/src/lv_themes/lv_theme.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_themes/lv_theme_empty.h: +../shared/thirdparty/lvgl/src/lv_themes/lv_theme_template.h: +../shared/thirdparty/lvgl/src/lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/src/lv_themes/lv_theme_mono.h: +../shared/thirdparty/lvgl/src/lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_font/lv_font_fmt_txt.h: +../shared/thirdparty/lvgl/src/lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_printf.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_btn.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_cont.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_indev.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_imgbtn.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_btn.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_page.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_cont.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_list.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_page.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_chart.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_table.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_checkbox.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_cpicker.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_bar.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_slider.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_bar.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_led.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_btnmatrix.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_keyboard.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_btnmatrix.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_dropdown.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_page.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_roller.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_textarea.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_canvas.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_win.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_tabview.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_win.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_tileview.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_msgbox.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_objmask.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_cont.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_gauge.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_linemeter.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_linemeter.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_switch.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_arc.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_spinner.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_arc.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_calendar.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_spinbox.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_textarea.h: +../shared/thirdparty/lvgl/src/lv_draw/lv_img_cache.h: +../shared/thirdparty/lvgl/src/lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_api_map.h: +../shared/thirdparty/lvgl/src/../lvgl.h: +../include/hornet.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/devices/p_screen.o b/software/firmware/oracle_same54n19a/gcc/shared/devices/p_screen.o new file mode 100644 index 00000000..bce96ecb Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/devices/p_screen.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/drivers/p_gpio.d b/software/firmware/oracle_same54n19a/gcc/shared/drivers/p_gpio.d new file mode 100644 index 00000000..5ea96204 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/drivers/p_gpio.d @@ -0,0 +1,363 @@ +shared/drivers/p_gpio.d shared/drivers/p_gpio.o: \ + ../shared/drivers/p_gpio.c ../shared/drivers/p_gpio.h \ + ../include/oracle.h ../config/pc_board.h ../hal/include/hal_gpio.h \ + ../hal/include/hpl_gpio.h ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h ../hpl/port/hpl_gpio_base.h \ + ../hal/utils/include/utils_assert.h ../config/hpl_port_config.h \ + ../config/pc_master.h ../hal/include/hal_delay.h \ + ../hal/include/hpl_irq.h ../hal/include/hpl_reset.h \ + ../hal/include/hpl_sleep.h ../hal/include/hal_init.h \ + ../hal/include/hpl_init.h ../hal/include/hal_io.h \ + ../hal/include/hal_sleep.h ../hal/include/hal_ext_irq.h \ + ../hal/include/hpl_ext_irq.h ../hal/include/hal_usart_async.h \ + ../hal/include/hal_io.h ../hal/include/hpl_usart_async.h \ + ../hal/include/hpl_usart.h ../hal/include/hpl_irq.h \ + ../hal/utils/include/utils_ringbuffer.h ../hal/utils/include/compiler.h \ + ../hal/utils/include/utils_assert.h ../hal/include/hal_i2c_m_sync.h \ + ../hal/include/hpl_i2c_m_sync.h ../hal/include/hal_timer.h \ + ../hal/utils/include/utils_list.h ../hal/include/hpl_timer.h \ + ../hpl/tc/hpl_tc_base.h ../hal/include/hpl_pwm.h \ + ../config/peripheral_clk_config.h ../hal/utils/include/utils.h \ + /usr/arm-none-eabi/include/stdio.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/types.h \ + /usr/arm-none-eabi/include/machine/endian.h \ + /usr/arm-none-eabi/include/machine/_endian.h \ + /usr/arm-none-eabi/include/sys/select.h \ + /usr/arm-none-eabi/include/sys/_sigset.h \ + /usr/arm-none-eabi/include/sys/_timeval.h \ + /usr/arm-none-eabi/include/sys/timespec.h \ + /usr/arm-none-eabi/include/sys/_timespec.h \ + /usr/arm-none-eabi/include/sys/_pthreadtypes.h \ + /usr/arm-none-eabi/include/sys/sched.h \ + /usr/arm-none-eabi/include/machine/types.h \ + /usr/arm-none-eabi/include/sys/stdio.h \ + /usr/arm-none-eabi/include/ssp/stdio.h \ + /usr/arm-none-eabi/include/ssp/ssp.h /usr/arm-none-eabi/include/stdlib.h \ + /usr/arm-none-eabi/include/machine/stdlib.h \ + /usr/arm-none-eabi/include/alloca.h \ + /usr/arm-none-eabi/include/ssp/stdlib.h \ + /usr/arm-none-eabi/include/string.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h +../shared/drivers/p_gpio.h: +../include/oracle.h: +../config/pc_board.h: +../hal/include/hal_gpio.h: +../hal/include/hpl_gpio.h: +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hal/include/hal_atomic.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: +../hpl/port/hpl_gpio_base.h: +../hal/utils/include/utils_assert.h: +../config/hpl_port_config.h: +../config/pc_master.h: +../hal/include/hal_delay.h: +../hal/include/hpl_irq.h: +../hal/include/hpl_reset.h: +../hal/include/hpl_sleep.h: +../hal/include/hal_init.h: +../hal/include/hpl_init.h: +../hal/include/hal_io.h: +../hal/include/hal_sleep.h: +../hal/include/hal_ext_irq.h: +../hal/include/hpl_ext_irq.h: +../hal/include/hal_usart_async.h: +../hal/include/hal_io.h: +../hal/include/hpl_usart_async.h: +../hal/include/hpl_usart.h: +../hal/include/hpl_irq.h: +../hal/utils/include/utils_ringbuffer.h: +../hal/utils/include/compiler.h: +../hal/utils/include/utils_assert.h: +../hal/include/hal_i2c_m_sync.h: +../hal/include/hpl_i2c_m_sync.h: +../hal/include/hal_timer.h: +../hal/utils/include/utils_list.h: +../hal/include/hpl_timer.h: +../hpl/tc/hpl_tc_base.h: +../hal/include/hpl_pwm.h: +../config/peripheral_clk_config.h: +../hal/utils/include/utils.h: +/usr/arm-none-eabi/include/stdio.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/types.h: +/usr/arm-none-eabi/include/machine/endian.h: +/usr/arm-none-eabi/include/machine/_endian.h: +/usr/arm-none-eabi/include/sys/select.h: +/usr/arm-none-eabi/include/sys/_sigset.h: +/usr/arm-none-eabi/include/sys/_timeval.h: +/usr/arm-none-eabi/include/sys/timespec.h: +/usr/arm-none-eabi/include/sys/_timespec.h: +/usr/arm-none-eabi/include/sys/_pthreadtypes.h: +/usr/arm-none-eabi/include/sys/sched.h: +/usr/arm-none-eabi/include/machine/types.h: +/usr/arm-none-eabi/include/sys/stdio.h: +/usr/arm-none-eabi/include/ssp/stdio.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/stdlib.h: +/usr/arm-none-eabi/include/machine/stdlib.h: +/usr/arm-none-eabi/include/alloca.h: +/usr/arm-none-eabi/include/ssp/stdlib.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/drivers/p_gpio.o b/software/firmware/oracle_same54n19a/gcc/shared/drivers/p_gpio.o new file mode 100644 index 00000000..93afb17d Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/drivers/p_gpio.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/drivers/p_i2c.d b/software/firmware/oracle_same54n19a/gcc/shared/drivers/p_i2c.d new file mode 100644 index 00000000..ae811dc5 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/drivers/p_i2c.d @@ -0,0 +1,363 @@ +shared/drivers/p_i2c.d shared/drivers/p_i2c.o: ../shared/drivers/p_i2c.c \ + ../shared/drivers/p_i2c.h ../include/oracle.h ../config/pc_board.h \ + ../hal/include/hal_gpio.h ../hal/include/hpl_gpio.h \ + ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h ../hpl/port/hpl_gpio_base.h \ + ../hal/utils/include/utils_assert.h ../config/hpl_port_config.h \ + ../config/pc_master.h ../hal/include/hal_delay.h \ + ../hal/include/hpl_irq.h ../hal/include/hpl_reset.h \ + ../hal/include/hpl_sleep.h ../hal/include/hal_init.h \ + ../hal/include/hpl_init.h ../hal/include/hal_io.h \ + ../hal/include/hal_sleep.h ../hal/include/hal_ext_irq.h \ + ../hal/include/hpl_ext_irq.h ../hal/include/hal_usart_async.h \ + ../hal/include/hal_io.h ../hal/include/hpl_usart_async.h \ + ../hal/include/hpl_usart.h ../hal/include/hpl_irq.h \ + ../hal/utils/include/utils_ringbuffer.h ../hal/utils/include/compiler.h \ + ../hal/utils/include/utils_assert.h ../hal/include/hal_i2c_m_sync.h \ + ../hal/include/hpl_i2c_m_sync.h ../hal/include/hal_timer.h \ + ../hal/utils/include/utils_list.h ../hal/include/hpl_timer.h \ + ../hpl/tc/hpl_tc_base.h ../hal/include/hpl_pwm.h \ + ../config/peripheral_clk_config.h ../hal/utils/include/utils.h \ + /usr/arm-none-eabi/include/stdio.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/types.h \ + /usr/arm-none-eabi/include/machine/endian.h \ + /usr/arm-none-eabi/include/machine/_endian.h \ + /usr/arm-none-eabi/include/sys/select.h \ + /usr/arm-none-eabi/include/sys/_sigset.h \ + /usr/arm-none-eabi/include/sys/_timeval.h \ + /usr/arm-none-eabi/include/sys/timespec.h \ + /usr/arm-none-eabi/include/sys/_timespec.h \ + /usr/arm-none-eabi/include/sys/_pthreadtypes.h \ + /usr/arm-none-eabi/include/sys/sched.h \ + /usr/arm-none-eabi/include/machine/types.h \ + /usr/arm-none-eabi/include/sys/stdio.h \ + /usr/arm-none-eabi/include/ssp/stdio.h \ + /usr/arm-none-eabi/include/ssp/ssp.h /usr/arm-none-eabi/include/stdlib.h \ + /usr/arm-none-eabi/include/machine/stdlib.h \ + /usr/arm-none-eabi/include/alloca.h \ + /usr/arm-none-eabi/include/ssp/stdlib.h \ + /usr/arm-none-eabi/include/string.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h +../shared/drivers/p_i2c.h: +../include/oracle.h: +../config/pc_board.h: +../hal/include/hal_gpio.h: +../hal/include/hpl_gpio.h: +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hal/include/hal_atomic.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: +../hpl/port/hpl_gpio_base.h: +../hal/utils/include/utils_assert.h: +../config/hpl_port_config.h: +../config/pc_master.h: +../hal/include/hal_delay.h: +../hal/include/hpl_irq.h: +../hal/include/hpl_reset.h: +../hal/include/hpl_sleep.h: +../hal/include/hal_init.h: +../hal/include/hpl_init.h: +../hal/include/hal_io.h: +../hal/include/hal_sleep.h: +../hal/include/hal_ext_irq.h: +../hal/include/hpl_ext_irq.h: +../hal/include/hal_usart_async.h: +../hal/include/hal_io.h: +../hal/include/hpl_usart_async.h: +../hal/include/hpl_usart.h: +../hal/include/hpl_irq.h: +../hal/utils/include/utils_ringbuffer.h: +../hal/utils/include/compiler.h: +../hal/utils/include/utils_assert.h: +../hal/include/hal_i2c_m_sync.h: +../hal/include/hpl_i2c_m_sync.h: +../hal/include/hal_timer.h: +../hal/utils/include/utils_list.h: +../hal/include/hpl_timer.h: +../hpl/tc/hpl_tc_base.h: +../hal/include/hpl_pwm.h: +../config/peripheral_clk_config.h: +../hal/utils/include/utils.h: +/usr/arm-none-eabi/include/stdio.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/types.h: +/usr/arm-none-eabi/include/machine/endian.h: +/usr/arm-none-eabi/include/machine/_endian.h: +/usr/arm-none-eabi/include/sys/select.h: +/usr/arm-none-eabi/include/sys/_sigset.h: +/usr/arm-none-eabi/include/sys/_timeval.h: +/usr/arm-none-eabi/include/sys/timespec.h: +/usr/arm-none-eabi/include/sys/_timespec.h: +/usr/arm-none-eabi/include/sys/_pthreadtypes.h: +/usr/arm-none-eabi/include/sys/sched.h: +/usr/arm-none-eabi/include/machine/types.h: +/usr/arm-none-eabi/include/sys/stdio.h: +/usr/arm-none-eabi/include/ssp/stdio.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/stdlib.h: +/usr/arm-none-eabi/include/machine/stdlib.h: +/usr/arm-none-eabi/include/alloca.h: +/usr/arm-none-eabi/include/ssp/stdlib.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/drivers/p_i2c.o b/software/firmware/oracle_same54n19a/gcc/shared/drivers/p_i2c.o new file mode 100644 index 00000000..dd829c42 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/drivers/p_i2c.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/drivers/p_tcc.d b/software/firmware/oracle_same54n19a/gcc/shared/drivers/p_tcc.d new file mode 100644 index 00000000..64b359c0 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/drivers/p_tcc.d @@ -0,0 +1,669 @@ +shared/drivers/p_tcc.d shared/drivers/p_tcc.o: ../shared/drivers/p_tcc.c \ + ../shared/drivers/p_tcc.h ../include/oracle.h ../config/pc_board.h \ + ../hal/include/hal_gpio.h ../hal/include/hpl_gpio.h \ + ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h ../hpl/port/hpl_gpio_base.h \ + ../hal/utils/include/utils_assert.h ../config/hpl_port_config.h \ + ../config/pc_master.h ../hal/include/hal_delay.h \ + ../hal/include/hpl_irq.h ../hal/include/hpl_reset.h \ + ../hal/include/hpl_sleep.h ../hal/include/hal_init.h \ + ../hal/include/hpl_init.h ../hal/include/hal_io.h \ + ../hal/include/hal_sleep.h ../hal/include/hal_ext_irq.h \ + ../hal/include/hpl_ext_irq.h ../hal/include/hal_usart_async.h \ + ../hal/include/hal_io.h ../hal/include/hpl_usart_async.h \ + ../hal/include/hpl_usart.h ../hal/include/hpl_irq.h \ + ../hal/utils/include/utils_ringbuffer.h ../hal/utils/include/compiler.h \ + ../hal/utils/include/utils_assert.h ../hal/include/hal_i2c_m_sync.h \ + ../hal/include/hpl_i2c_m_sync.h ../hal/include/hal_timer.h \ + ../hal/utils/include/utils_list.h ../hal/include/hpl_timer.h \ + ../hpl/tc/hpl_tc_base.h ../hal/include/hpl_pwm.h \ + ../config/peripheral_clk_config.h ../hal/utils/include/utils.h \ + /usr/arm-none-eabi/include/stdio.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/types.h \ + /usr/arm-none-eabi/include/machine/endian.h \ + /usr/arm-none-eabi/include/machine/_endian.h \ + /usr/arm-none-eabi/include/sys/select.h \ + /usr/arm-none-eabi/include/sys/_sigset.h \ + /usr/arm-none-eabi/include/sys/_timeval.h \ + /usr/arm-none-eabi/include/sys/timespec.h \ + /usr/arm-none-eabi/include/sys/_timespec.h \ + /usr/arm-none-eabi/include/sys/_pthreadtypes.h \ + /usr/arm-none-eabi/include/sys/sched.h \ + /usr/arm-none-eabi/include/machine/types.h \ + /usr/arm-none-eabi/include/sys/stdio.h \ + /usr/arm-none-eabi/include/ssp/stdio.h \ + /usr/arm-none-eabi/include/ssp/ssp.h /usr/arm-none-eabi/include/stdlib.h \ + /usr/arm-none-eabi/include/machine/stdlib.h \ + /usr/arm-none-eabi/include/alloca.h \ + /usr/arm-none-eabi/include/ssp/stdlib.h \ + /usr/arm-none-eabi/include/string.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h ../shared/thirdparty/lvgl/lvgl.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h \ + ../config/lv_conf.h ../shared/thirdparty/lvgl/src/lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_async.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_group.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_indev.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_core/lv_group.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_refr.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_disp.h \ + ../shared/thirdparty/lvgl/src/lv_themes/lv_theme.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_themes/lv_theme_empty.h \ + ../shared/thirdparty/lvgl/src/lv_themes/lv_theme_template.h \ + ../shared/thirdparty/lvgl/src/lv_themes/lv_theme_material.h \ + ../shared/thirdparty/lvgl/src/lv_themes/lv_theme_mono.h \ + ../shared/thirdparty/lvgl/src/lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_font/lv_font_fmt_txt.h \ + ../shared/thirdparty/lvgl/src/lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_printf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_btn.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_cont.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_imgbtn.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_btn.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_page.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_cont.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_list.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_page.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_chart.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_table.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_checkbox.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_cpicker.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_bar.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_slider.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_bar.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_led.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_btnmatrix.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_keyboard.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_btnmatrix.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_dropdown.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_page.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_roller.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_textarea.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_canvas.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_win.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_tabview.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_win.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_tileview.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_msgbox.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_objmask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_cont.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_gauge.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_linemeter.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_linemeter.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_switch.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_arc.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_spinner.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_arc.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_calendar.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_spinbox.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_textarea.h \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_img_cache.h \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_api_map.h \ + ../shared/thirdparty/lvgl/src/../lvgl.h +../shared/drivers/p_tcc.h: +../include/oracle.h: +../config/pc_board.h: +../hal/include/hal_gpio.h: +../hal/include/hpl_gpio.h: +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hal/include/hal_atomic.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: +../hpl/port/hpl_gpio_base.h: +../hal/utils/include/utils_assert.h: +../config/hpl_port_config.h: +../config/pc_master.h: +../hal/include/hal_delay.h: +../hal/include/hpl_irq.h: +../hal/include/hpl_reset.h: +../hal/include/hpl_sleep.h: +../hal/include/hal_init.h: +../hal/include/hpl_init.h: +../hal/include/hal_io.h: +../hal/include/hal_sleep.h: +../hal/include/hal_ext_irq.h: +../hal/include/hpl_ext_irq.h: +../hal/include/hal_usart_async.h: +../hal/include/hal_io.h: +../hal/include/hpl_usart_async.h: +../hal/include/hpl_usart.h: +../hal/include/hpl_irq.h: +../hal/utils/include/utils_ringbuffer.h: +../hal/utils/include/compiler.h: +../hal/utils/include/utils_assert.h: +../hal/include/hal_i2c_m_sync.h: +../hal/include/hpl_i2c_m_sync.h: +../hal/include/hal_timer.h: +../hal/utils/include/utils_list.h: +../hal/include/hpl_timer.h: +../hpl/tc/hpl_tc_base.h: +../hal/include/hpl_pwm.h: +../config/peripheral_clk_config.h: +../hal/utils/include/utils.h: +/usr/arm-none-eabi/include/stdio.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/types.h: +/usr/arm-none-eabi/include/machine/endian.h: +/usr/arm-none-eabi/include/machine/_endian.h: +/usr/arm-none-eabi/include/sys/select.h: +/usr/arm-none-eabi/include/sys/_sigset.h: +/usr/arm-none-eabi/include/sys/_timeval.h: +/usr/arm-none-eabi/include/sys/timespec.h: +/usr/arm-none-eabi/include/sys/_timespec.h: +/usr/arm-none-eabi/include/sys/_pthreadtypes.h: +/usr/arm-none-eabi/include/sys/sched.h: +/usr/arm-none-eabi/include/machine/types.h: +/usr/arm-none-eabi/include/sys/stdio.h: +/usr/arm-none-eabi/include/ssp/stdio.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/stdlib.h: +/usr/arm-none-eabi/include/machine/stdlib.h: +/usr/arm-none-eabi/include/alloca.h: +/usr/arm-none-eabi/include/ssp/stdlib.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/lvgl.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h: +../config/lv_conf.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_async.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_core/lv_group.h: +../shared/thirdparty/lvgl/src/lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_core/lv_indev.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_core/lv_group.h: +../shared/thirdparty/lvgl/src/lv_core/lv_refr.h: +../shared/thirdparty/lvgl/src/lv_core/lv_disp.h: +../shared/thirdparty/lvgl/src/lv_themes/lv_theme.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_themes/lv_theme_empty.h: +../shared/thirdparty/lvgl/src/lv_themes/lv_theme_template.h: +../shared/thirdparty/lvgl/src/lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/src/lv_themes/lv_theme_mono.h: +../shared/thirdparty/lvgl/src/lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_font/lv_font_fmt_txt.h: +../shared/thirdparty/lvgl/src/lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_printf.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_btn.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_cont.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_indev.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_imgbtn.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_btn.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_page.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_cont.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_list.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_page.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_chart.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_table.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_checkbox.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_cpicker.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_bar.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_slider.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_bar.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_led.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_btnmatrix.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_keyboard.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_btnmatrix.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_dropdown.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_page.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_roller.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_textarea.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_canvas.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_win.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_tabview.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_win.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_tileview.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_msgbox.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_objmask.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_cont.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_gauge.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_linemeter.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_linemeter.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_switch.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_arc.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_spinner.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_arc.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_calendar.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_spinbox.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_textarea.h: +../shared/thirdparty/lvgl/src/lv_draw/lv_img_cache.h: +../shared/thirdparty/lvgl/src/lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_api_map.h: +../shared/thirdparty/lvgl/src/../lvgl.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/drivers/p_tcc.o b/software/firmware/oracle_same54n19a/gcc/shared/drivers/p_tcc.o new file mode 100644 index 00000000..ef1be770 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/drivers/p_tcc.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/drivers/p_usart.d b/software/firmware/oracle_same54n19a/gcc/shared/drivers/p_usart.d new file mode 100644 index 00000000..535ff330 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/drivers/p_usart.d @@ -0,0 +1,363 @@ +shared/drivers/p_usart.d shared/drivers/p_usart.o: \ + ../shared/drivers/p_usart.c ../shared/drivers/p_usart.h \ + ../include/oracle.h ../config/pc_board.h ../hal/include/hal_gpio.h \ + ../hal/include/hpl_gpio.h ../hal/utils/include/compiler.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../hal/utils/include/parts.h ../include/same54.h ../include/same54n19a.h \ + ../CMSIS/Core/Include/core_cm4.h ../CMSIS/Core/Include/cmsis_version.h \ + ../CMSIS/Core/Include/cmsis_compiler.h ../CMSIS/Core/Include/cmsis_gcc.h \ + ../CMSIS/Core/Include/mpu_armv7.h ../include/system_same54.h \ + ../include/component/ac.h ../include/component/adc.h \ + ../include/component/aes.h ../include/component/can.h \ + ../include/component/ccl.h ../include/component/cmcc.h \ + ../include/component/dac.h ../include/component/dmac.h \ + ../include/component/dsu.h ../include/component/eic.h \ + ../include/component/evsys.h ../include/component/freqm.h \ + ../include/component/gclk.h ../include/component/gmac.h \ + ../include/component/hmatrixb.h ../include/component/icm.h \ + ../include/component/i2s.h ../include/component/mclk.h \ + ../include/component/nvmctrl.h ../include/component/oscctrl.h \ + ../include/component/osc32kctrl.h ../include/component/pac.h \ + ../include/component/pcc.h ../include/component/pdec.h \ + ../include/component/pm.h ../include/component/port.h \ + ../include/component/qspi.h ../include/component/ramecc.h \ + ../include/component/rstc.h ../include/component/rtc.h \ + ../include/component/sdhc.h ../include/component/sercom.h \ + ../include/component/supc.h ../include/component/tc.h \ + ../include/component/tcc.h ../include/component/trng.h \ + ../include/component/usb.h ../include/component/wdt.h \ + ../include/instance/ac.h ../include/instance/adc0.h \ + ../include/instance/adc1.h ../include/instance/aes.h \ + ../include/instance/can0.h ../include/instance/can1.h \ + ../include/instance/ccl.h ../include/instance/cmcc.h \ + ../include/instance/dac.h ../include/instance/dmac.h \ + ../include/instance/dsu.h ../include/instance/eic.h \ + ../include/instance/evsys.h ../include/instance/freqm.h \ + ../include/instance/gclk.h ../include/instance/gmac.h \ + ../include/instance/hmatrix.h ../include/instance/icm.h \ + ../include/instance/i2s.h ../include/instance/mclk.h \ + ../include/instance/nvmctrl.h ../include/instance/oscctrl.h \ + ../include/instance/osc32kctrl.h ../include/instance/pac.h \ + ../include/instance/pcc.h ../include/instance/pdec.h \ + ../include/instance/pm.h ../include/instance/port.h \ + ../include/instance/pukcc.h ../include/instance/qspi.h \ + ../include/instance/ramecc.h ../include/instance/rstc.h \ + ../include/instance/rtc.h ../include/instance/sdhc0.h \ + ../include/instance/sdhc1.h ../include/instance/sercom0.h \ + ../include/instance/sercom1.h ../include/instance/sercom2.h \ + ../include/instance/sercom3.h ../include/instance/sercom4.h \ + ../include/instance/sercom5.h ../include/instance/sercom6.h \ + ../include/instance/sercom7.h ../include/instance/supc.h \ + ../include/instance/tc0.h ../include/instance/tc1.h \ + ../include/instance/tc2.h ../include/instance/tc3.h \ + ../include/instance/tc4.h ../include/instance/tc5.h \ + ../include/instance/tc6.h ../include/instance/tc7.h \ + ../include/instance/tcc0.h ../include/instance/tcc1.h \ + ../include/instance/tcc2.h ../include/instance/tcc3.h \ + ../include/instance/tcc4.h ../include/instance/trng.h \ + ../include/instance/usb.h ../include/instance/wdt.h \ + ../include/pio/same54n19a.h ../hri/hri_e54.h ../include/sam.h \ + ../hri/hri_ac_e54.h ../hal/include/hal_atomic.h ../hri/hri_adc_e54.h \ + ../hri/hri_aes_e54.h ../hri/hri_can_e54.h ../hri/hri_ccl_e54.h \ + ../hri/hri_cmcc_e54.h ../hri/hri_dac_e54.h ../hri/hri_dmac_e54.h \ + ../hri/hri_dsu_e54.h ../hri/hri_eic_e54.h ../hri/hri_evsys_e54.h \ + ../hri/hri_freqm_e54.h ../hri/hri_gclk_e54.h ../hri/hri_gmac_e54.h \ + ../hri/hri_hmatrixb_e54.h ../hri/hri_i2s_e54.h ../hri/hri_icm_e54.h \ + ../hri/hri_mclk_e54.h ../hri/hri_nvmctrl_e54.h \ + ../hri/hri_osc32kctrl_e54.h ../hri/hri_oscctrl_e54.h \ + ../hri/hri_pac_e54.h ../hri/hri_pcc_e54.h ../hri/hri_pdec_e54.h \ + ../hri/hri_pm_e54.h ../hri/hri_port_e54.h ../hri/hri_qspi_e54.h \ + ../hri/hri_ramecc_e54.h ../hri/hri_rstc_e54.h ../hri/hri_rtc_e54.h \ + ../hri/hri_sdhc_e54.h ../hri/hri_sercom_e54.h ../hri/hri_supc_e54.h \ + ../hri/hri_tc_e54.h ../hri/hri_tcc_e54.h ../hri/hri_trng_e54.h \ + ../hri/hri_usb_e54.h ../hri/hri_wdt_e54.h \ + ../hal/utils/include/err_codes.h ../hpl/port/hpl_gpio_base.h \ + ../hal/utils/include/utils_assert.h ../config/hpl_port_config.h \ + ../config/pc_master.h ../hal/include/hal_delay.h \ + ../hal/include/hpl_irq.h ../hal/include/hpl_reset.h \ + ../hal/include/hpl_sleep.h ../hal/include/hal_init.h \ + ../hal/include/hpl_init.h ../hal/include/hal_io.h \ + ../hal/include/hal_sleep.h ../hal/include/hal_ext_irq.h \ + ../hal/include/hpl_ext_irq.h ../hal/include/hal_usart_async.h \ + ../hal/include/hal_io.h ../hal/include/hpl_usart_async.h \ + ../hal/include/hpl_usart.h ../hal/include/hpl_irq.h \ + ../hal/utils/include/utils_ringbuffer.h ../hal/utils/include/compiler.h \ + ../hal/utils/include/utils_assert.h ../hal/include/hal_i2c_m_sync.h \ + ../hal/include/hpl_i2c_m_sync.h ../hal/include/hal_timer.h \ + ../hal/utils/include/utils_list.h ../hal/include/hpl_timer.h \ + ../hpl/tc/hpl_tc_base.h ../hal/include/hpl_pwm.h \ + ../config/peripheral_clk_config.h ../hal/utils/include/utils.h \ + /usr/arm-none-eabi/include/stdio.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/types.h \ + /usr/arm-none-eabi/include/machine/endian.h \ + /usr/arm-none-eabi/include/machine/_endian.h \ + /usr/arm-none-eabi/include/sys/select.h \ + /usr/arm-none-eabi/include/sys/_sigset.h \ + /usr/arm-none-eabi/include/sys/_timeval.h \ + /usr/arm-none-eabi/include/sys/timespec.h \ + /usr/arm-none-eabi/include/sys/_timespec.h \ + /usr/arm-none-eabi/include/sys/_pthreadtypes.h \ + /usr/arm-none-eabi/include/sys/sched.h \ + /usr/arm-none-eabi/include/machine/types.h \ + /usr/arm-none-eabi/include/sys/stdio.h \ + /usr/arm-none-eabi/include/ssp/stdio.h \ + /usr/arm-none-eabi/include/ssp/ssp.h /usr/arm-none-eabi/include/stdlib.h \ + /usr/arm-none-eabi/include/machine/stdlib.h \ + /usr/arm-none-eabi/include/alloca.h \ + /usr/arm-none-eabi/include/ssp/stdlib.h \ + /usr/arm-none-eabi/include/string.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h +../shared/drivers/p_usart.h: +../include/oracle.h: +../config/pc_board.h: +../hal/include/hal_gpio.h: +../hal/include/hpl_gpio.h: +../hal/utils/include/compiler.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../hal/utils/include/parts.h: +../include/same54.h: +../include/same54n19a.h: +../CMSIS/Core/Include/core_cm4.h: +../CMSIS/Core/Include/cmsis_version.h: +../CMSIS/Core/Include/cmsis_compiler.h: +../CMSIS/Core/Include/cmsis_gcc.h: +../CMSIS/Core/Include/mpu_armv7.h: +../include/system_same54.h: +../include/component/ac.h: +../include/component/adc.h: +../include/component/aes.h: +../include/component/can.h: +../include/component/ccl.h: +../include/component/cmcc.h: +../include/component/dac.h: +../include/component/dmac.h: +../include/component/dsu.h: +../include/component/eic.h: +../include/component/evsys.h: +../include/component/freqm.h: +../include/component/gclk.h: +../include/component/gmac.h: +../include/component/hmatrixb.h: +../include/component/icm.h: +../include/component/i2s.h: +../include/component/mclk.h: +../include/component/nvmctrl.h: +../include/component/oscctrl.h: +../include/component/osc32kctrl.h: +../include/component/pac.h: +../include/component/pcc.h: +../include/component/pdec.h: +../include/component/pm.h: +../include/component/port.h: +../include/component/qspi.h: +../include/component/ramecc.h: +../include/component/rstc.h: +../include/component/rtc.h: +../include/component/sdhc.h: +../include/component/sercom.h: +../include/component/supc.h: +../include/component/tc.h: +../include/component/tcc.h: +../include/component/trng.h: +../include/component/usb.h: +../include/component/wdt.h: +../include/instance/ac.h: +../include/instance/adc0.h: +../include/instance/adc1.h: +../include/instance/aes.h: +../include/instance/can0.h: +../include/instance/can1.h: +../include/instance/ccl.h: +../include/instance/cmcc.h: +../include/instance/dac.h: +../include/instance/dmac.h: +../include/instance/dsu.h: +../include/instance/eic.h: +../include/instance/evsys.h: +../include/instance/freqm.h: +../include/instance/gclk.h: +../include/instance/gmac.h: +../include/instance/hmatrix.h: +../include/instance/icm.h: +../include/instance/i2s.h: +../include/instance/mclk.h: +../include/instance/nvmctrl.h: +../include/instance/oscctrl.h: +../include/instance/osc32kctrl.h: +../include/instance/pac.h: +../include/instance/pcc.h: +../include/instance/pdec.h: +../include/instance/pm.h: +../include/instance/port.h: +../include/instance/pukcc.h: +../include/instance/qspi.h: +../include/instance/ramecc.h: +../include/instance/rstc.h: +../include/instance/rtc.h: +../include/instance/sdhc0.h: +../include/instance/sdhc1.h: +../include/instance/sercom0.h: +../include/instance/sercom1.h: +../include/instance/sercom2.h: +../include/instance/sercom3.h: +../include/instance/sercom4.h: +../include/instance/sercom5.h: +../include/instance/sercom6.h: +../include/instance/sercom7.h: +../include/instance/supc.h: +../include/instance/tc0.h: +../include/instance/tc1.h: +../include/instance/tc2.h: +../include/instance/tc3.h: +../include/instance/tc4.h: +../include/instance/tc5.h: +../include/instance/tc6.h: +../include/instance/tc7.h: +../include/instance/tcc0.h: +../include/instance/tcc1.h: +../include/instance/tcc2.h: +../include/instance/tcc3.h: +../include/instance/tcc4.h: +../include/instance/trng.h: +../include/instance/usb.h: +../include/instance/wdt.h: +../include/pio/same54n19a.h: +../hri/hri_e54.h: +../include/sam.h: +../hri/hri_ac_e54.h: +../hal/include/hal_atomic.h: +../hri/hri_adc_e54.h: +../hri/hri_aes_e54.h: +../hri/hri_can_e54.h: +../hri/hri_ccl_e54.h: +../hri/hri_cmcc_e54.h: +../hri/hri_dac_e54.h: +../hri/hri_dmac_e54.h: +../hri/hri_dsu_e54.h: +../hri/hri_eic_e54.h: +../hri/hri_evsys_e54.h: +../hri/hri_freqm_e54.h: +../hri/hri_gclk_e54.h: +../hri/hri_gmac_e54.h: +../hri/hri_hmatrixb_e54.h: +../hri/hri_i2s_e54.h: +../hri/hri_icm_e54.h: +../hri/hri_mclk_e54.h: +../hri/hri_nvmctrl_e54.h: +../hri/hri_osc32kctrl_e54.h: +../hri/hri_oscctrl_e54.h: +../hri/hri_pac_e54.h: +../hri/hri_pcc_e54.h: +../hri/hri_pdec_e54.h: +../hri/hri_pm_e54.h: +../hri/hri_port_e54.h: +../hri/hri_qspi_e54.h: +../hri/hri_ramecc_e54.h: +../hri/hri_rstc_e54.h: +../hri/hri_rtc_e54.h: +../hri/hri_sdhc_e54.h: +../hri/hri_sercom_e54.h: +../hri/hri_supc_e54.h: +../hri/hri_tc_e54.h: +../hri/hri_tcc_e54.h: +../hri/hri_trng_e54.h: +../hri/hri_usb_e54.h: +../hri/hri_wdt_e54.h: +../hal/utils/include/err_codes.h: +../hpl/port/hpl_gpio_base.h: +../hal/utils/include/utils_assert.h: +../config/hpl_port_config.h: +../config/pc_master.h: +../hal/include/hal_delay.h: +../hal/include/hpl_irq.h: +../hal/include/hpl_reset.h: +../hal/include/hpl_sleep.h: +../hal/include/hal_init.h: +../hal/include/hpl_init.h: +../hal/include/hal_io.h: +../hal/include/hal_sleep.h: +../hal/include/hal_ext_irq.h: +../hal/include/hpl_ext_irq.h: +../hal/include/hal_usart_async.h: +../hal/include/hal_io.h: +../hal/include/hpl_usart_async.h: +../hal/include/hpl_usart.h: +../hal/include/hpl_irq.h: +../hal/utils/include/utils_ringbuffer.h: +../hal/utils/include/compiler.h: +../hal/utils/include/utils_assert.h: +../hal/include/hal_i2c_m_sync.h: +../hal/include/hpl_i2c_m_sync.h: +../hal/include/hal_timer.h: +../hal/utils/include/utils_list.h: +../hal/include/hpl_timer.h: +../hpl/tc/hpl_tc_base.h: +../hal/include/hpl_pwm.h: +../config/peripheral_clk_config.h: +../hal/utils/include/utils.h: +/usr/arm-none-eabi/include/stdio.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/types.h: +/usr/arm-none-eabi/include/machine/endian.h: +/usr/arm-none-eabi/include/machine/_endian.h: +/usr/arm-none-eabi/include/sys/select.h: +/usr/arm-none-eabi/include/sys/_sigset.h: +/usr/arm-none-eabi/include/sys/_timeval.h: +/usr/arm-none-eabi/include/sys/timespec.h: +/usr/arm-none-eabi/include/sys/_timespec.h: +/usr/arm-none-eabi/include/sys/_pthreadtypes.h: +/usr/arm-none-eabi/include/sys/sched.h: +/usr/arm-none-eabi/include/machine/types.h: +/usr/arm-none-eabi/include/sys/stdio.h: +/usr/arm-none-eabi/include/ssp/stdio.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/stdlib.h: +/usr/arm-none-eabi/include/machine/stdlib.h: +/usr/arm-none-eabi/include/alloca.h: +/usr/arm-none-eabi/include/ssp/stdlib.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/drivers/p_usart.o b/software/firmware/oracle_same54n19a/gcc/shared/drivers/p_usart.o new file mode 100644 index 00000000..2fc7963e Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/drivers/p_usart.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/porting/lv_port_disp_template.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/porting/lv_port_disp_template.d new file mode 100644 index 00000000..1f917492 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/porting/lv_port_disp_template.d @@ -0,0 +1,3 @@ +shared/thirdparty/lvgl/porting/lv_port_disp_template.d \ + shared/thirdparty/lvgl/porting/lv_port_disp_template.o: \ + ../shared/thirdparty/lvgl/porting/lv_port_disp_template.c diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/porting/lv_port_disp_template.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/porting/lv_port_disp_template.o new file mode 100644 index 00000000..4ecf5406 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/porting/lv_port_disp_template.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/porting/lv_port_fs_template.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/porting/lv_port_fs_template.d new file mode 100644 index 00000000..3abe43be --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/porting/lv_port_fs_template.d @@ -0,0 +1,3 @@ +shared/thirdparty/lvgl/porting/lv_port_fs_template.d \ + shared/thirdparty/lvgl/porting/lv_port_fs_template.o: \ + ../shared/thirdparty/lvgl/porting/lv_port_fs_template.c diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/porting/lv_port_fs_template.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/porting/lv_port_fs_template.o new file mode 100644 index 00000000..3f031686 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/porting/lv_port_fs_template.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/porting/lv_port_indev_template.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/porting/lv_port_indev_template.d new file mode 100644 index 00000000..ca8b64c5 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/porting/lv_port_indev_template.d @@ -0,0 +1,3 @@ +shared/thirdparty/lvgl/porting/lv_port_indev_template.d \ + shared/thirdparty/lvgl/porting/lv_port_indev_template.o: \ + ../shared/thirdparty/lvgl/porting/lv_port_indev_template.c diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/porting/lv_port_indev_template.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/porting/lv_port_indev_template.o new file mode 100644 index 00000000..89e25bcb Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/porting/lv_port_indev_template.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_debug.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_debug.d new file mode 100644 index 00000000..2a0ed529 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_debug.d @@ -0,0 +1,161 @@ +shared/thirdparty/lvgl/src/lv_core/lv_debug.d \ + shared/thirdparty/lvgl/src/lv_core/lv_debug.o: \ + ../shared/thirdparty/lvgl/src/lv_core/lv_debug.c \ + ../shared/thirdparty/lvgl/src/lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_debug.h +../shared/thirdparty/lvgl/src/lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/../lv_conf_internal.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_core/lv_debug.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_debug.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_debug.o new file mode 100644 index 00000000..24693564 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_debug.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_disp.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_disp.d new file mode 100644 index 00000000..6c77e1aa --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_disp.d @@ -0,0 +1,160 @@ +shared/thirdparty/lvgl/src/lv_core/lv_disp.d \ + shared/thirdparty/lvgl/src/lv_core/lv_disp.o: \ + ../shared/thirdparty/lvgl/src/lv_core/lv_disp.c \ + ../shared/thirdparty/lvgl/src/lv_core/lv_disp.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_disp.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_area.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_math.h +../shared/thirdparty/lvgl/src/lv_core/lv_disp.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_disp.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h: +../config/lv_conf.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_area.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_math.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_disp.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_disp.o new file mode 100644 index 00000000..fb46edf7 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_disp.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_group.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_group.d new file mode 100644 index 00000000..f7ff372b --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_group.d @@ -0,0 +1,193 @@ +shared/thirdparty/lvgl/src/lv_core/lv_group.d \ + shared/thirdparty/lvgl/src/lv_core/lv_group.o: \ + ../shared/thirdparty/lvgl/src/lv_core/lv_group.c \ + ../shared/thirdparty/lvgl/src/lv_core/lv_group.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_core/lv_debug.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_themes/lv_theme.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_themes/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_themes/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_themes/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_themes/lv_theme_empty.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_themes/lv_theme_template.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_themes/lv_theme_material.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_themes/lv_theme_mono.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_gc.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_draw/lv_img_cache.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_draw/lv_draw_mask.h +../shared/thirdparty/lvgl/src/lv_core/lv_group.h: +../shared/thirdparty/lvgl/src/lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/../lv_conf_internal.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_core/lv_debug.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_themes/lv_theme.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_themes/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_themes/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_themes/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_themes/lv_theme_empty.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_themes/lv_theme_template.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_themes/lv_theme_mono.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_gc.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_draw/lv_img_cache.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_draw/lv_draw_mask.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_group.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_group.o new file mode 100644 index 00000000..f97bc403 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_group.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_indev.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_indev.d new file mode 100644 index 00000000..2c19ad89 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_indev.d @@ -0,0 +1,177 @@ +shared/thirdparty/lvgl/src/lv_core/lv_indev.d \ + shared/thirdparty/lvgl/src/lv_core/lv_indev.o: \ + ../shared/thirdparty/lvgl/src/lv_core/lv_indev.c \ + ../shared/thirdparty/lvgl/src/lv_core/lv_indev.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_core/lv_group.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_disp.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_core/lv_refr.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_math.h +../shared/thirdparty/lvgl/src/lv_core/lv_indev.h: +../shared/thirdparty/lvgl/src/lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/../lv_conf_internal.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_core/lv_group.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_core/lv_disp.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_core/lv_refr.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_math.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_indev.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_indev.o new file mode 100644 index 00000000..06c75a6e Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_indev.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_obj.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_obj.d new file mode 100644 index 00000000..2d97f1a6 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_obj.d @@ -0,0 +1,231 @@ +shared/thirdparty/lvgl/src/lv_core/lv_obj.d \ + shared/thirdparty/lvgl/src/lv_core/lv_obj.o: \ + ../shared/thirdparty/lvgl/src/lv_core/lv_obj.c \ + ../shared/thirdparty/lvgl/src/lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_indev.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_core/lv_group.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_refr.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_group.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_disp.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_core/lv_debug.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_themes/lv_theme.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_themes/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_themes/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_themes/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_themes/lv_theme_empty.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_themes/lv_theme_template.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_themes/lv_theme_material.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_themes/lv_theme_mono.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_triangle.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_arc.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_async.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_gc.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_draw/lv_img_cache.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_log.h +../shared/thirdparty/lvgl/src/lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/../lv_conf_internal.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_core/lv_indev.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_core/lv_group.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_core/lv_refr.h: +../shared/thirdparty/lvgl/src/lv_core/lv_group.h: +../shared/thirdparty/lvgl/src/lv_core/lv_disp.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_core/lv_debug.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_themes/lv_theme.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_themes/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_themes/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_themes/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_themes/lv_theme_empty.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_themes/lv_theme_template.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_themes/lv_theme_mono.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_triangle.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_arc.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_async.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_gc.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_draw/lv_img_cache.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_log.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_obj.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_obj.o new file mode 100644 index 00000000..ec2911ba Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_obj.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_refr.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_refr.d new file mode 100644 index 00000000..f3997e1e --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_refr.d @@ -0,0 +1,205 @@ +shared/thirdparty/lvgl/src/lv_core/lv_refr.d \ + shared/thirdparty/lvgl/src/lv_core/lv_refr.o: \ + ../shared/thirdparty/lvgl/src/lv_core/lv_refr.c \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_refr.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_disp.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_gc.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_draw/lv_img_cache.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_triangle.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_arc.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_font_fmt_txt.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_font.h +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +../shared/thirdparty/lvgl/src/lv_core/lv_refr.h: +../shared/thirdparty/lvgl/src/lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/../lv_conf_internal.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_core/lv_disp.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_gc.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_draw/lv_img_cache.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_triangle.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_arc.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_font_fmt_txt.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_font.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_refr.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_refr.o new file mode 100644 index 00000000..5c6d4a48 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_refr.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_style.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_style.d new file mode 100644 index 00000000..b6d380f8 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_style.d @@ -0,0 +1,165 @@ +shared/thirdparty/lvgl/src/lv_core/lv_style.d \ + shared/thirdparty/lvgl/src/lv_core/lv_style.o: \ + ../shared/thirdparty/lvgl/src/lv_core/lv_style.c \ + ../shared/thirdparty/lvgl/src/lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_core/lv_debug.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_mem.h +../shared/thirdparty/lvgl/src/lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/../lv_conf_internal.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_font/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_core/lv_debug.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_core/../lv_misc/lv_mem.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_style.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_style.o new file mode 100644 index 00000000..44d9e723 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_core/lv_style.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_arc.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_arc.d new file mode 100644 index 00000000..39258438 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_arc.d @@ -0,0 +1,105 @@ +shared/thirdparty/lvgl/src/lv_draw/lv_draw_arc.d \ + shared/thirdparty/lvgl/src/lv_draw/lv_draw_arc.o: \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_draw_arc.c \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_draw_arc.h \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_style.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_math.h +../shared/thirdparty/lvgl/src/lv_draw/lv_draw_arc.h: +../shared/thirdparty/lvgl/src/lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_style.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_math.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_arc.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_arc.o new file mode 100644 index 00000000..f6f86936 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_arc.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_blend.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_blend.d new file mode 100644 index 00000000..8d4e8995 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_blend.d @@ -0,0 +1,177 @@ +shared/thirdparty/lvgl/src/lv_draw/lv_draw_blend.d \ + shared/thirdparty/lvgl/src/lv_draw/lv_draw_blend.o: \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_draw_blend.c \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_area.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_refr.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_gpu/lv_gpu_stm32_dma2d.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_gpu/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_gpu/../lv_misc/lv_color.h +../shared/thirdparty/lvgl/src/lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_area.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_refr.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_gpu/lv_gpu_stm32_dma2d.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_gpu/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_gpu/../lv_misc/lv_color.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_blend.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_blend.o new file mode 100644 index 00000000..b6af6d93 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_blend.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_img.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_img.d new file mode 100644 index 00000000..b8030913 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_img.d @@ -0,0 +1,183 @@ +shared/thirdparty/lvgl/src/lv_draw/lv_draw_img.d \ + shared/thirdparty/lvgl/src/lv_draw/lv_draw_img.o: \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_draw_img.c \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_img_buf.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_area.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_img_cache.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_refr.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_gpu/lv_gpu_stm32_dma2d.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_gpu/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_gpu/../lv_misc/lv_color.h +../shared/thirdparty/lvgl/src/lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +../shared/thirdparty/lvgl/src/lv_draw/lv_img_buf.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_area.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_draw/lv_img_cache.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_refr.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_gpu/lv_gpu_stm32_dma2d.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_gpu/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_gpu/../lv_misc/lv_color.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_img.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_img.o new file mode 100644 index 00000000..d2277138 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_img.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_label.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_label.d new file mode 100644 index 00000000..ebf7b55d --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_label.d @@ -0,0 +1,171 @@ +shared/thirdparty/lvgl/src/lv_draw/lv_draw_label.d \ + shared/thirdparty/lvgl/src/lv_draw/lv_draw_label.o: \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_draw_label.c \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_area.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_refr.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_debug.h +../shared/thirdparty/lvgl/src/lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_area.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_refr.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_debug.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_label.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_label.o new file mode 100644 index 00000000..a5c8886b Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_label.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_line.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_line.d new file mode 100644 index 00000000..da78c2ba --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_line.d @@ -0,0 +1,199 @@ +shared/thirdparty/lvgl/src/lv_draw/lv_draw_line.d \ + shared/thirdparty/lvgl/src/lv_draw/lv_draw_line.o: \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_draw_line.c \ + /usr/arm-none-eabi/include/stdio.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/types.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/arm-none-eabi/include/machine/endian.h \ + /usr/arm-none-eabi/include/machine/_endian.h \ + /usr/arm-none-eabi/include/sys/select.h \ + /usr/arm-none-eabi/include/sys/_sigset.h \ + /usr/arm-none-eabi/include/sys/_timeval.h \ + /usr/arm-none-eabi/include/sys/timespec.h \ + /usr/arm-none-eabi/include/sys/_timespec.h \ + /usr/arm-none-eabi/include/sys/_pthreadtypes.h \ + /usr/arm-none-eabi/include/sys/sched.h \ + /usr/arm-none-eabi/include/machine/types.h \ + /usr/arm-none-eabi/include/sys/stdio.h \ + /usr/arm-none-eabi/include/ssp/stdio.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/sys/_intsup.h ../config/lv_conf.h \ + /usr/arm-none-eabi/include/string.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_refr.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_math.h +/usr/arm-none-eabi/include/stdio.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/types.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/arm-none-eabi/include/machine/endian.h: +/usr/arm-none-eabi/include/machine/_endian.h: +/usr/arm-none-eabi/include/sys/select.h: +/usr/arm-none-eabi/include/sys/_sigset.h: +/usr/arm-none-eabi/include/sys/_timeval.h: +/usr/arm-none-eabi/include/sys/timespec.h: +/usr/arm-none-eabi/include/sys/_timespec.h: +/usr/arm-none-eabi/include/sys/_pthreadtypes.h: +/usr/arm-none-eabi/include/sys/sched.h: +/usr/arm-none-eabi/include/machine/types.h: +/usr/arm-none-eabi/include/sys/stdio.h: +/usr/arm-none-eabi/include/ssp/stdio.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +../config/lv_conf.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_refr.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_math.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_line.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_line.o new file mode 100644 index 00000000..7cd07d34 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_line.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_mask.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_mask.d new file mode 100644 index 00000000..6c89d383 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_mask.d @@ -0,0 +1,183 @@ +shared/thirdparty/lvgl/src/lv_draw/lv_draw_mask.d \ + shared/thirdparty/lvgl/src/lv_draw/lv_draw_mask.o: \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_draw_mask.c \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_draw_mask.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_debug.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_gc.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_draw/lv_img_cache.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_draw/lv_draw_mask.h +../shared/thirdparty/lvgl/src/lv_draw/lv_draw_mask.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_debug.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_gc.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_draw/lv_img_cache.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_draw/lv_draw_mask.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_mask.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_mask.o new file mode 100644 index 00000000..77283bee Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_mask.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_rect.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_rect.d new file mode 100644 index 00000000..42d1ab2a --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_rect.d @@ -0,0 +1,173 @@ +shared/thirdparty/lvgl/src/lv_draw/lv_draw_rect.d \ + shared/thirdparty/lvgl/src/lv_draw/lv_draw_rect.o: \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_draw_rect.c \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_style.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_refr.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_debug.h +../shared/thirdparty/lvgl/src/lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_style.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_refr.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_debug.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_rect.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_rect.o new file mode 100644 index 00000000..829d5307 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_rect.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_triangle.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_triangle.d new file mode 100644 index 00000000..ba3299d0 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_triangle.d @@ -0,0 +1,103 @@ +shared/thirdparty/lvgl/src/lv_draw/lv_draw_triangle.d \ + shared/thirdparty/lvgl/src/lv_draw/lv_draw_triangle.o: \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_draw_triangle.c \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_draw_triangle.h \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_style.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_mem.h +../shared/thirdparty/lvgl/src/lv_draw/lv_draw_triangle.h: +../shared/thirdparty/lvgl/src/lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_style.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_mem.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_triangle.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_triangle.o new file mode 100644 index 00000000..081c91f5 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_draw_triangle.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_img_buf.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_img_buf.d new file mode 100644 index 00000000..cce80051 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_img_buf.d @@ -0,0 +1,117 @@ +shared/thirdparty/lvgl/src/lv_draw/lv_img_buf.d \ + shared/thirdparty/lvgl/src/lv_draw/lv_img_buf.o: \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_img_buf.c \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_img_buf.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_mem.h +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_draw/lv_img_buf.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_mem.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_img_buf.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_img_buf.o new file mode 100644 index 00000000..1114cf86 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_img_buf.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_img_cache.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_img_cache.d new file mode 100644 index 00000000..c65f70e2 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_img_cache.d @@ -0,0 +1,181 @@ +shared/thirdparty/lvgl/src/lv_draw/lv_img_cache.d \ + shared/thirdparty/lvgl/src/lv_draw/lv_img_cache.o: \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_img_cache.c \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_debug.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_img_cache.h \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_gc.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_draw/lv_img_cache.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_draw/lv_draw_mask.h +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_debug.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_draw/lv_img_cache.h: +../shared/thirdparty/lvgl/src/lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_gc.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_draw/lv_img_cache.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_draw/lv_draw_mask.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_img_cache.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_img_cache.o new file mode 100644 index 00000000..3761db42 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_img_cache.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_img_decoder.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_img_decoder.d new file mode 100644 index 00000000..25c44fe0 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_img_decoder.d @@ -0,0 +1,185 @@ +shared/thirdparty/lvgl/src/lv_draw/lv_img_decoder.d \ + shared/thirdparty/lvgl/src/lv_draw/lv_img_decoder.o: \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_img_decoder.c \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_draw/lv_img_buf.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_area.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_debug.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_gc.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_draw/lv_img_cache.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_draw/lv_draw_mask.h +../shared/thirdparty/lvgl/src/lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +../shared/thirdparty/lvgl/src/lv_draw/lv_img_buf.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_area.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: 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+../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_debug.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_gc.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_draw/lv_img_cache.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_draw/../lv_misc/../lv_draw/lv_draw_mask.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_img_decoder.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_img_decoder.o new file mode 100644 index 00000000..54d3aa54 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_draw/lv_img_decoder.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font.d new file mode 100644 index 00000000..6cf9ad04 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font.d @@ -0,0 +1,75 @@ +shared/thirdparty/lvgl/src/lv_font/lv_font.d \ + shared/thirdparty/lvgl/src/lv_font/lv_font.o: \ + ../shared/thirdparty/lvgl/src/lv_font/lv_font.c \ + ../shared/thirdparty/lvgl/src/lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_misc/lv_utils.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_misc/lv_log.h +../shared/thirdparty/lvgl/src/lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_misc/../lv_conf_internal.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_misc/lv_utils.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_misc/lv_log.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font.o new file mode 100644 index 00000000..d02943d9 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_dejavu_16_persian_hebrew.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_dejavu_16_persian_hebrew.d new file mode 100644 index 00000000..340ad5ee --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_dejavu_16_persian_hebrew.d @@ -0,0 +1,363 @@ +shared/thirdparty/lvgl/src/lv_font/lv_font_dejavu_16_persian_hebrew.d \ + shared/thirdparty/lvgl/src/lv_font/lv_font_dejavu_16_persian_hebrew.o: \ + ../shared/thirdparty/lvgl/src/lv_font/lv_font_dejavu_16_persian_hebrew.c \ + ../shared/thirdparty/lvgl/src/lv_font/../../lvgl.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_task.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_mem.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_async.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/../lv_misc/lv_area.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/lv_group.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/lv_indev.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_core/lv_group.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/lv_refr.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/lv_disp.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_themes/lv_theme.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_themes/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_themes/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_themes/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_themes/lv_theme_empty.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_themes/lv_theme_template.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_themes/lv_theme_material.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_themes/lv_theme_mono.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_font/lv_font_fmt_txt.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_printf.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_btn.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_cont.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/../lv_core/lv_indev.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_imgbtn.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_btn.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_img.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_label.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/../lv_draw/lv_draw.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/../lv_draw/lv_draw_triangle.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/../lv_draw/lv_draw_arc.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_label.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_line.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_page.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_cont.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_list.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_page.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_img.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_chart.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_line.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_table.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_checkbox.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_cpicker.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_bar.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_slider.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_bar.h \ + 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+../shared/thirdparty/lvgl/src/lv_font/../../src/lv_api_map.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/../lvgl.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_dejavu_16_persian_hebrew.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_dejavu_16_persian_hebrew.o new file mode 100644 index 00000000..145a6afe Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_dejavu_16_persian_hebrew.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_fmt_txt.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_fmt_txt.d new file mode 100644 index 00000000..43aa5e57 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_fmt_txt.d @@ -0,0 +1,199 @@ +shared/thirdparty/lvgl/src/lv_font/lv_font_fmt_txt.d \ + shared/thirdparty/lvgl/src/lv_font/lv_font_fmt_txt.o: \ + ../shared/thirdparty/lvgl/src/lv_font/lv_font_fmt_txt.c \ + ../shared/thirdparty/lvgl/src/lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_font/lv_font_fmt_txt.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/lv_debug.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_draw/lv_draw.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_draw/lv_draw_triangle.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_draw/lv_draw_arc.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_misc/lv_utils.h \ + ../shared/thirdparty/lvgl/src/lv_font/../lv_misc/lv_mem.h +../shared/thirdparty/lvgl/src/lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_misc/../lv_conf_internal.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_font/lv_font_fmt_txt.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/lv_debug.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_hal/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_hal/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_hal/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_hal/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_draw/lv_draw.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_draw/lv_draw_triangle.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_draw/lv_draw_arc.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_misc/lv_utils.h: +../shared/thirdparty/lvgl/src/lv_font/../lv_misc/lv_mem.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_fmt_txt.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_fmt_txt.o new file mode 100644 index 00000000..cf650fd7 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_fmt_txt.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_12.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_12.d new file mode 100644 index 00000000..9833e80a --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_12.d @@ -0,0 +1,363 @@ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_12.d \ + shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_12.o: \ + ../shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_12.c \ + ../shared/thirdparty/lvgl/src/lv_font/../../lvgl.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_task.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_mem.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_async.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/../lv_misc/lv_area.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_font/../lv_conf_internal.h \ + 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--git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_14.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_14.d new file mode 100644 index 00000000..3354a066 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_14.d @@ -0,0 +1,363 @@ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_14.d \ + shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_14.o: \ + ../shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_14.c \ + ../shared/thirdparty/lvgl/src/lv_font/../../lvgl.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_task.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_mem.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_async.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/lv_hal_disp.h \ + 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+../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_win.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_tabview.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/../lv_widgets/lv_win.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_tileview.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_msgbox.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_objmask.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/../lv_widgets/lv_cont.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_gauge.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_linemeter.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_linemeter.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_switch.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_arc.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_spinner.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_arc.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_calendar.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_spinbox.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/../lv_widgets/lv_textarea.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_draw/lv_img_cache.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_api_map.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/../lvgl.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_16.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_16.o new file mode 100644 index 00000000..d2bd840d Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_16.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_18.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_18.d new file mode 100644 index 00000000..baff1ff0 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_18.d @@ -0,0 +1,363 @@ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_18.d \ + shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_18.o: \ + ../shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_18.c \ + ../shared/thirdparty/lvgl/src/lv_font/../../lvgl.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_task.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_mem.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_async.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/lv_hal_disp.h \ + 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+../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_arc.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_calendar.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_spinbox.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/../lv_widgets/lv_textarea.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_draw/lv_img_cache.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_api_map.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/../lvgl.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_20.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_20.o new file mode 100644 index 00000000..d06e13f7 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_20.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_22.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_22.d new file mode 100644 index 00000000..d5a0598c --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_22.d @@ -0,0 +1,363 @@ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_22.d \ + shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_22.o: \ + ../shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_22.c \ + ../shared/thirdparty/lvgl/src/lv_font/../../lvgl.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_task.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_mem.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_async.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/lv_hal_disp.h \ + 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+../shared/thirdparty/lvgl/src/lv_font/../../src/lv_api_map.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/../lvgl.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_26.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_26.o new file mode 100644 index 00000000..5cd40d36 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_26.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_28.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_28.d new file mode 100644 index 00000000..46b4b173 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_28.d @@ -0,0 +1,363 @@ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_28.d \ + shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_28.o: \ + ../shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_28.c \ + ../shared/thirdparty/lvgl/src/lv_font/../../lvgl.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_task.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_mem.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + 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+../shared/thirdparty/lvgl/src/lv_font/../../src/lv_api_map.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/../lvgl.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_34.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_34.o new file mode 100644 index 00000000..214c0799 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_34.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_36.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_36.d new file mode 100644 index 00000000..4c7c1f8d --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_36.d @@ -0,0 +1,363 @@ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_36.d \ + shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_36.o: \ + ../shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_36.c \ + ../shared/thirdparty/lvgl/src/lv_font/../../lvgl.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_task.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_mem.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + 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+../shared/thirdparty/lvgl/src/lv_font/../../src/lv_api_map.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/../lvgl.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_38.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_38.o new file mode 100644 index 00000000..f777baec Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_38.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_40.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_40.d new file mode 100644 index 00000000..6fa9b5a0 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_40.d @@ -0,0 +1,363 @@ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_40.d \ + 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a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_46.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_46.d new file mode 100644 index 00000000..7cb8113e --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_46.d @@ -0,0 +1,363 @@ +shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_46.d \ + shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_46.o: \ + ../shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_46.c \ + ../shared/thirdparty/lvgl/src/lv_font/../../lvgl.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_task.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_mem.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_async.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/../lv_misc/lv_area.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/lv_draw_line.h \ + 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+../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_win.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_tabview.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/../lv_widgets/lv_win.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_tileview.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_msgbox.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_objmask.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/../lv_widgets/lv_cont.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_gauge.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_linemeter.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_linemeter.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_switch.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_arc.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_spinner.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_arc.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_calendar.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/lv_spinbox.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_widgets/../lv_widgets/lv_textarea.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_draw/lv_img_cache.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/lv_api_map.h: +../shared/thirdparty/lvgl/src/lv_font/../../src/../lvgl.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_48.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_48.o new file mode 100644 index 00000000..3334f9e6 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_montserrat_48.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_simsun_16_cjk.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_simsun_16_cjk.d new file mode 100644 index 00000000..c4566690 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_font/lv_font_simsun_16_cjk.d @@ -0,0 +1,363 @@ +shared/thirdparty/lvgl/src/lv_font/lv_font_simsun_16_cjk.d \ + shared/thirdparty/lvgl/src/lv_font/lv_font_simsun_16_cjk.o: \ + ../shared/thirdparty/lvgl/src/lv_font/lv_font_simsun_16_cjk.c \ + ../shared/thirdparty/lvgl/src/lv_font/../../lvgl.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_task.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_mem.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_async.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/../lv_misc/lv_area.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_font/../lv_conf_internal.h \ + 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../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_font/../../src/lv_core/../lv_draw/lv_draw_line.h \ + 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+../shared/thirdparty/lvgl/src/lv_gpu/../lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_gpu/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_gpu/../lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_gpu/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_gpu/../lv_core/../lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_gpu/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_gpu/../lv_core/../lv_hal/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_gpu/../lv_core/../lv_hal/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_gpu/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_gpu/../lv_core/../lv_hal/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_gpu/../lv_core/../lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_gpu/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h: 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+../shared/thirdparty/lvgl/src/lv_gpu/../lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_gpu/../lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_gpu/../lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_gpu/../lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_gpu/../lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_gpu/../lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_gpu/../lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_gpu/../lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_gpu/../lv_core/lv_obj_style_dec.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_gpu/lv_gpu_stm32_dma2d.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_gpu/lv_gpu_stm32_dma2d.o new file mode 100644 index 00000000..78213129 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_gpu/lv_gpu_stm32_dma2d.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_hal/lv_hal_disp.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_hal/lv_hal_disp.d new file mode 100644 index 00000000..c92bce47 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_hal/lv_hal_disp.d @@ -0,0 +1,206 @@ +shared/thirdparty/lvgl/src/lv_hal/lv_hal_disp.d \ + shared/thirdparty/lvgl/src/lv_hal/lv_hal_disp.o: \ + ../shared/thirdparty/lvgl/src/lv_hal/lv_hal_disp.c \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + ../shared/thirdparty/lvgl/src/lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_hal/lv_hal_disp.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_conf_internal.h \ + ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_area.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_gc.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/lv_img_cache.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/lv_debug.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/lv_refr.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_themes/lv_theme.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_themes/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_themes/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_themes/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_themes/lv_theme_empty.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_themes/lv_theme_template.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_themes/lv_theme_material.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_themes/lv_theme_mono.h +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +../shared/thirdparty/lvgl/src/lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_hal/lv_hal_disp.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_conf_internal.h: +../config/lv_conf.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_area.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: 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+../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_gc.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/lv_img_cache.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_core/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/../lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/lv_debug.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/lv_refr.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_themes/lv_theme.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_themes/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_themes/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_themes/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_themes/lv_theme_empty.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_themes/lv_theme_template.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_themes/lv_theme_mono.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_hal/lv_hal_disp.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_hal/lv_hal_disp.o new file mode 100644 index 00000000..7ebdcaa3 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_hal/lv_hal_disp.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_hal/lv_hal_indev.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_hal/lv_hal_indev.d new file mode 100644 index 00000000..55bd3db9 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_hal/lv_hal_indev.d @@ -0,0 +1,189 @@ +shared/thirdparty/lvgl/src/lv_hal/lv_hal_indev.d \ + shared/thirdparty/lvgl/src/lv_hal/lv_hal_indev.o: \ + ../shared/thirdparty/lvgl/src/lv_hal/lv_hal_indev.c \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/lv_debug.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_font/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_font/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_font/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/lv_indev.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_core/lv_group.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_gc.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/lv_img_cache.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_hal/lv_hal_disp.h +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/lv_debug.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_font/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_font/../lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_font/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_hal/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_hal/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_hal/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_hal/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/lv_indev.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_core/lv_group.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_core/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_gc.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/lv_img_cache.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_misc/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_hal/lv_hal_disp.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_hal/lv_hal_indev.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_hal/lv_hal_indev.o new file mode 100644 index 00000000..884b19e2 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_hal/lv_hal_indev.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_hal/lv_hal_tick.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_hal/lv_hal_tick.d new file mode 100644 index 00000000..f80ee0ed --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_hal/lv_hal_tick.d @@ -0,0 +1,26 @@ +shared/thirdparty/lvgl/src/lv_hal/lv_hal_tick.d \ + shared/thirdparty/lvgl/src/lv_hal/lv_hal_tick.o: \ + ../shared/thirdparty/lvgl/src/lv_hal/lv_hal_tick.c \ + ../shared/thirdparty/lvgl/src/lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_hal/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h +../shared/thirdparty/lvgl/src/lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_hal/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_hal/lv_hal_tick.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_hal/lv_hal_tick.o new file mode 100644 index 00000000..bfbbc811 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_hal/lv_hal_tick.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_anim.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_anim.d new file mode 100644 index 00000000..aadcfb0d --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_anim.d @@ -0,0 +1,181 @@ +shared/thirdparty/lvgl/src/lv_misc/lv_anim.d \ + shared/thirdparty/lvgl/src/lv_misc/lv_anim.o: \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_anim.c \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/lv_debug.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_font/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_gc.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_img_cache.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_draw_mask.h +../shared/thirdparty/lvgl/src/lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/lv_debug.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_font/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_gc.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_img_cache.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_draw_mask.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_anim.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_anim.o new file mode 100644 index 00000000..500a238c Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_anim.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_area.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_area.d new file mode 100644 index 00000000..41e7a71d --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_area.d @@ -0,0 +1,67 @@ +shared/thirdparty/lvgl/src/lv_misc/lv_area.d \ + shared/thirdparty/lvgl/src/lv_misc/lv_area.o: \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_area.c \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_area.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_math.h +../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_area.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_math.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_area.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_area.o new file mode 100644 index 00000000..ac339fae Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_area.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_async.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_async.d new file mode 100644 index 00000000..d82e65b6 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_async.d @@ -0,0 +1,36 @@ +shared/thirdparty/lvgl/src/lv_misc/lv_async.d \ + shared/thirdparty/lvgl/src/lv_misc/lv_async.o: \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_async.c \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_async.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_mem.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_ll.h +../shared/thirdparty/lvgl/src/lv_misc/lv_async.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_mem.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_ll.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_async.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_async.o new file mode 100644 index 00000000..bc363bce Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_async.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_bidi.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_bidi.d new file mode 100644 index 00000000..9abc5ed6 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_bidi.d @@ -0,0 +1,79 @@ +shared/thirdparty/lvgl/src/lv_misc/lv_bidi.d \ + shared/thirdparty/lvgl/src/lv_misc/lv_bidi.o: \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_bidi.c \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_area.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_misc/lv_mem.h +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_area.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_misc/lv_mem.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_bidi.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_bidi.o new file mode 100644 index 00000000..16901aa6 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_bidi.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_color.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_color.d new file mode 100644 index 00000000..76297b8b --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_color.d @@ -0,0 +1,24 @@ +shared/thirdparty/lvgl/src/lv_misc/lv_color.d \ + shared/thirdparty/lvgl/src/lv_misc/lv_color.o: \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_color.c \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_math.h +../shared/thirdparty/lvgl/src/lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_math.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_color.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_color.o new file mode 100644 index 00000000..3e89016a Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_color.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_fs.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_fs.d new file mode 100644 index 00000000..805be9de --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_fs.d @@ -0,0 +1,177 @@ +shared/thirdparty/lvgl/src/lv_misc/lv_fs.d \ + shared/thirdparty/lvgl/src/lv_misc/lv_fs.o: \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_fs.c \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_mem.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/lv_debug.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_font/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_gc.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_img_cache.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_draw_mask.h +../shared/thirdparty/lvgl/src/lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_mem.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/lv_debug.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_font/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_gc.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_img_cache.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_draw_mask.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_fs.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_fs.o new file mode 100644 index 00000000..5ffd055c Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_fs.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_gc.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_gc.d new file mode 100644 index 00000000..b74def85 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_gc.d @@ -0,0 +1,123 @@ +shared/thirdparty/lvgl/src/lv_misc/lv_gc.d \ + shared/thirdparty/lvgl/src/lv_misc/lv_gc.o: \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_gc.c \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_gc.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h \ + ../config/lv_conf.h /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_img_cache.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_area.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_draw_mask.h +../shared/thirdparty/lvgl/src/lv_misc/lv_gc.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h: +../config/lv_conf.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_img_cache.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_area.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_draw_mask.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_gc.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_gc.o new file mode 100644 index 00000000..8f5d9d5b Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_gc.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_ll.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_ll.d new file mode 100644 index 00000000..60e039d1 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_ll.d @@ -0,0 +1,65 @@ +shared/thirdparty/lvgl/src/lv_misc/lv_ll.d \ + shared/thirdparty/lvgl/src/lv_misc/lv_ll.o: \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_ll.c \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h \ + ../config/lv_conf.h ../shared/thirdparty/lvgl/src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_types.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h: +../config/lv_conf.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_types.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_ll.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_ll.o new file mode 100644 index 00000000..08d37062 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_ll.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_log.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_log.d new file mode 100644 index 00000000..e6ce2df3 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_log.d @@ -0,0 +1,61 @@ +shared/thirdparty/lvgl/src/lv_misc/lv_log.d \ + shared/thirdparty/lvgl/src/lv_misc/lv_log.o: \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_log.c \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_printf.h +../shared/thirdparty/lvgl/src/lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_printf.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_log.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_log.o new file mode 100644 index 00000000..b543a840 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_log.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_math.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_math.d new file mode 100644 index 00000000..d2b3dd14 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_math.d @@ -0,0 +1,66 @@ +shared/thirdparty/lvgl/src/lv_misc/lv_math.d \ + shared/thirdparty/lvgl/src/lv_misc/lv_math.o: \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_math.c \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + /usr/arm-none-eabi/include/stdlib.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/_ansi.h /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/machine/stdlib.h \ + /usr/arm-none-eabi/include/alloca.h \ + /usr/arm-none-eabi/include/ssp/stdlib.h \ + /usr/arm-none-eabi/include/ssp/ssp.h /usr/arm-none-eabi/include/string.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h +../shared/thirdparty/lvgl/src/lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +/usr/arm-none-eabi/include/stdlib.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/machine/stdlib.h: +/usr/arm-none-eabi/include/alloca.h: +/usr/arm-none-eabi/include/ssp/stdlib.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_math.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_math.o new file mode 100644 index 00000000..0e0e3c0e Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_math.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_mem.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_mem.d new file mode 100644 index 00000000..f5f94729 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_mem.d @@ -0,0 +1,125 @@ +shared/thirdparty/lvgl/src/lv_misc/lv_mem.d \ + shared/thirdparty/lvgl/src/lv_misc/lv_mem.o: \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_mem.c \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_gc.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_img_cache.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_area.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_draw_mask.h +../shared/thirdparty/lvgl/src/lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_gc.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_img_cache.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_area.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_draw_mask.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_mem.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_mem.o new file mode 100644 index 00000000..2aec0b52 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_mem.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_printf.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_printf.d new file mode 100644 index 00000000..e02b064a --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_printf.d @@ -0,0 +1,28 @@ +shared/thirdparty/lvgl/src/lv_misc/lv_printf.d \ + shared/thirdparty/lvgl/src/lv_misc/lv_printf.o: \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_printf.c \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_printf.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h +../shared/thirdparty/lvgl/src/lv_misc/lv_printf.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_printf.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_printf.o new file mode 100644 index 00000000..13b7e6b6 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_printf.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_task.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_task.d new file mode 100644 index 00000000..46380c6e --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_task.d @@ -0,0 +1,173 @@ +shared/thirdparty/lvgl/src/lv_misc/lv_task.d \ + shared/thirdparty/lvgl/src/lv_misc/lv_task.o: \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_task.c \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/lv_debug.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_font/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_gc.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_img_cache.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_draw_mask.h +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/lv_debug.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_font/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_gc.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_img_cache.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_draw_mask.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_task.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_task.o new file mode 100644 index 00000000..6465d5ae Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_task.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_templ.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_templ.d new file mode 100644 index 00000000..12fd5f63 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_templ.d @@ -0,0 +1,3 @@ +shared/thirdparty/lvgl/src/lv_misc/lv_templ.d \ + shared/thirdparty/lvgl/src/lv_misc/lv_templ.o: \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_templ.c diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_templ.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_templ.o new file mode 100644 index 00000000..f83a9d8a Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_templ.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_txt.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_txt.d new file mode 100644 index 00000000..08943d56 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_txt.d @@ -0,0 +1,77 @@ +shared/thirdparty/lvgl/src/lv_misc/lv_txt.d \ + shared/thirdparty/lvgl/src/lv_misc/lv_txt.o: \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_txt.c \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_area.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_math.h +../shared/thirdparty/lvgl/src/lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_area.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_math.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_txt.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_txt.o new file mode 100644 index 00000000..8154279b Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_txt.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_txt_ap.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_txt_ap.d new file mode 100644 index 00000000..a332065a --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_txt_ap.d @@ -0,0 +1,145 @@ +shared/thirdparty/lvgl/src/lv_misc/lv_txt_ap.d \ + shared/thirdparty/lvgl/src/lv_misc/lv_txt_ap.o: \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_txt_ap.c \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_area.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_txt_ap.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_draw.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_draw_triangle.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_draw_arc.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_draw_mask.h +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_area.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_txt_ap.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_draw.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_draw_triangle.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_draw_arc.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_draw/lv_draw_mask.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_txt_ap.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_txt_ap.o new file mode 100644 index 00000000..aef614ac Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_txt_ap.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_utils.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_utils.d new file mode 100644 index 00000000..f1cead30 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_utils.d @@ -0,0 +1,83 @@ +shared/thirdparty/lvgl/src/lv_misc/lv_utils.d \ + shared/thirdparty/lvgl/src/lv_misc/lv_utils.o: \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_utils.c \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_utils.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h \ + ../config/lv_conf.h ../shared/thirdparty/lvgl/src/lv_misc/lv_printf.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_area.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_misc/../lv_font/../lv_misc/lv_area.h +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_utils.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_conf_internal.h: +../config/lv_conf.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_printf.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_area.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_misc/../lv_font/../lv_misc/lv_area.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_utils.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_utils.o new file mode 100644 index 00000000..8a34f17f Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_misc/lv_utils.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_themes/lv_theme.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_themes/lv_theme.d new file mode 100644 index 00000000..3f3989d8 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_themes/lv_theme.d @@ -0,0 +1,173 @@ +shared/thirdparty/lvgl/src/lv_themes/lv_theme.d \ + shared/thirdparty/lvgl/src/lv_themes/lv_theme.o: \ + ../shared/thirdparty/lvgl/src/lv_themes/lv_theme.c \ + ../shared/thirdparty/lvgl/src/lv_themes/lv_theme.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/lv_style.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_font/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_font/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_font/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_font/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_themes/lv_theme_empty.h \ + ../shared/thirdparty/lvgl/src/lv_themes/lv_theme_template.h \ + ../shared/thirdparty/lvgl/src/lv_themes/lv_theme_material.h \ + ../shared/thirdparty/lvgl/src/lv_themes/lv_theme_mono.h +../shared/thirdparty/lvgl/src/lv_themes/lv_theme.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/lv_style.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_font/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_font/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_font/../lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_font/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_hal/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_hal/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_hal/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_hal/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_themes/lv_theme_empty.h: +../shared/thirdparty/lvgl/src/lv_themes/lv_theme_template.h: +../shared/thirdparty/lvgl/src/lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/src/lv_themes/lv_theme_mono.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_themes/lv_theme.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_themes/lv_theme.o new file mode 100644 index 00000000..1e9c2079 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_themes/lv_theme.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_themes/lv_theme_empty.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_themes/lv_theme_empty.d new file mode 100644 index 00000000..b5b0c39e --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_themes/lv_theme_empty.d @@ -0,0 +1,376 @@ +shared/thirdparty/lvgl/src/lv_themes/lv_theme_empty.d \ + shared/thirdparty/lvgl/src/lv_themes/lv_theme_empty.o: \ + ../shared/thirdparty/lvgl/src/lv_themes/lv_theme_empty.c \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../lvgl.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_misc/../lv_conf_internal.h \ + ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_misc/lv_task.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_misc/lv_mem.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_misc/lv_async.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_hal/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_hal/../lv_misc/lv_area.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + 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+../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_objmask.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_widgets/lv_cont.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_gauge.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_linemeter.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_linemeter.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_switch.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_arc.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_spinner.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_arc.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_calendar.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_spinbox.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_widgets/lv_textarea.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_draw/lv_img_cache.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_api_map.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/../lvgl.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_misc/lv_gc.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_misc/../lv_draw/lv_img_cache.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_misc/../lv_draw/lv_draw_mask.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_themes/lv_theme_empty.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_themes/lv_theme_empty.o new file mode 100644 index 00000000..07912092 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_themes/lv_theme_empty.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_themes/lv_theme_material.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_themes/lv_theme_material.d new file mode 100644 index 00000000..d35dfd9e --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_themes/lv_theme_material.d @@ -0,0 +1,375 @@ +shared/thirdparty/lvgl/src/lv_themes/lv_theme_material.d \ + shared/thirdparty/lvgl/src/lv_themes/lv_theme_material.o: \ + ../shared/thirdparty/lvgl/src/lv_themes/lv_theme_material.c \ + ../shared/thirdparty/lvgl/src/lv_themes/../../lvgl.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_misc/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + 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+../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_widgets/lv_textarea.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_draw/lv_img_cache.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_api_map.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/../lvgl.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_misc/lv_gc.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_misc/../lv_draw/lv_img_cache.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_misc/../lv_draw/lv_draw_mask.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_themes/lv_theme_material.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_themes/lv_theme_material.o new file mode 100644 index 00000000..662a9b4f Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_themes/lv_theme_material.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_themes/lv_theme_mono.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_themes/lv_theme_mono.d new file mode 100644 index 00000000..ce7d56b1 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_themes/lv_theme_mono.d @@ -0,0 +1,375 @@ +shared/thirdparty/lvgl/src/lv_themes/lv_theme_mono.d \ + shared/thirdparty/lvgl/src/lv_themes/lv_theme_mono.o: \ + ../shared/thirdparty/lvgl/src/lv_themes/lv_theme_mono.c \ + ../shared/thirdparty/lvgl/src/lv_themes/../../lvgl.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_misc/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_misc/lv_task.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_misc/lv_mem.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_misc/lv_async.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_hal/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_hal/../lv_misc/lv_area.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + 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../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/lv_group.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/lv_indev.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_core/lv_group.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/lv_refr.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/lv_disp.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_themes/lv_theme.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_themes/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_themes/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_themes/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_themes/lv_theme_empty.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_themes/lv_theme_template.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_themes/lv_theme_material.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_themes/lv_theme_mono.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_font/lv_font_fmt_txt.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_misc/lv_printf.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_btn.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_cont.h \ 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../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/lv_draw_triangle.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/lv_draw_arc.h \ + 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../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_table.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_checkbox.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_cpicker.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_bar.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_slider.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_bar.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_led.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_btnmatrix.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_keyboard.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_btnmatrix.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_dropdown.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_widgets/lv_page.h \ + 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+../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/lv_group.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/lv_indev.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/../lv_core/lv_group.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/lv_refr.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_core/lv_disp.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_themes/lv_theme.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_themes/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_themes/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_themes/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_themes/lv_theme_empty.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_themes/lv_theme_template.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_themes/lv_theme_mono.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_font/lv_font_fmt_txt.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_misc/lv_printf.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_btn.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_cont.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_core/lv_indev.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_imgbtn.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_btn.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_img.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_label.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/lv_draw.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/lv_draw_triangle.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/lv_draw_arc.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_label.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_line.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_page.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_cont.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_list.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_page.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_img.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_chart.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_line.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_table.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_checkbox.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_cpicker.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_bar.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_slider.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_bar.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_led.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_btnmatrix.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_keyboard.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_btnmatrix.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_dropdown.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_widgets/lv_page.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_widgets/lv_label.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_roller.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_textarea.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_canvas.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_widgets/lv_img.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_win.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_tabview.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_widgets/lv_win.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_tileview.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_msgbox.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_objmask.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_widgets/lv_cont.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_gauge.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_linemeter.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_linemeter.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_switch.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_arc.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_spinner.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_arc.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_calendar.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_spinbox.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_widgets/lv_textarea.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_draw/lv_img_cache.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_api_map.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/../lvgl.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_misc/lv_gc.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_misc/../lv_draw/lv_img_cache.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_misc/../lv_draw/lv_draw_mask.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_themes/lv_theme_mono.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_themes/lv_theme_mono.o new file mode 100644 index 00000000..6a5a9db0 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_themes/lv_theme_mono.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_themes/lv_theme_template.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_themes/lv_theme_template.d new file mode 100644 index 00000000..3e06a5bc --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_themes/lv_theme_template.d @@ -0,0 +1,375 @@ +shared/thirdparty/lvgl/src/lv_themes/lv_theme_template.d \ + shared/thirdparty/lvgl/src/lv_themes/lv_theme_template.o: \ + ../shared/thirdparty/lvgl/src/lv_themes/lv_theme_template.c \ + ../shared/thirdparty/lvgl/src/lv_themes/../../lvgl.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_misc/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_misc/lv_task.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_misc/lv_mem.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_misc/lv_async.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_hal/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_hal/../lv_misc/lv_area.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + 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+../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_label.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/lv_draw.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/lv_draw_triangle.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/lv_draw_arc.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_label.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_line.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_page.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_cont.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_list.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_page.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_img.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_chart.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_line.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_table.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_checkbox.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_cpicker.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_bar.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_slider.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_bar.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_led.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_btnmatrix.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_keyboard.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_btnmatrix.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_dropdown.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_widgets/lv_page.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_widgets/lv_label.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_roller.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_textarea.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_canvas.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_widgets/lv_img.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_win.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_tabview.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_widgets/lv_win.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_tileview.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_msgbox.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_objmask.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_widgets/lv_cont.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_gauge.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_linemeter.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_linemeter.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_switch.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_arc.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_spinner.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_arc.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_calendar.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/lv_spinbox.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_widgets/../lv_widgets/lv_textarea.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_draw/lv_img_cache.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/lv_api_map.h: +../shared/thirdparty/lvgl/src/lv_themes/../../src/../lvgl.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_misc/lv_gc.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_misc/../lv_draw/lv_img_cache.h: +../shared/thirdparty/lvgl/src/lv_themes/../lv_misc/../lv_draw/lv_draw_mask.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_themes/lv_theme_template.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_themes/lv_theme_template.o new file mode 100644 index 00000000..3772a90a Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_themes/lv_theme_template.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_arc.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_arc.d new file mode 100644 index 00000000..6ebe5531 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_arc.d @@ -0,0 +1,189 @@ +shared/thirdparty/lvgl/src/lv_widgets/lv_arc.d \ + shared/thirdparty/lvgl/src/lv_widgets/lv_arc.o: \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_arc.c \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_arc.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h +../shared/thirdparty/lvgl/src/lv_widgets/lv_arc.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: 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+../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_cont.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_btn.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_indev.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_core/lv_group.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_label.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_math.h: +/usr/arm-none-eabi/include/stdio.h: +/usr/arm-none-eabi/include/sys/types.h: +/usr/arm-none-eabi/include/machine/endian.h: +/usr/arm-none-eabi/include/machine/_endian.h: +/usr/arm-none-eabi/include/sys/select.h: +/usr/arm-none-eabi/include/sys/_sigset.h: +/usr/arm-none-eabi/include/sys/_timeval.h: +/usr/arm-none-eabi/include/sys/timespec.h: +/usr/arm-none-eabi/include/sys/_timespec.h: +/usr/arm-none-eabi/include/sys/_pthreadtypes.h: +/usr/arm-none-eabi/include/sys/sched.h: +/usr/arm-none-eabi/include/machine/types.h: +/usr/arm-none-eabi/include/sys/stdio.h: +/usr/arm-none-eabi/include/ssp/stdio.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_bar.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_bar.o new file mode 100644 index 00000000..e8a79916 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_bar.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_btn.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_btn.d new file mode 100644 index 00000000..18354822 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_btn.d @@ -0,0 +1,227 @@ +shared/thirdparty/lvgl/src/lv_widgets/lv_btn.d \ + shared/thirdparty/lvgl/src/lv_widgets/lv_btn.o: \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_btn.c \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_btn.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_cont.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_core/lv_group.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_group.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h \ + 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+../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_indev.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_core/lv_group.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_group.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_math.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_btn.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_btn.o new file mode 100644 index 00000000..2a178183 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_btn.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_btnmatrix.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_btnmatrix.d new file mode 100644 index 00000000..afa15441 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_btnmatrix.d @@ -0,0 +1,235 @@ +shared/thirdparty/lvgl/src/lv_widgets/lv_btnmatrix.d \ + shared/thirdparty/lvgl/src/lv_widgets/lv_btnmatrix.o: \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_btnmatrix.c \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_btnmatrix.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_label.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h \ + 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+../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_label.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_btn.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_cont.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_indev.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_core/lv_group.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_group.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_refr.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_btnmatrix.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_btnmatrix.o new file mode 100644 index 00000000..673ec09f Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_btnmatrix.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_calendar.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_calendar.d new file mode 100644 index 00000000..deb35d72 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_calendar.d @@ -0,0 +1,221 @@ +shared/thirdparty/lvgl/src/lv_widgets/lv_calendar.d \ + shared/thirdparty/lvgl/src/lv_widgets/lv_calendar.o: \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_calendar.c \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_calendar.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + 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../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_task.h 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../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h \ + 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+../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_utils.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_indev.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_core/lv_group.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_calendar.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_calendar.o new file mode 100644 index 00000000..a59dfc0b Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_calendar.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_canvas.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_canvas.d new file mode 100644 index 00000000..e862870a --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_canvas.d @@ -0,0 +1,243 @@ +shared/thirdparty/lvgl/src/lv_widgets/lv_canvas.d \ + shared/thirdparty/lvgl/src/lv_widgets/lv_canvas.o: \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_canvas.c \ + /usr/arm-none-eabi/include/stdlib.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/_ansi.h /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/machine/stdlib.h \ + /usr/arm-none-eabi/include/alloca.h \ + /usr/arm-none-eabi/include/ssp/stdlib.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_canvas.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_label.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_draw/lv_draw.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_draw/lv_draw_triangle.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_draw/lv_draw_arc.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_refr.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h +/usr/arm-none-eabi/include/stdlib.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/machine/stdlib.h: +/usr/arm-none-eabi/include/alloca.h: +/usr/arm-none-eabi/include/ssp/stdlib.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_canvas.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_color.h: 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+../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_refr.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_chart.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_chart.o new file mode 100644 index 00000000..51e43490 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_chart.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_checkbox.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_checkbox.d new file mode 100644 index 00000000..d0e44f8d --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_checkbox.d @@ -0,0 +1,233 @@ +shared/thirdparty/lvgl/src/lv_widgets/lv_checkbox.d \ + shared/thirdparty/lvgl/src/lv_widgets/lv_checkbox.o: \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_checkbox.c \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_checkbox.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + 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+../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_group.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_checkbox.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_checkbox.o new file mode 100644 index 00000000..c5d43ab7 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_checkbox.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_cont.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_cont.d new file mode 100644 index 00000000..deed787f --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_cont.d @@ -0,0 +1,217 @@ +shared/thirdparty/lvgl/src/lv_widgets/lv_cont.d \ + shared/thirdparty/lvgl/src/lv_widgets/lv_cont.o: \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_cont.c \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_cont.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_math.h +../shared/thirdparty/lvgl/src/lv_widgets/lv_cont.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: 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+../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_math.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_cont.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_cont.o new file mode 100644 index 00000000..6880ad2f Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_cont.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_cpicker.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_cpicker.d new file mode 100644 index 00000000..5d38d529 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_cpicker.d @@ -0,0 +1,199 @@ +shared/thirdparty/lvgl/src/lv_widgets/lv_cpicker.d \ + shared/thirdparty/lvgl/src/lv_widgets/lv_cpicker.o: \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_cpicker.c \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_cpicker.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_core/lv_group.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_refr.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_math.h +../shared/thirdparty/lvgl/src/lv_widgets/lv_cpicker.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_indev.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_core/lv_group.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_refr.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_math.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_cpicker.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_cpicker.o new file mode 100644 index 00000000..97e07131 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_cpicker.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_dropdown.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_dropdown.d new file mode 100644 index 00000000..090c62f8 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_dropdown.d @@ -0,0 +1,253 @@ +shared/thirdparty/lvgl/src/lv_widgets/lv_dropdown.d \ + shared/thirdparty/lvgl/src/lv_widgets/lv_dropdown.o: \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_dropdown.c \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_dropdown.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_page.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_cont.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_font/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_font/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_font/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/lv_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_core/lv_group.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_label.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_draw/lv_draw.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_draw/lv_draw_triangle.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_draw/lv_draw_arc.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_group.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_disp.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_math.h +../shared/thirdparty/lvgl/src/lv_widgets/lv_dropdown.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: 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+../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_utils.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_fs.h: +/usr/arm-none-eabi/include/stdio.h: +/usr/arm-none-eabi/include/sys/types.h: +/usr/arm-none-eabi/include/machine/endian.h: +/usr/arm-none-eabi/include/machine/_endian.h: +/usr/arm-none-eabi/include/sys/select.h: +/usr/arm-none-eabi/include/sys/_sigset.h: +/usr/arm-none-eabi/include/sys/_timeval.h: +/usr/arm-none-eabi/include/sys/timespec.h: +/usr/arm-none-eabi/include/sys/_timespec.h: +/usr/arm-none-eabi/include/sys/_pthreadtypes.h: +/usr/arm-none-eabi/include/sys/sched.h: +/usr/arm-none-eabi/include/machine/types.h: +/usr/arm-none-eabi/include/sys/stdio.h: +/usr/arm-none-eabi/include/ssp/stdio.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_gauge.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_gauge.o new file mode 100644 index 00000000..14ac475d Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_gauge.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_img.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_img.d new file mode 100644 index 00000000..2f4f6514 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_img.d @@ -0,0 +1,227 @@ +shared/thirdparty/lvgl/src/lv_widgets/lv_img.d \ + shared/thirdparty/lvgl/src/lv_widgets/lv_img.o: \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_img.c \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_label.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_log.h +../shared/thirdparty/lvgl/src/lv_widgets/lv_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: 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+../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_log.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_img.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_img.o new file mode 100644 index 00000000..df8d7179 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_img.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_imgbtn.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_imgbtn.d new file mode 100644 index 00000000..8d9ea268 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_imgbtn.d @@ -0,0 +1,233 @@ +shared/thirdparty/lvgl/src/lv_widgets/lv_imgbtn.d \ + shared/thirdparty/lvgl/src/lv_widgets/lv_imgbtn.o: \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_imgbtn.c \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h \ + 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../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h 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+../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_imgbtn.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_imgbtn.o new file mode 100644 index 00000000..d4e21dfd Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_imgbtn.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_keyboard.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_keyboard.d new file mode 100644 index 00000000..69ac7874 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_keyboard.d @@ -0,0 +1,239 @@ +shared/thirdparty/lvgl/src/lv_widgets/lv_keyboard.d \ + shared/thirdparty/lvgl/src/lv_widgets/lv_keyboard.o: \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_keyboard.c \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_keyboard.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + 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../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_task.h 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../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_btnmatrix.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_label.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_btn.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_cont.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_core/lv_group.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h \ + 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+../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_core/lv_group.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_textarea.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_page.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_anim.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_keyboard.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_keyboard.o new file mode 100644 index 00000000..6abbe7ed Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_keyboard.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_label.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_label.d new file mode 100644 index 00000000..be8f7660 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_label.d @@ -0,0 +1,235 @@ +shared/thirdparty/lvgl/src/lv_widgets/lv_label.d \ + shared/thirdparty/lvgl/src/lv_widgets/lv_label.o: \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_label.c \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + 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+../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_group.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_txt_ap.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/../lv_draw/lv_draw.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_printf.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_label.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_label.o new file mode 100644 index 00000000..5fe92c4a Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_label.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_led.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_led.d new file mode 100644 index 00000000..e1fda93b --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_led.d @@ -0,0 +1,209 @@ +shared/thirdparty/lvgl/src/lv_widgets/lv_led.d \ + shared/thirdparty/lvgl/src/lv_widgets/lv_led.o: \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_led.c \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_led.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h +../shared/thirdparty/lvgl/src/lv_widgets/lv_led.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_led.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_led.o new file mode 100644 index 00000000..6063b3b3 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_led.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_line.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_line.d new file mode 100644 index 00000000..d8fc111e --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_line.d @@ -0,0 +1,211 @@ +shared/thirdparty/lvgl/src/lv_widgets/lv_line.d \ + shared/thirdparty/lvgl/src/lv_widgets/lv_line.o: \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_line.c \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h +../shared/thirdparty/lvgl/src/lv_widgets/lv_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_line.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_line.o new file mode 100644 index 00000000..76942b65 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_line.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_linemeter.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_linemeter.d new file mode 100644 index 00000000..2702a55d --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_linemeter.d @@ -0,0 +1,221 @@ +shared/thirdparty/lvgl/src/lv_widgets/lv_linemeter.d \ + shared/thirdparty/lvgl/src/lv_widgets/lv_linemeter.o: \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_linemeter.c \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_linemeter.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_group.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_math.h \ + /usr/arm-none-eabi/include/stdlib.h \ + /usr/arm-none-eabi/include/machine/stdlib.h \ + /usr/arm-none-eabi/include/alloca.h \ + /usr/arm-none-eabi/include/ssp/stdlib.h +../shared/thirdparty/lvgl/src/lv_widgets/lv_linemeter.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_group.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_math.h: +/usr/arm-none-eabi/include/stdlib.h: +/usr/arm-none-eabi/include/machine/stdlib.h: +/usr/arm-none-eabi/include/alloca.h: +/usr/arm-none-eabi/include/ssp/stdlib.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_linemeter.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_linemeter.o new file mode 100644 index 00000000..372fa245 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_linemeter.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_list.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_list.d new file mode 100644 index 00000000..163b9eb3 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_list.d @@ -0,0 +1,243 @@ +shared/thirdparty/lvgl/src/lv_widgets/lv_list.d \ + shared/thirdparty/lvgl/src/lv_widgets/lv_list.o: \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_list.c \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_list.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_page.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_cont.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_core/lv_group.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_btn.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_label.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_group.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_math.h +../shared/thirdparty/lvgl/src/lv_widgets/lv_list.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_conf_internal.h: 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+../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_page.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_cont.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_indev.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_core/lv_group.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_btn.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_label.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_group.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_math.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_list.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_list.o new file mode 100644 index 00000000..0897b33c Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_list.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_msgbox.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_msgbox.d new file mode 100644 index 00000000..4424d00d --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_msgbox.d @@ -0,0 +1,241 @@ +shared/thirdparty/lvgl/src/lv_widgets/lv_msgbox.d \ + shared/thirdparty/lvgl/src/lv_widgets/lv_msgbox.o: \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_msgbox.c \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_msgbox.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_cont.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_btnmatrix.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_label.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_btn.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_core/lv_group.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_group.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_disp.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_math.h +../shared/thirdparty/lvgl/src/lv_widgets/lv_msgbox.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_cont.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_btnmatrix.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_label.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_btn.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_indev.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_core/lv_group.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_group.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_disp.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_math.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_msgbox.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_msgbox.o new file mode 100644 index 00000000..bc6eb80d Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_msgbox.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_objmask.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_objmask.d new file mode 100644 index 00000000..c068e85a --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_objmask.d @@ -0,0 +1,215 @@ +shared/thirdparty/lvgl/src/lv_widgets/lv_objmask.d \ + shared/thirdparty/lvgl/src/lv_widgets/lv_objmask.o: \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_objmask.c \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_objmask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_cont.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h +../shared/thirdparty/lvgl/src/lv_widgets/lv_objmask.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_cont.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_objmask.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_objmask.o new file mode 100644 index 00000000..d2b70c08 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_objmask.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_objx_templ.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_objx_templ.d new file mode 100644 index 00000000..5b7c6ad0 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_objx_templ.d @@ -0,0 +1,161 @@ +shared/thirdparty/lvgl/src/lv_widgets/lv_objx_templ.d \ + shared/thirdparty/lvgl/src/lv_widgets/lv_objx_templ.o: \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_objx_templ.c \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: 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+../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_objx_templ.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_objx_templ.o new file mode 100644 index 00000000..745d591d Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_objx_templ.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_page.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_page.d new file mode 100644 index 00000000..1a5418f9 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_page.d @@ -0,0 +1,231 @@ +shared/thirdparty/lvgl/src/lv_widgets/lv_page.d \ + shared/thirdparty/lvgl/src/lv_widgets/lv_page.o: \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_page.c \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_page.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_cont.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_core/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + 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+../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_refr.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_math.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_page.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_page.o new file mode 100644 index 00000000..7bdae053 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_page.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_roller.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_roller.d new file mode 100644 index 00000000..e54c7e5b --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_roller.d @@ -0,0 +1,235 @@ +shared/thirdparty/lvgl/src/lv_widgets/lv_roller.d \ + shared/thirdparty/lvgl/src/lv_widgets/lv_roller.o: \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_roller.c \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_roller.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + 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../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_group.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h +../shared/thirdparty/lvgl/src/lv_widgets/lv_roller.h: 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+../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h: 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+../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_page.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_cont.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_indev.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_core/lv_group.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_label.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_group.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_roller.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_roller.o new file mode 100644 index 00000000..b9a50323 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_roller.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_slider.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_slider.d new file mode 100644 index 00000000..5acb446c --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_slider.d @@ -0,0 +1,243 @@ +shared/thirdparty/lvgl/src/lv_widgets/lv_slider.d \ + shared/thirdparty/lvgl/src/lv_widgets/lv_slider.o: \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_slider.c \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_slider.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + 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\ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_bar.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_cont.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_btn.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_core/lv_group.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_label.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_group.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_fs.h +../shared/thirdparty/lvgl/src/lv_widgets/lv_slider.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: +/usr/arm-none-eabi/include/sys/reent.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/sys/_types.h: +/usr/arm-none-eabi/include/machine/_types.h: +/usr/arm-none-eabi/include/sys/lock.h: +/usr/arm-none-eabi/include/sys/cdefs.h: +/usr/arm-none-eabi/include/sys/_locale.h: +/usr/arm-none-eabi/include/strings.h: +/usr/arm-none-eabi/include/ssp/strings.h: +/usr/arm-none-eabi/include/ssp/ssp.h: +/usr/arm-none-eabi/include/sys/string.h: +/usr/arm-none-eabi/include/ssp/string.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_log.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_bar.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_cont.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_btn.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_indev.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_core/lv_group.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_label.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_group.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_fs.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_slider.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_slider.o new file mode 100644 index 00000000..cd7fa96f Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_slider.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_spinbox.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_spinbox.d new file mode 100644 index 00000000..7eb3a767 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_spinbox.d @@ -0,0 +1,245 @@ +shared/thirdparty/lvgl/src/lv_widgets/lv_spinbox.d \ + shared/thirdparty/lvgl/src/lv_widgets/lv_spinbox.o: \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_spinbox.c \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_spinbox.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/sys/_types.h \ + /usr/arm-none-eabi/include/machine/_types.h \ + /usr/arm-none-eabi/include/sys/lock.h \ + /usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_txt.h \ + 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+../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_utils.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_spinbox.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_spinbox.o new file mode 100644 index 00000000..00c221af Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_spinbox.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_spinner.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_spinner.d new file mode 100644 index 00000000..c8062fda --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_spinner.d @@ -0,0 +1,195 @@ +shared/thirdparty/lvgl/src/lv_widgets/lv_spinner.d \ + shared/thirdparty/lvgl/src/lv_widgets/lv_spinner.o: \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_spinner.c \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_spinner.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + 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../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_arc.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h +../shared/thirdparty/lvgl/src/lv_widgets/lv_spinner.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h: +/usr/arm-none-eabi/include/string.h: +/usr/arm-none-eabi/include/_ansi.h: +/usr/arm-none-eabi/include/newlib.h: +/usr/arm-none-eabi/include/sys/config.h: +/usr/arm-none-eabi/include/machine/ieeefp.h: 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+../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_disp.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_task.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_tick.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_bidi.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_arc.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_spinner.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_spinner.o new file mode 100644 index 00000000..155bce6d Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_spinner.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_switch.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_switch.d new file mode 100644 index 00000000..66964438 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_switch.d @@ -0,0 +1,243 @@ +shared/thirdparty/lvgl/src/lv_widgets/lv_switch.d \ + shared/thirdparty/lvgl/src/lv_widgets/lv_switch.o: \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_switch.c \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_switch.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_font/../lv_misc/../lv_conf_internal.h \ + /usr/arm-none-eabi/include/string.h /usr/arm-none-eabi/include/_ansi.h \ + /usr/arm-none-eabi/include/newlib.h \ + /usr/arm-none-eabi/include/sys/config.h \ + /usr/arm-none-eabi/include/machine/ieeefp.h \ + /usr/arm-none-eabi/include/sys/reent.h \ + /usr/arm-none-eabi/include/_ansi.h \ + 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../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_disp.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_color.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_area.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_core/lv_style.h \ + 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../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_disp.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_fs.h +../shared/thirdparty/lvgl/src/lv_widgets/lv_switch.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h: +/usr/arm-none-eabi/include/stdint.h: +/usr/arm-none-eabi/include/machine/_default_types.h: +/usr/arm-none-eabi/include/sys/features.h: +/usr/arm-none-eabi/include/_newlib_version.h: +/usr/arm-none-eabi/include/sys/_intsup.h: +/usr/arm-none-eabi/include/sys/_stdint.h: +../config/lv_conf.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_conf_internal.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_style.h: 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+../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_math.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_disp.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_fs.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_switch.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_switch.o new file mode 100644 index 00000000..a648790f Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_switch.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_table.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_table.d new file mode 100644 index 00000000..2d04cdc8 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_table.d @@ -0,0 +1,231 @@ +shared/thirdparty/lvgl/src/lv_widgets/lv_table.d \ + shared/thirdparty/lvgl/src/lv_widgets/lv_table.o: \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_table.c \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_table.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + 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+../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_table.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_table.o new file mode 100644 index 00000000..a3457b19 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_table.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_tabview.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_tabview.d new file mode 100644 index 00000000..3ab87c79 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_tabview.d @@ -0,0 +1,259 @@ +shared/thirdparty/lvgl/src/lv_widgets/lv_tabview.d \ + shared/thirdparty/lvgl/src/lv_widgets/lv_tabview.o: \ + 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../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_draw/lv_draw_triangle.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_draw/lv_draw_arc.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_draw/lv_draw_blend.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_draw/lv_draw_mask.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_page.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_page.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_btnmatrix.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_btn.h \ + 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b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_textarea.d @@ -0,0 +1,239 @@ +shared/thirdparty/lvgl/src/lv_widgets/lv_textarea.d \ + shared/thirdparty/lvgl/src/lv_widgets/lv_textarea.o: \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_textarea.c \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_textarea.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + 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../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_bidi.h \ + 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../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_page.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_cont.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_core/lv_group.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_anim.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_label.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_symbol_def.h \ + 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+../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_math.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_textarea.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_textarea.o new file mode 100644 index 00000000..7ce90c75 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_textarea.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_tileview.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_tileview.d new file mode 100644 index 00000000..28d84b39 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_tileview.d @@ -0,0 +1,205 @@ +shared/thirdparty/lvgl/src/lv_widgets/lv_tileview.d \ + shared/thirdparty/lvgl/src/lv_widgets/lv_tileview.o: \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_tileview.c \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_tileview.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_widgets/lv_page.h \ + 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../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_cont.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_btn.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_core/lv_group.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/lv_label.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h \ + 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+../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_triangle.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_arc.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_img.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/src/lv_widgets/lv_page.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_debug.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_conf_internal.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_empty.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_template.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_themes/lv_theme_mono.h: +../shared/thirdparty/lvgl/src/lv_widgets/../lv_core/lv_disp.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_win.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_win.o new file mode 100644 index 00000000..a1294a33 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/src/lv_widgets/lv_win.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/tests/lv_test_assert.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/tests/lv_test_assert.d new file mode 100644 index 00000000..fc38a04f --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/tests/lv_test_assert.d @@ -0,0 +1,366 @@ +shared/thirdparty/lvgl/tests/lv_test_assert.d \ + shared/thirdparty/lvgl/tests/lv_test_assert.o: \ + ../shared/thirdparty/lvgl/tests/lv_test_assert.c \ + ../shared/thirdparty/lvgl/tests/lv_test_assert.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + 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+../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/../lv_draw/lv_draw_triangle.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/../lv_draw/lv_draw_arc.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_label.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_line.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_page.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_cont.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_list.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_page.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_img.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_chart.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_line.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_table.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_checkbox.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_cpicker.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_bar.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_slider.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_bar.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_led.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_btnmatrix.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_keyboard.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_btnmatrix.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_dropdown.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/../lv_widgets/lv_page.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/../lv_widgets/lv_label.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_roller.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_textarea.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_canvas.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/../lv_widgets/lv_img.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_win.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_tabview.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/../lv_widgets/lv_win.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_tileview.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_msgbox.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_objmask.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/../lv_widgets/lv_cont.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_gauge.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_linemeter.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_linemeter.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_switch.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_arc.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_spinner.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_arc.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_calendar.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/lv_spinbox.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_widgets/../lv_widgets/lv_textarea.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_draw/lv_img_cache.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/lv_api_map.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../src/../lvgl.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../lv_test_assert.h: +../shared/thirdparty/lvgl/tests/lv_test_core/../../lvgl.h: +../shared/thirdparty/lvgl/tests/lv_test_core/lv_test_style.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/tests/lv_test_core/lv_test_style.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/tests/lv_test_core/lv_test_style.o new file mode 100644 index 00000000..e3d81f4d Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/tests/lv_test_core/lv_test_style.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/tests/lv_test_main.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/tests/lv_test_main.d new file mode 100644 index 00000000..5c913009 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/tests/lv_test_main.d @@ -0,0 +1,408 @@ +shared/thirdparty/lvgl/tests/lv_test_main.d \ + shared/thirdparty/lvgl/tests/lv_test_main.o: \ + ../shared/thirdparty/lvgl/tests/lv_test_main.c \ + ../shared/thirdparty/lvgl/tests/../lvgl.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_misc/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + /usr/arm-none-eabi/include/_newlib_version.h \ + /usr/arm-none-eabi/include/sys/_intsup.h \ + /usr/arm-none-eabi/include/sys/_stdint.h ../config/lv_conf.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_misc/lv_task.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdbool.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_misc/lv_mem.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stddef.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_misc/lv_math.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_misc/lv_async.h \ + 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/usr/arm-none-eabi/include/sys/cdefs.h \ + /usr/arm-none-eabi/include/sys/_locale.h \ + /usr/arm-none-eabi/include/strings.h \ + /usr/arm-none-eabi/include/ssp/strings.h \ + /usr/arm-none-eabi/include/ssp/ssp.h \ + /usr/arm-none-eabi/include/sys/string.h \ + /usr/arm-none-eabi/include/ssp/string.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_hal/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_hal/../lv_misc/lv_ll.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_hal/../lv_misc/lv_task.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_hal/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_hal/lv_hal_tick.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_core/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_core/../lv_font/lv_font.h \ + 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../shared/thirdparty/lvgl/tests/../src/lv_core/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_core/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_core/../lv_draw/lv_img_buf.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_core/../lv_draw/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_core/../lv_draw/../lv_misc/lv_mem.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_core/../lv_draw/../lv_misc/lv_types.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_core/lv_obj_style_dec.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_core/lv_group.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_core/lv_indev.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_core/../lv_hal/lv_hal_indev.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_core/../lv_core/lv_group.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_core/lv_refr.h \ + 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\ + ../shared/thirdparty/lvgl/tests/../src/lv_widgets/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_widgets/lv_cont.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_widgets/../lv_core/lv_obj.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_widgets/../lv_core/lv_indev.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_widgets/lv_imgbtn.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_widgets/lv_btn.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_widgets/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_widgets/lv_img.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_widgets/../lv_misc/lv_fs.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_widgets/lv_label.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_widgets/../lv_font/lv_font.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_widgets/../lv_font/lv_symbol_def.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_widgets/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_widgets/../lv_draw/lv_draw.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_widgets/../lv_draw/../lv_conf_internal.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_widgets/../lv_draw/../lv_core/lv_style.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_widgets/../lv_draw/lv_img_decoder.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_widgets/../lv_draw/lv_draw_rect.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_widgets/../lv_draw/lv_draw_label.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_widgets/../lv_draw/lv_draw_img.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_widgets/../lv_draw/lv_draw_line.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_widgets/../lv_draw/lv_draw_triangle.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_widgets/../lv_draw/lv_draw_arc.h \ + ../shared/thirdparty/lvgl/tests/../src/lv_widgets/../lv_draw/lv_draw_blend.h \ + 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+/usr/arm-none-eabi/include/sys/_pthreadtypes.h: +/usr/arm-none-eabi/include/sys/sched.h: +/usr/arm-none-eabi/include/machine/types.h: +/usr/arm-none-eabi/include/sys/stdio.h: +/usr/arm-none-eabi/include/ssp/stdio.h: +/usr/arm-none-eabi/include/stdlib.h: +/usr/arm-none-eabi/include/machine/stdlib.h: +/usr/arm-none-eabi/include/alloca.h: +/usr/arm-none-eabi/include/ssp/stdlib.h: +/usr/arm-none-eabi/include/sys/time.h: +/usr/arm-none-eabi/include/time.h: +/usr/arm-none-eabi/include/machine/time.h: +/usr/arm-none-eabi/include/machine/_time.h: +../shared/thirdparty/lvgl/tests/lv_test_core/lv_test_core.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/tests/lv_test_main.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/tests/lv_test_main.o new file mode 100644 index 00000000..9d39206d Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/tests/lv_test_main.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/tests/lv_test_objx/lv_test_cont.d b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/tests/lv_test_objx/lv_test_cont.d new file mode 100644 index 00000000..c16f976d --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/tests/lv_test_objx/lv_test_cont.d @@ -0,0 +1,367 @@ +shared/thirdparty/lvgl/tests/lv_test_objx/lv_test_cont.d \ + shared/thirdparty/lvgl/tests/lv_test_objx/lv_test_cont.o: \ + ../shared/thirdparty/lvgl/tests/lv_test_objx/lv_test_cont.c \ + ../shared/thirdparty/lvgl/tests/lv_test_objx/../../lvgl.h \ + ../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_misc/lv_log.h \ + ../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_misc/../lv_conf_internal.h \ + /usr/lib/gcc/arm-none-eabi/11.2.1/include/stdint.h \ + /usr/arm-none-eabi/include/stdint.h \ + /usr/arm-none-eabi/include/machine/_default_types.h \ + /usr/arm-none-eabi/include/sys/features.h \ + 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+../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_core/../lv_conf_internal.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_core/lv_style.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_core/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_core/../lv_font/../lv_conf_internal.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_core/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_core/../lv_font/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_core/../lv_misc/lv_color.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_core/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_core/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_core/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_core/../lv_misc/lv_mem.h: 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+../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_core/../lv_draw/../lv_misc/../lv_conf_internal.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_core/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_core/../lv_draw/../lv_misc/lv_area.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_core/../lv_draw/../lv_misc/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_core/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_core/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_core/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_core/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_core/../lv_draw/lv_img_buf.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_core/../lv_draw/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_core/../lv_draw/../lv_misc/lv_mem.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_core/../lv_draw/../lv_misc/lv_types.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_core/lv_obj_style_dec.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_core/lv_group.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_core/lv_obj.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_core/lv_indev.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_core/../lv_hal/lv_hal_indev.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_core/../lv_core/lv_group.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_core/lv_refr.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_core/lv_disp.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_themes/lv_theme.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_themes/../lv_conf_internal.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_themes/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_themes/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_themes/lv_theme_empty.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_themes/lv_theme_template.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_themes/lv_theme_material.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_themes/lv_theme_mono.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_font/lv_font.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_font/lv_font_fmt_txt.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_font/lv_font.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_misc/lv_printf.h: +/usr/lib/gcc/arm-none-eabi/11.2.1/include/stdarg.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_btn.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/../lv_conf_internal.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_cont.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/../lv_core/lv_obj.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/../lv_core/lv_indev.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_imgbtn.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_btn.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_img.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/../lv_misc/lv_fs.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_label.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/../lv_font/lv_font.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/../lv_font/lv_symbol_def.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/../lv_draw/lv_draw.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/../lv_draw/../lv_conf_internal.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/../lv_draw/../lv_core/lv_style.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/../lv_draw/../lv_misc/lv_txt.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/../lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/../lv_draw/lv_draw_rect.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/../lv_draw/lv_draw_label.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/../lv_draw/lv_draw_img.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/../lv_draw/lv_draw_line.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/../lv_draw/lv_draw_triangle.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/../lv_draw/lv_draw_arc.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/../lv_draw/lv_draw_blend.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/../lv_draw/lv_draw_mask.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_label.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_line.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_page.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/../lv_misc/lv_anim.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_cont.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_list.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_page.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_img.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_chart.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_line.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_table.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_checkbox.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_cpicker.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_bar.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_slider.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_bar.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_led.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_btnmatrix.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_keyboard.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_btnmatrix.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_dropdown.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/../lv_widgets/lv_page.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/../lv_widgets/lv_label.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_roller.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_textarea.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_canvas.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/../lv_widgets/lv_img.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_win.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_tabview.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/../lv_widgets/lv_win.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_tileview.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_msgbox.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_objmask.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/../lv_widgets/lv_cont.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_gauge.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_linemeter.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_linemeter.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_switch.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_arc.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_spinner.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_arc.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_calendar.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/lv_spinbox.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_widgets/../lv_widgets/lv_textarea.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_draw/lv_img_cache.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_draw/lv_img_decoder.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/lv_api_map.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../src/../lvgl.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../lv_test_assert.h: +../shared/thirdparty/lvgl/tests/lv_test_objx/../../lvgl.h: diff --git a/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/tests/lv_test_objx/lv_test_cont.o b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/tests/lv_test_objx/lv_test_cont.o new file mode 100644 index 00000000..f5d5c238 Binary files /dev/null and b/software/firmware/oracle_same54n19a/gcc/shared/thirdparty/lvgl/tests/lv_test_objx/lv_test_cont.o differ diff --git a/software/firmware/oracle_same54n19a/gcc/system_same54.c b/software/firmware/oracle_same54n19a/gcc/system_same54.c new file mode 100644 index 00000000..468990e4 --- /dev/null +++ b/software/firmware/oracle_same54n19a/gcc/system_same54.c @@ -0,0 +1,64 @@ +/** + * \file + * + * \brief Low-level initialization functions called upon chip startup. + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#include "same54.h" + +/** + * Initial system clock frequency. The System RC Oscillator (RCSYS) provides + * the source for the main clock at chip startup. + */ +#define __SYSTEM_CLOCK (48000000) + +uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ + +/** + * Initialize the system + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +void SystemInit(void) +{ + // Keep the default device state after reset + SystemCoreClock = __SYSTEM_CLOCK; + return; +} + +/** + * Update SystemCoreClock variable + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +void SystemCoreClockUpdate(void) +{ + // Not implemented + SystemCoreClock = __SYSTEM_CLOCK; + return; +} diff --git a/software/firmware/oracle_same54n19a/hal/documentation/ext_irq.rst b/software/firmware/oracle_same54n19a/hal/documentation/ext_irq.rst new file mode 100644 index 00000000..7dcdc7c5 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/documentation/ext_irq.rst @@ -0,0 +1,39 @@ +============== +EXT IRQ driver +============== + +The External Interrupt driver allows external pins to be +configured as interrupt lines. Each interrupt line can be +individually masked and can generate an interrupt on rising, +falling or both edges, or on high or low levels. Some of +external pin can also be configured to wake up the device +from sleep modes where all clocks have been disabled. +External pins can also generate an event. + +Features +-------- +* Initialization and de-initialization +* Enabling and disabling +* Detect external pins interrupt + +Applications +------------ +* Generate an interrupt on rising, falling or both edges, + or on high or low levels. + +Dependencies +------------ +* GPIO hardware + +Concurrency +----------- +N/A + +Limitations +----------- +N/A + +Knows issues and workarounds +---------------------------- +N/A + diff --git a/software/firmware/oracle_same54n19a/hal/documentation/i2c_master_sync.rst b/software/firmware/oracle_same54n19a/hal/documentation/i2c_master_sync.rst new file mode 100644 index 00000000..77b4f6e9 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/documentation/i2c_master_sync.rst @@ -0,0 +1,87 @@ +============================= +I2C Master synchronous driver +============================= + +I2C (Inter-Integrated Circuit) is a two wire serial interface usually used +for on-board low-speed bi-directional communication between controllers and +peripherals. The master device is responsible for initiating and controlling +all transfers on the I2C bus. Only one master device can be active on the I2C +bus at the time, but the master role can be transferred between devices on the +same I2C bus. I2C uses only two bidirectional open-drain lines, usually +designated SDA (Serial Data Line) and SCL (Serial Clock Line), with pull up +resistors. + +The stop condition is automatically controlled by the driver if the I/O write and +read functions are used, but can be manually controlled by using the +i2c_m_sync_transfer function. + +Often a master accesses different information in the slave by accessing +different registers in the slave. This is done by first sending a message to +the target slave containing the register address, followed by a repeated start +condition (no stop condition between) ending with transferring register data. +This scheme is supported by the i2c_m_sync_cmd_write and i2c_m_sync_cmd_read +function, but limited to 8-bit register addresses. + +I2C Modes (standard mode/fastmode+/highspeed mode) can only be selected in +Atmel Start. If the SCL frequency (baudrate) has changed run-time, make sure to +stick within the SCL clock frequency range supported by the selected mode. +The requested SCL clock frequency is not validated by the +i2c_m_sync_set_baudrate function against the selected I2C mode. + +Features +-------- + + * I2C Master support + * Initialization and de-initialization + * Enabling and disabling + * Run-time bus speed configuration + * Write and read I2C messages + * Slave register access functions (limited to 8-bit address) + * Manual or automatic stop condition generation + * 10- and 7- bit addressing + * I2C Modes supported + +----------------------+-------------------+ + |* Standard/Fast mode | (SCL: 1 - 400kHz) | + +----------------------+-------------------+ + |* Fastmode+ | (SCL: 1 - 1000kHz)| + +----------------------+-------------------+ + |* Highspeed mode | (SCL: 1 - 3400kHz)| + +----------------------+-------------------+ + +Applications +------------ + +* Transfer data to and from one or multiple I2C slaves like I2C connected sensors, data storage or other I2C capable peripherals +* Data communication between micro controllers +* Controlling displays + +Dependencies +------------ + +* I2C Master capable hardware + +Concurrency +----------- + +N/A + +Limitations +----------- + +General +^^^^^^^ + + * System Managmenet Bus (SMBus) not supported. + * Power Management Bus (PMBus) not supported. + +Clock considerations +^^^^^^^^^^^^^^^^^^^^ + +The register value for the requested I2C speed is calculated and placed in the correct register, but not validated if it works correctly with the clock/prescaler settings used for the module. To validate the I2C speed setting use the formula found in the configuration file for the module. Selectable speed is automatically limited within the speed range defined by the I2C mode selected. + +Known issues and workarounds +---------------------------- + +N/A + + diff --git a/software/firmware/oracle_same54n19a/hal/documentation/timer.rst b/software/firmware/oracle_same54n19a/hal/documentation/timer.rst new file mode 100644 index 00000000..c5ca63d1 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/documentation/timer.rst @@ -0,0 +1,52 @@ +============================ +The Timer driver (bare-bone) +============================ + +The Timer driver provides means for delayed and periodical function invocation. + +A timer task is a piece of code (function) executed at a specific time or periodically by the timer after the task has +been added to the timers task queue. The execution delay or period is set in ticks, where one tick is defined as a +configurable number of clock cycles in the hardware timer. Changing the number of clock cycles in a tick automatically +changes execution delays and periods for all tasks in the timers task queue. + +A task has two operation modes, single-shot or repeating mode. In single-shot mode the task is removed from the task queue +and then is executed once, in repeating mode the task reschedules itself automatically after it has executed based on +the period set in the task configuration. +In single-shot mode a task is removed from the task queue before its callback is invoked. It allows an application to +reuse the memory of expired task in the callback. + +Each instance of the Timer driver supports infinite amount of timer tasks, only limited by the amount of RAM available. + +Features +-------- +* Initialization and de-initialization +* Starting and stopping +* Timer tasks - periodical invocation of functions +* Changing and obtaining of the period of a timer + +Applications +------------ +* Delayed and periodical function execution for middle-ware stacks and applications. + +Dependencies +------------ +* Each instance of the driver requires separate hardware timer capable of generating periodic interrupt. + +Concurrency +----------- +The Timer driver is an interrupt driven driver.This means that the interrupt that triggers a task may occur during +the process of adding or removing a task via the driver's API. In such case the interrupt processing is postponed +until the task adding or removing is complete. + +The task queue is not protected from the access by interrupts not used by the driver. Due to this +it is not recommended to add or remove a task from such interrupts: in case if a higher priority interrupt supersedes +the driver's interrupt, adding or removing a task may cause unpredictable behavior of the driver. + +Limitations +----------- +* The driver is designed to work outside of an operating system environment, the task queue is therefore processed in interrupt context which may delay execution of other interrupts. +* If there are a lot of frequently called interrupts with the priority higher than the driver's one, it may cause delay for triggering of a task. + +Knows issues and workarounds +---------------------------- +Not applicable diff --git a/software/firmware/oracle_same54n19a/hal/documentation/usart_async.rst b/software/firmware/oracle_same54n19a/hal/documentation/usart_async.rst new file mode 100644 index 00000000..6bf4a23e --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/documentation/usart_async.rst @@ -0,0 +1,72 @@ +The USART Asynchronous Driver +============================= + +The universal synchronous and asynchronous receiver and transmitter +(USART) is usually used to transfer data from one device to the other. + +The USART driver use a ring buffer to store received data. When the USART +raise the data received interrupt, this data will be stored in the ring buffer +at the next free location. When the ring buffer is full, the next reception +will overwrite the oldest data stored in the ring buffer. There is one +USART_BUFFER_SIZE macro per used hardware instance, e.g. for SERCOM0 the macro +is called SERCOM0_USART_BUFFER_SIZE. + +On the other hand, when sending data over USART, the data is not copied to an +internal buffer, but the data buffer supplied by the user is used. The callback +will only be generated at the end of the buffer and not for each byte. + +User can set action for flow control pins by function usart_set_flow_control, +if the flow control is enabled. All the available states are defined in union +usart_flow_control_state. + +Note that user can set state of flow control pins only if automatic support of +the flow control is not supported by the hardware. + +Features +-------- + +* Initialization/de-initialization +* Enabling/disabling +* Control of the following settings: + + * Baudrate + * UART or USRT communication mode + * Character size + * Data order + * Flow control +* Data transfer: transmission, reception +* Notifications about transfer done or error case via callbacks +* Status information with busy state and transfer count + +Applications +------------ + +They are commonly used in a terminal application or low-speed communication +between devices. + +Dependencies +------------ + +USART capable hardware, with interrupt on each character is sent or +received. + +Concurrency +----------- + +Write buffer should not be changed while data is being sent. + + +Limitations +----------- + +* The driver does not support 9-bit character size. +* The "USART with ISO7816" mode can be only used in ISO7816 capable devices. + And the SCK pin can't be set directly. Application can use a GCLK output PIN + to generate SCK. For example to communicate with a SMARTCARD with ISO7816 + (F = 372 ; D = 1), and baudrate=9600, the SCK pin output frequency should be + config as 372*9600=3571200Hz. More information can be refer to ISO7816 Specification. + +Known issues and workarounds +---------------------------- + +N/A diff --git a/software/firmware/oracle_same54n19a/hal/include/hal_atomic.h b/software/firmware/oracle_same54n19a/hal/include/hal_atomic.h new file mode 100644 index 00000000..82151fc5 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hal_atomic.h @@ -0,0 +1,120 @@ +/** + * \file + * + * \brief Critical sections related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_ATOMIC_H_INCLUDED +#define _HAL_ATOMIC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_helper_atomic + * + *@{ + */ + +/** + * \brief Type for the register holding global interrupt enable flag + */ +typedef uint32_t hal_atomic_t; + +/** + * \brief Helper macro for entering critical sections + * + * This macro is recommended to be used instead of a direct call + * hal_enterCritical() function to enter critical + * sections. No semicolon is required after the macro. + * + * \section atomic_usage Usage Example + * \code + * CRITICAL_SECTION_ENTER() + * Critical code + * CRITICAL_SECTION_LEAVE() + * \endcode + */ +#define CRITICAL_SECTION_ENTER() \ + { \ + volatile hal_atomic_t __atomic; \ + atomic_enter_critical(&__atomic); + +/** + * \brief Helper macro for leaving critical sections + * + * This macro is recommended to be used instead of a direct call + * hal_leaveCritical() function to leave critical + * sections. No semicolon is required after the macro. + */ +#define CRITICAL_SECTION_LEAVE() \ + atomic_leave_critical(&__atomic); \ + } + +/** + * \brief Disable interrupts, enter critical section + * + * Disables global interrupts. Supports nested critical sections, + * so that global interrupts are only re-enabled + * upon leaving the outermost nested critical section. + * + * \param[out] atomic The pointer to a variable to store the value of global + * interrupt enable flag + */ +void atomic_enter_critical(hal_atomic_t volatile *atomic); + +/** + * \brief Exit atomic section + * + * Enables global interrupts. Supports nested critical sections, + * so that global interrupts are only re-enabled + * upon leaving the outermost nested critical section. + * + * \param[in] atomic The pointer to a variable, which stores the latest stored + * value of the global interrupt enable flag + */ +void atomic_leave_critical(hal_atomic_t volatile *atomic); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t atomic_get_version(void); +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_ATOMIC_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/include/hal_cache.h b/software/firmware/oracle_same54n19a/hal/include/hal_cache.h new file mode 100644 index 00000000..071486b7 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hal_cache.h @@ -0,0 +1,96 @@ +/** + * \file + * + * \brief HAL cache functionality implementation. + * + * Copyright (c)2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef HAL_CACHE_H_ +#define HAL_CACHE_H_ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Enable cache module + * + * \param[in] pointer pointing to the starting address of cache module + * + * \return status of operation + */ +int32_t cache_enable(const void *hw); + +/** + * \brief Disable cache module + * + * \param[in] pointer pointing to the starting address of cache module + * + * \return status of operation + */ +int32_t cache_disable(const void *hw); + +/** + * \brief Initialize cache module + * + * This function initialize cache module configuration. + * + * \return status of operation + */ +int32_t cache_init(void); + +/** + * \brief Configure cache module + * + * \param[in] pointer pointing to the starting address of cache module + * \param[in] cache configuration structure pointer + * + * \return status of operation + */ +int32_t cache_configure(const void *hw, struct _cache_cfg *cache); + +/** + * \brief Invalidate entire cache entries + * + * \param[in] pointer pointing to the starting address of cache module + * + * \return status of operation + */ +int32_t cache_invalidate_all(const void *hw); + +#ifdef __cplusplus +} +#endif + +#endif /* HAL_CACHE_H_ */ diff --git a/software/firmware/oracle_same54n19a/hal/include/hal_delay.h b/software/firmware/oracle_same54n19a/hal/include/hal_delay.h new file mode 100644 index 00000000..9d4aa5c1 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hal_delay.h @@ -0,0 +1,89 @@ +/** + * \file + * + * \brief HAL delay related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +#ifndef _HAL_DELAY_H_INCLUDED +#define _HAL_DELAY_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_delay Delay Driver + * + *@{ + */ + +/** + * \brief Initialize Delay driver + * + * \param[in] hw The pointer to hardware instance + */ +void delay_init(void *const hw); + +/** + * \brief Perform delay in us + * + * This function performs delay for the given amount of microseconds. + * + * \param[in] us The amount delay in us + */ +void delay_us(const uint16_t us); + +/** + * \brief Perform delay in ms + * + * This function performs delay for the given amount of milliseconds. + * + * \param[in] ms The amount delay in ms + */ +void delay_ms(const uint16_t ms); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t delay_get_version(void); + +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_DELAY_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/include/hal_ext_irq.h b/software/firmware/oracle_same54n19a/hal/include/hal_ext_irq.h new file mode 100644 index 00000000..a7c26005 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hal_ext_irq.h @@ -0,0 +1,118 @@ +/** + * \file + * + * \brief External interrupt functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_EXT_IRQ_H_INCLUDED +#define _HAL_EXT_IRQ_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_ext_irq + * + * @{ + */ + +/** + * \brief External IRQ callback type + */ +typedef void (*ext_irq_cb_t)(void); + +/** + * \brief Initialize external IRQ component, if any + * + * \return Initialization status. + * \retval -1 External IRQ module is already initialized + * \retval 0 The initialization is completed successfully + */ +int32_t ext_irq_init(void); + +/** + * \brief Deinitialize external IRQ, if any + * + * \return De-initialization status. + * \retval -1 External IRQ module is already deinitialized + * \retval 0 The de-initialization is completed successfully + */ +int32_t ext_irq_deinit(void); + +/** + * \brief Register callback for the given external interrupt + * + * \param[in] pin Pin to enable external IRQ on + * \param[in] cb Callback function + * + * \return Registration status. + * \retval -1 Passed parameters were invalid + * \retval 0 The callback registration is completed successfully + */ +int32_t ext_irq_register(const uint32_t pin, ext_irq_cb_t cb); + +/** + * \brief Enable external IRQ + * + * \param[in] pin Pin to enable external IRQ on + * + * \return Enabling status. + * \retval -1 Passed parameters were invalid + * \retval 0 The enabling is completed successfully + */ +int32_t ext_irq_enable(const uint32_t pin); + +/** + * \brief Disable external IRQ + * + * \param[in] pin Pin to enable external IRQ on + * + * \return Disabling status. + * \retval -1 Passed parameters were invalid + * \retval 0 The disabling is completed successfully + */ +int32_t ext_irq_disable(const uint32_t pin); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t ext_irq_get_version(void); +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_EXT_IRQ_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/include/hal_gpio.h b/software/firmware/oracle_same54n19a/hal/include/hal_gpio.h new file mode 100644 index 00000000..fbfa2d4a --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hal_gpio.h @@ -0,0 +1,201 @@ +/** + * \file + * + * \brief Port + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ +#ifndef _HAL_GPIO_INCLUDED_ +#define _HAL_GPIO_INCLUDED_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Set gpio pull mode + * + * Set pin pull mode, non existing pull modes throws an fatal assert + * + * \param[in] pin The pin number for device + * \param[in] pull_mode GPIO_PULL_DOWN = Pull pin low with internal resistor + * GPIO_PULL_UP = Pull pin high with internal resistor + * GPIO_PULL_OFF = Disable pin pull mode + */ +static inline void gpio_set_pin_pull_mode(const uint8_t pin, const enum gpio_pull_mode pull_mode) +{ + _gpio_set_pin_pull_mode((enum gpio_port)GPIO_PORT(pin), pin & 0x1F, pull_mode); +} + +/** + * \brief Set pin function + * + * Select which function a pin will be used for + * + * \param[in] pin The pin number for device + * \param[in] function The pin function is given by a 32-bit wide bitfield + * found in the header files for the device + * + */ +static inline void gpio_set_pin_function(const uint32_t pin, uint32_t function) +{ + _gpio_set_pin_function(pin, function); +} + +/** + * \brief Set port data direction + * + * Select if the pin data direction is input, output or disabled. + * If disabled state is not possible, this function throws an assert. + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to the + * corresponding pin + * \param[in] direction GPIO_DIRECTION_IN = Data direction in + * GPIO_DIRECTION_OUT = Data direction out + * GPIO_DIRECTION_OFF = Disables the pin + * (low power state) + */ +static inline void gpio_set_port_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction) +{ + _gpio_set_direction(port, mask, direction); +} + +/** + * \brief Set gpio data direction + * + * Select if the pin data direction is input, output or disabled. + * If disabled state is not possible, this function throws an assert. + * + * \param[in] pin The pin number for device + * \param[in] direction GPIO_DIRECTION_IN = Data direction in + * GPIO_DIRECTION_OUT = Data direction out + * GPIO_DIRECTION_OFF = Disables the pin + * (low power state) + */ +static inline void gpio_set_pin_direction(const uint8_t pin, const enum gpio_direction direction) +{ + _gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction); +} + +/** + * \brief Set port level + * + * Sets output level on the pins defined by the bit mask + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply port level to the corresponding + * pin + * \param[in] level true = Pin levels set to "high" state + * false = Pin levels set to "low" state + */ +static inline void gpio_set_port_level(const enum gpio_port port, const uint32_t mask, const bool level) +{ + _gpio_set_level(port, mask, level); +} + +/** + * \brief Set gpio level + * + * Sets output level on a pin + * + * \param[in] pin The pin number for device + * \param[in] level true = Pin level set to "high" state + * false = Pin level set to "low" state + */ +static inline void gpio_set_pin_level(const uint8_t pin, const bool level) +{ + _gpio_set_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), level); +} + +/** + * \brief Toggle out level on pins + * + * Toggle the pin levels on pins defined by bit mask + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means toggle pin level to the corresponding + * pin + */ +static inline void gpio_toggle_port_level(const enum gpio_port port, const uint32_t mask) +{ + _gpio_toggle_level(port, mask); +} + +/** + * \brief Toggle output level on pin + * + * Toggle the pin levels on pins defined by bit mask + * + * \param[in] pin The pin number for device + */ +static inline void gpio_toggle_pin_level(const uint8_t pin) +{ + _gpio_toggle_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin)); +} + +/** + * \brief Get input level on pins + * + * Read the input level on pins connected to a port + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + */ +static inline uint32_t gpio_get_port_level(const enum gpio_port port) +{ + return _gpio_get_level(port); +} + +/** + * \brief Get level on pin + * + * Reads the level on pins connected to a port + * + * \param[in] pin The pin number for device + */ +static inline bool gpio_get_pin_level(const uint8_t pin) +{ + return (bool)(_gpio_get_level((enum gpio_port)GPIO_PORT(pin)) & (0x01U << GPIO_PIN(pin))); +} +/** + * \brief Get current driver version + */ +uint32_t gpio_get_version(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/software/firmware/oracle_same54n19a/hal/include/hal_i2c_m_sync.h b/software/firmware/oracle_same54n19a/hal/include/hal_i2c_m_sync.h new file mode 100644 index 00000000..24afd639 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hal_i2c_m_sync.h @@ -0,0 +1,244 @@ +/** + * \file + * + * \brief Sync I2C Hardware Abstraction Layer(HAL) declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_I2C_M_SYNC_H_INCLUDED +#define _HAL_I2C_M_SYNC_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_i2c_master_sync + * + * @{ + */ + +#define I2C_M_MAX_RETRY 1 + +/** + * \brief I2C descriptor structure, embed i2c_device & i2c_interface + */ +struct i2c_m_sync_desc { + struct _i2c_m_sync_device device; + struct io_descriptor io; + uint16_t slave_addr; +}; + +/** + * \brief Initialize synchronous I2C interface + * + * This function initializes the given I/O descriptor to be used as a + * synchronous I2C interface descriptor. + * It checks if the given hardware is not initialized and if the given hardware + * is permitted to be initialized. + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status. + * \retval -1 The passed parameters were invalid or the interface is already initialized + * \retval 0 The initialization is completed successfully + */ +int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw); + +/** + * \brief Deinitialize I2C interface + * + * This function deinitializes the given I/O descriptor. + * It checks if the given hardware is initialized and if the given hardware is permitted to be deinitialized. + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * + * \return Uninitialization status. + * \retval -1 The passed parameters were invalid or the interface is already deinitialized + * \retval 0 The de-initialization is completed successfully + */ +int32_t i2c_m_sync_deinit(struct i2c_m_sync_desc *i2c); + +/** + * \brief Set the slave device address + * + * This function sets the next transfer target slave I2C device address. + * It takes no effect to any already started access. + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] addr The slave address to access + * \param[in] addr_len The slave address length, can be I2C_M_TEN or I2C_M_SEVEN + * + * \return Masked slave address. The mask is a maximum 10-bit address, and 10th + * bit is set if a 10-bit address is used + */ +int32_t i2c_m_sync_set_slaveaddr(struct i2c_m_sync_desc *i2c, int16_t addr, int32_t addr_len); + +/** + * \brief Set baudrate + * + * This function sets the I2C device to the specified baudrate. + * It only takes effect when the hardware is disabled. + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] clkrate Unused parameter. Should always be 0 + * \param[in] baudrate The baudrate value set to master + * + * \return Whether successfully set the baudrate + * \retval -1 The passed parameters were invalid or the device is already enabled + * \retval 0 The baudrate set is completed successfully + */ +int32_t i2c_m_sync_set_baudrate(struct i2c_m_sync_desc *i2c, uint32_t clkrate, uint32_t baudrate); + +/** + * \brief Sync version of enable hardware + * + * This function enables the I2C device, and then waits for this enabling operation to be done + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * + * \return Whether successfully enable the device + * \retval -1 The passed parameters were invalid or the device enable failed + * \retval 0 The hardware enabling is completed successfully + */ +int32_t i2c_m_sync_enable(struct i2c_m_sync_desc *i2c); + +/** + * \brief Sync version of disable hardware + * + * This function disables the I2C device and then waits for this disabling operation to be done + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * + * \return Whether successfully disable the device + * \retval -1 The passed parameters were invalid or the device disable failed + * \retval 0 The hardware disabling is completed successfully + */ +int32_t i2c_m_sync_disable(struct i2c_m_sync_desc *i2c); + +/** + * \brief Sync version of write command to I2C slave + * + * This function will write the value to a specified register in the I2C slave device and + * then wait for this operation to be done. + * + * The sequence of this routine is + * sta->address(write)->ack->reg address->ack->resta->address(write)->ack->reg value->nack->stt + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] reg The internal address/register of the I2C slave device + * \param[in] buffer The buffer holding data to write to the I2C slave device + * \param[in] length The length (in bytes) to write to the I2C slave device + * + * \return Whether successfully write to the device + * \retval <0 The passed parameters were invalid or write fail + * \retval 0 Writing to register is completed successfully + */ +int32_t i2c_m_sync_cmd_write(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length); + +/** + * \brief Sync version of read register value from I2C slave + * + * This function will read a byte value from a specified register in the I2C slave device and + * then wait for this operation to be done. + * + * The sequence of this routine is + * sta->address(write)->ack->reg address->ack->resta->address(read)->ack->reg value->nack->stt + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] reg The internal address/register of the I2C slave device + * \param[in] buffer The buffer to hold the read data from the I2C slave device + * \param[in] length The length (in bytes) to read from the I2C slave device + * + * \return Whether successfully read from the device + * \retval <0 The passed parameters were invalid or read fail + * \retval 0 Reading from register is completed successfully + */ +int32_t i2c_m_sync_cmd_read(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length); + +/** + * \brief Sync version of transfer message to/from the I2C slave + * + * This function will transfer a message between the I2C slave and the master. This function will wait for the operation + * to be done. + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * \param[in] msg An i2c_m_msg struct + * + * \return The status of the operation + * \retval 0 Operation completed successfully + * \retval <0 Operation failed + */ +int32_t i2c_m_sync_transfer(struct i2c_m_sync_desc *const i2c, struct _i2c_m_msg *msg); + +/** + * \brief Sync version of send stop condition on the i2c bus + * + * This function will create a stop condition on the i2c bus to release the bus + * + * \param[in] i2c An I2C descriptor, which is used to communicate through I2C + * + * \return The status of the operation + * \retval 0 Operation completed successfully + * \retval <0 Operation failed + */ +int32_t i2c_m_sync_send_stop(struct i2c_m_sync_desc *const i2c); + +/** + * \brief Return I/O descriptor for this I2C instance + * + * This function will return a I/O instance for this I2C driver instance + * + * \param[in] i2c_m_sync_desc An I2C descriptor, which is used to communicate through I2C + * \param[in] io_descriptor A pointer to an I/O descriptor pointer type + * + * \return Error code + * \retval 0 No error detected + * \retval <0 Error code + */ +int32_t i2c_m_sync_get_io_descriptor(struct i2c_m_sync_desc *const i2c, struct io_descriptor **io); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t i2c_m_sync_get_version(void); + +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/software/firmware/oracle_same54n19a/hal/include/hal_init.h b/software/firmware/oracle_same54n19a/hal/include/hal_init.h new file mode 100644 index 00000000..d7bc6fe2 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hal_init.h @@ -0,0 +1,72 @@ +/** + * \file + * + * \brief HAL initialization related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_INIT_H_INCLUDED +#define _HAL_INIT_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_helper_init Init Driver + * + *@{ + */ + +/** + * \brief Initialize the hardware abstraction layer + * + * This function calls the various initialization functions. + * Currently the following initialization functions are supported: + * - System clock initialization + */ +static inline void init_mcu(void) +{ + _init_chip(); +} + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t init_get_version(void); + +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_INIT_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/include/hal_io.h b/software/firmware/oracle_same54n19a/hal/include/hal_io.h new file mode 100644 index 00000000..f50401d7 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hal_io.h @@ -0,0 +1,110 @@ +/** + * \file + * + * \brief I/O related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_IO_INCLUDED +#define _HAL_IO_INCLUDED + +/** + * \addtogroup doc_driver_hal_helper_io I/O Driver + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief I/O descriptor + * + * The I/O descriptor forward declaration. + */ +struct io_descriptor; + +/** + * \brief I/O write function pointer type + */ +typedef int32_t (*io_write_t)(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); + +/** + * \brief I/O read function pointer type + */ +typedef int32_t (*io_read_t)(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); + +/** + * \brief I/O descriptor + */ +struct io_descriptor { + io_write_t write; /*! The write function pointer. */ + io_read_t read; /*! The read function pointer. */ +}; + +/** + * \brief I/O write interface + * + * This function writes up to \p length of bytes to a given I/O descriptor. + * It returns the number of bytes actually write. + * + * \param[in] descr An I/O descriptor to write + * \param[in] buf The buffer pointer to story the write data + * \param[in] length The number of bytes to write + * + * \return The number of bytes written + */ +int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); + +/** + * \brief I/O read interface + * + * This function reads up to \p length bytes from a given I/O descriptor, and + * stores it in the buffer pointed to by \p buf. It returns the number of bytes + * actually read. + * + * \param[in] descr An I/O descriptor to read + * \param[in] buf The buffer pointer to story the read data + * \param[in] length The number of bytes to read + * + * \return The number of bytes actually read. This number can be less than the + * requested length. E.g., in a driver that uses ring buffer for + * reception, it may depend on the availability of data in the + * ring buffer. + */ +int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HAL_IO_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/include/hal_sleep.h b/software/firmware/oracle_same54n19a/hal/include/hal_sleep.h new file mode 100644 index 00000000..b90ef6a5 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hal_sleep.h @@ -0,0 +1,74 @@ +/** + * \file + * + * \brief Sleep related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_SLEEP_H_INCLUDED +#define _HAL_SLEEP_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_helper_sleep + * + *@{ + */ + +/** + * \brief Set the sleep mode of the device and put the MCU to sleep + * + * For an overview of which systems are disabled in sleep for the different + * sleep modes, see the data sheet. + * + * \param[in] mode Sleep mode to use + * + * \return The status of a sleep request + * \retval -1 The requested sleep mode was invalid or not available + * \retval 0 The operation completed successfully, returned after leaving the + * sleep + */ +int sleep(const uint8_t mode); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t sleep_get_version(void); +/**@}*/ +#ifdef __cplusplus +} +#endif +#endif /* _HAL_SLEEP_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/include/hal_timer.h b/software/firmware/oracle_same54n19a/hal/include/hal_timer.h new file mode 100644 index 00000000..43a1ff47 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hal_timer.h @@ -0,0 +1,206 @@ +/** + * \file + * + * \brief Timer task functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_TIMER_H_INCLUDED +#define _HAL_TIMER_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_timer + * + * @{ + */ + +/** + * \brief Timer mode type + */ +enum timer_task_mode { TIMER_TASK_ONE_SHOT, TIMER_TASK_REPEAT }; + +/** + * \brief Timer task descriptor + * + * The timer task descriptor forward declaration. + */ +struct timer_task; + +/** + * \brief Timer task callback function type + */ +typedef void (*timer_cb_t)(const struct timer_task *const timer_task); + +/** + * \brief Timer task structure + */ +struct timer_task { + struct list_element elem; /*! List element. */ + uint32_t time_label; /*! Absolute timer start time. */ + + uint32_t interval; /*! Number of timer ticks before calling the task. */ + timer_cb_t cb; /*! Function pointer to the task. */ + enum timer_task_mode mode; /*! Task mode: one shot or repeat. */ +}; + +/** + * \brief Timer structure + */ +struct timer_descriptor { + struct _timer_device device; + uint32_t time; + struct list_descriptor tasks; /*! Timer tasks list. */ + volatile uint8_t flags; +}; + +/** + * \brief Initialize timer + * + * This function initializes the given timer. + * It checks if the given hardware is not initialized and if the given hardware + * is permitted to be initialized. + * + * \param[out] descr A timer descriptor to initialize + * \param[in] hw The pointer to the hardware instance + * \param[in] func The pointer to a set of function pointers + * + * \return Initialization status. + */ +int32_t timer_init(struct timer_descriptor *const descr, void *const hw, struct _timer_hpl_interface *const func); + +/** + * \brief Deinitialize timer + * + * This function deinitializes the given timer. + * It checks if the given hardware is initialized and if the given hardware is + * permitted to be deinitialized. + * + * \param[in] descr A timer descriptor to deinitialize + * + * \return De-initialization status. + */ +int32_t timer_deinit(struct timer_descriptor *const descr); + +/** + * \brief Start timer + * + * This function starts the given timer. + * It checks if the given hardware is initialized. + * + * \param[in] descr The timer descriptor of a timer to start + * + * \return Timer starting status. + */ +int32_t timer_start(struct timer_descriptor *const descr); + +/** + * \brief Stop timer + * + * This function stops the given timer. + * It checks if the given hardware is initialized. + * + * \param[in] descr The timer descriptor of a timer to stop + * + * \return Timer stopping status. + */ +int32_t timer_stop(struct timer_descriptor *const descr); + +/** + * \brief Set amount of clock cycles per timer tick + * + * This function sets the amount of clock cycles per timer tick for the given timer. + * It checks if the given hardware is initialized. + * + * \param[in] descr The timer descriptor of a timer to stop + * \param[in] clock_cycles The amount of clock cycles per tick to set + * + * \return Setting clock cycles amount status. + */ +int32_t timer_set_clock_cycles_per_tick(struct timer_descriptor *const descr, const uint32_t clock_cycles); + +/** + * \brief Retrieve the amount of clock cycles in a tick + * + * This function retrieves how many clock cycles there are in a single timer tick. + * It checks if the given hardware is initialized. + * + * \param[in] descr The timer descriptor of a timer to convert ticks to + * clock cycles + * \param[out] cycles The amount of clock cycles + * + * \return The status of clock cycles retrieving. + */ +int32_t timer_get_clock_cycles_in_tick(const struct timer_descriptor *const descr, uint32_t *const cycles); + +/** + * \brief Add timer task + * + * This function adds the given timer task to the given timer. + * It checks if the given hardware is initialized. + * + * \param[in] descr The timer descriptor of a timer to add task to + * \param[in] task A task to add + * + * \return Timer's task adding status. + */ +int32_t timer_add_task(struct timer_descriptor *const descr, struct timer_task *const task); + +/** + * \brief Remove timer task + * + * This function removes the given timer task from the given timer. + * It checks if the given hardware is initialized. + * + * \param[in] descr The timer descriptor of a timer to remove task from + * \param[in] task A task to remove + * + * \return Timer's task removing status. + */ +int32_t timer_remove_task(struct timer_descriptor *const descr, const struct timer_task *const task); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t timer_get_version(void); +/**@}*/ + +#ifdef __cplusplus +} +#endif + +#endif /* _HAL_TIMER_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/include/hal_usart_async.h b/software/firmware/oracle_same54n19a/hal/include/hal_usart_async.h new file mode 100644 index 00000000..3a6de391 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hal_usart_async.h @@ -0,0 +1,339 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HAL_USART_ASYNC_H_INCLUDED +#define _HAL_USART_ASYNC_H_INCLUDED + +#include "hal_io.h" +#include +#include + +/** + * \addtogroup doc_driver_hal_usart_async + * + * @{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART descriptor + * + * The USART descriptor forward declaration. + */ +struct usart_async_descriptor; + +/** + * \brief USART callback type + */ +typedef void (*usart_cb_t)(const struct usart_async_descriptor *const descr); + +/** + * \brief USART callback types + */ +enum usart_async_callback_type { USART_ASYNC_RXC_CB, USART_ASYNC_TXC_CB, USART_ASYNC_ERROR_CB }; + +/** + * \brief USART callbacks + */ +struct usart_async_callbacks { + usart_cb_t tx_done; + usart_cb_t rx_done; + usart_cb_t error; +}; + +/** \brief USART status + * Status descriptor holds the current status of transfer. + */ +struct usart_async_status { + /** Status flags */ + uint32_t flags; + /** Number of characters transmitted */ + uint16_t txcnt; + /** Number of characters receviced */ + uint16_t rxcnt; +}; + +/** + * \brief Asynchronous USART descriptor structure + */ +struct usart_async_descriptor { + struct io_descriptor io; + struct _usart_async_device device; + struct usart_async_callbacks usart_cb; + uint32_t stat; + + struct ringbuffer rx; + uint16_t tx_por; + uint8_t * tx_buffer; + uint16_t tx_buffer_length; +}; + +/** USART write busy */ +#define USART_ASYNC_STATUS_BUSY 0x0001 + +/** + * \brief Initialize USART interface + * + * This function initializes the given I/O descriptor to be used as USART + * interface descriptor. + * It checks if the given hardware is not initialized and if the given hardware + * is permitted to be initialized. + * + * \param[out] descr A USART descriptor which is used to communicate via the USART + * \param[in] hw The pointer to the hardware instance + * \param[in] rx_buffer An RX buffer + * \param[in] rx_buffer_length The length of the buffer above + * \param[in] func The pointer to a set of function pointers + * + * \return Initialization status. + * \retval -1 Passed parameters were invalid or the interface is already + * initialized + * \retval 0 The initialization is completed successfully + */ +int32_t usart_async_init(struct usart_async_descriptor *const descr, void *const hw, uint8_t *const rx_buffer, + const uint16_t rx_buffer_length, void *const func); + +/** + * \brief Deinitialize USART interface + * + * This function deinitializes the given I/O descriptor. + * It checks if the given hardware is initialized and if the given hardware + * is permitted to be deinitialized. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return De-initialization status. + */ +int32_t usart_async_deinit(struct usart_async_descriptor *const descr); + +/** + * \brief Enable USART interface + * + * Enables the USART interface + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return Enabling status. + */ +int32_t usart_async_enable(struct usart_async_descriptor *const descr); + +/** + * \brief Disable USART interface + * + * Disables the USART interface + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return Disabling status. + */ +int32_t usart_async_disable(struct usart_async_descriptor *const descr); + +/** + * \brief Retrieve I/O descriptor + * + * This function retrieves the I/O descriptor of the given USART descriptor. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[out] io An I/O descriptor to retrieve + * + * \return The status of I/O descriptor retrieving. + */ +int32_t usart_async_get_io_descriptor(struct usart_async_descriptor *const descr, struct io_descriptor **io); + +/** + * \brief Register USART callback + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] type Callback type + * \param[in] cb A callback function + * + * \return The status of callback assignment. + * \retval -1 Passed parameters were invalid or the interface is not initialized + * \retval 0 A callback is registered successfully + */ +int32_t usart_async_register_callback(struct usart_async_descriptor *const descr, + const enum usart_async_callback_type type, usart_cb_t cb); + +/** + * \brief Specify action for flow control pins + * + * This function sets action (or state) for flow control pins if + * the flow control is enabled. + * It sets state of flow control pins only if automatic support of + * the flow control is not supported by the hardware. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] state A state to set the flow control pins + * + * \return The status of flow control action setup. + */ +int32_t usart_async_set_flow_control(struct usart_async_descriptor *const descr, + const union usart_flow_control_state state); + +/** + * \brief Set USART baud rate + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] baud_rate A baud rate to set + * + * \return The status of baud rate setting. + */ +int32_t usart_async_set_baud_rate(struct usart_async_descriptor *const descr, const uint32_t baud_rate); + +/** + * \brief Set USART data order + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] data_order A data order to set + * + * \return The status of data order setting. + */ +int32_t usart_async_set_data_order(struct usart_async_descriptor *const descr, const enum usart_data_order data_order); + +/** + * \brief Set USART mode + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] mode A mode to set + * + * \return The status of mode setting. + */ +int32_t usart_async_set_mode(struct usart_async_descriptor *const descr, const enum usart_mode mode); + +/** + * \brief Set USART parity + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] parity A parity to set + * + * \return The status of parity setting. + */ +int32_t usart_async_set_parity(struct usart_async_descriptor *const descr, const enum usart_parity parity); + +/** + * \brief Set USART stop bits + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] stop_bits Stop bits to set + * + * \return The status of stop bits setting. + */ +int32_t usart_async_set_stopbits(struct usart_async_descriptor *const descr, const enum usart_stop_bits stop_bits); + +/** + * \brief Set USART character size + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[in] size A character size to set + * + * \return The status of character size setting. + */ +int32_t usart_async_set_character_size(struct usart_async_descriptor *const descr, + const enum usart_character_size size); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the flow control pins + * if the flow control is enabled. + * + * The function can return USART_FLOW_CONTROL_STATE_UNAVAILABLE in case + * if the flow control is done by the hardware + * and the pins state cannot be read out. + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[out] state The state of flow control pins + * + * \return The status of flow control state reading. + */ +int32_t usart_async_flow_control_status(const struct usart_async_descriptor *const descr, + union usart_flow_control_state *const state); + +/** + * \brief Check if the USART transmitter is empty + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return The status of USART TX empty checking. + * \retval 0 The USART transmitter is not empty + * \retval 1 The USART transmitter is empty + */ +int32_t usart_async_is_tx_empty(const struct usart_async_descriptor *const descr); + +/** + * \brief Check if the USART receiver is not empty + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * + * \return The status of the USART RX empty checking. + * \retval 1 The USART receiver is not empty + * \retval 0 The USART receiver is empty + */ +int32_t usart_async_is_rx_not_empty(const struct usart_async_descriptor *const descr); + +/** + * \brief Retrieve the current interface status + * + * \param[in] descr A USART descriptor which is used to communicate via USART + * \param[out] status The state of USART + * + * \return The status of USART status retrieving. + */ +int32_t usart_async_get_status(struct usart_async_descriptor *const descr, struct usart_async_status *const status); + +/** + * \brief flush USART ringbuf + * + * This function flush USART RX ringbuf. + * + * \param[in] descr The pointer to USART descriptor + * + * \return ERR_NONE + */ +int32_t usart_async_flush_rx_buffer(struct usart_async_descriptor *const descr); + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version. + */ +uint32_t usart_async_get_version(void); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HAL_USART_ASYNC_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/include/hpl_cmcc.h b/software/firmware/oracle_same54n19a/hal/include/hpl_cmcc.h new file mode 100644 index 00000000..cb260913 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hpl_cmcc.h @@ -0,0 +1,277 @@ +/** + * \file + * + * \brief Generic CMCC(Cortex M Cache Controller) related functionality. + * + * Copyright (c)2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#ifndef HPL_CMCC_H_ +#define HPL_CMCC_H_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +/** + * \Cache driver MACROS + */ +#define CMCC_DISABLE 0U +#define CMCC_ENABLE 1U +#define IS_CMCC_DISABLED 0U +#define IS_CMCC_ENABLED 1U +#define CMCC_WAY_NOS 4U +#define CMCC_LINE_NOS 64U +#define CMCC_MONITOR_DISABLE 0U + +/** + * \brief Cache size configurations + */ +enum conf_cache_size { CONF_CSIZE_1KB = 0u, CONF_CSIZE_2KB, CONF_CSIZE_4KB }; + +/** + * \brief Way Numbers + */ +enum way_num_index { WAY0 = 1u, WAY1 = 2u, WAY2 = 4u, WAY3 = 8 }; + +/** + * \brief Cache monitor configurations + */ +enum conf_cache_monitor { CYCLE_COUNT = 0u, IHIT_COUNT, DHIT_COUNT }; + +/** + * \brief Cache configuration structure + */ +struct _cache_cfg { + enum conf_cache_size cache_size; + bool data_cache_disable; + bool inst_cache_disable; + bool gclk_gate_disable; +}; + +/** + * \brief Cache enable status + */ +static inline bool _is_cache_enabled(const void *hw) +{ + return (hri_cmcc_get_SR_CSTS_bit(hw) == IS_CMCC_ENABLED ? true : false); +} + +/** + * \brief Cache disable status + */ +static inline bool _is_cache_disabled(const void *hw) +{ + return (hri_cmcc_get_SR_CSTS_bit(hw) == IS_CMCC_DISABLED ? true : false); +} + +/** + * \brief Cache enable + */ +static inline int32_t _cmcc_enable(const void *hw) +{ + int32_t return_value; + + if (_is_cache_disabled(hw)) { + hri_cmcc_write_CTRL_reg(hw, CMCC_CTRL_CEN); + return_value = _is_cache_enabled(hw) == true ? ERR_NONE : ERR_FAILURE; + } else { + return_value = ERR_NO_CHANGE; + } + + return return_value; +} + +/** + * \brief Cache disable + */ +static inline int32_t _cmcc_disable(const void *hw) +{ + hri_cmcc_write_CTRL_reg(hw, (CMCC_DISABLE << CMCC_CTRL_CEN_Pos)); + while (!(_is_cache_disabled(hw))) + ; + + return ERR_NONE; +} + +/** + * \brief Initialize Cache Module + * + * This function initialize low level cmcc module configuration. + * + * \return initialize status + */ +int32_t _cmcc_init(void); + +/** + * \brief Configure CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] cache configuration structure pointer + * + * \return status of operation + */ +int32_t _cmcc_configure(const void *hw, struct _cache_cfg *cache_ctrl); + +/** + * \brief Enable data cache in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] boolean 1 -> Enable the data cache, 0 -> disable the data cache + * + * \return status of operation + */ +int32_t _cmcc_enable_data_cache(const void *hw, bool value); + +/** + * \brief Enable instruction cache in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] boolean 1 -> Enable the inst cache, 0 -> disable the inst cache + * + * \return status of operation + */ +int32_t _cmcc_enable_inst_cache(const void *hw, bool value); + +/** + * \brief Enable clock gating in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] boolean 1 -> Enable the clock gate, 0 -> disable the clock gate + * + * \return status of operation + */ +int32_t _cmcc_enable_clock_gating(const void *hw, bool value); + +/** + * \brief Configure the cache size in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from cache size configuration enumerator + * 0->1K, 1->2K, 2->4K(default) + * + * \return status of operation + */ +int32_t _cmcc_configure_cache_size(const void *hw, enum conf_cache_size size); + +/** + * \brief Lock the mentioned WAY in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from "way_num_index" enumerator + * + * \return status of operation + */ +int32_t _cmcc_lock_way(const void *hw, enum way_num_index); + +/** + * \brief Unlock the mentioned WAY in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from "way_num_index" enumerator + * + * \return status of operation + */ +int32_t _cmcc_unlock_way(const void *hw, enum way_num_index); + +/** + * \brief Invalidate the mentioned cache line in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from "way_num" enumerator (valid arg is 0-3) + * \param[in] line number (valid arg is 0-63 as each way will have 64 lines) + * + * \return status of operation + */ +int32_t _cmcc_invalidate_by_line(const void *hw, uint8_t way_num, uint8_t line_num); + +/** + * \brief Invalidate entire cache entries in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return status of operation + */ +int32_t _cmcc_invalidate_all(const void *hw); + +/** + * \brief Configure cache monitor in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from cache monitor configurations enumerator + * + * \return status of operation + */ +int32_t _cmcc_configure_monitor(const void *hw, enum conf_cache_monitor monitor_cfg); + +/** + * \brief Enable cache monitor in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return status of operation + */ +int32_t _cmcc_enable_monitor(const void *hw); + +/** + * \brief Disable cache monitor in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return status of operation + */ +int32_t _cmcc_disable_monitor(const void *hw); + +/** + * \brief Reset cache monitor in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return status of operation + */ +int32_t _cmcc_reset_monitor(const void *hw); + +/** + * \brief Get cache monitor event counter value from CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return event counter value + */ +uint32_t _cmcc_get_monitor_event_count(const void *hw); + +#ifdef __cplusplus +} +#endif +#endif /* HPL_CMCC_H_ */ diff --git a/software/firmware/oracle_same54n19a/hal/include/hpl_core.h b/software/firmware/oracle_same54n19a/hal/include/hpl_core.h new file mode 100644 index 00000000..9324c43e --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hpl_core.h @@ -0,0 +1,56 @@ +/** + * \file + * + * \brief CPU core related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_CORE_H_INCLUDED +#define _HPL_CORE_H_INCLUDED + +/** + * \addtogroup HPL Core + * + * \section hpl_core_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include "hpl_core_port.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_CORE_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/include/hpl_delay.h b/software/firmware/oracle_same54n19a/hal/include/hpl_delay.h new file mode 100644 index 00000000..a0f1ac81 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hpl_delay.h @@ -0,0 +1,97 @@ +/** + * \file + * + * \brief Delay related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_DELAY_H_INCLUDED +#define _HPL_DELAY_H_INCLUDED + +/** + * \addtogroup HPL Delay + * + * \section hpl_delay_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifndef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ + +/** + * \brief Initialize delay functionality + * + * \param[in] hw The pointer to hardware instance + */ +void _delay_init(void *const hw); + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of us + * + * \param[in] us The amount of us to delay for + * + * \return The amount of cycles + */ +uint32_t _get_cycles_for_us(const uint16_t us); + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of ms + * + * \param[in] ms The amount of ms to delay for + * + * \return The amount of cycles + */ +uint32_t _get_cycles_for_ms(const uint16_t ms); + +/** + * \brief Delay loop to delay n number of cycles + * + * \param[in] hw The pointer to hardware instance + * \param[in] cycles The amount of cycles to delay for + */ +void _delay_cycles(void *const hw, uint32_t cycles); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_DELAY_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/include/hpl_dma.h b/software/firmware/oracle_same54n19a/hal/include/hpl_dma.h new file mode 100644 index 00000000..1e08434a --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hpl_dma.h @@ -0,0 +1,176 @@ +/** + * \file + * + * \brief DMA related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_DMA_H_INCLUDED +#define _HPL_DMA_H_INCLUDED + +/** + * \addtogroup HPL DMA + * + * \section hpl_dma_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +struct _dma_resource; + +/** + * \brief DMA callback types + */ +enum _dma_callback_type { DMA_TRANSFER_COMPLETE_CB, DMA_TRANSFER_ERROR_CB }; + +/** + * \brief DMA interrupt callbacks + */ +struct _dma_callbacks { + void (*transfer_done)(struct _dma_resource *resource); + void (*error)(struct _dma_resource *resource); +}; + +/** + * \brief DMA resource structure + */ +struct _dma_resource { + struct _dma_callbacks dma_cb; + void * back; +}; + +/** + * \brief Initialize DMA + * + * This function does low level DMA configuration. + * + * \return initialize status + */ +int32_t _dma_init(void); + +/** + * \brief Set destination address + * + * \param[in] channel DMA channel to set destination address for + * \param[in] dst Destination address + * + * \return setting status + */ +int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst); + +/** + * \brief Set source address + * + * \param[in] channel DMA channel to set source address for + * \param[in] src Source address + * + * \return setting status + */ +int32_t _dma_set_source_address(const uint8_t channel, const void *const src); + +/** + * \brief Set next descriptor address + * + * \param[in] current_channel Current DMA channel to set next descriptor address + * \param[in] next_channel Next DMA channel used as next descriptor + * + * \return setting status + */ +int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel); + +/** + * \brief Enable/disable source address incrementation during DMA transaction + * + * \param[in] channel DMA channel to set source address for + * \param[in] enable True to enable, false to disable + * + * \return status of operation + */ +int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable); + +/** + * \brief Enable/disable Destination address incrementation during DMA transaction + * + * \param[in] channel DMA channel to set destination address for + * \param[in] enable True to enable, false to disable + * + * \return status of operation + */ +int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable); +/** + * \brief Set the amount of data to be transfered per transaction + * + * \param[in] channel DMA channel to set data amount for + * \param[in] amount Data amount + * + * \return status of operation + */ +int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount); + +/** + * \brief Trigger DMA transaction on the given channel + * + * \param[in] channel DMA channel to trigger transaction on + * + * \return status of operation + */ +int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger); + +/** + * \brief Retrieves DMA resource structure + * + * \param[out] resource The resource to be retrieved + * \param[in] channel DMA channel to retrieve structure for + * + * \return status of operation + */ +int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel); + +/** + * \brief Enable/disable DMA interrupt + * + * \param[in] channel DMA channel to enable/disable interrupt for + * \param[in] type The type of interrupt to disable/enable if applicable + * \param[in] state Enable or disable + */ +void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state); + +#ifdef __cplusplus +} +#endif + +#endif /* HPL_DMA_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/include/hpl_ext_irq.h b/software/firmware/oracle_same54n19a/hal/include/hpl_ext_irq.h new file mode 100644 index 00000000..3a169b69 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hpl_ext_irq.h @@ -0,0 +1,95 @@ +/** + * \file + * + * \brief External IRQ related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_EXT_IRQ_H_INCLUDED +#define _HPL_EXT_IRQ_H_INCLUDED + +/** + * \addtogroup HPL EXT IRQ + * + * \section hpl_ext_irq_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize external interrupt module + * + * This function does low level external interrupt configuration. + * + * \param[in] cb The pointer to callback function from external interrupt + * + * \return Initialization status. + * \retval -1 External irq module is already initialized + * \retval 0 The initialization is completed successfully + */ +int32_t _ext_irq_init(void (*cb)(const uint32_t pin)); + +/** + * \brief Deinitialize external interrupt module + * + * \return Initialization status. + * \retval -1 External irq module is already deinitialized + * \retval 0 The de-initialization is completed successfully + */ +int32_t _ext_irq_deinit(void); + +/** + * \brief Enable / disable external irq + * + * \param[in] pin Pin to enable external irq on + * \param[in] enable True to enable, false to disable + * + * \return Status of external irq enabling / disabling + * \retval -1 External irq module can't be enabled / disabled + * \retval 0 External irq module is enabled / disabled successfully + */ +int32_t _ext_irq_enable(const uint32_t pin, const bool enable); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_EXT_IRQ_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/include/hpl_gpio.h b/software/firmware/oracle_same54n19a/hal/include/hpl_gpio.h new file mode 100644 index 00000000..5cdd387b --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hpl_gpio.h @@ -0,0 +1,185 @@ +/** + * \file + * + * \brief Port related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_GPIO_H_INCLUDED +#define _HPL_GPIO_H_INCLUDED + +/** + * \addtogroup HPL Port + * + * \section hpl_port_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif +/** + * \brief Macros for the pin and port group, lower 5 + * bits stands for pin number in the group, higher 3 + * bits stands for port group + */ +#define GPIO_PIN(n) (((n)&0x1Fu) << 0) +#define GPIO_PORT(n) ((n) >> 5) +#define GPIO(port, pin) ((((port)&0x7u) << 5) + ((pin)&0x1Fu)) +#define GPIO_PIN_FUNCTION_OFF 0xffffffff + +/** + * \brief PORT pull mode settings + */ +enum gpio_pull_mode { GPIO_PULL_OFF, GPIO_PULL_UP, GPIO_PULL_DOWN }; + +/** + * \brief PORT direction settins + */ +enum gpio_direction { GPIO_DIRECTION_OFF, GPIO_DIRECTION_IN, GPIO_DIRECTION_OUT }; + +/** + * \brief PORT group abstraction + */ + +enum gpio_port { GPIO_PORTA, GPIO_PORTB, GPIO_PORTC, GPIO_PORTD, GPIO_PORTE }; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Port initialization function + * + * Port initialization function should setup the port module based + * on a static configuration file, this function should normally + * not be called directly, but is a part of hal_init() + */ +void _gpio_init(void); + +/** + * \brief Set direction on port with mask + * + * Set data direction for each pin, or disable the pin + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to the + * corresponding pin + * \param[in] direction GPIO_DIRECTION_OFF = set pin direction to input + * and disable input buffer to disable the pin + * GPIO_DIRECTION_IN = set pin direction to input + * and enable input buffer to enable the pin + * GPIO_DIRECTION_OUT = set pin direction to output + * and disable input buffer + */ +static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction); + +/** + * \brief Set output level on port with mask + * + * Sets output state on pin to high or low with pin masking + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to + * the corresponding pin + * \param[in] level true = pin level is set to 1 + * false = pin level is set to 0 + */ +static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level); + +/** + * \brief Change output level to the opposite with mask + * + * Change pin output level to the opposite with pin masking + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] mask Bit mask where 1 means apply direction setting to + * the corresponding pin + */ +static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask); + +/** + * \brief Get input levels on all port pins + * + * Get input level on all port pins, will read IN register if configured to + * input and OUT register if configured as output + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + */ +static inline uint32_t _gpio_get_level(const enum gpio_port port); + +/** + * \brief Set pin pull mode + * + * Set pull mode on a single pin + * + * \notice This function will automatically change pin direction to input + * + * \param[in] port Ports are grouped into groups of maximum 32 pins, + * GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc + * \param[in] pin The pin in the group that pull mode should be selected + * for + * \param[in] pull_mode GPIO_PULL_OFF = pull resistor on pin is disabled + * GPIO_PULL_DOWN = pull resistor on pin will pull pin + * level to ground level + * GPIO_PULL_UP = pull resistor on pin will pull pin + * level to VCC + */ +static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin, + const enum gpio_pull_mode pull_mode); + +/** + * \brief Set gpio function + * + * Select which function a gpio is used for + * + * \param[in] gpio The gpio to set function for + * \param[in] function The gpio function is given by a 32-bit wide bitfield + * found in the header files for the device + * + */ +static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function); + +#include +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_GPIO_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/include/hpl_i2c_m_async.h b/software/firmware/oracle_same54n19a/hal/include/hpl_i2c_m_async.h new file mode 100644 index 00000000..8a9491de --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hpl_i2c_m_async.h @@ -0,0 +1,205 @@ +/** + * \file + * + * \brief I2C Master Hardware Proxy Layer(HPL) declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_M_ASYNC_H_INCLUDED +#define _HPL_I2C_M_ASYNC_H_INCLUDED + +#include "hpl_i2c_m_sync.h" +#include "hpl_irq.h" +#include "utils.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief i2c master callback names + */ +enum _i2c_m_async_callback_type { + I2C_M_ASYNC_DEVICE_ERROR, + I2C_M_ASYNC_DEVICE_TX_COMPLETE, + I2C_M_ASYNC_DEVICE_RX_COMPLETE +}; + +struct _i2c_m_async_device; + +typedef void (*_i2c_complete_cb_t)(struct _i2c_m_async_device *i2c_dev); +typedef void (*_i2c_error_cb_t)(struct _i2c_m_async_device *i2c_dev, int32_t errcode); + +/** + * \brief i2c callback pointers structure + */ +struct _i2c_m_async_callback { + _i2c_error_cb_t error; + _i2c_complete_cb_t tx_complete; + _i2c_complete_cb_t rx_complete; +}; + +/** + * \brief i2c device structure + */ +struct _i2c_m_async_device { + struct _i2c_m_service service; + void * hw; + struct _i2c_m_async_callback cb; + struct _irq_descriptor irq; +}; + +/** + * \name HPL functions + */ + +/** + * \brief Initialize I2C in interrupt mode + * + * This function does low level I2C configuration. + * + * \param[in] i2c_dev The pointer to i2c interrupt device structure + * \param[in] hw The pointer to hardware instance + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw); + +/** + * \brief Deinitialize I2C in interrupt mode + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Transfer data by I2C + * + * This function does low level I2C data transfer. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] msg The pointer to i2c msg structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *const i2c_dev, struct _i2c_m_msg *msg); + +/** + * \brief Set baud rate of I2C + * + * This function does low level I2C set baud rate. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] clkrate The clock rate(KHz) input to i2c module + * \param[in] baudrate The demand baud rate(KHz) of i2c module + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate); + +/** + * \brief Register callback to I2C + * + * This function does low level I2C callback register. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] cb_type The callback type request + * \param[in] func The callback function pointer + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *i2c_dev, enum _i2c_m_async_callback_type cb_type, + FUNC_PTR func); + +/** + * \brief Generate stop condition on the I2C bus + * + * This function will generate a stop condition on the I2C bus + * + * \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C + * + * \return Operation status + * \retval 0 Operation executed successfully + * \retval <0 Operation failed + */ +int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Returns the number of bytes left or not used in the I2C message buffer + * + * This function will return the number of bytes left (not written to the bus) or still free + * (not received from the bus) in the message buffer, depending on direction of transmission. + * + * \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C + * + * \return Number of bytes or error code + * \retval >0 Positive number indicating bytes left + * \retval 0 Buffer is full/empty depending on direction + * \retval <0 Error code + */ +int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev); + +/** + * \brief Enable/disable I2C master interrupt + * + * param[in] device The pointer to I2C master device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type, + const bool state); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/software/firmware/oracle_same54n19a/hal/include/hpl_i2c_m_sync.h b/software/firmware/oracle_same54n19a/hal/include/hpl_i2c_m_sync.h new file mode 100644 index 00000000..ce173ae2 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hpl_i2c_m_sync.h @@ -0,0 +1,185 @@ +/** + * \file + * + * \brief I2C Master Hardware Proxy Layer(HPL) declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_M_SYNC_H_INCLUDED +#define _HPL_I2C_M_SYNC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief i2c flags + */ +#define I2C_M_RD 0x0001 /* read data, from slave to master */ +#define I2C_M_BUSY 0x0100 +#define I2C_M_TEN 0x0400 /* this is a ten bit chip address */ +#define I2C_M_SEVEN 0x0800 /* this is a seven bit chip address */ +#define I2C_M_FAIL 0x1000 +#define I2C_M_STOP 0x8000 /* if I2C_FUNC_PROTOCOL_MANGLING */ + +/** + * \brief i2c Return codes + */ +#define I2C_OK 0 /* Operation successful */ +#define I2C_ACK -1 /* Received ACK from device on I2C bus */ +#define I2C_NACK -2 /* Received NACK from device on I2C bus */ +#define I2C_ERR_ARBLOST -3 /* Arbitration lost */ +#define I2C_ERR_BAD_ADDRESS -4 /* Bad address */ +#define I2C_ERR_BUS -5 /* Bus error */ +#define I2C_ERR_BUSY -6 /* Device busy */ +#define I2c_ERR_PACKAGE_COLLISION -7 /* Package collision */ + +/** + * \brief i2c I2C Modes + */ +#define I2C_STANDARD_MODE 0x00 +#define I2C_FASTMODE 0x01 +#define I2C_HIGHSPEED_MODE 0x02 + +/** + * \brief i2c master message structure + */ +struct _i2c_m_msg { + uint16_t addr; + volatile uint16_t flags; + int32_t len; + uint8_t * buffer; +}; + +/** + * \brief i2c master service + */ +struct _i2c_m_service { + struct _i2c_m_msg msg; + uint16_t mode; + uint16_t trise; +}; + +/** + * \brief i2c sync master device structure + */ +struct _i2c_m_sync_device { + struct _i2c_m_service service; + void * hw; +}; + +/** + * \name HPL functions + */ + +/** + * \brief Initialize I2C + * + * This function does low level I2C configuration. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] hw The pointer to hardware instance + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw); + +/** + * \brief Deinitialize I2C + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] i2c_dev The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev); + +/** + * \brief Transfer data by I2C + * + * This function does low level I2C data transfer. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] msg The pointer to i2c msg structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg); + +/** + * \brief Set baud rate of I2C + * + * This function does low level I2C set baud rate. + * + * \param[in] i2c_dev The pointer to i2c device structure + * \param[in] clkrate The clock rate(KHz) input to i2c module + * \param[in] baudrate The demand baud rate(KHz) of i2c module + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate); + +/** + * \brief Send send condition on the I2C bus + * + * This function will generate a stop condition on the I2C bus + * + * \param[in] i2c_dev The pointer to i2c device struct + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/software/firmware/oracle_same54n19a/hal/include/hpl_i2c_s_async.h b/software/firmware/oracle_same54n19a/hal/include/hpl_i2c_s_async.h new file mode 100644 index 00000000..92a5765d --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hpl_i2c_s_async.h @@ -0,0 +1,184 @@ +/** + * \file + * + * \brief I2C Slave Hardware Proxy Layer(HPL) declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_S_ASYNC_H_INCLUDED +#define _HPL_I2C_S_ASYNC_H_INCLUDED + +#include "hpl_i2c_s_sync.h" +#include "hpl_irq.h" +#include "utils.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief i2c callback types + */ +enum _i2c_s_async_callback_type { I2C_S_DEVICE_ERROR, I2C_S_DEVICE_TX, I2C_S_DEVICE_RX_COMPLETE }; + +/** + * \brief Forward declaration of I2C Slave device + */ +struct _i2c_s_async_device; + +/** + * \brief i2c slave callback function type + */ +typedef void (*_i2c_s_async_cb_t)(struct _i2c_s_async_device *device); + +/** + * \brief i2c slave callback pointers structure + */ +struct _i2c_s_async_callback { + void (*error)(struct _i2c_s_async_device *const device); + void (*tx)(struct _i2c_s_async_device *const device); + void (*rx_done)(struct _i2c_s_async_device *const device, const uint8_t data); +}; + +/** + * \brief i2c slave device structure + */ +struct _i2c_s_async_device { + void * hw; + struct _i2c_s_async_callback cb; + struct _irq_descriptor irq; +}; + +/** + * \name HPL functions + */ + +/** + * \brief Initialize asynchronous I2C slave + * + * This function does low level I2C configuration. + * + * \param[in] device The pointer to i2c interrupt device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw); + +/** + * \brief Deinitialize asynchronous I2C in interrupt mode + * + * \param[in] device The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device); + +/** + * \brief Check if 10-bit addressing mode is on + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Cheking status + * \retval 1 10-bit addressing mode is on + * \retval 0 10-bit addressing mode is off + */ +int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device); + +/** + * \brief Set I2C slave address + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] address Address to set + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address); + +/** + * \brief Write a byte to the given I2C instance + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] data Data to write + */ +void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data); + +/** + * \brief Retrieve I2C slave status + * + * \param[in] device The pointer to i2c slave device structure + * + *\return I2C slave status + */ +i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device); + +/** + * \brief Abort data transmission + * + * \param[in] device The pointer to i2c device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device); + +/** + * \brief Enable/disable I2C slave interrupt + * + * param[in] device The pointer to I2C slave device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] disable Enable or disable + */ +int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type, + const bool disable); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_I2C_S_ASYNC_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/include/hpl_i2c_s_sync.h b/software/firmware/oracle_same54n19a/hal/include/hpl_i2c_s_sync.h new file mode 100644 index 00000000..93b59345 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hpl_i2c_s_sync.h @@ -0,0 +1,184 @@ +/** + * \file + * + * \brief I2C Slave Hardware Proxy Layer(HPL) declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_I2C_S_SYNC_H_INCLUDED +#define _HPL_I2C_S_SYNC_H_INCLUDED + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief I2C Slave status type + */ +typedef uint32_t i2c_s_status_t; + +/** + * \brief i2c slave device structure + */ +struct _i2c_s_sync_device { + void *hw; +}; + +#include + +/** + * \name HPL functions + */ + +/** + * \brief Initialize synchronous I2C slave + * + * This function does low level I2C configuration. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw); + +/** + * \brief Deinitialize synchronous I2C slave + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device); + +/** + * \brief Enable I2C module + * + * This function does low level I2C enable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device); + +/** + * \brief Disable I2C module + * + * This function does low level I2C disable. + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device); + +/** + * \brief Check if 10-bit addressing mode is on + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Cheking status + * \retval 1 10-bit addressing mode is on + * \retval 0 10-bit addressing mode is off + */ +int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device); + +/** + * \brief Set I2C slave address + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] address Address to set + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address); + +/** + * \brief Write a byte to the given I2C instance + * + * \param[in] device The pointer to i2c slave device structure + * \param[in] data Data to write + */ +void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data); + +/** + * \brief Retrieve I2C slave status + * + * \param[in] device The pointer to i2c slave device structure + * + *\return I2C slave status + */ +i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device); + +/** + * \brief Clear the Data Ready interrupt flag + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Return 0 for success and negative value for error + */ +int32_t _i2c_s_sync_clear_data_ready_flag(const struct _i2c_s_sync_device *const device); + +/** + * \brief Read a byte from the given I2C instance + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Data received via I2C interface. + */ +uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device); + +/** + * \brief Check if I2C is ready to send next byte + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Status of the ready check. + * \retval true if the I2C is ready to send next byte + * \retval false if the I2C is not ready to send next byte + */ +bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device); + +/** + * \brief Check if there is data received by I2C + * + * \param[in] device The pointer to i2c slave device structure + * + * \return Status of the data received check. + * \retval true if the I2C has received a byte + * \retval false if the I2C has not received a byte + */ +bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_I2C_S_SYNC_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/include/hpl_init.h b/software/firmware/oracle_same54n19a/hal/include/hpl_init.h new file mode 100644 index 00000000..71bf49c9 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hpl_init.h @@ -0,0 +1,124 @@ +/** + * \file + * + * \brief Init related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_INIT_H_INCLUDED +#define _HPL_INIT_H_INCLUDED + +/** + * \addtogroup HPL Init + * + * \section hpl_init_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initializes clock sources + */ +void _sysctrl_init_sources(void); + +/** + * \brief Initializes Power Manager + */ +void _pm_init(void); + +/** + * \brief Initialize generators + */ +void _gclk_init_generators(void); + +/** + * \brief Initialize 32 kHz clock sources + */ +void _osc32kctrl_init_sources(void); + +/** + * \brief Initialize clock sources + */ +void _oscctrl_init_sources(void); + +/** + * \brief Initialize clock sources that need input reference clocks + */ +void _sysctrl_init_referenced_generators(void); + +/** + * \brief Initialize clock sources that need input reference clocks + */ +void _oscctrl_init_referenced_generators(void); + +/** + * \brief Initialize master clock generator + */ +void _mclk_init(void); + +/** + * \brief Initialize clock generator + */ +void _lpmcu_misc_regs_init(void); + +/** + * \brief Initialize clock generator + */ +void _pmc_init(void); + +/** + * \brief Set performance level + * + * \param[in] level The performance level to set + */ +void _set_performance_level(const uint8_t level); + +/** + * \brief Initialize the chip + */ +void _init_chip(void); + +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_INIT_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/include/hpl_irq.h b/software/firmware/oracle_same54n19a/hal/include/hpl_irq.h new file mode 100644 index 00000000..2894944a --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hpl_irq.h @@ -0,0 +1,116 @@ +/** + * \file + * + * \brief IRQ related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_IRQ_H_INCLUDED +#define _HPL_IRQ_H_INCLUDED + +/** + * \addtogroup HPL IRQ + * + * \section hpl_irq_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief IRQ descriptor + */ +struct _irq_descriptor { + void (*handler)(void *parameter); + void *parameter; +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Retrieve current IRQ number + * + * \return The current IRQ number + */ +uint8_t _irq_get_current(void); + +/** + * \brief Disable the given IRQ + * + * \param[in] n The number of IRQ to disable + */ +void _irq_disable(uint8_t n); + +/** + * \brief Set the given IRQ + * + * \param[in] n The number of IRQ to set + */ +void _irq_set(uint8_t n); + +/** + * \brief Clear the given IRQ + * + * \param[in] n The number of IRQ to clear + */ +void _irq_clear(uint8_t n); + +/** + * \brief Enable the given IRQ + * + * \param[in] n The number of IRQ to enable + */ +void _irq_enable(uint8_t n); + +/** + * \brief Register IRQ handler + * + * \param[in] number The number registered IRQ + * \param[in] irq The pointer to irq handler to register + * + * \return The status of IRQ handler registering + * \retval -1 Passed parameters were invalid + * \retval 0 The registering is completed successfully + */ +void _irq_register(const uint8_t number, struct _irq_descriptor *const irq); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_IRQ_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/include/hpl_missing_features.h b/software/firmware/oracle_same54n19a/hal/include/hpl_missing_features.h new file mode 100644 index 00000000..7071db29 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hpl_missing_features.h @@ -0,0 +1,37 @@ +/** + * \file + * + * \brief Family-dependent missing features expected by HAL + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_MISSING_FEATURES +#define _HPL_MISSING_FEATURES + +#endif /* _HPL_MISSING_FEATURES */ diff --git a/software/firmware/oracle_same54n19a/hal/include/hpl_pwm.h b/software/firmware/oracle_same54n19a/hal/include/hpl_pwm.h new file mode 100644 index 00000000..ff870525 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hpl_pwm.h @@ -0,0 +1,193 @@ +/** + * \file + * + * \brief PWM related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _HPL_PWM_H_INCLUDED +#define _HPL_PWM_H_INCLUDED + +/** + * \addtogroup HPL PWM + * + * \section hpl_pwm_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include +#include "hpl_irq.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief PWM callback types + */ +enum _pwm_callback_type { PWM_DEVICE_PERIOD_CB, PWM_DEVICE_ERROR_CB }; + +/** + * \brief PWM pulse-width period + */ +typedef uint32_t pwm_period_t; + +/** + * \brief PWM device structure + * + * The PWM device structure forward declaration. + */ +struct _pwm_device; + +/** + * \brief PWM interrupt callbacks + */ +struct _pwm_callback { + void (*pwm_period_cb)(struct _pwm_device *device); + void (*pwm_error_cb)(struct _pwm_device *device); +}; + +/** + * \brief PWM descriptor device structure + */ +struct _pwm_device { + struct _pwm_callback callback; + struct _irq_descriptor irq; + void * hw; +}; + +/** + * \brief PWM functions, pointers to low-level functions + */ +struct _pwm_hpl_interface { + int32_t (*init)(struct _pwm_device *const device, void *const hw); + void (*deinit)(struct _pwm_device *const device); + void (*start_pwm)(struct _pwm_device *const device); + void (*stop_pwm)(struct _pwm_device *const device); + void (*set_pwm_param)(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle); + bool (*is_pwm_enabled)(const struct _pwm_device *const device); + pwm_period_t (*pwm_get_period)(const struct _pwm_device *const device); + uint32_t (*pwm_get_duty)(const struct _pwm_device *const device); + void (*set_irq_state)(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable); +}; +/** + * \brief Initialize TC + * + * This function does low level TC configuration. + * + * \param[in] device The pointer to PWM device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status. + */ +int32_t _pwm_init(struct _pwm_device *const device, void *const hw); + +/** + * \brief Deinitialize TC + * + * \param[in] device The pointer to PWM device instance + */ +void _pwm_deinit(struct _pwm_device *const device); + +/** + * \brief Retrieve offset of the given tc hardware instance + * + * \param[in] device The pointer to PWM device instance + * + * \return The offset of the given tc hardware instance + */ +uint8_t _pwm_get_hardware_offset(const struct _pwm_device *const device); + +/** + * \brief Start hardware pwm + * + * \param[in] device The pointer to PWM device instance + */ +void _pwm_enable(struct _pwm_device *const device); + +/** + * \brief Stop hardware pwm + * + * \param[in] device The pointer to PWM device instance + */ +void _pwm_disable(struct _pwm_device *const device); + +/** + * \brief Set pwm parameter + * + * \param[in] device The pointer to PWM device instance + * \param[in] period Total period of one PWM cycle. + * \param[in] duty_cycle Period of PWM first half during one cycle. + */ +void _pwm_set_param(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle); + +/** + * \brief Check if pwm is working + * + * \param[in] device The pointer to PWM device instance + * + * \return Check status. + * \retval true The given pwm is working + * \retval false The given pwm is not working + */ +bool _pwm_is_enabled(const struct _pwm_device *const device); + +/** + * \brief Get pwm waveform period value + * + * \param[in] device The pointer to PWM device instance + * + * \return Period value. + */ +pwm_period_t _pwm_get_period(const struct _pwm_device *const device); + +/** + * \brief Get pwm waveform duty cycle value + * + * \param[in] device The pointer to PWM device instance + * + * \return Duty cycle value + */ +uint32_t _pwm_get_duty(const struct _pwm_device *const device); + +/** + * \brief Enable/disable PWM interrupt + * + * param[in] device The pointer to PWM device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] disable Enable or disable + */ +void _pwm_set_irq_state(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_PWM_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/include/hpl_ramecc.h b/software/firmware/oracle_same54n19a/hal/include/hpl_ramecc.h new file mode 100644 index 00000000..d79d5141 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hpl_ramecc.h @@ -0,0 +1,100 @@ +/** + * \file + * + * \brief RAMECC related functionality declaration. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_RAMECC_H_INCLUDED +#define _HPL_RAMECC_H_INCLUDED + +/** + * \addtogroup HPL RAMECC + * + * \section hpl_ramecc_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief RAMECC callback type + */ +typedef void (*ramecc_cb_t)(const uint32_t data); + +/** + * \brief RAMECC callback types + */ +enum _ramecc_callback_type { RAMECC_DUAL_ERROR_CB, RAMECC_SINGLE_ERROR_CB }; + +/** + * \brief RAMECC interrupt callbacks + */ +struct _ramecc_callbacks { + ramecc_cb_t dual_bit_err; + ramecc_cb_t single_bit_err; +}; + +/** + * \brief RAMECC device structure + */ +struct _ramecc_device { + struct _ramecc_callbacks ramecc_cb; + struct _irq_descriptor irq; +}; + +/** + * \brief Initialize RAMECC + * + * This function does low level RAMECC configuration. + * + * \return initialize status + */ +int32_t _ramecc_init(void); + +/** + * \brief Register RAMECC callback + * + * \param[in] type The type of callback + * \param[in] cb A callback function + */ +void _ramecc_register_callback(const enum _ramecc_callback_type type, ramecc_cb_t cb); + +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_RAMECC_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/include/hpl_reset.h b/software/firmware/oracle_same54n19a/hal/include/hpl_reset.h new file mode 100644 index 00000000..d627ea65 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hpl_reset.h @@ -0,0 +1,93 @@ +/** + * \file + * + * \brief Reset related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_RESET_H_INCLUDED +#define _HPL_RESET_H_INCLUDED + +/** + * \addtogroup HPL Reset + * + * \section hpl_reset_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifndef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Reset reason enumeration + * + * The list of possible reset reasons. + */ +enum reset_reason { + RESET_REASON_POR = 1, + RESET_REASON_BOD12 = 2, + RESET_REASON_BOD33 = 4, + RESET_REASON_NVM = 8, + RESET_REASON_EXT = 16, + RESET_REASON_WDT = 32, + RESET_REASON_SYST = 64, + RESET_REASON_BACKUP = 128 +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Retrieve the reset reason + * + * Retrieves the reset reason of the last MCU reset. + * + *\return An enum value indicating the reason of the last reset. + */ +enum reset_reason _get_reset_reason(void); + +/** + * \brief Reset MCU + */ +void _reset_mcu(void); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_RESET_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/include/hpl_sleep.h b/software/firmware/oracle_same54n19a/hal/include/hpl_sleep.h new file mode 100644 index 00000000..6731ec30 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hpl_sleep.h @@ -0,0 +1,88 @@ +/** + * \file + * + * \brief Sleep related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SLEEP_H_INCLUDED +#define _HPL_SLEEP_H_INCLUDED + +/** + * \addtogroup HPL Sleep + * + * \section hpl_sleep_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifndef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Set the sleep mode for the device + * + * This function sets the sleep mode for the device. + * For an overview of which systems are disabled in sleep for the different + * sleep modes see datasheet. + * + * \param[in] mode Sleep mode to use + * + * \return the status of a sleep request + * \retval -1 The requested sleep mode was invalid + * \retval 0 The operation completed successfully, sleep mode is set + */ +int32_t _set_sleep_mode(const uint8_t mode); + +/** + * \brief Reset MCU + */ +void _reset_mcu(void); + +/** + * \brief Put MCU to sleep + */ +void _go_to_sleep(void); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_SLEEP_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/include/hpl_spi.h b/software/firmware/oracle_same54n19a/hal/include/hpl_spi.h new file mode 100644 index 00000000..a5652e50 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hpl_spi.h @@ -0,0 +1,163 @@ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_H_INCLUDED +#define _HPL_SPI_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief SPI Dummy char is used when reading data from the SPI slave + */ +#define SPI_DUMMY_CHAR 0x1ff + +/** + * \brief SPI message to let driver to process + */ +//@{ +struct spi_msg { + /** Pointer to the output data buffer */ + uint8_t *txbuf; + /** Pointer to the input data buffer */ + uint8_t *rxbuf; + /** Size of the message data in SPI characters */ + uint32_t size; +}; +//@} + +/** + * \brief SPI transfer modes + * SPI transfer mode controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + */ +enum spi_transfer_mode { + /** Leading edge is rising edge, data sample on leading edge. */ + SPI_MODE_0, + /** Leading edge is rising edge, data sample on trailing edge. */ + SPI_MODE_1, + /** Leading edge is falling edge, data sample on leading edge. */ + SPI_MODE_2, + /** Leading edge is falling edge, data sample on trailing edge. */ + SPI_MODE_3 +}; + +/** + * \brief SPI character sizes + * The character size influence the way the data is sent/received. + * For char size <= 8 data is stored byte by byte. + * For char size between 9 ~ 16 data is stored in 2-byte length. + * Note that the default and recommended char size is 8 bit since it's + * supported by all system. + */ +enum spi_char_size { + /** Character size is 8 bit. */ + SPI_CHAR_SIZE_8 = 0, + /** Character size is 9 bit. */ + SPI_CHAR_SIZE_9 = 1, + /** Character size is 10 bit. */ + SPI_CHAR_SIZE_10 = 2, + /** Character size is 11 bit. */ + SPI_CHAR_SIZE_11 = 3, + /** Character size is 12 bit. */ + SPI_CHAR_SIZE_12 = 4, + /** Character size is 13 bit. */ + SPI_CHAR_SIZE_13 = 5, + /** Character size is 14 bit. */ + SPI_CHAR_SIZE_14 = 6, + /** Character size is 15 bit. */ + SPI_CHAR_SIZE_15 = 7, + /** Character size is 16 bit. */ + SPI_CHAR_SIZE_16 = 8 +}; + +/** + * \brief SPI data order + */ +enum spi_data_order { + /** MSB goes first. */ + SPI_DATA_ORDER_MSB_1ST = 0, + /** LSB goes first. */ + SPI_DATA_ORDER_LSB_1ST = 1 +}; + +/** \brief Transfer descriptor for SPI + * Transfer descriptor holds TX and RX buffers + */ +struct spi_xfer { + /** Pointer to data buffer to TX */ + uint8_t *txbuf; + /** Pointer to data buffer to RX */ + uint8_t *rxbuf; + /** Size of data characters to TX & RX */ + uint32_t size; +}; + +/** SPI generic driver. */ +struct spi_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Reference start of sync/async variables */ + uint32_t sync_async_misc[1]; +}; + +/** + * \brief Calculate the baudrate value for hardware to use to set baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] clk Clock frequency (Hz) for baudrate generation. + * \param[in] baud Target baudrate (bps). + * \return Error or baudrate value. + * \retval >0 Baudrate value. + * \retval ERR_INVALID_ARG Calculation fail. + */ +int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud); + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/include/hpl_spi_async.h b/software/firmware/oracle_same54n19a/hal/include/hpl_spi_async.h new file mode 100644 index 00000000..8e5a8485 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hpl_spi_async.h @@ -0,0 +1,131 @@ +/** + * \file + * + * \brief Common SPI related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_ASYNC_H_INCLUDED +#define _HPL_SPI_ASYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Callbacks the SPI driver must offer in async mode + */ +//@{ +/** The callback types */ +enum _spi_async_dev_cb_type { + /** Callback type for transmit, see \ref _spi_async_dev_cb_xfer_t. */ + SPI_DEV_CB_TX, + /** Callback type for receive, see \ref _spi_async_dev_cb_xfer_t. */ + SPI_DEV_CB_RX, + /** Callback type for \ref _spi_async_dev_cb_complete_t. */ + SPI_DEV_CB_COMPLETE, + /** Callback type for error */ + SPI_DEV_CB_ERROR, + /** Number of callbacks. */ + SPI_DEV_CB_N +}; + +struct _spi_async_dev; + +/** \brief The prototype for callback on SPI transfer error. + * If status code is zero, it indicates the normal completion, that is, + * SS deactivation. + * If status code belows zero, it indicates complete. + */ +typedef void (*_spi_async_dev_cb_error_t)(struct _spi_async_dev *dev, int32_t status); + +/** \brief The prototype for callback on SPI transmit/receive event + * For TX, the callback is invoked when transmit is done or ready to start + * transmit. + * For RX, the callback is invoked when receive is done or ready to read data, + * see \ref _spi_async_dev_read_one_t on data reading. + * Without DMA enabled, the callback is invoked on each character event. + * With DMA enabled, the callback is invoked on DMA buffer done. + */ +typedef void (*_spi_async_dev_cb_xfer_t)(struct _spi_async_dev *dev); + +/** + * \brief The callbacks offered by SPI driver + */ +struct _spi_async_dev_callbacks { + /** TX callback, see \ref _spi_async_dev_cb_xfer_t. */ + _spi_async_dev_cb_xfer_t tx; + /** RX callback, see \ref _spi_async_dev_cb_xfer_t. */ + _spi_async_dev_cb_xfer_t rx; + /** Complete or complete callback, see \ref _spi_async_dev_cb_complete_t. */ + _spi_async_dev_cb_xfer_t complete; + /** Error callback, see \ref */ + _spi_async_dev_cb_error_t err; +}; +//@} + +/** + * \brief SPI async driver + */ +//@{ + +/** SPI driver to support async HAL */ +struct _spi_async_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Data size, number of bytes for each character */ + uint8_t char_size; + /** Dummy byte used in master mode when reading the slave */ + uint16_t dummy_byte; + + /** \brief Pointer to callback functions, ignored for polling mode + * Pointer to the callback functions so that initialize the driver to + * handle interrupts. + */ + struct _spi_async_dev_callbacks callbacks; + /** IRQ instance for SPI device. */ + struct _irq_descriptor irq; +}; +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_ASYNC_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/include/hpl_spi_m_async.h b/software/firmware/oracle_same54n19a/hal/include/hpl_spi_m_async.h new file mode 100644 index 00000000..8d3555ed --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hpl_spi_m_async.h @@ -0,0 +1,243 @@ +/** + * \file + * + * \brief SPI Slave Async related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_M_ASYNC_H_INCLUDED +#define _HPL_SPI_M_ASYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI async device driver. */ +#define _spi_m_async_dev _spi_async_dev + +#define _spi_m_async_dev_cb_type _spi_async_dev_cb_type + +/** Uses common SPI async device driver complete callback type. */ +#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t + +/** Uses common SPI async device driver transfer callback type. */ +#define _spi_m_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access with interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_init(struct _spi_m_async_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_deinit(struct _spi_m_async_dev *dev); + +/** + * \brief Enable SPI for access with interrupts + * Enable the SPI and enable callback generation of receive and error + * interrupts. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_enable(struct _spi_m_async_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI and interrupts. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_disable(struct _spi_m_async_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_mode(struct _spi_m_async_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on + * how it's generated. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_baudrate(struct _spi_m_async_dev *dev, const uint32_t baud_val); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_char_size(struct _spi_m_async_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_async_set_data_order(struct _spi_m_async_dev *dev, const enum spi_data_order dord); + +/** + * \brief Enable interrupt on character output + * + * Enable interrupt when a new character can be written + * to the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable output interrupt + * false = disable output interrupt + * + * \return Status code + * \retval 0 Ok status + */ +int32_t _spi_m_async_enable_tx(struct _spi_m_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on character input + * + * Enable interrupt when a new character is ready to be + * read from the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_m_async_enable_rx(struct _spi_m_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on after data transmission complate + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_m_async_enable_tx_complete(struct _spi_m_async_dev *dev, bool state); + +/** + * \brief Read one character to SPI device instance + * \param[in, out] dev Pointer to the SPI device instance. + * + * \return Character read from SPI module + */ +uint16_t _spi_m_async_read_one(struct _spi_m_async_dev *dev); + +/** + * \brief Write one character to assigned buffer + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] data + * + * \return Status code of write operation + * \retval 0 Write operation OK + */ +int32_t _spi_m_async_write_one(struct _spi_m_async_dev *dev, uint16_t data); + +/** + * \brief Register the SPI device callback + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] cb_type The callback type. + * \param[in] func The callback function to register. NULL to disable callback. + * \return Always 0. + */ +int32_t _spi_m_async_register_callback(struct _spi_m_async_dev *dev, const enum _spi_m_async_dev_cb_type cb_type, + const FUNC_PTR func); + +/** + * \brief Enable/disable SPI master interrupt + * + * param[in] device The pointer to SPI master device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_m_async_set_irq_state(struct _spi_m_async_dev *const device, const enum _spi_m_async_dev_cb_type type, + const bool state); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_M_ASYNC_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/include/hpl_spi_m_dma.h b/software/firmware/oracle_same54n19a/hal/include/hpl_spi_m_dma.h new file mode 100644 index 00000000..2b48300e --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hpl_spi_m_dma.h @@ -0,0 +1,182 @@ +/** + * \file + * + * \brief SPI Master DMA related functionality declaration. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_M_DMA_H_INCLUDED +#define _HPL_SPI_M_DMA_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI dma device driver. */ +#define _spi_m_dma_dev _spi_dma_dev + +#define _spi_m_dma_dev_cb_type _spi_dma_dev_cb_type + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access with interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_init(struct _spi_m_dma_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_deinit(struct _spi_m_dma_dev *dev); + +/** + * \brief Enable SPI for access with interrupts + * Enable the SPI and enable callback generation of receive and error + * interrupts. + * \param[in] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_enable(struct _spi_m_dma_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI and interrupts. Deactivate all CS pins if works as master. + * \param[in] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_disable(struct _spi_m_dma_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 ERR_NONE is operation done successfully. + */ +int32_t _spi_m_dma_set_mode(struct _spi_m_dma_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in] dev Pointer to the SPI device instance. + * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on + * how it's generated. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_dma_set_baudrate(struct _spi_m_dma_dev *dev, const uint32_t baud_val); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_dma_set_char_size(struct _spi_m_dma_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_dma_set_data_order(struct _spi_m_dma_dev *dev, const enum spi_data_order dord); + +/** + * \brief Register the SPI device callback + * \param[in] dev Pointer to the SPI device instance. + * \param[in] cb_type The callback type. + * \param[in] func The callback function to register. NULL to disable callback. + * \return Always 0. + */ +void _spi_m_dma_register_callback(struct _spi_m_dma_dev *dev, enum _spi_dma_dev_cb_type, _spi_dma_cb_t func); + +/** \brief Do SPI data transfer (TX & RX) with DMA + * Log the TX & RX buffers and transfer them in background. It never blocks. + * + * \param[in] dev Pointer to the SPI device instance. + * \param[in] txbuf Pointer to the transfer information (\ref spi_transfer). + * \param[out] rxbuf Pointer to the receiver information (\ref spi_receive). + * \param[in] length spi transfer data length. + * + * \return Operation status. + * \retval ERR_NONE Success. + * \retval ERR_BUSY Busy. + */ +int32_t _spi_m_dma_transfer(struct _spi_m_dma_dev *dev, uint8_t const *txbuf, uint8_t *const rxbuf, + const uint16_t length); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_M_DMA_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/include/hpl_spi_m_sync.h b/software/firmware/oracle_same54n19a/hal/include/hpl_spi_m_sync.h new file mode 100644 index 00000000..38df15b4 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hpl_spi_m_sync.h @@ -0,0 +1,166 @@ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_M_SYNC_H_INCLUDED +#define _HPL_SPI_M_SYNC_H_INCLUDED + +#include +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI sync device driver. */ +#define _spi_m_sync_dev _spi_sync_dev + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access without interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw); + +/** + * \brief Deinitialize SPI + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev); + +/** + * \brief Enable SPI for access without interrupts + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on + * how it's generated. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val); + +/** + * \brief Set SPI char size + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord); + +/** + * \brief Transfer the whole message without interrupt + * Transfer the message, it will keep waiting until the message finish or + * error. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] msg Pointer to the message instance to process. + * \return Error or number of characters transferred. + * \retval ERR_BUSY SPI hardware is not ready to start transfer (not + * enabled, busy applying settings, ...). + * \retval SPI_ERR_OVERFLOW Overflow error. + * \retval >=0 Number of characters transferred. + */ +int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_M_SYNC_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/include/hpl_spi_s_async.h b/software/firmware/oracle_same54n19a/hal/include/hpl_spi_s_async.h new file mode 100644 index 00000000..56472439 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hpl_spi_s_async.h @@ -0,0 +1,232 @@ +/** + * \file + * + * \brief SPI Slave Async related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_S_ASYNC_H_INCLUDED +#define _HPL_SPI_S_ASYNC_H_INCLUDED + +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI async device driver. */ +#define _spi_s_async_dev _spi_async_dev + +#define _spi_s_async_dev_cb_type _spi_async_dev_cb_type + +/** Uses common SPI async device driver complete callback type. */ +#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t + +/** Uses common SPI async device driver transfer callback type. */ +#define _spi_s_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access with interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev); + +/** + * \brief Enable SPI for access with interrupts + * Enable the SPI and enable callback generation of receive and error + * interrupts. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI and interrupts. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord); + +/** + * \brief Enable interrupt on character output + * + * Enable interrupt when a new character can be written + * to the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable output interrupt + * false = disable output interrupt + * + * \return Status code + * \retval 0 Ok status + */ +int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on character input + * + * Enable interrupt when a new character is ready to be + * read from the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state); + +/** + * \brief Enable interrupt on Slave Select (SS) rising + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retvat 0 OK Status + */ +int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state); + +/** + * \brief Read one character to SPI device instance + * \param[in, out] dev Pointer to the SPI device instance. + * + * \return Character read from SPI module + */ +uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev); + +/** + * \brief Write one character to assigned buffer + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] data + * + * \return Status code of write operation + * \retval 0 Write operation OK + */ +int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data); + +/** + * \brief Register the SPI device callback + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] cb_type The callback type. + * \param[in] func The callback function to register. NULL to disable callback. + * \return Always 0. + */ +int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type, + const FUNC_PTR func); + +/** + * \brief Enable/disable SPI slave interrupt + * + * param[in] device The pointer to SPI slave device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_s_async_set_irq_state(struct _spi_s_async_dev *const device, const enum _spi_async_dev_cb_type type, + const bool state); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_S_ASYNC_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/include/hpl_spi_s_sync.h b/software/firmware/oracle_same54n19a/hal/include/hpl_spi_s_sync.h new file mode 100644 index 00000000..ff4c811a --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hpl_spi_s_sync.h @@ -0,0 +1,232 @@ +/** + * \file + * + * \brief SPI related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_S_SYNC_H_INCLUDED +#define _HPL_SPI_S_SYNC_H_INCLUDED + +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** Uses common SPI sync device driver. */ +#define _spi_s_sync_dev _spi_sync_dev + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize SPI for access without interrupts + * It will load default hardware configuration and software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] hw Pointer to the hardware base. + * \return Operation status. + * \retval ERR_INVALID_ARG Input parameter problem. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval ERR_DENIED SPI has been enabled. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw); + +/** + * \brief Initialize SPI for access with interrupts + * Disable, reset the hardware and the software struct. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev); + +/** + * \brief Enable SPI for access without interrupts + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval ERR_BUSY SPI hardware not ready (resetting). + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev); + +/** + * \brief Disable SPI for access without interrupts + * Disable SPI. Deactivate all CS pins if works as master. + * \param[in, out] dev Pointer to the SPI device instance. + * \return Operation status. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev); + +/** + * \brief Set SPI transfer mode + * Set SPI transfer mode (\ref spi_transfer_mode), + * which controls clock polarity and clock phase. + * Mode 0: leading edge is rising edge, data sample on leading edge. + * Mode 1: leading edge is rising edge, data sample on trailing edge. + * Mode 2: leading edge is falling edge, data sample on leading edge. + * Mode 3: leading edge is falling edge, data sample on trailing edge. + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] mode The SPI transfer mode. + * \return Operation status. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode); + +/** + * \brief Set SPI baudrate + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] char_size The character size, see \ref spi_char_size. + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size); + +/** + * \brief Set SPI data order + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] dord SPI data order (LSB/MSB first). + * \return Operation status. + * \retval ERR_INVALID_ARG The character size is not supported. + * \retval ERR_BUSY SPI is not ready to accept new setting. + * \retval 0 Operation done successfully. + */ +int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord); + +/** + * \brief Enable interrupt on character output + * + * Enable interrupt when a new character can be written + * to the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable output interrupt + * false = disable output interrupt + * + * \return Status code + * \retval 0 Ok status + */ +int32_t _spi_s_sync_enable_tx(struct _spi_s_sync_dev *dev, bool state); + +/** + * \brief Enable interrupt on character input + * + * Enable interrupt when a new character is ready to be + * read from the SPI device. + * + * \param[in] dev Pointer to the SPI device instance + * \param[in] state true = enable input interrupts + * false = disable input interrupt + * + * \return Status code + * \retval 0 OK Status + */ +int32_t _spi_s_sync_enable_rx(struct _spi_s_sync_dev *dev, bool state); + +/** + * \brief Read one character to SPI device instance + * \param[in, out] dev Pointer to the SPI device instance. + * + * \return Character read from SPI module + */ +uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev); + +/** + * \brief Write one character to assigned buffer + * \param[in, out] dev Pointer to the SPI device instance. + * \param[in] data + * + * \return Status code of write operation + * \retval 0 Write operation OK + */ +int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data); + +/** + * \brief Check if TX ready + * + * \param[in] dev Pointer to the SPI device instance + * + * \return TX ready state + * \retval true TX ready + * \retval false TX not ready + */ +bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev); + +/** + * \brief Check if RX character ready + * + * \param[in] dev Pointer to the SPI device instance + * + * \return RX character ready state + * \retval true RX character ready + * \retval false RX character not ready + */ +bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev); + +/** + * \brief Check if SS deactiviation detected + * + * \param[in] dev Pointer to the SPI device instance + * + * \return SS deactiviation state + * \retval true SS deactiviation detected + * \retval false SS deactiviation not detected + */ +bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev); + +/** + * \brief Check if error is detected + * + * \param[in] dev Pointer to the SPI device instance + * + * \return Error detection state + * \retval true Error detected + * \retval false Error not detected + */ +bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev); +//@} + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_S_SYNC_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/include/hpl_spi_sync.h b/software/firmware/oracle_same54n19a/hal/include/hpl_spi_sync.h new file mode 100644 index 00000000..dc88648f --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hpl_spi_sync.h @@ -0,0 +1,70 @@ +/** + * \file + * + * \brief Common SPI related functionality declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SPI_SYNC_H_INCLUDED +#define _HPL_SPI_SYNC_H_INCLUDED + +#include +#include + +#include + +/** + * \addtogroup hpl_spi HPL SPI + * + * \section hpl_spi_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#ifdef __cplusplus +extern "C" { +#endif + +/** SPI driver to support sync HAL */ +struct _spi_sync_dev { + /** Pointer to the hardware base or private data for special device. */ + void *prvt; + /** Data size, number of bytes for each character */ + uint8_t char_size; + /** Dummy byte used in master mode when reading the slave */ + uint16_t dummy_byte; +}; + +#ifdef __cplusplus +} +#endif + +/**@}*/ +#endif /* ifndef _HPL_SPI_SYNC_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/include/hpl_timer.h b/software/firmware/oracle_same54n19a/hal/include/hpl_timer.h new file mode 100644 index 00000000..9bdfbb77 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hpl_timer.h @@ -0,0 +1,160 @@ +/** + * \file + * + * \brief Timer related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_TIMER_H_INCLUDED +#define _HPL_TIMER_H_INCLUDED + +/** + * \addtogroup HPL Timer + * + * \section hpl_timer_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Timer device structure + * + * The Timer device structure forward declaration. + */ +struct _timer_device; + +/** + * \brief Timer interrupt callbacks + */ +struct _timer_callbacks { + void (*period_expired)(struct _timer_device *device); +}; + +/** + * \brief Timer device structure + */ +struct _timer_device { + struct _timer_callbacks timer_cb; + struct _irq_descriptor irq; + void * hw; +}; + +/** + * \brief Timer functions, pointers to low-level functions + */ +struct _timer_hpl_interface { + int32_t (*init)(struct _timer_device *const device, void *const hw); + void (*deinit)(struct _timer_device *const device); + void (*start_timer)(struct _timer_device *const device); + void (*stop_timer)(struct _timer_device *const device); + void (*set_timer_period)(struct _timer_device *const device, const uint32_t clock_cycles); + uint32_t (*get_period)(const struct _timer_device *const device); + bool (*is_timer_started)(const struct _timer_device *const device); + void (*set_timer_irq)(struct _timer_device *const device); +}; +/** + * \brief Initialize TCC + * + * This function does low level TCC configuration. + * + * \param[in] device The pointer to timer device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status. + */ +int32_t _timer_init(struct _timer_device *const device, void *const hw); + +/** + * \brief Deinitialize TCC + * + * \param[in] device The pointer to timer device instance + */ +void _timer_deinit(struct _timer_device *const device); + +/** + * \brief Start hardware timer + * + * \param[in] device The pointer to timer device instance + */ +void _timer_start(struct _timer_device *const device); + +/** + * \brief Stop hardware timer + * + * \param[in] device The pointer to timer device instance + */ +void _timer_stop(struct _timer_device *const device); + +/** + * \brief Set timer period + * + * \param[in] device The pointer to timer device instance + */ +void _timer_set_period(struct _timer_device *const device, const uint32_t clock_cycles); + +/** + * \brief Retrieve timer period + * + * \param[in] device The pointer to timer device instance + * + * \return Timer period + */ +uint32_t _timer_get_period(const struct _timer_device *const device); + +/** + * \brief Check if timer is running + * + * \param[in] device The pointer to timer device instance + * + * \return Check status. + * \retval true The given timer is running + * \retval false The given timer is not running + */ +bool _timer_is_started(const struct _timer_device *const device); + +/** + * \brief Set timer IRQ + * + * \param[in] device The pointer to timer device instance + */ +void _timer_set_irq(struct _timer_device *const device); + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_TIMER_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/include/hpl_usart.h b/software/firmware/oracle_same54n19a/hal/include/hpl_usart.h new file mode 100644 index 00000000..0e09501d --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hpl_usart.h @@ -0,0 +1,113 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_USART_H_INCLUDED +#define _HPL_USART_H_INCLUDED + +/** + * \addtogroup HPL USART SYNC + * + * \section hpl_usart_sync_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART flow control state + */ +union usart_flow_control_state { + struct { + uint8_t cts : 1; + uint8_t rts : 1; + uint8_t unavailable : 1; + uint8_t reserved : 5; + } bit; + uint8_t value; +}; + +/** + * \brief USART baud rate mode + */ +enum usart_baud_rate_mode { USART_BAUDRATE_ASYNCH_ARITHMETIC, USART_BAUDRATE_ASYNCH_FRACTIONAL, USART_BAUDRATE_SYNCH }; + +/** + * \brief USART data order + */ +enum usart_data_order { USART_DATA_ORDER_MSB = 0, USART_DATA_ORDER_LSB = 1 }; + +/** + * \brief USART mode + */ +enum usart_mode { USART_MODE_ASYNCHRONOUS = 0, USART_MODE_SYNCHRONOUS = 1 }; + +/** + * \brief USART parity + */ +enum usart_parity { + USART_PARITY_EVEN = 0, + USART_PARITY_ODD = 1, + USART_PARITY_NONE = 2, + USART_PARITY_SPACE = 3, + USART_PARITY_MARK = 4 +}; + +/** + * \brief USART stop bits mode + */ +enum usart_stop_bits { USART_STOP_BITS_ONE = 0, USART_STOP_BITS_TWO = 1, USART_STOP_BITS_ONE_P_FIVE = 2 }; + +/** + * \brief USART character size + */ +enum usart_character_size { + USART_CHARACTER_SIZE_8BITS = 0, + USART_CHARACTER_SIZE_9BITS = 1, + USART_CHARACTER_SIZE_5BITS = 5, + USART_CHARACTER_SIZE_6BITS = 6, + USART_CHARACTER_SIZE_7BITS = 7 +}; + +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_USART_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/include/hpl_usart_async.h b/software/firmware/oracle_same54n19a/hal/include/hpl_usart_async.h new file mode 100644 index 00000000..3f833d1a --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hpl_usart_async.h @@ -0,0 +1,270 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_USART_ASYNC_H_INCLUDED +#define _HPL_USART_ASYNC_H_INCLUDED + +/** + * \addtogroup HPL USART + * + * \section hpl_usart_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include "hpl_usart.h" +#include "hpl_irq.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART callback types + */ +enum _usart_async_callback_type { USART_ASYNC_BYTE_SENT, USART_ASYNC_RX_DONE, USART_ASYNC_TX_DONE, USART_ASYNC_ERROR }; + +/** + * \brief USART device structure + * + * The USART device structure forward declaration. + */ +struct _usart_async_device; + +/** + * \brief USART interrupt callbacks + */ +struct _usart_async_callbacks { + void (*tx_byte_sent)(struct _usart_async_device *device); + void (*rx_done_cb)(struct _usart_async_device *device, uint8_t data); + void (*tx_done_cb)(struct _usart_async_device *device); + void (*error_cb)(struct _usart_async_device *device); +}; + +/** + * \brief USART descriptor device structure + */ +struct _usart_async_device { + struct _usart_async_callbacks usart_cb; + struct _irq_descriptor irq; + void * hw; +}; +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize asynchronous USART + * + * This function does low level USART configuration. + * + * \param[in] device The pointer to USART device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status + */ +int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw); + +/** + * \brief Deinitialize USART + * + * This function closes the given USART by disabling its clock. + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_deinit(struct _usart_async_device *const device); + +/** + * \brief Enable usart module + * + * This function will enable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_enable(struct _usart_async_device *const device); + +/** + * \brief Disable usart module + * + * This function will disable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_disable(struct _usart_async_device *const device); + +/** + * \brief Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); + +/** + * \brief Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate); + +/** + * \brief Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order); + +/** + * \brief Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode); + +/** + * \brief Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity); + +/** + * \brief Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits); + +/** + * \brief Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size); + +/** + * \brief Retrieve usart status + * + * \param[in] device The pointer to USART device instance + */ +uint32_t _usart_async_get_status(const struct _usart_async_device *const device); + +/** + * \brief Write a byte to the given USART instance + * + * \param[in] device The pointer to USART device instance + * \param[in] data Data to write + */ +void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data); + +/** + * \brief Check if USART is ready to send next byte + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the ready check. + * \retval true if the USART is ready to send next byte + * \retval false if the USART is not ready to send next byte + */ +bool _usart_async_is_byte_sent(const struct _usart_async_device *const device); + +/** + * \brief Set the state of flow control pins + * + * \param[in] device The pointer to USART device instance + * \param[in] state - A state of flow control pins to set + */ +void _usart_async_set_flow_control_state(struct _usart_async_device *const device, + const union usart_flow_control_state state); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the of flow control pins. + * + * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE. + */ +union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device); + +/** + * \brief Enable data register empty interrupt + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device); + +/** + * \brief Enable transmission complete interrupt + * + * \param[in] device The pointer to USART device instance + */ +void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device); + +/** + * \brief Retrieve ordinal number of the given USART hardware instance + * + * \param[in] device The pointer to USART device instance + * + * \return The ordinal number of the given USART hardware instance + */ +uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device); + +/** + * \brief Enable/disable USART interrupt + * + * param[in] device The pointer to USART device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type, + const bool state); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_USART_ASYNC_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/include/hpl_usart_sync.h b/software/firmware/oracle_same54n19a/hal/include/hpl_usart_sync.h new file mode 100644 index 00000000..abc7264f --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/include/hpl_usart_sync.h @@ -0,0 +1,254 @@ +/** + * \file + * + * \brief USART related functionality declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_SYNC_USART_H_INCLUDED +#define _HPL_SYNC_USART_H_INCLUDED + +/** + * \addtogroup HPL USART SYNC + * + * \section hpl_usart_sync_rev Revision History + * - v1.0.0 Initial Release + * + *@{ + */ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief USART descriptor device structure + */ +struct _usart_sync_device { + void *hw; +}; + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Initialize synchronous USART + * + * This function does low level USART configuration. + * + * \param[in] device The pointer to USART device instance + * \param[in] hw The pointer to hardware instance + * + * \return Initialization status + */ +int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw); + +/** + * \brief Deinitialize USART + * + * This function closes the given USART by disabling its clock. + * + * \param[in] device The pointer to USART device instance + */ +void _usart_sync_deinit(struct _usart_sync_device *const device); + +/** + * \brief Enable usart module + * + * This function will enable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_sync_enable(struct _usart_sync_device *const device); + +/** + * \brief Disable usart module + * + * This function will disable the usart module + * + * \param[in] device The pointer to USART device instance + */ +void _usart_sync_disable(struct _usart_sync_device *const device); + +/** + * \brief Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); + +/** + * \brief Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate); + +/** + * \brief Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order); + +/** + * \brief Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode); + +/** + * \brief Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity); + +/** + * \brief Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits); + +/** + * \brief Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size); + +/** + * \brief Retrieve usart status + * + * \param[in] device The pointer to USART device instance + */ +uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device); + +/** + * \brief Write a byte to the given USART instance + * + * \param[in] device The pointer to USART device instance + * \param[in] data Data to write + */ +void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data); + +/** + * \brief Read a byte from the given USART instance + * + * \param[in] device The pointer to USART device instance + * \param[in] data Data to write + * + * \return Data received via USART interface. + */ +uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device); + +/** + * \brief Check if USART is ready to send next byte + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the ready check. + * \retval true if the USART is ready to send next byte + * \retval false if the USART is not ready to send next byte + */ +bool _usart_sync_is_ready_to_send(const struct _usart_sync_device *const device); + +/** + * \brief Check if USART transmitter has sent the byte + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the ready check. + * \retval true if the USART transmitter has sent the byte + * \retval false if the USART transmitter has not send the byte + */ +bool _usart_sync_is_transmit_done(const struct _usart_sync_device *const device); + +/** + * \brief Check if there is data received by USART + * + * \param[in] device The pointer to USART device instance + * + * \return Status of the data received check. + * \retval true if the USART has received a byte + * \retval false if the USART has not received a byte + */ +bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device); + +/** + * \brief Set the state of flow control pins + * + * \param[in] device The pointer to USART device instance + * \param[in] state - A state of flow control pins to set + */ +void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device, + const union usart_flow_control_state state); + +/** + * \brief Retrieve the state of flow control pins + * + * This function retrieves the of flow control pins. + * + * \return USART_FLOW_CONTROL_STATE_UNAVAILABLE. + */ +union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device); + +/** + * \brief Retrieve ordinal number of the given USART hardware instance + * + * \param[in] device The pointer to USART device instance + * + * \return The ordinal number of the given USART hardware instance + */ +uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device); +//@} + +#ifdef __cplusplus +} +#endif +/**@}*/ +#endif /* _HPL_SYNC_USART_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/src/hal_atomic.c b/software/firmware/oracle_same54n19a/hal/src/hal_atomic.c new file mode 100644 index 00000000..f56418ee --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/src/hal_atomic.c @@ -0,0 +1,66 @@ +/** + * \file + * + * \brief Critical sections related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_atomic.h" + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Disable interrupts, enter critical section + */ +void atomic_enter_critical(hal_atomic_t volatile *atomic) +{ + *atomic = __get_PRIMASK(); + __disable_irq(); + __DMB(); +} + +/** + * \brief Exit atomic section + */ +void atomic_leave_critical(hal_atomic_t volatile *atomic) +{ + __DMB(); + __set_PRIMASK(*atomic); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t atomic_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/software/firmware/oracle_same54n19a/hal/src/hal_cache.c b/software/firmware/oracle_same54n19a/hal/src/hal_cache.c new file mode 100644 index 00000000..b2e75aa7 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/src/hal_cache.c @@ -0,0 +1,78 @@ +/** + * \file + * + * \brief HAL cache functionality implementation. + * + * Copyright (c)2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include +#include + +/** + * \brief Initialize cache module + */ +int32_t cache_init(void) +{ + return _cmcc_init(); +} + +/** + * \brief Enable cache module + */ +int32_t cache_enable(const void *hw) +{ + return _cmcc_enable(hw); +} + +/** + * \brief Disable cache module + */ +int32_t cache_disable(const void *hw) +{ + return _cmcc_disable(hw); +} + +/** + * \brief Configure cache module + */ +int32_t cache_configure(const void *hw, struct _cache_cfg *cache) +{ + return _cmcc_configure(hw, cache); +} + +/** + * \brief Invalidate entire cache entries + */ +int32_t cache_invalidate_all(const void *hw) +{ + return _cmcc_invalidate_all(hw); +} diff --git a/software/firmware/oracle_same54n19a/hal/src/hal_delay.c b/software/firmware/oracle_same54n19a/hal/src/hal_delay.c new file mode 100644 index 00000000..6f77cc70 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/src/hal_delay.c @@ -0,0 +1,80 @@ +/** + * \file + * + * \brief HAL delay related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include "hal_delay.h" +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief The pointer to a hardware instance used by the driver. + */ +static void *hardware; + +/** + * \brief Initialize Delay driver + */ +void delay_init(void *const hw) +{ + _delay_init(hardware = hw); +} + +/** + * \brief Perform delay in us + */ +void delay_us(const uint16_t us) +{ + _delay_cycles(hardware, _get_cycles_for_us(us)); +} + +/** + * \brief Perform delay in ms + */ +void delay_ms(const uint16_t ms) +{ + _delay_cycles(hardware, _get_cycles_for_ms(ms)); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t delay_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/software/firmware/oracle_same54n19a/hal/src/hal_ext_irq.c b/software/firmware/oracle_same54n19a/hal/src/hal_ext_irq.c new file mode 100644 index 00000000..2c1608c0 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/src/hal_ext_irq.c @@ -0,0 +1,188 @@ +/** + * \file + * + * \brief External interrupt functionality imkplementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_ext_irq.h" + +#define EXT_IRQ_AMOUNT 0 + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief External IRQ struct + */ +struct ext_irq { + ext_irq_cb_t cb; + uint32_t pin; +}; + +/* Remove KEIL compiling error in case no IRQ line selected */ +#if EXT_IRQ_AMOUNT == 0 +#undef EXT_IRQ_AMOUNT +#define EXT_IRQ_AMOUNT 1 +#endif + +/** + * \brief Array of external IRQs callbacks + */ +static struct ext_irq ext_irqs[EXT_IRQ_AMOUNT]; + +static void process_ext_irq(const uint32_t pin); + +/** + * \brief Initialize external irq component if any + */ +int32_t ext_irq_init(void) +{ + uint16_t i; + + for (i = 0; i < EXT_IRQ_AMOUNT; i++) { + ext_irqs[i].pin = 0xFFFFFFFF; + ext_irqs[i].cb = NULL; + } + + return _ext_irq_init(process_ext_irq); +} + +/** + * \brief Deinitialize external irq if any + */ +int32_t ext_irq_deinit(void) +{ + return _ext_irq_deinit(); +} + +/** + * \brief Register callback for the given external interrupt + */ +int32_t ext_irq_register(const uint32_t pin, ext_irq_cb_t cb) +{ + uint8_t i = 0, j = 0; + bool found = false; + + for (; i < EXT_IRQ_AMOUNT; i++) { + if (ext_irqs[i].pin == pin) { + ext_irqs[i].cb = cb; + found = true; + break; + } + } + + if (NULL == cb) { + if (!found) { + return ERR_INVALID_ARG; + } + return _ext_irq_enable(pin, false); + } + + if (!found) { + for (i = 0; i < EXT_IRQ_AMOUNT; i++) { + if (NULL == ext_irqs[i].cb) { + ext_irqs[i].cb = cb; + ext_irqs[i].pin = pin; + found = true; + break; + } + } + for (; (j < EXT_IRQ_AMOUNT) && (i < EXT_IRQ_AMOUNT); j++) { + if ((ext_irqs[i].pin < ext_irqs[j].pin) && (ext_irqs[j].pin != 0xFFFFFFFF)) { + struct ext_irq tmp = ext_irqs[j]; + + ext_irqs[j] = ext_irqs[i]; + ext_irqs[i] = tmp; + } + } + } + + if (!found) { + return ERR_INVALID_ARG; + } + + return _ext_irq_enable(pin, true); +} + +/** + * \brief Enable external irq + */ +int32_t ext_irq_enable(const uint32_t pin) +{ + return _ext_irq_enable(pin, true); +} + +/** + * \brief Disable external irq + */ +int32_t ext_irq_disable(const uint32_t pin) +{ + return _ext_irq_enable(pin, false); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t ext_irq_get_version(void) +{ + return DRIVER_VERSION; +} + +/** + * \brief Interrupt processing routine + * + * \param[in] pin The pin which triggered the interrupt + */ +static void process_ext_irq(const uint32_t pin) +{ + uint8_t lower = 0, middle, upper = EXT_IRQ_AMOUNT; + + while (upper >= lower) { + middle = (upper + lower) >> 1; + if (middle >= EXT_IRQ_AMOUNT) { + return; + } + + if (ext_irqs[middle].pin == pin) { + if (ext_irqs[middle].cb) { + ext_irqs[middle].cb(); + } + return; + } + + if (ext_irqs[middle].pin < pin) { + lower = middle + 1; + } else { + upper = middle - 1; + } + } +} diff --git a/software/firmware/oracle_same54n19a/hal/src/hal_gpio.c b/software/firmware/oracle_same54n19a/hal/src/hal_gpio.c new file mode 100644 index 00000000..00dfea6f --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/src/hal_gpio.c @@ -0,0 +1,44 @@ +/** + * \file + * + * \brief Port + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_gpio.h" + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +uint32_t gpio_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/software/firmware/oracle_same54n19a/hal/src/hal_i2c_m_sync.c b/software/firmware/oracle_same54n19a/hal/src/hal_i2c_m_sync.c new file mode 100644 index 00000000..30821a27 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/src/hal_i2c_m_sync.c @@ -0,0 +1,258 @@ +/** + * \file + * + * \brief I/O I2C related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Sync version of I2C I/O read + */ +static int32_t i2c_m_sync_read(struct io_descriptor *io, uint8_t *buf, const uint16_t n) +{ + struct i2c_m_sync_desc *i2c = CONTAINER_OF(io, struct i2c_m_sync_desc, io); + struct _i2c_m_msg msg; + int32_t ret; + + msg.addr = i2c->slave_addr; + msg.len = n; + msg.flags = I2C_M_STOP | I2C_M_RD; + msg.buffer = buf; + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret) { + return ret; + } + + return n; +} + +/** + * \brief Sync version of I2C I/O write + */ +static int32_t i2c_m_sync_write(struct io_descriptor *io, const uint8_t *buf, const uint16_t n) +{ + struct i2c_m_sync_desc *i2c = CONTAINER_OF(io, struct i2c_m_sync_desc, io); + struct _i2c_m_msg msg; + int32_t ret; + + msg.addr = i2c->slave_addr; + msg.len = n; + msg.flags = I2C_M_STOP; + msg.buffer = (uint8_t *)buf; + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret) { + return ret; + } + + return n; +} + +/** + * \brief Sync version of i2c initialize + */ +int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw) +{ + int32_t init_status; + ASSERT(i2c); + + init_status = _i2c_m_sync_init(&i2c->device, hw); + if (init_status) { + return init_status; + } + + /* Init I/O */ + i2c->io.read = i2c_m_sync_read; + i2c->io.write = i2c_m_sync_write; + + return ERR_NONE; +} + +/** + * \brief deinitialize + */ +int32_t i2c_m_sync_deinit(struct i2c_m_sync_desc *i2c) +{ + int32_t status; + ASSERT(i2c); + + status = _i2c_m_sync_deinit(&i2c->device); + if (status) { + return status; + } + + i2c->io.read = NULL; + i2c->io.write = NULL; + + return ERR_NONE; +} + +/** + * \brief Sync version of i2c enable + */ +int32_t i2c_m_sync_enable(struct i2c_m_sync_desc *i2c) +{ + return _i2c_m_sync_enable(&i2c->device); +} + +/** + * \brief Sync version of i2c disable + */ +int32_t i2c_m_sync_disable(struct i2c_m_sync_desc *i2c) +{ + return _i2c_m_sync_disable(&i2c->device); +} + +/** + * \brief Sync version of i2c set slave address + */ +int32_t i2c_m_sync_set_slaveaddr(struct i2c_m_sync_desc *i2c, int16_t addr, int32_t addr_len) +{ + return i2c->slave_addr = (addr & 0x3ff) | (addr_len & I2C_M_TEN); +} + +/** + * \brief Sync version of i2c set baudrate + */ +int32_t i2c_m_sync_set_baudrate(struct i2c_m_sync_desc *i2c, uint32_t clkrate, uint32_t baudrate) +{ + return _i2c_m_sync_set_baudrate(&i2c->device, clkrate, baudrate); +} + +/** + * \brief Sync version of i2c write command + */ +int32_t i2c_m_sync_cmd_write(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length) +{ + struct _i2c_m_msg msg; + int32_t ret; + + msg.addr = i2c->slave_addr; + msg.len = 1; + msg.flags = 0; + msg.buffer = ® + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret != 0) { + /* error occurred */ + return ret; + } + + msg.flags = I2C_M_STOP; + msg.buffer = buffer; + msg.len = length; + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret != 0) { + /* error occurred */ + return ret; + } + + return ERR_NONE; +} + +/** + * \brief Sync version of i2c read command + */ +int32_t i2c_m_sync_cmd_read(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length) +{ + struct _i2c_m_msg msg; + int32_t ret; + + msg.addr = i2c->slave_addr; + msg.len = 1; + msg.flags = 0; + msg.buffer = ® + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret != 0) { + /* error occurred */ + return ret; + } + + msg.flags = I2C_M_STOP | I2C_M_RD; + msg.buffer = buffer; + msg.len = length; + + ret = _i2c_m_sync_transfer(&i2c->device, &msg); + + if (ret != 0) { + /* error occurred */ + return ret; + } + + return ERR_NONE; +} + +/** + * \brief Sync version of i2c transfer command + */ +int32_t i2c_m_sync_transfer(struct i2c_m_sync_desc *const i2c, struct _i2c_m_msg *msg) +{ + return _i2c_m_sync_transfer(&i2c->device, msg); +} + +/** + * \brief Sync version of i2c send stop condition command + */ +int32_t i2c_m_sync_send_stop(struct i2c_m_sync_desc *const i2c) +{ + return _i2c_m_sync_send_stop(&i2c->device); +} + +/** + * \brief Retrieve I/O descriptor + */ +int32_t i2c_m_sync_get_io_descriptor(struct i2c_m_sync_desc *const i2c, struct io_descriptor **io) +{ + *io = &i2c->io; + return ERR_NONE; +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t i2c_m_sync_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/software/firmware/oracle_same54n19a/hal/src/hal_init.c b/software/firmware/oracle_same54n19a/hal/src/hal_init.c new file mode 100644 index 00000000..fb65341f --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/src/hal_init.c @@ -0,0 +1,47 @@ +/** + * \file + * + * \brief HAL initialization related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_init.h" + +/** + * \brief Driver version + */ +#define HAL_INIT_VERSION 0x00000001u + +/** + * \brief Retrieve the current driver version + */ +uint32_t init_get_version(void) +{ + return HAL_INIT_VERSION; +} diff --git a/software/firmware/oracle_same54n19a/hal/src/hal_io.c b/software/firmware/oracle_same54n19a/hal/src/hal_io.c new file mode 100644 index 00000000..7e8feb04 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/src/hal_io.c @@ -0,0 +1,63 @@ +/** + * \file + * + * \brief I/O functionality implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +uint32_t io_get_version(void) +{ + return DRIVER_VERSION; +} + +/** + * \brief I/O write interface + */ +int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) +{ + ASSERT(io_descr && buf); + return io_descr->write(io_descr, buf, length); +} + +/** + * \brief I/O read interface + */ +int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) +{ + ASSERT(io_descr && buf); + return io_descr->read(io_descr, buf, length); +} diff --git a/software/firmware/oracle_same54n19a/hal/src/hal_sleep.c b/software/firmware/oracle_same54n19a/hal/src/hal_sleep.c new file mode 100644 index 00000000..89472f15 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/src/hal_sleep.c @@ -0,0 +1,73 @@ +/** + * \file + * + * \brief Sleep related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_sleep.h" +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Set the sleep mode of the device and put the MCU to sleep + * + * For an overview of which systems are disabled in sleep for the different + * sleep modes, see the data sheet. + * + * \param[in] mode Sleep mode to use + * + * \return The status of a sleep request + * \retval -1 The requested sleep mode was invalid or not available + * \retval 0 The operation completed successfully, returned after leaving the + * sleep + */ +int sleep(const uint8_t mode) +{ + if (ERR_NONE != _set_sleep_mode(mode)) + return ERR_INVALID_ARG; + + _go_to_sleep(); + + return ERR_NONE; +} + +/** + * \brief Retrieve the current driver version + * + * \return Current driver version + */ +uint32_t sleep_get_version(void) +{ + return DRIVER_VERSION; +} diff --git a/software/firmware/oracle_same54n19a/hal/src/hal_timer.c b/software/firmware/oracle_same54n19a/hal/src/hal_timer.c new file mode 100644 index 00000000..565c6db1 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/src/hal_timer.c @@ -0,0 +1,250 @@ +/** + * \file + * + * \brief Timer functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_timer.h" +#include +#include +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +/** + * \brief Timer flags + */ +#define TIMER_FLAG_QUEUE_IS_TAKEN 1 +#define TIMER_FLAG_INTERRUPT_TRIGERRED 2 + +static void timer_add_timer_task(struct list_descriptor *list, struct timer_task *const new_task, const uint32_t time); +static void timer_process_counted(struct _timer_device *device); + +/** + * \brief Initialize timer + */ +int32_t timer_init(struct timer_descriptor *const descr, void *const hw, struct _timer_hpl_interface *const func) +{ + ASSERT(descr && hw); + _timer_init(&descr->device, hw); + descr->time = 0; + descr->device.timer_cb.period_expired = timer_process_counted; + + return ERR_NONE; +} + +/** + * \brief Deinitialize timer + */ +int32_t timer_deinit(struct timer_descriptor *const descr) +{ + ASSERT(descr); + _timer_deinit(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Start timer + */ +int32_t timer_start(struct timer_descriptor *const descr) +{ + ASSERT(descr); + if (_timer_is_started(&descr->device)) { + return ERR_DENIED; + } + _timer_start(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Stop timer + */ +int32_t timer_stop(struct timer_descriptor *const descr) +{ + ASSERT(descr); + if (!_timer_is_started(&descr->device)) { + return ERR_DENIED; + } + _timer_stop(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Set amount of clock cycler per timer tick + */ +int32_t timer_set_clock_cycles_per_tick(struct timer_descriptor *const descr, const uint32_t clock_cycles) +{ + ASSERT(descr); + _timer_set_period(&descr->device, clock_cycles); + + return ERR_NONE; +} + +/** + * \brief Add timer task + */ +int32_t timer_add_task(struct timer_descriptor *const descr, struct timer_task *const task) +{ + ASSERT(descr && task); + + descr->flags |= TIMER_FLAG_QUEUE_IS_TAKEN; + if (is_list_element(&descr->tasks, task)) { + descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; + ASSERT(false); + return ERR_ALREADY_INITIALIZED; + } + task->time_label = descr->time; + timer_add_timer_task(&descr->tasks, task, descr->time); + + descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; + if (descr->flags & TIMER_FLAG_INTERRUPT_TRIGERRED) { + CRITICAL_SECTION_ENTER() + descr->flags &= ~TIMER_FLAG_INTERRUPT_TRIGERRED; + _timer_set_irq(&descr->device); + CRITICAL_SECTION_LEAVE() + } + + return ERR_NONE; +} + +/** + * \brief Remove timer task + */ +int32_t timer_remove_task(struct timer_descriptor *const descr, const struct timer_task *const task) +{ + ASSERT(descr && task); + + descr->flags |= TIMER_FLAG_QUEUE_IS_TAKEN; + if (!is_list_element(&descr->tasks, task)) { + descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; + ASSERT(false); + return ERR_NOT_FOUND; + } + list_delete_element(&descr->tasks, task); + + descr->flags &= ~TIMER_FLAG_QUEUE_IS_TAKEN; + if (descr->flags & TIMER_FLAG_INTERRUPT_TRIGERRED) { + CRITICAL_SECTION_ENTER() + descr->flags &= ~TIMER_FLAG_INTERRUPT_TRIGERRED; + _timer_set_irq(&descr->device); + CRITICAL_SECTION_LEAVE() + } + + return ERR_NONE; +} + +/** + * \brief Retrieve the amount of clock cycles in a tick + */ +int32_t timer_get_clock_cycles_in_tick(const struct timer_descriptor *const descr, uint32_t *const cycles) +{ + ASSERT(descr && cycles); + *cycles = _timer_get_period(&descr->device); + return ERR_NONE; +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t timer_get_version(void) +{ + return DRIVER_VERSION; +} + +/** + * \internal Insert a timer task into sorted timer's list + * + * \param[in] head The pointer to the head of timer task list + * \param[in] task The pointer to task to add + * \param[in] time Current timer time + */ +static void timer_add_timer_task(struct list_descriptor *list, struct timer_task *const new_task, const uint32_t time) +{ + struct timer_task *it, *prev = NULL, *head = (struct timer_task *)list_get_head(list); + + if (!head) { + list_insert_as_head(list, new_task); + return; + } + + for (it = head; it; it = (struct timer_task *)list_get_next_element(it)) { + uint32_t time_left; + + if (it->time_label <= time) { + time_left = it->interval - (time - it->time_label); + } else { + time_left = it->interval - (0xFFFFFFFF - it->time_label) - time; + } + if (time_left >= new_task->interval) + break; + prev = it; + } + + if (it == head) { + list_insert_as_head(list, new_task); + } else { + list_insert_after(prev, new_task); + } +} + +/** + * \internal Process interrupts + */ +static void timer_process_counted(struct _timer_device *device) +{ + struct timer_descriptor *timer = CONTAINER_OF(device, struct timer_descriptor, device); + struct timer_task * it = (struct timer_task *)list_get_head(&timer->tasks); + uint32_t time = ++timer->time; + + if ((timer->flags & TIMER_FLAG_QUEUE_IS_TAKEN) || (timer->flags & TIMER_FLAG_INTERRUPT_TRIGERRED)) { + timer->flags |= TIMER_FLAG_INTERRUPT_TRIGERRED; + return; + } + + while (it && ((time - it->time_label) >= it->interval)) { + struct timer_task *tmp = it; + + list_remove_head(&timer->tasks); + if (TIMER_TASK_REPEAT == tmp->mode) { + tmp->time_label = time; + timer_add_timer_task(&timer->tasks, tmp, time); + } + it = (struct timer_task *)list_get_head(&timer->tasks); + + tmp->cb(tmp); + } +} diff --git a/software/firmware/oracle_same54n19a/hal/src/hal_usart_async.c b/software/firmware/oracle_same54n19a/hal/src/hal_usart_async.c new file mode 100644 index 00000000..f07b2661 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/src/hal_usart_async.c @@ -0,0 +1,420 @@ +/** + * \file + * + * \brief I/O USART related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include "hal_usart_async.h" +#include +#include +#include + +/** + * \brief Driver version + */ +#define DRIVER_VERSION 0x00000001u + +static int32_t usart_async_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length); +static int32_t usart_async_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length); +static void usart_process_byte_sent(struct _usart_async_device *device); +static void usart_transmission_complete(struct _usart_async_device *device); +static void usart_error(struct _usart_async_device *device); +static void usart_fill_rx_buffer(struct _usart_async_device *device, uint8_t data); + +/** + * \brief Initialize usart interface + */ +int32_t usart_async_init(struct usart_async_descriptor *const descr, void *const hw, uint8_t *rx_buffer, + uint16_t rx_buffer_length, void *const func) +{ + int32_t init_status; + ASSERT(descr && hw && rx_buffer && rx_buffer_length); + + if (ERR_NONE != ringbuffer_init(&descr->rx, rx_buffer, rx_buffer_length)) { + return ERR_INVALID_ARG; + } + init_status = _usart_async_init(&descr->device, hw); + if (init_status) { + return init_status; + } + + descr->io.read = usart_async_read; + descr->io.write = usart_async_write; + + descr->device.usart_cb.tx_byte_sent = usart_process_byte_sent; + descr->device.usart_cb.rx_done_cb = usart_fill_rx_buffer; + descr->device.usart_cb.tx_done_cb = usart_transmission_complete; + descr->device.usart_cb.error_cb = usart_error; + + return ERR_NONE; +} + +/** + * \brief Deinitialize usart interface + */ +int32_t usart_async_deinit(struct usart_async_descriptor *const descr) +{ + ASSERT(descr); + _usart_async_deinit(&descr->device); + descr->io.read = NULL; + descr->io.write = NULL; + + return ERR_NONE; +} + +/** + * \brief Enable usart interface + */ +int32_t usart_async_enable(struct usart_async_descriptor *const descr) +{ + ASSERT(descr); + _usart_async_enable(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Disable usart interface + */ +int32_t usart_async_disable(struct usart_async_descriptor *const descr) +{ + ASSERT(descr); + _usart_async_disable(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Retrieve I/O descriptor + */ +int32_t usart_async_get_io_descriptor(struct usart_async_descriptor *const descr, struct io_descriptor **io) +{ + ASSERT(descr && io); + + *io = &descr->io; + return ERR_NONE; +} + +/** + * \brief Register usart callback + */ +int32_t usart_async_register_callback(struct usart_async_descriptor *const descr, + const enum usart_async_callback_type type, usart_cb_t cb) +{ + ASSERT(descr); + + switch (type) { + case USART_ASYNC_RXC_CB: + descr->usart_cb.rx_done = cb; + _usart_async_set_irq_state(&descr->device, USART_ASYNC_RX_DONE, NULL != cb); + break; + case USART_ASYNC_TXC_CB: + descr->usart_cb.tx_done = cb; + _usart_async_set_irq_state(&descr->device, USART_ASYNC_TX_DONE, NULL != cb); + break; + case USART_ASYNC_ERROR_CB: + descr->usart_cb.error = cb; + _usart_async_set_irq_state(&descr->device, USART_ASYNC_ERROR, NULL != cb); + break; + default: + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} + +/** + * \brief Specify action for flow control pins + */ +int32_t usart_async_set_flow_control(struct usart_async_descriptor *const descr, + const union usart_flow_control_state state) +{ + ASSERT(descr); + _usart_async_set_flow_control_state(&descr->device, state); + + return ERR_NONE; +} + +/** + * \brief Set usart baud rate + */ +int32_t usart_async_set_baud_rate(struct usart_async_descriptor *const descr, const uint32_t baud_rate) +{ + ASSERT(descr); + _usart_async_set_baud_rate(&descr->device, baud_rate); + + return ERR_NONE; +} + +/** + * \brief Set usart data order + */ +int32_t usart_async_set_data_order(struct usart_async_descriptor *const descr, const enum usart_data_order data_order) +{ + ASSERT(descr); + _usart_async_set_data_order(&descr->device, data_order); + + return ERR_NONE; +} + +/** + * \brief Set usart mode + */ +int32_t usart_async_set_mode(struct usart_async_descriptor *const descr, const enum usart_mode mode) +{ + ASSERT(descr); + _usart_async_set_mode(&descr->device, mode); + + return ERR_NONE; +} + +/** + * \brief Set usart parity + */ +int32_t usart_async_set_parity(struct usart_async_descriptor *const descr, const enum usart_parity parity) +{ + ASSERT(descr); + _usart_async_set_parity(&descr->device, parity); + + return ERR_NONE; +} + +/** + * \brief Set usart stop bits + */ +int32_t usart_async_set_stopbits(struct usart_async_descriptor *const descr, const enum usart_stop_bits stop_bits) +{ + ASSERT(descr); + _usart_async_set_stop_bits(&descr->device, stop_bits); + + return ERR_NONE; +} + +/** + * \brief Set usart character size + */ +int32_t usart_async_set_character_size(struct usart_async_descriptor *const descr, const enum usart_character_size size) +{ + ASSERT(descr); + _usart_async_set_character_size(&descr->device, size); + + return ERR_NONE; +} + +/** + * \brief Retrieve the state of flow control pins + */ +int32_t usart_async_flow_control_status(const struct usart_async_descriptor *const descr, + union usart_flow_control_state *const state) +{ + ASSERT(descr && state); + *state = _usart_async_get_flow_control_state(&descr->device); + + return ERR_NONE; +} + +/** + * \brief Check if the usart transmitter is empty + */ +int32_t usart_async_is_tx_empty(const struct usart_async_descriptor *const descr) +{ + ASSERT(descr); + return _usart_async_is_byte_sent(&descr->device); +} + +/** + * \brief Check if the usart receiver is not empty + */ +int32_t usart_async_is_rx_not_empty(const struct usart_async_descriptor *const descr) +{ + ASSERT(descr); + + return ringbuffer_num(&descr->rx) > 0; +} + +/** + * \brief Retrieve the current interface status + */ +int32_t usart_async_get_status(struct usart_async_descriptor *const descr, struct usart_async_status *const status) +{ + ASSERT(descr); + + volatile uint32_t *tmp_stat = &(descr->stat); + volatile uint16_t *tmp_txcnt = &(descr->tx_por); + + if (status) { + status->flags = *tmp_stat; + status->txcnt = *tmp_txcnt; + status->rxcnt = ringbuffer_num(&descr->rx); + } + if (*tmp_stat & USART_ASYNC_STATUS_BUSY) { + return ERR_BUSY; + } + + return ERR_NONE; +} + +/** + * \brief flush usart rx ringbuf + */ +int32_t usart_async_flush_rx_buffer(struct usart_async_descriptor *const descr) +{ + ASSERT(descr); + + return ringbuffer_flush(&descr->rx); +} + +/** + * \brief Retrieve the current driver version + */ +uint32_t usart_async_get_version(void) +{ + return DRIVER_VERSION; +} + +/* + * \internal Write the given data to usart interface + * + * \param[in] descr The pointer to an io descriptor + * \param[in] buf Data to write to usart + * \param[in] length The number of bytes to write + * + * \return The number of bytes written. + */ +static int32_t usart_async_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length) +{ + struct usart_async_descriptor *descr = CONTAINER_OF(io_descr, struct usart_async_descriptor, io); + + ASSERT(descr && buf && length); + + if (descr->tx_por != descr->tx_buffer_length) { + return ERR_NO_RESOURCE; + } + descr->tx_buffer = (uint8_t *)buf; + descr->tx_buffer_length = length; + descr->tx_por = 0; + descr->stat = USART_ASYNC_STATUS_BUSY; + _usart_async_enable_byte_sent_irq(&descr->device); + + return (int32_t)length; +} + +/* + * \internal Read data from usart interface + * + * \param[in] descr The pointer to an io descriptor + * \param[in] buf A buffer to read data to + * \param[in] length The size of a buffer + * + * \return The number of bytes read. + */ +static int32_t usart_async_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length) +{ + uint16_t was_read = 0; + uint32_t num; + struct usart_async_descriptor *descr = CONTAINER_OF(io_descr, struct usart_async_descriptor, io); + + ASSERT(descr && buf && length); + + CRITICAL_SECTION_ENTER() + num = ringbuffer_num(&descr->rx); + CRITICAL_SECTION_LEAVE() + + while ((was_read < num) && (was_read < length)) { + ringbuffer_get(&descr->rx, &buf[was_read++]); + } + + return (int32_t)was_read; +} + +/** + * \brief Process "byte is sent" interrupt + * + * \param[in] device The pointer to device structure + */ +static void usart_process_byte_sent(struct _usart_async_device *device) +{ + struct usart_async_descriptor *descr = CONTAINER_OF(device, struct usart_async_descriptor, device); + if (descr->tx_por != descr->tx_buffer_length) { + _usart_async_write_byte(&descr->device, descr->tx_buffer[descr->tx_por++]); + _usart_async_enable_byte_sent_irq(&descr->device); + } else { + _usart_async_enable_tx_done_irq(&descr->device); + } +} + +/** + * \brief Process completion of data sending + * + * \param[in] device The pointer to device structure + */ +static void usart_transmission_complete(struct _usart_async_device *device) +{ + struct usart_async_descriptor *descr = CONTAINER_OF(device, struct usart_async_descriptor, device); + + descr->stat = 0; + if (descr->usart_cb.tx_done) { + descr->usart_cb.tx_done(descr); + } +} + +/** + * \brief Process byte reception + * + * \param[in] device The pointer to device structure + * \param[in] data Data read + */ +static void usart_fill_rx_buffer(struct _usart_async_device *device, uint8_t data) +{ + struct usart_async_descriptor *descr = CONTAINER_OF(device, struct usart_async_descriptor, device); + + ringbuffer_put(&descr->rx, data); + + if (descr->usart_cb.rx_done) { + descr->usart_cb.rx_done(descr); + } +} + +/** + * \brief Process error interrupt + * + * \param[in] device The pointer to device structure + */ +static void usart_error(struct _usart_async_device *device) +{ + struct usart_async_descriptor *descr = CONTAINER_OF(device, struct usart_async_descriptor, device); + + descr->stat = 0; + if (descr->usart_cb.error) { + descr->usart_cb.error(descr); + } +} + +//@} diff --git a/software/firmware/oracle_same54n19a/hal/utils/include/compiler.h b/software/firmware/oracle_same54n19a/hal/utils/include/compiler.h new file mode 100644 index 00000000..f35db3df --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/utils/include/compiler.h @@ -0,0 +1,64 @@ +/** + * \file + * + * \brief Header + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +/****************************************************************************** + * compiler.h + * + * Created: 05.05.2014 + * Author: N. Fomin + ******************************************************************************/ + +#ifndef _COMPILER_H +#define _COMPILER_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +#ifndef _UNIT_TEST_ +#include "parts.h" +#endif +#include "err_codes.h" + +#ifdef __cplusplus +} +#endif + +#endif /* _COMPILER_H */ diff --git a/software/firmware/oracle_same54n19a/hal/utils/include/err_codes.h b/software/firmware/oracle_same54n19a/hal/utils/include/err_codes.h new file mode 100644 index 00000000..a7aff018 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/utils/include/err_codes.h @@ -0,0 +1,73 @@ +/** + * \file + * + * \brief Error code definitions. + * + * This file defines various status codes returned by functions, + * indicating success or failure as well as what kind of failure. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef ERROR_CODES_H_INCLUDED +#define ERROR_CODES_H_INCLUDED + +#define ERR_NONE 0 +#define ERR_INVALID_DATA -1 +#define ERR_NO_CHANGE -2 +#define ERR_ABORTED -3 +#define ERR_BUSY -4 +#define ERR_SUSPEND -5 +#define ERR_IO -6 +#define ERR_REQ_FLUSHED -7 +#define ERR_TIMEOUT -8 +#define ERR_BAD_DATA -9 +#define ERR_NOT_FOUND -10 +#define ERR_UNSUPPORTED_DEV -11 +#define ERR_NO_MEMORY -12 +#define ERR_INVALID_ARG -13 +#define ERR_BAD_ADDRESS -14 +#define ERR_BAD_FORMAT -15 +#define ERR_BAD_FRQ -16 +#define ERR_DENIED -17 +#define ERR_ALREADY_INITIALIZED -18 +#define ERR_OVERFLOW -19 +#define ERR_NOT_INITIALIZED -20 +#define ERR_SAMPLERATE_UNAVAILABLE -21 +#define ERR_RESOLUTION_UNAVAILABLE -22 +#define ERR_BAUDRATE_UNAVAILABLE -23 +#define ERR_PACKET_COLLISION -24 +#define ERR_PROTOCOL -25 +#define ERR_PIN_MUX_INVALID -26 +#define ERR_UNSUPPORTED_OP -27 +#define ERR_NO_RESOURCE -28 +#define ERR_NOT_READY -29 +#define ERR_FAILURE -30 +#define ERR_WRONG_LENGTH -31 + +#endif diff --git a/software/firmware/oracle_same54n19a/hal/utils/include/events.h b/software/firmware/oracle_same54n19a/hal/utils/include/events.h new file mode 100644 index 00000000..3ee891a7 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/utils/include/events.h @@ -0,0 +1,54 @@ +/** + * \file + * + * \brief Events declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _EVENTS_H_INCLUDED +#define _EVENTS_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +/** + * \brief List of events. Must start with 0, be unique and follow numerical order. + */ +#define EVENT_IS_READY_TO_SLEEP_ID 0 +#define EVENT_PREPARE_TO_SLEEP_ID 1 +#define EVENT_WOKEN_UP_ID 2 + +#ifdef __cplusplus +} +#endif + +#endif /* _EVENTS_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/utils/include/parts.h b/software/firmware/oracle_same54n19a/hal/utils/include/parts.h new file mode 100644 index 00000000..98bb9690 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/utils/include/parts.h @@ -0,0 +1,41 @@ +/** + * \file + * + * \brief Atmel part identification macros + * + * Copyright (c) 2015-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef ATMEL_PARTS_H +#define ATMEL_PARTS_H + +#include "same54.h" + +#include "hri_e54.h" + +#endif /* ATMEL_PARTS_H */ diff --git a/software/firmware/oracle_same54n19a/hal/utils/include/utils.h b/software/firmware/oracle_same54n19a/hal/utils/include/utils.h new file mode 100644 index 00000000..1cf26996 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/utils/include/utils.h @@ -0,0 +1,368 @@ +/** + * \file + * + * \brief Different macros. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef UTILS_H_INCLUDED +#define UTILS_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_utils_macro + * + * @{ + */ + +/** + * \brief Retrieve pointer to parent structure + */ +#define CONTAINER_OF(ptr, type, field_name) ((type *)(((uint8_t *)ptr) - offsetof(type, field_name))) + +/** + * \brief Retrieve array size + */ +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) + +/** + * \brief Emit the compiler pragma \a arg. + * + * \param[in] arg The pragma directive as it would appear after \e \#pragma + * (i.e. not stringified). + */ +#define COMPILER_PRAGMA(arg) _Pragma(#arg) + +/** + * \def COMPILER_PACK_SET(alignment) + * \brief Set maximum alignment for subsequent struct and union definitions to \a alignment. + */ +#define COMPILER_PACK_SET(alignment) COMPILER_PRAGMA(pack(alignment)) + +/** + * \def COMPILER_PACK_RESET() + * \brief Set default alignment for subsequent struct and union definitions. + */ +#define COMPILER_PACK_RESET() COMPILER_PRAGMA(pack()) + +/** + * \brief Set aligned boundary. + */ +#if defined __GNUC__ +#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +#elif defined __ICCARM__ +#define COMPILER_ALIGNED(a) COMPILER_PRAGMA(data_alignment = a) +#elif defined __CC_ARM +#define COMPILER_ALIGNED(a) __attribute__((__aligned__(a))) +#endif + +/** + * \brief Flash located data macros + */ +#if defined __GNUC__ +#define PROGMEM_DECLARE(type, name) const type name +#define PROGMEM_T const +#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) +#define PROGMEM_PTR_T const * +#define PROGMEM_STRING_T const uint8_t * +#elif defined __ICCARM__ +#define PROGMEM_DECLARE(type, name) const type name +#define PROGMEM_T const +#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) +#define PROGMEM_PTR_T const * +#define PROGMEM_STRING_T const uint8_t * +#elif defined __CC_ARM +#define PROGMEM_DECLARE(type, name) const type name +#define PROGMEM_T const +#define PROGMEM_READ_BYTE(x) *((uint8_t *)(x)) +#define PROGMEM_PTR_T const * +#define PROGMEM_STRING_T const uint8_t * +#endif + +/** + * \brief Optimization + */ +#if defined __GNUC__ +#define OPTIMIZE_HIGH __attribute__((optimize(s))) +#elif defined __CC_ARM +#define OPTIMIZE_HIGH _Pragma("O3") +#elif defined __ICCARM__ +#define OPTIMIZE_HIGH _Pragma("optimize=high") +#endif + +/** + * \brief RAM located function attribute + */ +#if defined(__CC_ARM) /* Keil ?Vision 4 */ +#define RAMFUNC __attribute__((section(".ramfunc"))) +#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */ +#define RAMFUNC __ramfunc +#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */ +#define RAMFUNC __attribute__((section(".ramfunc"))) +#endif + +/** + * \brief No-init section. + * Place a data object or a function in a no-init section. + */ +#if defined(__CC_ARM) +#define NO_INIT(a) __attribute__((zero_init)) +#elif defined(__ICCARM__) +#define NO_INIT(a) __no_init +#elif defined(__GNUC__) +#define NO_INIT(a) __attribute__((section(".no_init"))) +#endif + +/** + * \brief Set user-defined section. + * Place a data object or a function in a user-defined section. + */ +#if defined(__CC_ARM) +#define COMPILER_SECTION(a) __attribute__((__section__(a))) +#elif defined(__ICCARM__) +#define COMPILER_SECTION(a) COMPILER_PRAGMA(location = a) +#elif defined(__GNUC__) +#define COMPILER_SECTION(a) __attribute__((__section__(a))) +#endif + +/** + * \brief Define WEAK attribute. + */ +#if defined(__CC_ARM) /* Keil ?Vision 4 */ +#define WEAK __attribute__((weak)) +#elif defined(__ICCARM__) /* IAR Ewarm 5.41+ */ +#define WEAK __weak +#elif defined(__GNUC__) /* GCC CS3 2009q3-68 */ +#define WEAK __attribute__((weak)) +#endif + +/** + * \brief Pointer to function + */ +typedef void (*FUNC_PTR)(void); + +#define LE_BYTE0(a) ((uint8_t)(a)) +#define LE_BYTE1(a) ((uint8_t)((a) >> 8)) +#define LE_BYTE2(a) ((uint8_t)((a) >> 16)) +#define LE_BYTE3(a) ((uint8_t)((a) >> 24)) + +#define LE_2_U16(p) ((p)[0] + ((p)[1] << 8)) +#define LE_2_U32(p) ((p)[0] + ((p)[1] << 8) + ((p)[2] << 16) + ((p)[3] << 24)) + +/** \name Zero-Bit Counting + * + * Under GCC, __builtin_clz and __builtin_ctz behave like macros when + * applied to constant expressions (values known at compile time), so they are + * more optimized than the use of the corresponding assembly instructions and + * they can be used as constant expressions e.g. to initialize objects having + * static storage duration, and like the corresponding assembly instructions + * when applied to non-constant expressions (values unknown at compile time), so + * they are more optimized than an assembly periphrasis. Hence, clz and ctz + * ensure a possible and optimized behavior for both constant and non-constant + * expressions. + * + * @{ */ + +/** \brief Counts the leading zero bits of the given value considered as a 32-bit integer. + * + * \param[in] u Value of which to count the leading zero bits. + * + * \return The count of leading zero bits in \a u. + */ +#if (defined __GNUC__) || (defined __CC_ARM) +#define clz(u) __builtin_clz(u) +#else +#define clz(u) \ + ( \ + ((u) == 0) \ + ? 32 \ + : ((u) & (1ul << 31)) \ + ? 0 \ + : ((u) & (1ul << 30)) \ + ? 1 \ + : ((u) & (1ul << 29)) \ + ? 2 \ + : ((u) & (1ul << 28)) \ + ? 3 \ + : ((u) & (1ul << 27)) \ + ? 4 \ + : ((u) & (1ul << 26)) \ + ? 5 \ + : ((u) & (1ul << 25)) \ + ? 6 \ + : ((u) & (1ul << 24)) \ + ? 7 \ + : ((u) & (1ul << 23)) \ + ? 8 \ + : ((u) & (1ul << 22)) \ + ? 9 \ + : ((u) & (1ul << 21)) \ + ? 10 \ + : ((u) & (1ul << 20)) \ + ? 11 \ + : ((u) & (1ul << 19)) \ + ? 12 \ + : ((u) & (1ul << 18)) \ + ? 13 \ + : ((u) & (1ul << 17)) ? 14 \ + : ((u) & (1ul << 16)) ? 15 \ + : ((u) & (1ul << 15)) ? 16 \ + : ((u) & (1ul << 14)) ? 17 \ + : ((u) & (1ul << 13)) ? 18 \ + : ((u) & (1ul << 12)) ? 19 \ + : ((u) \ + & (1ul \ + << 11)) \ + ? 20 \ + : ((u) \ + & (1ul \ + << 10)) \ + ? 21 \ + : ((u) \ + & (1ul \ + << 9)) \ + ? 22 \ + : ((u) \ + & (1ul \ + << 8)) \ + ? 23 \ + : ((u) & (1ul << 7)) ? 24 \ + : ((u) & (1ul << 6)) ? 25 \ + : ((u) \ + & (1ul \ + << 5)) \ + ? 26 \ + : ((u) & (1ul << 4)) ? 27 \ + : ((u) & (1ul << 3)) ? 28 \ + : ((u) & (1ul << 2)) ? 29 \ + : ( \ + (u) & (1ul << 1)) \ + ? 30 \ + : 31) +#endif + +/** \brief Counts the trailing zero bits of the given value considered as a 32-bit integer. + * + * \param[in] u Value of which to count the trailing zero bits. + * + * \return The count of trailing zero bits in \a u. + */ +#if (defined __GNUC__) || (defined __CC_ARM) +#define ctz(u) __builtin_ctz(u) +#else +#define ctz(u) \ + ( \ + (u) & (1ul << 0) \ + ? 0 \ + : (u) & (1ul << 1) \ + ? 1 \ + : (u) & (1ul << 2) \ + ? 2 \ + : (u) & (1ul << 3) \ + ? 3 \ + : (u) & (1ul << 4) \ + ? 4 \ + : (u) & (1ul << 5) \ + ? 5 \ + : (u) & (1ul << 6) \ + ? 6 \ + : (u) & (1ul << 7) \ + ? 7 \ + : (u) & (1ul << 8) \ + ? 8 \ + : (u) & (1ul << 9) \ + ? 9 \ + : (u) & (1ul << 10) \ + ? 10 \ + : (u) & (1ul << 11) \ + ? 11 \ + : (u) & (1ul << 12) \ + ? 12 \ + : (u) & (1ul << 13) \ + ? 13 \ + : (u) & (1ul << 14) \ + ? 14 \ + : (u) & (1ul << 15) \ + ? 15 \ + : (u) & (1ul << 16) \ + ? 16 \ + : (u) & (1ul << 17) \ + ? 17 \ + : (u) & (1ul << 18) \ + ? 18 \ + : (u) & (1ul << 19) ? 19 \ + : (u) & (1ul << 20) ? 20 \ + : (u) & (1ul << 21) ? 21 \ + : (u) & (1ul << 22) ? 22 \ + : (u) & (1ul << 23) ? 23 \ + : (u) & (1ul << 24) ? 24 \ + : (u) & (1ul << 25) ? 25 \ + : (u) & (1ul << 26) ? 26 \ + : (u) & (1ul << 27) ? 27 \ + : (u) & (1ul << 28) ? 28 : (u) & (1ul << 29) ? 29 : (u) & (1ul << 30) ? 30 : (u) & (1ul << 31) ? 31 : 32) +#endif +/** @} */ + +/** + * \brief Counts the number of bits in a mask (no more than 32 bits) + * \param[in] mask Mask of which to count the bits. + */ +#define size_of_mask(mask) (32 - clz(mask) - ctz(mask)) + +/** + * \brief Retrieve the start position of bits mask (no more than 32 bits) + * \param[in] mask Mask of which to retrieve the start position. + */ +#define pos_of_mask(mask) ctz(mask) + +/** + * \brief Return division result of a/b and round up the result to the closest + * number divisible by "b" + */ +#define round_up(a, b) (((a)-1) / (b) + 1) + +/** + * \brief Get the minimum of x and y + */ +#define min(x, y) ((x) > (y) ? (y) : (x)) + +/** + * \brief Get the maximum of x and y + */ +#define max(x, y) ((x) > (y) ? (x) : (y)) + +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif /* UTILS_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/utils/include/utils_assert.h b/software/firmware/oracle_same54n19a/hal/utils/include/utils_assert.h new file mode 100644 index 00000000..c2328d6c --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/utils/include/utils_assert.h @@ -0,0 +1,93 @@ +/** + * \file + * + * \brief Asserts related functionality. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _ASSERT_H_INCLUDED +#define _ASSERT_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#ifndef USE_SIMPLE_ASSERT +//# define USE_SIMPLE_ASSERT +#endif + +/** + * \brief Assert macro + * + * This macro is used to throw asserts. It can be mapped to different function + * based on debug level. + * + * \param[in] condition A condition to be checked; + * assert is thrown if the given condition is false + */ +#define ASSERT(condition) ASSERT_IMPL((condition), __FILE__, __LINE__) + +#ifdef DEBUG + +#ifdef USE_SIMPLE_ASSERT +#define ASSERT_IMPL(condition, file, line) \ + if (!(condition)) \ + __asm("BKPT #0"); +#else +#define ASSERT_IMPL(condition, file, line) assert((condition), file, line) +#endif + +#else /* DEBUG */ + +#ifdef USE_SIMPLE_ASSERT +#define ASSERT_IMPL(condition, file, line) ((void)0) +#else +#define ASSERT_IMPL(condition, file, line) ((void)0) +#endif + +#endif /* DEBUG */ + +/** + * \brief Assert function + * + * This function is used to throw asserts. + * + * \param[in] condition A condition to be checked; assert is thrown if the given + * condition is false + * \param[in] file File name + * \param[in] line Line number + */ +void assert(const bool condition, const char *const file, const int line); + +#ifdef __cplusplus +} +#endif +#endif /* _ASSERT_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/utils/include/utils_event.h b/software/firmware/oracle_same54n19a/hal/utils/include/utils_event.h new file mode 100644 index 00000000..13067c4f --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/utils/include/utils_event.h @@ -0,0 +1,115 @@ +/** + * \file + * + * \brief Events declaration. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_EVENT_H_INCLUDED +#define _UTILS_EVENT_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include + +/** + * \brief The maximum amount of events + */ +#define EVENT_MAX_AMOUNT 8 + +/** + * \brief The size of event mask used, it is EVENT_MAX_AMOUNT rounded up to the + * closest number divisible by 8. + */ +#define EVENT_MASK_SIZE (round_up(EVENT_MAX_AMOUNT, 8)) + +/** + * \brief The type of event ID. IDs should start with 0 and be in numerical order. + */ +typedef uint8_t event_id_t; + +/** + * \brief The type of returned parameter. This type is big enough to contain + * pointer to data on any platform. + */ +typedef uintptr_t event_data_t; + +/** + * \brief The type of returned parameter. This type is big enough to contain + * pointer to data on any platform. + */ +typedef void (*event_cb_t)(event_id_t id, event_data_t data); + +/** + * \brief Event structure + */ +struct event { + struct list_element elem; /*! The pointer to next event */ + uint8_t mask[EVENT_MASK_SIZE]; /*! Mask of event IDs callback is called for */ + event_cb_t cb; /*! Callback to be called when an event occurs */ +}; + +/** + * \brief Subscribe to event + * + * \param[in] event The pointer to event structure + * \param[in] id The event ID to subscribe to + * \param[in] cb The callback function to call when the given event occurs + * + * \return The status of subscription + */ +int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb); + +/** + * \brief Remove event from subscription + * + * \param[in] event The pointer to event structure + * \param[in] id The event ID to remove subscription from + * + * \return The status of subscription removing + */ +int32_t event_unsubscribe(struct event *const event, const event_id_t id); + +/** + * \brief Post event + * + * \param[in] id The event ID to post + * \param[in] data The event data to be passed to event subscribers + */ +void event_post(const event_id_t id, const event_data_t data); + +#ifdef __cplusplus +} +#endif + +#endif /* _UTILS_EVENT_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/utils/include/utils_increment_macro.h b/software/firmware/oracle_same54n19a/hal/utils/include/utils_increment_macro.h new file mode 100644 index 00000000..464c6cbb --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/utils/include/utils_increment_macro.h @@ -0,0 +1,308 @@ +/** + * \file + * + * \brief Increment macro. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_INCREMENT_MACRO_H +#define _UTILS_INCREMENT_MACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \brief Compile time increment, result value is entire integer literal + * + * \param[in] val - value to be incremented (254 max) + */ +#define INC_VALUE(val) SP_INC_##val + +// Preprocessor increment implementation +#define SP_INC_0 1 +#define SP_INC_1 2 +#define SP_INC_2 3 +#define SP_INC_3 4 +#define SP_INC_4 5 +#define SP_INC_5 6 +#define SP_INC_6 7 +#define SP_INC_7 8 +#define SP_INC_8 9 +#define SP_INC_9 10 +#define SP_INC_10 11 +#define SP_INC_11 12 +#define SP_INC_12 13 +#define SP_INC_13 14 +#define SP_INC_14 15 +#define SP_INC_15 16 +#define SP_INC_16 17 +#define SP_INC_17 18 +#define SP_INC_18 19 +#define SP_INC_19 20 +#define SP_INC_20 21 +#define SP_INC_21 22 +#define SP_INC_22 23 +#define SP_INC_23 24 +#define SP_INC_24 25 +#define SP_INC_25 26 +#define SP_INC_26 27 +#define SP_INC_27 28 +#define SP_INC_28 29 +#define SP_INC_29 30 +#define SP_INC_30 31 +#define SP_INC_31 32 +#define SP_INC_32 33 +#define SP_INC_33 34 +#define SP_INC_34 35 +#define SP_INC_35 36 +#define SP_INC_36 37 +#define SP_INC_37 38 +#define SP_INC_38 39 +#define SP_INC_39 40 +#define SP_INC_40 41 +#define SP_INC_41 42 +#define SP_INC_42 43 +#define SP_INC_43 44 +#define SP_INC_44 45 +#define SP_INC_45 46 +#define SP_INC_46 47 +#define SP_INC_47 48 +#define SP_INC_48 49 +#define SP_INC_49 50 +#define SP_INC_50 51 +#define SP_INC_51 52 +#define SP_INC_52 53 +#define SP_INC_53 54 +#define SP_INC_54 55 +#define SP_INC_55 56 +#define SP_INC_56 57 +#define SP_INC_57 58 +#define SP_INC_58 59 +#define SP_INC_59 60 +#define SP_INC_60 61 +#define SP_INC_61 62 +#define SP_INC_62 63 +#define SP_INC_63 64 +#define SP_INC_64 65 +#define SP_INC_65 66 +#define SP_INC_66 67 +#define SP_INC_67 68 +#define SP_INC_68 69 +#define SP_INC_69 70 +#define SP_INC_70 71 +#define SP_INC_71 72 +#define SP_INC_72 73 +#define SP_INC_73 74 +#define SP_INC_74 75 +#define SP_INC_75 76 +#define SP_INC_76 77 +#define SP_INC_77 78 +#define SP_INC_78 79 +#define SP_INC_79 80 +#define SP_INC_80 81 +#define SP_INC_81 82 +#define SP_INC_82 83 +#define SP_INC_83 84 +#define SP_INC_84 85 +#define SP_INC_85 86 +#define SP_INC_86 87 +#define SP_INC_87 88 +#define SP_INC_88 89 +#define SP_INC_89 90 +#define SP_INC_90 91 +#define SP_INC_91 92 +#define SP_INC_92 93 +#define SP_INC_93 94 +#define SP_INC_94 95 +#define SP_INC_95 96 +#define SP_INC_96 97 +#define SP_INC_97 98 +#define SP_INC_98 99 +#define SP_INC_99 100 +#define SP_INC_100 101 +#define SP_INC_101 102 +#define SP_INC_102 103 +#define SP_INC_103 104 +#define SP_INC_104 105 +#define SP_INC_105 106 +#define SP_INC_106 107 +#define SP_INC_107 108 +#define SP_INC_108 109 +#define SP_INC_109 110 +#define SP_INC_110 111 +#define SP_INC_111 112 +#define SP_INC_112 113 +#define SP_INC_113 114 +#define SP_INC_114 115 +#define SP_INC_115 116 +#define SP_INC_116 117 +#define SP_INC_117 118 +#define SP_INC_118 119 +#define SP_INC_119 120 +#define SP_INC_120 121 +#define SP_INC_121 122 +#define SP_INC_122 123 +#define SP_INC_123 124 +#define SP_INC_124 125 +#define SP_INC_125 126 +#define SP_INC_126 127 +#define SP_INC_127 128 +#define SP_INC_128 129 +#define SP_INC_129 130 +#define SP_INC_130 131 +#define SP_INC_131 132 +#define SP_INC_132 133 +#define SP_INC_133 134 +#define SP_INC_134 135 +#define SP_INC_135 136 +#define SP_INC_136 137 +#define SP_INC_137 138 +#define SP_INC_138 139 +#define SP_INC_139 140 +#define SP_INC_140 141 +#define SP_INC_141 142 +#define SP_INC_142 143 +#define SP_INC_143 144 +#define SP_INC_144 145 +#define SP_INC_145 146 +#define SP_INC_146 147 +#define SP_INC_147 148 +#define SP_INC_148 149 +#define SP_INC_149 150 +#define SP_INC_150 151 +#define SP_INC_151 152 +#define SP_INC_152 153 +#define SP_INC_153 154 +#define SP_INC_154 155 +#define SP_INC_155 156 +#define SP_INC_156 157 +#define SP_INC_157 158 +#define SP_INC_158 159 +#define SP_INC_159 160 +#define SP_INC_160 161 +#define SP_INC_161 162 +#define SP_INC_162 163 +#define SP_INC_163 164 +#define SP_INC_164 165 +#define SP_INC_165 166 +#define SP_INC_166 167 +#define SP_INC_167 168 +#define SP_INC_168 169 +#define SP_INC_169 170 +#define SP_INC_170 171 +#define SP_INC_171 172 +#define SP_INC_172 173 +#define SP_INC_173 174 +#define SP_INC_174 175 +#define SP_INC_175 176 +#define SP_INC_176 177 +#define SP_INC_177 178 +#define SP_INC_178 179 +#define SP_INC_179 180 +#define SP_INC_180 181 +#define SP_INC_181 182 +#define SP_INC_182 183 +#define SP_INC_183 184 +#define SP_INC_184 185 +#define SP_INC_185 186 +#define SP_INC_186 187 +#define SP_INC_187 188 +#define SP_INC_188 189 +#define SP_INC_189 190 +#define SP_INC_190 191 +#define SP_INC_191 192 +#define SP_INC_192 193 +#define SP_INC_193 194 +#define SP_INC_194 195 +#define SP_INC_195 196 +#define SP_INC_196 197 +#define SP_INC_197 198 +#define SP_INC_198 199 +#define SP_INC_199 200 +#define SP_INC_200 201 +#define SP_INC_201 202 +#define SP_INC_202 203 +#define SP_INC_203 204 +#define SP_INC_204 205 +#define SP_INC_205 206 +#define SP_INC_206 207 +#define SP_INC_207 208 +#define SP_INC_208 209 +#define SP_INC_209 210 +#define SP_INC_210 211 +#define SP_INC_211 212 +#define SP_INC_212 213 +#define SP_INC_213 214 +#define SP_INC_214 215 +#define SP_INC_215 216 +#define SP_INC_216 217 +#define SP_INC_217 218 +#define SP_INC_218 219 +#define SP_INC_219 220 +#define SP_INC_220 221 +#define SP_INC_221 222 +#define SP_INC_222 223 +#define SP_INC_223 224 +#define SP_INC_224 225 +#define SP_INC_225 226 +#define SP_INC_226 227 +#define SP_INC_227 228 +#define SP_INC_228 229 +#define SP_INC_229 230 +#define SP_INC_230 231 +#define SP_INC_231 232 +#define SP_INC_232 233 +#define SP_INC_233 234 +#define SP_INC_234 235 +#define SP_INC_235 236 +#define SP_INC_236 237 +#define SP_INC_237 238 +#define SP_INC_238 239 +#define SP_INC_239 240 +#define SP_INC_240 241 +#define SP_INC_241 242 +#define SP_INC_242 243 +#define SP_INC_243 244 +#define SP_INC_244 245 +#define SP_INC_245 246 +#define SP_INC_246 247 +#define SP_INC_247 248 +#define SP_INC_248 249 +#define SP_INC_249 250 +#define SP_INC_250 251 +#define SP_INC_251 252 +#define SP_INC_252 253 +#define SP_INC_253 254 +#define SP_INC_254 255 + +#ifdef __cplusplus +} +#endif +#endif /* _UTILS_INCREMENT_MACRO_H */ diff --git a/software/firmware/oracle_same54n19a/hal/utils/include/utils_list.h b/software/firmware/oracle_same54n19a/hal/utils/include/utils_list.h new file mode 100644 index 00000000..977e8cca --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/utils/include/utils_list.h @@ -0,0 +1,164 @@ +/** + * \file + * + * \brief List declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_LIST_H_INCLUDED +#define _UTILS_LIST_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_utils_list + * + * @{ + */ + +#include + +/** + * \brief List element type + */ +struct list_element { + struct list_element *next; +}; + +/** + * \brief List head type + */ +struct list_descriptor { + struct list_element *head; +}; + +/** + * \brief Reset list + * + * \param[in] list The pointer to a list descriptor + */ +static inline void list_reset(struct list_descriptor *const list) +{ + list->head = NULL; +} + +/** + * \brief Retrieve list head + * + * \param[in] list The pointer to a list descriptor + * + * \return A pointer to the head of the given list or NULL if the list is + * empty + */ +static inline void *list_get_head(const struct list_descriptor *const list) +{ + return (void *)list->head; +} + +/** + * \brief Retrieve next list head + * + * \param[in] list The pointer to a list element + * + * \return A pointer to the next list element or NULL if there is not next + * element + */ +static inline void *list_get_next_element(const void *const element) +{ + return element ? ((struct list_element *)element)->next : NULL; +} + +/** + * \brief Insert an element as list head + * + * \param[in] list The pointer to a list element + * \param[in] element An element to insert to the given list + */ +void list_insert_as_head(struct list_descriptor *const list, void *const element); + +/** + * \brief Insert an element after the given list element + * + * \param[in] after An element to insert after + * \param[in] element Element to insert to the given list + */ +void list_insert_after(void *const after, void *const element); + +/** + * \brief Insert an element at list end + * + * \param[in] after An element to insert after + * \param[in] element Element to insert to the given list + */ +void list_insert_at_end(struct list_descriptor *const list, void *const element); + +/** + * \brief Check whether an element belongs to a list + * + * \param[in] list The pointer to a list + * \param[in] element An element to check + * + * \return The result of checking + * \retval true If the given element is an element of the given list + * \retval false Otherwise + */ +bool is_list_element(const struct list_descriptor *const list, const void *const element); + +/** + * \brief Removes list head + * + * This function removes the list head and sets the next element after the list + * head as a new list head. + * + * \param[in] list The pointer to a list + * + * \return The pointer to the new list head of NULL if the list head is NULL + */ +void *list_remove_head(struct list_descriptor *const list); + +/** + * \brief Removes the list element + * + * \param[in] list The pointer to a list + * \param[in] element An element to remove + * + * \return The result of element removing + * \retval true The given element is removed from the given list + * \retval false The given element is not an element of the given list + */ +bool list_delete_element(struct list_descriptor *const list, const void *const element); + +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif /* _UTILS_LIST_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/utils/include/utils_repeat_macro.h b/software/firmware/oracle_same54n19a/hal/utils/include/utils_repeat_macro.h new file mode 100644 index 00000000..89e6f52d --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/utils/include/utils_repeat_macro.h @@ -0,0 +1,322 @@ +/** + * \file + * + * \brief Repeat macro. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _UTILS_REPEAT_MACRO_H +#define _UTILS_REPEAT_MACRO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* + * \brief Sequently repeates specified macro for n times (255 max). + * + * Specified macro shall have two arguments: macro(arg, i) + * arg - user defined argument, which have the same value for all iterations. + * i - iteration number; numbering begins from zero and increments on each + * iteration. + * + * \param[in] macro - macro to be repeated + * \param[in] arg - user defined argument for repeated macro + * \param[in] n - total number of iterations (255 max) + */ +#define REPEAT_MACRO(macro, arg, n) REPEAT_MACRO_I(macro, arg, n) + +/* + * \brief Second level is needed to get integer literal from "n" if it is + * defined as macro + */ +#define REPEAT_MACRO_I(macro, arg, n) REPEAT##n(macro, arg, 0) + +#define REPEAT1(macro, arg, n) macro(arg, n) +#define REPEAT2(macro, arg, n) macro(arg, n) REPEAT1(macro, arg, INC_VALUE(n)) +#define REPEAT3(macro, arg, n) macro(arg, n) REPEAT2(macro, arg, INC_VALUE(n)) +#define REPEAT4(macro, arg, n) macro(arg, n) REPEAT3(macro, arg, INC_VALUE(n)) +#define REPEAT5(macro, arg, n) macro(arg, n) REPEAT4(macro, arg, INC_VALUE(n)) +#define REPEAT6(macro, arg, n) macro(arg, n) REPEAT5(macro, arg, INC_VALUE(n)) +#define REPEAT7(macro, arg, n) macro(arg, n) REPEAT6(macro, arg, INC_VALUE(n)) +#define REPEAT8(macro, arg, n) macro(arg, n) REPEAT7(macro, arg, INC_VALUE(n)) +#define REPEAT9(macro, arg, n) macro(arg, n) REPEAT8(macro, arg, INC_VALUE(n)) +#define REPEAT10(macro, arg, n) macro(arg, n) REPEAT9(macro, arg, INC_VALUE(n)) +#define REPEAT11(macro, arg, n) macro(arg, n) REPEAT10(macro, arg, INC_VALUE(n)) +#define REPEAT12(macro, arg, n) macro(arg, n) REPEAT11(macro, arg, INC_VALUE(n)) +#define REPEAT13(macro, arg, n) macro(arg, n) REPEAT12(macro, arg, INC_VALUE(n)) +#define REPEAT14(macro, arg, n) macro(arg, n) REPEAT13(macro, arg, INC_VALUE(n)) +#define REPEAT15(macro, arg, n) macro(arg, n) REPEAT14(macro, arg, INC_VALUE(n)) +#define REPEAT16(macro, arg, n) macro(arg, n) REPEAT15(macro, arg, INC_VALUE(n)) +#define REPEAT17(macro, arg, n) macro(arg, n) REPEAT16(macro, arg, INC_VALUE(n)) +#define REPEAT18(macro, arg, n) macro(arg, n) REPEAT17(macro, arg, INC_VALUE(n)) +#define REPEAT19(macro, arg, n) macro(arg, n) REPEAT18(macro, arg, INC_VALUE(n)) +#define REPEAT20(macro, arg, n) macro(arg, n) REPEAT19(macro, arg, INC_VALUE(n)) +#define REPEAT21(macro, arg, n) macro(arg, n) REPEAT20(macro, arg, INC_VALUE(n)) +#define REPEAT22(macro, arg, n) macro(arg, n) REPEAT21(macro, arg, INC_VALUE(n)) +#define REPEAT23(macro, arg, n) macro(arg, n) REPEAT22(macro, arg, INC_VALUE(n)) +#define REPEAT24(macro, arg, n) macro(arg, n) REPEAT23(macro, arg, INC_VALUE(n)) +#define REPEAT25(macro, arg, n) macro(arg, n) REPEAT24(macro, arg, INC_VALUE(n)) +#define REPEAT26(macro, arg, n) macro(arg, n) REPEAT25(macro, arg, INC_VALUE(n)) +#define REPEAT27(macro, arg, n) macro(arg, n) REPEAT26(macro, arg, INC_VALUE(n)) +#define REPEAT28(macro, arg, n) macro(arg, n) REPEAT27(macro, arg, INC_VALUE(n)) +#define REPEAT29(macro, arg, n) macro(arg, n) REPEAT28(macro, arg, INC_VALUE(n)) +#define REPEAT30(macro, arg, n) macro(arg, n) REPEAT29(macro, arg, INC_VALUE(n)) +#define REPEAT31(macro, arg, n) macro(arg, n) REPEAT30(macro, arg, INC_VALUE(n)) +#define REPEAT32(macro, arg, n) macro(arg, n) REPEAT31(macro, arg, INC_VALUE(n)) +#define REPEAT33(macro, arg, n) macro(arg, n) REPEAT32(macro, arg, INC_VALUE(n)) +#define REPEAT34(macro, arg, n) macro(arg, n) REPEAT33(macro, arg, INC_VALUE(n)) +#define REPEAT35(macro, arg, n) macro(arg, n) REPEAT34(macro, arg, INC_VALUE(n)) +#define REPEAT36(macro, arg, n) macro(arg, n) REPEAT35(macro, arg, INC_VALUE(n)) +#define REPEAT37(macro, arg, n) macro(arg, n) REPEAT36(macro, arg, INC_VALUE(n)) +#define REPEAT38(macro, arg, n) macro(arg, n) REPEAT37(macro, arg, INC_VALUE(n)) +#define REPEAT39(macro, arg, n) macro(arg, n) REPEAT38(macro, arg, INC_VALUE(n)) +#define REPEAT40(macro, arg, n) macro(arg, n) REPEAT39(macro, arg, INC_VALUE(n)) +#define REPEAT41(macro, arg, n) macro(arg, n) REPEAT40(macro, arg, INC_VALUE(n)) +#define REPEAT42(macro, arg, n) macro(arg, n) REPEAT41(macro, arg, INC_VALUE(n)) +#define REPEAT43(macro, arg, n) macro(arg, n) REPEAT42(macro, arg, INC_VALUE(n)) +#define REPEAT44(macro, arg, n) macro(arg, n) REPEAT43(macro, arg, INC_VALUE(n)) +#define REPEAT45(macro, arg, n) macro(arg, n) REPEAT44(macro, arg, INC_VALUE(n)) +#define REPEAT46(macro, arg, n) macro(arg, n) REPEAT45(macro, arg, INC_VALUE(n)) +#define REPEAT47(macro, arg, n) macro(arg, n) REPEAT46(macro, arg, INC_VALUE(n)) +#define REPEAT48(macro, arg, n) macro(arg, n) REPEAT47(macro, arg, INC_VALUE(n)) +#define REPEAT49(macro, arg, n) macro(arg, n) REPEAT48(macro, arg, INC_VALUE(n)) +#define REPEAT50(macro, arg, n) macro(arg, n) REPEAT49(macro, arg, INC_VALUE(n)) +#define REPEAT51(macro, arg, n) macro(arg, n) REPEAT50(macro, arg, INC_VALUE(n)) +#define REPEAT52(macro, arg, n) macro(arg, n) REPEAT51(macro, arg, INC_VALUE(n)) +#define REPEAT53(macro, arg, n) macro(arg, n) REPEAT52(macro, arg, INC_VALUE(n)) +#define REPEAT54(macro, arg, n) macro(arg, n) REPEAT53(macro, arg, INC_VALUE(n)) +#define REPEAT55(macro, arg, n) macro(arg, n) REPEAT54(macro, arg, INC_VALUE(n)) +#define REPEAT56(macro, arg, n) macro(arg, n) REPEAT55(macro, arg, INC_VALUE(n)) +#define REPEAT57(macro, arg, n) macro(arg, n) REPEAT56(macro, arg, INC_VALUE(n)) +#define REPEAT58(macro, arg, n) macro(arg, n) REPEAT57(macro, arg, INC_VALUE(n)) +#define REPEAT59(macro, arg, n) macro(arg, n) REPEAT58(macro, arg, INC_VALUE(n)) +#define REPEAT60(macro, arg, n) macro(arg, n) REPEAT59(macro, arg, INC_VALUE(n)) +#define REPEAT61(macro, arg, n) macro(arg, n) REPEAT60(macro, arg, INC_VALUE(n)) +#define REPEAT62(macro, arg, n) macro(arg, n) REPEAT61(macro, arg, INC_VALUE(n)) +#define REPEAT63(macro, arg, n) macro(arg, n) REPEAT62(macro, arg, INC_VALUE(n)) +#define REPEAT64(macro, arg, n) macro(arg, n) REPEAT63(macro, arg, INC_VALUE(n)) +#define REPEAT65(macro, arg, n) macro(arg, n) REPEAT64(macro, arg, INC_VALUE(n)) +#define REPEAT66(macro, arg, n) macro(arg, n) REPEAT65(macro, arg, INC_VALUE(n)) +#define REPEAT67(macro, arg, n) macro(arg, n) REPEAT66(macro, arg, INC_VALUE(n)) +#define REPEAT68(macro, arg, n) macro(arg, n) REPEAT67(macro, arg, INC_VALUE(n)) +#define REPEAT69(macro, arg, n) macro(arg, n) REPEAT68(macro, arg, INC_VALUE(n)) +#define REPEAT70(macro, arg, n) macro(arg, n) REPEAT69(macro, arg, INC_VALUE(n)) +#define REPEAT71(macro, arg, n) macro(arg, n) REPEAT70(macro, arg, INC_VALUE(n)) +#define REPEAT72(macro, arg, n) macro(arg, n) REPEAT71(macro, arg, INC_VALUE(n)) +#define REPEAT73(macro, arg, n) macro(arg, n) REPEAT72(macro, arg, INC_VALUE(n)) +#define REPEAT74(macro, arg, n) macro(arg, n) REPEAT73(macro, arg, INC_VALUE(n)) +#define REPEAT75(macro, arg, n) macro(arg, n) REPEAT74(macro, arg, INC_VALUE(n)) +#define REPEAT76(macro, arg, n) macro(arg, n) REPEAT75(macro, arg, INC_VALUE(n)) +#define REPEAT77(macro, arg, n) macro(arg, n) REPEAT76(macro, arg, INC_VALUE(n)) +#define REPEAT78(macro, arg, n) macro(arg, n) REPEAT77(macro, arg, INC_VALUE(n)) +#define REPEAT79(macro, arg, n) macro(arg, n) REPEAT78(macro, arg, INC_VALUE(n)) +#define REPEAT80(macro, arg, n) macro(arg, n) REPEAT79(macro, arg, INC_VALUE(n)) +#define REPEAT81(macro, arg, n) macro(arg, n) REPEAT80(macro, arg, INC_VALUE(n)) +#define REPEAT82(macro, arg, n) macro(arg, n) REPEAT81(macro, arg, INC_VALUE(n)) +#define REPEAT83(macro, arg, n) macro(arg, n) REPEAT82(macro, arg, INC_VALUE(n)) +#define REPEAT84(macro, arg, n) macro(arg, n) REPEAT83(macro, arg, INC_VALUE(n)) +#define REPEAT85(macro, arg, n) macro(arg, n) REPEAT84(macro, arg, INC_VALUE(n)) +#define REPEAT86(macro, arg, n) macro(arg, n) REPEAT85(macro, arg, INC_VALUE(n)) +#define REPEAT87(macro, arg, n) macro(arg, n) REPEAT86(macro, arg, INC_VALUE(n)) +#define REPEAT88(macro, arg, n) macro(arg, n) REPEAT87(macro, arg, INC_VALUE(n)) +#define REPEAT89(macro, arg, n) macro(arg, n) REPEAT88(macro, arg, INC_VALUE(n)) +#define REPEAT90(macro, arg, n) macro(arg, n) REPEAT89(macro, arg, INC_VALUE(n)) +#define REPEAT91(macro, arg, n) macro(arg, n) REPEAT90(macro, arg, INC_VALUE(n)) +#define REPEAT92(macro, arg, n) macro(arg, n) REPEAT91(macro, arg, INC_VALUE(n)) +#define REPEAT93(macro, arg, n) macro(arg, n) REPEAT92(macro, arg, INC_VALUE(n)) +#define REPEAT94(macro, arg, n) macro(arg, n) REPEAT93(macro, arg, INC_VALUE(n)) +#define REPEAT95(macro, arg, n) macro(arg, n) REPEAT94(macro, arg, INC_VALUE(n)) +#define REPEAT96(macro, arg, n) macro(arg, n) REPEAT95(macro, arg, INC_VALUE(n)) +#define REPEAT97(macro, arg, n) macro(arg, n) REPEAT96(macro, arg, INC_VALUE(n)) +#define REPEAT98(macro, arg, n) macro(arg, n) REPEAT97(macro, arg, INC_VALUE(n)) +#define REPEAT99(macro, arg, n) macro(arg, n) REPEAT98(macro, arg, INC_VALUE(n)) +#define REPEAT100(macro, arg, n) macro(arg, n) REPEAT99(macro, arg, INC_VALUE(n)) +#define REPEAT101(macro, arg, n) macro(arg, n) REPEAT100(macro, arg, INC_VALUE(n)) +#define REPEAT102(macro, arg, n) macro(arg, n) REPEAT101(macro, arg, INC_VALUE(n)) +#define REPEAT103(macro, arg, n) macro(arg, n) REPEAT102(macro, arg, INC_VALUE(n)) +#define REPEAT104(macro, arg, n) macro(arg, n) REPEAT103(macro, arg, INC_VALUE(n)) +#define REPEAT105(macro, arg, n) macro(arg, n) REPEAT104(macro, arg, INC_VALUE(n)) +#define REPEAT106(macro, arg, n) macro(arg, n) REPEAT105(macro, arg, INC_VALUE(n)) +#define REPEAT107(macro, arg, n) macro(arg, n) REPEAT106(macro, arg, INC_VALUE(n)) +#define REPEAT108(macro, arg, n) macro(arg, n) REPEAT107(macro, arg, INC_VALUE(n)) +#define REPEAT109(macro, arg, n) macro(arg, n) REPEAT108(macro, arg, INC_VALUE(n)) +#define REPEAT110(macro, arg, n) macro(arg, n) REPEAT109(macro, arg, INC_VALUE(n)) +#define REPEAT111(macro, arg, n) macro(arg, n) REPEAT110(macro, arg, INC_VALUE(n)) +#define REPEAT112(macro, arg, n) macro(arg, n) REPEAT111(macro, arg, INC_VALUE(n)) +#define REPEAT113(macro, arg, n) macro(arg, n) REPEAT112(macro, arg, INC_VALUE(n)) +#define REPEAT114(macro, arg, n) macro(arg, n) REPEAT113(macro, arg, INC_VALUE(n)) +#define REPEAT115(macro, arg, n) macro(arg, n) REPEAT114(macro, arg, INC_VALUE(n)) +#define REPEAT116(macro, arg, n) macro(arg, n) REPEAT115(macro, arg, INC_VALUE(n)) +#define REPEAT117(macro, arg, n) macro(arg, n) REPEAT116(macro, arg, INC_VALUE(n)) +#define REPEAT118(macro, arg, n) macro(arg, n) REPEAT117(macro, arg, INC_VALUE(n)) +#define REPEAT119(macro, arg, n) macro(arg, n) REPEAT118(macro, arg, INC_VALUE(n)) +#define REPEAT120(macro, arg, n) macro(arg, n) REPEAT119(macro, arg, INC_VALUE(n)) +#define REPEAT121(macro, arg, n) macro(arg, n) REPEAT120(macro, arg, INC_VALUE(n)) +#define REPEAT122(macro, arg, n) macro(arg, n) REPEAT121(macro, arg, INC_VALUE(n)) +#define REPEAT123(macro, arg, n) macro(arg, n) REPEAT122(macro, arg, INC_VALUE(n)) +#define REPEAT124(macro, arg, n) macro(arg, n) REPEAT123(macro, arg, INC_VALUE(n)) +#define REPEAT125(macro, arg, n) macro(arg, n) REPEAT124(macro, arg, INC_VALUE(n)) +#define REPEAT126(macro, arg, n) macro(arg, n) REPEAT125(macro, arg, INC_VALUE(n)) +#define REPEAT127(macro, arg, n) macro(arg, n) REPEAT126(macro, arg, INC_VALUE(n)) +#define REPEAT128(macro, arg, n) macro(arg, n) REPEAT127(macro, arg, INC_VALUE(n)) +#define REPEAT129(macro, arg, n) macro(arg, n) REPEAT128(macro, arg, INC_VALUE(n)) +#define REPEAT130(macro, arg, n) macro(arg, n) REPEAT129(macro, arg, INC_VALUE(n)) +#define REPEAT131(macro, arg, n) macro(arg, n) REPEAT130(macro, arg, INC_VALUE(n)) +#define REPEAT132(macro, arg, n) macro(arg, n) REPEAT131(macro, arg, INC_VALUE(n)) +#define REPEAT133(macro, arg, n) macro(arg, n) REPEAT132(macro, arg, INC_VALUE(n)) +#define REPEAT134(macro, arg, n) macro(arg, n) REPEAT133(macro, arg, INC_VALUE(n)) +#define REPEAT135(macro, arg, n) macro(arg, n) REPEAT134(macro, arg, INC_VALUE(n)) +#define REPEAT136(macro, arg, n) macro(arg, n) REPEAT135(macro, arg, INC_VALUE(n)) +#define REPEAT137(macro, arg, n) macro(arg, n) REPEAT136(macro, arg, INC_VALUE(n)) +#define REPEAT138(macro, arg, n) macro(arg, n) REPEAT137(macro, arg, INC_VALUE(n)) +#define REPEAT139(macro, arg, n) macro(arg, n) REPEAT138(macro, arg, INC_VALUE(n)) +#define REPEAT140(macro, arg, n) macro(arg, n) REPEAT139(macro, arg, INC_VALUE(n)) +#define REPEAT141(macro, arg, n) macro(arg, n) REPEAT140(macro, arg, INC_VALUE(n)) +#define REPEAT142(macro, arg, n) macro(arg, n) REPEAT141(macro, arg, INC_VALUE(n)) +#define REPEAT143(macro, arg, n) macro(arg, n) REPEAT142(macro, arg, INC_VALUE(n)) +#define REPEAT144(macro, arg, n) macro(arg, n) REPEAT143(macro, arg, INC_VALUE(n)) +#define REPEAT145(macro, arg, n) macro(arg, n) REPEAT144(macro, arg, INC_VALUE(n)) +#define REPEAT146(macro, arg, n) macro(arg, n) REPEAT145(macro, arg, INC_VALUE(n)) +#define REPEAT147(macro, arg, n) macro(arg, n) REPEAT146(macro, arg, INC_VALUE(n)) +#define REPEAT148(macro, arg, n) macro(arg, n) REPEAT147(macro, arg, INC_VALUE(n)) +#define REPEAT149(macro, arg, n) macro(arg, n) REPEAT148(macro, arg, INC_VALUE(n)) +#define REPEAT150(macro, arg, n) macro(arg, n) REPEAT149(macro, arg, INC_VALUE(n)) +#define REPEAT151(macro, arg, n) macro(arg, n) REPEAT150(macro, arg, INC_VALUE(n)) +#define REPEAT152(macro, arg, n) macro(arg, n) REPEAT151(macro, arg, INC_VALUE(n)) +#define REPEAT153(macro, arg, n) macro(arg, n) REPEAT152(macro, arg, INC_VALUE(n)) +#define REPEAT154(macro, arg, n) macro(arg, n) REPEAT153(macro, arg, INC_VALUE(n)) +#define REPEAT155(macro, arg, n) macro(arg, n) REPEAT154(macro, arg, INC_VALUE(n)) +#define REPEAT156(macro, arg, n) macro(arg, n) REPEAT155(macro, arg, INC_VALUE(n)) +#define REPEAT157(macro, arg, n) macro(arg, n) REPEAT156(macro, arg, INC_VALUE(n)) +#define REPEAT158(macro, arg, n) macro(arg, n) REPEAT157(macro, arg, INC_VALUE(n)) +#define REPEAT159(macro, arg, n) macro(arg, n) REPEAT158(macro, arg, INC_VALUE(n)) +#define REPEAT160(macro, arg, n) macro(arg, n) REPEAT159(macro, arg, INC_VALUE(n)) +#define REPEAT161(macro, arg, n) macro(arg, n) REPEAT160(macro, arg, INC_VALUE(n)) +#define REPEAT162(macro, arg, n) macro(arg, n) REPEAT161(macro, arg, INC_VALUE(n)) +#define REPEAT163(macro, arg, n) macro(arg, n) REPEAT162(macro, arg, INC_VALUE(n)) +#define REPEAT164(macro, arg, n) macro(arg, n) REPEAT163(macro, arg, INC_VALUE(n)) +#define REPEAT165(macro, arg, n) macro(arg, n) REPEAT164(macro, arg, INC_VALUE(n)) +#define REPEAT166(macro, arg, n) macro(arg, n) REPEAT165(macro, arg, INC_VALUE(n)) +#define REPEAT167(macro, arg, n) macro(arg, n) REPEAT166(macro, arg, INC_VALUE(n)) +#define REPEAT168(macro, arg, n) macro(arg, n) REPEAT167(macro, arg, INC_VALUE(n)) +#define REPEAT169(macro, arg, n) macro(arg, n) REPEAT168(macro, arg, INC_VALUE(n)) +#define REPEAT170(macro, arg, n) macro(arg, n) REPEAT169(macro, arg, INC_VALUE(n)) +#define REPEAT171(macro, arg, n) macro(arg, n) REPEAT170(macro, arg, INC_VALUE(n)) +#define REPEAT172(macro, arg, n) macro(arg, n) REPEAT171(macro, arg, INC_VALUE(n)) +#define REPEAT173(macro, arg, n) macro(arg, n) REPEAT172(macro, arg, INC_VALUE(n)) +#define REPEAT174(macro, arg, n) macro(arg, n) REPEAT173(macro, arg, INC_VALUE(n)) +#define REPEAT175(macro, arg, n) macro(arg, n) REPEAT174(macro, arg, INC_VALUE(n)) +#define REPEAT176(macro, arg, n) macro(arg, n) REPEAT175(macro, arg, INC_VALUE(n)) +#define REPEAT177(macro, arg, n) macro(arg, n) REPEAT176(macro, arg, INC_VALUE(n)) +#define REPEAT178(macro, arg, n) macro(arg, n) REPEAT177(macro, arg, INC_VALUE(n)) +#define REPEAT179(macro, arg, n) macro(arg, n) REPEAT178(macro, arg, INC_VALUE(n)) +#define REPEAT180(macro, arg, n) macro(arg, n) REPEAT179(macro, arg, INC_VALUE(n)) +#define REPEAT181(macro, arg, n) macro(arg, n) REPEAT180(macro, arg, INC_VALUE(n)) +#define REPEAT182(macro, arg, n) macro(arg, n) REPEAT181(macro, arg, INC_VALUE(n)) +#define REPEAT183(macro, arg, n) macro(arg, n) REPEAT182(macro, arg, INC_VALUE(n)) +#define REPEAT184(macro, arg, n) macro(arg, n) REPEAT183(macro, arg, INC_VALUE(n)) +#define REPEAT185(macro, arg, n) macro(arg, n) REPEAT184(macro, arg, INC_VALUE(n)) +#define REPEAT186(macro, arg, n) macro(arg, n) REPEAT185(macro, arg, INC_VALUE(n)) +#define REPEAT187(macro, arg, n) macro(arg, n) REPEAT186(macro, arg, INC_VALUE(n)) +#define REPEAT188(macro, arg, n) macro(arg, n) REPEAT187(macro, arg, INC_VALUE(n)) +#define REPEAT189(macro, arg, n) macro(arg, n) REPEAT188(macro, arg, INC_VALUE(n)) +#define REPEAT190(macro, arg, n) macro(arg, n) REPEAT189(macro, arg, INC_VALUE(n)) +#define REPEAT191(macro, arg, n) macro(arg, n) REPEAT190(macro, arg, INC_VALUE(n)) +#define REPEAT192(macro, arg, n) macro(arg, n) REPEAT191(macro, arg, INC_VALUE(n)) +#define REPEAT193(macro, arg, n) macro(arg, n) REPEAT192(macro, arg, INC_VALUE(n)) +#define REPEAT194(macro, arg, n) macro(arg, n) REPEAT193(macro, arg, INC_VALUE(n)) +#define REPEAT195(macro, arg, n) macro(arg, n) REPEAT194(macro, arg, INC_VALUE(n)) +#define REPEAT196(macro, arg, n) macro(arg, n) REPEAT195(macro, arg, INC_VALUE(n)) +#define REPEAT197(macro, arg, n) macro(arg, n) REPEAT196(macro, arg, INC_VALUE(n)) +#define REPEAT198(macro, arg, n) macro(arg, n) REPEAT197(macro, arg, INC_VALUE(n)) +#define REPEAT199(macro, arg, n) macro(arg, n) REPEAT198(macro, arg, INC_VALUE(n)) +#define REPEAT200(macro, arg, n) macro(arg, n) REPEAT199(macro, arg, INC_VALUE(n)) +#define REPEAT201(macro, arg, n) macro(arg, n) REPEAT200(macro, arg, INC_VALUE(n)) +#define REPEAT202(macro, arg, n) macro(arg, n) REPEAT201(macro, arg, INC_VALUE(n)) +#define REPEAT203(macro, arg, n) macro(arg, n) REPEAT202(macro, arg, INC_VALUE(n)) +#define REPEAT204(macro, arg, n) macro(arg, n) REPEAT203(macro, arg, INC_VALUE(n)) +#define REPEAT205(macro, arg, n) macro(arg, n) REPEAT204(macro, arg, INC_VALUE(n)) +#define REPEAT206(macro, arg, n) macro(arg, n) REPEAT205(macro, arg, INC_VALUE(n)) +#define REPEAT207(macro, arg, n) macro(arg, n) REPEAT206(macro, arg, INC_VALUE(n)) +#define REPEAT208(macro, arg, n) macro(arg, n) REPEAT207(macro, arg, INC_VALUE(n)) +#define REPEAT209(macro, arg, n) macro(arg, n) REPEAT208(macro, arg, INC_VALUE(n)) +#define REPEAT210(macro, arg, n) macro(arg, n) REPEAT209(macro, arg, INC_VALUE(n)) +#define REPEAT211(macro, arg, n) macro(arg, n) REPEAT210(macro, arg, INC_VALUE(n)) +#define REPEAT212(macro, arg, n) macro(arg, n) REPEAT211(macro, arg, INC_VALUE(n)) +#define REPEAT213(macro, arg, n) macro(arg, n) REPEAT212(macro, arg, INC_VALUE(n)) +#define REPEAT214(macro, arg, n) macro(arg, n) REPEAT213(macro, arg, INC_VALUE(n)) +#define REPEAT215(macro, arg, n) macro(arg, n) REPEAT214(macro, arg, INC_VALUE(n)) +#define REPEAT216(macro, arg, n) macro(arg, n) REPEAT215(macro, arg, INC_VALUE(n)) +#define REPEAT217(macro, arg, n) macro(arg, n) REPEAT216(macro, arg, INC_VALUE(n)) +#define REPEAT218(macro, arg, n) macro(arg, n) REPEAT217(macro, arg, INC_VALUE(n)) +#define REPEAT219(macro, arg, n) macro(arg, n) REPEAT218(macro, arg, INC_VALUE(n)) +#define REPEAT220(macro, arg, n) macro(arg, n) REPEAT219(macro, arg, INC_VALUE(n)) +#define REPEAT221(macro, arg, n) macro(arg, n) REPEAT220(macro, arg, INC_VALUE(n)) +#define REPEAT222(macro, arg, n) macro(arg, n) REPEAT221(macro, arg, INC_VALUE(n)) +#define REPEAT223(macro, arg, n) macro(arg, n) REPEAT222(macro, arg, INC_VALUE(n)) +#define REPEAT224(macro, arg, n) macro(arg, n) REPEAT223(macro, arg, INC_VALUE(n)) +#define REPEAT225(macro, arg, n) macro(arg, n) REPEAT224(macro, arg, INC_VALUE(n)) +#define REPEAT226(macro, arg, n) macro(arg, n) REPEAT225(macro, arg, INC_VALUE(n)) +#define REPEAT227(macro, arg, n) macro(arg, n) REPEAT226(macro, arg, INC_VALUE(n)) +#define REPEAT228(macro, arg, n) macro(arg, n) REPEAT227(macro, arg, INC_VALUE(n)) +#define REPEAT229(macro, arg, n) macro(arg, n) REPEAT228(macro, arg, INC_VALUE(n)) +#define REPEAT230(macro, arg, n) macro(arg, n) REPEAT229(macro, arg, INC_VALUE(n)) +#define REPEAT231(macro, arg, n) macro(arg, n) REPEAT230(macro, arg, INC_VALUE(n)) +#define REPEAT232(macro, arg, n) macro(arg, n) REPEAT231(macro, arg, INC_VALUE(n)) +#define REPEAT233(macro, arg, n) macro(arg, n) REPEAT232(macro, arg, INC_VALUE(n)) +#define REPEAT234(macro, arg, n) macro(arg, n) REPEAT233(macro, arg, INC_VALUE(n)) +#define REPEAT235(macro, arg, n) macro(arg, n) REPEAT234(macro, arg, INC_VALUE(n)) +#define REPEAT236(macro, arg, n) macro(arg, n) REPEAT235(macro, arg, INC_VALUE(n)) +#define REPEAT237(macro, arg, n) macro(arg, n) REPEAT236(macro, arg, INC_VALUE(n)) +#define REPEAT238(macro, arg, n) macro(arg, n) REPEAT237(macro, arg, INC_VALUE(n)) +#define REPEAT239(macro, arg, n) macro(arg, n) REPEAT238(macro, arg, INC_VALUE(n)) +#define REPEAT240(macro, arg, n) macro(arg, n) REPEAT239(macro, arg, INC_VALUE(n)) +#define REPEAT241(macro, arg, n) macro(arg, n) REPEAT240(macro, arg, INC_VALUE(n)) +#define REPEAT242(macro, arg, n) macro(arg, n) REPEAT241(macro, arg, INC_VALUE(n)) +#define REPEAT243(macro, arg, n) macro(arg, n) REPEAT242(macro, arg, INC_VALUE(n)) +#define REPEAT244(macro, arg, n) macro(arg, n) REPEAT243(macro, arg, INC_VALUE(n)) +#define REPEAT245(macro, arg, n) macro(arg, n) REPEAT244(macro, arg, INC_VALUE(n)) +#define REPEAT246(macro, arg, n) macro(arg, n) REPEAT245(macro, arg, INC_VALUE(n)) +#define REPEAT247(macro, arg, n) macro(arg, n) REPEAT246(macro, arg, INC_VALUE(n)) +#define REPEAT248(macro, arg, n) macro(arg, n) REPEAT247(macro, arg, INC_VALUE(n)) +#define REPEAT249(macro, arg, n) macro(arg, n) REPEAT248(macro, arg, INC_VALUE(n)) +#define REPEAT250(macro, arg, n) macro(arg, n) REPEAT249(macro, arg, INC_VALUE(n)) +#define REPEAT251(macro, arg, n) macro(arg, n) REPEAT250(macro, arg, INC_VALUE(n)) +#define REPEAT252(macro, arg, n) macro(arg, n) REPEAT251(macro, arg, INC_VALUE(n)) +#define REPEAT253(macro, arg, n) macro(arg, n) REPEAT252(macro, arg, INC_VALUE(n)) +#define REPEAT254(macro, arg, n) macro(arg, n) REPEAT253(macro, arg, INC_VALUE(n)) +#define REPEAT255(macro, arg, n) macro(arg, n) REPEAT254(macro, arg, INC_VALUE(n)) + +#ifdef __cplusplus +} +#endif + +#include +#endif /* _UTILS_REPEAT_MACRO_H */ diff --git a/software/firmware/oracle_same54n19a/hal/utils/include/utils_ringbuffer.h b/software/firmware/oracle_same54n19a/hal/utils/include/utils_ringbuffer.h new file mode 100644 index 00000000..401d5572 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/utils/include/utils_ringbuffer.h @@ -0,0 +1,116 @@ +/** + * \file + * + * \brief Ringbuffer declaration. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#ifndef _UTILS_RINGBUFFER_H_INCLUDED +#define _UTILS_RINGBUFFER_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup doc_driver_hal_utils_ringbuffer + * + * @{ + */ + +#include "compiler.h" +#include "utils_assert.h" + +/** + * \brief Ring buffer element type + */ +struct ringbuffer { + uint8_t *buf; /** Buffer base address */ + uint32_t size; /** Buffer size */ + uint32_t read_index; /** Buffer read index */ + uint32_t write_index; /** Buffer write index */ +}; + +/** + * \brief Ring buffer init + * + * \param[in] rb The pointer to a ring buffer structure instance + * \param[in] buf Space to store the data + * \param[in] size The buffer length, must be aligned with power of 2 + * + * \return ERR_NONE on success, or an error code on failure. + */ +int32_t ringbuffer_init(struct ringbuffer *const rb, void *buf, uint32_t size); + +/** + * \brief Get one byte from ring buffer, the user needs to handle the concurrent + * access on buffer via put/get/flush + * + * \param[in] rb The pointer to a ring buffer structure instance + * \param[in] data One byte space to store the read data + * + * \return ERR_NONE on success, or an error code on failure. + */ +int32_t ringbuffer_get(struct ringbuffer *const rb, uint8_t *data); + +/** + * \brief Put one byte to ring buffer, the user needs to handle the concurrent access + * on buffer via put/get/flush + * + * \param[in] rb The pointer to a ring buffer structure instance + * \param[in] data One byte data to be put into ring buffer + * + * \return ERR_NONE on success, or an error code on failure. + */ +int32_t ringbuffer_put(struct ringbuffer *const rb, uint8_t data); + +/** + * \brief Return the element number of ring buffer + * + * \param[in] rb The pointer to a ring buffer structure instance + * + * \return The number of elements in ring buffer [0, rb->size] + */ +uint32_t ringbuffer_num(const struct ringbuffer *const rb); + +/** + * \brief Flush ring buffer, the user needs to handle the concurrent access on buffer + * via put/get/flush + * + * \param[in] rb The pointer to a ring buffer structure instance + * + * \return ERR_NONE on success, or an error code on failure. + */ +uint32_t ringbuffer_flush(struct ringbuffer *const rb); + +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif /* _UTILS_RINGBUFFER_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hal/utils/src/utils_assert.c b/software/firmware/oracle_same54n19a/hal/utils/src/utils_assert.c new file mode 100644 index 00000000..b376c970 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/utils/src/utils_assert.c @@ -0,0 +1,46 @@ +/** + * \file + * + * \brief Asserts related functionality. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include + +/** + * \brief Assert function + */ +void assert(const bool condition, const char *const file, const int line) +{ + if (!(condition)) { + __asm("BKPT #0"); + } + (void)file; + (void)line; +} diff --git a/software/firmware/oracle_same54n19a/hal/utils/src/utils_event.c b/software/firmware/oracle_same54n19a/hal/utils/src/utils_event.c new file mode 100644 index 00000000..d1af9d0c --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/utils/src/utils_event.c @@ -0,0 +1,125 @@ +/** + * \file + * + * \brief Events implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +#define EVENT_WORD_BITS (sizeof(event_word_t) * 8) + +static struct list_descriptor events; +static uint8_t subscribed[EVENT_MASK_SIZE]; + +int32_t event_subscribe(struct event *const event, const event_id_t id, event_cb_t cb) +{ + /* get byte and bit number of the given event in the event mask */ + const uint8_t position = id >> 3; + const uint8_t mask = 1 << (id & 0x7); + + ASSERT(event && cb && (id < EVENT_MAX_AMOUNT)); + + if (event->mask[position] & mask) { + return ERR_NO_CHANGE; /* Already subscribed */ + } + + if (!is_list_element(&events, event)) { + memset(event->mask, 0, EVENT_MASK_SIZE); + list_insert_as_head(&events, event); + } + event->cb = cb; + event->mask[position] |= mask; + + subscribed[position] |= mask; + + return ERR_NONE; +} + +int32_t event_unsubscribe(struct event *const event, const event_id_t id) +{ + /* get byte and bit number of the given event in the event mask */ + const uint8_t position = id >> 3; + const uint8_t mask = 1 << (id & 0x7); + const struct event *current; + uint8_t i; + + ASSERT(event && (id < EVENT_MAX_AMOUNT)); + + if (!(event->mask[position] & mask)) { + return ERR_NO_CHANGE; /* Already unsubscribed */ + } + + event->mask[position] &= ~mask; + + /* Check if there are more subscribers */ + for ((current = (const struct event *)list_get_head(&events)); current; + current = (const struct event *)list_get_next_element(current)) { + if (current->mask[position] & mask) { + break; + } + } + if (!current) { + subscribed[position] &= ~mask; + } + + /* Remove event from the list. Can be unsave, document it! */ + for (i = 0; i < ARRAY_SIZE(event->mask); i++) { + if (event->mask[i]) { + return ERR_NONE; + } + } + list_delete_element(&events, event); + + return ERR_NONE; +} + +void event_post(const event_id_t id, const event_data_t data) +{ + /* get byte and bit number of the given event in the event mask */ + const uint8_t position = id >> 3; + const uint8_t mask = 1 << (id & 0x7); + const struct event *current; + + ASSERT((id < EVENT_MAX_AMOUNT)); + + if (!(subscribed[position] & mask)) { + return; /* No subscribers */ + } + + /* Find all subscribers */ + for ((current = (const struct event *)list_get_head(&events)); current; + current = (const struct event *)list_get_next_element(current)) { + if (current->mask[position] & mask) { + current->cb(id, data); + } + } +} diff --git a/software/firmware/oracle_same54n19a/hal/utils/src/utils_list.c b/software/firmware/oracle_same54n19a/hal/utils/src/utils_list.c new file mode 100644 index 00000000..4006a019 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/utils/src/utils_list.c @@ -0,0 +1,136 @@ +/** + * \file + * + * \brief List functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Check whether element belongs to list + */ +bool is_list_element(const struct list_descriptor *const list, const void *const element) +{ + struct list_element *it; + for (it = list->head; it; it = it->next) { + if (it == element) { + return true; + } + } + + return false; +} + +/** + * \brief Insert an element as list head + */ +void list_insert_as_head(struct list_descriptor *const list, void *const element) +{ + ASSERT(!is_list_element(list, element)); + + ((struct list_element *)element)->next = list->head; + list->head = (struct list_element *)element; +} + +/** + * \brief Insert an element after the given list element + */ +void list_insert_after(void *const after, void *const element) +{ + ((struct list_element *)element)->next = ((struct list_element *)after)->next; + ((struct list_element *)after)->next = (struct list_element *)element; +} + +/** + * \brief Insert an element at list end + */ +void list_insert_at_end(struct list_descriptor *const list, void *const element) +{ + struct list_element *it = list->head; + + ASSERT(!is_list_element(list, element)); + + if (!list->head) { + list->head = (struct list_element *)element; + ((struct list_element *)element)->next = NULL; + return; + } + + while (it->next) { + it = it->next; + } + it->next = (struct list_element *)element; + ((struct list_element *)element)->next = NULL; +} + +/** + * \brief Removes list head + */ +void *list_remove_head(struct list_descriptor *const list) +{ + if (list->head) { + struct list_element *tmp = list->head; + + list->head = list->head->next; + return (void *)tmp; + } + + return NULL; +} + +/** + * \brief Removes list element + */ +bool list_delete_element(struct list_descriptor *const list, const void *const element) +{ + if (!element) { + return false; + } + + if (list->head == element) { + list->head = list->head->next; + return true; + } else { + struct list_element *it = list->head; + + while (it && it->next != element) { + it = it->next; + } + if (it) { + it->next = ((struct list_element *)element)->next; + return true; + } + } + + return false; +} + +//@} diff --git a/software/firmware/oracle_same54n19a/hal/utils/src/utils_ringbuffer.c b/software/firmware/oracle_same54n19a/hal/utils/src/utils_ringbuffer.c new file mode 100644 index 00000000..45cac83f --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/utils/src/utils_ringbuffer.c @@ -0,0 +1,118 @@ +/** + * \file + * + * \brief Ringbuffer functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include "utils_ringbuffer.h" + +/** + * \brief Ringbuffer init + */ +int32_t ringbuffer_init(struct ringbuffer *const rb, void *buf, uint32_t size) +{ + ASSERT(rb && buf && size); + + /* + * buf size must be aligned to power of 2 + */ + if ((size & (size - 1)) != 0) { + return ERR_INVALID_ARG; + } + + /* size - 1 is faster in calculation */ + rb->size = size - 1; + rb->read_index = 0; + rb->write_index = rb->read_index; + rb->buf = (uint8_t *)buf; + + return ERR_NONE; +} + +/** + * \brief Get one byte from ringbuffer + * + */ +int32_t ringbuffer_get(struct ringbuffer *const rb, uint8_t *data) +{ + ASSERT(rb && data); + + if (rb->write_index != rb->read_index) { + *data = rb->buf[rb->read_index & rb->size]; + rb->read_index++; + return ERR_NONE; + } + + return ERR_NOT_FOUND; +} + +/** + * \brief Put one byte to ringbuffer + * + */ +int32_t ringbuffer_put(struct ringbuffer *const rb, uint8_t data) +{ + ASSERT(rb); + + rb->buf[rb->write_index & rb->size] = data; + + /* + * buffer full strategy: new data will overwrite the oldest data in + * the buffer + */ + if ((rb->write_index - rb->read_index) > rb->size) { + rb->read_index = rb->write_index - rb->size; + } + + rb->write_index++; + + return ERR_NONE; +} + +/** + * \brief Return the element number of ringbuffer + */ +uint32_t ringbuffer_num(const struct ringbuffer *const rb) +{ + ASSERT(rb); + + return rb->write_index - rb->read_index; +} + +/** + * \brief Flush ringbuffer + */ +uint32_t ringbuffer_flush(struct ringbuffer *const rb) +{ + ASSERT(rb); + + rb->read_index = rb->write_index; + + return ERR_NONE; +} diff --git a/software/firmware/oracle_same54n19a/hal/utils/src/utils_syscalls.c b/software/firmware/oracle_same54n19a/hal/utils/src/utils_syscalls.c new file mode 100644 index 00000000..79e2f1fe --- /dev/null +++ b/software/firmware/oracle_same54n19a/hal/utils/src/utils_syscalls.c @@ -0,0 +1,152 @@ +/** + * \file + * + * \brief Syscalls for SAM0 (GCC). + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#undef errno +extern int errno; +extern int _end; + +extern caddr_t _sbrk(int incr); +extern int link(char *old, char *_new); +extern int _close(int file); +extern int _fstat(int file, struct stat *st); +extern int _isatty(int file); +extern int _lseek(int file, int ptr, int dir); +extern void _exit(int status); +extern void _kill(int pid, int sig); +extern int _getpid(void); + +/** + * \brief Replacement of C library of _sbrk + */ +extern caddr_t _sbrk(int incr) +{ + static unsigned char *heap = NULL; + unsigned char * prev_heap; + + if (heap == NULL) { + heap = (unsigned char *)&_end; + } + prev_heap = heap; + + heap += incr; + + return (caddr_t)prev_heap; +} + +/** + * \brief Replacement of C library of link + */ +extern int link(char *old, char *_new) +{ + (void)old, (void)_new; + return -1; +} + +/** + * \brief Replacement of C library of _close + */ +extern int _close(int file) +{ + (void)file; + return -1; +} + +/** + * \brief Replacement of C library of _fstat + */ +extern int _fstat(int file, struct stat *st) +{ + (void)file; + st->st_mode = S_IFCHR; + + return 0; +} + +/** + * \brief Replacement of C library of _isatty + */ +extern int _isatty(int file) +{ + (void)file; + return 1; +} + +/** + * \brief Replacement of C library of _lseek + */ +extern int _lseek(int file, int ptr, int dir) +{ + (void)file, (void)ptr, (void)dir; + return 0; +} + +/** + * \brief Replacement of C library of _exit + */ +extern void _exit(int status) +{ + printf("Exiting with status %d.\n", status); + + for (;;) + ; +} + +/** + * \brief Replacement of C library of _kill + */ +extern void _kill(int pid, int sig) +{ + (void)pid, (void)sig; + return; +} + +/** + * \brief Replacement of C library of _getpid + */ +extern int _getpid(void) +{ + return -1; +} + +#ifdef __cplusplus +} +#endif diff --git a/software/firmware/oracle_same54n19a/hpl/cmcc/hpl_cmcc.c b/software/firmware/oracle_same54n19a/hpl/cmcc/hpl_cmcc.c new file mode 100644 index 00000000..bddf0e1f --- /dev/null +++ b/software/firmware/oracle_same54n19a/hpl/cmcc/hpl_cmcc.c @@ -0,0 +1,354 @@ +/** + * \file + * + * \brief Generic CMCC(Cortex M Cache Controller) related functionality. + * + * Copyright (c)2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +/* + * Support and FAQ: visit Microchip Support + */ + +#include +#include +#include + +/** + * \brief Initialize Cache Module + * + * This function does low level cache configuration. + * + * \return initialize status + */ +int32_t _cmcc_init(void) +{ + int32_t return_value; + + _cmcc_disable(CMCC); + + if (_is_cache_disabled(CMCC)) { + hri_cmcc_write_CFG_reg( + CMCC, + (CMCC_CFG_CSIZESW(CONF_CMCC_CACHE_SIZE) | (CONF_CMCC_DATA_CACHE_DISABLE << CMCC_CFG_DCDIS_Pos) + | (CONF_CMCC_INST_CACHE_DISABLE << CMCC_CFG_ICDIS_Pos) | (CONF_CMCC_CLK_GATING_DISABLE))); + + _cmcc_enable(CMCC); + return_value = _is_cache_enabled(CMCC) == true ? ERR_NONE : ERR_FAILURE; + } else { + return_value = ERR_NOT_INITIALIZED; + } + + return return_value; +} + +/** + * \brief Configure CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] cache configuration structure pointer + * + * \return status of operation + */ +int32_t _cmcc_configure(const void *hw, struct _cache_cfg *cache_ctrl) +{ + int32_t return_value; + + _cmcc_disable(hw); + + if (_is_cache_disabled(hw)) { + hri_cmcc_write_CFG_reg( + hw, + (CMCC_CFG_CSIZESW(cache_ctrl->cache_size) | (cache_ctrl->data_cache_disable << CMCC_CFG_DCDIS_Pos) + | (cache_ctrl->inst_cache_disable << CMCC_CFG_ICDIS_Pos) | (cache_ctrl->gclk_gate_disable))); + + return_value = ERR_NONE; + } else { + return_value = ERR_NOT_INITIALIZED; + } + + return return_value; +} + +/** + * \brief Enable data cache in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] boolean 1 -> Enable the data cache, 0 -> disable the data cache + * + * \return status of operation + */ +int32_t _cmcc_enable_data_cache(const void *hw, bool value) +{ + uint32_t tmp; + int32_t ret; + + tmp = hri_cmcc_read_CFG_reg(hw); + tmp &= ~CMCC_CFG_DCDIS; + tmp |= ((!value) << CMCC_CFG_DCDIS_Pos); + + ret = _cmcc_disable(hw); + hri_cmcc_write_CFG_reg(hw, tmp); + ret = _cmcc_enable(hw); + + return ret; +} + +/** + * \brief Enable instruction cache in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] boolean 1 -> Enable the inst cache, 0 -> disable the inst cache + * + * \return status of operation + */ +int32_t _cmcc_enable_inst_cache(const void *hw, bool value) +{ + uint32_t tmp; + int32_t ret; + + tmp = hri_cmcc_read_CFG_reg(hw); + tmp &= ~CMCC_CFG_ICDIS; + tmp |= ((!value) << CMCC_CFG_ICDIS_Pos); + + ret = _cmcc_disable(hw); + hri_cmcc_write_CFG_reg(hw, tmp); + ret = _cmcc_enable(hw); + + return ret; +} + +/** + * \brief Enable clock gating in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] boolean 1 -> Enable the clock gate, 0 -> disable the clock gate + * + * \return status of operation + */ +int32_t _cmcc_enable_clock_gating(const void *hw, bool value) +{ + uint32_t tmp; + int32_t ret; + + tmp = hri_cmcc_read_CFG_reg(hw); + tmp |= value; + + ret = _cmcc_disable(hw); + hri_cmcc_write_CFG_reg(hw, tmp); + ret = _cmcc_enable(hw); + + return ret; +} + +/** + * \brief Configure the cache size in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from cache size configuration enumerator + * 0->1K, 1->2K, 2->4K(default) + * + * \return status of operation + */ +int32_t _cmcc_configure_cache_size(const void *hw, enum conf_cache_size size) +{ + uint32_t tmp; + int32_t ret; + + tmp = hri_cmcc_read_CFG_reg(hw); + tmp &= (~CMCC_CFG_CSIZESW_Msk); + tmp |= (size << CMCC_CFG_CSIZESW_Pos); + + ret = _cmcc_disable(hw); + hri_cmcc_write_CFG_reg(hw, tmp); + ret = _cmcc_enable(hw); + + return ret; +} + +/** + * \brief Lock the mentioned WAY in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from "way_num_index" enumerator + * + * \return status of operation + */ +int32_t _cmcc_lock_way(const void *hw, enum way_num_index num) +{ + uint32_t tmp; + int32_t ret; + + tmp = hri_cmcc_read_LCKWAY_reg(hw); + tmp |= CMCC_LCKWAY_LCKWAY(num); + + ret = _cmcc_disable(hw); + hri_cmcc_write_LCKWAY_reg(hw, tmp); + ret = _cmcc_enable(hw); + + return ret; +} + +/** + * \brief Unlock the mentioned WAY in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from "way_num_index" enumerator + * + * \return status of operation + */ +int32_t _cmcc_unlock_way(const void *hw, enum way_num_index num) +{ + uint32_t tmp; + int32_t ret; + + tmp = hri_cmcc_read_LCKWAY_reg(hw); + tmp &= (~CMCC_LCKWAY_LCKWAY(num)); + + ret = _cmcc_disable(hw); + hri_cmcc_write_LCKWAY_reg(hw, tmp); + ret = _cmcc_enable(hw); + + return ret; +} + +/** + * \brief Invalidate the mentioned cache line in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from "way_num" enumerator (valid arg is 0-3) + * \param[in] line number (valid arg is 0-63 as each way will have 64 lines) + * + * \return status of operation + */ +int32_t _cmcc_invalidate_by_line(const void *hw, uint8_t way_num, uint8_t line_num) +{ + int32_t return_value; + + if ((way_num < CMCC_WAY_NOS) && (line_num < CMCC_LINE_NOS)) { + _cmcc_disable(hw); + while (!(_is_cache_disabled(hw))) + ; + hri_cmcc_write_MAINT1_reg(hw, (CMCC_MAINT1_INDEX(line_num) | CMCC_MAINT1_WAY(way_num))); + return_value = ERR_NONE; + } else { + return_value = ERR_INVALID_ARG; + } + + return return_value; +} + +/** + * \brief Invalidate entire cache entries in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return status of operation + */ +int32_t _cmcc_invalidate_all(const void *hw) +{ + int32_t return_value; + + _cmcc_disable(hw); + if (_is_cache_disabled(hw)) { + hri_cmcc_write_MAINT0_reg(hw, CMCC_MAINT0_INVALL); + return_value = ERR_NONE; + } else { + return_value = ERR_FAILURE; + } + + return return_value; +} + +/** + * \brief Configure cache monitor in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * \param[in] element from cache monitor configurations enumerator + * + * \return status of operation + */ +int32_t _cmcc_configure_monitor(const void *hw, enum conf_cache_monitor monitor_cfg) +{ + hri_cmcc_write_MCFG_reg(hw, CMCC_MCFG_MODE(monitor_cfg)); + + return ERR_NONE; +} + +/** + * \brief Enable cache monitor in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return status of operation + */ +int32_t _cmcc_enable_monitor(const void *hw) +{ + hri_cmcc_write_MEN_reg(hw, CMCC_MEN_MENABLE); + + return ERR_NONE; +} + +/** + * \brief Disable cache monitor in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return status of operation + */ +int32_t _cmcc_disable_monitor(const void *hw) +{ + hri_cmcc_write_MEN_reg(hw, (CMCC_MONITOR_DISABLE << CMCC_MEN_MENABLE_Pos)); + + return ERR_NONE; +} + +/** + * \brief Reset cache monitor in CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return status of operation + */ +int32_t _cmcc_reset_monitor(const void *hw) +{ + hri_cmcc_write_MCTRL_reg(hw, CMCC_MCTRL_SWRST); + + return ERR_NONE; +} + +/** + * \brief Get cache monitor event counter value from CMCC module + * + * \param[in] pointer pointing to the starting address of CMCC module + * + * \return event counter value + */ +uint32_t _cmcc_get_monitor_event_count(const void *hw) +{ + return hri_cmcc_read_MSR_reg(hw); +} diff --git a/software/firmware/oracle_same54n19a/hpl/core/hpl_core_m4.c b/software/firmware/oracle_same54n19a/hpl/core/hpl_core_m4.c new file mode 100644 index 00000000..4680ec31 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hpl/core/hpl_core_m4.c @@ -0,0 +1,241 @@ +/** + * \file + * + * \brief Core related functionality implementation. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#ifndef _UNIT_TEST_ +#include +#endif +#include +#include + +#ifndef CONF_CPU_FREQUENCY +#define CONF_CPU_FREQUENCY 1000000 +#endif + +#if CONF_CPU_FREQUENCY < 1000 +#define CPU_FREQ_POWER 3 +#elif CONF_CPU_FREQUENCY < 10000 +#define CPU_FREQ_POWER 4 +#elif CONF_CPU_FREQUENCY < 100000 +#define CPU_FREQ_POWER 5 +#elif CONF_CPU_FREQUENCY < 1000000 +#define CPU_FREQ_POWER 6 +#elif CONF_CPU_FREQUENCY < 10000000 +#define CPU_FREQ_POWER 7 +#elif CONF_CPU_FREQUENCY < 100000000 +#define CPU_FREQ_POWER 8 +#elif CONF_CPU_FREQUENCY < 1000000000 +#define CPU_FREQ_POWER 9 +#endif + +/** + * \brief The array of interrupt handlers + */ +struct _irq_descriptor *_irq_table[PERIPH_COUNT_IRQn]; + +/** + * \brief Reset MCU + */ +void _reset_mcu(void) +{ + NVIC_SystemReset(); +} + +/** + * \brief Put MCU to sleep + */ +void _go_to_sleep(void) +{ + __DSB(); + __WFI(); +} + +/** + * \brief Retrieve current IRQ number + */ +uint8_t _irq_get_current(void) +{ + return (uint8_t)__get_IPSR() - 16; +} + +/** + * \brief Disable the given IRQ + */ +void _irq_disable(uint8_t n) +{ + NVIC_DisableIRQ((IRQn_Type)n); +} + +/** + * \brief Set the given IRQ + */ +void _irq_set(uint8_t n) +{ + NVIC_SetPendingIRQ((IRQn_Type)n); +} + +/** + * \brief Clear the given IRQ + */ +void _irq_clear(uint8_t n) +{ + NVIC_ClearPendingIRQ((IRQn_Type)n); +} + +/** + * \brief Enable the given IRQ + */ +void _irq_enable(uint8_t n) +{ + NVIC_EnableIRQ((IRQn_Type)n); +} + +/** + * \brief Register IRQ handler + */ +void _irq_register(const uint8_t n, struct _irq_descriptor *const irq) +{ + ASSERT(n < PERIPH_COUNT_IRQn); + + _irq_table[n] = irq; +} + +/** + * \brief Default interrupt handler for unused IRQs. + */ +void Default_Handler(void) +{ + while (1) { + } +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of us + */ +static inline uint32_t _get_cycles_for_us_internal(const uint16_t us, const uint32_t freq, const uint8_t power) +{ + switch (power) { + case 9: + return (us * (freq / 1000000) + 2) / 3; + case 8: + return (us * (freq / 100000) + 29) / 30; + case 7: + return (us * (freq / 10000) + 299) / 300; + case 6: + return (us * (freq / 1000) + 2999) / 3000; + case 5: + return (us * (freq / 100) + 29999) / 30000; + case 4: + return (us * (freq / 10) + 299999) / 300000; + default: + return (us * freq + 2999999) / 3000000; + } +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of us + */ +uint32_t _get_cycles_for_us(const uint16_t us) +{ + return _get_cycles_for_us_internal(us, CONF_CPU_FREQUENCY, CPU_FREQ_POWER); +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of ms + */ +static inline uint32_t _get_cycles_for_ms_internal(const uint16_t ms, const uint32_t freq, const uint8_t power) +{ + switch (power) { + case 9: + return (ms * (freq / 1000000) + 2) / 3 * 1000; + case 8: + return (ms * (freq / 100000) + 2) / 3 * 100; + case 7: + return (ms * (freq / 10000) + 2) / 3 * 10; + case 6: + return (ms * (freq / 1000) + 2) / 3; + case 5: + return (ms * (freq / 100) + 29) / 30; + case 4: + return (ms * (freq / 10) + 299) / 300; + default: + return (ms * (freq / 1) + 2999) / 3000; + } +} + +/** + * \brief Retrieve the amount of cycles to delay for the given amount of ms + */ +uint32_t _get_cycles_for_ms(const uint16_t ms) +{ + return _get_cycles_for_ms_internal(ms, CONF_CPU_FREQUENCY, CPU_FREQ_POWER); +} +/** + * \brief Initialize delay functionality + */ +void _delay_init(void *const hw) +{ + (void)hw; +} +/** + * \brief Delay loop to delay n number of cycles + */ +void _delay_cycles(void *const hw, uint32_t cycles) +{ +#ifndef _UNIT_TEST_ + (void)hw; + (void)cycles; +#if defined(__GNUC__) && (__ARMCOMPILER_VERSION > 6000000) /* Keil MDK with ARM Compiler 6 */ + __asm(".align 3 \n" + "__delay:\n" + "subs r1, r1, #1\n" + "bhi __delay\n"); +#elif defined __GNUC__ + __asm(".syntax unified\n" + ".align 3 \n" + "__delay:\n" + "subs r1, r1, #1\n" + "bhi __delay\n" + ".syntax divided"); +#elif defined __CC_ARM + __asm("__delay:\n" + "subs cycles, cycles, #1\n" + "bhi __delay\n"); +#elif defined __ICCARM__ + __asm("__delay:\n" + "subs r1, r1, #1\n" + "bhi.n __delay\n"); +#endif +#endif +} diff --git a/software/firmware/oracle_same54n19a/hpl/core/hpl_core_port.h b/software/firmware/oracle_same54n19a/hpl/core/hpl_core_port.h new file mode 100644 index 00000000..3f3e8f28 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hpl/core/hpl_core_port.h @@ -0,0 +1,61 @@ +/** + * \file + * + * \brief Core related functionality implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_CORE_PORT_H_INCLUDED +#define _HPL_CORE_PORT_H_INCLUDED + +#include + +/* It's possible to include this file in ARM ASM files (e.g., in FreeRTOS IAR + * portable implement, portasm.s -> FreeRTOSConfig.h -> hpl_core_port.h), + * there will be assembling errors. + * So the following things are not included for assembling. + */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) + +#ifndef _UNIT_TEST_ +#include +#endif + +/** + * \brief Check if it's in ISR handling + * \return \c true if it's in ISR + */ +static inline bool _is_in_isr(void) +{ + return (SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk); +} + +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#endif /* _HPL_CORE_PORT_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hpl/core/hpl_init.c b/software/firmware/oracle_same54n19a/hpl/core/hpl_init.c new file mode 100644 index 00000000..be0db930 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hpl/core/hpl_init.c @@ -0,0 +1,78 @@ +/** + * \file + * + * \brief HPL initialization related functionality implementation. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include + +#include +#include +#include +#include + +/* Referenced GCLKs (out of 0~11), should be initialized firstly + */ +#define _GCLK_INIT_1ST 0x00000000 +/* Not referenced GCLKs, initialized last */ +#define _GCLK_INIT_LAST 0x00000FFF + +/** + * \brief Initialize the hardware abstraction layer + */ +void _init_chip(void) +{ + hri_nvmctrl_set_CTRLA_RWS_bf(NVMCTRL, CONF_NVM_WAIT_STATE); + + _osc32kctrl_init_sources(); + _oscctrl_init_sources(); + _mclk_init(); +#if _GCLK_INIT_1ST + _gclk_init_generators_by_fref(_GCLK_INIT_1ST); +#endif + _oscctrl_init_referenced_generators(); + _gclk_init_generators_by_fref(_GCLK_INIT_LAST); + +#if CONF_DMAC_ENABLE + hri_mclk_set_AHBMASK_DMAC_bit(MCLK); + _dma_init(); +#endif + +#if (CONF_PORT_EVCTRL_PORT_0 | CONF_PORT_EVCTRL_PORT_1 | CONF_PORT_EVCTRL_PORT_2 | CONF_PORT_EVCTRL_PORT_3) + _port_event_init(); +#endif + +#if CONF_CMCC_ENABLE + cache_init(); +#endif +} diff --git a/software/firmware/oracle_same54n19a/hpl/dmac/hpl_dmac.c b/software/firmware/oracle_same54n19a/hpl/dmac/hpl_dmac.c new file mode 100644 index 00000000..c7b03b00 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hpl/dmac/hpl_dmac.c @@ -0,0 +1,263 @@ + +/** + * \file + * + * \brief Generic DMAC related functionality. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include +#include + +#if CONF_DMAC_ENABLE +/* Section containing first descriptors for all DMAC channels */ +COMPILER_ALIGNED(16) +DmacDescriptor _descriptor_section[DMAC_CH_NUM]; + +/* Section containing current descriptors for all DMAC channels */ +COMPILER_ALIGNED(16) +DmacDescriptor _write_back_section[DMAC_CH_NUM]; + +/* Array containing callbacks for DMAC channels */ +static struct _dma_resource _resources[DMAC_CH_NUM]; + +/* DMAC interrupt handler */ +static void _dmac_handler(void); + +/* This macro DMAC configuration */ +#define DMAC_CHANNEL_CFG(i, n) \ + {(CONF_DMAC_RUNSTDBY_##n << DMAC_CHCTRLA_RUNSTDBY_Pos) | DMAC_CHCTRLA_TRIGACT(CONF_DMAC_TRIGACT_##n) \ + | DMAC_CHCTRLA_TRIGSRC(CONF_DMAC_TRIGSRC_##n), \ + DMAC_CHPRILVL_PRILVL(CONF_DMAC_LVL_##n), \ + (CONF_DMAC_EVIE_##n << DMAC_CHEVCTRL_EVIE_Pos) | (CONF_DMAC_EVOE_##n << DMAC_CHEVCTRL_EVOE_Pos) \ + | (CONF_DMAC_EVACT_##n << DMAC_CHEVCTRL_EVACT_Pos), \ + DMAC_BTCTRL_STEPSIZE(CONF_DMAC_STEPSIZE_##n) | (CONF_DMAC_STEPSEL_##n << DMAC_BTCTRL_STEPSEL_Pos) \ + | (CONF_DMAC_DSTINC_##n << DMAC_BTCTRL_DSTINC_Pos) | (CONF_DMAC_SRCINC_##n << DMAC_BTCTRL_SRCINC_Pos) \ + | DMAC_BTCTRL_BEATSIZE(CONF_DMAC_BEATSIZE_##n) | DMAC_BTCTRL_BLOCKACT(CONF_DMAC_BLOCKACT_##n) \ + | DMAC_BTCTRL_EVOSEL(CONF_DMAC_EVOSEL_##n)}, + +/* DMAC channel configuration */ +struct dmac_channel_cfg { + uint32_t ctrla; + uint8_t prilvl; + uint8_t evctrl; + uint16_t btctrl; +}; + +/* DMAC channel configurations */ +const static struct dmac_channel_cfg _cfgs[] = {REPEAT_MACRO(DMAC_CHANNEL_CFG, i, DMAC_CH_NUM)}; + +/** + * \brief Initialize DMAC + */ +int32_t _dma_init(void) +{ + uint8_t i; + + hri_dmac_clear_CTRL_DMAENABLE_bit(DMAC); + hri_dmac_clear_CRCCTRL_reg(DMAC, DMAC_CRCCTRL_CRCSRC_Msk); + hri_dmac_set_CTRL_SWRST_bit(DMAC); + while (hri_dmac_get_CTRL_SWRST_bit(DMAC)) + ; + + hri_dmac_write_CTRL_reg(DMAC, + (CONF_DMAC_LVLEN0 << DMAC_CTRL_LVLEN0_Pos) | (CONF_DMAC_LVLEN1 << DMAC_CTRL_LVLEN1_Pos) + | (CONF_DMAC_LVLEN2 << DMAC_CTRL_LVLEN2_Pos) + | (CONF_DMAC_LVLEN3 << DMAC_CTRL_LVLEN3_Pos)); + hri_dmac_write_DBGCTRL_DBGRUN_bit(DMAC, CONF_DMAC_DBGRUN); + + hri_dmac_write_PRICTRL0_reg( + DMAC, + DMAC_PRICTRL0_LVLPRI0(CONF_DMAC_LVLPRI0) | DMAC_PRICTRL0_LVLPRI1(CONF_DMAC_LVLPRI1) + | DMAC_PRICTRL0_LVLPRI2(CONF_DMAC_LVLPRI2) | DMAC_PRICTRL0_LVLPRI3(CONF_DMAC_LVLPRI3) + | (CONF_DMAC_RRLVLEN0 << DMAC_PRICTRL0_RRLVLEN0_Pos) | (CONF_DMAC_RRLVLEN1 << DMAC_PRICTRL0_RRLVLEN1_Pos) + | (CONF_DMAC_RRLVLEN2 << DMAC_PRICTRL0_RRLVLEN2_Pos) | (CONF_DMAC_RRLVLEN3 << DMAC_PRICTRL0_RRLVLEN3_Pos)); + hri_dmac_write_BASEADDR_reg(DMAC, (uint32_t)_descriptor_section); + hri_dmac_write_WRBADDR_reg(DMAC, (uint32_t)_write_back_section); + + for (i = 0; i < DMAC_CH_NUM; i++) { + hri_dmac_write_CHCTRLA_reg(DMAC, i, _cfgs[i].ctrla); + hri_dmac_write_CHPRILVL_reg(DMAC, i, _cfgs[i].prilvl); + hri_dmac_write_CHEVCTRL_reg(DMAC, i, _cfgs[i].evctrl); + hri_dmacdescriptor_write_BTCTRL_reg(&_descriptor_section[i], _cfgs[i].btctrl); + hri_dmacdescriptor_write_DESCADDR_reg(&_descriptor_section[i], 0x0); + } + + for (i = 0; i < 5; i++) { + NVIC_DisableIRQ(DMAC_0_IRQn + i); + NVIC_ClearPendingIRQ(DMAC_0_IRQn + i); + NVIC_EnableIRQ(DMAC_0_IRQn + i); + } + + hri_dmac_set_CTRL_DMAENABLE_bit(DMAC); + + return ERR_NONE; +} + +/** + * \brief Enable/disable DMA interrupt + */ +void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state) +{ + if (DMA_TRANSFER_COMPLETE_CB == type) { + hri_dmac_write_CHINTEN_TCMPL_bit(DMAC, channel, state); + } else if (DMA_TRANSFER_ERROR_CB == type) { + hri_dmac_write_CHINTEN_TERR_bit(DMAC, channel, state); + } +} + +int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst) +{ + hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], (uint32_t)dst); + + return ERR_NONE; +} + +int32_t _dma_set_source_address(const uint8_t channel, const void *const src) +{ + hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], (uint32_t)src); + + return ERR_NONE; +} + +int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel) +{ + hri_dmacdescriptor_write_DESCADDR_reg(&_descriptor_section[current_channel], + (uint32_t)&_descriptor_section[next_channel]); + + return ERR_NONE; +} + +int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable) +{ + hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(&_descriptor_section[channel], enable); + + return ERR_NONE; +} + +int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount) +{ + uint32_t address = hri_dmacdescriptor_read_DSTADDR_reg(&_descriptor_section[channel]); + uint8_t beat_size = hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(&_descriptor_section[channel]); + + if (hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(&_descriptor_section[channel])) { + hri_dmacdescriptor_write_DSTADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size)); + } + + address = hri_dmacdescriptor_read_SRCADDR_reg(&_descriptor_section[channel]); + + if (hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(&_descriptor_section[channel])) { + hri_dmacdescriptor_write_SRCADDR_reg(&_descriptor_section[channel], address + amount * (1 << beat_size)); + } + + hri_dmacdescriptor_write_BTCNT_reg(&_descriptor_section[channel], amount); + + return ERR_NONE; +} + +int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger) +{ + hri_dmacdescriptor_set_BTCTRL_VALID_bit(&_descriptor_section[channel]); + hri_dmac_set_CHCTRLA_ENABLE_bit(DMAC, channel); + + if (software_trigger) { + hri_dmac_set_SWTRIGCTRL_reg(DMAC, 1 << channel); + } + + return ERR_NONE; +} + +int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel) +{ + *resource = &_resources[channel]; + + return ERR_NONE; +} + +int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable) +{ + hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(&_descriptor_section[channel], enable); + + return ERR_NONE; +} +/** + * \internal DMAC interrupt handler + */ +static void _dmac_handler(void) +{ + uint8_t channel = hri_dmac_get_INTPEND_reg(DMAC, DMAC_INTPEND_ID_Msk); + struct _dma_resource *tmp_resource = &_resources[channel]; + + if (hri_dmac_get_INTPEND_TERR_bit(DMAC)) { + hri_dmac_clear_CHINTFLAG_TERR_bit(DMAC, channel); + tmp_resource->dma_cb.error(tmp_resource); + } else if (hri_dmac_get_INTPEND_TCMPL_bit(DMAC)) { + hri_dmac_clear_CHINTFLAG_TCMPL_bit(DMAC, channel); + tmp_resource->dma_cb.transfer_done(tmp_resource); + } +} +/** + * \brief DMAC interrupt handler + */ +void DMAC_0_Handler(void) +{ + _dmac_handler(); +} +/** + * \brief DMAC interrupt handler + */ +void DMAC_1_Handler(void) +{ + _dmac_handler(); +} +/** + * \brief DMAC interrupt handler + */ +void DMAC_2_Handler(void) +{ + _dmac_handler(); +} +/** + * \brief DMAC interrupt handler + */ +void DMAC_3_Handler(void) +{ + _dmac_handler(); +} +/** + * \brief DMAC interrupt handler + */ +void DMAC_4_Handler(void) +{ + _dmac_handler(); +} + +#endif /* CONF_DMAC_ENABLE */ diff --git a/software/firmware/oracle_same54n19a/hpl/eic/hpl_eic.c b/software/firmware/oracle_same54n19a/hpl/eic/hpl_eic.c new file mode 100644 index 00000000..b6914095 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hpl/eic/hpl_eic.c @@ -0,0 +1,258 @@ + +/** + * \file + * + * \brief EIC related functionality implementation. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include +#include +#include + +#ifdef __MINGW32__ +#define ffs __builtin_ffs +#endif +#if defined(__CC_ARM) || defined(__ICCARM__) +/* Find the first bit set */ +static int ffs(int v) +{ + int i, bit = 1; + for (i = 0; i < sizeof(int) * 8; i++) { + if (v & bit) { + return i + 1; + } + bit <<= 1; + } + return 0; +} +#endif + +/** + * \brief Invalid external interrupt and pin numbers + */ +#define INVALID_EXTINT_NUMBER 0xFF +#define INVALID_PIN_NUMBER 0xFFFFFFFF + +#ifndef CONFIG_EIC_EXTINT_MAP +/** Dummy mapping to pass compiling. */ +#define CONFIG_EIC_EXTINT_MAP \ + { \ + INVALID_EXTINT_NUMBER, INVALID_PIN_NUMBER \ + } +#endif + +#define EXT_IRQ_AMOUNT 0 + +/** + * \brief EXTINTx and pin number map + */ +struct _eic_map { + uint8_t extint; + uint32_t pin; +}; + +/** + * \brief PIN and EXTINT map for enabled external interrupts + */ +static const struct _eic_map _map[] = {CONFIG_EIC_EXTINT_MAP}; + +/** + * \brief The callback to upper layer's interrupt processing routine + */ +static void (*callback)(const uint32_t pin); + +static void _ext_irq_handler(void); + +/** + * \brief Initialize external interrupt module + */ +int32_t _ext_irq_init(void (*cb)(const uint32_t pin)) +{ + if (!hri_eic_is_syncing(EIC, EIC_SYNCBUSY_SWRST)) { + if (hri_eic_get_CTRLA_reg(EIC, EIC_CTRLA_ENABLE)) { + hri_eic_clear_CTRLA_ENABLE_bit(EIC); + hri_eic_wait_for_sync(EIC, EIC_SYNCBUSY_ENABLE); + } + hri_eic_write_CTRLA_reg(EIC, EIC_CTRLA_SWRST); + } + hri_eic_wait_for_sync(EIC, EIC_SYNCBUSY_SWRST); + + hri_eic_write_CTRLA_CKSEL_bit(EIC, CONF_EIC_CKSEL); + + hri_eic_write_NMICTRL_reg(EIC, + (CONF_EIC_NMIFILTEN << EIC_NMICTRL_NMIFILTEN_Pos) + | EIC_NMICTRL_NMISENSE(CONF_EIC_NMISENSE) | EIC_ASYNCH_ASYNCH(CONF_EIC_NMIASYNCH) + | 0); + + hri_eic_write_EVCTRL_reg(EIC, + (CONF_EIC_EXTINTEO0 << 0) | (CONF_EIC_EXTINTEO1 << 1) | (CONF_EIC_EXTINTEO2 << 2) + | (CONF_EIC_EXTINTEO3 << 3) | (CONF_EIC_EXTINTEO4 << 4) | (CONF_EIC_EXTINTEO5 << 5) + | (CONF_EIC_EXTINTEO6 << 6) | (CONF_EIC_EXTINTEO7 << 7) | (CONF_EIC_EXTINTEO8 << 8) + | (CONF_EIC_EXTINTEO9 << 9) | (CONF_EIC_EXTINTEO10 << 10) | (CONF_EIC_EXTINTEO11 << 11) + | (CONF_EIC_EXTINTEO12 << 12) | (CONF_EIC_EXTINTEO13 << 13) + | (CONF_EIC_EXTINTEO14 << 14) | (CONF_EIC_EXTINTEO15 << 15) | 0); + hri_eic_write_ASYNCH_reg(EIC, + (CONF_EIC_ASYNCH0 << 0) | (CONF_EIC_ASYNCH1 << 1) | (CONF_EIC_ASYNCH2 << 2) + | (CONF_EIC_ASYNCH3 << 3) | (CONF_EIC_ASYNCH4 << 4) | (CONF_EIC_ASYNCH5 << 5) + | (CONF_EIC_ASYNCH6 << 6) | (CONF_EIC_ASYNCH7 << 7) | (CONF_EIC_ASYNCH8 << 8) + | (CONF_EIC_ASYNCH9 << 9) | (CONF_EIC_ASYNCH10 << 10) | (CONF_EIC_ASYNCH11 << 11) + | (CONF_EIC_ASYNCH12 << 12) | (CONF_EIC_ASYNCH13 << 13) | (CONF_EIC_ASYNCH14 << 14) + | (CONF_EIC_ASYNCH15 << 15) | 0); + hri_eic_write_DEBOUNCEN_reg( + EIC, + (CONF_EIC_DEBOUNCE_ENABLE0 << 0) | (CONF_EIC_DEBOUNCE_ENABLE1 << 1) | (CONF_EIC_DEBOUNCE_ENABLE2 << 2) + | (CONF_EIC_DEBOUNCE_ENABLE3 << 3) | (CONF_EIC_DEBOUNCE_ENABLE4 << 4) | (CONF_EIC_DEBOUNCE_ENABLE5 << 5) + | (CONF_EIC_DEBOUNCE_ENABLE6 << 6) | (CONF_EIC_DEBOUNCE_ENABLE7 << 7) | (CONF_EIC_DEBOUNCE_ENABLE8 << 8) + | (CONF_EIC_DEBOUNCE_ENABLE9 << 9) | (CONF_EIC_DEBOUNCE_ENABLE10 << 10) | (CONF_EIC_DEBOUNCE_ENABLE11 << 11) + | (CONF_EIC_DEBOUNCE_ENABLE12 << 12) | (CONF_EIC_DEBOUNCE_ENABLE13 << 13) + | (CONF_EIC_DEBOUNCE_ENABLE14 << 14) | (CONF_EIC_DEBOUNCE_ENABLE15 << 15) | 0); + + hri_eic_write_DPRESCALER_reg( + EIC, + (EIC_DPRESCALER_PRESCALER0(CONF_EIC_DPRESCALER0)) | (CONF_EIC_STATES0 << EIC_DPRESCALER_STATES0_Pos) + | (EIC_DPRESCALER_PRESCALER1(CONF_EIC_DPRESCALER1)) | (CONF_EIC_STATES1 << EIC_DPRESCALER_STATES1_Pos) + | CONF_EIC_TICKON << EIC_DPRESCALER_TICKON_Pos | 0); + + hri_eic_write_CONFIG_reg(EIC, + 0, + (CONF_EIC_FILTEN0 << EIC_CONFIG_FILTEN0_Pos) | EIC_CONFIG_SENSE0(CONF_EIC_SENSE0) + | (CONF_EIC_FILTEN1 << EIC_CONFIG_FILTEN1_Pos) | EIC_CONFIG_SENSE1(CONF_EIC_SENSE1) + | (CONF_EIC_FILTEN2 << EIC_CONFIG_FILTEN2_Pos) | EIC_CONFIG_SENSE2(CONF_EIC_SENSE2) + | (CONF_EIC_FILTEN3 << EIC_CONFIG_FILTEN3_Pos) | EIC_CONFIG_SENSE3(CONF_EIC_SENSE3) + | (CONF_EIC_FILTEN4 << EIC_CONFIG_FILTEN4_Pos) | EIC_CONFIG_SENSE4(CONF_EIC_SENSE4) + | (CONF_EIC_FILTEN5 << EIC_CONFIG_FILTEN5_Pos) | EIC_CONFIG_SENSE5(CONF_EIC_SENSE5) + | (CONF_EIC_FILTEN6 << EIC_CONFIG_FILTEN6_Pos) | EIC_CONFIG_SENSE6(CONF_EIC_SENSE6) + | (CONF_EIC_FILTEN7 << EIC_CONFIG_FILTEN7_Pos) | EIC_CONFIG_SENSE7(CONF_EIC_SENSE7) + | 0); + + hri_eic_write_CONFIG_reg(EIC, + 1, + (CONF_EIC_FILTEN8 << EIC_CONFIG_FILTEN0_Pos) | EIC_CONFIG_SENSE0(CONF_EIC_SENSE8) + | (CONF_EIC_FILTEN9 << EIC_CONFIG_FILTEN1_Pos) | EIC_CONFIG_SENSE1(CONF_EIC_SENSE9) + | (CONF_EIC_FILTEN10 << EIC_CONFIG_FILTEN2_Pos) | EIC_CONFIG_SENSE2(CONF_EIC_SENSE10) + | (CONF_EIC_FILTEN11 << EIC_CONFIG_FILTEN3_Pos) | EIC_CONFIG_SENSE3(CONF_EIC_SENSE11) + | (CONF_EIC_FILTEN12 << EIC_CONFIG_FILTEN4_Pos) | EIC_CONFIG_SENSE4(CONF_EIC_SENSE12) + | (CONF_EIC_FILTEN13 << EIC_CONFIG_FILTEN5_Pos) | EIC_CONFIG_SENSE5(CONF_EIC_SENSE13) + | (CONF_EIC_FILTEN14 << EIC_CONFIG_FILTEN6_Pos) | EIC_CONFIG_SENSE6(CONF_EIC_SENSE14) + | (CONF_EIC_FILTEN15 << EIC_CONFIG_FILTEN7_Pos) | EIC_CONFIG_SENSE7(CONF_EIC_SENSE15) + | 0); + + hri_eic_set_CTRLA_ENABLE_bit(EIC); + + callback = cb; + + return ERR_NONE; +} + +/** + * \brief De-initialize external interrupt module + */ +int32_t _ext_irq_deinit(void) +{ + + callback = NULL; + + hri_eic_clear_CTRLA_ENABLE_bit(EIC); + hri_eic_set_CTRLA_SWRST_bit(EIC); + + return ERR_NONE; +} + +/** + * \brief Enable / disable external irq + */ +int32_t _ext_irq_enable(const uint32_t pin, const bool enable) +{ + uint8_t extint = INVALID_EXTINT_NUMBER; + uint8_t i = 0; + + for (; i < ARRAY_SIZE(_map); i++) { + if (_map[i].pin == pin) { + extint = _map[i].extint; + break; + } + } + if (INVALID_EXTINT_NUMBER == extint) { + return -1; + } + + if (enable) { + hri_eic_set_INTEN_reg(EIC, 1ul << extint); + } else { + hri_eic_clear_INTEN_reg(EIC, 1ul << extint); + hri_eic_clear_INTFLAG_reg(EIC, 1ul << extint); + } + + return ERR_NONE; +} + +/** + * \brief Inter EIC interrupt handler + */ +static void _ext_irq_handler(void) +{ + volatile uint32_t flags = hri_eic_read_INTFLAG_reg(EIC); + int8_t pos; + uint32_t pin = INVALID_PIN_NUMBER; + + hri_eic_clear_INTFLAG_reg(EIC, flags); + + ASSERT(callback); + + while (flags) { + pos = ffs(flags) - 1; + while (-1 != pos) { + uint8_t lower = 0, middle, upper = EXT_IRQ_AMOUNT; + + while (upper >= lower) { + middle = (upper + lower) >> 1; + if (_map[middle].extint == pos) { + pin = _map[middle].pin; + break; + } + if (_map[middle].extint < pos) { + lower = middle + 1; + } else { + upper = middle - 1; + } + } + + if (INVALID_PIN_NUMBER != pin) { + callback(pin); + } + flags &= ~(1ul << pos); + pos = ffs(flags) - 1; + } + flags = hri_eic_read_INTFLAG_reg(EIC); + hri_eic_clear_INTFLAG_reg(EIC, flags); + } +} diff --git a/software/firmware/oracle_same54n19a/hpl/gclk/hpl_gclk.c b/software/firmware/oracle_same54n19a/hpl/gclk/hpl_gclk.c new file mode 100644 index 00000000..211ccc3f --- /dev/null +++ b/software/firmware/oracle_same54n19a/hpl/gclk/hpl_gclk.c @@ -0,0 +1,312 @@ + +/** + * \file + * + * \brief Generic Clock Controller related functionality. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +/** + * \brief Initializes generators + */ +void _gclk_init_generators(void) +{ + +#if CONF_GCLK_GENERATOR_0_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 0, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV) | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_0_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_1_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 1, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV) | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_1_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_2_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 2, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV) | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_3_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 3, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV) | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_3_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_3_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_4_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 4, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV) | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_5_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 5, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_5_DIV) | (CONF_GCLK_GEN_5_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_5_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_5_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_5_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_5_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_5_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_6_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 6, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_6_DIV) | (CONF_GCLK_GEN_6_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_6_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_6_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_6_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_6_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_6_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_6_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_7_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 7, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_7_DIV) | (CONF_GCLK_GEN_7_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_7_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_7_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_7_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_7_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_7_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_7_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_8_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 8, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_8_DIV) | (CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_8_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_8_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_9_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 9, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_9_DIV) | (CONF_GCLK_GEN_9_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_9_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_9_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_9_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_9_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_9_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_9_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_10_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 10, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_10_DIV) | (CONF_GCLK_GEN_10_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_10_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_10_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_10_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_10_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_10_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_10_SOURCE); +#endif + +#if CONF_GCLK_GENERATOR_11_CONFIG == 1 + hri_gclk_write_GENCTRL_reg( + GCLK, + 11, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_11_DIV) | (CONF_GCLK_GEN_11_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_11_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_11_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_11_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_11_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_11_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_11_SOURCE); +#endif +} + +void _gclk_init_generators_by_fref(uint32_t bm) +{ + +#if CONF_GCLK_GENERATOR_0_CONFIG == 1 + if (bm & (1ul << 0)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 0, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_0_DIV) | (CONF_GCLK_GEN_0_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_0_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_0_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_0_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_0_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_0_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_0_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_1_CONFIG == 1 + if (bm & (1ul << 1)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 1, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_1_DIV) | (CONF_GCLK_GEN_1_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_1_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_1_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_1_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_1_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_1_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_1_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_2_CONFIG == 1 + if (bm & (1ul << 2)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 2, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_2_DIV) | (CONF_GCLK_GEN_2_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_2_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_2_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_2_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_2_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_2_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_2_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_3_CONFIG == 1 + if (bm & (1ul << 3)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 3, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_3_DIV) | (CONF_GCLK_GEN_3_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_3_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_3_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_3_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_3_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_3_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_3_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_4_CONFIG == 1 + if (bm & (1ul << 4)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 4, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_4_DIV) | (CONF_GCLK_GEN_4_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_4_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_4_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_4_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_4_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_4_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_4_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_5_CONFIG == 1 + if (bm & (1ul << 5)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 5, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_5_DIV) | (CONF_GCLK_GEN_5_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_5_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_5_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_5_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_5_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_5_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_5_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_6_CONFIG == 1 + if (bm & (1ul << 6)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 6, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_6_DIV) | (CONF_GCLK_GEN_6_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_6_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_6_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_6_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_6_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_6_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_6_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_7_CONFIG == 1 + if (bm & (1ul << 7)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 7, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_7_DIV) | (CONF_GCLK_GEN_7_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_7_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_7_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_7_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_7_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_7_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_7_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_8_CONFIG == 1 + if (bm & (1ul << 8)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 8, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_8_DIV) | (CONF_GCLK_GEN_8_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_8_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_8_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_8_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_8_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_8_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_8_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_9_CONFIG == 1 + if (bm & (1ul << 9)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 9, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_9_DIV) | (CONF_GCLK_GEN_9_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_9_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_9_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_9_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_9_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_9_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_9_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_10_CONFIG == 1 + if (bm & (1ul << 10)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 10, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_10_DIV) | (CONF_GCLK_GEN_10_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_10_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_10_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_10_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_10_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_10_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_10_SOURCE); + } +#endif + +#if CONF_GCLK_GENERATOR_11_CONFIG == 1 + if (bm & (1ul << 11)) { + hri_gclk_write_GENCTRL_reg( + GCLK, + 11, + GCLK_GENCTRL_DIV(CONF_GCLK_GEN_11_DIV) | (CONF_GCLK_GEN_11_RUNSTDBY << GCLK_GENCTRL_RUNSTDBY_Pos) + | (CONF_GCLK_GEN_11_DIVSEL << GCLK_GENCTRL_DIVSEL_Pos) | (CONF_GCLK_GEN_11_OE << GCLK_GENCTRL_OE_Pos) + | (CONF_GCLK_GEN_11_OOV << GCLK_GENCTRL_OOV_Pos) | (CONF_GCLK_GEN_11_IDC << GCLK_GENCTRL_IDC_Pos) + | (CONF_GCLK_GENERATOR_11_CONFIG << GCLK_GENCTRL_GENEN_Pos) | CONF_GCLK_GEN_11_SOURCE); + } +#endif +} diff --git a/software/firmware/oracle_same54n19a/hpl/gclk/hpl_gclk_base.h b/software/firmware/oracle_same54n19a/hpl/gclk/hpl_gclk_base.h new file mode 100644 index 00000000..3e7d2825 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hpl/gclk/hpl_gclk_base.h @@ -0,0 +1,87 @@ +/** + * \file + * + * \brief Generic Clock Controller. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifndef _HPL_GCLK_H_INCLUDED +#define _HPL_GCLK_H_INCLUDED + +#include +#ifdef _UNIT_TEST_ +#include +#endif + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup gclk_group GCLK Hardware Proxy Layer + * + * \section gclk_hpl_rev Revision History + * - v0.0.0.1 Initial Commit + * + *@{ + */ + +/** + * \name HPL functions + */ +//@{ +/** + * \brief Enable clock on the given channel with the given clock source + * + * This function maps the given clock source to the given clock channel + * and enables channel. + * + * \param[in] channel The channel to enable clock for + * \param[in] source The clock source for the given channel + */ +static inline void _gclk_enable_channel(const uint8_t channel, const uint8_t source) +{ + + hri_gclk_write_PCHCTRL_reg(GCLK, channel, source | GCLK_PCHCTRL_CHEN); +} + +/** + * \brief Initialize GCLK generators by function references + * \param[in] bm Bit mapping for referenced generators, + * a bit 1 in position triggers generator initialization. + */ +void _gclk_init_generators_by_fref(uint32_t bm); + +//@} +/**@}*/ +#ifdef __cplusplus +} +#endif + +#endif /* _HPL_GCLK_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hpl/mclk/hpl_mclk.c b/software/firmware/oracle_same54n19a/hpl/mclk/hpl_mclk.c new file mode 100644 index 00000000..66843205 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hpl/mclk/hpl_mclk.c @@ -0,0 +1,44 @@ +/** + * \file + * + * \brief SAM Main Clock. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Initialize master clock generator + */ +void _mclk_init(void) +{ + void *hw = (void *)MCLK; + hri_mclk_write_CPUDIV_reg(hw, MCLK_CPUDIV_DIV(CONF_MCLK_CPUDIV)); +} diff --git a/software/firmware/oracle_same54n19a/hpl/osc32kctrl/hpl_osc32kctrl.c b/software/firmware/oracle_same54n19a/hpl/osc32kctrl/hpl_osc32kctrl.c new file mode 100644 index 00000000..8859b42e --- /dev/null +++ b/software/firmware/oracle_same54n19a/hpl/osc32kctrl/hpl_osc32kctrl.c @@ -0,0 +1,82 @@ + +/** + * \file + * + * \brief SAM 32k Oscillators Controller. + * + * Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include + +/** + * \brief Initialize 32 kHz clock sources + */ +void _osc32kctrl_init_sources(void) +{ + void * hw = (void *)OSC32KCTRL; + uint16_t calib = 0; + +#if CONF_XOSC32K_CONFIG == 1 + hri_osc32kctrl_write_XOSC32K_reg( + hw, + OSC32KCTRL_XOSC32K_STARTUP(CONF_XOSC32K_STARTUP) | (CONF_XOSC32K_ONDEMAND << OSC32KCTRL_XOSC32K_ONDEMAND_Pos) + | (CONF_XOSC32K_RUNSTDBY << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos) + | (CONF_XOSC32K_EN1K << OSC32KCTRL_XOSC32K_EN1K_Pos) | (CONF_XOSC32K_EN32K << OSC32KCTRL_XOSC32K_EN32K_Pos) + | (CONF_XOSC32K_XTALEN << OSC32KCTRL_XOSC32K_XTALEN_Pos) | +#ifdef CONF_XOSC32K_CGM + OSC32KCTRL_XOSC32K_CGM(CONF_XOSC32K_CGM) | +#endif + (CONF_XOSC32K_ENABLE << OSC32KCTRL_XOSC32K_ENABLE_Pos)); + + hri_osc32kctrl_write_CFDCTRL_reg(hw, (CONF_XOSC32K_CFDEN << OSC32KCTRL_CFDCTRL_CFDEN_Pos)); + + hri_osc32kctrl_write_EVCTRL_reg(hw, (CONF_XOSC32K_CFDEO << OSC32KCTRL_EVCTRL_CFDEO_Pos)); +#endif + +#if CONF_OSCULP32K_CONFIG == 1 + calib = hri_osc32kctrl_read_OSCULP32K_CALIB_bf(hw); + hri_osc32kctrl_write_OSCULP32K_reg(hw, +#if CONF_OSCULP32K_CALIB_ENABLE == 1 + OSC32KCTRL_OSCULP32K_CALIB(CONF_OSCULP32K_CALIB) +#else + OSC32KCTRL_OSCULP32K_CALIB(calib) +#endif + ); +#endif + +#if CONF_XOSC32K_CONFIG +#if CONF_XOSC32K_ENABLE == 1 && CONF_XOSC32K_ONDEMAND == 0 + while (!hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(hw)) + ; +#endif +#endif + + hri_osc32kctrl_write_RTCCTRL_reg(hw, OSC32KCTRL_RTCCTRL_RTCSEL(CONF_RTCCTRL)); + (void)calib; +} diff --git a/software/firmware/oracle_same54n19a/hpl/oscctrl/hpl_oscctrl.c b/software/firmware/oracle_same54n19a/hpl/oscctrl/hpl_oscctrl.c new file mode 100644 index 00000000..9f550763 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hpl/oscctrl/hpl_oscctrl.c @@ -0,0 +1,230 @@ + +/** + * \file + * + * \brief SAM Oscillators Controller. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +/** + * \brief Initialize clock sources + */ +void _oscctrl_init_sources(void) +{ + void *hw = (void *)OSCCTRL; + +#if CONF_XOSC0_CONFIG == 1 + hri_oscctrl_write_XOSCCTRL_reg( + hw, + 0, + OSCCTRL_XOSCCTRL_CFDPRESC(CONF_XOSC0_CFDPRESC) | OSCCTRL_XOSCCTRL_STARTUP(CONF_XOSC0_STARTUP) + | (CONF_XOSC0_SWBEN << OSCCTRL_XOSCCTRL_SWBEN_Pos) | (CONF_XOSC0_CFDEN << OSCCTRL_XOSCCTRL_CFDEN_Pos) + | (0 << OSCCTRL_XOSCCTRL_ENALC_Pos) | OSCCTRL_XOSCCTRL_IMULT(CONF_XOSC0_IMULT) + | OSCCTRL_XOSCCTRL_IPTAT(CONF_XOSC0_IPTAT) | (CONF_XOSC0_LOWBUFGAIN << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos) + | (0 << OSCCTRL_XOSCCTRL_ONDEMAND_Pos) | (CONF_XOSC0_RUNSTDBY << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos) + | (CONF_XOSC0_XTALEN << OSCCTRL_XOSCCTRL_XTALEN_Pos) | (CONF_XOSC0_ENABLE << OSCCTRL_XOSCCTRL_ENABLE_Pos)); +#endif + +#if CONF_XOSC0_CONFIG == 1 +#if CONF_XOSC0_ENABLE == 1 + while (!hri_oscctrl_get_STATUS_XOSCRDY0_bit(hw)) + ; +#endif +#if CONF_XOSC0_ENALC == 1 + hri_oscctrl_set_XOSCCTRL_ENALC_bit(hw, 0); +#endif +#if CONF_XOSC0_ONDEMAND == 1 + hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(hw, 0); +#endif +#endif + +#if CONF_XOSC1_CONFIG == 1 + hri_oscctrl_write_XOSCCTRL_reg( + hw, + 1, + OSCCTRL_XOSCCTRL_CFDPRESC(CONF_XOSC1_CFDPRESC) | OSCCTRL_XOSCCTRL_STARTUP(CONF_XOSC1_STARTUP) + | (CONF_XOSC1_SWBEN << OSCCTRL_XOSCCTRL_SWBEN_Pos) | (CONF_XOSC1_CFDEN << OSCCTRL_XOSCCTRL_CFDEN_Pos) + | (0 << OSCCTRL_XOSCCTRL_ENALC_Pos) | OSCCTRL_XOSCCTRL_IMULT(CONF_XOSC1_IMULT) + | OSCCTRL_XOSCCTRL_IPTAT(CONF_XOSC1_IPTAT) | (CONF_XOSC1_LOWBUFGAIN << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos) + | (0 << OSCCTRL_XOSCCTRL_ONDEMAND_Pos) | (CONF_XOSC1_RUNSTDBY << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos) + | (CONF_XOSC1_XTALEN << OSCCTRL_XOSCCTRL_XTALEN_Pos) | (CONF_XOSC1_ENABLE << OSCCTRL_XOSCCTRL_ENABLE_Pos)); +#endif + +#if CONF_XOSC1_CONFIG == 1 +#if CONF_XOSC1_ENABLE == 1 + while (!hri_oscctrl_get_STATUS_XOSCRDY1_bit(hw)) + ; +#endif +#if CONF_XOSC1_ENALC == 1 + hri_oscctrl_set_XOSCCTRL_ENALC_bit(hw, 1); +#endif +#if CONF_XOSC1_ONDEMAND == 1 + hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(hw, 1); +#endif +#endif + + (void)hw; +} + +void _oscctrl_init_referenced_generators(void) +{ + void *hw = (void *)OSCCTRL; + +#if CONF_DFLL_CONFIG == 1 + hri_gclk_write_GENCTRL_SRC_bf(GCLK, 0, GCLK_GENCTRL_SRC_OSCULP32K); + while (hri_gclk_get_SYNCBUSY_GENCTRL0_bit(GCLK)) + ; + uint8_t tmp; + hri_oscctrl_write_DFLLCTRLA_reg(hw, 0); +#if CONF_DFLL_USBCRM != 1 && CONF_DFLL_MODE != 0 + hri_gclk_write_PCHCTRL_reg( + GCLK, OSCCTRL_GCLK_ID_DFLL48, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_DFLL_GCLK)); +#endif + + hri_oscctrl_write_DFLLMUL_reg(hw, + OSCCTRL_DFLLMUL_CSTEP(CONF_DFLL_CSTEP) | OSCCTRL_DFLLMUL_FSTEP(CONF_DFLL_FSTEP) + | OSCCTRL_DFLLMUL_MUL(CONF_DFLL_MUL)); + while (hri_oscctrl_get_DFLLSYNC_DFLLMUL_bit(hw)) + ; + + hri_oscctrl_write_DFLLCTRLB_reg(hw, 0); + while (hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(hw)) + ; + + tmp = (CONF_DFLL_RUNSTDBY << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos) | OSCCTRL_DFLLCTRLA_ENABLE; + hri_oscctrl_write_DFLLCTRLA_reg(hw, tmp); + while (hri_oscctrl_get_DFLLSYNC_ENABLE_bit(hw)) + ; + +#if CONF_DFLL_OVERWRITE_CALIBRATION == 1 + hri_oscctrl_write_DFLLVAL_reg(hw, OSCCTRL_DFLLVAL_COARSE(CONF_DFLL_COARSE) | OSCCTRL_DFLLVAL_FINE(CONF_DFLL_FINE)); +#endif + hri_oscctrl_write_DFLLVAL_reg(hw, hri_oscctrl_read_DFLLVAL_reg(hw)); + while (hri_oscctrl_get_DFLLSYNC_DFLLVAL_bit(hw)) + ; + + tmp = (CONF_DFLL_WAITLOCK << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos) | (CONF_DFLL_BPLCKC << OSCCTRL_DFLLCTRLB_BPLCKC_Pos) + | (CONF_DFLL_QLDIS << OSCCTRL_DFLLCTRLB_QLDIS_Pos) | (CONF_DFLL_CCDIS << OSCCTRL_DFLLCTRLB_CCDIS_Pos) + | (CONF_DFLL_USBCRM << OSCCTRL_DFLLCTRLB_USBCRM_Pos) | (CONF_DFLL_LLAW << OSCCTRL_DFLLCTRLB_LLAW_Pos) + | (CONF_DFLL_STABLE << OSCCTRL_DFLLCTRLB_STABLE_Pos) | (CONF_DFLL_MODE << OSCCTRL_DFLLCTRLB_MODE_Pos) | 0; + hri_oscctrl_write_DFLLCTRLB_reg(hw, tmp); + while (hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(hw)) + ; +#endif + +#if CONF_FDPLL0_CONFIG == 1 +#if CONF_FDPLL0_REFCLK == 0 + hri_gclk_write_PCHCTRL_reg( + GCLK, OSCCTRL_GCLK_ID_FDPLL0, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_FDPLL0_GCLK)); +#endif + hri_oscctrl_write_DPLLRATIO_reg( + hw, 0, OSCCTRL_DPLLRATIO_LDRFRAC(CONF_FDPLL0_LDRFRAC) | OSCCTRL_DPLLRATIO_LDR(CONF_FDPLL0_LDR)); + hri_oscctrl_write_DPLLCTRLB_reg( + hw, + 0, + OSCCTRL_DPLLCTRLB_DIV(CONF_FDPLL0_DIV) | (CONF_FDPLL0_DCOEN << OSCCTRL_DPLLCTRLB_DCOEN_Pos) + | OSCCTRL_DPLLCTRLB_DCOFILTER(CONF_FDPLL0_DCOFILTER) + | (CONF_FDPLL0_LBYPASS << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) | OSCCTRL_DPLLCTRLB_LTIME(CONF_FDPLL0_LTIME) + | OSCCTRL_DPLLCTRLB_REFCLK(CONF_FDPLL0_REFCLK) | (CONF_FDPLL0_WUF << OSCCTRL_DPLLCTRLB_WUF_Pos) + | OSCCTRL_DPLLCTRLB_FILTER(CONF_FDPLL0_FILTER)); + hri_oscctrl_write_DPLLCTRLA_reg(hw, + 0, + (CONF_FDPLL0_RUNSTDBY << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos) + | (CONF_FDPLL0_ENABLE << OSCCTRL_DPLLCTRLA_ENABLE_Pos)); +#endif + +#if CONF_FDPLL1_CONFIG == 1 +#if CONF_FDPLL1_REFCLK == 0 + hri_gclk_write_PCHCTRL_reg( + GCLK, OSCCTRL_GCLK_ID_FDPLL1, (1 << GCLK_PCHCTRL_CHEN_Pos) | GCLK_PCHCTRL_GEN(CONF_FDPLL1_GCLK)); +#endif + hri_oscctrl_write_DPLLRATIO_reg( + hw, 1, OSCCTRL_DPLLRATIO_LDRFRAC(CONF_FDPLL1_LDRFRAC) | OSCCTRL_DPLLRATIO_LDR(CONF_FDPLL1_LDR)); + hri_oscctrl_write_DPLLCTRLB_reg( + hw, + 1, + OSCCTRL_DPLLCTRLB_DIV(CONF_FDPLL1_DIV) | (CONF_FDPLL1_DCOEN << OSCCTRL_DPLLCTRLB_DCOEN_Pos) + | OSCCTRL_DPLLCTRLB_DCOFILTER(CONF_FDPLL1_DCOFILTER) + | (CONF_FDPLL1_LBYPASS << OSCCTRL_DPLLCTRLB_LBYPASS_Pos) | OSCCTRL_DPLLCTRLB_LTIME(CONF_FDPLL1_LTIME) + | OSCCTRL_DPLLCTRLB_REFCLK(CONF_FDPLL1_REFCLK) | (CONF_FDPLL1_WUF << OSCCTRL_DPLLCTRLB_WUF_Pos) + | OSCCTRL_DPLLCTRLB_FILTER(CONF_FDPLL1_FILTER)); + hri_oscctrl_write_DPLLCTRLA_reg(hw, + 1, + (CONF_FDPLL1_RUNSTDBY << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos) + | (CONF_FDPLL1_ENABLE << OSCCTRL_DPLLCTRLA_ENABLE_Pos)); +#endif + +#if CONF_DFLL_CONFIG == 1 + if (hri_oscctrl_get_DFLLCTRLB_MODE_bit(hw)) { + hri_oscctrl_status_reg_t status_mask = OSCCTRL_STATUS_DFLLRDY | OSCCTRL_STATUS_DFLLLCKC; + + while (hri_oscctrl_get_STATUS_reg(hw, status_mask) != status_mask) + ; + } else { + while (!hri_oscctrl_get_STATUS_DFLLRDY_bit(hw)) + ; + } +#if CONF_DFLL_ONDEMAND == 1 + hri_oscctrl_set_DFLLCTRLA_ONDEMAND_bit(hw); +#endif +#endif + +#if CONF_FDPLL0_CONFIG == 1 +#if CONF_FDPLL0_ENABLE == 1 + while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw, 0) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw, 0))) + ; +#endif +#if CONF_FDPLL0_ONDEMAND == 1 + hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(hw, 0); +#endif +#endif + +#if CONF_FDPLL1_CONFIG == 1 +#if CONF_FDPLL1_ENABLE == 1 + while (!(hri_oscctrl_get_DPLLSTATUS_LOCK_bit(hw, 1) || hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(hw, 1))) + ; +#endif +#if CONF_FDPLL1_ONDEMAND == 1 + hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(hw, 1); +#endif +#endif + +#if CONF_DFLL_CONFIG == 1 + while (hri_gclk_read_SYNCBUSY_reg(GCLK)) + ; + hri_gclk_write_GENCTRL_SRC_bf(GCLK, 0, CONF_GCLK_GEN_0_SOURCE); + while (hri_gclk_get_SYNCBUSY_GENCTRL0_bit(GCLK)) + ; +#endif + (void)hw; +} diff --git a/software/firmware/oracle_same54n19a/hpl/pm/hpl_pm.c b/software/firmware/oracle_same54n19a/hpl/pm/hpl_pm.c new file mode 100644 index 00000000..55dc4dbe --- /dev/null +++ b/software/firmware/oracle_same54n19a/hpl/pm/hpl_pm.c @@ -0,0 +1,68 @@ + +/** + * \file + * + * \brief SAM Power manager + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include + +/** + * \brief Set the sleep mode for the device + */ +int32_t _set_sleep_mode(const uint8_t mode) +{ + uint8_t delay = 10; + + switch (mode) { + case 2: + case 4: + case 5: + case 6: + case 7: + hri_pm_write_SLEEPCFG_reg(PM, mode); + /* A small latency happens between the store instruction and actual + * writing of the SLEEPCFG register due to bridges. Software has to make + * sure the SLEEPCFG register reads the wanted value before issuing WFI + * instruction. + */ + do { + if (hri_pm_read_SLEEPCFG_reg(PM) == mode) { + break; + } + } while (--delay); + break; + default: + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} diff --git a/software/firmware/oracle_same54n19a/hpl/pm/hpl_pm_base.h b/software/firmware/oracle_same54n19a/hpl/pm/hpl_pm_base.h new file mode 100644 index 00000000..5a50a914 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hpl/pm/hpl_pm_base.h @@ -0,0 +1,45 @@ +/** + * \file + * + * \brief SAM Power manager + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifndef _HPL_PM_BASE_H_INCLUDED +#define _HPL_PM_BASE_H_INCLUDED + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +#ifdef __cplusplus +} +#endif +#endif /* _HPL_PM_BASE_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hpl/port/hpl_gpio_base.h b/software/firmware/oracle_same54n19a/hpl/port/hpl_gpio_base.h new file mode 100644 index 00000000..12ff6f74 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hpl/port/hpl_gpio_base.h @@ -0,0 +1,171 @@ + +/** + * \file + * + * \brief SAM PORT. + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include + +/** + * \brief Set direction on port with mask + */ +static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask, + const enum gpio_direction direction) +{ + switch (direction) { + case GPIO_DIRECTION_OFF: + hri_port_clear_DIR_reg(PORT, port, mask); + hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); + hri_port_write_WRCONFIG_reg( + PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); + break; + + case GPIO_DIRECTION_IN: + hri_port_clear_DIR_reg(PORT, port, mask); + hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN | (mask & 0xffff)); + hri_port_write_WRCONFIG_reg(PORT, + port, + PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | PORT_WRCONFIG_INEN + | ((mask & 0xffff0000) >> 16)); + break; + + case GPIO_DIRECTION_OUT: + hri_port_set_DIR_reg(PORT, port, mask); + hri_port_write_WRCONFIG_reg(PORT, port, PORT_WRCONFIG_WRPINCFG | (mask & 0xffff)); + hri_port_write_WRCONFIG_reg( + PORT, port, PORT_WRCONFIG_HWSEL | PORT_WRCONFIG_WRPINCFG | ((mask & 0xffff0000) >> 16)); + break; + + default: + ASSERT(false); + } +} + +/** + * \brief Set output level on port with mask + */ +static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level) +{ + if (level) { + hri_port_set_OUT_reg(PORT, port, mask); + } else { + hri_port_clear_OUT_reg(PORT, port, mask); + } +} + +/** + * \brief Change output level to the opposite with mask + */ +static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask) +{ + hri_port_toggle_OUT_reg(PORT, port, mask); +} + +/** + * \brief Get input levels on all port pins + */ +static inline uint32_t _gpio_get_level(const enum gpio_port port) +{ + uint32_t tmp; + + CRITICAL_SECTION_ENTER(); + + uint32_t dir_tmp = hri_port_read_DIR_reg(PORT, port); + + tmp = hri_port_read_IN_reg(PORT, port) & ~dir_tmp; + tmp |= hri_port_read_OUT_reg(PORT, port) & dir_tmp; + + CRITICAL_SECTION_LEAVE(); + + return tmp; +} + +/** + * \brief Set pin pull mode + */ +static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin, + const enum gpio_pull_mode pull_mode) +{ + switch (pull_mode) { + case GPIO_PULL_OFF: + hri_port_clear_PINCFG_PULLEN_bit(PORT, port, pin); + break; + + case GPIO_PULL_UP: + hri_port_clear_DIR_reg(PORT, port, 1U << pin); + hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin); + hri_port_set_OUT_reg(PORT, port, 1U << pin); + break; + + case GPIO_PULL_DOWN: + hri_port_clear_DIR_reg(PORT, port, 1U << pin); + hri_port_set_PINCFG_PULLEN_bit(PORT, port, pin); + hri_port_clear_OUT_reg(PORT, port, 1U << pin); + break; + + default: + ASSERT(false); + break; + } +} + +/** + * \brief Set gpio pin function + */ +static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function) +{ + uint8_t port = GPIO_PORT(gpio); + uint8_t pin = GPIO_PIN(gpio); + + if (function == GPIO_PIN_FUNCTION_OFF) { + hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, false); + + } else { + hri_port_write_PINCFG_PMUXEN_bit(PORT, port, pin, true); + + if (pin & 1) { + // Odd numbered pin + hri_port_write_PMUX_PMUXO_bf(PORT, port, pin >> 1, function & 0xffff); + } else { + // Even numbered pin + hri_port_write_PMUX_PMUXE_bf(PORT, port, pin >> 1, function & 0xffff); + } + } +} + +static inline void _port_event_init() +{ + hri_port_set_EVCTRL_reg(PORT, 0, CONF_PORTA_EVCTRL); + hri_port_set_EVCTRL_reg(PORT, 1, CONF_PORTB_EVCTRL); + hri_port_set_EVCTRL_reg(PORT, 2, CONF_PORTC_EVCTRL); +} diff --git a/software/firmware/oracle_same54n19a/hpl/ramecc/hpl_ramecc.c b/software/firmware/oracle_same54n19a/hpl/ramecc/hpl_ramecc.c new file mode 100644 index 00000000..4c158b20 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hpl/ramecc/hpl_ramecc.c @@ -0,0 +1,83 @@ +/** + * \file + * + * \brief Generic RAMECC related functionality. + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include + +/* RAMECC device descriptor */ +struct _ramecc_device device; + +/** + * \brief Initialize RAMECC + */ +int32_t _ramecc_init(void) +{ + if (hri_ramecc_get_STATUS_ECCDIS_bit(RAMECC)) { + return ERR_ABORTED; + } + + NVIC_DisableIRQ(RAMECC_IRQn); + NVIC_ClearPendingIRQ(RAMECC_IRQn); + NVIC_EnableIRQ(RAMECC_IRQn); + + return ERR_NONE; +} + +void _ramecc_register_callback(const enum _ramecc_callback_type type, ramecc_cb_t cb) +{ + if (RAMECC_DUAL_ERROR_CB == type) { + device.ramecc_cb.dual_bit_err = cb; + hri_ramecc_write_INTEN_DUALE_bit(RAMECC, NULL != cb); + } else if (RAMECC_SINGLE_ERROR_CB == type) { + device.ramecc_cb.single_bit_err = cb; + hri_ramecc_write_INTEN_SINGLEE_bit(RAMECC, NULL != cb); + } +} + +/** + * \internal RAMECC interrupt handler + */ +void RAMECC_Handler(void) +{ + struct _ramecc_device *dev = (struct _ramecc_device *)&device; + volatile uint32_t int_mask = hri_ramecc_read_INTFLAG_reg(RAMECC); + + if (int_mask & RAMECC_INTFLAG_DUALE && dev->ramecc_cb.dual_bit_err) { + dev->ramecc_cb.dual_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC)); + } else if (int_mask & RAMECC_INTFLAG_SINGLEE && dev->ramecc_cb.single_bit_err) { + dev->ramecc_cb.single_bit_err((uint32_t)hri_ramecc_read_ERRADDR_reg(RAMECC)); + } else { + return; + } +} diff --git a/software/firmware/oracle_same54n19a/hpl/sercom/hpl_sercom.c b/software/firmware/oracle_same54n19a/hpl/sercom/hpl_sercom.c new file mode 100644 index 00000000..47f3d378 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hpl/sercom/hpl_sercom.c @@ -0,0 +1,3028 @@ + +/** + * \file + * + * \brief SAM Serial Communication Interface + * + * Copyright (c) 2014-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef CONF_SERCOM_0_USART_ENABLE +#define CONF_SERCOM_0_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_USART_ENABLE +#define CONF_SERCOM_1_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_USART_ENABLE +#define CONF_SERCOM_2_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_USART_ENABLE +#define CONF_SERCOM_3_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_USART_ENABLE +#define CONF_SERCOM_4_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_USART_ENABLE +#define CONF_SERCOM_5_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_USART_ENABLE +#define CONF_SERCOM_6_USART_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_USART_ENABLE +#define CONF_SERCOM_7_USART_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as USART. */ +#define SERCOM_USART_AMOUNT \ + (CONF_SERCOM_0_USART_ENABLE + CONF_SERCOM_1_USART_ENABLE + CONF_SERCOM_2_USART_ENABLE + CONF_SERCOM_3_USART_ENABLE \ + + CONF_SERCOM_4_USART_ENABLE + CONF_SERCOM_5_USART_ENABLE + CONF_SERCOM_6_USART_ENABLE \ + + CONF_SERCOM_7_USART_ENABLE) + +/** + * \brief Macro is used to fill usart configuration structure based on + * its number + * + * \param[in] n The number of structures + */ +#define SERCOM_CONFIGURATION(n) \ + { \ + n, \ + SERCOM_USART_CTRLA_MODE(CONF_SERCOM_##n##_USART_MODE) \ + | (CONF_SERCOM_##n##_USART_RUNSTDBY << SERCOM_USART_CTRLA_RUNSTDBY_Pos) \ + | (CONF_SERCOM_##n##_USART_IBON << SERCOM_USART_CTRLA_IBON_Pos) \ + | (CONF_SERCOM_##n##_USART_TXINV << SERCOM_USART_CTRLA_TXINV_Pos) \ + | (CONF_SERCOM_##n##_USART_RXINV << SERCOM_USART_CTRLA_RXINV_Pos) \ + | SERCOM_USART_CTRLA_SAMPR(CONF_SERCOM_##n##_USART_SAMPR) \ + | SERCOM_USART_CTRLA_TXPO(CONF_SERCOM_##n##_USART_TXPO) \ + | SERCOM_USART_CTRLA_RXPO(CONF_SERCOM_##n##_USART_RXPO) \ + | SERCOM_USART_CTRLA_SAMPA(CONF_SERCOM_##n##_USART_SAMPA) \ + | SERCOM_USART_CTRLA_FORM(CONF_SERCOM_##n##_USART_FORM) \ + | (CONF_SERCOM_##n##_USART_CMODE << SERCOM_USART_CTRLA_CMODE_Pos) \ + | (CONF_SERCOM_##n##_USART_CPOL << SERCOM_USART_CTRLA_CPOL_Pos) \ + | (CONF_SERCOM_##n##_USART_DORD << SERCOM_USART_CTRLA_DORD_Pos), \ + SERCOM_USART_CTRLB_CHSIZE(CONF_SERCOM_##n##_USART_CHSIZE) \ + | (CONF_SERCOM_##n##_USART_SBMODE << SERCOM_USART_CTRLB_SBMODE_Pos) \ + | (CONF_SERCOM_##n##_USART_CLODEN << SERCOM_USART_CTRLB_COLDEN_Pos) \ + | (CONF_SERCOM_##n##_USART_SFDE << SERCOM_USART_CTRLB_SFDE_Pos) \ + | (CONF_SERCOM_##n##_USART_ENC << SERCOM_USART_CTRLB_ENC_Pos) \ + | (CONF_SERCOM_##n##_USART_PMODE << SERCOM_USART_CTRLB_PMODE_Pos) \ + | (CONF_SERCOM_##n##_USART_TXEN << SERCOM_USART_CTRLB_TXEN_Pos) \ + | (CONF_SERCOM_##n##_USART_RXEN << SERCOM_USART_CTRLB_RXEN_Pos), \ + SERCOM_USART_CTRLC_GTIME(CONF_SERCOM_##n##_USART_GTIME) \ + | (CONF_SERCOM_##n##_USART_DSNACK << SERCOM_USART_CTRLC_DSNACK_Pos) \ + | (CONF_SERCOM_##n##_USART_INACK << SERCOM_USART_CTRLC_INACK_Pos) \ + | SERCOM_USART_CTRLC_MAXITER(CONF_SERCOM_##n##_USART_MAXITER), \ + (uint16_t)(CONF_SERCOM_##n##_USART_BAUD_RATE), CONF_SERCOM_##n##_USART_FRACTIONAL, \ + CONF_SERCOM_##n##_USART_RECEIVE_PULSE_LENGTH, CONF_SERCOM_##n##_USART_DEBUG_STOP_MODE, \ + } + +/** + * \brief SERCOM USART configuration type + */ +struct usart_configuration { + uint8_t number; + hri_sercomusart_ctrla_reg_t ctrl_a; + hri_sercomusart_ctrlb_reg_t ctrl_b; + hri_sercomusart_ctrlc_reg_t ctrl_c; + hri_sercomusart_baud_reg_t baud; + uint8_t fractional; + hri_sercomusart_rxpl_reg_t rxpl; + hri_sercomusart_dbgctrl_reg_t debug_ctrl; +}; + +#if SERCOM_USART_AMOUNT < 1 +/** Dummy array to pass compiling. */ +static struct usart_configuration _usarts[1] = {{0}}; +#else +/** + * \brief Array of SERCOM USART configurations + */ +static struct usart_configuration _usarts[] = { +#if CONF_SERCOM_0_USART_ENABLE == 1 + SERCOM_CONFIGURATION(0), +#endif +#if CONF_SERCOM_1_USART_ENABLE == 1 + SERCOM_CONFIGURATION(1), +#endif +#if CONF_SERCOM_2_USART_ENABLE == 1 + SERCOM_CONFIGURATION(2), +#endif +#if CONF_SERCOM_3_USART_ENABLE == 1 + SERCOM_CONFIGURATION(3), +#endif +#if CONF_SERCOM_4_USART_ENABLE == 1 + SERCOM_CONFIGURATION(4), +#endif +#if CONF_SERCOM_5_USART_ENABLE == 1 + SERCOM_CONFIGURATION(5), +#endif +#if CONF_SERCOM_6_USART_ENABLE == 1 + SERCOM_CONFIGURATION(6), +#endif +#if CONF_SERCOM_7_USART_ENABLE == 1 + SERCOM_CONFIGURATION(7), +#endif +}; +#endif + +static struct _usart_async_device *_sercom0_dev = NULL; + +static uint8_t _get_sercom_index(const void *const hw); +static uint8_t _sercom_get_irq_num(const void *const hw); +static void _sercom_init_irq_param(const void *const hw, void *dev); +static uint8_t _sercom_get_hardware_index(const void *const hw); + +static int32_t _usart_init(void *const hw); +static inline void _usart_deinit(void *const hw); +static uint16_t _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction); +static void _usart_set_baud_rate(void *const hw, const uint32_t baud_rate); +static void _usart_set_data_order(void *const hw, const enum usart_data_order order); +static void _usart_set_mode(void *const hw, const enum usart_mode mode); +static void _usart_set_parity(void *const hw, const enum usart_parity parity); +static void _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits); +static void _usart_set_character_size(void *const hw, const enum usart_character_size size); + +/** + * \brief Initialize synchronous SERCOM USART + */ +int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw) +{ + ASSERT(device); + + device->hw = hw; + + return _usart_init(hw); +} + +/** + * \brief Initialize asynchronous SERCOM USART + */ +int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw) +{ + int32_t init_status; + + ASSERT(device); + + init_status = _usart_init(hw); + if (init_status) { + return init_status; + } + device->hw = hw; + _sercom_init_irq_param(hw, (void *)device); + uint8_t irq = _sercom_get_irq_num(hw); + for (uint32_t i = 0; i < 4; i++) { + NVIC_DisableIRQ((IRQn_Type)irq); + NVIC_ClearPendingIRQ((IRQn_Type)irq); + NVIC_EnableIRQ((IRQn_Type)irq); + irq++; + } + return ERR_NONE; +} + +/** + * \brief De-initialize SERCOM USART + */ +void _usart_sync_deinit(struct _usart_sync_device *const device) +{ + _usart_deinit(device->hw); +} + +/** + * \brief De-initialize SERCOM USART + */ +void _usart_async_deinit(struct _usart_async_device *const device) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(device->hw)); + _usart_deinit(device->hw); +} + +/** + * \brief Calculate baud rate register value + */ +uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction) +{ + return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction); +} + +/** + * \brief Calculate baud rate register value + */ +uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction) +{ + return _usart_calculate_baud_rate(baud, clock_rate, samples, mode, fraction); +} + +/** + * \brief Enable SERCOM module + */ +void _usart_sync_enable(struct _usart_sync_device *const device) +{ + hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Enable SERCOM module + */ +void _usart_async_enable(struct _usart_async_device *const device) +{ + hri_sercomusart_set_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Disable SERCOM module + */ +void _usart_sync_disable(struct _usart_sync_device *const device) +{ + hri_sercomusart_clear_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Disable SERCOM module + */ +void _usart_async_disable(struct _usart_async_device *const device) +{ + hri_sercomusart_clear_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Set baud rate + */ +void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate) +{ + _usart_set_baud_rate(device->hw, baud_rate); +} + +/** + * \brief Set baud rate + */ +void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate) +{ + _usart_set_baud_rate(device->hw, baud_rate); +} + +/** + * \brief Set data order + */ +void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order) +{ + _usart_set_data_order(device->hw, order); +} + +/** + * \brief Set data order + */ +void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order) +{ + _usart_set_data_order(device->hw, order); +} + +/** + * \brief Set mode + */ +void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode) +{ + _usart_set_mode(device->hw, mode); +} + +/** + * \brief Set mode + */ +void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode) +{ + _usart_set_mode(device->hw, mode); +} + +/** + * \brief Set parity + */ +void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity) +{ + _usart_set_parity(device->hw, parity); +} + +/** + * \brief Set parity + */ +void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity) +{ + _usart_set_parity(device->hw, parity); +} + +/** + * \brief Set stop bits mode + */ +void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits) +{ + _usart_set_stop_bits(device->hw, stop_bits); +} + +/** + * \brief Set stop bits mode + */ +void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits) +{ + _usart_set_stop_bits(device->hw, stop_bits); +} + +/** + * \brief Set character size + */ +void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size) +{ + _usart_set_character_size(device->hw, size); +} + +/** + * \brief Set character size + */ +void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size) +{ + _usart_set_character_size(device->hw, size); +} + +/** + * \brief Retrieve SERCOM usart status + */ +uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_read_STATUS_reg(device->hw); +} + +/** + * \brief Retrieve SERCOM usart status + */ +uint32_t _usart_async_get_status(const struct _usart_async_device *const device) +{ + return hri_sercomusart_read_STATUS_reg(device->hw); +} + +/** + * \brief Write a byte to the given SERCOM USART instance + */ +void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data) +{ + hri_sercomusart_write_DATA_reg(device->hw, data); +} + +/** + * \brief Write a byte to the given SERCOM USART instance + */ +void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data) +{ + hri_sercomusart_write_DATA_reg(device->hw, data); +} + +/** + * \brief Read a byte from the given SERCOM USART instance + */ +uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_read_DATA_reg(device->hw); +} + +/** + * \brief Check if USART is ready to send next byte + */ +bool _usart_sync_is_ready_to_send(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_get_interrupt_DRE_bit(device->hw); +} + +/** + * \brief Check if USART transmission complete + */ +bool _usart_sync_is_transmit_done(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_get_interrupt_TXC_bit(device->hw); +} + +/** + * \brief Check if USART is ready to send next byte + */ +bool _usart_async_is_byte_sent(const struct _usart_async_device *const device) +{ + return hri_sercomusart_get_interrupt_DRE_bit(device->hw); +} + +/** + * \brief Check if there is data received by USART + */ +bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device) +{ + return hri_sercomusart_get_interrupt_RXC_bit(device->hw); +} + +/** + * \brief Set the state of flow control pins + */ +void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device, + const union usart_flow_control_state state) +{ + (void)device; + (void)state; +} + +/** + * \brief Set the state of flow control pins + */ +void _usart_async_set_flow_control_state(struct _usart_async_device *const device, + const union usart_flow_control_state state) +{ + (void)device; + (void)state; +} + +/** + * \brief Retrieve the state of flow control pins + */ +union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device) +{ + (void)device; + union usart_flow_control_state state; + + state.value = 0; + state.bit.unavailable = 1; + return state; +} + +/** + * \brief Retrieve the state of flow control pins + */ +union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device) +{ + (void)device; + union usart_flow_control_state state; + + state.value = 0; + state.bit.unavailable = 1; + return state; +} + +/** + * \brief Enable data register empty interrupt + */ +void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device) +{ + hri_sercomusart_set_INTEN_DRE_bit(device->hw); +} + +/** + * \brief Enable transmission complete interrupt + */ +void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device) +{ + hri_sercomusart_set_INTEN_TXC_bit(device->hw); +} + +/** + * \brief Retrieve ordinal number of the given sercom hardware instance + */ +static uint8_t _sercom_get_hardware_index(const void *const hw) +{ + Sercom *const sercom_modules[] = SERCOM_INSTS; + /* Find index for SERCOM instance. */ + for (uint32_t i = 0; i < SERCOM_INST_NUM; i++) { + if ((uint32_t)hw == (uint32_t)sercom_modules[i]) { + return i; + } + } + return 0; +} + +/** + * \brief Retrieve ordinal number of the given SERCOM USART hardware instance + */ +uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device) +{ + return _sercom_get_hardware_index(device->hw); +} + +/** + * \brief Retrieve ordinal number of the given SERCOM USART hardware instance + */ +uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device) +{ + return _sercom_get_hardware_index(device->hw); +} + +/** + * \brief Enable/disable USART interrupt + */ +void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type, + const bool state) +{ + ASSERT(device); + + if (USART_ASYNC_BYTE_SENT == type || USART_ASYNC_TX_DONE == type) { + hri_sercomusart_write_INTEN_DRE_bit(device->hw, state); + hri_sercomusart_write_INTEN_TXC_bit(device->hw, state); + } else if (USART_ASYNC_RX_DONE == type) { + hri_sercomusart_write_INTEN_RXC_bit(device->hw, state); + } else if (USART_ASYNC_ERROR == type) { + hri_sercomusart_write_INTEN_ERROR_bit(device->hw, state); + } +} + +/** + * \internal Sercom interrupt handler + * + * \param[in] p The pointer to interrupt parameter + */ +static void _sercom_usart_interrupt_handler(struct _usart_async_device *device) +{ + void *hw = device->hw; + + if (hri_sercomusart_get_interrupt_DRE_bit(hw) && hri_sercomusart_get_INTEN_DRE_bit(hw)) { + hri_sercomusart_clear_INTEN_DRE_bit(hw); + device->usart_cb.tx_byte_sent(device); + } else if (hri_sercomusart_get_interrupt_TXC_bit(hw) && hri_sercomusart_get_INTEN_TXC_bit(hw)) { + hri_sercomusart_clear_INTEN_TXC_bit(hw); + device->usart_cb.tx_done_cb(device); + } else if (hri_sercomusart_get_interrupt_RXC_bit(hw)) { + if (hri_sercomusart_read_STATUS_reg(hw) + & (SERCOM_USART_STATUS_PERR | SERCOM_USART_STATUS_FERR | SERCOM_USART_STATUS_BUFOVF + | SERCOM_USART_STATUS_ISF | SERCOM_USART_STATUS_COLL)) { + hri_sercomusart_clear_STATUS_reg(hw, SERCOM_USART_STATUS_MASK); + return; + } + + device->usart_cb.rx_done_cb(device, hri_sercomusart_read_DATA_reg(hw)); + } else if (hri_sercomusart_get_interrupt_ERROR_bit(hw)) { + uint32_t status; + + hri_sercomusart_clear_interrupt_ERROR_bit(hw); + device->usart_cb.error_cb(device); + status = hri_sercomusart_read_STATUS_reg(hw); + hri_sercomusart_clear_STATUS_reg(hw, status); + } +} + +/** + * \internal Retrieve ordinal number of the given sercom hardware instance + * + * \param[in] hw The pointer to hardware instance + + * \return The ordinal number of the given sercom hardware instance + */ +static uint8_t _get_sercom_index(const void *const hw) +{ + uint8_t sercom_offset = _sercom_get_hardware_index(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_usarts); i++) { + if (_usarts[i].number == sercom_offset) { + return i; + } + } + + ASSERT(false); + return 0; +} + +/** + * \brief Init irq param with the given sercom hardware instance + */ +static void _sercom_init_irq_param(const void *const hw, void *dev) +{ + + if (hw == SERCOM0) { + _sercom0_dev = (struct _usart_async_device *)dev; + } +} + +/** + * \internal Initialize SERCOM USART + * + * \param[in] hw The pointer to hardware instance + * + * \return The status of initialization + */ +static int32_t _usart_init(void *const hw) +{ + uint8_t i = _get_sercom_index(hw); + + if (!hri_sercomusart_is_syncing(hw, SERCOM_USART_SYNCBUSY_SWRST)) { + uint32_t mode = _usarts[i].ctrl_a & SERCOM_USART_CTRLA_MODE_Msk; + if (hri_sercomusart_get_CTRLA_reg(hw, SERCOM_USART_CTRLA_ENABLE)) { + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + } + hri_sercomusart_write_CTRLA_reg(hw, SERCOM_USART_CTRLA_SWRST | mode); + } + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); + + hri_sercomusart_write_CTRLA_reg(hw, _usarts[i].ctrl_a); + hri_sercomusart_write_CTRLB_reg(hw, _usarts[i].ctrl_b); + hri_sercomusart_write_CTRLC_reg(hw, _usarts[i].ctrl_c); + if ((_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x1)) || (_usarts[i].ctrl_a & SERCOM_USART_CTRLA_SAMPR(0x3))) { + ((Sercom *)hw)->USART.BAUD.FRAC.BAUD = _usarts[i].baud; + ((Sercom *)hw)->USART.BAUD.FRAC.FP = _usarts[i].fractional; + } else { + hri_sercomusart_write_BAUD_reg(hw, _usarts[i].baud); + } + + hri_sercomusart_write_RXPL_reg(hw, _usarts[i].rxpl); + hri_sercomusart_write_DBGCTRL_reg(hw, _usarts[i].debug_ctrl); + + return ERR_NONE; +} + +/** + * \internal De-initialize SERCOM USART + * + * \param[in] hw The pointer to hardware instance + */ +static inline void _usart_deinit(void *const hw) +{ + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + hri_sercomusart_set_CTRLA_SWRST_bit(hw); +} + +/** + * \internal Calculate baud rate register value + * + * \param[in] baud Required baud rate + * \param[in] clock_rate SERCOM clock frequency + * \param[in] samples The number of samples + * \param[in] mode USART mode + * \param[in] fraction A fraction value + * + * \return Calculated baud rate register value + */ +static uint16_t _usart_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples, + const enum usart_baud_rate_mode mode, const uint8_t fraction) +{ + if (USART_BAUDRATE_ASYNCH_ARITHMETIC == mode) { + return 65536 - ((uint64_t)65536 * samples * baud) / clock_rate; + } + + if (USART_BAUDRATE_ASYNCH_FRACTIONAL == mode) { + return clock_rate / baud / samples + SERCOM_USART_BAUD_FRACFP_FP(fraction); + } + + if (USART_BAUDRATE_SYNCH == mode) { + return clock_rate / baud / 2 - 1; + } + + return 0; +} + +/** + * \internal Set baud rate + * + * \param[in] device The pointer to USART device instance + * \param[in] baud_rate A baud rate to set + */ +static void _usart_set_baud_rate(void *const hw, const uint32_t baud_rate) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_BAUD_reg(hw, baud_rate); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set data order + * + * \param[in] device The pointer to USART device instance + * \param[in] order A data order to set + */ +static void _usart_set_data_order(void *const hw, const enum usart_data_order order) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLA_DORD_bit(hw, order); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set mode + * + * \param[in] device The pointer to USART device instance + * \param[in] mode A mode to set + */ +static void _usart_set_mode(void *const hw, const enum usart_mode mode) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLA_CMODE_bit(hw, mode); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set parity + * + * \param[in] device The pointer to USART device instance + * \param[in] parity A parity to set + */ +static void _usart_set_parity(void *const hw, const enum usart_parity parity) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + + if (USART_PARITY_NONE != parity) { + hri_sercomusart_set_CTRLA_FORM_bf(hw, 1); + } else { + hri_sercomusart_clear_CTRLA_FORM_bf(hw, 1); + } + + hri_sercomusart_write_CTRLB_PMODE_bit(hw, parity); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set stop bits mode + * + * \param[in] device The pointer to USART device instance + * \param[in] stop_bits A stop bits mode to set + */ +static void _usart_set_stop_bits(void *const hw, const enum usart_stop_bits stop_bits) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLB_SBMODE_bit(hw, stop_bits); + CRITICAL_SECTION_LEAVE() + + hri_sercomusart_write_CTRLA_ENABLE_bit(hw, enabled); +} + +/** + * \internal Set character size + * + * \param[in] device The pointer to USART device instance + * \param[in] size A character size to set + */ +static void _usart_set_character_size(void *const hw, const enum usart_character_size size) +{ + bool enabled = hri_sercomusart_get_CTRLA_ENABLE_bit(hw); + + hri_sercomusart_clear_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_ENABLE); + hri_sercomusart_write_CTRLB_CHSIZE_bf(hw, size); + CRITICAL_SECTION_LEAVE() + + if (enabled) { + hri_sercomusart_set_CTRLA_ENABLE_bit(hw); + } +} + + /* Sercom I2C implementation */ + +#ifndef CONF_SERCOM_0_I2CM_ENABLE +#define CONF_SERCOM_0_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_I2CM_ENABLE +#define CONF_SERCOM_1_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_I2CM_ENABLE +#define CONF_SERCOM_2_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_I2CM_ENABLE +#define CONF_SERCOM_3_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_I2CM_ENABLE +#define CONF_SERCOM_4_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_I2CM_ENABLE +#define CONF_SERCOM_5_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_I2CM_ENABLE +#define CONF_SERCOM_6_I2CM_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_I2CM_ENABLE +#define CONF_SERCOM_7_I2CM_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as I2C Master. */ +#define SERCOM_I2CM_AMOUNT \ + (CONF_SERCOM_0_I2CM_ENABLE + CONF_SERCOM_1_I2CM_ENABLE + CONF_SERCOM_2_I2CM_ENABLE + CONF_SERCOM_3_I2CM_ENABLE \ + + CONF_SERCOM_4_I2CM_ENABLE + CONF_SERCOM_5_I2CM_ENABLE + CONF_SERCOM_6_I2CM_ENABLE + CONF_SERCOM_7_I2CM_ENABLE) + +/** + * \brief Macro is used to fill i2cm configuration structure based on + * its number + * + * \param[in] n The number of structures + */ +#define I2CM_CONFIGURATION(n) \ + { \ + (n), \ + (SERCOM_I2CM_CTRLA_MODE_I2C_MASTER) | (CONF_SERCOM_##n##_I2CM_RUNSTDBY << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos) \ + | (CONF_SERCOM_##n##_I2CM_SPEED << SERCOM_I2CM_CTRLA_SPEED_Pos) \ + | (CONF_SERCOM_##n##_I2CM_MEXTTOEN << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos) \ + | (CONF_SERCOM_##n##_I2CM_SEXTTOEN << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos) \ + | (CONF_SERCOM_##n##_I2CM_INACTOUT << SERCOM_I2CM_CTRLA_INACTOUT_Pos) \ + | (CONF_SERCOM_##n##_I2CM_LOWTOUT << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos) \ + | (CONF_SERCOM_##n##_I2CM_SDAHOLD << SERCOM_I2CM_CTRLA_SDAHOLD_Pos), \ + SERCOM_I2CM_CTRLB_SMEN, (uint32_t)(CONF_SERCOM_##n##_I2CM_BAUD_RATE), \ + CONF_SERCOM_##n##_I2CM_DEBUG_STOP_MODE, CONF_SERCOM_##n##_I2CM_TRISE, CONF_GCLK_SERCOM##n##_CORE_FREQUENCY \ + } + +#define ERROR_FLAG (1 << 7) +#define SB_FLAG (1 << 1) +#define MB_FLAG (1 << 0) + +#define CMD_STOP 0x3 +#define I2C_IDLE 0x1 +#define I2C_SM 0x0 +#define I2C_FM 0x1 +#define I2C_HS 0x2 +#define TEN_ADDR_FRAME 0x78 +#define TEN_ADDR_MASK 0x3ff +#define SEVEN_ADDR_MASK 0x7f + +/** + * \brief SERCOM I2CM configuration type + */ +struct i2cm_configuration { + uint8_t number; + hri_sercomi2cm_ctrla_reg_t ctrl_a; + hri_sercomi2cm_ctrlb_reg_t ctrl_b; + hri_sercomi2cm_baud_reg_t baud; + hri_sercomi2cm_dbgctrl_reg_t dbgctrl; + uint16_t trise; + uint32_t clk; /* SERCOM peripheral clock frequency */ +}; + +static inline int32_t _i2c_m_enable_implementation(void *hw); +static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw); + +#if SERCOM_I2CM_AMOUNT < 1 +/** Dummy array to pass compiling. */ +static struct i2cm_configuration _i2cms[1] = {{0}}; +#else +/** + * \brief Array of SERCOM I2CM configurations + */ +static struct i2cm_configuration _i2cms[] = { +#if CONF_SERCOM_0_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(0), +#endif +#if CONF_SERCOM_1_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(1), +#endif +#if CONF_SERCOM_2_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(2), +#endif +#if CONF_SERCOM_3_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(3), +#endif +#if CONF_SERCOM_4_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(4), +#endif +#if CONF_SERCOM_5_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(5), +#endif +#if CONF_SERCOM_6_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(6), +#endif +#if CONF_SERCOM_7_I2CM_ENABLE == 1 + I2CM_CONFIGURATION(7), +#endif +}; +#endif + +/** + * \internal Retrieve ordinal number of the given sercom hardware instance + * + * \param[in] hw The pointer to hardware instance + + * \return The ordinal number of the given sercom hardware instance + */ +static int8_t _get_i2cm_index(const void *const hw) +{ + uint8_t sercom_offset = _sercom_get_hardware_index(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_i2cms); i++) { + if (_i2cms[i].number == sercom_offset) { + return i; + } + } + + ASSERT(false); + return -1; +} + +static inline void _sercom_i2c_send_stop(void *const hw) +{ + hri_sercomi2cm_set_CTRLB_CMD_bf(hw, CMD_STOP); +} + +/** + * \brief SERCOM I2CM analyze hardware status and transfer next byte + */ +static inline int32_t _sercom_i2c_sync_analyse_flags(void *const hw, uint32_t flags, struct _i2c_m_msg *const msg) +{ + int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); + uint16_t status = hri_sercomi2cm_read_STATUS_reg(hw); + + if (flags & MB_FLAG) { + /* tx error */ + if (status & SERCOM_I2CM_STATUS_ARBLOST) { + hri_sercomi2cm_clear_interrupt_MB_bit(hw); + msg->flags |= I2C_M_FAIL; + msg->flags &= ~I2C_M_BUSY; + + if (status & SERCOM_I2CM_STATUS_BUSERR) { + return I2C_ERR_BUS; + } + + return I2C_ERR_BAD_ADDRESS; + } else { + if (status & SERCOM_I2CM_STATUS_RXNACK) { + + /* Slave rejects to receive more data */ + if (msg->len > 0) { + msg->flags |= I2C_M_FAIL; + } + + if (msg->flags & I2C_M_STOP) { + _sercom_i2c_send_stop(hw); + } + + msg->flags &= ~I2C_M_BUSY; + + return I2C_NACK; + } + + if (msg->flags & I2C_M_TEN) { + hri_sercomi2cm_write_ADDR_reg(hw, + ((((msg->addr & TEN_ADDR_MASK) >> 8) | TEN_ADDR_FRAME) << 1) | I2C_M_RD + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + msg->flags &= ~I2C_M_TEN; + + return I2C_OK; + } + + if (msg->len == 0) { + if (msg->flags & I2C_M_STOP) { + _sercom_i2c_send_stop(hw); + } + + msg->flags &= ~I2C_M_BUSY; + } else { + hri_sercomi2cm_write_DATA_reg(hw, *msg->buffer); + msg->buffer++; + msg->len--; + } + + return I2C_OK; + } + } else if (flags & SB_FLAG) { + if ((msg->len) && !(status & SERCOM_I2CM_STATUS_RXNACK)) { + msg->len--; + + /* last byte, send nack */ + if ((msg->len == 0 && !sclsm) || (msg->len == 1 && sclsm)) { + hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); + } + + if (msg->len == 0) { + if (msg->flags & I2C_M_STOP) { + hri_sercomi2cm_clear_CTRLB_SMEN_bit(hw); + _sercom_i2c_send_stop(hw); + } + + msg->flags &= ~I2C_M_BUSY; + } + + /* Accessing DATA.DATA auto-triggers I2C bus operations. + * The operation performed depends on the state of + * CTRLB.ACKACT, CTRLB.SMEN + **/ + *msg->buffer++ = hri_sercomi2cm_read_DATA_reg(hw); + } else { + hri_sercomi2cm_clear_interrupt_SB_bit(hw); + return I2C_NACK; + } + + hri_sercomi2cm_clear_interrupt_SB_bit(hw); + } + + return I2C_OK; +} + +/** + * \brief Enable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + return _i2c_m_enable_implementation(i2c_dev->hw); +} + +/** + * \brief Disable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(hw)); + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** + * \brief Set baudrate of master + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] clkrate The clock rate of i2c master, in KHz + * \param[in] baudrate The baud rate desired for i2c master, in KHz + */ +int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate) +{ + uint32_t tmp; + void * hw = i2c_dev->hw; + + if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + + tmp = _get_i2cm_index(hw); + clkrate = _i2cms[tmp].clk / 1000; + + if (i2c_dev->service.mode == I2C_STANDARD_MODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_FASTMODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) { + tmp = (clkrate - 2 * baudrate) / (2 * baudrate); + hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp); + } else { + /* error baudrate */ + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} + +/** + * \brief Retrieve IRQ number for the given hardware instance + */ +static uint8_t _sercom_get_irq_num(const void *const hw) +{ + return SERCOM0_0_IRQn + (_sercom_get_hardware_index(hw) << 2); +} + +/** + * \brief Initialize sercom i2c module to use in async mode + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw) +{ + int32_t init_status; + + ASSERT(i2c_dev); + + i2c_dev->hw = hw; + + init_status = _i2c_m_sync_init_impl(&i2c_dev->service, hw); + if (init_status) { + return init_status; + } + + _sercom_init_irq_param(hw, (void *)i2c_dev); + uint8_t irq = _sercom_get_irq_num(hw); + for (uint32_t i = 0; i < 4; i++) { + NVIC_DisableIRQ((IRQn_Type)irq); + NVIC_ClearPendingIRQ((IRQn_Type)irq); + NVIC_EnableIRQ((IRQn_Type)irq); + irq++; + } + return ERR_NONE; +} + +/** + * \brief Deinitialize sercom i2c module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(i2c_dev->hw); + hri_sercomi2cm_set_CTRLA_SWRST_bit(i2c_dev->hw); + + return ERR_NONE; +} + +/** + * \brief Transfer the slave address to bus, which will start the transfer + * + * \param[in] i2c_dev The pointer to i2c device + */ +static int32_t _sercom_i2c_send_address(struct _i2c_m_async_device *const i2c_dev) +{ + void * hw = i2c_dev->hw; + struct _i2c_m_msg *msg = &i2c_dev->service.msg; + int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); + + ASSERT(i2c_dev); + + if (msg->len == 1 && sclsm) { + hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); + } else { + hri_sercomi2cm_clear_CTRLB_ACKACT_bit(hw); + } + + /* ten bit address */ + if (msg->addr & I2C_M_TEN) { + if (msg->flags & I2C_M_RD) { + msg->flags |= I2C_M_TEN; + } + + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } else { + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0) + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } + + return ERR_NONE; +} + +/** + * \brief Transfer data specified by msg + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] msg The pointer to i2c message + * + * \return Transfer status. + * \retval 0 Transfer success + * \retval <0 Transfer fail, return the error code + */ +int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *i2c_dev, struct _i2c_m_msg *msg) +{ + int ret; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + ASSERT(msg); + + if (msg->len == 0) { + return ERR_NONE; + } + + if (i2c_dev->service.msg.flags & I2C_M_BUSY) { + return ERR_BUSY; + } + + msg->flags |= I2C_M_BUSY; + i2c_dev->service.msg = *msg; + hri_sercomi2cm_set_CTRLB_SMEN_bit(i2c_dev->hw); + + ret = _sercom_i2c_send_address(i2c_dev); + + if (ret) { + i2c_dev->service.msg.flags &= ~I2C_M_BUSY; + + return ret; + } + + return ERR_NONE; +} + +/** + * \brief Set callback to be called in interrupt handler + * + * \param[in] i2c_dev The pointer to master i2c device + * \param[in] type The callback type + * \param[in] func The callback function pointer + */ +int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *const i2c_dev, enum _i2c_m_async_callback_type type, + FUNC_PTR func) +{ + switch (type) { + case I2C_M_ASYNC_DEVICE_ERROR: + i2c_dev->cb.error = (_i2c_error_cb_t)func; + break; + case I2C_M_ASYNC_DEVICE_TX_COMPLETE: + i2c_dev->cb.tx_complete = (_i2c_complete_cb_t)func; + break; + case I2C_M_ASYNC_DEVICE_RX_COMPLETE: + i2c_dev->cb.rx_complete = (_i2c_complete_cb_t)func; + break; + default: + /* error */ + break; + } + + return ERR_NONE; +} + +/** + * \brief Set stop condition on I2C + * + * \param i2c_dev Pointer to master i2c device + * + * \return Operation status + * \retval I2C_OK Operation was successfull + */ +int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + _sercom_i2c_send_stop(hw); + + return I2C_OK; +} + +/** + * \brief Get number of bytes left in transfer buffer + * + * \param i2c_dev Pointer to i2c master device + * + * \return Bytes left in buffer + * \retval =>0 Bytes left in buffer + */ +int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev) +{ + if (i2c_dev->service.msg.flags & I2C_M_BUSY) { + return i2c_dev->service.msg.len; + } + + return 0; +} + +/** + * \brief Initialize sercom i2c module to use in sync mode + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw) +{ + ASSERT(i2c_dev); + + i2c_dev->hw = hw; + + return _i2c_m_sync_init_impl(&i2c_dev->service, hw); +} + +/** + * \brief Deinitialize sercom i2c module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(i2c_dev->hw); + hri_sercomi2cm_set_CTRLA_SWRST_bit(i2c_dev->hw); + + return ERR_NONE; +} + +/** + * \brief Enable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev) +{ + ASSERT(i2c_dev); + + return _i2c_m_enable_implementation(i2c_dev->hw); +} + +/** + * \brief Disable the i2c master module + * + * \param[in] i2c_dev The pointer to i2c device + */ +int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** + * \brief Set baudrate of master + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] clkrate The clock rate of i2c master, in KHz + * \param[in] baudrate The baud rate desired for i2c master, in KHz + */ +int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate) +{ + uint32_t tmp; + void * hw = i2c_dev->hw; + + if (hri_sercomi2cm_get_CTRLA_ENABLE_bit(hw)) { + return ERR_DENIED; + } + + tmp = _get_i2cm_index(hw); + clkrate = _i2cms[tmp].clk / 1000; + + if (i2c_dev->service.mode == I2C_STANDARD_MODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_FASTMODE) { + tmp = (uint32_t)((clkrate - 10 * baudrate - baudrate * clkrate * (i2c_dev->service.trise * 0.000000001)) + / (2 * baudrate)); + hri_sercomi2cm_write_BAUD_BAUD_bf(hw, tmp); + } else if (i2c_dev->service.mode == I2C_HIGHSPEED_MODE) { + tmp = (clkrate - 2 * baudrate) / (2 * baudrate); + hri_sercomi2cm_write_BAUD_HSBAUD_bf(hw, tmp); + } else { + /* error baudrate */ + return ERR_INVALID_ARG; + } + + return ERR_NONE; +} + +/** + * \brief Enable/disable I2C master interrupt + */ +void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type, + const bool state) +{ + if (I2C_M_ASYNC_DEVICE_TX_COMPLETE == type || I2C_M_ASYNC_DEVICE_RX_COMPLETE == type) { + hri_sercomi2cm_write_INTEN_SB_bit(device->hw, state); + hri_sercomi2cm_write_INTEN_MB_bit(device->hw, state); + } else if (I2C_M_ASYNC_DEVICE_ERROR == type) { + hri_sercomi2cm_write_INTEN_ERROR_bit(device->hw, state); + } +} + +/** + * \brief Wait for bus response + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] flags Store the hardware response + * + * \return Bus response status. + * \retval 0 Bus response status OK + * \retval <0 Bus response fail + */ +inline static int32_t _sercom_i2c_sync_wait_bus(struct _i2c_m_sync_device *const i2c_dev, uint32_t *flags) +{ + uint32_t timeout = 65535; + void * hw = i2c_dev->hw; + + do { + *flags = hri_sercomi2cm_read_INTFLAG_reg(hw); + + if (timeout-- == 0) { + return I2C_ERR_BUS; + } + } while (!(*flags & MB_FLAG) && !(*flags & SB_FLAG)); + + return I2C_OK; +} + +/** + * \brief Send the slave address to bus, which will start the transfer + * + * \param[in] i2c_dev The pointer to i2c device + */ +static int32_t _sercom_i2c_sync_send_address(struct _i2c_m_sync_device *const i2c_dev) +{ + void * hw = i2c_dev->hw; + struct _i2c_m_msg *msg = &i2c_dev->service.msg; + int sclsm = hri_sercomi2cm_get_CTRLA_SCLSM_bit(hw); + uint32_t flags; + + ASSERT(i2c_dev); + + if (msg->len == 1 && sclsm) { + hri_sercomi2cm_set_CTRLB_ACKACT_bit(hw); + } else { + hri_sercomi2cm_clear_CTRLB_ACKACT_bit(hw); + } + + /* ten bit address */ + if (msg->addr & I2C_M_TEN) { + if (msg->flags & I2C_M_RD) { + msg->flags |= I2C_M_TEN; + } + + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & TEN_ADDR_MASK) << 1) | SERCOM_I2CM_ADDR_TENBITEN + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } else { + hri_sercomi2cm_write_ADDR_reg(hw, + ((msg->addr & SEVEN_ADDR_MASK) << 1) | (msg->flags & I2C_M_RD ? I2C_M_RD : 0x0) + | (hri_sercomi2cm_read_ADDR_reg(hw) & SERCOM_I2CM_ADDR_HS)); + } + + _sercom_i2c_sync_wait_bus(i2c_dev, &flags); + return _sercom_i2c_sync_analyse_flags(hw, flags, msg); +} + +/** + * \brief Transfer data specified by msg + * + * \param[in] i2c_dev The pointer to i2c device + * \param[in] msg The pointer to i2c message + * + * \return Transfer status. + * \retval 0 Transfer success + * \retval <0 Transfer fail or partial fail, return the error code + */ +int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg) +{ + uint32_t flags; + int ret; + void * hw = i2c_dev->hw; + + ASSERT(i2c_dev); + ASSERT(i2c_dev->hw); + ASSERT(msg); + + if (i2c_dev->service.msg.flags & I2C_M_BUSY) { + return I2C_ERR_BUSY; + } + + msg->flags |= I2C_M_BUSY; + i2c_dev->service.msg = *msg; + hri_sercomi2cm_set_CTRLB_SMEN_bit(hw); + + ret = _sercom_i2c_sync_send_address(i2c_dev); + + if (ret) { + i2c_dev->service.msg.flags &= ~I2C_M_BUSY; + + return ret; + } + + while (i2c_dev->service.msg.flags & I2C_M_BUSY) { + ret = _sercom_i2c_sync_wait_bus(i2c_dev, &flags); + + if (ret) { + if (msg->flags & I2C_M_STOP) { + _sercom_i2c_send_stop(hw); + } + + i2c_dev->service.msg.flags &= ~I2C_M_BUSY; + + return ret; + } + + ret = _sercom_i2c_sync_analyse_flags(hw, flags, &i2c_dev->service.msg); + } + + return ret; +} + +int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev) +{ + void *hw = i2c_dev->hw; + + _sercom_i2c_send_stop(hw); + + return I2C_OK; +} + +static inline int32_t _i2c_m_enable_implementation(void *const hw) +{ + int timeout = 65535; + int timeout_attempt = 4; + + ASSERT(hw); + + /* Enable interrupts */ + hri_sercomi2cm_set_CTRLA_ENABLE_bit(hw); + + while (hri_sercomi2cm_read_STATUS_BUSSTATE_bf(hw) != I2C_IDLE) { + timeout--; + + if (timeout <= 0) { + if (--timeout_attempt) + timeout = 65535; + else + return I2C_ERR_BUSY; + hri_sercomi2cm_clear_STATUS_reg(hw, SERCOM_I2CM_STATUS_BUSSTATE(I2C_IDLE)); + } + } + return ERR_NONE; +} + +static int32_t _i2c_m_sync_init_impl(struct _i2c_m_service *const service, void *const hw) +{ + uint8_t i = _get_i2cm_index(hw); + + if (!hri_sercomi2cm_is_syncing(hw, SERCOM_I2CM_SYNCBUSY_SWRST)) { + uint32_t mode = _i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_MODE_Msk; + if (hri_sercomi2cm_get_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_ENABLE)) { + hri_sercomi2cm_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_ENABLE); + } + hri_sercomi2cm_write_CTRLA_reg(hw, SERCOM_I2CM_CTRLA_SWRST | mode); + } + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); + + hri_sercomi2cm_write_CTRLA_reg(hw, _i2cms[i].ctrl_a); + hri_sercomi2cm_write_CTRLB_reg(hw, _i2cms[i].ctrl_b); + hri_sercomi2cm_write_BAUD_reg(hw, _i2cms[i].baud); + + service->mode = (_i2cms[i].ctrl_a & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos; + hri_sercomi2cm_write_ADDR_HS_bit(hw, service->mode < I2C_HS ? 0 : 1); + + service->trise = _i2cms[i].trise; + + return ERR_NONE; +} + + /* SERCOM I2C slave */ + +#ifndef CONF_SERCOM_0_I2CS_ENABLE +#define CONF_SERCOM_0_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_I2CS_ENABLE +#define CONF_SERCOM_1_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_I2CS_ENABLE +#define CONF_SERCOM_2_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_I2CS_ENABLE +#define CONF_SERCOM_3_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_I2CS_ENABLE +#define CONF_SERCOM_4_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_I2CS_ENABLE +#define CONF_SERCOM_5_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_I2CS_ENABLE +#define CONF_SERCOM_6_I2CS_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_I2CS_ENABLE +#define CONF_SERCOM_7_I2CS_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as I2C Slave. */ +#define SERCOM_I2CS_AMOUNT \ + (CONF_SERCOM_0_I2CS_ENABLE + CONF_SERCOM_1_I2CS_ENABLE + CONF_SERCOM_2_I2CS_ENABLE + CONF_SERCOM_3_I2CS_ENABLE \ + + CONF_SERCOM_4_I2CS_ENABLE + CONF_SERCOM_5_I2CS_ENABLE + CONF_SERCOM_6_I2CS_ENABLE + CONF_SERCOM_7_I2CS_ENABLE) + +/** + * \brief Macro is used to fill I2C slave configuration structure based on + * its number + * + * \param[in] n The number of structures + */ +#define I2CS_CONFIGURATION(n) \ + { \ + n, \ + SERCOM_I2CM_CTRLA_MODE_I2C_SLAVE | (CONF_SERCOM_##n##_I2CS_RUNSTDBY << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos) \ + | SERCOM_I2CS_CTRLA_SDAHOLD(CONF_SERCOM_##n##_I2CS_SDAHOLD) \ + | (CONF_SERCOM_##n##_I2CS_SEXTTOEN << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos) \ + | (CONF_SERCOM_##n##_I2CS_SPEED << SERCOM_I2CS_CTRLA_SPEED_Pos) \ + | (CONF_SERCOM_##n##_I2CS_SCLSM << SERCOM_I2CS_CTRLA_SCLSM_Pos) \ + | (CONF_SERCOM_##n##_I2CS_LOWTOUT << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos), \ + SERCOM_I2CS_CTRLB_SMEN | SERCOM_I2CS_CTRLB_AACKEN | SERCOM_I2CS_CTRLB_AMODE(CONF_SERCOM_##n##_I2CS_AMODE), \ + (CONF_SERCOM_##n##_I2CS_GENCEN << SERCOM_I2CS_ADDR_GENCEN_Pos) \ + | SERCOM_I2CS_ADDR_ADDR(CONF_SERCOM_##n##_I2CS_ADDRESS) \ + | (CONF_SERCOM_##n##_I2CS_TENBITEN << SERCOM_I2CS_ADDR_TENBITEN_Pos) \ + | SERCOM_I2CS_ADDR_ADDRMASK(CONF_SERCOM_##n##_I2CS_ADDRESS_MASK) \ + } + +/** + * \brief Macro to check 10-bit addressing + */ +#define I2CS_7BIT_ADDRESSING_MASK 0x7F + +static int32_t _i2c_s_init(void *const hw); +static int8_t _get_i2c_s_index(const void *const hw); +static inline void _i2c_s_deinit(void *const hw); +static int32_t _i2c_s_set_address(void *const hw, const uint16_t address); + +/** + * \brief SERCOM I2C slave configuration type + */ +struct i2cs_configuration { + uint8_t number; + hri_sercomi2cs_ctrla_reg_t ctrl_a; + hri_sercomi2cs_ctrlb_reg_t ctrl_b; + hri_sercomi2cs_addr_reg_t address; +}; + +#if SERCOM_I2CS_AMOUNT < 1 +/** Dummy array for compiling. */ +static struct i2cs_configuration _i2css[1] = {{0}}; +#else +/** + * \brief Array of SERCOM I2C slave configurations + */ +static struct i2cs_configuration _i2css[] = { +#if CONF_SERCOM_0_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(0), +#endif +#if CONF_SERCOM_1_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(1), +#endif +#if CONF_SERCOM_2_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(2), +#endif +#if CONF_SERCOM_3_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(3), +#endif +#if CONF_SERCOM_4_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(4), +#endif +#if CONF_SERCOM_5_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(5), +#endif +#if CONF_SERCOM_6_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(6), +#endif +#if CONF_SERCOM_7_I2CS_ENABLE == 1 + I2CS_CONFIGURATION(7), +#endif +}; +#endif + +/** + * \brief Initialize synchronous I2C slave + */ +int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw) +{ + int32_t status; + + ASSERT(device); + + status = _i2c_s_init(hw); + if (status) { + return status; + } + device->hw = hw; + + return ERR_NONE; +} + +/** + * \brief Initialize asynchronous I2C slave + */ +int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw) +{ + int32_t init_status; + + ASSERT(device); + + init_status = _i2c_s_init(hw); + if (init_status) { + return init_status; + } + + device->hw = hw; + _sercom_init_irq_param(hw, (void *)device); + uint8_t irq = _sercom_get_irq_num(hw); + for (uint32_t i = 0; i < 4; i++) { + NVIC_DisableIRQ((IRQn_Type)irq); + NVIC_ClearPendingIRQ((IRQn_Type)irq); + NVIC_EnableIRQ((IRQn_Type)irq); + irq++; + } + // Enable Address Match and PREC interrupt by default. + hri_sercomi2cs_set_INTEN_AMATCH_bit(hw); + hri_sercomi2cs_set_INTEN_PREC_bit(hw); + + return ERR_NONE; +} + +/** + * \brief Deinitialize synchronous I2C + */ +int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device) +{ + _i2c_s_deinit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Deinitialize asynchronous I2C + */ +int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(device->hw)); + _i2c_s_deinit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Enable I2C module + */ +int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device) +{ + hri_sercomi2cs_set_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Enable I2C module + */ +int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device) +{ + hri_sercomi2cs_set_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Disable I2C module + */ +int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device) +{ + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Disable I2C module + */ +int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device) +{ + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Check if 10-bit addressing mode is on + */ +int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_get_ADDR_TENBITEN_bit(device->hw); +} + +/** + * \brief Check if 10-bit addressing mode is on + */ +int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device) +{ + return hri_sercomi2cs_get_ADDR_TENBITEN_bit(device->hw); +} + +/** + * \brief Set I2C slave address + */ +int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address) +{ + return _i2c_s_set_address(device->hw, address); +} + +/** + * \brief Set I2C slave address + */ +int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address) +{ + return _i2c_s_set_address(device->hw, address); +} + +/** + * \brief Write a byte to the given I2C instance + */ +void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data) +{ + hri_sercomi2cs_write_DATA_reg(device->hw, data); +} + +/** + * \brief Write a byte to the given I2C instance + */ +void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data) +{ + hri_sercomi2cs_write_DATA_reg(device->hw, data); +} + +/** + * \brief Read a byte from the given I2C instance + */ +uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_read_DATA_reg(device->hw); +} + +/** + * \brief Check if I2C is ready to send next byt + */ +bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_get_interrupt_DRDY_bit(device->hw); +} + +/** + * \brief Check if there is data received by I2C + */ +bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_get_interrupt_DRDY_bit(device->hw); +} + +/** + * \brief Retrieve I2C slave status + */ +i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device) +{ + return hri_sercomi2cs_read_STATUS_reg(device->hw); +} + +/** + * \brief Clear the Data Ready interrupt flag + */ +int32_t _i2c_s_sync_clear_data_ready_flag(const struct _i2c_s_sync_device *const device) +{ + hri_sercomi2cs_clear_INTFLAG_DRDY_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Retrieve I2C slave status + */ +i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device) +{ + return hri_sercomi2cs_read_STATUS_reg(device->hw); +} + +/** + * \brief Abort data transmission + */ +int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device) +{ + hri_sercomi2cs_clear_INTEN_DRDY_bit(device->hw); + + return ERR_NONE; +} + +/** + * \brief Enable/disable I2C slave interrupt + */ +int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type, + const bool state) +{ + ASSERT(device); + + if (I2C_S_DEVICE_TX == type || I2C_S_DEVICE_RX_COMPLETE == type) { + hri_sercomi2cs_write_INTEN_DRDY_bit(device->hw, state); + } else if (I2C_S_DEVICE_ERROR == type) { + hri_sercomi2cs_write_INTEN_ERROR_bit(device->hw, state); + } + + return ERR_NONE; +} + +/** + * \internal Initalize i2c slave hardware + * + * \param[in] p The pointer to hardware instance + * + *\ return status of initialization + */ +static int32_t _i2c_s_init(void *const hw) +{ + int8_t i = _get_i2c_s_index(hw); + if (i == -1) { + return ERR_INVALID_ARG; + } + + if (!hri_sercomi2cs_is_syncing(hw, SERCOM_I2CS_CTRLA_SWRST)) { + uint32_t mode = _i2css[i].ctrl_a & SERCOM_I2CS_CTRLA_MODE_Msk; + if (hri_sercomi2cs_get_CTRLA_reg(hw, SERCOM_I2CS_CTRLA_ENABLE)) { + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_ENABLE); + } + hri_sercomi2cs_write_CTRLA_reg(hw, SERCOM_I2CS_CTRLA_SWRST | mode); + } + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); + + hri_sercomi2cs_write_CTRLA_reg(hw, _i2css[i].ctrl_a); + hri_sercomi2cs_write_CTRLB_reg(hw, _i2css[i].ctrl_b); + hri_sercomi2cs_write_ADDR_reg(hw, _i2css[i].address); + + return ERR_NONE; +} + +/** + * \internal Retrieve ordinal number of the given sercom hardware instance + * + * \param[in] hw The pointer to hardware instance + * + * \return The ordinal number of the given sercom hardware instance + */ +static int8_t _get_i2c_s_index(const void *const hw) +{ + uint8_t sercom_offset = _sercom_get_hardware_index(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_i2css); i++) { + if (_i2css[i].number == sercom_offset) { + return i; + } + } + + ASSERT(false); + return -1; +} + +/** + * \internal De-initialize i2c slave + * + * \param[in] hw The pointer to hardware instance + */ +static inline void _i2c_s_deinit(void *const hw) +{ + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cs_set_CTRLA_SWRST_bit(hw); +} + +/** + * \internal De-initialize i2c slave + * + * \param[in] hw The pointer to hardware instance + * \param[in] address Address to set + */ +static int32_t _i2c_s_set_address(void *const hw, const uint16_t address) +{ + bool enabled; + + enabled = hri_sercomi2cs_get_CTRLA_ENABLE_bit(hw); + + CRITICAL_SECTION_ENTER() + hri_sercomi2cs_clear_CTRLA_ENABLE_bit(hw); + hri_sercomi2cs_write_ADDR_ADDR_bf(hw, address); + CRITICAL_SECTION_LEAVE() + + if (enabled) { + hri_sercomi2cs_set_CTRLA_ENABLE_bit(hw); + } + + return ERR_NONE; +} + + /* Sercom SPI implementation */ + +#ifndef SERCOM_USART_CTRLA_MODE_SPI_SLAVE +#define SERCOM_USART_CTRLA_MODE_SPI_SLAVE (2 << 2) +#endif + +#define SPI_DEV_IRQ_MODE 0x8000 + +#define _SPI_CS_PORT_EXTRACT(cs) (((cs) >> 0) & 0xFF) +#define _SPI_CS_PIN_EXTRACT(cs) (((cs) >> 8) & 0xFF) + +COMPILER_PACK_SET(1) +/** Initialization configuration of registers. */ +struct sercomspi_regs_cfg { + uint32_t ctrla; + uint32_t ctrlb; + uint32_t addr; + uint8_t baud; + uint8_t dbgctrl; + uint16_t dummy_byte; + uint8_t n; +}; +COMPILER_PACK_RESET() + +/** Build configuration from header macros. */ +#define SERCOMSPI_REGS(n) \ + { \ + (((CONF_SERCOM_##n##_SPI_DORD) << SERCOM_SPI_CTRLA_DORD_Pos) \ + | (CONF_SERCOM_##n##_SPI_CPOL << SERCOM_SPI_CTRLA_CPOL_Pos) \ + | (CONF_SERCOM_##n##_SPI_CPHA << SERCOM_SPI_CTRLA_CPHA_Pos) \ + | (CONF_SERCOM_##n##_SPI_AMODE_EN ? SERCOM_SPI_CTRLA_FORM(2) : SERCOM_SPI_CTRLA_FORM(0)) \ + | SERCOM_SPI_CTRLA_DOPO(CONF_SERCOM_##n##_SPI_TXPO) | SERCOM_SPI_CTRLA_DIPO(CONF_SERCOM_##n##_SPI_RXPO) \ + | (CONF_SERCOM_##n##_SPI_IBON << SERCOM_SPI_CTRLA_IBON_Pos) \ + | (CONF_SERCOM_##n##_SPI_RUNSTDBY << SERCOM_SPI_CTRLA_RUNSTDBY_Pos) \ + | SERCOM_SPI_CTRLA_MODE(CONF_SERCOM_##n##_SPI_MODE)), /* ctrla */ \ + ((CONF_SERCOM_##n##_SPI_RXEN << SERCOM_SPI_CTRLB_RXEN_Pos) \ + | (CONF_SERCOM_##n##_SPI_MSSEN << SERCOM_SPI_CTRLB_MSSEN_Pos) \ + | (CONF_SERCOM_##n##_SPI_SSDE << SERCOM_SPI_CTRLB_SSDE_Pos) \ + | (CONF_SERCOM_##n##_SPI_PLOADEN << SERCOM_SPI_CTRLB_PLOADEN_Pos) \ + | SERCOM_SPI_CTRLB_AMODE(CONF_SERCOM_##n##_SPI_AMODE) \ + | SERCOM_SPI_CTRLB_CHSIZE(CONF_SERCOM_##n##_SPI_CHSIZE)), /* ctrlb */ \ + (SERCOM_SPI_ADDR_ADDR(CONF_SERCOM_##n##_SPI_ADDR) \ + | SERCOM_SPI_ADDR_ADDRMASK(CONF_SERCOM_##n##_SPI_ADDRMASK)), /* addr */ \ + ((uint8_t)CONF_SERCOM_##n##_SPI_BAUD_RATE), /* baud */ \ + (CONF_SERCOM_##n##_SPI_DBGSTOP << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos), /* dbgctrl */ \ + CONF_SERCOM_##n##_SPI_DUMMYBYTE, /* Dummy byte for SPI master mode */ \ + n /* sercom number */ \ + } + +#ifndef CONF_SERCOM_0_SPI_ENABLE +#define CONF_SERCOM_0_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_1_SPI_ENABLE +#define CONF_SERCOM_1_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_2_SPI_ENABLE +#define CONF_SERCOM_2_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_3_SPI_ENABLE +#define CONF_SERCOM_3_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_4_SPI_ENABLE +#define CONF_SERCOM_4_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_5_SPI_ENABLE +#define CONF_SERCOM_5_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_6_SPI_ENABLE +#define CONF_SERCOM_6_SPI_ENABLE 0 +#endif +#ifndef CONF_SERCOM_7_SPI_ENABLE +#define CONF_SERCOM_7_SPI_ENABLE 0 +#endif + +/** Amount of SERCOM that is used as SPI */ +#define SERCOM_SPI_AMOUNT \ + (CONF_SERCOM_0_SPI_ENABLE + CONF_SERCOM_1_SPI_ENABLE + CONF_SERCOM_2_SPI_ENABLE + CONF_SERCOM_3_SPI_ENABLE \ + + CONF_SERCOM_4_SPI_ENABLE + CONF_SERCOM_5_SPI_ENABLE + CONF_SERCOM_6_SPI_ENABLE + CONF_SERCOM_7_SPI_ENABLE) + +#if SERCOM_SPI_AMOUNT < 1 +/** Dummy array for compiling. */ +static const struct sercomspi_regs_cfg sercomspi_regs[1] = {{0}}; +#else +/** The SERCOM SPI configurations of SERCOM that is used as SPI. */ +static const struct sercomspi_regs_cfg sercomspi_regs[] = { +#if CONF_SERCOM_0_SPI_ENABLE + SERCOMSPI_REGS(0), +#endif +#if CONF_SERCOM_1_SPI_ENABLE + SERCOMSPI_REGS(1), +#endif +#if CONF_SERCOM_2_SPI_ENABLE + SERCOMSPI_REGS(2), +#endif +#if CONF_SERCOM_3_SPI_ENABLE + SERCOMSPI_REGS(3), +#endif +#if CONF_SERCOM_4_SPI_ENABLE + SERCOMSPI_REGS(4), +#endif +#if CONF_SERCOM_5_SPI_ENABLE + SERCOMSPI_REGS(5), +#endif +#if CONF_SERCOM_6_SPI_ENABLE + SERCOMSPI_REGS(6), +#endif +#if CONF_SERCOM_7_SPI_ENABLE + SERCOMSPI_REGS(7), +#endif +}; +#endif + +/** \internal De-initialize SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return De-initialization status + */ +static int32_t _spi_deinit(void *const hw) +{ + hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); + hri_sercomspi_set_CTRLA_SWRST_bit(hw); + + return ERR_NONE; +} + +/** \internal Enable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Enabling status + */ +static int32_t _spi_sync_enable(void *const hw) +{ + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + + hri_sercomspi_set_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** \internal Enable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Enabling status + */ +static int32_t _spi_async_enable(void *const hw) +{ + _spi_sync_enable(hw); + uint8_t irq = _sercom_get_irq_num(hw); + for (uint32_t i = 0; i < 4; i++) { + NVIC_EnableIRQ((IRQn_Type)irq++); + } + + return ERR_NONE; +} + +/** \internal Disable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Disabling status + */ +static int32_t _spi_sync_disable(void *const hw) +{ + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); + + return ERR_NONE; +} + +/** \internal Disable SERCOM SPI + * + * \param[in] hw Pointer to the hardware register base. + * + * \return Disabling status + */ +static int32_t _spi_async_disable(void *const hw) +{ + _spi_sync_disable(hw); + hri_sercomspi_clear_INTEN_reg( + hw, SERCOM_SPI_INTFLAG_ERROR | SERCOM_SPI_INTFLAG_RXC | SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE); + uint8_t irq = _sercom_get_irq_num(hw); + for (uint32_t i = 0; i < 4; i++) { + NVIC_DisableIRQ((IRQn_Type)irq++); + } + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI mode + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] mode The mode to set + * + * \return Setting mode status + */ +static int32_t _spi_set_mode(void *const hw, const enum spi_transfer_mode mode) +{ + uint32_t ctrla; + + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE)) { + return ERR_BUSY; + } + + ctrla = hri_sercomspi_read_CTRLA_reg(hw); + ctrla &= ~(SERCOM_SPI_CTRLA_CPOL | SERCOM_SPI_CTRLA_CPHA); + ctrla |= (mode & 0x3u) << SERCOM_SPI_CTRLA_CPHA_Pos; + hri_sercomspi_write_CTRLA_reg(hw, ctrla); + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI baudrate + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] baud_val The baudrate to set + * + * \return Setting baudrate status + */ +static int32_t _spi_set_baudrate(void *const hw, const uint32_t baud_val) +{ + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + + hri_sercomspi_write_BAUD_reg(hw, baud_val); + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI char size + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] baud_val The baudrate to set + * \param[out] size Stored char size + * + * \return Setting char size status + */ +static int32_t _spi_set_char_size(void *const hw, const enum spi_char_size char_size, uint8_t *const size) +{ + /* Only 8-bit or 9-bit accepted */ + if (!(char_size == SPI_CHAR_SIZE_8 || char_size == SPI_CHAR_SIZE_9)) { + return ERR_INVALID_ARG; + } + + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_CTRLB)) { + return ERR_BUSY; + } + + hri_sercomspi_write_CTRLB_CHSIZE_bf(hw, char_size); + *size = (char_size == SPI_CHAR_SIZE_8) ? 1 : 2; + + return ERR_NONE; +} + +/** \internal Set SERCOM SPI data order + * + * \param[in] hw Pointer to the hardware register base. + * \param[in] baud_val The baudrate to set + * + * \return Setting data order status + */ +static int32_t _spi_set_data_order(void *const hw, const enum spi_data_order dord) +{ + uint32_t ctrla; + + if (hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + return ERR_BUSY; + } + + ctrla = hri_sercomspi_read_CTRLA_reg(hw); + + if (dord == SPI_DATA_ORDER_LSB_1ST) { + ctrla |= SERCOM_SPI_CTRLA_DORD; + } else { + ctrla &= ~SERCOM_SPI_CTRLA_DORD; + } + hri_sercomspi_write_CTRLA_reg(hw, ctrla); + + return ERR_NONE; +} + +/** \brief Load SERCOM registers to init for SPI master mode + * The settings will be applied with default master mode, unsupported things + * are ignored. + * \param[in, out] hw Pointer to the hardware register base. + * \param[in] regs Pointer to register configuration values. + */ +static inline void _spi_load_regs_master(void *const hw, const struct sercomspi_regs_cfg *regs) +{ + ASSERT(hw && regs); + hri_sercomspi_write_CTRLA_reg( + hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST)); + hri_sercomspi_write_CTRLB_reg( + hw, + (regs->ctrlb + & ~(SERCOM_SPI_CTRLB_MSSEN | SERCOM_SPI_CTRLB_AMODE_Msk | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN)) + | (SERCOM_SPI_CTRLB_RXEN)); + hri_sercomspi_write_BAUD_reg(hw, regs->baud); + hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl); +} + +/** \brief Load SERCOM registers to init for SPI slave mode + * The settings will be applied with default slave mode, unsupported things + * are ignored. + * \param[in, out] hw Pointer to the hardware register base. + * \param[in] regs Pointer to register configuration values. + */ +static inline void _spi_load_regs_slave(void *const hw, const struct sercomspi_regs_cfg *regs) +{ + ASSERT(hw && regs); + hri_sercomspi_write_CTRLA_reg( + hw, regs->ctrla & ~(SERCOM_SPI_CTRLA_IBON | SERCOM_SPI_CTRLA_ENABLE | SERCOM_SPI_CTRLA_SWRST)); + hri_sercomspi_write_CTRLB_reg(hw, + (regs->ctrlb & ~(SERCOM_SPI_CTRLB_MSSEN)) + | (SERCOM_SPI_CTRLB_RXEN | SERCOM_SPI_CTRLB_SSDE | SERCOM_SPI_CTRLB_PLOADEN)); + hri_sercomspi_write_ADDR_reg(hw, regs->addr); + hri_sercomspi_write_DBGCTRL_reg(hw, regs->dbgctrl); + while (hri_sercomspi_is_syncing(hw, 0xFFFFFFFF)) + ; +} + +/** \brief Return the pointer to register settings of specific SERCOM + * \param[in] hw_addr The hardware register base address. + * \return Pointer to register settings of specific SERCOM. + */ +static inline const struct sercomspi_regs_cfg *_spi_get_regs(const uint32_t hw_addr) +{ + uint8_t n = _sercom_get_hardware_index((const void *)hw_addr); + uint8_t i; + + for (i = 0; i < sizeof(sercomspi_regs) / sizeof(struct sercomspi_regs_cfg); i++) { + if (sercomspi_regs[i].n == n) { + return &sercomspi_regs[i]; + } + } + + return NULL; +} + +/** + * \internal Sercom interrupt handler + */ +void SERCOM0_0_Handler(void) +{ + _sercom_usart_interrupt_handler(_sercom0_dev); +} +/** + * \internal Sercom interrupt handler + */ +void SERCOM0_1_Handler(void) +{ + _sercom_usart_interrupt_handler(_sercom0_dev); +} +/** + * \internal Sercom interrupt handler + */ +void SERCOM0_2_Handler(void) +{ + _sercom_usart_interrupt_handler(_sercom0_dev); +} +/** + * \internal Sercom interrupt handler + */ +void SERCOM0_3_Handler(void) +{ + _sercom_usart_interrupt_handler(_sercom0_dev); +} + +int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw) +{ + const struct sercomspi_regs_cfg *regs = _spi_get_regs((uint32_t)hw); + + ASSERT(dev && hw); + + if (regs == NULL) { + return ERR_INVALID_ARG; + } + + if (!hri_sercomspi_is_syncing(hw, SERCOM_SPI_SYNCBUSY_SWRST)) { + uint32_t mode = regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk; + if (hri_sercomspi_get_CTRLA_reg(hw, SERCOM_SPI_CTRLA_ENABLE)) { + hri_sercomspi_clear_CTRLA_ENABLE_bit(hw); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_ENABLE); + } + hri_sercomspi_write_CTRLA_reg(hw, SERCOM_SPI_CTRLA_SWRST | mode); + } + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); + + dev->prvt = hw; + + if ((regs->ctrla & SERCOM_SPI_CTRLA_MODE_Msk) == SERCOM_USART_CTRLA_MODE_SPI_SLAVE) { + _spi_load_regs_slave(hw, regs); + } else { + _spi_load_regs_master(hw, regs); + } + + /* Load character size from default hardware configuration */ + dev->char_size = ((regs->ctrlb & SERCOM_SPI_CTRLB_CHSIZE_Msk) == 0) ? 1 : 2; + + dev->dummy_byte = regs->dummy_byte; + + return ERR_NONE; +} + +int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw) +{ + return _spi_m_sync_init(dev, hw); +} + +int32_t _spi_m_async_init(struct _spi_async_dev *dev, void *const hw) +{ + struct _spi_async_dev *spid = dev; + /* Do hardware initialize. */ + int32_t rc = _spi_m_sync_init((struct _spi_m_sync_dev *)dev, hw); + + if (rc < 0) { + return rc; + } + + _sercom_init_irq_param(hw, (void *)dev); + /* Initialize callbacks: must use them */ + spid->callbacks.complete = NULL; + spid->callbacks.rx = NULL; + spid->callbacks.tx = NULL; + uint8_t irq = _sercom_get_irq_num(hw); + for (uint32_t i = 0; i < 4; i++) { + NVIC_DisableIRQ((IRQn_Type)irq); + NVIC_ClearPendingIRQ((IRQn_Type)irq); + irq++; + } + + return ERR_NONE; +} + +int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw) +{ + return _spi_m_async_init(dev, hw); +} + +int32_t _spi_m_async_deinit(struct _spi_async_dev *dev) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + + return _spi_deinit(dev->prvt); +} + +int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev) +{ + NVIC_DisableIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + NVIC_ClearPendingIRQ((IRQn_Type)_sercom_get_irq_num(dev->prvt)); + + return _spi_deinit(dev->prvt); +} + +int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev) +{ + return _spi_deinit(dev->prvt); +} + +int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev) +{ + return _spi_deinit(dev->prvt); +} + +int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_enable(dev->prvt); +} + +int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_enable(dev->prvt); +} + +int32_t _spi_m_async_enable(struct _spi_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_enable(dev->prvt); +} + +int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_enable(dev->prvt); +} + +int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_disable(dev->prvt); +} + +int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_sync_disable(dev->prvt); +} + +int32_t _spi_m_async_disable(struct _spi_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_disable(dev->prvt); +} + +int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return _spi_async_disable(dev->prvt); +} + +int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_m_async_set_mode(struct _spi_async_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_mode(dev->prvt, mode); +} + +int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud) +{ + int32_t rc; + ASSERT(dev); + + /* Not accept 0es */ + if (clk == 0 || baud == 0) { + return ERR_INVALID_ARG; + } + + /* Check baudrate range of current assigned clock */ + if (!(baud <= (clk >> 1) && baud >= (clk >> 8))) { + return ERR_INVALID_ARG; + } + + rc = ((clk >> 1) / baud) - 1; + return rc; +} + +int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_baudrate(dev->prvt, baud_val); +} + +int32_t _spi_m_async_set_baudrate(struct _spi_async_dev *dev, const uint32_t baud_val) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_baudrate(dev->prvt, baud_val); +} + +int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_m_async_set_char_size(struct _spi_async_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_char_size(dev->prvt, char_size, &dev->char_size); +} + +int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +int32_t _spi_m_async_set_data_order(struct _spi_async_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord) +{ + ASSERT(dev && dev->prvt); + + return _spi_set_data_order(dev->prvt, dord); +} + +/** Wait until SPI bus idle. */ +static inline void _spi_wait_bus_idle(void *const hw) +{ + while (!(hri_sercomspi_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE))) { + ; + } + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC | SERCOM_SPI_INTFLAG_DRE); +} + +/** Holds run time information for message sync transaction. */ +struct _spi_trans_ctrl { + /** Pointer to transmitting data buffer. */ + uint8_t *txbuf; + /** Pointer to receiving data buffer. */ + uint8_t *rxbuf; + /** Count number of data transmitted. */ + uint32_t txcnt; + /** Count number of data received. */ + uint32_t rxcnt; + /** Data character size. */ + uint8_t char_size; +}; + +/** Check interrupt flag of RXC and update transaction runtime information. */ +static inline bool _spi_rx_check_and_receive(void *const hw, const uint32_t iflag, struct _spi_trans_ctrl *ctrl) +{ + uint32_t data; + + if (!(iflag & SERCOM_SPI_INTFLAG_RXC)) { + return false; + } + + data = hri_sercomspi_read_DATA_reg(hw); + + if (ctrl->rxbuf) { + *ctrl->rxbuf++ = (uint8_t)data; + + if (ctrl->char_size > 1) { + *ctrl->rxbuf++ = (uint8_t)(data >> 8); + } + } + + ctrl->rxcnt++; + + return true; +} + +/** Check interrupt flag of DRE and update transaction runtime information. */ +static inline void _spi_tx_check_and_send(void *const hw, const uint32_t iflag, struct _spi_trans_ctrl *ctrl, + uint16_t dummy) +{ + uint32_t data; + + if (!(SERCOM_SPI_INTFLAG_DRE & iflag)) { + return; + } + + if (ctrl->txbuf) { + data = *ctrl->txbuf++; + + if (ctrl->char_size > 1) { + data |= (*ctrl->txbuf) << 8; + ctrl->txbuf++; + } + } else { + data = dummy; + } + + ctrl->txcnt++; + hri_sercomspi_write_DATA_reg(hw, data); +} + +/** Check interrupt flag of ERROR and update transaction runtime information. */ +static inline int32_t _spi_err_check(const uint32_t iflag, void *const hw) +{ + if (SERCOM_SPI_INTFLAG_ERROR & iflag) { + hri_sercomspi_clear_STATUS_reg(hw, ~0); + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR); + return ERR_OVERFLOW; + } + + return ERR_NONE; +} + +int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg) +{ + void * hw = dev->prvt; + int32_t rc = 0; + struct _spi_trans_ctrl ctrl = {msg->txbuf, msg->rxbuf, 0, 0, dev->char_size}; + + ASSERT(dev && hw); + + /* If settings are not applied (pending), we can not go on */ + if (hri_sercomspi_is_syncing( + hw, (SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE | SERCOM_SPI_SYNCBUSY_CTRLB))) { + return ERR_BUSY; + } + + /* SPI must be enabled to start synchronous transfer */ + if (!hri_sercomspi_get_CTRLA_ENABLE_bit(hw)) { + return ERR_NOT_INITIALIZED; + } + + for (;;) { + uint32_t iflag = hri_sercomspi_read_INTFLAG_reg(hw); + + if (!_spi_rx_check_and_receive(hw, iflag, &ctrl)) { + /* In master mode, do not start next byte before previous byte received + * to make better output waveform */ + if (ctrl.rxcnt >= ctrl.txcnt) { + _spi_tx_check_and_send(hw, iflag, &ctrl, dev->dummy_byte); + } + } + + rc = _spi_err_check(iflag, hw); + + if (rc < 0) { + break; + } + if (ctrl.txcnt >= msg->size && ctrl.rxcnt >= msg->size) { + rc = ctrl.txcnt; + break; + } + } + /* Wait until SPI bus idle */ + _spi_wait_bus_idle(hw); + + return rc; +} + +int32_t _spi_m_async_enable_tx(struct _spi_async_dev *dev, bool state) +{ + void *hw = dev->prvt; + + ASSERT(dev && hw); + + if (state) { + hri_sercomspi_set_INTEN_DRE_bit(hw); + } else { + hri_sercomspi_clear_INTEN_DRE_bit(hw); + } + + return ERR_NONE; +} + +int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state) +{ + return _spi_m_async_enable_tx(dev, state); +} + +int32_t _spi_m_async_enable_rx(struct _spi_async_dev *dev, bool state) +{ + void *hw = dev->prvt; + + ASSERT(dev); + ASSERT(hw); + + if (state) { + hri_sercomspi_set_INTEN_RXC_bit(hw); + } else { + hri_sercomspi_clear_INTEN_RXC_bit(hw); + } + + return ERR_NONE; +} + +int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state) +{ + return _spi_m_async_enable_rx(dev, state); +} + +int32_t _spi_m_async_enable_tx_complete(struct _spi_async_dev *dev, bool state) +{ + ASSERT(dev && dev->prvt); + + if (state) { + hri_sercomspi_set_INTEN_TXC_bit(dev->prvt); + } else { + hri_sercomspi_clear_INTEN_TXC_bit(dev->prvt); + } + + return ERR_NONE; +} + +int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state) +{ + return _spi_m_async_enable_tx_complete(dev, state); +} + +int32_t _spi_m_async_write_one(struct _spi_async_dev *dev, uint16_t data) +{ + ASSERT(dev && dev->prvt); + + hri_sercomspi_write_DATA_reg(dev->prvt, data); + + return ERR_NONE; +} + +int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data) +{ + ASSERT(dev && dev->prvt); + + hri_sercomspi_write_DATA_reg(dev->prvt, data); + + return ERR_NONE; +} + +int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data) +{ + ASSERT(dev && dev->prvt); + + hri_sercomspi_write_DATA_reg(dev->prvt, data); + + return ERR_NONE; +} + +uint16_t _spi_m_async_read_one(struct _spi_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomspi_read_DATA_reg(dev->prvt); +} + +uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomspi_read_DATA_reg(dev->prvt); +} + +uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomspi_read_DATA_reg(dev->prvt); +} + +int32_t _spi_m_async_register_callback(struct _spi_async_dev *dev, const enum _spi_async_dev_cb_type cb_type, + const FUNC_PTR func) +{ + typedef void (*func_t)(void); + struct _spi_async_dev *spid = dev; + + ASSERT(dev && (cb_type < SPI_DEV_CB_N)); + + func_t *p_ls = (func_t *)&spid->callbacks; + p_ls[cb_type] = (func_t)func; + + return ERR_NONE; +} + +int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type, + const FUNC_PTR func) +{ + return _spi_m_async_register_callback(dev, cb_type, func); +} + +bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_DRE); +} + +bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev) +{ + ASSERT(dev && dev->prvt); + + return hri_sercomi2cm_get_INTFLAG_reg(dev->prvt, SERCOM_SPI_INTFLAG_RXC); +} + +bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev) +{ + void *hw = dev->prvt; + + ASSERT(dev && hw); + + if (hri_sercomi2cm_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC)) { + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_TXC); + return true; + } + return false; +} + +bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev) +{ + void *hw = dev->prvt; + + ASSERT(dev && hw); + + if (hri_sercomi2cm_get_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR)) { + hri_sercomspi_clear_STATUS_reg(hw, SERCOM_SPI_STATUS_BUFOVF); + hri_sercomspi_clear_INTFLAG_reg(hw, SERCOM_SPI_INTFLAG_ERROR); + return true; + } + return false; +} + +/** + * \brief Enable/disable SPI master interrupt + * + * param[in] device The pointer to SPI master device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_m_async_set_irq_state(struct _spi_async_dev *const device, const enum _spi_async_dev_cb_type type, + const bool state) +{ + ASSERT(device); + + if (SPI_DEV_CB_ERROR == type) { + hri_sercomspi_write_INTEN_ERROR_bit(device->prvt, state); + } +} + +/** + * \brief Enable/disable SPI slave interrupt + * + * param[in] device The pointer to SPI slave device instance + * param[in] type The type of interrupt to disable/enable if applicable + * param[in] state Enable or disable + */ +void _spi_s_async_set_irq_state(struct _spi_async_dev *const device, const enum _spi_async_dev_cb_type type, + const bool state) +{ + _spi_m_async_set_irq_state(device, type, state); +} diff --git a/software/firmware/oracle_same54n19a/hpl/tc/hpl_tc.c b/software/firmware/oracle_same54n19a/hpl/tc/hpl_tc.c new file mode 100644 index 00000000..c50f65df --- /dev/null +++ b/software/firmware/oracle_same54n19a/hpl/tc/hpl_tc.c @@ -0,0 +1,347 @@ + +/** + * \file + * + * \brief SAM TC + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#include +#include +#include +#include +#include +#include + +#ifndef CONF_TC0_ENABLE +#define CONF_TC0_ENABLE 0 +#endif +#ifndef CONF_TC1_ENABLE +#define CONF_TC1_ENABLE 0 +#endif +#ifndef CONF_TC2_ENABLE +#define CONF_TC2_ENABLE 0 +#endif +#ifndef CONF_TC3_ENABLE +#define CONF_TC3_ENABLE 0 +#endif +#ifndef CONF_TC4_ENABLE +#define CONF_TC4_ENABLE 0 +#endif +#ifndef CONF_TC5_ENABLE +#define CONF_TC5_ENABLE 0 +#endif +#ifndef CONF_TC6_ENABLE +#define CONF_TC6_ENABLE 0 +#endif +#ifndef CONF_TC7_ENABLE +#define CONF_TC7_ENABLE 0 +#endif + +/** + * \brief Macro is used to fill usart configuration structure based on its + * number + * + * \param[in] n The number of structures + */ +#define TC_CONFIGURATION(n) \ + { \ + n, TC##n##_IRQn, \ + TC_CTRLA_MODE(CONF_TC##n##_MODE) | TC_CTRLA_PRESCSYNC(CONF_TC##n##_PRESCSYNC) \ + | (CONF_TC##n##_RUNSTDBY << TC_CTRLA_RUNSTDBY_Pos) | (CONF_TC##n##_ONDEMAND << TC_CTRLA_ONDEMAND_Pos) \ + | TC_CTRLA_PRESCALER(CONF_TC##n##_PRESCALER) | (CONF_TC##n##_ALOCK << TC_CTRLA_ALOCK_Pos), \ + (CONF_TC##n##_OVFEO << TC_EVCTRL_OVFEO_Pos) | (CONF_TC##n##_TCEI << TC_EVCTRL_TCEI_Pos) \ + | (CONF_TC##n##_TCINV << TC_EVCTRL_TCINV_Pos) | (CONF_TC##n##_EVACT << TC_EVCTRL_EVACT_Pos) \ + | (CONF_TC##n##_MCEO0 << TC_EVCTRL_MCEO0_Pos) | (CONF_TC##n##_MCEO1 << TC_EVCTRL_MCEO1_Pos), \ + (CONF_TC##n##_DBGRUN << TC_DBGCTRL_DBGRUN_Pos), CONF_TC##n##_PER, CONF_TC##n##_CC0, CONF_TC##n##_CC1, \ + } +/** + * \brief TC configuration type + */ +struct tc_configuration { + uint8_t number; + IRQn_Type irq; + hri_tc_ctrla_reg_t ctrl_a; + hri_tc_evctrl_reg_t event_ctrl; + hri_tc_dbgctrl_reg_t dbg_ctrl; + hri_tccount8_per_reg_t per; + hri_tccount32_cc_reg_t cc0; + hri_tccount32_cc_reg_t cc1; +}; + +/** + * \brief Array of TC configurations + */ +static struct tc_configuration _tcs[] = { +#if CONF_TC0_ENABLE == 1 + TC_CONFIGURATION(0), +#endif +#if CONF_TC1_ENABLE == 1 + TC_CONFIGURATION(1), +#endif +#if CONF_TC2_ENABLE == 1 + TC_CONFIGURATION(2), +#endif +#if CONF_TC3_ENABLE == 1 + TC_CONFIGURATION(3), +#endif +#if CONF_TC4_ENABLE == 1 + TC_CONFIGURATION(4), +#endif +#if CONF_TC5_ENABLE == 1 + TC_CONFIGURATION(5), +#endif +#if CONF_TC6_ENABLE == 1 + TC_CONFIGURATION(6), +#endif +#if CONF_TC7_ENABLE == 1 + TC_CONFIGURATION(7), +#endif +}; + +static struct _timer_device *_tc0_dev = NULL; + +static int8_t get_tc_index(const void *const hw); +static void _tc_init_irq_param(const void *const hw, void *dev); +static inline uint8_t _get_hardware_offset(const void *const hw); +/** + * \brief Initialize TC + */ +int32_t _timer_init(struct _timer_device *const device, void *const hw) +{ + int8_t i = get_tc_index(hw); + + device->hw = hw; + ASSERT(ARRAY_SIZE(_tcs)); + + if (!hri_tc_is_syncing(hw, TC_SYNCBUSY_SWRST)) { + if (hri_tc_get_CTRLA_reg(hw, TC_CTRLA_ENABLE)) { + hri_tc_clear_CTRLA_ENABLE_bit(hw); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_ENABLE); + } + hri_tc_write_CTRLA_reg(hw, TC_CTRLA_SWRST); + } + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); + + hri_tc_write_CTRLA_reg(hw, _tcs[i].ctrl_a); + hri_tc_write_DBGCTRL_reg(hw, _tcs[i].dbg_ctrl); + hri_tc_write_EVCTRL_reg(hw, _tcs[i].event_ctrl); + hri_tc_write_WAVE_reg(hw, TC_WAVE_WAVEGEN_MFRQ); + + if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT32) { + hri_tccount32_write_CC_reg(hw, 0, _tcs[i].cc0); + hri_tccount32_write_CC_reg(hw, 1, _tcs[i].cc1); + + } else if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT16) { + hri_tccount16_write_CC_reg(hw, 0, (uint16_t)_tcs[i].cc0); + hri_tccount16_write_CC_reg(hw, 1, (uint16_t)_tcs[i].cc1); + + } else if ((_tcs[i].ctrl_a & TC_CTRLA_MODE_Msk) == TC_CTRLA_MODE_COUNT8) { + hri_tccount8_write_CC_reg(hw, 0, (uint8_t)_tcs[i].cc0); + hri_tccount8_write_CC_reg(hw, 1, (uint8_t)_tcs[i].cc1); + hri_tccount8_write_PER_reg(hw, _tcs[i].per); + } + hri_tc_set_INTEN_OVF_bit(hw); + + _tc_init_irq_param(hw, (void *)device); + NVIC_DisableIRQ(_tcs[i].irq); + NVIC_ClearPendingIRQ(_tcs[i].irq); + NVIC_EnableIRQ(_tcs[i].irq); + + return ERR_NONE; +} +/** + * \brief De-initialize TC + */ +void _timer_deinit(struct _timer_device *const device) +{ + void *const hw = device->hw; + int8_t i = get_tc_index(hw); + ASSERT(ARRAY_SIZE(_tcs)); + + NVIC_DisableIRQ(_tcs[i].irq); + + hri_tc_clear_CTRLA_ENABLE_bit(hw); + hri_tc_set_CTRLA_SWRST_bit(hw); +} +/** + * \brief Start hardware timer + */ +void _timer_start(struct _timer_device *const device) +{ + hri_tc_set_CTRLA_ENABLE_bit(device->hw); +} +/** + * \brief Stop hardware timer + */ +void _timer_stop(struct _timer_device *const device) +{ + hri_tc_clear_CTRLA_ENABLE_bit(device->hw); +} +/** + * \brief Set timer period + */ +void _timer_set_period(struct _timer_device *const device, const uint32_t clock_cycles) +{ + void *const hw = device->hw; + + if (TC_CTRLA_MODE_COUNT32_Val == hri_tc_read_CTRLA_MODE_bf(hw)) { + hri_tccount32_write_CC_reg(hw, 0, clock_cycles); + } else if (TC_CTRLA_MODE_COUNT16_Val == hri_tc_read_CTRLA_MODE_bf(hw)) { + hri_tccount16_write_CC_reg(hw, 0, (uint16_t)clock_cycles); + } else if (TC_CTRLA_MODE_COUNT8_Val == hri_tc_read_CTRLA_MODE_bf(hw)) { + hri_tccount8_write_PER_reg(hw, clock_cycles); + } +} +/** + * \brief Retrieve timer period + */ +uint32_t _timer_get_period(const struct _timer_device *const device) +{ + void *const hw = device->hw; + + if (TC_CTRLA_MODE_COUNT32_Val == hri_tc_read_CTRLA_MODE_bf(hw)) { + return hri_tccount32_read_CC_reg(hw, 0); + } else if (TC_CTRLA_MODE_COUNT16_Val == hri_tc_read_CTRLA_MODE_bf(hw)) { + return hri_tccount16_read_CC_reg(hw, 0); + } else if (TC_CTRLA_MODE_COUNT8_Val == hri_tc_read_CTRLA_MODE_bf(hw)) { + return hri_tccount8_read_PER_reg(hw); + } + + return 0; +} +/** + * \brief Check if timer is running + */ +bool _timer_is_started(const struct _timer_device *const device) +{ + return hri_tc_get_CTRLA_ENABLE_bit(device->hw); +} + +/** + * \brief Retrieve timer helper functions + */ +struct _timer_hpl_interface *_tc_get_timer(void) +{ + return NULL; +} + +/** + * \brief Retrieve pwm helper functions + */ +struct _pwm_hpl_interface *_tc_get_pwm(void) +{ + return NULL; +} +/** + * \brief Set timer IRQ + * + * \param[in] hw The pointer to hardware instance + */ +void _timer_set_irq(struct _timer_device *const device) +{ + void *const hw = device->hw; + int8_t i = get_tc_index(hw); + ASSERT(ARRAY_SIZE(_tcs)); + + _irq_set(_tcs[i].irq); +} +/** + * \internal TC interrupt handler for Timer + * + * \param[in] instance TC instance number + */ +static void tc_interrupt_handler(struct _timer_device *device) +{ + void *const hw = device->hw; + + if (hri_tc_get_interrupt_OVF_bit(hw)) { + hri_tc_clear_interrupt_OVF_bit(hw); + device->timer_cb.period_expired(device); + } +} + +/** + * \brief TC interrupt handler + */ +void TC0_Handler(void) +{ + tc_interrupt_handler(_tc0_dev); +} + +/** + * \internal Retrieve TC index + * + * \param[in] hw The pointer to hardware instance + * + * \return The index of TC configuration + */ +static int8_t get_tc_index(const void *const hw) +{ + uint8_t index = _get_hardware_offset(hw); + uint8_t i; + + for (i = 0; i < ARRAY_SIZE(_tcs); i++) { + if (_tcs[i].number == index) { + return i; + } + } + + ASSERT(false); + return -1; +} + +/** + * \brief Init irq param with the given tc hardware instance + */ +static void _tc_init_irq_param(const void *const hw, void *dev) +{ + if (hw == TC0) { + _tc0_dev = (struct _timer_device *)dev; + } +} + +/** + * \internal Retrieve TC hardware index + * + * \param[in] hw The pointer to hardware instance + */ +static inline uint8_t _get_hardware_offset(const void *const hw) +{ + /* List of available TC modules. */ + Tc *const tc_modules[TC_INST_NUM] = TC_INSTS; + + /* Find index for TC instance. */ + for (uint32_t i = 0; i < TC_INST_NUM; i++) { + if ((uint32_t)hw == (uint32_t)tc_modules[i]) { + return i; + } + } + return 0; +} diff --git a/software/firmware/oracle_same54n19a/hpl/tc/hpl_tc_base.h b/software/firmware/oracle_same54n19a/hpl/tc/hpl_tc_base.h new file mode 100644 index 00000000..ae77c904 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hpl/tc/hpl_tc_base.h @@ -0,0 +1,77 @@ +/** + * \file + * + * \brief SAM Timer/Counter + * + * Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifndef _HPL_TC_BASE_H_INCLUDED +#define _HPL_TC_BASE_H_INCLUDED + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * \addtogroup tc_group TC Hardware Proxy Layer + * + * \section tc_hpl_rev Revision History + * - v0.0.0.1 Initial Commit + * + *@{ + */ + +/** + * \name HPL functions + */ +//@{ + +/** + * \brief Retrieve timer helper functions + * + * \return A pointer to set of timer helper functions + */ +struct _timer_hpl_interface *_tc_get_timer(void); + +/** + * \brief Retrieve pwm helper functions + * + * \return A pointer to set of pwm helper functions + */ +struct _pwm_hpl_interface *_tc_get_pwm(void); + +//@} +/**@}*/ + +#ifdef __cplusplus +} +#endif +#endif /* _HPL_TC_BASE_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_ac_e54.h b/software/firmware/oracle_same54n19a/hri/hri_ac_e54.h new file mode 100644 index 00000000..588499e4 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_ac_e54.h @@ -0,0 +1,1836 @@ +/** + * \file + * + * \brief SAM AC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_AC_COMPONENT_ +#ifndef _HRI_AC_E54_H_INCLUDED_ +#define _HRI_AC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_AC_CRITICAL_SECTIONS) +#define AC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define AC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define AC_CRITICAL_SECTION_ENTER() +#define AC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_ac_calib_reg_t; +typedef uint16_t hri_ac_evctrl_reg_t; +typedef uint32_t hri_ac_compctrl_reg_t; +typedef uint32_t hri_ac_syncbusy_reg_t; +typedef uint8_t hri_ac_ctrla_reg_t; +typedef uint8_t hri_ac_ctrlb_reg_t; +typedef uint8_t hri_ac_dbgctrl_reg_t; +typedef uint8_t hri_ac_intenset_reg_t; +typedef uint8_t hri_ac_intflag_reg_t; +typedef uint8_t hri_ac_scaler_reg_t; +typedef uint8_t hri_ac_statusa_reg_t; +typedef uint8_t hri_ac_statusb_reg_t; +typedef uint8_t hri_ac_winctrl_reg_t; + +static inline void hri_ac_wait_for_sync(const void *const hw, hri_ac_syncbusy_reg_t reg) +{ + while (((Ac *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_ac_is_syncing(const void *const hw, hri_ac_syncbusy_reg_t reg) +{ + return ((Ac *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_ac_get_INTFLAG_COMP0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos; +} + +static inline void hri_ac_clear_INTFLAG_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0; +} + +static inline bool hri_ac_get_INTFLAG_COMP1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos; +} + +static inline void hri_ac_clear_INTFLAG_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1; +} + +static inline bool hri_ac_get_INTFLAG_WIN0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos; +} + +static inline void hri_ac_clear_INTFLAG_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0; +} + +static inline bool hri_ac_get_interrupt_COMP0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP0) >> AC_INTFLAG_COMP0_Pos; +} + +static inline void hri_ac_clear_interrupt_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP0; +} + +static inline bool hri_ac_get_interrupt_COMP1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_COMP1) >> AC_INTFLAG_COMP1_Pos; +} + +static inline void hri_ac_clear_interrupt_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_COMP1; +} + +static inline bool hri_ac_get_interrupt_WIN0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTFLAG.reg & AC_INTFLAG_WIN0) >> AC_INTFLAG_WIN0_Pos; +} + +static inline void hri_ac_clear_interrupt_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTFLAG.reg = AC_INTFLAG_WIN0; +} + +static inline hri_ac_intflag_reg_t hri_ac_get_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_intflag_reg_t hri_ac_read_INTFLAG_reg(const void *const hw) +{ + return ((Ac *)hw)->INTFLAG.reg; +} + +static inline void hri_ac_clear_INTFLAG_reg(const void *const hw, hri_ac_intflag_reg_t mask) +{ + ((Ac *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_ac_set_INTEN_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; +} + +static inline bool hri_ac_get_INTEN_COMP0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP0) >> AC_INTENSET_COMP0_Pos; +} + +static inline void hri_ac_write_INTEN_COMP0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP0; + } +} + +static inline void hri_ac_clear_INTEN_COMP0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP0; +} + +static inline void hri_ac_set_INTEN_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1; +} + +static inline bool hri_ac_get_INTEN_COMP1_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_COMP1) >> AC_INTENSET_COMP1_Pos; +} + +static inline void hri_ac_write_INTEN_COMP1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_COMP1; + } +} + +static inline void hri_ac_clear_INTEN_COMP1_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_COMP1; +} + +static inline void hri_ac_set_INTEN_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0; +} + +static inline bool hri_ac_get_INTEN_WIN0_bit(const void *const hw) +{ + return (((Ac *)hw)->INTENSET.reg & AC_INTENSET_WIN0) >> AC_INTENSET_WIN0_Pos; +} + +static inline void hri_ac_write_INTEN_WIN0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0; + } else { + ((Ac *)hw)->INTENSET.reg = AC_INTENSET_WIN0; + } +} + +static inline void hri_ac_clear_INTEN_WIN0_bit(const void *const hw) +{ + ((Ac *)hw)->INTENCLR.reg = AC_INTENSET_WIN0; +} + +static inline void hri_ac_set_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) +{ + ((Ac *)hw)->INTENSET.reg = mask; +} + +static inline hri_ac_intenset_reg_t hri_ac_get_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_intenset_reg_t hri_ac_read_INTEN_reg(const void *const hw) +{ + return ((Ac *)hw)->INTENSET.reg; +} + +static inline void hri_ac_write_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t data) +{ + ((Ac *)hw)->INTENSET.reg = data; + ((Ac *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_ac_clear_INTEN_reg(const void *const hw, hri_ac_intenset_reg_t mask) +{ + ((Ac *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_ac_get_STATUSA_STATE0_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE0) >> AC_STATUSA_STATE0_Pos; +} + +static inline bool hri_ac_get_STATUSA_STATE1_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_STATE1) >> AC_STATUSA_STATE1_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_WSTATE0_bf(const void *const hw, hri_ac_statusa_reg_t mask) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0(mask)) >> AC_STATUSA_WSTATE0_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_WSTATE0_bf(const void *const hw) +{ + return (((Ac *)hw)->STATUSA.reg & AC_STATUSA_WSTATE0_Msk) >> AC_STATUSA_WSTATE0_Pos; +} + +static inline hri_ac_statusa_reg_t hri_ac_get_STATUSA_reg(const void *const hw, hri_ac_statusa_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->STATUSA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_statusa_reg_t hri_ac_read_STATUSA_reg(const void *const hw) +{ + return ((Ac *)hw)->STATUSA.reg; +} + +static inline bool hri_ac_get_STATUSB_READY0_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY0) >> AC_STATUSB_READY0_Pos; +} + +static inline bool hri_ac_get_STATUSB_READY1_bit(const void *const hw) +{ + return (((Ac *)hw)->STATUSB.reg & AC_STATUSB_READY1) >> AC_STATUSB_READY1_Pos; +} + +static inline hri_ac_statusb_reg_t hri_ac_get_STATUSB_reg(const void *const hw, hri_ac_statusb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->STATUSB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_statusb_reg_t hri_ac_read_STATUSB_reg(const void *const hw) +{ + return ((Ac *)hw)->STATUSB.reg; +} + +static inline bool hri_ac_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_SWRST) >> AC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_ENABLE) >> AC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_WINCTRL_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_WINCTRL) >> AC_SYNCBUSY_WINCTRL_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_COMPCTRL0_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL0) >> AC_SYNCBUSY_COMPCTRL0_Pos; +} + +static inline bool hri_ac_get_SYNCBUSY_COMPCTRL1_bit(const void *const hw) +{ + return (((Ac *)hw)->SYNCBUSY.reg & AC_SYNCBUSY_COMPCTRL1) >> AC_SYNCBUSY_COMPCTRL1_Pos; +} + +static inline hri_ac_syncbusy_reg_t hri_ac_get_SYNCBUSY_reg(const void *const hw, hri_ac_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ac_syncbusy_reg_t hri_ac_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Ac *)hw)->SYNCBUSY.reg; +} + +static inline void hri_ac_set_CTRLA_SWRST_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_SWRST; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp = (tmp & AC_CTRLA_SWRST) >> AC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_ac_set_CTRLA_ENABLE_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg |= AC_CTRLA_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp = (tmp & AC_CTRLA_ENABLE) >> AC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp &= ~AC_CTRLA_ENABLE; + tmp |= value << AC_CTRLA_ENABLE_Pos; + ((Ac *)hw)->CTRLA.reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg &= ~AC_CTRLA_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg ^= AC_CTRLA_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg |= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_ctrla_reg_t hri_ac_get_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg = data; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg &= ~mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_CTRLA_reg(const void *const hw, hri_ac_ctrla_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLA.reg ^= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_ctrla_reg_t hri_ac_read_CTRLA_reg(const void *const hw) +{ + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_SWRST | AC_SYNCBUSY_ENABLE); + return ((Ac *)hw)->CTRLA.reg; +} + +static inline void hri_ac_set_EVCTRL_COMPEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEO0) >> AC_EVCTRL_COMPEO0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEO0; + tmp |= value << AC_EVCTRL_COMPEO0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEO1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEO1) >> AC_EVCTRL_COMPEO1_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEO1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEO1; + tmp |= value << AC_EVCTRL_COMPEO1_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEO1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEO1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_WINEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_WINEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_WINEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_WINEO0) >> AC_EVCTRL_WINEO0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_WINEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_WINEO0; + tmp |= value << AC_EVCTRL_WINEO0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_WINEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_WINEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_WINEO0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_WINEO0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEI0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEI0) >> AC_EVCTRL_COMPEI0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEI0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEI0; + tmp |= value << AC_EVCTRL_COMPEI0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_COMPEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_COMPEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_COMPEI1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_COMPEI1) >> AC_EVCTRL_COMPEI1_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_COMPEI1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_COMPEI1; + tmp |= value << AC_EVCTRL_COMPEI1_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_COMPEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_COMPEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_COMPEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_COMPEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_INVEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_INVEI0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_INVEI0) >> AC_EVCTRL_INVEI0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_INVEI0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_INVEI0; + tmp |= value << AC_EVCTRL_INVEI0_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_INVEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_INVEI0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI0; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_INVEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= AC_EVCTRL_INVEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_EVCTRL_INVEI1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp = (tmp & AC_EVCTRL_INVEI1) >> AC_EVCTRL_INVEI1_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_EVCTRL_INVEI1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= ~AC_EVCTRL_INVEI1; + tmp |= value << AC_EVCTRL_INVEI1_Pos; + ((Ac *)hw)->EVCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_INVEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~AC_EVCTRL_INVEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_INVEI1_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= AC_EVCTRL_INVEI1; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_evctrl_reg_t hri_ac_get_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_EVCTRL_reg(const void *const hw, hri_ac_evctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->EVCTRL.reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_evctrl_reg_t hri_ac_read_EVCTRL_reg(const void *const hw) +{ + return ((Ac *)hw)->EVCTRL.reg; +} + +static inline void hri_ac_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg |= AC_DBGCTRL_DBGRUN; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->DBGCTRL.reg; + tmp = (tmp & AC_DBGCTRL_DBGRUN) >> AC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->DBGCTRL.reg; + tmp &= ~AC_DBGCTRL_DBGRUN; + tmp |= value << AC_DBGCTRL_DBGRUN_Pos; + ((Ac *)hw)->DBGCTRL.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg &= ~AC_DBGCTRL_DBGRUN; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg ^= AC_DBGCTRL_DBGRUN; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_dbgctrl_reg_t hri_ac_get_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_DBGCTRL_reg(const void *const hw, hri_ac_dbgctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->DBGCTRL.reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_dbgctrl_reg_t hri_ac_read_DBGCTRL_reg(const void *const hw) +{ + return ((Ac *)hw)->DBGCTRL.reg; +} + +static inline void hri_ac_set_WINCTRL_WEN0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WEN0; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_WINCTRL_WEN0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WEN0) >> AC_WINCTRL_WEN0_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_WINCTRL_WEN0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= ~AC_WINCTRL_WEN0; + tmp |= value << AC_WINCTRL_WEN0_Pos; + ((Ac *)hw)->WINCTRL.reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_WEN0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WEN0; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_WEN0_bit(const void *const hw) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WEN0; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg |= AC_WINCTRL_WINTSEL0(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WINTSEL0(mask)) >> AC_WINCTRL_WINTSEL0_Pos; + return tmp; +} + +static inline void hri_ac_write_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t data) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= ~AC_WINCTRL_WINTSEL0_Msk; + tmp |= AC_WINCTRL_WINTSEL0(data); + ((Ac *)hw)->WINCTRL.reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg &= ~AC_WINCTRL_WINTSEL0(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_WINTSEL0_bf(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg ^= AC_WINCTRL_WINTSEL0(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_WINTSEL0_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp = (tmp & AC_WINCTRL_WINTSEL0_Msk) >> AC_WINCTRL_WINTSEL0_Pos; + return tmp; +} + +static inline void hri_ac_set_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg |= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_get_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + uint8_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + tmp = ((Ac *)hw)->WINCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg = data; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg &= ~mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_WINCTRL_reg(const void *const hw, hri_ac_winctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->WINCTRL.reg ^= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_winctrl_reg_t hri_ac_read_WINCTRL_reg(const void *const hw) +{ + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + return ((Ac *)hw)->WINCTRL.reg; +} + +static inline void hri_ac_set_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg |= AC_SCALER_VALUE(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_VALUE_bf(const void *const hw, uint8_t index, + hri_ac_scaler_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp = (tmp & AC_SCALER_VALUE(mask)) >> AC_SCALER_VALUE_Pos; + return tmp; +} + +static inline void hri_ac_write_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data) +{ + uint8_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp &= ~AC_SCALER_VALUE_Msk; + tmp |= AC_SCALER_VALUE(data); + ((Ac *)hw)->SCALER[index].reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg &= ~AC_SCALER_VALUE(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_SCALER_VALUE_bf(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg ^= AC_SCALER_VALUE(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_VALUE_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp = (tmp & AC_SCALER_VALUE_Msk) >> AC_SCALER_VALUE_Pos; + return tmp; +} + +static inline void hri_ac_set_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_get_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ac *)hw)->SCALER[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_SCALER_reg(const void *const hw, uint8_t index, hri_ac_scaler_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->SCALER[index].reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_scaler_reg_t hri_ac_read_SCALER_reg(const void *const hw, uint8_t index) +{ + return ((Ac *)hw)->SCALER[index].reg; +} + +static inline void hri_ac_set_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_ENABLE) >> AC_COMPCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_ENABLE; + tmp |= value << AC_COMPCTRL_ENABLE_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_ENABLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SINGLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SINGLE) >> AC_COMPCTRL_SINGLE_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_SINGLE; + tmp |= value << AC_COMPCTRL_SINGLE_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SINGLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_SINGLE_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SINGLE; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_RUNSTDBY; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_RUNSTDBY) >> AC_COMPCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_RUNSTDBY; + tmp |= value << AC_COMPCTRL_RUNSTDBY_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_RUNSTDBY; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_RUNSTDBY; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SWAP; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SWAP) >> AC_COMPCTRL_SWAP_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_SWAP; + tmp |= value << AC_COMPCTRL_SWAP_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SWAP; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_SWAP_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SWAP; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYSTEN; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ac_get_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_HYSTEN) >> AC_COMPCTRL_HYSTEN_Pos; + return (bool)tmp; +} + +static inline void hri_ac_write_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_HYSTEN; + tmp |= value << AC_COMPCTRL_HYSTEN_Pos; + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYSTEN; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_HYSTEN_bit(const void *const hw, uint8_t index) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYSTEN; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_set_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_INTSEL(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_INTSEL(mask)) >> AC_COMPCTRL_INTSEL_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_INTSEL_Msk; + tmp |= AC_COMPCTRL_INTSEL(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_INTSEL(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_INTSEL(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_INTSEL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_INTSEL_Msk) >> AC_COMPCTRL_INTSEL_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXNEG(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXNEG(mask)) >> AC_COMPCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_MUXNEG_Msk; + tmp |= AC_COMPCTRL_MUXNEG(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXNEG(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXNEG(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXNEG_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXNEG_Msk) >> AC_COMPCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_MUXPOS(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXPOS(mask)) >> AC_COMPCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_MUXPOS_Msk; + tmp |= AC_COMPCTRL_MUXPOS(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_MUXPOS(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_MUXPOS(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_MUXPOS_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_MUXPOS_Msk) >> AC_COMPCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_SPEED(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SPEED(mask)) >> AC_COMPCTRL_SPEED_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_SPEED_Msk; + tmp |= AC_COMPCTRL_SPEED(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_SPEED(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_SPEED(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_SPEED_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_SPEED_Msk) >> AC_COMPCTRL_SPEED_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_HYST(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_HYST(mask)) >> AC_COMPCTRL_HYST_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_HYST_Msk; + tmp |= AC_COMPCTRL_HYST(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_HYST(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_HYST_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_HYST(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_HYST_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_HYST_Msk) >> AC_COMPCTRL_HYST_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_FLEN(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_FLEN(mask)) >> AC_COMPCTRL_FLEN_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_FLEN_Msk; + tmp |= AC_COMPCTRL_FLEN(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_FLEN(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_FLEN(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_FLEN_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_FLEN_Msk) >> AC_COMPCTRL_FLEN_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= AC_COMPCTRL_OUT(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_OUT(mask)) >> AC_COMPCTRL_OUT_Pos; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + uint32_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= ~AC_COMPCTRL_OUT_Msk; + tmp |= AC_COMPCTRL_OUT(data); + ((Ac *)hw)->COMPCTRL[index].reg = tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~AC_COMPCTRL_OUT(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_OUT_bf(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= AC_COMPCTRL_OUT(mask); + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_MASK); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_OUT_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp = (tmp & AC_COMPCTRL_OUT_Msk) >> AC_COMPCTRL_OUT_Pos; + return tmp; +} + +static inline void hri_ac_set_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg |= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_get_COMPCTRL_reg(const void *const hw, uint8_t index, + hri_ac_compctrl_reg_t mask) +{ + uint32_t tmp; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + tmp = ((Ac *)hw)->COMPCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg = data; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg &= ~mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_COMPCTRL_reg(const void *const hw, uint8_t index, hri_ac_compctrl_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->COMPCTRL[index].reg ^= mask; + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_compctrl_reg_t hri_ac_read_COMPCTRL_reg(const void *const hw, uint8_t index) +{ + hri_ac_wait_for_sync(hw, AC_SYNCBUSY_ENABLE); + return ((Ac *)hw)->COMPCTRL[index].reg; +} + +static inline void hri_ac_set_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CALIB.reg |= AC_CALIB_BIAS0(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_calib_reg_t hri_ac_get_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->CALIB.reg; + tmp = (tmp & AC_CALIB_BIAS0(mask)) >> AC_CALIB_BIAS0_Pos; + return tmp; +} + +static inline void hri_ac_write_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t data) +{ + uint16_t tmp; + AC_CRITICAL_SECTION_ENTER(); + tmp = ((Ac *)hw)->CALIB.reg; + tmp &= ~AC_CALIB_BIAS0_Msk; + tmp |= AC_CALIB_BIAS0(data); + ((Ac *)hw)->CALIB.reg = tmp; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CALIB.reg &= ~AC_CALIB_BIAS0(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_CALIB_BIAS0_bf(const void *const hw, hri_ac_calib_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CALIB.reg ^= AC_CALIB_BIAS0(mask); + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_calib_reg_t hri_ac_read_CALIB_BIAS0_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->CALIB.reg; + tmp = (tmp & AC_CALIB_BIAS0_Msk) >> AC_CALIB_BIAS0_Pos; + return tmp; +} + +static inline void hri_ac_set_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CALIB.reg |= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_calib_reg_t hri_ac_get_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Ac *)hw)->CALIB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ac_write_CALIB_reg(const void *const hw, hri_ac_calib_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CALIB.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_clear_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CALIB.reg &= ~mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ac_toggle_CALIB_reg(const void *const hw, hri_ac_calib_reg_t mask) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CALIB.reg ^= mask; + AC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ac_calib_reg_t hri_ac_read_CALIB_reg(const void *const hw) +{ + return ((Ac *)hw)->CALIB.reg; +} + +static inline void hri_ac_write_CTRLB_reg(const void *const hw, hri_ac_ctrlb_reg_t data) +{ + AC_CRITICAL_SECTION_ENTER(); + ((Ac *)hw)->CTRLB.reg = data; + AC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_AC_E54_H_INCLUDED */ +#endif /* _SAME54_AC_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_adc_e54.h b/software/firmware/oracle_same54n19a/hri/hri_adc_e54.h new file mode 100644 index 00000000..7bb7e6f8 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_adc_e54.h @@ -0,0 +1,3663 @@ +/** + * \file + * + * \brief SAM ADC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_ADC_COMPONENT_ +#ifndef _HRI_ADC_E54_H_INCLUDED_ +#define _HRI_ADC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_ADC_CRITICAL_SECTIONS) +#define ADC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define ADC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define ADC_CRITICAL_SECTION_ENTER() +#define ADC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_adc_calib_reg_t; +typedef uint16_t hri_adc_ctrla_reg_t; +typedef uint16_t hri_adc_ctrlb_reg_t; +typedef uint16_t hri_adc_gaincorr_reg_t; +typedef uint16_t hri_adc_inputctrl_reg_t; +typedef uint16_t hri_adc_offsetcorr_reg_t; +typedef uint16_t hri_adc_ress_reg_t; +typedef uint16_t hri_adc_result_reg_t; +typedef uint16_t hri_adc_winlt_reg_t; +typedef uint16_t hri_adc_winut_reg_t; +typedef uint32_t hri_adc_dseqctrl_reg_t; +typedef uint32_t hri_adc_dseqdata_reg_t; +typedef uint32_t hri_adc_dseqstat_reg_t; +typedef uint32_t hri_adc_syncbusy_reg_t; +typedef uint8_t hri_adc_avgctrl_reg_t; +typedef uint8_t hri_adc_dbgctrl_reg_t; +typedef uint8_t hri_adc_evctrl_reg_t; +typedef uint8_t hri_adc_intenset_reg_t; +typedef uint8_t hri_adc_intflag_reg_t; +typedef uint8_t hri_adc_refctrl_reg_t; +typedef uint8_t hri_adc_sampctrl_reg_t; +typedef uint8_t hri_adc_status_reg_t; +typedef uint8_t hri_adc_swtrig_reg_t; + +static inline void hri_adc_wait_for_sync(const void *const hw, hri_adc_syncbusy_reg_t reg) +{ + while (((Adc *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_adc_is_syncing(const void *const hw, hri_adc_syncbusy_reg_t reg) +{ + return ((Adc *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_adc_get_INTFLAG_RESRDY_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos; +} + +static inline void hri_adc_clear_INTFLAG_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY; +} + +static inline bool hri_adc_get_INTFLAG_OVERRUN_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos; +} + +static inline void hri_adc_clear_INTFLAG_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN; +} + +static inline bool hri_adc_get_INTFLAG_WINMON_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos; +} + +static inline void hri_adc_clear_INTFLAG_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON; +} + +static inline bool hri_adc_get_interrupt_RESRDY_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_RESRDY) >> ADC_INTFLAG_RESRDY_Pos; +} + +static inline void hri_adc_clear_interrupt_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_RESRDY; +} + +static inline bool hri_adc_get_interrupt_OVERRUN_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_OVERRUN) >> ADC_INTFLAG_OVERRUN_Pos; +} + +static inline void hri_adc_clear_interrupt_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_OVERRUN; +} + +static inline bool hri_adc_get_interrupt_WINMON_bit(const void *const hw) +{ + return (((Adc *)hw)->INTFLAG.reg & ADC_INTFLAG_WINMON) >> ADC_INTFLAG_WINMON_Pos; +} + +static inline void hri_adc_clear_interrupt_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTFLAG.reg = ADC_INTFLAG_WINMON; +} + +static inline hri_adc_intflag_reg_t hri_adc_get_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_intflag_reg_t hri_adc_read_INTFLAG_reg(const void *const hw) +{ + return ((Adc *)hw)->INTFLAG.reg; +} + +static inline void hri_adc_clear_INTFLAG_reg(const void *const hw, hri_adc_intflag_reg_t mask) +{ + ((Adc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_adc_set_INTEN_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; +} + +static inline bool hri_adc_get_INTEN_RESRDY_bit(const void *const hw) +{ + return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_RESRDY) >> ADC_INTENSET_RESRDY_Pos; +} + +static inline void hri_adc_write_INTEN_RESRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; + } else { + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_RESRDY; + } +} + +static inline void hri_adc_clear_INTEN_RESRDY_bit(const void *const hw) +{ + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_RESRDY; +} + +static inline void hri_adc_set_INTEN_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; +} + +static inline bool hri_adc_get_INTEN_OVERRUN_bit(const void *const hw) +{ + return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_OVERRUN) >> ADC_INTENSET_OVERRUN_Pos; +} + +static inline void hri_adc_write_INTEN_OVERRUN_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN; + } else { + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_OVERRUN; + } +} + +static inline void hri_adc_clear_INTEN_OVERRUN_bit(const void *const hw) +{ + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_OVERRUN; +} + +static inline void hri_adc_set_INTEN_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON; +} + +static inline bool hri_adc_get_INTEN_WINMON_bit(const void *const hw) +{ + return (((Adc *)hw)->INTENSET.reg & ADC_INTENSET_WINMON) >> ADC_INTENSET_WINMON_Pos; +} + +static inline void hri_adc_write_INTEN_WINMON_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON; + } else { + ((Adc *)hw)->INTENSET.reg = ADC_INTENSET_WINMON; + } +} + +static inline void hri_adc_clear_INTEN_WINMON_bit(const void *const hw) +{ + ((Adc *)hw)->INTENCLR.reg = ADC_INTENSET_WINMON; +} + +static inline void hri_adc_set_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) +{ + ((Adc *)hw)->INTENSET.reg = mask; +} + +static inline hri_adc_intenset_reg_t hri_adc_get_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_intenset_reg_t hri_adc_read_INTEN_reg(const void *const hw) +{ + return ((Adc *)hw)->INTENSET.reg; +} + +static inline void hri_adc_write_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t data) +{ + ((Adc *)hw)->INTENSET.reg = data; + ((Adc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_adc_clear_INTEN_reg(const void *const hw, hri_adc_intenset_reg_t mask) +{ + ((Adc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_adc_get_STATUS_ADCBUSY_bit(const void *const hw) +{ + return (((Adc *)hw)->STATUS.reg & ADC_STATUS_ADCBUSY) >> ADC_STATUS_ADCBUSY_Pos; +} + +static inline hri_adc_status_reg_t hri_adc_get_STATUS_WCC_bf(const void *const hw, hri_adc_status_reg_t mask) +{ + return (((Adc *)hw)->STATUS.reg & ADC_STATUS_WCC(mask)) >> ADC_STATUS_WCC_Pos; +} + +static inline hri_adc_status_reg_t hri_adc_read_STATUS_WCC_bf(const void *const hw) +{ + return (((Adc *)hw)->STATUS.reg & ADC_STATUS_WCC_Msk) >> ADC_STATUS_WCC_Pos; +} + +static inline hri_adc_status_reg_t hri_adc_get_STATUS_reg(const void *const hw, hri_adc_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_status_reg_t hri_adc_read_STATUS_reg(const void *const hw) +{ + return ((Adc *)hw)->STATUS.reg; +} + +static inline bool hri_adc_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWRST) >> ADC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_ENABLE) >> ADC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_INPUTCTRL_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_INPUTCTRL) >> ADC_SYNCBUSY_INPUTCTRL_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_CTRLB) >> ADC_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_REFCTRL_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_REFCTRL) >> ADC_SYNCBUSY_REFCTRL_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_AVGCTRL_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_AVGCTRL) >> ADC_SYNCBUSY_AVGCTRL_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_SAMPCTRL_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SAMPCTRL) >> ADC_SYNCBUSY_SAMPCTRL_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_WINLT_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINLT) >> ADC_SYNCBUSY_WINLT_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_WINUT_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_WINUT) >> ADC_SYNCBUSY_WINUT_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_GAINCORR_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_GAINCORR) >> ADC_SYNCBUSY_GAINCORR_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_OFFSETCORR_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_OFFSETCORR) >> ADC_SYNCBUSY_OFFSETCORR_Pos; +} + +static inline bool hri_adc_get_SYNCBUSY_SWTRIG_bit(const void *const hw) +{ + return (((Adc *)hw)->SYNCBUSY.reg & ADC_SYNCBUSY_SWTRIG) >> ADC_SYNCBUSY_SWTRIG_Pos; +} + +static inline hri_adc_syncbusy_reg_t hri_adc_get_SYNCBUSY_reg(const void *const hw, hri_adc_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Adc *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_syncbusy_reg_t hri_adc_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Adc *)hw)->SYNCBUSY.reg; +} + +static inline bool hri_adc_get_DSEQSTAT_INPUTCTRL_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_INPUTCTRL) >> ADC_DSEQSTAT_INPUTCTRL_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_CTRLB_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_CTRLB) >> ADC_DSEQSTAT_CTRLB_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_REFCTRL_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_REFCTRL) >> ADC_DSEQSTAT_REFCTRL_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_AVGCTRL_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_AVGCTRL) >> ADC_DSEQSTAT_AVGCTRL_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_SAMPCTRL_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_SAMPCTRL) >> ADC_DSEQSTAT_SAMPCTRL_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_WINLT_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_WINLT) >> ADC_DSEQSTAT_WINLT_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_WINUT_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_WINUT) >> ADC_DSEQSTAT_WINUT_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_GAINCORR_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_GAINCORR) >> ADC_DSEQSTAT_GAINCORR_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_OFFSETCORR_bit(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_OFFSETCORR) >> ADC_DSEQSTAT_OFFSETCORR_Pos; +} + +static inline bool hri_adc_get_DSEQSTAT_BUSY_bit(const void *const hw) +{ + return (((Adc *)hw)->DSEQSTAT.reg & ADC_DSEQSTAT_BUSY) >> ADC_DSEQSTAT_BUSY_Pos; +} + +static inline hri_adc_dseqstat_reg_t hri_adc_get_DSEQSTAT_reg(const void *const hw, hri_adc_dseqstat_reg_t mask) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQSTAT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_dseqstat_reg_t hri_adc_read_DSEQSTAT_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return ((Adc *)hw)->DSEQSTAT.reg; +} + +static inline hri_adc_result_reg_t hri_adc_get_RESULT_RESULT_bf(const void *const hw, hri_adc_result_reg_t mask) +{ + return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT(mask)) >> ADC_RESULT_RESULT_Pos; +} + +static inline hri_adc_result_reg_t hri_adc_read_RESULT_RESULT_bf(const void *const hw) +{ + return (((Adc *)hw)->RESULT.reg & ADC_RESULT_RESULT_Msk) >> ADC_RESULT_RESULT_Pos; +} + +static inline hri_adc_result_reg_t hri_adc_get_RESULT_reg(const void *const hw, hri_adc_result_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->RESULT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_result_reg_t hri_adc_read_RESULT_reg(const void *const hw) +{ + return ((Adc *)hw)->RESULT.reg; +} + +static inline hri_adc_ress_reg_t hri_adc_get_RESS_RESS_bf(const void *const hw, hri_adc_ress_reg_t mask) +{ + return (((Adc *)hw)->RESS.reg & ADC_RESS_RESS(mask)) >> ADC_RESS_RESS_Pos; +} + +static inline hri_adc_ress_reg_t hri_adc_read_RESS_RESS_bf(const void *const hw) +{ + return (((Adc *)hw)->RESS.reg & ADC_RESS_RESS_Msk) >> ADC_RESS_RESS_Pos; +} + +static inline hri_adc_ress_reg_t hri_adc_get_RESS_reg(const void *const hw, hri_adc_ress_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->RESS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_adc_ress_reg_t hri_adc_read_RESS_reg(const void *const hw) +{ + return ((Adc *)hw)->RESS.reg; +} + +static inline void hri_adc_set_CTRLA_SWRST_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SWRST; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_SWRST) >> ADC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_adc_set_CTRLA_ENABLE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ENABLE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_ENABLE) >> ADC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_ENABLE; + tmp |= value << ADC_CTRLA_ENABLE_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ENABLE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ENABLE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_SLAVEEN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_SLAVEEN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_SLAVEEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_SLAVEEN) >> ADC_CTRLA_SLAVEEN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_SLAVEEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_SLAVEEN; + tmp |= value << ADC_CTRLA_SLAVEEN_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_SLAVEEN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_SLAVEEN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_SLAVEEN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_SLAVEEN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_RUNSTDBY; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_RUNSTDBY) >> ADC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_RUNSTDBY; + tmp |= value << ADC_CTRLA_RUNSTDBY_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_RUNSTDBY; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_RUNSTDBY; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_ONDEMAND_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_ONDEMAND; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_ONDEMAND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_ONDEMAND) >> ADC_CTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_ONDEMAND; + tmp |= value << ADC_CTRLA_ONDEMAND_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_ONDEMAND_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_ONDEMAND; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_ONDEMAND_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_ONDEMAND; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_R2R_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_R2R; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLA_R2R_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_R2R) >> ADC_CTRLA_R2R_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLA_R2R_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_R2R; + tmp |= value << ADC_CTRLA_R2R_Pos; + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_R2R_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_R2R; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_R2R_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_R2R; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_DUALSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_DUALSEL(mask)) >> ADC_CTRLA_DUALSEL_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_DUALSEL_Msk; + tmp |= ADC_CTRLA_DUALSEL(data); + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_DUALSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_DUALSEL_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_DUALSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_DUALSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_DUALSEL_Msk) >> ADC_CTRLA_DUALSEL_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= ADC_CTRLA_PRESCALER(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_PRESCALER(mask)) >> ADC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= ~ADC_CTRLA_PRESCALER_Msk; + tmp |= ADC_CTRLA_PRESCALER(data); + ((Adc *)hw)->CTRLA.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~ADC_CTRLA_PRESCALER(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= ADC_CTRLA_PRESCALER(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLA.reg; + tmp = (tmp & ADC_CTRLA_PRESCALER_Msk) >> ADC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_get_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + tmp = ((Adc *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLA_reg(const void *const hw, hri_adc_ctrla_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLA.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrla_reg_t hri_adc_read_CTRLA_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_SWRST | ADC_SYNCBUSY_ENABLE); + return ((Adc *)hw)->CTRLA.reg; +} + +static inline void hri_adc_set_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_FLUSHEI) >> ADC_EVCTRL_FLUSHEI_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_FLUSHEI_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_FLUSHEI; + tmp |= value << ADC_EVCTRL_FLUSHEI_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_FLUSHEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_STARTEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_STARTEI_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_STARTEI) >> ADC_EVCTRL_STARTEI_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_STARTEI_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_STARTEI; + tmp |= value << ADC_EVCTRL_STARTEI_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_STARTEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_STARTEI_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTEI; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_FLUSHINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_FLUSHINV) >> ADC_EVCTRL_FLUSHINV_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_FLUSHINV_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_FLUSHINV; + tmp |= value << ADC_EVCTRL_FLUSHINV_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_FLUSHINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_FLUSHINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_FLUSHINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_STARTINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_STARTINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_STARTINV_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_STARTINV) >> ADC_EVCTRL_STARTINV_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_STARTINV_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_STARTINV; + tmp |= value << ADC_EVCTRL_STARTINV_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_STARTINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_STARTINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_STARTINV_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_STARTINV; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_RESRDYEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_RESRDYEO) >> ADC_EVCTRL_RESRDYEO_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_RESRDYEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_RESRDYEO; + tmp |= value << ADC_EVCTRL_RESRDYEO_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_RESRDYEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_RESRDYEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_RESRDYEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_WINMONEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= ADC_EVCTRL_WINMONEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_EVCTRL_WINMONEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp = (tmp & ADC_EVCTRL_WINMONEO) >> ADC_EVCTRL_WINMONEO_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_EVCTRL_WINMONEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= ~ADC_EVCTRL_WINMONEO; + tmp |= value << ADC_EVCTRL_WINMONEO_Pos; + ((Adc *)hw)->EVCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_WINMONEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~ADC_EVCTRL_WINMONEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_WINMONEO_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= ADC_EVCTRL_WINMONEO; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_evctrl_reg_t hri_adc_get_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_EVCTRL_reg(const void *const hw, hri_adc_evctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->EVCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_evctrl_reg_t hri_adc_read_EVCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->EVCTRL.reg; +} + +static inline void hri_adc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg |= ADC_DBGCTRL_DBGRUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->DBGCTRL.reg; + tmp = (tmp & ADC_DBGCTRL_DBGRUN) >> ADC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DBGCTRL.reg; + tmp &= ~ADC_DBGCTRL_DBGRUN; + tmp |= value << ADC_DBGCTRL_DBGRUN_Pos; + ((Adc *)hw)->DBGCTRL.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg &= ~ADC_DBGCTRL_DBGRUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg ^= ADC_DBGCTRL_DBGRUN; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_dbgctrl_reg_t hri_adc_get_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DBGCTRL_reg(const void *const hw, hri_adc_dbgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DBGCTRL.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_dbgctrl_reg_t hri_adc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Adc *)hw)->DBGCTRL.reg; +} + +static inline void hri_adc_set_INPUTCTRL_DIFFMODE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_DIFFMODE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_INPUTCTRL_DIFFMODE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_DIFFMODE) >> ADC_INPUTCTRL_DIFFMODE_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_INPUTCTRL_DIFFMODE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= ~ADC_INPUTCTRL_DIFFMODE; + tmp |= value << ADC_INPUTCTRL_DIFFMODE_Pos; + ((Adc *)hw)->INPUTCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_DIFFMODE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_DIFFMODE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_DIFFMODE_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_DIFFMODE; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_INPUTCTRL_DSEQSTOP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_DSEQSTOP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_INPUTCTRL_DSEQSTOP_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_DSEQSTOP) >> ADC_INPUTCTRL_DSEQSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_INPUTCTRL_DSEQSTOP_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= ~ADC_INPUTCTRL_DSEQSTOP; + tmp |= value << ADC_INPUTCTRL_DSEQSTOP_Pos; + ((Adc *)hw)->INPUTCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_DSEQSTOP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_DSEQSTOP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_DSEQSTOP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_DSEQSTOP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXPOS(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXPOS_bf(const void *const hw, + hri_adc_inputctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXPOS(mask)) >> ADC_INPUTCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_adc_write_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= ~ADC_INPUTCTRL_MUXPOS_Msk; + tmp |= ADC_INPUTCTRL_MUXPOS(data); + ((Adc *)hw)->INPUTCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXPOS(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_MUXPOS_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXPOS(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXPOS_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXPOS_Msk) >> ADC_INPUTCTRL_MUXPOS_Pos; + return tmp; +} + +static inline void hri_adc_set_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= ADC_INPUTCTRL_MUXNEG(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_MUXNEG_bf(const void *const hw, + hri_adc_inputctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXNEG(mask)) >> ADC_INPUTCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_adc_write_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= ~ADC_INPUTCTRL_MUXNEG_Msk; + tmp |= ADC_INPUTCTRL_MUXNEG(data); + ((Adc *)hw)->INPUTCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~ADC_INPUTCTRL_MUXNEG(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_MUXNEG_bf(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= ADC_INPUTCTRL_MUXNEG(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_MUXNEG_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp = (tmp & ADC_INPUTCTRL_MUXNEG_Msk) >> ADC_INPUTCTRL_MUXNEG_Pos; + return tmp; +} + +static inline void hri_adc_set_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_get_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->INPUTCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_INPUTCTRL_reg(const void *const hw, hri_adc_inputctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->INPUTCTRL.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_inputctrl_reg_t hri_adc_read_INPUTCTRL_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->INPUTCTRL.reg; +} + +static inline void hri_adc_set_CTRLB_LEFTADJ_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_LEFTADJ; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLB_LEFTADJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_LEFTADJ) >> ADC_CTRLB_LEFTADJ_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLB_LEFTADJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_LEFTADJ; + tmp |= value << ADC_CTRLB_LEFTADJ_Pos; + ((Adc *)hw)->CTRLB.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_LEFTADJ_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_LEFTADJ; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_LEFTADJ_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_LEFTADJ; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLB_FREERUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_FREERUN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLB_FREERUN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_FREERUN) >> ADC_CTRLB_FREERUN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLB_FREERUN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_FREERUN; + tmp |= value << ADC_CTRLB_FREERUN_Pos; + ((Adc *)hw)->CTRLB.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_FREERUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_FREERUN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_FREERUN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_FREERUN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLB_CORREN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_CORREN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLB_CORREN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_CORREN) >> ADC_CTRLB_CORREN_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLB_CORREN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_CORREN; + tmp |= value << ADC_CTRLB_CORREN_Pos; + ((Adc *)hw)->CTRLB.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_CORREN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_CORREN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_CORREN_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_CORREN; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLB_WINSS_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_WINSS; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_CTRLB_WINSS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_WINSS) >> ADC_CTRLB_WINSS_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_CTRLB_WINSS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_WINSS; + tmp |= value << ADC_CTRLB_WINSS_Pos; + ((Adc *)hw)->CTRLB.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_WINSS_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_WINSS; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_WINSS_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_WINSS; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_RESSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_RESSEL(mask)) >> ADC_CTRLB_RESSEL_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_RESSEL_Msk; + tmp |= ADC_CTRLB_RESSEL(data); + ((Adc *)hw)->CTRLB.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_RESSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_RESSEL_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_RESSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_RESSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_RESSEL_Msk) >> ADC_CTRLB_RESSEL_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= ADC_CTRLB_WINMODE(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_WINMODE(mask)) >> ADC_CTRLB_WINMODE_Pos; + return tmp; +} + +static inline void hri_adc_write_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= ~ADC_CTRLB_WINMODE_Msk; + tmp |= ADC_CTRLB_WINMODE(data); + ((Adc *)hw)->CTRLB.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~ADC_CTRLB_WINMODE(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_WINMODE_bf(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= ADC_CTRLB_WINMODE(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_WINMODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CTRLB.reg; + tmp = (tmp & ADC_CTRLB_WINMODE_Msk) >> ADC_CTRLB_WINMODE_Pos; + return tmp; +} + +static inline void hri_adc_set_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_get_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CTRLB_reg(const void *const hw, hri_adc_ctrlb_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CTRLB.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_ctrlb_reg_t hri_adc_read_CTRLB_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->CTRLB.reg; +} + +static inline void hri_adc_set_REFCTRL_REFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_REFCTRL_REFCOMP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp = (tmp & ADC_REFCTRL_REFCOMP) >> ADC_REFCTRL_REFCOMP_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_REFCTRL_REFCOMP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp &= ~ADC_REFCTRL_REFCOMP; + tmp |= value << ADC_REFCTRL_REFCOMP_Pos; + ((Adc *)hw)->REFCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_REFCTRL_REFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_REFCTRL_REFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg |= ADC_REFCTRL_REFSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp = (tmp & ADC_REFCTRL_REFSEL(mask)) >> ADC_REFCTRL_REFSEL_Pos; + return tmp; +} + +static inline void hri_adc_write_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp &= ~ADC_REFCTRL_REFSEL_Msk; + tmp |= ADC_REFCTRL_REFSEL(data); + ((Adc *)hw)->REFCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg &= ~ADC_REFCTRL_REFSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_REFCTRL_REFSEL_bf(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg ^= ADC_REFCTRL_REFSEL(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_REFSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp = (tmp & ADC_REFCTRL_REFSEL_Msk) >> ADC_REFCTRL_REFSEL_Pos; + return tmp; +} + +static inline void hri_adc_set_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_get_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->REFCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_REFCTRL_reg(const void *const hw, hri_adc_refctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->REFCTRL.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_refctrl_reg_t hri_adc_read_REFCTRL_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->REFCTRL.reg; +} + +static inline void hri_adc_set_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_SAMPLENUM(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_SAMPLENUM(mask)) >> ADC_AVGCTRL_SAMPLENUM_Pos; + return tmp; +} + +static inline void hri_adc_write_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp &= ~ADC_AVGCTRL_SAMPLENUM_Msk; + tmp |= ADC_AVGCTRL_SAMPLENUM(data); + ((Adc *)hw)->AVGCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_SAMPLENUM(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_AVGCTRL_SAMPLENUM_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_SAMPLENUM(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_SAMPLENUM_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_SAMPLENUM_Msk) >> ADC_AVGCTRL_SAMPLENUM_Pos; + return tmp; +} + +static inline void hri_adc_set_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg |= ADC_AVGCTRL_ADJRES(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_ADJRES(mask)) >> ADC_AVGCTRL_ADJRES_Pos; + return tmp; +} + +static inline void hri_adc_write_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp &= ~ADC_AVGCTRL_ADJRES_Msk; + tmp |= ADC_AVGCTRL_ADJRES(data); + ((Adc *)hw)->AVGCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg &= ~ADC_AVGCTRL_ADJRES(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_AVGCTRL_ADJRES_bf(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg ^= ADC_AVGCTRL_ADJRES(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_ADJRES_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp = (tmp & ADC_AVGCTRL_ADJRES_Msk) >> ADC_AVGCTRL_ADJRES_Pos; + return tmp; +} + +static inline void hri_adc_set_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_get_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->AVGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_AVGCTRL_reg(const void *const hw, hri_adc_avgctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->AVGCTRL.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_avgctrl_reg_t hri_adc_read_AVGCTRL_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->AVGCTRL.reg; +} + +static inline void hri_adc_set_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_OFFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp = (tmp & ADC_SAMPCTRL_OFFCOMP) >> ADC_SAMPCTRL_OFFCOMP_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_SAMPCTRL_OFFCOMP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp &= ~ADC_SAMPCTRL_OFFCOMP; + tmp |= value << ADC_SAMPCTRL_OFFCOMP_Pos; + ((Adc *)hw)->SAMPCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_OFFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SAMPCTRL_OFFCOMP_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_OFFCOMP; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg |= ADC_SAMPCTRL_SAMPLEN(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp = (tmp & ADC_SAMPCTRL_SAMPLEN(mask)) >> ADC_SAMPCTRL_SAMPLEN_Pos; + return tmp; +} + +static inline void hri_adc_write_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t data) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp &= ~ADC_SAMPCTRL_SAMPLEN_Msk; + tmp |= ADC_SAMPCTRL_SAMPLEN(data); + ((Adc *)hw)->SAMPCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg &= ~ADC_SAMPCTRL_SAMPLEN(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SAMPCTRL_SAMPLEN_bf(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg ^= ADC_SAMPCTRL_SAMPLEN(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_SAMPLEN_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp = (tmp & ADC_SAMPCTRL_SAMPLEN_Msk) >> ADC_SAMPCTRL_SAMPLEN_Pos; + return tmp; +} + +static inline void hri_adc_set_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_get_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->SAMPCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SAMPCTRL_reg(const void *const hw, hri_adc_sampctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SAMPCTRL.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_sampctrl_reg_t hri_adc_read_SAMPCTRL_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->SAMPCTRL.reg; +} + +static inline void hri_adc_set_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg |= ADC_WINLT_WINLT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + tmp = ((Adc *)hw)->WINLT.reg; + tmp = (tmp & ADC_WINLT_WINLT(mask)) >> ADC_WINLT_WINLT_Pos; + return tmp; +} + +static inline void hri_adc_write_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->WINLT.reg; + tmp &= ~ADC_WINLT_WINLT_Msk; + tmp |= ADC_WINLT_WINLT(data); + ((Adc *)hw)->WINLT.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg &= ~ADC_WINLT_WINLT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINLT_WINLT_bf(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg ^= ADC_WINLT_WINLT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_WINLT_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + tmp = ((Adc *)hw)->WINLT.reg; + tmp = (tmp & ADC_WINLT_WINLT_Msk) >> ADC_WINLT_WINLT_Pos; + return tmp; +} + +static inline void hri_adc_set_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_get_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + tmp = ((Adc *)hw)->WINLT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINLT_reg(const void *const hw, hri_adc_winlt_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINLT.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winlt_reg_t hri_adc_read_WINLT_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINLT); + return ((Adc *)hw)->WINLT.reg; +} + +static inline void hri_adc_set_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg |= ADC_WINUT_WINUT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_get_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + tmp = ((Adc *)hw)->WINUT.reg; + tmp = (tmp & ADC_WINUT_WINUT(mask)) >> ADC_WINUT_WINUT_Pos; + return tmp; +} + +static inline void hri_adc_write_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->WINUT.reg; + tmp &= ~ADC_WINUT_WINUT_Msk; + tmp |= ADC_WINUT_WINUT(data); + ((Adc *)hw)->WINUT.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg &= ~ADC_WINUT_WINUT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINUT_WINUT_bf(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg ^= ADC_WINUT_WINUT(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_read_WINUT_WINUT_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + tmp = ((Adc *)hw)->WINUT.reg; + tmp = (tmp & ADC_WINUT_WINUT_Msk) >> ADC_WINUT_WINUT_Pos; + return tmp; +} + +static inline void hri_adc_set_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_get_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + tmp = ((Adc *)hw)->WINUT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_WINUT_reg(const void *const hw, hri_adc_winut_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_WINUT_reg(const void *const hw, hri_adc_winut_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->WINUT.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_winut_reg_t hri_adc_read_WINUT_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_WINUT); + return ((Adc *)hw)->WINUT.reg; +} + +static inline void hri_adc_set_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg |= ADC_GAINCORR_GAINCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp = (tmp & ADC_GAINCORR_GAINCORR(mask)) >> ADC_GAINCORR_GAINCORR_Pos; + return tmp; +} + +static inline void hri_adc_write_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp &= ~ADC_GAINCORR_GAINCORR_Msk; + tmp |= ADC_GAINCORR_GAINCORR(data); + ((Adc *)hw)->GAINCORR.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg &= ~ADC_GAINCORR_GAINCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_GAINCORR_GAINCORR_bf(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg ^= ADC_GAINCORR_GAINCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_GAINCORR_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp = (tmp & ADC_GAINCORR_GAINCORR_Msk) >> ADC_GAINCORR_GAINCORR_Pos; + return tmp; +} + +static inline void hri_adc_set_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_get_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + tmp = ((Adc *)hw)->GAINCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_GAINCORR_reg(const void *const hw, hri_adc_gaincorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->GAINCORR.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_gaincorr_reg_t hri_adc_read_GAINCORR_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_GAINCORR); + return ((Adc *)hw)->GAINCORR.reg; +} + +static inline void hri_adc_set_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg |= ADC_OFFSETCORR_OFFSETCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_OFFSETCORR_bf(const void *const hw, + hri_adc_offsetcorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR(mask)) >> ADC_OFFSETCORR_OFFSETCORR_Pos; + return tmp; +} + +static inline void hri_adc_write_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp &= ~ADC_OFFSETCORR_OFFSETCORR_Msk; + tmp |= ADC_OFFSETCORR_OFFSETCORR(data); + ((Adc *)hw)->OFFSETCORR.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg &= ~ADC_OFFSETCORR_OFFSETCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_OFFSETCORR_OFFSETCORR_bf(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg ^= ADC_OFFSETCORR_OFFSETCORR(mask); + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_OFFSETCORR_bf(const void *const hw) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp = (tmp & ADC_OFFSETCORR_OFFSETCORR_Msk) >> ADC_OFFSETCORR_OFFSETCORR_Pos; + return tmp; +} + +static inline void hri_adc_set_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_get_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + uint16_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->OFFSETCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_OFFSETCORR_reg(const void *const hw, hri_adc_offsetcorr_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->OFFSETCORR.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_offsetcorr_reg_t hri_adc_read_OFFSETCORR_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_OFFSETCORR); + return ((Adc *)hw)->OFFSETCORR.reg; +} + +static inline void hri_adc_set_SWTRIG_FLUSH_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_FLUSH; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_SWTRIG_FLUSH_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp = (tmp & ADC_SWTRIG_FLUSH) >> ADC_SWTRIG_FLUSH_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_SWTRIG_FLUSH_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp &= ~ADC_SWTRIG_FLUSH; + tmp |= value << ADC_SWTRIG_FLUSH_Pos; + ((Adc *)hw)->SWTRIG.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SWTRIG_FLUSH_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_FLUSH; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SWTRIG_FLUSH_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_FLUSH; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_SWTRIG_START_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg |= ADC_SWTRIG_START; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_SWTRIG_START_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp = (tmp & ADC_SWTRIG_START) >> ADC_SWTRIG_START_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_SWTRIG_START_bit(const void *const hw, bool value) +{ + uint8_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp &= ~ADC_SWTRIG_START; + tmp |= value << ADC_SWTRIG_START_Pos; + ((Adc *)hw)->SWTRIG.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SWTRIG_START_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg &= ~ADC_SWTRIG_START; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SWTRIG_START_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg ^= ADC_SWTRIG_START; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg |= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_swtrig_reg_t hri_adc_get_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + uint8_t tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + tmp = ((Adc *)hw)->SWTRIG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg = data; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg &= ~mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_SWTRIG_reg(const void *const hw, hri_adc_swtrig_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->SWTRIG.reg ^= mask; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_swtrig_reg_t hri_adc_read_SWTRIG_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + return ((Adc *)hw)->SWTRIG.reg; +} + +static inline void hri_adc_set_DSEQCTRL_INPUTCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_INPUTCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_INPUTCTRL_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_INPUTCTRL) >> ADC_DSEQCTRL_INPUTCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_INPUTCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_INPUTCTRL; + tmp |= value << ADC_DSEQCTRL_INPUTCTRL_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_INPUTCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_INPUTCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_INPUTCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_INPUTCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_CTRLB_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_CTRLB; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_CTRLB_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_CTRLB) >> ADC_DSEQCTRL_CTRLB_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_CTRLB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_CTRLB; + tmp |= value << ADC_DSEQCTRL_CTRLB_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_CTRLB_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_CTRLB; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_CTRLB_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_CTRLB; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_REFCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_REFCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_REFCTRL_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_REFCTRL) >> ADC_DSEQCTRL_REFCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_REFCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_REFCTRL; + tmp |= value << ADC_DSEQCTRL_REFCTRL_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_REFCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_REFCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_REFCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_REFCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_AVGCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_AVGCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_AVGCTRL_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_AVGCTRL) >> ADC_DSEQCTRL_AVGCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_AVGCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_AVGCTRL; + tmp |= value << ADC_DSEQCTRL_AVGCTRL_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_AVGCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_AVGCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_AVGCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_AVGCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_SAMPCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_SAMPCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_SAMPCTRL_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_SAMPCTRL) >> ADC_DSEQCTRL_SAMPCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_SAMPCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_SAMPCTRL; + tmp |= value << ADC_DSEQCTRL_SAMPCTRL_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_SAMPCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_SAMPCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_SAMPCTRL_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_SAMPCTRL; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_WINLT_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_WINLT; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_WINLT_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_WINLT) >> ADC_DSEQCTRL_WINLT_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_WINLT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_WINLT; + tmp |= value << ADC_DSEQCTRL_WINLT_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_WINLT_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_WINLT; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_WINLT_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_WINLT; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_WINUT_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_WINUT; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_WINUT_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_WINUT) >> ADC_DSEQCTRL_WINUT_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_WINUT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_WINUT; + tmp |= value << ADC_DSEQCTRL_WINUT_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_WINUT_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_WINUT; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_WINUT_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_WINUT; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_GAINCORR_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_GAINCORR; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_GAINCORR_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_GAINCORR) >> ADC_DSEQCTRL_GAINCORR_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_GAINCORR_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_GAINCORR; + tmp |= value << ADC_DSEQCTRL_GAINCORR_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_GAINCORR_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_GAINCORR; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_GAINCORR_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_GAINCORR; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_OFFSETCORR_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_OFFSETCORR; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_OFFSETCORR_bit(const void *const hw) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_OFFSETCORR) >> ADC_DSEQCTRL_OFFSETCORR_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_OFFSETCORR_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_OFFSETCORR; + tmp |= value << ADC_DSEQCTRL_OFFSETCORR_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_OFFSETCORR_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_OFFSETCORR; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_OFFSETCORR_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_OFFSETCORR; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_AUTOSTART_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= ADC_DSEQCTRL_AUTOSTART; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_adc_get_DSEQCTRL_AUTOSTART_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp = (tmp & ADC_DSEQCTRL_AUTOSTART) >> ADC_DSEQCTRL_AUTOSTART_Pos; + return (bool)tmp; +} + +static inline void hri_adc_write_DSEQCTRL_AUTOSTART_bit(const void *const hw, bool value) +{ + uint32_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= ~ADC_DSEQCTRL_AUTOSTART; + tmp |= value << ADC_DSEQCTRL_AUTOSTART_Pos; + ((Adc *)hw)->DSEQCTRL.reg = tmp; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_AUTOSTART_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~ADC_DSEQCTRL_AUTOSTART; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_AUTOSTART_bit(const void *const hw) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= ADC_DSEQCTRL_AUTOSTART; + hri_adc_wait_for_sync(hw, ADC_SYNCBUSY_MASK); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_set_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg |= mask; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_dseqctrl_reg_t hri_adc_get_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask) +{ + uint32_t tmp; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + tmp = ((Adc *)hw)->DSEQCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg = data; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg &= ~mask; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_DSEQCTRL_reg(const void *const hw, hri_adc_dseqctrl_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQCTRL.reg ^= mask; + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_dseqctrl_reg_t hri_adc_read_DSEQCTRL_reg(const void *const hw) +{ + hri_adc_wait_for_sync(hw, + ADC_SYNCBUSY_INPUTCTRL | ADC_SYNCBUSY_CTRLB | ADC_SYNCBUSY_REFCTRL | ADC_SYNCBUSY_AVGCTRL + | ADC_SYNCBUSY_SAMPCTRL | ADC_SYNCBUSY_WINLT | ADC_SYNCBUSY_WINUT | ADC_SYNCBUSY_GAINCORR + | ADC_SYNCBUSY_OFFSETCORR); + return ((Adc *)hw)->DSEQCTRL.reg; +} + +static inline void hri_adc_set_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASCOMP(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASCOMP(mask)) >> ADC_CALIB_BIASCOMP_Pos; + return tmp; +} + +static inline void hri_adc_write_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= ~ADC_CALIB_BIASCOMP_Msk; + tmp |= ADC_CALIB_BIASCOMP(data); + ((Adc *)hw)->CALIB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASCOMP(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_BIASCOMP_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASCOMP(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASCOMP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASCOMP_Msk) >> ADC_CALIB_BIASCOMP_Pos; + return tmp; +} + +static inline void hri_adc_set_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASR2R(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASR2R(mask)) >> ADC_CALIB_BIASR2R_Pos; + return tmp; +} + +static inline void hri_adc_write_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= ~ADC_CALIB_BIASR2R_Msk; + tmp |= ADC_CALIB_BIASR2R(data); + ((Adc *)hw)->CALIB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASR2R(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_BIASR2R_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASR2R(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASR2R_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASR2R_Msk) >> ADC_CALIB_BIASR2R_Pos; + return tmp; +} + +static inline void hri_adc_set_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= ADC_CALIB_BIASREFBUF(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASREFBUF(mask)) >> ADC_CALIB_BIASREFBUF_Pos; + return tmp; +} + +static inline void hri_adc_write_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t data) +{ + uint16_t tmp; + ADC_CRITICAL_SECTION_ENTER(); + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= ~ADC_CALIB_BIASREFBUF_Msk; + tmp |= ADC_CALIB_BIASREFBUF(data); + ((Adc *)hw)->CALIB.reg = tmp; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~ADC_CALIB_BIASREFBUF(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_BIASREFBUF_bf(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= ADC_CALIB_BIASREFBUF(mask); + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_BIASREFBUF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp = (tmp & ADC_CALIB_BIASREFBUF_Msk) >> ADC_CALIB_BIASREFBUF_Pos; + return tmp; +} + +static inline void hri_adc_set_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg |= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_get_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + uint16_t tmp; + tmp = ((Adc *)hw)->CALIB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_adc_write_CALIB_reg(const void *const hw, hri_adc_calib_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_clear_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg &= ~mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_adc_toggle_CALIB_reg(const void *const hw, hri_adc_calib_reg_t mask) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->CALIB.reg ^= mask; + ADC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_adc_calib_reg_t hri_adc_read_CALIB_reg(const void *const hw) +{ + return ((Adc *)hw)->CALIB.reg; +} + +static inline void hri_adc_write_DSEQDATA_reg(const void *const hw, hri_adc_dseqdata_reg_t data) +{ + ADC_CRITICAL_SECTION_ENTER(); + ((Adc *)hw)->DSEQDATA.reg = data; + ADC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_ADC_E54_H_INCLUDED */ +#endif /* _SAME54_ADC_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_aes_e54.h b/software/firmware/oracle_same54n19a/hri/hri_aes_e54.h new file mode 100644 index 00000000..c1070e2a --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_aes_e54.h @@ -0,0 +1,1287 @@ +/** + * \file + * + * \brief SAM AES + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_AES_COMPONENT_ +#ifndef _HRI_AES_E54_H_INCLUDED_ +#define _HRI_AES_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_AES_CRITICAL_SECTIONS) +#define AES_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define AES_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define AES_CRITICAL_SECTION_ENTER() +#define AES_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_aes_ciplen_reg_t; +typedef uint32_t hri_aes_ctrla_reg_t; +typedef uint32_t hri_aes_ghash_reg_t; +typedef uint32_t hri_aes_hashkey_reg_t; +typedef uint32_t hri_aes_indata_reg_t; +typedef uint32_t hri_aes_intvectv_reg_t; +typedef uint32_t hri_aes_keyword_reg_t; +typedef uint32_t hri_aes_randseed_reg_t; +typedef uint8_t hri_aes_ctrlb_reg_t; +typedef uint8_t hri_aes_databufptr_reg_t; +typedef uint8_t hri_aes_dbgctrl_reg_t; +typedef uint8_t hri_aes_intenset_reg_t; +typedef uint8_t hri_aes_intflag_reg_t; + +static inline bool hri_aes_get_INTFLAG_ENCCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_ENCCMP) >> AES_INTFLAG_ENCCMP_Pos; +} + +static inline void hri_aes_clear_INTFLAG_ENCCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_ENCCMP; +} + +static inline bool hri_aes_get_INTFLAG_GFMCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_GFMCMP) >> AES_INTFLAG_GFMCMP_Pos; +} + +static inline void hri_aes_clear_INTFLAG_GFMCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_GFMCMP; +} + +static inline bool hri_aes_get_interrupt_ENCCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_ENCCMP) >> AES_INTFLAG_ENCCMP_Pos; +} + +static inline void hri_aes_clear_interrupt_ENCCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_ENCCMP; +} + +static inline bool hri_aes_get_interrupt_GFMCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTFLAG.reg & AES_INTFLAG_GFMCMP) >> AES_INTFLAG_GFMCMP_Pos; +} + +static inline void hri_aes_clear_interrupt_GFMCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTFLAG.reg = AES_INTFLAG_GFMCMP; +} + +static inline hri_aes_intflag_reg_t hri_aes_get_INTFLAG_reg(const void *const hw, hri_aes_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_aes_intflag_reg_t hri_aes_read_INTFLAG_reg(const void *const hw) +{ + return ((Aes *)hw)->INTFLAG.reg; +} + +static inline void hri_aes_clear_INTFLAG_reg(const void *const hw, hri_aes_intflag_reg_t mask) +{ + ((Aes *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_aes_set_INTEN_ENCCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP; +} + +static inline bool hri_aes_get_INTEN_ENCCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_ENCCMP) >> AES_INTENSET_ENCCMP_Pos; +} + +static inline void hri_aes_write_INTEN_ENCCMP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP; + } else { + ((Aes *)hw)->INTENSET.reg = AES_INTENSET_ENCCMP; + } +} + +static inline void hri_aes_clear_INTEN_ENCCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_ENCCMP; +} + +static inline void hri_aes_set_INTEN_GFMCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP; +} + +static inline bool hri_aes_get_INTEN_GFMCMP_bit(const void *const hw) +{ + return (((Aes *)hw)->INTENSET.reg & AES_INTENSET_GFMCMP) >> AES_INTENSET_GFMCMP_Pos; +} + +static inline void hri_aes_write_INTEN_GFMCMP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP; + } else { + ((Aes *)hw)->INTENSET.reg = AES_INTENSET_GFMCMP; + } +} + +static inline void hri_aes_clear_INTEN_GFMCMP_bit(const void *const hw) +{ + ((Aes *)hw)->INTENCLR.reg = AES_INTENSET_GFMCMP; +} + +static inline void hri_aes_set_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) +{ + ((Aes *)hw)->INTENSET.reg = mask; +} + +static inline hri_aes_intenset_reg_t hri_aes_get_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_aes_intenset_reg_t hri_aes_read_INTEN_reg(const void *const hw) +{ + return ((Aes *)hw)->INTENSET.reg; +} + +static inline void hri_aes_write_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t data) +{ + ((Aes *)hw)->INTENSET.reg = data; + ((Aes *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_aes_clear_INTEN_reg(const void *const hw, hri_aes_intenset_reg_t mask) +{ + ((Aes *)hw)->INTENCLR.reg = mask; +} + +static inline void hri_aes_set_CTRLA_SWRST_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_SWRST; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_SWRST) >> AES_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_aes_set_CTRLA_ENABLE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_ENABLE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_ENABLE) >> AES_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_ENABLE; + tmp |= value << AES_CTRLA_ENABLE_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_ENABLE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_ENABLE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_CIPHER_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CIPHER; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_CIPHER_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CIPHER) >> AES_CTRLA_CIPHER_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_CIPHER_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_CIPHER; + tmp |= value << AES_CTRLA_CIPHER_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_CIPHER_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CIPHER; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_CIPHER_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CIPHER; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_STARTMODE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_STARTMODE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_STARTMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_STARTMODE) >> AES_CTRLA_STARTMODE_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_STARTMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_STARTMODE; + tmp |= value << AES_CTRLA_STARTMODE_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_STARTMODE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_STARTMODE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_STARTMODE_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_STARTMODE; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_LOD_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_LOD; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_LOD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_LOD) >> AES_CTRLA_LOD_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_LOD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_LOD; + tmp |= value << AES_CTRLA_LOD_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_LOD_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_LOD; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_LOD_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_LOD; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_KEYGEN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_KEYGEN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_KEYGEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_KEYGEN) >> AES_CTRLA_KEYGEN_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_KEYGEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_KEYGEN; + tmp |= value << AES_CTRLA_KEYGEN_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_KEYGEN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_KEYGEN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_KEYGEN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_KEYGEN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_XORKEY_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_XORKEY; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLA_XORKEY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_XORKEY) >> AES_CTRLA_XORKEY_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLA_XORKEY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_XORKEY; + tmp |= value << AES_CTRLA_XORKEY_Pos; + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_XORKEY_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_XORKEY; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_XORKEY_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_XORKEY; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_AESMODE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_AESMODE(mask)) >> AES_CTRLA_AESMODE_Pos; + return tmp; +} + +static inline void hri_aes_write_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_AESMODE_Msk; + tmp |= AES_CTRLA_AESMODE(data); + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_AESMODE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_AESMODE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_AESMODE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_AESMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_AESMODE_Msk) >> AES_CTRLA_AESMODE_Pos; + return tmp; +} + +static inline void hri_aes_set_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CFBS(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CFBS(mask)) >> AES_CTRLA_CFBS_Pos; + return tmp; +} + +static inline void hri_aes_write_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_CFBS_Msk; + tmp |= AES_CTRLA_CFBS(data); + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CFBS(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_CFBS_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CFBS(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_CFBS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CFBS_Msk) >> AES_CTRLA_CFBS_Pos; + return tmp; +} + +static inline void hri_aes_set_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_KEYSIZE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_KEYSIZE(mask)) >> AES_CTRLA_KEYSIZE_Pos; + return tmp; +} + +static inline void hri_aes_write_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_KEYSIZE_Msk; + tmp |= AES_CTRLA_KEYSIZE(data); + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_KEYSIZE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_KEYSIZE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_KEYSIZE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_KEYSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_KEYSIZE_Msk) >> AES_CTRLA_KEYSIZE_Pos; + return tmp; +} + +static inline void hri_aes_set_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= AES_CTRLA_CTYPE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CTYPE(mask)) >> AES_CTRLA_CTYPE_Pos; + return tmp; +} + +static inline void hri_aes_write_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t data) +{ + uint32_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= ~AES_CTRLA_CTYPE_Msk; + tmp |= AES_CTRLA_CTYPE(data); + ((Aes *)hw)->CTRLA.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~AES_CTRLA_CTYPE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_CTYPE_bf(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= AES_CTRLA_CTYPE(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_CTYPE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp = (tmp & AES_CTRLA_CTYPE_Msk) >> AES_CTRLA_CTYPE_Pos; + return tmp; +} + +static inline void hri_aes_set_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_get_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLA_reg(const void *const hw, hri_aes_ctrla_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLA.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrla_reg_t hri_aes_read_CTRLA_reg(const void *const hw) +{ + return ((Aes *)hw)->CTRLA.reg; +} + +static inline void hri_aes_set_CTRLB_START_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_START; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLB_START_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp = (tmp & AES_CTRLB_START) >> AES_CTRLB_START_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLB_START_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= ~AES_CTRLB_START; + tmp |= value << AES_CTRLB_START_Pos; + ((Aes *)hw)->CTRLB.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_START_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_START; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_START_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_START; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLB_NEWMSG_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_NEWMSG; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLB_NEWMSG_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp = (tmp & AES_CTRLB_NEWMSG) >> AES_CTRLB_NEWMSG_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLB_NEWMSG_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= ~AES_CTRLB_NEWMSG; + tmp |= value << AES_CTRLB_NEWMSG_Pos; + ((Aes *)hw)->CTRLB.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_NEWMSG_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_NEWMSG; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_NEWMSG_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_NEWMSG; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLB_EOM_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_EOM; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLB_EOM_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp = (tmp & AES_CTRLB_EOM) >> AES_CTRLB_EOM_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLB_EOM_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= ~AES_CTRLB_EOM; + tmp |= value << AES_CTRLB_EOM_Pos; + ((Aes *)hw)->CTRLB.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_EOM_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_EOM; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_EOM_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_EOM; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLB_GFMUL_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= AES_CTRLB_GFMUL; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_CTRLB_GFMUL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp = (tmp & AES_CTRLB_GFMUL) >> AES_CTRLB_GFMUL_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_CTRLB_GFMUL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= ~AES_CTRLB_GFMUL; + tmp |= value << AES_CTRLB_GFMUL_Pos; + ((Aes *)hw)->CTRLB.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_GFMUL_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~AES_CTRLB_GFMUL; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_GFMUL_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= AES_CTRLB_GFMUL; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrlb_reg_t hri_aes_get_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CTRLB_reg(const void *const hw, hri_aes_ctrlb_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CTRLB.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ctrlb_reg_t hri_aes_read_CTRLB_reg(const void *const hw) +{ + return ((Aes *)hw)->CTRLB.reg; +} + +static inline void hri_aes_set_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg |= AES_DATABUFPTR_INDATAPTR(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_databufptr_reg_t hri_aes_get_DATABUFPTR_INDATAPTR_bf(const void *const hw, + hri_aes_databufptr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->DATABUFPTR.reg; + tmp = (tmp & AES_DATABUFPTR_INDATAPTR(mask)) >> AES_DATABUFPTR_INDATAPTR_Pos; + return tmp; +} + +static inline void hri_aes_write_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t data) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->DATABUFPTR.reg; + tmp &= ~AES_DATABUFPTR_INDATAPTR_Msk; + tmp |= AES_DATABUFPTR_INDATAPTR(data); + ((Aes *)hw)->DATABUFPTR.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg &= ~AES_DATABUFPTR_INDATAPTR(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_DATABUFPTR_INDATAPTR_bf(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg ^= AES_DATABUFPTR_INDATAPTR(mask); + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_databufptr_reg_t hri_aes_read_DATABUFPTR_INDATAPTR_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->DATABUFPTR.reg; + tmp = (tmp & AES_DATABUFPTR_INDATAPTR_Msk) >> AES_DATABUFPTR_INDATAPTR_Pos; + return tmp; +} + +static inline void hri_aes_set_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_databufptr_reg_t hri_aes_get_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->DATABUFPTR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_DATABUFPTR_reg(const void *const hw, hri_aes_databufptr_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DATABUFPTR.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_databufptr_reg_t hri_aes_read_DATABUFPTR_reg(const void *const hw) +{ + return ((Aes *)hw)->DATABUFPTR.reg; +} + +static inline void hri_aes_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg |= AES_DBGCTRL_DBGRUN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_aes_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->DBGCTRL.reg; + tmp = (tmp & AES_DBGCTRL_DBGRUN) >> AES_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_aes_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + AES_CRITICAL_SECTION_ENTER(); + tmp = ((Aes *)hw)->DBGCTRL.reg; + tmp &= ~AES_DBGCTRL_DBGRUN; + tmp |= value << AES_DBGCTRL_DBGRUN_Pos; + ((Aes *)hw)->DBGCTRL.reg = tmp; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg &= ~AES_DBGCTRL_DBGRUN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg ^= AES_DBGCTRL_DBGRUN; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_set_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_dbgctrl_reg_t hri_aes_get_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Aes *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_DBGCTRL_reg(const void *const hw, hri_aes_dbgctrl_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->DBGCTRL.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_dbgctrl_reg_t hri_aes_read_DBGCTRL_reg(const void *const hw) +{ + return ((Aes *)hw)->DBGCTRL.reg; +} + +static inline void hri_aes_set_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INDATA.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_indata_reg_t hri_aes_get_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->INDATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_INDATA_reg(const void *const hw, hri_aes_indata_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INDATA.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INDATA.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_INDATA_reg(const void *const hw, hri_aes_indata_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INDATA.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_indata_reg_t hri_aes_read_INDATA_reg(const void *const hw) +{ + return ((Aes *)hw)->INDATA.reg; +} + +static inline void hri_aes_set_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->HASHKEY[index].reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_hashkey_reg_t hri_aes_get_HASHKEY_reg(const void *const hw, uint8_t index, + hri_aes_hashkey_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->HASHKEY[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->HASHKEY[index].reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->HASHKEY[index].reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_HASHKEY_reg(const void *const hw, uint8_t index, hri_aes_hashkey_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->HASHKEY[index].reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_hashkey_reg_t hri_aes_read_HASHKEY_reg(const void *const hw, uint8_t index) +{ + return ((Aes *)hw)->HASHKEY[index].reg; +} + +static inline void hri_aes_set_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->GHASH[index].reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ghash_reg_t hri_aes_get_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->GHASH[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->GHASH[index].reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->GHASH[index].reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_GHASH_reg(const void *const hw, uint8_t index, hri_aes_ghash_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->GHASH[index].reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ghash_reg_t hri_aes_read_GHASH_reg(const void *const hw, uint8_t index) +{ + return ((Aes *)hw)->GHASH[index].reg; +} + +static inline void hri_aes_set_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CIPLEN.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ciplen_reg_t hri_aes_get_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->CIPLEN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CIPLEN.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CIPLEN.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_CIPLEN_reg(const void *const hw, hri_aes_ciplen_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->CIPLEN.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_ciplen_reg_t hri_aes_read_CIPLEN_reg(const void *const hw) +{ + return ((Aes *)hw)->CIPLEN.reg; +} + +static inline void hri_aes_set_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->RANDSEED.reg |= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_randseed_reg_t hri_aes_get_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) +{ + uint32_t tmp; + tmp = ((Aes *)hw)->RANDSEED.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_aes_write_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->RANDSEED.reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_clear_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->RANDSEED.reg &= ~mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_toggle_RANDSEED_reg(const void *const hw, hri_aes_randseed_reg_t mask) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->RANDSEED.reg ^= mask; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_aes_randseed_reg_t hri_aes_read_RANDSEED_reg(const void *const hw) +{ + return ((Aes *)hw)->RANDSEED.reg; +} + +static inline void hri_aes_write_KEYWORD_reg(const void *const hw, uint8_t index, hri_aes_keyword_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->KEYWORD[index].reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_aes_write_INTVECTV_reg(const void *const hw, uint8_t index, hri_aes_intvectv_reg_t data) +{ + AES_CRITICAL_SECTION_ENTER(); + ((Aes *)hw)->INTVECTV[index].reg = data; + AES_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_AES_E54_H_INCLUDED */ +#endif /* _SAME54_AES_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_can_e54.h b/software/firmware/oracle_same54n19a/hri/hri_can_e54.h new file mode 100644 index 00000000..2c028846 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_can_e54.h @@ -0,0 +1,16997 @@ +/** + * \file + * + * \brief SAM CAN + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_CAN_COMPONENT_ +#ifndef _HRI_CAN_E54_H_INCLUDED_ +#define _HRI_CAN_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_CAN_CRITICAL_SECTIONS) +#define CAN_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define CAN_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define CAN_CRITICAL_SECTION_ENTER() +#define CAN_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_can_cccr_reg_t; +typedef uint32_t hri_can_crel_reg_t; +typedef uint32_t hri_can_dbtp_reg_t; +typedef uint32_t hri_can_ecr_reg_t; +typedef uint32_t hri_can_endn_reg_t; +typedef uint32_t hri_can_gfc_reg_t; +typedef uint32_t hri_can_hpms_reg_t; +typedef uint32_t hri_can_ie_reg_t; +typedef uint32_t hri_can_ile_reg_t; +typedef uint32_t hri_can_ils_reg_t; +typedef uint32_t hri_can_ir_reg_t; +typedef uint32_t hri_can_mrcfg_reg_t; +typedef uint32_t hri_can_nbtp_reg_t; +typedef uint32_t hri_can_ndat1_reg_t; +typedef uint32_t hri_can_ndat2_reg_t; +typedef uint32_t hri_can_psr_reg_t; +typedef uint32_t hri_can_rwd_reg_t; +typedef uint32_t hri_can_rxbc_reg_t; +typedef uint32_t hri_can_rxesc_reg_t; +typedef uint32_t hri_can_rxf0a_reg_t; +typedef uint32_t hri_can_rxf0c_reg_t; +typedef uint32_t hri_can_rxf0s_reg_t; +typedef uint32_t hri_can_rxf1a_reg_t; +typedef uint32_t hri_can_rxf1c_reg_t; +typedef uint32_t hri_can_rxf1s_reg_t; +typedef uint32_t hri_can_sidfc_reg_t; +typedef uint32_t hri_can_tdcr_reg_t; +typedef uint32_t hri_can_test_reg_t; +typedef uint32_t hri_can_tocc_reg_t; +typedef uint32_t hri_can_tocv_reg_t; +typedef uint32_t hri_can_tscc_reg_t; +typedef uint32_t hri_can_tscv_reg_t; +typedef uint32_t hri_can_txbar_reg_t; +typedef uint32_t hri_can_txbc_reg_t; +typedef uint32_t hri_can_txbcf_reg_t; +typedef uint32_t hri_can_txbcie_reg_t; +typedef uint32_t hri_can_txbcr_reg_t; +typedef uint32_t hri_can_txbrp_reg_t; +typedef uint32_t hri_can_txbtie_reg_t; +typedef uint32_t hri_can_txbto_reg_t; +typedef uint32_t hri_can_txefa_reg_t; +typedef uint32_t hri_can_txefc_reg_t; +typedef uint32_t hri_can_txefs_reg_t; +typedef uint32_t hri_can_txesc_reg_t; +typedef uint32_t hri_can_txfqs_reg_t; +typedef uint32_t hri_can_xidam_reg_t; +typedef uint32_t hri_can_xidfc_reg_t; + +static inline hri_can_crel_reg_t hri_can_get_CREL_SUBSTEP_bf(const void *const hw, hri_can_crel_reg_t mask) +{ + return (((Can *)hw)->CREL.reg & CAN_CREL_SUBSTEP(mask)) >> CAN_CREL_SUBSTEP_Pos; +} + +static inline hri_can_crel_reg_t hri_can_read_CREL_SUBSTEP_bf(const void *const hw) +{ + return (((Can *)hw)->CREL.reg & CAN_CREL_SUBSTEP_Msk) >> CAN_CREL_SUBSTEP_Pos; +} + +static inline hri_can_crel_reg_t hri_can_get_CREL_STEP_bf(const void *const hw, hri_can_crel_reg_t mask) +{ + return (((Can *)hw)->CREL.reg & CAN_CREL_STEP(mask)) >> CAN_CREL_STEP_Pos; +} + +static inline hri_can_crel_reg_t hri_can_read_CREL_STEP_bf(const void *const hw) +{ + return (((Can *)hw)->CREL.reg & CAN_CREL_STEP_Msk) >> CAN_CREL_STEP_Pos; +} + +static inline hri_can_crel_reg_t hri_can_get_CREL_REL_bf(const void *const hw, hri_can_crel_reg_t mask) +{ + return (((Can *)hw)->CREL.reg & CAN_CREL_REL(mask)) >> CAN_CREL_REL_Pos; +} + +static inline hri_can_crel_reg_t hri_can_read_CREL_REL_bf(const void *const hw) +{ + return (((Can *)hw)->CREL.reg & CAN_CREL_REL_Msk) >> CAN_CREL_REL_Pos; +} + +static inline hri_can_crel_reg_t hri_can_get_CREL_reg(const void *const hw, hri_can_crel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CREL.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_crel_reg_t hri_can_read_CREL_reg(const void *const hw) +{ + return ((Can *)hw)->CREL.reg; +} + +static inline hri_can_endn_reg_t hri_can_get_ENDN_ETV_bf(const void *const hw, hri_can_endn_reg_t mask) +{ + return (((Can *)hw)->ENDN.reg & CAN_ENDN_ETV(mask)) >> CAN_ENDN_ETV_Pos; +} + +static inline hri_can_endn_reg_t hri_can_read_ENDN_ETV_bf(const void *const hw) +{ + return (((Can *)hw)->ENDN.reg & CAN_ENDN_ETV_Msk) >> CAN_ENDN_ETV_Pos; +} + +static inline hri_can_endn_reg_t hri_can_get_ENDN_reg(const void *const hw, hri_can_endn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ENDN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_endn_reg_t hri_can_read_ENDN_reg(const void *const hw) +{ + return ((Can *)hw)->ENDN.reg; +} + +static inline hri_can_tscv_reg_t hri_can_get_TSCV_TSC_bf(const void *const hw, hri_can_tscv_reg_t mask) +{ + return (((Can *)hw)->TSCV.reg & CAN_TSCV_TSC(mask)) >> CAN_TSCV_TSC_Pos; +} + +static inline hri_can_tscv_reg_t hri_can_read_TSCV_TSC_bf(const void *const hw) +{ + return (((Can *)hw)->TSCV.reg & CAN_TSCV_TSC_Msk) >> CAN_TSCV_TSC_Pos; +} + +static inline hri_can_tscv_reg_t hri_can_get_TSCV_reg(const void *const hw, hri_can_tscv_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TSCV.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_tscv_reg_t hri_can_read_TSCV_reg(const void *const hw) +{ + return ((Can *)hw)->TSCV.reg; +} + +static inline bool hri_can_get_ECR_RP_bit(const void *const hw) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_RP) >> CAN_ECR_RP_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_get_ECR_TEC_bf(const void *const hw, hri_can_ecr_reg_t mask) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_TEC(mask)) >> CAN_ECR_TEC_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_read_ECR_TEC_bf(const void *const hw) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_TEC_Msk) >> CAN_ECR_TEC_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_get_ECR_REC_bf(const void *const hw, hri_can_ecr_reg_t mask) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_REC(mask)) >> CAN_ECR_REC_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_read_ECR_REC_bf(const void *const hw) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_REC_Msk) >> CAN_ECR_REC_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_get_ECR_CEL_bf(const void *const hw, hri_can_ecr_reg_t mask) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_CEL(mask)) >> CAN_ECR_CEL_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_read_ECR_CEL_bf(const void *const hw) +{ + return (((Can *)hw)->ECR.reg & CAN_ECR_CEL_Msk) >> CAN_ECR_CEL_Pos; +} + +static inline hri_can_ecr_reg_t hri_can_get_ECR_reg(const void *const hw, hri_can_ecr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ECR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_ecr_reg_t hri_can_read_ECR_reg(const void *const hw) +{ + return ((Can *)hw)->ECR.reg; +} + +static inline bool hri_can_get_PSR_EP_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_EP) >> CAN_PSR_EP_Pos; +} + +static inline bool hri_can_get_PSR_EW_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_EW) >> CAN_PSR_EW_Pos; +} + +static inline bool hri_can_get_PSR_BO_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_BO) >> CAN_PSR_BO_Pos; +} + +static inline bool hri_can_get_PSR_RESI_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_RESI) >> CAN_PSR_RESI_Pos; +} + +static inline bool hri_can_get_PSR_RBRS_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_RBRS) >> CAN_PSR_RBRS_Pos; +} + +static inline bool hri_can_get_PSR_RFDF_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_RFDF) >> CAN_PSR_RFDF_Pos; +} + +static inline bool hri_can_get_PSR_PXE_bit(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_PXE) >> CAN_PSR_PXE_Pos; +} + +static inline hri_can_psr_reg_t hri_can_get_PSR_LEC_bf(const void *const hw, hri_can_psr_reg_t mask) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_LEC(mask)) >> CAN_PSR_LEC_Pos; +} + +static inline hri_can_psr_reg_t hri_can_read_PSR_LEC_bf(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_LEC_Msk) >> CAN_PSR_LEC_Pos; +} + +static inline hri_can_psr_reg_t hri_can_get_PSR_ACT_bf(const void *const hw, hri_can_psr_reg_t mask) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_ACT(mask)) >> CAN_PSR_ACT_Pos; +} + +static inline hri_can_psr_reg_t hri_can_read_PSR_ACT_bf(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_ACT_Msk) >> CAN_PSR_ACT_Pos; +} + +static inline hri_can_psr_reg_t hri_can_get_PSR_DLEC_bf(const void *const hw, hri_can_psr_reg_t mask) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_DLEC(mask)) >> CAN_PSR_DLEC_Pos; +} + +static inline hri_can_psr_reg_t hri_can_read_PSR_DLEC_bf(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_DLEC_Msk) >> CAN_PSR_DLEC_Pos; +} + +static inline hri_can_psr_reg_t hri_can_get_PSR_TDCV_bf(const void *const hw, hri_can_psr_reg_t mask) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_TDCV(mask)) >> CAN_PSR_TDCV_Pos; +} + +static inline hri_can_psr_reg_t hri_can_read_PSR_TDCV_bf(const void *const hw) +{ + return (((Can *)hw)->PSR.reg & CAN_PSR_TDCV_Msk) >> CAN_PSR_TDCV_Pos; +} + +static inline hri_can_psr_reg_t hri_can_get_PSR_reg(const void *const hw, hri_can_psr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->PSR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_psr_reg_t hri_can_read_PSR_reg(const void *const hw) +{ + return ((Can *)hw)->PSR.reg; +} + +static inline bool hri_can_get_HPMS_FLST_bit(const void *const hw) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_FLST) >> CAN_HPMS_FLST_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_get_HPMS_BIDX_bf(const void *const hw, hri_can_hpms_reg_t mask) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_BIDX(mask)) >> CAN_HPMS_BIDX_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_read_HPMS_BIDX_bf(const void *const hw) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_BIDX_Msk) >> CAN_HPMS_BIDX_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_get_HPMS_MSI_bf(const void *const hw, hri_can_hpms_reg_t mask) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_MSI(mask)) >> CAN_HPMS_MSI_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_read_HPMS_MSI_bf(const void *const hw) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_MSI_Msk) >> CAN_HPMS_MSI_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_get_HPMS_FIDX_bf(const void *const hw, hri_can_hpms_reg_t mask) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_FIDX(mask)) >> CAN_HPMS_FIDX_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_read_HPMS_FIDX_bf(const void *const hw) +{ + return (((Can *)hw)->HPMS.reg & CAN_HPMS_FIDX_Msk) >> CAN_HPMS_FIDX_Pos; +} + +static inline hri_can_hpms_reg_t hri_can_get_HPMS_reg(const void *const hw, hri_can_hpms_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->HPMS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_hpms_reg_t hri_can_read_HPMS_reg(const void *const hw) +{ + return ((Can *)hw)->HPMS.reg; +} + +static inline bool hri_can_get_RXF0S_F0F_bit(const void *const hw) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0F) >> CAN_RXF0S_F0F_Pos; +} + +static inline bool hri_can_get_RXF0S_RF0L_bit(const void *const hw) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_RF0L) >> CAN_RXF0S_RF0L_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_F0FL_bf(const void *const hw, hri_can_rxf0s_reg_t mask) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0FL(mask)) >> CAN_RXF0S_F0FL_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_F0FL_bf(const void *const hw) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0FL_Msk) >> CAN_RXF0S_F0FL_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_F0GI_bf(const void *const hw, hri_can_rxf0s_reg_t mask) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0GI(mask)) >> CAN_RXF0S_F0GI_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_F0GI_bf(const void *const hw) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0GI_Msk) >> CAN_RXF0S_F0GI_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_F0PI_bf(const void *const hw, hri_can_rxf0s_reg_t mask) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0PI(mask)) >> CAN_RXF0S_F0PI_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_F0PI_bf(const void *const hw) +{ + return (((Can *)hw)->RXF0S.reg & CAN_RXF0S_F0PI_Msk) >> CAN_RXF0S_F0PI_Pos; +} + +static inline hri_can_rxf0s_reg_t hri_can_get_RXF0S_reg(const void *const hw, hri_can_rxf0s_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0S.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_rxf0s_reg_t hri_can_read_RXF0S_reg(const void *const hw) +{ + return ((Can *)hw)->RXF0S.reg; +} + +static inline bool hri_can_get_RXF1S_F1F_bit(const void *const hw) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1F) >> CAN_RXF1S_F1F_Pos; +} + +static inline bool hri_can_get_RXF1S_RF1L_bit(const void *const hw) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_RF1L) >> CAN_RXF1S_RF1L_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_F1FL_bf(const void *const hw, hri_can_rxf1s_reg_t mask) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1FL(mask)) >> CAN_RXF1S_F1FL_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_F1FL_bf(const void *const hw) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1FL_Msk) >> CAN_RXF1S_F1FL_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_F1GI_bf(const void *const hw, hri_can_rxf1s_reg_t mask) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1GI(mask)) >> CAN_RXF1S_F1GI_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_F1GI_bf(const void *const hw) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1GI_Msk) >> CAN_RXF1S_F1GI_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_F1PI_bf(const void *const hw, hri_can_rxf1s_reg_t mask) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1PI(mask)) >> CAN_RXF1S_F1PI_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_F1PI_bf(const void *const hw) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_F1PI_Msk) >> CAN_RXF1S_F1PI_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_DMS_bf(const void *const hw, hri_can_rxf1s_reg_t mask) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_DMS(mask)) >> CAN_RXF1S_DMS_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_DMS_bf(const void *const hw) +{ + return (((Can *)hw)->RXF1S.reg & CAN_RXF1S_DMS_Msk) >> CAN_RXF1S_DMS_Pos; +} + +static inline hri_can_rxf1s_reg_t hri_can_get_RXF1S_reg(const void *const hw, hri_can_rxf1s_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1S.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_rxf1s_reg_t hri_can_read_RXF1S_reg(const void *const hw) +{ + return ((Can *)hw)->RXF1S.reg; +} + +static inline bool hri_can_get_TXFQS_TFQF_bit(const void *const hw) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFQF) >> CAN_TXFQS_TFQF_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_TFFL_bf(const void *const hw, hri_can_txfqs_reg_t mask) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFFL(mask)) >> CAN_TXFQS_TFFL_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_TFFL_bf(const void *const hw) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFFL_Msk) >> CAN_TXFQS_TFFL_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_TFGI_bf(const void *const hw, hri_can_txfqs_reg_t mask) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFGI(mask)) >> CAN_TXFQS_TFGI_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_TFGI_bf(const void *const hw) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFGI_Msk) >> CAN_TXFQS_TFGI_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_TFQPI_bf(const void *const hw, hri_can_txfqs_reg_t mask) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFQPI(mask)) >> CAN_TXFQS_TFQPI_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_TFQPI_bf(const void *const hw) +{ + return (((Can *)hw)->TXFQS.reg & CAN_TXFQS_TFQPI_Msk) >> CAN_TXFQS_TFQPI_Pos; +} + +static inline hri_can_txfqs_reg_t hri_can_get_TXFQS_reg(const void *const hw, hri_can_txfqs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXFQS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_txfqs_reg_t hri_can_read_TXFQS_reg(const void *const hw) +{ + return ((Can *)hw)->TXFQS.reg; +} + +static inline bool hri_can_get_TXBRP_TRP0_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP0) >> CAN_TXBRP_TRP0_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP1_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP1) >> CAN_TXBRP_TRP1_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP2_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP2) >> CAN_TXBRP_TRP2_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP3_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP3) >> CAN_TXBRP_TRP3_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP4_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP4) >> CAN_TXBRP_TRP4_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP5_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP5) >> CAN_TXBRP_TRP5_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP6_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP6) >> CAN_TXBRP_TRP6_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP7_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP7) >> CAN_TXBRP_TRP7_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP8_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP8) >> CAN_TXBRP_TRP8_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP9_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP9) >> CAN_TXBRP_TRP9_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP10_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP10) >> CAN_TXBRP_TRP10_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP11_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP11) >> CAN_TXBRP_TRP11_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP12_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP12) >> CAN_TXBRP_TRP12_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP13_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP13) >> CAN_TXBRP_TRP13_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP14_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP14) >> CAN_TXBRP_TRP14_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP15_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP15) >> CAN_TXBRP_TRP15_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP16_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP16) >> CAN_TXBRP_TRP16_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP17_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP17) >> CAN_TXBRP_TRP17_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP18_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP18) >> CAN_TXBRP_TRP18_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP19_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP19) >> CAN_TXBRP_TRP19_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP20_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP20) >> CAN_TXBRP_TRP20_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP21_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP21) >> CAN_TXBRP_TRP21_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP22_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP22) >> CAN_TXBRP_TRP22_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP23_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP23) >> CAN_TXBRP_TRP23_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP24_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP24) >> CAN_TXBRP_TRP24_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP25_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP25) >> CAN_TXBRP_TRP25_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP26_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP26) >> CAN_TXBRP_TRP26_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP27_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP27) >> CAN_TXBRP_TRP27_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP28_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP28) >> CAN_TXBRP_TRP28_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP29_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP29) >> CAN_TXBRP_TRP29_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP30_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP30) >> CAN_TXBRP_TRP30_Pos; +} + +static inline bool hri_can_get_TXBRP_TRP31_bit(const void *const hw) +{ + return (((Can *)hw)->TXBRP.reg & CAN_TXBRP_TRP31) >> CAN_TXBRP_TRP31_Pos; +} + +static inline hri_can_txbrp_reg_t hri_can_get_TXBRP_reg(const void *const hw, hri_can_txbrp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBRP.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_txbrp_reg_t hri_can_read_TXBRP_reg(const void *const hw) +{ + return ((Can *)hw)->TXBRP.reg; +} + +static inline bool hri_can_get_TXBTO_TO0_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO0) >> CAN_TXBTO_TO0_Pos; +} + +static inline bool hri_can_get_TXBTO_TO1_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO1) >> CAN_TXBTO_TO1_Pos; +} + +static inline bool hri_can_get_TXBTO_TO2_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO2) >> CAN_TXBTO_TO2_Pos; +} + +static inline bool hri_can_get_TXBTO_TO3_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO3) >> CAN_TXBTO_TO3_Pos; +} + +static inline bool hri_can_get_TXBTO_TO4_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO4) >> CAN_TXBTO_TO4_Pos; +} + +static inline bool hri_can_get_TXBTO_TO5_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO5) >> CAN_TXBTO_TO5_Pos; +} + +static inline bool hri_can_get_TXBTO_TO6_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO6) >> CAN_TXBTO_TO6_Pos; +} + +static inline bool hri_can_get_TXBTO_TO7_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO7) >> CAN_TXBTO_TO7_Pos; +} + +static inline bool hri_can_get_TXBTO_TO8_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO8) >> CAN_TXBTO_TO8_Pos; +} + +static inline bool hri_can_get_TXBTO_TO9_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO9) >> CAN_TXBTO_TO9_Pos; +} + +static inline bool hri_can_get_TXBTO_TO10_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO10) >> CAN_TXBTO_TO10_Pos; +} + +static inline bool hri_can_get_TXBTO_TO11_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO11) >> CAN_TXBTO_TO11_Pos; +} + +static inline bool hri_can_get_TXBTO_TO12_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO12) >> CAN_TXBTO_TO12_Pos; +} + +static inline bool hri_can_get_TXBTO_TO13_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO13) >> CAN_TXBTO_TO13_Pos; +} + +static inline bool hri_can_get_TXBTO_TO14_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO14) >> CAN_TXBTO_TO14_Pos; +} + +static inline bool hri_can_get_TXBTO_TO15_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO15) >> CAN_TXBTO_TO15_Pos; +} + +static inline bool hri_can_get_TXBTO_TO16_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO16) >> CAN_TXBTO_TO16_Pos; +} + +static inline bool hri_can_get_TXBTO_TO17_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO17) >> CAN_TXBTO_TO17_Pos; +} + +static inline bool hri_can_get_TXBTO_TO18_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO18) >> CAN_TXBTO_TO18_Pos; +} + +static inline bool hri_can_get_TXBTO_TO19_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO19) >> CAN_TXBTO_TO19_Pos; +} + +static inline bool hri_can_get_TXBTO_TO20_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO20) >> CAN_TXBTO_TO20_Pos; +} + +static inline bool hri_can_get_TXBTO_TO21_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO21) >> CAN_TXBTO_TO21_Pos; +} + +static inline bool hri_can_get_TXBTO_TO22_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO22) >> CAN_TXBTO_TO22_Pos; +} + +static inline bool hri_can_get_TXBTO_TO23_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO23) >> CAN_TXBTO_TO23_Pos; +} + +static inline bool hri_can_get_TXBTO_TO24_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO24) >> CAN_TXBTO_TO24_Pos; +} + +static inline bool hri_can_get_TXBTO_TO25_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO25) >> CAN_TXBTO_TO25_Pos; +} + +static inline bool hri_can_get_TXBTO_TO26_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO26) >> CAN_TXBTO_TO26_Pos; +} + +static inline bool hri_can_get_TXBTO_TO27_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO27) >> CAN_TXBTO_TO27_Pos; +} + +static inline bool hri_can_get_TXBTO_TO28_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO28) >> CAN_TXBTO_TO28_Pos; +} + +static inline bool hri_can_get_TXBTO_TO29_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO29) >> CAN_TXBTO_TO29_Pos; +} + +static inline bool hri_can_get_TXBTO_TO30_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO30) >> CAN_TXBTO_TO30_Pos; +} + +static inline bool hri_can_get_TXBTO_TO31_bit(const void *const hw) +{ + return (((Can *)hw)->TXBTO.reg & CAN_TXBTO_TO31) >> CAN_TXBTO_TO31_Pos; +} + +static inline hri_can_txbto_reg_t hri_can_get_TXBTO_reg(const void *const hw, hri_can_txbto_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTO.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_txbto_reg_t hri_can_read_TXBTO_reg(const void *const hw) +{ + return ((Can *)hw)->TXBTO.reg; +} + +static inline bool hri_can_get_TXBCF_CF0_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF0) >> CAN_TXBCF_CF0_Pos; +} + +static inline bool hri_can_get_TXBCF_CF1_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF1) >> CAN_TXBCF_CF1_Pos; +} + +static inline bool hri_can_get_TXBCF_CF2_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF2) >> CAN_TXBCF_CF2_Pos; +} + +static inline bool hri_can_get_TXBCF_CF3_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF3) >> CAN_TXBCF_CF3_Pos; +} + +static inline bool hri_can_get_TXBCF_CF4_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF4) >> CAN_TXBCF_CF4_Pos; +} + +static inline bool hri_can_get_TXBCF_CF5_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF5) >> CAN_TXBCF_CF5_Pos; +} + +static inline bool hri_can_get_TXBCF_CF6_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF6) >> CAN_TXBCF_CF6_Pos; +} + +static inline bool hri_can_get_TXBCF_CF7_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF7) >> CAN_TXBCF_CF7_Pos; +} + +static inline bool hri_can_get_TXBCF_CF8_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF8) >> CAN_TXBCF_CF8_Pos; +} + +static inline bool hri_can_get_TXBCF_CF9_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF9) >> CAN_TXBCF_CF9_Pos; +} + +static inline bool hri_can_get_TXBCF_CF10_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF10) >> CAN_TXBCF_CF10_Pos; +} + +static inline bool hri_can_get_TXBCF_CF11_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF11) >> CAN_TXBCF_CF11_Pos; +} + +static inline bool hri_can_get_TXBCF_CF12_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF12) >> CAN_TXBCF_CF12_Pos; +} + +static inline bool hri_can_get_TXBCF_CF13_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF13) >> CAN_TXBCF_CF13_Pos; +} + +static inline bool hri_can_get_TXBCF_CF14_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF14) >> CAN_TXBCF_CF14_Pos; +} + +static inline bool hri_can_get_TXBCF_CF15_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF15) >> CAN_TXBCF_CF15_Pos; +} + +static inline bool hri_can_get_TXBCF_CF16_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF16) >> CAN_TXBCF_CF16_Pos; +} + +static inline bool hri_can_get_TXBCF_CF17_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF17) >> CAN_TXBCF_CF17_Pos; +} + +static inline bool hri_can_get_TXBCF_CF18_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF18) >> CAN_TXBCF_CF18_Pos; +} + +static inline bool hri_can_get_TXBCF_CF19_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF19) >> CAN_TXBCF_CF19_Pos; +} + +static inline bool hri_can_get_TXBCF_CF20_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF20) >> CAN_TXBCF_CF20_Pos; +} + +static inline bool hri_can_get_TXBCF_CF21_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF21) >> CAN_TXBCF_CF21_Pos; +} + +static inline bool hri_can_get_TXBCF_CF22_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF22) >> CAN_TXBCF_CF22_Pos; +} + +static inline bool hri_can_get_TXBCF_CF23_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF23) >> CAN_TXBCF_CF23_Pos; +} + +static inline bool hri_can_get_TXBCF_CF24_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF24) >> CAN_TXBCF_CF24_Pos; +} + +static inline bool hri_can_get_TXBCF_CF25_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF25) >> CAN_TXBCF_CF25_Pos; +} + +static inline bool hri_can_get_TXBCF_CF26_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF26) >> CAN_TXBCF_CF26_Pos; +} + +static inline bool hri_can_get_TXBCF_CF27_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF27) >> CAN_TXBCF_CF27_Pos; +} + +static inline bool hri_can_get_TXBCF_CF28_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF28) >> CAN_TXBCF_CF28_Pos; +} + +static inline bool hri_can_get_TXBCF_CF29_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF29) >> CAN_TXBCF_CF29_Pos; +} + +static inline bool hri_can_get_TXBCF_CF30_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF30) >> CAN_TXBCF_CF30_Pos; +} + +static inline bool hri_can_get_TXBCF_CF31_bit(const void *const hw) +{ + return (((Can *)hw)->TXBCF.reg & CAN_TXBCF_CF31) >> CAN_TXBCF_CF31_Pos; +} + +static inline hri_can_txbcf_reg_t hri_can_get_TXBCF_reg(const void *const hw, hri_can_txbcf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCF.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_txbcf_reg_t hri_can_read_TXBCF_reg(const void *const hw) +{ + return ((Can *)hw)->TXBCF.reg; +} + +static inline bool hri_can_get_TXEFS_EFF_bit(const void *const hw) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFF) >> CAN_TXEFS_EFF_Pos; +} + +static inline bool hri_can_get_TXEFS_TEFL_bit(const void *const hw) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_TEFL) >> CAN_TXEFS_TEFL_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_get_TXEFS_EFFL_bf(const void *const hw, hri_can_txefs_reg_t mask) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFFL(mask)) >> CAN_TXEFS_EFFL_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_read_TXEFS_EFFL_bf(const void *const hw) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFFL_Msk) >> CAN_TXEFS_EFFL_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_get_TXEFS_EFGI_bf(const void *const hw, hri_can_txefs_reg_t mask) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFGI(mask)) >> CAN_TXEFS_EFGI_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_read_TXEFS_EFGI_bf(const void *const hw) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFGI_Msk) >> CAN_TXEFS_EFGI_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_get_TXEFS_EFPI_bf(const void *const hw, hri_can_txefs_reg_t mask) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFPI(mask)) >> CAN_TXEFS_EFPI_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_read_TXEFS_EFPI_bf(const void *const hw) +{ + return (((Can *)hw)->TXEFS.reg & CAN_TXEFS_EFPI_Msk) >> CAN_TXEFS_EFPI_Pos; +} + +static inline hri_can_txefs_reg_t hri_can_get_TXEFS_reg(const void *const hw, hri_can_txefs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_can_txefs_reg_t hri_can_read_TXEFS_reg(const void *const hw) +{ + return ((Can *)hw)->TXEFS.reg; +} + +static inline void hri_can_set_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg |= CAN_MRCFG_QOS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_mrcfg_reg_t hri_can_get_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->MRCFG.reg; + tmp = (tmp & CAN_MRCFG_QOS(mask)) >> CAN_MRCFG_QOS_Pos; + return tmp; +} + +static inline void hri_can_write_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->MRCFG.reg; + tmp &= ~CAN_MRCFG_QOS_Msk; + tmp |= CAN_MRCFG_QOS(data); + ((Can *)hw)->MRCFG.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg &= ~CAN_MRCFG_QOS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_MRCFG_QOS_bf(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg ^= CAN_MRCFG_QOS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_mrcfg_reg_t hri_can_read_MRCFG_QOS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->MRCFG.reg; + tmp = (tmp & CAN_MRCFG_QOS_Msk) >> CAN_MRCFG_QOS_Pos; + return tmp; +} + +static inline void hri_can_set_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_mrcfg_reg_t hri_can_get_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->MRCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_MRCFG_reg(const void *const hw, hri_can_mrcfg_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->MRCFG.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_mrcfg_reg_t hri_can_read_MRCFG_reg(const void *const hw) +{ + return ((Can *)hw)->MRCFG.reg; +} + +static inline void hri_can_set_DBTP_TDC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg |= CAN_DBTP_TDC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_DBTP_TDC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_TDC) >> CAN_DBTP_TDC_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_DBTP_TDC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->DBTP.reg; + tmp &= ~CAN_DBTP_TDC; + tmp |= value << CAN_DBTP_TDC_Pos; + ((Can *)hw)->DBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_DBTP_TDC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_TDC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_DBTP_TDC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg ^= CAN_DBTP_TDC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg |= CAN_DBTP_DSJW(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DSJW(mask)) >> CAN_DBTP_DSJW_Pos; + return tmp; +} + +static inline void hri_can_write_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->DBTP.reg; + tmp &= ~CAN_DBTP_DSJW_Msk; + tmp |= CAN_DBTP_DSJW(data); + ((Can *)hw)->DBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DSJW(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_DBTP_DSJW_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg ^= CAN_DBTP_DSJW(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DSJW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DSJW_Msk) >> CAN_DBTP_DSJW_Pos; + return tmp; +} + +static inline void hri_can_set_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg |= CAN_DBTP_DTSEG2(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DTSEG2(mask)) >> CAN_DBTP_DTSEG2_Pos; + return tmp; +} + +static inline void hri_can_write_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->DBTP.reg; + tmp &= ~CAN_DBTP_DTSEG2_Msk; + tmp |= CAN_DBTP_DTSEG2(data); + ((Can *)hw)->DBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DTSEG2(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_DBTP_DTSEG2_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg ^= CAN_DBTP_DTSEG2(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DTSEG2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DTSEG2_Msk) >> CAN_DBTP_DTSEG2_Pos; + return tmp; +} + +static inline void hri_can_set_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg |= CAN_DBTP_DTSEG1(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DTSEG1(mask)) >> CAN_DBTP_DTSEG1_Pos; + return tmp; +} + +static inline void hri_can_write_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->DBTP.reg; + tmp &= ~CAN_DBTP_DTSEG1_Msk; + tmp |= CAN_DBTP_DTSEG1(data); + ((Can *)hw)->DBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DTSEG1(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_DBTP_DTSEG1_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg ^= CAN_DBTP_DTSEG1(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DTSEG1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DTSEG1_Msk) >> CAN_DBTP_DTSEG1_Pos; + return tmp; +} + +static inline void hri_can_set_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg |= CAN_DBTP_DBRP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_get_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DBRP(mask)) >> CAN_DBTP_DBRP_Pos; + return tmp; +} + +static inline void hri_can_write_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->DBTP.reg; + tmp &= ~CAN_DBTP_DBRP_Msk; + tmp |= CAN_DBTP_DBRP(data); + ((Can *)hw)->DBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg &= ~CAN_DBTP_DBRP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_DBTP_DBRP_bf(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg ^= CAN_DBTP_DBRP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_read_DBTP_DBRP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp = (tmp & CAN_DBTP_DBRP_Msk) >> CAN_DBTP_DBRP_Pos; + return tmp; +} + +static inline void hri_can_set_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_get_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->DBTP.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_DBTP_reg(const void *const hw, hri_can_dbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->DBTP.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_dbtp_reg_t hri_can_read_DBTP_reg(const void *const hw) +{ + return ((Can *)hw)->DBTP.reg; +} + +static inline void hri_can_set_TEST_LBCK_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg |= CAN_TEST_LBCK; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TEST_LBCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TEST.reg; + tmp = (tmp & CAN_TEST_LBCK) >> CAN_TEST_LBCK_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TEST_LBCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TEST.reg; + tmp &= ~CAN_TEST_LBCK; + tmp |= value << CAN_TEST_LBCK_Pos; + ((Can *)hw)->TEST.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TEST_LBCK_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg &= ~CAN_TEST_LBCK; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TEST_LBCK_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg ^= CAN_TEST_LBCK; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TEST_RX_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg |= CAN_TEST_RX; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TEST_RX_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TEST.reg; + tmp = (tmp & CAN_TEST_RX) >> CAN_TEST_RX_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TEST_RX_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TEST.reg; + tmp &= ~CAN_TEST_RX; + tmp |= value << CAN_TEST_RX_Pos; + ((Can *)hw)->TEST.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TEST_RX_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg &= ~CAN_TEST_RX; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TEST_RX_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg ^= CAN_TEST_RX; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg |= CAN_TEST_TX(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_test_reg_t hri_can_get_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TEST.reg; + tmp = (tmp & CAN_TEST_TX(mask)) >> CAN_TEST_TX_Pos; + return tmp; +} + +static inline void hri_can_write_TEST_TX_bf(const void *const hw, hri_can_test_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TEST.reg; + tmp &= ~CAN_TEST_TX_Msk; + tmp |= CAN_TEST_TX(data); + ((Can *)hw)->TEST.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg &= ~CAN_TEST_TX(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TEST_TX_bf(const void *const hw, hri_can_test_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg ^= CAN_TEST_TX(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_test_reg_t hri_can_read_TEST_TX_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TEST.reg; + tmp = (tmp & CAN_TEST_TX_Msk) >> CAN_TEST_TX_Pos; + return tmp; +} + +static inline void hri_can_set_TEST_reg(const void *const hw, hri_can_test_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_test_reg_t hri_can_get_TEST_reg(const void *const hw, hri_can_test_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TEST.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TEST_reg(const void *const hw, hri_can_test_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TEST_reg(const void *const hw, hri_can_test_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TEST_reg(const void *const hw, hri_can_test_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TEST.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_test_reg_t hri_can_read_TEST_reg(const void *const hw) +{ + return ((Can *)hw)->TEST.reg; +} + +static inline void hri_can_set_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg |= CAN_RWD_WDC(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rwd_reg_t hri_can_get_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RWD.reg; + tmp = (tmp & CAN_RWD_WDC(mask)) >> CAN_RWD_WDC_Pos; + return tmp; +} + +static inline void hri_can_write_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RWD.reg; + tmp &= ~CAN_RWD_WDC_Msk; + tmp |= CAN_RWD_WDC(data); + ((Can *)hw)->RWD.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg &= ~CAN_RWD_WDC(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RWD_WDC_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg ^= CAN_RWD_WDC(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rwd_reg_t hri_can_read_RWD_WDC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RWD.reg; + tmp = (tmp & CAN_RWD_WDC_Msk) >> CAN_RWD_WDC_Pos; + return tmp; +} + +static inline void hri_can_set_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg |= CAN_RWD_WDV(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rwd_reg_t hri_can_get_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RWD.reg; + tmp = (tmp & CAN_RWD_WDV(mask)) >> CAN_RWD_WDV_Pos; + return tmp; +} + +static inline void hri_can_write_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RWD.reg; + tmp &= ~CAN_RWD_WDV_Msk; + tmp |= CAN_RWD_WDV(data); + ((Can *)hw)->RWD.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg &= ~CAN_RWD_WDV(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RWD_WDV_bf(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg ^= CAN_RWD_WDV(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rwd_reg_t hri_can_read_RWD_WDV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RWD.reg; + tmp = (tmp & CAN_RWD_WDV_Msk) >> CAN_RWD_WDV_Pos; + return tmp; +} + +static inline void hri_can_set_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rwd_reg_t hri_can_get_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RWD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RWD_reg(const void *const hw, hri_can_rwd_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RWD_reg(const void *const hw, hri_can_rwd_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RWD.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rwd_reg_t hri_can_read_RWD_reg(const void *const hw) +{ + return ((Can *)hw)->RWD.reg; +} + +static inline void hri_can_set_CCCR_INIT_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_INIT; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_INIT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_INIT) >> CAN_CCCR_INIT_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_INIT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_INIT; + tmp |= value << CAN_CCCR_INIT_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_INIT_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_INIT; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_INIT_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_INIT; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_CCE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_CCE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_CCE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_CCE) >> CAN_CCCR_CCE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_CCE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_CCE; + tmp |= value << CAN_CCCR_CCE_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_CCE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_CCE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_CCE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_CCE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_ASM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_ASM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_ASM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_ASM) >> CAN_CCCR_ASM_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_ASM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_ASM; + tmp |= value << CAN_CCCR_ASM_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_ASM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_ASM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_ASM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_ASM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_CSA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_CSA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_CSA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_CSA) >> CAN_CCCR_CSA_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_CSA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_CSA; + tmp |= value << CAN_CCCR_CSA_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_CSA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_CSA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_CSA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_CSA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_CSR_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_CSR; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_CSR_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_CSR) >> CAN_CCCR_CSR_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_CSR_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_CSR; + tmp |= value << CAN_CCCR_CSR_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_CSR_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_CSR; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_CSR_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_CSR; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_MON_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_MON; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_MON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_MON) >> CAN_CCCR_MON_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_MON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_MON; + tmp |= value << CAN_CCCR_MON_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_MON_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_MON; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_MON_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_MON; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_DAR_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_DAR; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_DAR_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_DAR) >> CAN_CCCR_DAR_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_DAR_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_DAR; + tmp |= value << CAN_CCCR_DAR_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_DAR_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_DAR; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_DAR_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_DAR; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_TEST_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_TEST; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_TEST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_TEST) >> CAN_CCCR_TEST_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_TEST_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_TEST; + tmp |= value << CAN_CCCR_TEST_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_TEST_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_TEST; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_TEST_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_TEST; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_FDOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_FDOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_FDOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_FDOE) >> CAN_CCCR_FDOE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_FDOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_FDOE; + tmp |= value << CAN_CCCR_FDOE_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_FDOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_FDOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_FDOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_FDOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_BRSE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_BRSE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_BRSE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_BRSE) >> CAN_CCCR_BRSE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_BRSE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_BRSE; + tmp |= value << CAN_CCCR_BRSE_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_BRSE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_BRSE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_BRSE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_BRSE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_PXHD_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_PXHD; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_PXHD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_PXHD) >> CAN_CCCR_PXHD_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_PXHD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_PXHD; + tmp |= value << CAN_CCCR_PXHD_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_PXHD_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_PXHD; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_PXHD_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_PXHD; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_EFBI_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_EFBI; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_EFBI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_EFBI) >> CAN_CCCR_EFBI_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_EFBI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_EFBI; + tmp |= value << CAN_CCCR_EFBI_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_EFBI_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_EFBI; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_EFBI_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_EFBI; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_TXP_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_TXP; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_TXP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_TXP) >> CAN_CCCR_TXP_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_TXP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_TXP; + tmp |= value << CAN_CCCR_TXP_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_TXP_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_TXP; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_TXP_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_TXP; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_NISO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= CAN_CCCR_NISO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_CCCR_NISO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp = (tmp & CAN_CCCR_NISO) >> CAN_CCCR_NISO_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_CCCR_NISO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->CCCR.reg; + tmp &= ~CAN_CCCR_NISO; + tmp |= value << CAN_CCCR_NISO_Pos; + ((Can *)hw)->CCCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_NISO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~CAN_CCCR_NISO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_NISO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= CAN_CCCR_NISO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_cccr_reg_t hri_can_get_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->CCCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_CCCR_reg(const void *const hw, hri_can_cccr_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_CCCR_reg(const void *const hw, hri_can_cccr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->CCCR.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_cccr_reg_t hri_can_read_CCCR_reg(const void *const hw) +{ + return ((Can *)hw)->CCCR.reg; +} + +static inline void hri_can_set_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg |= CAN_NBTP_NTSEG2(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NTSEG2(mask)) >> CAN_NBTP_NTSEG2_Pos; + return tmp; +} + +static inline void hri_can_write_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NBTP.reg; + tmp &= ~CAN_NBTP_NTSEG2_Msk; + tmp |= CAN_NBTP_NTSEG2(data); + ((Can *)hw)->NBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NTSEG2(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NBTP_NTSEG2_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg ^= CAN_NBTP_NTSEG2(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NTSEG2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NTSEG2_Msk) >> CAN_NBTP_NTSEG2_Pos; + return tmp; +} + +static inline void hri_can_set_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg |= CAN_NBTP_NTSEG1(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NTSEG1(mask)) >> CAN_NBTP_NTSEG1_Pos; + return tmp; +} + +static inline void hri_can_write_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NBTP.reg; + tmp &= ~CAN_NBTP_NTSEG1_Msk; + tmp |= CAN_NBTP_NTSEG1(data); + ((Can *)hw)->NBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NTSEG1(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NBTP_NTSEG1_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg ^= CAN_NBTP_NTSEG1(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NTSEG1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NTSEG1_Msk) >> CAN_NBTP_NTSEG1_Pos; + return tmp; +} + +static inline void hri_can_set_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg |= CAN_NBTP_NBRP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NBRP(mask)) >> CAN_NBTP_NBRP_Pos; + return tmp; +} + +static inline void hri_can_write_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NBTP.reg; + tmp &= ~CAN_NBTP_NBRP_Msk; + tmp |= CAN_NBTP_NBRP(data); + ((Can *)hw)->NBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NBRP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NBTP_NBRP_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg ^= CAN_NBTP_NBRP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NBRP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NBRP_Msk) >> CAN_NBTP_NBRP_Pos; + return tmp; +} + +static inline void hri_can_set_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg |= CAN_NBTP_NSJW(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_get_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NSJW(mask)) >> CAN_NBTP_NSJW_Pos; + return tmp; +} + +static inline void hri_can_write_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NBTP.reg; + tmp &= ~CAN_NBTP_NSJW_Msk; + tmp |= CAN_NBTP_NSJW(data); + ((Can *)hw)->NBTP.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg &= ~CAN_NBTP_NSJW(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NBTP_NSJW_bf(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg ^= CAN_NBTP_NSJW(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_read_NBTP_NSJW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp = (tmp & CAN_NBTP_NSJW_Msk) >> CAN_NBTP_NSJW_Pos; + return tmp; +} + +static inline void hri_can_set_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_get_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NBTP.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NBTP_reg(const void *const hw, hri_can_nbtp_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NBTP.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_nbtp_reg_t hri_can_read_NBTP_reg(const void *const hw) +{ + return ((Can *)hw)->NBTP.reg; +} + +static inline void hri_can_set_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg |= CAN_TSCC_TSS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tscc_reg_t hri_can_get_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TSCC.reg; + tmp = (tmp & CAN_TSCC_TSS(mask)) >> CAN_TSCC_TSS_Pos; + return tmp; +} + +static inline void hri_can_write_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TSCC.reg; + tmp &= ~CAN_TSCC_TSS_Msk; + tmp |= CAN_TSCC_TSS(data); + ((Can *)hw)->TSCC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg &= ~CAN_TSCC_TSS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TSCC_TSS_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg ^= CAN_TSCC_TSS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tscc_reg_t hri_can_read_TSCC_TSS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TSCC.reg; + tmp = (tmp & CAN_TSCC_TSS_Msk) >> CAN_TSCC_TSS_Pos; + return tmp; +} + +static inline void hri_can_set_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg |= CAN_TSCC_TCP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tscc_reg_t hri_can_get_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TSCC.reg; + tmp = (tmp & CAN_TSCC_TCP(mask)) >> CAN_TSCC_TCP_Pos; + return tmp; +} + +static inline void hri_can_write_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TSCC.reg; + tmp &= ~CAN_TSCC_TCP_Msk; + tmp |= CAN_TSCC_TCP(data); + ((Can *)hw)->TSCC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg &= ~CAN_TSCC_TCP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TSCC_TCP_bf(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg ^= CAN_TSCC_TCP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tscc_reg_t hri_can_read_TSCC_TCP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TSCC.reg; + tmp = (tmp & CAN_TSCC_TCP_Msk) >> CAN_TSCC_TCP_Pos; + return tmp; +} + +static inline void hri_can_set_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tscc_reg_t hri_can_get_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TSCC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TSCC_reg(const void *const hw, hri_can_tscc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TSCC_reg(const void *const hw, hri_can_tscc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TSCC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tscc_reg_t hri_can_read_TSCC_reg(const void *const hw) +{ + return ((Can *)hw)->TSCC.reg; +} + +static inline void hri_can_set_TOCC_ETOC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg |= CAN_TOCC_ETOC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TOCC_ETOC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCC.reg; + tmp = (tmp & CAN_TOCC_ETOC) >> CAN_TOCC_ETOC_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TOCC_ETOC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TOCC.reg; + tmp &= ~CAN_TOCC_ETOC; + tmp |= value << CAN_TOCC_ETOC_Pos; + ((Can *)hw)->TOCC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TOCC_ETOC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg &= ~CAN_TOCC_ETOC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TOCC_ETOC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg ^= CAN_TOCC_ETOC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg |= CAN_TOCC_TOS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocc_reg_t hri_can_get_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCC.reg; + tmp = (tmp & CAN_TOCC_TOS(mask)) >> CAN_TOCC_TOS_Pos; + return tmp; +} + +static inline void hri_can_write_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TOCC.reg; + tmp &= ~CAN_TOCC_TOS_Msk; + tmp |= CAN_TOCC_TOS(data); + ((Can *)hw)->TOCC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg &= ~CAN_TOCC_TOS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TOCC_TOS_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg ^= CAN_TOCC_TOS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocc_reg_t hri_can_read_TOCC_TOS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCC.reg; + tmp = (tmp & CAN_TOCC_TOS_Msk) >> CAN_TOCC_TOS_Pos; + return tmp; +} + +static inline void hri_can_set_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg |= CAN_TOCC_TOP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocc_reg_t hri_can_get_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCC.reg; + tmp = (tmp & CAN_TOCC_TOP(mask)) >> CAN_TOCC_TOP_Pos; + return tmp; +} + +static inline void hri_can_write_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TOCC.reg; + tmp &= ~CAN_TOCC_TOP_Msk; + tmp |= CAN_TOCC_TOP(data); + ((Can *)hw)->TOCC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg &= ~CAN_TOCC_TOP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TOCC_TOP_bf(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg ^= CAN_TOCC_TOP(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocc_reg_t hri_can_read_TOCC_TOP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCC.reg; + tmp = (tmp & CAN_TOCC_TOP_Msk) >> CAN_TOCC_TOP_Pos; + return tmp; +} + +static inline void hri_can_set_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocc_reg_t hri_can_get_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TOCC_reg(const void *const hw, hri_can_tocc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TOCC_reg(const void *const hw, hri_can_tocc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocc_reg_t hri_can_read_TOCC_reg(const void *const hw) +{ + return ((Can *)hw)->TOCC.reg; +} + +static inline void hri_can_set_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg |= CAN_TOCV_TOC(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocv_reg_t hri_can_get_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCV.reg; + tmp = (tmp & CAN_TOCV_TOC(mask)) >> CAN_TOCV_TOC_Pos; + return tmp; +} + +static inline void hri_can_write_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TOCV.reg; + tmp &= ~CAN_TOCV_TOC_Msk; + tmp |= CAN_TOCV_TOC(data); + ((Can *)hw)->TOCV.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg &= ~CAN_TOCV_TOC(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TOCV_TOC_bf(const void *const hw, hri_can_tocv_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg ^= CAN_TOCV_TOC(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocv_reg_t hri_can_read_TOCV_TOC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCV.reg; + tmp = (tmp & CAN_TOCV_TOC_Msk) >> CAN_TOCV_TOC_Pos; + return tmp; +} + +static inline void hri_can_set_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocv_reg_t hri_can_get_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TOCV.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TOCV_reg(const void *const hw, hri_can_tocv_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TOCV_reg(const void *const hw, hri_can_tocv_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TOCV.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tocv_reg_t hri_can_read_TOCV_reg(const void *const hw) +{ + return ((Can *)hw)->TOCV.reg; +} + +static inline void hri_can_set_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg |= CAN_TDCR_TDCF(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tdcr_reg_t hri_can_get_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TDCR.reg; + tmp = (tmp & CAN_TDCR_TDCF(mask)) >> CAN_TDCR_TDCF_Pos; + return tmp; +} + +static inline void hri_can_write_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TDCR.reg; + tmp &= ~CAN_TDCR_TDCF_Msk; + tmp |= CAN_TDCR_TDCF(data); + ((Can *)hw)->TDCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg &= ~CAN_TDCR_TDCF(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TDCR_TDCF_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg ^= CAN_TDCR_TDCF(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tdcr_reg_t hri_can_read_TDCR_TDCF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TDCR.reg; + tmp = (tmp & CAN_TDCR_TDCF_Msk) >> CAN_TDCR_TDCF_Pos; + return tmp; +} + +static inline void hri_can_set_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg |= CAN_TDCR_TDCO(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tdcr_reg_t hri_can_get_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TDCR.reg; + tmp = (tmp & CAN_TDCR_TDCO(mask)) >> CAN_TDCR_TDCO_Pos; + return tmp; +} + +static inline void hri_can_write_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TDCR.reg; + tmp &= ~CAN_TDCR_TDCO_Msk; + tmp |= CAN_TDCR_TDCO(data); + ((Can *)hw)->TDCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg &= ~CAN_TDCR_TDCO(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TDCR_TDCO_bf(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg ^= CAN_TDCR_TDCO(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tdcr_reg_t hri_can_read_TDCR_TDCO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TDCR.reg; + tmp = (tmp & CAN_TDCR_TDCO_Msk) >> CAN_TDCR_TDCO_Pos; + return tmp; +} + +static inline void hri_can_set_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tdcr_reg_t hri_can_get_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TDCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TDCR_reg(const void *const hw, hri_can_tdcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TDCR.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_tdcr_reg_t hri_can_read_TDCR_reg(const void *const hw) +{ + return ((Can *)hw)->TDCR.reg; +} + +static inline void hri_can_set_IR_RF0N_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF0N; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF0N_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF0N) >> CAN_IR_RF0N_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF0N_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF0N; + tmp |= value << CAN_IR_RF0N_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF0N_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF0N; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF0N_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF0N; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF0W_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF0W; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF0W_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF0W) >> CAN_IR_RF0W_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF0W_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF0W; + tmp |= value << CAN_IR_RF0W_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF0W_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF0W; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF0W_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF0W; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF0F_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF0F; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF0F_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF0F) >> CAN_IR_RF0F_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF0F_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF0F; + tmp |= value << CAN_IR_RF0F_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF0F_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF0F; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF0F_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF0F; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF0L_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF0L; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF0L_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF0L) >> CAN_IR_RF0L_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF0L_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF0L; + tmp |= value << CAN_IR_RF0L_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF0L_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF0L; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF0L_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF0L; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF1N_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF1N; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF1N_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF1N) >> CAN_IR_RF1N_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF1N_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF1N; + tmp |= value << CAN_IR_RF1N_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF1N_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF1N; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF1N_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF1N; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF1W_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF1W; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF1W_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF1W) >> CAN_IR_RF1W_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF1W_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF1W; + tmp |= value << CAN_IR_RF1W_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF1W_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF1W; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF1W_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF1W; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF1F_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF1F; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF1F_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF1F) >> CAN_IR_RF1F_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF1F_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF1F; + tmp |= value << CAN_IR_RF1F_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF1F_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF1F; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF1F_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF1F; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_RF1L_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_RF1L; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_RF1L_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_RF1L) >> CAN_IR_RF1L_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_RF1L_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_RF1L; + tmp |= value << CAN_IR_RF1L_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_RF1L_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_RF1L; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_RF1L_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_RF1L; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_HPM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_HPM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_HPM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_HPM) >> CAN_IR_HPM_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_HPM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_HPM; + tmp |= value << CAN_IR_HPM_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_HPM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_HPM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_HPM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_HPM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TC) >> CAN_IR_TC_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TC; + tmp |= value << CAN_IR_TC_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TCF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TCF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TCF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TCF) >> CAN_IR_TCF_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TCF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TCF; + tmp |= value << CAN_IR_TCF_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TCF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TCF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TCF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TCF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TFE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TFE) >> CAN_IR_TFE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TFE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TFE; + tmp |= value << CAN_IR_TFE_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TEFN_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TEFN; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TEFN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TEFN) >> CAN_IR_TEFN_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TEFN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TEFN; + tmp |= value << CAN_IR_TEFN_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TEFN_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TEFN; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TEFN_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TEFN; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TEFW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TEFW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TEFW_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TEFW) >> CAN_IR_TEFW_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TEFW_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TEFW; + tmp |= value << CAN_IR_TEFW_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TEFW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TEFW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TEFW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TEFW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TEFF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TEFF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TEFF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TEFF) >> CAN_IR_TEFF_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TEFF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TEFF; + tmp |= value << CAN_IR_TEFF_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TEFF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TEFF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TEFF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TEFF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TEFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TEFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TEFL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TEFL) >> CAN_IR_TEFL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TEFL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TEFL; + tmp |= value << CAN_IR_TEFL_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TEFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TEFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TEFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TEFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TSW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TSW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TSW_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TSW) >> CAN_IR_TSW_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TSW_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TSW; + tmp |= value << CAN_IR_TSW_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TSW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TSW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TSW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TSW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_MRAF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_MRAF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_MRAF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_MRAF) >> CAN_IR_MRAF_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_MRAF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_MRAF; + tmp |= value << CAN_IR_MRAF_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_MRAF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_MRAF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_MRAF_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_MRAF; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_TOO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_TOO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_TOO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_TOO) >> CAN_IR_TOO_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_TOO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_TOO; + tmp |= value << CAN_IR_TOO_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_TOO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_TOO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_TOO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_TOO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_DRX_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_DRX; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_DRX_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_DRX) >> CAN_IR_DRX_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_DRX_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_DRX; + tmp |= value << CAN_IR_DRX_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_DRX_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_DRX; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_DRX_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_DRX; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_BEC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_BEC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_BEC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_BEC) >> CAN_IR_BEC_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_BEC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_BEC; + tmp |= value << CAN_IR_BEC_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_BEC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_BEC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_BEC_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_BEC; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_BEU_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_BEU; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_BEU_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_BEU) >> CAN_IR_BEU_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_BEU_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_BEU; + tmp |= value << CAN_IR_BEU_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_BEU_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_BEU; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_BEU_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_BEU; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_ELO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_ELO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_ELO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_ELO) >> CAN_IR_ELO_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_ELO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_ELO; + tmp |= value << CAN_IR_ELO_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_ELO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_ELO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_ELO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_ELO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_EP_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_EP; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_EP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_EP) >> CAN_IR_EP_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_EP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_EP; + tmp |= value << CAN_IR_EP_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_EP_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_EP; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_EP_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_EP; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_EW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_EW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_EW_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_EW) >> CAN_IR_EW_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_EW_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_EW; + tmp |= value << CAN_IR_EW_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_EW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_EW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_EW_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_EW; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_BO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_BO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_BO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_BO) >> CAN_IR_BO_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_BO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_BO; + tmp |= value << CAN_IR_BO_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_BO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_BO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_BO_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_BO; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_WDI_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_WDI; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_WDI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_WDI) >> CAN_IR_WDI_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_WDI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_WDI; + tmp |= value << CAN_IR_WDI_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_WDI_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_WDI; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_WDI_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_WDI; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_PEA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_PEA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_PEA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_PEA) >> CAN_IR_PEA_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_PEA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_PEA; + tmp |= value << CAN_IR_PEA_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_PEA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_PEA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_PEA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_PEA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_PED_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_PED; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_PED_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_PED) >> CAN_IR_PED_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_PED_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_PED; + tmp |= value << CAN_IR_PED_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_PED_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_PED; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_PED_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_PED; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_ARA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= CAN_IR_ARA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IR_ARA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp = (tmp & CAN_IR_ARA) >> CAN_IR_ARA_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IR_ARA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IR.reg; + tmp &= ~CAN_IR_ARA; + tmp |= value << CAN_IR_ARA_Pos; + ((Can *)hw)->IR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_ARA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~CAN_IR_ARA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_ARA_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= CAN_IR_ARA; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IR_reg(const void *const hw, hri_can_ir_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ir_reg_t hri_can_get_IR_reg(const void *const hw, hri_can_ir_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_IR_reg(const void *const hw, hri_can_ir_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IR_reg(const void *const hw, hri_can_ir_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IR_reg(const void *const hw, hri_can_ir_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IR.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ir_reg_t hri_can_read_IR_reg(const void *const hw) +{ + return ((Can *)hw)->IR.reg; +} + +static inline void hri_can_set_IE_RF0NE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF0NE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF0NE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF0NE) >> CAN_IE_RF0NE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF0NE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF0NE; + tmp |= value << CAN_IE_RF0NE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF0NE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF0NE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF0NE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF0NE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF0WE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF0WE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF0WE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF0WE) >> CAN_IE_RF0WE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF0WE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF0WE; + tmp |= value << CAN_IE_RF0WE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF0WE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF0WE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF0WE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF0WE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF0FE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF0FE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF0FE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF0FE) >> CAN_IE_RF0FE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF0FE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF0FE; + tmp |= value << CAN_IE_RF0FE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF0FE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF0FE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF0FE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF0FE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF0LE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF0LE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF0LE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF0LE) >> CAN_IE_RF0LE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF0LE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF0LE; + tmp |= value << CAN_IE_RF0LE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF0LE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF0LE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF0LE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF0LE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF1NE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF1NE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF1NE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF1NE) >> CAN_IE_RF1NE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF1NE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF1NE; + tmp |= value << CAN_IE_RF1NE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF1NE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF1NE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF1NE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF1NE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF1WE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF1WE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF1WE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF1WE) >> CAN_IE_RF1WE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF1WE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF1WE; + tmp |= value << CAN_IE_RF1WE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF1WE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF1WE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF1WE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF1WE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF1FE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF1FE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF1FE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF1FE) >> CAN_IE_RF1FE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF1FE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF1FE; + tmp |= value << CAN_IE_RF1FE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF1FE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF1FE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF1FE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF1FE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_RF1LE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_RF1LE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_RF1LE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_RF1LE) >> CAN_IE_RF1LE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_RF1LE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_RF1LE; + tmp |= value << CAN_IE_RF1LE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_RF1LE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_RF1LE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_RF1LE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_RF1LE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_HPME_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_HPME; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_HPME_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_HPME) >> CAN_IE_HPME_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_HPME_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_HPME; + tmp |= value << CAN_IE_HPME_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_HPME_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_HPME; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_HPME_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_HPME; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TCE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TCE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TCE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TCE) >> CAN_IE_TCE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TCE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TCE; + tmp |= value << CAN_IE_TCE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TCE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TCE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TCE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TCE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TCFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TCFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TCFE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TCFE) >> CAN_IE_TCFE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TCFE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TCFE; + tmp |= value << CAN_IE_TCFE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TCFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TCFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TCFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TCFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TFEE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TFEE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TFEE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TFEE) >> CAN_IE_TFEE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TFEE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TFEE; + tmp |= value << CAN_IE_TFEE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TFEE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TFEE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TFEE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TFEE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TEFNE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TEFNE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TEFNE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TEFNE) >> CAN_IE_TEFNE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TEFNE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TEFNE; + tmp |= value << CAN_IE_TEFNE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TEFNE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TEFNE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TEFNE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TEFNE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TEFWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TEFWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TEFWE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TEFWE) >> CAN_IE_TEFWE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TEFWE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TEFWE; + tmp |= value << CAN_IE_TEFWE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TEFWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TEFWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TEFWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TEFWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TEFFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TEFFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TEFFE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TEFFE) >> CAN_IE_TEFFE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TEFFE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TEFFE; + tmp |= value << CAN_IE_TEFFE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TEFFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TEFFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TEFFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TEFFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TEFLE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TEFLE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TEFLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TEFLE) >> CAN_IE_TEFLE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TEFLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TEFLE; + tmp |= value << CAN_IE_TEFLE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TEFLE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TEFLE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TEFLE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TEFLE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TSWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TSWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TSWE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TSWE) >> CAN_IE_TSWE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TSWE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TSWE; + tmp |= value << CAN_IE_TSWE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TSWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TSWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TSWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TSWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_MRAFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_MRAFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_MRAFE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_MRAFE) >> CAN_IE_MRAFE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_MRAFE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_MRAFE; + tmp |= value << CAN_IE_MRAFE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_MRAFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_MRAFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_MRAFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_MRAFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_TOOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_TOOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_TOOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_TOOE) >> CAN_IE_TOOE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_TOOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_TOOE; + tmp |= value << CAN_IE_TOOE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_TOOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_TOOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_TOOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_TOOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_DRXE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_DRXE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_DRXE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_DRXE) >> CAN_IE_DRXE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_DRXE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_DRXE; + tmp |= value << CAN_IE_DRXE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_DRXE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_DRXE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_DRXE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_DRXE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_BECE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_BECE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_BECE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_BECE) >> CAN_IE_BECE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_BECE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_BECE; + tmp |= value << CAN_IE_BECE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_BECE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_BECE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_BECE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_BECE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_BEUE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_BEUE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_BEUE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_BEUE) >> CAN_IE_BEUE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_BEUE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_BEUE; + tmp |= value << CAN_IE_BEUE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_BEUE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_BEUE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_BEUE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_BEUE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_ELOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_ELOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_ELOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_ELOE) >> CAN_IE_ELOE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_ELOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_ELOE; + tmp |= value << CAN_IE_ELOE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_ELOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_ELOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_ELOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_ELOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_EPE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_EPE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_EPE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_EPE) >> CAN_IE_EPE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_EPE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_EPE; + tmp |= value << CAN_IE_EPE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_EPE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_EPE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_EPE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_EPE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_EWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_EWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_EWE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_EWE) >> CAN_IE_EWE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_EWE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_EWE; + tmp |= value << CAN_IE_EWE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_EWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_EWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_EWE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_EWE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_BOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_BOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_BOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_BOE) >> CAN_IE_BOE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_BOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_BOE; + tmp |= value << CAN_IE_BOE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_BOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_BOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_BOE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_BOE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_WDIE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_WDIE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_WDIE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_WDIE) >> CAN_IE_WDIE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_WDIE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_WDIE; + tmp |= value << CAN_IE_WDIE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_WDIE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_WDIE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_WDIE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_WDIE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_PEAE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_PEAE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_PEAE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_PEAE) >> CAN_IE_PEAE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_PEAE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_PEAE; + tmp |= value << CAN_IE_PEAE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_PEAE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_PEAE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_PEAE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_PEAE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_PEDE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_PEDE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_PEDE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_PEDE) >> CAN_IE_PEDE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_PEDE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_PEDE; + tmp |= value << CAN_IE_PEDE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_PEDE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_PEDE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_PEDE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_PEDE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_ARAE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= CAN_IE_ARAE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_IE_ARAE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp = (tmp & CAN_IE_ARAE) >> CAN_IE_ARAE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_IE_ARAE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->IE.reg; + tmp &= ~CAN_IE_ARAE; + tmp |= value << CAN_IE_ARAE_Pos; + ((Can *)hw)->IE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_ARAE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~CAN_IE_ARAE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_ARAE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= CAN_IE_ARAE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_IE_reg(const void *const hw, hri_can_ie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ie_reg_t hri_can_get_IE_reg(const void *const hw, hri_can_ie_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->IE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_IE_reg(const void *const hw, hri_can_ie_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_IE_reg(const void *const hw, hri_can_ie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_IE_reg(const void *const hw, hri_can_ie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->IE.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ie_reg_t hri_can_read_IE_reg(const void *const hw) +{ + return ((Can *)hw)->IE.reg; +} + +static inline void hri_can_set_ILS_RF0NL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF0NL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF0NL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF0NL) >> CAN_ILS_RF0NL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF0NL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF0NL; + tmp |= value << CAN_ILS_RF0NL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF0NL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0NL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF0NL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF0NL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF0WL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF0WL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF0WL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF0WL) >> CAN_ILS_RF0WL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF0WL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF0WL; + tmp |= value << CAN_ILS_RF0WL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF0WL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0WL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF0WL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF0WL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF0FL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF0FL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF0FL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF0FL) >> CAN_ILS_RF0FL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF0FL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF0FL; + tmp |= value << CAN_ILS_RF0FL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF0FL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0FL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF0FL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF0FL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF0LL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF0LL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF0LL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF0LL) >> CAN_ILS_RF0LL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF0LL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF0LL; + tmp |= value << CAN_ILS_RF0LL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF0LL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF0LL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF0LL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF0LL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF1NL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF1NL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF1NL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF1NL) >> CAN_ILS_RF1NL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF1NL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF1NL; + tmp |= value << CAN_ILS_RF1NL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF1NL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1NL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF1NL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF1NL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF1WL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF1WL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF1WL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF1WL) >> CAN_ILS_RF1WL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF1WL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF1WL; + tmp |= value << CAN_ILS_RF1WL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF1WL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1WL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF1WL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF1WL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF1FL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF1FL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF1FL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF1FL) >> CAN_ILS_RF1FL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF1FL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF1FL; + tmp |= value << CAN_ILS_RF1FL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF1FL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1FL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF1FL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF1FL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_RF1LL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_RF1LL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_RF1LL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_RF1LL) >> CAN_ILS_RF1LL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_RF1LL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_RF1LL; + tmp |= value << CAN_ILS_RF1LL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_RF1LL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_RF1LL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_RF1LL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_RF1LL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_HPML_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_HPML; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_HPML_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_HPML) >> CAN_ILS_HPML_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_HPML_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_HPML; + tmp |= value << CAN_ILS_HPML_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_HPML_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_HPML; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_HPML_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_HPML; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TCL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TCL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TCL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TCL) >> CAN_ILS_TCL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TCL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TCL; + tmp |= value << CAN_ILS_TCL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TCL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TCL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TCL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TCL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TCFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TCFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TCFL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TCFL) >> CAN_ILS_TCFL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TCFL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TCFL; + tmp |= value << CAN_ILS_TCFL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TCFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TCFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TCFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TCFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TFEL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TFEL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TFEL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TFEL) >> CAN_ILS_TFEL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TFEL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TFEL; + tmp |= value << CAN_ILS_TFEL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TFEL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TFEL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TFEL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TFEL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TEFNL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TEFNL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TEFNL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TEFNL) >> CAN_ILS_TEFNL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TEFNL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TEFNL; + tmp |= value << CAN_ILS_TEFNL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TEFNL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFNL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TEFNL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TEFNL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TEFWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TEFWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TEFWL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TEFWL) >> CAN_ILS_TEFWL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TEFWL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TEFWL; + tmp |= value << CAN_ILS_TEFWL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TEFWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TEFWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TEFWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TEFFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TEFFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TEFFL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TEFFL) >> CAN_ILS_TEFFL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TEFFL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TEFFL; + tmp |= value << CAN_ILS_TEFFL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TEFFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TEFFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TEFFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TEFLL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TEFLL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TEFLL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TEFLL) >> CAN_ILS_TEFLL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TEFLL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TEFLL; + tmp |= value << CAN_ILS_TEFLL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TEFLL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TEFLL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TEFLL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TEFLL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TSWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TSWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TSWL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TSWL) >> CAN_ILS_TSWL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TSWL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TSWL; + tmp |= value << CAN_ILS_TSWL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TSWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TSWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TSWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TSWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_MRAFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_MRAFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_MRAFL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_MRAFL) >> CAN_ILS_MRAFL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_MRAFL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_MRAFL; + tmp |= value << CAN_ILS_MRAFL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_MRAFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_MRAFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_MRAFL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_MRAFL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_TOOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_TOOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_TOOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_TOOL) >> CAN_ILS_TOOL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_TOOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_TOOL; + tmp |= value << CAN_ILS_TOOL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_TOOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_TOOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_TOOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_TOOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_DRXL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_DRXL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_DRXL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_DRXL) >> CAN_ILS_DRXL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_DRXL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_DRXL; + tmp |= value << CAN_ILS_DRXL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_DRXL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_DRXL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_DRXL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_DRXL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_BECL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_BECL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_BECL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_BECL) >> CAN_ILS_BECL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_BECL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_BECL; + tmp |= value << CAN_ILS_BECL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_BECL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_BECL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_BECL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_BECL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_BEUL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_BEUL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_BEUL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_BEUL) >> CAN_ILS_BEUL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_BEUL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_BEUL; + tmp |= value << CAN_ILS_BEUL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_BEUL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_BEUL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_BEUL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_BEUL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_ELOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_ELOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_ELOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_ELOL) >> CAN_ILS_ELOL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_ELOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_ELOL; + tmp |= value << CAN_ILS_ELOL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_ELOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_ELOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_ELOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_ELOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_EPL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_EPL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_EPL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_EPL) >> CAN_ILS_EPL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_EPL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_EPL; + tmp |= value << CAN_ILS_EPL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_EPL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_EPL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_EPL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_EPL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_EWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_EWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_EWL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_EWL) >> CAN_ILS_EWL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_EWL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_EWL; + tmp |= value << CAN_ILS_EWL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_EWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_EWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_EWL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_EWL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_BOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_BOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_BOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_BOL) >> CAN_ILS_BOL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_BOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_BOL; + tmp |= value << CAN_ILS_BOL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_BOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_BOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_BOL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_BOL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_WDIL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_WDIL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_WDIL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_WDIL) >> CAN_ILS_WDIL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_WDIL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_WDIL; + tmp |= value << CAN_ILS_WDIL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_WDIL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_WDIL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_WDIL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_WDIL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_PEAL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_PEAL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_PEAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_PEAL) >> CAN_ILS_PEAL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_PEAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_PEAL; + tmp |= value << CAN_ILS_PEAL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_PEAL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_PEAL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_PEAL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_PEAL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_PEDL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_PEDL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_PEDL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_PEDL) >> CAN_ILS_PEDL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_PEDL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_PEDL; + tmp |= value << CAN_ILS_PEDL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_PEDL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_PEDL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_PEDL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_PEDL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_ARAL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= CAN_ILS_ARAL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILS_ARAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp = (tmp & CAN_ILS_ARAL) >> CAN_ILS_ARAL_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILS_ARAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILS.reg; + tmp &= ~CAN_ILS_ARAL; + tmp |= value << CAN_ILS_ARAL_Pos; + ((Can *)hw)->ILS.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_ARAL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~CAN_ILS_ARAL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_ARAL_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= CAN_ILS_ARAL; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILS_reg(const void *const hw, hri_can_ils_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ils_reg_t hri_can_get_ILS_reg(const void *const hw, hri_can_ils_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_ILS_reg(const void *const hw, hri_can_ils_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILS_reg(const void *const hw, hri_can_ils_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILS_reg(const void *const hw, hri_can_ils_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILS.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ils_reg_t hri_can_read_ILS_reg(const void *const hw) +{ + return ((Can *)hw)->ILS.reg; +} + +static inline void hri_can_set_ILE_EINT0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg |= CAN_ILE_EINT0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILE_EINT0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILE.reg; + tmp = (tmp & CAN_ILE_EINT0) >> CAN_ILE_EINT0_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILE_EINT0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILE.reg; + tmp &= ~CAN_ILE_EINT0; + tmp |= value << CAN_ILE_EINT0_Pos; + ((Can *)hw)->ILE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILE_EINT0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg &= ~CAN_ILE_EINT0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILE_EINT0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg ^= CAN_ILE_EINT0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILE_EINT1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg |= CAN_ILE_EINT1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_ILE_EINT1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILE.reg; + tmp = (tmp & CAN_ILE_EINT1) >> CAN_ILE_EINT1_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_ILE_EINT1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->ILE.reg; + tmp &= ~CAN_ILE_EINT1; + tmp |= value << CAN_ILE_EINT1_Pos; + ((Can *)hw)->ILE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILE_EINT1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg &= ~CAN_ILE_EINT1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILE_EINT1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg ^= CAN_ILE_EINT1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_ILE_reg(const void *const hw, hri_can_ile_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ile_reg_t hri_can_get_ILE_reg(const void *const hw, hri_can_ile_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->ILE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_ILE_reg(const void *const hw, hri_can_ile_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_ILE_reg(const void *const hw, hri_can_ile_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_ILE_reg(const void *const hw, hri_can_ile_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->ILE.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ile_reg_t hri_can_read_ILE_reg(const void *const hw) +{ + return ((Can *)hw)->ILE.reg; +} + +static inline void hri_can_set_GFC_RRFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg |= CAN_GFC_RRFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_GFC_RRFE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp = (tmp & CAN_GFC_RRFE) >> CAN_GFC_RRFE_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_GFC_RRFE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->GFC.reg; + tmp &= ~CAN_GFC_RRFE; + tmp |= value << CAN_GFC_RRFE_Pos; + ((Can *)hw)->GFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_GFC_RRFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg &= ~CAN_GFC_RRFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_GFC_RRFE_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg ^= CAN_GFC_RRFE; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_GFC_RRFS_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg |= CAN_GFC_RRFS; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_GFC_RRFS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp = (tmp & CAN_GFC_RRFS) >> CAN_GFC_RRFS_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_GFC_RRFS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->GFC.reg; + tmp &= ~CAN_GFC_RRFS; + tmp |= value << CAN_GFC_RRFS_Pos; + ((Can *)hw)->GFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_GFC_RRFS_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg &= ~CAN_GFC_RRFS; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_GFC_RRFS_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg ^= CAN_GFC_RRFS; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg |= CAN_GFC_ANFE(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_gfc_reg_t hri_can_get_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp = (tmp & CAN_GFC_ANFE(mask)) >> CAN_GFC_ANFE_Pos; + return tmp; +} + +static inline void hri_can_write_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->GFC.reg; + tmp &= ~CAN_GFC_ANFE_Msk; + tmp |= CAN_GFC_ANFE(data); + ((Can *)hw)->GFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg &= ~CAN_GFC_ANFE(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_GFC_ANFE_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg ^= CAN_GFC_ANFE(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_gfc_reg_t hri_can_read_GFC_ANFE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp = (tmp & CAN_GFC_ANFE_Msk) >> CAN_GFC_ANFE_Pos; + return tmp; +} + +static inline void hri_can_set_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg |= CAN_GFC_ANFS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_gfc_reg_t hri_can_get_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp = (tmp & CAN_GFC_ANFS(mask)) >> CAN_GFC_ANFS_Pos; + return tmp; +} + +static inline void hri_can_write_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->GFC.reg; + tmp &= ~CAN_GFC_ANFS_Msk; + tmp |= CAN_GFC_ANFS(data); + ((Can *)hw)->GFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg &= ~CAN_GFC_ANFS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_GFC_ANFS_bf(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg ^= CAN_GFC_ANFS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_gfc_reg_t hri_can_read_GFC_ANFS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp = (tmp & CAN_GFC_ANFS_Msk) >> CAN_GFC_ANFS_Pos; + return tmp; +} + +static inline void hri_can_set_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_gfc_reg_t hri_can_get_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->GFC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_GFC_reg(const void *const hw, hri_can_gfc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_GFC_reg(const void *const hw, hri_can_gfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->GFC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_gfc_reg_t hri_can_read_GFC_reg(const void *const hw) +{ + return ((Can *)hw)->GFC.reg; +} + +static inline void hri_can_set_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg |= CAN_SIDFC_FLSSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_sidfc_reg_t hri_can_get_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->SIDFC.reg; + tmp = (tmp & CAN_SIDFC_FLSSA(mask)) >> CAN_SIDFC_FLSSA_Pos; + return tmp; +} + +static inline void hri_can_write_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->SIDFC.reg; + tmp &= ~CAN_SIDFC_FLSSA_Msk; + tmp |= CAN_SIDFC_FLSSA(data); + ((Can *)hw)->SIDFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg &= ~CAN_SIDFC_FLSSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_SIDFC_FLSSA_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg ^= CAN_SIDFC_FLSSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_sidfc_reg_t hri_can_read_SIDFC_FLSSA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->SIDFC.reg; + tmp = (tmp & CAN_SIDFC_FLSSA_Msk) >> CAN_SIDFC_FLSSA_Pos; + return tmp; +} + +static inline void hri_can_set_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg |= CAN_SIDFC_LSS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_sidfc_reg_t hri_can_get_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->SIDFC.reg; + tmp = (tmp & CAN_SIDFC_LSS(mask)) >> CAN_SIDFC_LSS_Pos; + return tmp; +} + +static inline void hri_can_write_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->SIDFC.reg; + tmp &= ~CAN_SIDFC_LSS_Msk; + tmp |= CAN_SIDFC_LSS(data); + ((Can *)hw)->SIDFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg &= ~CAN_SIDFC_LSS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_SIDFC_LSS_bf(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg ^= CAN_SIDFC_LSS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_sidfc_reg_t hri_can_read_SIDFC_LSS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->SIDFC.reg; + tmp = (tmp & CAN_SIDFC_LSS_Msk) >> CAN_SIDFC_LSS_Pos; + return tmp; +} + +static inline void hri_can_set_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_sidfc_reg_t hri_can_get_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->SIDFC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_SIDFC_reg(const void *const hw, hri_can_sidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->SIDFC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_sidfc_reg_t hri_can_read_SIDFC_reg(const void *const hw) +{ + return ((Can *)hw)->SIDFC.reg; +} + +static inline void hri_can_set_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg |= CAN_XIDFC_FLESA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidfc_reg_t hri_can_get_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDFC.reg; + tmp = (tmp & CAN_XIDFC_FLESA(mask)) >> CAN_XIDFC_FLESA_Pos; + return tmp; +} + +static inline void hri_can_write_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->XIDFC.reg; + tmp &= ~CAN_XIDFC_FLESA_Msk; + tmp |= CAN_XIDFC_FLESA(data); + ((Can *)hw)->XIDFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg &= ~CAN_XIDFC_FLESA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_XIDFC_FLESA_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg ^= CAN_XIDFC_FLESA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidfc_reg_t hri_can_read_XIDFC_FLESA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDFC.reg; + tmp = (tmp & CAN_XIDFC_FLESA_Msk) >> CAN_XIDFC_FLESA_Pos; + return tmp; +} + +static inline void hri_can_set_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg |= CAN_XIDFC_LSE(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidfc_reg_t hri_can_get_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDFC.reg; + tmp = (tmp & CAN_XIDFC_LSE(mask)) >> CAN_XIDFC_LSE_Pos; + return tmp; +} + +static inline void hri_can_write_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->XIDFC.reg; + tmp &= ~CAN_XIDFC_LSE_Msk; + tmp |= CAN_XIDFC_LSE(data); + ((Can *)hw)->XIDFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg &= ~CAN_XIDFC_LSE(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_XIDFC_LSE_bf(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg ^= CAN_XIDFC_LSE(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidfc_reg_t hri_can_read_XIDFC_LSE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDFC.reg; + tmp = (tmp & CAN_XIDFC_LSE_Msk) >> CAN_XIDFC_LSE_Pos; + return tmp; +} + +static inline void hri_can_set_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidfc_reg_t hri_can_get_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDFC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_XIDFC_reg(const void *const hw, hri_can_xidfc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDFC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidfc_reg_t hri_can_read_XIDFC_reg(const void *const hw) +{ + return ((Can *)hw)->XIDFC.reg; +} + +static inline void hri_can_set_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg |= CAN_XIDAM_EIDM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidam_reg_t hri_can_get_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDAM.reg; + tmp = (tmp & CAN_XIDAM_EIDM(mask)) >> CAN_XIDAM_EIDM_Pos; + return tmp; +} + +static inline void hri_can_write_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->XIDAM.reg; + tmp &= ~CAN_XIDAM_EIDM_Msk; + tmp |= CAN_XIDAM_EIDM(data); + ((Can *)hw)->XIDAM.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg &= ~CAN_XIDAM_EIDM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_XIDAM_EIDM_bf(const void *const hw, hri_can_xidam_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg ^= CAN_XIDAM_EIDM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidam_reg_t hri_can_read_XIDAM_EIDM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDAM.reg; + tmp = (tmp & CAN_XIDAM_EIDM_Msk) >> CAN_XIDAM_EIDM_Pos; + return tmp; +} + +static inline void hri_can_set_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidam_reg_t hri_can_get_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->XIDAM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_XIDAM_reg(const void *const hw, hri_can_xidam_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->XIDAM.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_xidam_reg_t hri_can_read_XIDAM_reg(const void *const hw) +{ + return ((Can *)hw)->XIDAM.reg; +} + +static inline void hri_can_set_NDAT1_ND0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND0) >> CAN_NDAT1_ND0_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND0; + tmp |= value << CAN_NDAT1_ND0_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND1) >> CAN_NDAT1_ND1_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND1; + tmp |= value << CAN_NDAT1_ND1_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND2) >> CAN_NDAT1_ND2_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND2; + tmp |= value << CAN_NDAT1_ND2_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND3) >> CAN_NDAT1_ND3_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND3; + tmp |= value << CAN_NDAT1_ND3_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND4) >> CAN_NDAT1_ND4_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND4; + tmp |= value << CAN_NDAT1_ND4_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND5) >> CAN_NDAT1_ND5_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND5; + tmp |= value << CAN_NDAT1_ND5_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND6) >> CAN_NDAT1_ND6_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND6; + tmp |= value << CAN_NDAT1_ND6_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND7) >> CAN_NDAT1_ND7_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND7; + tmp |= value << CAN_NDAT1_ND7_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND8) >> CAN_NDAT1_ND8_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND8; + tmp |= value << CAN_NDAT1_ND8_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND9) >> CAN_NDAT1_ND9_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND9; + tmp |= value << CAN_NDAT1_ND9_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND10) >> CAN_NDAT1_ND10_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND10; + tmp |= value << CAN_NDAT1_ND10_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND11) >> CAN_NDAT1_ND11_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND11; + tmp |= value << CAN_NDAT1_ND11_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND12) >> CAN_NDAT1_ND12_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND12; + tmp |= value << CAN_NDAT1_ND12_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND13) >> CAN_NDAT1_ND13_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND13; + tmp |= value << CAN_NDAT1_ND13_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND14) >> CAN_NDAT1_ND14_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND14; + tmp |= value << CAN_NDAT1_ND14_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND15) >> CAN_NDAT1_ND15_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND15; + tmp |= value << CAN_NDAT1_ND15_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND16) >> CAN_NDAT1_ND16_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND16; + tmp |= value << CAN_NDAT1_ND16_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND17) >> CAN_NDAT1_ND17_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND17; + tmp |= value << CAN_NDAT1_ND17_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND18) >> CAN_NDAT1_ND18_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND18; + tmp |= value << CAN_NDAT1_ND18_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND19) >> CAN_NDAT1_ND19_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND19; + tmp |= value << CAN_NDAT1_ND19_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND20) >> CAN_NDAT1_ND20_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND20; + tmp |= value << CAN_NDAT1_ND20_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND21) >> CAN_NDAT1_ND21_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND21; + tmp |= value << CAN_NDAT1_ND21_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND22) >> CAN_NDAT1_ND22_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND22; + tmp |= value << CAN_NDAT1_ND22_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND23) >> CAN_NDAT1_ND23_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND23; + tmp |= value << CAN_NDAT1_ND23_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND24) >> CAN_NDAT1_ND24_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND24; + tmp |= value << CAN_NDAT1_ND24_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND25) >> CAN_NDAT1_ND25_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND25; + tmp |= value << CAN_NDAT1_ND25_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND26) >> CAN_NDAT1_ND26_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND26; + tmp |= value << CAN_NDAT1_ND26_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND27) >> CAN_NDAT1_ND27_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND27; + tmp |= value << CAN_NDAT1_ND27_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND28) >> CAN_NDAT1_ND28_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND28; + tmp |= value << CAN_NDAT1_ND28_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND29) >> CAN_NDAT1_ND29_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND29; + tmp |= value << CAN_NDAT1_ND29_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND30) >> CAN_NDAT1_ND30_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND30; + tmp |= value << CAN_NDAT1_ND30_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_ND31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= CAN_NDAT1_ND31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT1_ND31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp = (tmp & CAN_NDAT1_ND31) >> CAN_NDAT1_ND31_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT1_ND31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= ~CAN_NDAT1_ND31; + tmp |= value << CAN_NDAT1_ND31_Pos; + ((Can *)hw)->NDAT1.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_ND31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~CAN_NDAT1_ND31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_ND31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= CAN_NDAT1_ND31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ndat1_reg_t hri_can_get_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT1.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT1_reg(const void *const hw, hri_can_ndat1_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT1.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ndat1_reg_t hri_can_read_NDAT1_reg(const void *const hw) +{ + return ((Can *)hw)->NDAT1.reg; +} + +static inline void hri_can_set_NDAT2_ND32_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND32; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND32_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND32) >> CAN_NDAT2_ND32_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND32_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND32; + tmp |= value << CAN_NDAT2_ND32_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND32_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND32; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND32_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND32; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND33_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND33; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND33_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND33) >> CAN_NDAT2_ND33_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND33_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND33; + tmp |= value << CAN_NDAT2_ND33_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND33_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND33; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND33_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND33; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND34_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND34; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND34_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND34) >> CAN_NDAT2_ND34_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND34_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND34; + tmp |= value << CAN_NDAT2_ND34_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND34_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND34; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND34_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND34; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND35_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND35; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND35_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND35) >> CAN_NDAT2_ND35_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND35_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND35; + tmp |= value << CAN_NDAT2_ND35_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND35_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND35; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND35_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND35; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND36_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND36; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND36_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND36) >> CAN_NDAT2_ND36_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND36_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND36; + tmp |= value << CAN_NDAT2_ND36_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND36_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND36; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND36_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND36; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND37_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND37; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND37_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND37) >> CAN_NDAT2_ND37_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND37_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND37; + tmp |= value << CAN_NDAT2_ND37_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND37_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND37; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND37_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND37; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND38_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND38; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND38_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND38) >> CAN_NDAT2_ND38_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND38_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND38; + tmp |= value << CAN_NDAT2_ND38_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND38_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND38; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND38_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND38; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND39_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND39; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND39_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND39) >> CAN_NDAT2_ND39_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND39_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND39; + tmp |= value << CAN_NDAT2_ND39_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND39_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND39; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND39_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND39; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND40_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND40; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND40_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND40) >> CAN_NDAT2_ND40_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND40_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND40; + tmp |= value << CAN_NDAT2_ND40_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND40_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND40; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND40_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND40; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND41_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND41; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND41_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND41) >> CAN_NDAT2_ND41_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND41_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND41; + tmp |= value << CAN_NDAT2_ND41_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND41_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND41; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND41_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND41; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND42_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND42; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND42_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND42) >> CAN_NDAT2_ND42_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND42_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND42; + tmp |= value << CAN_NDAT2_ND42_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND42_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND42; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND42_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND42; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND43_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND43; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND43_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND43) >> CAN_NDAT2_ND43_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND43_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND43; + tmp |= value << CAN_NDAT2_ND43_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND43_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND43; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND43_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND43; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND44_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND44; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND44_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND44) >> CAN_NDAT2_ND44_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND44_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND44; + tmp |= value << CAN_NDAT2_ND44_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND44_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND44; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND44_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND44; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND45_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND45; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND45_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND45) >> CAN_NDAT2_ND45_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND45_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND45; + tmp |= value << CAN_NDAT2_ND45_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND45_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND45; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND45_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND45; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND46_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND46; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND46_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND46) >> CAN_NDAT2_ND46_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND46_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND46; + tmp |= value << CAN_NDAT2_ND46_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND46_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND46; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND46_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND46; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND47_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND47; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND47_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND47) >> CAN_NDAT2_ND47_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND47_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND47; + tmp |= value << CAN_NDAT2_ND47_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND47_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND47; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND47_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND47; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND48_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND48; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND48_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND48) >> CAN_NDAT2_ND48_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND48_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND48; + tmp |= value << CAN_NDAT2_ND48_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND48_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND48; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND48_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND48; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND49_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND49; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND49_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND49) >> CAN_NDAT2_ND49_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND49_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND49; + tmp |= value << CAN_NDAT2_ND49_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND49_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND49; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND49_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND49; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND50_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND50; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND50_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND50) >> CAN_NDAT2_ND50_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND50_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND50; + tmp |= value << CAN_NDAT2_ND50_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND50_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND50; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND50_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND50; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND51_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND51; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND51_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND51) >> CAN_NDAT2_ND51_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND51_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND51; + tmp |= value << CAN_NDAT2_ND51_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND51_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND51; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND51_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND51; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND52_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND52; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND52_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND52) >> CAN_NDAT2_ND52_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND52_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND52; + tmp |= value << CAN_NDAT2_ND52_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND52_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND52; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND52_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND52; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND53_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND53; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND53_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND53) >> CAN_NDAT2_ND53_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND53_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND53; + tmp |= value << CAN_NDAT2_ND53_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND53_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND53; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND53_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND53; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND54_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND54; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND54_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND54) >> CAN_NDAT2_ND54_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND54_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND54; + tmp |= value << CAN_NDAT2_ND54_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND54_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND54; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND54_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND54; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND55_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND55; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND55_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND55) >> CAN_NDAT2_ND55_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND55_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND55; + tmp |= value << CAN_NDAT2_ND55_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND55_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND55; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND55_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND55; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND56_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND56; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND56_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND56) >> CAN_NDAT2_ND56_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND56_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND56; + tmp |= value << CAN_NDAT2_ND56_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND56_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND56; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND56_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND56; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND57_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND57; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND57_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND57) >> CAN_NDAT2_ND57_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND57_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND57; + tmp |= value << CAN_NDAT2_ND57_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND57_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND57; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND57_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND57; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND58_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND58; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND58_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND58) >> CAN_NDAT2_ND58_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND58_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND58; + tmp |= value << CAN_NDAT2_ND58_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND58_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND58; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND58_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND58; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND59_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND59; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND59_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND59) >> CAN_NDAT2_ND59_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND59_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND59; + tmp |= value << CAN_NDAT2_ND59_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND59_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND59; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND59_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND59; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND60_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND60; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND60_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND60) >> CAN_NDAT2_ND60_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND60_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND60; + tmp |= value << CAN_NDAT2_ND60_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND60_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND60; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND60_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND60; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND61_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND61; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND61_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND61) >> CAN_NDAT2_ND61_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND61_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND61; + tmp |= value << CAN_NDAT2_ND61_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND61_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND61; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND61_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND61; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND62_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND62; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND62_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND62) >> CAN_NDAT2_ND62_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND62_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND62; + tmp |= value << CAN_NDAT2_ND62_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND62_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND62; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND62_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND62; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_ND63_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= CAN_NDAT2_ND63; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_NDAT2_ND63_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp = (tmp & CAN_NDAT2_ND63) >> CAN_NDAT2_ND63_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_NDAT2_ND63_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= ~CAN_NDAT2_ND63; + tmp |= value << CAN_NDAT2_ND63_Pos; + ((Can *)hw)->NDAT2.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_ND63_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~CAN_NDAT2_ND63; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_ND63_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= CAN_NDAT2_ND63; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ndat2_reg_t hri_can_get_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->NDAT2.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_NDAT2_reg(const void *const hw, hri_can_ndat2_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->NDAT2.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_ndat2_reg_t hri_can_read_NDAT2_reg(const void *const hw) +{ + return ((Can *)hw)->NDAT2.reg; +} + +static inline void hri_can_set_RXF0C_F0OM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0OM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_RXF0C_F0OM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0OM) >> CAN_RXF0C_F0OM_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_RXF0C_F0OM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF0C.reg; + tmp &= ~CAN_RXF0C_F0OM; + tmp |= value << CAN_RXF0C_F0OM_Pos; + ((Can *)hw)->RXF0C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0C_F0OM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0OM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0C_F0OM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0OM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0SA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0SA(mask)) >> CAN_RXF0C_F0SA_Pos; + return tmp; +} + +static inline void hri_can_write_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF0C.reg; + tmp &= ~CAN_RXF0C_F0SA_Msk; + tmp |= CAN_RXF0C_F0SA(data); + ((Can *)hw)->RXF0C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0SA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0C_F0SA_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0SA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_F0SA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0SA_Msk) >> CAN_RXF0C_F0SA_Pos; + return tmp; +} + +static inline void hri_can_set_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0S(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0S(mask)) >> CAN_RXF0C_F0S_Pos; + return tmp; +} + +static inline void hri_can_write_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF0C.reg; + tmp &= ~CAN_RXF0C_F0S_Msk; + tmp |= CAN_RXF0C_F0S(data); + ((Can *)hw)->RXF0C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0S(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0C_F0S_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0S(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_F0S_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0S_Msk) >> CAN_RXF0C_F0S_Pos; + return tmp; +} + +static inline void hri_can_set_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg |= CAN_RXF0C_F0WM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0WM(mask)) >> CAN_RXF0C_F0WM_Pos; + return tmp; +} + +static inline void hri_can_write_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF0C.reg; + tmp &= ~CAN_RXF0C_F0WM_Msk; + tmp |= CAN_RXF0C_F0WM(data); + ((Can *)hw)->RXF0C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg &= ~CAN_RXF0C_F0WM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0C_F0WM_bf(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg ^= CAN_RXF0C_F0WM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_F0WM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp = (tmp & CAN_RXF0C_F0WM_Msk) >> CAN_RXF0C_F0WM_Pos; + return tmp; +} + +static inline void hri_can_set_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_get_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0C.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0C_reg(const void *const hw, hri_can_rxf0c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0C.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0c_reg_t hri_can_read_RXF0C_reg(const void *const hw) +{ + return ((Can *)hw)->RXF0C.reg; +} + +static inline void hri_can_set_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg |= CAN_RXF0A_F0AI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0a_reg_t hri_can_get_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0A.reg; + tmp = (tmp & CAN_RXF0A_F0AI(mask)) >> CAN_RXF0A_F0AI_Pos; + return tmp; +} + +static inline void hri_can_write_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF0A.reg; + tmp &= ~CAN_RXF0A_F0AI_Msk; + tmp |= CAN_RXF0A_F0AI(data); + ((Can *)hw)->RXF0A.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg &= ~CAN_RXF0A_F0AI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0A_F0AI_bf(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg ^= CAN_RXF0A_F0AI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0a_reg_t hri_can_read_RXF0A_F0AI_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0A.reg; + tmp = (tmp & CAN_RXF0A_F0AI_Msk) >> CAN_RXF0A_F0AI_Pos; + return tmp; +} + +static inline void hri_can_set_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0a_reg_t hri_can_get_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF0A.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF0A_reg(const void *const hw, hri_can_rxf0a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF0A.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf0a_reg_t hri_can_read_RXF0A_reg(const void *const hw) +{ + return ((Can *)hw)->RXF0A.reg; +} + +static inline void hri_can_set_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg |= CAN_RXBC_RBSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxbc_reg_t hri_can_get_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXBC.reg; + tmp = (tmp & CAN_RXBC_RBSA(mask)) >> CAN_RXBC_RBSA_Pos; + return tmp; +} + +static inline void hri_can_write_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXBC.reg; + tmp &= ~CAN_RXBC_RBSA_Msk; + tmp |= CAN_RXBC_RBSA(data); + ((Can *)hw)->RXBC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg &= ~CAN_RXBC_RBSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXBC_RBSA_bf(const void *const hw, hri_can_rxbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg ^= CAN_RXBC_RBSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxbc_reg_t hri_can_read_RXBC_RBSA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXBC.reg; + tmp = (tmp & CAN_RXBC_RBSA_Msk) >> CAN_RXBC_RBSA_Pos; + return tmp; +} + +static inline void hri_can_set_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxbc_reg_t hri_can_get_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXBC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXBC_reg(const void *const hw, hri_can_rxbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXBC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxbc_reg_t hri_can_read_RXBC_reg(const void *const hw) +{ + return ((Can *)hw)->RXBC.reg; +} + +static inline void hri_can_set_RXF1C_F1OM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1OM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_RXF1C_F1OM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1OM) >> CAN_RXF1C_F1OM_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_RXF1C_F1OM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF1C.reg; + tmp &= ~CAN_RXF1C_F1OM; + tmp |= value << CAN_RXF1C_F1OM_Pos; + ((Can *)hw)->RXF1C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1C_F1OM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1OM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1C_F1OM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1OM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1SA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1SA(mask)) >> CAN_RXF1C_F1SA_Pos; + return tmp; +} + +static inline void hri_can_write_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF1C.reg; + tmp &= ~CAN_RXF1C_F1SA_Msk; + tmp |= CAN_RXF1C_F1SA(data); + ((Can *)hw)->RXF1C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1SA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1C_F1SA_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1SA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_F1SA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1SA_Msk) >> CAN_RXF1C_F1SA_Pos; + return tmp; +} + +static inline void hri_can_set_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1S(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1S(mask)) >> CAN_RXF1C_F1S_Pos; + return tmp; +} + +static inline void hri_can_write_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF1C.reg; + tmp &= ~CAN_RXF1C_F1S_Msk; + tmp |= CAN_RXF1C_F1S(data); + ((Can *)hw)->RXF1C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1S(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1C_F1S_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1S(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_F1S_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1S_Msk) >> CAN_RXF1C_F1S_Pos; + return tmp; +} + +static inline void hri_can_set_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg |= CAN_RXF1C_F1WM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1WM(mask)) >> CAN_RXF1C_F1WM_Pos; + return tmp; +} + +static inline void hri_can_write_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF1C.reg; + tmp &= ~CAN_RXF1C_F1WM_Msk; + tmp |= CAN_RXF1C_F1WM(data); + ((Can *)hw)->RXF1C.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg &= ~CAN_RXF1C_F1WM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1C_F1WM_bf(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg ^= CAN_RXF1C_F1WM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_F1WM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp = (tmp & CAN_RXF1C_F1WM_Msk) >> CAN_RXF1C_F1WM_Pos; + return tmp; +} + +static inline void hri_can_set_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_get_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1C.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1C_reg(const void *const hw, hri_can_rxf1c_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1C.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1c_reg_t hri_can_read_RXF1C_reg(const void *const hw) +{ + return ((Can *)hw)->RXF1C.reg; +} + +static inline void hri_can_set_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg |= CAN_RXF1A_F1AI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1a_reg_t hri_can_get_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1A.reg; + tmp = (tmp & CAN_RXF1A_F1AI(mask)) >> CAN_RXF1A_F1AI_Pos; + return tmp; +} + +static inline void hri_can_write_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXF1A.reg; + tmp &= ~CAN_RXF1A_F1AI_Msk; + tmp |= CAN_RXF1A_F1AI(data); + ((Can *)hw)->RXF1A.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg &= ~CAN_RXF1A_F1AI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1A_F1AI_bf(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg ^= CAN_RXF1A_F1AI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1a_reg_t hri_can_read_RXF1A_F1AI_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1A.reg; + tmp = (tmp & CAN_RXF1A_F1AI_Msk) >> CAN_RXF1A_F1AI_Pos; + return tmp; +} + +static inline void hri_can_set_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1a_reg_t hri_can_get_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXF1A.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXF1A_reg(const void *const hw, hri_can_rxf1a_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXF1A.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxf1a_reg_t hri_can_read_RXF1A_reg(const void *const hw) +{ + return ((Can *)hw)->RXF1A.reg; +} + +static inline void hri_can_set_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg |= CAN_RXESC_F0DS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_get_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp = (tmp & CAN_RXESC_F0DS(mask)) >> CAN_RXESC_F0DS_Pos; + return tmp; +} + +static inline void hri_can_write_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXESC.reg; + tmp &= ~CAN_RXESC_F0DS_Msk; + tmp |= CAN_RXESC_F0DS(data); + ((Can *)hw)->RXESC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg &= ~CAN_RXESC_F0DS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXESC_F0DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg ^= CAN_RXESC_F0DS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_read_RXESC_F0DS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp = (tmp & CAN_RXESC_F0DS_Msk) >> CAN_RXESC_F0DS_Pos; + return tmp; +} + +static inline void hri_can_set_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg |= CAN_RXESC_F1DS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_get_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp = (tmp & CAN_RXESC_F1DS(mask)) >> CAN_RXESC_F1DS_Pos; + return tmp; +} + +static inline void hri_can_write_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXESC.reg; + tmp &= ~CAN_RXESC_F1DS_Msk; + tmp |= CAN_RXESC_F1DS(data); + ((Can *)hw)->RXESC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg &= ~CAN_RXESC_F1DS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXESC_F1DS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg ^= CAN_RXESC_F1DS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_read_RXESC_F1DS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp = (tmp & CAN_RXESC_F1DS_Msk) >> CAN_RXESC_F1DS_Pos; + return tmp; +} + +static inline void hri_can_set_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg |= CAN_RXESC_RBDS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_get_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp = (tmp & CAN_RXESC_RBDS(mask)) >> CAN_RXESC_RBDS_Pos; + return tmp; +} + +static inline void hri_can_write_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->RXESC.reg; + tmp &= ~CAN_RXESC_RBDS_Msk; + tmp |= CAN_RXESC_RBDS(data); + ((Can *)hw)->RXESC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg &= ~CAN_RXESC_RBDS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXESC_RBDS_bf(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg ^= CAN_RXESC_RBDS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_read_RXESC_RBDS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp = (tmp & CAN_RXESC_RBDS_Msk) >> CAN_RXESC_RBDS_Pos; + return tmp; +} + +static inline void hri_can_set_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_get_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->RXESC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_RXESC_reg(const void *const hw, hri_can_rxesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->RXESC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_rxesc_reg_t hri_can_read_RXESC_reg(const void *const hw) +{ + return ((Can *)hw)->RXESC.reg; +} + +static inline void hri_can_set_TXBC_TFQM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg |= CAN_TXBC_TFQM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBC_TFQM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_TFQM) >> CAN_TXBC_TFQM_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBC_TFQM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBC.reg; + tmp &= ~CAN_TXBC_TFQM; + tmp |= value << CAN_TXBC_TFQM_Pos; + ((Can *)hw)->TXBC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBC_TFQM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg &= ~CAN_TXBC_TFQM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBC_TFQM_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg ^= CAN_TXBC_TFQM; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg |= CAN_TXBC_TBSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_get_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_TBSA(mask)) >> CAN_TXBC_TBSA_Pos; + return tmp; +} + +static inline void hri_can_write_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBC.reg; + tmp &= ~CAN_TXBC_TBSA_Msk; + tmp |= CAN_TXBC_TBSA(data); + ((Can *)hw)->TXBC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg &= ~CAN_TXBC_TBSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBC_TBSA_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg ^= CAN_TXBC_TBSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_read_TXBC_TBSA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_TBSA_Msk) >> CAN_TXBC_TBSA_Pos; + return tmp; +} + +static inline void hri_can_set_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg |= CAN_TXBC_NDTB(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_get_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_NDTB(mask)) >> CAN_TXBC_NDTB_Pos; + return tmp; +} + +static inline void hri_can_write_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBC.reg; + tmp &= ~CAN_TXBC_NDTB_Msk; + tmp |= CAN_TXBC_NDTB(data); + ((Can *)hw)->TXBC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg &= ~CAN_TXBC_NDTB(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBC_NDTB_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg ^= CAN_TXBC_NDTB(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_read_TXBC_NDTB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_NDTB_Msk) >> CAN_TXBC_NDTB_Pos; + return tmp; +} + +static inline void hri_can_set_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg |= CAN_TXBC_TFQS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_get_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_TFQS(mask)) >> CAN_TXBC_TFQS_Pos; + return tmp; +} + +static inline void hri_can_write_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBC.reg; + tmp &= ~CAN_TXBC_TFQS_Msk; + tmp |= CAN_TXBC_TFQS(data); + ((Can *)hw)->TXBC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg &= ~CAN_TXBC_TFQS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBC_TFQS_bf(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg ^= CAN_TXBC_TFQS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_read_TXBC_TFQS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp = (tmp & CAN_TXBC_TFQS_Msk) >> CAN_TXBC_TFQS_Pos; + return tmp; +} + +static inline void hri_can_set_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_get_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXBC_reg(const void *const hw, hri_can_txbc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBC_reg(const void *const hw, hri_can_txbc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbc_reg_t hri_can_read_TXBC_reg(const void *const hw) +{ + return ((Can *)hw)->TXBC.reg; +} + +static inline void hri_can_set_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg |= CAN_TXESC_TBDS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txesc_reg_t hri_can_get_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXESC.reg; + tmp = (tmp & CAN_TXESC_TBDS(mask)) >> CAN_TXESC_TBDS_Pos; + return tmp; +} + +static inline void hri_can_write_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXESC.reg; + tmp &= ~CAN_TXESC_TBDS_Msk; + tmp |= CAN_TXESC_TBDS(data); + ((Can *)hw)->TXESC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg &= ~CAN_TXESC_TBDS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXESC_TBDS_bf(const void *const hw, hri_can_txesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg ^= CAN_TXESC_TBDS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txesc_reg_t hri_can_read_TXESC_TBDS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXESC.reg; + tmp = (tmp & CAN_TXESC_TBDS_Msk) >> CAN_TXESC_TBDS_Pos; + return tmp; +} + +static inline void hri_can_set_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txesc_reg_t hri_can_get_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXESC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXESC_reg(const void *const hw, hri_can_txesc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXESC_reg(const void *const hw, hri_can_txesc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXESC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txesc_reg_t hri_can_read_TXESC_reg(const void *const hw) +{ + return ((Can *)hw)->TXESC.reg; +} + +static inline void hri_can_set_TXBAR_AR0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR0) >> CAN_TXBAR_AR0_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR0; + tmp |= value << CAN_TXBAR_AR0_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR1) >> CAN_TXBAR_AR1_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR1; + tmp |= value << CAN_TXBAR_AR1_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR2) >> CAN_TXBAR_AR2_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR2; + tmp |= value << CAN_TXBAR_AR2_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR3) >> CAN_TXBAR_AR3_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR3; + tmp |= value << CAN_TXBAR_AR3_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR4) >> CAN_TXBAR_AR4_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR4; + tmp |= value << CAN_TXBAR_AR4_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR5) >> CAN_TXBAR_AR5_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR5; + tmp |= value << CAN_TXBAR_AR5_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR6) >> CAN_TXBAR_AR6_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR6; + tmp |= value << CAN_TXBAR_AR6_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR7) >> CAN_TXBAR_AR7_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR7; + tmp |= value << CAN_TXBAR_AR7_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR8) >> CAN_TXBAR_AR8_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR8; + tmp |= value << CAN_TXBAR_AR8_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR9) >> CAN_TXBAR_AR9_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR9; + tmp |= value << CAN_TXBAR_AR9_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR10) >> CAN_TXBAR_AR10_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR10; + tmp |= value << CAN_TXBAR_AR10_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR11) >> CAN_TXBAR_AR11_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR11; + tmp |= value << CAN_TXBAR_AR11_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR12) >> CAN_TXBAR_AR12_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR12; + tmp |= value << CAN_TXBAR_AR12_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR13) >> CAN_TXBAR_AR13_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR13; + tmp |= value << CAN_TXBAR_AR13_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR14) >> CAN_TXBAR_AR14_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR14; + tmp |= value << CAN_TXBAR_AR14_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR15) >> CAN_TXBAR_AR15_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR15; + tmp |= value << CAN_TXBAR_AR15_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR16) >> CAN_TXBAR_AR16_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR16; + tmp |= value << CAN_TXBAR_AR16_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR17) >> CAN_TXBAR_AR17_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR17; + tmp |= value << CAN_TXBAR_AR17_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR18) >> CAN_TXBAR_AR18_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR18; + tmp |= value << CAN_TXBAR_AR18_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR19) >> CAN_TXBAR_AR19_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR19; + tmp |= value << CAN_TXBAR_AR19_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR20) >> CAN_TXBAR_AR20_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR20; + tmp |= value << CAN_TXBAR_AR20_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR21) >> CAN_TXBAR_AR21_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR21; + tmp |= value << CAN_TXBAR_AR21_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR22) >> CAN_TXBAR_AR22_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR22; + tmp |= value << CAN_TXBAR_AR22_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR23) >> CAN_TXBAR_AR23_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR23; + tmp |= value << CAN_TXBAR_AR23_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR24) >> CAN_TXBAR_AR24_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR24; + tmp |= value << CAN_TXBAR_AR24_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR25) >> CAN_TXBAR_AR25_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR25; + tmp |= value << CAN_TXBAR_AR25_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR26) >> CAN_TXBAR_AR26_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR26; + tmp |= value << CAN_TXBAR_AR26_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR27) >> CAN_TXBAR_AR27_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR27; + tmp |= value << CAN_TXBAR_AR27_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR28) >> CAN_TXBAR_AR28_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR28; + tmp |= value << CAN_TXBAR_AR28_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR29) >> CAN_TXBAR_AR29_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR29; + tmp |= value << CAN_TXBAR_AR29_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR30) >> CAN_TXBAR_AR30_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR30; + tmp |= value << CAN_TXBAR_AR30_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_AR31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= CAN_TXBAR_AR31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBAR_AR31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp = (tmp & CAN_TXBAR_AR31) >> CAN_TXBAR_AR31_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBAR_AR31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= ~CAN_TXBAR_AR31; + tmp |= value << CAN_TXBAR_AR31_Pos; + ((Can *)hw)->TXBAR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_AR31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~CAN_TXBAR_AR31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_AR31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= CAN_TXBAR_AR31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbar_reg_t hri_can_get_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBAR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBAR_reg(const void *const hw, hri_can_txbar_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBAR.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbar_reg_t hri_can_read_TXBAR_reg(const void *const hw) +{ + return ((Can *)hw)->TXBAR.reg; +} + +static inline void hri_can_set_TXBCR_CR0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR0) >> CAN_TXBCR_CR0_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR0; + tmp |= value << CAN_TXBCR_CR0_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR1) >> CAN_TXBCR_CR1_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR1; + tmp |= value << CAN_TXBCR_CR1_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR2) >> CAN_TXBCR_CR2_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR2; + tmp |= value << CAN_TXBCR_CR2_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR3) >> CAN_TXBCR_CR3_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR3; + tmp |= value << CAN_TXBCR_CR3_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR4) >> CAN_TXBCR_CR4_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR4; + tmp |= value << CAN_TXBCR_CR4_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR5) >> CAN_TXBCR_CR5_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR5; + tmp |= value << CAN_TXBCR_CR5_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR6) >> CAN_TXBCR_CR6_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR6; + tmp |= value << CAN_TXBCR_CR6_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR7) >> CAN_TXBCR_CR7_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR7; + tmp |= value << CAN_TXBCR_CR7_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR8) >> CAN_TXBCR_CR8_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR8; + tmp |= value << CAN_TXBCR_CR8_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR9) >> CAN_TXBCR_CR9_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR9; + tmp |= value << CAN_TXBCR_CR9_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR10) >> CAN_TXBCR_CR10_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR10; + tmp |= value << CAN_TXBCR_CR10_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR11) >> CAN_TXBCR_CR11_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR11; + tmp |= value << CAN_TXBCR_CR11_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR12) >> CAN_TXBCR_CR12_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR12; + tmp |= value << CAN_TXBCR_CR12_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR13) >> CAN_TXBCR_CR13_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR13; + tmp |= value << CAN_TXBCR_CR13_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR14) >> CAN_TXBCR_CR14_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR14; + tmp |= value << CAN_TXBCR_CR14_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR15) >> CAN_TXBCR_CR15_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR15; + tmp |= value << CAN_TXBCR_CR15_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR16) >> CAN_TXBCR_CR16_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR16; + tmp |= value << CAN_TXBCR_CR16_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR17) >> CAN_TXBCR_CR17_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR17; + tmp |= value << CAN_TXBCR_CR17_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR18) >> CAN_TXBCR_CR18_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR18; + tmp |= value << CAN_TXBCR_CR18_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR19) >> CAN_TXBCR_CR19_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR19; + tmp |= value << CAN_TXBCR_CR19_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR20) >> CAN_TXBCR_CR20_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR20; + tmp |= value << CAN_TXBCR_CR20_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR21) >> CAN_TXBCR_CR21_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR21; + tmp |= value << CAN_TXBCR_CR21_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR22) >> CAN_TXBCR_CR22_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR22; + tmp |= value << CAN_TXBCR_CR22_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR23) >> CAN_TXBCR_CR23_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR23; + tmp |= value << CAN_TXBCR_CR23_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR24) >> CAN_TXBCR_CR24_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR24; + tmp |= value << CAN_TXBCR_CR24_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR25) >> CAN_TXBCR_CR25_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR25; + tmp |= value << CAN_TXBCR_CR25_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR26) >> CAN_TXBCR_CR26_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR26; + tmp |= value << CAN_TXBCR_CR26_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR27) >> CAN_TXBCR_CR27_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR27; + tmp |= value << CAN_TXBCR_CR27_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR28) >> CAN_TXBCR_CR28_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR28; + tmp |= value << CAN_TXBCR_CR28_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR29) >> CAN_TXBCR_CR29_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR29; + tmp |= value << CAN_TXBCR_CR29_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR30) >> CAN_TXBCR_CR30_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR30; + tmp |= value << CAN_TXBCR_CR30_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_CR31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= CAN_TXBCR_CR31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCR_CR31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp = (tmp & CAN_TXBCR_CR31) >> CAN_TXBCR_CR31_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCR_CR31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= ~CAN_TXBCR_CR31; + tmp |= value << CAN_TXBCR_CR31_Pos; + ((Can *)hw)->TXBCR.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_CR31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~CAN_TXBCR_CR31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_CR31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= CAN_TXBCR_CR31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbcr_reg_t hri_can_get_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCR_reg(const void *const hw, hri_can_txbcr_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCR.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbcr_reg_t hri_can_read_TXBCR_reg(const void *const hw) +{ + return ((Can *)hw)->TXBCR.reg; +} + +static inline void hri_can_set_TXBTIE_TIE0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE0) >> CAN_TXBTIE_TIE0_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE0; + tmp |= value << CAN_TXBTIE_TIE0_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE1) >> CAN_TXBTIE_TIE1_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE1; + tmp |= value << CAN_TXBTIE_TIE1_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE2) >> CAN_TXBTIE_TIE2_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE2; + tmp |= value << CAN_TXBTIE_TIE2_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE3) >> CAN_TXBTIE_TIE3_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE3; + tmp |= value << CAN_TXBTIE_TIE3_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE4) >> CAN_TXBTIE_TIE4_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE4; + tmp |= value << CAN_TXBTIE_TIE4_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE5) >> CAN_TXBTIE_TIE5_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE5; + tmp |= value << CAN_TXBTIE_TIE5_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE6) >> CAN_TXBTIE_TIE6_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE6; + tmp |= value << CAN_TXBTIE_TIE6_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE7) >> CAN_TXBTIE_TIE7_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE7; + tmp |= value << CAN_TXBTIE_TIE7_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE8) >> CAN_TXBTIE_TIE8_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE8; + tmp |= value << CAN_TXBTIE_TIE8_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE9) >> CAN_TXBTIE_TIE9_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE9; + tmp |= value << CAN_TXBTIE_TIE9_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE10) >> CAN_TXBTIE_TIE10_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE10; + tmp |= value << CAN_TXBTIE_TIE10_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE11) >> CAN_TXBTIE_TIE11_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE11; + tmp |= value << CAN_TXBTIE_TIE11_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE12) >> CAN_TXBTIE_TIE12_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE12; + tmp |= value << CAN_TXBTIE_TIE12_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE13) >> CAN_TXBTIE_TIE13_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE13; + tmp |= value << CAN_TXBTIE_TIE13_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE14) >> CAN_TXBTIE_TIE14_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE14; + tmp |= value << CAN_TXBTIE_TIE14_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE15) >> CAN_TXBTIE_TIE15_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE15; + tmp |= value << CAN_TXBTIE_TIE15_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE16) >> CAN_TXBTIE_TIE16_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE16; + tmp |= value << CAN_TXBTIE_TIE16_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE17) >> CAN_TXBTIE_TIE17_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE17; + tmp |= value << CAN_TXBTIE_TIE17_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE18) >> CAN_TXBTIE_TIE18_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE18; + tmp |= value << CAN_TXBTIE_TIE18_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE19) >> CAN_TXBTIE_TIE19_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE19; + tmp |= value << CAN_TXBTIE_TIE19_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE20) >> CAN_TXBTIE_TIE20_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE20; + tmp |= value << CAN_TXBTIE_TIE20_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE21) >> CAN_TXBTIE_TIE21_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE21; + tmp |= value << CAN_TXBTIE_TIE21_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE22) >> CAN_TXBTIE_TIE22_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE22; + tmp |= value << CAN_TXBTIE_TIE22_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE23) >> CAN_TXBTIE_TIE23_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE23; + tmp |= value << CAN_TXBTIE_TIE23_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE24) >> CAN_TXBTIE_TIE24_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE24; + tmp |= value << CAN_TXBTIE_TIE24_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE25) >> CAN_TXBTIE_TIE25_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE25; + tmp |= value << CAN_TXBTIE_TIE25_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE26) >> CAN_TXBTIE_TIE26_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE26; + tmp |= value << CAN_TXBTIE_TIE26_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE27) >> CAN_TXBTIE_TIE27_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE27; + tmp |= value << CAN_TXBTIE_TIE27_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE28) >> CAN_TXBTIE_TIE28_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE28; + tmp |= value << CAN_TXBTIE_TIE28_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE29) >> CAN_TXBTIE_TIE29_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE29; + tmp |= value << CAN_TXBTIE_TIE29_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE30) >> CAN_TXBTIE_TIE30_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE30; + tmp |= value << CAN_TXBTIE_TIE30_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_TIE31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= CAN_TXBTIE_TIE31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBTIE_TIE31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp = (tmp & CAN_TXBTIE_TIE31) >> CAN_TXBTIE_TIE31_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBTIE_TIE31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= ~CAN_TXBTIE_TIE31; + tmp |= value << CAN_TXBTIE_TIE31_Pos; + ((Can *)hw)->TXBTIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_TIE31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~CAN_TXBTIE_TIE31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_TIE31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= CAN_TXBTIE_TIE31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbtie_reg_t hri_can_get_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBTIE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBTIE_reg(const void *const hw, hri_can_txbtie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBTIE.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbtie_reg_t hri_can_read_TXBTIE_reg(const void *const hw) +{ + return ((Can *)hw)->TXBTIE.reg; +} + +static inline void hri_can_set_TXBCIE_CFIE0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE0) >> CAN_TXBCIE_CFIE0_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE0; + tmp |= value << CAN_TXBCIE_CFIE0_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE0_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE0; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE1) >> CAN_TXBCIE_CFIE1_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE1; + tmp |= value << CAN_TXBCIE_CFIE1_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE1_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE1; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE2) >> CAN_TXBCIE_CFIE2_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE2; + tmp |= value << CAN_TXBCIE_CFIE2_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE2_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE2; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE3) >> CAN_TXBCIE_CFIE3_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE3; + tmp |= value << CAN_TXBCIE_CFIE3_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE3_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE3; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE4) >> CAN_TXBCIE_CFIE4_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE4; + tmp |= value << CAN_TXBCIE_CFIE4_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE4_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE4; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE5) >> CAN_TXBCIE_CFIE5_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE5; + tmp |= value << CAN_TXBCIE_CFIE5_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE5_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE5; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE6) >> CAN_TXBCIE_CFIE6_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE6; + tmp |= value << CAN_TXBCIE_CFIE6_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE6_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE6; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE7) >> CAN_TXBCIE_CFIE7_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE7; + tmp |= value << CAN_TXBCIE_CFIE7_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE7_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE7; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE8) >> CAN_TXBCIE_CFIE8_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE8; + tmp |= value << CAN_TXBCIE_CFIE8_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE8_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE8; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE9) >> CAN_TXBCIE_CFIE9_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE9; + tmp |= value << CAN_TXBCIE_CFIE9_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE9_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE9; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE10) >> CAN_TXBCIE_CFIE10_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE10; + tmp |= value << CAN_TXBCIE_CFIE10_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE10_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE10; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE11) >> CAN_TXBCIE_CFIE11_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE11; + tmp |= value << CAN_TXBCIE_CFIE11_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE11_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE11; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE12) >> CAN_TXBCIE_CFIE12_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE12; + tmp |= value << CAN_TXBCIE_CFIE12_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE12_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE12; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE13) >> CAN_TXBCIE_CFIE13_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE13; + tmp |= value << CAN_TXBCIE_CFIE13_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE13_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE13; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE14) >> CAN_TXBCIE_CFIE14_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE14; + tmp |= value << CAN_TXBCIE_CFIE14_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE14_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE14; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE15) >> CAN_TXBCIE_CFIE15_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE15; + tmp |= value << CAN_TXBCIE_CFIE15_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE15_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE15; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE16) >> CAN_TXBCIE_CFIE16_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE16; + tmp |= value << CAN_TXBCIE_CFIE16_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE16_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE16; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE17) >> CAN_TXBCIE_CFIE17_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE17; + tmp |= value << CAN_TXBCIE_CFIE17_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE17_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE17; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE18) >> CAN_TXBCIE_CFIE18_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE18; + tmp |= value << CAN_TXBCIE_CFIE18_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE18_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE18; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE19) >> CAN_TXBCIE_CFIE19_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE19; + tmp |= value << CAN_TXBCIE_CFIE19_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE19_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE19; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE20) >> CAN_TXBCIE_CFIE20_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE20; + tmp |= value << CAN_TXBCIE_CFIE20_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE20_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE20; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE21) >> CAN_TXBCIE_CFIE21_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE21; + tmp |= value << CAN_TXBCIE_CFIE21_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE21_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE21; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE22) >> CAN_TXBCIE_CFIE22_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE22; + tmp |= value << CAN_TXBCIE_CFIE22_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE22_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE22; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE23) >> CAN_TXBCIE_CFIE23_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE23; + tmp |= value << CAN_TXBCIE_CFIE23_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE23_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE23; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE24) >> CAN_TXBCIE_CFIE24_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE24; + tmp |= value << CAN_TXBCIE_CFIE24_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE24_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE24; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE25) >> CAN_TXBCIE_CFIE25_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE25; + tmp |= value << CAN_TXBCIE_CFIE25_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE25_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE25; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE26) >> CAN_TXBCIE_CFIE26_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE26; + tmp |= value << CAN_TXBCIE_CFIE26_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE26_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE26; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE27) >> CAN_TXBCIE_CFIE27_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE27; + tmp |= value << CAN_TXBCIE_CFIE27_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE27_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE27; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE28) >> CAN_TXBCIE_CFIE28_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE28; + tmp |= value << CAN_TXBCIE_CFIE28_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE28_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE28; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE29) >> CAN_TXBCIE_CFIE29_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE29; + tmp |= value << CAN_TXBCIE_CFIE29_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE29_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE29; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE30) >> CAN_TXBCIE_CFIE30_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE30; + tmp |= value << CAN_TXBCIE_CFIE30_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE30_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE30; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_CFIE31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= CAN_TXBCIE_CFIE31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_can_get_TXBCIE_CFIE31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp = (tmp & CAN_TXBCIE_CFIE31) >> CAN_TXBCIE_CFIE31_Pos; + return (bool)tmp; +} + +static inline void hri_can_write_TXBCIE_CFIE31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= ~CAN_TXBCIE_CFIE31; + tmp |= value << CAN_TXBCIE_CFIE31_Pos; + ((Can *)hw)->TXBCIE.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_CFIE31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~CAN_TXBCIE_CFIE31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_CFIE31_bit(const void *const hw) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= CAN_TXBCIE_CFIE31; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_set_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbcie_reg_t hri_can_get_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXBCIE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXBCIE_reg(const void *const hw, hri_can_txbcie_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXBCIE.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txbcie_reg_t hri_can_read_TXBCIE_reg(const void *const hw) +{ + return ((Can *)hw)->TXBCIE.reg; +} + +static inline void hri_can_set_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg |= CAN_TXEFC_EFSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_get_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp = (tmp & CAN_TXEFC_EFSA(mask)) >> CAN_TXEFC_EFSA_Pos; + return tmp; +} + +static inline void hri_can_write_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXEFC.reg; + tmp &= ~CAN_TXEFC_EFSA_Msk; + tmp |= CAN_TXEFC_EFSA(data); + ((Can *)hw)->TXEFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg &= ~CAN_TXEFC_EFSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXEFC_EFSA_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg ^= CAN_TXEFC_EFSA(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_read_TXEFC_EFSA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp = (tmp & CAN_TXEFC_EFSA_Msk) >> CAN_TXEFC_EFSA_Pos; + return tmp; +} + +static inline void hri_can_set_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg |= CAN_TXEFC_EFS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_get_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp = (tmp & CAN_TXEFC_EFS(mask)) >> CAN_TXEFC_EFS_Pos; + return tmp; +} + +static inline void hri_can_write_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXEFC.reg; + tmp &= ~CAN_TXEFC_EFS_Msk; + tmp |= CAN_TXEFC_EFS(data); + ((Can *)hw)->TXEFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg &= ~CAN_TXEFC_EFS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXEFC_EFS_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg ^= CAN_TXEFC_EFS(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_read_TXEFC_EFS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp = (tmp & CAN_TXEFC_EFS_Msk) >> CAN_TXEFC_EFS_Pos; + return tmp; +} + +static inline void hri_can_set_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg |= CAN_TXEFC_EFWM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_get_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp = (tmp & CAN_TXEFC_EFWM(mask)) >> CAN_TXEFC_EFWM_Pos; + return tmp; +} + +static inline void hri_can_write_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXEFC.reg; + tmp &= ~CAN_TXEFC_EFWM_Msk; + tmp |= CAN_TXEFC_EFWM(data); + ((Can *)hw)->TXEFC.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg &= ~CAN_TXEFC_EFWM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXEFC_EFWM_bf(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg ^= CAN_TXEFC_EFWM(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_read_TXEFC_EFWM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp = (tmp & CAN_TXEFC_EFWM_Msk) >> CAN_TXEFC_EFWM_Pos; + return tmp; +} + +static inline void hri_can_set_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_get_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXEFC_reg(const void *const hw, hri_can_txefc_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFC.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefc_reg_t hri_can_read_TXEFC_reg(const void *const hw) +{ + return ((Can *)hw)->TXEFC.reg; +} + +static inline void hri_can_set_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg |= CAN_TXEFA_EFAI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefa_reg_t hri_can_get_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFA.reg; + tmp = (tmp & CAN_TXEFA_EFAI(mask)) >> CAN_TXEFA_EFAI_Pos; + return tmp; +} + +static inline void hri_can_write_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t data) +{ + uint32_t tmp; + CAN_CRITICAL_SECTION_ENTER(); + tmp = ((Can *)hw)->TXEFA.reg; + tmp &= ~CAN_TXEFA_EFAI_Msk; + tmp |= CAN_TXEFA_EFAI(data); + ((Can *)hw)->TXEFA.reg = tmp; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg &= ~CAN_TXEFA_EFAI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXEFA_EFAI_bf(const void *const hw, hri_can_txefa_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg ^= CAN_TXEFA_EFAI(mask); + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefa_reg_t hri_can_read_TXEFA_EFAI_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFA.reg; + tmp = (tmp & CAN_TXEFA_EFAI_Msk) >> CAN_TXEFA_EFAI_Pos; + return tmp; +} + +static inline void hri_can_set_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg |= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefa_reg_t hri_can_get_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask) +{ + uint32_t tmp; + tmp = ((Can *)hw)->TXEFA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_can_write_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t data) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg = data; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_clear_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg &= ~mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_can_toggle_TXEFA_reg(const void *const hw, hri_can_txefa_reg_t mask) +{ + CAN_CRITICAL_SECTION_ENTER(); + ((Can *)hw)->TXEFA.reg ^= mask; + CAN_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_can_txefa_reg_t hri_can_read_TXEFA_reg(const void *const hw) +{ + return ((Can *)hw)->TXEFA.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_CAN_E54_H_INCLUDED */ +#endif /* _SAME54_CAN_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_ccl_e54.h b/software/firmware/oracle_same54n19a/hri/hri_ccl_e54.h new file mode 100644 index 00000000..c5c48675 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_ccl_e54.h @@ -0,0 +1,776 @@ +/** + * \file + * + * \brief SAM CCL + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_CCL_COMPONENT_ +#ifndef _HRI_CCL_E54_H_INCLUDED_ +#define _HRI_CCL_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_CCL_CRITICAL_SECTIONS) +#define CCL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define CCL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define CCL_CRITICAL_SECTION_ENTER() +#define CCL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_ccl_lutctrl_reg_t; +typedef uint8_t hri_ccl_ctrl_reg_t; +typedef uint8_t hri_ccl_seqctrl_reg_t; + +static inline void hri_ccl_set_CTRL_SWRST_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_SWRST; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_CTRL_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp = (tmp & CCL_CTRL_SWRST) >> CCL_CTRL_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_set_CTRL_ENABLE_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_CTRL_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp = (tmp & CCL_CTRL_ENABLE) >> CCL_CTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_CTRL_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->CTRL.reg; + tmp &= ~CCL_CTRL_ENABLE; + tmp |= value << CCL_CTRL_ENABLE_Pos; + ((Ccl *)hw)->CTRL.reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_CTRL_ENABLE_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_CTRL_ENABLE_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_CTRL_RUNSTDBY_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= CCL_CTRL_RUNSTDBY; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_CTRL_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp = (tmp & CCL_CTRL_RUNSTDBY) >> CCL_CTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_CTRL_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->CTRL.reg; + tmp &= ~CCL_CTRL_RUNSTDBY; + tmp |= value << CCL_CTRL_RUNSTDBY_Pos; + ((Ccl *)hw)->CTRL.reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_CTRL_RUNSTDBY_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg &= ~CCL_CTRL_RUNSTDBY; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_CTRL_RUNSTDBY_bit(const void *const hw) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg ^= CCL_CTRL_RUNSTDBY; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg |= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_ctrl_reg_t hri_ccl_get_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ccl_write_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t data) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg = data; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg &= ~mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_CTRL_reg(const void *const hw, hri_ccl_ctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->CTRL.reg ^= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_ctrl_reg_t hri_ccl_read_CTRL_reg(const void *const hw) +{ + return ((Ccl *)hw)->CTRL.reg; +} + +static inline void hri_ccl_set_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg |= CCL_SEQCTRL_SEQSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, + hri_ccl_seqctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp = (tmp & CCL_SEQCTRL_SEQSEL(mask)) >> CCL_SEQCTRL_SEQSEL_Pos; + return tmp; +} + +static inline void hri_ccl_write_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data) +{ + uint8_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp &= ~CCL_SEQCTRL_SEQSEL_Msk; + tmp |= CCL_SEQCTRL_SEQSEL(data); + ((Ccl *)hw)->SEQCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg &= ~CCL_SEQCTRL_SEQSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg ^= CCL_SEQCTRL_SEQSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_SEQSEL_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp = (tmp & CCL_SEQCTRL_SEQSEL_Msk) >> CCL_SEQCTRL_SEQSEL_Pos; + return tmp; +} + +static inline void hri_ccl_set_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg |= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_get_SEQCTRL_reg(const void *const hw, uint8_t index, + hri_ccl_seqctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ccl *)hw)->SEQCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ccl_write_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t data) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg = data; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg &= ~mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_SEQCTRL_reg(const void *const hw, uint8_t index, hri_ccl_seqctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->SEQCTRL[index].reg ^= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_seqctrl_reg_t hri_ccl_read_SEQCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Ccl *)hw)->SEQCTRL[index].reg; +} + +static inline void hri_ccl_set_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_ENABLE) >> CCL_LUTCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_ENABLE; + tmp |= value << CCL_LUTCTRL_ENABLE_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_ENABLE; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_EDGESEL; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_EDGESEL) >> CCL_LUTCTRL_EDGESEL_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_EDGESEL; + tmp |= value << CCL_LUTCTRL_EDGESEL_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_EDGESEL; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_EDGESEL_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_EDGESEL; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INVEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INVEI) >> CCL_LUTCTRL_INVEI_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INVEI; + tmp |= value << CCL_LUTCTRL_INVEI_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INVEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INVEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INVEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_LUTEI) >> CCL_LUTCTRL_LUTEI_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_LUTEI; + tmp |= value << CCL_LUTCTRL_LUTEI_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_LUTEI_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEI; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_LUTEO; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ccl_get_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_LUTEO) >> CCL_LUTCTRL_LUTEO_Pos; + return (bool)tmp; +} + +static inline void hri_ccl_write_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_LUTEO; + tmp |= value << CCL_LUTCTRL_LUTEO_Pos; + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_LUTEO; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_LUTEO_bit(const void *const hw, uint8_t index) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_LUTEO; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_set_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_FILTSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_FILTSEL(mask)) >> CCL_LUTCTRL_FILTSEL_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_FILTSEL_Msk; + tmp |= CCL_LUTCTRL_FILTSEL(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_FILTSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_FILTSEL(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_FILTSEL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_FILTSEL_Msk) >> CCL_LUTCTRL_FILTSEL_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL0(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL0(mask)) >> CCL_LUTCTRL_INSEL0_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INSEL0_Msk; + tmp |= CCL_LUTCTRL_INSEL0(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL0(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL0(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL0_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL0_Msk) >> CCL_LUTCTRL_INSEL0_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL1(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL1(mask)) >> CCL_LUTCTRL_INSEL1_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INSEL1_Msk; + tmp |= CCL_LUTCTRL_INSEL1(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL1(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL1(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL1_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL1_Msk) >> CCL_LUTCTRL_INSEL1_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_INSEL2(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL2(mask)) >> CCL_LUTCTRL_INSEL2_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_INSEL2_Msk; + tmp |= CCL_LUTCTRL_INSEL2(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_INSEL2(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_INSEL2(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_INSEL2_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_INSEL2_Msk) >> CCL_LUTCTRL_INSEL2_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= CCL_LUTCTRL_TRUTH(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_TRUTH(mask)) >> CCL_LUTCTRL_TRUTH_Pos; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + uint32_t tmp; + CCL_CRITICAL_SECTION_ENTER(); + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= ~CCL_LUTCTRL_TRUTH_Msk; + tmp |= CCL_LUTCTRL_TRUTH(data); + ((Ccl *)hw)->LUTCTRL[index].reg = tmp; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~CCL_LUTCTRL_TRUTH(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= CCL_LUTCTRL_TRUTH(mask); + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_TRUTH_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp = (tmp & CCL_LUTCTRL_TRUTH_Msk) >> CCL_LUTCTRL_TRUTH_Pos; + return tmp; +} + +static inline void hri_ccl_set_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg |= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_get_LUTCTRL_reg(const void *const hw, uint8_t index, + hri_ccl_lutctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ccl *)hw)->LUTCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ccl_write_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t data) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg = data; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_clear_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg &= ~mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ccl_toggle_LUTCTRL_reg(const void *const hw, uint8_t index, hri_ccl_lutctrl_reg_t mask) +{ + CCL_CRITICAL_SECTION_ENTER(); + ((Ccl *)hw)->LUTCTRL[index].reg ^= mask; + CCL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ccl_lutctrl_reg_t hri_ccl_read_LUTCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Ccl *)hw)->LUTCTRL[index].reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_CCL_E54_H_INCLUDED */ +#endif /* _SAME54_CCL_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_cmcc_e54.h b/software/firmware/oracle_same54n19a/hri/hri_cmcc_e54.h new file mode 100644 index 00000000..c973d357 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_cmcc_e54.h @@ -0,0 +1,361 @@ +/** + * \file + * + * \brief SAM CMCC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_CMCC_COMPONENT_ +#ifndef _HRI_CMCC_E54_H_INCLUDED_ +#define _HRI_CMCC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_CMCC_CRITICAL_SECTIONS) +#define CMCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define CMCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define CMCC_CRITICAL_SECTION_ENTER() +#define CMCC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_cmcc_cfg_reg_t; +typedef uint32_t hri_cmcc_ctrl_reg_t; +typedef uint32_t hri_cmcc_lckway_reg_t; +typedef uint32_t hri_cmcc_maint0_reg_t; +typedef uint32_t hri_cmcc_maint1_reg_t; +typedef uint32_t hri_cmcc_mcfg_reg_t; +typedef uint32_t hri_cmcc_mctrl_reg_t; +typedef uint32_t hri_cmcc_men_reg_t; +typedef uint32_t hri_cmcc_msr_reg_t; +typedef uint32_t hri_cmcc_sr_reg_t; +typedef uint32_t hri_cmcc_type_reg_t; + +static inline bool hri_cmcc_get_TYPE_GCLK_bit(const void *const hw) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_GCLK) >> CMCC_TYPE_GCLK_Pos; +} + +static inline bool hri_cmcc_get_TYPE_RRP_bit(const void *const hw) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_RRP) >> CMCC_TYPE_RRP_Pos; +} + +static inline bool hri_cmcc_get_TYPE_LCKDOWN_bit(const void *const hw) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_LCKDOWN) >> CMCC_TYPE_LCKDOWN_Pos; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_WAYNUM_bf(const void *const hw, hri_cmcc_type_reg_t mask) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_WAYNUM(mask)) >> CMCC_TYPE_WAYNUM_Pos; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_WAYNUM_bf(const void *const hw) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_WAYNUM_Msk) >> CMCC_TYPE_WAYNUM_Pos; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_CSIZE_bf(const void *const hw, hri_cmcc_type_reg_t mask) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CSIZE(mask)) >> CMCC_TYPE_CSIZE_Pos; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_CSIZE_bf(const void *const hw) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CSIZE_Msk) >> CMCC_TYPE_CSIZE_Pos; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_CLSIZE_bf(const void *const hw, hri_cmcc_type_reg_t mask) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CLSIZE(mask)) >> CMCC_TYPE_CLSIZE_Pos; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_CLSIZE_bf(const void *const hw) +{ + return (((Cmcc *)hw)->TYPE.reg & CMCC_TYPE_CLSIZE_Msk) >> CMCC_TYPE_CLSIZE_Pos; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_get_TYPE_reg(const void *const hw, hri_cmcc_type_reg_t mask) +{ + uint32_t tmp; + tmp = ((Cmcc *)hw)->TYPE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_cmcc_type_reg_t hri_cmcc_read_TYPE_reg(const void *const hw) +{ + return ((Cmcc *)hw)->TYPE.reg; +} + +static inline bool hri_cmcc_get_SR_CSTS_bit(const void *const hw) +{ + return (((Cmcc *)hw)->SR.reg & CMCC_SR_CSTS) >> CMCC_SR_CSTS_Pos; +} + +static inline hri_cmcc_sr_reg_t hri_cmcc_get_SR_reg(const void *const hw, hri_cmcc_sr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Cmcc *)hw)->SR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_cmcc_sr_reg_t hri_cmcc_read_SR_reg(const void *const hw) +{ + return ((Cmcc *)hw)->SR.reg; +} + +static inline hri_cmcc_msr_reg_t hri_cmcc_get_MSR_EVENT_CNT_bf(const void *const hw, hri_cmcc_msr_reg_t mask) +{ + return (((Cmcc *)hw)->MSR.reg & CMCC_MSR_EVENT_CNT(mask)) >> CMCC_MSR_EVENT_CNT_Pos; +} + +static inline hri_cmcc_msr_reg_t hri_cmcc_read_MSR_EVENT_CNT_bf(const void *const hw) +{ + return (((Cmcc *)hw)->MSR.reg & CMCC_MSR_EVENT_CNT_Msk) >> CMCC_MSR_EVENT_CNT_Pos; +} + +static inline hri_cmcc_msr_reg_t hri_cmcc_get_MSR_reg(const void *const hw, hri_cmcc_msr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Cmcc *)hw)->MSR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_cmcc_msr_reg_t hri_cmcc_read_MSR_reg(const void *const hw) +{ + return ((Cmcc *)hw)->MSR.reg; +} + +static inline void hri_cmcc_set_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->CFG.reg |= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_cfg_reg_t hri_cmcc_get_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Cmcc *)hw)->CFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_cmcc_write_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->CFG.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_clear_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->CFG.reg &= ~mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_toggle_CFG_reg(const void *const hw, hri_cmcc_cfg_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->CFG.reg ^= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_cfg_reg_t hri_cmcc_read_CFG_reg(const void *const hw) +{ + return ((Cmcc *)hw)->CFG.reg; +} + +static inline void hri_cmcc_set_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->LCKWAY.reg |= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_lckway_reg_t hri_cmcc_get_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask) +{ + uint32_t tmp; + tmp = ((Cmcc *)hw)->LCKWAY.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_cmcc_write_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->LCKWAY.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_clear_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->LCKWAY.reg &= ~mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_toggle_LCKWAY_reg(const void *const hw, hri_cmcc_lckway_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->LCKWAY.reg ^= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_lckway_reg_t hri_cmcc_read_LCKWAY_reg(const void *const hw) +{ + return ((Cmcc *)hw)->LCKWAY.reg; +} + +static inline void hri_cmcc_set_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MCFG.reg |= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_mcfg_reg_t hri_cmcc_get_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Cmcc *)hw)->MCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_cmcc_write_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MCFG.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_clear_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MCFG.reg &= ~mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_toggle_MCFG_reg(const void *const hw, hri_cmcc_mcfg_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MCFG.reg ^= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_mcfg_reg_t hri_cmcc_read_MCFG_reg(const void *const hw) +{ + return ((Cmcc *)hw)->MCFG.reg; +} + +static inline void hri_cmcc_set_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MEN.reg |= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_men_reg_t hri_cmcc_get_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask) +{ + uint32_t tmp; + tmp = ((Cmcc *)hw)->MEN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_cmcc_write_MEN_reg(const void *const hw, hri_cmcc_men_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MEN.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_clear_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MEN.reg &= ~mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_toggle_MEN_reg(const void *const hw, hri_cmcc_men_reg_t mask) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MEN.reg ^= mask; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_cmcc_men_reg_t hri_cmcc_read_MEN_reg(const void *const hw) +{ + return ((Cmcc *)hw)->MEN.reg; +} + +static inline void hri_cmcc_write_CTRL_reg(const void *const hw, hri_cmcc_ctrl_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->CTRL.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_write_MAINT0_reg(const void *const hw, hri_cmcc_maint0_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MAINT0.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_write_MAINT1_reg(const void *const hw, hri_cmcc_maint1_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MAINT1.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_cmcc_write_MCTRL_reg(const void *const hw, hri_cmcc_mctrl_reg_t data) +{ + CMCC_CRITICAL_SECTION_ENTER(); + ((Cmcc *)hw)->MCTRL.reg = data; + CMCC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_CMCC_E54_H_INCLUDED */ +#endif /* _SAME54_CMCC_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_dac_e54.h b/software/firmware/oracle_same54n19a/hri/hri_dac_e54.h new file mode 100644 index 00000000..911dd529 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_dac_e54.h @@ -0,0 +1,1706 @@ +/** + * \file + * + * \brief SAM DAC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_DAC_COMPONENT_ +#ifndef _HRI_DAC_E54_H_INCLUDED_ +#define _HRI_DAC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_DAC_CRITICAL_SECTIONS) +#define DAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define DAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define DAC_CRITICAL_SECTION_ENTER() +#define DAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_dac_dacctrl_reg_t; +typedef uint16_t hri_dac_data_reg_t; +typedef uint16_t hri_dac_databuf_reg_t; +typedef uint16_t hri_dac_result_reg_t; +typedef uint32_t hri_dac_syncbusy_reg_t; +typedef uint8_t hri_dac_ctrla_reg_t; +typedef uint8_t hri_dac_ctrlb_reg_t; +typedef uint8_t hri_dac_dbgctrl_reg_t; +typedef uint8_t hri_dac_evctrl_reg_t; +typedef uint8_t hri_dac_intenset_reg_t; +typedef uint8_t hri_dac_intflag_reg_t; +typedef uint8_t hri_dac_status_reg_t; + +static inline void hri_dac_wait_for_sync(const void *const hw, hri_dac_syncbusy_reg_t reg) +{ + while (((Dac *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_dac_is_syncing(const void *const hw, hri_dac_syncbusy_reg_t reg) +{ + return ((Dac *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_dac_get_INTFLAG_UNDERRUN0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN0) >> DAC_INTFLAG_UNDERRUN0_Pos; +} + +static inline void hri_dac_clear_INTFLAG_UNDERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0; +} + +static inline bool hri_dac_get_INTFLAG_UNDERRUN1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN1) >> DAC_INTFLAG_UNDERRUN1_Pos; +} + +static inline void hri_dac_clear_INTFLAG_UNDERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1; +} + +static inline bool hri_dac_get_INTFLAG_EMPTY0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY0) >> DAC_INTFLAG_EMPTY0_Pos; +} + +static inline void hri_dac_clear_INTFLAG_EMPTY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY0; +} + +static inline bool hri_dac_get_INTFLAG_EMPTY1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY1) >> DAC_INTFLAG_EMPTY1_Pos; +} + +static inline void hri_dac_clear_INTFLAG_EMPTY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY1; +} + +static inline bool hri_dac_get_INTFLAG_RESRDY0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY0) >> DAC_INTFLAG_RESRDY0_Pos; +} + +static inline void hri_dac_clear_INTFLAG_RESRDY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY0; +} + +static inline bool hri_dac_get_INTFLAG_RESRDY1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY1) >> DAC_INTFLAG_RESRDY1_Pos; +} + +static inline void hri_dac_clear_INTFLAG_RESRDY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY1; +} + +static inline bool hri_dac_get_INTFLAG_OVERRUN0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN0) >> DAC_INTFLAG_OVERRUN0_Pos; +} + +static inline void hri_dac_clear_INTFLAG_OVERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN0; +} + +static inline bool hri_dac_get_INTFLAG_OVERRUN1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN1) >> DAC_INTFLAG_OVERRUN1_Pos; +} + +static inline void hri_dac_clear_INTFLAG_OVERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN1; +} + +static inline bool hri_dac_get_interrupt_UNDERRUN0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN0) >> DAC_INTFLAG_UNDERRUN0_Pos; +} + +static inline void hri_dac_clear_interrupt_UNDERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN0; +} + +static inline bool hri_dac_get_interrupt_UNDERRUN1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_UNDERRUN1) >> DAC_INTFLAG_UNDERRUN1_Pos; +} + +static inline void hri_dac_clear_interrupt_UNDERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_UNDERRUN1; +} + +static inline bool hri_dac_get_interrupt_EMPTY0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY0) >> DAC_INTFLAG_EMPTY0_Pos; +} + +static inline void hri_dac_clear_interrupt_EMPTY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY0; +} + +static inline bool hri_dac_get_interrupt_EMPTY1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_EMPTY1) >> DAC_INTFLAG_EMPTY1_Pos; +} + +static inline void hri_dac_clear_interrupt_EMPTY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_EMPTY1; +} + +static inline bool hri_dac_get_interrupt_RESRDY0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY0) >> DAC_INTFLAG_RESRDY0_Pos; +} + +static inline void hri_dac_clear_interrupt_RESRDY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY0; +} + +static inline bool hri_dac_get_interrupt_RESRDY1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_RESRDY1) >> DAC_INTFLAG_RESRDY1_Pos; +} + +static inline void hri_dac_clear_interrupt_RESRDY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_RESRDY1; +} + +static inline bool hri_dac_get_interrupt_OVERRUN0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN0) >> DAC_INTFLAG_OVERRUN0_Pos; +} + +static inline void hri_dac_clear_interrupt_OVERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN0; +} + +static inline bool hri_dac_get_interrupt_OVERRUN1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTFLAG.reg & DAC_INTFLAG_OVERRUN1) >> DAC_INTFLAG_OVERRUN1_Pos; +} + +static inline void hri_dac_clear_interrupt_OVERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTFLAG.reg = DAC_INTFLAG_OVERRUN1; +} + +static inline hri_dac_intflag_reg_t hri_dac_get_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_intflag_reg_t hri_dac_read_INTFLAG_reg(const void *const hw) +{ + return ((Dac *)hw)->INTFLAG.reg; +} + +static inline void hri_dac_clear_INTFLAG_reg(const void *const hw, hri_dac_intflag_reg_t mask) +{ + ((Dac *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_dac_set_INTEN_UNDERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN0; +} + +static inline bool hri_dac_get_INTEN_UNDERRUN0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN0) >> DAC_INTENSET_UNDERRUN0_Pos; +} + +static inline void hri_dac_write_INTEN_UNDERRUN0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN0; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN0; + } +} + +static inline void hri_dac_clear_INTEN_UNDERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN0; +} + +static inline void hri_dac_set_INTEN_UNDERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN1; +} + +static inline bool hri_dac_get_INTEN_UNDERRUN1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_UNDERRUN1) >> DAC_INTENSET_UNDERRUN1_Pos; +} + +static inline void hri_dac_write_INTEN_UNDERRUN1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN1; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_UNDERRUN1; + } +} + +static inline void hri_dac_clear_INTEN_UNDERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_UNDERRUN1; +} + +static inline void hri_dac_set_INTEN_EMPTY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY0; +} + +static inline bool hri_dac_get_INTEN_EMPTY0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_EMPTY0) >> DAC_INTENSET_EMPTY0_Pos; +} + +static inline void hri_dac_write_INTEN_EMPTY0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY0; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY0; + } +} + +static inline void hri_dac_clear_INTEN_EMPTY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY0; +} + +static inline void hri_dac_set_INTEN_EMPTY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY1; +} + +static inline bool hri_dac_get_INTEN_EMPTY1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_EMPTY1) >> DAC_INTENSET_EMPTY1_Pos; +} + +static inline void hri_dac_write_INTEN_EMPTY1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY1; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_EMPTY1; + } +} + +static inline void hri_dac_clear_INTEN_EMPTY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_EMPTY1; +} + +static inline void hri_dac_set_INTEN_RESRDY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY0; +} + +static inline bool hri_dac_get_INTEN_RESRDY0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_RESRDY0) >> DAC_INTENSET_RESRDY0_Pos; +} + +static inline void hri_dac_write_INTEN_RESRDY0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY0; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY0; + } +} + +static inline void hri_dac_clear_INTEN_RESRDY0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY0; +} + +static inline void hri_dac_set_INTEN_RESRDY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY1; +} + +static inline bool hri_dac_get_INTEN_RESRDY1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_RESRDY1) >> DAC_INTENSET_RESRDY1_Pos; +} + +static inline void hri_dac_write_INTEN_RESRDY1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY1; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_RESRDY1; + } +} + +static inline void hri_dac_clear_INTEN_RESRDY1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_RESRDY1; +} + +static inline void hri_dac_set_INTEN_OVERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN0; +} + +static inline bool hri_dac_get_INTEN_OVERRUN0_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_OVERRUN0) >> DAC_INTENSET_OVERRUN0_Pos; +} + +static inline void hri_dac_write_INTEN_OVERRUN0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN0; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN0; + } +} + +static inline void hri_dac_clear_INTEN_OVERRUN0_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN0; +} + +static inline void hri_dac_set_INTEN_OVERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN1; +} + +static inline bool hri_dac_get_INTEN_OVERRUN1_bit(const void *const hw) +{ + return (((Dac *)hw)->INTENSET.reg & DAC_INTENSET_OVERRUN1) >> DAC_INTENSET_OVERRUN1_Pos; +} + +static inline void hri_dac_write_INTEN_OVERRUN1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN1; + } else { + ((Dac *)hw)->INTENSET.reg = DAC_INTENSET_OVERRUN1; + } +} + +static inline void hri_dac_clear_INTEN_OVERRUN1_bit(const void *const hw) +{ + ((Dac *)hw)->INTENCLR.reg = DAC_INTENSET_OVERRUN1; +} + +static inline void hri_dac_set_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) +{ + ((Dac *)hw)->INTENSET.reg = mask; +} + +static inline hri_dac_intenset_reg_t hri_dac_get_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_intenset_reg_t hri_dac_read_INTEN_reg(const void *const hw) +{ + return ((Dac *)hw)->INTENSET.reg; +} + +static inline void hri_dac_write_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t data) +{ + ((Dac *)hw)->INTENSET.reg = data; + ((Dac *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_dac_clear_INTEN_reg(const void *const hw, hri_dac_intenset_reg_t mask) +{ + ((Dac *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_dac_get_STATUS_READY0_bit(const void *const hw) +{ + return (((Dac *)hw)->STATUS.reg & DAC_STATUS_READY0) >> DAC_STATUS_READY0_Pos; +} + +static inline bool hri_dac_get_STATUS_READY1_bit(const void *const hw) +{ + return (((Dac *)hw)->STATUS.reg & DAC_STATUS_READY1) >> DAC_STATUS_READY1_Pos; +} + +static inline bool hri_dac_get_STATUS_EOC0_bit(const void *const hw) +{ + return (((Dac *)hw)->STATUS.reg & DAC_STATUS_EOC0) >> DAC_STATUS_EOC0_Pos; +} + +static inline bool hri_dac_get_STATUS_EOC1_bit(const void *const hw) +{ + return (((Dac *)hw)->STATUS.reg & DAC_STATUS_EOC1) >> DAC_STATUS_EOC1_Pos; +} + +static inline hri_dac_status_reg_t hri_dac_get_STATUS_reg(const void *const hw, hri_dac_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_status_reg_t hri_dac_read_STATUS_reg(const void *const hw) +{ + return ((Dac *)hw)->STATUS.reg; +} + +static inline bool hri_dac_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_SWRST) >> DAC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_ENABLE) >> DAC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_DATA0_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATA0) >> DAC_SYNCBUSY_DATA0_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_DATA1_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATA1) >> DAC_SYNCBUSY_DATA1_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_DATABUF0_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATABUF0) >> DAC_SYNCBUSY_DATABUF0_Pos; +} + +static inline bool hri_dac_get_SYNCBUSY_DATABUF1_bit(const void *const hw) +{ + return (((Dac *)hw)->SYNCBUSY.reg & DAC_SYNCBUSY_DATABUF1) >> DAC_SYNCBUSY_DATABUF1_Pos; +} + +static inline hri_dac_syncbusy_reg_t hri_dac_get_SYNCBUSY_reg(const void *const hw, hri_dac_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dac *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_syncbusy_reg_t hri_dac_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Dac *)hw)->SYNCBUSY.reg; +} + +static inline hri_dac_result_reg_t hri_dac_get_RESULT_RESULT_bf(const void *const hw, uint8_t index, + hri_dac_result_reg_t mask) +{ + return (((Dac *)hw)->RESULT[index].reg & DAC_RESULT_RESULT(mask)) >> DAC_RESULT_RESULT_Pos; +} + +static inline hri_dac_result_reg_t hri_dac_read_RESULT_RESULT_bf(const void *const hw, uint8_t index) +{ + return (((Dac *)hw)->RESULT[index].reg & DAC_RESULT_RESULT_Msk) >> DAC_RESULT_RESULT_Pos; +} + +static inline hri_dac_result_reg_t hri_dac_get_RESULT_reg(const void *const hw, uint8_t index, + hri_dac_result_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->RESULT[index].reg; + tmp &= mask; + return tmp; +} + +static inline hri_dac_result_reg_t hri_dac_read_RESULT_reg(const void *const hw, uint8_t index) +{ + return ((Dac *)hw)->RESULT[index].reg; +} + +static inline void hri_dac_set_CTRLA_SWRST_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_SWRST; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp = (tmp & DAC_CTRLA_SWRST) >> DAC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dac_set_CTRLA_ENABLE_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg |= DAC_CTRLA_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp = (tmp & DAC_CTRLA_ENABLE) >> DAC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp &= ~DAC_CTRLA_ENABLE; + tmp |= value << DAC_CTRLA_ENABLE_Pos; + ((Dac *)hw)->CTRLA.reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg &= ~DAC_CTRLA_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg ^= DAC_CTRLA_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg |= mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrla_reg_t hri_dac_get_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + tmp = ((Dac *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg = data; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg &= ~mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLA_reg(const void *const hw, hri_dac_ctrla_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLA.reg ^= mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrla_reg_t hri_dac_read_CTRLA_reg(const void *const hw) +{ + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_SWRST | DAC_SYNCBUSY_ENABLE); + return ((Dac *)hw)->CTRLA.reg; +} + +static inline void hri_dac_set_CTRLB_DIFF_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_DIFF; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_CTRLB_DIFF_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_DIFF) >> DAC_CTRLB_DIFF_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_CTRLB_DIFF_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= ~DAC_CTRLB_DIFF; + tmp |= value << DAC_CTRLB_DIFF_Pos; + ((Dac *)hw)->CTRLB.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_DIFF_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_DIFF; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_DIFF_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_DIFF; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= DAC_CTRLB_REFSEL(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_REFSEL(mask)) >> DAC_CTRLB_REFSEL_Pos; + return tmp; +} + +static inline void hri_dac_write_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t data) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= ~DAC_CTRLB_REFSEL_Msk; + tmp |= DAC_CTRLB_REFSEL(data); + ((Dac *)hw)->CTRLB.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~DAC_CTRLB_REFSEL(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_REFSEL_bf(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= DAC_CTRLB_REFSEL(mask); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_REFSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp = (tmp & DAC_CTRLB_REFSEL_Msk) >> DAC_CTRLB_REFSEL_Pos; + return tmp; +} + +static inline void hri_dac_set_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg |= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_get_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg = data; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg &= ~mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_CTRLB_reg(const void *const hw, hri_dac_ctrlb_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->CTRLB.reg ^= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_ctrlb_reg_t hri_dac_read_CTRLB_reg(const void *const hw) +{ + return ((Dac *)hw)->CTRLB.reg; +} + +static inline void hri_dac_set_EVCTRL_STARTEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_STARTEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_STARTEI0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_STARTEI0) >> DAC_EVCTRL_STARTEI0_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_STARTEI0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_STARTEI0; + tmp |= value << DAC_EVCTRL_STARTEI0_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_STARTEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_STARTEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_STARTEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_STARTEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_STARTEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_STARTEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_STARTEI1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_STARTEI1) >> DAC_EVCTRL_STARTEI1_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_STARTEI1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_STARTEI1; + tmp |= value << DAC_EVCTRL_STARTEI1_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_STARTEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_STARTEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_STARTEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_STARTEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_EMPTYEO0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_EMPTYEO0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_EMPTYEO0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_EMPTYEO0) >> DAC_EVCTRL_EMPTYEO0_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_EMPTYEO0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_EMPTYEO0; + tmp |= value << DAC_EVCTRL_EMPTYEO0_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_EMPTYEO0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_EMPTYEO0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_EMPTYEO0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_EMPTYEO0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_EMPTYEO1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_EMPTYEO1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_EMPTYEO1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_EMPTYEO1) >> DAC_EVCTRL_EMPTYEO1_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_EMPTYEO1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_EMPTYEO1; + tmp |= value << DAC_EVCTRL_EMPTYEO1_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_EMPTYEO1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_EMPTYEO1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_EMPTYEO1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_EMPTYEO1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_INVEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_INVEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_INVEI0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_INVEI0) >> DAC_EVCTRL_INVEI0_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_INVEI0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_INVEI0; + tmp |= value << DAC_EVCTRL_INVEI0_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_INVEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_INVEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_INVEI0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_INVEI0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_INVEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_INVEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_INVEI1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_INVEI1) >> DAC_EVCTRL_INVEI1_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_INVEI1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_INVEI1; + tmp |= value << DAC_EVCTRL_INVEI1_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_INVEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_INVEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_INVEI1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_INVEI1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_RESRDYEO0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_RESRDYEO0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_RESRDYEO0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_RESRDYEO0) >> DAC_EVCTRL_RESRDYEO0_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_RESRDYEO0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_RESRDYEO0; + tmp |= value << DAC_EVCTRL_RESRDYEO0_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_RESRDYEO0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_RESRDYEO0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_RESRDYEO0_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_RESRDYEO0; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_RESRDYEO1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= DAC_EVCTRL_RESRDYEO1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_EVCTRL_RESRDYEO1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp = (tmp & DAC_EVCTRL_RESRDYEO1) >> DAC_EVCTRL_RESRDYEO1_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_EVCTRL_RESRDYEO1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= ~DAC_EVCTRL_RESRDYEO1; + tmp |= value << DAC_EVCTRL_RESRDYEO1_Pos; + ((Dac *)hw)->EVCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_RESRDYEO1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~DAC_EVCTRL_RESRDYEO1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_RESRDYEO1_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= DAC_EVCTRL_RESRDYEO1; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg |= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_evctrl_reg_t hri_dac_get_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg = data; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg &= ~mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_EVCTRL_reg(const void *const hw, hri_dac_evctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->EVCTRL.reg ^= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_evctrl_reg_t hri_dac_read_EVCTRL_reg(const void *const hw) +{ + return ((Dac *)hw)->EVCTRL.reg; +} + +static inline void hri_dac_set_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_LEFTADJ; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_LEFTADJ) >> DAC_DACCTRL_LEFTADJ_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_LEFTADJ; + tmp |= value << DAC_DACCTRL_LEFTADJ_Pos; + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_LEFTADJ; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_LEFTADJ_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_LEFTADJ; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_ENABLE) >> DAC_DACCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_ENABLE; + tmp |= value << DAC_DACCTRL_ENABLE_Pos; + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_ENABLE; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DACCTRL_FEXT_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_FEXT; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DACCTRL_FEXT_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_FEXT) >> DAC_DACCTRL_FEXT_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DACCTRL_FEXT_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_FEXT; + tmp |= value << DAC_DACCTRL_FEXT_Pos; + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_FEXT_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_FEXT; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_FEXT_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_FEXT; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_RUNSTDBY; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_RUNSTDBY) >> DAC_DACCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_RUNSTDBY; + tmp |= value << DAC_DACCTRL_RUNSTDBY_Pos; + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_RUNSTDBY; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_RUNSTDBY; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_DITHER; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_DITHER) >> DAC_DACCTRL_DITHER_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DACCTRL_DITHER_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_DITHER; + tmp |= value << DAC_DACCTRL_DITHER_Pos; + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_DITHER; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_DITHER_bit(const void *const hw, uint8_t index) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_DITHER; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_CCTRL(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, + hri_dac_dacctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_CCTRL(mask)) >> DAC_DACCTRL_CCTRL_Pos; + return tmp; +} + +static inline void hri_dac_write_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_CCTRL_Msk; + tmp |= DAC_DACCTRL_CCTRL(data); + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_CCTRL(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_CCTRL(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_CCTRL_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_CCTRL_Msk) >> DAC_DACCTRL_CCTRL_Pos; + return tmp; +} + +static inline void hri_dac_set_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_REFRESH(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, + hri_dac_dacctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_REFRESH(mask)) >> DAC_DACCTRL_REFRESH_Pos; + return tmp; +} + +static inline void hri_dac_write_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_REFRESH_Msk; + tmp |= DAC_DACCTRL_REFRESH(data); + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_REFRESH(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_REFRESH(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_REFRESH_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_REFRESH_Msk) >> DAC_DACCTRL_REFRESH_Pos; + return tmp; +} + +static inline void hri_dac_set_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= DAC_DACCTRL_OSR(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_OSR_bf(const void *const hw, uint8_t index, + hri_dac_dacctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_OSR(mask)) >> DAC_DACCTRL_OSR_Pos; + return tmp; +} + +static inline void hri_dac_write_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) +{ + uint16_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= ~DAC_DACCTRL_OSR_Msk; + tmp |= DAC_DACCTRL_OSR(data); + ((Dac *)hw)->DACCTRL[index].reg = tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~DAC_DACCTRL_OSR(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_OSR_bf(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= DAC_DACCTRL_OSR(mask); + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_MASK); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_OSR_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp = (tmp & DAC_DACCTRL_OSR_Msk) >> DAC_DACCTRL_OSR_Pos; + return tmp; +} + +static inline void hri_dac_set_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg |= mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_get_DACCTRL_reg(const void *const hw, uint8_t index, + hri_dac_dacctrl_reg_t mask) +{ + uint16_t tmp; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + tmp = ((Dac *)hw)->DACCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg = data; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg &= ~mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DACCTRL_reg(const void *const hw, uint8_t index, hri_dac_dacctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DACCTRL[index].reg ^= mask; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dacctrl_reg_t hri_dac_read_DACCTRL_reg(const void *const hw, uint8_t index) +{ + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_ENABLE); + return ((Dac *)hw)->DACCTRL[index].reg; +} + +static inline void hri_dac_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg |= DAC_DBGCTRL_DBGRUN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dac_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->DBGCTRL.reg; + tmp = (tmp & DAC_DBGCTRL_DBGRUN) >> DAC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_dac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dac *)hw)->DBGCTRL.reg; + tmp &= ~DAC_DBGCTRL_DBGRUN; + tmp |= value << DAC_DBGCTRL_DBGRUN_Pos; + ((Dac *)hw)->DBGCTRL.reg = tmp; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg &= ~DAC_DBGCTRL_DBGRUN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg ^= DAC_DBGCTRL_DBGRUN; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_set_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg |= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dbgctrl_reg_t hri_dac_get_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dac *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dac_write_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg = data; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_clear_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg &= ~mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_toggle_DBGCTRL_reg(const void *const hw, hri_dac_dbgctrl_reg_t mask) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DBGCTRL.reg ^= mask; + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dac_dbgctrl_reg_t hri_dac_read_DBGCTRL_reg(const void *const hw) +{ + return ((Dac *)hw)->DBGCTRL.reg; +} + +static inline void hri_dac_write_DATA_reg(const void *const hw, uint8_t index, hri_dac_data_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DATA[index].reg = data; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_DATA0 | DAC_SYNCBUSY_DATA1); + DAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dac_write_DATABUF_reg(const void *const hw, uint8_t index, hri_dac_databuf_reg_t data) +{ + DAC_CRITICAL_SECTION_ENTER(); + ((Dac *)hw)->DATABUF[index].reg = data; + hri_dac_wait_for_sync(hw, DAC_SYNCBUSY_DATABUF0 | DAC_SYNCBUSY_DATABUF1); + DAC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_DAC_E54_H_INCLUDED */ +#endif /* _SAME54_DAC_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_dmac_e54.h b/software/firmware/oracle_same54n19a/hri/hri_dmac_e54.h new file mode 100644 index 00000000..b4a6ba1e --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_dmac_e54.h @@ -0,0 +1,6800 @@ +/** + * \file + * + * \brief SAM DMAC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_DMAC_COMPONENT_ +#ifndef _HRI_DMAC_E54_H_INCLUDED_ +#define _HRI_DMAC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_DMAC_CRITICAL_SECTIONS) +#define DMAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define DMAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define DMAC_CRITICAL_SECTION_ENTER() +#define DMAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_dmac_crcctrl_reg_t; +typedef uint16_t hri_dmac_ctrl_reg_t; +typedef uint16_t hri_dmac_intpend_reg_t; +typedef uint16_t hri_dmacdescriptor_btcnt_reg_t; +typedef uint16_t hri_dmacdescriptor_btctrl_reg_t; +typedef uint32_t hri_dmac_active_reg_t; +typedef uint32_t hri_dmac_baseaddr_reg_t; +typedef uint32_t hri_dmac_busych_reg_t; +typedef uint32_t hri_dmac_chctrla_reg_t; +typedef uint32_t hri_dmac_crcchksum_reg_t; +typedef uint32_t hri_dmac_crcdatain_reg_t; +typedef uint32_t hri_dmac_intstatus_reg_t; +typedef uint32_t hri_dmac_pendch_reg_t; +typedef uint32_t hri_dmac_prictrl0_reg_t; +typedef uint32_t hri_dmac_swtrigctrl_reg_t; +typedef uint32_t hri_dmac_wrbaddr_reg_t; +typedef uint32_t hri_dmacchannel_chctrla_reg_t; +typedef uint32_t hri_dmacdescriptor_descaddr_reg_t; +typedef uint32_t hri_dmacdescriptor_dstaddr_reg_t; +typedef uint32_t hri_dmacdescriptor_srcaddr_reg_t; +typedef uint8_t hri_dmac_chctrlb_reg_t; +typedef uint8_t hri_dmac_chevctrl_reg_t; +typedef uint8_t hri_dmac_chintenset_reg_t; +typedef uint8_t hri_dmac_chintflag_reg_t; +typedef uint8_t hri_dmac_chprilvl_reg_t; +typedef uint8_t hri_dmac_chstatus_reg_t; +typedef uint8_t hri_dmac_crcstatus_reg_t; +typedef uint8_t hri_dmac_dbgctrl_reg_t; +typedef uint8_t hri_dmacchannel_chctrlb_reg_t; +typedef uint8_t hri_dmacchannel_chevctrl_reg_t; +typedef uint8_t hri_dmacchannel_chintenset_reg_t; +typedef uint8_t hri_dmacchannel_chintflag_reg_t; +typedef uint8_t hri_dmacchannel_chprilvl_reg_t; +typedef uint8_t hri_dmacchannel_chstatus_reg_t; + +static inline bool hri_dmac_get_INTSTATUS_CHINT0_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT0) >> DMAC_INTSTATUS_CHINT0_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT1_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT1) >> DMAC_INTSTATUS_CHINT1_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT2_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT2) >> DMAC_INTSTATUS_CHINT2_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT3_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT3) >> DMAC_INTSTATUS_CHINT3_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT4_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT4) >> DMAC_INTSTATUS_CHINT4_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT5_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT5) >> DMAC_INTSTATUS_CHINT5_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT6_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT6) >> DMAC_INTSTATUS_CHINT6_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT7_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT7) >> DMAC_INTSTATUS_CHINT7_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT8_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT8) >> DMAC_INTSTATUS_CHINT8_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT9_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT9) >> DMAC_INTSTATUS_CHINT9_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT10_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT10) >> DMAC_INTSTATUS_CHINT10_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT11_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT11) >> DMAC_INTSTATUS_CHINT11_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT12_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT12) >> DMAC_INTSTATUS_CHINT12_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT13_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT13) >> DMAC_INTSTATUS_CHINT13_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT14_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT14) >> DMAC_INTSTATUS_CHINT14_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT15_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT15) >> DMAC_INTSTATUS_CHINT15_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT16_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT16) >> DMAC_INTSTATUS_CHINT16_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT17_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT17) >> DMAC_INTSTATUS_CHINT17_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT18_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT18) >> DMAC_INTSTATUS_CHINT18_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT19_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT19) >> DMAC_INTSTATUS_CHINT19_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT20_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT20) >> DMAC_INTSTATUS_CHINT20_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT21_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT21) >> DMAC_INTSTATUS_CHINT21_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT22_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT22) >> DMAC_INTSTATUS_CHINT22_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT23_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT23) >> DMAC_INTSTATUS_CHINT23_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT24_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT24) >> DMAC_INTSTATUS_CHINT24_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT25_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT25) >> DMAC_INTSTATUS_CHINT25_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT26_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT26) >> DMAC_INTSTATUS_CHINT26_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT27_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT27) >> DMAC_INTSTATUS_CHINT27_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT28_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT28) >> DMAC_INTSTATUS_CHINT28_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT29_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT29) >> DMAC_INTSTATUS_CHINT29_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT30_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT30) >> DMAC_INTSTATUS_CHINT30_Pos; +} + +static inline bool hri_dmac_get_INTSTATUS_CHINT31_bit(const void *const hw) +{ + return (((Dmac *)hw)->INTSTATUS.reg & DMAC_INTSTATUS_CHINT31) >> DMAC_INTSTATUS_CHINT31_Pos; +} + +static inline hri_dmac_intstatus_reg_t hri_dmac_get_INTSTATUS_reg(const void *const hw, hri_dmac_intstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->INTSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_intstatus_reg_t hri_dmac_read_INTSTATUS_reg(const void *const hw) +{ + return ((Dmac *)hw)->INTSTATUS.reg; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH0_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH0) >> DMAC_BUSYCH_BUSYCH0_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH1_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH1) >> DMAC_BUSYCH_BUSYCH1_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH2_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH2) >> DMAC_BUSYCH_BUSYCH2_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH3_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH3) >> DMAC_BUSYCH_BUSYCH3_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH4_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH4) >> DMAC_BUSYCH_BUSYCH4_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH5_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH5) >> DMAC_BUSYCH_BUSYCH5_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH6_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH6) >> DMAC_BUSYCH_BUSYCH6_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH7_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH7) >> DMAC_BUSYCH_BUSYCH7_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH8_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH8) >> DMAC_BUSYCH_BUSYCH8_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH9_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH9) >> DMAC_BUSYCH_BUSYCH9_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH10_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH10) >> DMAC_BUSYCH_BUSYCH10_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH11_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH11) >> DMAC_BUSYCH_BUSYCH11_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH12_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH12) >> DMAC_BUSYCH_BUSYCH12_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH13_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH13) >> DMAC_BUSYCH_BUSYCH13_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH14_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH14) >> DMAC_BUSYCH_BUSYCH14_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH15_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH15) >> DMAC_BUSYCH_BUSYCH15_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH16_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH16) >> DMAC_BUSYCH_BUSYCH16_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH17_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH17) >> DMAC_BUSYCH_BUSYCH17_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH18_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH18) >> DMAC_BUSYCH_BUSYCH18_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH19_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH19) >> DMAC_BUSYCH_BUSYCH19_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH20_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH20) >> DMAC_BUSYCH_BUSYCH20_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH21_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH21) >> DMAC_BUSYCH_BUSYCH21_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH22_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH22) >> DMAC_BUSYCH_BUSYCH22_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH23_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH23) >> DMAC_BUSYCH_BUSYCH23_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH24_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH24) >> DMAC_BUSYCH_BUSYCH24_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH25_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH25) >> DMAC_BUSYCH_BUSYCH25_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH26_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH26) >> DMAC_BUSYCH_BUSYCH26_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH27_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH27) >> DMAC_BUSYCH_BUSYCH27_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH28_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH28) >> DMAC_BUSYCH_BUSYCH28_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH29_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH29) >> DMAC_BUSYCH_BUSYCH29_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH30_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH30) >> DMAC_BUSYCH_BUSYCH30_Pos; +} + +static inline bool hri_dmac_get_BUSYCH_BUSYCH31_bit(const void *const hw) +{ + return (((Dmac *)hw)->BUSYCH.reg & DMAC_BUSYCH_BUSYCH31) >> DMAC_BUSYCH_BUSYCH31_Pos; +} + +static inline hri_dmac_busych_reg_t hri_dmac_get_BUSYCH_reg(const void *const hw, hri_dmac_busych_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BUSYCH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_busych_reg_t hri_dmac_read_BUSYCH_reg(const void *const hw) +{ + return ((Dmac *)hw)->BUSYCH.reg; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH0_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH0) >> DMAC_PENDCH_PENDCH0_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH1_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH1) >> DMAC_PENDCH_PENDCH1_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH2_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH2) >> DMAC_PENDCH_PENDCH2_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH3_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH3) >> DMAC_PENDCH_PENDCH3_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH4_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH4) >> DMAC_PENDCH_PENDCH4_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH5_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH5) >> DMAC_PENDCH_PENDCH5_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH6_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH6) >> DMAC_PENDCH_PENDCH6_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH7_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH7) >> DMAC_PENDCH_PENDCH7_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH8_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH8) >> DMAC_PENDCH_PENDCH8_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH9_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH9) >> DMAC_PENDCH_PENDCH9_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH10_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH10) >> DMAC_PENDCH_PENDCH10_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH11_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH11) >> DMAC_PENDCH_PENDCH11_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH12_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH12) >> DMAC_PENDCH_PENDCH12_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH13_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH13) >> DMAC_PENDCH_PENDCH13_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH14_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH14) >> DMAC_PENDCH_PENDCH14_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH15_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH15) >> DMAC_PENDCH_PENDCH15_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH16_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH16) >> DMAC_PENDCH_PENDCH16_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH17_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH17) >> DMAC_PENDCH_PENDCH17_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH18_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH18) >> DMAC_PENDCH_PENDCH18_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH19_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH19) >> DMAC_PENDCH_PENDCH19_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH20_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH20) >> DMAC_PENDCH_PENDCH20_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH21_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH21) >> DMAC_PENDCH_PENDCH21_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH22_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH22) >> DMAC_PENDCH_PENDCH22_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH23_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH23) >> DMAC_PENDCH_PENDCH23_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH24_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH24) >> DMAC_PENDCH_PENDCH24_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH25_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH25) >> DMAC_PENDCH_PENDCH25_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH26_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH26) >> DMAC_PENDCH_PENDCH26_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH27_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH27) >> DMAC_PENDCH_PENDCH27_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH28_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH28) >> DMAC_PENDCH_PENDCH28_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH29_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH29) >> DMAC_PENDCH_PENDCH29_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH30_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH30) >> DMAC_PENDCH_PENDCH30_Pos; +} + +static inline bool hri_dmac_get_PENDCH_PENDCH31_bit(const void *const hw) +{ + return (((Dmac *)hw)->PENDCH.reg & DMAC_PENDCH_PENDCH31) >> DMAC_PENDCH_PENDCH31_Pos; +} + +static inline hri_dmac_pendch_reg_t hri_dmac_get_PENDCH_reg(const void *const hw, hri_dmac_pendch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PENDCH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_pendch_reg_t hri_dmac_read_PENDCH_reg(const void *const hw) +{ + return ((Dmac *)hw)->PENDCH.reg; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX0_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX0) >> DMAC_ACTIVE_LVLEX0_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX1_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX1) >> DMAC_ACTIVE_LVLEX1_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX2_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX2) >> DMAC_ACTIVE_LVLEX2_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_LVLEX3_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_LVLEX3) >> DMAC_ACTIVE_LVLEX3_Pos; +} + +static inline bool hri_dmac_get_ACTIVE_ABUSY_bit(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ABUSY) >> DMAC_ACTIVE_ABUSY_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_ID_bf(const void *const hw, hri_dmac_active_reg_t mask) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID(mask)) >> DMAC_ACTIVE_ID_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_ID_bf(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_ID_Msk) >> DMAC_ACTIVE_ID_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_BTCNT_bf(const void *const hw, hri_dmac_active_reg_t mask) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT(mask)) >> DMAC_ACTIVE_BTCNT_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_BTCNT_bf(const void *const hw) +{ + return (((Dmac *)hw)->ACTIVE.reg & DMAC_ACTIVE_BTCNT_Msk) >> DMAC_ACTIVE_BTCNT_Pos; +} + +static inline hri_dmac_active_reg_t hri_dmac_get_ACTIVE_reg(const void *const hw, hri_dmac_active_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->ACTIVE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_active_reg_t hri_dmac_read_ACTIVE_reg(const void *const hw) +{ + return ((Dmac *)hw)->ACTIVE.reg; +} + +static inline void hri_dmac_set_CTRL_SWRST_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_SWRST; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_SWRST) >> DMAC_CTRL_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_set_CTRL_DMAENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_DMAENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_DMAENABLE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_DMAENABLE) >> DMAC_CTRL_DMAENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_DMAENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_DMAENABLE; + tmp |= value << DMAC_CTRL_DMAENABLE_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_DMAENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_DMAENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_DMAENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_DMAENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN0) >> DMAC_CTRL_LVLEN0_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN0; + tmp |= value << DMAC_CTRL_LVLEN0_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN1) >> DMAC_CTRL_LVLEN1_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN1; + tmp |= value << DMAC_CTRL_LVLEN1_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN2) >> DMAC_CTRL_LVLEN2_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN2; + tmp |= value << DMAC_CTRL_LVLEN2_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_LVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= DMAC_CTRL_LVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CTRL_LVLEN3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp = (tmp & DMAC_CTRL_LVLEN3) >> DMAC_CTRL_LVLEN3_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CTRL_LVLEN3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= ~DMAC_CTRL_LVLEN3; + tmp |= value << DMAC_CTRL_LVLEN3_Pos; + ((Dmac *)hw)->CTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_LVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~DMAC_CTRL_LVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_LVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= DMAC_CTRL_LVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_ctrl_reg_t hri_dmac_get_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CTRL_reg(const void *const hw, hri_dmac_ctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_ctrl_reg_t hri_dmac_read_CTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->CTRL.reg; +} + +static inline void hri_dmac_set_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCBEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, + hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE(mask)) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCBEATSIZE_Msk; + tmp |= DMAC_CRCCTRL_CRCBEATSIZE(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCBEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCBEATSIZE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCBEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCBEATSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCBEATSIZE_Msk) >> DMAC_CRCCTRL_CRCBEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCPOLY(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCPOLY(mask)) >> DMAC_CRCCTRL_CRCPOLY_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCPOLY_Msk; + tmp |= DMAC_CRCCTRL_CRCPOLY(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCPOLY(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCPOLY_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCPOLY(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCPOLY_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCPOLY_Msk) >> DMAC_CRCCTRL_CRCPOLY_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCSRC(mask)) >> DMAC_CRCCTRL_CRCSRC_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCSRC_Msk; + tmp |= DMAC_CRCCTRL_CRCSRC(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCSRC_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCSRC_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCSRC_Msk) >> DMAC_CRCCTRL_CRCSRC_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= DMAC_CRCCTRL_CRCMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCMODE(mask)) >> DMAC_CRCCTRL_CRCMODE_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= ~DMAC_CRCCTRL_CRCMODE_Msk; + tmp |= DMAC_CRCCTRL_CRCMODE(data); + ((Dmac *)hw)->CRCCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~DMAC_CRCCTRL_CRCMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_CRCMODE_bf(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= DMAC_CRCCTRL_CRCMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_CRCMODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp = (tmp & DMAC_CRCCTRL_CRCMODE_Msk) >> DMAC_CRCCTRL_CRCMODE_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_get_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->CRCCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCTRL_reg(const void *const hw, hri_dmac_crcctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcctrl_reg_t hri_dmac_read_CRCCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCCTRL.reg; +} + +static inline void hri_dmac_set_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg |= DMAC_CRCDATAIN_CRCDATAIN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_CRCDATAIN_bf(const void *const hw, + hri_dmac_crcdatain_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN(mask)) >> DMAC_CRCDATAIN_CRCDATAIN_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp &= ~DMAC_CRCDATAIN_CRCDATAIN_Msk; + tmp |= DMAC_CRCDATAIN_CRCDATAIN(data); + ((Dmac *)hw)->CRCDATAIN.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg &= ~DMAC_CRCDATAIN_CRCDATAIN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCDATAIN_CRCDATAIN_bf(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg ^= DMAC_CRCDATAIN_CRCDATAIN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_CRCDATAIN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp = (tmp & DMAC_CRCDATAIN_CRCDATAIN_Msk) >> DMAC_CRCDATAIN_CRCDATAIN_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_get_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCDATAIN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCDATAIN_reg(const void *const hw, hri_dmac_crcdatain_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCDATAIN.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcdatain_reg_t hri_dmac_read_CRCDATAIN_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCDATAIN.reg; +} + +static inline void hri_dmac_set_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg |= DMAC_CRCCHKSUM_CRCCHKSUM(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, + hri_dmac_crcchksum_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM(mask)) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos; + return tmp; +} + +static inline void hri_dmac_write_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp &= ~DMAC_CRCCHKSUM_CRCCHKSUM_Msk; + tmp |= DMAC_CRCCHKSUM_CRCCHKSUM(data); + ((Dmac *)hw)->CRCCHKSUM.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg &= ~DMAC_CRCCHKSUM_CRCCHKSUM(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg ^= DMAC_CRCCHKSUM_CRCCHKSUM(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_CRCCHKSUM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp = (tmp & DMAC_CRCCHKSUM_CRCCHKSUM_Msk) >> DMAC_CRCCHKSUM_CRCCHKSUM_Pos; + return tmp; +} + +static inline void hri_dmac_set_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_get_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->CRCCHKSUM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CRCCHKSUM_reg(const void *const hw, hri_dmac_crcchksum_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCCHKSUM.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcchksum_reg_t hri_dmac_read_CRCCHKSUM_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCCHKSUM.reg; +} + +static inline void hri_dmac_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg |= DMAC_DBGCTRL_DBGRUN; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->DBGCTRL.reg; + tmp = (tmp & DMAC_DBGCTRL_DBGRUN) >> DMAC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->DBGCTRL.reg; + tmp &= ~DMAC_DBGCTRL_DBGRUN; + tmp |= value << DMAC_DBGCTRL_DBGRUN_Pos; + ((Dmac *)hw)->DBGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg &= ~DMAC_DBGCTRL_DBGRUN; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg ^= DMAC_DBGCTRL_DBGRUN; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_dbgctrl_reg_t hri_dmac_get_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_DBGCTRL_reg(const void *const hw, hri_dmac_dbgctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->DBGCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_dbgctrl_reg_t hri_dmac_read_DBGCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->DBGCTRL.reg; +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG0) >> DMAC_SWTRIGCTRL_SWTRIG0_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG0; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG0_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG1) >> DMAC_SWTRIGCTRL_SWTRIG1_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG1; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG1_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG2) >> DMAC_SWTRIGCTRL_SWTRIG2_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG2; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG2_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG3) >> DMAC_SWTRIGCTRL_SWTRIG3_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG3; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG3_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG4; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG4) >> DMAC_SWTRIGCTRL_SWTRIG4_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG4; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG4_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG4; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG4_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG4; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG5; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG5) >> DMAC_SWTRIGCTRL_SWTRIG5_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG5; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG5_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG5; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG5_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG5; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG6; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG6) >> DMAC_SWTRIGCTRL_SWTRIG6_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG6; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG6_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG6; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG6_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG6; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG7; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG7) >> DMAC_SWTRIGCTRL_SWTRIG7_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG7; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG7_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG7; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG7_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG7; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG8; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG8) >> DMAC_SWTRIGCTRL_SWTRIG8_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG8_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG8; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG8_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG8; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG8_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG8; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG9; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG9) >> DMAC_SWTRIGCTRL_SWTRIG9_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG9_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG9; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG9_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG9; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG9_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG9; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG10; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG10) >> DMAC_SWTRIGCTRL_SWTRIG10_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG10_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG10; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG10_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG10; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG10_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG10; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG11; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG11) >> DMAC_SWTRIGCTRL_SWTRIG11_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG11_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG11; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG11_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG11; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG11_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG11; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG12; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG12) >> DMAC_SWTRIGCTRL_SWTRIG12_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG12_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG12; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG12_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG12; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG12_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG12; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG13; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG13) >> DMAC_SWTRIGCTRL_SWTRIG13_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG13_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG13; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG13_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG13; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG13_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG13; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG14; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG14) >> DMAC_SWTRIGCTRL_SWTRIG14_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG14_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG14; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG14_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG14; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG14_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG14; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG15; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG15) >> DMAC_SWTRIGCTRL_SWTRIG15_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG15_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG15; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG15_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG15; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG15_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG15; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG16_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG16; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG16_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG16) >> DMAC_SWTRIGCTRL_SWTRIG16_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG16_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG16; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG16_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG16_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG16; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG16_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG16; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG17_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG17; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG17_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG17) >> DMAC_SWTRIGCTRL_SWTRIG17_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG17_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG17; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG17_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG17_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG17; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG17_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG17; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG18_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG18; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG18_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG18) >> DMAC_SWTRIGCTRL_SWTRIG18_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG18_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG18; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG18_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG18_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG18; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG18_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG18; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG19_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG19; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG19_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG19) >> DMAC_SWTRIGCTRL_SWTRIG19_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG19_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG19; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG19_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG19_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG19; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG19_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG19; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG20_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG20; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG20_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG20) >> DMAC_SWTRIGCTRL_SWTRIG20_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG20_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG20; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG20_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG20_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG20; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG20_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG20; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG21_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG21; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG21_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG21) >> DMAC_SWTRIGCTRL_SWTRIG21_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG21_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG21; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG21_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG21_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG21; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG21_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG21; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG22_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG22; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG22_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG22) >> DMAC_SWTRIGCTRL_SWTRIG22_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG22_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG22; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG22_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG22_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG22; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG22_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG22; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG23_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG23; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG23_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG23) >> DMAC_SWTRIGCTRL_SWTRIG23_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG23_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG23; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG23_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG23_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG23; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG23_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG23; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG24_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG24; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG24_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG24) >> DMAC_SWTRIGCTRL_SWTRIG24_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG24_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG24; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG24_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG24_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG24; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG24_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG24; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG25_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG25; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG25_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG25) >> DMAC_SWTRIGCTRL_SWTRIG25_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG25_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG25; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG25_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG25_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG25; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG25_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG25; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG26_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG26; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG26_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG26) >> DMAC_SWTRIGCTRL_SWTRIG26_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG26_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG26; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG26_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG26_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG26; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG26_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG26; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG27_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG27; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG27_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG27) >> DMAC_SWTRIGCTRL_SWTRIG27_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG27_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG27; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG27_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG27_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG27; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG27_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG27; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG28_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG28; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG28_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG28) >> DMAC_SWTRIGCTRL_SWTRIG28_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG28_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG28; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG28_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG28_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG28; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG28_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG28; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG29_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG29; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG29_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG29) >> DMAC_SWTRIGCTRL_SWTRIG29_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG29_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG29; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG29_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG29_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG29; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG29_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG29; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG30_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG30; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG30_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG30) >> DMAC_SWTRIGCTRL_SWTRIG30_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG30_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG30; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG30_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG30_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG30; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG30_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG30; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_SWTRIG31_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= DMAC_SWTRIGCTRL_SWTRIG31; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_SWTRIGCTRL_SWTRIG31_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp = (tmp & DMAC_SWTRIGCTRL_SWTRIG31) >> DMAC_SWTRIGCTRL_SWTRIG31_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_SWTRIG31_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= ~DMAC_SWTRIGCTRL_SWTRIG31; + tmp |= value << DMAC_SWTRIGCTRL_SWTRIG31_Pos; + ((Dmac *)hw)->SWTRIGCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_SWTRIG31_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~DMAC_SWTRIGCTRL_SWTRIG31; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_SWTRIG31_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= DMAC_SWTRIGCTRL_SWTRIG31; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_swtrigctrl_reg_t hri_dmac_get_SWTRIGCTRL_reg(const void *const hw, + hri_dmac_swtrigctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->SWTRIGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_SWTRIGCTRL_reg(const void *const hw, hri_dmac_swtrigctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->SWTRIGCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_swtrigctrl_reg_t hri_dmac_read_SWTRIGCTRL_reg(const void *const hw) +{ + return ((Dmac *)hw)->SWTRIGCTRL.reg; +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN0) >> DMAC_PRICTRL0_RRLVLEN0_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN0; + tmp |= value << DMAC_PRICTRL0_RRLVLEN0_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN0_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN0; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN1) >> DMAC_PRICTRL0_RRLVLEN1_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN1; + tmp |= value << DMAC_PRICTRL0_RRLVLEN1_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN1_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN1; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN2) >> DMAC_PRICTRL0_RRLVLEN2_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN2; + tmp |= value << DMAC_PRICTRL0_RRLVLEN2_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN2_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN2; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_RRLVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_RRLVLEN3) >> DMAC_PRICTRL0_RRLVLEN3_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_PRICTRL0_RRLVLEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_RRLVLEN3; + tmp |= value << DMAC_PRICTRL0_RRLVLEN3_Pos; + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_RRLVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_RRLVLEN3_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_RRLVLEN3; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI0_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI0(mask)) >> DMAC_PRICTRL0_LVLPRI0_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI0_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI0(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI0_Msk) >> DMAC_PRICTRL0_LVLPRI0_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS0(mask)) >> DMAC_PRICTRL0_QOS0_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_QOS0_Msk; + tmp |= DMAC_PRICTRL0_QOS0(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_QOS0_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS0(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS0_Msk) >> DMAC_PRICTRL0_QOS0_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI1_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI1(mask)) >> DMAC_PRICTRL0_LVLPRI1_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI1_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI1(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI1_Msk) >> DMAC_PRICTRL0_LVLPRI1_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS1(mask)) >> DMAC_PRICTRL0_QOS1_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_QOS1_Msk; + tmp |= DMAC_PRICTRL0_QOS1(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_QOS1_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS1(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS1_Msk) >> DMAC_PRICTRL0_QOS1_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI2_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI2(mask)) >> DMAC_PRICTRL0_LVLPRI2_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI2_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI2(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI2_Msk) >> DMAC_PRICTRL0_LVLPRI2_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS2(mask)) >> DMAC_PRICTRL0_QOS2_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_QOS2_Msk; + tmp |= DMAC_PRICTRL0_QOS2(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_QOS2_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS2(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS2_Msk) >> DMAC_PRICTRL0_QOS2_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_LVLPRI3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_LVLPRI3_bf(const void *const hw, + hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI3(mask)) >> DMAC_PRICTRL0_LVLPRI3_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_LVLPRI3_Msk; + tmp |= DMAC_PRICTRL0_LVLPRI3(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_LVLPRI3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_LVLPRI3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_LVLPRI3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_LVLPRI3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_LVLPRI3_Msk) >> DMAC_PRICTRL0_LVLPRI3_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= DMAC_PRICTRL0_QOS3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS3(mask)) >> DMAC_PRICTRL0_QOS3_Pos; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= ~DMAC_PRICTRL0_QOS3_Msk; + tmp |= DMAC_PRICTRL0_QOS3(data); + ((Dmac *)hw)->PRICTRL0.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~DMAC_PRICTRL0_QOS3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_QOS3_bf(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= DMAC_PRICTRL0_QOS3(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_QOS3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp = (tmp & DMAC_PRICTRL0_QOS3_Msk) >> DMAC_PRICTRL0_QOS3_Pos; + return tmp; +} + +static inline void hri_dmac_set_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_get_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->PRICTRL0.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_PRICTRL0_reg(const void *const hw, hri_dmac_prictrl0_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->PRICTRL0.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_prictrl0_reg_t hri_dmac_read_PRICTRL0_reg(const void *const hw) +{ + return ((Dmac *)hw)->PRICTRL0.reg; +} + +static inline void hri_dmac_set_INTPEND_TERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_TERR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_TERR) >> DMAC_INTPEND_TERR_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_TERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_TERR; + tmp |= value << DMAC_INTPEND_TERR_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_TERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_TERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_TCMPL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_TCMPL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_TCMPL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_TCMPL) >> DMAC_INTPEND_TCMPL_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_TCMPL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_TCMPL; + tmp |= value << DMAC_INTPEND_TCMPL_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_TCMPL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_TCMPL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_TCMPL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_TCMPL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_SUSP_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_SUSP; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_SUSP_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_SUSP) >> DMAC_INTPEND_SUSP_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_SUSP_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_SUSP; + tmp |= value << DMAC_INTPEND_SUSP_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_SUSP_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_SUSP; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_SUSP_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_SUSP; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_CRCERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_CRCERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_CRCERR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_CRCERR) >> DMAC_INTPEND_CRCERR_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_CRCERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_CRCERR; + tmp |= value << DMAC_INTPEND_CRCERR_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_CRCERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_CRCERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_CRCERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_CRCERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_FERR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_FERR) >> DMAC_INTPEND_FERR_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_FERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_FERR; + tmp |= value << DMAC_INTPEND_FERR_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_BUSY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_BUSY) >> DMAC_INTPEND_BUSY_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_BUSY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_BUSY; + tmp |= value << DMAC_INTPEND_BUSY_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_INTPEND_PEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_PEND) >> DMAC_INTPEND_PEND_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_INTPEND_PEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_PEND; + tmp |= value << DMAC_INTPEND_PEND_Pos; + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= DMAC_INTPEND_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_ID(mask)) >> DMAC_INTPEND_ID_Pos; + return tmp; +} + +static inline void hri_dmac_write_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= ~DMAC_INTPEND_ID_Msk; + tmp |= DMAC_INTPEND_ID(data); + ((Dmac *)hw)->INTPEND.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~DMAC_INTPEND_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_ID_bf(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= DMAC_INTPEND_ID(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_ID_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp = (tmp & DMAC_INTPEND_ID_Msk) >> DMAC_INTPEND_ID_Pos; + return tmp; +} + +static inline void hri_dmac_set_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_get_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + uint16_t tmp; + tmp = ((Dmac *)hw)->INTPEND.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_INTPEND_reg(const void *const hw, hri_dmac_intpend_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->INTPEND.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_intpend_reg_t hri_dmac_read_INTPEND_reg(const void *const hw) +{ + return ((Dmac *)hw)->INTPEND.reg; +} + +static inline void hri_dmac_set_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg |= DMAC_BASEADDR_BASEADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_BASEADDR_bf(const void *const hw, + hri_dmac_baseaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp = (tmp & DMAC_BASEADDR_BASEADDR(mask)) >> DMAC_BASEADDR_BASEADDR_Pos; + return tmp; +} + +static inline void hri_dmac_write_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp &= ~DMAC_BASEADDR_BASEADDR_Msk; + tmp |= DMAC_BASEADDR_BASEADDR(data); + ((Dmac *)hw)->BASEADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg &= ~DMAC_BASEADDR_BASEADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_BASEADDR_BASEADDR_bf(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg ^= DMAC_BASEADDR_BASEADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_BASEADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp = (tmp & DMAC_BASEADDR_BASEADDR_Msk) >> DMAC_BASEADDR_BASEADDR_Pos; + return tmp; +} + +static inline void hri_dmac_set_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_get_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->BASEADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_BASEADDR_reg(const void *const hw, hri_dmac_baseaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->BASEADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_baseaddr_reg_t hri_dmac_read_BASEADDR_reg(const void *const hw) +{ + return ((Dmac *)hw)->BASEADDR.reg; +} + +static inline void hri_dmac_set_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg |= DMAC_WRBADDR_WRBADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp = (tmp & DMAC_WRBADDR_WRBADDR(mask)) >> DMAC_WRBADDR_WRBADDR_Pos; + return tmp; +} + +static inline void hri_dmac_write_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp &= ~DMAC_WRBADDR_WRBADDR_Msk; + tmp |= DMAC_WRBADDR_WRBADDR(data); + ((Dmac *)hw)->WRBADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg &= ~DMAC_WRBADDR_WRBADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_WRBADDR_WRBADDR_bf(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg ^= DMAC_WRBADDR_WRBADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_WRBADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp = (tmp & DMAC_WRBADDR_WRBADDR_Msk) >> DMAC_WRBADDR_WRBADDR_Pos; + return tmp; +} + +static inline void hri_dmac_set_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_get_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->WRBADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_WRBADDR_reg(const void *const hw, hri_dmac_wrbaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->WRBADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_wrbaddr_reg_t hri_dmac_read_WRBADDR_reg(const void *const hw) +{ + return ((Dmac *)hw)->WRBADDR.reg; +} + +static inline bool hri_dmac_get_CRCSTATUS_CRCBUSY_bit(const void *const hw) +{ + return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCBUSY) >> DMAC_CRCSTATUS_CRCBUSY_Pos; +} + +static inline void hri_dmac_clear_CRCSTATUS_CRCBUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCBUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CRCSTATUS_CRCZERO_bit(const void *const hw) +{ + return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCZERO) >> DMAC_CRCSTATUS_CRCZERO_Pos; +} + +static inline void hri_dmac_clear_CRCSTATUS_CRCZERO_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCZERO; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CRCSTATUS_CRCERR_bit(const void *const hw) +{ + return (((Dmac *)hw)->CRCSTATUS.reg & DMAC_CRCSTATUS_CRCERR) >> DMAC_CRCSTATUS_CRCERR_Pos; +} + +static inline void hri_dmac_clear_CRCSTATUS_CRCERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = DMAC_CRCSTATUS_CRCERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcstatus_reg_t hri_dmac_get_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->CRCSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_clear_CRCSTATUS_reg(const void *const hw, hri_dmac_crcstatus_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->CRCSTATUS.reg = mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_crcstatus_reg_t hri_dmac_read_CRCSTATUS_reg(const void *const hw) +{ + return ((Dmac *)hw)->CRCSTATUS.reg; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_VALID_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_VALID; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_VALID_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_VALID) >> DMAC_BTCTRL_VALID_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_VALID_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_VALID; + tmp |= value << DMAC_BTCTRL_VALID_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_VALID_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_VALID; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_VALID_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_VALID; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_SRCINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_SRCINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_SRCINC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_SRCINC) >> DMAC_BTCTRL_SRCINC_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_SRCINC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_SRCINC; + tmp |= value << DMAC_BTCTRL_SRCINC_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_SRCINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_SRCINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_SRCINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_SRCINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_DSTINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_DSTINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_DSTINC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_DSTINC) >> DMAC_BTCTRL_DSTINC_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_DSTINC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_DSTINC; + tmp |= value << DMAC_BTCTRL_DSTINC_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_DSTINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_DSTINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_DSTINC_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_DSTINC; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_STEPSEL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSEL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacdescriptor_get_BTCTRL_STEPSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_STEPSEL) >> DMAC_BTCTRL_STEPSEL_Pos; + return (bool)tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_STEPSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_STEPSEL; + tmp |= value << DMAC_BTCTRL_STEPSEL_Pos; + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSEL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSEL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSEL_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSEL; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_set_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_EVOSEL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_EVOSEL(mask)) >> DMAC_BTCTRL_EVOSEL_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_EVOSEL_Msk; + tmp |= DMAC_BTCTRL_EVOSEL(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_EVOSEL_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_EVOSEL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_EVOSEL_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_EVOSEL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_EVOSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_EVOSEL_Msk) >> DMAC_BTCTRL_EVOSEL_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BLOCKACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_BLOCKACT_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BLOCKACT(mask)) >> DMAC_BTCTRL_BLOCKACT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_BLOCKACT_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_BLOCKACT_Msk; + tmp |= DMAC_BTCTRL_BLOCKACT(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_BLOCKACT_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BLOCKACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_BLOCKACT_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BLOCKACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BLOCKACT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BLOCKACT_Msk) >> DMAC_BTCTRL_BLOCKACT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_BEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_BEATSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BEATSIZE(mask)) >> DMAC_BTCTRL_BEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_BEATSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_BEATSIZE_Msk; + tmp |= DMAC_BTCTRL_BEATSIZE(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_BEATSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_BEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_BEATSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_BEATSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_BEATSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_BEATSIZE_Msk) >> DMAC_BTCTRL_BEATSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= DMAC_BTCTRL_STEPSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t +hri_dmacdescriptor_get_BTCTRL_STEPSIZE_bf(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_STEPSIZE(mask)) >> DMAC_BTCTRL_STEPSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_STEPSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= ~DMAC_BTCTRL_STEPSIZE_Msk; + tmp |= DMAC_BTCTRL_STEPSIZE(data); + ((DmacDescriptor *)hw)->BTCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_STEPSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~DMAC_BTCTRL_STEPSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_STEPSIZE_bf(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= DMAC_BTCTRL_STEPSIZE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_STEPSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp = (tmp & DMAC_BTCTRL_STEPSIZE_Msk) >> DMAC_BTCTRL_STEPSIZE_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_get_BTCTRL_reg(const void *const hw, + hri_dmacdescriptor_btctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCTRL_reg(const void *const hw, hri_dmacdescriptor_btctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btctrl_reg_t hri_dmacdescriptor_read_BTCTRL_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->BTCTRL.reg; +} + +static inline void hri_dmacdescriptor_set_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg |= DMAC_BTCNT_BTCNT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_BTCNT_bf(const void *const hw, + hri_dmacdescriptor_btcnt_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp = (tmp & DMAC_BTCNT_BTCNT(mask)) >> DMAC_BTCNT_BTCNT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data) +{ + uint16_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp &= ~DMAC_BTCNT_BTCNT_Msk; + tmp |= DMAC_BTCNT_BTCNT(data); + ((DmacDescriptor *)hw)->BTCNT.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg &= ~DMAC_BTCNT_BTCNT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCNT_BTCNT_bf(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg ^= DMAC_BTCNT_BTCNT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_BTCNT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp = (tmp & DMAC_BTCNT_BTCNT_Msk) >> DMAC_BTCNT_BTCNT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_get_BTCNT_reg(const void *const hw, + hri_dmacdescriptor_btcnt_reg_t mask) +{ + uint16_t tmp; + tmp = ((DmacDescriptor *)hw)->BTCNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_BTCNT_reg(const void *const hw, hri_dmacdescriptor_btcnt_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->BTCNT.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_btcnt_reg_t hri_dmacdescriptor_read_BTCNT_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->BTCNT.reg; +} + +static inline void hri_dmacdescriptor_set_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg |= DMAC_SRCADDR_SRCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t +hri_dmacdescriptor_get_SRCADDR_SRCADDR_bf(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp = (tmp & DMAC_SRCADDR_SRCADDR(mask)) >> DMAC_SRCADDR_SRCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp &= ~DMAC_SRCADDR_SRCADDR_Msk; + tmp |= DMAC_SRCADDR_SRCADDR(data); + ((DmacDescriptor *)hw)->SRCADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg &= ~DMAC_SRCADDR_SRCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_SRCADDR_SRCADDR_bf(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg ^= DMAC_SRCADDR_SRCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_SRCADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp = (tmp & DMAC_SRCADDR_SRCADDR_Msk) >> DMAC_SRCADDR_SRCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_get_SRCADDR_reg(const void *const hw, + hri_dmacdescriptor_srcaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->SRCADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_SRCADDR_reg(const void *const hw, hri_dmacdescriptor_srcaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->SRCADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_srcaddr_reg_t hri_dmacdescriptor_read_SRCADDR_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->SRCADDR.reg; +} + +static inline void hri_dmacdescriptor_set_DSTADDR_CRC_CHKINIT_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg |= DMAC_DSTADDR_CRC_CHKINIT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t +hri_dmacdescriptor_get_DSTADDR_CRC_CHKINIT_bf(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp = (tmp & DMAC_DSTADDR_CRC_CHKINIT(mask)) >> DMAC_DSTADDR_CRC_CHKINIT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DSTADDR_CRC_CHKINIT_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp &= ~DMAC_DSTADDR_CRC_CHKINIT_Msk; + tmp |= DMAC_DSTADDR_CRC_CHKINIT(data); + ((DmacDescriptor *)hw)->DSTADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DSTADDR_CRC_CHKINIT_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg &= ~DMAC_DSTADDR_CRC_CHKINIT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DSTADDR_CRC_CHKINIT_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg ^= DMAC_DSTADDR_CRC_CHKINIT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_CRC_CHKINIT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp = (tmp & DMAC_DSTADDR_CRC_CHKINIT_Msk) >> DMAC_DSTADDR_CRC_CHKINIT_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg |= DMAC_DSTADDR_DSTADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t +hri_dmacdescriptor_get_DSTADDR_DSTADDR_bf(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp = (tmp & DMAC_DSTADDR_DSTADDR(mask)) >> DMAC_DSTADDR_DSTADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp &= ~DMAC_DSTADDR_DSTADDR_Msk; + tmp |= DMAC_DSTADDR_DSTADDR(data); + ((DmacDescriptor *)hw)->DSTADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg &= ~DMAC_DSTADDR_DSTADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DSTADDR_DSTADDR_bf(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg ^= DMAC_DSTADDR_DSTADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_DSTADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp = (tmp & DMAC_DSTADDR_DSTADDR_Msk) >> DMAC_DSTADDR_DSTADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_get_DSTADDR_reg(const void *const hw, + hri_dmacdescriptor_dstaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DSTADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DSTADDR_reg(const void *const hw, hri_dmacdescriptor_dstaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DSTADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_dstaddr_reg_t hri_dmacdescriptor_read_DSTADDR_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->DSTADDR.reg; +} + +static inline void hri_dmacdescriptor_set_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg |= DMAC_DESCADDR_DESCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t +hri_dmacdescriptor_get_DESCADDR_DESCADDR_bf(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp = (tmp & DMAC_DESCADDR_DESCADDR(mask)) >> DMAC_DESCADDR_DESCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp &= ~DMAC_DESCADDR_DESCADDR_Msk; + tmp |= DMAC_DESCADDR_DESCADDR(data); + ((DmacDescriptor *)hw)->DESCADDR.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg &= ~DMAC_DESCADDR_DESCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DESCADDR_DESCADDR_bf(const void *const hw, + hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg ^= DMAC_DESCADDR_DESCADDR(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_DESCADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp = (tmp & DMAC_DESCADDR_DESCADDR_Msk) >> DMAC_DESCADDR_DESCADDR_Pos; + return tmp; +} + +static inline void hri_dmacdescriptor_set_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t +hri_dmacdescriptor_get_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacDescriptor *)hw)->DESCADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacdescriptor_write_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_clear_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacdescriptor_toggle_DESCADDR_reg(const void *const hw, hri_dmacdescriptor_descaddr_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacDescriptor *)hw)->DESCADDR.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmacdescriptor_descaddr_reg_t hri_dmacdescriptor_read_DESCADDR_reg(const void *const hw) +{ + return ((DmacDescriptor *)hw)->DESCADDR.reg; +} + +static inline bool hri_dmacchannel_get_CHINTFLAG_TERR_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; +} + +static inline void hri_dmacchannel_clear_CHINTFLAG_TERR_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; +} + +static inline bool hri_dmacchannel_get_CHINTFLAG_TCMPL_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; +} + +static inline void hri_dmacchannel_clear_CHINTFLAG_TCMPL_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; +} + +static inline bool hri_dmacchannel_get_CHINTFLAG_SUSP_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; +} + +static inline void hri_dmacchannel_clear_CHINTFLAG_SUSP_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; +} + +static inline bool hri_dmacchannel_get_interrupt_TERR_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; +} + +static inline void hri_dmacchannel_clear_interrupt_TERR_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; +} + +static inline bool hri_dmacchannel_get_interrupt_TCMPL_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; +} + +static inline void hri_dmacchannel_clear_interrupt_TCMPL_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; +} + +static inline bool hri_dmacchannel_get_interrupt_SUSP_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; +} + +static inline void hri_dmacchannel_clear_interrupt_SUSP_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; +} + +static inline hri_dmac_chintflag_reg_t hri_dmacchannel_get_CHINTFLAG_reg(const void *const hw, + hri_dmac_chintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chintflag_reg_t hri_dmacchannel_read_CHINTFLAG_reg(const void *const hw) +{ + return ((DmacChannel *)hw)->CHINTFLAG.reg; +} + +static inline void hri_dmacchannel_clear_CHINTFLAG_reg(const void *const hw, hri_dmac_chintflag_reg_t mask) +{ + ((DmacChannel *)hw)->CHINTFLAG.reg = mask; +} + +static inline void hri_dmacchannel_set_CHINTEN_TERR_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; +} + +static inline bool hri_dmacchannel_get_CHINTEN_TERR_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos; +} + +static inline void hri_dmacchannel_write_CHINTEN_TERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; + } else { + ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TERR; + } +} + +static inline void hri_dmacchannel_clear_CHINTEN_TERR_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TERR; +} + +static inline void hri_dmacchannel_set_CHINTEN_TCMPL_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; +} + +static inline bool hri_dmacchannel_get_CHINTEN_TCMPL_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos; +} + +static inline void hri_dmacchannel_write_CHINTEN_TCMPL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; + } else { + ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; + } +} + +static inline void hri_dmacchannel_clear_CHINTEN_TCMPL_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; +} + +static inline void hri_dmacchannel_set_CHINTEN_SUSP_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP; +} + +static inline bool hri_dmacchannel_get_CHINTEN_SUSP_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos; +} + +static inline void hri_dmacchannel_write_CHINTEN_SUSP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; + } else { + ((DmacChannel *)hw)->CHINTENSET.reg = DMAC_CHINTENSET_SUSP; + } +} + +static inline void hri_dmacchannel_clear_CHINTEN_SUSP_bit(const void *const hw) +{ + ((DmacChannel *)hw)->CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; +} + +static inline void hri_dmacchannel_set_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) +{ + ((DmacChannel *)hw)->CHINTENSET.reg = mask; +} + +static inline hri_dmac_chintenset_reg_t hri_dmacchannel_get_CHINTEN_reg(const void *const hw, + hri_dmac_chintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chintenset_reg_t hri_dmacchannel_read_CHINTEN_reg(const void *const hw) +{ + return ((DmacChannel *)hw)->CHINTENSET.reg; +} + +static inline void hri_dmacchannel_write_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t data) +{ + ((DmacChannel *)hw)->CHINTENSET.reg = data; + ((DmacChannel *)hw)->CHINTENCLR.reg = ~data; +} + +static inline void hri_dmacchannel_clear_CHINTEN_reg(const void *const hw, hri_dmac_chintenset_reg_t mask) +{ + ((DmacChannel *)hw)->CHINTENCLR.reg = mask; +} + +static inline void hri_dmacchannel_set_CHCTRLA_SWRST_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_SWRST; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHCTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_SWRST) >> DMAC_CHCTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dmacchannel_set_CHCTRLA_ENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHCTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_ENABLE) >> DMAC_CHCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_ENABLE; + tmp |= value << DMAC_CHCTRLA_ENABLE_Pos; + ((DmacChannel *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLA_ENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLA_ENABLE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_set_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_RUNSTDBY) >> DMAC_CHCTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_RUNSTDBY; + tmp |= value << DMAC_CHCTRLA_RUNSTDBY_Pos; + ((DmacChannel *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLA_RUNSTDBY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_set_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_TRIGSRC_bf(const void *const hw, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGSRC(mask)) >> DMAC_CHCTRLA_TRIGSRC_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_TRIGSRC_Msk; + tmp |= DMAC_CHCTRLA_TRIGSRC(data); + ((DmacChannel *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLA_TRIGSRC_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_TRIGSRC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGSRC_Msk) >> DMAC_CHCTRLA_TRIGSRC_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_TRIGACT_bf(const void *const hw, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGACT(mask)) >> DMAC_CHCTRLA_TRIGACT_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_TRIGACT_Msk; + tmp |= DMAC_CHCTRLA_TRIGACT(data); + ((DmacChannel *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLA_TRIGACT_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_TRIGACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGACT_Msk) >> DMAC_CHCTRLA_TRIGACT_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_BURSTLEN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_BURSTLEN_bf(const void *const hw, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_BURSTLEN(mask)) >> DMAC_CHCTRLA_BURSTLEN_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_BURSTLEN_Msk; + tmp |= DMAC_CHCTRLA_BURSTLEN(data); + ((DmacChannel *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_BURSTLEN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLA_BURSTLEN_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_BURSTLEN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_BURSTLEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_BURSTLEN_Msk) >> DMAC_CHCTRLA_BURSTLEN_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= DMAC_CHCTRLA_THRESHOLD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_THRESHOLD_bf(const void *const hw, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_THRESHOLD(mask)) >> DMAC_CHCTRLA_THRESHOLD_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_THRESHOLD_Msk; + tmp |= DMAC_CHCTRLA_THRESHOLD(data); + ((DmacChannel *)hw)->CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg &= ~DMAC_CHCTRLA_THRESHOLD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLA_THRESHOLD_bf(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg ^= DMAC_CHCTRLA_THRESHOLD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_THRESHOLD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_THRESHOLD_Msk) >> DMAC_CHCTRLA_THRESHOLD_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_get_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLA_reg(const void *const hw, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLA.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmacchannel_read_CHCTRLA_reg(const void *const hw) +{ + return ((DmacChannel *)hw)->CHCTRLA.reg; +} + +static inline void hri_dmacchannel_set_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLB.reg |= DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_get_CHCTRLB_CMD_bf(const void *const hw, + hri_dmac_chctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_CMD(mask)) >> DMAC_CHCTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_CMD_Msk; + tmp |= DMAC_CHCTRLB_CMD(data); + ((DmacChannel *)hw)->CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLB.reg &= ~DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLB_CMD_bf(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLB.reg ^= DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_read_CHCTRLB_CMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_CMD_Msk) >> DMAC_CHCTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLB.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_get_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacchannel_write_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLB.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLB.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHCTRLB_reg(const void *const hw, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHCTRLB.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmacchannel_read_CHCTRLB_reg(const void *const hw) +{ + return ((DmacChannel *)hw)->CHCTRLB.reg; +} + +static inline void hri_dmacchannel_set_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHPRILVL.reg |= DMAC_CHPRILVL_PRILVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_get_CHPRILVL_PRILVL_bf(const void *const hw, + hri_dmac_chprilvl_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHPRILVL.reg; + tmp = (tmp & DMAC_CHPRILVL_PRILVL(mask)) >> DMAC_CHPRILVL_PRILVL_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHPRILVL.reg; + tmp &= ~DMAC_CHPRILVL_PRILVL_Msk; + tmp |= DMAC_CHPRILVL_PRILVL(data); + ((DmacChannel *)hw)->CHPRILVL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHPRILVL.reg &= ~DMAC_CHPRILVL_PRILVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHPRILVL_PRILVL_bf(const void *const hw, hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHPRILVL.reg ^= DMAC_CHPRILVL_PRILVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_read_CHPRILVL_PRILVL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHPRILVL.reg; + tmp = (tmp & DMAC_CHPRILVL_PRILVL_Msk) >> DMAC_CHPRILVL_PRILVL_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHPRILVL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_get_CHPRILVL_reg(const void *const hw, + hri_dmac_chprilvl_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHPRILVL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacchannel_write_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHPRILVL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHPRILVL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHPRILVL_reg(const void *const hw, hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHPRILVL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmacchannel_read_CHPRILVL_reg(const void *const hw) +{ + return ((DmacChannel *)hw)->CHPRILVL.reg; +} + +static inline void hri_dmacchannel_set_CHEVCTRL_EVIE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHEVCTRL_EVIE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVIE) >> DMAC_CHEVCTRL_EVIE_Pos; + return (bool)tmp; +} + +static inline void hri_dmacchannel_write_CHEVCTRL_EVIE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVIE; + tmp |= value << DMAC_CHEVCTRL_EVIE_Pos; + ((DmacChannel *)hw)->CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHEVCTRL_EVIE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHEVCTRL_EVIE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_set_CHEVCTRL_EVOE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHEVCTRL_EVOE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVOE) >> DMAC_CHEVCTRL_EVOE_Pos; + return (bool)tmp; +} + +static inline void hri_dmacchannel_write_CHEVCTRL_EVOE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVOE; + tmp |= value << DMAC_CHEVCTRL_EVOE_Pos; + ((DmacChannel *)hw)->CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHEVCTRL_EVOE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHEVCTRL_EVOE_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_set_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_get_CHEVCTRL_EVACT_bf(const void *const hw, + hri_dmac_chevctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVACT(mask)) >> DMAC_CHEVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVACT_Msk; + tmp |= DMAC_CHEVCTRL_EVACT(data); + ((DmacChannel *)hw)->CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHEVCTRL_EVACT_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_read_CHEVCTRL_EVACT_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVACT_Msk) >> DMAC_CHEVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_get_CHEVCTRL_EVOMODE_bf(const void *const hw, + hri_dmac_chevctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVOMODE(mask)) >> DMAC_CHEVCTRL_EVOMODE_Pos; + return tmp; +} + +static inline void hri_dmacchannel_write_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVOMODE_Msk; + tmp |= DMAC_CHEVCTRL_EVOMODE(data); + ((DmacChannel *)hw)->CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHEVCTRL_EVOMODE_bf(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_read_CHEVCTRL_EVOMODE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVOMODE_Msk) >> DMAC_CHEVCTRL_EVOMODE_Pos; + return tmp; +} + +static inline void hri_dmacchannel_set_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_get_CHEVCTRL_reg(const void *const hw, + hri_dmac_chevctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHEVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacchannel_write_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_clear_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmacchannel_toggle_CHEVCTRL_reg(const void *const hw, hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHEVCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmacchannel_read_CHEVCTRL_reg(const void *const hw) +{ + return ((DmacChannel *)hw)->CHEVCTRL.reg; +} + +static inline bool hri_dmacchannel_get_CHSTATUS_PEND_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_PEND) >> DMAC_CHSTATUS_PEND_Pos; +} + +static inline void hri_dmacchannel_clear_CHSTATUS_PEND_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHSTATUS_BUSY_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_BUSY) >> DMAC_CHSTATUS_BUSY_Pos; +} + +static inline void hri_dmacchannel_clear_CHSTATUS_BUSY_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHSTATUS_FERR_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_FERR) >> DMAC_CHSTATUS_FERR_Pos; +} + +static inline void hri_dmacchannel_clear_CHSTATUS_FERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmacchannel_get_CHSTATUS_CRCERR_bit(const void *const hw) +{ + return (((DmacChannel *)hw)->CHSTATUS.reg & DMAC_CHSTATUS_CRCERR) >> DMAC_CHSTATUS_CRCERR_Pos; +} + +static inline void hri_dmacchannel_clear_CHSTATUS_CRCERR_bit(const void *const hw) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHSTATUS.reg = DMAC_CHSTATUS_CRCERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chstatus_reg_t hri_dmacchannel_get_CHSTATUS_reg(const void *const hw, + hri_dmac_chstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((DmacChannel *)hw)->CHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmacchannel_clear_CHSTATUS_reg(const void *const hw, hri_dmac_chstatus_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((DmacChannel *)hw)->CHSTATUS.reg = mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chstatus_reg_t hri_dmacchannel_read_CHSTATUS_reg(const void *const hw) +{ + return ((DmacChannel *)hw)->CHSTATUS.reg; +} + +static inline bool hri_dmac_get_CHINTFLAG_TERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; +} + +static inline void hri_dmac_clear_CHINTFLAG_TERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; +} + +static inline bool hri_dmac_get_CHINTFLAG_TCMPL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; +} + +static inline void hri_dmac_clear_CHINTFLAG_TCMPL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; +} + +static inline bool hri_dmac_get_CHINTFLAG_SUSP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; +} + +static inline void hri_dmac_clear_CHINTFLAG_SUSP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; +} + +static inline bool hri_dmac_get_interrupt_TERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TERR) >> DMAC_CHINTFLAG_TERR_Pos; +} + +static inline void hri_dmac_clear_interrupt_TERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TERR; +} + +static inline bool hri_dmac_get_interrupt_TCMPL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_TCMPL) >> DMAC_CHINTFLAG_TCMPL_Pos; +} + +static inline void hri_dmac_clear_interrupt_TCMPL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_TCMPL; +} + +static inline bool hri_dmac_get_interrupt_SUSP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg & DMAC_CHINTFLAG_SUSP) >> DMAC_CHINTFLAG_SUSP_Pos; +} + +static inline void hri_dmac_clear_interrupt_SUSP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = DMAC_CHINTFLAG_SUSP; +} + +static inline hri_dmac_chintflag_reg_t hri_dmac_get_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chintflag_reg_t hri_dmac_read_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg; +} + +static inline void hri_dmac_clear_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chintflag_reg_t mask) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTFLAG.reg = mask; +} + +static inline void hri_dmac_set_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TERR; +} + +static inline bool hri_dmac_get_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg & DMAC_CHINTENSET_TERR) >> DMAC_CHINTENSET_TERR_Pos; +} + +static inline void hri_dmac_write_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TERR; + } else { + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TERR; + } +} + +static inline void hri_dmac_clear_CHINTEN_TERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TERR; +} + +static inline void hri_dmac_set_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; +} + +static inline bool hri_dmac_get_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg & DMAC_CHINTENSET_TCMPL) >> DMAC_CHINTENSET_TCMPL_Pos; +} + +static inline void hri_dmac_write_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; + } else { + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_TCMPL; + } +} + +static inline void hri_dmac_clear_CHINTEN_TCMPL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_TCMPL; +} + +static inline void hri_dmac_set_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_SUSP; +} + +static inline bool hri_dmac_get_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg & DMAC_CHINTENSET_SUSP) >> DMAC_CHINTENSET_SUSP_Pos; +} + +static inline void hri_dmac_write_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; + } else { + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = DMAC_CHINTENSET_SUSP; + } +} + +static inline void hri_dmac_clear_CHINTEN_SUSP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = DMAC_CHINTENSET_SUSP; +} + +static inline void hri_dmac_set_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chintenset_reg_t mask) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = mask; +} + +static inline hri_dmac_chintenset_reg_t hri_dmac_get_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dmac_chintenset_reg_t hri_dmac_read_CHINTEN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg; +} + +static inline void hri_dmac_write_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chintenset_reg_t data) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENSET.reg = data; + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = ~data; +} + +static inline void hri_dmac_clear_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chintenset_reg_t mask) +{ + ((Dmac *)hw)->Channel[submodule_index].CHINTENCLR.reg = mask; +} + +static inline void hri_dmac_set_CHCTRLA_SWRST_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_SWRST; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLA_SWRST_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_SWRST) >> DMAC_CHCTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_set_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_ENABLE) >> DMAC_CHCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_ENABLE; + tmp |= value << DMAC_CHCTRLA_ENABLE_Pos; + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_ENABLE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_RUNSTDBY) >> DMAC_CHCTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_RUNSTDBY; + tmp |= value << DMAC_CHCTRLA_RUNSTDBY_Pos; + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_RUNSTDBY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGSRC(mask)) >> DMAC_CHCTRLA_TRIGSRC_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_TRIGSRC_Msk; + tmp |= DMAC_CHCTRLA_TRIGSRC(data); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGSRC(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_TRIGSRC_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGSRC_Msk) >> DMAC_CHCTRLA_TRIGSRC_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGACT(mask)) >> DMAC_CHCTRLA_TRIGACT_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_TRIGACT_Msk; + tmp |= DMAC_CHCTRLA_TRIGACT(data); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_TRIGACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_TRIGACT_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_TRIGACT_Msk) >> DMAC_CHCTRLA_TRIGACT_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_BURSTLEN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_BURSTLEN(mask)) >> DMAC_CHCTRLA_BURSTLEN_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_BURSTLEN_Msk; + tmp |= DMAC_CHCTRLA_BURSTLEN(data); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_BURSTLEN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_BURSTLEN(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_BURSTLEN_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_BURSTLEN_Msk) >> DMAC_CHCTRLA_BURSTLEN_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= DMAC_CHCTRLA_THRESHOLD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_THRESHOLD(mask)) >> DMAC_CHCTRLA_THRESHOLD_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t data) +{ + uint32_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp &= ~DMAC_CHCTRLA_THRESHOLD_Msk; + tmp |= DMAC_CHCTRLA_THRESHOLD(data); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~DMAC_CHCTRLA_THRESHOLD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= DMAC_CHCTRLA_THRESHOLD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_THRESHOLD_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp = (tmp & DMAC_CHCTRLA_THRESHOLD_Msk) >> DMAC_CHCTRLA_THRESHOLD_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_get_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrla_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrla_reg_t hri_dmac_read_CHCTRLA_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Dmac *)hw)->Channel[submodule_index].CHCTRLA.reg; +} + +static inline void hri_dmac_set_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg |= DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_CMD(mask)) >> DMAC_CHCTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; + tmp &= ~DMAC_CHCTRLB_CMD_Msk; + tmp |= DMAC_CHCTRLB_CMD(data); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg &= ~DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg ^= DMAC_CHCTRLB_CMD(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_CMD_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; + tmp = (tmp & DMAC_CHCTRLB_CMD_Msk) >> DMAC_CHCTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_get_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chctrlb_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chctrlb_reg_t hri_dmac_read_CHCTRLB_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Dmac *)hw)->Channel[submodule_index].CHCTRLB.reg; +} + +static inline void hri_dmac_set_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg |= DMAC_CHPRILVL_PRILVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmac_get_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; + tmp = (tmp & DMAC_CHPRILVL_PRILVL(mask)) >> DMAC_CHPRILVL_PRILVL_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; + tmp &= ~DMAC_CHPRILVL_PRILVL_Msk; + tmp |= DMAC_CHPRILVL_PRILVL(data); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg &= ~DMAC_CHPRILVL_PRILVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg ^= DMAC_CHPRILVL_PRILVL(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmac_read_CHPRILVL_PRILVL_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; + tmp = (tmp & DMAC_CHPRILVL_PRILVL_Msk) >> DMAC_CHPRILVL_PRILVL_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmac_get_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHPRILVL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chprilvl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chprilvl_reg_t hri_dmac_read_CHPRILVL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Dmac *)hw)->Channel[submodule_index].CHPRILVL.reg; +} + +static inline void hri_dmac_set_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVIE) >> DMAC_CHEVCTRL_EVIE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVIE; + tmp |= value << DMAC_CHEVCTRL_EVIE_Pos; + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHEVCTRL_EVIE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVIE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVOE) >> DMAC_CHEVCTRL_EVOE_Pos; + return (bool)tmp; +} + +static inline void hri_dmac_write_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVOE; + tmp |= value << DMAC_CHEVCTRL_EVOE_Pos; + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHEVCTRL_EVOE_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOE; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_set_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmac_get_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVACT(mask)) >> DMAC_CHEVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVACT_Msk; + tmp |= DMAC_CHEVCTRL_EVACT(data); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVACT(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmac_read_CHEVCTRL_EVACT_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVACT_Msk) >> DMAC_CHEVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= DMAC_CHEVCTRL_EVOMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmac_get_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVOMODE(mask)) >> DMAC_CHEVCTRL_EVOMODE_Pos; + return tmp; +} + +static inline void hri_dmac_write_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t data) +{ + uint8_t tmp; + DMAC_CRITICAL_SECTION_ENTER(); + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp &= ~DMAC_CHEVCTRL_EVOMODE_Msk; + tmp |= DMAC_CHEVCTRL_EVOMODE(data); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = tmp; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~DMAC_CHEVCTRL_EVOMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= DMAC_CHEVCTRL_EVOMODE(mask); + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmac_read_CHEVCTRL_EVOMODE_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp = (tmp & DMAC_CHEVCTRL_EVOMODE_Msk) >> DMAC_CHEVCTRL_EVOMODE_Pos; + return tmp; +} + +static inline void hri_dmac_set_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg |= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmac_get_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_write_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t data) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg = data; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_clear_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg &= ~mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dmac_toggle_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chevctrl_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg ^= mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chevctrl_reg_t hri_dmac_read_CHEVCTRL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Dmac *)hw)->Channel[submodule_index].CHEVCTRL.reg; +} + +static inline bool hri_dmac_get_CHSTATUS_PEND_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_PEND) >> DMAC_CHSTATUS_PEND_Pos; +} + +static inline void hri_dmac_clear_CHSTATUS_PEND_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_PEND; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHSTATUS_BUSY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_BUSY) >> DMAC_CHSTATUS_BUSY_Pos; +} + +static inline void hri_dmac_clear_CHSTATUS_BUSY_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_BUSY; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHSTATUS_FERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_FERR) >> DMAC_CHSTATUS_FERR_Pos; +} + +static inline void hri_dmac_clear_CHSTATUS_FERR_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_FERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dmac_get_CHSTATUS_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg & DMAC_CHSTATUS_CRCERR) >> DMAC_CHSTATUS_CRCERR_Pos; +} + +static inline void hri_dmac_clear_CHSTATUS_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = DMAC_CHSTATUS_CRCERR; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chstatus_reg_t hri_dmac_get_CHSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dmac_clear_CHSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_dmac_chstatus_reg_t mask) +{ + DMAC_CRITICAL_SECTION_ENTER(); + ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg = mask; + DMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dmac_chstatus_reg_t hri_dmac_read_CHSTATUS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Dmac *)hw)->Channel[submodule_index].CHSTATUS.reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_dmacdescriptor_set_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_set_DSTADDR_reg(a, b) +#define hri_dmacdescriptor_get_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_get_DSTADDR_reg(a, b) +#define hri_dmacdescriptor_write_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_write_DSTADDR_reg(a, b) +#define hri_dmacdescriptor_clear_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_clear_DSTADDR_reg(a, b) +#define hri_dmacdescriptor_toggle_DSTADDR_CRC_reg(a, b) hri_dmacdescriptor_toggle_DSTADDR_reg(a, b) +#define hri_dmacdescriptor_read_DSTADDR_CRC_reg(a) hri_dmacdescriptor_read_DSTADDR_reg(a) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_DMAC_E54_H_INCLUDED */ +#endif /* _SAME54_DMAC_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_dsu_e54.h b/software/firmware/oracle_same54n19a/hri/hri_dsu_e54.h new file mode 100644 index 00000000..b192276f --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_dsu_e54.h @@ -0,0 +1,1256 @@ +/** + * \file + * + * \brief SAM DSU + * + * Copyright (c) 2017-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_DSU_COMPONENT_ +#ifndef _HRI_DSU_E54_H_INCLUDED_ +#define _HRI_DSU_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_DSU_CRITICAL_SECTIONS) +#define DSU_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define DSU_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define DSU_CRITICAL_SECTION_ENTER() +#define DSU_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_dsu_addr_reg_t; +typedef uint32_t hri_dsu_cfg_reg_t; +typedef uint32_t hri_dsu_cid0_reg_t; +typedef uint32_t hri_dsu_cid1_reg_t; +typedef uint32_t hri_dsu_cid2_reg_t; +typedef uint32_t hri_dsu_cid3_reg_t; +typedef uint32_t hri_dsu_data_reg_t; +typedef uint32_t hri_dsu_dcc_reg_t; +typedef uint32_t hri_dsu_did_reg_t; +typedef uint32_t hri_dsu_end_reg_t; +typedef uint32_t hri_dsu_entry0_reg_t; +typedef uint32_t hri_dsu_entry1_reg_t; +typedef uint32_t hri_dsu_length_reg_t; +typedef uint32_t hri_dsu_memtype_reg_t; +typedef uint32_t hri_dsu_pid0_reg_t; +typedef uint32_t hri_dsu_pid1_reg_t; +typedef uint32_t hri_dsu_pid2_reg_t; +typedef uint32_t hri_dsu_pid3_reg_t; +typedef uint32_t hri_dsu_pid4_reg_t; +typedef uint32_t hri_dsu_pid5_reg_t; +typedef uint32_t hri_dsu_pid6_reg_t; +typedef uint32_t hri_dsu_pid7_reg_t; +typedef uint8_t hri_dsu_ctrl_reg_t; +typedef uint8_t hri_dsu_statusa_reg_t; +typedef uint8_t hri_dsu_statusb_reg_t; + +static inline bool hri_dsu_get_STATUSB_PROT_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_PROT) >> DSU_STATUSB_PROT_Pos; +} + +static inline bool hri_dsu_get_STATUSB_DBGPRES_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DBGPRES) >> DSU_STATUSB_DBGPRES_Pos; +} + +static inline bool hri_dsu_get_STATUSB_DCCD0_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD0) >> DSU_STATUSB_DCCD0_Pos; +} + +static inline bool hri_dsu_get_STATUSB_DCCD1_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_DCCD1) >> DSU_STATUSB_DCCD1_Pos; +} + +static inline bool hri_dsu_get_STATUSB_HPE_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_HPE) >> DSU_STATUSB_HPE_Pos; +} + +static inline bool hri_dsu_get_STATUSB_CELCK_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSB.reg & DSU_STATUSB_CELCK) >> DSU_STATUSB_CELCK_Pos; +} + +static inline hri_dsu_statusb_reg_t hri_dsu_get_STATUSB_reg(const void *const hw, hri_dsu_statusb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dsu *)hw)->STATUSB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_statusb_reg_t hri_dsu_read_STATUSB_reg(const void *const hw) +{ + return ((Dsu *)hw)->STATUSB.reg; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_DEVSEL_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL(mask)) >> DSU_DID_DEVSEL_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_DEVSEL_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DEVSEL_Msk) >> DSU_DID_DEVSEL_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_REVISION_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION(mask)) >> DSU_DID_REVISION_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_REVISION_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_REVISION_Msk) >> DSU_DID_REVISION_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_DIE_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DIE(mask)) >> DSU_DID_DIE_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_DIE_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_DIE_Msk) >> DSU_DID_DIE_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_SERIES_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES(mask)) >> DSU_DID_SERIES_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_SERIES_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_SERIES_Msk) >> DSU_DID_SERIES_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_FAMILY_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY(mask)) >> DSU_DID_FAMILY_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_FAMILY_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_FAMILY_Msk) >> DSU_DID_FAMILY_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_PROCESSOR_bf(const void *const hw, hri_dsu_did_reg_t mask) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR(mask)) >> DSU_DID_PROCESSOR_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_PROCESSOR_bf(const void *const hw) +{ + return (((Dsu *)hw)->DID.reg & DSU_DID_PROCESSOR_Msk) >> DSU_DID_PROCESSOR_Pos; +} + +static inline hri_dsu_did_reg_t hri_dsu_get_DID_reg(const void *const hw, hri_dsu_did_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DID.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_did_reg_t hri_dsu_read_DID_reg(const void *const hw) +{ + return ((Dsu *)hw)->DID.reg; +} + +static inline bool hri_dsu_get_ENTRY0_EPRES_bit(const void *const hw) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_EPRES) >> DSU_ENTRY0_EPRES_Pos; +} + +static inline bool hri_dsu_get_ENTRY0_FMT_bit(const void *const hw) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_FMT) >> DSU_ENTRY0_FMT_Pos; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_ADDOFF_bf(const void *const hw, hri_dsu_entry0_reg_t mask) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF(mask)) >> DSU_ENTRY0_ADDOFF_Pos; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_ADDOFF_bf(const void *const hw) +{ + return (((Dsu *)hw)->ENTRY0.reg & DSU_ENTRY0_ADDOFF_Msk) >> DSU_ENTRY0_ADDOFF_Pos; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_get_ENTRY0_reg(const void *const hw, hri_dsu_entry0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ENTRY0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_entry0_reg_t hri_dsu_read_ENTRY0_reg(const void *const hw) +{ + return ((Dsu *)hw)->ENTRY0.reg; +} + +static inline hri_dsu_entry1_reg_t hri_dsu_get_ENTRY1_reg(const void *const hw, hri_dsu_entry1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ENTRY1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_entry1_reg_t hri_dsu_read_ENTRY1_reg(const void *const hw) +{ + return ((Dsu *)hw)->ENTRY1.reg; +} + +static inline hri_dsu_end_reg_t hri_dsu_get_END_END_bf(const void *const hw, hri_dsu_end_reg_t mask) +{ + return (((Dsu *)hw)->END.reg & DSU_END_END(mask)) >> DSU_END_END_Pos; +} + +static inline hri_dsu_end_reg_t hri_dsu_read_END_END_bf(const void *const hw) +{ + return (((Dsu *)hw)->END.reg & DSU_END_END_Msk) >> DSU_END_END_Pos; +} + +static inline hri_dsu_end_reg_t hri_dsu_get_END_reg(const void *const hw, hri_dsu_end_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->END.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_end_reg_t hri_dsu_read_END_reg(const void *const hw) +{ + return ((Dsu *)hw)->END.reg; +} + +static inline bool hri_dsu_get_MEMTYPE_SMEMP_bit(const void *const hw) +{ + return (((Dsu *)hw)->MEMTYPE.reg & DSU_MEMTYPE_SMEMP) >> DSU_MEMTYPE_SMEMP_Pos; +} + +static inline hri_dsu_memtype_reg_t hri_dsu_get_MEMTYPE_reg(const void *const hw, hri_dsu_memtype_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->MEMTYPE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_memtype_reg_t hri_dsu_read_MEMTYPE_reg(const void *const hw) +{ + return ((Dsu *)hw)->MEMTYPE.reg; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_JEPCC_bf(const void *const hw, hri_dsu_pid4_reg_t mask) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC(mask)) >> DSU_PID4_JEPCC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_JEPCC_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_JEPCC_Msk) >> DSU_PID4_JEPCC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_FKBC_bf(const void *const hw, hri_dsu_pid4_reg_t mask) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC(mask)) >> DSU_PID4_FKBC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_FKBC_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID4.reg & DSU_PID4_FKBC_Msk) >> DSU_PID4_FKBC_Pos; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_get_PID4_reg(const void *const hw, hri_dsu_pid4_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID4.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid4_reg_t hri_dsu_read_PID4_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID4.reg; +} + +static inline hri_dsu_pid5_reg_t hri_dsu_get_PID5_reg(const void *const hw, hri_dsu_pid5_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID5.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid5_reg_t hri_dsu_read_PID5_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID5.reg; +} + +static inline hri_dsu_pid6_reg_t hri_dsu_get_PID6_reg(const void *const hw, hri_dsu_pid6_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID6.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid6_reg_t hri_dsu_read_PID6_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID6.reg; +} + +static inline hri_dsu_pid7_reg_t hri_dsu_get_PID7_reg(const void *const hw, hri_dsu_pid7_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID7.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid7_reg_t hri_dsu_read_PID7_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID7.reg; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_PARTNBL_bf(const void *const hw, hri_dsu_pid0_reg_t mask) +{ + return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL(mask)) >> DSU_PID0_PARTNBL_Pos; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_PARTNBL_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID0.reg & DSU_PID0_PARTNBL_Msk) >> DSU_PID0_PARTNBL_Pos; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_get_PID0_reg(const void *const hw, hri_dsu_pid0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid0_reg_t hri_dsu_read_PID0_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID0.reg; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_PARTNBH_bf(const void *const hw, hri_dsu_pid1_reg_t mask) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH(mask)) >> DSU_PID1_PARTNBH_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_PARTNBH_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_PARTNBH_Msk) >> DSU_PID1_PARTNBH_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_JEPIDCL_bf(const void *const hw, hri_dsu_pid1_reg_t mask) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL(mask)) >> DSU_PID1_JEPIDCL_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_JEPIDCL_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID1.reg & DSU_PID1_JEPIDCL_Msk) >> DSU_PID1_JEPIDCL_Pos; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_get_PID1_reg(const void *const hw, hri_dsu_pid1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid1_reg_t hri_dsu_read_PID1_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID1.reg; +} + +static inline bool hri_dsu_get_PID2_JEPU_bit(const void *const hw) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPU) >> DSU_PID2_JEPU_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_JEPIDCH_bf(const void *const hw, hri_dsu_pid2_reg_t mask) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH(mask)) >> DSU_PID2_JEPIDCH_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_JEPIDCH_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_JEPIDCH_Msk) >> DSU_PID2_JEPIDCH_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_REVISION_bf(const void *const hw, hri_dsu_pid2_reg_t mask) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION(mask)) >> DSU_PID2_REVISION_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_REVISION_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID2.reg & DSU_PID2_REVISION_Msk) >> DSU_PID2_REVISION_Pos; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_get_PID2_reg(const void *const hw, hri_dsu_pid2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID2.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid2_reg_t hri_dsu_read_PID2_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID2.reg; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_CUSMOD_bf(const void *const hw, hri_dsu_pid3_reg_t mask) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD(mask)) >> DSU_PID3_CUSMOD_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_CUSMOD_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_CUSMOD_Msk) >> DSU_PID3_CUSMOD_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_REVAND_bf(const void *const hw, hri_dsu_pid3_reg_t mask) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND(mask)) >> DSU_PID3_REVAND_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_REVAND_bf(const void *const hw) +{ + return (((Dsu *)hw)->PID3.reg & DSU_PID3_REVAND_Msk) >> DSU_PID3_REVAND_Pos; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_get_PID3_reg(const void *const hw, hri_dsu_pid3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->PID3.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_pid3_reg_t hri_dsu_read_PID3_reg(const void *const hw) +{ + return ((Dsu *)hw)->PID3.reg; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_PREAMBLEB0_bf(const void *const hw, hri_dsu_cid0_reg_t mask) +{ + return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0(mask)) >> DSU_CID0_PREAMBLEB0_Pos; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_PREAMBLEB0_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID0.reg & DSU_CID0_PREAMBLEB0_Msk) >> DSU_CID0_PREAMBLEB0_Pos; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_get_CID0_reg(const void *const hw, hri_dsu_cid0_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID0.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid0_reg_t hri_dsu_read_CID0_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID0.reg; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_PREAMBLE_bf(const void *const hw, hri_dsu_cid1_reg_t mask) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE(mask)) >> DSU_CID1_PREAMBLE_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_PREAMBLE_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_PREAMBLE_Msk) >> DSU_CID1_PREAMBLE_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_CCLASS_bf(const void *const hw, hri_dsu_cid1_reg_t mask) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS(mask)) >> DSU_CID1_CCLASS_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_CCLASS_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID1.reg & DSU_CID1_CCLASS_Msk) >> DSU_CID1_CCLASS_Pos; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_get_CID1_reg(const void *const hw, hri_dsu_cid1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID1.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid1_reg_t hri_dsu_read_CID1_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID1.reg; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_PREAMBLEB2_bf(const void *const hw, hri_dsu_cid2_reg_t mask) +{ + return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2(mask)) >> DSU_CID2_PREAMBLEB2_Pos; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_PREAMBLEB2_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID2.reg & DSU_CID2_PREAMBLEB2_Msk) >> DSU_CID2_PREAMBLEB2_Pos; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_get_CID2_reg(const void *const hw, hri_dsu_cid2_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID2.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid2_reg_t hri_dsu_read_CID2_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID2.reg; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_PREAMBLEB3_bf(const void *const hw, hri_dsu_cid3_reg_t mask) +{ + return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3(mask)) >> DSU_CID3_PREAMBLEB3_Pos; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_PREAMBLEB3_bf(const void *const hw) +{ + return (((Dsu *)hw)->CID3.reg & DSU_CID3_PREAMBLEB3_Msk) >> DSU_CID3_PREAMBLEB3_Pos; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_get_CID3_reg(const void *const hw, hri_dsu_cid3_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CID3.reg; + tmp &= mask; + return tmp; +} + +static inline hri_dsu_cid3_reg_t hri_dsu_read_CID3_reg(const void *const hw) +{ + return ((Dsu *)hw)->CID3.reg; +} + +static inline void hri_dsu_set_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_AMOD(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_AMOD(mask)) >> DSU_ADDR_AMOD_Pos; + return tmp; +} + +static inline void hri_dsu_write_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->ADDR.reg; + tmp &= ~DSU_ADDR_AMOD_Msk; + tmp |= DSU_ADDR_AMOD(data); + ((Dsu *)hw)->ADDR.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_AMOD(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_ADDR_AMOD_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_AMOD(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_AMOD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_AMOD_Msk) >> DSU_ADDR_AMOD_Pos; + return tmp; +} + +static inline void hri_dsu_set_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg |= DSU_ADDR_ADDR(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_ADDR(mask)) >> DSU_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_dsu_write_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->ADDR.reg; + tmp &= ~DSU_ADDR_ADDR_Msk; + tmp |= DSU_ADDR_ADDR(data); + ((Dsu *)hw)->ADDR.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg &= ~DSU_ADDR_ADDR(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_ADDR_ADDR_bf(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg ^= DSU_ADDR_ADDR(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp = (tmp & DSU_ADDR_ADDR_Msk) >> DSU_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_dsu_set_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_get_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_ADDR_reg(const void *const hw, hri_dsu_addr_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->ADDR.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_addr_reg_t hri_dsu_read_ADDR_reg(const void *const hw) +{ + return ((Dsu *)hw)->ADDR.reg; +} + +static inline void hri_dsu_set_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg |= DSU_LENGTH_LENGTH(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp = (tmp & DSU_LENGTH_LENGTH(mask)) >> DSU_LENGTH_LENGTH_Pos; + return tmp; +} + +static inline void hri_dsu_write_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp &= ~DSU_LENGTH_LENGTH_Msk; + tmp |= DSU_LENGTH_LENGTH(data); + ((Dsu *)hw)->LENGTH.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg &= ~DSU_LENGTH_LENGTH(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_LENGTH_LENGTH_bf(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg ^= DSU_LENGTH_LENGTH(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_LENGTH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp = (tmp & DSU_LENGTH_LENGTH_Msk) >> DSU_LENGTH_LENGTH_Pos; + return tmp; +} + +static inline void hri_dsu_set_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_get_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->LENGTH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_LENGTH_reg(const void *const hw, hri_dsu_length_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->LENGTH.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_length_reg_t hri_dsu_read_LENGTH_reg(const void *const hw) +{ + return ((Dsu *)hw)->LENGTH.reg; +} + +static inline void hri_dsu_set_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg |= DSU_DATA_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_get_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DATA.reg; + tmp = (tmp & DSU_DATA_DATA(mask)) >> DSU_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_write_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->DATA.reg; + tmp &= ~DSU_DATA_DATA_Msk; + tmp |= DSU_DATA_DATA(data); + ((Dsu *)hw)->DATA.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg &= ~DSU_DATA_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DATA_DATA_bf(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg ^= DSU_DATA_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_read_DATA_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DATA.reg; + tmp = (tmp & DSU_DATA_DATA_Msk) >> DSU_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_set_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_get_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_DATA_reg(const void *const hw, hri_dsu_data_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DATA_reg(const void *const hw, hri_dsu_data_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DATA.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_data_reg_t hri_dsu_read_DATA_reg(const void *const hw) +{ + return ((Dsu *)hw)->DATA.reg; +} + +static inline void hri_dsu_set_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg |= DSU_DCC_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp = (tmp & DSU_DCC_DATA(mask)) >> DSU_DCC_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_write_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp &= ~DSU_DCC_DATA_Msk; + tmp |= DSU_DCC_DATA(data); + ((Dsu *)hw)->DCC[index].reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg &= ~DSU_DCC_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DCC_DATA_bf(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg ^= DSU_DCC_DATA(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_DATA_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp = (tmp & DSU_DCC_DATA_Msk) >> DSU_DCC_DATA_Pos; + return tmp; +} + +static inline void hri_dsu_set_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_get_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->DCC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_DCC_reg(const void *const hw, uint8_t index, hri_dsu_dcc_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->DCC[index].reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_dcc_reg_t hri_dsu_read_DCC_reg(const void *const hw, uint8_t index) +{ + return ((Dsu *)hw)->DCC[index].reg; +} + +static inline void hri_dsu_set_CFG_ETBRAMEN_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg |= DSU_CFG_ETBRAMEN; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_CFG_ETBRAMEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CFG.reg; + tmp = (tmp & DSU_CFG_ETBRAMEN) >> DSU_CFG_ETBRAMEN_Pos; + return (bool)tmp; +} + +static inline void hri_dsu_write_CFG_ETBRAMEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->CFG.reg; + tmp &= ~DSU_CFG_ETBRAMEN; + tmp |= value << DSU_CFG_ETBRAMEN_Pos; + ((Dsu *)hw)->CFG.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_CFG_ETBRAMEN_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg &= ~DSU_CFG_ETBRAMEN; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_CFG_ETBRAMEN_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg ^= DSU_CFG_ETBRAMEN; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_set_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg |= DSU_CFG_LQOS(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CFG.reg; + tmp = (tmp & DSU_CFG_LQOS(mask)) >> DSU_CFG_LQOS_Pos; + return tmp; +} + +static inline void hri_dsu_write_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->CFG.reg; + tmp &= ~DSU_CFG_LQOS_Msk; + tmp |= DSU_CFG_LQOS(data); + ((Dsu *)hw)->CFG.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg &= ~DSU_CFG_LQOS(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_CFG_LQOS_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg ^= DSU_CFG_LQOS(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_LQOS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CFG.reg; + tmp = (tmp & DSU_CFG_LQOS_Msk) >> DSU_CFG_LQOS_Pos; + return tmp; +} + +static inline void hri_dsu_set_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg |= DSU_CFG_DCCDMALEVEL(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CFG.reg; + tmp = (tmp & DSU_CFG_DCCDMALEVEL(mask)) >> DSU_CFG_DCCDMALEVEL_Pos; + return tmp; +} + +static inline void hri_dsu_write_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t data) +{ + uint32_t tmp; + DSU_CRITICAL_SECTION_ENTER(); + tmp = ((Dsu *)hw)->CFG.reg; + tmp &= ~DSU_CFG_DCCDMALEVEL_Msk; + tmp |= DSU_CFG_DCCDMALEVEL(data); + ((Dsu *)hw)->CFG.reg = tmp; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg &= ~DSU_CFG_DCCDMALEVEL(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_CFG_DCCDMALEVEL_bf(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg ^= DSU_CFG_DCCDMALEVEL(mask); + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_DCCDMALEVEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CFG.reg; + tmp = (tmp & DSU_CFG_DCCDMALEVEL_Msk) >> DSU_CFG_DCCDMALEVEL_Pos; + return tmp; +} + +static inline void hri_dsu_set_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg |= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_cfg_reg_t hri_dsu_get_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Dsu *)hw)->CFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_write_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_clear_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg &= ~mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_dsu_toggle_CFG_reg(const void *const hw, hri_dsu_cfg_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CFG.reg ^= mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_cfg_reg_t hri_dsu_read_CFG_reg(const void *const hw) +{ + return ((Dsu *)hw)->CFG.reg; +} + +static inline bool hri_dsu_get_STATUSA_DONE_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_DONE) >> DSU_STATUSA_DONE_Pos; +} + +static inline void hri_dsu_clear_STATUSA_DONE_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_DONE; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_CRSTEXT_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_CRSTEXT) >> DSU_STATUSA_CRSTEXT_Pos; +} + +static inline void hri_dsu_clear_STATUSA_CRSTEXT_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_CRSTEXT; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_BERR_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_BERR) >> DSU_STATUSA_BERR_Pos; +} + +static inline void hri_dsu_clear_STATUSA_BERR_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_BERR; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_FAIL_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_FAIL) >> DSU_STATUSA_FAIL_Pos; +} + +static inline void hri_dsu_clear_STATUSA_FAIL_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_FAIL; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_dsu_get_STATUSA_PERR_bit(const void *const hw) +{ + return (((Dsu *)hw)->STATUSA.reg & DSU_STATUSA_PERR) >> DSU_STATUSA_PERR_Pos; +} + +static inline void hri_dsu_clear_STATUSA_PERR_bit(const void *const hw) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = DSU_STATUSA_PERR; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_statusa_reg_t hri_dsu_get_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask) +{ + uint8_t tmp; + tmp = ((Dsu *)hw)->STATUSA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_dsu_clear_STATUSA_reg(const void *const hw, hri_dsu_statusa_reg_t mask) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->STATUSA.reg = mask; + DSU_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_dsu_statusa_reg_t hri_dsu_read_STATUSA_reg(const void *const hw) +{ + return ((Dsu *)hw)->STATUSA.reg; +} + +static inline void hri_dsu_write_CTRL_reg(const void *const hw, hri_dsu_ctrl_reg_t data) +{ + DSU_CRITICAL_SECTION_ENTER(); + ((Dsu *)hw)->CTRL.reg = data; + DSU_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_DSU_E54_H_INCLUDED */ +#endif /* _SAME54_DSU_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_e54.h b/software/firmware/oracle_same54n19a/hri/hri_e54.h new file mode 100644 index 00000000..46e77ca0 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_e54.h @@ -0,0 +1,76 @@ +/** + * \file + * + * \brief SAM E54 HRI top-level header file + * + * Copyright (c) 2016-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + */ + +#ifndef _HRI_E54_H_INCLUDED_ +#define _HRI_E54_H_INCLUDED_ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#endif /* _HRI_E54_H_INCLUDED_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_eic_e54.h b/software/firmware/oracle_same54n19a/hri/hri_eic_e54.h new file mode 100644 index 00000000..f86e452c --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_eic_e54.h @@ -0,0 +1,1838 @@ +/** + * \file + * + * \brief SAM EIC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_EIC_COMPONENT_ +#ifndef _HRI_EIC_E54_H_INCLUDED_ +#define _HRI_EIC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_EIC_CRITICAL_SECTIONS) +#define EIC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define EIC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define EIC_CRITICAL_SECTION_ENTER() +#define EIC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_eic_nmiflag_reg_t; +typedef uint32_t hri_eic_asynch_reg_t; +typedef uint32_t hri_eic_config_reg_t; +typedef uint32_t hri_eic_debouncen_reg_t; +typedef uint32_t hri_eic_dprescaler_reg_t; +typedef uint32_t hri_eic_evctrl_reg_t; +typedef uint32_t hri_eic_intenset_reg_t; +typedef uint32_t hri_eic_intflag_reg_t; +typedef uint32_t hri_eic_pinstate_reg_t; +typedef uint32_t hri_eic_syncbusy_reg_t; +typedef uint8_t hri_eic_ctrla_reg_t; +typedef uint8_t hri_eic_nmictrl_reg_t; + +static inline void hri_eic_wait_for_sync(const void *const hw, hri_eic_syncbusy_reg_t reg) +{ + while (((Eic *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_eic_is_syncing(const void *const hw, hri_eic_syncbusy_reg_t reg) +{ + return ((Eic *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_eic_get_NMIFLAG_NMI_bit(const void *const hw) +{ + return (((Eic *)hw)->NMIFLAG.reg & EIC_NMIFLAG_NMI) >> EIC_NMIFLAG_NMI_Pos; +} + +static inline void hri_eic_clear_NMIFLAG_NMI_bit(const void *const hw) +{ + ((Eic *)hw)->NMIFLAG.reg = EIC_NMIFLAG_NMI; +} + +static inline hri_eic_nmiflag_reg_t hri_eic_get_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Eic *)hw)->NMIFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_nmiflag_reg_t hri_eic_read_NMIFLAG_reg(const void *const hw) +{ + return ((Eic *)hw)->NMIFLAG.reg; +} + +static inline void hri_eic_clear_NMIFLAG_reg(const void *const hw, hri_eic_nmiflag_reg_t mask) +{ + ((Eic *)hw)->NMIFLAG.reg = mask; +} + +static inline hri_eic_intflag_reg_t hri_eic_get_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_intflag_reg_t hri_eic_read_INTFLAG_reg(const void *const hw) +{ + return ((Eic *)hw)->INTFLAG.reg; +} + +static inline void hri_eic_clear_INTFLAG_reg(const void *const hw, hri_eic_intflag_reg_t mask) +{ + ((Eic *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_eic_set_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(mask); +} + +static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTENSET.reg; + tmp = (tmp & EIC_INTENSET_EXTINT(mask)) >> EIC_INTENSET_EXTINT_Pos; + return tmp; +} + +static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_EXTINT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTENSET.reg; + tmp = (tmp & EIC_INTENSET_EXTINT_Msk) >> EIC_INTENSET_EXTINT_Pos; + return tmp; +} + +static inline void hri_eic_write_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t data) +{ + ((Eic *)hw)->INTENSET.reg = EIC_INTENSET_EXTINT(data); + ((Eic *)hw)->INTENCLR.reg = ~EIC_INTENSET_EXTINT(data); +} + +static inline void hri_eic_clear_INTEN_EXTINT_bf(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENCLR.reg = EIC_INTENSET_EXTINT(mask); +} + +static inline void hri_eic_set_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENSET.reg = mask; +} + +static inline hri_eic_intenset_reg_t hri_eic_get_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_intenset_reg_t hri_eic_read_INTEN_reg(const void *const hw) +{ + return ((Eic *)hw)->INTENSET.reg; +} + +static inline void hri_eic_write_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t data) +{ + ((Eic *)hw)->INTENSET.reg = data; + ((Eic *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_eic_clear_INTEN_reg(const void *const hw, hri_eic_intenset_reg_t mask) +{ + ((Eic *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_eic_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_SWRST) >> EIC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_eic_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Eic *)hw)->SYNCBUSY.reg & EIC_SYNCBUSY_ENABLE) >> EIC_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_eic_syncbusy_reg_t hri_eic_get_SYNCBUSY_reg(const void *const hw, hri_eic_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_syncbusy_reg_t hri_eic_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Eic *)hw)->SYNCBUSY.reg; +} + +static inline hri_eic_pinstate_reg_t hri_eic_get_PINSTATE_PINSTATE_bf(const void *const hw, hri_eic_pinstate_reg_t mask) +{ + return (((Eic *)hw)->PINSTATE.reg & EIC_PINSTATE_PINSTATE(mask)) >> EIC_PINSTATE_PINSTATE_Pos; +} + +static inline hri_eic_pinstate_reg_t hri_eic_read_PINSTATE_PINSTATE_bf(const void *const hw) +{ + return (((Eic *)hw)->PINSTATE.reg & EIC_PINSTATE_PINSTATE_Msk) >> EIC_PINSTATE_PINSTATE_Pos; +} + +static inline hri_eic_pinstate_reg_t hri_eic_get_PINSTATE_reg(const void *const hw, hri_eic_pinstate_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->PINSTATE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_eic_pinstate_reg_t hri_eic_read_PINSTATE_reg(const void *const hw) +{ + return ((Eic *)hw)->PINSTATE.reg; +} + +static inline void hri_eic_set_CTRLA_SWRST_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_SWRST; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp = (tmp & EIC_CTRLA_SWRST) >> EIC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_eic_set_CTRLA_ENABLE_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_ENABLE; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp = (tmp & EIC_CTRLA_ENABLE) >> EIC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp &= ~EIC_CTRLA_ENABLE; + tmp |= value << EIC_CTRLA_ENABLE_Pos; + ((Eic *)hw)->CTRLA.reg = tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_ENABLE; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_ENABLE; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_SWRST | EIC_SYNCBUSY_ENABLE); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CTRLA_CKSEL_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= EIC_CTRLA_CKSEL; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CTRLA_CKSEL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->CTRLA.reg; + tmp = (tmp & EIC_CTRLA_CKSEL) >> EIC_CTRLA_CKSEL_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CTRLA_CKSEL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp &= ~EIC_CTRLA_CKSEL; + tmp |= value << EIC_CTRLA_CKSEL_Pos; + ((Eic *)hw)->CTRLA.reg = tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CTRLA_CKSEL_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg &= ~EIC_CTRLA_CKSEL; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CTRLA_CKSEL_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg ^= EIC_CTRLA_CKSEL; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg |= mask; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_ctrla_reg_t hri_eic_get_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + tmp = ((Eic *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg = data; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg &= ~mask; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CTRLA_reg(const void *const hw, hri_eic_ctrla_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CTRLA.reg ^= mask; + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_ctrla_reg_t hri_eic_read_CTRLA_reg(const void *const hw) +{ + hri_eic_wait_for_sync(hw, EIC_SYNCBUSY_MASK); + return ((Eic *)hw)->CTRLA.reg; +} + +static inline void hri_eic_set_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIFILTEN; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMIFILTEN) >> EIC_NMICTRL_NMIFILTEN_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_NMICTRL_NMIFILTEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= ~EIC_NMICTRL_NMIFILTEN; + tmp |= value << EIC_NMICTRL_NMIFILTEN_Pos; + ((Eic *)hw)->NMICTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIFILTEN; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_NMIFILTEN_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIFILTEN; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMIASYNCH; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMIASYNCH) >> EIC_NMICTRL_NMIASYNCH_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_NMICTRL_NMIASYNCH_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= ~EIC_NMICTRL_NMIASYNCH; + tmp |= value << EIC_NMICTRL_NMIASYNCH_Pos; + ((Eic *)hw)->NMICTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMIASYNCH; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_NMIASYNCH_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMIASYNCH; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= EIC_NMICTRL_NMISENSE(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMISENSE(mask)) >> EIC_NMICTRL_NMISENSE_Pos; + return tmp; +} + +static inline void hri_eic_write_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t data) +{ + uint8_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= ~EIC_NMICTRL_NMISENSE_Msk; + tmp |= EIC_NMICTRL_NMISENSE(data); + ((Eic *)hw)->NMICTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~EIC_NMICTRL_NMISENSE(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_NMISENSE_bf(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= EIC_NMICTRL_NMISENSE(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_NMISENSE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp = (tmp & EIC_NMICTRL_NMISENSE_Msk) >> EIC_NMICTRL_NMISENSE_Pos; + return tmp; +} + +static inline void hri_eic_set_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_get_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Eic *)hw)->NMICTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_NMICTRL_reg(const void *const hw, hri_eic_nmictrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->NMICTRL.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_nmictrl_reg_t hri_eic_read_NMICTRL_reg(const void *const hw) +{ + return ((Eic *)hw)->NMICTRL.reg; +} + +static inline void hri_eic_set_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= EIC_EVCTRL_EXTINTEO(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp = (tmp & EIC_EVCTRL_EXTINTEO(mask)) >> EIC_EVCTRL_EXTINTEO_Pos; + return tmp; +} + +static inline void hri_eic_write_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= ~EIC_EVCTRL_EXTINTEO_Msk; + tmp |= EIC_EVCTRL_EXTINTEO(data); + ((Eic *)hw)->EVCTRL.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~EIC_EVCTRL_EXTINTEO(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_EXTINTEO_bf(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= EIC_EVCTRL_EXTINTEO(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_EXTINTEO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp = (tmp & EIC_EVCTRL_EXTINTEO_Msk) >> EIC_EVCTRL_EXTINTEO_Pos; + return tmp; +} + +static inline void hri_eic_set_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_get_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_EVCTRL_reg(const void *const hw, hri_eic_evctrl_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->EVCTRL.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_evctrl_reg_t hri_eic_read_EVCTRL_reg(const void *const hw) +{ + return ((Eic *)hw)->EVCTRL.reg; +} + +static inline void hri_eic_set_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg |= EIC_ASYNCH_ASYNCH(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp = (tmp & EIC_ASYNCH_ASYNCH(mask)) >> EIC_ASYNCH_ASYNCH_Pos; + return tmp; +} + +static inline void hri_eic_write_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp &= ~EIC_ASYNCH_ASYNCH_Msk; + tmp |= EIC_ASYNCH_ASYNCH(data); + ((Eic *)hw)->ASYNCH.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg &= ~EIC_ASYNCH_ASYNCH(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_ASYNCH_ASYNCH_bf(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg ^= EIC_ASYNCH_ASYNCH(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_ASYNCH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp = (tmp & EIC_ASYNCH_ASYNCH_Msk) >> EIC_ASYNCH_ASYNCH_Pos; + return tmp; +} + +static inline void hri_eic_set_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_get_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->ASYNCH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_ASYNCH_reg(const void *const hw, hri_eic_asynch_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->ASYNCH.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_asynch_reg_t hri_eic_read_ASYNCH_reg(const void *const hw) +{ + return ((Eic *)hw)->ASYNCH.reg; +} + +static inline void hri_eic_set_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN0) >> EIC_CONFIG_FILTEN0_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN0; + tmp |= value << EIC_CONFIG_FILTEN0_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN0_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN1) >> EIC_CONFIG_FILTEN1_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN1; + tmp |= value << EIC_CONFIG_FILTEN1_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN1_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN2) >> EIC_CONFIG_FILTEN2_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN2; + tmp |= value << EIC_CONFIG_FILTEN2_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN2_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN2; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN3) >> EIC_CONFIG_FILTEN3_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN3; + tmp |= value << EIC_CONFIG_FILTEN3_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN3_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN3; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN4) >> EIC_CONFIG_FILTEN4_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN4; + tmp |= value << EIC_CONFIG_FILTEN4_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN4_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN4; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN5) >> EIC_CONFIG_FILTEN5_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN5; + tmp |= value << EIC_CONFIG_FILTEN5_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN5_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN5; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN6) >> EIC_CONFIG_FILTEN6_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN6; + tmp |= value << EIC_CONFIG_FILTEN6_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN6_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN6; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_FILTEN7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_FILTEN7) >> EIC_CONFIG_FILTEN7_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_FILTEN7; + tmp |= value << EIC_CONFIG_FILTEN7_Pos; + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_FILTEN7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_FILTEN7_bit(const void *const hw, uint8_t index) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_FILTEN7; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE0(mask)) >> EIC_CONFIG_SENSE0_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE0_Msk; + tmp |= EIC_CONFIG_SENSE0(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE0_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE0_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE0_Msk) >> EIC_CONFIG_SENSE0_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE1(mask)) >> EIC_CONFIG_SENSE1_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE1_Msk; + tmp |= EIC_CONFIG_SENSE1(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE1_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE1_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE1_Msk) >> EIC_CONFIG_SENSE1_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE2(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE2(mask)) >> EIC_CONFIG_SENSE2_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE2_Msk; + tmp |= EIC_CONFIG_SENSE2(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE2(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE2_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE2(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE2_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE2_Msk) >> EIC_CONFIG_SENSE2_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE3(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE3(mask)) >> EIC_CONFIG_SENSE3_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE3_Msk; + tmp |= EIC_CONFIG_SENSE3(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE3(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE3_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE3(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE3_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE3_Msk) >> EIC_CONFIG_SENSE3_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE4(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE4(mask)) >> EIC_CONFIG_SENSE4_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE4_Msk; + tmp |= EIC_CONFIG_SENSE4(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE4(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE4_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE4(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE4_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE4_Msk) >> EIC_CONFIG_SENSE4_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE5(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE5(mask)) >> EIC_CONFIG_SENSE5_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE5_Msk; + tmp |= EIC_CONFIG_SENSE5(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE5(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE5_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE5(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE5_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE5_Msk) >> EIC_CONFIG_SENSE5_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE6(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE6(mask)) >> EIC_CONFIG_SENSE6_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE6_Msk; + tmp |= EIC_CONFIG_SENSE6(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE6(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE6_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE6(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE6_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE6_Msk) >> EIC_CONFIG_SENSE6_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= EIC_CONFIG_SENSE7(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE7(mask)) >> EIC_CONFIG_SENSE7_Pos; + return tmp; +} + +static inline void hri_eic_write_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= ~EIC_CONFIG_SENSE7_Msk; + tmp |= EIC_CONFIG_SENSE7(data); + ((Eic *)hw)->CONFIG[index].reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~EIC_CONFIG_SENSE7(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_SENSE7_bf(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= EIC_CONFIG_SENSE7(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_SENSE7_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp = (tmp & EIC_CONFIG_SENSE7_Msk) >> EIC_CONFIG_SENSE7_Pos; + return tmp; +} + +static inline void hri_eic_set_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_get_CONFIG_reg(const void *const hw, uint8_t index, + hri_eic_config_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->CONFIG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_CONFIG_reg(const void *const hw, uint8_t index, hri_eic_config_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->CONFIG[index].reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_config_reg_t hri_eic_read_CONFIG_reg(const void *const hw, uint8_t index) +{ + return ((Eic *)hw)->CONFIG[index].reg; +} + +static inline void hri_eic_set_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DEBOUNCEN.reg |= EIC_DEBOUNCEN_DEBOUNCEN(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_debouncen_reg_t hri_eic_get_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, + hri_eic_debouncen_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DEBOUNCEN.reg; + tmp = (tmp & EIC_DEBOUNCEN_DEBOUNCEN(mask)) >> EIC_DEBOUNCEN_DEBOUNCEN_Pos; + return tmp; +} + +static inline void hri_eic_write_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->DEBOUNCEN.reg; + tmp &= ~EIC_DEBOUNCEN_DEBOUNCEN_Msk; + tmp |= EIC_DEBOUNCEN_DEBOUNCEN(data); + ((Eic *)hw)->DEBOUNCEN.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DEBOUNCEN.reg &= ~EIC_DEBOUNCEN_DEBOUNCEN(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw, hri_eic_debouncen_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DEBOUNCEN.reg ^= EIC_DEBOUNCEN_DEBOUNCEN(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_debouncen_reg_t hri_eic_read_DEBOUNCEN_DEBOUNCEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DEBOUNCEN.reg; + tmp = (tmp & EIC_DEBOUNCEN_DEBOUNCEN_Msk) >> EIC_DEBOUNCEN_DEBOUNCEN_Pos; + return tmp; +} + +static inline void hri_eic_set_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DEBOUNCEN.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_debouncen_reg_t hri_eic_get_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DEBOUNCEN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DEBOUNCEN.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DEBOUNCEN.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DEBOUNCEN_reg(const void *const hw, hri_eic_debouncen_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DEBOUNCEN.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_debouncen_reg_t hri_eic_read_DEBOUNCEN_reg(const void *const hw) +{ + return ((Eic *)hw)->DEBOUNCEN.reg; +} + +static inline void hri_eic_set_DPRESCALER_STATES0_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_STATES0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_DPRESCALER_STATES0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp = (tmp & EIC_DPRESCALER_STATES0) >> EIC_DPRESCALER_STATES0_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_DPRESCALER_STATES0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp &= ~EIC_DPRESCALER_STATES0; + tmp |= value << EIC_DPRESCALER_STATES0_Pos; + ((Eic *)hw)->DPRESCALER.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DPRESCALER_STATES0_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_STATES0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DPRESCALER_STATES0_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_STATES0; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_DPRESCALER_STATES1_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_STATES1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_DPRESCALER_STATES1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp = (tmp & EIC_DPRESCALER_STATES1) >> EIC_DPRESCALER_STATES1_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_DPRESCALER_STATES1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp &= ~EIC_DPRESCALER_STATES1; + tmp |= value << EIC_DPRESCALER_STATES1_Pos; + ((Eic *)hw)->DPRESCALER.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DPRESCALER_STATES1_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_STATES1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DPRESCALER_STATES1_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_STATES1; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_DPRESCALER_TICKON_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_TICKON; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_eic_get_DPRESCALER_TICKON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp = (tmp & EIC_DPRESCALER_TICKON) >> EIC_DPRESCALER_TICKON_Pos; + return (bool)tmp; +} + +static inline void hri_eic_write_DPRESCALER_TICKON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp &= ~EIC_DPRESCALER_TICKON; + tmp |= value << EIC_DPRESCALER_TICKON_Pos; + ((Eic *)hw)->DPRESCALER.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DPRESCALER_TICKON_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_TICKON; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DPRESCALER_TICKON_bit(const void *const hw) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_TICKON; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_set_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_PRESCALER0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_dprescaler_reg_t hri_eic_get_DPRESCALER_PRESCALER0_bf(const void *const hw, + hri_eic_dprescaler_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp = (tmp & EIC_DPRESCALER_PRESCALER0(mask)) >> EIC_DPRESCALER_PRESCALER0_Pos; + return tmp; +} + +static inline void hri_eic_write_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp &= ~EIC_DPRESCALER_PRESCALER0_Msk; + tmp |= EIC_DPRESCALER_PRESCALER0(data); + ((Eic *)hw)->DPRESCALER.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_PRESCALER0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DPRESCALER_PRESCALER0_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_PRESCALER0(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_dprescaler_reg_t hri_eic_read_DPRESCALER_PRESCALER0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp = (tmp & EIC_DPRESCALER_PRESCALER0_Msk) >> EIC_DPRESCALER_PRESCALER0_Pos; + return tmp; +} + +static inline void hri_eic_set_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg |= EIC_DPRESCALER_PRESCALER1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_dprescaler_reg_t hri_eic_get_DPRESCALER_PRESCALER1_bf(const void *const hw, + hri_eic_dprescaler_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp = (tmp & EIC_DPRESCALER_PRESCALER1(mask)) >> EIC_DPRESCALER_PRESCALER1_Pos; + return tmp; +} + +static inline void hri_eic_write_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t data) +{ + uint32_t tmp; + EIC_CRITICAL_SECTION_ENTER(); + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp &= ~EIC_DPRESCALER_PRESCALER1_Msk; + tmp |= EIC_DPRESCALER_PRESCALER1(data); + ((Eic *)hw)->DPRESCALER.reg = tmp; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg &= ~EIC_DPRESCALER_PRESCALER1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DPRESCALER_PRESCALER1_bf(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg ^= EIC_DPRESCALER_PRESCALER1(mask); + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_dprescaler_reg_t hri_eic_read_DPRESCALER_PRESCALER1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp = (tmp & EIC_DPRESCALER_PRESCALER1_Msk) >> EIC_DPRESCALER_PRESCALER1_Pos; + return tmp; +} + +static inline void hri_eic_set_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg |= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_dprescaler_reg_t hri_eic_get_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + uint32_t tmp; + tmp = ((Eic *)hw)->DPRESCALER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_eic_write_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t data) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg = data; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_clear_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg &= ~mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_eic_toggle_DPRESCALER_reg(const void *const hw, hri_eic_dprescaler_reg_t mask) +{ + EIC_CRITICAL_SECTION_ENTER(); + ((Eic *)hw)->DPRESCALER.reg ^= mask; + EIC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_eic_dprescaler_reg_t hri_eic_read_DPRESCALER_reg(const void *const hw) +{ + return ((Eic *)hw)->DPRESCALER.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_EIC_E54_H_INCLUDED */ +#endif /* _SAME54_EIC_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_evsys_e54.h b/software/firmware/oracle_same54n19a/hri/hri_evsys_e54.h new file mode 100644 index 00000000..cd4a98a4 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_evsys_e54.h @@ -0,0 +1,1707 @@ +/** + * \file + * + * \brief SAM EVSYS + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_EVSYS_COMPONENT_ +#ifndef _HRI_EVSYS_E54_H_INCLUDED_ +#define _HRI_EVSYS_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_EVSYS_CRITICAL_SECTIONS) +#define EVSYS_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define EVSYS_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define EVSYS_CRITICAL_SECTION_ENTER() +#define EVSYS_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_evsys_intpend_reg_t; +typedef uint32_t hri_evsys_busych_reg_t; +typedef uint32_t hri_evsys_channel_reg_t; +typedef uint32_t hri_evsys_intstatus_reg_t; +typedef uint32_t hri_evsys_readyusr_reg_t; +typedef uint32_t hri_evsys_swevt_reg_t; +typedef uint32_t hri_evsys_user_reg_t; +typedef uint32_t hri_evsyschannel_channel_reg_t; +typedef uint8_t hri_evsys_chintenset_reg_t; +typedef uint8_t hri_evsys_chintflag_reg_t; +typedef uint8_t hri_evsys_chstatus_reg_t; +typedef uint8_t hri_evsys_ctrla_reg_t; +typedef uint8_t hri_evsys_prictrl_reg_t; +typedef uint8_t hri_evsyschannel_chintenset_reg_t; +typedef uint8_t hri_evsyschannel_chintflag_reg_t; +typedef uint8_t hri_evsyschannel_chstatus_reg_t; + +static inline bool hri_evsys_get_INTSTATUS_CHINT0_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT0) >> EVSYS_INTSTATUS_CHINT0_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT1_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT1) >> EVSYS_INTSTATUS_CHINT1_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT2_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT2) >> EVSYS_INTSTATUS_CHINT2_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT3_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT3) >> EVSYS_INTSTATUS_CHINT3_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT4_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT4) >> EVSYS_INTSTATUS_CHINT4_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT5_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT5) >> EVSYS_INTSTATUS_CHINT5_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT6_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT6) >> EVSYS_INTSTATUS_CHINT6_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT7_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT7) >> EVSYS_INTSTATUS_CHINT7_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT8_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT8) >> EVSYS_INTSTATUS_CHINT8_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT9_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT9) >> EVSYS_INTSTATUS_CHINT9_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT10_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT10) >> EVSYS_INTSTATUS_CHINT10_Pos; +} + +static inline bool hri_evsys_get_INTSTATUS_CHINT11_bit(const void *const hw) +{ + return (((Evsys *)hw)->INTSTATUS.reg & EVSYS_INTSTATUS_CHINT11) >> EVSYS_INTSTATUS_CHINT11_Pos; +} + +static inline hri_evsys_intstatus_reg_t hri_evsys_get_INTSTATUS_reg(const void *const hw, + hri_evsys_intstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->INTSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_intstatus_reg_t hri_evsys_read_INTSTATUS_reg(const void *const hw) +{ + return ((Evsys *)hw)->INTSTATUS.reg; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH0_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH0) >> EVSYS_BUSYCH_BUSYCH0_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH1_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH1) >> EVSYS_BUSYCH_BUSYCH1_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH2_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH2) >> EVSYS_BUSYCH_BUSYCH2_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH3_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH3) >> EVSYS_BUSYCH_BUSYCH3_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH4_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH4) >> EVSYS_BUSYCH_BUSYCH4_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH5_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH5) >> EVSYS_BUSYCH_BUSYCH5_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH6_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH6) >> EVSYS_BUSYCH_BUSYCH6_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH7_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH7) >> EVSYS_BUSYCH_BUSYCH7_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH8_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH8) >> EVSYS_BUSYCH_BUSYCH8_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH9_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH9) >> EVSYS_BUSYCH_BUSYCH9_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH10_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH10) >> EVSYS_BUSYCH_BUSYCH10_Pos; +} + +static inline bool hri_evsys_get_BUSYCH_BUSYCH11_bit(const void *const hw) +{ + return (((Evsys *)hw)->BUSYCH.reg & EVSYS_BUSYCH_BUSYCH11) >> EVSYS_BUSYCH_BUSYCH11_Pos; +} + +static inline hri_evsys_busych_reg_t hri_evsys_get_BUSYCH_reg(const void *const hw, hri_evsys_busych_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->BUSYCH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_busych_reg_t hri_evsys_read_BUSYCH_reg(const void *const hw) +{ + return ((Evsys *)hw)->BUSYCH.reg; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR0_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR0) >> EVSYS_READYUSR_READYUSR0_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR1_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR1) >> EVSYS_READYUSR_READYUSR1_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR2_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR2) >> EVSYS_READYUSR_READYUSR2_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR3_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR3) >> EVSYS_READYUSR_READYUSR3_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR4_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR4) >> EVSYS_READYUSR_READYUSR4_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR5_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR5) >> EVSYS_READYUSR_READYUSR5_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR6_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR6) >> EVSYS_READYUSR_READYUSR6_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR7_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR7) >> EVSYS_READYUSR_READYUSR7_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR8_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR8) >> EVSYS_READYUSR_READYUSR8_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR9_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR9) >> EVSYS_READYUSR_READYUSR9_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR10_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR10) >> EVSYS_READYUSR_READYUSR10_Pos; +} + +static inline bool hri_evsys_get_READYUSR_READYUSR11_bit(const void *const hw) +{ + return (((Evsys *)hw)->READYUSR.reg & EVSYS_READYUSR_READYUSR11) >> EVSYS_READYUSR_READYUSR11_Pos; +} + +static inline hri_evsys_readyusr_reg_t hri_evsys_get_READYUSR_reg(const void *const hw, hri_evsys_readyusr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->READYUSR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_readyusr_reg_t hri_evsys_read_READYUSR_reg(const void *const hw) +{ + return ((Evsys *)hw)->READYUSR.reg; +} + +static inline void hri_evsys_set_CTRLA_SWRST_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg |= EVSYS_CTRLA_SWRST; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->CTRLA.reg; + tmp = (tmp & EVSYS_CTRLA_SWRST) >> EVSYS_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_set_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_ctrla_reg_t hri_evsys_get_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CTRLA_reg(const void *const hw, hri_evsys_ctrla_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->CTRLA.reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_ctrla_reg_t hri_evsys_read_CTRLA_reg(const void *const hw) +{ + return ((Evsys *)hw)->CTRLA.reg; +} + +static inline void hri_evsys_set_PRICTRL_RREN_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg |= EVSYS_PRICTRL_RREN; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_PRICTRL_RREN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->PRICTRL.reg; + tmp = (tmp & EVSYS_PRICTRL_RREN) >> EVSYS_PRICTRL_RREN_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_PRICTRL_RREN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->PRICTRL.reg; + tmp &= ~EVSYS_PRICTRL_RREN; + tmp |= value << EVSYS_PRICTRL_RREN_Pos; + ((Evsys *)hw)->PRICTRL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_PRICTRL_RREN_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg &= ~EVSYS_PRICTRL_RREN; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_PRICTRL_RREN_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg ^= EVSYS_PRICTRL_RREN; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg |= EVSYS_PRICTRL_PRI(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_prictrl_reg_t hri_evsys_get_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->PRICTRL.reg; + tmp = (tmp & EVSYS_PRICTRL_PRI(mask)) >> EVSYS_PRICTRL_PRI_Pos; + return tmp; +} + +static inline void hri_evsys_write_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t data) +{ + uint8_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->PRICTRL.reg; + tmp &= ~EVSYS_PRICTRL_PRI_Msk; + tmp |= EVSYS_PRICTRL_PRI(data); + ((Evsys *)hw)->PRICTRL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg &= ~EVSYS_PRICTRL_PRI(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_PRICTRL_PRI_bf(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg ^= EVSYS_PRICTRL_PRI(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_prictrl_reg_t hri_evsys_read_PRICTRL_PRI_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->PRICTRL.reg; + tmp = (tmp & EVSYS_PRICTRL_PRI_Msk) >> EVSYS_PRICTRL_PRI_Pos; + return tmp; +} + +static inline void hri_evsys_set_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_prictrl_reg_t hri_evsys_get_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->PRICTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_PRICTRL_reg(const void *const hw, hri_evsys_prictrl_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->PRICTRL.reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_prictrl_reg_t hri_evsys_read_PRICTRL_reg(const void *const hw) +{ + return ((Evsys *)hw)->PRICTRL.reg; +} + +static inline void hri_evsys_set_INTPEND_OVR_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_OVR; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_INTPEND_OVR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp = (tmp & EVSYS_INTPEND_OVR) >> EVSYS_INTPEND_OVR_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_INTPEND_OVR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp &= ~EVSYS_INTPEND_OVR; + tmp |= value << EVSYS_INTPEND_OVR_Pos; + ((Evsys *)hw)->INTPEND.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_INTPEND_OVR_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_OVR; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_INTPEND_OVR_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_OVR; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_INTPEND_EVD_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_EVD; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_INTPEND_EVD_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp = (tmp & EVSYS_INTPEND_EVD) >> EVSYS_INTPEND_EVD_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_INTPEND_EVD_bit(const void *const hw, bool value) +{ + uint16_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp &= ~EVSYS_INTPEND_EVD; + tmp |= value << EVSYS_INTPEND_EVD_Pos; + ((Evsys *)hw)->INTPEND.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_INTPEND_EVD_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_EVD; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_INTPEND_EVD_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_EVD; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_INTPEND_READY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_READY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_INTPEND_READY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp = (tmp & EVSYS_INTPEND_READY) >> EVSYS_INTPEND_READY_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_INTPEND_READY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp &= ~EVSYS_INTPEND_READY; + tmp |= value << EVSYS_INTPEND_READY_Pos; + ((Evsys *)hw)->INTPEND.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_INTPEND_READY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_READY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_INTPEND_READY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_READY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_INTPEND_BUSY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_BUSY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_INTPEND_BUSY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp = (tmp & EVSYS_INTPEND_BUSY) >> EVSYS_INTPEND_BUSY_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_INTPEND_BUSY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp &= ~EVSYS_INTPEND_BUSY; + tmp |= value << EVSYS_INTPEND_BUSY_Pos; + ((Evsys *)hw)->INTPEND.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_INTPEND_BUSY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_BUSY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_INTPEND_BUSY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_BUSY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg |= EVSYS_INTPEND_ID(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_intpend_reg_t hri_evsys_get_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp = (tmp & EVSYS_INTPEND_ID(mask)) >> EVSYS_INTPEND_ID_Pos; + return tmp; +} + +static inline void hri_evsys_write_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t data) +{ + uint16_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp &= ~EVSYS_INTPEND_ID_Msk; + tmp |= EVSYS_INTPEND_ID(data); + ((Evsys *)hw)->INTPEND.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg &= ~EVSYS_INTPEND_ID(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_INTPEND_ID_bf(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg ^= EVSYS_INTPEND_ID(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_intpend_reg_t hri_evsys_read_INTPEND_ID_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp = (tmp & EVSYS_INTPEND_ID_Msk) >> EVSYS_INTPEND_ID_Pos; + return tmp; +} + +static inline void hri_evsys_set_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_intpend_reg_t hri_evsys_get_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + uint16_t tmp; + tmp = ((Evsys *)hw)->INTPEND.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_INTPEND_reg(const void *const hw, hri_evsys_intpend_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->INTPEND.reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_intpend_reg_t hri_evsys_read_INTPEND_reg(const void *const hw) +{ + return ((Evsys *)hw)->INTPEND.reg; +} + +static inline void hri_evsys_set_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg |= EVSYS_USER_CHANNEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_get_USER_CHANNEL_bf(const void *const hw, uint8_t index, + hri_evsys_user_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->USER[index].reg; + tmp = (tmp & EVSYS_USER_CHANNEL(mask)) >> EVSYS_USER_CHANNEL_Pos; + return tmp; +} + +static inline void hri_evsys_write_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->USER[index].reg; + tmp &= ~EVSYS_USER_CHANNEL_Msk; + tmp |= EVSYS_USER_CHANNEL(data); + ((Evsys *)hw)->USER[index].reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg &= ~EVSYS_USER_CHANNEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_USER_CHANNEL_bf(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg ^= EVSYS_USER_CHANNEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_read_USER_CHANNEL_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->USER[index].reg; + tmp = (tmp & EVSYS_USER_CHANNEL_Msk) >> EVSYS_USER_CHANNEL_Pos; + return tmp; +} + +static inline void hri_evsys_set_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_get_USER_reg(const void *const hw, uint8_t index, + hri_evsys_user_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->USER[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_USER_reg(const void *const hw, uint8_t index, hri_evsys_user_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->USER[index].reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_user_reg_t hri_evsys_read_USER_reg(const void *const hw, uint8_t index) +{ + return ((Evsys *)hw)->USER[index].reg; +} + +static inline void hri_evsys_write_SWEVT_reg(const void *const hw, hri_evsys_swevt_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->SWEVT.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsyschannel_get_CHINTFLAG_OVR_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos; +} + +static inline void hri_evsyschannel_clear_CHINTFLAG_OVR_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR; +} + +static inline bool hri_evsyschannel_get_CHINTFLAG_EVD_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos; +} + +static inline void hri_evsyschannel_clear_CHINTFLAG_EVD_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD; +} + +static inline bool hri_evsyschannel_get_interrupt_OVR_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos; +} + +static inline void hri_evsyschannel_clear_interrupt_OVR_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR; +} + +static inline bool hri_evsyschannel_get_interrupt_EVD_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos; +} + +static inline void hri_evsyschannel_clear_interrupt_EVD_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD; +} + +static inline hri_evsys_chintflag_reg_t hri_evsyschannel_get_CHINTFLAG_reg(const void *const hw, + hri_evsys_chintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((EvsysChannel *)hw)->CHINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_chintflag_reg_t hri_evsyschannel_read_CHINTFLAG_reg(const void *const hw) +{ + return ((EvsysChannel *)hw)->CHINTFLAG.reg; +} + +static inline void hri_evsyschannel_clear_CHINTFLAG_reg(const void *const hw, hri_evsys_chintflag_reg_t mask) +{ + ((EvsysChannel *)hw)->CHINTFLAG.reg = mask; +} + +static inline void hri_evsyschannel_set_CHINTEN_OVR_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_OVR; +} + +static inline bool hri_evsyschannel_get_CHINTEN_OVR_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHINTENSET.reg & EVSYS_CHINTENSET_OVR) >> EVSYS_CHINTENSET_OVR_Pos; +} + +static inline void hri_evsyschannel_write_CHINTEN_OVR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_OVR; + } else { + ((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_OVR; + } +} + +static inline void hri_evsyschannel_clear_CHINTEN_OVR_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_OVR; +} + +static inline void hri_evsyschannel_set_CHINTEN_EVD_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_EVD; +} + +static inline bool hri_evsyschannel_get_CHINTEN_EVD_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHINTENSET.reg & EVSYS_CHINTENSET_EVD) >> EVSYS_CHINTENSET_EVD_Pos; +} + +static inline void hri_evsyschannel_write_CHINTEN_EVD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_EVD; + } else { + ((EvsysChannel *)hw)->CHINTENSET.reg = EVSYS_CHINTENSET_EVD; + } +} + +static inline void hri_evsyschannel_clear_CHINTEN_EVD_bit(const void *const hw) +{ + ((EvsysChannel *)hw)->CHINTENCLR.reg = EVSYS_CHINTENSET_EVD; +} + +static inline void hri_evsyschannel_set_CHINTEN_reg(const void *const hw, hri_evsys_chintenset_reg_t mask) +{ + ((EvsysChannel *)hw)->CHINTENSET.reg = mask; +} + +static inline hri_evsys_chintenset_reg_t hri_evsyschannel_get_CHINTEN_reg(const void *const hw, + hri_evsys_chintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((EvsysChannel *)hw)->CHINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_chintenset_reg_t hri_evsyschannel_read_CHINTEN_reg(const void *const hw) +{ + return ((EvsysChannel *)hw)->CHINTENSET.reg; +} + +static inline void hri_evsyschannel_write_CHINTEN_reg(const void *const hw, hri_evsys_chintenset_reg_t data) +{ + ((EvsysChannel *)hw)->CHINTENSET.reg = data; + ((EvsysChannel *)hw)->CHINTENCLR.reg = ~data; +} + +static inline void hri_evsyschannel_clear_CHINTEN_reg(const void *const hw, hri_evsys_chintenset_reg_t mask) +{ + ((EvsysChannel *)hw)->CHINTENCLR.reg = mask; +} + +static inline bool hri_evsyschannel_get_CHSTATUS_RDYUSR_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_RDYUSR) >> EVSYS_CHSTATUS_RDYUSR_Pos; +} + +static inline bool hri_evsyschannel_get_CHSTATUS_BUSYCH_bit(const void *const hw) +{ + return (((EvsysChannel *)hw)->CHSTATUS.reg & EVSYS_CHSTATUS_BUSYCH) >> EVSYS_CHSTATUS_BUSYCH_Pos; +} + +static inline hri_evsys_chstatus_reg_t hri_evsyschannel_get_CHSTATUS_reg(const void *const hw, + hri_evsys_chstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((EvsysChannel *)hw)->CHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_chstatus_reg_t hri_evsyschannel_read_CHSTATUS_reg(const void *const hw) +{ + return ((EvsysChannel *)hw)->CHSTATUS.reg; +} + +static inline void hri_evsyschannel_set_CHANNEL_RUNSTDBY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsyschannel_get_CHANNEL_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_RUNSTDBY) >> EVSYS_CHANNEL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_evsyschannel_write_CHANNEL_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_RUNSTDBY; + tmp |= value << EVSYS_CHANNEL_RUNSTDBY_Pos; + ((EvsysChannel *)hw)->CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_clear_CHANNEL_RUNSTDBY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_toggle_CHANNEL_RUNSTDBY_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_set_CHANNEL_ONDEMAND_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsyschannel_get_CHANNEL_ONDEMAND_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_ONDEMAND) >> EVSYS_CHANNEL_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_evsyschannel_write_CHANNEL_ONDEMAND_bit(const void *const hw, bool value) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_ONDEMAND; + tmp |= value << EVSYS_CHANNEL_ONDEMAND_Pos; + ((EvsysChannel *)hw)->CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_clear_CHANNEL_ONDEMAND_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_toggle_CHANNEL_ONDEMAND_bit(const void *const hw) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_set_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_EVGEN_bf(const void *const hw, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EVGEN(mask)) >> EVSYS_CHANNEL_EVGEN_Pos; + return tmp; +} + +static inline void hri_evsyschannel_write_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_EVGEN_Msk; + tmp |= EVSYS_CHANNEL_EVGEN(data); + ((EvsysChannel *)hw)->CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_clear_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_toggle_CHANNEL_EVGEN_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_EVGEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EVGEN_Msk) >> EVSYS_CHANNEL_EVGEN_Pos; + return tmp; +} + +static inline void hri_evsyschannel_set_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_PATH_bf(const void *const hw, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_PATH(mask)) >> EVSYS_CHANNEL_PATH_Pos; + return tmp; +} + +static inline void hri_evsyschannel_write_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_PATH_Msk; + tmp |= EVSYS_CHANNEL_PATH(data); + ((EvsysChannel *)hw)->CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_clear_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_toggle_CHANNEL_PATH_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_PATH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_PATH_Msk) >> EVSYS_CHANNEL_PATH_Pos; + return tmp; +} + +static inline void hri_evsyschannel_set_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg |= EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_EDGSEL_bf(const void *const hw, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EDGSEL(mask)) >> EVSYS_CHANNEL_EDGSEL_Pos; + return tmp; +} + +static inline void hri_evsyschannel_write_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_EDGSEL_Msk; + tmp |= EVSYS_CHANNEL_EDGSEL(data); + ((EvsysChannel *)hw)->CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_clear_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg &= ~EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_toggle_CHANNEL_EDGSEL_bf(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg ^= EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_EDGSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EDGSEL_Msk) >> EVSYS_CHANNEL_EDGSEL_Pos; + return tmp; +} + +static inline void hri_evsyschannel_set_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_get_CHANNEL_reg(const void *const hw, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((EvsysChannel *)hw)->CHANNEL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsyschannel_write_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_clear_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsyschannel_toggle_CHANNEL_reg(const void *const hw, hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((EvsysChannel *)hw)->CHANNEL.reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsyschannel_read_CHANNEL_reg(const void *const hw) +{ + return ((EvsysChannel *)hw)->CHANNEL.reg; +} + +static inline bool hri_evsys_get_CHINTFLAG_OVR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos; +} + +static inline void hri_evsys_clear_CHINTFLAG_OVR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR; +} + +static inline bool hri_evsys_get_CHINTFLAG_EVD_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos; +} + +static inline void hri_evsys_clear_CHINTFLAG_EVD_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD; +} + +static inline bool hri_evsys_get_interrupt_OVR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_OVR) >> EVSYS_CHINTFLAG_OVR_Pos; +} + +static inline void hri_evsys_clear_interrupt_OVR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_OVR; +} + +static inline bool hri_evsys_get_interrupt_EVD_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg & EVSYS_CHINTFLAG_EVD) >> EVSYS_CHINTFLAG_EVD_Pos; +} + +static inline void hri_evsys_clear_interrupt_EVD_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = EVSYS_CHINTFLAG_EVD; +} + +static inline hri_evsys_chintflag_reg_t hri_evsys_get_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_chintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_chintflag_reg_t hri_evsys_read_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg; +} + +static inline void hri_evsys_clear_CHINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_chintflag_reg_t mask) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTFLAG.reg = mask; +} + +static inline void hri_evsys_set_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_OVR; +} + +static inline bool hri_evsys_get_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg & EVSYS_CHINTENSET_OVR) >> EVSYS_CHINTENSET_OVR_Pos; +} + +static inline void hri_evsys_write_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_OVR; + } else { + ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_OVR; + } +} + +static inline void hri_evsys_clear_CHINTEN_OVR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_OVR; +} + +static inline void hri_evsys_set_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_EVD; +} + +static inline bool hri_evsys_get_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg & EVSYS_CHINTENSET_EVD) >> EVSYS_CHINTENSET_EVD_Pos; +} + +static inline void hri_evsys_write_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_EVD; + } else { + ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = EVSYS_CHINTENSET_EVD; + } +} + +static inline void hri_evsys_clear_CHINTEN_EVD_bit(const void *const hw, uint8_t submodule_index) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = EVSYS_CHINTENSET_EVD; +} + +static inline void hri_evsys_set_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_chintenset_reg_t mask) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = mask; +} + +static inline hri_evsys_chintenset_reg_t hri_evsys_get_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_chintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_chintenset_reg_t hri_evsys_read_CHINTEN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg; +} + +static inline void hri_evsys_write_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_chintenset_reg_t data) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTENSET.reg = data; + ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = ~data; +} + +static inline void hri_evsys_clear_CHINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_chintenset_reg_t mask) +{ + ((Evsys *)hw)->Channel[submodule_index].CHINTENCLR.reg = mask; +} + +static inline bool hri_evsys_get_CHSTATUS_RDYUSR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg & EVSYS_CHSTATUS_RDYUSR) >> EVSYS_CHSTATUS_RDYUSR_Pos; +} + +static inline bool hri_evsys_get_CHSTATUS_BUSYCH_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg & EVSYS_CHSTATUS_BUSYCH) >> EVSYS_CHSTATUS_BUSYCH_Pos; +} + +static inline hri_evsys_chstatus_reg_t hri_evsys_get_CHSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_chstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_evsys_chstatus_reg_t hri_evsys_read_CHSTATUS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Evsys *)hw)->Channel[submodule_index].CHSTATUS.reg; +} + +static inline void hri_evsys_set_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_RUNSTDBY) >> EVSYS_CHANNEL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_RUNSTDBY; + tmp |= value << EVSYS_CHANNEL_RUNSTDBY_Pos; + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_RUNSTDBY; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_evsys_get_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_ONDEMAND) >> EVSYS_CHANNEL_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_evsys_write_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_ONDEMAND; + tmp |= value << EVSYS_CHANNEL_ONDEMAND_Pos; + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_ONDEMAND; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_set_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EVGEN(mask)) >> EVSYS_CHANNEL_EVGEN_Pos; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_EVGEN_Msk; + tmp |= EVSYS_CHANNEL_EVGEN(data); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_EVGEN(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EVGEN_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EVGEN_Msk) >> EVSYS_CHANNEL_EVGEN_Pos; + return tmp; +} + +static inline void hri_evsys_set_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_PATH(mask)) >> EVSYS_CHANNEL_PATH_Pos; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_PATH_Msk; + tmp |= EVSYS_CHANNEL_PATH(data); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_PATH(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_PATH_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_PATH_Msk) >> EVSYS_CHANNEL_PATH_Pos; + return tmp; +} + +static inline void hri_evsys_set_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EDGSEL(mask)) >> EVSYS_CHANNEL_EDGSEL_Pos; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t data) +{ + uint32_t tmp; + EVSYS_CRITICAL_SECTION_ENTER(); + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp &= ~EVSYS_CHANNEL_EDGSEL_Msk; + tmp |= EVSYS_CHANNEL_EDGSEL(data); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = tmp; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= EVSYS_CHANNEL_EDGSEL(mask); + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_EDGSEL_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp = (tmp & EVSYS_CHANNEL_EDGSEL_Msk) >> EVSYS_CHANNEL_EDGSEL_Pos; + return tmp; +} + +static inline void hri_evsys_set_CHANNEL_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg |= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_get_CHANNEL_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + uint32_t tmp; + tmp = ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_evsys_write_CHANNEL_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t data) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg = data; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_clear_CHANNEL_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg &= ~mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_evsys_toggle_CHANNEL_reg(const void *const hw, uint8_t submodule_index, + hri_evsys_channel_reg_t mask) +{ + EVSYS_CRITICAL_SECTION_ENTER(); + ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg ^= mask; + EVSYS_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_evsys_channel_reg_t hri_evsys_read_CHANNEL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Evsys *)hw)->Channel[submodule_index].CHANNEL.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_EVSYS_E54_H_INCLUDED */ +#endif /* _SAME54_EVSYS_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_freqm_e54.h b/software/firmware/oracle_same54n19a/hri/hri_freqm_e54.h new file mode 100644 index 00000000..8cbc484f --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_freqm_e54.h @@ -0,0 +1,464 @@ +/** + * \file + * + * \brief SAM FREQM + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_FREQM_COMPONENT_ +#ifndef _HRI_FREQM_E54_H_INCLUDED_ +#define _HRI_FREQM_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_FREQM_CRITICAL_SECTIONS) +#define FREQM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define FREQM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define FREQM_CRITICAL_SECTION_ENTER() +#define FREQM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_freqm_cfga_reg_t; +typedef uint32_t hri_freqm_syncbusy_reg_t; +typedef uint32_t hri_freqm_value_reg_t; +typedef uint8_t hri_freqm_ctrla_reg_t; +typedef uint8_t hri_freqm_ctrlb_reg_t; +typedef uint8_t hri_freqm_intenset_reg_t; +typedef uint8_t hri_freqm_intflag_reg_t; +typedef uint8_t hri_freqm_status_reg_t; + +static inline void hri_freqm_wait_for_sync(const void *const hw, hri_freqm_syncbusy_reg_t reg) +{ + while (((Freqm *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_freqm_is_syncing(const void *const hw, hri_freqm_syncbusy_reg_t reg) +{ + return ((Freqm *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_freqm_get_INTFLAG_DONE_bit(const void *const hw) +{ + return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos; +} + +static inline void hri_freqm_clear_INTFLAG_DONE_bit(const void *const hw) +{ + ((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE; +} + +static inline bool hri_freqm_get_interrupt_DONE_bit(const void *const hw) +{ + return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos; +} + +static inline void hri_freqm_clear_interrupt_DONE_bit(const void *const hw) +{ + ((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE; +} + +static inline hri_freqm_intflag_reg_t hri_freqm_get_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Freqm *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_freqm_intflag_reg_t hri_freqm_read_INTFLAG_reg(const void *const hw) +{ + return ((Freqm *)hw)->INTFLAG.reg; +} + +static inline void hri_freqm_clear_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask) +{ + ((Freqm *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_freqm_set_INTEN_DONE_bit(const void *const hw) +{ + ((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE; +} + +static inline bool hri_freqm_get_INTEN_DONE_bit(const void *const hw) +{ + return (((Freqm *)hw)->INTENSET.reg & FREQM_INTENSET_DONE) >> FREQM_INTENSET_DONE_Pos; +} + +static inline void hri_freqm_write_INTEN_DONE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE; + } else { + ((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE; + } +} + +static inline void hri_freqm_clear_INTEN_DONE_bit(const void *const hw) +{ + ((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE; +} + +static inline void hri_freqm_set_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) +{ + ((Freqm *)hw)->INTENSET.reg = mask; +} + +static inline hri_freqm_intenset_reg_t hri_freqm_get_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Freqm *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_freqm_intenset_reg_t hri_freqm_read_INTEN_reg(const void *const hw) +{ + return ((Freqm *)hw)->INTENSET.reg; +} + +static inline void hri_freqm_write_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t data) +{ + ((Freqm *)hw)->INTENSET.reg = data; + ((Freqm *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_freqm_clear_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask) +{ + ((Freqm *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_freqm_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_SWRST) >> FREQM_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_freqm_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_ENABLE) >> FREQM_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_freqm_syncbusy_reg_t hri_freqm_get_SYNCBUSY_reg(const void *const hw, hri_freqm_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Freqm *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_freqm_syncbusy_reg_t hri_freqm_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Freqm *)hw)->SYNCBUSY.reg; +} + +static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_VALUE_bf(const void *const hw, hri_freqm_value_reg_t mask) +{ + return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE(mask)) >> FREQM_VALUE_VALUE_Pos; +} + +static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_VALUE_bf(const void *const hw) +{ + return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE_Msk) >> FREQM_VALUE_VALUE_Pos; +} + +static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_reg(const void *const hw, hri_freqm_value_reg_t mask) +{ + uint32_t tmp; + tmp = ((Freqm *)hw)->VALUE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_reg(const void *const hw) +{ + return ((Freqm *)hw)->VALUE.reg; +} + +static inline void hri_freqm_set_CTRLA_SWRST_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_SWRST; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_freqm_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST); + tmp = ((Freqm *)hw)->CTRLA.reg; + tmp = (tmp & FREQM_CTRLA_SWRST) >> FREQM_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_freqm_set_CTRLA_ENABLE_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_ENABLE; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_freqm_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + tmp = ((Freqm *)hw)->CTRLA.reg; + tmp = (tmp & FREQM_CTRLA_ENABLE) >> FREQM_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_freqm_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + FREQM_CRITICAL_SECTION_ENTER(); + tmp = ((Freqm *)hw)->CTRLA.reg; + tmp &= ~FREQM_CTRLA_ENABLE; + tmp |= value << FREQM_CTRLA_ENABLE_Pos; + ((Freqm *)hw)->CTRLA.reg = tmp; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg &= ~FREQM_CTRLA_ENABLE; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg ^= FREQM_CTRLA_ENABLE; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_set_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg |= mask; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_ctrla_reg_t hri_freqm_get_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + tmp = ((Freqm *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_freqm_write_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t data) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg = data; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_clear_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg &= ~mask; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_toggle_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLA.reg ^= mask; + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_ctrla_reg_t hri_freqm_read_CTRLA_reg(const void *const hw) +{ + hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK); + return ((Freqm *)hw)->CTRLA.reg; +} + +static inline void hri_freqm_set_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg |= FREQM_CFGA_REFNUM(mask); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + uint16_t tmp; + tmp = ((Freqm *)hw)->CFGA.reg; + tmp = (tmp & FREQM_CFGA_REFNUM(mask)) >> FREQM_CFGA_REFNUM_Pos; + return tmp; +} + +static inline void hri_freqm_write_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t data) +{ + uint16_t tmp; + FREQM_CRITICAL_SECTION_ENTER(); + tmp = ((Freqm *)hw)->CFGA.reg; + tmp &= ~FREQM_CFGA_REFNUM_Msk; + tmp |= FREQM_CFGA_REFNUM(data); + ((Freqm *)hw)->CFGA.reg = tmp; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_clear_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg &= ~FREQM_CFGA_REFNUM(mask); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_toggle_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg ^= FREQM_CFGA_REFNUM(mask); + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_REFNUM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Freqm *)hw)->CFGA.reg; + tmp = (tmp & FREQM_CFGA_REFNUM_Msk) >> FREQM_CFGA_REFNUM_Pos; + return tmp; +} + +static inline void hri_freqm_set_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg |= mask; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + uint16_t tmp; + tmp = ((Freqm *)hw)->CFGA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_freqm_write_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t data) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg = data; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_clear_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg &= ~mask; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_freqm_toggle_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CFGA.reg ^= mask; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_reg(const void *const hw) +{ + return ((Freqm *)hw)->CFGA.reg; +} + +static inline bool hri_freqm_get_STATUS_BUSY_bit(const void *const hw) +{ + return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_BUSY) >> FREQM_STATUS_BUSY_Pos; +} + +static inline void hri_freqm_clear_STATUS_BUSY_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->STATUS.reg = FREQM_STATUS_BUSY; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_freqm_get_STATUS_OVF_bit(const void *const hw) +{ + return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_OVF) >> FREQM_STATUS_OVF_Pos; +} + +static inline void hri_freqm_clear_STATUS_OVF_bit(const void *const hw) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->STATUS.reg = FREQM_STATUS_OVF; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_status_reg_t hri_freqm_get_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Freqm *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_freqm_clear_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->STATUS.reg = mask; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_freqm_status_reg_t hri_freqm_read_STATUS_reg(const void *const hw) +{ + return ((Freqm *)hw)->STATUS.reg; +} + +static inline void hri_freqm_write_CTRLB_reg(const void *const hw, hri_freqm_ctrlb_reg_t data) +{ + FREQM_CRITICAL_SECTION_ENTER(); + ((Freqm *)hw)->CTRLB.reg = data; + FREQM_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_FREQM_E54_H_INCLUDED */ +#endif /* _SAME54_FREQM_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_gclk_e54.h b/software/firmware/oracle_same54n19a/hri/hri_gclk_e54.h new file mode 100644 index 00000000..f83af2a0 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_gclk_e54.h @@ -0,0 +1,805 @@ +/** + * \file + * + * \brief SAM GCLK + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_GCLK_COMPONENT_ +#ifndef _HRI_GCLK_E54_H_INCLUDED_ +#define _HRI_GCLK_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_GCLK_CRITICAL_SECTIONS) +#define GCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define GCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define GCLK_CRITICAL_SECTION_ENTER() +#define GCLK_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_gclk_genctrl_reg_t; +typedef uint32_t hri_gclk_pchctrl_reg_t; +typedef uint32_t hri_gclk_syncbusy_reg_t; +typedef uint8_t hri_gclk_ctrla_reg_t; + +static inline void hri_gclk_wait_for_sync(const void *const hw, hri_gclk_syncbusy_reg_t reg) +{ + while (((Gclk *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_gclk_is_syncing(const void *const hw, hri_gclk_syncbusy_reg_t reg) +{ + return ((Gclk *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_gclk_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) >> GCLK_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL0_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL0) >> GCLK_SYNCBUSY_GENCTRL0_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL1_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL1) >> GCLK_SYNCBUSY_GENCTRL1_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL2_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL2) >> GCLK_SYNCBUSY_GENCTRL2_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL3_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL3) >> GCLK_SYNCBUSY_GENCTRL3_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL4_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL4) >> GCLK_SYNCBUSY_GENCTRL4_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL5_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL5) >> GCLK_SYNCBUSY_GENCTRL5_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL6_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL6) >> GCLK_SYNCBUSY_GENCTRL6_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL7_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL7) >> GCLK_SYNCBUSY_GENCTRL7_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL8_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL8) >> GCLK_SYNCBUSY_GENCTRL8_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL9_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL9) >> GCLK_SYNCBUSY_GENCTRL9_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL10_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL10) >> GCLK_SYNCBUSY_GENCTRL10_Pos; +} + +static inline bool hri_gclk_get_SYNCBUSY_GENCTRL11_bit(const void *const hw) +{ + return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL11) >> GCLK_SYNCBUSY_GENCTRL11_Pos; +} + +static inline hri_gclk_syncbusy_reg_t hri_gclk_get_SYNCBUSY_reg(const void *const hw, hri_gclk_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gclk_syncbusy_reg_t hri_gclk_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Gclk *)hw)->SYNCBUSY.reg; +} + +static inline void hri_gclk_set_CTRLA_SWRST_bit(const void *const hw) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg |= GCLK_CTRLA_SWRST; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + tmp = ((Gclk *)hw)->CTRLA.reg; + tmp = (tmp & GCLK_CTRLA_SWRST) >> GCLK_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_set_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg |= mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_ctrla_reg_t hri_gclk_get_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + tmp = ((Gclk *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gclk_write_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t data) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg = data; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg &= ~mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->CTRLA.reg ^= mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_ctrla_reg_t hri_gclk_read_CTRLA_reg(const void *const hw) +{ + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST); + return ((Gclk *)hw)->CTRLA.reg; +} + +static inline void hri_gclk_set_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_GENEN; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_GENEN) >> GCLK_GENCTRL_GENEN_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_GENEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_GENEN; + tmp |= value << GCLK_GENCTRL_GENEN_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_GENEN; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_GENEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_GENEN; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_IDC; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_IDC) >> GCLK_GENCTRL_IDC_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_IDC_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_IDC; + tmp |= value << GCLK_GENCTRL_IDC_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_IDC; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_IDC_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_IDC; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OOV; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_OOV) >> GCLK_GENCTRL_OOV_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_OOV_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_OOV; + tmp |= value << GCLK_GENCTRL_OOV_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OOV; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_OOV_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OOV; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OE; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_OE) >> GCLK_GENCTRL_OE_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_OE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_OE; + tmp |= value << GCLK_GENCTRL_OE_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OE; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_OE_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OE; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIVSEL; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_DIVSEL) >> GCLK_GENCTRL_DIVSEL_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_DIVSEL; + tmp |= value << GCLK_GENCTRL_DIVSEL_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIVSEL; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIVSEL; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_RUNSTDBY; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_RUNSTDBY) >> GCLK_GENCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_RUNSTDBY; + tmp |= value << GCLK_GENCTRL_RUNSTDBY_Pos; + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_RUNSTDBY; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_RUNSTDBY; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_SRC(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_SRC_bf(const void *const hw, uint8_t index, + hri_gclk_genctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_SRC(mask)) >> GCLK_GENCTRL_SRC_Pos; + return tmp; +} + +static inline void hri_gclk_write_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_SRC_Msk; + tmp |= GCLK_GENCTRL_SRC(data); + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_SRC(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_SRC(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_SRC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_SRC_Msk) >> GCLK_GENCTRL_SRC_Pos; + return tmp; +} + +static inline void hri_gclk_set_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIV(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_DIV_bf(const void *const hw, uint8_t index, + hri_gclk_genctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_DIV(mask)) >> GCLK_GENCTRL_DIV_Pos; + return tmp; +} + +static inline void hri_gclk_write_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= ~GCLK_GENCTRL_DIV_Msk; + tmp |= GCLK_GENCTRL_DIV(data); + ((Gclk *)hw)->GENCTRL[index].reg = tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIV(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIV(mask); + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_DIV_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp = (tmp & GCLK_GENCTRL_DIV_Msk) >> GCLK_GENCTRL_DIV_Pos; + return tmp; +} + +static inline void hri_gclk_set_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg |= mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_reg(const void *const hw, uint8_t index, + hri_gclk_genctrl_reg_t mask) +{ + uint32_t tmp; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + tmp = ((Gclk *)hw)->GENCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gclk_write_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg = data; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg &= ~mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->GENCTRL[index].reg ^= mask; + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_reg(const void *const hw, uint8_t index) +{ + hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK); + return ((Gclk *)hw)->GENCTRL[index].reg; +} + +static inline void hri_gclk_set_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_CHEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_CHEN) >> GCLK_PCHCTRL_CHEN_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= ~GCLK_PCHCTRL_CHEN; + tmp |= value << GCLK_PCHCTRL_CHEN_Pos; + ((Gclk *)hw)->PCHCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_CHEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_CHEN; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_WRTLOCK; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_gclk_get_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_WRTLOCK) >> GCLK_PCHCTRL_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_gclk_write_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= ~GCLK_PCHCTRL_WRTLOCK; + tmp |= value << GCLK_PCHCTRL_WRTLOCK_Pos; + ((Gclk *)hw)->PCHCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_WRTLOCK; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_WRTLOCK; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_set_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_GEN(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, + hri_gclk_pchctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_GEN(mask)) >> GCLK_PCHCTRL_GEN_Pos; + return tmp; +} + +static inline void hri_gclk_write_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data) +{ + uint32_t tmp; + GCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= ~GCLK_PCHCTRL_GEN_Msk; + tmp |= GCLK_PCHCTRL_GEN(data); + ((Gclk *)hw)->PCHCTRL[index].reg = tmp; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_GEN(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_GEN(mask); + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_GEN_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp = (tmp & GCLK_PCHCTRL_GEN_Msk) >> GCLK_PCHCTRL_GEN_Pos; + return tmp; +} + +static inline void hri_gclk_set_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg |= mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_reg(const void *const hw, uint8_t index, + hri_gclk_pchctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gclk *)hw)->PCHCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gclk_write_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg = data; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_clear_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg &= ~mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gclk_toggle_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask) +{ + GCLK_CRITICAL_SECTION_ENTER(); + ((Gclk *)hw)->PCHCTRL[index].reg ^= mask; + GCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Gclk *)hw)->PCHCTRL[index].reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_GCLK_E54_H_INCLUDED */ +#endif /* _SAME54_GCLK_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_gmac_e54.h b/software/firmware/oracle_same54n19a/hri/hri_gmac_e54.h new file mode 100644 index 00000000..28750610 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_gmac_e54.h @@ -0,0 +1,3766 @@ +/** + * \file + * + * \brief SAM GMAC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_GMAC_COMPONENT_ +#ifndef _HRI_GMAC_E54_H_INCLUDED_ +#define _HRI_GMAC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_GMAC_CRITICAL_SECTIONS) +#define GMAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define GMAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define GMAC_CRITICAL_SECTION_ENTER() +#define GMAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_gmac_ae_reg_t; +typedef uint32_t hri_gmac_bcfr_reg_t; +typedef uint32_t hri_gmac_bcft_reg_t; +typedef uint32_t hri_gmac_bfr64_reg_t; +typedef uint32_t hri_gmac_bft64_reg_t; +typedef uint32_t hri_gmac_cse_reg_t; +typedef uint32_t hri_gmac_dcfgr_reg_t; +typedef uint32_t hri_gmac_dtf_reg_t; +typedef uint32_t hri_gmac_ec_reg_t; +typedef uint32_t hri_gmac_efrn_reg_t; +typedef uint32_t hri_gmac_efrsh_reg_t; +typedef uint32_t hri_gmac_efrsl_reg_t; +typedef uint32_t hri_gmac_eftn_reg_t; +typedef uint32_t hri_gmac_eftsh_reg_t; +typedef uint32_t hri_gmac_eftsl_reg_t; +typedef uint32_t hri_gmac_fcse_reg_t; +typedef uint32_t hri_gmac_fr_reg_t; +typedef uint32_t hri_gmac_ft_reg_t; +typedef uint32_t hri_gmac_gtbft1518_reg_t; +typedef uint32_t hri_gmac_hrb_reg_t; +typedef uint32_t hri_gmac_hrt_reg_t; +typedef uint32_t hri_gmac_ihce_reg_t; +typedef uint32_t hri_gmac_imr_reg_t; +typedef uint32_t hri_gmac_ipgs_reg_t; +typedef uint32_t hri_gmac_isr_reg_t; +typedef uint32_t hri_gmac_jr_reg_t; +typedef uint32_t hri_gmac_lc_reg_t; +typedef uint32_t hri_gmac_lffe_reg_t; +typedef uint32_t hri_gmac_man_reg_t; +typedef uint32_t hri_gmac_mcf_reg_t; +typedef uint32_t hri_gmac_mfr_reg_t; +typedef uint32_t hri_gmac_mft_reg_t; +typedef uint32_t hri_gmac_ncfgr_reg_t; +typedef uint32_t hri_gmac_ncr_reg_t; +typedef uint32_t hri_gmac_nsc_reg_t; +typedef uint32_t hri_gmac_nsr_reg_t; +typedef uint32_t hri_gmac_ofr_reg_t; +typedef uint32_t hri_gmac_orhi_reg_t; +typedef uint32_t hri_gmac_orlo_reg_t; +typedef uint32_t hri_gmac_othi_reg_t; +typedef uint32_t hri_gmac_otlo_reg_t; +typedef uint32_t hri_gmac_pefrn_reg_t; +typedef uint32_t hri_gmac_pefrsh_reg_t; +typedef uint32_t hri_gmac_pefrsl_reg_t; +typedef uint32_t hri_gmac_peftn_reg_t; +typedef uint32_t hri_gmac_peftsh_reg_t; +typedef uint32_t hri_gmac_peftsl_reg_t; +typedef uint32_t hri_gmac_pfr_reg_t; +typedef uint32_t hri_gmac_pft_reg_t; +typedef uint32_t hri_gmac_rbqb_reg_t; +typedef uint32_t hri_gmac_rjfml_reg_t; +typedef uint32_t hri_gmac_rlpiti_reg_t; +typedef uint32_t hri_gmac_rlpitr_reg_t; +typedef uint32_t hri_gmac_roe_reg_t; +typedef uint32_t hri_gmac_rpq_reg_t; +typedef uint32_t hri_gmac_rpsf_reg_t; +typedef uint32_t hri_gmac_rre_reg_t; +typedef uint32_t hri_gmac_rse_reg_t; +typedef uint32_t hri_gmac_rsr_reg_t; +typedef uint32_t hri_gmac_sab_reg_t; +typedef uint32_t hri_gmac_samb1_reg_t; +typedef uint32_t hri_gmac_samt1_reg_t; +typedef uint32_t hri_gmac_sat_reg_t; +typedef uint32_t hri_gmac_scf_reg_t; +typedef uint32_t hri_gmac_sch_reg_t; +typedef uint32_t hri_gmac_scl_reg_t; +typedef uint32_t hri_gmac_svlan_reg_t; +typedef uint32_t hri_gmac_ta_reg_t; +typedef uint32_t hri_gmac_tbfr1023_reg_t; +typedef uint32_t hri_gmac_tbfr127_reg_t; +typedef uint32_t hri_gmac_tbfr1518_reg_t; +typedef uint32_t hri_gmac_tbfr255_reg_t; +typedef uint32_t hri_gmac_tbfr511_reg_t; +typedef uint32_t hri_gmac_tbft1023_reg_t; +typedef uint32_t hri_gmac_tbft127_reg_t; +typedef uint32_t hri_gmac_tbft1518_reg_t; +typedef uint32_t hri_gmac_tbft255_reg_t; +typedef uint32_t hri_gmac_tbft511_reg_t; +typedef uint32_t hri_gmac_tbqb_reg_t; +typedef uint32_t hri_gmac_tce_reg_t; +typedef uint32_t hri_gmac_ti_reg_t; +typedef uint32_t hri_gmac_tidm_reg_t; +typedef uint32_t hri_gmac_tisubn_reg_t; +typedef uint32_t hri_gmac_tlpiti_reg_t; +typedef uint32_t hri_gmac_tlpitr_reg_t; +typedef uint32_t hri_gmac_tmxbfr_reg_t; +typedef uint32_t hri_gmac_tn_reg_t; +typedef uint32_t hri_gmac_tpfcp_reg_t; +typedef uint32_t hri_gmac_tpq_reg_t; +typedef uint32_t hri_gmac_tpsf_reg_t; +typedef uint32_t hri_gmac_tsh_reg_t; +typedef uint32_t hri_gmac_tsl_reg_t; +typedef uint32_t hri_gmac_tsr_reg_t; +typedef uint32_t hri_gmac_tssn_reg_t; +typedef uint32_t hri_gmac_tsssl_reg_t; +typedef uint32_t hri_gmac_tur_reg_t; +typedef uint32_t hri_gmac_uce_reg_t; +typedef uint32_t hri_gmac_ufr_reg_t; +typedef uint32_t hri_gmac_ur_reg_t; +typedef uint32_t hri_gmac_wol_reg_t; +typedef uint32_t hri_gmacsa_sab_reg_t; +typedef uint32_t hri_gmacsa_sat_reg_t; + +static inline void hri_gmacsa_set_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->SAB.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sab_reg_t hri_gmacsa_get_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask) +{ + uint32_t tmp; + tmp = ((GmacSa *)hw)->SAB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmacsa_write_SAB_reg(const void *const hw, hri_gmac_sab_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->SAB.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacsa_clear_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->SAB.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacsa_toggle_SAB_reg(const void *const hw, hri_gmac_sab_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->SAB.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sab_reg_t hri_gmacsa_read_SAB_reg(const void *const hw) +{ + return ((GmacSa *)hw)->SAB.reg; +} + +static inline void hri_gmacsa_set_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->SAT.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sat_reg_t hri_gmacsa_get_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask) +{ + uint32_t tmp; + tmp = ((GmacSa *)hw)->SAT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmacsa_write_SAT_reg(const void *const hw, hri_gmac_sat_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->SAT.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacsa_clear_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->SAT.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmacsa_toggle_SAT_reg(const void *const hw, hri_gmac_sat_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((GmacSa *)hw)->SAT.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sat_reg_t hri_gmacsa_read_SAT_reg(const void *const hw) +{ + return ((GmacSa *)hw)->SAT.reg; +} + +static inline void hri_gmac_set_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->Sa[submodule_index].SAB.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sab_reg_t hri_gmac_get_SAB_reg(const void *const hw, uint8_t submodule_index, + hri_gmac_sab_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->Sa[submodule_index].SAB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->Sa[submodule_index].SAB.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->Sa[submodule_index].SAB.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SAB_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sab_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->Sa[submodule_index].SAB.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sab_reg_t hri_gmac_read_SAB_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Gmac *)hw)->Sa[submodule_index].SAB.reg; +} + +static inline void hri_gmac_set_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->Sa[submodule_index].SAT.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sat_reg_t hri_gmac_get_SAT_reg(const void *const hw, uint8_t submodule_index, + hri_gmac_sat_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->Sa[submodule_index].SAT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->Sa[submodule_index].SAT.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->Sa[submodule_index].SAT.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SAT_reg(const void *const hw, uint8_t submodule_index, hri_gmac_sat_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->Sa[submodule_index].SAT.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sat_reg_t hri_gmac_read_SAT_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Gmac *)hw)->Sa[submodule_index].SAT.reg; +} + +static inline void hri_gmac_set_IMR_MFS_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_MFS; +} + +static inline bool hri_gmac_get_IMR_MFS_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_MFS) >> GMAC_IMR_MFS_Pos; +} + +static inline void hri_gmac_write_IMR_MFS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_MFS; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_MFS; + } +} + +static inline void hri_gmac_clear_IMR_MFS_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_MFS; +} + +static inline void hri_gmac_set_IMR_RCOMP_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_RCOMP; +} + +static inline bool hri_gmac_get_IMR_RCOMP_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_RCOMP) >> GMAC_IMR_RCOMP_Pos; +} + +static inline void hri_gmac_write_IMR_RCOMP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_RCOMP; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_RCOMP; + } +} + +static inline void hri_gmac_clear_IMR_RCOMP_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_RCOMP; +} + +static inline void hri_gmac_set_IMR_RXUBR_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_RXUBR; +} + +static inline bool hri_gmac_get_IMR_RXUBR_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_RXUBR) >> GMAC_IMR_RXUBR_Pos; +} + +static inline void hri_gmac_write_IMR_RXUBR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_RXUBR; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_RXUBR; + } +} + +static inline void hri_gmac_clear_IMR_RXUBR_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_RXUBR; +} + +static inline void hri_gmac_set_IMR_TXUBR_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_TXUBR; +} + +static inline bool hri_gmac_get_IMR_TXUBR_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TXUBR) >> GMAC_IMR_TXUBR_Pos; +} + +static inline void hri_gmac_write_IMR_TXUBR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TXUBR; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_TXUBR; + } +} + +static inline void hri_gmac_clear_IMR_TXUBR_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TXUBR; +} + +static inline void hri_gmac_set_IMR_TUR_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_TUR; +} + +static inline bool hri_gmac_get_IMR_TUR_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TUR) >> GMAC_IMR_TUR_Pos; +} + +static inline void hri_gmac_write_IMR_TUR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TUR; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_TUR; + } +} + +static inline void hri_gmac_clear_IMR_TUR_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TUR; +} + +static inline void hri_gmac_set_IMR_RLEX_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_RLEX; +} + +static inline bool hri_gmac_get_IMR_RLEX_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_RLEX) >> GMAC_IMR_RLEX_Pos; +} + +static inline void hri_gmac_write_IMR_RLEX_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_RLEX; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_RLEX; + } +} + +static inline void hri_gmac_clear_IMR_RLEX_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_RLEX; +} + +static inline void hri_gmac_set_IMR_TFC_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_TFC; +} + +static inline bool hri_gmac_get_IMR_TFC_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TFC) >> GMAC_IMR_TFC_Pos; +} + +static inline void hri_gmac_write_IMR_TFC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TFC; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_TFC; + } +} + +static inline void hri_gmac_clear_IMR_TFC_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TFC; +} + +static inline void hri_gmac_set_IMR_TCOMP_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_TCOMP; +} + +static inline bool hri_gmac_get_IMR_TCOMP_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TCOMP) >> GMAC_IMR_TCOMP_Pos; +} + +static inline void hri_gmac_write_IMR_TCOMP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TCOMP; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_TCOMP; + } +} + +static inline void hri_gmac_clear_IMR_TCOMP_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TCOMP; +} + +static inline void hri_gmac_set_IMR_ROVR_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_ROVR; +} + +static inline bool hri_gmac_get_IMR_ROVR_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_ROVR) >> GMAC_IMR_ROVR_Pos; +} + +static inline void hri_gmac_write_IMR_ROVR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_ROVR; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_ROVR; + } +} + +static inline void hri_gmac_clear_IMR_ROVR_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_ROVR; +} + +static inline void hri_gmac_set_IMR_HRESP_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_HRESP; +} + +static inline bool hri_gmac_get_IMR_HRESP_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_HRESP) >> GMAC_IMR_HRESP_Pos; +} + +static inline void hri_gmac_write_IMR_HRESP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_HRESP; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_HRESP; + } +} + +static inline void hri_gmac_clear_IMR_HRESP_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_HRESP; +} + +static inline void hri_gmac_set_IMR_PFNZ_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_PFNZ; +} + +static inline bool hri_gmac_get_IMR_PFNZ_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PFNZ) >> GMAC_IMR_PFNZ_Pos; +} + +static inline void hri_gmac_write_IMR_PFNZ_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PFNZ; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_PFNZ; + } +} + +static inline void hri_gmac_clear_IMR_PFNZ_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PFNZ; +} + +static inline void hri_gmac_set_IMR_PTZ_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_PTZ; +} + +static inline bool hri_gmac_get_IMR_PTZ_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PTZ) >> GMAC_IMR_PTZ_Pos; +} + +static inline void hri_gmac_write_IMR_PTZ_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PTZ; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_PTZ; + } +} + +static inline void hri_gmac_clear_IMR_PTZ_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PTZ; +} + +static inline void hri_gmac_set_IMR_PFTR_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_PFTR; +} + +static inline bool hri_gmac_get_IMR_PFTR_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PFTR) >> GMAC_IMR_PFTR_Pos; +} + +static inline void hri_gmac_write_IMR_PFTR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PFTR; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_PFTR; + } +} + +static inline void hri_gmac_clear_IMR_PFTR_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PFTR; +} + +static inline void hri_gmac_set_IMR_EXINT_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_EXINT; +} + +static inline bool hri_gmac_get_IMR_EXINT_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_EXINT) >> GMAC_IMR_EXINT_Pos; +} + +static inline void hri_gmac_write_IMR_EXINT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_EXINT; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_EXINT; + } +} + +static inline void hri_gmac_clear_IMR_EXINT_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_EXINT; +} + +static inline void hri_gmac_set_IMR_DRQFR_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_DRQFR; +} + +static inline bool hri_gmac_get_IMR_DRQFR_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_DRQFR) >> GMAC_IMR_DRQFR_Pos; +} + +static inline void hri_gmac_write_IMR_DRQFR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_DRQFR; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_DRQFR; + } +} + +static inline void hri_gmac_clear_IMR_DRQFR_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_DRQFR; +} + +static inline void hri_gmac_set_IMR_SFR_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_SFR; +} + +static inline bool hri_gmac_get_IMR_SFR_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_SFR) >> GMAC_IMR_SFR_Pos; +} + +static inline void hri_gmac_write_IMR_SFR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_SFR; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_SFR; + } +} + +static inline void hri_gmac_clear_IMR_SFR_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_SFR; +} + +static inline void hri_gmac_set_IMR_DRQFT_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_DRQFT; +} + +static inline bool hri_gmac_get_IMR_DRQFT_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_DRQFT) >> GMAC_IMR_DRQFT_Pos; +} + +static inline void hri_gmac_write_IMR_DRQFT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_DRQFT; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_DRQFT; + } +} + +static inline void hri_gmac_clear_IMR_DRQFT_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_DRQFT; +} + +static inline void hri_gmac_set_IMR_SFT_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_SFT; +} + +static inline bool hri_gmac_get_IMR_SFT_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_SFT) >> GMAC_IMR_SFT_Pos; +} + +static inline void hri_gmac_write_IMR_SFT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_SFT; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_SFT; + } +} + +static inline void hri_gmac_clear_IMR_SFT_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_SFT; +} + +static inline void hri_gmac_set_IMR_PDRQFR_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRQFR; +} + +static inline bool hri_gmac_get_IMR_PDRQFR_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PDRQFR) >> GMAC_IMR_PDRQFR_Pos; +} + +static inline void hri_gmac_write_IMR_PDRQFR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRQFR; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRQFR; + } +} + +static inline void hri_gmac_clear_IMR_PDRQFR_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRQFR; +} + +static inline void hri_gmac_set_IMR_PDRSFR_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRSFR; +} + +static inline bool hri_gmac_get_IMR_PDRSFR_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PDRSFR) >> GMAC_IMR_PDRSFR_Pos; +} + +static inline void hri_gmac_write_IMR_PDRSFR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRSFR; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRSFR; + } +} + +static inline void hri_gmac_clear_IMR_PDRSFR_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRSFR; +} + +static inline void hri_gmac_set_IMR_PDRQFT_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRQFT; +} + +static inline bool hri_gmac_get_IMR_PDRQFT_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PDRQFT) >> GMAC_IMR_PDRQFT_Pos; +} + +static inline void hri_gmac_write_IMR_PDRQFT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRQFT; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRQFT; + } +} + +static inline void hri_gmac_clear_IMR_PDRQFT_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRQFT; +} + +static inline void hri_gmac_set_IMR_PDRSFT_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRSFT; +} + +static inline bool hri_gmac_get_IMR_PDRSFT_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_PDRSFT) >> GMAC_IMR_PDRSFT_Pos; +} + +static inline void hri_gmac_write_IMR_PDRSFT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRSFT; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_PDRSFT; + } +} + +static inline void hri_gmac_clear_IMR_PDRSFT_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_PDRSFT; +} + +static inline void hri_gmac_set_IMR_SRI_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_SRI; +} + +static inline bool hri_gmac_get_IMR_SRI_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_SRI) >> GMAC_IMR_SRI_Pos; +} + +static inline void hri_gmac_write_IMR_SRI_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_SRI; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_SRI; + } +} + +static inline void hri_gmac_clear_IMR_SRI_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_SRI; +} + +static inline void hri_gmac_set_IMR_WOL_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_WOL; +} + +static inline bool hri_gmac_get_IMR_WOL_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_WOL) >> GMAC_IMR_WOL_Pos; +} + +static inline void hri_gmac_write_IMR_WOL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_WOL; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_WOL; + } +} + +static inline void hri_gmac_clear_IMR_WOL_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_WOL; +} + +static inline void hri_gmac_set_IMR_TSUCMP_bit(const void *const hw) +{ + ((Gmac *)hw)->IER.reg = GMAC_IMR_TSUCMP; +} + +static inline bool hri_gmac_get_IMR_TSUCMP_bit(const void *const hw) +{ + return (((Gmac *)hw)->IMR.reg & GMAC_IMR_TSUCMP) >> GMAC_IMR_TSUCMP_Pos; +} + +static inline void hri_gmac_write_IMR_TSUCMP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TSUCMP; + } else { + ((Gmac *)hw)->IER.reg = GMAC_IMR_TSUCMP; + } +} + +static inline void hri_gmac_clear_IMR_TSUCMP_bit(const void *const hw) +{ + ((Gmac *)hw)->IDR.reg = GMAC_IMR_TSUCMP; +} + +static inline void hri_gmac_set_IMR_reg(const void *const hw, hri_gmac_imr_reg_t mask) +{ + ((Gmac *)hw)->IER.reg = mask; +} + +static inline hri_gmac_imr_reg_t hri_gmac_get_IMR_reg(const void *const hw, hri_gmac_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->IMR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_imr_reg_t hri_gmac_read_IMR_reg(const void *const hw) +{ + return ((Gmac *)hw)->IMR.reg; +} + +static inline void hri_gmac_write_IMR_reg(const void *const hw, hri_gmac_imr_reg_t data) +{ + ((Gmac *)hw)->IER.reg = data; + ((Gmac *)hw)->IDR.reg = ~data; +} + +static inline void hri_gmac_clear_IMR_reg(const void *const hw, hri_gmac_imr_reg_t mask) +{ + ((Gmac *)hw)->IDR.reg = mask; +} + +static inline bool hri_gmac_get_NSR_MDIO_bit(const void *const hw) +{ + return (((Gmac *)hw)->NSR.reg & GMAC_NSR_MDIO) >> GMAC_NSR_MDIO_Pos; +} + +static inline bool hri_gmac_get_NSR_IDLE_bit(const void *const hw) +{ + return (((Gmac *)hw)->NSR.reg & GMAC_NSR_IDLE) >> GMAC_NSR_IDLE_Pos; +} + +static inline hri_gmac_nsr_reg_t hri_gmac_get_NSR_reg(const void *const hw, hri_gmac_nsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->NSR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_nsr_reg_t hri_gmac_read_NSR_reg(const void *const hw) +{ + return ((Gmac *)hw)->NSR.reg; +} + +static inline hri_gmac_rpq_reg_t hri_gmac_get_RPQ_RPQ_bf(const void *const hw, hri_gmac_rpq_reg_t mask) +{ + return (((Gmac *)hw)->RPQ.reg & GMAC_RPQ_RPQ(mask)) >> GMAC_RPQ_RPQ_Pos; +} + +static inline hri_gmac_rpq_reg_t hri_gmac_read_RPQ_RPQ_bf(const void *const hw) +{ + return (((Gmac *)hw)->RPQ.reg & GMAC_RPQ_RPQ_Msk) >> GMAC_RPQ_RPQ_Pos; +} + +static inline hri_gmac_rpq_reg_t hri_gmac_get_RPQ_reg(const void *const hw, hri_gmac_rpq_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->RPQ.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_rpq_reg_t hri_gmac_read_RPQ_reg(const void *const hw) +{ + return ((Gmac *)hw)->RPQ.reg; +} + +static inline hri_gmac_eftsh_reg_t hri_gmac_get_EFTSH_RUD_bf(const void *const hw, hri_gmac_eftsh_reg_t mask) +{ + return (((Gmac *)hw)->EFTSH.reg & GMAC_EFTSH_RUD(mask)) >> GMAC_EFTSH_RUD_Pos; +} + +static inline hri_gmac_eftsh_reg_t hri_gmac_read_EFTSH_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->EFTSH.reg & GMAC_EFTSH_RUD_Msk) >> GMAC_EFTSH_RUD_Pos; +} + +static inline hri_gmac_eftsh_reg_t hri_gmac_get_EFTSH_reg(const void *const hw, hri_gmac_eftsh_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->EFTSH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_eftsh_reg_t hri_gmac_read_EFTSH_reg(const void *const hw) +{ + return ((Gmac *)hw)->EFTSH.reg; +} + +static inline hri_gmac_efrsh_reg_t hri_gmac_get_EFRSH_RUD_bf(const void *const hw, hri_gmac_efrsh_reg_t mask) +{ + return (((Gmac *)hw)->EFRSH.reg & GMAC_EFRSH_RUD(mask)) >> GMAC_EFRSH_RUD_Pos; +} + +static inline hri_gmac_efrsh_reg_t hri_gmac_read_EFRSH_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->EFRSH.reg & GMAC_EFRSH_RUD_Msk) >> GMAC_EFRSH_RUD_Pos; +} + +static inline hri_gmac_efrsh_reg_t hri_gmac_get_EFRSH_reg(const void *const hw, hri_gmac_efrsh_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->EFRSH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_efrsh_reg_t hri_gmac_read_EFRSH_reg(const void *const hw) +{ + return ((Gmac *)hw)->EFRSH.reg; +} + +static inline hri_gmac_peftsh_reg_t hri_gmac_get_PEFTSH_RUD_bf(const void *const hw, hri_gmac_peftsh_reg_t mask) +{ + return (((Gmac *)hw)->PEFTSH.reg & GMAC_PEFTSH_RUD(mask)) >> GMAC_PEFTSH_RUD_Pos; +} + +static inline hri_gmac_peftsh_reg_t hri_gmac_read_PEFTSH_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->PEFTSH.reg & GMAC_PEFTSH_RUD_Msk) >> GMAC_PEFTSH_RUD_Pos; +} + +static inline hri_gmac_peftsh_reg_t hri_gmac_get_PEFTSH_reg(const void *const hw, hri_gmac_peftsh_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->PEFTSH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_peftsh_reg_t hri_gmac_read_PEFTSH_reg(const void *const hw) +{ + return ((Gmac *)hw)->PEFTSH.reg; +} + +static inline hri_gmac_pefrsh_reg_t hri_gmac_get_PEFRSH_RUD_bf(const void *const hw, hri_gmac_pefrsh_reg_t mask) +{ + return (((Gmac *)hw)->PEFRSH.reg & GMAC_PEFRSH_RUD(mask)) >> GMAC_PEFRSH_RUD_Pos; +} + +static inline hri_gmac_pefrsh_reg_t hri_gmac_read_PEFRSH_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->PEFRSH.reg & GMAC_PEFRSH_RUD_Msk) >> GMAC_PEFRSH_RUD_Pos; +} + +static inline hri_gmac_pefrsh_reg_t hri_gmac_get_PEFRSH_reg(const void *const hw, hri_gmac_pefrsh_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->PEFRSH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_pefrsh_reg_t hri_gmac_read_PEFRSH_reg(const void *const hw) +{ + return ((Gmac *)hw)->PEFRSH.reg; +} + +static inline hri_gmac_otlo_reg_t hri_gmac_get_OTLO_TXO_bf(const void *const hw, hri_gmac_otlo_reg_t mask) +{ + return (((Gmac *)hw)->OTLO.reg & GMAC_OTLO_TXO(mask)) >> GMAC_OTLO_TXO_Pos; +} + +static inline hri_gmac_otlo_reg_t hri_gmac_read_OTLO_TXO_bf(const void *const hw) +{ + return (((Gmac *)hw)->OTLO.reg & GMAC_OTLO_TXO_Msk) >> GMAC_OTLO_TXO_Pos; +} + +static inline hri_gmac_otlo_reg_t hri_gmac_get_OTLO_reg(const void *const hw, hri_gmac_otlo_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->OTLO.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_otlo_reg_t hri_gmac_read_OTLO_reg(const void *const hw) +{ + return ((Gmac *)hw)->OTLO.reg; +} + +static inline hri_gmac_othi_reg_t hri_gmac_get_OTHI_TXO_bf(const void *const hw, hri_gmac_othi_reg_t mask) +{ + return (((Gmac *)hw)->OTHI.reg & GMAC_OTHI_TXO(mask)) >> GMAC_OTHI_TXO_Pos; +} + +static inline hri_gmac_othi_reg_t hri_gmac_read_OTHI_TXO_bf(const void *const hw) +{ + return (((Gmac *)hw)->OTHI.reg & GMAC_OTHI_TXO_Msk) >> GMAC_OTHI_TXO_Pos; +} + +static inline hri_gmac_othi_reg_t hri_gmac_get_OTHI_reg(const void *const hw, hri_gmac_othi_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->OTHI.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_othi_reg_t hri_gmac_read_OTHI_reg(const void *const hw) +{ + return ((Gmac *)hw)->OTHI.reg; +} + +static inline hri_gmac_ft_reg_t hri_gmac_get_FT_FTX_bf(const void *const hw, hri_gmac_ft_reg_t mask) +{ + return (((Gmac *)hw)->FT.reg & GMAC_FT_FTX(mask)) >> GMAC_FT_FTX_Pos; +} + +static inline hri_gmac_ft_reg_t hri_gmac_read_FT_FTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->FT.reg & GMAC_FT_FTX_Msk) >> GMAC_FT_FTX_Pos; +} + +static inline hri_gmac_ft_reg_t hri_gmac_get_FT_reg(const void *const hw, hri_gmac_ft_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->FT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_ft_reg_t hri_gmac_read_FT_reg(const void *const hw) +{ + return ((Gmac *)hw)->FT.reg; +} + +static inline hri_gmac_bcft_reg_t hri_gmac_get_BCFT_BFTX_bf(const void *const hw, hri_gmac_bcft_reg_t mask) +{ + return (((Gmac *)hw)->BCFT.reg & GMAC_BCFT_BFTX(mask)) >> GMAC_BCFT_BFTX_Pos; +} + +static inline hri_gmac_bcft_reg_t hri_gmac_read_BCFT_BFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->BCFT.reg & GMAC_BCFT_BFTX_Msk) >> GMAC_BCFT_BFTX_Pos; +} + +static inline hri_gmac_bcft_reg_t hri_gmac_get_BCFT_reg(const void *const hw, hri_gmac_bcft_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->BCFT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_bcft_reg_t hri_gmac_read_BCFT_reg(const void *const hw) +{ + return ((Gmac *)hw)->BCFT.reg; +} + +static inline hri_gmac_mft_reg_t hri_gmac_get_MFT_MFTX_bf(const void *const hw, hri_gmac_mft_reg_t mask) +{ + return (((Gmac *)hw)->MFT.reg & GMAC_MFT_MFTX(mask)) >> GMAC_MFT_MFTX_Pos; +} + +static inline hri_gmac_mft_reg_t hri_gmac_read_MFT_MFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->MFT.reg & GMAC_MFT_MFTX_Msk) >> GMAC_MFT_MFTX_Pos; +} + +static inline hri_gmac_mft_reg_t hri_gmac_get_MFT_reg(const void *const hw, hri_gmac_mft_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->MFT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_mft_reg_t hri_gmac_read_MFT_reg(const void *const hw) +{ + return ((Gmac *)hw)->MFT.reg; +} + +static inline hri_gmac_pft_reg_t hri_gmac_get_PFT_PFTX_bf(const void *const hw, hri_gmac_pft_reg_t mask) +{ + return (((Gmac *)hw)->PFT.reg & GMAC_PFT_PFTX(mask)) >> GMAC_PFT_PFTX_Pos; +} + +static inline hri_gmac_pft_reg_t hri_gmac_read_PFT_PFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->PFT.reg & GMAC_PFT_PFTX_Msk) >> GMAC_PFT_PFTX_Pos; +} + +static inline hri_gmac_pft_reg_t hri_gmac_get_PFT_reg(const void *const hw, hri_gmac_pft_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->PFT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_pft_reg_t hri_gmac_read_PFT_reg(const void *const hw) +{ + return ((Gmac *)hw)->PFT.reg; +} + +static inline hri_gmac_bft64_reg_t hri_gmac_get_BFT64_NFTX_bf(const void *const hw, hri_gmac_bft64_reg_t mask) +{ + return (((Gmac *)hw)->BFT64.reg & GMAC_BFT64_NFTX(mask)) >> GMAC_BFT64_NFTX_Pos; +} + +static inline hri_gmac_bft64_reg_t hri_gmac_read_BFT64_NFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->BFT64.reg & GMAC_BFT64_NFTX_Msk) >> GMAC_BFT64_NFTX_Pos; +} + +static inline hri_gmac_bft64_reg_t hri_gmac_get_BFT64_reg(const void *const hw, hri_gmac_bft64_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->BFT64.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_bft64_reg_t hri_gmac_read_BFT64_reg(const void *const hw) +{ + return ((Gmac *)hw)->BFT64.reg; +} + +static inline hri_gmac_tbft127_reg_t hri_gmac_get_TBFT127_NFTX_bf(const void *const hw, hri_gmac_tbft127_reg_t mask) +{ + return (((Gmac *)hw)->TBFT127.reg & GMAC_TBFT127_NFTX(mask)) >> GMAC_TBFT127_NFTX_Pos; +} + +static inline hri_gmac_tbft127_reg_t hri_gmac_read_TBFT127_NFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFT127.reg & GMAC_TBFT127_NFTX_Msk) >> GMAC_TBFT127_NFTX_Pos; +} + +static inline hri_gmac_tbft127_reg_t hri_gmac_get_TBFT127_reg(const void *const hw, hri_gmac_tbft127_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFT127.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbft127_reg_t hri_gmac_read_TBFT127_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFT127.reg; +} + +static inline hri_gmac_tbft255_reg_t hri_gmac_get_TBFT255_NFTX_bf(const void *const hw, hri_gmac_tbft255_reg_t mask) +{ + return (((Gmac *)hw)->TBFT255.reg & GMAC_TBFT255_NFTX(mask)) >> GMAC_TBFT255_NFTX_Pos; +} + +static inline hri_gmac_tbft255_reg_t hri_gmac_read_TBFT255_NFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFT255.reg & GMAC_TBFT255_NFTX_Msk) >> GMAC_TBFT255_NFTX_Pos; +} + +static inline hri_gmac_tbft255_reg_t hri_gmac_get_TBFT255_reg(const void *const hw, hri_gmac_tbft255_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFT255.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbft255_reg_t hri_gmac_read_TBFT255_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFT255.reg; +} + +static inline hri_gmac_tbft511_reg_t hri_gmac_get_TBFT511_NFTX_bf(const void *const hw, hri_gmac_tbft511_reg_t mask) +{ + return (((Gmac *)hw)->TBFT511.reg & GMAC_TBFT511_NFTX(mask)) >> GMAC_TBFT511_NFTX_Pos; +} + +static inline hri_gmac_tbft511_reg_t hri_gmac_read_TBFT511_NFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFT511.reg & GMAC_TBFT511_NFTX_Msk) >> GMAC_TBFT511_NFTX_Pos; +} + +static inline hri_gmac_tbft511_reg_t hri_gmac_get_TBFT511_reg(const void *const hw, hri_gmac_tbft511_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFT511.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbft511_reg_t hri_gmac_read_TBFT511_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFT511.reg; +} + +static inline hri_gmac_tbft1023_reg_t hri_gmac_get_TBFT1023_NFTX_bf(const void *const hw, hri_gmac_tbft1023_reg_t mask) +{ + return (((Gmac *)hw)->TBFT1023.reg & GMAC_TBFT1023_NFTX(mask)) >> GMAC_TBFT1023_NFTX_Pos; +} + +static inline hri_gmac_tbft1023_reg_t hri_gmac_read_TBFT1023_NFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFT1023.reg & GMAC_TBFT1023_NFTX_Msk) >> GMAC_TBFT1023_NFTX_Pos; +} + +static inline hri_gmac_tbft1023_reg_t hri_gmac_get_TBFT1023_reg(const void *const hw, hri_gmac_tbft1023_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFT1023.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbft1023_reg_t hri_gmac_read_TBFT1023_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFT1023.reg; +} + +static inline hri_gmac_tbft1518_reg_t hri_gmac_get_TBFT1518_NFTX_bf(const void *const hw, hri_gmac_tbft1518_reg_t mask) +{ + return (((Gmac *)hw)->TBFT1518.reg & GMAC_TBFT1518_NFTX(mask)) >> GMAC_TBFT1518_NFTX_Pos; +} + +static inline hri_gmac_tbft1518_reg_t hri_gmac_read_TBFT1518_NFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFT1518.reg & GMAC_TBFT1518_NFTX_Msk) >> GMAC_TBFT1518_NFTX_Pos; +} + +static inline hri_gmac_tbft1518_reg_t hri_gmac_get_TBFT1518_reg(const void *const hw, hri_gmac_tbft1518_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFT1518.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbft1518_reg_t hri_gmac_read_TBFT1518_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFT1518.reg; +} + +static inline hri_gmac_gtbft1518_reg_t hri_gmac_get_GTBFT1518_NFTX_bf(const void *const hw, + hri_gmac_gtbft1518_reg_t mask) +{ + return (((Gmac *)hw)->GTBFT1518.reg & GMAC_GTBFT1518_NFTX(mask)) >> GMAC_GTBFT1518_NFTX_Pos; +} + +static inline hri_gmac_gtbft1518_reg_t hri_gmac_read_GTBFT1518_NFTX_bf(const void *const hw) +{ + return (((Gmac *)hw)->GTBFT1518.reg & GMAC_GTBFT1518_NFTX_Msk) >> GMAC_GTBFT1518_NFTX_Pos; +} + +static inline hri_gmac_gtbft1518_reg_t hri_gmac_get_GTBFT1518_reg(const void *const hw, hri_gmac_gtbft1518_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->GTBFT1518.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_gtbft1518_reg_t hri_gmac_read_GTBFT1518_reg(const void *const hw) +{ + return ((Gmac *)hw)->GTBFT1518.reg; +} + +static inline hri_gmac_tur_reg_t hri_gmac_get_TUR_TXUNR_bf(const void *const hw, hri_gmac_tur_reg_t mask) +{ + return (((Gmac *)hw)->TUR.reg & GMAC_TUR_TXUNR(mask)) >> GMAC_TUR_TXUNR_Pos; +} + +static inline hri_gmac_tur_reg_t hri_gmac_read_TUR_TXUNR_bf(const void *const hw) +{ + return (((Gmac *)hw)->TUR.reg & GMAC_TUR_TXUNR_Msk) >> GMAC_TUR_TXUNR_Pos; +} + +static inline hri_gmac_tur_reg_t hri_gmac_get_TUR_reg(const void *const hw, hri_gmac_tur_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TUR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tur_reg_t hri_gmac_read_TUR_reg(const void *const hw) +{ + return ((Gmac *)hw)->TUR.reg; +} + +static inline hri_gmac_scf_reg_t hri_gmac_get_SCF_SCOL_bf(const void *const hw, hri_gmac_scf_reg_t mask) +{ + return (((Gmac *)hw)->SCF.reg & GMAC_SCF_SCOL(mask)) >> GMAC_SCF_SCOL_Pos; +} + +static inline hri_gmac_scf_reg_t hri_gmac_read_SCF_SCOL_bf(const void *const hw) +{ + return (((Gmac *)hw)->SCF.reg & GMAC_SCF_SCOL_Msk) >> GMAC_SCF_SCOL_Pos; +} + +static inline hri_gmac_scf_reg_t hri_gmac_get_SCF_reg(const void *const hw, hri_gmac_scf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->SCF.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_scf_reg_t hri_gmac_read_SCF_reg(const void *const hw) +{ + return ((Gmac *)hw)->SCF.reg; +} + +static inline hri_gmac_mcf_reg_t hri_gmac_get_MCF_MCOL_bf(const void *const hw, hri_gmac_mcf_reg_t mask) +{ + return (((Gmac *)hw)->MCF.reg & GMAC_MCF_MCOL(mask)) >> GMAC_MCF_MCOL_Pos; +} + +static inline hri_gmac_mcf_reg_t hri_gmac_read_MCF_MCOL_bf(const void *const hw) +{ + return (((Gmac *)hw)->MCF.reg & GMAC_MCF_MCOL_Msk) >> GMAC_MCF_MCOL_Pos; +} + +static inline hri_gmac_mcf_reg_t hri_gmac_get_MCF_reg(const void *const hw, hri_gmac_mcf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->MCF.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_mcf_reg_t hri_gmac_read_MCF_reg(const void *const hw) +{ + return ((Gmac *)hw)->MCF.reg; +} + +static inline hri_gmac_ec_reg_t hri_gmac_get_EC_XCOL_bf(const void *const hw, hri_gmac_ec_reg_t mask) +{ + return (((Gmac *)hw)->EC.reg & GMAC_EC_XCOL(mask)) >> GMAC_EC_XCOL_Pos; +} + +static inline hri_gmac_ec_reg_t hri_gmac_read_EC_XCOL_bf(const void *const hw) +{ + return (((Gmac *)hw)->EC.reg & GMAC_EC_XCOL_Msk) >> GMAC_EC_XCOL_Pos; +} + +static inline hri_gmac_ec_reg_t hri_gmac_get_EC_reg(const void *const hw, hri_gmac_ec_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->EC.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_ec_reg_t hri_gmac_read_EC_reg(const void *const hw) +{ + return ((Gmac *)hw)->EC.reg; +} + +static inline hri_gmac_lc_reg_t hri_gmac_get_LC_LCOL_bf(const void *const hw, hri_gmac_lc_reg_t mask) +{ + return (((Gmac *)hw)->LC.reg & GMAC_LC_LCOL(mask)) >> GMAC_LC_LCOL_Pos; +} + +static inline hri_gmac_lc_reg_t hri_gmac_read_LC_LCOL_bf(const void *const hw) +{ + return (((Gmac *)hw)->LC.reg & GMAC_LC_LCOL_Msk) >> GMAC_LC_LCOL_Pos; +} + +static inline hri_gmac_lc_reg_t hri_gmac_get_LC_reg(const void *const hw, hri_gmac_lc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->LC.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_lc_reg_t hri_gmac_read_LC_reg(const void *const hw) +{ + return ((Gmac *)hw)->LC.reg; +} + +static inline hri_gmac_dtf_reg_t hri_gmac_get_DTF_DEFT_bf(const void *const hw, hri_gmac_dtf_reg_t mask) +{ + return (((Gmac *)hw)->DTF.reg & GMAC_DTF_DEFT(mask)) >> GMAC_DTF_DEFT_Pos; +} + +static inline hri_gmac_dtf_reg_t hri_gmac_read_DTF_DEFT_bf(const void *const hw) +{ + return (((Gmac *)hw)->DTF.reg & GMAC_DTF_DEFT_Msk) >> GMAC_DTF_DEFT_Pos; +} + +static inline hri_gmac_dtf_reg_t hri_gmac_get_DTF_reg(const void *const hw, hri_gmac_dtf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->DTF.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_dtf_reg_t hri_gmac_read_DTF_reg(const void *const hw) +{ + return ((Gmac *)hw)->DTF.reg; +} + +static inline hri_gmac_cse_reg_t hri_gmac_get_CSE_CSR_bf(const void *const hw, hri_gmac_cse_reg_t mask) +{ + return (((Gmac *)hw)->CSE.reg & GMAC_CSE_CSR(mask)) >> GMAC_CSE_CSR_Pos; +} + +static inline hri_gmac_cse_reg_t hri_gmac_read_CSE_CSR_bf(const void *const hw) +{ + return (((Gmac *)hw)->CSE.reg & GMAC_CSE_CSR_Msk) >> GMAC_CSE_CSR_Pos; +} + +static inline hri_gmac_cse_reg_t hri_gmac_get_CSE_reg(const void *const hw, hri_gmac_cse_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->CSE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_cse_reg_t hri_gmac_read_CSE_reg(const void *const hw) +{ + return ((Gmac *)hw)->CSE.reg; +} + +static inline hri_gmac_orlo_reg_t hri_gmac_get_ORLO_RXO_bf(const void *const hw, hri_gmac_orlo_reg_t mask) +{ + return (((Gmac *)hw)->ORLO.reg & GMAC_ORLO_RXO(mask)) >> GMAC_ORLO_RXO_Pos; +} + +static inline hri_gmac_orlo_reg_t hri_gmac_read_ORLO_RXO_bf(const void *const hw) +{ + return (((Gmac *)hw)->ORLO.reg & GMAC_ORLO_RXO_Msk) >> GMAC_ORLO_RXO_Pos; +} + +static inline hri_gmac_orlo_reg_t hri_gmac_get_ORLO_reg(const void *const hw, hri_gmac_orlo_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->ORLO.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_orlo_reg_t hri_gmac_read_ORLO_reg(const void *const hw) +{ + return ((Gmac *)hw)->ORLO.reg; +} + +static inline hri_gmac_orhi_reg_t hri_gmac_get_ORHI_RXO_bf(const void *const hw, hri_gmac_orhi_reg_t mask) +{ + return (((Gmac *)hw)->ORHI.reg & GMAC_ORHI_RXO(mask)) >> GMAC_ORHI_RXO_Pos; +} + +static inline hri_gmac_orhi_reg_t hri_gmac_read_ORHI_RXO_bf(const void *const hw) +{ + return (((Gmac *)hw)->ORHI.reg & GMAC_ORHI_RXO_Msk) >> GMAC_ORHI_RXO_Pos; +} + +static inline hri_gmac_orhi_reg_t hri_gmac_get_ORHI_reg(const void *const hw, hri_gmac_orhi_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->ORHI.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_orhi_reg_t hri_gmac_read_ORHI_reg(const void *const hw) +{ + return ((Gmac *)hw)->ORHI.reg; +} + +static inline hri_gmac_fr_reg_t hri_gmac_get_FR_FRX_bf(const void *const hw, hri_gmac_fr_reg_t mask) +{ + return (((Gmac *)hw)->FR.reg & GMAC_FR_FRX(mask)) >> GMAC_FR_FRX_Pos; +} + +static inline hri_gmac_fr_reg_t hri_gmac_read_FR_FRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->FR.reg & GMAC_FR_FRX_Msk) >> GMAC_FR_FRX_Pos; +} + +static inline hri_gmac_fr_reg_t hri_gmac_get_FR_reg(const void *const hw, hri_gmac_fr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->FR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_fr_reg_t hri_gmac_read_FR_reg(const void *const hw) +{ + return ((Gmac *)hw)->FR.reg; +} + +static inline hri_gmac_bcfr_reg_t hri_gmac_get_BCFR_BFRX_bf(const void *const hw, hri_gmac_bcfr_reg_t mask) +{ + return (((Gmac *)hw)->BCFR.reg & GMAC_BCFR_BFRX(mask)) >> GMAC_BCFR_BFRX_Pos; +} + +static inline hri_gmac_bcfr_reg_t hri_gmac_read_BCFR_BFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->BCFR.reg & GMAC_BCFR_BFRX_Msk) >> GMAC_BCFR_BFRX_Pos; +} + +static inline hri_gmac_bcfr_reg_t hri_gmac_get_BCFR_reg(const void *const hw, hri_gmac_bcfr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->BCFR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_bcfr_reg_t hri_gmac_read_BCFR_reg(const void *const hw) +{ + return ((Gmac *)hw)->BCFR.reg; +} + +static inline hri_gmac_mfr_reg_t hri_gmac_get_MFR_MFRX_bf(const void *const hw, hri_gmac_mfr_reg_t mask) +{ + return (((Gmac *)hw)->MFR.reg & GMAC_MFR_MFRX(mask)) >> GMAC_MFR_MFRX_Pos; +} + +static inline hri_gmac_mfr_reg_t hri_gmac_read_MFR_MFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->MFR.reg & GMAC_MFR_MFRX_Msk) >> GMAC_MFR_MFRX_Pos; +} + +static inline hri_gmac_mfr_reg_t hri_gmac_get_MFR_reg(const void *const hw, hri_gmac_mfr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->MFR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_mfr_reg_t hri_gmac_read_MFR_reg(const void *const hw) +{ + return ((Gmac *)hw)->MFR.reg; +} + +static inline hri_gmac_pfr_reg_t hri_gmac_get_PFR_PFRX_bf(const void *const hw, hri_gmac_pfr_reg_t mask) +{ + return (((Gmac *)hw)->PFR.reg & GMAC_PFR_PFRX(mask)) >> GMAC_PFR_PFRX_Pos; +} + +static inline hri_gmac_pfr_reg_t hri_gmac_read_PFR_PFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->PFR.reg & GMAC_PFR_PFRX_Msk) >> GMAC_PFR_PFRX_Pos; +} + +static inline hri_gmac_pfr_reg_t hri_gmac_get_PFR_reg(const void *const hw, hri_gmac_pfr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->PFR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_pfr_reg_t hri_gmac_read_PFR_reg(const void *const hw) +{ + return ((Gmac *)hw)->PFR.reg; +} + +static inline hri_gmac_bfr64_reg_t hri_gmac_get_BFR64_NFRX_bf(const void *const hw, hri_gmac_bfr64_reg_t mask) +{ + return (((Gmac *)hw)->BFR64.reg & GMAC_BFR64_NFRX(mask)) >> GMAC_BFR64_NFRX_Pos; +} + +static inline hri_gmac_bfr64_reg_t hri_gmac_read_BFR64_NFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->BFR64.reg & GMAC_BFR64_NFRX_Msk) >> GMAC_BFR64_NFRX_Pos; +} + +static inline hri_gmac_bfr64_reg_t hri_gmac_get_BFR64_reg(const void *const hw, hri_gmac_bfr64_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->BFR64.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_bfr64_reg_t hri_gmac_read_BFR64_reg(const void *const hw) +{ + return ((Gmac *)hw)->BFR64.reg; +} + +static inline hri_gmac_tbfr127_reg_t hri_gmac_get_TBFR127_NFRX_bf(const void *const hw, hri_gmac_tbfr127_reg_t mask) +{ + return (((Gmac *)hw)->TBFR127.reg & GMAC_TBFR127_NFRX(mask)) >> GMAC_TBFR127_NFRX_Pos; +} + +static inline hri_gmac_tbfr127_reg_t hri_gmac_read_TBFR127_NFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFR127.reg & GMAC_TBFR127_NFRX_Msk) >> GMAC_TBFR127_NFRX_Pos; +} + +static inline hri_gmac_tbfr127_reg_t hri_gmac_get_TBFR127_reg(const void *const hw, hri_gmac_tbfr127_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFR127.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbfr127_reg_t hri_gmac_read_TBFR127_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFR127.reg; +} + +static inline hri_gmac_tbfr255_reg_t hri_gmac_get_TBFR255_NFRX_bf(const void *const hw, hri_gmac_tbfr255_reg_t mask) +{ + return (((Gmac *)hw)->TBFR255.reg & GMAC_TBFR255_NFRX(mask)) >> GMAC_TBFR255_NFRX_Pos; +} + +static inline hri_gmac_tbfr255_reg_t hri_gmac_read_TBFR255_NFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFR255.reg & GMAC_TBFR255_NFRX_Msk) >> GMAC_TBFR255_NFRX_Pos; +} + +static inline hri_gmac_tbfr255_reg_t hri_gmac_get_TBFR255_reg(const void *const hw, hri_gmac_tbfr255_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFR255.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbfr255_reg_t hri_gmac_read_TBFR255_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFR255.reg; +} + +static inline hri_gmac_tbfr511_reg_t hri_gmac_get_TBFR511_NFRX_bf(const void *const hw, hri_gmac_tbfr511_reg_t mask) +{ + return (((Gmac *)hw)->TBFR511.reg & GMAC_TBFR511_NFRX(mask)) >> GMAC_TBFR511_NFRX_Pos; +} + +static inline hri_gmac_tbfr511_reg_t hri_gmac_read_TBFR511_NFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFR511.reg & GMAC_TBFR511_NFRX_Msk) >> GMAC_TBFR511_NFRX_Pos; +} + +static inline hri_gmac_tbfr511_reg_t hri_gmac_get_TBFR511_reg(const void *const hw, hri_gmac_tbfr511_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFR511.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbfr511_reg_t hri_gmac_read_TBFR511_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFR511.reg; +} + +static inline hri_gmac_tbfr1023_reg_t hri_gmac_get_TBFR1023_NFRX_bf(const void *const hw, hri_gmac_tbfr1023_reg_t mask) +{ + return (((Gmac *)hw)->TBFR1023.reg & GMAC_TBFR1023_NFRX(mask)) >> GMAC_TBFR1023_NFRX_Pos; +} + +static inline hri_gmac_tbfr1023_reg_t hri_gmac_read_TBFR1023_NFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFR1023.reg & GMAC_TBFR1023_NFRX_Msk) >> GMAC_TBFR1023_NFRX_Pos; +} + +static inline hri_gmac_tbfr1023_reg_t hri_gmac_get_TBFR1023_reg(const void *const hw, hri_gmac_tbfr1023_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFR1023.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbfr1023_reg_t hri_gmac_read_TBFR1023_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFR1023.reg; +} + +static inline hri_gmac_tbfr1518_reg_t hri_gmac_get_TBFR1518_NFRX_bf(const void *const hw, hri_gmac_tbfr1518_reg_t mask) +{ + return (((Gmac *)hw)->TBFR1518.reg & GMAC_TBFR1518_NFRX(mask)) >> GMAC_TBFR1518_NFRX_Pos; +} + +static inline hri_gmac_tbfr1518_reg_t hri_gmac_read_TBFR1518_NFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TBFR1518.reg & GMAC_TBFR1518_NFRX_Msk) >> GMAC_TBFR1518_NFRX_Pos; +} + +static inline hri_gmac_tbfr1518_reg_t hri_gmac_get_TBFR1518_reg(const void *const hw, hri_gmac_tbfr1518_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBFR1518.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tbfr1518_reg_t hri_gmac_read_TBFR1518_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBFR1518.reg; +} + +static inline hri_gmac_tmxbfr_reg_t hri_gmac_get_TMXBFR_NFRX_bf(const void *const hw, hri_gmac_tmxbfr_reg_t mask) +{ + return (((Gmac *)hw)->TMXBFR.reg & GMAC_TMXBFR_NFRX(mask)) >> GMAC_TMXBFR_NFRX_Pos; +} + +static inline hri_gmac_tmxbfr_reg_t hri_gmac_read_TMXBFR_NFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->TMXBFR.reg & GMAC_TMXBFR_NFRX_Msk) >> GMAC_TMXBFR_NFRX_Pos; +} + +static inline hri_gmac_tmxbfr_reg_t hri_gmac_get_TMXBFR_reg(const void *const hw, hri_gmac_tmxbfr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TMXBFR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tmxbfr_reg_t hri_gmac_read_TMXBFR_reg(const void *const hw) +{ + return ((Gmac *)hw)->TMXBFR.reg; +} + +static inline hri_gmac_ufr_reg_t hri_gmac_get_UFR_UFRX_bf(const void *const hw, hri_gmac_ufr_reg_t mask) +{ + return (((Gmac *)hw)->UFR.reg & GMAC_UFR_UFRX(mask)) >> GMAC_UFR_UFRX_Pos; +} + +static inline hri_gmac_ufr_reg_t hri_gmac_read_UFR_UFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->UFR.reg & GMAC_UFR_UFRX_Msk) >> GMAC_UFR_UFRX_Pos; +} + +static inline hri_gmac_ufr_reg_t hri_gmac_get_UFR_reg(const void *const hw, hri_gmac_ufr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->UFR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_ufr_reg_t hri_gmac_read_UFR_reg(const void *const hw) +{ + return ((Gmac *)hw)->UFR.reg; +} + +static inline hri_gmac_ofr_reg_t hri_gmac_get_OFR_OFRX_bf(const void *const hw, hri_gmac_ofr_reg_t mask) +{ + return (((Gmac *)hw)->OFR.reg & GMAC_OFR_OFRX(mask)) >> GMAC_OFR_OFRX_Pos; +} + +static inline hri_gmac_ofr_reg_t hri_gmac_read_OFR_OFRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->OFR.reg & GMAC_OFR_OFRX_Msk) >> GMAC_OFR_OFRX_Pos; +} + +static inline hri_gmac_ofr_reg_t hri_gmac_get_OFR_reg(const void *const hw, hri_gmac_ofr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->OFR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_ofr_reg_t hri_gmac_read_OFR_reg(const void *const hw) +{ + return ((Gmac *)hw)->OFR.reg; +} + +static inline hri_gmac_jr_reg_t hri_gmac_get_JR_JRX_bf(const void *const hw, hri_gmac_jr_reg_t mask) +{ + return (((Gmac *)hw)->JR.reg & GMAC_JR_JRX(mask)) >> GMAC_JR_JRX_Pos; +} + +static inline hri_gmac_jr_reg_t hri_gmac_read_JR_JRX_bf(const void *const hw) +{ + return (((Gmac *)hw)->JR.reg & GMAC_JR_JRX_Msk) >> GMAC_JR_JRX_Pos; +} + +static inline hri_gmac_jr_reg_t hri_gmac_get_JR_reg(const void *const hw, hri_gmac_jr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->JR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_jr_reg_t hri_gmac_read_JR_reg(const void *const hw) +{ + return ((Gmac *)hw)->JR.reg; +} + +static inline hri_gmac_fcse_reg_t hri_gmac_get_FCSE_FCKR_bf(const void *const hw, hri_gmac_fcse_reg_t mask) +{ + return (((Gmac *)hw)->FCSE.reg & GMAC_FCSE_FCKR(mask)) >> GMAC_FCSE_FCKR_Pos; +} + +static inline hri_gmac_fcse_reg_t hri_gmac_read_FCSE_FCKR_bf(const void *const hw) +{ + return (((Gmac *)hw)->FCSE.reg & GMAC_FCSE_FCKR_Msk) >> GMAC_FCSE_FCKR_Pos; +} + +static inline hri_gmac_fcse_reg_t hri_gmac_get_FCSE_reg(const void *const hw, hri_gmac_fcse_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->FCSE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_fcse_reg_t hri_gmac_read_FCSE_reg(const void *const hw) +{ + return ((Gmac *)hw)->FCSE.reg; +} + +static inline hri_gmac_lffe_reg_t hri_gmac_get_LFFE_LFER_bf(const void *const hw, hri_gmac_lffe_reg_t mask) +{ + return (((Gmac *)hw)->LFFE.reg & GMAC_LFFE_LFER(mask)) >> GMAC_LFFE_LFER_Pos; +} + +static inline hri_gmac_lffe_reg_t hri_gmac_read_LFFE_LFER_bf(const void *const hw) +{ + return (((Gmac *)hw)->LFFE.reg & GMAC_LFFE_LFER_Msk) >> GMAC_LFFE_LFER_Pos; +} + +static inline hri_gmac_lffe_reg_t hri_gmac_get_LFFE_reg(const void *const hw, hri_gmac_lffe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->LFFE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_lffe_reg_t hri_gmac_read_LFFE_reg(const void *const hw) +{ + return ((Gmac *)hw)->LFFE.reg; +} + +static inline hri_gmac_rse_reg_t hri_gmac_get_RSE_RXSE_bf(const void *const hw, hri_gmac_rse_reg_t mask) +{ + return (((Gmac *)hw)->RSE.reg & GMAC_RSE_RXSE(mask)) >> GMAC_RSE_RXSE_Pos; +} + +static inline hri_gmac_rse_reg_t hri_gmac_read_RSE_RXSE_bf(const void *const hw) +{ + return (((Gmac *)hw)->RSE.reg & GMAC_RSE_RXSE_Msk) >> GMAC_RSE_RXSE_Pos; +} + +static inline hri_gmac_rse_reg_t hri_gmac_get_RSE_reg(const void *const hw, hri_gmac_rse_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->RSE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_rse_reg_t hri_gmac_read_RSE_reg(const void *const hw) +{ + return ((Gmac *)hw)->RSE.reg; +} + +static inline hri_gmac_ae_reg_t hri_gmac_get_AE_AER_bf(const void *const hw, hri_gmac_ae_reg_t mask) +{ + return (((Gmac *)hw)->AE.reg & GMAC_AE_AER(mask)) >> GMAC_AE_AER_Pos; +} + +static inline hri_gmac_ae_reg_t hri_gmac_read_AE_AER_bf(const void *const hw) +{ + return (((Gmac *)hw)->AE.reg & GMAC_AE_AER_Msk) >> GMAC_AE_AER_Pos; +} + +static inline hri_gmac_ae_reg_t hri_gmac_get_AE_reg(const void *const hw, hri_gmac_ae_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->AE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_ae_reg_t hri_gmac_read_AE_reg(const void *const hw) +{ + return ((Gmac *)hw)->AE.reg; +} + +static inline hri_gmac_rre_reg_t hri_gmac_get_RRE_RXRER_bf(const void *const hw, hri_gmac_rre_reg_t mask) +{ + return (((Gmac *)hw)->RRE.reg & GMAC_RRE_RXRER(mask)) >> GMAC_RRE_RXRER_Pos; +} + +static inline hri_gmac_rre_reg_t hri_gmac_read_RRE_RXRER_bf(const void *const hw) +{ + return (((Gmac *)hw)->RRE.reg & GMAC_RRE_RXRER_Msk) >> GMAC_RRE_RXRER_Pos; +} + +static inline hri_gmac_rre_reg_t hri_gmac_get_RRE_reg(const void *const hw, hri_gmac_rre_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->RRE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_rre_reg_t hri_gmac_read_RRE_reg(const void *const hw) +{ + return ((Gmac *)hw)->RRE.reg; +} + +static inline hri_gmac_roe_reg_t hri_gmac_get_ROE_RXOVR_bf(const void *const hw, hri_gmac_roe_reg_t mask) +{ + return (((Gmac *)hw)->ROE.reg & GMAC_ROE_RXOVR(mask)) >> GMAC_ROE_RXOVR_Pos; +} + +static inline hri_gmac_roe_reg_t hri_gmac_read_ROE_RXOVR_bf(const void *const hw) +{ + return (((Gmac *)hw)->ROE.reg & GMAC_ROE_RXOVR_Msk) >> GMAC_ROE_RXOVR_Pos; +} + +static inline hri_gmac_roe_reg_t hri_gmac_get_ROE_reg(const void *const hw, hri_gmac_roe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->ROE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_roe_reg_t hri_gmac_read_ROE_reg(const void *const hw) +{ + return ((Gmac *)hw)->ROE.reg; +} + +static inline hri_gmac_ihce_reg_t hri_gmac_get_IHCE_HCKER_bf(const void *const hw, hri_gmac_ihce_reg_t mask) +{ + return (((Gmac *)hw)->IHCE.reg & GMAC_IHCE_HCKER(mask)) >> GMAC_IHCE_HCKER_Pos; +} + +static inline hri_gmac_ihce_reg_t hri_gmac_read_IHCE_HCKER_bf(const void *const hw) +{ + return (((Gmac *)hw)->IHCE.reg & GMAC_IHCE_HCKER_Msk) >> GMAC_IHCE_HCKER_Pos; +} + +static inline hri_gmac_ihce_reg_t hri_gmac_get_IHCE_reg(const void *const hw, hri_gmac_ihce_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->IHCE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_ihce_reg_t hri_gmac_read_IHCE_reg(const void *const hw) +{ + return ((Gmac *)hw)->IHCE.reg; +} + +static inline hri_gmac_tce_reg_t hri_gmac_get_TCE_TCKER_bf(const void *const hw, hri_gmac_tce_reg_t mask) +{ + return (((Gmac *)hw)->TCE.reg & GMAC_TCE_TCKER(mask)) >> GMAC_TCE_TCKER_Pos; +} + +static inline hri_gmac_tce_reg_t hri_gmac_read_TCE_TCKER_bf(const void *const hw) +{ + return (((Gmac *)hw)->TCE.reg & GMAC_TCE_TCKER_Msk) >> GMAC_TCE_TCKER_Pos; +} + +static inline hri_gmac_tce_reg_t hri_gmac_get_TCE_reg(const void *const hw, hri_gmac_tce_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TCE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tce_reg_t hri_gmac_read_TCE_reg(const void *const hw) +{ + return ((Gmac *)hw)->TCE.reg; +} + +static inline hri_gmac_uce_reg_t hri_gmac_get_UCE_UCKER_bf(const void *const hw, hri_gmac_uce_reg_t mask) +{ + return (((Gmac *)hw)->UCE.reg & GMAC_UCE_UCKER(mask)) >> GMAC_UCE_UCKER_Pos; +} + +static inline hri_gmac_uce_reg_t hri_gmac_read_UCE_UCKER_bf(const void *const hw) +{ + return (((Gmac *)hw)->UCE.reg & GMAC_UCE_UCKER_Msk) >> GMAC_UCE_UCKER_Pos; +} + +static inline hri_gmac_uce_reg_t hri_gmac_get_UCE_reg(const void *const hw, hri_gmac_uce_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->UCE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_uce_reg_t hri_gmac_read_UCE_reg(const void *const hw) +{ + return ((Gmac *)hw)->UCE.reg; +} + +static inline hri_gmac_eftsl_reg_t hri_gmac_get_EFTSL_RUD_bf(const void *const hw, hri_gmac_eftsl_reg_t mask) +{ + return (((Gmac *)hw)->EFTSL.reg & GMAC_EFTSL_RUD(mask)) >> GMAC_EFTSL_RUD_Pos; +} + +static inline hri_gmac_eftsl_reg_t hri_gmac_read_EFTSL_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->EFTSL.reg & GMAC_EFTSL_RUD_Msk) >> GMAC_EFTSL_RUD_Pos; +} + +static inline hri_gmac_eftsl_reg_t hri_gmac_get_EFTSL_reg(const void *const hw, hri_gmac_eftsl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->EFTSL.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_eftsl_reg_t hri_gmac_read_EFTSL_reg(const void *const hw) +{ + return ((Gmac *)hw)->EFTSL.reg; +} + +static inline hri_gmac_eftn_reg_t hri_gmac_get_EFTN_RUD_bf(const void *const hw, hri_gmac_eftn_reg_t mask) +{ + return (((Gmac *)hw)->EFTN.reg & GMAC_EFTN_RUD(mask)) >> GMAC_EFTN_RUD_Pos; +} + +static inline hri_gmac_eftn_reg_t hri_gmac_read_EFTN_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->EFTN.reg & GMAC_EFTN_RUD_Msk) >> GMAC_EFTN_RUD_Pos; +} + +static inline hri_gmac_eftn_reg_t hri_gmac_get_EFTN_reg(const void *const hw, hri_gmac_eftn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->EFTN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_eftn_reg_t hri_gmac_read_EFTN_reg(const void *const hw) +{ + return ((Gmac *)hw)->EFTN.reg; +} + +static inline hri_gmac_efrsl_reg_t hri_gmac_get_EFRSL_RUD_bf(const void *const hw, hri_gmac_efrsl_reg_t mask) +{ + return (((Gmac *)hw)->EFRSL.reg & GMAC_EFRSL_RUD(mask)) >> GMAC_EFRSL_RUD_Pos; +} + +static inline hri_gmac_efrsl_reg_t hri_gmac_read_EFRSL_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->EFRSL.reg & GMAC_EFRSL_RUD_Msk) >> GMAC_EFRSL_RUD_Pos; +} + +static inline hri_gmac_efrsl_reg_t hri_gmac_get_EFRSL_reg(const void *const hw, hri_gmac_efrsl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->EFRSL.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_efrsl_reg_t hri_gmac_read_EFRSL_reg(const void *const hw) +{ + return ((Gmac *)hw)->EFRSL.reg; +} + +static inline hri_gmac_efrn_reg_t hri_gmac_get_EFRN_RUD_bf(const void *const hw, hri_gmac_efrn_reg_t mask) +{ + return (((Gmac *)hw)->EFRN.reg & GMAC_EFRN_RUD(mask)) >> GMAC_EFRN_RUD_Pos; +} + +static inline hri_gmac_efrn_reg_t hri_gmac_read_EFRN_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->EFRN.reg & GMAC_EFRN_RUD_Msk) >> GMAC_EFRN_RUD_Pos; +} + +static inline hri_gmac_efrn_reg_t hri_gmac_get_EFRN_reg(const void *const hw, hri_gmac_efrn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->EFRN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_efrn_reg_t hri_gmac_read_EFRN_reg(const void *const hw) +{ + return ((Gmac *)hw)->EFRN.reg; +} + +static inline hri_gmac_peftsl_reg_t hri_gmac_get_PEFTSL_RUD_bf(const void *const hw, hri_gmac_peftsl_reg_t mask) +{ + return (((Gmac *)hw)->PEFTSL.reg & GMAC_PEFTSL_RUD(mask)) >> GMAC_PEFTSL_RUD_Pos; +} + +static inline hri_gmac_peftsl_reg_t hri_gmac_read_PEFTSL_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->PEFTSL.reg & GMAC_PEFTSL_RUD_Msk) >> GMAC_PEFTSL_RUD_Pos; +} + +static inline hri_gmac_peftsl_reg_t hri_gmac_get_PEFTSL_reg(const void *const hw, hri_gmac_peftsl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->PEFTSL.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_peftsl_reg_t hri_gmac_read_PEFTSL_reg(const void *const hw) +{ + return ((Gmac *)hw)->PEFTSL.reg; +} + +static inline hri_gmac_peftn_reg_t hri_gmac_get_PEFTN_RUD_bf(const void *const hw, hri_gmac_peftn_reg_t mask) +{ + return (((Gmac *)hw)->PEFTN.reg & GMAC_PEFTN_RUD(mask)) >> GMAC_PEFTN_RUD_Pos; +} + +static inline hri_gmac_peftn_reg_t hri_gmac_read_PEFTN_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->PEFTN.reg & GMAC_PEFTN_RUD_Msk) >> GMAC_PEFTN_RUD_Pos; +} + +static inline hri_gmac_peftn_reg_t hri_gmac_get_PEFTN_reg(const void *const hw, hri_gmac_peftn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->PEFTN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_peftn_reg_t hri_gmac_read_PEFTN_reg(const void *const hw) +{ + return ((Gmac *)hw)->PEFTN.reg; +} + +static inline hri_gmac_pefrsl_reg_t hri_gmac_get_PEFRSL_RUD_bf(const void *const hw, hri_gmac_pefrsl_reg_t mask) +{ + return (((Gmac *)hw)->PEFRSL.reg & GMAC_PEFRSL_RUD(mask)) >> GMAC_PEFRSL_RUD_Pos; +} + +static inline hri_gmac_pefrsl_reg_t hri_gmac_read_PEFRSL_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->PEFRSL.reg & GMAC_PEFRSL_RUD_Msk) >> GMAC_PEFRSL_RUD_Pos; +} + +static inline hri_gmac_pefrsl_reg_t hri_gmac_get_PEFRSL_reg(const void *const hw, hri_gmac_pefrsl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->PEFRSL.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_pefrsl_reg_t hri_gmac_read_PEFRSL_reg(const void *const hw) +{ + return ((Gmac *)hw)->PEFRSL.reg; +} + +static inline hri_gmac_pefrn_reg_t hri_gmac_get_PEFRN_RUD_bf(const void *const hw, hri_gmac_pefrn_reg_t mask) +{ + return (((Gmac *)hw)->PEFRN.reg & GMAC_PEFRN_RUD(mask)) >> GMAC_PEFRN_RUD_Pos; +} + +static inline hri_gmac_pefrn_reg_t hri_gmac_read_PEFRN_RUD_bf(const void *const hw) +{ + return (((Gmac *)hw)->PEFRN.reg & GMAC_PEFRN_RUD_Msk) >> GMAC_PEFRN_RUD_Pos; +} + +static inline hri_gmac_pefrn_reg_t hri_gmac_get_PEFRN_reg(const void *const hw, hri_gmac_pefrn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->PEFRN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_pefrn_reg_t hri_gmac_read_PEFRN_reg(const void *const hw) +{ + return ((Gmac *)hw)->PEFRN.reg; +} + +static inline hri_gmac_rlpitr_reg_t hri_gmac_get_RLPITR_RLPITR_bf(const void *const hw, hri_gmac_rlpitr_reg_t mask) +{ + return (((Gmac *)hw)->RLPITR.reg & GMAC_RLPITR_RLPITR(mask)) >> GMAC_RLPITR_RLPITR_Pos; +} + +static inline hri_gmac_rlpitr_reg_t hri_gmac_read_RLPITR_RLPITR_bf(const void *const hw) +{ + return (((Gmac *)hw)->RLPITR.reg & GMAC_RLPITR_RLPITR_Msk) >> GMAC_RLPITR_RLPITR_Pos; +} + +static inline hri_gmac_rlpitr_reg_t hri_gmac_get_RLPITR_reg(const void *const hw, hri_gmac_rlpitr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->RLPITR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_rlpitr_reg_t hri_gmac_read_RLPITR_reg(const void *const hw) +{ + return ((Gmac *)hw)->RLPITR.reg; +} + +static inline hri_gmac_rlpiti_reg_t hri_gmac_get_RLPITI_RLPITI_bf(const void *const hw, hri_gmac_rlpiti_reg_t mask) +{ + return (((Gmac *)hw)->RLPITI.reg & GMAC_RLPITI_RLPITI(mask)) >> GMAC_RLPITI_RLPITI_Pos; +} + +static inline hri_gmac_rlpiti_reg_t hri_gmac_read_RLPITI_RLPITI_bf(const void *const hw) +{ + return (((Gmac *)hw)->RLPITI.reg & GMAC_RLPITI_RLPITI_Msk) >> GMAC_RLPITI_RLPITI_Pos; +} + +static inline hri_gmac_rlpiti_reg_t hri_gmac_get_RLPITI_reg(const void *const hw, hri_gmac_rlpiti_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->RLPITI.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_rlpiti_reg_t hri_gmac_read_RLPITI_reg(const void *const hw) +{ + return ((Gmac *)hw)->RLPITI.reg; +} + +static inline hri_gmac_tlpitr_reg_t hri_gmac_get_TLPITR_TLPITR_bf(const void *const hw, hri_gmac_tlpitr_reg_t mask) +{ + return (((Gmac *)hw)->TLPITR.reg & GMAC_TLPITR_TLPITR(mask)) >> GMAC_TLPITR_TLPITR_Pos; +} + +static inline hri_gmac_tlpitr_reg_t hri_gmac_read_TLPITR_TLPITR_bf(const void *const hw) +{ + return (((Gmac *)hw)->TLPITR.reg & GMAC_TLPITR_TLPITR_Msk) >> GMAC_TLPITR_TLPITR_Pos; +} + +static inline hri_gmac_tlpitr_reg_t hri_gmac_get_TLPITR_reg(const void *const hw, hri_gmac_tlpitr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TLPITR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tlpitr_reg_t hri_gmac_read_TLPITR_reg(const void *const hw) +{ + return ((Gmac *)hw)->TLPITR.reg; +} + +static inline hri_gmac_tlpiti_reg_t hri_gmac_get_TLPITI_TLPITI_bf(const void *const hw, hri_gmac_tlpiti_reg_t mask) +{ + return (((Gmac *)hw)->TLPITI.reg & GMAC_TLPITI_TLPITI(mask)) >> GMAC_TLPITI_TLPITI_Pos; +} + +static inline hri_gmac_tlpiti_reg_t hri_gmac_read_TLPITI_TLPITI_bf(const void *const hw) +{ + return (((Gmac *)hw)->TLPITI.reg & GMAC_TLPITI_TLPITI_Msk) >> GMAC_TLPITI_TLPITI_Pos; +} + +static inline hri_gmac_tlpiti_reg_t hri_gmac_get_TLPITI_reg(const void *const hw, hri_gmac_tlpiti_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TLPITI.reg; + tmp &= mask; + return tmp; +} + +static inline hri_gmac_tlpiti_reg_t hri_gmac_read_TLPITI_reg(const void *const hw) +{ + return ((Gmac *)hw)->TLPITI.reg; +} + +static inline void hri_gmac_set_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NCR.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ncr_reg_t hri_gmac_get_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->NCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NCR.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NCR.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCR_reg(const void *const hw, hri_gmac_ncr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NCR.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ncr_reg_t hri_gmac_read_NCR_reg(const void *const hw) +{ + return ((Gmac *)hw)->NCR.reg; +} + +static inline void hri_gmac_set_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NCFGR.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ncfgr_reg_t hri_gmac_get_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->NCFGR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NCFGR.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NCFGR.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NCFGR_reg(const void *const hw, hri_gmac_ncfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NCFGR.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ncfgr_reg_t hri_gmac_read_NCFGR_reg(const void *const hw) +{ + return ((Gmac *)hw)->NCFGR.reg; +} + +static inline void hri_gmac_set_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->UR.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ur_reg_t hri_gmac_get_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->UR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_UR_reg(const void *const hw, hri_gmac_ur_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->UR.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->UR.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_UR_reg(const void *const hw, hri_gmac_ur_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->UR.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ur_reg_t hri_gmac_read_UR_reg(const void *const hw) +{ + return ((Gmac *)hw)->UR.reg; +} + +static inline void hri_gmac_set_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->DCFGR.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_dcfgr_reg_t hri_gmac_get_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->DCFGR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->DCFGR.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->DCFGR.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_DCFGR_reg(const void *const hw, hri_gmac_dcfgr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->DCFGR.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_dcfgr_reg_t hri_gmac_read_DCFGR_reg(const void *const hw) +{ + return ((Gmac *)hw)->DCFGR.reg; +} + +static inline void hri_gmac_set_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSR.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsr_reg_t hri_gmac_get_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TSR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSR.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSR.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TSR_reg(const void *const hw, hri_gmac_tsr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSR.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsr_reg_t hri_gmac_read_TSR_reg(const void *const hw) +{ + return ((Gmac *)hw)->TSR.reg; +} + +static inline void hri_gmac_set_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RBQB.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rbqb_reg_t hri_gmac_get_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->RBQB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RBQB.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RBQB.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_RBQB_reg(const void *const hw, hri_gmac_rbqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RBQB.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rbqb_reg_t hri_gmac_read_RBQB_reg(const void *const hw) +{ + return ((Gmac *)hw)->RBQB.reg; +} + +static inline void hri_gmac_set_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TBQB.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tbqb_reg_t hri_gmac_get_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TBQB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TBQB.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TBQB.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TBQB_reg(const void *const hw, hri_gmac_tbqb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TBQB.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tbqb_reg_t hri_gmac_read_TBQB_reg(const void *const hw) +{ + return ((Gmac *)hw)->TBQB.reg; +} + +static inline void hri_gmac_set_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RSR.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rsr_reg_t hri_gmac_get_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->RSR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RSR.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RSR.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_RSR_reg(const void *const hw, hri_gmac_rsr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RSR.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rsr_reg_t hri_gmac_read_RSR_reg(const void *const hw) +{ + return ((Gmac *)hw)->RSR.reg; +} + +static inline void hri_gmac_set_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->ISR.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_isr_reg_t hri_gmac_get_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->ISR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_ISR_reg(const void *const hw, hri_gmac_isr_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->ISR.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->ISR.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_ISR_reg(const void *const hw, hri_gmac_isr_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->ISR.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_isr_reg_t hri_gmac_read_ISR_reg(const void *const hw) +{ + return ((Gmac *)hw)->ISR.reg; +} + +static inline void hri_gmac_set_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->MAN.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_man_reg_t hri_gmac_get_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->MAN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_MAN_reg(const void *const hw, hri_gmac_man_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->MAN.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->MAN.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_MAN_reg(const void *const hw, hri_gmac_man_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->MAN.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_man_reg_t hri_gmac_read_MAN_reg(const void *const hw) +{ + return ((Gmac *)hw)->MAN.reg; +} + +static inline void hri_gmac_set_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPQ.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpq_reg_t hri_gmac_get_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TPQ.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPQ.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPQ.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TPQ_reg(const void *const hw, hri_gmac_tpq_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPQ.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpq_reg_t hri_gmac_read_TPQ_reg(const void *const hw) +{ + return ((Gmac *)hw)->TPQ.reg; +} + +static inline void hri_gmac_set_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPSF.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpsf_reg_t hri_gmac_get_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TPSF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPSF.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPSF.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TPSF_reg(const void *const hw, hri_gmac_tpsf_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPSF.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpsf_reg_t hri_gmac_read_TPSF_reg(const void *const hw) +{ + return ((Gmac *)hw)->TPSF.reg; +} + +static inline void hri_gmac_set_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RPSF.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rpsf_reg_t hri_gmac_get_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->RPSF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RPSF.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RPSF.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_RPSF_reg(const void *const hw, hri_gmac_rpsf_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RPSF.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rpsf_reg_t hri_gmac_read_RPSF_reg(const void *const hw) +{ + return ((Gmac *)hw)->RPSF.reg; +} + +static inline void hri_gmac_set_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RJFML.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rjfml_reg_t hri_gmac_get_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->RJFML.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RJFML.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RJFML.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_RJFML_reg(const void *const hw, hri_gmac_rjfml_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->RJFML.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_rjfml_reg_t hri_gmac_read_RJFML_reg(const void *const hw) +{ + return ((Gmac *)hw)->RJFML.reg; +} + +static inline void hri_gmac_set_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->HRB.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_hrb_reg_t hri_gmac_get_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->HRB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->HRB.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->HRB.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_HRB_reg(const void *const hw, hri_gmac_hrb_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->HRB.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_hrb_reg_t hri_gmac_read_HRB_reg(const void *const hw) +{ + return ((Gmac *)hw)->HRB.reg; +} + +static inline void hri_gmac_set_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->HRT.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_hrt_reg_t hri_gmac_get_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->HRT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->HRT.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->HRT.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_HRT_reg(const void *const hw, hri_gmac_hrt_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->HRT.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_hrt_reg_t hri_gmac_read_HRT_reg(const void *const hw) +{ + return ((Gmac *)hw)->HRT.reg; +} + +static inline void hri_gmac_set_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TIDM[index].reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tidm_reg_t hri_gmac_get_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TIDM[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TIDM[index].reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TIDM[index].reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TIDM_reg(const void *const hw, uint8_t index, hri_gmac_tidm_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TIDM[index].reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tidm_reg_t hri_gmac_read_TIDM_reg(const void *const hw, uint8_t index) +{ + return ((Gmac *)hw)->TIDM[index].reg; +} + +static inline void hri_gmac_set_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->WOL.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_wol_reg_t hri_gmac_get_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->WOL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_WOL_reg(const void *const hw, hri_gmac_wol_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->WOL.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->WOL.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_WOL_reg(const void *const hw, hri_gmac_wol_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->WOL.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_wol_reg_t hri_gmac_read_WOL_reg(const void *const hw) +{ + return ((Gmac *)hw)->WOL.reg; +} + +static inline void hri_gmac_set_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->IPGS.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ipgs_reg_t hri_gmac_get_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->IPGS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->IPGS.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->IPGS.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_IPGS_reg(const void *const hw, hri_gmac_ipgs_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->IPGS.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ipgs_reg_t hri_gmac_read_IPGS_reg(const void *const hw) +{ + return ((Gmac *)hw)->IPGS.reg; +} + +static inline void hri_gmac_set_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SVLAN.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_svlan_reg_t hri_gmac_get_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->SVLAN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SVLAN.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SVLAN.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SVLAN_reg(const void *const hw, hri_gmac_svlan_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SVLAN.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_svlan_reg_t hri_gmac_read_SVLAN_reg(const void *const hw) +{ + return ((Gmac *)hw)->SVLAN.reg; +} + +static inline void hri_gmac_set_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPFCP.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpfcp_reg_t hri_gmac_get_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TPFCP.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPFCP.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPFCP.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TPFCP_reg(const void *const hw, hri_gmac_tpfcp_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TPFCP.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tpfcp_reg_t hri_gmac_read_TPFCP_reg(const void *const hw) +{ + return ((Gmac *)hw)->TPFCP.reg; +} + +static inline void hri_gmac_set_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SAMB1.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_samb1_reg_t hri_gmac_get_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->SAMB1.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SAMB1.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SAMB1.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SAMB1_reg(const void *const hw, hri_gmac_samb1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SAMB1.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_samb1_reg_t hri_gmac_read_SAMB1_reg(const void *const hw) +{ + return ((Gmac *)hw)->SAMB1.reg; +} + +static inline void hri_gmac_set_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SAMT1.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_samt1_reg_t hri_gmac_get_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->SAMT1.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SAMT1.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SAMT1.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SAMT1_reg(const void *const hw, hri_gmac_samt1_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SAMT1.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_samt1_reg_t hri_gmac_read_SAMT1_reg(const void *const hw) +{ + return ((Gmac *)hw)->SAMT1.reg; +} + +static inline void hri_gmac_set_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NSC.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_nsc_reg_t hri_gmac_get_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->NSC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NSC.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NSC.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_NSC_reg(const void *const hw, hri_gmac_nsc_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->NSC.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_nsc_reg_t hri_gmac_read_NSC_reg(const void *const hw) +{ + return ((Gmac *)hw)->NSC.reg; +} + +static inline void hri_gmac_set_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SCL.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_scl_reg_t hri_gmac_get_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->SCL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_SCL_reg(const void *const hw, hri_gmac_scl_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SCL.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SCL.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SCL_reg(const void *const hw, hri_gmac_scl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SCL.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_scl_reg_t hri_gmac_read_SCL_reg(const void *const hw) +{ + return ((Gmac *)hw)->SCL.reg; +} + +static inline void hri_gmac_set_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SCH.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sch_reg_t hri_gmac_get_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->SCH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_SCH_reg(const void *const hw, hri_gmac_sch_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SCH.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SCH.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_SCH_reg(const void *const hw, hri_gmac_sch_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->SCH.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_sch_reg_t hri_gmac_read_SCH_reg(const void *const hw) +{ + return ((Gmac *)hw)->SCH.reg; +} + +static inline void hri_gmac_set_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TISUBN.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tisubn_reg_t hri_gmac_get_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TISUBN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TISUBN.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TISUBN.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TISUBN_reg(const void *const hw, hri_gmac_tisubn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TISUBN.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tisubn_reg_t hri_gmac_read_TISUBN_reg(const void *const hw) +{ + return ((Gmac *)hw)->TISUBN.reg; +} + +static inline void hri_gmac_set_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSH.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsh_reg_t hri_gmac_get_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TSH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSH.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSH.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TSH_reg(const void *const hw, hri_gmac_tsh_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSH.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsh_reg_t hri_gmac_read_TSH_reg(const void *const hw) +{ + return ((Gmac *)hw)->TSH.reg; +} + +static inline void hri_gmac_set_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSSSL.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsssl_reg_t hri_gmac_get_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TSSSL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSSSL.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSSSL.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TSSSL_reg(const void *const hw, hri_gmac_tsssl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSSSL.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsssl_reg_t hri_gmac_read_TSSSL_reg(const void *const hw) +{ + return ((Gmac *)hw)->TSSSL.reg; +} + +static inline void hri_gmac_set_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSSN.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tssn_reg_t hri_gmac_get_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TSSN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSSN.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSSN.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TSSN_reg(const void *const hw, hri_gmac_tssn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSSN.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tssn_reg_t hri_gmac_read_TSSN_reg(const void *const hw) +{ + return ((Gmac *)hw)->TSSN.reg; +} + +static inline void hri_gmac_set_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSL.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsl_reg_t hri_gmac_get_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TSL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSL.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSL.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TSL_reg(const void *const hw, hri_gmac_tsl_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TSL.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tsl_reg_t hri_gmac_read_TSL_reg(const void *const hw) +{ + return ((Gmac *)hw)->TSL.reg; +} + +static inline void hri_gmac_set_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TN.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tn_reg_t hri_gmac_get_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TN.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TN_reg(const void *const hw, hri_gmac_tn_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TN.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TN.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TN_reg(const void *const hw, hri_gmac_tn_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TN.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_tn_reg_t hri_gmac_read_TN_reg(const void *const hw) +{ + return ((Gmac *)hw)->TN.reg; +} + +static inline void hri_gmac_set_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TI.reg |= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ti_reg_t hri_gmac_get_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask) +{ + uint32_t tmp; + tmp = ((Gmac *)hw)->TI.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_gmac_write_TI_reg(const void *const hw, hri_gmac_ti_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TI.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_clear_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TI.reg &= ~mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_gmac_toggle_TI_reg(const void *const hw, hri_gmac_ti_reg_t mask) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TI.reg ^= mask; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_gmac_ti_reg_t hri_gmac_read_TI_reg(const void *const hw) +{ + return ((Gmac *)hw)->TI.reg; +} + +static inline void hri_gmac_write_TA_reg(const void *const hw, hri_gmac_ta_reg_t data) +{ + GMAC_CRITICAL_SECTION_ENTER(); + ((Gmac *)hw)->TA.reg = data; + GMAC_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_GMAC_E54_H_INCLUDED */ +#endif /* _SAME54_GMAC_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_hmatrixb_e54.h b/software/firmware/oracle_same54n19a/hri/hri_hmatrixb_e54.h new file mode 100644 index 00000000..2ef06845 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_hmatrixb_e54.h @@ -0,0 +1,237 @@ +/** + * \file + * + * \brief SAM HMATRIXB + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_HMATRIXB_COMPONENT_ +#ifndef _HRI_HMATRIXB_E54_H_INCLUDED_ +#define _HRI_HMATRIXB_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_HMATRIXB_CRITICAL_SECTIONS) +#define HMATRIXB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define HMATRIXB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define HMATRIXB_CRITICAL_SECTION_ENTER() +#define HMATRIXB_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_hmatrixb_pras_reg_t; +typedef uint32_t hri_hmatrixb_prbs_reg_t; +typedef uint32_t hri_hmatrixbprs_pras_reg_t; +typedef uint32_t hri_hmatrixbprs_prbs_reg_t; + +static inline void hri_hmatrixbprs_set_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRAS.reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_pras_reg_t hri_hmatrixbprs_get_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) +{ + uint32_t tmp; + tmp = ((HmatrixbPrs *)hw)->PRAS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixbprs_write_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRAS.reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixbprs_clear_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRAS.reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixbprs_toggle_PRAS_reg(const void *const hw, hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRAS.reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_pras_reg_t hri_hmatrixbprs_read_PRAS_reg(const void *const hw) +{ + return ((HmatrixbPrs *)hw)->PRAS.reg; +} + +static inline void hri_hmatrixbprs_set_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRBS.reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_prbs_reg_t hri_hmatrixbprs_get_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) +{ + uint32_t tmp; + tmp = ((HmatrixbPrs *)hw)->PRBS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixbprs_write_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRBS.reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixbprs_clear_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRBS.reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixbprs_toggle_PRBS_reg(const void *const hw, hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((HmatrixbPrs *)hw)->PRBS.reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_prbs_reg_t hri_hmatrixbprs_read_PRBS_reg(const void *const hw) +{ + return ((HmatrixbPrs *)hw)->PRBS.reg; +} + +static inline void hri_hmatrixb_set_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_pras_reg_t hri_hmatrixb_get_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixb_write_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_clear_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_toggle_PRAS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_pras_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_pras_reg_t hri_hmatrixb_read_PRAS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Hmatrixb *)hw)->Prs[submodule_index].PRAS.reg; +} + +static inline void hri_hmatrixb_set_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg |= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_prbs_reg_t hri_hmatrixb_get_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t mask) +{ + uint32_t tmp; + tmp = ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_hmatrixb_write_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t data) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg = data; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_clear_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg &= ~mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_hmatrixb_toggle_PRBS_reg(const void *const hw, uint8_t submodule_index, + hri_hmatrixb_prbs_reg_t mask) +{ + HMATRIXB_CRITICAL_SECTION_ENTER(); + ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg ^= mask; + HMATRIXB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_hmatrixb_prbs_reg_t hri_hmatrixb_read_PRBS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Hmatrixb *)hw)->Prs[submodule_index].PRBS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_HMATRIXB_E54_H_INCLUDED */ +#endif /* _SAME54_HMATRIXB_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_i2s_e54.h b/software/firmware/oracle_same54n19a/hri/hri_i2s_e54.h new file mode 100644 index 00000000..42b88dc0 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_i2s_e54.h @@ -0,0 +1,3032 @@ +/** + * \file + * + * \brief SAM I2S + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_I2S_COMPONENT_ +#ifndef _HRI_I2S_E54_H_INCLUDED_ +#define _HRI_I2S_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_I2S_CRITICAL_SECTIONS) +#define I2S_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define I2S_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define I2S_CRITICAL_SECTION_ENTER() +#define I2S_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_i2s_intenset_reg_t; +typedef uint16_t hri_i2s_intflag_reg_t; +typedef uint16_t hri_i2s_syncbusy_reg_t; +typedef uint32_t hri_i2s_clkctrl_reg_t; +typedef uint32_t hri_i2s_rxctrl_reg_t; +typedef uint32_t hri_i2s_rxdata_reg_t; +typedef uint32_t hri_i2s_txctrl_reg_t; +typedef uint32_t hri_i2s_txdata_reg_t; +typedef uint8_t hri_i2s_ctrla_reg_t; + +static inline void hri_i2s_wait_for_sync(const void *const hw, hri_i2s_syncbusy_reg_t reg) +{ + while (((I2s *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_i2s_is_syncing(const void *const hw, hri_i2s_syncbusy_reg_t reg) +{ + return ((I2s *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_i2s_get_INTFLAG_RXRDY0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY0) >> I2S_INTFLAG_RXRDY0_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_RXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY0; +} + +static inline bool hri_i2s_get_INTFLAG_RXRDY1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY1) >> I2S_INTFLAG_RXRDY1_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_RXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY1; +} + +static inline bool hri_i2s_get_INTFLAG_RXOR0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR0) >> I2S_INTFLAG_RXOR0_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_RXOR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR0; +} + +static inline bool hri_i2s_get_INTFLAG_RXOR1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR1) >> I2S_INTFLAG_RXOR1_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_RXOR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR1; +} + +static inline bool hri_i2s_get_INTFLAG_TXRDY0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY0) >> I2S_INTFLAG_TXRDY0_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_TXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY0; +} + +static inline bool hri_i2s_get_INTFLAG_TXRDY1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY1) >> I2S_INTFLAG_TXRDY1_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_TXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY1; +} + +static inline bool hri_i2s_get_INTFLAG_TXUR0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR0) >> I2S_INTFLAG_TXUR0_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_TXUR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR0; +} + +static inline bool hri_i2s_get_INTFLAG_TXUR1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR1) >> I2S_INTFLAG_TXUR1_Pos; +} + +static inline void hri_i2s_clear_INTFLAG_TXUR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR1; +} + +static inline bool hri_i2s_get_interrupt_RXRDY0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY0) >> I2S_INTFLAG_RXRDY0_Pos; +} + +static inline void hri_i2s_clear_interrupt_RXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY0; +} + +static inline bool hri_i2s_get_interrupt_RXRDY1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXRDY1) >> I2S_INTFLAG_RXRDY1_Pos; +} + +static inline void hri_i2s_clear_interrupt_RXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXRDY1; +} + +static inline bool hri_i2s_get_interrupt_RXOR0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR0) >> I2S_INTFLAG_RXOR0_Pos; +} + +static inline void hri_i2s_clear_interrupt_RXOR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR0; +} + +static inline bool hri_i2s_get_interrupt_RXOR1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_RXOR1) >> I2S_INTFLAG_RXOR1_Pos; +} + +static inline void hri_i2s_clear_interrupt_RXOR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_RXOR1; +} + +static inline bool hri_i2s_get_interrupt_TXRDY0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY0) >> I2S_INTFLAG_TXRDY0_Pos; +} + +static inline void hri_i2s_clear_interrupt_TXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY0; +} + +static inline bool hri_i2s_get_interrupt_TXRDY1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXRDY1) >> I2S_INTFLAG_TXRDY1_Pos; +} + +static inline void hri_i2s_clear_interrupt_TXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXRDY1; +} + +static inline bool hri_i2s_get_interrupt_TXUR0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR0) >> I2S_INTFLAG_TXUR0_Pos; +} + +static inline void hri_i2s_clear_interrupt_TXUR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR0; +} + +static inline bool hri_i2s_get_interrupt_TXUR1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTFLAG.reg & I2S_INTFLAG_TXUR1) >> I2S_INTFLAG_TXUR1_Pos; +} + +static inline void hri_i2s_clear_interrupt_TXUR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTFLAG.reg = I2S_INTFLAG_TXUR1; +} + +static inline hri_i2s_intflag_reg_t hri_i2s_get_INTFLAG_reg(const void *const hw, hri_i2s_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((I2s *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_i2s_intflag_reg_t hri_i2s_read_INTFLAG_reg(const void *const hw) +{ + return ((I2s *)hw)->INTFLAG.reg; +} + +static inline void hri_i2s_clear_INTFLAG_reg(const void *const hw, hri_i2s_intflag_reg_t mask) +{ + ((I2s *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_i2s_set_INTEN_RXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY0; +} + +static inline bool hri_i2s_get_INTEN_RXRDY0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXRDY0) >> I2S_INTENSET_RXRDY0_Pos; +} + +static inline void hri_i2s_write_INTEN_RXRDY0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY0; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY0; + } +} + +static inline void hri_i2s_clear_INTEN_RXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY0; +} + +static inline void hri_i2s_set_INTEN_RXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY1; +} + +static inline bool hri_i2s_get_INTEN_RXRDY1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXRDY1) >> I2S_INTENSET_RXRDY1_Pos; +} + +static inline void hri_i2s_write_INTEN_RXRDY1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY1; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXRDY1; + } +} + +static inline void hri_i2s_clear_INTEN_RXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXRDY1; +} + +static inline void hri_i2s_set_INTEN_RXOR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR0; +} + +static inline bool hri_i2s_get_INTEN_RXOR0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXOR0) >> I2S_INTENSET_RXOR0_Pos; +} + +static inline void hri_i2s_write_INTEN_RXOR0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR0; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR0; + } +} + +static inline void hri_i2s_clear_INTEN_RXOR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR0; +} + +static inline void hri_i2s_set_INTEN_RXOR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR1; +} + +static inline bool hri_i2s_get_INTEN_RXOR1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_RXOR1) >> I2S_INTENSET_RXOR1_Pos; +} + +static inline void hri_i2s_write_INTEN_RXOR1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR1; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_RXOR1; + } +} + +static inline void hri_i2s_clear_INTEN_RXOR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_RXOR1; +} + +static inline void hri_i2s_set_INTEN_TXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY0; +} + +static inline bool hri_i2s_get_INTEN_TXRDY0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXRDY0) >> I2S_INTENSET_TXRDY0_Pos; +} + +static inline void hri_i2s_write_INTEN_TXRDY0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY0; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY0; + } +} + +static inline void hri_i2s_clear_INTEN_TXRDY0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY0; +} + +static inline void hri_i2s_set_INTEN_TXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY1; +} + +static inline bool hri_i2s_get_INTEN_TXRDY1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXRDY1) >> I2S_INTENSET_TXRDY1_Pos; +} + +static inline void hri_i2s_write_INTEN_TXRDY1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY1; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXRDY1; + } +} + +static inline void hri_i2s_clear_INTEN_TXRDY1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXRDY1; +} + +static inline void hri_i2s_set_INTEN_TXUR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR0; +} + +static inline bool hri_i2s_get_INTEN_TXUR0_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXUR0) >> I2S_INTENSET_TXUR0_Pos; +} + +static inline void hri_i2s_write_INTEN_TXUR0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR0; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR0; + } +} + +static inline void hri_i2s_clear_INTEN_TXUR0_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR0; +} + +static inline void hri_i2s_set_INTEN_TXUR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR1; +} + +static inline bool hri_i2s_get_INTEN_TXUR1_bit(const void *const hw) +{ + return (((I2s *)hw)->INTENSET.reg & I2S_INTENSET_TXUR1) >> I2S_INTENSET_TXUR1_Pos; +} + +static inline void hri_i2s_write_INTEN_TXUR1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR1; + } else { + ((I2s *)hw)->INTENSET.reg = I2S_INTENSET_TXUR1; + } +} + +static inline void hri_i2s_clear_INTEN_TXUR1_bit(const void *const hw) +{ + ((I2s *)hw)->INTENCLR.reg = I2S_INTENSET_TXUR1; +} + +static inline void hri_i2s_set_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask) +{ + ((I2s *)hw)->INTENSET.reg = mask; +} + +static inline hri_i2s_intenset_reg_t hri_i2s_get_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((I2s *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_i2s_intenset_reg_t hri_i2s_read_INTEN_reg(const void *const hw) +{ + return ((I2s *)hw)->INTENSET.reg; +} + +static inline void hri_i2s_write_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t data) +{ + ((I2s *)hw)->INTENSET.reg = data; + ((I2s *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_i2s_clear_INTEN_reg(const void *const hw, hri_i2s_intenset_reg_t mask) +{ + ((I2s *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_i2s_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_SWRST) >> I2S_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_ENABLE) >> I2S_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_CKEN0_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_CKEN0) >> I2S_SYNCBUSY_CKEN0_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_CKEN1_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_CKEN1) >> I2S_SYNCBUSY_CKEN1_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_TXEN_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_TXEN) >> I2S_SYNCBUSY_TXEN_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_RXEN_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_RXEN) >> I2S_SYNCBUSY_RXEN_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_TXDATA_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_TXDATA) >> I2S_SYNCBUSY_TXDATA_Pos; +} + +static inline bool hri_i2s_get_SYNCBUSY_RXDATA_bit(const void *const hw) +{ + return (((I2s *)hw)->SYNCBUSY.reg & I2S_SYNCBUSY_RXDATA) >> I2S_SYNCBUSY_RXDATA_Pos; +} + +static inline hri_i2s_syncbusy_reg_t hri_i2s_get_SYNCBUSY_reg(const void *const hw, hri_i2s_syncbusy_reg_t mask) +{ + uint16_t tmp; + tmp = ((I2s *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_i2s_syncbusy_reg_t hri_i2s_read_SYNCBUSY_reg(const void *const hw) +{ + return ((I2s *)hw)->SYNCBUSY.reg; +} + +static inline hri_i2s_rxdata_reg_t hri_i2s_get_RXDATA_DATA_bf(const void *const hw, hri_i2s_rxdata_reg_t mask) +{ + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + return (((I2s *)hw)->RXDATA.reg & I2S_RXDATA_DATA(mask)) >> I2S_RXDATA_DATA_Pos; +} + +static inline hri_i2s_rxdata_reg_t hri_i2s_read_RXDATA_DATA_bf(const void *const hw) +{ + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + return (((I2s *)hw)->RXDATA.reg & I2S_RXDATA_DATA_Msk) >> I2S_RXDATA_DATA_Pos; +} + +static inline hri_i2s_rxdata_reg_t hri_i2s_get_RXDATA_reg(const void *const hw, hri_i2s_rxdata_reg_t mask) +{ + uint32_t tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + tmp = ((I2s *)hw)->RXDATA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_i2s_rxdata_reg_t hri_i2s_read_RXDATA_reg(const void *const hw) +{ + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + return ((I2s *)hw)->RXDATA.reg; +} + +static inline void hri_i2s_set_CTRLA_SWRST_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_SWRST; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp = (tmp & I2S_CTRLA_SWRST) >> I2S_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_set_CTRLA_ENABLE_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_ENABLE; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp = (tmp & I2S_CTRLA_ENABLE) >> I2S_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp &= ~I2S_CTRLA_ENABLE; + tmp |= value << I2S_CTRLA_ENABLE_Pos; + ((I2s *)hw)->CTRLA.reg = tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_ENABLE; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_ENABLE; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CTRLA_CKEN0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_CKEN0; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CTRLA_CKEN0_bit(const void *const hw) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp = (tmp & I2S_CTRLA_CKEN0) >> I2S_CTRLA_CKEN0_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CTRLA_CKEN0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp &= ~I2S_CTRLA_CKEN0; + tmp |= value << I2S_CTRLA_CKEN0_Pos; + ((I2s *)hw)->CTRLA.reg = tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CTRLA_CKEN0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_CKEN0; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CTRLA_CKEN0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_CKEN0; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CTRLA_CKEN1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_CKEN1; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CTRLA_CKEN1_bit(const void *const hw) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp = (tmp & I2S_CTRLA_CKEN1) >> I2S_CTRLA_CKEN1_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CTRLA_CKEN1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp &= ~I2S_CTRLA_CKEN1; + tmp |= value << I2S_CTRLA_CKEN1_Pos; + ((I2s *)hw)->CTRLA.reg = tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CTRLA_CKEN1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_CKEN1; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CTRLA_CKEN1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_CKEN1; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CTRLA_TXEN_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_TXEN; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CTRLA_TXEN_bit(const void *const hw) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp = (tmp & I2S_CTRLA_TXEN) >> I2S_CTRLA_TXEN_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CTRLA_TXEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp &= ~I2S_CTRLA_TXEN; + tmp |= value << I2S_CTRLA_TXEN_Pos; + ((I2s *)hw)->CTRLA.reg = tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CTRLA_TXEN_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_TXEN; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CTRLA_TXEN_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_TXEN; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CTRLA_RXEN_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg |= I2S_CTRLA_RXEN; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CTRLA_RXEN_bit(const void *const hw) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp = (tmp & I2S_CTRLA_RXEN) >> I2S_CTRLA_RXEN_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CTRLA_RXEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp &= ~I2S_CTRLA_RXEN; + tmp |= value << I2S_CTRLA_RXEN_Pos; + ((I2s *)hw)->CTRLA.reg = tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CTRLA_RXEN_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg &= ~I2S_CTRLA_RXEN; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CTRLA_RXEN_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg ^= I2S_CTRLA_RXEN; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg |= mask; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_ctrla_reg_t hri_i2s_get_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + tmp = ((I2s *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_i2s_write_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t data) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg = data; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg &= ~mask; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CTRLA_reg(const void *const hw, hri_i2s_ctrla_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CTRLA.reg ^= mask; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_ctrla_reg_t hri_i2s_read_CTRLA_reg(const void *const hw) +{ + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_SWRST | I2S_SYNCBUSY_ENABLE | I2S_SYNCBUSY_TXEN | I2S_SYNCBUSY_RXEN); + return ((I2s *)hw)->CTRLA.reg; +} + +static inline void hri_i2s_set_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_BITDELAY; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_BITDELAY) >> I2S_CLKCTRL_BITDELAY_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_BITDELAY; + tmp |= value << I2S_CLKCTRL_BITDELAY_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_BITDELAY; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_BITDELAY_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_BITDELAY; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_FSSEL) >> I2S_CLKCTRL_FSSEL_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_FSSEL; + tmp |= value << I2S_CLKCTRL_FSSEL_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_FSSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_FSINV) >> I2S_CLKCTRL_FSINV_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_FSINV; + tmp |= value << I2S_CLKCTRL_FSINV_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_FSINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_FSOUTINV) >> I2S_CLKCTRL_FSOUTINV_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_FSOUTINV; + tmp |= value << I2S_CLKCTRL_FSOUTINV_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_FSOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SCKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_SCKSEL) >> I2S_CLKCTRL_SCKSEL_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_SCKSEL; + tmp |= value << I2S_CLKCTRL_SCKSEL_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SCKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_SCKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SCKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SCKOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_SCKOUTINV) >> I2S_CLKCTRL_SCKOUTINV_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_SCKOUTINV; + tmp |= value << I2S_CLKCTRL_SCKOUTINV_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SCKOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_SCKOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SCKOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKSEL) >> I2S_CLKCTRL_MCKSEL_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_MCKSEL; + tmp |= value << I2S_CLKCTRL_MCKSEL_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_MCKSEL_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKEN; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKEN) >> I2S_CLKCTRL_MCKEN_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_MCKEN; + tmp |= value << I2S_CLKCTRL_MCKEN_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKEN; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_MCKEN_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKEN; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKOUTINV) >> I2S_CLKCTRL_MCKOUTINV_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_MCKOUTINV; + tmp |= value << I2S_CLKCTRL_MCKOUTINV_Pos; + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_MCKOUTINV_bit(const void *const hw, uint8_t index) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKOUTINV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_SLOTSIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, + hri_i2s_clkctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_SLOTSIZE(mask)) >> I2S_CLKCTRL_SLOTSIZE_Pos; + return tmp; +} + +static inline void hri_i2s_write_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_SLOTSIZE_Msk; + tmp |= I2S_CLKCTRL_SLOTSIZE(data); + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_SLOTSIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_SLOTSIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_SLOTSIZE_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_SLOTSIZE_Msk) >> I2S_CLKCTRL_SLOTSIZE_Pos; + return tmp; +} + +static inline void hri_i2s_set_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_NBSLOTS(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, + hri_i2s_clkctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_NBSLOTS(mask)) >> I2S_CLKCTRL_NBSLOTS_Pos; + return tmp; +} + +static inline void hri_i2s_write_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_NBSLOTS_Msk; + tmp |= I2S_CLKCTRL_NBSLOTS(data); + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_NBSLOTS(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_NBSLOTS(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_NBSLOTS_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_NBSLOTS_Msk) >> I2S_CLKCTRL_NBSLOTS_Pos; + return tmp; +} + +static inline void hri_i2s_set_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_FSWIDTH(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, + hri_i2s_clkctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_FSWIDTH(mask)) >> I2S_CLKCTRL_FSWIDTH_Pos; + return tmp; +} + +static inline void hri_i2s_write_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_FSWIDTH_Msk; + tmp |= I2S_CLKCTRL_FSWIDTH(data); + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_FSWIDTH(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_FSWIDTH(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_FSWIDTH_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_FSWIDTH_Msk) >> I2S_CLKCTRL_FSWIDTH_Pos; + return tmp; +} + +static inline void hri_i2s_set_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKDIV(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, + hri_i2s_clkctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKDIV(mask)) >> I2S_CLKCTRL_MCKDIV_Pos; + return tmp; +} + +static inline void hri_i2s_write_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_MCKDIV_Msk; + tmp |= I2S_CLKCTRL_MCKDIV(data); + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKDIV(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKDIV(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_MCKDIV_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKDIV_Msk) >> I2S_CLKCTRL_MCKDIV_Pos; + return tmp; +} + +static inline void hri_i2s_set_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= I2S_CLKCTRL_MCKOUTDIV(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, + hri_i2s_clkctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKOUTDIV(mask)) >> I2S_CLKCTRL_MCKOUTDIV_Pos; + return tmp; +} + +static inline void hri_i2s_write_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= ~I2S_CLKCTRL_MCKOUTDIV_Msk; + tmp |= I2S_CLKCTRL_MCKOUTDIV(data); + ((I2s *)hw)->CLKCTRL[index].reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~I2S_CLKCTRL_MCKOUTDIV(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= I2S_CLKCTRL_MCKOUTDIV(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_MCKOUTDIV_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp = (tmp & I2S_CLKCTRL_MCKOUTDIV_Msk) >> I2S_CLKCTRL_MCKOUTDIV_Pos; + return tmp; +} + +static inline void hri_i2s_set_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg |= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_get_CLKCTRL_reg(const void *const hw, uint8_t index, + hri_i2s_clkctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->CLKCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_i2s_write_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t data) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg = data; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg &= ~mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_CLKCTRL_reg(const void *const hw, uint8_t index, hri_i2s_clkctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->CLKCTRL[index].reg ^= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_clkctrl_reg_t hri_i2s_read_CLKCTRL_reg(const void *const hw, uint8_t index) +{ + return ((I2s *)hw)->CLKCTRL[index].reg; +} + +static inline void hri_i2s_set_TXCTRL_TXSAME_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_TXSAME; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_TXSAME_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_TXSAME) >> I2S_TXCTRL_TXSAME_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_TXSAME_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_TXSAME; + tmp |= value << I2S_TXCTRL_TXSAME_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_TXSAME_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_TXSAME; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_TXSAME_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_TXSAME; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTADJ_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTADJ) >> I2S_TXCTRL_SLOTADJ_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTADJ_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTADJ; + tmp |= value << I2S_TXCTRL_SLOTADJ_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_WORDADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_WORDADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_WORDADJ_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_WORDADJ) >> I2S_TXCTRL_WORDADJ_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_WORDADJ_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_WORDADJ; + tmp |= value << I2S_TXCTRL_WORDADJ_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_WORDADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_WORDADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_WORDADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_WORDADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_BITREV_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_BITREV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_BITREV_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_BITREV) >> I2S_TXCTRL_BITREV_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_BITREV_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_BITREV; + tmp |= value << I2S_TXCTRL_BITREV_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_BITREV_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_BITREV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_BITREV_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_BITREV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS0) >> I2S_TXCTRL_SLOTDIS0_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS0; + tmp |= value << I2S_TXCTRL_SLOTDIS0_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS1) >> I2S_TXCTRL_SLOTDIS1_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS1; + tmp |= value << I2S_TXCTRL_SLOTDIS1_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS2_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS2; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS2) >> I2S_TXCTRL_SLOTDIS2_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS2; + tmp |= value << I2S_TXCTRL_SLOTDIS2_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS2_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS2; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS2_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS2; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS3_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS3; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS3) >> I2S_TXCTRL_SLOTDIS3_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS3; + tmp |= value << I2S_TXCTRL_SLOTDIS3_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS3_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS3; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS3_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS3; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS4_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS4; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS4) >> I2S_TXCTRL_SLOTDIS4_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS4; + tmp |= value << I2S_TXCTRL_SLOTDIS4_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS4_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS4; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS4_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS4; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS5_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS5; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS5) >> I2S_TXCTRL_SLOTDIS5_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS5; + tmp |= value << I2S_TXCTRL_SLOTDIS5_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS5_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS5; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS5_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS5; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS6_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS6; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS6) >> I2S_TXCTRL_SLOTDIS6_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS6; + tmp |= value << I2S_TXCTRL_SLOTDIS6_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS6_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS6; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS6_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS6; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_SLOTDIS7_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_SLOTDIS7; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_SLOTDIS7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_SLOTDIS7) >> I2S_TXCTRL_SLOTDIS7_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_SLOTDIS7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_SLOTDIS7; + tmp |= value << I2S_TXCTRL_SLOTDIS7_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_SLOTDIS7_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_SLOTDIS7; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_SLOTDIS7_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_SLOTDIS7; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_MONO_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_MONO; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_MONO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_MONO) >> I2S_TXCTRL_MONO_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_MONO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_MONO; + tmp |= value << I2S_TXCTRL_MONO_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_MONO_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_MONO; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_MONO_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_MONO; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_DMA_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_DMA; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_TXCTRL_DMA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_DMA) >> I2S_TXCTRL_DMA_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_TXCTRL_DMA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_DMA; + tmp |= value << I2S_TXCTRL_DMA_Pos; + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_DMA_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_DMA; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_DMA_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_DMA; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_TXDEFAULT(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_TXDEFAULT(mask)) >> I2S_TXCTRL_TXDEFAULT_Pos; + return tmp; +} + +static inline void hri_i2s_write_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_TXDEFAULT_Msk; + tmp |= I2S_TXCTRL_TXDEFAULT(data); + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_TXDEFAULT(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_TXDEFAULT_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_TXDEFAULT(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_TXDEFAULT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_TXDEFAULT_Msk) >> I2S_TXCTRL_TXDEFAULT_Pos; + return tmp; +} + +static inline void hri_i2s_set_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_DATASIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_DATASIZE(mask)) >> I2S_TXCTRL_DATASIZE_Pos; + return tmp; +} + +static inline void hri_i2s_write_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_DATASIZE_Msk; + tmp |= I2S_TXCTRL_DATASIZE(data); + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_DATASIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_DATASIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_DATASIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_DATASIZE_Msk) >> I2S_TXCTRL_DATASIZE_Pos; + return tmp; +} + +static inline void hri_i2s_set_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= I2S_TXCTRL_EXTEND(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_EXTEND(mask)) >> I2S_TXCTRL_EXTEND_Pos; + return tmp; +} + +static inline void hri_i2s_write_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= ~I2S_TXCTRL_EXTEND_Msk; + tmp |= I2S_TXCTRL_EXTEND(data); + ((I2s *)hw)->TXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~I2S_TXCTRL_EXTEND(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_EXTEND_bf(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= I2S_TXCTRL_EXTEND(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_EXTEND_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp = (tmp & I2S_TXCTRL_EXTEND_Msk) >> I2S_TXCTRL_EXTEND_Pos; + return tmp; +} + +static inline void hri_i2s_set_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg |= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_get_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->TXCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_i2s_write_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t data) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg = data; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg &= ~mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_TXCTRL_reg(const void *const hw, hri_i2s_txctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXCTRL.reg ^= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_txctrl_reg_t hri_i2s_read_TXCTRL_reg(const void *const hw) +{ + return ((I2s *)hw)->TXCTRL.reg; +} + +static inline void hri_i2s_set_RXCTRL_CLKSEL_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_CLKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_CLKSEL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_CLKSEL) >> I2S_RXCTRL_CLKSEL_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_CLKSEL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_CLKSEL; + tmp |= value << I2S_RXCTRL_CLKSEL_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_CLKSEL_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_CLKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_CLKSEL_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_CLKSEL; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTADJ_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTADJ) >> I2S_RXCTRL_SLOTADJ_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTADJ_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTADJ; + tmp |= value << I2S_RXCTRL_SLOTADJ_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_WORDADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_WORDADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_WORDADJ_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_WORDADJ) >> I2S_RXCTRL_WORDADJ_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_WORDADJ_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_WORDADJ; + tmp |= value << I2S_RXCTRL_WORDADJ_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_WORDADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_WORDADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_WORDADJ_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_WORDADJ; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_BITREV_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_BITREV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_BITREV_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_BITREV) >> I2S_RXCTRL_BITREV_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_BITREV_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_BITREV; + tmp |= value << I2S_RXCTRL_BITREV_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_BITREV_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_BITREV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_BITREV_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_BITREV; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS0) >> I2S_RXCTRL_SLOTDIS0_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS0; + tmp |= value << I2S_RXCTRL_SLOTDIS0_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS0_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS0; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS1) >> I2S_RXCTRL_SLOTDIS1_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS1; + tmp |= value << I2S_RXCTRL_SLOTDIS1_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS1_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS1; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS2_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS2; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS2) >> I2S_RXCTRL_SLOTDIS2_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS2; + tmp |= value << I2S_RXCTRL_SLOTDIS2_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS2_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS2; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS2_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS2; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS3_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS3; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS3) >> I2S_RXCTRL_SLOTDIS3_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS3; + tmp |= value << I2S_RXCTRL_SLOTDIS3_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS3_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS3; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS3_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS3; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS4_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS4; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS4) >> I2S_RXCTRL_SLOTDIS4_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS4; + tmp |= value << I2S_RXCTRL_SLOTDIS4_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS4_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS4; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS4_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS4; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS5_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS5; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS5) >> I2S_RXCTRL_SLOTDIS5_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS5; + tmp |= value << I2S_RXCTRL_SLOTDIS5_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS5_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS5; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS5_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS5; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS6_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS6; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS6) >> I2S_RXCTRL_SLOTDIS6_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS6; + tmp |= value << I2S_RXCTRL_SLOTDIS6_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS6_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS6; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS6_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS6; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SLOTDIS7_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SLOTDIS7; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_SLOTDIS7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SLOTDIS7) >> I2S_RXCTRL_SLOTDIS7_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_SLOTDIS7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SLOTDIS7; + tmp |= value << I2S_RXCTRL_SLOTDIS7_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SLOTDIS7_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SLOTDIS7; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SLOTDIS7_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SLOTDIS7; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_MONO_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_MONO; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_MONO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_MONO) >> I2S_RXCTRL_MONO_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_MONO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_MONO; + tmp |= value << I2S_RXCTRL_MONO_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_MONO_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_MONO; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_MONO_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_MONO; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_DMA_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_DMA; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_DMA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_DMA) >> I2S_RXCTRL_DMA_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_DMA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_DMA; + tmp |= value << I2S_RXCTRL_DMA_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_DMA_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_DMA; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_DMA_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_DMA; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_RXLOOP_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_RXLOOP; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_i2s_get_RXCTRL_RXLOOP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_RXLOOP) >> I2S_RXCTRL_RXLOOP_Pos; + return (bool)tmp; +} + +static inline void hri_i2s_write_RXCTRL_RXLOOP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_RXLOOP; + tmp |= value << I2S_RXCTRL_RXLOOP_Pos; + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_RXLOOP_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_RXLOOP; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_RXLOOP_bit(const void *const hw) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_RXLOOP; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_set_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_SERMODE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SERMODE(mask)) >> I2S_RXCTRL_SERMODE_Pos; + return tmp; +} + +static inline void hri_i2s_write_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_SERMODE_Msk; + tmp |= I2S_RXCTRL_SERMODE(data); + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_SERMODE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_SERMODE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_SERMODE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_SERMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_SERMODE_Msk) >> I2S_RXCTRL_SERMODE_Pos; + return tmp; +} + +static inline void hri_i2s_set_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_DATASIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_DATASIZE(mask)) >> I2S_RXCTRL_DATASIZE_Pos; + return tmp; +} + +static inline void hri_i2s_write_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_DATASIZE_Msk; + tmp |= I2S_RXCTRL_DATASIZE(data); + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_DATASIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_DATASIZE_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_DATASIZE(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_DATASIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_DATASIZE_Msk) >> I2S_RXCTRL_DATASIZE_Pos; + return tmp; +} + +static inline void hri_i2s_set_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= I2S_RXCTRL_EXTEND(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_EXTEND(mask)) >> I2S_RXCTRL_EXTEND_Pos; + return tmp; +} + +static inline void hri_i2s_write_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t data) +{ + uint32_t tmp; + I2S_CRITICAL_SECTION_ENTER(); + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= ~I2S_RXCTRL_EXTEND_Msk; + tmp |= I2S_RXCTRL_EXTEND(data); + ((I2s *)hw)->RXCTRL.reg = tmp; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~I2S_RXCTRL_EXTEND(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_EXTEND_bf(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= I2S_RXCTRL_EXTEND(mask); + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_EXTEND_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp = (tmp & I2S_RXCTRL_EXTEND_Msk) >> I2S_RXCTRL_EXTEND_Pos; + return tmp; +} + +static inline void hri_i2s_set_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg |= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_get_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((I2s *)hw)->RXCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_i2s_write_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t data) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg = data; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_clear_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg &= ~mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_i2s_toggle_RXCTRL_reg(const void *const hw, hri_i2s_rxctrl_reg_t mask) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->RXCTRL.reg ^= mask; + I2S_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_i2s_rxctrl_reg_t hri_i2s_read_RXCTRL_reg(const void *const hw) +{ + return ((I2s *)hw)->RXCTRL.reg; +} + +static inline void hri_i2s_write_TXDATA_reg(const void *const hw, hri_i2s_txdata_reg_t data) +{ + I2S_CRITICAL_SECTION_ENTER(); + ((I2s *)hw)->TXDATA.reg = data; + hri_i2s_wait_for_sync(hw, I2S_SYNCBUSY_MASK); + I2S_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_I2S_E54_H_INCLUDED */ +#endif /* _SAME54_I2S_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_icm_e54.h b/software/firmware/oracle_same54n19a/hri/hri_icm_e54.h new file mode 100644 index 00000000..374caa4f --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_icm_e54.h @@ -0,0 +1,761 @@ +/** + * \file + * + * \brief SAM ICM + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_ICM_COMPONENT_ +#ifndef _HRI_ICM_E54_H_INCLUDED_ +#define _HRI_ICM_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_ICM_CRITICAL_SECTIONS) +#define ICM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define ICM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define ICM_CRITICAL_SECTION_ENTER() +#define ICM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_icm_cfg_reg_t; +typedef uint32_t hri_icm_ctrl_reg_t; +typedef uint32_t hri_icm_dscr_reg_t; +typedef uint32_t hri_icm_hash_reg_t; +typedef uint32_t hri_icm_imr_reg_t; +typedef uint32_t hri_icm_isr_reg_t; +typedef uint32_t hri_icm_sr_reg_t; +typedef uint32_t hri_icm_uasr_reg_t; +typedef uint32_t hri_icm_uihval_reg_t; +typedef uint32_t hri_icmdescriptor_raddr_reg_t; +typedef uint32_t hri_icmdescriptor_rcfg_reg_t; +typedef uint32_t hri_icmdescriptor_rctrl_reg_t; +typedef uint32_t hri_icmdescriptor_rnext_reg_t; + +static inline void hri_icmdescriptor_set_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RADDR.reg |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_raddr_reg_t hri_icmdescriptor_get_RADDR_reg(const void *const hw, + hri_icmdescriptor_raddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((IcmDescriptor *)hw)->RADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_icmdescriptor_write_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RADDR.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_clear_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RADDR.reg &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_toggle_RADDR_reg(const void *const hw, hri_icmdescriptor_raddr_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RADDR.reg ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_raddr_reg_t hri_icmdescriptor_read_RADDR_reg(const void *const hw) +{ + return ((IcmDescriptor *)hw)->RADDR.reg; +} + +static inline void hri_icmdescriptor_set_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCFG.reg |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_rcfg_reg_t hri_icmdescriptor_get_RCFG_reg(const void *const hw, + hri_icmdescriptor_rcfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((IcmDescriptor *)hw)->RCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_icmdescriptor_write_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCFG.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_clear_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCFG.reg &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_toggle_RCFG_reg(const void *const hw, hri_icmdescriptor_rcfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCFG.reg ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_rcfg_reg_t hri_icmdescriptor_read_RCFG_reg(const void *const hw) +{ + return ((IcmDescriptor *)hw)->RCFG.reg; +} + +static inline void hri_icmdescriptor_set_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCTRL.reg |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_rctrl_reg_t hri_icmdescriptor_get_RCTRL_reg(const void *const hw, + hri_icmdescriptor_rctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((IcmDescriptor *)hw)->RCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_icmdescriptor_write_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCTRL.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_clear_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCTRL.reg &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_toggle_RCTRL_reg(const void *const hw, hri_icmdescriptor_rctrl_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RCTRL.reg ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_rctrl_reg_t hri_icmdescriptor_read_RCTRL_reg(const void *const hw) +{ + return ((IcmDescriptor *)hw)->RCTRL.reg; +} + +static inline void hri_icmdescriptor_set_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RNEXT.reg |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_rnext_reg_t hri_icmdescriptor_get_RNEXT_reg(const void *const hw, + hri_icmdescriptor_rnext_reg_t mask) +{ + uint32_t tmp; + tmp = ((IcmDescriptor *)hw)->RNEXT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_icmdescriptor_write_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RNEXT.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_clear_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RNEXT.reg &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icmdescriptor_toggle_RNEXT_reg(const void *const hw, hri_icmdescriptor_rnext_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((IcmDescriptor *)hw)->RNEXT.reg ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icmdescriptor_rnext_reg_t hri_icmdescriptor_read_RNEXT_reg(const void *const hw) +{ + return ((IcmDescriptor *)hw)->RNEXT.reg; +} + +static inline void hri_icm_set_IMR_URAD_bit(const void *const hw) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_URAD; +} + +static inline bool hri_icm_get_IMR_URAD_bit(const void *const hw) +{ + return (((Icm *)hw)->IMR.reg & ICM_IMR_URAD) >> ICM_IMR_URAD_Pos; +} + +static inline void hri_icm_write_IMR_URAD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Icm *)hw)->IDR.reg = ICM_IMR_URAD; + } else { + ((Icm *)hw)->IER.reg = ICM_IMR_URAD; + } +} + +static inline void hri_icm_clear_IMR_URAD_bit(const void *const hw) +{ + ((Icm *)hw)->IDR.reg = ICM_IMR_URAD; +} + +static inline void hri_icm_set_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RHC(mask); +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RHC(mask)) >> ICM_IMR_RHC_Pos; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_RHC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RHC_Msk) >> ICM_IMR_RHC_Pos; + return tmp; +} + +static inline void hri_icm_write_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RHC(data); + ((Icm *)hw)->IDR.reg = ~ICM_IMR_RHC(data); +} + +static inline void hri_icm_clear_IMR_RHC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IDR.reg = ICM_IMR_RHC(mask); +} + +static inline void hri_icm_set_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RDM(mask); +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RDM(mask)) >> ICM_IMR_RDM_Pos; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_RDM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RDM_Msk) >> ICM_IMR_RDM_Pos; + return tmp; +} + +static inline void hri_icm_write_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RDM(data); + ((Icm *)hw)->IDR.reg = ~ICM_IMR_RDM(data); +} + +static inline void hri_icm_clear_IMR_RDM_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IDR.reg = ICM_IMR_RDM(mask); +} + +static inline void hri_icm_set_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RBE(mask); +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RBE(mask)) >> ICM_IMR_RBE_Pos; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_RBE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RBE_Msk) >> ICM_IMR_RBE_Pos; + return tmp; +} + +static inline void hri_icm_write_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RBE(data); + ((Icm *)hw)->IDR.reg = ~ICM_IMR_RBE(data); +} + +static inline void hri_icm_clear_IMR_RBE_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IDR.reg = ICM_IMR_RBE(mask); +} + +static inline void hri_icm_set_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RWC(mask); +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RWC(mask)) >> ICM_IMR_RWC_Pos; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_RWC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RWC_Msk) >> ICM_IMR_RWC_Pos; + return tmp; +} + +static inline void hri_icm_write_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RWC(data); + ((Icm *)hw)->IDR.reg = ~ICM_IMR_RWC(data); +} + +static inline void hri_icm_clear_IMR_RWC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IDR.reg = ICM_IMR_RWC(mask); +} + +static inline void hri_icm_set_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_REC(mask); +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_REC(mask)) >> ICM_IMR_REC_Pos; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_REC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_REC_Msk) >> ICM_IMR_REC_Pos; + return tmp; +} + +static inline void hri_icm_write_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_REC(data); + ((Icm *)hw)->IDR.reg = ~ICM_IMR_REC(data); +} + +static inline void hri_icm_clear_IMR_REC_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IDR.reg = ICM_IMR_REC(mask); +} + +static inline void hri_icm_set_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RSU(mask); +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RSU(mask)) >> ICM_IMR_RSU_Pos; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_RSU_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp = (tmp & ICM_IMR_RSU_Msk) >> ICM_IMR_RSU_Pos; + return tmp; +} + +static inline void hri_icm_write_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->IER.reg = ICM_IMR_RSU(data); + ((Icm *)hw)->IDR.reg = ~ICM_IMR_RSU(data); +} + +static inline void hri_icm_clear_IMR_RSU_bf(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IDR.reg = ICM_IMR_RSU(mask); +} + +static inline void hri_icm_set_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IER.reg = mask; +} + +static inline hri_icm_imr_reg_t hri_icm_get_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->IMR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_icm_imr_reg_t hri_icm_read_IMR_reg(const void *const hw) +{ + return ((Icm *)hw)->IMR.reg; +} + +static inline void hri_icm_write_IMR_reg(const void *const hw, hri_icm_imr_reg_t data) +{ + ((Icm *)hw)->IER.reg = data; + ((Icm *)hw)->IDR.reg = ~data; +} + +static inline void hri_icm_clear_IMR_reg(const void *const hw, hri_icm_imr_reg_t mask) +{ + ((Icm *)hw)->IDR.reg = mask; +} + +static inline bool hri_icm_get_SR_ENABLE_bit(const void *const hw) +{ + return (((Icm *)hw)->SR.reg & ICM_SR_ENABLE) >> ICM_SR_ENABLE_Pos; +} + +static inline hri_icm_sr_reg_t hri_icm_get_SR_RAWRMDIS_bf(const void *const hw, hri_icm_sr_reg_t mask) +{ + return (((Icm *)hw)->SR.reg & ICM_SR_RAWRMDIS(mask)) >> ICM_SR_RAWRMDIS_Pos; +} + +static inline hri_icm_sr_reg_t hri_icm_read_SR_RAWRMDIS_bf(const void *const hw) +{ + return (((Icm *)hw)->SR.reg & ICM_SR_RAWRMDIS_Msk) >> ICM_SR_RAWRMDIS_Pos; +} + +static inline hri_icm_sr_reg_t hri_icm_get_SR_RMDIS_bf(const void *const hw, hri_icm_sr_reg_t mask) +{ + return (((Icm *)hw)->SR.reg & ICM_SR_RMDIS(mask)) >> ICM_SR_RMDIS_Pos; +} + +static inline hri_icm_sr_reg_t hri_icm_read_SR_RMDIS_bf(const void *const hw) +{ + return (((Icm *)hw)->SR.reg & ICM_SR_RMDIS_Msk) >> ICM_SR_RMDIS_Pos; +} + +static inline hri_icm_sr_reg_t hri_icm_get_SR_reg(const void *const hw, hri_icm_sr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->SR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_icm_sr_reg_t hri_icm_read_SR_reg(const void *const hw) +{ + return ((Icm *)hw)->SR.reg; +} + +static inline bool hri_icm_get_ISR_URAD_bit(const void *const hw) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_URAD) >> ICM_ISR_URAD_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_get_ISR_RHC_bf(const void *const hw, hri_icm_isr_reg_t mask) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RHC(mask)) >> ICM_ISR_RHC_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_read_ISR_RHC_bf(const void *const hw) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RHC_Msk) >> ICM_ISR_RHC_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_get_ISR_RDM_bf(const void *const hw, hri_icm_isr_reg_t mask) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RDM(mask)) >> ICM_ISR_RDM_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_read_ISR_RDM_bf(const void *const hw) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RDM_Msk) >> ICM_ISR_RDM_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_get_ISR_RBE_bf(const void *const hw, hri_icm_isr_reg_t mask) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RBE(mask)) >> ICM_ISR_RBE_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_read_ISR_RBE_bf(const void *const hw) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RBE_Msk) >> ICM_ISR_RBE_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_get_ISR_RWC_bf(const void *const hw, hri_icm_isr_reg_t mask) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RWC(mask)) >> ICM_ISR_RWC_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_read_ISR_RWC_bf(const void *const hw) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RWC_Msk) >> ICM_ISR_RWC_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_get_ISR_REC_bf(const void *const hw, hri_icm_isr_reg_t mask) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_REC(mask)) >> ICM_ISR_REC_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_read_ISR_REC_bf(const void *const hw) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_REC_Msk) >> ICM_ISR_REC_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_get_ISR_RSU_bf(const void *const hw, hri_icm_isr_reg_t mask) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RSU(mask)) >> ICM_ISR_RSU_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_read_ISR_RSU_bf(const void *const hw) +{ + return (((Icm *)hw)->ISR.reg & ICM_ISR_RSU_Msk) >> ICM_ISR_RSU_Pos; +} + +static inline hri_icm_isr_reg_t hri_icm_get_ISR_reg(const void *const hw, hri_icm_isr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->ISR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_icm_isr_reg_t hri_icm_read_ISR_reg(const void *const hw) +{ + return ((Icm *)hw)->ISR.reg; +} + +static inline hri_icm_uasr_reg_t hri_icm_get_UASR_URAT_bf(const void *const hw, hri_icm_uasr_reg_t mask) +{ + return (((Icm *)hw)->UASR.reg & ICM_UASR_URAT(mask)) >> ICM_UASR_URAT_Pos; +} + +static inline hri_icm_uasr_reg_t hri_icm_read_UASR_URAT_bf(const void *const hw) +{ + return (((Icm *)hw)->UASR.reg & ICM_UASR_URAT_Msk) >> ICM_UASR_URAT_Pos; +} + +static inline hri_icm_uasr_reg_t hri_icm_get_UASR_reg(const void *const hw, hri_icm_uasr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->UASR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_icm_uasr_reg_t hri_icm_read_UASR_reg(const void *const hw) +{ + return ((Icm *)hw)->UASR.reg; +} + +static inline void hri_icm_set_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->CFG.reg |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_cfg_reg_t hri_icm_get_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->CFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_icm_write_CFG_reg(const void *const hw, hri_icm_cfg_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->CFG.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_clear_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->CFG.reg &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_toggle_CFG_reg(const void *const hw, hri_icm_cfg_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->CFG.reg ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_cfg_reg_t hri_icm_read_CFG_reg(const void *const hw) +{ + return ((Icm *)hw)->CFG.reg; +} + +static inline void hri_icm_set_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->DSCR.reg |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_dscr_reg_t hri_icm_get_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->DSCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_icm_write_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->DSCR.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_clear_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->DSCR.reg &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_toggle_DSCR_reg(const void *const hw, hri_icm_dscr_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->DSCR.reg ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_dscr_reg_t hri_icm_read_DSCR_reg(const void *const hw) +{ + return ((Icm *)hw)->DSCR.reg; +} + +static inline void hri_icm_set_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->HASH.reg |= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_hash_reg_t hri_icm_get_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) +{ + uint32_t tmp; + tmp = ((Icm *)hw)->HASH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_icm_write_HASH_reg(const void *const hw, hri_icm_hash_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->HASH.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_clear_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->HASH.reg &= ~mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_toggle_HASH_reg(const void *const hw, hri_icm_hash_reg_t mask) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->HASH.reg ^= mask; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_icm_hash_reg_t hri_icm_read_HASH_reg(const void *const hw) +{ + return ((Icm *)hw)->HASH.reg; +} + +static inline void hri_icm_write_CTRL_reg(const void *const hw, hri_icm_ctrl_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->CTRL.reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_icm_write_UIHVAL_reg(const void *const hw, uint8_t index, hri_icm_uihval_reg_t data) +{ + ICM_CRITICAL_SECTION_ENTER(); + ((Icm *)hw)->UIHVAL[index].reg = data; + ICM_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_ICM_E54_H_INCLUDED */ +#endif /* _SAME54_ICM_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_mclk_e54.h b/software/firmware/oracle_same54n19a/hri/hri_mclk_e54.h new file mode 100644 index 00000000..7e3963b1 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_mclk_e54.h @@ -0,0 +1,3556 @@ +/** + * \file + * + * \brief SAM MCLK + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_MCLK_COMPONENT_ +#ifndef _HRI_MCLK_E54_H_INCLUDED_ +#define _HRI_MCLK_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_MCLK_CRITICAL_SECTIONS) +#define MCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define MCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define MCLK_CRITICAL_SECTION_ENTER() +#define MCLK_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_mclk_ahbmask_reg_t; +typedef uint32_t hri_mclk_apbamask_reg_t; +typedef uint32_t hri_mclk_apbbmask_reg_t; +typedef uint32_t hri_mclk_apbcmask_reg_t; +typedef uint32_t hri_mclk_apbdmask_reg_t; +typedef uint8_t hri_mclk_cpudiv_reg_t; +typedef uint8_t hri_mclk_hsdiv_reg_t; +typedef uint8_t hri_mclk_intenset_reg_t; +typedef uint8_t hri_mclk_intflag_reg_t; + +static inline bool hri_mclk_get_INTFLAG_CKRDY_bit(const void *const hw) +{ + return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos; +} + +static inline void hri_mclk_clear_INTFLAG_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY; +} + +static inline bool hri_mclk_get_interrupt_CKRDY_bit(const void *const hw) +{ + return (((Mclk *)hw)->INTFLAG.reg & MCLK_INTFLAG_CKRDY) >> MCLK_INTFLAG_CKRDY_Pos; +} + +static inline void hri_mclk_clear_interrupt_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTFLAG.reg = MCLK_INTFLAG_CKRDY; +} + +static inline hri_mclk_intflag_reg_t hri_mclk_get_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mclk_intflag_reg_t hri_mclk_read_INTFLAG_reg(const void *const hw) +{ + return ((Mclk *)hw)->INTFLAG.reg; +} + +static inline void hri_mclk_clear_INTFLAG_reg(const void *const hw, hri_mclk_intflag_reg_t mask) +{ + ((Mclk *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_mclk_set_INTEN_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY; +} + +static inline bool hri_mclk_get_INTEN_CKRDY_bit(const void *const hw) +{ + return (((Mclk *)hw)->INTENSET.reg & MCLK_INTENSET_CKRDY) >> MCLK_INTENSET_CKRDY_Pos; +} + +static inline void hri_mclk_write_INTEN_CKRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY; + } else { + ((Mclk *)hw)->INTENSET.reg = MCLK_INTENSET_CKRDY; + } +} + +static inline void hri_mclk_clear_INTEN_CKRDY_bit(const void *const hw) +{ + ((Mclk *)hw)->INTENCLR.reg = MCLK_INTENSET_CKRDY; +} + +static inline void hri_mclk_set_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) +{ + ((Mclk *)hw)->INTENSET.reg = mask; +} + +static inline hri_mclk_intenset_reg_t hri_mclk_get_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mclk_intenset_reg_t hri_mclk_read_INTEN_reg(const void *const hw) +{ + return ((Mclk *)hw)->INTENSET.reg; +} + +static inline void hri_mclk_write_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t data) +{ + ((Mclk *)hw)->INTENSET.reg = data; + ((Mclk *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_mclk_clear_INTEN_reg(const void *const hw, hri_mclk_intenset_reg_t mask) +{ + ((Mclk *)hw)->INTENCLR.reg = mask; +} + +static inline hri_mclk_hsdiv_reg_t hri_mclk_get_HSDIV_DIV_bf(const void *const hw, hri_mclk_hsdiv_reg_t mask) +{ + return (((Mclk *)hw)->HSDIV.reg & MCLK_HSDIV_DIV(mask)) >> MCLK_HSDIV_DIV_Pos; +} + +static inline hri_mclk_hsdiv_reg_t hri_mclk_read_HSDIV_DIV_bf(const void *const hw) +{ + return (((Mclk *)hw)->HSDIV.reg & MCLK_HSDIV_DIV_Msk) >> MCLK_HSDIV_DIV_Pos; +} + +static inline hri_mclk_hsdiv_reg_t hri_mclk_get_HSDIV_reg(const void *const hw, hri_mclk_hsdiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->HSDIV.reg; + tmp &= mask; + return tmp; +} + +static inline hri_mclk_hsdiv_reg_t hri_mclk_read_HSDIV_reg(const void *const hw) +{ + return ((Mclk *)hw)->HSDIV.reg; +} + +static inline void hri_mclk_set_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg |= MCLK_CPUDIV_DIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp = (tmp & MCLK_CPUDIV_DIV(mask)) >> MCLK_CPUDIV_DIV_Pos; + return tmp; +} + +static inline void hri_mclk_write_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t data) +{ + uint8_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp &= ~MCLK_CPUDIV_DIV_Msk; + tmp |= MCLK_CPUDIV_DIV(data); + ((Mclk *)hw)->CPUDIV.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg &= ~MCLK_CPUDIV_DIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_CPUDIV_DIV_bf(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg ^= MCLK_CPUDIV_DIV(mask); + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_DIV_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp = (tmp & MCLK_CPUDIV_DIV_Msk) >> MCLK_CPUDIV_DIV_Pos; + return tmp; +} + +static inline void hri_mclk_set_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_get_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + uint8_t tmp; + tmp = ((Mclk *)hw)->CPUDIV.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_CPUDIV_reg(const void *const hw, hri_mclk_cpudiv_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->CPUDIV.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_cpudiv_reg_t hri_mclk_read_CPUDIV_reg(const void *const hw) +{ + return ((Mclk *)hw)->CPUDIV.reg; +} + +static inline void hri_mclk_set_AHBMASK_HPB0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB0) >> MCLK_AHBMASK_HPB0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB0; + tmp |= value << MCLK_AHBMASK_HPB0_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HPB1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB1) >> MCLK_AHBMASK_HPB1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB1; + tmp |= value << MCLK_AHBMASK_HPB1_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HPB2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB2) >> MCLK_AHBMASK_HPB2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB2; + tmp |= value << MCLK_AHBMASK_HPB2_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HPB3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HPB3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HPB3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HPB3) >> MCLK_AHBMASK_HPB3_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HPB3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HPB3; + tmp |= value << MCLK_AHBMASK_HPB3_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HPB3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HPB3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HPB3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HPB3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_DSU_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_DSU) >> MCLK_AHBMASK_DSU_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_DSU_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_DSU; + tmp |= value << MCLK_AHBMASK_DSU_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HMATRIX_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HMATRIX; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HMATRIX_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HMATRIX) >> MCLK_AHBMASK_HMATRIX_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HMATRIX_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HMATRIX; + tmp |= value << MCLK_AHBMASK_HMATRIX_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HMATRIX_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HMATRIX; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HMATRIX_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HMATRIX; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_NVMCTRL) >> MCLK_AHBMASK_NVMCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_NVMCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_NVMCTRL; + tmp |= value << MCLK_AHBMASK_NVMCTRL_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_HSRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_HSRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_HSRAM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_HSRAM) >> MCLK_AHBMASK_HSRAM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_HSRAM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_HSRAM; + tmp |= value << MCLK_AHBMASK_HSRAM_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_HSRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_HSRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_HSRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_HSRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_CMCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_CMCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_CMCC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_CMCC) >> MCLK_AHBMASK_CMCC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_CMCC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_CMCC; + tmp |= value << MCLK_AHBMASK_CMCC_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_CMCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_CMCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_CMCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_CMCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_DMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_DMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_DMAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_DMAC) >> MCLK_AHBMASK_DMAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_DMAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_DMAC; + tmp |= value << MCLK_AHBMASK_DMAC_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_DMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_DMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_DMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_DMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_USB_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_USB) >> MCLK_AHBMASK_USB_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_USB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_USB; + tmp |= value << MCLK_AHBMASK_USB_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_BKUPRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_BKUPRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_BKUPRAM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_BKUPRAM) >> MCLK_AHBMASK_BKUPRAM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_BKUPRAM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_BKUPRAM; + tmp |= value << MCLK_AHBMASK_BKUPRAM_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_BKUPRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_BKUPRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_BKUPRAM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_BKUPRAM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_PAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_PAC) >> MCLK_AHBMASK_PAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_PAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_PAC; + tmp |= value << MCLK_AHBMASK_PAC_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_QSPI_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_QSPI; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_QSPI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_QSPI) >> MCLK_AHBMASK_QSPI_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_QSPI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_QSPI; + tmp |= value << MCLK_AHBMASK_QSPI_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_QSPI_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_QSPI; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_QSPI_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_QSPI; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_GMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_GMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_GMAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_GMAC) >> MCLK_AHBMASK_GMAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_GMAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_GMAC; + tmp |= value << MCLK_AHBMASK_GMAC_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_GMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_GMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_GMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_GMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_SDHC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_SDHC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_SDHC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_SDHC0) >> MCLK_AHBMASK_SDHC0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_SDHC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_SDHC0; + tmp |= value << MCLK_AHBMASK_SDHC0_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_SDHC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_SDHC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_SDHC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_SDHC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_SDHC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_SDHC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_SDHC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_SDHC1) >> MCLK_AHBMASK_SDHC1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_SDHC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_SDHC1; + tmp |= value << MCLK_AHBMASK_SDHC1_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_SDHC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_SDHC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_SDHC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_SDHC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_CAN0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_CAN0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_CAN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_CAN0) >> MCLK_AHBMASK_CAN0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_CAN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_CAN0; + tmp |= value << MCLK_AHBMASK_CAN0_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_CAN0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_CAN0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_CAN0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_CAN0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_CAN1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_CAN1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_CAN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_CAN1) >> MCLK_AHBMASK_CAN1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_CAN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_CAN1; + tmp |= value << MCLK_AHBMASK_CAN1_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_CAN1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_CAN1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_CAN1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_CAN1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_ICM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_ICM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_ICM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_ICM) >> MCLK_AHBMASK_ICM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_ICM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_ICM; + tmp |= value << MCLK_AHBMASK_ICM_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_ICM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_ICM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_ICM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_ICM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_PUKCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_PUKCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_PUKCC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_PUKCC) >> MCLK_AHBMASK_PUKCC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_PUKCC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_PUKCC; + tmp |= value << MCLK_AHBMASK_PUKCC_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_PUKCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_PUKCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_PUKCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_PUKCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_QSPI_2X_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_QSPI_2X; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_QSPI_2X_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_QSPI_2X) >> MCLK_AHBMASK_QSPI_2X_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_QSPI_2X_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_QSPI_2X; + tmp |= value << MCLK_AHBMASK_QSPI_2X_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_QSPI_2X_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_QSPI_2X; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_QSPI_2X_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_QSPI_2X; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL_SMEEPROM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_NVMCTRL_SMEEPROM) >> MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_NVMCTRL_SMEEPROM; + tmp |= value << MCLK_AHBMASK_NVMCTRL_SMEEPROM_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL_SMEEPROM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_SMEEPROM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL_SMEEPROM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= MCLK_AHBMASK_NVMCTRL_CACHE; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp = (tmp & MCLK_AHBMASK_NVMCTRL_CACHE) >> MCLK_AHBMASK_NVMCTRL_CACHE_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= ~MCLK_AHBMASK_NVMCTRL_CACHE; + tmp |= value << MCLK_AHBMASK_NVMCTRL_CACHE_Pos; + ((Mclk *)hw)->AHBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~MCLK_AHBMASK_NVMCTRL_CACHE; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_NVMCTRL_CACHE_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= MCLK_AHBMASK_NVMCTRL_CACHE; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_ahbmask_reg_t hri_mclk_get_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->AHBMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_AHBMASK_reg(const void *const hw, hri_mclk_ahbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->AHBMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_ahbmask_reg_t hri_mclk_read_AHBMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->AHBMASK.reg; +} + +static inline void hri_mclk_set_APBAMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_PAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_PAC) >> MCLK_APBAMASK_PAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_PAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_PAC; + tmp |= value << MCLK_APBAMASK_PAC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_PAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_PM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_PM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_PM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_PM) >> MCLK_APBAMASK_PM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_PM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_PM; + tmp |= value << MCLK_APBAMASK_PM_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_PM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_PM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_PM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_PM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_MCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_MCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_MCLK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_MCLK) >> MCLK_APBAMASK_MCLK_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_MCLK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_MCLK; + tmp |= value << MCLK_APBAMASK_MCLK_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_MCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_MCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_MCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_MCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_RSTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RSTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_RSTC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_RSTC) >> MCLK_APBAMASK_RSTC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_RSTC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_RSTC; + tmp |= value << MCLK_APBAMASK_RSTC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_RSTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RSTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_RSTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RSTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSCCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_OSCCTRL) >> MCLK_APBAMASK_OSCCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_OSCCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_OSCCTRL; + tmp |= value << MCLK_APBAMASK_OSCCTRL_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSCCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_OSCCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSCCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_OSC32KCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_OSC32KCTRL) >> MCLK_APBAMASK_OSC32KCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_OSC32KCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_OSC32KCTRL; + tmp |= value << MCLK_APBAMASK_OSC32KCTRL_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_OSC32KCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_OSC32KCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_OSC32KCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_SUPC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SUPC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_SUPC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_SUPC) >> MCLK_APBAMASK_SUPC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_SUPC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_SUPC; + tmp |= value << MCLK_APBAMASK_SUPC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_SUPC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SUPC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_SUPC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SUPC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_GCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_GCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_GCLK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_GCLK) >> MCLK_APBAMASK_GCLK_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_GCLK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_GCLK; + tmp |= value << MCLK_APBAMASK_GCLK_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_GCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_GCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_GCLK_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_GCLK; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_WDT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_WDT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_WDT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_WDT) >> MCLK_APBAMASK_WDT_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_WDT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_WDT; + tmp |= value << MCLK_APBAMASK_WDT_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_WDT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_WDT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_WDT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_WDT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_RTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_RTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_RTC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_RTC) >> MCLK_APBAMASK_RTC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_RTC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_RTC; + tmp |= value << MCLK_APBAMASK_RTC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_RTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_RTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_RTC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_RTC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_EIC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_EIC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_EIC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_EIC) >> MCLK_APBAMASK_EIC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_EIC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_EIC; + tmp |= value << MCLK_APBAMASK_EIC_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_EIC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_EIC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_EIC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_EIC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_FREQM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_FREQM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_FREQM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_FREQM) >> MCLK_APBAMASK_FREQM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_FREQM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_FREQM; + tmp |= value << MCLK_APBAMASK_FREQM_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_FREQM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_FREQM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_FREQM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_FREQM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_SERCOM0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SERCOM0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_SERCOM0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_SERCOM0) >> MCLK_APBAMASK_SERCOM0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_SERCOM0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_SERCOM0; + tmp |= value << MCLK_APBAMASK_SERCOM0_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_SERCOM0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SERCOM0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_SERCOM0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SERCOM0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_SERCOM1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_SERCOM1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_SERCOM1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_SERCOM1) >> MCLK_APBAMASK_SERCOM1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_SERCOM1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_SERCOM1; + tmp |= value << MCLK_APBAMASK_SERCOM1_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_SERCOM1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_SERCOM1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_SERCOM1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_SERCOM1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_TC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_TC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_TC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_TC0) >> MCLK_APBAMASK_TC0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_TC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_TC0; + tmp |= value << MCLK_APBAMASK_TC0_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_TC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_TC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_TC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_TC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_TC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= MCLK_APBAMASK_TC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBAMASK_TC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp = (tmp & MCLK_APBAMASK_TC1) >> MCLK_APBAMASK_TC1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBAMASK_TC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= ~MCLK_APBAMASK_TC1; + tmp |= value << MCLK_APBAMASK_TC1_Pos; + ((Mclk *)hw)->APBAMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_TC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~MCLK_APBAMASK_TC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_TC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= MCLK_APBAMASK_TC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbamask_reg_t hri_mclk_get_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBAMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBAMASK_reg(const void *const hw, hri_mclk_apbamask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBAMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbamask_reg_t hri_mclk_read_APBAMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBAMASK.reg; +} + +static inline void hri_mclk_set_APBBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_USB_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_USB) >> MCLK_APBBMASK_USB_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_USB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_USB; + tmp |= value << MCLK_APBBMASK_USB_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_USB_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_USB; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_DSU_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_DSU) >> MCLK_APBBMASK_DSU_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_DSU_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_DSU; + tmp |= value << MCLK_APBBMASK_DSU_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_DSU_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_DSU; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_NVMCTRL) >> MCLK_APBBMASK_NVMCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_NVMCTRL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_NVMCTRL; + tmp |= value << MCLK_APBBMASK_NVMCTRL_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_NVMCTRL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_NVMCTRL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_PORT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_PORT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_PORT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_PORT) >> MCLK_APBBMASK_PORT_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_PORT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_PORT; + tmp |= value << MCLK_APBBMASK_PORT_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_PORT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_PORT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_PORT_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_PORT; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_HMATRIX_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_HMATRIX; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_HMATRIX_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_HMATRIX) >> MCLK_APBBMASK_HMATRIX_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_HMATRIX_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_HMATRIX; + tmp |= value << MCLK_APBBMASK_HMATRIX_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_HMATRIX_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_HMATRIX; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_HMATRIX_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_HMATRIX; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_EVSYS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_EVSYS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_EVSYS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_EVSYS) >> MCLK_APBBMASK_EVSYS_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_EVSYS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_EVSYS; + tmp |= value << MCLK_APBBMASK_EVSYS_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_EVSYS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_EVSYS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_EVSYS_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_EVSYS; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_SERCOM2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_SERCOM2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_SERCOM2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_SERCOM2) >> MCLK_APBBMASK_SERCOM2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_SERCOM2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_SERCOM2; + tmp |= value << MCLK_APBBMASK_SERCOM2_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_SERCOM2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_SERCOM2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_SERCOM2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_SERCOM2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_SERCOM3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_SERCOM3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_SERCOM3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_SERCOM3) >> MCLK_APBBMASK_SERCOM3_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_SERCOM3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_SERCOM3; + tmp |= value << MCLK_APBBMASK_SERCOM3_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_SERCOM3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_SERCOM3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_SERCOM3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_SERCOM3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_TCC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TCC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_TCC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_TCC0) >> MCLK_APBBMASK_TCC0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_TCC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_TCC0; + tmp |= value << MCLK_APBBMASK_TCC0_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_TCC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TCC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_TCC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TCC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_TCC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TCC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_TCC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_TCC1) >> MCLK_APBBMASK_TCC1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_TCC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_TCC1; + tmp |= value << MCLK_APBBMASK_TCC1_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_TCC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TCC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_TCC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TCC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_TC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_TC2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_TC2) >> MCLK_APBBMASK_TC2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_TC2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_TC2; + tmp |= value << MCLK_APBBMASK_TC2_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_TC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_TC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_TC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_TC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_TC3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_TC3) >> MCLK_APBBMASK_TC3_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_TC3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_TC3; + tmp |= value << MCLK_APBBMASK_TC3_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_TC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_TC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_TC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_TC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_RAMECC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= MCLK_APBBMASK_RAMECC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBBMASK_RAMECC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp = (tmp & MCLK_APBBMASK_RAMECC) >> MCLK_APBBMASK_RAMECC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBBMASK_RAMECC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= ~MCLK_APBBMASK_RAMECC; + tmp |= value << MCLK_APBBMASK_RAMECC_Pos; + ((Mclk *)hw)->APBBMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_RAMECC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~MCLK_APBBMASK_RAMECC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_RAMECC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= MCLK_APBBMASK_RAMECC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbbmask_reg_t hri_mclk_get_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBBMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBBMASK_reg(const void *const hw, hri_mclk_apbbmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBBMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbbmask_reg_t hri_mclk_read_APBBMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBBMASK.reg; +} + +static inline void hri_mclk_set_APBCMASK_GMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_GMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_GMAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_GMAC) >> MCLK_APBCMASK_GMAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_GMAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_GMAC; + tmp |= value << MCLK_APBCMASK_GMAC_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_GMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_GMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_GMAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_GMAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TCC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TCC2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TCC2) >> MCLK_APBCMASK_TCC2_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TCC2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TCC2; + tmp |= value << MCLK_APBCMASK_TCC2_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TCC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TCC2_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC2; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TCC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TCC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TCC3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TCC3) >> MCLK_APBCMASK_TCC3_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TCC3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TCC3; + tmp |= value << MCLK_APBCMASK_TCC3_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TCC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TCC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TCC3_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TCC3; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TC4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TC4) >> MCLK_APBCMASK_TC4_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TC4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TC4; + tmp |= value << MCLK_APBCMASK_TC4_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TC5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TC5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TC5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TC5) >> MCLK_APBCMASK_TC5_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TC5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TC5; + tmp |= value << MCLK_APBCMASK_TC5_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TC5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TC5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TC5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TC5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_PDEC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_PDEC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_PDEC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_PDEC) >> MCLK_APBCMASK_PDEC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_PDEC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_PDEC; + tmp |= value << MCLK_APBCMASK_PDEC_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_PDEC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_PDEC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_PDEC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_PDEC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_AC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_AC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_AC) >> MCLK_APBCMASK_AC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_AC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_AC; + tmp |= value << MCLK_APBCMASK_AC_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_AC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_AC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_AES_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_AES; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_AES_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_AES) >> MCLK_APBCMASK_AES_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_AES_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_AES; + tmp |= value << MCLK_APBCMASK_AES_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_AES_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_AES; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_AES_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_AES; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_TRNG_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_TRNG; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_TRNG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_TRNG) >> MCLK_APBCMASK_TRNG_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_TRNG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_TRNG; + tmp |= value << MCLK_APBCMASK_TRNG_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_TRNG_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_TRNG; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_TRNG_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_TRNG; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_ICM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_ICM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_ICM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_ICM) >> MCLK_APBCMASK_ICM_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_ICM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_ICM; + tmp |= value << MCLK_APBCMASK_ICM_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_ICM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_ICM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_ICM_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_ICM; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_QSPI_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_QSPI; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_QSPI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_QSPI) >> MCLK_APBCMASK_QSPI_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_QSPI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_QSPI; + tmp |= value << MCLK_APBCMASK_QSPI_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_QSPI_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_QSPI; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_QSPI_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_QSPI; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_CCL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= MCLK_APBCMASK_CCL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBCMASK_CCL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp = (tmp & MCLK_APBCMASK_CCL) >> MCLK_APBCMASK_CCL_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBCMASK_CCL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= ~MCLK_APBCMASK_CCL; + tmp |= value << MCLK_APBCMASK_CCL_Pos; + ((Mclk *)hw)->APBCMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_CCL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~MCLK_APBCMASK_CCL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_CCL_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= MCLK_APBCMASK_CCL; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbcmask_reg_t hri_mclk_get_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBCMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBCMASK_reg(const void *const hw, hri_mclk_apbcmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBCMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbcmask_reg_t hri_mclk_read_APBCMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBCMASK.reg; +} + +static inline void hri_mclk_set_APBDMASK_SERCOM4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_SERCOM4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_SERCOM4) >> MCLK_APBDMASK_SERCOM4_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_SERCOM4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_SERCOM4; + tmp |= value << MCLK_APBDMASK_SERCOM4_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_SERCOM4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_SERCOM4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_SERCOM5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_SERCOM5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_SERCOM5) >> MCLK_APBDMASK_SERCOM5_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_SERCOM5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_SERCOM5; + tmp |= value << MCLK_APBDMASK_SERCOM5_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_SERCOM5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_SERCOM5_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM5; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_SERCOM6_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM6; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_SERCOM6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_SERCOM6) >> MCLK_APBDMASK_SERCOM6_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_SERCOM6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_SERCOM6; + tmp |= value << MCLK_APBDMASK_SERCOM6_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_SERCOM6_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM6; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_SERCOM6_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM6; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_SERCOM7_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_SERCOM7; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_SERCOM7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_SERCOM7) >> MCLK_APBDMASK_SERCOM7_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_SERCOM7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_SERCOM7; + tmp |= value << MCLK_APBDMASK_SERCOM7_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_SERCOM7_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_SERCOM7; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_SERCOM7_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_SERCOM7; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_TCC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TCC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_TCC4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_TCC4) >> MCLK_APBDMASK_TCC4_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_TCC4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_TCC4; + tmp |= value << MCLK_APBDMASK_TCC4_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_TCC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TCC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_TCC4_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TCC4; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_TC6_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TC6; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_TC6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_TC6) >> MCLK_APBDMASK_TC6_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_TC6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_TC6; + tmp |= value << MCLK_APBDMASK_TC6_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_TC6_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TC6; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_TC6_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TC6; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_TC7_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_TC7; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_TC7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_TC7) >> MCLK_APBDMASK_TC7_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_TC7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_TC7; + tmp |= value << MCLK_APBDMASK_TC7_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_TC7_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_TC7; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_TC7_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_TC7; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_ADC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_ADC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_ADC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_ADC0) >> MCLK_APBDMASK_ADC0_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_ADC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_ADC0; + tmp |= value << MCLK_APBDMASK_ADC0_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_ADC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_ADC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_ADC0_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_ADC0; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_ADC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_ADC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_ADC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_ADC1) >> MCLK_APBDMASK_ADC1_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_ADC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_ADC1; + tmp |= value << MCLK_APBDMASK_ADC1_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_ADC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_ADC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_ADC1_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_ADC1; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_DAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_DAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_DAC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_DAC) >> MCLK_APBDMASK_DAC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_DAC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_DAC; + tmp |= value << MCLK_APBDMASK_DAC_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_DAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_DAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_DAC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_DAC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_I2S_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_I2S; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_I2S_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_I2S) >> MCLK_APBDMASK_I2S_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_I2S_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_I2S; + tmp |= value << MCLK_APBDMASK_I2S_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_I2S_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_I2S; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_I2S_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_I2S; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_PCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= MCLK_APBDMASK_PCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_mclk_get_APBDMASK_PCC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp = (tmp & MCLK_APBDMASK_PCC) >> MCLK_APBDMASK_PCC_Pos; + return (bool)tmp; +} + +static inline void hri_mclk_write_APBDMASK_PCC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + MCLK_CRITICAL_SECTION_ENTER(); + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= ~MCLK_APBDMASK_PCC; + tmp |= value << MCLK_APBDMASK_PCC_Pos; + ((Mclk *)hw)->APBDMASK.reg = tmp; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_PCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~MCLK_APBDMASK_PCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_PCC_bit(const void *const hw) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= MCLK_APBDMASK_PCC; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_set_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg |= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbdmask_reg_t hri_mclk_get_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) +{ + uint32_t tmp; + tmp = ((Mclk *)hw)->APBDMASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_mclk_write_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t data) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg = data; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_clear_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg &= ~mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_mclk_toggle_APBDMASK_reg(const void *const hw, hri_mclk_apbdmask_reg_t mask) +{ + MCLK_CRITICAL_SECTION_ENTER(); + ((Mclk *)hw)->APBDMASK.reg ^= mask; + MCLK_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_mclk_apbdmask_reg_t hri_mclk_read_APBDMASK_reg(const void *const hw) +{ + return ((Mclk *)hw)->APBDMASK.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_MCLK_E54_H_INCLUDED */ +#endif /* _SAME54_MCLK_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_nvmctrl_e54.h b/software/firmware/oracle_same54n19a/hri/hri_nvmctrl_e54.h new file mode 100644 index 00000000..12d40223 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_nvmctrl_e54.h @@ -0,0 +1,1618 @@ +/** + * \file + * + * \brief SAM NVMCTRL + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_NVMCTRL_COMPONENT_ +#ifndef _HRI_NVMCTRL_E54_H_INCLUDED_ +#define _HRI_NVMCTRL_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_NVMCTRL_CRITICAL_SECTIONS) +#define NVMCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define NVMCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define NVMCTRL_CRITICAL_SECTION_ENTER() +#define NVMCTRL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_nvmctrl_ctrla_reg_t; +typedef uint16_t hri_nvmctrl_ctrlb_reg_t; +typedef uint16_t hri_nvmctrl_intenset_reg_t; +typedef uint16_t hri_nvmctrl_intflag_reg_t; +typedef uint16_t hri_nvmctrl_status_reg_t; +typedef uint32_t hri_nvmctrl_addr_reg_t; +typedef uint32_t hri_nvmctrl_eccerr_reg_t; +typedef uint32_t hri_nvmctrl_param_reg_t; +typedef uint32_t hri_nvmctrl_pbldata_reg_t; +typedef uint32_t hri_nvmctrl_runlock_reg_t; +typedef uint32_t hri_nvmctrl_seestat_reg_t; +typedef uint8_t hri_nvmctrl_dbgctrl_reg_t; +typedef uint8_t hri_nvmctrl_seecfg_reg_t; + +static inline bool hri_nvmctrl_get_INTFLAG_DONE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_DONE) >> NVMCTRL_INTFLAG_DONE_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_DONE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_DONE; +} + +static inline bool hri_nvmctrl_get_INTFLAG_ADDRE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ADDRE) >> NVMCTRL_INTFLAG_ADDRE_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_ADDRE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ADDRE; +} + +static inline bool hri_nvmctrl_get_INTFLAG_PROGE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_PROGE) >> NVMCTRL_INTFLAG_PROGE_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_PROGE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_PROGE; +} + +static inline bool hri_nvmctrl_get_INTFLAG_LOCKE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_LOCKE) >> NVMCTRL_INTFLAG_LOCKE_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_LOCKE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_LOCKE; +} + +static inline bool hri_nvmctrl_get_INTFLAG_ECCSE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCSE) >> NVMCTRL_INTFLAG_ECCSE_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_ECCSE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCSE; +} + +static inline bool hri_nvmctrl_get_INTFLAG_ECCDE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCDE) >> NVMCTRL_INTFLAG_ECCDE_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_ECCDE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCDE; +} + +static inline bool hri_nvmctrl_get_INTFLAG_NVME_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_NVME) >> NVMCTRL_INTFLAG_NVME_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_NVME_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_NVME; +} + +static inline bool hri_nvmctrl_get_INTFLAG_SUSP_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SUSP) >> NVMCTRL_INTFLAG_SUSP_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_SUSP_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SUSP; +} + +static inline bool hri_nvmctrl_get_INTFLAG_SEESFULL_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESFULL) >> NVMCTRL_INTFLAG_SEESFULL_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_SEESFULL_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESFULL; +} + +static inline bool hri_nvmctrl_get_INTFLAG_SEESOVF_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESOVF) >> NVMCTRL_INTFLAG_SEESOVF_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_SEESOVF_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESOVF; +} + +static inline bool hri_nvmctrl_get_INTFLAG_SEEWRC_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEEWRC) >> NVMCTRL_INTFLAG_SEEWRC_Pos; +} + +static inline void hri_nvmctrl_clear_INTFLAG_SEEWRC_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEEWRC; +} + +static inline bool hri_nvmctrl_get_interrupt_DONE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_DONE) >> NVMCTRL_INTFLAG_DONE_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_DONE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_DONE; +} + +static inline bool hri_nvmctrl_get_interrupt_ADDRE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ADDRE) >> NVMCTRL_INTFLAG_ADDRE_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_ADDRE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ADDRE; +} + +static inline bool hri_nvmctrl_get_interrupt_PROGE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_PROGE) >> NVMCTRL_INTFLAG_PROGE_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_PROGE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_PROGE; +} + +static inline bool hri_nvmctrl_get_interrupt_LOCKE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_LOCKE) >> NVMCTRL_INTFLAG_LOCKE_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_LOCKE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_LOCKE; +} + +static inline bool hri_nvmctrl_get_interrupt_ECCSE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCSE) >> NVMCTRL_INTFLAG_ECCSE_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_ECCSE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCSE; +} + +static inline bool hri_nvmctrl_get_interrupt_ECCDE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_ECCDE) >> NVMCTRL_INTFLAG_ECCDE_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_ECCDE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_ECCDE; +} + +static inline bool hri_nvmctrl_get_interrupt_NVME_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_NVME) >> NVMCTRL_INTFLAG_NVME_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_NVME_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_NVME; +} + +static inline bool hri_nvmctrl_get_interrupt_SUSP_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SUSP) >> NVMCTRL_INTFLAG_SUSP_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_SUSP_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SUSP; +} + +static inline bool hri_nvmctrl_get_interrupt_SEESFULL_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESFULL) >> NVMCTRL_INTFLAG_SEESFULL_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_SEESFULL_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESFULL; +} + +static inline bool hri_nvmctrl_get_interrupt_SEESOVF_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEESOVF) >> NVMCTRL_INTFLAG_SEESOVF_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_SEESOVF_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEESOVF; +} + +static inline bool hri_nvmctrl_get_interrupt_SEEWRC_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTFLAG.reg & NVMCTRL_INTFLAG_SEEWRC) >> NVMCTRL_INTFLAG_SEEWRC_Pos; +} + +static inline void hri_nvmctrl_clear_interrupt_SEEWRC_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = NVMCTRL_INTFLAG_SEEWRC; +} + +static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_get_INTFLAG_reg(const void *const hw, + hri_nvmctrl_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_intflag_reg_t hri_nvmctrl_read_INTFLAG_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->INTFLAG.reg; +} + +static inline void hri_nvmctrl_clear_INTFLAG_reg(const void *const hw, hri_nvmctrl_intflag_reg_t mask) +{ + ((Nvmctrl *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_nvmctrl_set_INTEN_DONE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_DONE; +} + +static inline bool hri_nvmctrl_get_INTEN_DONE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_DONE) >> NVMCTRL_INTENSET_DONE_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_DONE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_DONE; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_DONE; + } +} + +static inline void hri_nvmctrl_clear_INTEN_DONE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_DONE; +} + +static inline void hri_nvmctrl_set_INTEN_ADDRE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ADDRE; +} + +static inline bool hri_nvmctrl_get_INTEN_ADDRE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ADDRE) >> NVMCTRL_INTENSET_ADDRE_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_ADDRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ADDRE; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ADDRE; + } +} + +static inline void hri_nvmctrl_clear_INTEN_ADDRE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ADDRE; +} + +static inline void hri_nvmctrl_set_INTEN_PROGE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_PROGE; +} + +static inline bool hri_nvmctrl_get_INTEN_PROGE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_PROGE) >> NVMCTRL_INTENSET_PROGE_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_PROGE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_PROGE; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_PROGE; + } +} + +static inline void hri_nvmctrl_clear_INTEN_PROGE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_PROGE; +} + +static inline void hri_nvmctrl_set_INTEN_LOCKE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_LOCKE; +} + +static inline bool hri_nvmctrl_get_INTEN_LOCKE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_LOCKE) >> NVMCTRL_INTENSET_LOCKE_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_LOCKE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_LOCKE; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_LOCKE; + } +} + +static inline void hri_nvmctrl_clear_INTEN_LOCKE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_LOCKE; +} + +static inline void hri_nvmctrl_set_INTEN_ECCSE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCSE; +} + +static inline bool hri_nvmctrl_get_INTEN_ECCSE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ECCSE) >> NVMCTRL_INTENSET_ECCSE_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_ECCSE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCSE; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCSE; + } +} + +static inline void hri_nvmctrl_clear_INTEN_ECCSE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCSE; +} + +static inline void hri_nvmctrl_set_INTEN_ECCDE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCDE; +} + +static inline bool hri_nvmctrl_get_INTEN_ECCDE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_ECCDE) >> NVMCTRL_INTENSET_ECCDE_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_ECCDE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCDE; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_ECCDE; + } +} + +static inline void hri_nvmctrl_clear_INTEN_ECCDE_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_ECCDE; +} + +static inline void hri_nvmctrl_set_INTEN_NVME_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_NVME; +} + +static inline bool hri_nvmctrl_get_INTEN_NVME_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_NVME) >> NVMCTRL_INTENSET_NVME_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_NVME_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_NVME; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_NVME; + } +} + +static inline void hri_nvmctrl_clear_INTEN_NVME_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_NVME; +} + +static inline void hri_nvmctrl_set_INTEN_SUSP_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SUSP; +} + +static inline bool hri_nvmctrl_get_INTEN_SUSP_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SUSP) >> NVMCTRL_INTENSET_SUSP_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_SUSP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SUSP; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SUSP; + } +} + +static inline void hri_nvmctrl_clear_INTEN_SUSP_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SUSP; +} + +static inline void hri_nvmctrl_set_INTEN_SEESFULL_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESFULL; +} + +static inline bool hri_nvmctrl_get_INTEN_SEESFULL_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SEESFULL) >> NVMCTRL_INTENSET_SEESFULL_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_SEESFULL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESFULL; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESFULL; + } +} + +static inline void hri_nvmctrl_clear_INTEN_SEESFULL_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESFULL; +} + +static inline void hri_nvmctrl_set_INTEN_SEESOVF_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESOVF; +} + +static inline bool hri_nvmctrl_get_INTEN_SEESOVF_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SEESOVF) >> NVMCTRL_INTENSET_SEESOVF_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_SEESOVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESOVF; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEESOVF; + } +} + +static inline void hri_nvmctrl_clear_INTEN_SEESOVF_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEESOVF; +} + +static inline void hri_nvmctrl_set_INTEN_SEEWRC_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEEWRC; +} + +static inline bool hri_nvmctrl_get_INTEN_SEEWRC_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->INTENSET.reg & NVMCTRL_INTENSET_SEEWRC) >> NVMCTRL_INTENSET_SEEWRC_Pos; +} + +static inline void hri_nvmctrl_write_INTEN_SEEWRC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEEWRC; + } else { + ((Nvmctrl *)hw)->INTENSET.reg = NVMCTRL_INTENSET_SEEWRC; + } +} + +static inline void hri_nvmctrl_clear_INTEN_SEEWRC_bit(const void *const hw) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = NVMCTRL_INTENSET_SEEWRC; +} + +static inline void hri_nvmctrl_set_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask) +{ + ((Nvmctrl *)hw)->INTENSET.reg = mask; +} + +static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_get_INTEN_reg(const void *const hw, + hri_nvmctrl_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_intenset_reg_t hri_nvmctrl_read_INTEN_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->INTENSET.reg; +} + +static inline void hri_nvmctrl_write_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t data) +{ + ((Nvmctrl *)hw)->INTENSET.reg = data; + ((Nvmctrl *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_nvmctrl_clear_INTEN_reg(const void *const hw, hri_nvmctrl_intenset_reg_t mask) +{ + ((Nvmctrl *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_nvmctrl_get_PARAM_SEE_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_SEE) >> NVMCTRL_PARAM_SEE_Pos; +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_NVMP_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_NVMP(mask)) >> NVMCTRL_PARAM_NVMP_Pos; +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_NVMP_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_NVMP_Msk) >> NVMCTRL_PARAM_NVMP_Pos; +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_PSZ_bf(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_PSZ(mask)) >> NVMCTRL_PARAM_PSZ_Pos; +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_PSZ_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->PARAM.reg & NVMCTRL_PARAM_PSZ_Msk) >> NVMCTRL_PARAM_PSZ_Pos; +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_get_PARAM_reg(const void *const hw, hri_nvmctrl_param_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PARAM.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_param_reg_t hri_nvmctrl_read_PARAM_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->PARAM.reg; +} + +static inline bool hri_nvmctrl_get_STATUS_READY_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_READY) >> NVMCTRL_STATUS_READY_Pos; +} + +static inline bool hri_nvmctrl_get_STATUS_PRM_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_PRM) >> NVMCTRL_STATUS_PRM_Pos; +} + +static inline bool hri_nvmctrl_get_STATUS_LOAD_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_LOAD) >> NVMCTRL_STATUS_LOAD_Pos; +} + +static inline bool hri_nvmctrl_get_STATUS_SUSP_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_SUSP) >> NVMCTRL_STATUS_SUSP_Pos; +} + +static inline bool hri_nvmctrl_get_STATUS_AFIRST_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_AFIRST) >> NVMCTRL_STATUS_AFIRST_Pos; +} + +static inline bool hri_nvmctrl_get_STATUS_BPDIS_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_BPDIS) >> NVMCTRL_STATUS_BPDIS_Pos; +} + +static inline hri_nvmctrl_status_reg_t hri_nvmctrl_get_STATUS_BOOTPROT_bf(const void *const hw, + hri_nvmctrl_status_reg_t mask) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_BOOTPROT(mask)) >> NVMCTRL_STATUS_BOOTPROT_Pos; +} + +static inline hri_nvmctrl_status_reg_t hri_nvmctrl_read_STATUS_BOOTPROT_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->STATUS.reg & NVMCTRL_STATUS_BOOTPROT_Msk) >> NVMCTRL_STATUS_BOOTPROT_Pos; +} + +static inline hri_nvmctrl_status_reg_t hri_nvmctrl_get_STATUS_reg(const void *const hw, hri_nvmctrl_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_status_reg_t hri_nvmctrl_read_STATUS_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->STATUS.reg; +} + +static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_get_RUNLOCK_RUNLOCK_bf(const void *const hw, + hri_nvmctrl_runlock_reg_t mask) +{ + return (((Nvmctrl *)hw)->RUNLOCK.reg & NVMCTRL_RUNLOCK_RUNLOCK(mask)) >> NVMCTRL_RUNLOCK_RUNLOCK_Pos; +} + +static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_read_RUNLOCK_RUNLOCK_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->RUNLOCK.reg & NVMCTRL_RUNLOCK_RUNLOCK_Msk) >> NVMCTRL_RUNLOCK_RUNLOCK_Pos; +} + +static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_get_RUNLOCK_reg(const void *const hw, + hri_nvmctrl_runlock_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->RUNLOCK.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_runlock_reg_t hri_nvmctrl_read_RUNLOCK_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->RUNLOCK.reg; +} + +static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_get_PBLDATA_DATA_bf(const void *const hw, uint8_t index, + hri_nvmctrl_pbldata_reg_t mask) +{ + return (((Nvmctrl *)hw)->PBLDATA[index].reg & NVMCTRL_PBLDATA_DATA(mask)) >> NVMCTRL_PBLDATA_DATA_Pos; +} + +static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_read_PBLDATA_DATA_bf(const void *const hw, uint8_t index) +{ + return (((Nvmctrl *)hw)->PBLDATA[index].reg & NVMCTRL_PBLDATA_DATA_Msk) >> NVMCTRL_PBLDATA_DATA_Pos; +} + +static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_get_PBLDATA_reg(const void *const hw, uint8_t index, + hri_nvmctrl_pbldata_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->PBLDATA[index].reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_pbldata_reg_t hri_nvmctrl_read_PBLDATA_reg(const void *const hw, uint8_t index) +{ + return ((Nvmctrl *)hw)->PBLDATA[index].reg; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_ADDR_bf(const void *const hw, + hri_nvmctrl_eccerr_reg_t mask) +{ + return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_ADDR(mask)) >> NVMCTRL_ECCERR_ADDR_Pos; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_ADDR_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_ADDR_Msk) >> NVMCTRL_ECCERR_ADDR_Pos; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_TYPEL_bf(const void *const hw, + hri_nvmctrl_eccerr_reg_t mask) +{ + return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEL(mask)) >> NVMCTRL_ECCERR_TYPEL_Pos; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_TYPEL_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEL_Msk) >> NVMCTRL_ECCERR_TYPEL_Pos; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_TYPEH_bf(const void *const hw, + hri_nvmctrl_eccerr_reg_t mask) +{ + return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEH(mask)) >> NVMCTRL_ECCERR_TYPEH_Pos; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_TYPEH_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->ECCERR.reg & NVMCTRL_ECCERR_TYPEH_Msk) >> NVMCTRL_ECCERR_TYPEH_Pos; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_get_ECCERR_reg(const void *const hw, hri_nvmctrl_eccerr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ECCERR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_eccerr_reg_t hri_nvmctrl_read_ECCERR_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->ECCERR.reg; +} + +static inline bool hri_nvmctrl_get_SEESTAT_ASEES_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_ASEES) >> NVMCTRL_SEESTAT_ASEES_Pos; +} + +static inline bool hri_nvmctrl_get_SEESTAT_LOAD_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_LOAD) >> NVMCTRL_SEESTAT_LOAD_Pos; +} + +static inline bool hri_nvmctrl_get_SEESTAT_BUSY_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_BUSY) >> NVMCTRL_SEESTAT_BUSY_Pos; +} + +static inline bool hri_nvmctrl_get_SEESTAT_LOCK_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_LOCK) >> NVMCTRL_SEESTAT_LOCK_Pos; +} + +static inline bool hri_nvmctrl_get_SEESTAT_RLOCK_bit(const void *const hw) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_RLOCK) >> NVMCTRL_SEESTAT_RLOCK_Pos; +} + +static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_get_SEESTAT_SBLK_bf(const void *const hw, + hri_nvmctrl_seestat_reg_t mask) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_SBLK(mask)) >> NVMCTRL_SEESTAT_SBLK_Pos; +} + +static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_read_SEESTAT_SBLK_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_SBLK_Msk) >> NVMCTRL_SEESTAT_SBLK_Pos; +} + +static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_get_SEESTAT_PSZ_bf(const void *const hw, + hri_nvmctrl_seestat_reg_t mask) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_PSZ(mask)) >> NVMCTRL_SEESTAT_PSZ_Pos; +} + +static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_read_SEESTAT_PSZ_bf(const void *const hw) +{ + return (((Nvmctrl *)hw)->SEESTAT.reg & NVMCTRL_SEESTAT_PSZ_Msk) >> NVMCTRL_SEESTAT_PSZ_Pos; +} + +static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_get_SEESTAT_reg(const void *const hw, + hri_nvmctrl_seestat_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->SEESTAT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_nvmctrl_seestat_reg_t hri_nvmctrl_read_SEESTAT_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->SEESTAT.reg; +} + +static inline void hri_nvmctrl_set_CTRLA_AUTOWS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_AUTOWS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLA_AUTOWS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_AUTOWS) >> NVMCTRL_CTRLA_AUTOWS_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_AUTOWS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_AUTOWS; + tmp |= value << NVMCTRL_CTRLA_AUTOWS_Pos; + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_AUTOWS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_AUTOWS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_AUTOWS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_AUTOWS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLA_SUSPEN_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_SUSPEN; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLA_SUSPEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_SUSPEN) >> NVMCTRL_CTRLA_SUSPEN_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_SUSPEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_SUSPEN; + tmp |= value << NVMCTRL_CTRLA_SUSPEN_Pos; + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_SUSPEN_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_SUSPEN; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_SUSPEN_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_SUSPEN; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLA_AHBNS0_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_AHBNS0; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLA_AHBNS0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_AHBNS0) >> NVMCTRL_CTRLA_AHBNS0_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_AHBNS0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_AHBNS0; + tmp |= value << NVMCTRL_CTRLA_AHBNS0_Pos; + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_AHBNS0_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_AHBNS0; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_AHBNS0_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_AHBNS0; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLA_AHBNS1_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_AHBNS1; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLA_AHBNS1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_AHBNS1) >> NVMCTRL_CTRLA_AHBNS1_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_AHBNS1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_AHBNS1; + tmp |= value << NVMCTRL_CTRLA_AHBNS1_Pos; + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_AHBNS1_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_AHBNS1; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_AHBNS1_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_AHBNS1; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLA_CACHEDIS0_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CACHEDIS0; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLA_CACHEDIS0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_CACHEDIS0) >> NVMCTRL_CTRLA_CACHEDIS0_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_CACHEDIS0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_CACHEDIS0; + tmp |= value << NVMCTRL_CTRLA_CACHEDIS0_Pos; + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_CACHEDIS0_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CACHEDIS0; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_CACHEDIS0_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CACHEDIS0; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLA_CACHEDIS1_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_CACHEDIS1; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_CTRLA_CACHEDIS1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_CACHEDIS1) >> NVMCTRL_CTRLA_CACHEDIS1_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_CACHEDIS1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_CACHEDIS1; + tmp |= value << NVMCTRL_CTRLA_CACHEDIS1_Pos; + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_CACHEDIS1_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_CACHEDIS1; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_CACHEDIS1_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_CACHEDIS1; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_WMODE(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_WMODE(mask)) >> NVMCTRL_CTRLA_WMODE_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_WMODE_Msk; + tmp |= NVMCTRL_CTRLA_WMODE(data); + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_WMODE(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_WMODE_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_WMODE(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_WMODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_WMODE_Msk) >> NVMCTRL_CTRLA_WMODE_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_PRM(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_PRM(mask)) >> NVMCTRL_CTRLA_PRM_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_PRM_Msk; + tmp |= NVMCTRL_CTRLA_PRM(data); + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_PRM(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_PRM_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_PRM(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_PRM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_PRM_Msk) >> NVMCTRL_CTRLA_PRM_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= NVMCTRL_CTRLA_RWS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_RWS(mask)) >> NVMCTRL_CTRLA_RWS_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + uint16_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= ~NVMCTRL_CTRLA_RWS_Msk; + tmp |= NVMCTRL_CTRLA_RWS(data); + ((Nvmctrl *)hw)->CTRLA.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~NVMCTRL_CTRLA_RWS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_RWS_bf(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= NVMCTRL_CTRLA_RWS(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_RWS_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp = (tmp & NVMCTRL_CTRLA_RWS_Msk) >> NVMCTRL_CTRLA_RWS_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_get_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Nvmctrl *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_CTRLA_reg(const void *const hw, hri_nvmctrl_ctrla_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLA.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_ctrla_reg_t hri_nvmctrl_read_CTRLA_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->CTRLA.reg; +} + +static inline void hri_nvmctrl_set_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg |= NVMCTRL_ADDR_ADDR(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp = (tmp & NVMCTRL_ADDR_ADDR(mask)) >> NVMCTRL_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_nvmctrl_write_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t data) +{ + uint32_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp &= ~NVMCTRL_ADDR_ADDR_Msk; + tmp |= NVMCTRL_ADDR_ADDR(data); + ((Nvmctrl *)hw)->ADDR.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg &= ~NVMCTRL_ADDR_ADDR(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_ADDR_ADDR_bf(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg ^= NVMCTRL_ADDR_ADDR(mask); + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp = (tmp & NVMCTRL_ADDR_ADDR_Msk) >> NVMCTRL_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_nvmctrl_set_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_get_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Nvmctrl *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_ADDR_reg(const void *const hw, hri_nvmctrl_addr_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->ADDR.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_addr_reg_t hri_nvmctrl_read_ADDR_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->ADDR.reg; +} + +static inline void hri_nvmctrl_set_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg |= NVMCTRL_DBGCTRL_ECCDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; + tmp = (tmp & NVMCTRL_DBGCTRL_ECCDIS) >> NVMCTRL_DBGCTRL_ECCDIS_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_DBGCTRL_ECCDIS_bit(const void *const hw, bool value) +{ + uint8_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; + tmp &= ~NVMCTRL_DBGCTRL_ECCDIS; + tmp |= value << NVMCTRL_DBGCTRL_ECCDIS_Pos; + ((Nvmctrl *)hw)->DBGCTRL.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg &= ~NVMCTRL_DBGCTRL_ECCDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg ^= NVMCTRL_DBGCTRL_ECCDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg |= NVMCTRL_DBGCTRL_ECCELOG; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; + tmp = (tmp & NVMCTRL_DBGCTRL_ECCELOG) >> NVMCTRL_DBGCTRL_ECCELOG_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_DBGCTRL_ECCELOG_bit(const void *const hw, bool value) +{ + uint8_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; + tmp &= ~NVMCTRL_DBGCTRL_ECCELOG; + tmp |= value << NVMCTRL_DBGCTRL_ECCELOG_Pos; + ((Nvmctrl *)hw)->DBGCTRL.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg &= ~NVMCTRL_DBGCTRL_ECCELOG; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg ^= NVMCTRL_DBGCTRL_ECCELOG; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_dbgctrl_reg_t hri_nvmctrl_get_DBGCTRL_reg(const void *const hw, + hri_nvmctrl_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_DBGCTRL_reg(const void *const hw, hri_nvmctrl_dbgctrl_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->DBGCTRL.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_dbgctrl_reg_t hri_nvmctrl_read_DBGCTRL_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->DBGCTRL.reg; +} + +static inline void hri_nvmctrl_set_SEECFG_WMODE_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg |= NVMCTRL_SEECFG_WMODE; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_SEECFG_WMODE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->SEECFG.reg; + tmp = (tmp & NVMCTRL_SEECFG_WMODE) >> NVMCTRL_SEECFG_WMODE_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_SEECFG_WMODE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->SEECFG.reg; + tmp &= ~NVMCTRL_SEECFG_WMODE; + tmp |= value << NVMCTRL_SEECFG_WMODE_Pos; + ((Nvmctrl *)hw)->SEECFG.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_SEECFG_WMODE_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg &= ~NVMCTRL_SEECFG_WMODE; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_SEECFG_WMODE_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg ^= NVMCTRL_SEECFG_WMODE; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_SEECFG_APRDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg |= NVMCTRL_SEECFG_APRDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_nvmctrl_get_SEECFG_APRDIS_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->SEECFG.reg; + tmp = (tmp & NVMCTRL_SEECFG_APRDIS) >> NVMCTRL_SEECFG_APRDIS_Pos; + return (bool)tmp; +} + +static inline void hri_nvmctrl_write_SEECFG_APRDIS_bit(const void *const hw, bool value) +{ + uint8_t tmp; + NVMCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Nvmctrl *)hw)->SEECFG.reg; + tmp &= ~NVMCTRL_SEECFG_APRDIS; + tmp |= value << NVMCTRL_SEECFG_APRDIS_Pos; + ((Nvmctrl *)hw)->SEECFG.reg = tmp; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_SEECFG_APRDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg &= ~NVMCTRL_SEECFG_APRDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_SEECFG_APRDIS_bit(const void *const hw) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg ^= NVMCTRL_SEECFG_APRDIS; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_set_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg |= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_seecfg_reg_t hri_nvmctrl_get_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Nvmctrl *)hw)->SEECFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_nvmctrl_write_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_clear_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg &= ~mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_nvmctrl_toggle_SEECFG_reg(const void *const hw, hri_nvmctrl_seecfg_reg_t mask) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->SEECFG.reg ^= mask; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_nvmctrl_seecfg_reg_t hri_nvmctrl_read_SEECFG_reg(const void *const hw) +{ + return ((Nvmctrl *)hw)->SEECFG.reg; +} + +static inline void hri_nvmctrl_write_CTRLB_reg(const void *const hw, hri_nvmctrl_ctrlb_reg_t data) +{ + NVMCTRL_CRITICAL_SECTION_ENTER(); + ((Nvmctrl *)hw)->CTRLB.reg = data; + NVMCTRL_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_NVMCTRL_E54_H_INCLUDED */ +#endif /* _SAME54_NVMCTRL_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_osc32kctrl_e54.h b/software/firmware/oracle_same54n19a/hri/hri_osc32kctrl_e54.h new file mode 100644 index 00000000..2eabbca0 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_osc32kctrl_e54.h @@ -0,0 +1,1199 @@ +/** + * \file + * + * \brief SAM OSC32KCTRL + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_OSC32KCTRL_COMPONENT_ +#ifndef _HRI_OSC32KCTRL_E54_H_INCLUDED_ +#define _HRI_OSC32KCTRL_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_OSC32KCTRL_CRITICAL_SECTIONS) +#define OSC32KCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define OSC32KCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define OSC32KCTRL_CRITICAL_SECTION_ENTER() +#define OSC32KCTRL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_osc32kctrl_xosc32k_reg_t; +typedef uint32_t hri_osc32kctrl_intenset_reg_t; +typedef uint32_t hri_osc32kctrl_intflag_reg_t; +typedef uint32_t hri_osc32kctrl_osculp32k_reg_t; +typedef uint32_t hri_osc32kctrl_status_reg_t; +typedef uint8_t hri_osc32kctrl_cfdctrl_reg_t; +typedef uint8_t hri_osc32kctrl_evctrl_reg_t; +typedef uint8_t hri_osc32kctrl_rtcctrl_reg_t; + +static inline bool hri_osc32kctrl_get_INTFLAG_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_clear_INTFLAG_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_INTFLAG_XOSC32KFAIL_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KFAIL) >> OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos; +} + +static inline void hri_osc32kctrl_clear_INTFLAG_XOSC32KFAIL_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KFAIL; +} + +static inline bool hri_osc32kctrl_get_interrupt_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KRDY) >> OSC32KCTRL_INTFLAG_XOSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_clear_interrupt_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_interrupt_XOSC32KFAIL_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTFLAG.reg & OSC32KCTRL_INTFLAG_XOSC32KFAIL) >> OSC32KCTRL_INTFLAG_XOSC32KFAIL_Pos; +} + +static inline void hri_osc32kctrl_clear_interrupt_XOSC32KFAIL_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = OSC32KCTRL_INTFLAG_XOSC32KFAIL; +} + +static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_get_INTFLAG_reg(const void *const hw, + hri_osc32kctrl_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_osc32kctrl_intflag_reg_t hri_osc32kctrl_read_INTFLAG_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->INTFLAG.reg; +} + +static inline void hri_osc32kctrl_clear_INTFLAG_reg(const void *const hw, hri_osc32kctrl_intflag_reg_t mask) +{ + ((Osc32kctrl *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_osc32kctrl_set_INTEN_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; +} + +static inline bool hri_osc32kctrl_get_INTEN_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_XOSC32KRDY) >> OSC32KCTRL_INTENSET_XOSC32KRDY_Pos; +} + +static inline void hri_osc32kctrl_write_INTEN_XOSC32KRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; + } else { + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; + } +} + +static inline void hri_osc32kctrl_clear_INTEN_XOSC32KRDY_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KRDY; +} + +static inline void hri_osc32kctrl_set_INTEN_XOSC32KFAIL_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL; +} + +static inline bool hri_osc32kctrl_get_INTEN_XOSC32KFAIL_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->INTENSET.reg & OSC32KCTRL_INTENSET_XOSC32KFAIL) >> OSC32KCTRL_INTENSET_XOSC32KFAIL_Pos; +} + +static inline void hri_osc32kctrl_write_INTEN_XOSC32KFAIL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL; + } else { + ((Osc32kctrl *)hw)->INTENSET.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL; + } +} + +static inline void hri_osc32kctrl_clear_INTEN_XOSC32KFAIL_bit(const void *const hw) +{ + ((Osc32kctrl *)hw)->INTENCLR.reg = OSC32KCTRL_INTENSET_XOSC32KFAIL; +} + +static inline void hri_osc32kctrl_set_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = mask; +} + +static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_get_INTEN_reg(const void *const hw, + hri_osc32kctrl_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_osc32kctrl_intenset_reg_t hri_osc32kctrl_read_INTEN_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->INTENSET.reg; +} + +static inline void hri_osc32kctrl_write_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t data) +{ + ((Osc32kctrl *)hw)->INTENSET.reg = data; + ((Osc32kctrl *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_osc32kctrl_clear_INTEN_reg(const void *const hw, hri_osc32kctrl_intenset_reg_t mask) +{ + ((Osc32kctrl *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_osc32kctrl_get_STATUS_XOSC32KRDY_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KRDY) >> OSC32KCTRL_STATUS_XOSC32KRDY_Pos; +} + +static inline bool hri_osc32kctrl_get_STATUS_XOSC32KFAIL_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KFAIL) >> OSC32KCTRL_STATUS_XOSC32KFAIL_Pos; +} + +static inline bool hri_osc32kctrl_get_STATUS_XOSC32KSW_bit(const void *const hw) +{ + return (((Osc32kctrl *)hw)->STATUS.reg & OSC32KCTRL_STATUS_XOSC32KSW) >> OSC32KCTRL_STATUS_XOSC32KSW_Pos; +} + +static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_get_STATUS_reg(const void *const hw, + hri_osc32kctrl_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_osc32kctrl_status_reg_t hri_osc32kctrl_read_STATUS_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->STATUS.reg; +} + +static inline void hri_osc32kctrl_set_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg |= OSC32KCTRL_RTCCTRL_RTCSEL(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_RTCSEL_bf(const void *const hw, + hri_osc32kctrl_rtcctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL(mask)) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp &= ~OSC32KCTRL_RTCCTRL_RTCSEL_Msk; + tmp |= OSC32KCTRL_RTCCTRL_RTCSEL(data); + ((Osc32kctrl *)hw)->RTCCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg &= ~OSC32KCTRL_RTCCTRL_RTCSEL(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_RTCCTRL_RTCSEL_bf(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg ^= OSC32KCTRL_RTCCTRL_RTCSEL(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_RTCSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp = (tmp & OSC32KCTRL_RTCCTRL_RTCSEL_Msk) >> OSC32KCTRL_RTCCTRL_RTCSEL_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_get_RTCCTRL_reg(const void *const hw, + hri_osc32kctrl_rtcctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->RTCCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_RTCCTRL_reg(const void *const hw, hri_osc32kctrl_rtcctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->RTCCTRL.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_rtcctrl_reg_t hri_osc32kctrl_read_RTCCTRL_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->RTCCTRL.reg; +} + +static inline void hri_osc32kctrl_set_XOSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_ENABLE) >> OSC32KCTRL_XOSC32K_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_ENABLE; + tmp |= value << OSC32KCTRL_XOSC32K_ENABLE_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_ENABLE_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ENABLE; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_XTALEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_XTALEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_XTALEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_XTALEN) >> OSC32KCTRL_XOSC32K_XTALEN_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_XTALEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_XTALEN; + tmp |= value << OSC32KCTRL_XOSC32K_XTALEN_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_XTALEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_XTALEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_XTALEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_XTALEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_EN32K_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_EN32K) >> OSC32KCTRL_XOSC32K_EN32K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_EN32K_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_EN32K; + tmp |= value << OSC32KCTRL_XOSC32K_EN32K_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_EN1K_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_EN1K) >> OSC32KCTRL_XOSC32K_EN1K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_EN1K_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_EN1K; + tmp |= value << OSC32KCTRL_XOSC32K_EN1K_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_RUNSTDBY) >> OSC32KCTRL_XOSC32K_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_RUNSTDBY; + tmp |= value << OSC32KCTRL_XOSC32K_RUNSTDBY_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_RUNSTDBY_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_RUNSTDBY; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_ONDEMAND) >> OSC32KCTRL_XOSC32K_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_ONDEMAND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_ONDEMAND; + tmp |= value << OSC32KCTRL_XOSC32K_ONDEMAND_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_ONDEMAND_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_ONDEMAND; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_WRTLOCK) >> OSC32KCTRL_XOSC32K_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_WRTLOCK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_WRTLOCK; + tmp |= value << OSC32KCTRL_XOSC32K_WRTLOCK_Pos; + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_STARTUP_bf(const void *const hw, + hri_osc32kctrl_xosc32k_reg_t mask) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP(mask)) >> OSC32KCTRL_XOSC32K_STARTUP_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_STARTUP_Msk; + tmp |= OSC32KCTRL_XOSC32K_STARTUP(data); + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_STARTUP_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_STARTUP(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_STARTUP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_STARTUP_Msk) >> OSC32KCTRL_XOSC32K_STARTUP_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= OSC32KCTRL_XOSC32K_CGM(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_CGM_bf(const void *const hw, + hri_osc32kctrl_xosc32k_reg_t mask) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_CGM(mask)) >> OSC32KCTRL_XOSC32K_CGM_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) +{ + uint16_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= ~OSC32KCTRL_XOSC32K_CGM_Msk; + tmp |= OSC32KCTRL_XOSC32K_CGM(data); + ((Osc32kctrl *)hw)->XOSC32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~OSC32KCTRL_XOSC32K_CGM(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_CGM_bf(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= OSC32KCTRL_XOSC32K_CGM(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_CGM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp = (tmp & OSC32KCTRL_XOSC32K_CGM_Msk) >> OSC32KCTRL_XOSC32K_CGM_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_get_XOSC32K_reg(const void *const hw, + hri_osc32kctrl_xosc32k_reg_t mask) +{ + uint16_t tmp; + tmp = ((Osc32kctrl *)hw)->XOSC32K.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_XOSC32K_reg(const void *const hw, hri_osc32kctrl_xosc32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->XOSC32K.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_xosc32k_reg_t hri_osc32kctrl_read_XOSC32K_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->XOSC32K.reg; +} + +static inline void hri_osc32kctrl_set_CFDCTRL_CFDEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_CFDCTRL_CFDEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDEN) >> OSC32KCTRL_CFDCTRL_CFDEN_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_CFDCTRL_CFDEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp &= ~OSC32KCTRL_CFDCTRL_CFDEN; + tmp |= value << OSC32KCTRL_CFDCTRL_CFDEN_Pos; + ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_CFDCTRL_CFDEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDEN_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDEN; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_CFDCTRL_SWBACK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_SWBACK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_CFDCTRL_SWBACK_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp = (tmp & OSC32KCTRL_CFDCTRL_SWBACK) >> OSC32KCTRL_CFDCTRL_SWBACK_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_CFDCTRL_SWBACK_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp &= ~OSC32KCTRL_CFDCTRL_SWBACK; + tmp |= value << OSC32KCTRL_CFDCTRL_SWBACK_Pos; + ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_CFDCTRL_SWBACK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_SWBACK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_CFDCTRL_SWBACK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_SWBACK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_CFDCTRL_CFDPRESC_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg |= OSC32KCTRL_CFDCTRL_CFDPRESC; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_CFDCTRL_CFDPRESC_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp = (tmp & OSC32KCTRL_CFDCTRL_CFDPRESC) >> OSC32KCTRL_CFDCTRL_CFDPRESC_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_CFDCTRL_CFDPRESC_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp &= ~OSC32KCTRL_CFDCTRL_CFDPRESC; + tmp |= value << OSC32KCTRL_CFDCTRL_CFDPRESC_Pos; + ((Osc32kctrl *)hw)->CFDCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_CFDCTRL_CFDPRESC_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~OSC32KCTRL_CFDCTRL_CFDPRESC; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_CFDCTRL_CFDPRESC_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg ^= OSC32KCTRL_CFDCTRL_CFDPRESC; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_get_CFDCTRL_reg(const void *const hw, + hri_osc32kctrl_cfdctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->CFDCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_CFDCTRL_reg(const void *const hw, hri_osc32kctrl_cfdctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->CFDCTRL.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_cfdctrl_reg_t hri_osc32kctrl_read_CFDCTRL_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->CFDCTRL.reg; +} + +static inline void hri_osc32kctrl_set_EVCTRL_CFDEO_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg |= OSC32KCTRL_EVCTRL_CFDEO; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_EVCTRL_CFDEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; + tmp = (tmp & OSC32KCTRL_EVCTRL_CFDEO) >> OSC32KCTRL_EVCTRL_CFDEO_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_EVCTRL_CFDEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; + tmp &= ~OSC32KCTRL_EVCTRL_CFDEO; + tmp |= value << OSC32KCTRL_EVCTRL_CFDEO_Pos; + ((Osc32kctrl *)hw)->EVCTRL.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_EVCTRL_CFDEO_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg &= ~OSC32KCTRL_EVCTRL_CFDEO; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_EVCTRL_CFDEO_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg ^= OSC32KCTRL_EVCTRL_CFDEO; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_get_EVCTRL_reg(const void *const hw, + hri_osc32kctrl_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Osc32kctrl *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_EVCTRL_reg(const void *const hw, hri_osc32kctrl_evctrl_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->EVCTRL.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_evctrl_reg_t hri_osc32kctrl_read_EVCTRL_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->EVCTRL.reg; +} + +static inline void hri_osc32kctrl_set_OSCULP32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSCULP32K_EN32K_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_EN32K) >> OSC32KCTRL_OSCULP32K_EN32K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_EN32K_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= ~OSC32KCTRL_OSCULP32K_EN32K; + tmp |= value << OSC32KCTRL_OSCULP32K_EN32K_Pos; + ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_EN32K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_EN32K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSCULP32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSCULP32K_EN1K_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_EN1K) >> OSC32KCTRL_OSCULP32K_EN1K_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_EN1K_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= ~OSC32KCTRL_OSCULP32K_EN1K; + tmp |= value << OSC32KCTRL_OSCULP32K_EN1K_Pos; + ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_EN1K_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_EN1K; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_osc32kctrl_get_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_WRTLOCK) >> OSC32KCTRL_OSCULP32K_WRTLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_WRTLOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= ~OSC32KCTRL_OSCULP32K_WRTLOCK; + tmp |= value << OSC32KCTRL_OSCULP32K_WRTLOCK_Pos; + ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_WRTLOCK_bit(const void *const hw) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_WRTLOCK; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_set_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= OSC32KCTRL_OSCULP32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_CALIB_bf(const void *const hw, + hri_osc32kctrl_osculp32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB(mask)) >> OSC32KCTRL_OSCULP32K_CALIB_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data) +{ + uint32_t tmp; + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= ~OSC32KCTRL_OSCULP32K_CALIB_Msk; + tmp |= OSC32KCTRL_OSCULP32K_CALIB(data); + ((Osc32kctrl *)hw)->OSCULP32K.reg = tmp; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~OSC32KCTRL_OSCULP32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_CALIB_bf(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= OSC32KCTRL_OSCULP32K_CALIB(mask); + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_CALIB_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp = (tmp & OSC32KCTRL_OSCULP32K_CALIB_Msk) >> OSC32KCTRL_OSCULP32K_CALIB_Pos; + return tmp; +} + +static inline void hri_osc32kctrl_set_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg |= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_get_OSCULP32K_reg(const void *const hw, + hri_osc32kctrl_osculp32k_reg_t mask) +{ + uint32_t tmp; + tmp = ((Osc32kctrl *)hw)->OSCULP32K.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_osc32kctrl_write_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t data) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg = data; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_clear_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg &= ~mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_osc32kctrl_toggle_OSCULP32K_reg(const void *const hw, hri_osc32kctrl_osculp32k_reg_t mask) +{ + OSC32KCTRL_CRITICAL_SECTION_ENTER(); + ((Osc32kctrl *)hw)->OSCULP32K.reg ^= mask; + OSC32KCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_osc32kctrl_osculp32k_reg_t hri_osc32kctrl_read_OSCULP32K_reg(const void *const hw) +{ + return ((Osc32kctrl *)hw)->OSCULP32K.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_OSC32KCTRL_E54_H_INCLUDED */ +#endif /* _SAME54_OSC32KCTRL_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_oscctrl_e54.h b/software/firmware/oracle_same54n19a/hri/hri_oscctrl_e54.h new file mode 100644 index 00000000..f3314109 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_oscctrl_e54.h @@ -0,0 +1,4441 @@ +/** + * \file + * + * \brief SAM OSCCTRL + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_OSCCTRL_COMPONENT_ +#ifndef _HRI_OSCCTRL_E54_H_INCLUDED_ +#define _HRI_OSCCTRL_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_OSCCTRL_CRITICAL_SECTIONS) +#define OSCCTRL_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define OSCCTRL_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define OSCCTRL_CRITICAL_SECTION_ENTER() +#define OSCCTRL_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_oscctrl_dfllmul_reg_t; +typedef uint32_t hri_oscctrl_dfllval_reg_t; +typedef uint32_t hri_oscctrl_dpllctrlb_reg_t; +typedef uint32_t hri_oscctrl_dpllratio_reg_t; +typedef uint32_t hri_oscctrl_dpllstatus_reg_t; +typedef uint32_t hri_oscctrl_dpllsyncbusy_reg_t; +typedef uint32_t hri_oscctrl_intenset_reg_t; +typedef uint32_t hri_oscctrl_intflag_reg_t; +typedef uint32_t hri_oscctrl_status_reg_t; +typedef uint32_t hri_oscctrl_xoscctrl_reg_t; +typedef uint32_t hri_oscctrldpll_dpllctrlb_reg_t; +typedef uint32_t hri_oscctrldpll_dpllratio_reg_t; +typedef uint32_t hri_oscctrldpll_dpllstatus_reg_t; +typedef uint32_t hri_oscctrldpll_dpllsyncbusy_reg_t; +typedef uint8_t hri_oscctrl_dfllctrla_reg_t; +typedef uint8_t hri_oscctrl_dfllctrlb_reg_t; +typedef uint8_t hri_oscctrl_dfllsync_reg_t; +typedef uint8_t hri_oscctrl_dpllctrla_reg_t; +typedef uint8_t hri_oscctrl_evctrl_reg_t; +typedef uint8_t hri_oscctrldpll_dpllctrla_reg_t; + +static inline void hri_oscctrldpll_wait_for_sync(const void *const hw, hri_oscctrl_dpllsyncbusy_reg_t reg) +{ + while (((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_oscctrldpll_is_syncing(const void *const hw, hri_oscctrl_dpllsyncbusy_reg_t reg) +{ + return ((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & reg; +} + +static inline void hri_oscctrl_wait_for_sync(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllsyncbusy_reg_t reg) +{ + while (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_oscctrl_is_syncing(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllsyncbusy_reg_t reg) +{ + return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & reg; +} + +static inline bool hri_oscctrldpll_get_DPLLSYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_ENABLE) >> OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_oscctrldpll_get_DPLLSYNCBUSY_DPLLRATIO_bit(const void *const hw) +{ + return (((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO) + >> OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos; +} + +static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrldpll_get_DPLLSYNCBUSY_reg(const void *const hw, + hri_oscctrl_dpllsyncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrldpll_read_DPLLSYNCBUSY_reg(const void *const hw) +{ + return ((OscctrlDpll *)hw)->DPLLSYNCBUSY.reg; +} + +static inline bool hri_oscctrldpll_get_DPLLSTATUS_LOCK_bit(const void *const hw) +{ + return (((OscctrlDpll *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK) >> OSCCTRL_DPLLSTATUS_LOCK_Pos; +} + +static inline bool hri_oscctrldpll_get_DPLLSTATUS_CLKRDY_bit(const void *const hw) +{ + return (((OscctrlDpll *)hw)->DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY) >> OSCCTRL_DPLLSTATUS_CLKRDY_Pos; +} + +static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrldpll_get_DPLLSTATUS_reg(const void *const hw, + hri_oscctrl_dpllstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrldpll_read_DPLLSTATUS_reg(const void *const hw) +{ + return ((OscctrlDpll *)hw)->DPLLSTATUS.reg; +} + +static inline void hri_oscctrldpll_set_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrldpll_get_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_ENABLE) >> OSCCTRL_DPLLCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_ENABLE; + tmp |= value << OSCCTRL_DPLLCTRLA_ENABLE_Pos; + ((OscctrlDpll *)hw)->DPLLCTRLA.reg = tmp; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_set_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrldpll_get_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_RUNSTDBY) >> OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; + tmp |= value << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; + ((OscctrlDpll *)hw)->DPLLCTRLA.reg = tmp; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_set_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrldpll_get_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_ONDEMAND) >> OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; + tmp |= value << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; + ((OscctrlDpll *)hw)->DPLLCTRLA.reg = tmp; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_set_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg |= mask; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrldpll_get_DPLLCTRLA_reg(const void *const hw, + hri_oscctrl_dpllctrla_reg_t mask) +{ + uint8_t tmp; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg = data; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg &= ~mask; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLA_reg(const void *const hw, hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLA.reg ^= mask; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrldpll_read_DPLLCTRLA_reg(const void *const hw) +{ + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_ENABLE); + return ((OscctrlDpll *)hw)->DPLLCTRLA.reg; +} + +static inline void hri_oscctrldpll_set_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_get_DPLLRATIO_LDR_bf(const void *const hw, + hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDR(mask)) >> OSCCTRL_DPLLRATIO_LDR_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; + tmp &= ~OSCCTRL_DPLLRATIO_LDR_Msk; + tmp |= OSCCTRL_DPLLRATIO_LDR(data); + ((OscctrlDpll *)hw)->DPLLRATIO.reg = tmp; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLRATIO_LDR_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_read_DPLLRATIO_LDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDR_Msk) >> OSCCTRL_DPLLRATIO_LDR_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_set_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_get_DPLLRATIO_LDRFRAC_bf(const void *const hw, + hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC(mask)) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; + tmp &= ~OSCCTRL_DPLLRATIO_LDRFRAC_Msk; + tmp |= OSCCTRL_DPLLRATIO_LDRFRAC(data); + ((OscctrlDpll *)hw)->DPLLRATIO.reg = tmp; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLRATIO_LDRFRAC_bf(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_read_DPLLRATIO_LDRFRAC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC_Msk) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_set_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg |= mask; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_get_DPLLRATIO_reg(const void *const hw, + hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + tmp = ((OscctrlDpll *)hw)->DPLLRATIO.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg = data; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg &= ~mask; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLRATIO_reg(const void *const hw, hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLRATIO.reg ^= mask; + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrldpll_read_DPLLRATIO_reg(const void *const hw) +{ + hri_oscctrldpll_wait_for_sync(hw, OSCCTRL_DPLLSYNCBUSY_MASK); + return ((OscctrlDpll *)hw)->DPLLRATIO.reg; +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_WUF_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrldpll_get_DPLLCTRLB_WUF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_WUF) >> OSCCTRL_DPLLCTRLB_WUF_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_WUF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_WUF; + tmp |= value << OSCCTRL_DPLLCTRLB_WUF_Pos; + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_WUF_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_WUF_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrldpll_get_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LBYPASS) >> OSCCTRL_DPLLCTRLB_LBYPASS_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_LBYPASS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_LBYPASS; + tmp |= value << OSCCTRL_DPLLCTRLB_LBYPASS_Pos; + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_LBYPASS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_DCOEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrldpll_get_DPLLCTRLB_DCOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOEN) >> OSCCTRL_DPLLCTRLB_DCOEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_DCOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_DCOEN; + tmp |= value << OSCCTRL_DPLLCTRLB_DCOEN_Pos; + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_DCOEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_DCOEN_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_FILTER_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER(mask)) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_FILTER_Msk; + tmp |= OSCCTRL_DPLLCTRLB_FILTER(data); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_FILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_FILTER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER_Msk) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_REFCLK_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK(mask)) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_REFCLK_Msk; + tmp |= OSCCTRL_DPLLCTRLB_REFCLK(data); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_REFCLK_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_REFCLK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK_Msk) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_LTIME_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME(mask)) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_LTIME_Msk; + tmp |= OSCCTRL_DPLLCTRLB_LTIME(data); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_LTIME_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_LTIME_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME_Msk) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOFILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_DCOFILTER_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER(mask)) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_DCOFILTER_Msk; + tmp |= OSCCTRL_DPLLCTRLB_DCOFILTER(data); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOFILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_DCOFILTER_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOFILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_DCOFILTER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER_Msk) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_DIV_bf(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV(mask)) >> OSCCTRL_DPLLCTRLB_DIV_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_DIV_Msk; + tmp |= OSCCTRL_DPLLCTRLB_DIV(data); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_DIV_bf(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_DIV_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV_Msk) >> OSCCTRL_DPLLCTRLB_DIV_Pos; + return tmp; +} + +static inline void hri_oscctrldpll_set_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_get_DPLLCTRLB_reg(const void *const hw, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((OscctrlDpll *)hw)->DPLLCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrldpll_write_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_clear_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrldpll_toggle_DPLLCTRLB_reg(const void *const hw, hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((OscctrlDpll *)hw)->DPLLCTRLB.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrldpll_read_DPLLCTRLB_reg(const void *const hw) +{ + return ((OscctrlDpll *)hw)->DPLLCTRLB.reg; +} + +static inline bool hri_oscctrl_get_DPLLSYNCBUSY_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_ENABLE) + >> OSCCTRL_DPLLSYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_oscctrl_get_DPLLSYNCBUSY_DPLLRATIO_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg & OSCCTRL_DPLLSYNCBUSY_DPLLRATIO) + >> OSCCTRL_DPLLSYNCBUSY_DPLLRATIO_Pos; +} + +static inline hri_oscctrl_dpllsyncbusy_reg_t +hri_oscctrl_get_DPLLSYNCBUSY_reg(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllsyncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_dpllsyncbusy_reg_t hri_oscctrl_read_DPLLSYNCBUSY_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSYNCBUSY.reg; +} + +static inline bool hri_oscctrl_get_DPLLSTATUS_LOCK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_LOCK) + >> OSCCTRL_DPLLSTATUS_LOCK_Pos; +} + +static inline bool hri_oscctrl_get_DPLLSTATUS_CLKRDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg & OSCCTRL_DPLLSTATUS_CLKRDY) + >> OSCCTRL_DPLLSTATUS_CLKRDY_Pos; +} + +static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_get_DPLLSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllstatus_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_dpllstatus_reg_t hri_oscctrl_read_DPLLSTATUS_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLSTATUS.reg; +} + +static inline void hri_oscctrl_set_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_ENABLE) >> OSCCTRL_DPLLCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_ENABLE; + tmp |= value << OSCCTRL_DPLLCTRLA_ENABLE_Pos; + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = tmp; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_ENABLE_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ENABLE; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_RUNSTDBY) >> OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; + tmp |= value << OSCCTRL_DPLLCTRLA_RUNSTDBY_Pos; + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = tmp; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_RUNSTDBY_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_RUNSTDBY; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLA_ONDEMAND) >> OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; + tmp &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; + tmp |= value << OSCCTRL_DPLLCTRLA_ONDEMAND_Pos; + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = tmp; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_ONDEMAND_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= OSCCTRL_DPLLCTRLA_ONDEMAND; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg |= mask; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_get_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrla_reg_t mask) +{ + uint8_t tmp; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrla_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg = data; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg &= ~mask; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg ^= mask; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrla_reg_t hri_oscctrl_read_DPLLCTRLA_reg(const void *const hw, uint8_t submodule_index) +{ + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_ENABLE); + return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLA.reg; +} + +static inline void hri_oscctrl_set_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t +hri_oscctrl_get_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDR(mask)) >> OSCCTRL_DPLLRATIO_LDR_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; + tmp &= ~OSCCTRL_DPLLRATIO_LDR_Msk; + tmp |= OSCCTRL_DPLLRATIO_LDR(data); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = tmp; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLRATIO_LDR_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDR(mask); + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDR_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDR_Msk) >> OSCCTRL_DPLLRATIO_LDR_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg |= OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t +hri_oscctrl_get_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC(mask)) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; + tmp &= ~OSCCTRL_DPLLRATIO_LDRFRAC_Msk; + tmp |= OSCCTRL_DPLLRATIO_LDRFRAC(data); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = tmp; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg &= ~OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLRATIO_LDRFRAC_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg ^= OSCCTRL_DPLLRATIO_LDRFRAC(mask); + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_LDRFRAC_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; + tmp = (tmp & OSCCTRL_DPLLRATIO_LDRFRAC_Msk) >> OSCCTRL_DPLLRATIO_LDRFRAC_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg |= mask; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_get_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + uint32_t tmp; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg = data; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg &= ~mask; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllratio_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg ^= mask; + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllratio_reg_t hri_oscctrl_read_DPLLRATIO_reg(const void *const hw, uint8_t submodule_index) +{ + hri_oscctrl_wait_for_sync(hw, submodule_index, OSCCTRL_DPLLSYNCBUSY_MASK); + return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLRATIO.reg; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_WUF) >> OSCCTRL_DPLLCTRLB_WUF_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_WUF; + tmp |= value << OSCCTRL_DPLLCTRLB_WUF_Pos; + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_WUF_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_WUF; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LBYPASS) >> OSCCTRL_DPLLCTRLB_LBYPASS_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_LBYPASS; + tmp |= value << OSCCTRL_DPLLCTRLB_LBYPASS_Pos; + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_LBYPASS_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LBYPASS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOEN) >> OSCCTRL_DPLLCTRLB_DCOEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_DCOEN; + tmp |= value << OSCCTRL_DPLLCTRLB_DCOEN_Pos; + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_DCOEN_bit(const void *const hw, uint8_t submodule_index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t +hri_oscctrl_get_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER(mask)) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_FILTER_Msk; + tmp |= OSCCTRL_DPLLCTRLB_FILTER(data); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_FILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_FILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_FILTER_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_FILTER_Msk) >> OSCCTRL_DPLLCTRLB_FILTER_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t +hri_oscctrl_get_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK(mask)) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_REFCLK_Msk; + tmp |= OSCCTRL_DPLLCTRLB_REFCLK(data); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_REFCLK_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_REFCLK(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_REFCLK_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_REFCLK_Msk) >> OSCCTRL_DPLLCTRLB_REFCLK_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t +hri_oscctrl_get_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME(mask)) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_LTIME_Msk; + tmp |= OSCCTRL_DPLLCTRLB_LTIME(data); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_LTIME_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_LTIME(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_LTIME_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_LTIME_Msk) >> OSCCTRL_DPLLCTRLB_LTIME_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DCOFILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t +hri_oscctrl_get_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER(mask)) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_DCOFILTER_Msk; + tmp |= OSCCTRL_DPLLCTRLB_DCOFILTER(data); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DCOFILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_DCOFILTER_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DCOFILTER(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_DCOFILTER_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DCOFILTER_Msk) >> OSCCTRL_DPLLCTRLB_DCOFILTER_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t +hri_oscctrl_get_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV(mask)) >> OSCCTRL_DPLLCTRLB_DIV_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= ~OSCCTRL_DPLLCTRLB_DIV_Msk; + tmp |= OSCCTRL_DPLLCTRLB_DIV(data); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_DIV_bf(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= OSCCTRL_DPLLCTRLB_DIV(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_DIV_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DPLLCTRLB_DIV_Msk) >> OSCCTRL_DPLLCTRLB_DIV_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_get_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index, + hri_oscctrl_dpllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dpllctrlb_reg_t hri_oscctrl_read_DPLLCTRLB_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Oscctrl *)hw)->Dpll[submodule_index].DPLLCTRLB.reg; +} + +static inline bool hri_oscctrl_get_INTFLAG_XOSCRDY0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY0) >> OSCCTRL_INTFLAG_XOSCRDY0_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_XOSCRDY0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY0; +} + +static inline bool hri_oscctrl_get_INTFLAG_XOSCRDY1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY1) >> OSCCTRL_INTFLAG_XOSCRDY1_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_XOSCRDY1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY1; +} + +static inline bool hri_oscctrl_get_INTFLAG_XOSCFAIL0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL0) >> OSCCTRL_INTFLAG_XOSCFAIL0_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_XOSCFAIL0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL0; +} + +static inline bool hri_oscctrl_get_INTFLAG_XOSCFAIL1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL1) >> OSCCTRL_INTFLAG_XOSCFAIL1_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_XOSCFAIL1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL1; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRDY) >> OSCCTRL_INTFLAG_DFLLRDY_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLOOB_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLOOB) >> OSCCTRL_INTFLAG_DFLLOOB_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLOOB_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLOOB; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKF) >> OSCCTRL_INTFLAG_DFLLLCKF_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKF; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLLCKC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKC) >> OSCCTRL_INTFLAG_DFLLLCKC_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLLCKC_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKC; +} + +static inline bool hri_oscctrl_get_INTFLAG_DFLLRCS_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRCS) >> OSCCTRL_INTFLAG_DFLLRCS_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DFLLRCS_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRCS; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL0LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKR) >> OSCCTRL_INTFLAG_DPLL0LCKR_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL0LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKR; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL0LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKF) >> OSCCTRL_INTFLAG_DPLL0LCKF_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL0LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKF; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL0LTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LTO) >> OSCCTRL_INTFLAG_DPLL0LTO_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL0LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LTO; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL0LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LDRTO) >> OSCCTRL_INTFLAG_DPLL0LDRTO_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL0LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LDRTO; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL1LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKR) >> OSCCTRL_INTFLAG_DPLL1LCKR_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL1LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKR; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL1LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKF) >> OSCCTRL_INTFLAG_DPLL1LCKF_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL1LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKF; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL1LTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LTO) >> OSCCTRL_INTFLAG_DPLL1LTO_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL1LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LTO; +} + +static inline bool hri_oscctrl_get_INTFLAG_DPLL1LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LDRTO) >> OSCCTRL_INTFLAG_DPLL1LDRTO_Pos; +} + +static inline void hri_oscctrl_clear_INTFLAG_DPLL1LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LDRTO; +} + +static inline bool hri_oscctrl_get_interrupt_XOSCRDY0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY0) >> OSCCTRL_INTFLAG_XOSCRDY0_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_XOSCRDY0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY0; +} + +static inline bool hri_oscctrl_get_interrupt_XOSCRDY1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCRDY1) >> OSCCTRL_INTFLAG_XOSCRDY1_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_XOSCRDY1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCRDY1; +} + +static inline bool hri_oscctrl_get_interrupt_XOSCFAIL0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL0) >> OSCCTRL_INTFLAG_XOSCFAIL0_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_XOSCFAIL0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL0; +} + +static inline bool hri_oscctrl_get_interrupt_XOSCFAIL1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_XOSCFAIL1) >> OSCCTRL_INTFLAG_XOSCFAIL1_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_XOSCFAIL1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_XOSCFAIL1; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRDY) >> OSCCTRL_INTFLAG_DFLLRDY_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRDY; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLOOB_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLOOB) >> OSCCTRL_INTFLAG_DFLLOOB_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLOOB_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLOOB; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKF) >> OSCCTRL_INTFLAG_DFLLLCKF_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKF; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLLCKC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLLCKC) >> OSCCTRL_INTFLAG_DFLLLCKC_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLLCKC_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLLCKC; +} + +static inline bool hri_oscctrl_get_interrupt_DFLLRCS_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DFLLRCS) >> OSCCTRL_INTFLAG_DFLLRCS_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DFLLRCS_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DFLLRCS; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL0LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKR) >> OSCCTRL_INTFLAG_DPLL0LCKR_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL0LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKR; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL0LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LCKF) >> OSCCTRL_INTFLAG_DPLL0LCKF_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL0LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LCKF; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL0LTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LTO) >> OSCCTRL_INTFLAG_DPLL0LTO_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL0LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LTO; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL0LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL0LDRTO) >> OSCCTRL_INTFLAG_DPLL0LDRTO_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL0LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL0LDRTO; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL1LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKR) >> OSCCTRL_INTFLAG_DPLL1LCKR_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL1LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKR; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL1LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LCKF) >> OSCCTRL_INTFLAG_DPLL1LCKF_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL1LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LCKF; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL1LTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LTO) >> OSCCTRL_INTFLAG_DPLL1LTO_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL1LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LTO; +} + +static inline bool hri_oscctrl_get_interrupt_DPLL1LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTFLAG.reg & OSCCTRL_INTFLAG_DPLL1LDRTO) >> OSCCTRL_INTFLAG_DPLL1LDRTO_Pos; +} + +static inline void hri_oscctrl_clear_interrupt_DPLL1LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTFLAG.reg = OSCCTRL_INTFLAG_DPLL1LDRTO; +} + +static inline hri_oscctrl_intflag_reg_t hri_oscctrl_get_INTFLAG_reg(const void *const hw, + hri_oscctrl_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_intflag_reg_t hri_oscctrl_read_INTFLAG_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->INTFLAG.reg; +} + +static inline void hri_oscctrl_clear_INTFLAG_reg(const void *const hw, hri_oscctrl_intflag_reg_t mask) +{ + ((Oscctrl *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_oscctrl_set_INTEN_XOSCRDY0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY0; +} + +static inline bool hri_oscctrl_get_INTEN_XOSCRDY0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCRDY0) >> OSCCTRL_INTENSET_XOSCRDY0_Pos; +} + +static inline void hri_oscctrl_write_INTEN_XOSCRDY0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY0; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY0; + } +} + +static inline void hri_oscctrl_clear_INTEN_XOSCRDY0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY0; +} + +static inline void hri_oscctrl_set_INTEN_XOSCRDY1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY1; +} + +static inline bool hri_oscctrl_get_INTEN_XOSCRDY1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCRDY1) >> OSCCTRL_INTENSET_XOSCRDY1_Pos; +} + +static inline void hri_oscctrl_write_INTEN_XOSCRDY1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY1; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCRDY1; + } +} + +static inline void hri_oscctrl_clear_INTEN_XOSCRDY1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCRDY1; +} + +static inline void hri_oscctrl_set_INTEN_XOSCFAIL0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL0; +} + +static inline bool hri_oscctrl_get_INTEN_XOSCFAIL0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCFAIL0) >> OSCCTRL_INTENSET_XOSCFAIL0_Pos; +} + +static inline void hri_oscctrl_write_INTEN_XOSCFAIL0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL0; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL0; + } +} + +static inline void hri_oscctrl_clear_INTEN_XOSCFAIL0_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL0; +} + +static inline void hri_oscctrl_set_INTEN_XOSCFAIL1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL1; +} + +static inline bool hri_oscctrl_get_INTEN_XOSCFAIL1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_XOSCFAIL1) >> OSCCTRL_INTENSET_XOSCFAIL1_Pos; +} + +static inline void hri_oscctrl_write_INTEN_XOSCFAIL1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL1; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_XOSCFAIL1; + } +} + +static inline void hri_oscctrl_clear_INTEN_XOSCFAIL1_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_XOSCFAIL1; +} + +static inline void hri_oscctrl_set_INTEN_DFLLRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRDY) >> OSCCTRL_INTENSET_DFLLRDY_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRDY; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLRDY_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRDY; +} + +static inline void hri_oscctrl_set_INTEN_DFLLOOB_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLOOB_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLOOB) >> OSCCTRL_INTENSET_DFLLOOB_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLOOB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLOOB; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLOOB_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLOOB; +} + +static inline void hri_oscctrl_set_INTEN_DFLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKF; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLLCKF) >> OSCCTRL_INTENSET_DFLLLCKF_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLLCKF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKF; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLLCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKF; +} + +static inline void hri_oscctrl_set_INTEN_DFLLLCKC_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKC; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLLCKC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLLCKC) >> OSCCTRL_INTENSET_DFLLLCKC_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLLCKC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKC; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLLCKC; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLLCKC_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLLCKC; +} + +static inline void hri_oscctrl_set_INTEN_DFLLRCS_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRCS; +} + +static inline bool hri_oscctrl_get_INTEN_DFLLRCS_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DFLLRCS) >> OSCCTRL_INTENSET_DFLLRCS_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DFLLRCS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRCS; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DFLLRCS; + } +} + +static inline void hri_oscctrl_clear_INTEN_DFLLRCS_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DFLLRCS; +} + +static inline void hri_oscctrl_set_INTEN_DPLL0LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKR; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL0LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LCKR) >> OSCCTRL_INTENSET_DPLL0LCKR_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL0LCKR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKR; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKR; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL0LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKR; +} + +static inline void hri_oscctrl_set_INTEN_DPLL0LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKF; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL0LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LCKF) >> OSCCTRL_INTENSET_DPLL0LCKF_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL0LCKF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKF; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LCKF; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL0LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LCKF; +} + +static inline void hri_oscctrl_set_INTEN_DPLL0LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LTO; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL0LTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LTO) >> OSCCTRL_INTENSET_DPLL0LTO_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL0LTO_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LTO; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LTO; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL0LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LTO; +} + +static inline void hri_oscctrl_set_INTEN_DPLL0LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LDRTO; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL0LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL0LDRTO) >> OSCCTRL_INTENSET_DPLL0LDRTO_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL0LDRTO_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LDRTO; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL0LDRTO; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL0LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL0LDRTO; +} + +static inline void hri_oscctrl_set_INTEN_DPLL1LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKR; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL1LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LCKR) >> OSCCTRL_INTENSET_DPLL1LCKR_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL1LCKR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKR; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKR; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL1LCKR_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKR; +} + +static inline void hri_oscctrl_set_INTEN_DPLL1LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKF; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL1LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LCKF) >> OSCCTRL_INTENSET_DPLL1LCKF_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL1LCKF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKF; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LCKF; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL1LCKF_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LCKF; +} + +static inline void hri_oscctrl_set_INTEN_DPLL1LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LTO; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL1LTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LTO) >> OSCCTRL_INTENSET_DPLL1LTO_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL1LTO_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LTO; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LTO; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL1LTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LTO; +} + +static inline void hri_oscctrl_set_INTEN_DPLL1LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LDRTO; +} + +static inline bool hri_oscctrl_get_INTEN_DPLL1LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->INTENSET.reg & OSCCTRL_INTENSET_DPLL1LDRTO) >> OSCCTRL_INTENSET_DPLL1LDRTO_Pos; +} + +static inline void hri_oscctrl_write_INTEN_DPLL1LDRTO_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LDRTO; + } else { + ((Oscctrl *)hw)->INTENSET.reg = OSCCTRL_INTENSET_DPLL1LDRTO; + } +} + +static inline void hri_oscctrl_clear_INTEN_DPLL1LDRTO_bit(const void *const hw) +{ + ((Oscctrl *)hw)->INTENCLR.reg = OSCCTRL_INTENSET_DPLL1LDRTO; +} + +static inline void hri_oscctrl_set_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask) +{ + ((Oscctrl *)hw)->INTENSET.reg = mask; +} + +static inline hri_oscctrl_intenset_reg_t hri_oscctrl_get_INTEN_reg(const void *const hw, + hri_oscctrl_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_intenset_reg_t hri_oscctrl_read_INTEN_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->INTENSET.reg; +} + +static inline void hri_oscctrl_write_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t data) +{ + ((Oscctrl *)hw)->INTENSET.reg = data; + ((Oscctrl *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_oscctrl_clear_INTEN_reg(const void *const hw, hri_oscctrl_intenset_reg_t mask) +{ + ((Oscctrl *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCRDY0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCRDY0) >> OSCCTRL_STATUS_XOSCRDY0_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCRDY1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCRDY1) >> OSCCTRL_STATUS_XOSCRDY1_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCFAIL0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCFAIL0) >> OSCCTRL_STATUS_XOSCFAIL0_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCFAIL1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCFAIL1) >> OSCCTRL_STATUS_XOSCFAIL1_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCCKSW0_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCCKSW0) >> OSCCTRL_STATUS_XOSCCKSW0_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_XOSCCKSW1_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_XOSCCKSW1) >> OSCCTRL_STATUS_XOSCCKSW1_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLRDY_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRDY) >> OSCCTRL_STATUS_DFLLRDY_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLOOB_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLOOB) >> OSCCTRL_STATUS_DFLLOOB_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLLCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLLCKF) >> OSCCTRL_STATUS_DFLLLCKF_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLLCKC_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLLCKC) >> OSCCTRL_STATUS_DFLLLCKC_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DFLLRCS_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DFLLRCS) >> OSCCTRL_STATUS_DFLLRCS_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL0LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0LCKR) >> OSCCTRL_STATUS_DPLL0LCKR_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL0LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0LCKF) >> OSCCTRL_STATUS_DPLL0LCKF_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL0TO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0TO) >> OSCCTRL_STATUS_DPLL0TO_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL0LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL0LDRTO) >> OSCCTRL_STATUS_DPLL0LDRTO_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL1LCKR_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1LCKR) >> OSCCTRL_STATUS_DPLL1LCKR_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL1LCKF_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1LCKF) >> OSCCTRL_STATUS_DPLL1LCKF_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL1TO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1TO) >> OSCCTRL_STATUS_DPLL1TO_Pos; +} + +static inline bool hri_oscctrl_get_STATUS_DPLL1LDRTO_bit(const void *const hw) +{ + return (((Oscctrl *)hw)->STATUS.reg & OSCCTRL_STATUS_DPLL1LDRTO) >> OSCCTRL_STATUS_DPLL1LDRTO_Pos; +} + +static inline hri_oscctrl_status_reg_t hri_oscctrl_get_STATUS_reg(const void *const hw, hri_oscctrl_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_oscctrl_status_reg_t hri_oscctrl_read_STATUS_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->STATUS.reg; +} + +static inline void hri_oscctrl_set_EVCTRL_CFDEO0_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg |= OSCCTRL_EVCTRL_CFDEO0; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_EVCTRL_CFDEO0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->EVCTRL.reg; + tmp = (tmp & OSCCTRL_EVCTRL_CFDEO0) >> OSCCTRL_EVCTRL_CFDEO0_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_EVCTRL_CFDEO0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->EVCTRL.reg; + tmp &= ~OSCCTRL_EVCTRL_CFDEO0; + tmp |= value << OSCCTRL_EVCTRL_CFDEO0_Pos; + ((Oscctrl *)hw)->EVCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_EVCTRL_CFDEO0_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg &= ~OSCCTRL_EVCTRL_CFDEO0; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_EVCTRL_CFDEO0_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg ^= OSCCTRL_EVCTRL_CFDEO0; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_EVCTRL_CFDEO1_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg |= OSCCTRL_EVCTRL_CFDEO1; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_EVCTRL_CFDEO1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->EVCTRL.reg; + tmp = (tmp & OSCCTRL_EVCTRL_CFDEO1) >> OSCCTRL_EVCTRL_CFDEO1_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_EVCTRL_CFDEO1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->EVCTRL.reg; + tmp &= ~OSCCTRL_EVCTRL_CFDEO1; + tmp |= value << OSCCTRL_EVCTRL_CFDEO1_Pos; + ((Oscctrl *)hw)->EVCTRL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_EVCTRL_CFDEO1_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg &= ~OSCCTRL_EVCTRL_CFDEO1; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_EVCTRL_CFDEO1_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg ^= OSCCTRL_EVCTRL_CFDEO1; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_evctrl_reg_t hri_oscctrl_get_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_EVCTRL_reg(const void *const hw, hri_oscctrl_evctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->EVCTRL.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_evctrl_reg_t hri_oscctrl_read_EVCTRL_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->EVCTRL.reg; +} + +static inline void hri_oscctrl_set_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_ENABLE) >> OSCCTRL_XOSCCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_ENABLE; + tmp |= value << OSCCTRL_XOSCCTRL_ENABLE_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_ENABLE_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_XTALEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_XTALEN) >> OSCCTRL_XOSCCTRL_XTALEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_XTALEN; + tmp |= value << OSCCTRL_XOSCCTRL_XTALEN_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_XTALEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_XTALEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_XTALEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_RUNSTDBY) >> OSCCTRL_XOSCCTRL_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_RUNSTDBY; + tmp |= value << OSCCTRL_XOSCCTRL_RUNSTDBY_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_ONDEMAND) >> OSCCTRL_XOSCCTRL_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_ONDEMAND; + tmp |= value << OSCCTRL_XOSCCTRL_ONDEMAND_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_ONDEMAND_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_LOWBUFGAIN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_LOWBUFGAIN) >> OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_LOWBUFGAIN; + tmp |= value << OSCCTRL_XOSCCTRL_LOWBUFGAIN_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_LOWBUFGAIN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_LOWBUFGAIN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_LOWBUFGAIN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_ENALC; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_ENALC) >> OSCCTRL_XOSCCTRL_ENALC_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_ENALC; + tmp |= value << OSCCTRL_XOSCCTRL_ENALC_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_ENALC; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_ENALC_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_ENALC; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_CFDEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_CFDEN) >> OSCCTRL_XOSCCTRL_CFDEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_CFDEN; + tmp |= value << OSCCTRL_XOSCCTRL_CFDEN_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_CFDEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_CFDEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_CFDEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_SWBEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_SWBEN) >> OSCCTRL_XOSCCTRL_SWBEN_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_SWBEN; + tmp |= value << OSCCTRL_XOSCCTRL_SWBEN_Pos; + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_SWBEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_SWBEN_bit(const void *const hw, uint8_t index) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_SWBEN; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_IPTAT(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_IPTAT(mask)) >> OSCCTRL_XOSCCTRL_IPTAT_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_IPTAT_Msk; + tmp |= OSCCTRL_XOSCCTRL_IPTAT(data); + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_IPTAT(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_IPTAT(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_IPTAT_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_IPTAT_Msk) >> OSCCTRL_XOSCCTRL_IPTAT_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_IMULT(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_IMULT(mask)) >> OSCCTRL_XOSCCTRL_IMULT_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_IMULT_Msk; + tmp |= OSCCTRL_XOSCCTRL_IMULT(data); + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_IMULT(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_IMULT(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_IMULT_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_IMULT_Msk) >> OSCCTRL_XOSCCTRL_IMULT_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_STARTUP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP(mask)) >> OSCCTRL_XOSCCTRL_STARTUP_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_STARTUP_Msk; + tmp |= OSCCTRL_XOSCCTRL_STARTUP(data); + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_STARTUP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_STARTUP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_STARTUP_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_STARTUP_Msk) >> OSCCTRL_XOSCCTRL_STARTUP_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= OSCCTRL_XOSCCTRL_CFDPRESC(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_CFDPRESC(mask)) >> OSCCTRL_XOSCCTRL_CFDPRESC_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= ~OSCCTRL_XOSCCTRL_CFDPRESC_Msk; + tmp |= OSCCTRL_XOSCCTRL_CFDPRESC(data); + ((Oscctrl *)hw)->XOSCCTRL[index].reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~OSCCTRL_XOSCCTRL_CFDPRESC(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= OSCCTRL_XOSCCTRL_CFDPRESC(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_CFDPRESC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp = (tmp & OSCCTRL_XOSCCTRL_CFDPRESC_Msk) >> OSCCTRL_XOSCCTRL_CFDPRESC_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_get_XOSCCTRL_reg(const void *const hw, uint8_t index, + hri_oscctrl_xoscctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->XOSCCTRL[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_XOSCCTRL_reg(const void *const hw, uint8_t index, hri_oscctrl_xoscctrl_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->XOSCCTRL[index].reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_xoscctrl_reg_t hri_oscctrl_read_XOSCCTRL_reg(const void *const hw, uint8_t index) +{ + return ((Oscctrl *)hw)->XOSCCTRL[index].reg; +} + +static inline void hri_oscctrl_set_DFLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLA_ENABLE) >> OSCCTRL_DFLLCTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; + tmp &= ~OSCCTRL_DFLLCTRLA_ENABLE; + tmp |= value << OSCCTRL_DFLLCTRLA_ENABLE_Pos; + ((Oscctrl *)hw)->DFLLCTRLA.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg &= ~OSCCTRL_DFLLCTRLA_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLA_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg ^= OSCCTRL_DFLLCTRLA_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLA_RUNSTDBY) >> OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; + tmp &= ~OSCCTRL_DFLLCTRLA_RUNSTDBY; + tmp |= value << OSCCTRL_DFLLCTRLA_RUNSTDBY_Pos; + ((Oscctrl *)hw)->DFLLCTRLA.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg &= ~OSCCTRL_DFLLCTRLA_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLA_RUNSTDBY_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg ^= OSCCTRL_DFLLCTRLA_RUNSTDBY; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg |= OSCCTRL_DFLLCTRLA_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLA_ONDEMAND) >> OSCCTRL_DFLLCTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; + tmp &= ~OSCCTRL_DFLLCTRLA_ONDEMAND; + tmp |= value << OSCCTRL_DFLLCTRLA_ONDEMAND_Pos; + ((Oscctrl *)hw)->DFLLCTRLA.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg &= ~OSCCTRL_DFLLCTRLA_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLA_ONDEMAND_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg ^= OSCCTRL_DFLLCTRLA_ONDEMAND; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllctrla_reg_t hri_oscctrl_get_DFLLCTRLA_reg(const void *const hw, + hri_oscctrl_dfllctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLA_reg(const void *const hw, hri_oscctrl_dfllctrla_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLA.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllctrla_reg_t hri_oscctrl_read_DFLLCTRLA_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DFLLCTRLA.reg; +} + +static inline void hri_oscctrl_set_DFLLCTRLB_MODE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_MODE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_MODE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_MODE) >> OSCCTRL_DFLLCTRLB_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_MODE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_MODE; + tmp |= value << OSCCTRL_DFLLCTRLB_MODE_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_MODE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_MODE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_MODE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_MODE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_STABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_STABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_STABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_STABLE) >> OSCCTRL_DFLLCTRLB_STABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_STABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_STABLE; + tmp |= value << OSCCTRL_DFLLCTRLB_STABLE_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_STABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_STABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_STABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_STABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_LLAW_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_LLAW; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_LLAW_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_LLAW) >> OSCCTRL_DFLLCTRLB_LLAW_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_LLAW_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_LLAW; + tmp |= value << OSCCTRL_DFLLCTRLB_LLAW_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_LLAW_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_LLAW; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_LLAW_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_LLAW; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_USBCRM_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_USBCRM; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_USBCRM_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_USBCRM) >> OSCCTRL_DFLLCTRLB_USBCRM_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_USBCRM_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_USBCRM; + tmp |= value << OSCCTRL_DFLLCTRLB_USBCRM_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_USBCRM_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_USBCRM; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_USBCRM_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_USBCRM; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_CCDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_CCDIS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_CCDIS_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_CCDIS) >> OSCCTRL_DFLLCTRLB_CCDIS_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_CCDIS_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_CCDIS; + tmp |= value << OSCCTRL_DFLLCTRLB_CCDIS_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_CCDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_CCDIS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_CCDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_CCDIS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_QLDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_QLDIS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_QLDIS_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_QLDIS) >> OSCCTRL_DFLLCTRLB_QLDIS_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_QLDIS_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_QLDIS; + tmp |= value << OSCCTRL_DFLLCTRLB_QLDIS_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_QLDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_QLDIS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_QLDIS_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_QLDIS; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_BPLCKC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_BPLCKC; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_BPLCKC_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_BPLCKC) >> OSCCTRL_DFLLCTRLB_BPLCKC_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_BPLCKC_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_BPLCKC; + tmp |= value << OSCCTRL_DFLLCTRLB_BPLCKC_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_BPLCKC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_BPLCKC; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_BPLCKC_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_BPLCKC; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_WAITLOCK_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= OSCCTRL_DFLLCTRLB_WAITLOCK; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLCTRLB_WAITLOCK_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp = (tmp & OSCCTRL_DFLLCTRLB_WAITLOCK) >> OSCCTRL_DFLLCTRLB_WAITLOCK_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_WAITLOCK_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= ~OSCCTRL_DFLLCTRLB_WAITLOCK; + tmp |= value << OSCCTRL_DFLLCTRLB_WAITLOCK_Pos; + ((Oscctrl *)hw)->DFLLCTRLB.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_WAITLOCK_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~OSCCTRL_DFLLCTRLB_WAITLOCK; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_WAITLOCK_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= OSCCTRL_DFLLCTRLB_WAITLOCK; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllctrlb_reg_t hri_oscctrl_get_DFLLCTRLB_reg(const void *const hw, + hri_oscctrl_dfllctrlb_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLCTRLB_reg(const void *const hw, hri_oscctrl_dfllctrlb_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLCTRLB.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllctrlb_reg_t hri_oscctrl_read_DFLLCTRLB_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DFLLCTRLB.reg; +} + +static inline void hri_oscctrl_set_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_FINE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_FINE_bf(const void *const hw, + hri_oscctrl_dfllval_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_FINE(mask)) >> OSCCTRL_DFLLVAL_FINE_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp &= ~OSCCTRL_DFLLVAL_FINE_Msk; + tmp |= OSCCTRL_DFLLVAL_FINE(data); + ((Oscctrl *)hw)->DFLLVAL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_FINE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLVAL_FINE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_FINE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_FINE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_FINE_Msk) >> OSCCTRL_DFLLVAL_FINE_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_COARSE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_COARSE_bf(const void *const hw, + hri_oscctrl_dfllval_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_COARSE(mask)) >> OSCCTRL_DFLLVAL_COARSE_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp &= ~OSCCTRL_DFLLVAL_COARSE_Msk; + tmp |= OSCCTRL_DFLLVAL_COARSE(data); + ((Oscctrl *)hw)->DFLLVAL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_COARSE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLVAL_COARSE_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_COARSE(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_COARSE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_COARSE_Msk) >> OSCCTRL_DFLLVAL_COARSE_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg |= OSCCTRL_DFLLVAL_DIFF(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_DIFF_bf(const void *const hw, + hri_oscctrl_dfllval_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_DIFF(mask)) >> OSCCTRL_DFLLVAL_DIFF_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp &= ~OSCCTRL_DFLLVAL_DIFF_Msk; + tmp |= OSCCTRL_DFLLVAL_DIFF(data); + ((Oscctrl *)hw)->DFLLVAL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg &= ~OSCCTRL_DFLLVAL_DIFF(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLVAL_DIFF_bf(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg ^= OSCCTRL_DFLLVAL_DIFF(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_DIFF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp = (tmp & OSCCTRL_DFLLVAL_DIFF_Msk) >> OSCCTRL_DFLLVAL_DIFF_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_get_DFLLVAL_reg(const void *const hw, + hri_oscctrl_dfllval_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLVAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLVAL_reg(const void *const hw, hri_oscctrl_dfllval_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLVAL.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllval_reg_t hri_oscctrl_read_DFLLVAL_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DFLLVAL.reg; +} + +static inline void hri_oscctrl_set_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_MUL(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_MUL_bf(const void *const hw, + hri_oscctrl_dfllmul_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_MUL(mask)) >> OSCCTRL_DFLLMUL_MUL_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp &= ~OSCCTRL_DFLLMUL_MUL_Msk; + tmp |= OSCCTRL_DFLLMUL_MUL(data); + ((Oscctrl *)hw)->DFLLMUL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_MUL(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLMUL_MUL_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_MUL(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_MUL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_MUL_Msk) >> OSCCTRL_DFLLMUL_MUL_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_FSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_FSTEP_bf(const void *const hw, + hri_oscctrl_dfllmul_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_FSTEP(mask)) >> OSCCTRL_DFLLMUL_FSTEP_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp &= ~OSCCTRL_DFLLMUL_FSTEP_Msk; + tmp |= OSCCTRL_DFLLMUL_FSTEP(data); + ((Oscctrl *)hw)->DFLLMUL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_FSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLMUL_FSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_FSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_FSTEP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_FSTEP_Msk) >> OSCCTRL_DFLLMUL_FSTEP_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg |= OSCCTRL_DFLLMUL_CSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_CSTEP_bf(const void *const hw, + hri_oscctrl_dfllmul_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_CSTEP(mask)) >> OSCCTRL_DFLLMUL_CSTEP_Pos; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t data) +{ + uint32_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp &= ~OSCCTRL_DFLLMUL_CSTEP_Msk; + tmp |= OSCCTRL_DFLLMUL_CSTEP(data); + ((Oscctrl *)hw)->DFLLMUL.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg &= ~OSCCTRL_DFLLMUL_CSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLMUL_CSTEP_bf(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg ^= OSCCTRL_DFLLMUL_CSTEP(mask); + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_CSTEP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp = (tmp & OSCCTRL_DFLLMUL_CSTEP_Msk) >> OSCCTRL_DFLLMUL_CSTEP_Pos; + return tmp; +} + +static inline void hri_oscctrl_set_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_get_DFLLMUL_reg(const void *const hw, + hri_oscctrl_dfllmul_reg_t mask) +{ + uint32_t tmp; + tmp = ((Oscctrl *)hw)->DFLLMUL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLMUL_reg(const void *const hw, hri_oscctrl_dfllmul_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLMUL.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllmul_reg_t hri_oscctrl_read_DFLLMUL_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DFLLMUL.reg; +} + +static inline void hri_oscctrl_set_DFLLSYNC_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLSYNC_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp = (tmp & OSCCTRL_DFLLSYNC_ENABLE) >> OSCCTRL_DFLLSYNC_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLSYNC_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp &= ~OSCCTRL_DFLLSYNC_ENABLE; + tmp |= value << OSCCTRL_DFLLSYNC_ENABLE_Pos; + ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLSYNC_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLSYNC_ENABLE_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_ENABLE; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLSYNC_DFLLCTRLB_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_DFLLCTRLB; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLSYNC_DFLLCTRLB_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp = (tmp & OSCCTRL_DFLLSYNC_DFLLCTRLB) >> OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLSYNC_DFLLCTRLB_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp &= ~OSCCTRL_DFLLSYNC_DFLLCTRLB; + tmp |= value << OSCCTRL_DFLLSYNC_DFLLCTRLB_Pos; + ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLSYNC_DFLLCTRLB_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_DFLLCTRLB; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLSYNC_DFLLCTRLB_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_DFLLCTRLB; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLSYNC_DFLLVAL_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_DFLLVAL; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLSYNC_DFLLVAL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp = (tmp & OSCCTRL_DFLLSYNC_DFLLVAL) >> OSCCTRL_DFLLSYNC_DFLLVAL_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLSYNC_DFLLVAL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp &= ~OSCCTRL_DFLLSYNC_DFLLVAL; + tmp |= value << OSCCTRL_DFLLSYNC_DFLLVAL_Pos; + ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLSYNC_DFLLVAL_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_DFLLVAL; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLSYNC_DFLLVAL_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_DFLLVAL; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLSYNC_DFLLMUL_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg |= OSCCTRL_DFLLSYNC_DFLLMUL; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_oscctrl_get_DFLLSYNC_DFLLMUL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp = (tmp & OSCCTRL_DFLLSYNC_DFLLMUL) >> OSCCTRL_DFLLSYNC_DFLLMUL_Pos; + return (bool)tmp; +} + +static inline void hri_oscctrl_write_DFLLSYNC_DFLLMUL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + OSCCTRL_CRITICAL_SECTION_ENTER(); + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp &= ~OSCCTRL_DFLLSYNC_DFLLMUL; + tmp |= value << OSCCTRL_DFLLSYNC_DFLLMUL_Pos; + ((Oscctrl *)hw)->DFLLSYNC.reg = tmp; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLSYNC_DFLLMUL_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg &= ~OSCCTRL_DFLLSYNC_DFLLMUL; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLSYNC_DFLLMUL_bit(const void *const hw) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg ^= OSCCTRL_DFLLSYNC_DFLLMUL; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_set_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg |= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllsync_reg_t hri_oscctrl_get_DFLLSYNC_reg(const void *const hw, + hri_oscctrl_dfllsync_reg_t mask) +{ + uint8_t tmp; + tmp = ((Oscctrl *)hw)->DFLLSYNC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_oscctrl_write_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t data) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg = data; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_clear_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg &= ~mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_oscctrl_toggle_DFLLSYNC_reg(const void *const hw, hri_oscctrl_dfllsync_reg_t mask) +{ + OSCCTRL_CRITICAL_SECTION_ENTER(); + ((Oscctrl *)hw)->DFLLSYNC.reg ^= mask; + OSCCTRL_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_oscctrl_dfllsync_reg_t hri_oscctrl_read_DFLLSYNC_reg(const void *const hw) +{ + return ((Oscctrl *)hw)->DFLLSYNC.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_OSCCTRL_E54_H_INCLUDED */ +#endif /* _SAME54_OSCCTRL_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_pac_e54.h b/software/firmware/oracle_same54n19a/hri/hri_pac_e54.h new file mode 100644 index 00000000..89631354 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_pac_e54.h @@ -0,0 +1,1514 @@ +/** + * \file + * + * \brief SAM PAC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_PAC_COMPONENT_ +#ifndef _HRI_PAC_E54_H_INCLUDED_ +#define _HRI_PAC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PAC_CRITICAL_SECTIONS) +#define PAC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PAC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PAC_CRITICAL_SECTION_ENTER() +#define PAC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_pac_intflaga_reg_t; +typedef uint32_t hri_pac_intflagahb_reg_t; +typedef uint32_t hri_pac_intflagb_reg_t; +typedef uint32_t hri_pac_intflagc_reg_t; +typedef uint32_t hri_pac_intflagd_reg_t; +typedef uint32_t hri_pac_statusa_reg_t; +typedef uint32_t hri_pac_statusb_reg_t; +typedef uint32_t hri_pac_statusc_reg_t; +typedef uint32_t hri_pac_statusd_reg_t; +typedef uint32_t hri_pac_wrctrl_reg_t; +typedef uint8_t hri_pac_evctrl_reg_t; +typedef uint8_t hri_pac_intenset_reg_t; + +static inline bool hri_pac_get_INTFLAGAHB_FLASH_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_FLASH) >> PAC_INTFLAGAHB_FLASH_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_FLASH_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_FLASH; +} + +static inline bool hri_pac_get_INTFLAGAHB_FLASH_ALT_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_FLASH_ALT) >> PAC_INTFLAGAHB_FLASH_ALT_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_FLASH_ALT_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_FLASH_ALT; +} + +static inline bool hri_pac_get_INTFLAGAHB_SEEPROM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_SEEPROM) >> PAC_INTFLAGAHB_SEEPROM_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_SEEPROM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_SEEPROM; +} + +static inline bool hri_pac_get_INTFLAGAHB_RAMCM4S_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMCM4S) >> PAC_INTFLAGAHB_RAMCM4S_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_RAMCM4S_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMCM4S; +} + +static inline bool hri_pac_get_INTFLAGAHB_RAMPPPDSU_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMPPPDSU) >> PAC_INTFLAGAHB_RAMPPPDSU_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_RAMPPPDSU_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMPPPDSU; +} + +static inline bool hri_pac_get_INTFLAGAHB_RAMDMAWR_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMDMAWR) >> PAC_INTFLAGAHB_RAMDMAWR_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_RAMDMAWR_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMDMAWR; +} + +static inline bool hri_pac_get_INTFLAGAHB_RAMDMACICM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_RAMDMACICM) >> PAC_INTFLAGAHB_RAMDMACICM_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_RAMDMACICM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_RAMDMACICM; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB0) >> PAC_INTFLAGAHB_HPB0_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB0; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB1) >> PAC_INTFLAGAHB_HPB1_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB1; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB2) >> PAC_INTFLAGAHB_HPB2_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB2; +} + +static inline bool hri_pac_get_INTFLAGAHB_HPB3_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_HPB3) >> PAC_INTFLAGAHB_HPB3_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_HPB3_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_HPB3; +} + +static inline bool hri_pac_get_INTFLAGAHB_PUKCC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_PUKCC) >> PAC_INTFLAGAHB_PUKCC_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_PUKCC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_PUKCC; +} + +static inline bool hri_pac_get_INTFLAGAHB_SDHC0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_SDHC0) >> PAC_INTFLAGAHB_SDHC0_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_SDHC0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_SDHC0; +} + +static inline bool hri_pac_get_INTFLAGAHB_SDHC1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_SDHC1) >> PAC_INTFLAGAHB_SDHC1_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_SDHC1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_SDHC1; +} + +static inline bool hri_pac_get_INTFLAGAHB_QSPI_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_QSPI) >> PAC_INTFLAGAHB_QSPI_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_QSPI_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_QSPI; +} + +static inline bool hri_pac_get_INTFLAGAHB_BKUPRAM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGAHB.reg & PAC_INTFLAGAHB_BKUPRAM) >> PAC_INTFLAGAHB_BKUPRAM_Pos; +} + +static inline void hri_pac_clear_INTFLAGAHB_BKUPRAM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGAHB.reg = PAC_INTFLAGAHB_BKUPRAM; +} + +static inline hri_pac_intflagahb_reg_t hri_pac_get_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGAHB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagahb_reg_t hri_pac_read_INTFLAGAHB_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGAHB.reg; +} + +static inline void hri_pac_clear_INTFLAGAHB_reg(const void *const hw, hri_pac_intflagahb_reg_t mask) +{ + ((Pac *)hw)->INTFLAGAHB.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGA_PAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PAC) >> PAC_INTFLAGA_PAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_PAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PAC; +} + +static inline bool hri_pac_get_INTFLAGA_PM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_PM) >> PAC_INTFLAGA_PM_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_PM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_PM; +} + +static inline bool hri_pac_get_INTFLAGA_MCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_MCLK) >> PAC_INTFLAGA_MCLK_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_MCLK_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_MCLK; +} + +static inline bool hri_pac_get_INTFLAGA_RSTC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RSTC) >> PAC_INTFLAGA_RSTC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_RSTC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RSTC; +} + +static inline bool hri_pac_get_INTFLAGA_OSCCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSCCTRL) >> PAC_INTFLAGA_OSCCTRL_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_OSCCTRL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSCCTRL; +} + +static inline bool hri_pac_get_INTFLAGA_OSC32KCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_OSC32KCTRL) >> PAC_INTFLAGA_OSC32KCTRL_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_OSC32KCTRL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_OSC32KCTRL; +} + +static inline bool hri_pac_get_INTFLAGA_SUPC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SUPC) >> PAC_INTFLAGA_SUPC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_SUPC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SUPC; +} + +static inline bool hri_pac_get_INTFLAGA_GCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_GCLK) >> PAC_INTFLAGA_GCLK_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_GCLK_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_GCLK; +} + +static inline bool hri_pac_get_INTFLAGA_WDT_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_WDT) >> PAC_INTFLAGA_WDT_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_WDT_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_WDT; +} + +static inline bool hri_pac_get_INTFLAGA_RTC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_RTC) >> PAC_INTFLAGA_RTC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_RTC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_RTC; +} + +static inline bool hri_pac_get_INTFLAGA_EIC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_EIC) >> PAC_INTFLAGA_EIC_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_EIC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_EIC; +} + +static inline bool hri_pac_get_INTFLAGA_FREQM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_FREQM) >> PAC_INTFLAGA_FREQM_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_FREQM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_FREQM; +} + +static inline bool hri_pac_get_INTFLAGA_SERCOM0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SERCOM0) >> PAC_INTFLAGA_SERCOM0_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_SERCOM0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SERCOM0; +} + +static inline bool hri_pac_get_INTFLAGA_SERCOM1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_SERCOM1) >> PAC_INTFLAGA_SERCOM1_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_SERCOM1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_SERCOM1; +} + +static inline bool hri_pac_get_INTFLAGA_TC0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_TC0) >> PAC_INTFLAGA_TC0_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_TC0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_TC0; +} + +static inline bool hri_pac_get_INTFLAGA_TC1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGA.reg & PAC_INTFLAGA_TC1) >> PAC_INTFLAGA_TC1_Pos; +} + +static inline void hri_pac_clear_INTFLAGA_TC1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGA.reg = PAC_INTFLAGA_TC1; +} + +static inline hri_pac_intflaga_reg_t hri_pac_get_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflaga_reg_t hri_pac_read_INTFLAGA_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGA.reg; +} + +static inline void hri_pac_clear_INTFLAGA_reg(const void *const hw, hri_pac_intflaga_reg_t mask) +{ + ((Pac *)hw)->INTFLAGA.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGB_USB_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_USB) >> PAC_INTFLAGB_USB_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_USB_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_USB; +} + +static inline bool hri_pac_get_INTFLAGB_DSU_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DSU) >> PAC_INTFLAGB_DSU_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_DSU_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DSU; +} + +static inline bool hri_pac_get_INTFLAGB_NVMCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_NVMCTRL) >> PAC_INTFLAGB_NVMCTRL_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_NVMCTRL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_NVMCTRL; +} + +static inline bool hri_pac_get_INTFLAGB_CMCC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_CMCC) >> PAC_INTFLAGB_CMCC_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_CMCC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_CMCC; +} + +static inline bool hri_pac_get_INTFLAGB_PORT_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_PORT) >> PAC_INTFLAGB_PORT_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_PORT_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_PORT; +} + +static inline bool hri_pac_get_INTFLAGB_DMAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_DMAC) >> PAC_INTFLAGB_DMAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_DMAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_DMAC; +} + +static inline bool hri_pac_get_INTFLAGB_HMATRIX_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_HMATRIX) >> PAC_INTFLAGB_HMATRIX_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_HMATRIX_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_HMATRIX; +} + +static inline bool hri_pac_get_INTFLAGB_EVSYS_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_EVSYS) >> PAC_INTFLAGB_EVSYS_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_EVSYS_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_EVSYS; +} + +static inline bool hri_pac_get_INTFLAGB_SERCOM2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_SERCOM2) >> PAC_INTFLAGB_SERCOM2_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_SERCOM2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_SERCOM2; +} + +static inline bool hri_pac_get_INTFLAGB_SERCOM3_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_SERCOM3) >> PAC_INTFLAGB_SERCOM3_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_SERCOM3_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_SERCOM3; +} + +static inline bool hri_pac_get_INTFLAGB_TCC0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TCC0) >> PAC_INTFLAGB_TCC0_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_TCC0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TCC0; +} + +static inline bool hri_pac_get_INTFLAGB_TCC1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TCC1) >> PAC_INTFLAGB_TCC1_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_TCC1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TCC1; +} + +static inline bool hri_pac_get_INTFLAGB_TC2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TC2) >> PAC_INTFLAGB_TC2_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_TC2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TC2; +} + +static inline bool hri_pac_get_INTFLAGB_TC3_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_TC3) >> PAC_INTFLAGB_TC3_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_TC3_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_TC3; +} + +static inline bool hri_pac_get_INTFLAGB_RAMECC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGB.reg & PAC_INTFLAGB_RAMECC) >> PAC_INTFLAGB_RAMECC_Pos; +} + +static inline void hri_pac_clear_INTFLAGB_RAMECC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGB.reg = PAC_INTFLAGB_RAMECC; +} + +static inline hri_pac_intflagb_reg_t hri_pac_get_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagb_reg_t hri_pac_read_INTFLAGB_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGB.reg; +} + +static inline void hri_pac_clear_INTFLAGB_reg(const void *const hw, hri_pac_intflagb_reg_t mask) +{ + ((Pac *)hw)->INTFLAGB.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGC_CAN0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CAN0) >> PAC_INTFLAGC_CAN0_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_CAN0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CAN0; +} + +static inline bool hri_pac_get_INTFLAGC_CAN1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CAN1) >> PAC_INTFLAGC_CAN1_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_CAN1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CAN1; +} + +static inline bool hri_pac_get_INTFLAGC_GMAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_GMAC) >> PAC_INTFLAGC_GMAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_GMAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_GMAC; +} + +static inline bool hri_pac_get_INTFLAGC_TCC2_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC2) >> PAC_INTFLAGC_TCC2_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TCC2_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC2; +} + +static inline bool hri_pac_get_INTFLAGC_TCC3_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TCC3) >> PAC_INTFLAGC_TCC3_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TCC3_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TCC3; +} + +static inline bool hri_pac_get_INTFLAGC_TC4_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC4) >> PAC_INTFLAGC_TC4_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TC4_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC4; +} + +static inline bool hri_pac_get_INTFLAGC_TC5_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TC5) >> PAC_INTFLAGC_TC5_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TC5_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TC5; +} + +static inline bool hri_pac_get_INTFLAGC_PDEC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_PDEC) >> PAC_INTFLAGC_PDEC_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_PDEC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_PDEC; +} + +static inline bool hri_pac_get_INTFLAGC_AC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_AC) >> PAC_INTFLAGC_AC_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_AC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_AC; +} + +static inline bool hri_pac_get_INTFLAGC_AES_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_AES) >> PAC_INTFLAGC_AES_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_AES_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_AES; +} + +static inline bool hri_pac_get_INTFLAGC_TRNG_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_TRNG) >> PAC_INTFLAGC_TRNG_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_TRNG_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_TRNG; +} + +static inline bool hri_pac_get_INTFLAGC_ICM_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_ICM) >> PAC_INTFLAGC_ICM_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_ICM_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_ICM; +} + +static inline bool hri_pac_get_INTFLAGC_PUKCC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_PUKCC) >> PAC_INTFLAGC_PUKCC_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_PUKCC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_PUKCC; +} + +static inline bool hri_pac_get_INTFLAGC_QSPI_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_QSPI) >> PAC_INTFLAGC_QSPI_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_QSPI_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_QSPI; +} + +static inline bool hri_pac_get_INTFLAGC_CCL_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGC.reg & PAC_INTFLAGC_CCL) >> PAC_INTFLAGC_CCL_Pos; +} + +static inline void hri_pac_clear_INTFLAGC_CCL_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGC.reg = PAC_INTFLAGC_CCL; +} + +static inline hri_pac_intflagc_reg_t hri_pac_get_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGC.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagc_reg_t hri_pac_read_INTFLAGC_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGC.reg; +} + +static inline void hri_pac_clear_INTFLAGC_reg(const void *const hw, hri_pac_intflagc_reg_t mask) +{ + ((Pac *)hw)->INTFLAGC.reg = mask; +} + +static inline bool hri_pac_get_INTFLAGD_SERCOM4_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM4) >> PAC_INTFLAGD_SERCOM4_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_SERCOM4_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM4; +} + +static inline bool hri_pac_get_INTFLAGD_SERCOM5_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM5) >> PAC_INTFLAGD_SERCOM5_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_SERCOM5_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM5; +} + +static inline bool hri_pac_get_INTFLAGD_SERCOM6_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM6) >> PAC_INTFLAGD_SERCOM6_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_SERCOM6_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM6; +} + +static inline bool hri_pac_get_INTFLAGD_SERCOM7_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_SERCOM7) >> PAC_INTFLAGD_SERCOM7_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_SERCOM7_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_SERCOM7; +} + +static inline bool hri_pac_get_INTFLAGD_TCC4_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TCC4) >> PAC_INTFLAGD_TCC4_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_TCC4_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TCC4; +} + +static inline bool hri_pac_get_INTFLAGD_TC6_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TC6) >> PAC_INTFLAGD_TC6_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_TC6_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TC6; +} + +static inline bool hri_pac_get_INTFLAGD_TC7_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_TC7) >> PAC_INTFLAGD_TC7_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_TC7_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_TC7; +} + +static inline bool hri_pac_get_INTFLAGD_ADC0_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_ADC0) >> PAC_INTFLAGD_ADC0_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_ADC0_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_ADC0; +} + +static inline bool hri_pac_get_INTFLAGD_ADC1_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_ADC1) >> PAC_INTFLAGD_ADC1_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_ADC1_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_ADC1; +} + +static inline bool hri_pac_get_INTFLAGD_DAC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_DAC) >> PAC_INTFLAGD_DAC_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_DAC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_DAC; +} + +static inline bool hri_pac_get_INTFLAGD_I2S_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_I2S) >> PAC_INTFLAGD_I2S_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_I2S_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_I2S; +} + +static inline bool hri_pac_get_INTFLAGD_PCC_bit(const void *const hw) +{ + return (((Pac *)hw)->INTFLAGD.reg & PAC_INTFLAGD_PCC) >> PAC_INTFLAGD_PCC_Pos; +} + +static inline void hri_pac_clear_INTFLAGD_PCC_bit(const void *const hw) +{ + ((Pac *)hw)->INTFLAGD.reg = PAC_INTFLAGD_PCC; +} + +static inline hri_pac_intflagd_reg_t hri_pac_get_INTFLAGD_reg(const void *const hw, hri_pac_intflagd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->INTFLAGD.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intflagd_reg_t hri_pac_read_INTFLAGD_reg(const void *const hw) +{ + return ((Pac *)hw)->INTFLAGD.reg; +} + +static inline void hri_pac_clear_INTFLAGD_reg(const void *const hw, hri_pac_intflagd_reg_t mask) +{ + ((Pac *)hw)->INTFLAGD.reg = mask; +} + +static inline void hri_pac_set_INTEN_ERR_bit(const void *const hw) +{ + ((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR; +} + +static inline bool hri_pac_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Pac *)hw)->INTENSET.reg & PAC_INTENSET_ERR) >> PAC_INTENSET_ERR_Pos; +} + +static inline void hri_pac_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR; + } else { + ((Pac *)hw)->INTENSET.reg = PAC_INTENSET_ERR; + } +} + +static inline void hri_pac_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Pac *)hw)->INTENCLR.reg = PAC_INTENSET_ERR; +} + +static inline void hri_pac_set_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) +{ + ((Pac *)hw)->INTENSET.reg = mask; +} + +static inline hri_pac_intenset_reg_t hri_pac_get_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pac *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_intenset_reg_t hri_pac_read_INTEN_reg(const void *const hw) +{ + return ((Pac *)hw)->INTENSET.reg; +} + +static inline void hri_pac_write_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t data) +{ + ((Pac *)hw)->INTENSET.reg = data; + ((Pac *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_pac_clear_INTEN_reg(const void *const hw, hri_pac_intenset_reg_t mask) +{ + ((Pac *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_pac_get_STATUSA_PAC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PAC) >> PAC_STATUSA_PAC_Pos; +} + +static inline bool hri_pac_get_STATUSA_PM_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_PM) >> PAC_STATUSA_PM_Pos; +} + +static inline bool hri_pac_get_STATUSA_MCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_MCLK) >> PAC_STATUSA_MCLK_Pos; +} + +static inline bool hri_pac_get_STATUSA_RSTC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RSTC) >> PAC_STATUSA_RSTC_Pos; +} + +static inline bool hri_pac_get_STATUSA_OSCCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSCCTRL) >> PAC_STATUSA_OSCCTRL_Pos; +} + +static inline bool hri_pac_get_STATUSA_OSC32KCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_OSC32KCTRL) >> PAC_STATUSA_OSC32KCTRL_Pos; +} + +static inline bool hri_pac_get_STATUSA_SUPC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SUPC) >> PAC_STATUSA_SUPC_Pos; +} + +static inline bool hri_pac_get_STATUSA_GCLK_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_GCLK) >> PAC_STATUSA_GCLK_Pos; +} + +static inline bool hri_pac_get_STATUSA_WDT_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_WDT) >> PAC_STATUSA_WDT_Pos; +} + +static inline bool hri_pac_get_STATUSA_RTC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_RTC) >> PAC_STATUSA_RTC_Pos; +} + +static inline bool hri_pac_get_STATUSA_EIC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_EIC) >> PAC_STATUSA_EIC_Pos; +} + +static inline bool hri_pac_get_STATUSA_FREQM_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_FREQM) >> PAC_STATUSA_FREQM_Pos; +} + +static inline bool hri_pac_get_STATUSA_SERCOM0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SERCOM0) >> PAC_STATUSA_SERCOM0_Pos; +} + +static inline bool hri_pac_get_STATUSA_SERCOM1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_SERCOM1) >> PAC_STATUSA_SERCOM1_Pos; +} + +static inline bool hri_pac_get_STATUSA_TC0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_TC0) >> PAC_STATUSA_TC0_Pos; +} + +static inline bool hri_pac_get_STATUSA_TC1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSA.reg & PAC_STATUSA_TC1) >> PAC_STATUSA_TC1_Pos; +} + +static inline hri_pac_statusa_reg_t hri_pac_get_STATUSA_reg(const void *const hw, hri_pac_statusa_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusa_reg_t hri_pac_read_STATUSA_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSA.reg; +} + +static inline bool hri_pac_get_STATUSB_USB_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_USB) >> PAC_STATUSB_USB_Pos; +} + +static inline bool hri_pac_get_STATUSB_DSU_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DSU) >> PAC_STATUSB_DSU_Pos; +} + +static inline bool hri_pac_get_STATUSB_NVMCTRL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_NVMCTRL) >> PAC_STATUSB_NVMCTRL_Pos; +} + +static inline bool hri_pac_get_STATUSB_CMCC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_CMCC) >> PAC_STATUSB_CMCC_Pos; +} + +static inline bool hri_pac_get_STATUSB_PORT_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_PORT) >> PAC_STATUSB_PORT_Pos; +} + +static inline bool hri_pac_get_STATUSB_DMAC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_DMAC) >> PAC_STATUSB_DMAC_Pos; +} + +static inline bool hri_pac_get_STATUSB_HMATRIX_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_HMATRIX) >> PAC_STATUSB_HMATRIX_Pos; +} + +static inline bool hri_pac_get_STATUSB_EVSYS_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_EVSYS) >> PAC_STATUSB_EVSYS_Pos; +} + +static inline bool hri_pac_get_STATUSB_SERCOM2_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_SERCOM2) >> PAC_STATUSB_SERCOM2_Pos; +} + +static inline bool hri_pac_get_STATUSB_SERCOM3_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_SERCOM3) >> PAC_STATUSB_SERCOM3_Pos; +} + +static inline bool hri_pac_get_STATUSB_TCC0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TCC0) >> PAC_STATUSB_TCC0_Pos; +} + +static inline bool hri_pac_get_STATUSB_TCC1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TCC1) >> PAC_STATUSB_TCC1_Pos; +} + +static inline bool hri_pac_get_STATUSB_TC2_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TC2) >> PAC_STATUSB_TC2_Pos; +} + +static inline bool hri_pac_get_STATUSB_TC3_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_TC3) >> PAC_STATUSB_TC3_Pos; +} + +static inline bool hri_pac_get_STATUSB_RAMECC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSB.reg & PAC_STATUSB_RAMECC) >> PAC_STATUSB_RAMECC_Pos; +} + +static inline hri_pac_statusb_reg_t hri_pac_get_STATUSB_reg(const void *const hw, hri_pac_statusb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSB.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusb_reg_t hri_pac_read_STATUSB_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSB.reg; +} + +static inline bool hri_pac_get_STATUSC_CAN0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CAN0) >> PAC_STATUSC_CAN0_Pos; +} + +static inline bool hri_pac_get_STATUSC_CAN1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CAN1) >> PAC_STATUSC_CAN1_Pos; +} + +static inline bool hri_pac_get_STATUSC_GMAC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_GMAC) >> PAC_STATUSC_GMAC_Pos; +} + +static inline bool hri_pac_get_STATUSC_TCC2_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC2) >> PAC_STATUSC_TCC2_Pos; +} + +static inline bool hri_pac_get_STATUSC_TCC3_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TCC3) >> PAC_STATUSC_TCC3_Pos; +} + +static inline bool hri_pac_get_STATUSC_TC4_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC4) >> PAC_STATUSC_TC4_Pos; +} + +static inline bool hri_pac_get_STATUSC_TC5_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TC5) >> PAC_STATUSC_TC5_Pos; +} + +static inline bool hri_pac_get_STATUSC_PDEC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_PDEC) >> PAC_STATUSC_PDEC_Pos; +} + +static inline bool hri_pac_get_STATUSC_AC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_AC) >> PAC_STATUSC_AC_Pos; +} + +static inline bool hri_pac_get_STATUSC_AES_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_AES) >> PAC_STATUSC_AES_Pos; +} + +static inline bool hri_pac_get_STATUSC_TRNG_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_TRNG) >> PAC_STATUSC_TRNG_Pos; +} + +static inline bool hri_pac_get_STATUSC_ICM_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_ICM) >> PAC_STATUSC_ICM_Pos; +} + +static inline bool hri_pac_get_STATUSC_PUKCC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_PUKCC) >> PAC_STATUSC_PUKCC_Pos; +} + +static inline bool hri_pac_get_STATUSC_QSPI_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_QSPI) >> PAC_STATUSC_QSPI_Pos; +} + +static inline bool hri_pac_get_STATUSC_CCL_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSC.reg & PAC_STATUSC_CCL) >> PAC_STATUSC_CCL_Pos; +} + +static inline hri_pac_statusc_reg_t hri_pac_get_STATUSC_reg(const void *const hw, hri_pac_statusc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSC.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusc_reg_t hri_pac_read_STATUSC_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSC.reg; +} + +static inline bool hri_pac_get_STATUSD_SERCOM4_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM4) >> PAC_STATUSD_SERCOM4_Pos; +} + +static inline bool hri_pac_get_STATUSD_SERCOM5_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM5) >> PAC_STATUSD_SERCOM5_Pos; +} + +static inline bool hri_pac_get_STATUSD_SERCOM6_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM6) >> PAC_STATUSD_SERCOM6_Pos; +} + +static inline bool hri_pac_get_STATUSD_SERCOM7_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_SERCOM7) >> PAC_STATUSD_SERCOM7_Pos; +} + +static inline bool hri_pac_get_STATUSD_TCC4_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TCC4) >> PAC_STATUSD_TCC4_Pos; +} + +static inline bool hri_pac_get_STATUSD_TC6_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TC6) >> PAC_STATUSD_TC6_Pos; +} + +static inline bool hri_pac_get_STATUSD_TC7_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_TC7) >> PAC_STATUSD_TC7_Pos; +} + +static inline bool hri_pac_get_STATUSD_ADC0_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_ADC0) >> PAC_STATUSD_ADC0_Pos; +} + +static inline bool hri_pac_get_STATUSD_ADC1_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_ADC1) >> PAC_STATUSD_ADC1_Pos; +} + +static inline bool hri_pac_get_STATUSD_DAC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_DAC) >> PAC_STATUSD_DAC_Pos; +} + +static inline bool hri_pac_get_STATUSD_I2S_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_I2S) >> PAC_STATUSD_I2S_Pos; +} + +static inline bool hri_pac_get_STATUSD_PCC_bit(const void *const hw) +{ + return (((Pac *)hw)->STATUSD.reg & PAC_STATUSD_PCC) >> PAC_STATUSD_PCC_Pos; +} + +static inline hri_pac_statusd_reg_t hri_pac_get_STATUSD_reg(const void *const hw, hri_pac_statusd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->STATUSD.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pac_statusd_reg_t hri_pac_read_STATUSD_reg(const void *const hw) +{ + return ((Pac *)hw)->STATUSD.reg; +} + +static inline void hri_pac_set_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_PERID(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_PERID(mask)) >> PAC_WRCTRL_PERID_Pos; + return tmp; +} + +static inline void hri_pac_write_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t data) +{ + uint32_t tmp; + PAC_CRITICAL_SECTION_ENTER(); + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp &= ~PAC_WRCTRL_PERID_Msk; + tmp |= PAC_WRCTRL_PERID(data); + ((Pac *)hw)->WRCTRL.reg = tmp; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_PERID(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_WRCTRL_PERID_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_PERID(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_PERID_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_PERID_Msk) >> PAC_WRCTRL_PERID_Pos; + return tmp; +} + +static inline void hri_pac_set_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg |= PAC_WRCTRL_KEY(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_KEY(mask)) >> PAC_WRCTRL_KEY_Pos; + return tmp; +} + +static inline void hri_pac_write_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t data) +{ + uint32_t tmp; + PAC_CRITICAL_SECTION_ENTER(); + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp &= ~PAC_WRCTRL_KEY_Msk; + tmp |= PAC_WRCTRL_KEY(data); + ((Pac *)hw)->WRCTRL.reg = tmp; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg &= ~PAC_WRCTRL_KEY(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_WRCTRL_KEY_bf(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg ^= PAC_WRCTRL_KEY(mask); + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_KEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp = (tmp & PAC_WRCTRL_KEY_Msk) >> PAC_WRCTRL_KEY_Pos; + return tmp; +} + +static inline void hri_pac_set_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg |= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_get_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pac *)hw)->WRCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pac_write_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t data) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg = data; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg &= ~mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_WRCTRL_reg(const void *const hw, hri_pac_wrctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->WRCTRL.reg ^= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_wrctrl_reg_t hri_pac_read_WRCTRL_reg(const void *const hw) +{ + return ((Pac *)hw)->WRCTRL.reg; +} + +static inline void hri_pac_set_EVCTRL_ERREO_bit(const void *const hw) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg |= PAC_EVCTRL_ERREO; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pac_get_EVCTRL_ERREO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pac *)hw)->EVCTRL.reg; + tmp = (tmp & PAC_EVCTRL_ERREO) >> PAC_EVCTRL_ERREO_Pos; + return (bool)tmp; +} + +static inline void hri_pac_write_EVCTRL_ERREO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + PAC_CRITICAL_SECTION_ENTER(); + tmp = ((Pac *)hw)->EVCTRL.reg; + tmp &= ~PAC_EVCTRL_ERREO; + tmp |= value << PAC_EVCTRL_ERREO_Pos; + ((Pac *)hw)->EVCTRL.reg = tmp; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_EVCTRL_ERREO_bit(const void *const hw) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg &= ~PAC_EVCTRL_ERREO; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_EVCTRL_ERREO_bit(const void *const hw) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg ^= PAC_EVCTRL_ERREO; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_set_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg |= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_evctrl_reg_t hri_pac_get_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pac *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pac_write_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t data) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg = data; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_clear_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg &= ~mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pac_toggle_EVCTRL_reg(const void *const hw, hri_pac_evctrl_reg_t mask) +{ + PAC_CRITICAL_SECTION_ENTER(); + ((Pac *)hw)->EVCTRL.reg ^= mask; + PAC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pac_evctrl_reg_t hri_pac_read_EVCTRL_reg(const void *const hw) +{ + return ((Pac *)hw)->EVCTRL.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PAC_E54_H_INCLUDED */ +#endif /* _SAME54_PAC_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_pcc_e54.h b/software/firmware/oracle_same54n19a/hri/hri_pcc_e54.h new file mode 100644 index 00000000..42a56000 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_pcc_e54.h @@ -0,0 +1,298 @@ +/** + * \file + * + * \brief SAM PCC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_PCC_COMPONENT_ +#ifndef _HRI_PCC_E54_H_INCLUDED_ +#define _HRI_PCC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PCC_CRITICAL_SECTIONS) +#define PCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PCC_CRITICAL_SECTION_ENTER() +#define PCC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_pcc_imr_reg_t; +typedef uint32_t hri_pcc_isr_reg_t; +typedef uint32_t hri_pcc_mr_reg_t; +typedef uint32_t hri_pcc_rhr_reg_t; +typedef uint32_t hri_pcc_wpmr_reg_t; +typedef uint32_t hri_pcc_wpsr_reg_t; + +static inline void hri_pcc_set_IMR_DRDY_bit(const void *const hw) +{ + ((Pcc *)hw)->IER.reg = PCC_IMR_DRDY; +} + +static inline bool hri_pcc_get_IMR_DRDY_bit(const void *const hw) +{ + return (((Pcc *)hw)->IMR.reg & PCC_IMR_DRDY) >> PCC_IMR_DRDY_Pos; +} + +static inline void hri_pcc_write_IMR_DRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pcc *)hw)->IDR.reg = PCC_IMR_DRDY; + } else { + ((Pcc *)hw)->IER.reg = PCC_IMR_DRDY; + } +} + +static inline void hri_pcc_clear_IMR_DRDY_bit(const void *const hw) +{ + ((Pcc *)hw)->IDR.reg = PCC_IMR_DRDY; +} + +static inline void hri_pcc_set_IMR_OVRE_bit(const void *const hw) +{ + ((Pcc *)hw)->IER.reg = PCC_IMR_OVRE; +} + +static inline bool hri_pcc_get_IMR_OVRE_bit(const void *const hw) +{ + return (((Pcc *)hw)->IMR.reg & PCC_IMR_OVRE) >> PCC_IMR_OVRE_Pos; +} + +static inline void hri_pcc_write_IMR_OVRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pcc *)hw)->IDR.reg = PCC_IMR_OVRE; + } else { + ((Pcc *)hw)->IER.reg = PCC_IMR_OVRE; + } +} + +static inline void hri_pcc_clear_IMR_OVRE_bit(const void *const hw) +{ + ((Pcc *)hw)->IDR.reg = PCC_IMR_OVRE; +} + +static inline void hri_pcc_set_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask) +{ + ((Pcc *)hw)->IER.reg = mask; +} + +static inline hri_pcc_imr_reg_t hri_pcc_get_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pcc *)hw)->IMR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pcc_imr_reg_t hri_pcc_read_IMR_reg(const void *const hw) +{ + return ((Pcc *)hw)->IMR.reg; +} + +static inline void hri_pcc_write_IMR_reg(const void *const hw, hri_pcc_imr_reg_t data) +{ + ((Pcc *)hw)->IER.reg = data; + ((Pcc *)hw)->IDR.reg = ~data; +} + +static inline void hri_pcc_clear_IMR_reg(const void *const hw, hri_pcc_imr_reg_t mask) +{ + ((Pcc *)hw)->IDR.reg = mask; +} + +static inline bool hri_pcc_get_ISR_DRDY_bit(const void *const hw) +{ + return (((Pcc *)hw)->ISR.reg & PCC_ISR_DRDY) >> PCC_ISR_DRDY_Pos; +} + +static inline bool hri_pcc_get_ISR_OVRE_bit(const void *const hw) +{ + return (((Pcc *)hw)->ISR.reg & PCC_ISR_OVRE) >> PCC_ISR_OVRE_Pos; +} + +static inline hri_pcc_isr_reg_t hri_pcc_get_ISR_reg(const void *const hw, hri_pcc_isr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pcc *)hw)->ISR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pcc_isr_reg_t hri_pcc_read_ISR_reg(const void *const hw) +{ + return ((Pcc *)hw)->ISR.reg; +} + +static inline hri_pcc_rhr_reg_t hri_pcc_get_RHR_RDATA_bf(const void *const hw, hri_pcc_rhr_reg_t mask) +{ + return (((Pcc *)hw)->RHR.reg & PCC_RHR_RDATA(mask)) >> PCC_RHR_RDATA_Pos; +} + +static inline hri_pcc_rhr_reg_t hri_pcc_read_RHR_RDATA_bf(const void *const hw) +{ + return (((Pcc *)hw)->RHR.reg & PCC_RHR_RDATA_Msk) >> PCC_RHR_RDATA_Pos; +} + +static inline hri_pcc_rhr_reg_t hri_pcc_get_RHR_reg(const void *const hw, hri_pcc_rhr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pcc *)hw)->RHR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pcc_rhr_reg_t hri_pcc_read_RHR_reg(const void *const hw) +{ + return ((Pcc *)hw)->RHR.reg; +} + +static inline bool hri_pcc_get_WPSR_WPVS_bit(const void *const hw) +{ + return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVS) >> PCC_WPSR_WPVS_Pos; +} + +static inline hri_pcc_wpsr_reg_t hri_pcc_get_WPSR_WPVSRC_bf(const void *const hw, hri_pcc_wpsr_reg_t mask) +{ + return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVSRC(mask)) >> PCC_WPSR_WPVSRC_Pos; +} + +static inline hri_pcc_wpsr_reg_t hri_pcc_read_WPSR_WPVSRC_bf(const void *const hw) +{ + return (((Pcc *)hw)->WPSR.reg & PCC_WPSR_WPVSRC_Msk) >> PCC_WPSR_WPVSRC_Pos; +} + +static inline hri_pcc_wpsr_reg_t hri_pcc_get_WPSR_reg(const void *const hw, hri_pcc_wpsr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pcc *)hw)->WPSR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pcc_wpsr_reg_t hri_pcc_read_WPSR_reg(const void *const hw) +{ + return ((Pcc *)hw)->WPSR.reg; +} + +static inline void hri_pcc_set_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->MR.reg |= mask; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pcc_mr_reg_t hri_pcc_get_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pcc *)hw)->MR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pcc_write_MR_reg(const void *const hw, hri_pcc_mr_reg_t data) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->MR.reg = data; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pcc_clear_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->MR.reg &= ~mask; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pcc_toggle_MR_reg(const void *const hw, hri_pcc_mr_reg_t mask) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->MR.reg ^= mask; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pcc_mr_reg_t hri_pcc_read_MR_reg(const void *const hw) +{ + return ((Pcc *)hw)->MR.reg; +} + +static inline void hri_pcc_set_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->WPMR.reg |= mask; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pcc_wpmr_reg_t hri_pcc_get_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pcc *)hw)->WPMR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pcc_write_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t data) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->WPMR.reg = data; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pcc_clear_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->WPMR.reg &= ~mask; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pcc_toggle_WPMR_reg(const void *const hw, hri_pcc_wpmr_reg_t mask) +{ + PCC_CRITICAL_SECTION_ENTER(); + ((Pcc *)hw)->WPMR.reg ^= mask; + PCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pcc_wpmr_reg_t hri_pcc_read_WPMR_reg(const void *const hw) +{ + return ((Pcc *)hw)->WPMR.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PCC_E54_H_INCLUDED */ +#endif /* _SAME54_PCC_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_pdec_e54.h b/software/firmware/oracle_same54n19a/hri/hri_pdec_e54.h new file mode 100644 index 00000000..ec7ce303 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_pdec_e54.h @@ -0,0 +1,2684 @@ +/** + * \file + * + * \brief SAM PDEC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_PDEC_COMPONENT_ +#ifndef _HRI_PDEC_E54_H_INCLUDED_ +#define _HRI_PDEC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PDEC_CRITICAL_SECTIONS) +#define PDEC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PDEC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PDEC_CRITICAL_SECTION_ENTER() +#define PDEC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_pdec_evctrl_reg_t; +typedef uint16_t hri_pdec_status_reg_t; +typedef uint32_t hri_pdec_cc_reg_t; +typedef uint32_t hri_pdec_ccbuf_reg_t; +typedef uint32_t hri_pdec_count_reg_t; +typedef uint32_t hri_pdec_ctrla_reg_t; +typedef uint32_t hri_pdec_syncbusy_reg_t; +typedef uint8_t hri_pdec_ctrlbset_reg_t; +typedef uint8_t hri_pdec_dbgctrl_reg_t; +typedef uint8_t hri_pdec_filter_reg_t; +typedef uint8_t hri_pdec_filterbuf_reg_t; +typedef uint8_t hri_pdec_intenset_reg_t; +typedef uint8_t hri_pdec_intflag_reg_t; +typedef uint8_t hri_pdec_presc_reg_t; +typedef uint8_t hri_pdec_prescbuf_reg_t; + +static inline void hri_pdec_wait_for_sync(const void *const hw, hri_pdec_syncbusy_reg_t reg) +{ + while (((Pdec *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_pdec_is_syncing(const void *const hw, hri_pdec_syncbusy_reg_t reg) +{ + return ((Pdec *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_pdec_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_OVF) >> PDEC_INTFLAG_OVF_Pos; +} + +static inline void hri_pdec_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_OVF; +} + +static inline bool hri_pdec_get_INTFLAG_ERR_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_ERR) >> PDEC_INTFLAG_ERR_Pos; +} + +static inline void hri_pdec_clear_INTFLAG_ERR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_ERR; +} + +static inline bool hri_pdec_get_INTFLAG_DIR_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_DIR) >> PDEC_INTFLAG_DIR_Pos; +} + +static inline void hri_pdec_clear_INTFLAG_DIR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_DIR; +} + +static inline bool hri_pdec_get_INTFLAG_VLC_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_VLC) >> PDEC_INTFLAG_VLC_Pos; +} + +static inline void hri_pdec_clear_INTFLAG_VLC_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_VLC; +} + +static inline bool hri_pdec_get_INTFLAG_MC0_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC0) >> PDEC_INTFLAG_MC0_Pos; +} + +static inline void hri_pdec_clear_INTFLAG_MC0_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC0; +} + +static inline bool hri_pdec_get_INTFLAG_MC1_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC1) >> PDEC_INTFLAG_MC1_Pos; +} + +static inline void hri_pdec_clear_INTFLAG_MC1_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC1; +} + +static inline bool hri_pdec_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_OVF) >> PDEC_INTFLAG_OVF_Pos; +} + +static inline void hri_pdec_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_OVF; +} + +static inline bool hri_pdec_get_interrupt_ERR_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_ERR) >> PDEC_INTFLAG_ERR_Pos; +} + +static inline void hri_pdec_clear_interrupt_ERR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_ERR; +} + +static inline bool hri_pdec_get_interrupt_DIR_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_DIR) >> PDEC_INTFLAG_DIR_Pos; +} + +static inline void hri_pdec_clear_interrupt_DIR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_DIR; +} + +static inline bool hri_pdec_get_interrupt_VLC_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_VLC) >> PDEC_INTFLAG_VLC_Pos; +} + +static inline void hri_pdec_clear_interrupt_VLC_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_VLC; +} + +static inline bool hri_pdec_get_interrupt_MC0_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC0) >> PDEC_INTFLAG_MC0_Pos; +} + +static inline void hri_pdec_clear_interrupt_MC0_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC0; +} + +static inline bool hri_pdec_get_interrupt_MC1_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTFLAG.reg & PDEC_INTFLAG_MC1) >> PDEC_INTFLAG_MC1_Pos; +} + +static inline void hri_pdec_clear_interrupt_MC1_bit(const void *const hw) +{ + ((Pdec *)hw)->INTFLAG.reg = PDEC_INTFLAG_MC1; +} + +static inline hri_pdec_intflag_reg_t hri_pdec_get_INTFLAG_reg(const void *const hw, hri_pdec_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pdec_intflag_reg_t hri_pdec_read_INTFLAG_reg(const void *const hw) +{ + return ((Pdec *)hw)->INTFLAG.reg; +} + +static inline void hri_pdec_clear_INTFLAG_reg(const void *const hw, hri_pdec_intflag_reg_t mask) +{ + ((Pdec *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_pdec_set_CTRLB_LUPD_bit(const void *const hw) +{ + ((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_LUPD; +} + +static inline bool hri_pdec_get_CTRLB_LUPD_bit(const void *const hw) +{ + return (((Pdec *)hw)->CTRLBSET.reg & PDEC_CTRLBSET_LUPD) >> PDEC_CTRLBSET_LUPD_Pos; +} + +static inline void hri_pdec_write_CTRLB_LUPD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pdec *)hw)->CTRLBCLR.reg = PDEC_CTRLBSET_LUPD; + } else { + ((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_LUPD; + } +} + +static inline void hri_pdec_clear_CTRLB_LUPD_bit(const void *const hw) +{ + ((Pdec *)hw)->CTRLBCLR.reg = PDEC_CTRLBSET_LUPD; +} + +static inline void hri_pdec_set_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t mask) +{ + ((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_CMD(mask); +} + +static inline hri_pdec_ctrlbset_reg_t hri_pdec_get_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->CTRLBSET.reg; + tmp = (tmp & PDEC_CTRLBSET_CMD(mask)) >> PDEC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline hri_pdec_ctrlbset_reg_t hri_pdec_read_CTRLB_CMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->CTRLBSET.reg; + tmp = (tmp & PDEC_CTRLBSET_CMD_Msk) >> PDEC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline void hri_pdec_write_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t data) +{ + ((Pdec *)hw)->CTRLBSET.reg = PDEC_CTRLBSET_CMD(data); + ((Pdec *)hw)->CTRLBCLR.reg = ~PDEC_CTRLBSET_CMD(data); +} + +static inline void hri_pdec_clear_CTRLB_CMD_bf(const void *const hw, hri_pdec_ctrlbset_reg_t mask) +{ + ((Pdec *)hw)->CTRLBCLR.reg = PDEC_CTRLBSET_CMD(mask); +} + +static inline void hri_pdec_set_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t mask) +{ + ((Pdec *)hw)->CTRLBSET.reg = mask; +} + +static inline hri_pdec_ctrlbset_reg_t hri_pdec_get_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->CTRLBSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pdec_ctrlbset_reg_t hri_pdec_read_CTRLB_reg(const void *const hw) +{ + return ((Pdec *)hw)->CTRLBSET.reg; +} + +static inline void hri_pdec_write_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t data) +{ + ((Pdec *)hw)->CTRLBSET.reg = data; + ((Pdec *)hw)->CTRLBCLR.reg = ~data; +} + +static inline void hri_pdec_clear_CTRLB_reg(const void *const hw, hri_pdec_ctrlbset_reg_t mask) +{ + ((Pdec *)hw)->CTRLBCLR.reg = mask; +} + +static inline void hri_pdec_set_INTEN_OVF_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_OVF; +} + +static inline bool hri_pdec_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_OVF) >> PDEC_INTENSET_OVF_Pos; +} + +static inline void hri_pdec_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_OVF; + } else { + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_OVF; + } +} + +static inline void hri_pdec_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_OVF; +} + +static inline void hri_pdec_set_INTEN_ERR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_ERR; +} + +static inline bool hri_pdec_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_ERR) >> PDEC_INTENSET_ERR_Pos; +} + +static inline void hri_pdec_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_ERR; + } else { + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_ERR; + } +} + +static inline void hri_pdec_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_ERR; +} + +static inline void hri_pdec_set_INTEN_DIR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_DIR; +} + +static inline bool hri_pdec_get_INTEN_DIR_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_DIR) >> PDEC_INTENSET_DIR_Pos; +} + +static inline void hri_pdec_write_INTEN_DIR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_DIR; + } else { + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_DIR; + } +} + +static inline void hri_pdec_clear_INTEN_DIR_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_DIR; +} + +static inline void hri_pdec_set_INTEN_VLC_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_VLC; +} + +static inline bool hri_pdec_get_INTEN_VLC_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_VLC) >> PDEC_INTENSET_VLC_Pos; +} + +static inline void hri_pdec_write_INTEN_VLC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_VLC; + } else { + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_VLC; + } +} + +static inline void hri_pdec_clear_INTEN_VLC_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_VLC; +} + +static inline void hri_pdec_set_INTEN_MC0_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC0; +} + +static inline bool hri_pdec_get_INTEN_MC0_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_MC0) >> PDEC_INTENSET_MC0_Pos; +} + +static inline void hri_pdec_write_INTEN_MC0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC0; + } else { + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC0; + } +} + +static inline void hri_pdec_clear_INTEN_MC0_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC0; +} + +static inline void hri_pdec_set_INTEN_MC1_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC1; +} + +static inline bool hri_pdec_get_INTEN_MC1_bit(const void *const hw) +{ + return (((Pdec *)hw)->INTENSET.reg & PDEC_INTENSET_MC1) >> PDEC_INTENSET_MC1_Pos; +} + +static inline void hri_pdec_write_INTEN_MC1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC1; + } else { + ((Pdec *)hw)->INTENSET.reg = PDEC_INTENSET_MC1; + } +} + +static inline void hri_pdec_clear_INTEN_MC1_bit(const void *const hw) +{ + ((Pdec *)hw)->INTENCLR.reg = PDEC_INTENSET_MC1; +} + +static inline void hri_pdec_set_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t mask) +{ + ((Pdec *)hw)->INTENSET.reg = mask; +} + +static inline hri_pdec_intenset_reg_t hri_pdec_get_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pdec_intenset_reg_t hri_pdec_read_INTEN_reg(const void *const hw) +{ + return ((Pdec *)hw)->INTENSET.reg; +} + +static inline void hri_pdec_write_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t data) +{ + ((Pdec *)hw)->INTENSET.reg = data; + ((Pdec *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_pdec_clear_INTEN_reg(const void *const hw, hri_pdec_intenset_reg_t mask) +{ + ((Pdec *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_pdec_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_SWRST) >> PDEC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_ENABLE) >> PDEC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_CTRLB) >> PDEC_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_STATUS_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_STATUS) >> PDEC_SYNCBUSY_STATUS_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_PRESC_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_PRESC) >> PDEC_SYNCBUSY_PRESC_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_FILTER_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_FILTER) >> PDEC_SYNCBUSY_FILTER_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_COUNT) >> PDEC_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_CC0_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_CC0) >> PDEC_SYNCBUSY_CC0_Pos; +} + +static inline bool hri_pdec_get_SYNCBUSY_CC1_bit(const void *const hw) +{ + return (((Pdec *)hw)->SYNCBUSY.reg & PDEC_SYNCBUSY_CC1) >> PDEC_SYNCBUSY_CC1_Pos; +} + +static inline hri_pdec_syncbusy_reg_t hri_pdec_get_SYNCBUSY_reg(const void *const hw, hri_pdec_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pdec_syncbusy_reg_t hri_pdec_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Pdec *)hw)->SYNCBUSY.reg; +} + +static inline void hri_pdec_set_CTRLA_SWRST_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_SWRST; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_SWRST) >> PDEC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_set_CTRLA_ENABLE_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_ENABLE; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_ENABLE) >> PDEC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_ENABLE; + tmp |= value << PDEC_CTRLA_ENABLE_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ENABLE; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_ENABLE; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_RUNSTDBY; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_RUNSTDBY) >> PDEC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_RUNSTDBY; + tmp |= value << PDEC_CTRLA_RUNSTDBY_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_RUNSTDBY; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_RUNSTDBY; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_ALOCK_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_ALOCK; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_ALOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_ALOCK) >> PDEC_CTRLA_ALOCK_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_ALOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_ALOCK; + tmp |= value << PDEC_CTRLA_ALOCK_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_ALOCK_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ALOCK; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_ALOCK_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_ALOCK; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_SWAP_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_SWAP; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_SWAP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_SWAP) >> PDEC_CTRLA_SWAP_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_SWAP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_SWAP; + tmp |= value << PDEC_CTRLA_SWAP_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_SWAP_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_SWAP; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_SWAP_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_SWAP; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_PEREN_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PEREN; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_PEREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_PEREN) >> PDEC_CTRLA_PEREN_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_PEREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_PEREN; + tmp |= value << PDEC_CTRLA_PEREN_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_PEREN_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PEREN; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_PEREN_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PEREN; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_PINEN0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINEN0; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_PINEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_PINEN0) >> PDEC_CTRLA_PINEN0_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_PINEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_PINEN0; + tmp |= value << PDEC_CTRLA_PINEN0_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_PINEN0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINEN0; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_PINEN0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINEN0; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_PINEN1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINEN1; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_PINEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_PINEN1) >> PDEC_CTRLA_PINEN1_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_PINEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_PINEN1; + tmp |= value << PDEC_CTRLA_PINEN1_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_PINEN1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINEN1; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_PINEN1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINEN1; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_PINEN2_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINEN2; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_PINEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_PINEN2) >> PDEC_CTRLA_PINEN2_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_PINEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_PINEN2; + tmp |= value << PDEC_CTRLA_PINEN2_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_PINEN2_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINEN2; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_PINEN2_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINEN2; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_PINVEN0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINVEN0; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_PINVEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_PINVEN0) >> PDEC_CTRLA_PINVEN0_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_PINVEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_PINVEN0; + tmp |= value << PDEC_CTRLA_PINVEN0_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_PINVEN0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINVEN0; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_PINVEN0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINVEN0; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_PINVEN1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINVEN1; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_PINVEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_PINVEN1) >> PDEC_CTRLA_PINVEN1_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_PINVEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_PINVEN1; + tmp |= value << PDEC_CTRLA_PINVEN1_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_PINVEN1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINVEN1; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_PINVEN1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINVEN1; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_PINVEN2_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_PINVEN2; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_CTRLA_PINVEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_PINVEN2) >> PDEC_CTRLA_PINVEN2_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_CTRLA_PINVEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_PINVEN2; + tmp |= value << PDEC_CTRLA_PINVEN2_Pos; + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_PINVEN2_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_PINVEN2; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_PINVEN2_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_PINVEN2; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_MODE(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_MODE(mask)) >> PDEC_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_pdec_write_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t data) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_MODE_Msk; + tmp |= PDEC_CTRLA_MODE(data); + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_MODE(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_MODE_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_MODE(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_MODE_Msk) >> PDEC_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_pdec_set_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_CONF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_CONF(mask)) >> PDEC_CTRLA_CONF_Pos; + return tmp; +} + +static inline void hri_pdec_write_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t data) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_CONF_Msk; + tmp |= PDEC_CTRLA_CONF(data); + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_CONF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_CONF_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_CONF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_CONF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_CONF_Msk) >> PDEC_CTRLA_CONF_Pos; + return tmp; +} + +static inline void hri_pdec_set_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_ANGULAR(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_ANGULAR(mask)) >> PDEC_CTRLA_ANGULAR_Pos; + return tmp; +} + +static inline void hri_pdec_write_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t data) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_ANGULAR_Msk; + tmp |= PDEC_CTRLA_ANGULAR(data); + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_ANGULAR(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_ANGULAR_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_ANGULAR(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_ANGULAR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_ANGULAR_Msk) >> PDEC_CTRLA_ANGULAR_Pos; + return tmp; +} + +static inline void hri_pdec_set_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= PDEC_CTRLA_MAXCMP(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_MAXCMP(mask)) >> PDEC_CTRLA_MAXCMP_Pos; + return tmp; +} + +static inline void hri_pdec_write_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t data) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= ~PDEC_CTRLA_MAXCMP_Msk; + tmp |= PDEC_CTRLA_MAXCMP(data); + ((Pdec *)hw)->CTRLA.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~PDEC_CTRLA_MAXCMP(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_MAXCMP_bf(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= PDEC_CTRLA_MAXCMP(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_MAXCMP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp = (tmp & PDEC_CTRLA_MAXCMP_Msk) >> PDEC_CTRLA_MAXCMP_Pos; + return tmp; +} + +static inline void hri_pdec_set_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg |= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_get_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + tmp = ((Pdec *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg = data; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg &= ~mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CTRLA_reg(const void *const hw, hri_pdec_ctrla_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CTRLA.reg ^= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ctrla_reg_t hri_pdec_read_CTRLA_reg(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_SWRST | PDEC_SYNCBUSY_ENABLE); + return ((Pdec *)hw)->CTRLA.reg; +} + +static inline void hri_pdec_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_OVFEO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_OVFEO) >> PDEC_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_OVFEO; + tmp |= value << PDEC_EVCTRL_OVFEO_Pos; + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_OVFEO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_OVFEO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_EVCTRL_ERREO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_ERREO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_EVCTRL_ERREO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_ERREO) >> PDEC_EVCTRL_ERREO_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_EVCTRL_ERREO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_ERREO; + tmp |= value << PDEC_EVCTRL_ERREO_Pos; + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_ERREO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_ERREO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_ERREO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_ERREO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_EVCTRL_DIREO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_DIREO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_EVCTRL_DIREO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_DIREO) >> PDEC_EVCTRL_DIREO_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_EVCTRL_DIREO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_DIREO; + tmp |= value << PDEC_EVCTRL_DIREO_Pos; + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_DIREO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_DIREO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_DIREO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_DIREO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_EVCTRL_VLCEO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_VLCEO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_EVCTRL_VLCEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_VLCEO) >> PDEC_EVCTRL_VLCEO_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_EVCTRL_VLCEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_VLCEO; + tmp |= value << PDEC_EVCTRL_VLCEO_Pos; + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_VLCEO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_VLCEO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_VLCEO_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_VLCEO; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_EVCTRL_MCEO0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_MCEO0; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_EVCTRL_MCEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_MCEO0) >> PDEC_EVCTRL_MCEO0_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_MCEO0; + tmp |= value << PDEC_EVCTRL_MCEO0_Pos; + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_MCEO0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_MCEO0; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_MCEO0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_MCEO0; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_EVCTRL_MCEO1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_MCEO1; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_EVCTRL_MCEO1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_MCEO1) >> PDEC_EVCTRL_MCEO1_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_MCEO1; + tmp |= value << PDEC_EVCTRL_MCEO1_Pos; + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_MCEO1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_MCEO1; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_MCEO1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_MCEO1; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_EVACT(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_EVACT(mask)) >> PDEC_EVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_pdec_write_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t data) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_EVACT_Msk; + tmp |= PDEC_EVCTRL_EVACT(data); + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_EVACT(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_EVACT_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_EVACT(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_EVACT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_EVACT_Msk) >> PDEC_EVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_pdec_set_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_EVINV(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_EVINV(mask)) >> PDEC_EVCTRL_EVINV_Pos; + return tmp; +} + +static inline void hri_pdec_write_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t data) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_EVINV_Msk; + tmp |= PDEC_EVCTRL_EVINV(data); + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_EVINV(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_EVINV_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_EVINV(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_EVINV_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_EVINV_Msk) >> PDEC_EVCTRL_EVINV_Pos; + return tmp; +} + +static inline void hri_pdec_set_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= PDEC_EVCTRL_EVEI(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_EVEI(mask)) >> PDEC_EVCTRL_EVEI_Pos; + return tmp; +} + +static inline void hri_pdec_write_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t data) +{ + uint16_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= ~PDEC_EVCTRL_EVEI_Msk; + tmp |= PDEC_EVCTRL_EVEI(data); + ((Pdec *)hw)->EVCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~PDEC_EVCTRL_EVEI(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_EVEI_bf(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= PDEC_EVCTRL_EVEI(mask); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_EVEI_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp = (tmp & PDEC_EVCTRL_EVEI_Msk) >> PDEC_EVCTRL_EVEI_Pos; + return tmp; +} + +static inline void hri_pdec_set_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg |= mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_get_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Pdec *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg = data; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg &= ~mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_EVCTRL_reg(const void *const hw, hri_pdec_evctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->EVCTRL.reg ^= mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_evctrl_reg_t hri_pdec_read_EVCTRL_reg(const void *const hw) +{ + return ((Pdec *)hw)->EVCTRL.reg; +} + +static inline void hri_pdec_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->DBGCTRL.reg |= PDEC_DBGCTRL_DBGRUN; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->DBGCTRL.reg; + tmp = (tmp & PDEC_DBGCTRL_DBGRUN) >> PDEC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_pdec_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->DBGCTRL.reg; + tmp &= ~PDEC_DBGCTRL_DBGRUN; + tmp |= value << PDEC_DBGCTRL_DBGRUN_Pos; + ((Pdec *)hw)->DBGCTRL.reg = tmp; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->DBGCTRL.reg &= ~PDEC_DBGCTRL_DBGRUN; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->DBGCTRL.reg ^= PDEC_DBGCTRL_DBGRUN; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_set_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->DBGCTRL.reg |= mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_dbgctrl_reg_t hri_pdec_get_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->DBGCTRL.reg = data; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->DBGCTRL.reg &= ~mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_DBGCTRL_reg(const void *const hw, hri_pdec_dbgctrl_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->DBGCTRL.reg ^= mask; + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_dbgctrl_reg_t hri_pdec_read_DBGCTRL_reg(const void *const hw) +{ + return ((Pdec *)hw)->DBGCTRL.reg; +} + +static inline void hri_pdec_set_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESC.reg |= PDEC_PRESC_PRESC(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_presc_reg_t hri_pdec_get_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask) +{ + uint8_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + tmp = ((Pdec *)hw)->PRESC.reg; + tmp = (tmp & PDEC_PRESC_PRESC(mask)) >> PDEC_PRESC_PRESC_Pos; + return tmp; +} + +static inline void hri_pdec_write_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t data) +{ + uint8_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->PRESC.reg; + tmp &= ~PDEC_PRESC_PRESC_Msk; + tmp |= PDEC_PRESC_PRESC(data); + ((Pdec *)hw)->PRESC.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESC.reg &= ~PDEC_PRESC_PRESC(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_PRESC_PRESC_bf(const void *const hw, hri_pdec_presc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESC.reg ^= PDEC_PRESC_PRESC(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_presc_reg_t hri_pdec_read_PRESC_PRESC_bf(const void *const hw) +{ + uint8_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + tmp = ((Pdec *)hw)->PRESC.reg; + tmp = (tmp & PDEC_PRESC_PRESC_Msk) >> PDEC_PRESC_PRESC_Pos; + return tmp; +} + +static inline void hri_pdec_set_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESC.reg |= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_presc_reg_t hri_pdec_get_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask) +{ + uint8_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + tmp = ((Pdec *)hw)->PRESC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESC.reg = data; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESC.reg &= ~mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_PRESC_reg(const void *const hw, hri_pdec_presc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESC.reg ^= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_presc_reg_t hri_pdec_read_PRESC_reg(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_PRESC); + return ((Pdec *)hw)->PRESC.reg; +} + +static inline void hri_pdec_set_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTER.reg |= PDEC_FILTER_FILTER(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filter_reg_t hri_pdec_get_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask) +{ + uint8_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + tmp = ((Pdec *)hw)->FILTER.reg; + tmp = (tmp & PDEC_FILTER_FILTER(mask)) >> PDEC_FILTER_FILTER_Pos; + return tmp; +} + +static inline void hri_pdec_write_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t data) +{ + uint8_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->FILTER.reg; + tmp &= ~PDEC_FILTER_FILTER_Msk; + tmp |= PDEC_FILTER_FILTER(data); + ((Pdec *)hw)->FILTER.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTER.reg &= ~PDEC_FILTER_FILTER(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_FILTER_FILTER_bf(const void *const hw, hri_pdec_filter_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTER.reg ^= PDEC_FILTER_FILTER(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filter_reg_t hri_pdec_read_FILTER_FILTER_bf(const void *const hw) +{ + uint8_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + tmp = ((Pdec *)hw)->FILTER.reg; + tmp = (tmp & PDEC_FILTER_FILTER_Msk) >> PDEC_FILTER_FILTER_Pos; + return tmp; +} + +static inline void hri_pdec_set_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTER.reg |= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filter_reg_t hri_pdec_get_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask) +{ + uint8_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + tmp = ((Pdec *)hw)->FILTER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTER.reg = data; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTER.reg &= ~mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_FILTER_reg(const void *const hw, hri_pdec_filter_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTER.reg ^= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filter_reg_t hri_pdec_read_FILTER_reg(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_FILTER); + return ((Pdec *)hw)->FILTER.reg; +} + +static inline void hri_pdec_set_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESCBUF.reg |= PDEC_PRESCBUF_PRESCBUF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_prescbuf_reg_t hri_pdec_get_PRESCBUF_PRESCBUF_bf(const void *const hw, + hri_pdec_prescbuf_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->PRESCBUF.reg; + tmp = (tmp & PDEC_PRESCBUF_PRESCBUF(mask)) >> PDEC_PRESCBUF_PRESCBUF_Pos; + return tmp; +} + +static inline void hri_pdec_write_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t data) +{ + uint8_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->PRESCBUF.reg; + tmp &= ~PDEC_PRESCBUF_PRESCBUF_Msk; + tmp |= PDEC_PRESCBUF_PRESCBUF(data); + ((Pdec *)hw)->PRESCBUF.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESCBUF.reg &= ~PDEC_PRESCBUF_PRESCBUF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_PRESCBUF_PRESCBUF_bf(const void *const hw, hri_pdec_prescbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESCBUF.reg ^= PDEC_PRESCBUF_PRESCBUF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_prescbuf_reg_t hri_pdec_read_PRESCBUF_PRESCBUF_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->PRESCBUF.reg; + tmp = (tmp & PDEC_PRESCBUF_PRESCBUF_Msk) >> PDEC_PRESCBUF_PRESCBUF_Pos; + return tmp; +} + +static inline void hri_pdec_set_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESCBUF.reg |= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_prescbuf_reg_t hri_pdec_get_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask) +{ + uint8_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + tmp = ((Pdec *)hw)->PRESCBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESCBUF.reg = data; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESCBUF.reg &= ~mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_PRESCBUF_reg(const void *const hw, hri_pdec_prescbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->PRESCBUF.reg ^= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_prescbuf_reg_t hri_pdec_read_PRESCBUF_reg(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return ((Pdec *)hw)->PRESCBUF.reg; +} + +static inline void hri_pdec_set_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTERBUF.reg |= PDEC_FILTERBUF_FILTERBUF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filterbuf_reg_t hri_pdec_get_FILTERBUF_FILTERBUF_bf(const void *const hw, + hri_pdec_filterbuf_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->FILTERBUF.reg; + tmp = (tmp & PDEC_FILTERBUF_FILTERBUF(mask)) >> PDEC_FILTERBUF_FILTERBUF_Pos; + return tmp; +} + +static inline void hri_pdec_write_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t data) +{ + uint8_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->FILTERBUF.reg; + tmp &= ~PDEC_FILTERBUF_FILTERBUF_Msk; + tmp |= PDEC_FILTERBUF_FILTERBUF(data); + ((Pdec *)hw)->FILTERBUF.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTERBUF.reg &= ~PDEC_FILTERBUF_FILTERBUF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_FILTERBUF_FILTERBUF_bf(const void *const hw, hri_pdec_filterbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTERBUF.reg ^= PDEC_FILTERBUF_FILTERBUF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filterbuf_reg_t hri_pdec_read_FILTERBUF_FILTERBUF_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pdec *)hw)->FILTERBUF.reg; + tmp = (tmp & PDEC_FILTERBUF_FILTERBUF_Msk) >> PDEC_FILTERBUF_FILTERBUF_Pos; + return tmp; +} + +static inline void hri_pdec_set_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTERBUF.reg |= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filterbuf_reg_t hri_pdec_get_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask) +{ + uint8_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + tmp = ((Pdec *)hw)->FILTERBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTERBUF.reg = data; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTERBUF.reg &= ~mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_FILTERBUF_reg(const void *const hw, hri_pdec_filterbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->FILTERBUF.reg ^= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_filterbuf_reg_t hri_pdec_read_FILTERBUF_reg(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return ((Pdec *)hw)->FILTERBUF.reg; +} + +static inline void hri_pdec_set_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->COUNT.reg |= PDEC_COUNT_COUNT(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_count_reg_t hri_pdec_get_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + tmp = ((Pdec *)hw)->COUNT.reg; + tmp = (tmp & PDEC_COUNT_COUNT(mask)) >> PDEC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_pdec_write_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t data) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->COUNT.reg; + tmp &= ~PDEC_COUNT_COUNT_Msk; + tmp |= PDEC_COUNT_COUNT(data); + ((Pdec *)hw)->COUNT.reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->COUNT.reg &= ~PDEC_COUNT_COUNT(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_COUNT_COUNT_bf(const void *const hw, hri_pdec_count_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->COUNT.reg ^= PDEC_COUNT_COUNT(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_count_reg_t hri_pdec_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + tmp = ((Pdec *)hw)->COUNT.reg; + tmp = (tmp & PDEC_COUNT_COUNT_Msk) >> PDEC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_pdec_set_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->COUNT.reg |= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_count_reg_t hri_pdec_get_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + tmp = ((Pdec *)hw)->COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_COUNT_reg(const void *const hw, hri_pdec_count_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->COUNT.reg = data; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->COUNT.reg &= ~mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_COUNT_reg(const void *const hw, hri_pdec_count_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->COUNT.reg ^= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_count_reg_t hri_pdec_read_COUNT_reg(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_COUNT); + return ((Pdec *)hw)->COUNT.reg; +} + +static inline void hri_pdec_set_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CC[index].reg |= PDEC_CC_CC(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_cc_reg_t hri_pdec_get_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + tmp = ((Pdec *)hw)->CC[index].reg; + tmp = (tmp & PDEC_CC_CC(mask)) >> PDEC_CC_CC_Pos; + return tmp; +} + +static inline void hri_pdec_write_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t data) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CC[index].reg; + tmp &= ~PDEC_CC_CC_Msk; + tmp |= PDEC_CC_CC(data); + ((Pdec *)hw)->CC[index].reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CC[index].reg &= ~PDEC_CC_CC(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CC[index].reg ^= PDEC_CC_CC(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_cc_reg_t hri_pdec_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + tmp = ((Pdec *)hw)->CC[index].reg; + tmp = (tmp & PDEC_CC_CC_Msk) >> PDEC_CC_CC_Pos; + return tmp; +} + +static inline void hri_pdec_set_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CC[index].reg |= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_cc_reg_t hri_pdec_get_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + tmp = ((Pdec *)hw)->CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CC[index].reg = data; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CC[index].reg &= ~mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CC_reg(const void *const hw, uint8_t index, hri_pdec_cc_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CC[index].reg ^= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_cc_reg_t hri_pdec_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_CC0 | PDEC_SYNCBUSY_CC1); + return ((Pdec *)hw)->CC[index].reg; +} + +static inline void hri_pdec_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CCBUF[index].reg |= PDEC_CCBUF_CCBUF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ccbuf_reg_t hri_pdec_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_pdec_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CCBUF[index].reg; + tmp = (tmp & PDEC_CCBUF_CCBUF(mask)) >> PDEC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_pdec_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t data) +{ + uint32_t tmp; + PDEC_CRITICAL_SECTION_ENTER(); + tmp = ((Pdec *)hw)->CCBUF[index].reg; + tmp &= ~PDEC_CCBUF_CCBUF_Msk; + tmp |= PDEC_CCBUF_CCBUF(data); + ((Pdec *)hw)->CCBUF[index].reg = tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CCBUF[index].reg &= ~PDEC_CCBUF_CCBUF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CCBUF[index].reg ^= PDEC_CCBUF_CCBUF(mask); + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ccbuf_reg_t hri_pdec_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Pdec *)hw)->CCBUF[index].reg; + tmp = (tmp & PDEC_CCBUF_CCBUF_Msk) >> PDEC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_pdec_set_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CCBUF[index].reg |= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ccbuf_reg_t hri_pdec_get_CCBUF_reg(const void *const hw, uint8_t index, + hri_pdec_ccbuf_reg_t mask) +{ + uint32_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + tmp = ((Pdec *)hw)->CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_write_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t data) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CCBUF[index].reg = data; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CCBUF[index].reg &= ~mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pdec_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_pdec_ccbuf_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->CCBUF[index].reg ^= mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_ccbuf_reg_t hri_pdec_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return ((Pdec *)hw)->CCBUF[index].reg; +} + +static inline bool hri_pdec_get_STATUS_QERR_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_QERR) >> PDEC_STATUS_QERR_Pos; +} + +static inline void hri_pdec_clear_STATUS_QERR_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_QERR; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_IDXERR_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_IDXERR) >> PDEC_STATUS_IDXERR_Pos; +} + +static inline void hri_pdec_clear_STATUS_IDXERR_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_IDXERR; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_MPERR_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_MPERR) >> PDEC_STATUS_MPERR_Pos; +} + +static inline void hri_pdec_clear_STATUS_MPERR_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_MPERR; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_WINERR_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_WINERR) >> PDEC_STATUS_WINERR_Pos; +} + +static inline void hri_pdec_clear_STATUS_WINERR_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_WINERR; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_HERR_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_HERR) >> PDEC_STATUS_HERR_Pos; +} + +static inline void hri_pdec_clear_STATUS_HERR_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_HERR; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_STOP_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_STOP) >> PDEC_STATUS_STOP_Pos; +} + +static inline void hri_pdec_clear_STATUS_STOP_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_STOP; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_DIR_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_DIR) >> PDEC_STATUS_DIR_Pos; +} + +static inline void hri_pdec_clear_STATUS_DIR_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_DIR; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_PRESCBUFV_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_PRESCBUFV) >> PDEC_STATUS_PRESCBUFV_Pos; +} + +static inline void hri_pdec_clear_STATUS_PRESCBUFV_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_PRESCBUFV; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_FILTERBUFV_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_FILTERBUFV) >> PDEC_STATUS_FILTERBUFV_Pos; +} + +static inline void hri_pdec_clear_STATUS_FILTERBUFV_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_FILTERBUFV; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_CCBUFV0_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_CCBUFV0) >> PDEC_STATUS_CCBUFV0_Pos; +} + +static inline void hri_pdec_clear_STATUS_CCBUFV0_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_CCBUFV0; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pdec_get_STATUS_CCBUFV1_bit(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return (((Pdec *)hw)->STATUS.reg & PDEC_STATUS_CCBUFV1) >> PDEC_STATUS_CCBUFV1_Pos; +} + +static inline void hri_pdec_clear_STATUS_CCBUFV1_bit(const void *const hw) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = PDEC_STATUS_CCBUFV1; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_status_reg_t hri_pdec_get_STATUS_reg(const void *const hw, hri_pdec_status_reg_t mask) +{ + uint16_t tmp; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + tmp = ((Pdec *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pdec_clear_STATUS_reg(const void *const hw, hri_pdec_status_reg_t mask) +{ + PDEC_CRITICAL_SECTION_ENTER(); + ((Pdec *)hw)->STATUS.reg = mask; + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + PDEC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pdec_status_reg_t hri_pdec_read_STATUS_reg(const void *const hw) +{ + hri_pdec_wait_for_sync(hw, PDEC_SYNCBUSY_MASK); + return ((Pdec *)hw)->STATUS.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PDEC_E54_H_INCLUDED */ +#endif /* _SAME54_PDEC_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_pm_e54.h b/software/firmware/oracle_same54n19a/hri/hri_pm_e54.h new file mode 100644 index 00000000..0b91beef --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_pm_e54.h @@ -0,0 +1,820 @@ +/** + * \file + * + * \brief SAM PM + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_PM_COMPONENT_ +#ifndef _HRI_PM_E54_H_INCLUDED_ +#define _HRI_PM_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PM_CRITICAL_SECTIONS) +#define PM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PM_CRITICAL_SECTION_ENTER() +#define PM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint8_t hri_pm_bkupcfg_reg_t; +typedef uint8_t hri_pm_ctrla_reg_t; +typedef uint8_t hri_pm_hibcfg_reg_t; +typedef uint8_t hri_pm_intenset_reg_t; +typedef uint8_t hri_pm_intflag_reg_t; +typedef uint8_t hri_pm_pwsakdly_reg_t; +typedef uint8_t hri_pm_sleepcfg_reg_t; +typedef uint8_t hri_pm_stdbycfg_reg_t; + +static inline bool hri_pm_get_INTFLAG_SLEEPRDY_bit(const void *const hw) +{ + return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_SLEEPRDY) >> PM_INTFLAG_SLEEPRDY_Pos; +} + +static inline void hri_pm_clear_INTFLAG_SLEEPRDY_bit(const void *const hw) +{ + ((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_SLEEPRDY; +} + +static inline bool hri_pm_get_interrupt_SLEEPRDY_bit(const void *const hw) +{ + return (((Pm *)hw)->INTFLAG.reg & PM_INTFLAG_SLEEPRDY) >> PM_INTFLAG_SLEEPRDY_Pos; +} + +static inline void hri_pm_clear_interrupt_SLEEPRDY_bit(const void *const hw) +{ + ((Pm *)hw)->INTFLAG.reg = PM_INTFLAG_SLEEPRDY; +} + +static inline hri_pm_intflag_reg_t hri_pm_get_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pm_intflag_reg_t hri_pm_read_INTFLAG_reg(const void *const hw) +{ + return ((Pm *)hw)->INTFLAG.reg; +} + +static inline void hri_pm_clear_INTFLAG_reg(const void *const hw, hri_pm_intflag_reg_t mask) +{ + ((Pm *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_pm_set_INTEN_SLEEPRDY_bit(const void *const hw) +{ + ((Pm *)hw)->INTENSET.reg = PM_INTENSET_SLEEPRDY; +} + +static inline bool hri_pm_get_INTEN_SLEEPRDY_bit(const void *const hw) +{ + return (((Pm *)hw)->INTENSET.reg & PM_INTENSET_SLEEPRDY) >> PM_INTENSET_SLEEPRDY_Pos; +} + +static inline void hri_pm_write_INTEN_SLEEPRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_SLEEPRDY; + } else { + ((Pm *)hw)->INTENSET.reg = PM_INTENSET_SLEEPRDY; + } +} + +static inline void hri_pm_clear_INTEN_SLEEPRDY_bit(const void *const hw) +{ + ((Pm *)hw)->INTENCLR.reg = PM_INTENSET_SLEEPRDY; +} + +static inline void hri_pm_set_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) +{ + ((Pm *)hw)->INTENSET.reg = mask; +} + +static inline hri_pm_intenset_reg_t hri_pm_get_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_pm_intenset_reg_t hri_pm_read_INTEN_reg(const void *const hw) +{ + return ((Pm *)hw)->INTENSET.reg; +} + +static inline void hri_pm_write_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t data) +{ + ((Pm *)hw)->INTENSET.reg = data; + ((Pm *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_pm_clear_INTEN_reg(const void *const hw, hri_pm_intenset_reg_t mask) +{ + ((Pm *)hw)->INTENCLR.reg = mask; +} + +static inline void hri_pm_set_CTRLA_IORET_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg |= PM_CTRLA_IORET; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_CTRLA_IORET_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->CTRLA.reg; + tmp = (tmp & PM_CTRLA_IORET) >> PM_CTRLA_IORET_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_CTRLA_IORET_bit(const void *const hw, bool value) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->CTRLA.reg; + tmp &= ~PM_CTRLA_IORET; + tmp |= value << PM_CTRLA_IORET_Pos; + ((Pm *)hw)->CTRLA.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_CTRLA_IORET_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg &= ~PM_CTRLA_IORET; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_CTRLA_IORET_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg ^= PM_CTRLA_IORET; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_ctrla_reg_t hri_pm_get_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_CTRLA_reg(const void *const hw, hri_pm_ctrla_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->CTRLA.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_ctrla_reg_t hri_pm_read_CTRLA_reg(const void *const hw) +{ + return ((Pm *)hw)->CTRLA.reg; +} + +static inline void hri_pm_set_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg |= PM_SLEEPCFG_SLEEPMODE(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp = (tmp & PM_SLEEPCFG_SLEEPMODE(mask)) >> PM_SLEEPCFG_SLEEPMODE_Pos; + return tmp; +} + +static inline void hri_pm_write_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp &= ~PM_SLEEPCFG_SLEEPMODE_Msk; + tmp |= PM_SLEEPCFG_SLEEPMODE(data); + ((Pm *)hw)->SLEEPCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg &= ~PM_SLEEPCFG_SLEEPMODE(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_SLEEPCFG_SLEEPMODE_bf(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg ^= PM_SLEEPCFG_SLEEPMODE(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_SLEEPMODE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp = (tmp & PM_SLEEPCFG_SLEEPMODE_Msk) >> PM_SLEEPCFG_SLEEPMODE_Pos; + return tmp; +} + +static inline void hri_pm_set_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_get_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->SLEEPCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_SLEEPCFG_reg(const void *const hw, hri_pm_sleepcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->SLEEPCFG.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_sleepcfg_reg_t hri_pm_read_SLEEPCFG_reg(const void *const hw) +{ + return ((Pm *)hw)->SLEEPCFG.reg; +} + +static inline void hri_pm_set_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_RAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_RAMCFG(mask)) >> PM_STDBYCFG_RAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_write_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= ~PM_STDBYCFG_RAMCFG_Msk; + tmp |= PM_STDBYCFG_RAMCFG(data); + ((Pm *)hw)->STDBYCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_RAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_RAMCFG_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_RAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_RAMCFG_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_RAMCFG_Msk) >> PM_STDBYCFG_RAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_set_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= PM_STDBYCFG_FASTWKUP(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_FASTWKUP(mask)) >> PM_STDBYCFG_FASTWKUP_Pos; + return tmp; +} + +static inline void hri_pm_write_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= ~PM_STDBYCFG_FASTWKUP_Msk; + tmp |= PM_STDBYCFG_FASTWKUP(data); + ((Pm *)hw)->STDBYCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~PM_STDBYCFG_FASTWKUP(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_FASTWKUP_bf(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= PM_STDBYCFG_FASTWKUP(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_FASTWKUP_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp = (tmp & PM_STDBYCFG_FASTWKUP_Msk) >> PM_STDBYCFG_FASTWKUP_Pos; + return tmp; +} + +static inline void hri_pm_set_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_get_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->STDBYCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_STDBYCFG_reg(const void *const hw, hri_pm_stdbycfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->STDBYCFG.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_stdbycfg_reg_t hri_pm_read_STDBYCFG_reg(const void *const hw) +{ + return ((Pm *)hw)->STDBYCFG.reg; +} + +static inline void hri_pm_set_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg |= PM_HIBCFG_RAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_hibcfg_reg_t hri_pm_get_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->HIBCFG.reg; + tmp = (tmp & PM_HIBCFG_RAMCFG(mask)) >> PM_HIBCFG_RAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_write_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->HIBCFG.reg; + tmp &= ~PM_HIBCFG_RAMCFG_Msk; + tmp |= PM_HIBCFG_RAMCFG(data); + ((Pm *)hw)->HIBCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg &= ~PM_HIBCFG_RAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_HIBCFG_RAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg ^= PM_HIBCFG_RAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_hibcfg_reg_t hri_pm_read_HIBCFG_RAMCFG_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->HIBCFG.reg; + tmp = (tmp & PM_HIBCFG_RAMCFG_Msk) >> PM_HIBCFG_RAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_set_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg |= PM_HIBCFG_BRAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_hibcfg_reg_t hri_pm_get_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->HIBCFG.reg; + tmp = (tmp & PM_HIBCFG_BRAMCFG(mask)) >> PM_HIBCFG_BRAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_write_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->HIBCFG.reg; + tmp &= ~PM_HIBCFG_BRAMCFG_Msk; + tmp |= PM_HIBCFG_BRAMCFG(data); + ((Pm *)hw)->HIBCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg &= ~PM_HIBCFG_BRAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_HIBCFG_BRAMCFG_bf(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg ^= PM_HIBCFG_BRAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_hibcfg_reg_t hri_pm_read_HIBCFG_BRAMCFG_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->HIBCFG.reg; + tmp = (tmp & PM_HIBCFG_BRAMCFG_Msk) >> PM_HIBCFG_BRAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_set_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_hibcfg_reg_t hri_pm_get_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->HIBCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_HIBCFG_reg(const void *const hw, hri_pm_hibcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->HIBCFG.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_hibcfg_reg_t hri_pm_read_HIBCFG_reg(const void *const hw) +{ + return ((Pm *)hw)->HIBCFG.reg; +} + +static inline void hri_pm_set_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->BKUPCFG.reg |= PM_BKUPCFG_BRAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_bkupcfg_reg_t hri_pm_get_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->BKUPCFG.reg; + tmp = (tmp & PM_BKUPCFG_BRAMCFG(mask)) >> PM_BKUPCFG_BRAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_write_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->BKUPCFG.reg; + tmp &= ~PM_BKUPCFG_BRAMCFG_Msk; + tmp |= PM_BKUPCFG_BRAMCFG(data); + ((Pm *)hw)->BKUPCFG.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->BKUPCFG.reg &= ~PM_BKUPCFG_BRAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_BKUPCFG_BRAMCFG_bf(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->BKUPCFG.reg ^= PM_BKUPCFG_BRAMCFG(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_bkupcfg_reg_t hri_pm_read_BKUPCFG_BRAMCFG_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->BKUPCFG.reg; + tmp = (tmp & PM_BKUPCFG_BRAMCFG_Msk) >> PM_BKUPCFG_BRAMCFG_Pos; + return tmp; +} + +static inline void hri_pm_set_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->BKUPCFG.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_bkupcfg_reg_t hri_pm_get_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->BKUPCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->BKUPCFG.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->BKUPCFG.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_BKUPCFG_reg(const void *const hw, hri_pm_bkupcfg_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->BKUPCFG.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_bkupcfg_reg_t hri_pm_read_BKUPCFG_reg(const void *const hw) +{ + return ((Pm *)hw)->BKUPCFG.reg; +} + +static inline void hri_pm_set_PWSAKDLY_IGNACK_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg |= PM_PWSAKDLY_IGNACK; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_pm_get_PWSAKDLY_IGNACK_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp = (tmp & PM_PWSAKDLY_IGNACK) >> PM_PWSAKDLY_IGNACK_Pos; + return (bool)tmp; +} + +static inline void hri_pm_write_PWSAKDLY_IGNACK_bit(const void *const hw, bool value) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp &= ~PM_PWSAKDLY_IGNACK; + tmp |= value << PM_PWSAKDLY_IGNACK_Pos; + ((Pm *)hw)->PWSAKDLY.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_PWSAKDLY_IGNACK_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg &= ~PM_PWSAKDLY_IGNACK; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_PWSAKDLY_IGNACK_bit(const void *const hw) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg ^= PM_PWSAKDLY_IGNACK; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_set_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg |= PM_PWSAKDLY_DLYVAL(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_pwsakdly_reg_t hri_pm_get_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp = (tmp & PM_PWSAKDLY_DLYVAL(mask)) >> PM_PWSAKDLY_DLYVAL_Pos; + return tmp; +} + +static inline void hri_pm_write_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t data) +{ + uint8_t tmp; + PM_CRITICAL_SECTION_ENTER(); + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp &= ~PM_PWSAKDLY_DLYVAL_Msk; + tmp |= PM_PWSAKDLY_DLYVAL(data); + ((Pm *)hw)->PWSAKDLY.reg = tmp; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg &= ~PM_PWSAKDLY_DLYVAL(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_PWSAKDLY_DLYVAL_bf(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg ^= PM_PWSAKDLY_DLYVAL(mask); + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_pwsakdly_reg_t hri_pm_read_PWSAKDLY_DLYVAL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp = (tmp & PM_PWSAKDLY_DLYVAL_Msk) >> PM_PWSAKDLY_DLYVAL_Pos; + return tmp; +} + +static inline void hri_pm_set_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg |= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_pwsakdly_reg_t hri_pm_get_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + uint8_t tmp; + tmp = ((Pm *)hw)->PWSAKDLY.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_pm_write_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t data) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg = data; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_clear_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg &= ~mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_pm_toggle_PWSAKDLY_reg(const void *const hw, hri_pm_pwsakdly_reg_t mask) +{ + PM_CRITICAL_SECTION_ENTER(); + ((Pm *)hw)->PWSAKDLY.reg ^= mask; + PM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_pm_pwsakdly_reg_t hri_pm_read_PWSAKDLY_reg(const void *const hw) +{ + return ((Pm *)hw)->PWSAKDLY.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PM_E54_H_INCLUDED */ +#endif /* _SAME54_PM_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_port_e54.h b/software/firmware/oracle_same54n19a/hri/hri_port_e54.h new file mode 100644 index 00000000..261fcf57 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_port_e54.h @@ -0,0 +1,2528 @@ +/** + * \file + * + * \brief SAM PORT + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_PORT_COMPONENT_ +#ifndef _HRI_PORT_E54_H_INCLUDED_ +#define _HRI_PORT_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_PORT_CRITICAL_SECTIONS) +#define PORT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define PORT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define PORT_CRITICAL_SECTION_ENTER() +#define PORT_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_port_ctrl_reg_t; +typedef uint32_t hri_port_dir_reg_t; +typedef uint32_t hri_port_evctrl_reg_t; +typedef uint32_t hri_port_in_reg_t; +typedef uint32_t hri_port_out_reg_t; +typedef uint32_t hri_port_wrconfig_reg_t; +typedef uint32_t hri_portgroup_ctrl_reg_t; +typedef uint32_t hri_portgroup_dir_reg_t; +typedef uint32_t hri_portgroup_evctrl_reg_t; +typedef uint32_t hri_portgroup_in_reg_t; +typedef uint32_t hri_portgroup_out_reg_t; +typedef uint32_t hri_portgroup_wrconfig_reg_t; +typedef uint8_t hri_port_pincfg_reg_t; +typedef uint8_t hri_port_pmux_reg_t; +typedef uint8_t hri_portgroup_pincfg_reg_t; +typedef uint8_t hri_portgroup_pmux_reg_t; + +static inline void hri_portgroup_set_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRSET.reg = PORT_DIR_DIR(mask); +} + +static inline hri_port_dir_reg_t hri_portgroup_get_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->DIR.reg; + tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos; + return tmp; +} + +static inline hri_port_dir_reg_t hri_portgroup_read_DIR_DIR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->DIR.reg; + tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos; + return tmp; +} + +static inline void hri_portgroup_write_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t data) +{ + ((PortGroup *)hw)->DIRSET.reg = PORT_DIR_DIR(data); + ((PortGroup *)hw)->DIRCLR.reg = ~PORT_DIR_DIR(data); +} + +static inline void hri_portgroup_clear_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRCLR.reg = PORT_DIR_DIR(mask); +} + +static inline void hri_portgroup_toggle_DIR_DIR_bf(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRTGL.reg = PORT_DIR_DIR(mask); +} + +static inline void hri_portgroup_set_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRSET.reg = mask; +} + +static inline hri_port_dir_reg_t hri_portgroup_get_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->DIR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_dir_reg_t hri_portgroup_read_DIR_reg(const void *const hw) +{ + return ((PortGroup *)hw)->DIR.reg; +} + +static inline void hri_portgroup_write_DIR_reg(const void *const hw, hri_port_dir_reg_t data) +{ + ((PortGroup *)hw)->DIRSET.reg = data; + ((PortGroup *)hw)->DIRCLR.reg = ~data; +} + +static inline void hri_portgroup_clear_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRCLR.reg = mask; +} + +static inline void hri_portgroup_toggle_DIR_reg(const void *const hw, hri_port_dir_reg_t mask) +{ + ((PortGroup *)hw)->DIRTGL.reg = mask; +} + +static inline void hri_portgroup_set_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTSET.reg = PORT_OUT_OUT(mask); +} + +static inline hri_port_out_reg_t hri_portgroup_get_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->OUT.reg; + tmp = (tmp & PORT_OUT_OUT(mask)) >> PORT_OUT_OUT_Pos; + return tmp; +} + +static inline hri_port_out_reg_t hri_portgroup_read_OUT_OUT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->OUT.reg; + tmp = (tmp & PORT_OUT_OUT_Msk) >> PORT_OUT_OUT_Pos; + return tmp; +} + +static inline void hri_portgroup_write_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t data) +{ + ((PortGroup *)hw)->OUTSET.reg = PORT_OUT_OUT(data); + ((PortGroup *)hw)->OUTCLR.reg = ~PORT_OUT_OUT(data); +} + +static inline void hri_portgroup_clear_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTCLR.reg = PORT_OUT_OUT(mask); +} + +static inline void hri_portgroup_toggle_OUT_OUT_bf(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTTGL.reg = PORT_OUT_OUT(mask); +} + +static inline void hri_portgroup_set_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTSET.reg = mask; +} + +static inline hri_port_out_reg_t hri_portgroup_get_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->OUT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_out_reg_t hri_portgroup_read_OUT_reg(const void *const hw) +{ + return ((PortGroup *)hw)->OUT.reg; +} + +static inline void hri_portgroup_write_OUT_reg(const void *const hw, hri_port_out_reg_t data) +{ + ((PortGroup *)hw)->OUTSET.reg = data; + ((PortGroup *)hw)->OUTCLR.reg = ~data; +} + +static inline void hri_portgroup_clear_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTCLR.reg = mask; +} + +static inline void hri_portgroup_toggle_OUT_reg(const void *const hw, hri_port_out_reg_t mask) +{ + ((PortGroup *)hw)->OUTTGL.reg = mask; +} + +static inline hri_port_in_reg_t hri_portgroup_get_IN_IN_bf(const void *const hw, hri_port_in_reg_t mask) +{ + return (((PortGroup *)hw)->IN.reg & PORT_IN_IN(mask)) >> PORT_IN_IN_Pos; +} + +static inline hri_port_in_reg_t hri_portgroup_read_IN_IN_bf(const void *const hw) +{ + return (((PortGroup *)hw)->IN.reg & PORT_IN_IN_Msk) >> PORT_IN_IN_Pos; +} + +static inline hri_port_in_reg_t hri_portgroup_get_IN_reg(const void *const hw, hri_port_in_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->IN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_in_reg_t hri_portgroup_read_IN_reg(const void *const hw) +{ + return ((PortGroup *)hw)->IN.reg; +} + +static inline void hri_portgroup_set_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg |= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_portgroup_write_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp &= ~PORT_CTRL_SAMPLING_Msk; + tmp |= PORT_CTRL_SAMPLING(data); + ((PortGroup *)hw)->CTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg &= ~PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_CTRL_SAMPLING_bf(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg ^= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_SAMPLING_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_portgroup_set_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_get_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_CTRL_reg(const void *const hw, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->CTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_portgroup_read_CTRL_reg(const void *const hw) +{ + return ((PortGroup *)hw)->CTRL.reg; +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI0_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI0; + tmp |= value << PORT_EVCTRL_PORTEI0_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI0_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI0_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI1_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI1; + tmp |= value << PORT_EVCTRL_PORTEI1_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI1_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI1_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI2_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI2; + tmp |= value << PORT_EVCTRL_PORTEI2_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI2_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI2_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PORTEI3_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_EVCTRL_PORTEI3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PORTEI3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI3; + tmp |= value << PORT_EVCTRL_PORTEI3_Pos; + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PORTEI3_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PORTEI3_bit(const void *const hw) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID0_Msk; + tmp |= PORT_EVCTRL_PID0(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT0_Msk; + tmp |= PORT_EVCTRL_EVACT0(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID1_Msk; + tmp |= PORT_EVCTRL_PID1(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT1_Msk; + tmp |= PORT_EVCTRL_EVACT1(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID2_Msk; + tmp |= PORT_EVCTRL_PID2(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT2_Msk; + tmp |= PORT_EVCTRL_EVACT2(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT2_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID3_Msk; + tmp |= PORT_EVCTRL_PID3(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_PID3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_PID3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT3_Msk; + tmp |= PORT_EVCTRL_EVACT3(data); + ((PortGroup *)hw)->EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_EVACT3_bf(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_EVACT3_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_portgroup_set_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_get_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((PortGroup *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_EVCTRL_reg(const void *const hw, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->EVCTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_portgroup_read_EVCTRL_reg(const void *const hw) +{ + return ((PortGroup *)hw)->EVCTRL.reg; +} + +static inline void hri_portgroup_set_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXE_bf(const void *const hw, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_portgroup_write_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXE_Msk; + tmp |= PORT_PMUX_PMUXE(data); + ((PortGroup *)hw)->PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXE_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_portgroup_set_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg |= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_PMUXO_bf(const void *const hw, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_portgroup_write_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXO_Msk; + tmp |= PORT_PMUX_PMUXO(data); + ((PortGroup *)hw)->PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg ^= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_PMUXO_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_portgroup_set_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_get_PMUX_reg(const void *const hw, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PMUX[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PMUX_reg(const void *const hw, uint8_t index, hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PMUX[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_portgroup_read_PMUX_reg(const void *const hw, uint8_t index) +{ + return ((PortGroup *)hw)->PMUX[index].reg; +} + +static inline void hri_portgroup_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PMUXEN; + tmp |= value << PORT_PINCFG_PMUXEN_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_INEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_INEN; + tmp |= value << PORT_PINCFG_INEN_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PULLEN; + tmp |= value << PORT_PINCFG_PULLEN_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_portgroup_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos; + return (bool)tmp; +} + +static inline void hri_portgroup_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index, bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= ~PORT_PINCFG_DRVSTR; + tmp |= value << PORT_PINCFG_DRVSTR_Pos; + ((PortGroup *)hw)->PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_set_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_portgroup_get_PINCFG_reg(const void *const hw, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((PortGroup *)hw)->PINCFG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_portgroup_write_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_clear_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_portgroup_toggle_PINCFG_reg(const void *const hw, uint8_t index, hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->PINCFG[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_portgroup_read_PINCFG_reg(const void *const hw, uint8_t index) +{ + return ((PortGroup *)hw)->PINCFG[index].reg; +} + +static inline void hri_portgroup_write_WRCONFIG_reg(const void *const hw, hri_port_wrconfig_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((PortGroup *)hw)->WRCONFIG.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = PORT_DIR_DIR(mask); +} + +static inline hri_port_dir_reg_t hri_port_get_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, + hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; + tmp = (tmp & PORT_DIR_DIR(mask)) >> PORT_DIR_DIR_Pos; + return tmp; +} + +static inline hri_port_dir_reg_t hri_port_read_DIR_DIR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; + tmp = (tmp & PORT_DIR_DIR_Msk) >> PORT_DIR_DIR_Pos; + return tmp; +} + +static inline void hri_port_write_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = PORT_DIR_DIR(data); + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~PORT_DIR_DIR(data); +} + +static inline void hri_port_clear_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = PORT_DIR_DIR(mask); +} + +static inline void hri_port_toggle_DIR_DIR_bf(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRTGL.reg = PORT_DIR_DIR(mask); +} + +static inline void hri_port_set_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = mask; +} + +static inline hri_port_dir_reg_t hri_port_get_DIR_reg(const void *const hw, uint8_t submodule_index, + hri_port_dir_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].DIR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_dir_reg_t hri_port_read_DIR_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].DIR.reg; +} + +static inline void hri_port_write_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].DIRSET.reg = data; + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = ~data; +} + +static inline void hri_port_clear_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRCLR.reg = mask; +} + +static inline void hri_port_toggle_DIR_reg(const void *const hw, uint8_t submodule_index, hri_port_dir_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].DIRTGL.reg = mask; +} + +static inline void hri_port_set_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = PORT_OUT_OUT(mask); +} + +static inline hri_port_out_reg_t hri_port_get_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, + hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; + tmp = (tmp & PORT_OUT_OUT(mask)) >> PORT_OUT_OUT_Pos; + return tmp; +} + +static inline hri_port_out_reg_t hri_port_read_OUT_OUT_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; + tmp = (tmp & PORT_OUT_OUT_Msk) >> PORT_OUT_OUT_Pos; + return tmp; +} + +static inline void hri_port_write_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = PORT_OUT_OUT(data); + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~PORT_OUT_OUT(data); +} + +static inline void hri_port_clear_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = PORT_OUT_OUT(mask); +} + +static inline void hri_port_toggle_OUT_OUT_bf(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTTGL.reg = PORT_OUT_OUT(mask); +} + +static inline void hri_port_set_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = mask; +} + +static inline hri_port_out_reg_t hri_port_get_OUT_reg(const void *const hw, uint8_t submodule_index, + hri_port_out_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].OUT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_out_reg_t hri_port_read_OUT_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].OUT.reg; +} + +static inline void hri_port_write_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t data) +{ + ((Port *)hw)->Group[submodule_index].OUTSET.reg = data; + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = ~data; +} + +static inline void hri_port_clear_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTCLR.reg = mask; +} + +static inline void hri_port_toggle_OUT_reg(const void *const hw, uint8_t submodule_index, hri_port_out_reg_t mask) +{ + ((Port *)hw)->Group[submodule_index].OUTTGL.reg = mask; +} + +static inline hri_port_in_reg_t hri_port_get_IN_IN_bf(const void *const hw, uint8_t submodule_index, + hri_port_in_reg_t mask) +{ + return (((Port *)hw)->Group[submodule_index].IN.reg & PORT_IN_IN(mask)) >> PORT_IN_IN_Pos; +} + +static inline hri_port_in_reg_t hri_port_read_IN_IN_bf(const void *const hw, uint8_t submodule_index) +{ + return (((Port *)hw)->Group[submodule_index].IN.reg & PORT_IN_IN_Msk) >> PORT_IN_IN_Pos; +} + +static inline hri_port_in_reg_t hri_port_get_IN_reg(const void *const hw, uint8_t submodule_index, + hri_port_in_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].IN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_port_in_reg_t hri_port_read_IN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].IN.reg; +} + +static inline void hri_port_set_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg |= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_get_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING(mask)) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_port_write_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp &= ~PORT_CTRL_SAMPLING_Msk; + tmp |= PORT_CTRL_SAMPLING(data); + ((Port *)hw)->Group[submodule_index].CTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg &= ~PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg ^= PORT_CTRL_SAMPLING(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_read_CTRL_SAMPLING_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp = (tmp & PORT_CTRL_SAMPLING_Msk) >> PORT_CTRL_SAMPLING_Pos; + return tmp; +} + +static inline void hri_port_set_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_get_CTRL_reg(const void *const hw, uint8_t submodule_index, + hri_port_ctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].CTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_CTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_ctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].CTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_ctrl_reg_t hri_port_read_CTRL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].CTRL.reg; +} + +static inline void hri_port_set_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI0) >> PORT_EVCTRL_PORTEI0_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI0; + tmp |= value << PORT_EVCTRL_PORTEI0_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI0_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI0; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI1) >> PORT_EVCTRL_PORTEI1_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI1; + tmp |= value << PORT_EVCTRL_PORTEI1_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI1_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI1; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI2) >> PORT_EVCTRL_PORTEI2_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI2; + tmp |= value << PORT_EVCTRL_PORTEI2_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI2_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI2; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PORTEI3) >> PORT_EVCTRL_PORTEI3_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PORTEI3; + tmp |= value << PORT_EVCTRL_PORTEI3_Pos; + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PORTEI3_bit(const void *const hw, uint8_t submodule_index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PORTEI3; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0(mask)) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID0_Msk; + tmp |= PORT_EVCTRL_PID0(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID0_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID0_Msk) >> PORT_EVCTRL_PID0_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0(mask)) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT0_Msk; + tmp |= PORT_EVCTRL_EVACT0(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT0(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT0_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT0_Msk) >> PORT_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1(mask)) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID1_Msk; + tmp |= PORT_EVCTRL_PID1(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID1_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID1_Msk) >> PORT_EVCTRL_PID1_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1(mask)) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT1_Msk; + tmp |= PORT_EVCTRL_EVACT1(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT1(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT1_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT1_Msk) >> PORT_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2(mask)) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID2_Msk; + tmp |= PORT_EVCTRL_PID2(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID2_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID2_Msk) >> PORT_EVCTRL_PID2_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2(mask)) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT2_Msk; + tmp |= PORT_EVCTRL_EVACT2(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT2(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT2_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT2_Msk) >> PORT_EVCTRL_EVACT2_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3(mask)) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_PID3_Msk; + tmp |= PORT_EVCTRL_PID3(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_PID3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_PID3_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_PID3_Msk) >> PORT_EVCTRL_PID3_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3(mask)) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_port_write_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t data) +{ + uint32_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= ~PORT_EVCTRL_EVACT3_Msk; + tmp |= PORT_EVCTRL_EVACT3(data); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= PORT_EVCTRL_EVACT3(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_EVACT3_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp = (tmp & PORT_EVCTRL_EVACT3_Msk) >> PORT_EVCTRL_EVACT3_Pos; + return tmp; +} + +static inline void hri_port_set_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_get_EVCTRL_reg(const void *const hw, uint8_t submodule_index, + hri_port_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_EVCTRL_reg(const void *const hw, uint8_t submodule_index, hri_port_evctrl_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].EVCTRL.reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_evctrl_reg_t hri_port_read_EVCTRL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Port *)hw)->Group[submodule_index].EVCTRL.reg; +} + +static inline void hri_port_set_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, + uint8_t index, hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE(mask)) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_port_write_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXE_Msk; + tmp |= PORT_PMUX_PMUXE(data); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXE(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXE_bf(const void *const hw, uint8_t submodule_index, + uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXE_Msk) >> PORT_PMUX_PMUXE_Pos; + return tmp; +} + +static inline void hri_port_set_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_get_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, + uint8_t index, hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO(mask)) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_port_write_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t data) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp &= ~PORT_PMUX_PMUXO_Msk; + tmp |= PORT_PMUX_PMUXO(data); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= PORT_PMUX_PMUXO(mask); + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_read_PMUX_PMUXO_bf(const void *const hw, uint8_t submodule_index, + uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp = (tmp & PORT_PMUX_PMUXO_Msk) >> PORT_PMUX_PMUXO_Pos; + return tmp; +} + +static inline void hri_port_set_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_get_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PMUX[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pmux_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PMUX[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pmux_reg_t hri_port_read_PMUX_reg(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + return ((Port *)hw)->Group[submodule_index].PMUX[index].reg; +} + +static inline void hri_port_set_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PMUXEN) >> PORT_PINCFG_PMUXEN_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PMUXEN; + tmp |= value << PORT_PINCFG_PMUXEN_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_PMUXEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PMUXEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_INEN) >> PORT_PINCFG_INEN_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_INEN; + tmp |= value << PORT_PINCFG_INEN_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_INEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_INEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_PULLEN) >> PORT_PINCFG_PULLEN_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_PULLEN; + tmp |= value << PORT_PINCFG_PULLEN_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_PULLEN_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_PULLEN; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_port_get_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp = (tmp & PORT_PINCFG_DRVSTR) >> PORT_PINCFG_DRVSTR_Pos; + return (bool)tmp; +} + +static inline void hri_port_write_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index, + bool value) +{ + uint8_t tmp; + PORT_CRITICAL_SECTION_ENTER(); + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= ~PORT_PINCFG_DRVSTR; + tmp |= value << PORT_PINCFG_DRVSTR_Pos; + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = tmp; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_DRVSTR_bit(const void *const hw, uint8_t submodule_index, uint8_t index) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= PORT_PINCFG_DRVSTR; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_set_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg |= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_port_get_PINCFG_reg(const void *const hw, uint8_t submodule_index, + uint8_t index, hri_port_pincfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_port_write_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_clear_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg &= ~mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_port_toggle_PINCFG_reg(const void *const hw, uint8_t submodule_index, uint8_t index, + hri_port_pincfg_reg_t mask) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].PINCFG[index].reg ^= mask; + PORT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_port_pincfg_reg_t hri_port_read_PINCFG_reg(const void *const hw, uint8_t submodule_index, + uint8_t index) +{ + return ((Port *)hw)->Group[submodule_index].PINCFG[index].reg; +} + +static inline void hri_port_write_WRCONFIG_reg(const void *const hw, uint8_t submodule_index, + hri_port_wrconfig_reg_t data) +{ + PORT_CRITICAL_SECTION_ENTER(); + ((Port *)hw)->Group[submodule_index].WRCONFIG.reg = data; + PORT_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_PORT_E54_H_INCLUDED */ +#endif /* _SAME54_PORT_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_qspi_e54.h b/software/firmware/oracle_same54n19a/hri/hri_qspi_e54.h new file mode 100644 index 00000000..23742bce --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_qspi_e54.h @@ -0,0 +1,2058 @@ +/** + * \file + * + * \brief SAM QSPI + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_QSPI_COMPONENT_ +#ifndef _HRI_QSPI_E54_H_INCLUDED_ +#define _HRI_QSPI_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_QSPI_CRITICAL_SECTIONS) +#define QSPI_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define QSPI_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define QSPI_CRITICAL_SECTION_ENTER() +#define QSPI_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_qspi_baud_reg_t; +typedef uint32_t hri_qspi_ctrla_reg_t; +typedef uint32_t hri_qspi_ctrlb_reg_t; +typedef uint32_t hri_qspi_instraddr_reg_t; +typedef uint32_t hri_qspi_instrctrl_reg_t; +typedef uint32_t hri_qspi_instrframe_reg_t; +typedef uint32_t hri_qspi_intenset_reg_t; +typedef uint32_t hri_qspi_intflag_reg_t; +typedef uint32_t hri_qspi_rxdata_reg_t; +typedef uint32_t hri_qspi_scrambctrl_reg_t; +typedef uint32_t hri_qspi_scrambkey_reg_t; +typedef uint32_t hri_qspi_status_reg_t; +typedef uint32_t hri_qspi_txdata_reg_t; + +static inline bool hri_qspi_get_INTFLAG_RXC_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_RXC) >> QSPI_INTFLAG_RXC_Pos; +} + +static inline void hri_qspi_clear_INTFLAG_RXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_RXC; +} + +static inline bool hri_qspi_get_INTFLAG_DRE_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_DRE) >> QSPI_INTFLAG_DRE_Pos; +} + +static inline void hri_qspi_clear_INTFLAG_DRE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_DRE; +} + +static inline bool hri_qspi_get_INTFLAG_TXC_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_TXC) >> QSPI_INTFLAG_TXC_Pos; +} + +static inline void hri_qspi_clear_INTFLAG_TXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_TXC; +} + +static inline bool hri_qspi_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_ERROR) >> QSPI_INTFLAG_ERROR_Pos; +} + +static inline void hri_qspi_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_ERROR; +} + +static inline bool hri_qspi_get_INTFLAG_CSRISE_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_CSRISE) >> QSPI_INTFLAG_CSRISE_Pos; +} + +static inline void hri_qspi_clear_INTFLAG_CSRISE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_CSRISE; +} + +static inline bool hri_qspi_get_INTFLAG_INSTREND_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_INSTREND) >> QSPI_INTFLAG_INSTREND_Pos; +} + +static inline void hri_qspi_clear_INTFLAG_INSTREND_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_INSTREND; +} + +static inline bool hri_qspi_get_interrupt_RXC_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_RXC) >> QSPI_INTFLAG_RXC_Pos; +} + +static inline void hri_qspi_clear_interrupt_RXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_RXC; +} + +static inline bool hri_qspi_get_interrupt_DRE_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_DRE) >> QSPI_INTFLAG_DRE_Pos; +} + +static inline void hri_qspi_clear_interrupt_DRE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_DRE; +} + +static inline bool hri_qspi_get_interrupt_TXC_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_TXC) >> QSPI_INTFLAG_TXC_Pos; +} + +static inline void hri_qspi_clear_interrupt_TXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_TXC; +} + +static inline bool hri_qspi_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_ERROR) >> QSPI_INTFLAG_ERROR_Pos; +} + +static inline void hri_qspi_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_ERROR; +} + +static inline bool hri_qspi_get_interrupt_CSRISE_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_CSRISE) >> QSPI_INTFLAG_CSRISE_Pos; +} + +static inline void hri_qspi_clear_interrupt_CSRISE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_CSRISE; +} + +static inline bool hri_qspi_get_interrupt_INSTREND_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTFLAG.reg & QSPI_INTFLAG_INSTREND) >> QSPI_INTFLAG_INSTREND_Pos; +} + +static inline void hri_qspi_clear_interrupt_INSTREND_bit(const void *const hw) +{ + ((Qspi *)hw)->INTFLAG.reg = QSPI_INTFLAG_INSTREND; +} + +static inline hri_qspi_intflag_reg_t hri_qspi_get_INTFLAG_reg(const void *const hw, hri_qspi_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_qspi_intflag_reg_t hri_qspi_read_INTFLAG_reg(const void *const hw) +{ + return ((Qspi *)hw)->INTFLAG.reg; +} + +static inline void hri_qspi_clear_INTFLAG_reg(const void *const hw, hri_qspi_intflag_reg_t mask) +{ + ((Qspi *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_qspi_set_INTEN_RXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_RXC; +} + +static inline bool hri_qspi_get_INTEN_RXC_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_RXC) >> QSPI_INTENSET_RXC_Pos; +} + +static inline void hri_qspi_write_INTEN_RXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_RXC; + } else { + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_RXC; + } +} + +static inline void hri_qspi_clear_INTEN_RXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_RXC; +} + +static inline void hri_qspi_set_INTEN_DRE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_DRE; +} + +static inline bool hri_qspi_get_INTEN_DRE_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_DRE) >> QSPI_INTENSET_DRE_Pos; +} + +static inline void hri_qspi_write_INTEN_DRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_DRE; + } else { + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_DRE; + } +} + +static inline void hri_qspi_clear_INTEN_DRE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_DRE; +} + +static inline void hri_qspi_set_INTEN_TXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_TXC; +} + +static inline bool hri_qspi_get_INTEN_TXC_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_TXC) >> QSPI_INTENSET_TXC_Pos; +} + +static inline void hri_qspi_write_INTEN_TXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_TXC; + } else { + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_TXC; + } +} + +static inline void hri_qspi_clear_INTEN_TXC_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_TXC; +} + +static inline void hri_qspi_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_ERROR; +} + +static inline bool hri_qspi_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_ERROR) >> QSPI_INTENSET_ERROR_Pos; +} + +static inline void hri_qspi_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_ERROR; + } else { + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_ERROR; + } +} + +static inline void hri_qspi_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_ERROR; +} + +static inline void hri_qspi_set_INTEN_CSRISE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_CSRISE; +} + +static inline bool hri_qspi_get_INTEN_CSRISE_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_CSRISE) >> QSPI_INTENSET_CSRISE_Pos; +} + +static inline void hri_qspi_write_INTEN_CSRISE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_CSRISE; + } else { + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_CSRISE; + } +} + +static inline void hri_qspi_clear_INTEN_CSRISE_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_CSRISE; +} + +static inline void hri_qspi_set_INTEN_INSTREND_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_INSTREND; +} + +static inline bool hri_qspi_get_INTEN_INSTREND_bit(const void *const hw) +{ + return (((Qspi *)hw)->INTENSET.reg & QSPI_INTENSET_INSTREND) >> QSPI_INTENSET_INSTREND_Pos; +} + +static inline void hri_qspi_write_INTEN_INSTREND_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_INSTREND; + } else { + ((Qspi *)hw)->INTENSET.reg = QSPI_INTENSET_INSTREND; + } +} + +static inline void hri_qspi_clear_INTEN_INSTREND_bit(const void *const hw) +{ + ((Qspi *)hw)->INTENCLR.reg = QSPI_INTENSET_INSTREND; +} + +static inline void hri_qspi_set_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t mask) +{ + ((Qspi *)hw)->INTENSET.reg = mask; +} + +static inline hri_qspi_intenset_reg_t hri_qspi_get_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_qspi_intenset_reg_t hri_qspi_read_INTEN_reg(const void *const hw) +{ + return ((Qspi *)hw)->INTENSET.reg; +} + +static inline void hri_qspi_write_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t data) +{ + ((Qspi *)hw)->INTENSET.reg = data; + ((Qspi *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_qspi_clear_INTEN_reg(const void *const hw, hri_qspi_intenset_reg_t mask) +{ + ((Qspi *)hw)->INTENCLR.reg = mask; +} + +static inline hri_qspi_rxdata_reg_t hri_qspi_get_RXDATA_DATA_bf(const void *const hw, hri_qspi_rxdata_reg_t mask) +{ + return (((Qspi *)hw)->RXDATA.reg & QSPI_RXDATA_DATA(mask)) >> QSPI_RXDATA_DATA_Pos; +} + +static inline hri_qspi_rxdata_reg_t hri_qspi_read_RXDATA_DATA_bf(const void *const hw) +{ + return (((Qspi *)hw)->RXDATA.reg & QSPI_RXDATA_DATA_Msk) >> QSPI_RXDATA_DATA_Pos; +} + +static inline hri_qspi_rxdata_reg_t hri_qspi_get_RXDATA_reg(const void *const hw, hri_qspi_rxdata_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->RXDATA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_qspi_rxdata_reg_t hri_qspi_read_RXDATA_reg(const void *const hw) +{ + return ((Qspi *)hw)->RXDATA.reg; +} + +static inline bool hri_qspi_get_STATUS_ENABLE_bit(const void *const hw) +{ + return (((Qspi *)hw)->STATUS.reg & QSPI_STATUS_ENABLE) >> QSPI_STATUS_ENABLE_Pos; +} + +static inline bool hri_qspi_get_STATUS_CSSTATUS_bit(const void *const hw) +{ + return (((Qspi *)hw)->STATUS.reg & QSPI_STATUS_CSSTATUS) >> QSPI_STATUS_CSSTATUS_Pos; +} + +static inline hri_qspi_status_reg_t hri_qspi_get_STATUS_reg(const void *const hw, hri_qspi_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_qspi_status_reg_t hri_qspi_read_STATUS_reg(const void *const hw) +{ + return ((Qspi *)hw)->STATUS.reg; +} + +static inline void hri_qspi_set_CTRLA_SWRST_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg |= QSPI_CTRLA_SWRST; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLA.reg; + tmp = (tmp & QSPI_CTRLA_SWRST) >> QSPI_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_set_CTRLA_ENABLE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg |= QSPI_CTRLA_ENABLE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLA.reg; + tmp = (tmp & QSPI_CTRLA_ENABLE) >> QSPI_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLA.reg; + tmp &= ~QSPI_CTRLA_ENABLE; + tmp |= value << QSPI_CTRLA_ENABLE_Pos; + ((Qspi *)hw)->CTRLA.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg &= ~QSPI_CTRLA_ENABLE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg ^= QSPI_CTRLA_ENABLE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_CTRLA_LASTXFER_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg |= QSPI_CTRLA_LASTXFER; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_CTRLA_LASTXFER_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLA.reg; + tmp = (tmp & QSPI_CTRLA_LASTXFER) >> QSPI_CTRLA_LASTXFER_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_CTRLA_LASTXFER_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLA.reg; + tmp &= ~QSPI_CTRLA_LASTXFER; + tmp |= value << QSPI_CTRLA_LASTXFER_Pos; + ((Qspi *)hw)->CTRLA.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLA_LASTXFER_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg &= ~QSPI_CTRLA_LASTXFER; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLA_LASTXFER_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg ^= QSPI_CTRLA_LASTXFER; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrla_reg_t hri_qspi_get_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLA_reg(const void *const hw, hri_qspi_ctrla_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLA.reg ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrla_reg_t hri_qspi_read_CTRLA_reg(const void *const hw) +{ + return ((Qspi *)hw)->CTRLA.reg; +} + +static inline void hri_qspi_set_CTRLB_MODE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_MODE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_CTRLB_MODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_MODE) >> QSPI_CTRLB_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_CTRLB_MODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_MODE; + tmp |= value << QSPI_CTRLB_MODE_Pos; + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_MODE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_MODE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_MODE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_MODE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_CTRLB_LOOPEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_LOOPEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_CTRLB_LOOPEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_LOOPEN) >> QSPI_CTRLB_LOOPEN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_CTRLB_LOOPEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_LOOPEN; + tmp |= value << QSPI_CTRLB_LOOPEN_Pos; + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_LOOPEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_LOOPEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_LOOPEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_LOOPEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_CTRLB_WDRBT_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_WDRBT; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_CTRLB_WDRBT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_WDRBT) >> QSPI_CTRLB_WDRBT_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_CTRLB_WDRBT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_WDRBT; + tmp |= value << QSPI_CTRLB_WDRBT_Pos; + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_WDRBT_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_WDRBT; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_WDRBT_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_WDRBT; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_CTRLB_SMEMREG_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_SMEMREG; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_CTRLB_SMEMREG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_SMEMREG) >> QSPI_CTRLB_SMEMREG_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_CTRLB_SMEMREG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_SMEMREG; + tmp |= value << QSPI_CTRLB_SMEMREG_Pos; + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_SMEMREG_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_SMEMREG; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_SMEMREG_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_SMEMREG; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_CSMODE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_CSMODE(mask)) >> QSPI_CTRLB_CSMODE_Pos; + return tmp; +} + +static inline void hri_qspi_write_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_CSMODE_Msk; + tmp |= QSPI_CTRLB_CSMODE(data); + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_CSMODE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_CSMODE_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_CSMODE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_CSMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_CSMODE_Msk) >> QSPI_CTRLB_CSMODE_Pos; + return tmp; +} + +static inline void hri_qspi_set_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_DATALEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_DATALEN(mask)) >> QSPI_CTRLB_DATALEN_Pos; + return tmp; +} + +static inline void hri_qspi_write_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_DATALEN_Msk; + tmp |= QSPI_CTRLB_DATALEN(data); + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_DATALEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_DATALEN_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_DATALEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_DATALEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_DATALEN_Msk) >> QSPI_CTRLB_DATALEN_Pos; + return tmp; +} + +static inline void hri_qspi_set_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_DLYBCT(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_DLYBCT(mask)) >> QSPI_CTRLB_DLYBCT_Pos; + return tmp; +} + +static inline void hri_qspi_write_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_DLYBCT_Msk; + tmp |= QSPI_CTRLB_DLYBCT(data); + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_DLYBCT(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_DLYBCT_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_DLYBCT(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_DLYBCT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_DLYBCT_Msk) >> QSPI_CTRLB_DLYBCT_Pos; + return tmp; +} + +static inline void hri_qspi_set_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= QSPI_CTRLB_DLYCS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_DLYCS(mask)) >> QSPI_CTRLB_DLYCS_Pos; + return tmp; +} + +static inline void hri_qspi_write_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= ~QSPI_CTRLB_DLYCS_Msk; + tmp |= QSPI_CTRLB_DLYCS(data); + ((Qspi *)hw)->CTRLB.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~QSPI_CTRLB_DLYCS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_DLYCS_bf(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= QSPI_CTRLB_DLYCS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_DLYCS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp = (tmp & QSPI_CTRLB_DLYCS_Msk) >> QSPI_CTRLB_DLYCS_Pos; + return tmp; +} + +static inline void hri_qspi_set_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_get_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_CTRLB_reg(const void *const hw, hri_qspi_ctrlb_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->CTRLB.reg ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_ctrlb_reg_t hri_qspi_read_CTRLB_reg(const void *const hw) +{ + return ((Qspi *)hw)->CTRLB.reg; +} + +static inline void hri_qspi_set_BAUD_CPOL_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_CPOL; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_BAUD_CPOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->BAUD.reg; + tmp = (tmp & QSPI_BAUD_CPOL) >> QSPI_BAUD_CPOL_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_BAUD_CPOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->BAUD.reg; + tmp &= ~QSPI_BAUD_CPOL; + tmp |= value << QSPI_BAUD_CPOL_Pos; + ((Qspi *)hw)->BAUD.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_BAUD_CPOL_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_CPOL; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_BAUD_CPOL_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_CPOL; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_BAUD_CPHA_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_CPHA; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_BAUD_CPHA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->BAUD.reg; + tmp = (tmp & QSPI_BAUD_CPHA) >> QSPI_BAUD_CPHA_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_BAUD_CPHA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->BAUD.reg; + tmp &= ~QSPI_BAUD_CPHA; + tmp |= value << QSPI_BAUD_CPHA_Pos; + ((Qspi *)hw)->BAUD.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_BAUD_CPHA_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_CPHA; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_BAUD_CPHA_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_CPHA; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_BAUD(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_baud_reg_t hri_qspi_get_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->BAUD.reg; + tmp = (tmp & QSPI_BAUD_BAUD(mask)) >> QSPI_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_qspi_write_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->BAUD.reg; + tmp &= ~QSPI_BAUD_BAUD_Msk; + tmp |= QSPI_BAUD_BAUD(data); + ((Qspi *)hw)->BAUD.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_BAUD(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_BAUD_BAUD_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_BAUD(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_baud_reg_t hri_qspi_read_BAUD_BAUD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->BAUD.reg; + tmp = (tmp & QSPI_BAUD_BAUD_Msk) >> QSPI_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_qspi_set_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg |= QSPI_BAUD_DLYBS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_baud_reg_t hri_qspi_get_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->BAUD.reg; + tmp = (tmp & QSPI_BAUD_DLYBS(mask)) >> QSPI_BAUD_DLYBS_Pos; + return tmp; +} + +static inline void hri_qspi_write_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->BAUD.reg; + tmp &= ~QSPI_BAUD_DLYBS_Msk; + tmp |= QSPI_BAUD_DLYBS(data); + ((Qspi *)hw)->BAUD.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg &= ~QSPI_BAUD_DLYBS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_BAUD_DLYBS_bf(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg ^= QSPI_BAUD_DLYBS(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_baud_reg_t hri_qspi_read_BAUD_DLYBS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->BAUD.reg; + tmp = (tmp & QSPI_BAUD_DLYBS_Msk) >> QSPI_BAUD_DLYBS_Pos; + return tmp; +} + +static inline void hri_qspi_set_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_baud_reg_t hri_qspi_get_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_BAUD_reg(const void *const hw, hri_qspi_baud_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->BAUD.reg ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_baud_reg_t hri_qspi_read_BAUD_reg(const void *const hw) +{ + return ((Qspi *)hw)->BAUD.reg; +} + +static inline void hri_qspi_set_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRADDR.reg |= QSPI_INSTRADDR_ADDR(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instraddr_reg_t hri_qspi_get_INSTRADDR_ADDR_bf(const void *const hw, + hri_qspi_instraddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRADDR.reg; + tmp = (tmp & QSPI_INSTRADDR_ADDR(mask)) >> QSPI_INSTRADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_qspi_write_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRADDR.reg; + tmp &= ~QSPI_INSTRADDR_ADDR_Msk; + tmp |= QSPI_INSTRADDR_ADDR(data); + ((Qspi *)hw)->INSTRADDR.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRADDR.reg &= ~QSPI_INSTRADDR_ADDR(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRADDR_ADDR_bf(const void *const hw, hri_qspi_instraddr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRADDR.reg ^= QSPI_INSTRADDR_ADDR(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instraddr_reg_t hri_qspi_read_INSTRADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRADDR.reg; + tmp = (tmp & QSPI_INSTRADDR_ADDR_Msk) >> QSPI_INSTRADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_qspi_set_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRADDR.reg |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instraddr_reg_t hri_qspi_get_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRADDR.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRADDR.reg &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRADDR_reg(const void *const hw, hri_qspi_instraddr_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRADDR.reg ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instraddr_reg_t hri_qspi_read_INSTRADDR_reg(const void *const hw) +{ + return ((Qspi *)hw)->INSTRADDR.reg; +} + +static inline void hri_qspi_set_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg |= QSPI_INSTRCTRL_INSTR(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrctrl_reg_t hri_qspi_get_INSTRCTRL_INSTR_bf(const void *const hw, + hri_qspi_instrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRCTRL.reg; + tmp = (tmp & QSPI_INSTRCTRL_INSTR(mask)) >> QSPI_INSTRCTRL_INSTR_Pos; + return tmp; +} + +static inline void hri_qspi_write_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRCTRL.reg; + tmp &= ~QSPI_INSTRCTRL_INSTR_Msk; + tmp |= QSPI_INSTRCTRL_INSTR(data); + ((Qspi *)hw)->INSTRCTRL.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg &= ~QSPI_INSTRCTRL_INSTR(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRCTRL_INSTR_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg ^= QSPI_INSTRCTRL_INSTR(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrctrl_reg_t hri_qspi_read_INSTRCTRL_INSTR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRCTRL.reg; + tmp = (tmp & QSPI_INSTRCTRL_INSTR_Msk) >> QSPI_INSTRCTRL_INSTR_Pos; + return tmp; +} + +static inline void hri_qspi_set_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg |= QSPI_INSTRCTRL_OPTCODE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrctrl_reg_t hri_qspi_get_INSTRCTRL_OPTCODE_bf(const void *const hw, + hri_qspi_instrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRCTRL.reg; + tmp = (tmp & QSPI_INSTRCTRL_OPTCODE(mask)) >> QSPI_INSTRCTRL_OPTCODE_Pos; + return tmp; +} + +static inline void hri_qspi_write_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRCTRL.reg; + tmp &= ~QSPI_INSTRCTRL_OPTCODE_Msk; + tmp |= QSPI_INSTRCTRL_OPTCODE(data); + ((Qspi *)hw)->INSTRCTRL.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg &= ~QSPI_INSTRCTRL_OPTCODE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRCTRL_OPTCODE_bf(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg ^= QSPI_INSTRCTRL_OPTCODE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrctrl_reg_t hri_qspi_read_INSTRCTRL_OPTCODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRCTRL.reg; + tmp = (tmp & QSPI_INSTRCTRL_OPTCODE_Msk) >> QSPI_INSTRCTRL_OPTCODE_Pos; + return tmp; +} + +static inline void hri_qspi_set_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrctrl_reg_t hri_qspi_get_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRCTRL_reg(const void *const hw, hri_qspi_instrctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRCTRL.reg ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrctrl_reg_t hri_qspi_read_INSTRCTRL_reg(const void *const hw) +{ + return ((Qspi *)hw)->INSTRCTRL.reg; +} + +static inline void hri_qspi_set_INSTRFRAME_INSTREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_INSTREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_INSTRFRAME_INSTREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_INSTREN) >> QSPI_INSTRFRAME_INSTREN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_INSTREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_INSTREN; + tmp |= value << QSPI_INSTRFRAME_INSTREN_Pos; + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_INSTREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_INSTREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_INSTREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_INSTREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_INSTRFRAME_ADDREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_ADDREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_INSTRFRAME_ADDREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_ADDREN) >> QSPI_INSTRFRAME_ADDREN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_ADDREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_ADDREN; + tmp |= value << QSPI_INSTRFRAME_ADDREN_Pos; + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_ADDREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_ADDREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_ADDREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_ADDREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_INSTRFRAME_OPTCODEEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_OPTCODEEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_INSTRFRAME_OPTCODEEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_OPTCODEEN) >> QSPI_INSTRFRAME_OPTCODEEN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_OPTCODEEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_OPTCODEEN; + tmp |= value << QSPI_INSTRFRAME_OPTCODEEN_Pos; + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_OPTCODEEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_OPTCODEEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_OPTCODEEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_OPTCODEEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_INSTRFRAME_DATAEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_DATAEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_INSTRFRAME_DATAEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_DATAEN) >> QSPI_INSTRFRAME_DATAEN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_DATAEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_DATAEN; + tmp |= value << QSPI_INSTRFRAME_DATAEN_Pos; + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_DATAEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_DATAEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_DATAEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_DATAEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_INSTRFRAME_ADDRLEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_ADDRLEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_INSTRFRAME_ADDRLEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_ADDRLEN) >> QSPI_INSTRFRAME_ADDRLEN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_ADDRLEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_ADDRLEN; + tmp |= value << QSPI_INSTRFRAME_ADDRLEN_Pos; + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_ADDRLEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_ADDRLEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_ADDRLEN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_ADDRLEN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_INSTRFRAME_CRMODE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_CRMODE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_INSTRFRAME_CRMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_CRMODE) >> QSPI_INSTRFRAME_CRMODE_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_CRMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_CRMODE; + tmp |= value << QSPI_INSTRFRAME_CRMODE_Pos; + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_CRMODE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_CRMODE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_CRMODE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_CRMODE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_INSTRFRAME_DDREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_DDREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_INSTRFRAME_DDREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_DDREN) >> QSPI_INSTRFRAME_DDREN_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_DDREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_DDREN; + tmp |= value << QSPI_INSTRFRAME_DDREN_Pos; + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_DDREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_DDREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_DDREN_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_DDREN; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_WIDTH(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_WIDTH_bf(const void *const hw, + hri_qspi_instrframe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_WIDTH(mask)) >> QSPI_INSTRFRAME_WIDTH_Pos; + return tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_WIDTH_Msk; + tmp |= QSPI_INSTRFRAME_WIDTH(data); + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_WIDTH(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_WIDTH_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_WIDTH(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_WIDTH_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_WIDTH_Msk) >> QSPI_INSTRFRAME_WIDTH_Pos; + return tmp; +} + +static inline void hri_qspi_set_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_OPTCODELEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_OPTCODELEN_bf(const void *const hw, + hri_qspi_instrframe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_OPTCODELEN(mask)) >> QSPI_INSTRFRAME_OPTCODELEN_Pos; + return tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_OPTCODELEN_Msk; + tmp |= QSPI_INSTRFRAME_OPTCODELEN(data); + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_OPTCODELEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_OPTCODELEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_OPTCODELEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_OPTCODELEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_OPTCODELEN_Msk) >> QSPI_INSTRFRAME_OPTCODELEN_Pos; + return tmp; +} + +static inline void hri_qspi_set_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_TFRTYPE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_TFRTYPE_bf(const void *const hw, + hri_qspi_instrframe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_TFRTYPE(mask)) >> QSPI_INSTRFRAME_TFRTYPE_Pos; + return tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_TFRTYPE_Msk; + tmp |= QSPI_INSTRFRAME_TFRTYPE(data); + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_TFRTYPE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_TFRTYPE_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_TFRTYPE(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_TFRTYPE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_TFRTYPE_Msk) >> QSPI_INSTRFRAME_TFRTYPE_Pos; + return tmp; +} + +static inline void hri_qspi_set_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= QSPI_INSTRFRAME_DUMMYLEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_DUMMYLEN_bf(const void *const hw, + hri_qspi_instrframe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_DUMMYLEN(mask)) >> QSPI_INSTRFRAME_DUMMYLEN_Pos; + return tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t data) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= ~QSPI_INSTRFRAME_DUMMYLEN_Msk; + tmp |= QSPI_INSTRFRAME_DUMMYLEN(data); + ((Qspi *)hw)->INSTRFRAME.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~QSPI_INSTRFRAME_DUMMYLEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_DUMMYLEN_bf(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= QSPI_INSTRFRAME_DUMMYLEN(mask); + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_DUMMYLEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp = (tmp & QSPI_INSTRFRAME_DUMMYLEN_Msk) >> QSPI_INSTRFRAME_DUMMYLEN_Pos; + return tmp; +} + +static inline void hri_qspi_set_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_get_INSTRFRAME_reg(const void *const hw, + hri_qspi_instrframe_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->INSTRFRAME.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_INSTRFRAME_reg(const void *const hw, hri_qspi_instrframe_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->INSTRFRAME.reg ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_instrframe_reg_t hri_qspi_read_INSTRFRAME_reg(const void *const hw) +{ + return ((Qspi *)hw)->INSTRFRAME.reg; +} + +static inline void hri_qspi_set_SCRAMBCTRL_ENABLE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg |= QSPI_SCRAMBCTRL_ENABLE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_SCRAMBCTRL_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; + tmp = (tmp & QSPI_SCRAMBCTRL_ENABLE) >> QSPI_SCRAMBCTRL_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_SCRAMBCTRL_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; + tmp &= ~QSPI_SCRAMBCTRL_ENABLE; + tmp |= value << QSPI_SCRAMBCTRL_ENABLE_Pos; + ((Qspi *)hw)->SCRAMBCTRL.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_SCRAMBCTRL_ENABLE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg &= ~QSPI_SCRAMBCTRL_ENABLE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_SCRAMBCTRL_ENABLE_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg ^= QSPI_SCRAMBCTRL_ENABLE; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg |= QSPI_SCRAMBCTRL_RANDOMDIS; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_qspi_get_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; + tmp = (tmp & QSPI_SCRAMBCTRL_RANDOMDIS) >> QSPI_SCRAMBCTRL_RANDOMDIS_Pos; + return (bool)tmp; +} + +static inline void hri_qspi_write_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + QSPI_CRITICAL_SECTION_ENTER(); + tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; + tmp &= ~QSPI_SCRAMBCTRL_RANDOMDIS; + tmp |= value << QSPI_SCRAMBCTRL_RANDOMDIS_Pos; + ((Qspi *)hw)->SCRAMBCTRL.reg = tmp; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg &= ~QSPI_SCRAMBCTRL_RANDOMDIS; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_SCRAMBCTRL_RANDOMDIS_bit(const void *const hw) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg ^= QSPI_SCRAMBCTRL_RANDOMDIS; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_set_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg |= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_scrambctrl_reg_t hri_qspi_get_SCRAMBCTRL_reg(const void *const hw, + hri_qspi_scrambctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Qspi *)hw)->SCRAMBCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_qspi_write_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_clear_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg &= ~mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_toggle_SCRAMBCTRL_reg(const void *const hw, hri_qspi_scrambctrl_reg_t mask) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBCTRL.reg ^= mask; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_qspi_scrambctrl_reg_t hri_qspi_read_SCRAMBCTRL_reg(const void *const hw) +{ + return ((Qspi *)hw)->SCRAMBCTRL.reg; +} + +static inline void hri_qspi_write_TXDATA_reg(const void *const hw, hri_qspi_txdata_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->TXDATA.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_qspi_write_SCRAMBKEY_reg(const void *const hw, hri_qspi_scrambkey_reg_t data) +{ + QSPI_CRITICAL_SECTION_ENTER(); + ((Qspi *)hw)->SCRAMBKEY.reg = data; + QSPI_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_QSPI_E54_H_INCLUDED */ +#endif /* _SAME54_QSPI_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_ramecc_e54.h b/software/firmware/oracle_same54n19a/hri/hri_ramecc_e54.h new file mode 100644 index 00000000..6031cce1 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_ramecc_e54.h @@ -0,0 +1,362 @@ +/** + * \file + * + * \brief SAM RAMECC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_RAMECC_COMPONENT_ +#ifndef _HRI_RAMECC_E54_H_INCLUDED_ +#define _HRI_RAMECC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_RAMECC_CRITICAL_SECTIONS) +#define RAMECC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define RAMECC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define RAMECC_CRITICAL_SECTION_ENTER() +#define RAMECC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_ramecc_erraddr_reg_t; +typedef uint8_t hri_ramecc_dbgctrl_reg_t; +typedef uint8_t hri_ramecc_intenset_reg_t; +typedef uint8_t hri_ramecc_intflag_reg_t; +typedef uint8_t hri_ramecc_status_reg_t; + +static inline bool hri_ramecc_get_INTFLAG_SINGLEE_bit(const void *const hw) +{ + return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_SINGLEE) >> RAMECC_INTFLAG_SINGLEE_Pos; +} + +static inline void hri_ramecc_clear_INTFLAG_SINGLEE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_SINGLEE; +} + +static inline bool hri_ramecc_get_INTFLAG_DUALE_bit(const void *const hw) +{ + return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_DUALE) >> RAMECC_INTFLAG_DUALE_Pos; +} + +static inline void hri_ramecc_clear_INTFLAG_DUALE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_DUALE; +} + +static inline bool hri_ramecc_get_interrupt_SINGLEE_bit(const void *const hw) +{ + return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_SINGLEE) >> RAMECC_INTFLAG_SINGLEE_Pos; +} + +static inline void hri_ramecc_clear_interrupt_SINGLEE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_SINGLEE; +} + +static inline bool hri_ramecc_get_interrupt_DUALE_bit(const void *const hw) +{ + return (((Ramecc *)hw)->INTFLAG.reg & RAMECC_INTFLAG_DUALE) >> RAMECC_INTFLAG_DUALE_Pos; +} + +static inline void hri_ramecc_clear_interrupt_DUALE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTFLAG.reg = RAMECC_INTFLAG_DUALE; +} + +static inline hri_ramecc_intflag_reg_t hri_ramecc_get_INTFLAG_reg(const void *const hw, hri_ramecc_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ramecc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ramecc_intflag_reg_t hri_ramecc_read_INTFLAG_reg(const void *const hw) +{ + return ((Ramecc *)hw)->INTFLAG.reg; +} + +static inline void hri_ramecc_clear_INTFLAG_reg(const void *const hw, hri_ramecc_intflag_reg_t mask) +{ + ((Ramecc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_ramecc_set_INTEN_SINGLEE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_SINGLEE; +} + +static inline bool hri_ramecc_get_INTEN_SINGLEE_bit(const void *const hw) +{ + return (((Ramecc *)hw)->INTENSET.reg & RAMECC_INTENSET_SINGLEE) >> RAMECC_INTENSET_SINGLEE_Pos; +} + +static inline void hri_ramecc_write_INTEN_SINGLEE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_SINGLEE; + } else { + ((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_SINGLEE; + } +} + +static inline void hri_ramecc_clear_INTEN_SINGLEE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_SINGLEE; +} + +static inline void hri_ramecc_set_INTEN_DUALE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_DUALE; +} + +static inline bool hri_ramecc_get_INTEN_DUALE_bit(const void *const hw) +{ + return (((Ramecc *)hw)->INTENSET.reg & RAMECC_INTENSET_DUALE) >> RAMECC_INTENSET_DUALE_Pos; +} + +static inline void hri_ramecc_write_INTEN_DUALE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_DUALE; + } else { + ((Ramecc *)hw)->INTENSET.reg = RAMECC_INTENSET_DUALE; + } +} + +static inline void hri_ramecc_clear_INTEN_DUALE_bit(const void *const hw) +{ + ((Ramecc *)hw)->INTENCLR.reg = RAMECC_INTENSET_DUALE; +} + +static inline void hri_ramecc_set_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t mask) +{ + ((Ramecc *)hw)->INTENSET.reg = mask; +} + +static inline hri_ramecc_intenset_reg_t hri_ramecc_get_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ramecc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ramecc_intenset_reg_t hri_ramecc_read_INTEN_reg(const void *const hw) +{ + return ((Ramecc *)hw)->INTENSET.reg; +} + +static inline void hri_ramecc_write_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t data) +{ + ((Ramecc *)hw)->INTENSET.reg = data; + ((Ramecc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_ramecc_clear_INTEN_reg(const void *const hw, hri_ramecc_intenset_reg_t mask) +{ + ((Ramecc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_ramecc_get_STATUS_ECCDIS_bit(const void *const hw) +{ + return (((Ramecc *)hw)->STATUS.reg & RAMECC_STATUS_ECCDIS) >> RAMECC_STATUS_ECCDIS_Pos; +} + +static inline hri_ramecc_status_reg_t hri_ramecc_get_STATUS_reg(const void *const hw, hri_ramecc_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ramecc *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ramecc_status_reg_t hri_ramecc_read_STATUS_reg(const void *const hw) +{ + return ((Ramecc *)hw)->STATUS.reg; +} + +static inline hri_ramecc_erraddr_reg_t hri_ramecc_get_ERRADDR_ERRADDR_bf(const void *const hw, + hri_ramecc_erraddr_reg_t mask) +{ + return (((Ramecc *)hw)->ERRADDR.reg & RAMECC_ERRADDR_ERRADDR(mask)) >> RAMECC_ERRADDR_ERRADDR_Pos; +} + +static inline hri_ramecc_erraddr_reg_t hri_ramecc_read_ERRADDR_ERRADDR_bf(const void *const hw) +{ + return (((Ramecc *)hw)->ERRADDR.reg & RAMECC_ERRADDR_ERRADDR_Msk) >> RAMECC_ERRADDR_ERRADDR_Pos; +} + +static inline hri_ramecc_erraddr_reg_t hri_ramecc_get_ERRADDR_reg(const void *const hw, hri_ramecc_erraddr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Ramecc *)hw)->ERRADDR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_ramecc_erraddr_reg_t hri_ramecc_read_ERRADDR_reg(const void *const hw) +{ + return ((Ramecc *)hw)->ERRADDR.reg; +} + +static inline void hri_ramecc_set_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg |= RAMECC_DBGCTRL_ECCDIS; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ramecc_get_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ramecc *)hw)->DBGCTRL.reg; + tmp = (tmp & RAMECC_DBGCTRL_ECCDIS) >> RAMECC_DBGCTRL_ECCDIS_Pos; + return (bool)tmp; +} + +static inline void hri_ramecc_write_DBGCTRL_ECCDIS_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RAMECC_CRITICAL_SECTION_ENTER(); + tmp = ((Ramecc *)hw)->DBGCTRL.reg; + tmp &= ~RAMECC_DBGCTRL_ECCDIS; + tmp |= value << RAMECC_DBGCTRL_ECCDIS_Pos; + ((Ramecc *)hw)->DBGCTRL.reg = tmp; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_clear_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg &= ~RAMECC_DBGCTRL_ECCDIS; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_toggle_DBGCTRL_ECCDIS_bit(const void *const hw) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg ^= RAMECC_DBGCTRL_ECCDIS; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_set_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg |= RAMECC_DBGCTRL_ECCELOG; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_ramecc_get_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Ramecc *)hw)->DBGCTRL.reg; + tmp = (tmp & RAMECC_DBGCTRL_ECCELOG) >> RAMECC_DBGCTRL_ECCELOG_Pos; + return (bool)tmp; +} + +static inline void hri_ramecc_write_DBGCTRL_ECCELOG_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RAMECC_CRITICAL_SECTION_ENTER(); + tmp = ((Ramecc *)hw)->DBGCTRL.reg; + tmp &= ~RAMECC_DBGCTRL_ECCELOG; + tmp |= value << RAMECC_DBGCTRL_ECCELOG_Pos; + ((Ramecc *)hw)->DBGCTRL.reg = tmp; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_clear_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg &= ~RAMECC_DBGCTRL_ECCELOG; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_toggle_DBGCTRL_ECCELOG_bit(const void *const hw) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg ^= RAMECC_DBGCTRL_ECCELOG; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_set_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg |= mask; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ramecc_dbgctrl_reg_t hri_ramecc_get_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Ramecc *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_ramecc_write_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t data) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg = data; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_clear_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg &= ~mask; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_ramecc_toggle_DBGCTRL_reg(const void *const hw, hri_ramecc_dbgctrl_reg_t mask) +{ + RAMECC_CRITICAL_SECTION_ENTER(); + ((Ramecc *)hw)->DBGCTRL.reg ^= mask; + RAMECC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_ramecc_dbgctrl_reg_t hri_ramecc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Ramecc *)hw)->DBGCTRL.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_RAMECC_E54_H_INCLUDED */ +#endif /* _SAME54_RAMECC_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_rstc_e54.h b/software/firmware/oracle_same54n19a/hri/hri_rstc_e54.h new file mode 100644 index 00000000..bf5592a9 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_rstc_e54.h @@ -0,0 +1,142 @@ +/** + * \file + * + * \brief SAM RSTC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_RSTC_COMPONENT_ +#ifndef _HRI_RSTC_E54_H_INCLUDED_ +#define _HRI_RSTC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_RSTC_CRITICAL_SECTIONS) +#define RSTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define RSTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define RSTC_CRITICAL_SECTION_ENTER() +#define RSTC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint8_t hri_rstc_bkupexit_reg_t; +typedef uint8_t hri_rstc_rcause_reg_t; + +static inline bool hri_rstc_get_RCAUSE_POR_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_POR) >> RSTC_RCAUSE_POR_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_BODCORE_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODCORE) >> RSTC_RCAUSE_BODCORE_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_BODVDD_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BODVDD) >> RSTC_RCAUSE_BODVDD_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_NVM_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_NVM) >> RSTC_RCAUSE_NVM_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_EXT_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_EXT) >> RSTC_RCAUSE_EXT_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_WDT_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_WDT) >> RSTC_RCAUSE_WDT_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_SYST_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_SYST) >> RSTC_RCAUSE_SYST_Pos; +} + +static inline bool hri_rstc_get_RCAUSE_BACKUP_bit(const void *const hw) +{ + return (((Rstc *)hw)->RCAUSE.reg & RSTC_RCAUSE_BACKUP) >> RSTC_RCAUSE_BACKUP_Pos; +} + +static inline hri_rstc_rcause_reg_t hri_rstc_get_RCAUSE_reg(const void *const hw, hri_rstc_rcause_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rstc *)hw)->RCAUSE.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rstc_rcause_reg_t hri_rstc_read_RCAUSE_reg(const void *const hw) +{ + return ((Rstc *)hw)->RCAUSE.reg; +} + +static inline bool hri_rstc_get_BKUPEXIT_RTC_bit(const void *const hw) +{ + return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_RTC) >> RSTC_BKUPEXIT_RTC_Pos; +} + +static inline bool hri_rstc_get_BKUPEXIT_BBPS_bit(const void *const hw) +{ + return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_BBPS) >> RSTC_BKUPEXIT_BBPS_Pos; +} + +static inline bool hri_rstc_get_BKUPEXIT_HIB_bit(const void *const hw) +{ + return (((Rstc *)hw)->BKUPEXIT.reg & RSTC_BKUPEXIT_HIB) >> RSTC_BKUPEXIT_HIB_Pos; +} + +static inline hri_rstc_bkupexit_reg_t hri_rstc_get_BKUPEXIT_reg(const void *const hw, hri_rstc_bkupexit_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rstc *)hw)->BKUPEXIT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rstc_bkupexit_reg_t hri_rstc_read_BKUPEXIT_reg(const void *const hw) +{ + return ((Rstc *)hw)->BKUPEXIT.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_RSTC_E54_H_INCLUDED */ +#endif /* _SAME54_RSTC_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_rtc_e54.h b/software/firmware/oracle_same54n19a/hri/hri_rtc_e54.h new file mode 100644 index 00000000..2f2fa3b4 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_rtc_e54.h @@ -0,0 +1,10139 @@ +/** + * \file + * + * \brief SAM RTC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_RTC_COMPONENT_ +#ifndef _HRI_RTC_E54_H_INCLUDED_ +#define _HRI_RTC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_RTC_CRITICAL_SECTIONS) +#define RTC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define RTC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define RTC_CRITICAL_SECTION_ENTER() +#define RTC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_rtcmode0_ctrla_reg_t; +typedef uint16_t hri_rtcmode0_ctrlb_reg_t; +typedef uint16_t hri_rtcmode0_intenset_reg_t; +typedef uint16_t hri_rtcmode0_intflag_reg_t; +typedef uint16_t hri_rtcmode1_comp_reg_t; +typedef uint16_t hri_rtcmode1_count_reg_t; +typedef uint16_t hri_rtcmode1_ctrla_reg_t; +typedef uint16_t hri_rtcmode1_ctrlb_reg_t; +typedef uint16_t hri_rtcmode1_intenset_reg_t; +typedef uint16_t hri_rtcmode1_intflag_reg_t; +typedef uint16_t hri_rtcmode1_per_reg_t; +typedef uint16_t hri_rtcmode2_ctrla_reg_t; +typedef uint16_t hri_rtcmode2_ctrlb_reg_t; +typedef uint16_t hri_rtcmode2_intenset_reg_t; +typedef uint16_t hri_rtcmode2_intflag_reg_t; +typedef uint32_t hri_rtc_bkup_reg_t; +typedef uint32_t hri_rtc_gp_reg_t; +typedef uint32_t hri_rtc_tampctrl_reg_t; +typedef uint32_t hri_rtc_tampid_reg_t; +typedef uint32_t hri_rtcalarm_alarm_reg_t; +typedef uint32_t hri_rtcmode0_comp_reg_t; +typedef uint32_t hri_rtcmode0_count_reg_t; +typedef uint32_t hri_rtcmode0_evctrl_reg_t; +typedef uint32_t hri_rtcmode0_syncbusy_reg_t; +typedef uint32_t hri_rtcmode0_timestamp_reg_t; +typedef uint32_t hri_rtcmode1_evctrl_reg_t; +typedef uint32_t hri_rtcmode1_syncbusy_reg_t; +typedef uint32_t hri_rtcmode1_timestamp_reg_t; +typedef uint32_t hri_rtcmode2_alarm_reg_t; +typedef uint32_t hri_rtcmode2_clock_reg_t; +typedef uint32_t hri_rtcmode2_evctrl_reg_t; +typedef uint32_t hri_rtcmode2_syncbusy_reg_t; +typedef uint32_t hri_rtcmode2_timestamp_reg_t; +typedef uint8_t hri_rtc_dbgctrl_reg_t; +typedef uint8_t hri_rtc_freqcorr_reg_t; +typedef uint8_t hri_rtcalarm_mask_reg_t; +typedef uint8_t hri_rtcmode2_mask_reg_t; + +static inline void hri_rtcmode0_wait_for_sync(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg) +{ + while (((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_rtcmode0_is_syncing(const void *const hw, hri_rtcmode0_syncbusy_reg_t reg) +{ + return ((Rtc *)hw)->MODE0.SYNCBUSY.reg & reg; +} + +static inline void hri_rtcmode1_wait_for_sync(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg) +{ + while (((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_rtcmode1_is_syncing(const void *const hw, hri_rtcmode1_syncbusy_reg_t reg) +{ + return ((Rtc *)hw)->MODE1.SYNCBUSY.reg & reg; +} + +static inline void hri_rtcmode2_wait_for_sync(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg) +{ + while (((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_rtcmode2_is_syncing(const void *const hw, hri_rtcmode2_syncbusy_reg_t reg) +{ + return ((Rtc *)hw)->MODE2.SYNCBUSY.reg & reg; +} + +static inline void hri_rtcalarm_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_SECOND_Msk; + tmp |= RTC_MODE2_ALARM_SECOND(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk; + tmp |= RTC_MODE2_ALARM_MINUTE(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_HOUR_Msk; + tmp |= RTC_MODE2_ALARM_HOUR(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_DAY_Msk; + tmp |= RTC_MODE2_ALARM_DAY(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MONTH_Msk; + tmp |= RTC_MODE2_ALARM_MONTH(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_YEAR_Msk; + tmp |= RTC_MODE2_ALARM_YEAR(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_get_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcalarm_write_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcalarm_read_ALARM_reg(const void *const hw, uint8_t submodule_index) +{ + return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].ALARM.reg; +} + +static inline void hri_rtcalarm_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcalarm_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp &= ~RTC_MODE2_MASK_SEL_Msk; + tmp |= RTC_MODE2_MASK_SEL(data); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcalarm_set_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_get_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcalarm_write_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_clear_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcalarm_toggle_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcalarm_read_MASK_reg(const void *const hw, uint8_t submodule_index) +{ + return ((RtcMode2 *)hw)->Mode2Alarm[submodule_index].MASK.reg; +} + +static inline void hri_rtcmode2_set_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND(mask)) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_SECOND_Msk; + tmp |= RTC_MODE2_ALARM_SECOND(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_SECOND(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_SECOND_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_SECOND_Msk) >> RTC_MODE2_ALARM_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE(mask)) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MINUTE_Msk; + tmp |= RTC_MODE2_ALARM_MINUTE(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MINUTE(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MINUTE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MINUTE_Msk) >> RTC_MODE2_ALARM_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR(mask)) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_HOUR_Msk; + tmp |= RTC_MODE2_ALARM_HOUR(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_HOUR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_HOUR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_HOUR_Msk) >> RTC_MODE2_ALARM_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY(mask)) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_DAY_Msk; + tmp |= RTC_MODE2_ALARM_DAY(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_DAY(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_DAY_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_DAY_Msk) >> RTC_MODE2_ALARM_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH(mask)) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_MONTH_Msk; + tmp |= RTC_MODE2_ALARM_MONTH(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_MONTH(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_MONTH_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_MONTH_Msk) >> RTC_MODE2_ALARM_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR(mask)) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= ~RTC_MODE2_ALARM_YEAR_Msk; + tmp |= RTC_MODE2_ALARM_YEAR(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= RTC_MODE2_ALARM_YEAR(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_YEAR_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp = (tmp & RTC_MODE2_ALARM_YEAR_Msk) >> RTC_MODE2_ALARM_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_get_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_ALARM_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_alarm_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_alarm_reg_t hri_rtcmode2_read_ALARM_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].ALARM.reg; +} + +static inline void hri_rtcmode2_set_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL(mask)) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp &= ~RTC_MODE2_MASK_SEL_Msk; + tmp |= RTC_MODE2_MASK_SEL(data); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_MASK_SEL_bf(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= RTC_MODE2_MASK_SEL(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_SEL_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp = (tmp & RTC_MODE2_MASK_SEL_Msk) >> RTC_MODE2_MASK_SEL_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_get_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_MASK_reg(const void *const hw, uint8_t submodule_index, + hri_rtcmode2_mask_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_mask_reg_t hri_rtcmode2_read_MASK_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Rtc *)hw)->MODE2.Mode2Alarm[submodule_index].MASK.reg; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6; +} + +static inline bool hri_rtcmode0_get_INTFLAG_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7; +} + +static inline bool hri_rtcmode0_get_INTFLAG_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode0_get_INTFLAG_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP1) >> RTC_MODE0_INTFLAG_CMP1_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP1; +} + +static inline bool hri_rtcmode0_get_INTFLAG_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_TAMPER) >> RTC_MODE0_INTFLAG_TAMPER_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER; +} + +static inline bool hri_rtcmode0_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode0_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF; +} + +static inline bool hri_rtcmode0_get_interrupt_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER0) >> RTC_MODE0_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER0; +} + +static inline bool hri_rtcmode0_get_interrupt_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER1) >> RTC_MODE0_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER1; +} + +static inline bool hri_rtcmode0_get_interrupt_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER2) >> RTC_MODE0_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER2; +} + +static inline bool hri_rtcmode0_get_interrupt_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER3) >> RTC_MODE0_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER3; +} + +static inline bool hri_rtcmode0_get_interrupt_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER4) >> RTC_MODE0_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER4; +} + +static inline bool hri_rtcmode0_get_interrupt_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER5) >> RTC_MODE0_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER5; +} + +static inline bool hri_rtcmode0_get_interrupt_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER6) >> RTC_MODE0_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER6; +} + +static inline bool hri_rtcmode0_get_interrupt_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_PER7) >> RTC_MODE0_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_PER7; +} + +static inline bool hri_rtcmode0_get_interrupt_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP0) >> RTC_MODE0_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode0_get_interrupt_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_CMP1) >> RTC_MODE0_INTFLAG_CMP1_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_CMP1; +} + +static inline bool hri_rtcmode0_get_interrupt_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_TAMPER) >> RTC_MODE0_INTFLAG_TAMPER_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_TAMPER; +} + +static inline bool hri_rtcmode0_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTFLAG.reg & RTC_MODE0_INTFLAG_OVF) >> RTC_MODE0_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode0_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = RTC_MODE0_INTFLAG_OVF; +} + +static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_get_INTFLAG_reg(const void *const hw, + hri_rtcmode0_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_intflag_reg_t hri_rtcmode0_read_INTFLAG_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.INTFLAG.reg; +} + +static inline void hri_rtcmode0_clear_INTFLAG_reg(const void *const hw, hri_rtcmode0_intflag_reg_t mask) +{ + ((Rtc *)hw)->MODE0.INTFLAG.reg = mask; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6; +} + +static inline bool hri_rtcmode1_get_INTFLAG_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7; +} + +static inline bool hri_rtcmode1_get_INTFLAG_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode1_get_INTFLAG_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1; +} + +static inline bool hri_rtcmode1_get_INTFLAG_CMP2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP2) >> RTC_MODE1_INTFLAG_CMP2_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_CMP2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP2; +} + +static inline bool hri_rtcmode1_get_INTFLAG_CMP3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP3) >> RTC_MODE1_INTFLAG_CMP3_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_CMP3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP3; +} + +static inline bool hri_rtcmode1_get_INTFLAG_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_TAMPER) >> RTC_MODE1_INTFLAG_TAMPER_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_TAMPER; +} + +static inline bool hri_rtcmode1_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode1_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF; +} + +static inline bool hri_rtcmode1_get_interrupt_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER0) >> RTC_MODE1_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER0; +} + +static inline bool hri_rtcmode1_get_interrupt_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER1) >> RTC_MODE1_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER1; +} + +static inline bool hri_rtcmode1_get_interrupt_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER2) >> RTC_MODE1_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER2; +} + +static inline bool hri_rtcmode1_get_interrupt_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER3) >> RTC_MODE1_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER3; +} + +static inline bool hri_rtcmode1_get_interrupt_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER4) >> RTC_MODE1_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER4; +} + +static inline bool hri_rtcmode1_get_interrupt_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER5) >> RTC_MODE1_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER5; +} + +static inline bool hri_rtcmode1_get_interrupt_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER6) >> RTC_MODE1_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER6; +} + +static inline bool hri_rtcmode1_get_interrupt_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_PER7) >> RTC_MODE1_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_PER7; +} + +static inline bool hri_rtcmode1_get_interrupt_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP0) >> RTC_MODE1_INTFLAG_CMP0_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP0; +} + +static inline bool hri_rtcmode1_get_interrupt_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP1) >> RTC_MODE1_INTFLAG_CMP1_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP1; +} + +static inline bool hri_rtcmode1_get_interrupt_CMP2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP2) >> RTC_MODE1_INTFLAG_CMP2_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_CMP2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP2; +} + +static inline bool hri_rtcmode1_get_interrupt_CMP3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_CMP3) >> RTC_MODE1_INTFLAG_CMP3_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_CMP3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_CMP3; +} + +static inline bool hri_rtcmode1_get_interrupt_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_TAMPER) >> RTC_MODE1_INTFLAG_TAMPER_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_TAMPER; +} + +static inline bool hri_rtcmode1_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTFLAG.reg & RTC_MODE1_INTFLAG_OVF) >> RTC_MODE1_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode1_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = RTC_MODE1_INTFLAG_OVF; +} + +static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_get_INTFLAG_reg(const void *const hw, + hri_rtcmode1_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_intflag_reg_t hri_rtcmode1_read_INTFLAG_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.INTFLAG.reg; +} + +static inline void hri_rtcmode1_clear_INTFLAG_reg(const void *const hw, hri_rtcmode1_intflag_reg_t mask) +{ + ((Rtc *)hw)->MODE1.INTFLAG.reg = mask; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6; +} + +static inline bool hri_rtcmode2_get_INTFLAG_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7; +} + +static inline bool hri_rtcmode2_get_INTFLAG_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0; +} + +static inline bool hri_rtcmode2_get_INTFLAG_ALARM1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM1) >> RTC_MODE2_INTFLAG_ALARM1_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_ALARM1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM1; +} + +static inline bool hri_rtcmode2_get_INTFLAG_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_TAMPER) >> RTC_MODE2_INTFLAG_TAMPER_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER; +} + +static inline bool hri_rtcmode2_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode2_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF; +} + +static inline bool hri_rtcmode2_get_interrupt_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER0) >> RTC_MODE2_INTFLAG_PER0_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER0; +} + +static inline bool hri_rtcmode2_get_interrupt_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER1) >> RTC_MODE2_INTFLAG_PER1_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER1; +} + +static inline bool hri_rtcmode2_get_interrupt_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER2) >> RTC_MODE2_INTFLAG_PER2_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER2; +} + +static inline bool hri_rtcmode2_get_interrupt_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER3) >> RTC_MODE2_INTFLAG_PER3_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER3; +} + +static inline bool hri_rtcmode2_get_interrupt_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER4) >> RTC_MODE2_INTFLAG_PER4_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER4; +} + +static inline bool hri_rtcmode2_get_interrupt_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER5) >> RTC_MODE2_INTFLAG_PER5_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER5; +} + +static inline bool hri_rtcmode2_get_interrupt_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER6) >> RTC_MODE2_INTFLAG_PER6_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER6; +} + +static inline bool hri_rtcmode2_get_interrupt_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_PER7) >> RTC_MODE2_INTFLAG_PER7_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_PER7; +} + +static inline bool hri_rtcmode2_get_interrupt_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM0) >> RTC_MODE2_INTFLAG_ALARM0_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM0; +} + +static inline bool hri_rtcmode2_get_interrupt_ALARM1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_ALARM1) >> RTC_MODE2_INTFLAG_ALARM1_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_ALARM1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_ALARM1; +} + +static inline bool hri_rtcmode2_get_interrupt_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_TAMPER) >> RTC_MODE2_INTFLAG_TAMPER_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_TAMPER; +} + +static inline bool hri_rtcmode2_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTFLAG.reg & RTC_MODE2_INTFLAG_OVF) >> RTC_MODE2_INTFLAG_OVF_Pos; +} + +static inline void hri_rtcmode2_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = RTC_MODE2_INTFLAG_OVF; +} + +static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_get_INTFLAG_reg(const void *const hw, + hri_rtcmode2_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_intflag_reg_t hri_rtcmode2_read_INTFLAG_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.INTFLAG.reg; +} + +static inline void hri_rtcmode2_clear_INTFLAG_reg(const void *const hw, hri_rtcmode2_intflag_reg_t mask) +{ + ((Rtc *)hw)->MODE2.INTFLAG.reg = mask; +} + +static inline void hri_rtcmode0_set_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0; +} + +static inline bool hri_rtcmode0_get_INTEN_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER0) >> RTC_MODE0_INTENSET_PER0_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER0; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER0; +} + +static inline void hri_rtcmode0_set_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1; +} + +static inline bool hri_rtcmode0_get_INTEN_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER1) >> RTC_MODE0_INTENSET_PER1_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER1; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER1; +} + +static inline void hri_rtcmode0_set_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2; +} + +static inline bool hri_rtcmode0_get_INTEN_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER2) >> RTC_MODE0_INTENSET_PER2_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER2; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER2; +} + +static inline void hri_rtcmode0_set_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3; +} + +static inline bool hri_rtcmode0_get_INTEN_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER3) >> RTC_MODE0_INTENSET_PER3_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER3; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER3; +} + +static inline void hri_rtcmode0_set_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4; +} + +static inline bool hri_rtcmode0_get_INTEN_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER4) >> RTC_MODE0_INTENSET_PER4_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER4; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER4; +} + +static inline void hri_rtcmode0_set_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5; +} + +static inline bool hri_rtcmode0_get_INTEN_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER5) >> RTC_MODE0_INTENSET_PER5_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER5; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER5; +} + +static inline void hri_rtcmode0_set_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6; +} + +static inline bool hri_rtcmode0_get_INTEN_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER6) >> RTC_MODE0_INTENSET_PER6_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER6; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER6; +} + +static inline void hri_rtcmode0_set_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7; +} + +static inline bool hri_rtcmode0_get_INTEN_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_PER7) >> RTC_MODE0_INTENSET_PER7_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_PER7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_PER7; + } +} + +static inline void hri_rtcmode0_clear_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_PER7; +} + +static inline void hri_rtcmode0_set_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; +} + +static inline bool hri_rtcmode0_get_INTEN_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_CMP0) >> RTC_MODE0_INTENSET_CMP0_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_CMP0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP0; + } +} + +static inline void hri_rtcmode0_clear_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP0; +} + +static inline void hri_rtcmode0_set_INTEN_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP1; +} + +static inline bool hri_rtcmode0_get_INTEN_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_CMP1) >> RTC_MODE0_INTENSET_CMP1_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_CMP1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP1; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_CMP1; + } +} + +static inline void hri_rtcmode0_clear_INTEN_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_CMP1; +} + +static inline void hri_rtcmode0_set_INTEN_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_TAMPER; +} + +static inline bool hri_rtcmode0_get_INTEN_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_TAMPER) >> RTC_MODE0_INTENSET_TAMPER_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_TAMPER_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_TAMPER; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_TAMPER; + } +} + +static inline void hri_rtcmode0_clear_INTEN_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_TAMPER; +} + +static inline void hri_rtcmode0_set_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF; +} + +static inline bool hri_rtcmode0_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.INTENSET.reg & RTC_MODE0_INTENSET_OVF) >> RTC_MODE0_INTENSET_OVF_Pos; +} + +static inline void hri_rtcmode0_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF; + } else { + ((Rtc *)hw)->MODE0.INTENSET.reg = RTC_MODE0_INTENSET_OVF; + } +} + +static inline void hri_rtcmode0_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = RTC_MODE0_INTENSET_OVF; +} + +static inline void hri_rtcmode0_set_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = mask; +} + +static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_get_INTEN_reg(const void *const hw, + hri_rtcmode0_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_intenset_reg_t hri_rtcmode0_read_INTEN_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.INTENSET.reg; +} + +static inline void hri_rtcmode0_write_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t data) +{ + ((Rtc *)hw)->MODE0.INTENSET.reg = data; + ((Rtc *)hw)->MODE0.INTENCLR.reg = ~data; +} + +static inline void hri_rtcmode0_clear_INTEN_reg(const void *const hw, hri_rtcmode0_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE0.INTENCLR.reg = mask; +} + +static inline void hri_rtcmode1_set_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0; +} + +static inline bool hri_rtcmode1_get_INTEN_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER0) >> RTC_MODE1_INTENSET_PER0_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER0; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER0; +} + +static inline void hri_rtcmode1_set_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1; +} + +static inline bool hri_rtcmode1_get_INTEN_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER1) >> RTC_MODE1_INTENSET_PER1_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER1; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER1; +} + +static inline void hri_rtcmode1_set_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2; +} + +static inline bool hri_rtcmode1_get_INTEN_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER2) >> RTC_MODE1_INTENSET_PER2_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER2; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER2; +} + +static inline void hri_rtcmode1_set_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3; +} + +static inline bool hri_rtcmode1_get_INTEN_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER3) >> RTC_MODE1_INTENSET_PER3_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER3; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER3; +} + +static inline void hri_rtcmode1_set_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4; +} + +static inline bool hri_rtcmode1_get_INTEN_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER4) >> RTC_MODE1_INTENSET_PER4_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER4; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER4; +} + +static inline void hri_rtcmode1_set_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5; +} + +static inline bool hri_rtcmode1_get_INTEN_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER5) >> RTC_MODE1_INTENSET_PER5_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER5; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER5; +} + +static inline void hri_rtcmode1_set_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6; +} + +static inline bool hri_rtcmode1_get_INTEN_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER6) >> RTC_MODE1_INTENSET_PER6_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER6; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER6; +} + +static inline void hri_rtcmode1_set_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7; +} + +static inline bool hri_rtcmode1_get_INTEN_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_PER7) >> RTC_MODE1_INTENSET_PER7_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_PER7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_PER7; + } +} + +static inline void hri_rtcmode1_clear_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_PER7; +} + +static inline void hri_rtcmode1_set_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0; +} + +static inline bool hri_rtcmode1_get_INTEN_CMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP0) >> RTC_MODE1_INTENSET_CMP0_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_CMP0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP0; + } +} + +static inline void hri_rtcmode1_clear_INTEN_CMP0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP0; +} + +static inline void hri_rtcmode1_set_INTEN_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1; +} + +static inline bool hri_rtcmode1_get_INTEN_CMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP1) >> RTC_MODE1_INTENSET_CMP1_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_CMP1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP1; + } +} + +static inline void hri_rtcmode1_clear_INTEN_CMP1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP1; +} + +static inline void hri_rtcmode1_set_INTEN_CMP2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP2; +} + +static inline bool hri_rtcmode1_get_INTEN_CMP2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP2) >> RTC_MODE1_INTENSET_CMP2_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_CMP2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP2; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP2; + } +} + +static inline void hri_rtcmode1_clear_INTEN_CMP2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP2; +} + +static inline void hri_rtcmode1_set_INTEN_CMP3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP3; +} + +static inline bool hri_rtcmode1_get_INTEN_CMP3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_CMP3) >> RTC_MODE1_INTENSET_CMP3_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_CMP3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP3; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_CMP3; + } +} + +static inline void hri_rtcmode1_clear_INTEN_CMP3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_CMP3; +} + +static inline void hri_rtcmode1_set_INTEN_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_TAMPER; +} + +static inline bool hri_rtcmode1_get_INTEN_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_TAMPER) >> RTC_MODE1_INTENSET_TAMPER_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_TAMPER_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_TAMPER; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_TAMPER; + } +} + +static inline void hri_rtcmode1_clear_INTEN_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_TAMPER; +} + +static inline void hri_rtcmode1_set_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF; +} + +static inline bool hri_rtcmode1_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.INTENSET.reg & RTC_MODE1_INTENSET_OVF) >> RTC_MODE1_INTENSET_OVF_Pos; +} + +static inline void hri_rtcmode1_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF; + } else { + ((Rtc *)hw)->MODE1.INTENSET.reg = RTC_MODE1_INTENSET_OVF; + } +} + +static inline void hri_rtcmode1_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = RTC_MODE1_INTENSET_OVF; +} + +static inline void hri_rtcmode1_set_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = mask; +} + +static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_get_INTEN_reg(const void *const hw, + hri_rtcmode1_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_intenset_reg_t hri_rtcmode1_read_INTEN_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.INTENSET.reg; +} + +static inline void hri_rtcmode1_write_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t data) +{ + ((Rtc *)hw)->MODE1.INTENSET.reg = data; + ((Rtc *)hw)->MODE1.INTENCLR.reg = ~data; +} + +static inline void hri_rtcmode1_clear_INTEN_reg(const void *const hw, hri_rtcmode1_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE1.INTENCLR.reg = mask; +} + +static inline void hri_rtcmode2_set_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0; +} + +static inline bool hri_rtcmode2_get_INTEN_PER0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER0) >> RTC_MODE2_INTENSET_PER0_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER0; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER0; +} + +static inline void hri_rtcmode2_set_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1; +} + +static inline bool hri_rtcmode2_get_INTEN_PER1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER1) >> RTC_MODE2_INTENSET_PER1_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER1; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER1; +} + +static inline void hri_rtcmode2_set_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2; +} + +static inline bool hri_rtcmode2_get_INTEN_PER2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER2) >> RTC_MODE2_INTENSET_PER2_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER2; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER2_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER2; +} + +static inline void hri_rtcmode2_set_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3; +} + +static inline bool hri_rtcmode2_get_INTEN_PER3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER3) >> RTC_MODE2_INTENSET_PER3_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER3; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER3_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER3; +} + +static inline void hri_rtcmode2_set_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4; +} + +static inline bool hri_rtcmode2_get_INTEN_PER4_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER4) >> RTC_MODE2_INTENSET_PER4_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER4; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER4_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER4; +} + +static inline void hri_rtcmode2_set_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5; +} + +static inline bool hri_rtcmode2_get_INTEN_PER5_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER5) >> RTC_MODE2_INTENSET_PER5_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER5; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER5_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER5; +} + +static inline void hri_rtcmode2_set_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6; +} + +static inline bool hri_rtcmode2_get_INTEN_PER6_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER6) >> RTC_MODE2_INTENSET_PER6_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER6_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER6; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER6_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER6; +} + +static inline void hri_rtcmode2_set_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7; +} + +static inline bool hri_rtcmode2_get_INTEN_PER7_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_PER7) >> RTC_MODE2_INTENSET_PER7_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_PER7_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_PER7; + } +} + +static inline void hri_rtcmode2_clear_INTEN_PER7_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_PER7; +} + +static inline void hri_rtcmode2_set_INTEN_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; +} + +static inline bool hri_rtcmode2_get_INTEN_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_ALARM0) >> RTC_MODE2_INTENSET_ALARM0_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_ALARM0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM0; + } +} + +static inline void hri_rtcmode2_clear_INTEN_ALARM0_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM0; +} + +static inline void hri_rtcmode2_set_INTEN_ALARM1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM1; +} + +static inline bool hri_rtcmode2_get_INTEN_ALARM1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_ALARM1) >> RTC_MODE2_INTENSET_ALARM1_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_ALARM1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM1; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_ALARM1; + } +} + +static inline void hri_rtcmode2_clear_INTEN_ALARM1_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_ALARM1; +} + +static inline void hri_rtcmode2_set_INTEN_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_TAMPER; +} + +static inline bool hri_rtcmode2_get_INTEN_TAMPER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_TAMPER) >> RTC_MODE2_INTENSET_TAMPER_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_TAMPER_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_TAMPER; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_TAMPER; + } +} + +static inline void hri_rtcmode2_clear_INTEN_TAMPER_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_TAMPER; +} + +static inline void hri_rtcmode2_set_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF; +} + +static inline bool hri_rtcmode2_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.INTENSET.reg & RTC_MODE2_INTENSET_OVF) >> RTC_MODE2_INTENSET_OVF_Pos; +} + +static inline void hri_rtcmode2_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF; + } else { + ((Rtc *)hw)->MODE2.INTENSET.reg = RTC_MODE2_INTENSET_OVF; + } +} + +static inline void hri_rtcmode2_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = RTC_MODE2_INTENSET_OVF; +} + +static inline void hri_rtcmode2_set_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = mask; +} + +static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_get_INTEN_reg(const void *const hw, + hri_rtcmode2_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_intenset_reg_t hri_rtcmode2_read_INTEN_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.INTENSET.reg; +} + +static inline void hri_rtcmode2_write_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t data) +{ + ((Rtc *)hw)->MODE2.INTENSET.reg = data; + ((Rtc *)hw)->MODE2.INTENCLR.reg = ~data; +} + +static inline void hri_rtcmode2_clear_INTEN_reg(const void *const hw, hri_rtcmode2_intenset_reg_t mask) +{ + ((Rtc *)hw)->MODE2.INTENCLR.reg = mask; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_SWRST) >> RTC_MODE0_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_ENABLE) >> RTC_MODE0_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_FREQCORR_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_FREQCORR) >> RTC_MODE0_SYNCBUSY_FREQCORR_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNT) >> RTC_MODE0_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_COMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COMP0) >> RTC_MODE0_SYNCBUSY_COMP0_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_COMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COMP1) >> RTC_MODE0_SYNCBUSY_COMP1_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_COUNTSYNC) >> RTC_MODE0_SYNCBUSY_COUNTSYNC_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_GP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP0) >> RTC_MODE0_SYNCBUSY_GP0_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_GP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP1) >> RTC_MODE0_SYNCBUSY_GP1_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_GP2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP2) >> RTC_MODE0_SYNCBUSY_GP2_Pos; +} + +static inline bool hri_rtcmode0_get_SYNCBUSY_GP3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE0.SYNCBUSY.reg & RTC_MODE0_SYNCBUSY_GP3) >> RTC_MODE0_SYNCBUSY_GP3_Pos; +} + +static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_get_SYNCBUSY_reg(const void *const hw, + hri_rtcmode0_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_syncbusy_reg_t hri_rtcmode0_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.SYNCBUSY.reg; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_SWRST) >> RTC_MODE1_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_ENABLE) >> RTC_MODE1_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_FREQCORR_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_FREQCORR) >> RTC_MODE1_SYNCBUSY_FREQCORR_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNT) >> RTC_MODE1_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_PER_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_PER) >> RTC_MODE1_SYNCBUSY_PER_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COMP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP0) >> RTC_MODE1_SYNCBUSY_COMP0_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COMP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP1) >> RTC_MODE1_SYNCBUSY_COMP1_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COMP2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP2) >> RTC_MODE1_SYNCBUSY_COMP2_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COMP3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COMP3) >> RTC_MODE1_SYNCBUSY_COMP3_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_COUNTSYNC_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_COUNTSYNC) >> RTC_MODE1_SYNCBUSY_COUNTSYNC_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_GP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP0) >> RTC_MODE1_SYNCBUSY_GP0_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_GP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP1) >> RTC_MODE1_SYNCBUSY_GP1_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_GP2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP2) >> RTC_MODE1_SYNCBUSY_GP2_Pos; +} + +static inline bool hri_rtcmode1_get_SYNCBUSY_GP3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE1.SYNCBUSY.reg & RTC_MODE1_SYNCBUSY_GP3) >> RTC_MODE1_SYNCBUSY_GP3_Pos; +} + +static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_get_SYNCBUSY_reg(const void *const hw, + hri_rtcmode1_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_syncbusy_reg_t hri_rtcmode1_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.SYNCBUSY.reg; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_SWRST) >> RTC_MODE2_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ENABLE) >> RTC_MODE2_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_FREQCORR_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_FREQCORR) >> RTC_MODE2_SYNCBUSY_FREQCORR_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCK_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCK) >> RTC_MODE2_SYNCBUSY_CLOCK_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_ALARM0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ALARM0) >> RTC_MODE2_SYNCBUSY_ALARM0_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_ALARM1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_ALARM1) >> RTC_MODE2_SYNCBUSY_ALARM1_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_MASK0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_MASK0) >> RTC_MODE2_SYNCBUSY_MASK0_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_MASK1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_MASK1) >> RTC_MODE2_SYNCBUSY_MASK1_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_CLOCKSYNC_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_CLOCKSYNC) >> RTC_MODE2_SYNCBUSY_CLOCKSYNC_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_GP0_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP0) >> RTC_MODE2_SYNCBUSY_GP0_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_GP1_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP1) >> RTC_MODE2_SYNCBUSY_GP1_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_GP2_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP2) >> RTC_MODE2_SYNCBUSY_GP2_Pos; +} + +static inline bool hri_rtcmode2_get_SYNCBUSY_GP3_bit(const void *const hw) +{ + return (((Rtc *)hw)->MODE2.SYNCBUSY.reg & RTC_MODE2_SYNCBUSY_GP3) >> RTC_MODE2_SYNCBUSY_GP3_Pos; +} + +static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_get_SYNCBUSY_reg(const void *const hw, + hri_rtcmode2_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_syncbusy_reg_t hri_rtcmode2_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.SYNCBUSY.reg; +} + +static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_get_TIMESTAMP_COUNT_bf(const void *const hw, + hri_rtcmode0_timestamp_reg_t mask) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + return (((Rtc *)hw)->MODE0.TIMESTAMP.reg & RTC_MODE0_TIMESTAMP_COUNT(mask)) >> RTC_MODE0_TIMESTAMP_COUNT_Pos; +} + +static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_read_TIMESTAMP_COUNT_bf(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + return (((Rtc *)hw)->MODE0.TIMESTAMP.reg & RTC_MODE0_TIMESTAMP_COUNT_Msk) >> RTC_MODE0_TIMESTAMP_COUNT_Pos; +} + +static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_get_TIMESTAMP_reg(const void *const hw, + hri_rtcmode0_timestamp_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE0.TIMESTAMP.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode0_timestamp_reg_t hri_rtcmode0_read_TIMESTAMP_reg(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + return ((Rtc *)hw)->MODE0.TIMESTAMP.reg; +} + +static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_get_TIMESTAMP_COUNT_bf(const void *const hw, + hri_rtcmode1_timestamp_reg_t mask) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + return (((Rtc *)hw)->MODE1.TIMESTAMP.reg & RTC_MODE1_TIMESTAMP_COUNT(mask)) >> RTC_MODE1_TIMESTAMP_COUNT_Pos; +} + +static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_read_TIMESTAMP_COUNT_bf(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + return (((Rtc *)hw)->MODE1.TIMESTAMP.reg & RTC_MODE1_TIMESTAMP_COUNT_Msk) >> RTC_MODE1_TIMESTAMP_COUNT_Pos; +} + +static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_get_TIMESTAMP_reg(const void *const hw, + hri_rtcmode1_timestamp_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE1.TIMESTAMP.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode1_timestamp_reg_t hri_rtcmode1_read_TIMESTAMP_reg(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + return ((Rtc *)hw)->MODE1.TIMESTAMP.reg; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_SECOND_bf(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_SECOND(mask)) >> RTC_MODE2_TIMESTAMP_SECOND_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_SECOND_bf(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_SECOND_Msk) >> RTC_MODE2_TIMESTAMP_SECOND_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_MINUTE_bf(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MINUTE(mask)) >> RTC_MODE2_TIMESTAMP_MINUTE_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_MINUTE_bf(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MINUTE_Msk) >> RTC_MODE2_TIMESTAMP_MINUTE_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_HOUR_bf(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_HOUR(mask)) >> RTC_MODE2_TIMESTAMP_HOUR_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_HOUR_bf(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_HOUR_Msk) >> RTC_MODE2_TIMESTAMP_HOUR_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_DAY_bf(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_DAY(mask)) >> RTC_MODE2_TIMESTAMP_DAY_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_DAY_bf(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_DAY_Msk) >> RTC_MODE2_TIMESTAMP_DAY_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_MONTH_bf(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MONTH(mask)) >> RTC_MODE2_TIMESTAMP_MONTH_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_MONTH_bf(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_MONTH_Msk) >> RTC_MODE2_TIMESTAMP_MONTH_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_YEAR_bf(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_YEAR(mask)) >> RTC_MODE2_TIMESTAMP_YEAR_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_YEAR_bf(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return (((Rtc *)hw)->MODE2.TIMESTAMP.reg & RTC_MODE2_TIMESTAMP_YEAR_Msk) >> RTC_MODE2_TIMESTAMP_YEAR_Pos; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_get_TIMESTAMP_reg(const void *const hw, + hri_rtcmode2_timestamp_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.TIMESTAMP.reg; + tmp &= mask; + return tmp; +} + +static inline hri_rtcmode2_timestamp_reg_t hri_rtcmode2_read_TIMESTAMP_reg(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return ((Rtc *)hw)->MODE2.TIMESTAMP.reg; +} + +static inline void hri_rtcmode0_set_CTRLA_SWRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_SWRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_SWRST) >> RTC_MODE0_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_set_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_ENABLE; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_ENABLE) >> RTC_MODE0_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_ENABLE; + tmp |= value << RTC_MODE0_CTRLA_ENABLE_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_ENABLE; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_ENABLE; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MATCHCLR; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_MATCHCLR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_MATCHCLR) >> RTC_MODE0_CTRLA_MATCHCLR_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_MATCHCLR; + tmp |= value << RTC_MODE0_CTRLA_MATCHCLR_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MATCHCLR; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MATCHCLR; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_BKTRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_BKTRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_BKTRST) >> RTC_MODE0_CTRLA_BKTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_BKTRST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_BKTRST; + tmp |= value << RTC_MODE0_CTRLA_BKTRST_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_BKTRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_BKTRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_GPTRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_GPTRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_GPTRST) >> RTC_MODE0_CTRLA_GPTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_GPTRST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_GPTRST; + tmp |= value << RTC_MODE0_CTRLA_GPTRST_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_GPTRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_GPTRST; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_COUNTSYNC; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_COUNTSYNC) >> RTC_MODE0_CTRLA_COUNTSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_COUNTSYNC; + tmp |= value << RTC_MODE0_CTRLA_COUNTSYNC_Pos; + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_COUNTSYNC; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_COUNTSYNC; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_MODE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_MODE_bf(const void *const hw, + hri_rtcmode0_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_MODE(mask)) >> RTC_MODE0_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_MODE_Msk; + tmp |= RTC_MODE0_CTRLA_MODE(data); + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_MODE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_MODE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_MODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_MODE_Msk) >> RTC_MODE0_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= RTC_MODE0_CTRLA_PRESCALER(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_PRESCALER_bf(const void *const hw, + hri_rtcmode0_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER(mask)) >> RTC_MODE0_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= ~RTC_MODE0_CTRLA_PRESCALER_Msk; + tmp |= RTC_MODE0_CTRLA_PRESCALER(data); + ((Rtc *)hw)->MODE0.CTRLA.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~RTC_MODE0_CTRLA_PRESCALER(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= RTC_MODE0_CTRLA_PRESCALER(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp = (tmp & RTC_MODE0_CTRLA_PRESCALER_Msk) >> RTC_MODE0_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_get_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE0.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLA_reg(const void *const hw, hri_rtcmode0_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLA.reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrla_reg_t hri_rtcmode0_read_CTRLA_reg(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_SWRST | RTC_MODE0_SYNCBUSY_ENABLE | RTC_MODE0_SYNCBUSY_COUNTSYNC); + return ((Rtc *)hw)->MODE0.CTRLA.reg; +} + +static inline void hri_rtcmode1_set_CTRLA_SWRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_SWRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_SWRST) >> RTC_MODE1_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_set_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_ENABLE; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_ENABLE) >> RTC_MODE1_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_ENABLE; + tmp |= value << RTC_MODE1_CTRLA_ENABLE_Pos; + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_ENABLE; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_ENABLE; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_BKTRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_BKTRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_BKTRST) >> RTC_MODE1_CTRLA_BKTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_BKTRST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_BKTRST; + tmp |= value << RTC_MODE1_CTRLA_BKTRST_Pos; + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_BKTRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_BKTRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_GPTRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_GPTRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_GPTRST) >> RTC_MODE1_CTRLA_GPTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_GPTRST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_GPTRST; + tmp |= value << RTC_MODE1_CTRLA_GPTRST_Pos; + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_GPTRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_GPTRST; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_COUNTSYNC; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_COUNTSYNC) >> RTC_MODE1_CTRLA_COUNTSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_COUNTSYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_COUNTSYNC; + tmp |= value << RTC_MODE1_CTRLA_COUNTSYNC_Pos; + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_COUNTSYNC; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_COUNTSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_COUNTSYNC; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_MODE(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_MODE_bf(const void *const hw, + hri_rtcmode1_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_MODE(mask)) >> RTC_MODE1_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_MODE_Msk; + tmp |= RTC_MODE1_CTRLA_MODE(data); + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_MODE(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_MODE(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_MODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_MODE_Msk) >> RTC_MODE1_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= RTC_MODE1_CTRLA_PRESCALER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_PRESCALER_bf(const void *const hw, + hri_rtcmode1_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER(mask)) >> RTC_MODE1_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= ~RTC_MODE1_CTRLA_PRESCALER_Msk; + tmp |= RTC_MODE1_CTRLA_PRESCALER(data); + ((Rtc *)hw)->MODE1.CTRLA.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~RTC_MODE1_CTRLA_PRESCALER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= RTC_MODE1_CTRLA_PRESCALER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp = (tmp & RTC_MODE1_CTRLA_PRESCALER_Msk) >> RTC_MODE1_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg |= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_get_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + tmp = ((Rtc *)hw)->MODE1.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg = data; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg &= ~mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLA_reg(const void *const hw, hri_rtcmode1_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLA.reg ^= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrla_reg_t hri_rtcmode1_read_CTRLA_reg(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_SWRST | RTC_MODE1_SYNCBUSY_ENABLE | RTC_MODE1_SYNCBUSY_COUNTSYNC); + return ((Rtc *)hw)->MODE1.CTRLA.reg; +} + +static inline void hri_rtcmode2_set_CTRLA_SWRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_SWRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_SWRST) >> RTC_MODE2_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_set_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_ENABLE; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_ENABLE) >> RTC_MODE2_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_ENABLE; + tmp |= value << RTC_MODE2_CTRLA_ENABLE_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_ENABLE; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_ENABLE; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_CLKREP_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLKREP; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_CLKREP_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_CLKREP) >> RTC_MODE2_CTRLA_CLKREP_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_CLKREP_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_CLKREP; + tmp |= value << RTC_MODE2_CTRLA_CLKREP_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_CLKREP_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLKREP; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_CLKREP_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLKREP; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MATCHCLR; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_MATCHCLR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_MATCHCLR) >> RTC_MODE2_CTRLA_MATCHCLR_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_MATCHCLR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_MATCHCLR; + tmp |= value << RTC_MODE2_CTRLA_MATCHCLR_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MATCHCLR; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_MATCHCLR_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MATCHCLR; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_BKTRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_BKTRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_BKTRST) >> RTC_MODE2_CTRLA_BKTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_BKTRST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_BKTRST; + tmp |= value << RTC_MODE2_CTRLA_BKTRST_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_BKTRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_BKTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_BKTRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_GPTRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_GPTRST_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_GPTRST) >> RTC_MODE2_CTRLA_GPTRST_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_GPTRST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_GPTRST; + tmp |= value << RTC_MODE2_CTRLA_GPTRST_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_GPTRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_GPTRST_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_GPTRST; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_CLOCKSYNC; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_CLOCKSYNC) >> RTC_MODE2_CTRLA_CLOCKSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_CLOCKSYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_CLOCKSYNC; + tmp |= value << RTC_MODE2_CTRLA_CLOCKSYNC_Pos; + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_CLOCKSYNC; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_CLOCKSYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_CLOCKSYNC; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_MODE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_MODE_bf(const void *const hw, + hri_rtcmode2_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_MODE(mask)) >> RTC_MODE2_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_MODE_Msk; + tmp |= RTC_MODE2_CTRLA_MODE(data); + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_MODE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_MODE_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_MODE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_MODE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_MODE_Msk) >> RTC_MODE2_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= RTC_MODE2_CTRLA_PRESCALER(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_PRESCALER_bf(const void *const hw, + hri_rtcmode2_ctrla_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER(mask)) >> RTC_MODE2_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= ~RTC_MODE2_CTRLA_PRESCALER_Msk; + tmp |= RTC_MODE2_CTRLA_PRESCALER(data); + ((Rtc *)hw)->MODE2.CTRLA.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~RTC_MODE2_CTRLA_PRESCALER(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= RTC_MODE2_CTRLA_PRESCALER(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp = (tmp & RTC_MODE2_CTRLA_PRESCALER_Msk) >> RTC_MODE2_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg |= mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_get_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + tmp = ((Rtc *)hw)->MODE2.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg = data; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg &= ~mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLA_reg(const void *const hw, hri_rtcmode2_ctrla_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLA.reg ^= mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrla_reg_t hri_rtcmode2_read_CTRLA_reg(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_SWRST | RTC_MODE2_SYNCBUSY_ENABLE | RTC_MODE2_SYNCBUSY_CLOCKSYNC); + return ((Rtc *)hw)->MODE2.CTRLA.reg; +} + +static inline void hri_rtcmode0_set_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLB_GP0EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_GP0EN) >> RTC_MODE0_CTRLB_GP0EN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_GP0EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_GP0EN; + tmp |= value << RTC_MODE0_CTRLB_GP0EN_Pos; + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLB_GP2EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_GP2EN) >> RTC_MODE0_CTRLB_GP2EN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_GP2EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_GP2EN; + tmp |= value << RTC_MODE0_CTRLB_GP2EN_Pos; + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLB_DEBMAJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_DEBMAJ) >> RTC_MODE0_CTRLB_DEBMAJ_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_DEBMAJ; + tmp |= value << RTC_MODE0_CTRLB_DEBMAJ_Pos; + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLB_DEBASYNC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_DEBASYNC) >> RTC_MODE0_CTRLB_DEBASYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_DEBASYNC; + tmp |= value << RTC_MODE0_CTRLB_DEBASYNC_Pos; + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLB_RTCOUT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_RTCOUT) >> RTC_MODE0_CTRLB_RTCOUT_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_RTCOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_RTCOUT; + tmp |= value << RTC_MODE0_CTRLB_RTCOUT_Pos; + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_CTRLB_DMAEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_DMAEN) >> RTC_MODE0_CTRLB_DMAEN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_DMAEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_DMAEN; + tmp |= value << RTC_MODE0_CTRLB_DMAEN_Pos; + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_DEBF_bf(const void *const hw, + hri_rtcmode0_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_DEBF(mask)) >> RTC_MODE0_CTRLB_DEBF_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_DEBF_Msk; + tmp |= RTC_MODE0_CTRLB_DEBF(data); + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_DEBF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_DEBF_Msk) >> RTC_MODE0_CTRLB_DEBF_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= RTC_MODE0_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_ACTF_bf(const void *const hw, + hri_rtcmode0_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_ACTF(mask)) >> RTC_MODE0_CTRLB_ACTF_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= ~RTC_MODE0_CTRLB_ACTF_Msk; + tmp |= RTC_MODE0_CTRLB_ACTF(data); + ((Rtc *)hw)->MODE0.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~RTC_MODE0_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= RTC_MODE0_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_ACTF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp = (tmp & RTC_MODE0_CTRLB_ACTF_Msk) >> RTC_MODE0_CTRLB_ACTF_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_get_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE0.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_CTRLB_reg(const void *const hw, hri_rtcmode0_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.CTRLB.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_ctrlb_reg_t hri_rtcmode0_read_CTRLB_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.CTRLB.reg; +} + +static inline void hri_rtcmode1_set_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLB_GP0EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_GP0EN) >> RTC_MODE1_CTRLB_GP0EN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_GP0EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_GP0EN; + tmp |= value << RTC_MODE1_CTRLB_GP0EN_Pos; + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLB_GP2EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_GP2EN) >> RTC_MODE1_CTRLB_GP2EN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_GP2EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_GP2EN; + tmp |= value << RTC_MODE1_CTRLB_GP2EN_Pos; + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLB_DEBMAJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_DEBMAJ) >> RTC_MODE1_CTRLB_DEBMAJ_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_DEBMAJ; + tmp |= value << RTC_MODE1_CTRLB_DEBMAJ_Pos; + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLB_DEBASYNC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_DEBASYNC) >> RTC_MODE1_CTRLB_DEBASYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_DEBASYNC; + tmp |= value << RTC_MODE1_CTRLB_DEBASYNC_Pos; + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLB_RTCOUT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_RTCOUT) >> RTC_MODE1_CTRLB_RTCOUT_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_RTCOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_RTCOUT; + tmp |= value << RTC_MODE1_CTRLB_RTCOUT_Pos; + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_CTRLB_DMAEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_DMAEN) >> RTC_MODE1_CTRLB_DMAEN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_DMAEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_DMAEN; + tmp |= value << RTC_MODE1_CTRLB_DMAEN_Pos; + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_DEBF_bf(const void *const hw, + hri_rtcmode1_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_DEBF(mask)) >> RTC_MODE1_CTRLB_DEBF_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_DEBF_Msk; + tmp |= RTC_MODE1_CTRLB_DEBF(data); + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_DEBF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_DEBF_Msk) >> RTC_MODE1_CTRLB_DEBF_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= RTC_MODE1_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_ACTF_bf(const void *const hw, + hri_rtcmode1_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_ACTF(mask)) >> RTC_MODE1_CTRLB_ACTF_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= ~RTC_MODE1_CTRLB_ACTF_Msk; + tmp |= RTC_MODE1_CTRLB_ACTF(data); + ((Rtc *)hw)->MODE1.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~RTC_MODE1_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= RTC_MODE1_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_ACTF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp = (tmp & RTC_MODE1_CTRLB_ACTF_Msk) >> RTC_MODE1_CTRLB_ACTF_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_get_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_CTRLB_reg(const void *const hw, hri_rtcmode1_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.CTRLB.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_ctrlb_reg_t hri_rtcmode1_read_CTRLB_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.CTRLB.reg; +} + +static inline void hri_rtcmode2_set_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLB_GP0EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_GP0EN) >> RTC_MODE2_CTRLB_GP0EN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_GP0EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_GP0EN; + tmp |= value << RTC_MODE2_CTRLB_GP0EN_Pos; + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_GP0EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_GP0EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLB_GP2EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_GP2EN) >> RTC_MODE2_CTRLB_GP2EN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_GP2EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_GP2EN; + tmp |= value << RTC_MODE2_CTRLB_GP2EN_Pos; + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_GP2EN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_GP2EN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLB_DEBMAJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_DEBMAJ) >> RTC_MODE2_CTRLB_DEBMAJ_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_DEBMAJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_DEBMAJ; + tmp |= value << RTC_MODE2_CTRLB_DEBMAJ_Pos; + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_DEBMAJ_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBMAJ; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLB_DEBASYNC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_DEBASYNC) >> RTC_MODE2_CTRLB_DEBASYNC_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_DEBASYNC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_DEBASYNC; + tmp |= value << RTC_MODE2_CTRLB_DEBASYNC_Pos; + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_DEBASYNC_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBASYNC; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLB_RTCOUT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_RTCOUT) >> RTC_MODE2_CTRLB_RTCOUT_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_RTCOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_RTCOUT; + tmp |= value << RTC_MODE2_CTRLB_RTCOUT_Pos; + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_RTCOUT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_RTCOUT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_CTRLB_DMAEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_DMAEN) >> RTC_MODE2_CTRLB_DMAEN_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_DMAEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_DMAEN; + tmp |= value << RTC_MODE2_CTRLB_DMAEN_Pos; + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_DMAEN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DMAEN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_DEBF_bf(const void *const hw, + hri_rtcmode2_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_DEBF(mask)) >> RTC_MODE2_CTRLB_DEBF_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_DEBF_Msk; + tmp |= RTC_MODE2_CTRLB_DEBF(data); + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_DEBF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_DEBF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_DEBF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_DEBF_Msk) >> RTC_MODE2_CTRLB_DEBF_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= RTC_MODE2_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_ACTF_bf(const void *const hw, + hri_rtcmode2_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_ACTF(mask)) >> RTC_MODE2_CTRLB_ACTF_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= ~RTC_MODE2_CTRLB_ACTF_Msk; + tmp |= RTC_MODE2_CTRLB_ACTF(data); + ((Rtc *)hw)->MODE2.CTRLB.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~RTC_MODE2_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_ACTF_bf(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= RTC_MODE2_CTRLB_ACTF(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_ACTF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp = (tmp & RTC_MODE2_CTRLB_ACTF_Msk) >> RTC_MODE2_CTRLB_ACTF_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_get_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE2.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CTRLB_reg(const void *const hw, hri_rtcmode2_ctrlb_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CTRLB.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_ctrlb_reg_t hri_rtcmode2_read_CTRLB_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.CTRLB.reg; +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO0) >> RTC_MODE0_EVCTRL_PEREO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO0; + tmp |= value << RTC_MODE0_EVCTRL_PEREO0_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO1) >> RTC_MODE0_EVCTRL_PEREO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO1; + tmp |= value << RTC_MODE0_EVCTRL_PEREO1_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO2) >> RTC_MODE0_EVCTRL_PEREO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO2; + tmp |= value << RTC_MODE0_EVCTRL_PEREO2_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO3) >> RTC_MODE0_EVCTRL_PEREO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO3; + tmp |= value << RTC_MODE0_EVCTRL_PEREO3_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO4) >> RTC_MODE0_EVCTRL_PEREO4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO4; + tmp |= value << RTC_MODE0_EVCTRL_PEREO4_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO5) >> RTC_MODE0_EVCTRL_PEREO5_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO5; + tmp |= value << RTC_MODE0_EVCTRL_PEREO5_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO6) >> RTC_MODE0_EVCTRL_PEREO6_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO6; + tmp |= value << RTC_MODE0_EVCTRL_PEREO6_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_PEREO7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_PEREO7) >> RTC_MODE0_EVCTRL_PEREO7_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_PEREO7; + tmp |= value << RTC_MODE0_EVCTRL_PEREO7_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_CMPEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_CMPEO0) >> RTC_MODE0_EVCTRL_CMPEO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_CMPEO0; + tmp |= value << RTC_MODE0_EVCTRL_CMPEO0_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_CMPEO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_CMPEO1) >> RTC_MODE0_EVCTRL_CMPEO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_CMPEO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_CMPEO1; + tmp |= value << RTC_MODE0_EVCTRL_CMPEO1_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_TAMPEREO) >> RTC_MODE0_EVCTRL_TAMPEREO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_TAMPEREO; + tmp |= value << RTC_MODE0_EVCTRL_TAMPEREO_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_OVFEO) >> RTC_MODE0_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_OVFEO; + tmp |= value << RTC_MODE0_EVCTRL_OVFEO_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= RTC_MODE0_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode0_get_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp = (tmp & RTC_MODE0_EVCTRL_TAMPEVEI) >> RTC_MODE0_EVCTRL_TAMPEVEI_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= ~RTC_MODE0_EVCTRL_TAMPEVEI; + tmp |= value << RTC_MODE0_EVCTRL_TAMPEVEI_Pos; + ((Rtc *)hw)->MODE0.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~RTC_MODE0_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= RTC_MODE0_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_set_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_get_EVCTRL_reg(const void *const hw, + hri_rtcmode0_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode0_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.EVCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_evctrl_reg_t hri_rtcmode0_read_EVCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.EVCTRL.reg; +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO0) >> RTC_MODE1_EVCTRL_PEREO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO0; + tmp |= value << RTC_MODE1_EVCTRL_PEREO0_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO1) >> RTC_MODE1_EVCTRL_PEREO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO1; + tmp |= value << RTC_MODE1_EVCTRL_PEREO1_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO2) >> RTC_MODE1_EVCTRL_PEREO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO2; + tmp |= value << RTC_MODE1_EVCTRL_PEREO2_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO3) >> RTC_MODE1_EVCTRL_PEREO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO3; + tmp |= value << RTC_MODE1_EVCTRL_PEREO3_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO4) >> RTC_MODE1_EVCTRL_PEREO4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO4; + tmp |= value << RTC_MODE1_EVCTRL_PEREO4_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO5) >> RTC_MODE1_EVCTRL_PEREO5_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO5; + tmp |= value << RTC_MODE1_EVCTRL_PEREO5_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO6) >> RTC_MODE1_EVCTRL_PEREO6_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO6; + tmp |= value << RTC_MODE1_EVCTRL_PEREO6_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_PEREO7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_PEREO7) >> RTC_MODE1_EVCTRL_PEREO7_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_PEREO7; + tmp |= value << RTC_MODE1_EVCTRL_PEREO7_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_CMPEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO0) >> RTC_MODE1_EVCTRL_CMPEO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_CMPEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_CMPEO0; + tmp |= value << RTC_MODE1_EVCTRL_CMPEO0_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_CMPEO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO1) >> RTC_MODE1_EVCTRL_CMPEO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_CMPEO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_CMPEO1; + tmp |= value << RTC_MODE1_EVCTRL_CMPEO1_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_CMPEO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_CMPEO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO2) >> RTC_MODE1_EVCTRL_CMPEO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_CMPEO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_CMPEO2; + tmp |= value << RTC_MODE1_EVCTRL_CMPEO2_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_CMPEO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_CMPEO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_CMPEO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_CMPEO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_CMPEO3) >> RTC_MODE1_EVCTRL_CMPEO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_CMPEO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_CMPEO3; + tmp |= value << RTC_MODE1_EVCTRL_CMPEO3_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_CMPEO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_CMPEO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_CMPEO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_CMPEO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_TAMPEREO) >> RTC_MODE1_EVCTRL_TAMPEREO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_TAMPEREO; + tmp |= value << RTC_MODE1_EVCTRL_TAMPEREO_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_OVFEO) >> RTC_MODE1_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_OVFEO; + tmp |= value << RTC_MODE1_EVCTRL_OVFEO_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= RTC_MODE1_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode1_get_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp = (tmp & RTC_MODE1_EVCTRL_TAMPEVEI) >> RTC_MODE1_EVCTRL_TAMPEVEI_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= ~RTC_MODE1_EVCTRL_TAMPEVEI; + tmp |= value << RTC_MODE1_EVCTRL_TAMPEVEI_Pos; + ((Rtc *)hw)->MODE1.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~RTC_MODE1_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= RTC_MODE1_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_set_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_get_EVCTRL_reg(const void *const hw, + hri_rtcmode1_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE1.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode1_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.EVCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_evctrl_reg_t hri_rtcmode1_read_EVCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE1.EVCTRL.reg; +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO0) >> RTC_MODE2_EVCTRL_PEREO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO0; + tmp |= value << RTC_MODE2_EVCTRL_PEREO0_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO1) >> RTC_MODE2_EVCTRL_PEREO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO1; + tmp |= value << RTC_MODE2_EVCTRL_PEREO1_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO2) >> RTC_MODE2_EVCTRL_PEREO2_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO2; + tmp |= value << RTC_MODE2_EVCTRL_PEREO2_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO3) >> RTC_MODE2_EVCTRL_PEREO3_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO3; + tmp |= value << RTC_MODE2_EVCTRL_PEREO3_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO4) >> RTC_MODE2_EVCTRL_PEREO4_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO4; + tmp |= value << RTC_MODE2_EVCTRL_PEREO4_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO5) >> RTC_MODE2_EVCTRL_PEREO5_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO5; + tmp |= value << RTC_MODE2_EVCTRL_PEREO5_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO5_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO5; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO6) >> RTC_MODE2_EVCTRL_PEREO6_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO6; + tmp |= value << RTC_MODE2_EVCTRL_PEREO6_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO6_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO6; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_PEREO7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_PEREO7) >> RTC_MODE2_EVCTRL_PEREO7_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_PEREO7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_PEREO7; + tmp |= value << RTC_MODE2_EVCTRL_PEREO7_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_PEREO7_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_PEREO7; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_ALARMEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_ALARMEO0) >> RTC_MODE2_EVCTRL_ALARMEO0_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_ALARMEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_ALARMEO0; + tmp |= value << RTC_MODE2_EVCTRL_ALARMEO0_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_ALARMEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_ALARMEO0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_ALARMEO0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_ALARMEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_ALARMEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_ALARMEO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_ALARMEO1) >> RTC_MODE2_EVCTRL_ALARMEO1_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_ALARMEO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_ALARMEO1; + tmp |= value << RTC_MODE2_EVCTRL_ALARMEO1_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_ALARMEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_ALARMEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_ALARMEO1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_ALARMEO1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_TAMPEREO) >> RTC_MODE2_EVCTRL_TAMPEREO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_TAMPEREO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_TAMPEREO; + tmp |= value << RTC_MODE2_EVCTRL_TAMPEREO_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_TAMPEREO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_TAMPEREO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_OVFEO) >> RTC_MODE2_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_OVFEO; + tmp |= value << RTC_MODE2_EVCTRL_OVFEO_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_OVFEO; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= RTC_MODE2_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtcmode2_get_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp = (tmp & RTC_MODE2_EVCTRL_TAMPEVEI) >> RTC_MODE2_EVCTRL_TAMPEVEI_Pos; + return (bool)tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_TAMPEVEI_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= ~RTC_MODE2_EVCTRL_TAMPEVEI; + tmp |= value << RTC_MODE2_EVCTRL_TAMPEVEI_Pos; + ((Rtc *)hw)->MODE2.EVCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~RTC_MODE2_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_TAMPEVEI_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= RTC_MODE2_EVCTRL_TAMPEVEI; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_set_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_get_EVCTRL_reg(const void *const hw, + hri_rtcmode2_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE2.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_EVCTRL_reg(const void *const hw, hri_rtcmode2_evctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.EVCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_evctrl_reg_t hri_rtcmode2_read_EVCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE2.EVCTRL.reg; +} + +static inline void hri_rtc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg |= RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; + tmp = (tmp & RTC_DBGCTRL_DBGRUN) >> RTC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; + tmp &= ~RTC_DBGCTRL_DBGRUN; + tmp |= value << RTC_DBGCTRL_DBGRUN_Pos; + ((Rtc *)hw)->MODE0.DBGCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg ^= RTC_DBGCTRL_DBGRUN; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_dbgctrl_reg_t hri_rtc_get_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_DBGCTRL_reg(const void *const hw, hri_rtc_dbgctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.DBGCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_dbgctrl_reg_t hri_rtc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.DBGCTRL.reg; +} + +static inline void hri_rtc_set_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_SIGN; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_FREQCORR_SIGN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_SIGN) >> RTC_FREQCORR_SIGN_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_FREQCORR_SIGN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp &= ~RTC_FREQCORR_SIGN; + tmp |= value << RTC_FREQCORR_SIGN_Pos; + ((Rtc *)hw)->MODE0.FREQCORR.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_SIGN; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_FREQCORR_SIGN_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_SIGN; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg |= RTC_FREQCORR_VALUE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_freqcorr_reg_t hri_rtc_get_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_VALUE(mask)) >> RTC_FREQCORR_VALUE_Pos; + return tmp; +} + +static inline void hri_rtc_write_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t data) +{ + uint8_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp &= ~RTC_FREQCORR_VALUE_Msk; + tmp |= RTC_FREQCORR_VALUE(data); + ((Rtc *)hw)->MODE0.FREQCORR.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~RTC_FREQCORR_VALUE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_FREQCORR_VALUE_bf(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg ^= RTC_FREQCORR_VALUE(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_freqcorr_reg_t hri_rtc_read_FREQCORR_VALUE_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp = (tmp & RTC_FREQCORR_VALUE_Msk) >> RTC_FREQCORR_VALUE_Pos; + return tmp; +} + +static inline void hri_rtc_set_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_freqcorr_reg_t hri_rtc_get_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + uint8_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + tmp = ((Rtc *)hw)->MODE0.FREQCORR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_FREQCORR_reg(const void *const hw, hri_rtc_freqcorr_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.FREQCORR.reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_freqcorr_reg_t hri_rtc_read_FREQCORR_reg(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_MASK); + return ((Rtc *)hw)->MODE0.FREQCORR.reg; +} + +static inline void hri_rtcmode0_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg |= RTC_MODE0_COUNT_COUNT(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_COUNT_bf(const void *const hw, + hri_rtcmode0_count_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp = (tmp & RTC_MODE0_COUNT_COUNT(mask)) >> RTC_MODE0_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp &= ~RTC_MODE0_COUNT_COUNT_Msk; + tmp |= RTC_MODE0_COUNT_COUNT(data); + ((Rtc *)hw)->MODE0.COUNT.reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg &= ~RTC_MODE0_COUNT_COUNT(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg ^= RTC_MODE0_COUNT_COUNT(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp = (tmp & RTC_MODE0_COUNT_COUNT_Msk) >> RTC_MODE0_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_get_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE0.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COUNT_reg(const void *const hw, hri_rtcmode0_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COUNT.reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_count_reg_t hri_rtcmode0_read_COUNT_reg(const void *const hw) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COUNT); + return ((Rtc *)hw)->MODE0.COUNT.reg; +} + +static inline void hri_rtcmode1_set_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg |= RTC_MODE1_COUNT_COUNT(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_COUNT_bf(const void *const hw, + hri_rtcmode1_count_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp = (tmp & RTC_MODE1_COUNT_COUNT(mask)) >> RTC_MODE1_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp &= ~RTC_MODE1_COUNT_COUNT_Msk; + tmp |= RTC_MODE1_COUNT_COUNT(data); + ((Rtc *)hw)->MODE1.COUNT.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg &= ~RTC_MODE1_COUNT_COUNT(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COUNT_COUNT_bf(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg ^= RTC_MODE1_COUNT_COUNT(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_COUNT_bf(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp = (tmp & RTC_MODE1_COUNT_COUNT_Msk) >> RTC_MODE1_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg |= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_get_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + tmp = ((Rtc *)hw)->MODE1.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg = data; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg &= ~mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COUNT_reg(const void *const hw, hri_rtcmode1_count_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COUNT.reg ^= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_count_reg_t hri_rtcmode1_read_COUNT_reg(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_COUNT); + return ((Rtc *)hw)->MODE1.COUNT.reg; +} + +static inline void hri_rtcmode2_set_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_SECOND(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_SECOND_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_SECOND(mask)) >> RTC_MODE2_CLOCK_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_SECOND_Msk; + tmp |= RTC_MODE2_CLOCK_SECOND(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_SECOND(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_SECOND_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_SECOND(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_SECOND_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_SECOND_Msk) >> RTC_MODE2_CLOCK_SECOND_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MINUTE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MINUTE_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MINUTE(mask)) >> RTC_MODE2_CLOCK_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_MINUTE_Msk; + tmp |= RTC_MODE2_CLOCK_MINUTE(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MINUTE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_MINUTE_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MINUTE(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MINUTE_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MINUTE_Msk) >> RTC_MODE2_CLOCK_MINUTE_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_HOUR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_HOUR_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_HOUR(mask)) >> RTC_MODE2_CLOCK_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_HOUR_Msk; + tmp |= RTC_MODE2_CLOCK_HOUR(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_HOUR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_HOUR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_HOUR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_HOUR_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_HOUR_Msk) >> RTC_MODE2_CLOCK_HOUR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_DAY(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_DAY_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_DAY(mask)) >> RTC_MODE2_CLOCK_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_DAY_Msk; + tmp |= RTC_MODE2_CLOCK_DAY(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_DAY(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_DAY_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_DAY(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_DAY_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_DAY_Msk) >> RTC_MODE2_CLOCK_DAY_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_MONTH(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_MONTH_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MONTH(mask)) >> RTC_MODE2_CLOCK_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_MONTH_Msk; + tmp |= RTC_MODE2_CLOCK_MONTH(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_MONTH(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_MONTH_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_MONTH(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_MONTH_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_MONTH_Msk) >> RTC_MODE2_CLOCK_MONTH_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= RTC_MODE2_CLOCK_YEAR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_YEAR_bf(const void *const hw, + hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_YEAR(mask)) >> RTC_MODE2_CLOCK_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= ~RTC_MODE2_CLOCK_YEAR_Msk; + tmp |= RTC_MODE2_CLOCK_YEAR(data); + ((Rtc *)hw)->MODE2.CLOCK.reg = tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~RTC_MODE2_CLOCK_YEAR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_YEAR_bf(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= RTC_MODE2_CLOCK_YEAR(mask); + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_YEAR_bf(const void *const hw) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp = (tmp & RTC_MODE2_CLOCK_YEAR_Msk) >> RTC_MODE2_CLOCK_YEAR_Pos; + return tmp; +} + +static inline void hri_rtcmode2_set_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg |= mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_get_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + tmp = ((Rtc *)hw)->MODE2.CLOCK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode2_write_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg = data; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_clear_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg &= ~mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode2_toggle_CLOCK_reg(const void *const hw, hri_rtcmode2_clock_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE2.CLOCK.reg ^= mask; + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode2_clock_reg_t hri_rtcmode2_read_CLOCK_reg(const void *const hw) +{ + hri_rtcmode2_wait_for_sync(hw, RTC_MODE2_SYNCBUSY_MASK_); + return ((Rtc *)hw)->MODE2.CLOCK.reg; +} + +static inline void hri_rtcmode1_set_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg |= RTC_MODE1_PER_PER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp = (tmp & RTC_MODE1_PER_PER(mask)) >> RTC_MODE1_PER_PER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp &= ~RTC_MODE1_PER_PER_Msk; + tmp |= RTC_MODE1_PER_PER(data); + ((Rtc *)hw)->MODE1.PER.reg = tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg &= ~RTC_MODE1_PER_PER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_PER_PER_bf(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg ^= RTC_MODE1_PER_PER(mask); + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_PER_bf(const void *const hw) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp = (tmp & RTC_MODE1_PER_PER_Msk) >> RTC_MODE1_PER_PER_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg |= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_get_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + tmp = ((Rtc *)hw)->MODE1.PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg = data; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg &= ~mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_PER_reg(const void *const hw, hri_rtcmode1_per_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.PER.reg ^= mask; + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_per_reg_t hri_rtcmode1_read_PER_reg(const void *const hw) +{ + hri_rtcmode1_wait_for_sync(hw, RTC_MODE1_SYNCBUSY_PER); + return ((Rtc *)hw)->MODE1.PER.reg; +} + +static inline void hri_rtcmode0_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg |= RTC_MODE0_COMP_COMP(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_COMP_bf(const void *const hw, uint8_t index, + hri_rtcmode0_comp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp = (tmp & RTC_MODE0_COMP_COMP(mask)) >> RTC_MODE0_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode0_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp &= ~RTC_MODE0_COMP_COMP_Msk; + tmp |= RTC_MODE0_COMP_COMP(data); + ((Rtc *)hw)->MODE0.COMP[index].reg = tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg &= ~RTC_MODE0_COMP_COMP(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg ^= RTC_MODE0_COMP_COMP(mask); + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_COMP_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp = (tmp & RTC_MODE0_COMP_COMP_Msk) >> RTC_MODE0_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode0_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg |= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_get_COMP_reg(const void *const hw, uint8_t index, + hri_rtcmode0_comp_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + tmp = ((Rtc *)hw)->MODE0.COMP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode0_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg = data; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg &= ~mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode0_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode0_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.COMP[index].reg ^= mask; + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode0_comp_reg_t hri_rtcmode0_read_COMP_reg(const void *const hw, uint8_t index) +{ + hri_rtcmode0_wait_for_sync(hw, RTC_MODE0_SYNCBUSY_COMP0 | RTC_MODE0_SYNCBUSY_COMP1); + return ((Rtc *)hw)->MODE0.COMP[index].reg; +} + +static inline void hri_rtcmode1_set_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg |= RTC_MODE1_COMP_COMP(mask); + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_COMP_bf(const void *const hw, uint8_t index, + hri_rtcmode1_comp_reg_t mask) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp = (tmp & RTC_MODE1_COMP_COMP(mask)) >> RTC_MODE1_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode1_write_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data) +{ + uint16_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp &= ~RTC_MODE1_COMP_COMP_Msk; + tmp |= RTC_MODE1_COMP_COMP(data); + ((Rtc *)hw)->MODE1.COMP[index].reg = tmp; + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg &= ~RTC_MODE1_COMP_COMP(mask); + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COMP_COMP_bf(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg ^= RTC_MODE1_COMP_COMP(mask); + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_COMP_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp = (tmp & RTC_MODE1_COMP_COMP_Msk) >> RTC_MODE1_COMP_COMP_Pos; + return tmp; +} + +static inline void hri_rtcmode1_set_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg |= mask; + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_get_COMP_reg(const void *const hw, uint8_t index, + hri_rtcmode1_comp_reg_t mask) +{ + uint16_t tmp; + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + tmp = ((Rtc *)hw)->MODE1.COMP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtcmode1_write_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg = data; + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_clear_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg &= ~mask; + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtcmode1_toggle_COMP_reg(const void *const hw, uint8_t index, hri_rtcmode1_comp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE1.COMP[index].reg ^= mask; + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtcmode1_comp_reg_t hri_rtcmode1_read_COMP_reg(const void *const hw, uint8_t index) +{ + hri_rtcmode1_wait_for_sync( + hw, RTC_MODE1_SYNCBUSY_COMP0 | RTC_MODE1_SYNCBUSY_COMP1 | RTC_MODE1_SYNCBUSY_COMP2 | RTC_MODE1_SYNCBUSY_COMP3); + return ((Rtc *)hw)->MODE1.COMP[index].reg; +} + +static inline void hri_rtc_set_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg |= RTC_GP_GP(mask); + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_gp_reg_t hri_rtc_get_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.GP[index].reg; + tmp = (tmp & RTC_GP_GP(mask)) >> RTC_GP_GP_Pos; + return tmp; +} + +static inline void hri_rtc_write_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.GP[index].reg; + tmp &= ~RTC_GP_GP_Msk; + tmp |= RTC_GP_GP(data); + ((Rtc *)hw)->MODE0.GP[index].reg = tmp; + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg &= ~RTC_GP_GP(mask); + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_GP_GP_bf(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg ^= RTC_GP_GP(mask); + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_gp_reg_t hri_rtc_read_GP_GP_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.GP[index].reg; + tmp = (tmp & RTC_GP_GP_Msk) >> RTC_GP_GP_Pos; + return tmp; +} + +static inline void hri_rtc_set_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg |= mask; + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_gp_reg_t hri_rtc_get_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + uint32_t tmp; + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + tmp = ((Rtc *)hw)->MODE0.GP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg = data; + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg &= ~mask; + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_GP_reg(const void *const hw, uint8_t index, hri_rtc_gp_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.GP[index].reg ^= mask; + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_gp_reg_t hri_rtc_read_GP_reg(const void *const hw, uint8_t index) +{ + hri_rtcmode0_wait_for_sync( + hw, RTC_MODE0_SYNCBUSY_GP0 | RTC_MODE0_SYNCBUSY_GP1 | RTC_MODE0_SYNCBUSY_GP2 | RTC_MODE0_SYNCBUSY_GP3); + return ((Rtc *)hw)->MODE0.GP[index].reg; +} + +static inline void hri_rtc_set_TAMPCTRL_TAMLVL0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_TAMLVL0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL0) >> RTC_TAMPCTRL_TAMLVL0_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_TAMLVL0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL0; + tmp |= value << RTC_TAMPCTRL_TAMLVL0_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_TAMLVL1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_TAMLVL1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL1) >> RTC_TAMPCTRL_TAMLVL1_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_TAMLVL1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL1; + tmp |= value << RTC_TAMPCTRL_TAMLVL1_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_TAMLVL2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_TAMLVL2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL2) >> RTC_TAMPCTRL_TAMLVL2_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_TAMLVL2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL2; + tmp |= value << RTC_TAMPCTRL_TAMLVL2_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_TAMLVL3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_TAMLVL3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL3) >> RTC_TAMPCTRL_TAMLVL3_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_TAMLVL3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL3; + tmp |= value << RTC_TAMPCTRL_TAMLVL3_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_TAMLVL4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_TAMLVL4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_TAMLVL4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_TAMLVL4) >> RTC_TAMPCTRL_TAMLVL4_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_TAMLVL4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_TAMLVL4; + tmp |= value << RTC_TAMPCTRL_TAMLVL4_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_TAMLVL4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_TAMLVL4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_DEBNC0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_DEBNC0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC0) >> RTC_TAMPCTRL_DEBNC0_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_DEBNC0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC0; + tmp |= value << RTC_TAMPCTRL_DEBNC0_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_DEBNC0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_DEBNC1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_DEBNC1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC1) >> RTC_TAMPCTRL_DEBNC1_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_DEBNC1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC1; + tmp |= value << RTC_TAMPCTRL_DEBNC1_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_DEBNC1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_DEBNC2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_DEBNC2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC2) >> RTC_TAMPCTRL_DEBNC2_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_DEBNC2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC2; + tmp |= value << RTC_TAMPCTRL_DEBNC2_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_DEBNC2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_DEBNC3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_DEBNC3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC3) >> RTC_TAMPCTRL_DEBNC3_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_DEBNC3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC3; + tmp |= value << RTC_TAMPCTRL_DEBNC3_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_DEBNC3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_DEBNC4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_DEBNC4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPCTRL_DEBNC4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_DEBNC4) >> RTC_TAMPCTRL_DEBNC4_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_DEBNC4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_DEBNC4; + tmp |= value << RTC_TAMPCTRL_DEBNC4_Pos; + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_DEBNC4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_DEBNC4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_DEBNC4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN0ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN0ACT(mask)) >> RTC_TAMPCTRL_IN0ACT_Pos; + return tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN0ACT_Msk; + tmp |= RTC_TAMPCTRL_IN0ACT(data); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN0ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN0ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN0ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN0ACT_Msk) >> RTC_TAMPCTRL_IN0ACT_Pos; + return tmp; +} + +static inline void hri_rtc_set_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN1ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN1ACT(mask)) >> RTC_TAMPCTRL_IN1ACT_Pos; + return tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN1ACT_Msk; + tmp |= RTC_TAMPCTRL_IN1ACT(data); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN1ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN1ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN1ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN1ACT_Msk) >> RTC_TAMPCTRL_IN1ACT_Pos; + return tmp; +} + +static inline void hri_rtc_set_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN2ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN2ACT(mask)) >> RTC_TAMPCTRL_IN2ACT_Pos; + return tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN2ACT_Msk; + tmp |= RTC_TAMPCTRL_IN2ACT(data); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN2ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN2ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN2ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN2ACT_Msk) >> RTC_TAMPCTRL_IN2ACT_Pos; + return tmp; +} + +static inline void hri_rtc_set_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN3ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN3ACT(mask)) >> RTC_TAMPCTRL_IN3ACT_Pos; + return tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN3ACT_Msk; + tmp |= RTC_TAMPCTRL_IN3ACT(data); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN3ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN3ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN3ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN3ACT_Msk) >> RTC_TAMPCTRL_IN3ACT_Pos; + return tmp; +} + +static inline void hri_rtc_set_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= RTC_TAMPCTRL_IN4ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN4ACT(mask)) >> RTC_TAMPCTRL_IN4ACT_Pos; + return tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= ~RTC_TAMPCTRL_IN4ACT_Msk; + tmp |= RTC_TAMPCTRL_IN4ACT(data); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~RTC_TAMPCTRL_IN4ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= RTC_TAMPCTRL_IN4ACT(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_IN4ACT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp = (tmp & RTC_TAMPCTRL_IN4ACT_Msk) >> RTC_TAMPCTRL_IN4ACT_Pos; + return tmp; +} + +static inline void hri_rtc_set_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_get_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPCTRL_reg(const void *const hw, hri_rtc_tampctrl_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPCTRL.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampctrl_reg_t hri_rtc_read_TAMPCTRL_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.TAMPCTRL.reg; +} + +static inline void hri_rtc_set_TAMPID_TAMPID0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPID_TAMPID0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID0) >> RTC_TAMPID_TAMPID0_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPID_TAMPID0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID0; + tmp |= value << RTC_TAMPID_TAMPID0_Pos; + ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPID_TAMPID0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPID_TAMPID0_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID0; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPID_TAMPID1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPID_TAMPID1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID1) >> RTC_TAMPID_TAMPID1_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPID_TAMPID1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID1; + tmp |= value << RTC_TAMPID_TAMPID1_Pos; + ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPID_TAMPID1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPID_TAMPID1_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID1; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPID_TAMPID2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPID_TAMPID2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID2) >> RTC_TAMPID_TAMPID2_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPID_TAMPID2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID2; + tmp |= value << RTC_TAMPID_TAMPID2_Pos; + ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPID_TAMPID2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPID_TAMPID2_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID2; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPID_TAMPID3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPID_TAMPID3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID3) >> RTC_TAMPID_TAMPID3_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPID_TAMPID3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID3; + tmp |= value << RTC_TAMPID_TAMPID3_Pos; + ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPID_TAMPID3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPID_TAMPID3_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID3; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPID_TAMPID4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPID4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPID_TAMPID4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPID4) >> RTC_TAMPID_TAMPID4_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPID_TAMPID4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPID4; + tmp |= value << RTC_TAMPID_TAMPID4_Pos; + ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPID_TAMPID4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPID4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPID_TAMPID4_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPID4; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPID_TAMPEVT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= RTC_TAMPID_TAMPEVT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_rtc_get_TAMPID_TAMPEVT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp = (tmp & RTC_TAMPID_TAMPEVT) >> RTC_TAMPID_TAMPEVT_Pos; + return (bool)tmp; +} + +static inline void hri_rtc_write_TAMPID_TAMPEVT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= ~RTC_TAMPID_TAMPEVT; + tmp |= value << RTC_TAMPID_TAMPEVT_Pos; + ((Rtc *)hw)->MODE0.TAMPID.reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPID_TAMPEVT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~RTC_TAMPID_TAMPEVT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPID_TAMPEVT_bit(const void *const hw) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= RTC_TAMPID_TAMPEVT; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_set_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampid_reg_t hri_rtc_get_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.TAMPID.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_TAMPID_reg(const void *const hw, hri_rtc_tampid_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.TAMPID.reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_tampid_reg_t hri_rtc_read_TAMPID_reg(const void *const hw) +{ + return ((Rtc *)hw)->MODE0.TAMPID.reg; +} + +static inline void hri_rtc_set_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg |= RTC_BKUP_BKUP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_bkup_reg_t hri_rtc_get_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; + tmp = (tmp & RTC_BKUP_BKUP(mask)) >> RTC_BKUP_BKUP_Pos; + return tmp; +} + +static inline void hri_rtc_write_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t data) +{ + uint32_t tmp; + RTC_CRITICAL_SECTION_ENTER(); + tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; + tmp &= ~RTC_BKUP_BKUP_Msk; + tmp |= RTC_BKUP_BKUP(data); + ((Rtc *)hw)->MODE0.BKUP[index].reg = tmp; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg &= ~RTC_BKUP_BKUP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_BKUP_BKUP_bf(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg ^= RTC_BKUP_BKUP(mask); + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_bkup_reg_t hri_rtc_read_BKUP_BKUP_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; + tmp = (tmp & RTC_BKUP_BKUP_Msk) >> RTC_BKUP_BKUP_Pos; + return tmp; +} + +static inline void hri_rtc_set_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg |= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_bkup_reg_t hri_rtc_get_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + uint32_t tmp; + tmp = ((Rtc *)hw)->MODE0.BKUP[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_rtc_write_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t data) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg = data; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_clear_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg &= ~mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_rtc_toggle_BKUP_reg(const void *const hw, uint8_t index, hri_rtc_bkup_reg_t mask) +{ + RTC_CRITICAL_SECTION_ENTER(); + ((Rtc *)hw)->MODE0.BKUP[index].reg ^= mask; + RTC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_rtc_bkup_reg_t hri_rtc_read_BKUP_reg(const void *const hw, uint8_t index) +{ + return ((Rtc *)hw)->MODE0.BKUP[index].reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_rtcmode2_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode2_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode2_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b) +#define hri_rtcmode2_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode2_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode2_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b) +#define hri_rtcmode2_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b) +#define hri_rtcmode2_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b) +#define hri_rtcmode2_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b) +#define hri_rtcmode2_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b) +#define hri_rtcmode2_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a) +#define hri_rtcmode2_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a) +#define hri_rtcmode2_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a) +#define hri_rtcmode2_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b) +#define hri_rtcmode2_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a) +#define hri_rtcmode2_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a) +#define hri_rtcmode2_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode2_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a) +#define hri_rtcmode2_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b) +#define hri_rtcmode2_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b) +#define hri_rtcmode2_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b) +#define hri_rtcmode2_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b) +#define hri_rtcmode2_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b) +#define hri_rtcmode2_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a) +#define hri_rtcmode2_set_GP_GP_bf(a, b, c) hri_rtc_set_GP_GP_bf(a, b, c) +#define hri_rtcmode2_get_GP_GP_bf(a, b, c) hri_rtc_get_GP_GP_bf(a, b, c) +#define hri_rtcmode2_write_GP_GP_bf(a, b, c) hri_rtc_write_GP_GP_bf(a, b, c) +#define hri_rtcmode2_clear_GP_GP_bf(a, b, c) hri_rtc_clear_GP_GP_bf(a, b, c) +#define hri_rtcmode2_toggle_GP_GP_bf(a, b, c) hri_rtc_toggle_GP_GP_bf(a, b, c) +#define hri_rtcmode2_read_GP_GP_bf(a, b) hri_rtc_read_GP_GP_bf(a, b) +#define hri_rtcmode2_set_GP_reg(a, b, c) hri_rtc_set_GP_reg(a, b, c) +#define hri_rtcmode2_get_GP_reg(a, b, c) hri_rtc_get_GP_reg(a, b, c) +#define hri_rtcmode2_write_GP_reg(a, b, c) hri_rtc_write_GP_reg(a, b, c) +#define hri_rtcmode2_clear_GP_reg(a, b, c) hri_rtc_clear_GP_reg(a, b, c) +#define hri_rtcmode2_toggle_GP_reg(a, b, c) hri_rtc_toggle_GP_reg(a, b, c) +#define hri_rtcmode2_read_GP_reg(a, b) hri_rtc_read_GP_reg(a, b) +#define hri_rtcmode2_set_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_TAMLVL0_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL0_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_TAMLVL1_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL1_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_TAMLVL2_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL2_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_TAMLVL3_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL3_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_TAMLVL4_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL4_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_DEBNC0_bit(a) hri_rtc_set_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_DEBNC0_bit(a) hri_rtc_get_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_DEBNC0_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC0_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_DEBNC0_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC0_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_DEBNC1_bit(a) hri_rtc_set_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_DEBNC1_bit(a) hri_rtc_get_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_DEBNC1_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC1_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_DEBNC1_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC1_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_DEBNC2_bit(a) hri_rtc_set_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_DEBNC2_bit(a) hri_rtc_get_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_DEBNC2_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC2_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_DEBNC2_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC2_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_DEBNC3_bit(a) hri_rtc_set_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_DEBNC3_bit(a) hri_rtc_get_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_DEBNC3_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC3_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_DEBNC3_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC3_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_DEBNC4_bit(a) hri_rtc_set_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode2_get_TAMPCTRL_DEBNC4_bit(a) hri_rtc_get_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode2_write_TAMPCTRL_DEBNC4_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC4_bit(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_DEBNC4_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode2_toggle_TAMPCTRL_DEBNC4_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode2_set_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode2_get_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode2_write_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode2_toggle_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode2_read_TAMPCTRL_IN0ACT_bf(a) hri_rtc_read_TAMPCTRL_IN0ACT_bf(a) +#define hri_rtcmode2_set_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode2_get_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode2_write_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode2_toggle_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode2_read_TAMPCTRL_IN1ACT_bf(a) hri_rtc_read_TAMPCTRL_IN1ACT_bf(a) +#define hri_rtcmode2_set_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode2_get_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode2_write_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode2_toggle_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode2_read_TAMPCTRL_IN2ACT_bf(a) hri_rtc_read_TAMPCTRL_IN2ACT_bf(a) +#define hri_rtcmode2_set_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode2_get_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode2_write_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode2_toggle_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode2_read_TAMPCTRL_IN3ACT_bf(a) hri_rtc_read_TAMPCTRL_IN3ACT_bf(a) +#define hri_rtcmode2_set_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode2_get_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode2_write_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode2_toggle_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode2_read_TAMPCTRL_IN4ACT_bf(a) hri_rtc_read_TAMPCTRL_IN4ACT_bf(a) +#define hri_rtcmode2_set_TAMPCTRL_reg(a, b) hri_rtc_set_TAMPCTRL_reg(a, b) +#define hri_rtcmode2_get_TAMPCTRL_reg(a, b) hri_rtc_get_TAMPCTRL_reg(a, b) +#define hri_rtcmode2_write_TAMPCTRL_reg(a, b) hri_rtc_write_TAMPCTRL_reg(a, b) +#define hri_rtcmode2_clear_TAMPCTRL_reg(a, b) hri_rtc_clear_TAMPCTRL_reg(a, b) +#define hri_rtcmode2_toggle_TAMPCTRL_reg(a, b) hri_rtc_toggle_TAMPCTRL_reg(a, b) +#define hri_rtcmode2_read_TAMPCTRL_reg(a) hri_rtc_read_TAMPCTRL_reg(a) +#define hri_rtcmode2_set_TAMPID_TAMPID0_bit(a) hri_rtc_set_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode2_get_TAMPID_TAMPID0_bit(a) hri_rtc_get_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode2_write_TAMPID_TAMPID0_bit(a, b) hri_rtc_write_TAMPID_TAMPID0_bit(a, b) +#define hri_rtcmode2_clear_TAMPID_TAMPID0_bit(a) hri_rtc_clear_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode2_toggle_TAMPID_TAMPID0_bit(a) hri_rtc_toggle_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode2_set_TAMPID_TAMPID1_bit(a) hri_rtc_set_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode2_get_TAMPID_TAMPID1_bit(a) hri_rtc_get_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode2_write_TAMPID_TAMPID1_bit(a, b) hri_rtc_write_TAMPID_TAMPID1_bit(a, b) +#define hri_rtcmode2_clear_TAMPID_TAMPID1_bit(a) hri_rtc_clear_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode2_toggle_TAMPID_TAMPID1_bit(a) hri_rtc_toggle_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode2_set_TAMPID_TAMPID2_bit(a) hri_rtc_set_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode2_get_TAMPID_TAMPID2_bit(a) hri_rtc_get_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode2_write_TAMPID_TAMPID2_bit(a, b) hri_rtc_write_TAMPID_TAMPID2_bit(a, b) +#define hri_rtcmode2_clear_TAMPID_TAMPID2_bit(a) hri_rtc_clear_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode2_toggle_TAMPID_TAMPID2_bit(a) hri_rtc_toggle_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode2_set_TAMPID_TAMPID3_bit(a) hri_rtc_set_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode2_get_TAMPID_TAMPID3_bit(a) hri_rtc_get_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode2_write_TAMPID_TAMPID3_bit(a, b) hri_rtc_write_TAMPID_TAMPID3_bit(a, b) +#define hri_rtcmode2_clear_TAMPID_TAMPID3_bit(a) hri_rtc_clear_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode2_toggle_TAMPID_TAMPID3_bit(a) hri_rtc_toggle_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode2_set_TAMPID_TAMPID4_bit(a) hri_rtc_set_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode2_get_TAMPID_TAMPID4_bit(a) hri_rtc_get_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode2_write_TAMPID_TAMPID4_bit(a, b) hri_rtc_write_TAMPID_TAMPID4_bit(a, b) +#define hri_rtcmode2_clear_TAMPID_TAMPID4_bit(a) hri_rtc_clear_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode2_toggle_TAMPID_TAMPID4_bit(a) hri_rtc_toggle_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode2_set_TAMPID_TAMPEVT_bit(a) hri_rtc_set_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode2_get_TAMPID_TAMPEVT_bit(a) hri_rtc_get_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode2_write_TAMPID_TAMPEVT_bit(a, b) hri_rtc_write_TAMPID_TAMPEVT_bit(a, b) +#define hri_rtcmode2_clear_TAMPID_TAMPEVT_bit(a) hri_rtc_clear_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode2_toggle_TAMPID_TAMPEVT_bit(a) hri_rtc_toggle_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode2_set_TAMPID_reg(a, b) hri_rtc_set_TAMPID_reg(a, b) +#define hri_rtcmode2_get_TAMPID_reg(a, b) hri_rtc_get_TAMPID_reg(a, b) +#define hri_rtcmode2_write_TAMPID_reg(a, b) hri_rtc_write_TAMPID_reg(a, b) +#define hri_rtcmode2_clear_TAMPID_reg(a, b) hri_rtc_clear_TAMPID_reg(a, b) +#define hri_rtcmode2_toggle_TAMPID_reg(a, b) hri_rtc_toggle_TAMPID_reg(a, b) +#define hri_rtcmode2_read_TAMPID_reg(a) hri_rtc_read_TAMPID_reg(a) +#define hri_rtcmode2_set_BKUP_BKUP_bf(a, b, c) hri_rtc_set_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode2_get_BKUP_BKUP_bf(a, b, c) hri_rtc_get_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode2_write_BKUP_BKUP_bf(a, b, c) hri_rtc_write_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode2_clear_BKUP_BKUP_bf(a, b, c) hri_rtc_clear_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode2_toggle_BKUP_BKUP_bf(a, b, c) hri_rtc_toggle_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode2_read_BKUP_BKUP_bf(a, b) hri_rtc_read_BKUP_BKUP_bf(a, b) +#define hri_rtcmode2_set_BKUP_reg(a, b, c) hri_rtc_set_BKUP_reg(a, b, c) +#define hri_rtcmode2_get_BKUP_reg(a, b, c) hri_rtc_get_BKUP_reg(a, b, c) +#define hri_rtcmode2_write_BKUP_reg(a, b, c) hri_rtc_write_BKUP_reg(a, b, c) +#define hri_rtcmode2_clear_BKUP_reg(a, b, c) hri_rtc_clear_BKUP_reg(a, b, c) +#define hri_rtcmode2_toggle_BKUP_reg(a, b, c) hri_rtc_toggle_BKUP_reg(a, b, c) +#define hri_rtcmode2_read_BKUP_reg(a, b) hri_rtc_read_BKUP_reg(a, b) +#define hri_rtcmode0_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode0_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode0_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b) +#define hri_rtcmode0_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode0_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode0_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b) +#define hri_rtcmode0_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b) +#define hri_rtcmode0_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b) +#define hri_rtcmode0_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b) +#define hri_rtcmode0_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b) +#define hri_rtcmode0_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a) +#define hri_rtcmode0_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a) +#define hri_rtcmode0_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a) +#define hri_rtcmode0_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b) +#define hri_rtcmode0_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a) +#define hri_rtcmode0_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a) +#define hri_rtcmode0_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode0_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a) +#define hri_rtcmode0_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b) +#define hri_rtcmode0_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b) +#define hri_rtcmode0_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b) +#define hri_rtcmode0_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b) +#define hri_rtcmode0_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b) +#define hri_rtcmode0_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a) +#define hri_rtcmode0_set_GP_GP_bf(a, b, c) hri_rtc_set_GP_GP_bf(a, b, c) +#define hri_rtcmode0_get_GP_GP_bf(a, b, c) hri_rtc_get_GP_GP_bf(a, b, c) +#define hri_rtcmode0_write_GP_GP_bf(a, b, c) hri_rtc_write_GP_GP_bf(a, b, c) +#define hri_rtcmode0_clear_GP_GP_bf(a, b, c) hri_rtc_clear_GP_GP_bf(a, b, c) +#define hri_rtcmode0_toggle_GP_GP_bf(a, b, c) hri_rtc_toggle_GP_GP_bf(a, b, c) +#define hri_rtcmode0_read_GP_GP_bf(a, b) hri_rtc_read_GP_GP_bf(a, b) +#define hri_rtcmode0_set_GP_reg(a, b, c) hri_rtc_set_GP_reg(a, b, c) +#define hri_rtcmode0_get_GP_reg(a, b, c) hri_rtc_get_GP_reg(a, b, c) +#define hri_rtcmode0_write_GP_reg(a, b, c) hri_rtc_write_GP_reg(a, b, c) +#define hri_rtcmode0_clear_GP_reg(a, b, c) hri_rtc_clear_GP_reg(a, b, c) +#define hri_rtcmode0_toggle_GP_reg(a, b, c) hri_rtc_toggle_GP_reg(a, b, c) +#define hri_rtcmode0_read_GP_reg(a, b) hri_rtc_read_GP_reg(a, b) +#define hri_rtcmode0_set_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_TAMLVL0_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL0_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_TAMLVL1_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL1_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_TAMLVL2_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL2_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_TAMLVL3_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL3_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_TAMLVL4_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL4_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_DEBNC0_bit(a) hri_rtc_set_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_DEBNC0_bit(a) hri_rtc_get_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_DEBNC0_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC0_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_DEBNC0_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC0_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_DEBNC1_bit(a) hri_rtc_set_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_DEBNC1_bit(a) hri_rtc_get_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_DEBNC1_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC1_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_DEBNC1_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC1_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_DEBNC2_bit(a) hri_rtc_set_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_DEBNC2_bit(a) hri_rtc_get_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_DEBNC2_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC2_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_DEBNC2_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC2_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_DEBNC3_bit(a) hri_rtc_set_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_DEBNC3_bit(a) hri_rtc_get_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_DEBNC3_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC3_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_DEBNC3_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC3_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_DEBNC4_bit(a) hri_rtc_set_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode0_get_TAMPCTRL_DEBNC4_bit(a) hri_rtc_get_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode0_write_TAMPCTRL_DEBNC4_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC4_bit(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_DEBNC4_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode0_toggle_TAMPCTRL_DEBNC4_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode0_set_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode0_get_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode0_write_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode0_toggle_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode0_read_TAMPCTRL_IN0ACT_bf(a) hri_rtc_read_TAMPCTRL_IN0ACT_bf(a) +#define hri_rtcmode0_set_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode0_get_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode0_write_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode0_toggle_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode0_read_TAMPCTRL_IN1ACT_bf(a) hri_rtc_read_TAMPCTRL_IN1ACT_bf(a) +#define hri_rtcmode0_set_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode0_get_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode0_write_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode0_toggle_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode0_read_TAMPCTRL_IN2ACT_bf(a) hri_rtc_read_TAMPCTRL_IN2ACT_bf(a) +#define hri_rtcmode0_set_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode0_get_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode0_write_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode0_toggle_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode0_read_TAMPCTRL_IN3ACT_bf(a) hri_rtc_read_TAMPCTRL_IN3ACT_bf(a) +#define hri_rtcmode0_set_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode0_get_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode0_write_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode0_toggle_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode0_read_TAMPCTRL_IN4ACT_bf(a) hri_rtc_read_TAMPCTRL_IN4ACT_bf(a) +#define hri_rtcmode0_set_TAMPCTRL_reg(a, b) hri_rtc_set_TAMPCTRL_reg(a, b) +#define hri_rtcmode0_get_TAMPCTRL_reg(a, b) hri_rtc_get_TAMPCTRL_reg(a, b) +#define hri_rtcmode0_write_TAMPCTRL_reg(a, b) hri_rtc_write_TAMPCTRL_reg(a, b) +#define hri_rtcmode0_clear_TAMPCTRL_reg(a, b) hri_rtc_clear_TAMPCTRL_reg(a, b) +#define hri_rtcmode0_toggle_TAMPCTRL_reg(a, b) hri_rtc_toggle_TAMPCTRL_reg(a, b) +#define hri_rtcmode0_read_TAMPCTRL_reg(a) hri_rtc_read_TAMPCTRL_reg(a) +#define hri_rtcmode0_set_TAMPID_TAMPID0_bit(a) hri_rtc_set_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode0_get_TAMPID_TAMPID0_bit(a) hri_rtc_get_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode0_write_TAMPID_TAMPID0_bit(a, b) hri_rtc_write_TAMPID_TAMPID0_bit(a, b) +#define hri_rtcmode0_clear_TAMPID_TAMPID0_bit(a) hri_rtc_clear_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode0_toggle_TAMPID_TAMPID0_bit(a) hri_rtc_toggle_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode0_set_TAMPID_TAMPID1_bit(a) hri_rtc_set_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode0_get_TAMPID_TAMPID1_bit(a) hri_rtc_get_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode0_write_TAMPID_TAMPID1_bit(a, b) hri_rtc_write_TAMPID_TAMPID1_bit(a, b) +#define hri_rtcmode0_clear_TAMPID_TAMPID1_bit(a) hri_rtc_clear_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode0_toggle_TAMPID_TAMPID1_bit(a) hri_rtc_toggle_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode0_set_TAMPID_TAMPID2_bit(a) hri_rtc_set_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode0_get_TAMPID_TAMPID2_bit(a) hri_rtc_get_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode0_write_TAMPID_TAMPID2_bit(a, b) hri_rtc_write_TAMPID_TAMPID2_bit(a, b) +#define hri_rtcmode0_clear_TAMPID_TAMPID2_bit(a) hri_rtc_clear_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode0_toggle_TAMPID_TAMPID2_bit(a) hri_rtc_toggle_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode0_set_TAMPID_TAMPID3_bit(a) hri_rtc_set_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode0_get_TAMPID_TAMPID3_bit(a) hri_rtc_get_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode0_write_TAMPID_TAMPID3_bit(a, b) hri_rtc_write_TAMPID_TAMPID3_bit(a, b) +#define hri_rtcmode0_clear_TAMPID_TAMPID3_bit(a) hri_rtc_clear_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode0_toggle_TAMPID_TAMPID3_bit(a) hri_rtc_toggle_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode0_set_TAMPID_TAMPID4_bit(a) hri_rtc_set_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode0_get_TAMPID_TAMPID4_bit(a) hri_rtc_get_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode0_write_TAMPID_TAMPID4_bit(a, b) hri_rtc_write_TAMPID_TAMPID4_bit(a, b) +#define hri_rtcmode0_clear_TAMPID_TAMPID4_bit(a) hri_rtc_clear_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode0_toggle_TAMPID_TAMPID4_bit(a) hri_rtc_toggle_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode0_set_TAMPID_TAMPEVT_bit(a) hri_rtc_set_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode0_get_TAMPID_TAMPEVT_bit(a) hri_rtc_get_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode0_write_TAMPID_TAMPEVT_bit(a, b) hri_rtc_write_TAMPID_TAMPEVT_bit(a, b) +#define hri_rtcmode0_clear_TAMPID_TAMPEVT_bit(a) hri_rtc_clear_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode0_toggle_TAMPID_TAMPEVT_bit(a) hri_rtc_toggle_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode0_set_TAMPID_reg(a, b) hri_rtc_set_TAMPID_reg(a, b) +#define hri_rtcmode0_get_TAMPID_reg(a, b) hri_rtc_get_TAMPID_reg(a, b) +#define hri_rtcmode0_write_TAMPID_reg(a, b) hri_rtc_write_TAMPID_reg(a, b) +#define hri_rtcmode0_clear_TAMPID_reg(a, b) hri_rtc_clear_TAMPID_reg(a, b) +#define hri_rtcmode0_toggle_TAMPID_reg(a, b) hri_rtc_toggle_TAMPID_reg(a, b) +#define hri_rtcmode0_read_TAMPID_reg(a) hri_rtc_read_TAMPID_reg(a) +#define hri_rtcmode0_set_BKUP_BKUP_bf(a, b, c) hri_rtc_set_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode0_get_BKUP_BKUP_bf(a, b, c) hri_rtc_get_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode0_write_BKUP_BKUP_bf(a, b, c) hri_rtc_write_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode0_clear_BKUP_BKUP_bf(a, b, c) hri_rtc_clear_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode0_toggle_BKUP_BKUP_bf(a, b, c) hri_rtc_toggle_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode0_read_BKUP_BKUP_bf(a, b) hri_rtc_read_BKUP_BKUP_bf(a, b) +#define hri_rtcmode0_set_BKUP_reg(a, b, c) hri_rtc_set_BKUP_reg(a, b, c) +#define hri_rtcmode0_get_BKUP_reg(a, b, c) hri_rtc_get_BKUP_reg(a, b, c) +#define hri_rtcmode0_write_BKUP_reg(a, b, c) hri_rtc_write_BKUP_reg(a, b, c) +#define hri_rtcmode0_clear_BKUP_reg(a, b, c) hri_rtc_clear_BKUP_reg(a, b, c) +#define hri_rtcmode0_toggle_BKUP_reg(a, b, c) hri_rtc_toggle_BKUP_reg(a, b, c) +#define hri_rtcmode0_read_BKUP_reg(a, b) hri_rtc_read_BKUP_reg(a, b) +#define hri_rtcmode1_set_DBGCTRL_DBGRUN_bit(a) hri_rtc_set_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode1_get_DBGCTRL_DBGRUN_bit(a) hri_rtc_get_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode1_write_DBGCTRL_DBGRUN_bit(a, b) hri_rtc_write_DBGCTRL_DBGRUN_bit(a, b) +#define hri_rtcmode1_clear_DBGCTRL_DBGRUN_bit(a) hri_rtc_clear_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode1_toggle_DBGCTRL_DBGRUN_bit(a) hri_rtc_toggle_DBGCTRL_DBGRUN_bit(a) +#define hri_rtcmode1_set_DBGCTRL_reg(a, b) hri_rtc_set_DBGCTRL_reg(a, b) +#define hri_rtcmode1_get_DBGCTRL_reg(a, b) hri_rtc_get_DBGCTRL_reg(a, b) +#define hri_rtcmode1_write_DBGCTRL_reg(a, b) hri_rtc_write_DBGCTRL_reg(a, b) +#define hri_rtcmode1_clear_DBGCTRL_reg(a, b) hri_rtc_clear_DBGCTRL_reg(a, b) +#define hri_rtcmode1_toggle_DBGCTRL_reg(a, b) hri_rtc_toggle_DBGCTRL_reg(a, b) +#define hri_rtcmode1_read_DBGCTRL_reg(a) hri_rtc_read_DBGCTRL_reg(a) +#define hri_rtcmode1_set_FREQCORR_SIGN_bit(a) hri_rtc_set_FREQCORR_SIGN_bit(a) +#define hri_rtcmode1_get_FREQCORR_SIGN_bit(a) hri_rtc_get_FREQCORR_SIGN_bit(a) +#define hri_rtcmode1_write_FREQCORR_SIGN_bit(a, b) hri_rtc_write_FREQCORR_SIGN_bit(a, b) +#define hri_rtcmode1_clear_FREQCORR_SIGN_bit(a) hri_rtc_clear_FREQCORR_SIGN_bit(a) +#define hri_rtcmode1_toggle_FREQCORR_SIGN_bit(a) hri_rtc_toggle_FREQCORR_SIGN_bit(a) +#define hri_rtcmode1_set_FREQCORR_VALUE_bf(a, b) hri_rtc_set_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_get_FREQCORR_VALUE_bf(a, b) hri_rtc_get_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_write_FREQCORR_VALUE_bf(a, b) hri_rtc_write_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_clear_FREQCORR_VALUE_bf(a, b) hri_rtc_clear_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_toggle_FREQCORR_VALUE_bf(a, b) hri_rtc_toggle_FREQCORR_VALUE_bf(a, b) +#define hri_rtcmode1_read_FREQCORR_VALUE_bf(a) hri_rtc_read_FREQCORR_VALUE_bf(a) +#define hri_rtcmode1_set_FREQCORR_reg(a, b) hri_rtc_set_FREQCORR_reg(a, b) +#define hri_rtcmode1_get_FREQCORR_reg(a, b) hri_rtc_get_FREQCORR_reg(a, b) +#define hri_rtcmode1_write_FREQCORR_reg(a, b) hri_rtc_write_FREQCORR_reg(a, b) +#define hri_rtcmode1_clear_FREQCORR_reg(a, b) hri_rtc_clear_FREQCORR_reg(a, b) +#define hri_rtcmode1_toggle_FREQCORR_reg(a, b) hri_rtc_toggle_FREQCORR_reg(a, b) +#define hri_rtcmode1_read_FREQCORR_reg(a) hri_rtc_read_FREQCORR_reg(a) +#define hri_rtcmode1_set_GP_GP_bf(a, b, c) hri_rtc_set_GP_GP_bf(a, b, c) +#define hri_rtcmode1_get_GP_GP_bf(a, b, c) hri_rtc_get_GP_GP_bf(a, b, c) +#define hri_rtcmode1_write_GP_GP_bf(a, b, c) hri_rtc_write_GP_GP_bf(a, b, c) +#define hri_rtcmode1_clear_GP_GP_bf(a, b, c) hri_rtc_clear_GP_GP_bf(a, b, c) +#define hri_rtcmode1_toggle_GP_GP_bf(a, b, c) hri_rtc_toggle_GP_GP_bf(a, b, c) +#define hri_rtcmode1_read_GP_GP_bf(a, b) hri_rtc_read_GP_GP_bf(a, b) +#define hri_rtcmode1_set_GP_reg(a, b, c) hri_rtc_set_GP_reg(a, b, c) +#define hri_rtcmode1_get_GP_reg(a, b, c) hri_rtc_get_GP_reg(a, b, c) +#define hri_rtcmode1_write_GP_reg(a, b, c) hri_rtc_write_GP_reg(a, b, c) +#define hri_rtcmode1_clear_GP_reg(a, b, c) hri_rtc_clear_GP_reg(a, b, c) +#define hri_rtcmode1_toggle_GP_reg(a, b, c) hri_rtc_toggle_GP_reg(a, b, c) +#define hri_rtcmode1_read_GP_reg(a, b) hri_rtc_read_GP_reg(a, b) +#define hri_rtcmode1_set_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_TAMLVL0_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL0_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL0_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL0_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_TAMLVL1_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL1_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL1_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL1_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_TAMLVL2_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL2_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL2_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL2_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_TAMLVL3_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL3_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL3_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL3_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_set_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_get_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_TAMLVL4_bit(a, b) hri_rtc_write_TAMPCTRL_TAMLVL4_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_clear_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_TAMLVL4_bit(a) hri_rtc_toggle_TAMPCTRL_TAMLVL4_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_DEBNC0_bit(a) hri_rtc_set_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_DEBNC0_bit(a) hri_rtc_get_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_DEBNC0_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC0_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_DEBNC0_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC0_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC0_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_DEBNC1_bit(a) hri_rtc_set_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_DEBNC1_bit(a) hri_rtc_get_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_DEBNC1_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC1_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_DEBNC1_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC1_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC1_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_DEBNC2_bit(a) hri_rtc_set_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_DEBNC2_bit(a) hri_rtc_get_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_DEBNC2_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC2_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_DEBNC2_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC2_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC2_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_DEBNC3_bit(a) hri_rtc_set_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_DEBNC3_bit(a) hri_rtc_get_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_DEBNC3_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC3_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_DEBNC3_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC3_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC3_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_DEBNC4_bit(a) hri_rtc_set_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode1_get_TAMPCTRL_DEBNC4_bit(a) hri_rtc_get_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode1_write_TAMPCTRL_DEBNC4_bit(a, b) hri_rtc_write_TAMPCTRL_DEBNC4_bit(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_DEBNC4_bit(a) hri_rtc_clear_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode1_toggle_TAMPCTRL_DEBNC4_bit(a) hri_rtc_toggle_TAMPCTRL_DEBNC4_bit(a) +#define hri_rtcmode1_set_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode1_get_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode1_write_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode1_toggle_TAMPCTRL_IN0ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN0ACT_bf(a, b) +#define hri_rtcmode1_read_TAMPCTRL_IN0ACT_bf(a) hri_rtc_read_TAMPCTRL_IN0ACT_bf(a) +#define hri_rtcmode1_set_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode1_get_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode1_write_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode1_toggle_TAMPCTRL_IN1ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN1ACT_bf(a, b) +#define hri_rtcmode1_read_TAMPCTRL_IN1ACT_bf(a) hri_rtc_read_TAMPCTRL_IN1ACT_bf(a) +#define hri_rtcmode1_set_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode1_get_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode1_write_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode1_toggle_TAMPCTRL_IN2ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN2ACT_bf(a, b) +#define hri_rtcmode1_read_TAMPCTRL_IN2ACT_bf(a) hri_rtc_read_TAMPCTRL_IN2ACT_bf(a) +#define hri_rtcmode1_set_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode1_get_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode1_write_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode1_toggle_TAMPCTRL_IN3ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN3ACT_bf(a, b) +#define hri_rtcmode1_read_TAMPCTRL_IN3ACT_bf(a) hri_rtc_read_TAMPCTRL_IN3ACT_bf(a) +#define hri_rtcmode1_set_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_set_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode1_get_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_get_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode1_write_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_write_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_clear_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode1_toggle_TAMPCTRL_IN4ACT_bf(a, b) hri_rtc_toggle_TAMPCTRL_IN4ACT_bf(a, b) +#define hri_rtcmode1_read_TAMPCTRL_IN4ACT_bf(a) hri_rtc_read_TAMPCTRL_IN4ACT_bf(a) +#define hri_rtcmode1_set_TAMPCTRL_reg(a, b) hri_rtc_set_TAMPCTRL_reg(a, b) +#define hri_rtcmode1_get_TAMPCTRL_reg(a, b) hri_rtc_get_TAMPCTRL_reg(a, b) +#define hri_rtcmode1_write_TAMPCTRL_reg(a, b) hri_rtc_write_TAMPCTRL_reg(a, b) +#define hri_rtcmode1_clear_TAMPCTRL_reg(a, b) hri_rtc_clear_TAMPCTRL_reg(a, b) +#define hri_rtcmode1_toggle_TAMPCTRL_reg(a, b) hri_rtc_toggle_TAMPCTRL_reg(a, b) +#define hri_rtcmode1_read_TAMPCTRL_reg(a) hri_rtc_read_TAMPCTRL_reg(a) +#define hri_rtcmode1_set_TAMPID_TAMPID0_bit(a) hri_rtc_set_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode1_get_TAMPID_TAMPID0_bit(a) hri_rtc_get_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode1_write_TAMPID_TAMPID0_bit(a, b) hri_rtc_write_TAMPID_TAMPID0_bit(a, b) +#define hri_rtcmode1_clear_TAMPID_TAMPID0_bit(a) hri_rtc_clear_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode1_toggle_TAMPID_TAMPID0_bit(a) hri_rtc_toggle_TAMPID_TAMPID0_bit(a) +#define hri_rtcmode1_set_TAMPID_TAMPID1_bit(a) hri_rtc_set_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode1_get_TAMPID_TAMPID1_bit(a) hri_rtc_get_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode1_write_TAMPID_TAMPID1_bit(a, b) hri_rtc_write_TAMPID_TAMPID1_bit(a, b) +#define hri_rtcmode1_clear_TAMPID_TAMPID1_bit(a) hri_rtc_clear_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode1_toggle_TAMPID_TAMPID1_bit(a) hri_rtc_toggle_TAMPID_TAMPID1_bit(a) +#define hri_rtcmode1_set_TAMPID_TAMPID2_bit(a) hri_rtc_set_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode1_get_TAMPID_TAMPID2_bit(a) hri_rtc_get_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode1_write_TAMPID_TAMPID2_bit(a, b) hri_rtc_write_TAMPID_TAMPID2_bit(a, b) +#define hri_rtcmode1_clear_TAMPID_TAMPID2_bit(a) hri_rtc_clear_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode1_toggle_TAMPID_TAMPID2_bit(a) hri_rtc_toggle_TAMPID_TAMPID2_bit(a) +#define hri_rtcmode1_set_TAMPID_TAMPID3_bit(a) hri_rtc_set_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode1_get_TAMPID_TAMPID3_bit(a) hri_rtc_get_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode1_write_TAMPID_TAMPID3_bit(a, b) hri_rtc_write_TAMPID_TAMPID3_bit(a, b) +#define hri_rtcmode1_clear_TAMPID_TAMPID3_bit(a) hri_rtc_clear_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode1_toggle_TAMPID_TAMPID3_bit(a) hri_rtc_toggle_TAMPID_TAMPID3_bit(a) +#define hri_rtcmode1_set_TAMPID_TAMPID4_bit(a) hri_rtc_set_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode1_get_TAMPID_TAMPID4_bit(a) hri_rtc_get_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode1_write_TAMPID_TAMPID4_bit(a, b) hri_rtc_write_TAMPID_TAMPID4_bit(a, b) +#define hri_rtcmode1_clear_TAMPID_TAMPID4_bit(a) hri_rtc_clear_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode1_toggle_TAMPID_TAMPID4_bit(a) hri_rtc_toggle_TAMPID_TAMPID4_bit(a) +#define hri_rtcmode1_set_TAMPID_TAMPEVT_bit(a) hri_rtc_set_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode1_get_TAMPID_TAMPEVT_bit(a) hri_rtc_get_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode1_write_TAMPID_TAMPEVT_bit(a, b) hri_rtc_write_TAMPID_TAMPEVT_bit(a, b) +#define hri_rtcmode1_clear_TAMPID_TAMPEVT_bit(a) hri_rtc_clear_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode1_toggle_TAMPID_TAMPEVT_bit(a) hri_rtc_toggle_TAMPID_TAMPEVT_bit(a) +#define hri_rtcmode1_set_TAMPID_reg(a, b) hri_rtc_set_TAMPID_reg(a, b) +#define hri_rtcmode1_get_TAMPID_reg(a, b) hri_rtc_get_TAMPID_reg(a, b) +#define hri_rtcmode1_write_TAMPID_reg(a, b) hri_rtc_write_TAMPID_reg(a, b) +#define hri_rtcmode1_clear_TAMPID_reg(a, b) hri_rtc_clear_TAMPID_reg(a, b) +#define hri_rtcmode1_toggle_TAMPID_reg(a, b) hri_rtc_toggle_TAMPID_reg(a, b) +#define hri_rtcmode1_read_TAMPID_reg(a) hri_rtc_read_TAMPID_reg(a) +#define hri_rtcmode1_set_BKUP_BKUP_bf(a, b, c) hri_rtc_set_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode1_get_BKUP_BKUP_bf(a, b, c) hri_rtc_get_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode1_write_BKUP_BKUP_bf(a, b, c) hri_rtc_write_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode1_clear_BKUP_BKUP_bf(a, b, c) hri_rtc_clear_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode1_toggle_BKUP_BKUP_bf(a, b, c) hri_rtc_toggle_BKUP_BKUP_bf(a, b, c) +#define hri_rtcmode1_read_BKUP_BKUP_bf(a, b) hri_rtc_read_BKUP_BKUP_bf(a, b) +#define hri_rtcmode1_set_BKUP_reg(a, b, c) hri_rtc_set_BKUP_reg(a, b, c) +#define hri_rtcmode1_get_BKUP_reg(a, b, c) hri_rtc_get_BKUP_reg(a, b, c) +#define hri_rtcmode1_write_BKUP_reg(a, b, c) hri_rtc_write_BKUP_reg(a, b, c) +#define hri_rtcmode1_clear_BKUP_reg(a, b, c) hri_rtc_clear_BKUP_reg(a, b, c) +#define hri_rtcmode1_toggle_BKUP_reg(a, b, c) hri_rtc_toggle_BKUP_reg(a, b, c) +#define hri_rtcmode1_read_BKUP_reg(a, b) hri_rtc_read_BKUP_reg(a, b) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_RTC_E54_H_INCLUDED */ +#endif /* _SAME54_RTC_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_sdhc_e54.h b/software/firmware/oracle_same54n19a/hri/hri_sdhc_e54.h new file mode 100644 index 00000000..0b7f609e --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_sdhc_e54.h @@ -0,0 +1,7477 @@ +/** + * \file + * + * \brief SAM SDHC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_SDHC_COMPONENT_ +#ifndef _HRI_SDHC_E54_H_INCLUDED_ +#define _HRI_SDHC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SDHC_CRITICAL_SECTIONS) +#define SDHC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SDHC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SDHC_CRITICAL_SECTION_ENTER() +#define SDHC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_sdhc_acesr_reg_t; +typedef uint16_t hri_sdhc_bcr_reg_t; +typedef uint16_t hri_sdhc_bsr_reg_t; +typedef uint16_t hri_sdhc_ccr_reg_t; +typedef uint16_t hri_sdhc_cr_reg_t; +typedef uint16_t hri_sdhc_eisier_reg_t; +typedef uint16_t hri_sdhc_eister_reg_t; +typedef uint16_t hri_sdhc_eistr_reg_t; +typedef uint16_t hri_sdhc_feraces_reg_t; +typedef uint16_t hri_sdhc_fereis_reg_t; +typedef uint16_t hri_sdhc_hc2r_reg_t; +typedef uint16_t hri_sdhc_hcvr_reg_t; +typedef uint16_t hri_sdhc_nisier_reg_t; +typedef uint16_t hri_sdhc_nister_reg_t; +typedef uint16_t hri_sdhc_nistr_reg_t; +typedef uint16_t hri_sdhc_pvr_reg_t; +typedef uint16_t hri_sdhc_sisr_reg_t; +typedef uint16_t hri_sdhc_tmr_reg_t; +typedef uint32_t hri_sdhc_acr_reg_t; +typedef uint32_t hri_sdhc_arg1r_reg_t; +typedef uint32_t hri_sdhc_asar_reg_t; +typedef uint32_t hri_sdhc_bdpr_reg_t; +typedef uint32_t hri_sdhc_ca0r_reg_t; +typedef uint32_t hri_sdhc_ca1r_reg_t; +typedef uint32_t hri_sdhc_cacr_reg_t; +typedef uint32_t hri_sdhc_cc2r_reg_t; +typedef uint32_t hri_sdhc_mccar_reg_t; +typedef uint32_t hri_sdhc_psr_reg_t; +typedef uint32_t hri_sdhc_rr_reg_t; +typedef uint32_t hri_sdhc_ssar_reg_t; +typedef uint8_t hri_sdhc_aesr_reg_t; +typedef uint8_t hri_sdhc_bgcr_reg_t; +typedef uint8_t hri_sdhc_dbgr_reg_t; +typedef uint8_t hri_sdhc_hc1r_reg_t; +typedef uint8_t hri_sdhc_mc1r_reg_t; +typedef uint8_t hri_sdhc_mc2r_reg_t; +typedef uint8_t hri_sdhc_pcr_reg_t; +typedef uint8_t hri_sdhc_srr_reg_t; +typedef uint8_t hri_sdhc_tcr_reg_t; +typedef uint8_t hri_sdhc_wcr_reg_t; + +static inline hri_sdhc_rr_reg_t hri_sdhc_get_RR_CMDRESP_bf(const void *const hw, uint8_t index, hri_sdhc_rr_reg_t mask) +{ + return (((Sdhc *)hw)->RR[index].reg & SDHC_RR_CMDRESP(mask)) >> SDHC_RR_CMDRESP_Pos; +} + +static inline hri_sdhc_rr_reg_t hri_sdhc_read_RR_CMDRESP_bf(const void *const hw, uint8_t index) +{ + return (((Sdhc *)hw)->RR[index].reg & SDHC_RR_CMDRESP_Msk) >> SDHC_RR_CMDRESP_Pos; +} + +static inline hri_sdhc_rr_reg_t hri_sdhc_get_RR_reg(const void *const hw, uint8_t index, hri_sdhc_rr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->RR[index].reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_rr_reg_t hri_sdhc_read_RR_reg(const void *const hw, uint8_t index) +{ + return ((Sdhc *)hw)->RR[index].reg; +} + +static inline bool hri_sdhc_get_PSR_CMDINHC_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CMDINHC) >> SDHC_PSR_CMDINHC_Pos; +} + +static inline bool hri_sdhc_get_PSR_CMDINHD_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CMDINHD) >> SDHC_PSR_CMDINHD_Pos; +} + +static inline bool hri_sdhc_get_PSR_DLACT_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_DLACT) >> SDHC_PSR_DLACT_Pos; +} + +static inline bool hri_sdhc_get_PSR_RTREQ_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_RTREQ) >> SDHC_PSR_RTREQ_Pos; +} + +static inline bool hri_sdhc_get_PSR_WTACT_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_WTACT) >> SDHC_PSR_WTACT_Pos; +} + +static inline bool hri_sdhc_get_PSR_RTACT_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_RTACT) >> SDHC_PSR_RTACT_Pos; +} + +static inline bool hri_sdhc_get_PSR_BUFWREN_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_BUFWREN) >> SDHC_PSR_BUFWREN_Pos; +} + +static inline bool hri_sdhc_get_PSR_BUFRDEN_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_BUFRDEN) >> SDHC_PSR_BUFRDEN_Pos; +} + +static inline bool hri_sdhc_get_PSR_CARDINS_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CARDINS) >> SDHC_PSR_CARDINS_Pos; +} + +static inline bool hri_sdhc_get_PSR_CARDSS_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CARDSS) >> SDHC_PSR_CARDSS_Pos; +} + +static inline bool hri_sdhc_get_PSR_CARDDPL_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CARDDPL) >> SDHC_PSR_CARDDPL_Pos; +} + +static inline bool hri_sdhc_get_PSR_WRPPL_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_WRPPL) >> SDHC_PSR_WRPPL_Pos; +} + +static inline bool hri_sdhc_get_PSR_CMDLL_bit(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_CMDLL) >> SDHC_PSR_CMDLL_Pos; +} + +static inline hri_sdhc_psr_reg_t hri_sdhc_get_PSR_DATLL_bf(const void *const hw, hri_sdhc_psr_reg_t mask) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_DATLL(mask)) >> SDHC_PSR_DATLL_Pos; +} + +static inline hri_sdhc_psr_reg_t hri_sdhc_read_PSR_DATLL_bf(const void *const hw) +{ + return (((Sdhc *)hw)->PSR.reg & SDHC_PSR_DATLL_Msk) >> SDHC_PSR_DATLL_Pos; +} + +static inline hri_sdhc_psr_reg_t hri_sdhc_get_PSR_reg(const void *const hw, hri_sdhc_psr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->PSR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_psr_reg_t hri_sdhc_read_PSR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->PSR.reg; +} + +static inline bool hri_sdhc_get_ACESR_ACMD12NE_bit(const void *const hw) +{ + return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMD12NE) >> SDHC_ACESR_ACMD12NE_Pos; +} + +static inline bool hri_sdhc_get_ACESR_ACMDTEO_bit(const void *const hw) +{ + return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDTEO) >> SDHC_ACESR_ACMDTEO_Pos; +} + +static inline bool hri_sdhc_get_ACESR_ACMDCRC_bit(const void *const hw) +{ + return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDCRC) >> SDHC_ACESR_ACMDCRC_Pos; +} + +static inline bool hri_sdhc_get_ACESR_ACMDEND_bit(const void *const hw) +{ + return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDEND) >> SDHC_ACESR_ACMDEND_Pos; +} + +static inline bool hri_sdhc_get_ACESR_ACMDIDX_bit(const void *const hw) +{ + return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_ACMDIDX) >> SDHC_ACESR_ACMDIDX_Pos; +} + +static inline bool hri_sdhc_get_ACESR_CMDNI_bit(const void *const hw) +{ + return (((Sdhc *)hw)->ACESR.reg & SDHC_ACESR_CMDNI) >> SDHC_ACESR_CMDNI_Pos; +} + +static inline hri_sdhc_acesr_reg_t hri_sdhc_get_ACESR_reg(const void *const hw, hri_sdhc_acesr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->ACESR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_acesr_reg_t hri_sdhc_read_ACESR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->ACESR.reg; +} + +static inline bool hri_sdhc_get_CA0R_TEOCLKU_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_TEOCLKU) >> SDHC_CA0R_TEOCLKU_Pos; +} + +static inline bool hri_sdhc_get_CA0R_ED8SUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_ED8SUP) >> SDHC_CA0R_ED8SUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_ADMA2SUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_ADMA2SUP) >> SDHC_CA0R_ADMA2SUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_HSSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_HSSUP) >> SDHC_CA0R_HSSUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_SDMASUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SDMASUP) >> SDHC_CA0R_SDMASUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_SRSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SRSUP) >> SDHC_CA0R_SRSUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_V33VSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_V33VSUP) >> SDHC_CA0R_V33VSUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_V30VSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_V30VSUP) >> SDHC_CA0R_V30VSUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_V18VSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_V18VSUP) >> SDHC_CA0R_V18VSUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_SB64SUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SB64SUP) >> SDHC_CA0R_SB64SUP_Pos; +} + +static inline bool hri_sdhc_get_CA0R_ASINTSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_ASINTSUP) >> SDHC_CA0R_ASINTSUP_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_TEOCLKF_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_TEOCLKF(mask)) >> SDHC_CA0R_TEOCLKF_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_TEOCLKF_bf(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_TEOCLKF_Msk) >> SDHC_CA0R_TEOCLKF_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_BASECLKF_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_BASECLKF(mask)) >> SDHC_CA0R_BASECLKF_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_BASECLKF_bf(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_BASECLKF_Msk) >> SDHC_CA0R_BASECLKF_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_MAXBLKL_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_MAXBLKL(mask)) >> SDHC_CA0R_MAXBLKL_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_MAXBLKL_bf(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_MAXBLKL_Msk) >> SDHC_CA0R_MAXBLKL_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_SLTYPE_bf(const void *const hw, hri_sdhc_ca0r_reg_t mask) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SLTYPE(mask)) >> SDHC_CA0R_SLTYPE_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_SLTYPE_bf(const void *const hw) +{ + return (((Sdhc *)hw)->CA0R.reg & SDHC_CA0R_SLTYPE_Msk) >> SDHC_CA0R_SLTYPE_Pos; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_get_CA0R_reg(const void *const hw, hri_sdhc_ca0r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CA0R.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_ca0r_reg_t hri_sdhc_read_CA0R_reg(const void *const hw) +{ + return ((Sdhc *)hw)->CA0R.reg; +} + +static inline bool hri_sdhc_get_CA1R_SDR50SUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_SDR50SUP) >> SDHC_CA1R_SDR50SUP_Pos; +} + +static inline bool hri_sdhc_get_CA1R_SDR104SUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_SDR104SUP) >> SDHC_CA1R_SDR104SUP_Pos; +} + +static inline bool hri_sdhc_get_CA1R_DDR50SUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DDR50SUP) >> SDHC_CA1R_DDR50SUP_Pos; +} + +static inline bool hri_sdhc_get_CA1R_DRVASUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DRVASUP) >> SDHC_CA1R_DRVASUP_Pos; +} + +static inline bool hri_sdhc_get_CA1R_DRVCSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DRVCSUP) >> SDHC_CA1R_DRVCSUP_Pos; +} + +static inline bool hri_sdhc_get_CA1R_DRVDSUP_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_DRVDSUP) >> SDHC_CA1R_DRVDSUP_Pos; +} + +static inline bool hri_sdhc_get_CA1R_TSDR50_bit(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_TSDR50) >> SDHC_CA1R_TSDR50_Pos; +} + +static inline hri_sdhc_ca1r_reg_t hri_sdhc_get_CA1R_TCNTRT_bf(const void *const hw, hri_sdhc_ca1r_reg_t mask) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_TCNTRT(mask)) >> SDHC_CA1R_TCNTRT_Pos; +} + +static inline hri_sdhc_ca1r_reg_t hri_sdhc_read_CA1R_TCNTRT_bf(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_TCNTRT_Msk) >> SDHC_CA1R_TCNTRT_Pos; +} + +static inline hri_sdhc_ca1r_reg_t hri_sdhc_get_CA1R_CLKMULT_bf(const void *const hw, hri_sdhc_ca1r_reg_t mask) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_CLKMULT(mask)) >> SDHC_CA1R_CLKMULT_Pos; +} + +static inline hri_sdhc_ca1r_reg_t hri_sdhc_read_CA1R_CLKMULT_bf(const void *const hw) +{ + return (((Sdhc *)hw)->CA1R.reg & SDHC_CA1R_CLKMULT_Msk) >> SDHC_CA1R_CLKMULT_Pos; +} + +static inline hri_sdhc_ca1r_reg_t hri_sdhc_get_CA1R_reg(const void *const hw, hri_sdhc_ca1r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CA1R.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_ca1r_reg_t hri_sdhc_read_CA1R_reg(const void *const hw) +{ + return ((Sdhc *)hw)->CA1R.reg; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_MAXCUR33V_bf(const void *const hw, hri_sdhc_mccar_reg_t mask) +{ + return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR33V(mask)) >> SDHC_MCCAR_MAXCUR33V_Pos; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_MAXCUR33V_bf(const void *const hw) +{ + return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR33V_Msk) >> SDHC_MCCAR_MAXCUR33V_Pos; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_MAXCUR30V_bf(const void *const hw, hri_sdhc_mccar_reg_t mask) +{ + return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR30V(mask)) >> SDHC_MCCAR_MAXCUR30V_Pos; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_MAXCUR30V_bf(const void *const hw) +{ + return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR30V_Msk) >> SDHC_MCCAR_MAXCUR30V_Pos; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_MAXCUR18V_bf(const void *const hw, hri_sdhc_mccar_reg_t mask) +{ + return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR18V(mask)) >> SDHC_MCCAR_MAXCUR18V_Pos; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_MAXCUR18V_bf(const void *const hw) +{ + return (((Sdhc *)hw)->MCCAR.reg & SDHC_MCCAR_MAXCUR18V_Msk) >> SDHC_MCCAR_MAXCUR18V_Pos; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_get_MCCAR_reg(const void *const hw, hri_sdhc_mccar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->MCCAR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_mccar_reg_t hri_sdhc_read_MCCAR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->MCCAR.reg; +} + +static inline bool hri_sdhc_get_AESR_LMIS_bit(const void *const hw) +{ + return (((Sdhc *)hw)->AESR.reg & SDHC_AESR_LMIS) >> SDHC_AESR_LMIS_Pos; +} + +static inline hri_sdhc_aesr_reg_t hri_sdhc_get_AESR_ERRST_bf(const void *const hw, hri_sdhc_aesr_reg_t mask) +{ + return (((Sdhc *)hw)->AESR.reg & SDHC_AESR_ERRST(mask)) >> SDHC_AESR_ERRST_Pos; +} + +static inline hri_sdhc_aesr_reg_t hri_sdhc_read_AESR_ERRST_bf(const void *const hw) +{ + return (((Sdhc *)hw)->AESR.reg & SDHC_AESR_ERRST_Msk) >> SDHC_AESR_ERRST_Pos; +} + +static inline hri_sdhc_aesr_reg_t hri_sdhc_get_AESR_reg(const void *const hw, hri_sdhc_aesr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->AESR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_aesr_reg_t hri_sdhc_read_AESR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->AESR.reg; +} + +static inline bool hri_sdhc_get_SISR_INTSSL_bit(const void *const hw) +{ + return (((Sdhc *)hw)->SISR.reg & SDHC_SISR_INTSSL_Msk) >> SDHC_SISR_INTSSL_Pos; +} + +static inline hri_sdhc_sisr_reg_t hri_sdhc_get_SISR_reg(const void *const hw, hri_sdhc_sisr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->SISR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_sisr_reg_t hri_sdhc_read_SISR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->SISR.reg; +} + +static inline hri_sdhc_hcvr_reg_t hri_sdhc_get_HCVR_SVER_bf(const void *const hw, hri_sdhc_hcvr_reg_t mask) +{ + return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_SVER(mask)) >> SDHC_HCVR_SVER_Pos; +} + +static inline hri_sdhc_hcvr_reg_t hri_sdhc_read_HCVR_SVER_bf(const void *const hw) +{ + return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_SVER_Msk) >> SDHC_HCVR_SVER_Pos; +} + +static inline hri_sdhc_hcvr_reg_t hri_sdhc_get_HCVR_VVER_bf(const void *const hw, hri_sdhc_hcvr_reg_t mask) +{ + return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_VVER(mask)) >> SDHC_HCVR_VVER_Pos; +} + +static inline hri_sdhc_hcvr_reg_t hri_sdhc_read_HCVR_VVER_bf(const void *const hw) +{ + return (((Sdhc *)hw)->HCVR.reg & SDHC_HCVR_VVER_Msk) >> SDHC_HCVR_VVER_Pos; +} + +static inline hri_sdhc_hcvr_reg_t hri_sdhc_get_HCVR_reg(const void *const hw, hri_sdhc_hcvr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HCVR.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sdhc_hcvr_reg_t hri_sdhc_read_HCVR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->HCVR.reg; +} + +static inline void hri_sdhc_set_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg |= SDHC_SSAR_ADDR(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->SSAR.reg; + tmp = (tmp & SDHC_SSAR_ADDR(mask)) >> SDHC_SSAR_ADDR_Pos; + return tmp; +} + +static inline void hri_sdhc_write_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t data) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->SSAR.reg; + tmp &= ~SDHC_SSAR_ADDR_Msk; + tmp |= SDHC_SSAR_ADDR(data); + ((Sdhc *)hw)->SSAR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg &= ~SDHC_SSAR_ADDR(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_SSAR_ADDR_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg ^= SDHC_SSAR_ADDR(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->SSAR.reg; + tmp = (tmp & SDHC_SSAR_ADDR_Msk) >> SDHC_SSAR_ADDR_Pos; + return tmp; +} + +static inline void hri_sdhc_set_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg |= SDHC_SSAR_CMD23_ARG2(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->SSAR.reg; + tmp = (tmp & SDHC_SSAR_CMD23_ARG2(mask)) >> SDHC_SSAR_CMD23_ARG2_Pos; + return tmp; +} + +static inline void hri_sdhc_write_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t data) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->SSAR.reg; + tmp &= ~SDHC_SSAR_CMD23_ARG2_Msk; + tmp |= SDHC_SSAR_CMD23_ARG2(data); + ((Sdhc *)hw)->SSAR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg &= ~SDHC_SSAR_CMD23_ARG2(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_SSAR_CMD23_ARG2_bf(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg ^= SDHC_SSAR_CMD23_ARG2(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_CMD23_ARG2_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->SSAR.reg; + tmp = (tmp & SDHC_SSAR_CMD23_ARG2_Msk) >> SDHC_SSAR_CMD23_ARG2_Pos; + return tmp; +} + +static inline void hri_sdhc_set_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ssar_reg_t hri_sdhc_get_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->SSAR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_SSAR_reg(const void *const hw, hri_sdhc_ssar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SSAR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ssar_reg_t hri_sdhc_read_SSAR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->SSAR.reg; +} + +static inline void hri_sdhc_set_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg |= SDHC_BSR_BLOCKSIZE(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bsr_reg_t hri_sdhc_get_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BSR.reg; + tmp = (tmp & SDHC_BSR_BLOCKSIZE(mask)) >> SDHC_BSR_BLOCKSIZE_Pos; + return tmp; +} + +static inline void hri_sdhc_write_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BSR.reg; + tmp &= ~SDHC_BSR_BLOCKSIZE_Msk; + tmp |= SDHC_BSR_BLOCKSIZE(data); + ((Sdhc *)hw)->BSR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg &= ~SDHC_BSR_BLOCKSIZE(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BSR_BLOCKSIZE_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg ^= SDHC_BSR_BLOCKSIZE(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bsr_reg_t hri_sdhc_read_BSR_BLOCKSIZE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BSR.reg; + tmp = (tmp & SDHC_BSR_BLOCKSIZE_Msk) >> SDHC_BSR_BLOCKSIZE_Pos; + return tmp; +} + +static inline void hri_sdhc_set_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg |= SDHC_BSR_BOUNDARY(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bsr_reg_t hri_sdhc_get_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BSR.reg; + tmp = (tmp & SDHC_BSR_BOUNDARY(mask)) >> SDHC_BSR_BOUNDARY_Pos; + return tmp; +} + +static inline void hri_sdhc_write_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BSR.reg; + tmp &= ~SDHC_BSR_BOUNDARY_Msk; + tmp |= SDHC_BSR_BOUNDARY(data); + ((Sdhc *)hw)->BSR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg &= ~SDHC_BSR_BOUNDARY(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BSR_BOUNDARY_bf(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg ^= SDHC_BSR_BOUNDARY(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bsr_reg_t hri_sdhc_read_BSR_BOUNDARY_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BSR.reg; + tmp = (tmp & SDHC_BSR_BOUNDARY_Msk) >> SDHC_BSR_BOUNDARY_Pos; + return tmp; +} + +static inline void hri_sdhc_set_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bsr_reg_t hri_sdhc_get_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BSR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BSR_reg(const void *const hw, hri_sdhc_bsr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BSR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bsr_reg_t hri_sdhc_read_BSR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->BSR.reg; +} + +static inline void hri_sdhc_set_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BCR.reg |= SDHC_BCR_BCNT(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bcr_reg_t hri_sdhc_get_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BCR.reg; + tmp = (tmp & SDHC_BCR_BCNT(mask)) >> SDHC_BCR_BCNT_Pos; + return tmp; +} + +static inline void hri_sdhc_write_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BCR.reg; + tmp &= ~SDHC_BCR_BCNT_Msk; + tmp |= SDHC_BCR_BCNT(data); + ((Sdhc *)hw)->BCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BCR.reg &= ~SDHC_BCR_BCNT(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BCR_BCNT_bf(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BCR.reg ^= SDHC_BCR_BCNT(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bcr_reg_t hri_sdhc_read_BCR_BCNT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BCR.reg; + tmp = (tmp & SDHC_BCR_BCNT_Msk) >> SDHC_BCR_BCNT_Pos; + return tmp; +} + +static inline void hri_sdhc_set_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BCR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bcr_reg_t hri_sdhc_get_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->BCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BCR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BCR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BCR_reg(const void *const hw, hri_sdhc_bcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BCR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bcr_reg_t hri_sdhc_read_BCR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->BCR.reg; +} + +static inline void hri_sdhc_set_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ARG1R.reg |= SDHC_ARG1R_ARG(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_arg1r_reg_t hri_sdhc_get_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ARG1R.reg; + tmp = (tmp & SDHC_ARG1R_ARG(mask)) >> SDHC_ARG1R_ARG_Pos; + return tmp; +} + +static inline void hri_sdhc_write_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t data) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->ARG1R.reg; + tmp &= ~SDHC_ARG1R_ARG_Msk; + tmp |= SDHC_ARG1R_ARG(data); + ((Sdhc *)hw)->ARG1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ARG1R.reg &= ~SDHC_ARG1R_ARG(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_ARG1R_ARG_bf(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ARG1R.reg ^= SDHC_ARG1R_ARG(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_arg1r_reg_t hri_sdhc_read_ARG1R_ARG_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ARG1R.reg; + tmp = (tmp & SDHC_ARG1R_ARG_Msk) >> SDHC_ARG1R_ARG_Pos; + return tmp; +} + +static inline void hri_sdhc_set_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ARG1R.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_arg1r_reg_t hri_sdhc_get_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ARG1R.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ARG1R.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ARG1R.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_ARG1R_reg(const void *const hw, hri_sdhc_arg1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ARG1R.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_arg1r_reg_t hri_sdhc_read_ARG1R_reg(const void *const hw) +{ + return ((Sdhc *)hw)->ARG1R.reg; +} + +static inline void hri_sdhc_set_TMR_DMAEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_DMAEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_TMR_DMAEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->TMR.reg; + tmp = (tmp & SDHC_TMR_DMAEN) >> SDHC_TMR_DMAEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_TMR_DMAEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->TMR.reg; + tmp &= ~SDHC_TMR_DMAEN; + tmp |= value << SDHC_TMR_DMAEN_Pos; + ((Sdhc *)hw)->TMR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TMR_DMAEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_DMAEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TMR_DMAEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_DMAEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_TMR_BCEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_BCEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_TMR_BCEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->TMR.reg; + tmp = (tmp & SDHC_TMR_BCEN) >> SDHC_TMR_BCEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_TMR_BCEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->TMR.reg; + tmp &= ~SDHC_TMR_BCEN; + tmp |= value << SDHC_TMR_BCEN_Pos; + ((Sdhc *)hw)->TMR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TMR_BCEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_BCEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TMR_BCEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_BCEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_TMR_DTDSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_DTDSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_TMR_DTDSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->TMR.reg; + tmp = (tmp & SDHC_TMR_DTDSEL) >> SDHC_TMR_DTDSEL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_TMR_DTDSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->TMR.reg; + tmp &= ~SDHC_TMR_DTDSEL; + tmp |= value << SDHC_TMR_DTDSEL_Pos; + ((Sdhc *)hw)->TMR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TMR_DTDSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_DTDSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TMR_DTDSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_DTDSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_TMR_MSBSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_MSBSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_TMR_MSBSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->TMR.reg; + tmp = (tmp & SDHC_TMR_MSBSEL) >> SDHC_TMR_MSBSEL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_TMR_MSBSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->TMR.reg; + tmp &= ~SDHC_TMR_MSBSEL; + tmp |= value << SDHC_TMR_MSBSEL_Pos; + ((Sdhc *)hw)->TMR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TMR_MSBSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_MSBSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TMR_MSBSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_MSBSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg |= SDHC_TMR_ACMDEN(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tmr_reg_t hri_sdhc_get_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->TMR.reg; + tmp = (tmp & SDHC_TMR_ACMDEN(mask)) >> SDHC_TMR_ACMDEN_Pos; + return tmp; +} + +static inline void hri_sdhc_write_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->TMR.reg; + tmp &= ~SDHC_TMR_ACMDEN_Msk; + tmp |= SDHC_TMR_ACMDEN(data); + ((Sdhc *)hw)->TMR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg &= ~SDHC_TMR_ACMDEN(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TMR_ACMDEN_bf(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg ^= SDHC_TMR_ACMDEN(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tmr_reg_t hri_sdhc_read_TMR_ACMDEN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->TMR.reg; + tmp = (tmp & SDHC_TMR_ACMDEN_Msk) >> SDHC_TMR_ACMDEN_Pos; + return tmp; +} + +static inline void hri_sdhc_set_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tmr_reg_t hri_sdhc_get_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->TMR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TMR_reg(const void *const hw, hri_sdhc_tmr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TMR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tmr_reg_t hri_sdhc_read_TMR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->TMR.reg; +} + +static inline void hri_sdhc_set_CR_CMDCCEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDCCEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CR_CMDCCEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_CMDCCEN) >> SDHC_CR_CMDCCEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CR_CMDCCEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CR.reg; + tmp &= ~SDHC_CR_CMDCCEN; + tmp |= value << SDHC_CR_CMDCCEN_Pos; + ((Sdhc *)hw)->CR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CR_CMDCCEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDCCEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CR_CMDCCEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDCCEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CR_CMDICEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDICEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CR_CMDICEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_CMDICEN) >> SDHC_CR_CMDICEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CR_CMDICEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CR.reg; + tmp &= ~SDHC_CR_CMDICEN; + tmp |= value << SDHC_CR_CMDICEN_Pos; + ((Sdhc *)hw)->CR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CR_CMDICEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDICEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CR_CMDICEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDICEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CR_DPSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg |= SDHC_CR_DPSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CR_DPSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_DPSEL) >> SDHC_CR_DPSEL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CR_DPSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CR.reg; + tmp &= ~SDHC_CR_DPSEL; + tmp |= value << SDHC_CR_DPSEL_Pos; + ((Sdhc *)hw)->CR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CR_DPSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_DPSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CR_DPSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg ^= SDHC_CR_DPSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg |= SDHC_CR_RESPTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_RESPTYP(mask)) >> SDHC_CR_RESPTYP_Pos; + return tmp; +} + +static inline void hri_sdhc_write_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CR.reg; + tmp &= ~SDHC_CR_RESPTYP_Msk; + tmp |= SDHC_CR_RESPTYP(data); + ((Sdhc *)hw)->CR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_RESPTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CR_RESPTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg ^= SDHC_CR_RESPTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_RESPTYP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_RESPTYP_Msk) >> SDHC_CR_RESPTYP_Pos; + return tmp; +} + +static inline void hri_sdhc_set_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_CMDTYP(mask)) >> SDHC_CR_CMDTYP_Pos; + return tmp; +} + +static inline void hri_sdhc_write_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CR.reg; + tmp &= ~SDHC_CR_CMDTYP_Msk; + tmp |= SDHC_CR_CMDTYP(data); + ((Sdhc *)hw)->CR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CR_CMDTYP_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_CMDTYP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_CMDTYP_Msk) >> SDHC_CR_CMDTYP_Pos; + return tmp; +} + +static inline void hri_sdhc_set_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg |= SDHC_CR_CMDIDX(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_CMDIDX(mask)) >> SDHC_CR_CMDIDX_Pos; + return tmp; +} + +static inline void hri_sdhc_write_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CR.reg; + tmp &= ~SDHC_CR_CMDIDX_Msk; + tmp |= SDHC_CR_CMDIDX(data); + ((Sdhc *)hw)->CR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg &= ~SDHC_CR_CMDIDX(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CR_CMDIDX_bf(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg ^= SDHC_CR_CMDIDX(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_CMDIDX_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp = (tmp & SDHC_CR_CMDIDX_Msk) >> SDHC_CR_CMDIDX_Pos; + return tmp; +} + +static inline void hri_sdhc_set_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_get_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_CR_reg(const void *const hw, hri_sdhc_cr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CR_reg(const void *const hw, hri_sdhc_cr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cr_reg_t hri_sdhc_read_CR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->CR.reg; +} + +static inline void hri_sdhc_set_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BDPR.reg |= SDHC_BDPR_BUFDATA(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bdpr_reg_t hri_sdhc_get_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->BDPR.reg; + tmp = (tmp & SDHC_BDPR_BUFDATA(mask)) >> SDHC_BDPR_BUFDATA_Pos; + return tmp; +} + +static inline void hri_sdhc_write_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t data) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BDPR.reg; + tmp &= ~SDHC_BDPR_BUFDATA_Msk; + tmp |= SDHC_BDPR_BUFDATA(data); + ((Sdhc *)hw)->BDPR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BDPR.reg &= ~SDHC_BDPR_BUFDATA(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BDPR_BUFDATA_bf(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BDPR.reg ^= SDHC_BDPR_BUFDATA(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bdpr_reg_t hri_sdhc_read_BDPR_BUFDATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->BDPR.reg; + tmp = (tmp & SDHC_BDPR_BUFDATA_Msk) >> SDHC_BDPR_BUFDATA_Pos; + return tmp; +} + +static inline void hri_sdhc_set_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BDPR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bdpr_reg_t hri_sdhc_get_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->BDPR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BDPR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BDPR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BDPR_reg(const void *const hw, hri_sdhc_bdpr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BDPR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bdpr_reg_t hri_sdhc_read_BDPR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->BDPR.reg; +} + +static inline void hri_sdhc_set_HC1R_LEDCTRL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_LEDCTRL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC1R_LEDCTRL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_LEDCTRL) >> SDHC_HC1R_LEDCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC1R_LEDCTRL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= ~SDHC_HC1R_LEDCTRL; + tmp |= value << SDHC_HC1R_LEDCTRL_Pos; + ((Sdhc *)hw)->HC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_LEDCTRL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_LEDCTRL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_LEDCTRL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_LEDCTRL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC1R_DW_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_DW; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC1R_DW_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_DW) >> SDHC_HC1R_DW_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC1R_DW_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= ~SDHC_HC1R_DW; + tmp |= value << SDHC_HC1R_DW_Pos; + ((Sdhc *)hw)->HC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_DW_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_DW; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_DW_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_DW; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC1R_HSEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_HSEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC1R_HSEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_HSEN) >> SDHC_HC1R_HSEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC1R_HSEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= ~SDHC_HC1R_HSEN; + tmp |= value << SDHC_HC1R_HSEN_Pos; + ((Sdhc *)hw)->HC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_HSEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_HSEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_HSEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_HSEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC1R_CARDDTL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_CARDDTL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC1R_CARDDTL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_CARDDTL) >> SDHC_HC1R_CARDDTL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC1R_CARDDTL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= ~SDHC_HC1R_CARDDTL; + tmp |= value << SDHC_HC1R_CARDDTL_Pos; + ((Sdhc *)hw)->HC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_CARDDTL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_CARDDTL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_CARDDTL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_CARDDTL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC1R_CARDDSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_CARDDSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC1R_CARDDSEL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_CARDDSEL) >> SDHC_HC1R_CARDDSEL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC1R_CARDDSEL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= ~SDHC_HC1R_CARDDSEL; + tmp |= value << SDHC_HC1R_CARDDSEL_Pos; + ((Sdhc *)hw)->HC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_CARDDSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_CARDDSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_CARDDSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_CARDDSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= SDHC_HC1R_DMASEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc1r_reg_t hri_sdhc_get_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_DMASEL(mask)) >> SDHC_HC1R_DMASEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t data) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= ~SDHC_HC1R_DMASEL_Msk; + tmp |= SDHC_HC1R_DMASEL(data); + ((Sdhc *)hw)->HC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~SDHC_HC1R_DMASEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_DMASEL_bf(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= SDHC_HC1R_DMASEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc1r_reg_t hri_sdhc_read_HC1R_DMASEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp = (tmp & SDHC_HC1R_DMASEL_Msk) >> SDHC_HC1R_DMASEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc1r_reg_t hri_sdhc_get_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->HC1R.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC1R_reg(const void *const hw, hri_sdhc_hc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC1R.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc1r_reg_t hri_sdhc_read_HC1R_reg(const void *const hw) +{ + return ((Sdhc *)hw)->HC1R.reg; +} + +static inline void hri_sdhc_set_PCR_SDBPWR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg |= SDHC_PCR_SDBPWR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_PCR_SDBPWR_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->PCR.reg; + tmp = (tmp & SDHC_PCR_SDBPWR) >> SDHC_PCR_SDBPWR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_PCR_SDBPWR_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->PCR.reg; + tmp &= ~SDHC_PCR_SDBPWR; + tmp |= value << SDHC_PCR_SDBPWR_Pos; + ((Sdhc *)hw)->PCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_PCR_SDBPWR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg &= ~SDHC_PCR_SDBPWR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_PCR_SDBPWR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg ^= SDHC_PCR_SDBPWR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg |= SDHC_PCR_SDBVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pcr_reg_t hri_sdhc_get_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->PCR.reg; + tmp = (tmp & SDHC_PCR_SDBVSEL(mask)) >> SDHC_PCR_SDBVSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t data) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->PCR.reg; + tmp &= ~SDHC_PCR_SDBVSEL_Msk; + tmp |= SDHC_PCR_SDBVSEL(data); + ((Sdhc *)hw)->PCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg &= ~SDHC_PCR_SDBVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_PCR_SDBVSEL_bf(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg ^= SDHC_PCR_SDBVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pcr_reg_t hri_sdhc_read_PCR_SDBVSEL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->PCR.reg; + tmp = (tmp & SDHC_PCR_SDBVSEL_Msk) >> SDHC_PCR_SDBVSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pcr_reg_t hri_sdhc_get_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->PCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_PCR_reg(const void *const hw, hri_sdhc_pcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PCR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pcr_reg_t hri_sdhc_read_PCR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->PCR.reg; +} + +static inline void hri_sdhc_set_BGCR_STPBGR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_STPBGR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_BGCR_STPBGR_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp = (tmp & SDHC_BGCR_STPBGR) >> SDHC_BGCR_STPBGR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_BGCR_STPBGR_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp &= ~SDHC_BGCR_STPBGR; + tmp |= value << SDHC_BGCR_STPBGR_Pos; + ((Sdhc *)hw)->BGCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BGCR_STPBGR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_STPBGR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BGCR_STPBGR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_STPBGR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_BGCR_CONTR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_CONTR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_BGCR_CONTR_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp = (tmp & SDHC_BGCR_CONTR) >> SDHC_BGCR_CONTR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_BGCR_CONTR_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp &= ~SDHC_BGCR_CONTR; + tmp |= value << SDHC_BGCR_CONTR_Pos; + ((Sdhc *)hw)->BGCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BGCR_CONTR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_CONTR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BGCR_CONTR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_CONTR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_BGCR_RWCTRL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_RWCTRL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_BGCR_RWCTRL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp = (tmp & SDHC_BGCR_RWCTRL) >> SDHC_BGCR_RWCTRL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_BGCR_RWCTRL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp &= ~SDHC_BGCR_RWCTRL; + tmp |= value << SDHC_BGCR_RWCTRL_Pos; + ((Sdhc *)hw)->BGCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BGCR_RWCTRL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_RWCTRL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BGCR_RWCTRL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_RWCTRL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_BGCR_INTBG_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg |= SDHC_BGCR_INTBG; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_BGCR_INTBG_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp = (tmp & SDHC_BGCR_INTBG) >> SDHC_BGCR_INTBG_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_BGCR_INTBG_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp &= ~SDHC_BGCR_INTBG; + tmp |= value << SDHC_BGCR_INTBG_Pos; + ((Sdhc *)hw)->BGCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BGCR_INTBG_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg &= ~SDHC_BGCR_INTBG; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BGCR_INTBG_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg ^= SDHC_BGCR_INTBG; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bgcr_reg_t hri_sdhc_get_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->BGCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_BGCR_reg(const void *const hw, hri_sdhc_bgcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->BGCR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_bgcr_reg_t hri_sdhc_read_BGCR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->BGCR.reg; +} + +static inline void hri_sdhc_set_WCR_WKENCINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg |= SDHC_WCR_WKENCINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_WCR_WKENCINT_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->WCR.reg; + tmp = (tmp & SDHC_WCR_WKENCINT) >> SDHC_WCR_WKENCINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_WCR_WKENCINT_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->WCR.reg; + tmp &= ~SDHC_WCR_WKENCINT; + tmp |= value << SDHC_WCR_WKENCINT_Pos; + ((Sdhc *)hw)->WCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_WCR_WKENCINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg &= ~SDHC_WCR_WKENCINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_WCR_WKENCINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg ^= SDHC_WCR_WKENCINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_WCR_WKENCINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg |= SDHC_WCR_WKENCINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_WCR_WKENCINS_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->WCR.reg; + tmp = (tmp & SDHC_WCR_WKENCINS) >> SDHC_WCR_WKENCINS_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_WCR_WKENCINS_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->WCR.reg; + tmp &= ~SDHC_WCR_WKENCINS; + tmp |= value << SDHC_WCR_WKENCINS_Pos; + ((Sdhc *)hw)->WCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_WCR_WKENCINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg &= ~SDHC_WCR_WKENCINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_WCR_WKENCINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg ^= SDHC_WCR_WKENCINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_WCR_WKENCREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg |= SDHC_WCR_WKENCREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_WCR_WKENCREM_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->WCR.reg; + tmp = (tmp & SDHC_WCR_WKENCREM) >> SDHC_WCR_WKENCREM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_WCR_WKENCREM_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->WCR.reg; + tmp &= ~SDHC_WCR_WKENCREM; + tmp |= value << SDHC_WCR_WKENCREM_Pos; + ((Sdhc *)hw)->WCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_WCR_WKENCREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg &= ~SDHC_WCR_WKENCREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_WCR_WKENCREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg ^= SDHC_WCR_WKENCREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_wcr_reg_t hri_sdhc_get_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->WCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_WCR_reg(const void *const hw, hri_sdhc_wcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->WCR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_wcr_reg_t hri_sdhc_read_WCR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->WCR.reg; +} + +static inline void hri_sdhc_set_CCR_INTCLKEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_INTCLKEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CCR_INTCLKEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_INTCLKEN) >> SDHC_CCR_INTCLKEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CCR_INTCLKEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CCR.reg; + tmp &= ~SDHC_CCR_INTCLKEN; + tmp |= value << SDHC_CCR_INTCLKEN_Pos; + ((Sdhc *)hw)->CCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CCR_INTCLKEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_INTCLKEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CCR_INTCLKEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_INTCLKEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CCR_INTCLKS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_INTCLKS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CCR_INTCLKS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_INTCLKS) >> SDHC_CCR_INTCLKS_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CCR_INTCLKS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CCR.reg; + tmp &= ~SDHC_CCR_INTCLKS; + tmp |= value << SDHC_CCR_INTCLKS_Pos; + ((Sdhc *)hw)->CCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CCR_INTCLKS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_INTCLKS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CCR_INTCLKS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_INTCLKS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CCR_SDCLKEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_SDCLKEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CCR_SDCLKEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_SDCLKEN) >> SDHC_CCR_SDCLKEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CCR_SDCLKEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CCR.reg; + tmp &= ~SDHC_CCR_SDCLKEN; + tmp |= value << SDHC_CCR_SDCLKEN_Pos; + ((Sdhc *)hw)->CCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CCR_SDCLKEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_SDCLKEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CCR_SDCLKEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_SDCLKEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CCR_CLKGSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_CLKGSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CCR_CLKGSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_CLKGSEL) >> SDHC_CCR_CLKGSEL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CCR_CLKGSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CCR.reg; + tmp &= ~SDHC_CCR_CLKGSEL; + tmp |= value << SDHC_CCR_CLKGSEL_Pos; + ((Sdhc *)hw)->CCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CCR_CLKGSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_CLKGSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CCR_CLKGSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_CLKGSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_USDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ccr_reg_t hri_sdhc_get_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_USDCLKFSEL(mask)) >> SDHC_CCR_USDCLKFSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CCR.reg; + tmp &= ~SDHC_CCR_USDCLKFSEL_Msk; + tmp |= SDHC_CCR_USDCLKFSEL(data); + ((Sdhc *)hw)->CCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_USDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CCR_USDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_USDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ccr_reg_t hri_sdhc_read_CCR_USDCLKFSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_USDCLKFSEL_Msk) >> SDHC_CCR_USDCLKFSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg |= SDHC_CCR_SDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ccr_reg_t hri_sdhc_get_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_SDCLKFSEL(mask)) >> SDHC_CCR_SDCLKFSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CCR.reg; + tmp &= ~SDHC_CCR_SDCLKFSEL_Msk; + tmp |= SDHC_CCR_SDCLKFSEL(data); + ((Sdhc *)hw)->CCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg &= ~SDHC_CCR_SDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CCR_SDCLKFSEL_bf(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg ^= SDHC_CCR_SDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ccr_reg_t hri_sdhc_read_CCR_SDCLKFSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp = (tmp & SDHC_CCR_SDCLKFSEL_Msk) >> SDHC_CCR_SDCLKFSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ccr_reg_t hri_sdhc_get_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->CCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CCR_reg(const void *const hw, hri_sdhc_ccr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CCR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_ccr_reg_t hri_sdhc_read_CCR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->CCR.reg; +} + +static inline void hri_sdhc_set_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TCR.reg |= SDHC_TCR_DTCVAL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tcr_reg_t hri_sdhc_get_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->TCR.reg; + tmp = (tmp & SDHC_TCR_DTCVAL(mask)) >> SDHC_TCR_DTCVAL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t data) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->TCR.reg; + tmp &= ~SDHC_TCR_DTCVAL_Msk; + tmp |= SDHC_TCR_DTCVAL(data); + ((Sdhc *)hw)->TCR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TCR.reg &= ~SDHC_TCR_DTCVAL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TCR_DTCVAL_bf(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TCR.reg ^= SDHC_TCR_DTCVAL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tcr_reg_t hri_sdhc_read_TCR_DTCVAL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->TCR.reg; + tmp = (tmp & SDHC_TCR_DTCVAL_Msk) >> SDHC_TCR_DTCVAL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TCR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tcr_reg_t hri_sdhc_get_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->TCR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TCR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TCR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_TCR_reg(const void *const hw, hri_sdhc_tcr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->TCR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_tcr_reg_t hri_sdhc_read_TCR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->TCR.reg; +} + +static inline void hri_sdhc_set_SRR_SWRSTALL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTALL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_SRR_SWRSTALL_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->SRR.reg; + tmp = (tmp & SDHC_SRR_SWRSTALL) >> SDHC_SRR_SWRSTALL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_SRR_SWRSTALL_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->SRR.reg; + tmp &= ~SDHC_SRR_SWRSTALL; + tmp |= value << SDHC_SRR_SWRSTALL_Pos; + ((Sdhc *)hw)->SRR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_SRR_SWRSTALL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg &= ~SDHC_SRR_SWRSTALL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_SRR_SWRSTALL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg ^= SDHC_SRR_SWRSTALL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_SRR_SWRSTCMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTCMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_SRR_SWRSTCMD_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->SRR.reg; + tmp = (tmp & SDHC_SRR_SWRSTCMD) >> SDHC_SRR_SWRSTCMD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_SRR_SWRSTCMD_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->SRR.reg; + tmp &= ~SDHC_SRR_SWRSTCMD; + tmp |= value << SDHC_SRR_SWRSTCMD_Pos; + ((Sdhc *)hw)->SRR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_SRR_SWRSTCMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg &= ~SDHC_SRR_SWRSTCMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_SRR_SWRSTCMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg ^= SDHC_SRR_SWRSTCMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_SRR_SWRSTDAT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg |= SDHC_SRR_SWRSTDAT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_SRR_SWRSTDAT_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->SRR.reg; + tmp = (tmp & SDHC_SRR_SWRSTDAT) >> SDHC_SRR_SWRSTDAT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_SRR_SWRSTDAT_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->SRR.reg; + tmp &= ~SDHC_SRR_SWRSTDAT; + tmp |= value << SDHC_SRR_SWRSTDAT_Pos; + ((Sdhc *)hw)->SRR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_SRR_SWRSTDAT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg &= ~SDHC_SRR_SWRSTDAT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_SRR_SWRSTDAT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg ^= SDHC_SRR_SWRSTDAT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_srr_reg_t hri_sdhc_get_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->SRR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_SRR_reg(const void *const hw, hri_sdhc_srr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->SRR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_srr_reg_t hri_sdhc_read_SRR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->SRR.reg; +} + +static inline void hri_sdhc_set_NISTR_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_CMDC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_CMDC) >> SDHC_NISTR_CMDC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_CMDC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_CMDC; + tmp |= value << SDHC_NISTR_CMDC_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_TRFC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_TRFC) >> SDHC_NISTR_TRFC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_TRFC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_TRFC; + tmp |= value << SDHC_NISTR_TRFC_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_BLKGE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_BLKGE) >> SDHC_NISTR_BLKGE_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_BLKGE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_BLKGE; + tmp |= value << SDHC_NISTR_BLKGE_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_DMAINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_DMAINT) >> SDHC_NISTR_DMAINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_DMAINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_DMAINT; + tmp |= value << SDHC_NISTR_DMAINT_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_BWRRDY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_BWRRDY) >> SDHC_NISTR_BWRRDY_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_BWRRDY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_BWRRDY; + tmp |= value << SDHC_NISTR_BWRRDY_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_BRDRDY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_BRDRDY) >> SDHC_NISTR_BRDRDY_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_BRDRDY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_BRDRDY; + tmp |= value << SDHC_NISTR_BRDRDY_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_CINS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_CINS) >> SDHC_NISTR_CINS_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_CINS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_CINS; + tmp |= value << SDHC_NISTR_CINS_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_CREM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_CREM) >> SDHC_NISTR_CREM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_CREM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_CREM; + tmp |= value << SDHC_NISTR_CREM_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_CINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_CINT) >> SDHC_NISTR_CINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_CINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_CINT; + tmp |= value << SDHC_NISTR_CINT_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_EMMC_BOOTAR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_EMMC_BOOTAR) >> SDHC_NISTR_EMMC_BOOTAR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_EMMC_BOOTAR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_EMMC_BOOTAR; + tmp |= value << SDHC_NISTR_EMMC_BOOTAR_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_ERRINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= SDHC_NISTR_ERRINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTR_ERRINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp = (tmp & SDHC_NISTR_ERRINT) >> SDHC_NISTR_ERRINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTR_ERRINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= ~SDHC_NISTR_ERRINT; + tmp |= value << SDHC_NISTR_ERRINT_Pos; + ((Sdhc *)hw)->NISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_ERRINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~SDHC_NISTR_ERRINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_ERRINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= SDHC_NISTR_ERRINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_nistr_reg_t hri_sdhc_get_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTR_reg(const void *const hw, hri_sdhc_nistr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_nistr_reg_t hri_sdhc_read_NISTR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->NISTR.reg; +} + +static inline void hri_sdhc_set_EISTR_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_CMDTEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_CMDTEO) >> SDHC_EISTR_CMDTEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_CMDTEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_CMDTEO; + tmp |= value << SDHC_EISTR_CMDTEO_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_CMDCRC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_CMDCRC) >> SDHC_EISTR_CMDCRC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_CMDCRC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_CMDCRC; + tmp |= value << SDHC_EISTR_CMDCRC_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_CMDEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_CMDEND) >> SDHC_EISTR_CMDEND_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_CMDEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_CMDEND; + tmp |= value << SDHC_EISTR_CMDEND_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_CMDIDX_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_CMDIDX) >> SDHC_EISTR_CMDIDX_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_CMDIDX_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_CMDIDX; + tmp |= value << SDHC_EISTR_CMDIDX_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_DATTEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_DATTEO) >> SDHC_EISTR_DATTEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_DATTEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_DATTEO; + tmp |= value << SDHC_EISTR_DATTEO_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_DATCRC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_DATCRC) >> SDHC_EISTR_DATCRC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_DATCRC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_DATCRC; + tmp |= value << SDHC_EISTR_DATCRC_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_DATEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_DATEND) >> SDHC_EISTR_DATEND_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_DATEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_DATEND; + tmp |= value << SDHC_EISTR_DATEND_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_CURLIM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_CURLIM) >> SDHC_EISTR_CURLIM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_CURLIM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_CURLIM; + tmp |= value << SDHC_EISTR_CURLIM_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_ACMD_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_ACMD) >> SDHC_EISTR_ACMD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_ACMD_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_ACMD; + tmp |= value << SDHC_EISTR_ACMD_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_ADMA_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_ADMA) >> SDHC_EISTR_ADMA_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_ADMA_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_ADMA; + tmp |= value << SDHC_EISTR_ADMA_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= SDHC_EISTR_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTR_EMMC_BOOTAE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp = (tmp & SDHC_EISTR_EMMC_BOOTAE) >> SDHC_EISTR_EMMC_BOOTAE_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTR_EMMC_BOOTAE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= ~SDHC_EISTR_EMMC_BOOTAE; + tmp |= value << SDHC_EISTR_EMMC_BOOTAE_Pos; + ((Sdhc *)hw)->EISTR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~SDHC_EISTR_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= SDHC_EISTR_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_eistr_reg_t hri_sdhc_get_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTR_reg(const void *const hw, hri_sdhc_eistr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_eistr_reg_t hri_sdhc_read_EISTR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->EISTR.reg; +} + +static inline void hri_sdhc_set_NISTER_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_CMDC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_CMDC) >> SDHC_NISTER_CMDC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_CMDC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_CMDC; + tmp |= value << SDHC_NISTER_CMDC_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_TRFC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_TRFC) >> SDHC_NISTER_TRFC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_TRFC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_TRFC; + tmp |= value << SDHC_NISTER_TRFC_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_BLKGE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_BLKGE) >> SDHC_NISTER_BLKGE_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_BLKGE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_BLKGE; + tmp |= value << SDHC_NISTER_BLKGE_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_DMAINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_DMAINT) >> SDHC_NISTER_DMAINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_DMAINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_DMAINT; + tmp |= value << SDHC_NISTER_DMAINT_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_BWRRDY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_BWRRDY) >> SDHC_NISTER_BWRRDY_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_BWRRDY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_BWRRDY; + tmp |= value << SDHC_NISTER_BWRRDY_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_BRDRDY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_BRDRDY) >> SDHC_NISTER_BRDRDY_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_BRDRDY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_BRDRDY; + tmp |= value << SDHC_NISTER_BRDRDY_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_CINS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_CINS) >> SDHC_NISTER_CINS_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_CINS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_CINS; + tmp |= value << SDHC_NISTER_CINS_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_CREM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_CREM) >> SDHC_NISTER_CREM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_CREM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_CREM; + tmp |= value << SDHC_NISTER_CREM_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_CINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_CINT) >> SDHC_NISTER_CINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_CINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_CINT; + tmp |= value << SDHC_NISTER_CINT_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= SDHC_NISTER_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISTER_EMMC_BOOTAR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp = (tmp & SDHC_NISTER_EMMC_BOOTAR) >> SDHC_NISTER_EMMC_BOOTAR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISTER_EMMC_BOOTAR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= ~SDHC_NISTER_EMMC_BOOTAR; + tmp |= value << SDHC_NISTER_EMMC_BOOTAR_Pos; + ((Sdhc *)hw)->NISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~SDHC_NISTER_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= SDHC_NISTER_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_nister_reg_t hri_sdhc_get_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISTER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISTER_reg(const void *const hw, hri_sdhc_nister_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISTER.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_nister_reg_t hri_sdhc_read_NISTER_reg(const void *const hw) +{ + return ((Sdhc *)hw)->NISTER.reg; +} + +static inline void hri_sdhc_set_EISTER_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_CMDTEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_CMDTEO) >> SDHC_EISTER_CMDTEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_CMDTEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_CMDTEO; + tmp |= value << SDHC_EISTER_CMDTEO_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_CMDCRC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_CMDCRC) >> SDHC_EISTER_CMDCRC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_CMDCRC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_CMDCRC; + tmp |= value << SDHC_EISTER_CMDCRC_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_CMDEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_CMDEND) >> SDHC_EISTER_CMDEND_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_CMDEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_CMDEND; + tmp |= value << SDHC_EISTER_CMDEND_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_CMDIDX_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_CMDIDX) >> SDHC_EISTER_CMDIDX_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_CMDIDX_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_CMDIDX; + tmp |= value << SDHC_EISTER_CMDIDX_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_DATTEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_DATTEO) >> SDHC_EISTER_DATTEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_DATTEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_DATTEO; + tmp |= value << SDHC_EISTER_DATTEO_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_DATCRC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_DATCRC) >> SDHC_EISTER_DATCRC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_DATCRC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_DATCRC; + tmp |= value << SDHC_EISTER_DATCRC_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_DATEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_DATEND) >> SDHC_EISTER_DATEND_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_DATEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_DATEND; + tmp |= value << SDHC_EISTER_DATEND_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_CURLIM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_CURLIM) >> SDHC_EISTER_CURLIM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_CURLIM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_CURLIM; + tmp |= value << SDHC_EISTER_CURLIM_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_ACMD_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_ACMD) >> SDHC_EISTER_ACMD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_ACMD_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_ACMD; + tmp |= value << SDHC_EISTER_ACMD_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_ADMA_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_ADMA) >> SDHC_EISTER_ADMA_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_ADMA_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_ADMA; + tmp |= value << SDHC_EISTER_ADMA_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= SDHC_EISTER_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISTER_EMMC_BOOTAE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp = (tmp & SDHC_EISTER_EMMC_BOOTAE) >> SDHC_EISTER_EMMC_BOOTAE_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISTER_EMMC_BOOTAE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= ~SDHC_EISTER_EMMC_BOOTAE; + tmp |= value << SDHC_EISTER_EMMC_BOOTAE_Pos; + ((Sdhc *)hw)->EISTER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~SDHC_EISTER_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= SDHC_EISTER_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_eister_reg_t hri_sdhc_get_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISTER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISTER_reg(const void *const hw, hri_sdhc_eister_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISTER.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_eister_reg_t hri_sdhc_read_EISTER_reg(const void *const hw) +{ + return ((Sdhc *)hw)->EISTER.reg; +} + +static inline void hri_sdhc_set_NISIER_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_CMDC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_CMDC) >> SDHC_NISIER_CMDC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_CMDC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_CMDC; + tmp |= value << SDHC_NISIER_CMDC_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_CMDC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CMDC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_TRFC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_TRFC) >> SDHC_NISIER_TRFC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_TRFC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_TRFC; + tmp |= value << SDHC_NISIER_TRFC_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_TRFC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_TRFC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_BLKGE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_BLKGE) >> SDHC_NISIER_BLKGE_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_BLKGE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_BLKGE; + tmp |= value << SDHC_NISIER_BLKGE_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_BLKGE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_BLKGE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_DMAINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_DMAINT) >> SDHC_NISIER_DMAINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_DMAINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_DMAINT; + tmp |= value << SDHC_NISIER_DMAINT_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_DMAINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_DMAINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_BWRRDY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_BWRRDY) >> SDHC_NISIER_BWRRDY_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_BWRRDY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_BWRRDY; + tmp |= value << SDHC_NISIER_BWRRDY_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_BWRRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_BWRRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_BRDRDY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_BRDRDY) >> SDHC_NISIER_BRDRDY_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_BRDRDY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_BRDRDY; + tmp |= value << SDHC_NISIER_BRDRDY_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_BRDRDY_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_BRDRDY; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_CINS_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_CINS) >> SDHC_NISIER_CINS_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_CINS_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_CINS; + tmp |= value << SDHC_NISIER_CINS_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_CINS_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CINS; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_CREM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_CREM) >> SDHC_NISIER_CREM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_CREM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_CREM; + tmp |= value << SDHC_NISIER_CREM_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_CREM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CREM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_CINT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_CINT) >> SDHC_NISIER_CINT_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_CINT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_CINT; + tmp |= value << SDHC_NISIER_CINT_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_CINT_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_CINT; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= SDHC_NISIER_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_NISIER_EMMC_BOOTAR_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp = (tmp & SDHC_NISIER_EMMC_BOOTAR) >> SDHC_NISIER_EMMC_BOOTAR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_NISIER_EMMC_BOOTAR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= ~SDHC_NISIER_EMMC_BOOTAR; + tmp |= value << SDHC_NISIER_EMMC_BOOTAR_Pos; + ((Sdhc *)hw)->NISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~SDHC_NISIER_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_EMMC_BOOTAR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= SDHC_NISIER_EMMC_BOOTAR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_nisier_reg_t hri_sdhc_get_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->NISIER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_NISIER_reg(const void *const hw, hri_sdhc_nisier_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->NISIER.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_nisier_reg_t hri_sdhc_read_NISIER_reg(const void *const hw) +{ + return ((Sdhc *)hw)->NISIER.reg; +} + +static inline void hri_sdhc_set_EISIER_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_CMDTEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_CMDTEO) >> SDHC_EISIER_CMDTEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_CMDTEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_CMDTEO; + tmp |= value << SDHC_EISIER_CMDTEO_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_CMDTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_CMDCRC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_CMDCRC) >> SDHC_EISIER_CMDCRC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_CMDCRC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_CMDCRC; + tmp |= value << SDHC_EISIER_CMDCRC_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_CMDCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_CMDEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_CMDEND) >> SDHC_EISIER_CMDEND_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_CMDEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_CMDEND; + tmp |= value << SDHC_EISIER_CMDEND_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_CMDEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_CMDIDX_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_CMDIDX) >> SDHC_EISIER_CMDIDX_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_CMDIDX_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_CMDIDX; + tmp |= value << SDHC_EISIER_CMDIDX_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_CMDIDX_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CMDIDX; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_DATTEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_DATTEO) >> SDHC_EISIER_DATTEO_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_DATTEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_DATTEO; + tmp |= value << SDHC_EISIER_DATTEO_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_DATTEO_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_DATTEO; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_DATCRC_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_DATCRC) >> SDHC_EISIER_DATCRC_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_DATCRC_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_DATCRC; + tmp |= value << SDHC_EISIER_DATCRC_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_DATCRC_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_DATCRC; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_DATEND_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_DATEND) >> SDHC_EISIER_DATEND_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_DATEND_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_DATEND; + tmp |= value << SDHC_EISIER_DATEND_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_DATEND_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_DATEND; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_CURLIM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_CURLIM) >> SDHC_EISIER_CURLIM_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_CURLIM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_CURLIM; + tmp |= value << SDHC_EISIER_CURLIM_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_CURLIM_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_CURLIM; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_ACMD_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_ACMD) >> SDHC_EISIER_ACMD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_ACMD_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_ACMD; + tmp |= value << SDHC_EISIER_ACMD_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_ACMD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_ACMD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_ADMA_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_ADMA) >> SDHC_EISIER_ADMA_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_ADMA_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_ADMA; + tmp |= value << SDHC_EISIER_ADMA_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_ADMA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_ADMA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= SDHC_EISIER_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_EISIER_EMMC_BOOTAE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp = (tmp & SDHC_EISIER_EMMC_BOOTAE) >> SDHC_EISIER_EMMC_BOOTAE_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_EISIER_EMMC_BOOTAE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= ~SDHC_EISIER_EMMC_BOOTAE; + tmp |= value << SDHC_EISIER_EMMC_BOOTAE_Pos; + ((Sdhc *)hw)->EISIER.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~SDHC_EISIER_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_EMMC_BOOTAE_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= SDHC_EISIER_EMMC_BOOTAE; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_eisier_reg_t hri_sdhc_get_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->EISIER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_EISIER_reg(const void *const hw, hri_sdhc_eisier_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->EISIER.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_eisier_reg_t hri_sdhc_read_EISIER_reg(const void *const hw) +{ + return ((Sdhc *)hw)->EISIER.reg; +} + +static inline void hri_sdhc_set_HC2R_VS18EN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_VS18EN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC2R_VS18EN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_VS18EN) >> SDHC_HC2R_VS18EN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC2R_VS18EN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_VS18EN; + tmp |= value << SDHC_HC2R_VS18EN_Pos; + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_VS18EN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_VS18EN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_VS18EN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_VS18EN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC2R_EXTUN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_EXTUN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC2R_EXTUN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_EXTUN) >> SDHC_HC2R_EXTUN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC2R_EXTUN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_EXTUN; + tmp |= value << SDHC_HC2R_EXTUN_Pos; + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_EXTUN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_EXTUN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_EXTUN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_EXTUN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC2R_SLCKSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_SLCKSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC2R_SLCKSEL_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_SLCKSEL) >> SDHC_HC2R_SLCKSEL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC2R_SLCKSEL_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_SLCKSEL; + tmp |= value << SDHC_HC2R_SLCKSEL_Pos; + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_SLCKSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_SLCKSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_SLCKSEL_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_SLCKSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC2R_ASINTEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_ASINTEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC2R_ASINTEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_ASINTEN) >> SDHC_HC2R_ASINTEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC2R_ASINTEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_ASINTEN; + tmp |= value << SDHC_HC2R_ASINTEN_Pos; + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_ASINTEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_ASINTEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_ASINTEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_ASINTEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC2R_PVALEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_PVALEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_HC2R_PVALEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_PVALEN) >> SDHC_HC2R_PVALEN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_HC2R_PVALEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_PVALEN; + tmp |= value << SDHC_HC2R_PVALEN_Pos; + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_PVALEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_PVALEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_PVALEN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_PVALEN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_UHSMS(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_UHSMS(mask)) >> SDHC_HC2R_UHSMS_Pos; + return tmp; +} + +static inline void hri_sdhc_write_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_UHSMS_Msk; + tmp |= SDHC_HC2R_UHSMS(data); + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_UHSMS(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_UHSMS_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_UHSMS(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_UHSMS_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_UHSMS_Msk) >> SDHC_HC2R_UHSMS_Pos; + return tmp; +} + +static inline void hri_sdhc_set_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_EMMC_HS200EN(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_EMMC_HS200EN(mask)) >> SDHC_HC2R_EMMC_HS200EN_Pos; + return tmp; +} + +static inline void hri_sdhc_write_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_EMMC_HS200EN_Msk; + tmp |= SDHC_HC2R_EMMC_HS200EN(data); + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_EMMC_HS200EN(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_EMMC_HS200EN_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_EMMC_HS200EN(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_EMMC_HS200EN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_EMMC_HS200EN_Msk) >> SDHC_HC2R_EMMC_HS200EN_Pos; + return tmp; +} + +static inline void hri_sdhc_set_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= SDHC_HC2R_DRVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_DRVSEL(mask)) >> SDHC_HC2R_DRVSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= ~SDHC_HC2R_DRVSEL_Msk; + tmp |= SDHC_HC2R_DRVSEL(data); + ((Sdhc *)hw)->HC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~SDHC_HC2R_DRVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_DRVSEL_bf(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= SDHC_HC2R_DRVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_DRVSEL_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp = (tmp & SDHC_HC2R_DRVSEL_Msk) >> SDHC_HC2R_DRVSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_get_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->HC2R.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_HC2R_reg(const void *const hw, hri_sdhc_hc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->HC2R.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_hc2r_reg_t hri_sdhc_read_HC2R_reg(const void *const hw) +{ + return ((Sdhc *)hw)->HC2R.reg; +} + +static inline void hri_sdhc_set_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ASAR[index].reg |= SDHC_ASAR_ADMASA(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_asar_reg_t hri_sdhc_get_ASAR_ADMASA_bf(const void *const hw, uint8_t index, + hri_sdhc_asar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ASAR[index].reg; + tmp = (tmp & SDHC_ASAR_ADMASA(mask)) >> SDHC_ASAR_ADMASA_Pos; + return tmp; +} + +static inline void hri_sdhc_write_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t data) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->ASAR[index].reg; + tmp &= ~SDHC_ASAR_ADMASA_Msk; + tmp |= SDHC_ASAR_ADMASA(data); + ((Sdhc *)hw)->ASAR[index].reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ASAR[index].reg &= ~SDHC_ASAR_ADMASA(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_ASAR_ADMASA_bf(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ASAR[index].reg ^= SDHC_ASAR_ADMASA(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_asar_reg_t hri_sdhc_read_ASAR_ADMASA_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ASAR[index].reg; + tmp = (tmp & SDHC_ASAR_ADMASA_Msk) >> SDHC_ASAR_ADMASA_Pos; + return tmp; +} + +static inline void hri_sdhc_set_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ASAR[index].reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_asar_reg_t hri_sdhc_get_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ASAR[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ASAR[index].reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ASAR[index].reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_ASAR_reg(const void *const hw, uint8_t index, hri_sdhc_asar_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ASAR[index].reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_asar_reg_t hri_sdhc_read_ASAR_reg(const void *const hw, uint8_t index) +{ + return ((Sdhc *)hw)->ASAR[index].reg; +} + +static inline void hri_sdhc_set_PVR_CLKGSEL_bit(const void *const hw, uint8_t index) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg |= SDHC_PVR_CLKGSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_PVR_CLKGSEL_bit(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp = (tmp & SDHC_PVR_CLKGSEL) >> SDHC_PVR_CLKGSEL_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_PVR_CLKGSEL_bit(const void *const hw, uint8_t index, bool value) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp &= ~SDHC_PVR_CLKGSEL; + tmp |= value << SDHC_PVR_CLKGSEL_Pos; + ((Sdhc *)hw)->PVR[index].reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_PVR_CLKGSEL_bit(const void *const hw, uint8_t index) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg &= ~SDHC_PVR_CLKGSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_PVR_CLKGSEL_bit(const void *const hw, uint8_t index) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg ^= SDHC_PVR_CLKGSEL; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg |= SDHC_PVR_SDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pvr_reg_t hri_sdhc_get_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, + hri_sdhc_pvr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp = (tmp & SDHC_PVR_SDCLKFSEL(mask)) >> SDHC_PVR_SDCLKFSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp &= ~SDHC_PVR_SDCLKFSEL_Msk; + tmp |= SDHC_PVR_SDCLKFSEL(data); + ((Sdhc *)hw)->PVR[index].reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg &= ~SDHC_PVR_SDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg ^= SDHC_PVR_SDCLKFSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pvr_reg_t hri_sdhc_read_PVR_SDCLKFSEL_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp = (tmp & SDHC_PVR_SDCLKFSEL_Msk) >> SDHC_PVR_SDCLKFSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg |= SDHC_PVR_DRVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pvr_reg_t hri_sdhc_get_PVR_DRVSEL_bf(const void *const hw, uint8_t index, + hri_sdhc_pvr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp = (tmp & SDHC_PVR_DRVSEL(mask)) >> SDHC_PVR_DRVSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_write_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t data) +{ + uint16_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp &= ~SDHC_PVR_DRVSEL_Msk; + tmp |= SDHC_PVR_DRVSEL(data); + ((Sdhc *)hw)->PVR[index].reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg &= ~SDHC_PVR_DRVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_PVR_DRVSEL_bf(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg ^= SDHC_PVR_DRVSEL(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pvr_reg_t hri_sdhc_read_PVR_DRVSEL_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp = (tmp & SDHC_PVR_DRVSEL_Msk) >> SDHC_PVR_DRVSEL_Pos; + return tmp; +} + +static inline void hri_sdhc_set_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pvr_reg_t hri_sdhc_get_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sdhc *)hw)->PVR[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_PVR_reg(const void *const hw, uint8_t index, hri_sdhc_pvr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->PVR[index].reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_pvr_reg_t hri_sdhc_read_PVR_reg(const void *const hw, uint8_t index) +{ + return ((Sdhc *)hw)->PVR[index].reg; +} + +static inline void hri_sdhc_set_MC1R_DDR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_DDR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_MC1R_DDR_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp = (tmp & SDHC_MC1R_DDR) >> SDHC_MC1R_DDR_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_MC1R_DDR_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp &= ~SDHC_MC1R_DDR; + tmp |= value << SDHC_MC1R_DDR_Pos; + ((Sdhc *)hw)->MC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_MC1R_DDR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_DDR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_MC1R_DDR_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_DDR; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_MC1R_OPD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_OPD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_MC1R_OPD_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp = (tmp & SDHC_MC1R_OPD) >> SDHC_MC1R_OPD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_MC1R_OPD_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp &= ~SDHC_MC1R_OPD; + tmp |= value << SDHC_MC1R_OPD_Pos; + ((Sdhc *)hw)->MC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_MC1R_OPD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_OPD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_MC1R_OPD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_OPD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_MC1R_BOOTA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_BOOTA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_MC1R_BOOTA_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp = (tmp & SDHC_MC1R_BOOTA) >> SDHC_MC1R_BOOTA_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_MC1R_BOOTA_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp &= ~SDHC_MC1R_BOOTA; + tmp |= value << SDHC_MC1R_BOOTA_Pos; + ((Sdhc *)hw)->MC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_MC1R_BOOTA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_BOOTA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_MC1R_BOOTA_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_BOOTA; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_MC1R_RSTN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_RSTN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_MC1R_RSTN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp = (tmp & SDHC_MC1R_RSTN) >> SDHC_MC1R_RSTN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_MC1R_RSTN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp &= ~SDHC_MC1R_RSTN; + tmp |= value << SDHC_MC1R_RSTN_Pos; + ((Sdhc *)hw)->MC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_MC1R_RSTN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_RSTN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_MC1R_RSTN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_RSTN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_MC1R_FCD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_FCD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_MC1R_FCD_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp = (tmp & SDHC_MC1R_FCD) >> SDHC_MC1R_FCD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_MC1R_FCD_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp &= ~SDHC_MC1R_FCD; + tmp |= value << SDHC_MC1R_FCD_Pos; + ((Sdhc *)hw)->MC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_MC1R_FCD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_FCD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_MC1R_FCD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_FCD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg |= SDHC_MC1R_CMDTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_mc1r_reg_t hri_sdhc_get_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp = (tmp & SDHC_MC1R_CMDTYP(mask)) >> SDHC_MC1R_CMDTYP_Pos; + return tmp; +} + +static inline void hri_sdhc_write_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t data) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp &= ~SDHC_MC1R_CMDTYP_Msk; + tmp |= SDHC_MC1R_CMDTYP(data); + ((Sdhc *)hw)->MC1R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg &= ~SDHC_MC1R_CMDTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_MC1R_CMDTYP_bf(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg ^= SDHC_MC1R_CMDTYP(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_mc1r_reg_t hri_sdhc_read_MC1R_CMDTYP_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp = (tmp & SDHC_MC1R_CMDTYP_Msk) >> SDHC_MC1R_CMDTYP_Pos; + return tmp; +} + +static inline void hri_sdhc_set_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_mc1r_reg_t hri_sdhc_get_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->MC1R.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_MC1R_reg(const void *const hw, hri_sdhc_mc1r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC1R.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_mc1r_reg_t hri_sdhc_read_MC1R_reg(const void *const hw) +{ + return ((Sdhc *)hw)->MC1R.reg; +} + +static inline void hri_sdhc_set_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ACR.reg |= SDHC_ACR_BMAX(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_acr_reg_t hri_sdhc_get_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ACR.reg; + tmp = (tmp & SDHC_ACR_BMAX(mask)) >> SDHC_ACR_BMAX_Pos; + return tmp; +} + +static inline void hri_sdhc_write_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t data) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->ACR.reg; + tmp &= ~SDHC_ACR_BMAX_Msk; + tmp |= SDHC_ACR_BMAX(data); + ((Sdhc *)hw)->ACR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ACR.reg &= ~SDHC_ACR_BMAX(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_ACR_BMAX_bf(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ACR.reg ^= SDHC_ACR_BMAX(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_acr_reg_t hri_sdhc_read_ACR_BMAX_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ACR.reg; + tmp = (tmp & SDHC_ACR_BMAX_Msk) >> SDHC_ACR_BMAX_Pos; + return tmp; +} + +static inline void hri_sdhc_set_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ACR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_acr_reg_t hri_sdhc_get_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->ACR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ACR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ACR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_ACR_reg(const void *const hw, hri_sdhc_acr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->ACR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_acr_reg_t hri_sdhc_read_ACR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->ACR.reg; +} + +static inline void hri_sdhc_set_CC2R_FSDCLKD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CC2R.reg |= SDHC_CC2R_FSDCLKD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CC2R_FSDCLKD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CC2R.reg; + tmp = (tmp & SDHC_CC2R_FSDCLKD) >> SDHC_CC2R_FSDCLKD_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CC2R_FSDCLKD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CC2R.reg; + tmp &= ~SDHC_CC2R_FSDCLKD; + tmp |= value << SDHC_CC2R_FSDCLKD_Pos; + ((Sdhc *)hw)->CC2R.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CC2R_FSDCLKD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CC2R.reg &= ~SDHC_CC2R_FSDCLKD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CC2R_FSDCLKD_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CC2R.reg ^= SDHC_CC2R_FSDCLKD; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CC2R.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cc2r_reg_t hri_sdhc_get_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CC2R.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CC2R.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CC2R.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CC2R_reg(const void *const hw, hri_sdhc_cc2r_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CC2R.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cc2r_reg_t hri_sdhc_read_CC2R_reg(const void *const hw) +{ + return ((Sdhc *)hw)->CC2R.reg; +} + +static inline void hri_sdhc_set_CACR_CAPWREN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg |= SDHC_CACR_CAPWREN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_CACR_CAPWREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CACR.reg; + tmp = (tmp & SDHC_CACR_CAPWREN) >> SDHC_CACR_CAPWREN_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_CACR_CAPWREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CACR.reg; + tmp &= ~SDHC_CACR_CAPWREN; + tmp |= value << SDHC_CACR_CAPWREN_Pos; + ((Sdhc *)hw)->CACR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CACR_CAPWREN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg &= ~SDHC_CACR_CAPWREN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CACR_CAPWREN_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg ^= SDHC_CACR_CAPWREN; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg |= SDHC_CACR_KEY(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cacr_reg_t hri_sdhc_get_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CACR.reg; + tmp = (tmp & SDHC_CACR_KEY(mask)) >> SDHC_CACR_KEY_Pos; + return tmp; +} + +static inline void hri_sdhc_write_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t data) +{ + uint32_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->CACR.reg; + tmp &= ~SDHC_CACR_KEY_Msk; + tmp |= SDHC_CACR_KEY(data); + ((Sdhc *)hw)->CACR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg &= ~SDHC_CACR_KEY(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CACR_KEY_bf(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg ^= SDHC_CACR_KEY(mask); + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cacr_reg_t hri_sdhc_read_CACR_KEY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CACR.reg; + tmp = (tmp & SDHC_CACR_KEY_Msk) >> SDHC_CACR_KEY_Pos; + return tmp; +} + +static inline void hri_sdhc_set_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cacr_reg_t hri_sdhc_get_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sdhc *)hw)->CACR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_CACR_reg(const void *const hw, hri_sdhc_cacr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->CACR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_cacr_reg_t hri_sdhc_read_CACR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->CACR.reg; +} + +static inline void hri_sdhc_set_DBGR_NIDBG_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->DBGR.reg |= SDHC_DBGR_NIDBG; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sdhc_get_DBGR_NIDBG_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->DBGR.reg; + tmp = (tmp & SDHC_DBGR_NIDBG) >> SDHC_DBGR_NIDBG_Pos; + return (bool)tmp; +} + +static inline void hri_sdhc_write_DBGR_NIDBG_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SDHC_CRITICAL_SECTION_ENTER(); + tmp = ((Sdhc *)hw)->DBGR.reg; + tmp &= ~SDHC_DBGR_NIDBG; + tmp |= value << SDHC_DBGR_NIDBG_Pos; + ((Sdhc *)hw)->DBGR.reg = tmp; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_DBGR_NIDBG_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->DBGR.reg &= ~SDHC_DBGR_NIDBG; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_DBGR_NIDBG_bit(const void *const hw) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->DBGR.reg ^= SDHC_DBGR_NIDBG; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_set_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->DBGR.reg |= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_dbgr_reg_t hri_sdhc_get_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sdhc *)hw)->DBGR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sdhc_write_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->DBGR.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_clear_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->DBGR.reg &= ~mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_toggle_DBGR_reg(const void *const hw, hri_sdhc_dbgr_reg_t mask) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->DBGR.reg ^= mask; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sdhc_dbgr_reg_t hri_sdhc_read_DBGR_reg(const void *const hw) +{ + return ((Sdhc *)hw)->DBGR.reg; +} + +static inline void hri_sdhc_write_FERACES_reg(const void *const hw, hri_sdhc_feraces_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->FERACES.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_write_FEREIS_reg(const void *const hw, hri_sdhc_fereis_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->FEREIS.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sdhc_write_MC2R_reg(const void *const hw, hri_sdhc_mc2r_reg_t data) +{ + SDHC_CRITICAL_SECTION_ENTER(); + ((Sdhc *)hw)->MC2R.reg = data; + SDHC_CRITICAL_SECTION_LEAVE(); +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_sdhc_set_SSAR_CMD23_reg(a, b) hri_sdhc_set_SSAR_reg(a, b) +#define hri_sdhc_get_SSAR_CMD23_reg(a, b) hri_sdhc_get_SSAR_reg(a, b) +#define hri_sdhc_write_SSAR_CMD23_reg(a, b) hri_sdhc_write_SSAR_reg(a, b) +#define hri_sdhc_clear_SSAR_CMD23_reg(a, b) hri_sdhc_clear_SSAR_reg(a, b) +#define hri_sdhc_toggle_SSAR_CMD23_reg(a, b) hri_sdhc_toggle_SSAR_reg(a, b) +#define hri_sdhc_read_SSAR_CMD23_reg(a) hri_sdhc_read_SSAR_reg(a) +#define hri_sdhc_set_HC1R_EMMC_DW_bit(a) hri_sdhc_set_HC1R_DW_bit(a) +#define hri_sdhc_get_HC1R_EMMC_DW_bit(a) hri_sdhc_get_HC1R_DW_bit(a) +#define hri_sdhc_write_HC1R_EMMC_DW_bit(a, b) hri_sdhc_write_HC1R_DW_bit(a, b) +#define hri_sdhc_clear_HC1R_EMMC_DW_bit(a) hri_sdhc_clear_HC1R_DW_bit(a) +#define hri_sdhc_toggle_HC1R_EMMC_DW_bit(a) hri_sdhc_toggle_HC1R_DW_bit(a) +#define hri_sdhc_set_HC1R_EMMC_HSEN_bit(a) hri_sdhc_set_HC1R_HSEN_bit(a) +#define hri_sdhc_get_HC1R_EMMC_HSEN_bit(a) hri_sdhc_get_HC1R_HSEN_bit(a) +#define hri_sdhc_write_HC1R_EMMC_HSEN_bit(a, b) hri_sdhc_write_HC1R_HSEN_bit(a, b) +#define hri_sdhc_clear_HC1R_EMMC_HSEN_bit(a) hri_sdhc_clear_HC1R_HSEN_bit(a) +#define hri_sdhc_toggle_HC1R_EMMC_HSEN_bit(a) hri_sdhc_toggle_HC1R_HSEN_bit(a) +#define hri_sdhc_set_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_set_HC1R_DMASEL_bf(a, b) +#define hri_sdhc_get_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_get_HC1R_DMASEL_bf(a, b) +#define hri_sdhc_write_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_write_HC1R_DMASEL_bf(a, b) +#define hri_sdhc_clear_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_clear_HC1R_DMASEL_bf(a, b) +#define hri_sdhc_toggle_HC1R_EMMC_DMASEL_bf(a, b) hri_sdhc_toggle_HC1R_DMASEL_bf(a, b) +#define hri_sdhc_read_HC1R_EMMC_DMASEL_bf(a) hri_sdhc_read_HC1R_DMASEL_bf(a) +#define hri_sdhc_set_HC1R_EMMC_reg(a, b) hri_sdhc_set_HC1R_reg(a, b) +#define hri_sdhc_get_HC1R_EMMC_reg(a, b) hri_sdhc_get_HC1R_reg(a, b) +#define hri_sdhc_write_HC1R_EMMC_reg(a, b) hri_sdhc_write_HC1R_reg(a, b) +#define hri_sdhc_clear_HC1R_EMMC_reg(a, b) hri_sdhc_clear_HC1R_reg(a, b) +#define hri_sdhc_toggle_HC1R_EMMC_reg(a, b) hri_sdhc_toggle_HC1R_reg(a, b) +#define hri_sdhc_read_HC1R_EMMC_reg(a) hri_sdhc_read_HC1R_reg(a) +#define hri_sdhc_set_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_set_BGCR_STPBGR_bit(a) +#define hri_sdhc_get_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_get_BGCR_STPBGR_bit(a) +#define hri_sdhc_write_BGCR_EMMC_STPBGR_bit(a, b) hri_sdhc_write_BGCR_STPBGR_bit(a, b) +#define hri_sdhc_clear_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_clear_BGCR_STPBGR_bit(a) +#define hri_sdhc_toggle_BGCR_EMMC_STPBGR_bit(a) hri_sdhc_toggle_BGCR_STPBGR_bit(a) +#define hri_sdhc_set_BGCR_EMMC_CONTR_bit(a) hri_sdhc_set_BGCR_CONTR_bit(a) +#define hri_sdhc_get_BGCR_EMMC_CONTR_bit(a) hri_sdhc_get_BGCR_CONTR_bit(a) +#define hri_sdhc_write_BGCR_EMMC_CONTR_bit(a, b) hri_sdhc_write_BGCR_CONTR_bit(a, b) +#define hri_sdhc_clear_BGCR_EMMC_CONTR_bit(a) hri_sdhc_clear_BGCR_CONTR_bit(a) +#define hri_sdhc_toggle_BGCR_EMMC_CONTR_bit(a) hri_sdhc_toggle_BGCR_CONTR_bit(a) +#define hri_sdhc_set_BGCR_EMMC_reg(a, b) hri_sdhc_set_BGCR_reg(a, b) +#define hri_sdhc_get_BGCR_EMMC_reg(a, b) hri_sdhc_get_BGCR_reg(a, b) +#define hri_sdhc_write_BGCR_EMMC_reg(a, b) hri_sdhc_write_BGCR_reg(a, b) +#define hri_sdhc_clear_BGCR_EMMC_reg(a, b) hri_sdhc_clear_BGCR_reg(a, b) +#define hri_sdhc_toggle_BGCR_EMMC_reg(a, b) hri_sdhc_toggle_BGCR_reg(a, b) +#define hri_sdhc_read_BGCR_EMMC_reg(a) hri_sdhc_read_BGCR_reg(a) +#define hri_sdhc_set_NISTR_EMMC_CMDC_bit(a) hri_sdhc_set_NISTR_CMDC_bit(a) +#define hri_sdhc_get_NISTR_EMMC_CMDC_bit(a) hri_sdhc_get_NISTR_CMDC_bit(a) +#define hri_sdhc_write_NISTR_EMMC_CMDC_bit(a, b) hri_sdhc_write_NISTR_CMDC_bit(a, b) +#define hri_sdhc_clear_NISTR_EMMC_CMDC_bit(a) hri_sdhc_clear_NISTR_CMDC_bit(a) +#define hri_sdhc_toggle_NISTR_EMMC_CMDC_bit(a) hri_sdhc_toggle_NISTR_CMDC_bit(a) +#define hri_sdhc_set_NISTR_EMMC_TRFC_bit(a) hri_sdhc_set_NISTR_TRFC_bit(a) +#define hri_sdhc_get_NISTR_EMMC_TRFC_bit(a) hri_sdhc_get_NISTR_TRFC_bit(a) +#define hri_sdhc_write_NISTR_EMMC_TRFC_bit(a, b) hri_sdhc_write_NISTR_TRFC_bit(a, b) +#define hri_sdhc_clear_NISTR_EMMC_TRFC_bit(a) hri_sdhc_clear_NISTR_TRFC_bit(a) +#define hri_sdhc_toggle_NISTR_EMMC_TRFC_bit(a) hri_sdhc_toggle_NISTR_TRFC_bit(a) +#define hri_sdhc_set_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_set_NISTR_BLKGE_bit(a) +#define hri_sdhc_get_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_get_NISTR_BLKGE_bit(a) +#define hri_sdhc_write_NISTR_EMMC_BLKGE_bit(a, b) hri_sdhc_write_NISTR_BLKGE_bit(a, b) +#define hri_sdhc_clear_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_clear_NISTR_BLKGE_bit(a) +#define hri_sdhc_toggle_NISTR_EMMC_BLKGE_bit(a) hri_sdhc_toggle_NISTR_BLKGE_bit(a) +#define hri_sdhc_set_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_set_NISTR_DMAINT_bit(a) +#define hri_sdhc_get_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_get_NISTR_DMAINT_bit(a) +#define hri_sdhc_write_NISTR_EMMC_DMAINT_bit(a, b) hri_sdhc_write_NISTR_DMAINT_bit(a, b) +#define hri_sdhc_clear_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_clear_NISTR_DMAINT_bit(a) +#define hri_sdhc_toggle_NISTR_EMMC_DMAINT_bit(a) hri_sdhc_toggle_NISTR_DMAINT_bit(a) +#define hri_sdhc_set_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_set_NISTR_BWRRDY_bit(a) +#define hri_sdhc_get_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_get_NISTR_BWRRDY_bit(a) +#define hri_sdhc_write_NISTR_EMMC_BWRRDY_bit(a, b) hri_sdhc_write_NISTR_BWRRDY_bit(a, b) +#define hri_sdhc_clear_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_clear_NISTR_BWRRDY_bit(a) +#define hri_sdhc_toggle_NISTR_EMMC_BWRRDY_bit(a) hri_sdhc_toggle_NISTR_BWRRDY_bit(a) +#define hri_sdhc_set_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_set_NISTR_BRDRDY_bit(a) +#define hri_sdhc_get_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_get_NISTR_BRDRDY_bit(a) +#define hri_sdhc_write_NISTR_EMMC_BRDRDY_bit(a, b) hri_sdhc_write_NISTR_BRDRDY_bit(a, b) +#define hri_sdhc_clear_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_clear_NISTR_BRDRDY_bit(a) +#define hri_sdhc_toggle_NISTR_EMMC_BRDRDY_bit(a) hri_sdhc_toggle_NISTR_BRDRDY_bit(a) +#define hri_sdhc_set_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_set_NISTR_ERRINT_bit(a) +#define hri_sdhc_get_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_get_NISTR_ERRINT_bit(a) +#define hri_sdhc_write_NISTR_EMMC_ERRINT_bit(a, b) hri_sdhc_write_NISTR_ERRINT_bit(a, b) +#define hri_sdhc_clear_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_clear_NISTR_ERRINT_bit(a) +#define hri_sdhc_toggle_NISTR_EMMC_ERRINT_bit(a) hri_sdhc_toggle_NISTR_ERRINT_bit(a) +#define hri_sdhc_set_NISTR_EMMC_reg(a, b) hri_sdhc_set_NISTR_reg(a, b) +#define hri_sdhc_get_NISTR_EMMC_reg(a, b) hri_sdhc_get_NISTR_reg(a, b) +#define hri_sdhc_write_NISTR_EMMC_reg(a, b) hri_sdhc_write_NISTR_reg(a, b) +#define hri_sdhc_clear_NISTR_EMMC_reg(a, b) hri_sdhc_clear_NISTR_reg(a, b) +#define hri_sdhc_toggle_NISTR_EMMC_reg(a, b) hri_sdhc_toggle_NISTR_reg(a, b) +#define hri_sdhc_read_NISTR_EMMC_reg(a) hri_sdhc_read_NISTR_reg(a) +#define hri_sdhc_set_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_set_EISTR_CMDTEO_bit(a) +#define hri_sdhc_get_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_get_EISTR_CMDTEO_bit(a) +#define hri_sdhc_write_EISTR_EMMC_CMDTEO_bit(a, b) hri_sdhc_write_EISTR_CMDTEO_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_clear_EISTR_CMDTEO_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_CMDTEO_bit(a) hri_sdhc_toggle_EISTR_CMDTEO_bit(a) +#define hri_sdhc_set_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_set_EISTR_CMDCRC_bit(a) +#define hri_sdhc_get_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_get_EISTR_CMDCRC_bit(a) +#define hri_sdhc_write_EISTR_EMMC_CMDCRC_bit(a, b) hri_sdhc_write_EISTR_CMDCRC_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_clear_EISTR_CMDCRC_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_CMDCRC_bit(a) hri_sdhc_toggle_EISTR_CMDCRC_bit(a) +#define hri_sdhc_set_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_set_EISTR_CMDEND_bit(a) +#define hri_sdhc_get_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_get_EISTR_CMDEND_bit(a) +#define hri_sdhc_write_EISTR_EMMC_CMDEND_bit(a, b) hri_sdhc_write_EISTR_CMDEND_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_clear_EISTR_CMDEND_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_CMDEND_bit(a) hri_sdhc_toggle_EISTR_CMDEND_bit(a) +#define hri_sdhc_set_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_set_EISTR_CMDIDX_bit(a) +#define hri_sdhc_get_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_get_EISTR_CMDIDX_bit(a) +#define hri_sdhc_write_EISTR_EMMC_CMDIDX_bit(a, b) hri_sdhc_write_EISTR_CMDIDX_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_clear_EISTR_CMDIDX_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_CMDIDX_bit(a) hri_sdhc_toggle_EISTR_CMDIDX_bit(a) +#define hri_sdhc_set_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_set_EISTR_DATTEO_bit(a) +#define hri_sdhc_get_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_get_EISTR_DATTEO_bit(a) +#define hri_sdhc_write_EISTR_EMMC_DATTEO_bit(a, b) hri_sdhc_write_EISTR_DATTEO_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_clear_EISTR_DATTEO_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_DATTEO_bit(a) hri_sdhc_toggle_EISTR_DATTEO_bit(a) +#define hri_sdhc_set_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_set_EISTR_DATCRC_bit(a) +#define hri_sdhc_get_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_get_EISTR_DATCRC_bit(a) +#define hri_sdhc_write_EISTR_EMMC_DATCRC_bit(a, b) hri_sdhc_write_EISTR_DATCRC_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_clear_EISTR_DATCRC_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_DATCRC_bit(a) hri_sdhc_toggle_EISTR_DATCRC_bit(a) +#define hri_sdhc_set_EISTR_EMMC_DATEND_bit(a) hri_sdhc_set_EISTR_DATEND_bit(a) +#define hri_sdhc_get_EISTR_EMMC_DATEND_bit(a) hri_sdhc_get_EISTR_DATEND_bit(a) +#define hri_sdhc_write_EISTR_EMMC_DATEND_bit(a, b) hri_sdhc_write_EISTR_DATEND_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_DATEND_bit(a) hri_sdhc_clear_EISTR_DATEND_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_DATEND_bit(a) hri_sdhc_toggle_EISTR_DATEND_bit(a) +#define hri_sdhc_set_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_set_EISTR_CURLIM_bit(a) +#define hri_sdhc_get_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_get_EISTR_CURLIM_bit(a) +#define hri_sdhc_write_EISTR_EMMC_CURLIM_bit(a, b) hri_sdhc_write_EISTR_CURLIM_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_clear_EISTR_CURLIM_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_CURLIM_bit(a) hri_sdhc_toggle_EISTR_CURLIM_bit(a) +#define hri_sdhc_set_EISTR_EMMC_ACMD_bit(a) hri_sdhc_set_EISTR_ACMD_bit(a) +#define hri_sdhc_get_EISTR_EMMC_ACMD_bit(a) hri_sdhc_get_EISTR_ACMD_bit(a) +#define hri_sdhc_write_EISTR_EMMC_ACMD_bit(a, b) hri_sdhc_write_EISTR_ACMD_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_ACMD_bit(a) hri_sdhc_clear_EISTR_ACMD_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_ACMD_bit(a) hri_sdhc_toggle_EISTR_ACMD_bit(a) +#define hri_sdhc_set_EISTR_EMMC_ADMA_bit(a) hri_sdhc_set_EISTR_ADMA_bit(a) +#define hri_sdhc_get_EISTR_EMMC_ADMA_bit(a) hri_sdhc_get_EISTR_ADMA_bit(a) +#define hri_sdhc_write_EISTR_EMMC_ADMA_bit(a, b) hri_sdhc_write_EISTR_ADMA_bit(a, b) +#define hri_sdhc_clear_EISTR_EMMC_ADMA_bit(a) hri_sdhc_clear_EISTR_ADMA_bit(a) +#define hri_sdhc_toggle_EISTR_EMMC_ADMA_bit(a) hri_sdhc_toggle_EISTR_ADMA_bit(a) +#define hri_sdhc_set_EISTR_EMMC_reg(a, b) hri_sdhc_set_EISTR_reg(a, b) +#define hri_sdhc_get_EISTR_EMMC_reg(a, b) hri_sdhc_get_EISTR_reg(a, b) +#define hri_sdhc_write_EISTR_EMMC_reg(a, b) hri_sdhc_write_EISTR_reg(a, b) +#define hri_sdhc_clear_EISTR_EMMC_reg(a, b) hri_sdhc_clear_EISTR_reg(a, b) +#define hri_sdhc_toggle_EISTR_EMMC_reg(a, b) hri_sdhc_toggle_EISTR_reg(a, b) +#define hri_sdhc_read_EISTR_EMMC_reg(a) hri_sdhc_read_EISTR_reg(a) +#define hri_sdhc_set_NISTER_EMMC_CMDC_bit(a) hri_sdhc_set_NISTER_CMDC_bit(a) +#define hri_sdhc_get_NISTER_EMMC_CMDC_bit(a) hri_sdhc_get_NISTER_CMDC_bit(a) +#define hri_sdhc_write_NISTER_EMMC_CMDC_bit(a, b) hri_sdhc_write_NISTER_CMDC_bit(a, b) +#define hri_sdhc_clear_NISTER_EMMC_CMDC_bit(a) hri_sdhc_clear_NISTER_CMDC_bit(a) +#define hri_sdhc_toggle_NISTER_EMMC_CMDC_bit(a) hri_sdhc_toggle_NISTER_CMDC_bit(a) +#define hri_sdhc_set_NISTER_EMMC_TRFC_bit(a) hri_sdhc_set_NISTER_TRFC_bit(a) +#define hri_sdhc_get_NISTER_EMMC_TRFC_bit(a) hri_sdhc_get_NISTER_TRFC_bit(a) +#define hri_sdhc_write_NISTER_EMMC_TRFC_bit(a, b) hri_sdhc_write_NISTER_TRFC_bit(a, b) +#define hri_sdhc_clear_NISTER_EMMC_TRFC_bit(a) hri_sdhc_clear_NISTER_TRFC_bit(a) +#define hri_sdhc_toggle_NISTER_EMMC_TRFC_bit(a) hri_sdhc_toggle_NISTER_TRFC_bit(a) +#define hri_sdhc_set_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_set_NISTER_BLKGE_bit(a) +#define hri_sdhc_get_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_get_NISTER_BLKGE_bit(a) +#define hri_sdhc_write_NISTER_EMMC_BLKGE_bit(a, b) hri_sdhc_write_NISTER_BLKGE_bit(a, b) +#define hri_sdhc_clear_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_clear_NISTER_BLKGE_bit(a) +#define hri_sdhc_toggle_NISTER_EMMC_BLKGE_bit(a) hri_sdhc_toggle_NISTER_BLKGE_bit(a) +#define hri_sdhc_set_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_set_NISTER_DMAINT_bit(a) +#define hri_sdhc_get_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_get_NISTER_DMAINT_bit(a) +#define hri_sdhc_write_NISTER_EMMC_DMAINT_bit(a, b) hri_sdhc_write_NISTER_DMAINT_bit(a, b) +#define hri_sdhc_clear_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_clear_NISTER_DMAINT_bit(a) +#define hri_sdhc_toggle_NISTER_EMMC_DMAINT_bit(a) hri_sdhc_toggle_NISTER_DMAINT_bit(a) +#define hri_sdhc_set_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_set_NISTER_BWRRDY_bit(a) +#define hri_sdhc_get_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_get_NISTER_BWRRDY_bit(a) +#define hri_sdhc_write_NISTER_EMMC_BWRRDY_bit(a, b) hri_sdhc_write_NISTER_BWRRDY_bit(a, b) +#define hri_sdhc_clear_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_clear_NISTER_BWRRDY_bit(a) +#define hri_sdhc_toggle_NISTER_EMMC_BWRRDY_bit(a) hri_sdhc_toggle_NISTER_BWRRDY_bit(a) +#define hri_sdhc_set_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_set_NISTER_BRDRDY_bit(a) +#define hri_sdhc_get_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_get_NISTER_BRDRDY_bit(a) +#define hri_sdhc_write_NISTER_EMMC_BRDRDY_bit(a, b) hri_sdhc_write_NISTER_BRDRDY_bit(a, b) +#define hri_sdhc_clear_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_clear_NISTER_BRDRDY_bit(a) +#define hri_sdhc_toggle_NISTER_EMMC_BRDRDY_bit(a) hri_sdhc_toggle_NISTER_BRDRDY_bit(a) +#define hri_sdhc_set_NISTER_EMMC_reg(a, b) hri_sdhc_set_NISTER_reg(a, b) +#define hri_sdhc_get_NISTER_EMMC_reg(a, b) hri_sdhc_get_NISTER_reg(a, b) +#define hri_sdhc_write_NISTER_EMMC_reg(a, b) hri_sdhc_write_NISTER_reg(a, b) +#define hri_sdhc_clear_NISTER_EMMC_reg(a, b) hri_sdhc_clear_NISTER_reg(a, b) +#define hri_sdhc_toggle_NISTER_EMMC_reg(a, b) hri_sdhc_toggle_NISTER_reg(a, b) +#define hri_sdhc_read_NISTER_EMMC_reg(a) hri_sdhc_read_NISTER_reg(a) +#define hri_sdhc_set_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_set_EISTER_CMDTEO_bit(a) +#define hri_sdhc_get_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_get_EISTER_CMDTEO_bit(a) +#define hri_sdhc_write_EISTER_EMMC_CMDTEO_bit(a, b) hri_sdhc_write_EISTER_CMDTEO_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_clear_EISTER_CMDTEO_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_CMDTEO_bit(a) hri_sdhc_toggle_EISTER_CMDTEO_bit(a) +#define hri_sdhc_set_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_set_EISTER_CMDCRC_bit(a) +#define hri_sdhc_get_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_get_EISTER_CMDCRC_bit(a) +#define hri_sdhc_write_EISTER_EMMC_CMDCRC_bit(a, b) hri_sdhc_write_EISTER_CMDCRC_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_clear_EISTER_CMDCRC_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_CMDCRC_bit(a) hri_sdhc_toggle_EISTER_CMDCRC_bit(a) +#define hri_sdhc_set_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_set_EISTER_CMDEND_bit(a) +#define hri_sdhc_get_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_get_EISTER_CMDEND_bit(a) +#define hri_sdhc_write_EISTER_EMMC_CMDEND_bit(a, b) hri_sdhc_write_EISTER_CMDEND_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_clear_EISTER_CMDEND_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_CMDEND_bit(a) hri_sdhc_toggle_EISTER_CMDEND_bit(a) +#define hri_sdhc_set_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_set_EISTER_CMDIDX_bit(a) +#define hri_sdhc_get_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_get_EISTER_CMDIDX_bit(a) +#define hri_sdhc_write_EISTER_EMMC_CMDIDX_bit(a, b) hri_sdhc_write_EISTER_CMDIDX_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_clear_EISTER_CMDIDX_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_CMDIDX_bit(a) hri_sdhc_toggle_EISTER_CMDIDX_bit(a) +#define hri_sdhc_set_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_set_EISTER_DATTEO_bit(a) +#define hri_sdhc_get_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_get_EISTER_DATTEO_bit(a) +#define hri_sdhc_write_EISTER_EMMC_DATTEO_bit(a, b) hri_sdhc_write_EISTER_DATTEO_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_clear_EISTER_DATTEO_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_DATTEO_bit(a) hri_sdhc_toggle_EISTER_DATTEO_bit(a) +#define hri_sdhc_set_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_set_EISTER_DATCRC_bit(a) +#define hri_sdhc_get_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_get_EISTER_DATCRC_bit(a) +#define hri_sdhc_write_EISTER_EMMC_DATCRC_bit(a, b) hri_sdhc_write_EISTER_DATCRC_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_clear_EISTER_DATCRC_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_DATCRC_bit(a) hri_sdhc_toggle_EISTER_DATCRC_bit(a) +#define hri_sdhc_set_EISTER_EMMC_DATEND_bit(a) hri_sdhc_set_EISTER_DATEND_bit(a) +#define hri_sdhc_get_EISTER_EMMC_DATEND_bit(a) hri_sdhc_get_EISTER_DATEND_bit(a) +#define hri_sdhc_write_EISTER_EMMC_DATEND_bit(a, b) hri_sdhc_write_EISTER_DATEND_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_DATEND_bit(a) hri_sdhc_clear_EISTER_DATEND_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_DATEND_bit(a) hri_sdhc_toggle_EISTER_DATEND_bit(a) +#define hri_sdhc_set_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_set_EISTER_CURLIM_bit(a) +#define hri_sdhc_get_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_get_EISTER_CURLIM_bit(a) +#define hri_sdhc_write_EISTER_EMMC_CURLIM_bit(a, b) hri_sdhc_write_EISTER_CURLIM_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_clear_EISTER_CURLIM_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_CURLIM_bit(a) hri_sdhc_toggle_EISTER_CURLIM_bit(a) +#define hri_sdhc_set_EISTER_EMMC_ACMD_bit(a) hri_sdhc_set_EISTER_ACMD_bit(a) +#define hri_sdhc_get_EISTER_EMMC_ACMD_bit(a) hri_sdhc_get_EISTER_ACMD_bit(a) +#define hri_sdhc_write_EISTER_EMMC_ACMD_bit(a, b) hri_sdhc_write_EISTER_ACMD_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_ACMD_bit(a) hri_sdhc_clear_EISTER_ACMD_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_ACMD_bit(a) hri_sdhc_toggle_EISTER_ACMD_bit(a) +#define hri_sdhc_set_EISTER_EMMC_ADMA_bit(a) hri_sdhc_set_EISTER_ADMA_bit(a) +#define hri_sdhc_get_EISTER_EMMC_ADMA_bit(a) hri_sdhc_get_EISTER_ADMA_bit(a) +#define hri_sdhc_write_EISTER_EMMC_ADMA_bit(a, b) hri_sdhc_write_EISTER_ADMA_bit(a, b) +#define hri_sdhc_clear_EISTER_EMMC_ADMA_bit(a) hri_sdhc_clear_EISTER_ADMA_bit(a) +#define hri_sdhc_toggle_EISTER_EMMC_ADMA_bit(a) hri_sdhc_toggle_EISTER_ADMA_bit(a) +#define hri_sdhc_set_EISTER_EMMC_reg(a, b) hri_sdhc_set_EISTER_reg(a, b) +#define hri_sdhc_get_EISTER_EMMC_reg(a, b) hri_sdhc_get_EISTER_reg(a, b) +#define hri_sdhc_write_EISTER_EMMC_reg(a, b) hri_sdhc_write_EISTER_reg(a, b) +#define hri_sdhc_clear_EISTER_EMMC_reg(a, b) hri_sdhc_clear_EISTER_reg(a, b) +#define hri_sdhc_toggle_EISTER_EMMC_reg(a, b) hri_sdhc_toggle_EISTER_reg(a, b) +#define hri_sdhc_read_EISTER_EMMC_reg(a) hri_sdhc_read_EISTER_reg(a) +#define hri_sdhc_set_NISIER_EMMC_CMDC_bit(a) hri_sdhc_set_NISIER_CMDC_bit(a) +#define hri_sdhc_get_NISIER_EMMC_CMDC_bit(a) hri_sdhc_get_NISIER_CMDC_bit(a) +#define hri_sdhc_write_NISIER_EMMC_CMDC_bit(a, b) hri_sdhc_write_NISIER_CMDC_bit(a, b) +#define hri_sdhc_clear_NISIER_EMMC_CMDC_bit(a) hri_sdhc_clear_NISIER_CMDC_bit(a) +#define hri_sdhc_toggle_NISIER_EMMC_CMDC_bit(a) hri_sdhc_toggle_NISIER_CMDC_bit(a) +#define hri_sdhc_set_NISIER_EMMC_TRFC_bit(a) hri_sdhc_set_NISIER_TRFC_bit(a) +#define hri_sdhc_get_NISIER_EMMC_TRFC_bit(a) hri_sdhc_get_NISIER_TRFC_bit(a) +#define hri_sdhc_write_NISIER_EMMC_TRFC_bit(a, b) hri_sdhc_write_NISIER_TRFC_bit(a, b) +#define hri_sdhc_clear_NISIER_EMMC_TRFC_bit(a) hri_sdhc_clear_NISIER_TRFC_bit(a) +#define hri_sdhc_toggle_NISIER_EMMC_TRFC_bit(a) hri_sdhc_toggle_NISIER_TRFC_bit(a) +#define hri_sdhc_set_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_set_NISIER_BLKGE_bit(a) +#define hri_sdhc_get_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_get_NISIER_BLKGE_bit(a) +#define hri_sdhc_write_NISIER_EMMC_BLKGE_bit(a, b) hri_sdhc_write_NISIER_BLKGE_bit(a, b) +#define hri_sdhc_clear_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_clear_NISIER_BLKGE_bit(a) +#define hri_sdhc_toggle_NISIER_EMMC_BLKGE_bit(a) hri_sdhc_toggle_NISIER_BLKGE_bit(a) +#define hri_sdhc_set_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_set_NISIER_DMAINT_bit(a) +#define hri_sdhc_get_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_get_NISIER_DMAINT_bit(a) +#define hri_sdhc_write_NISIER_EMMC_DMAINT_bit(a, b) hri_sdhc_write_NISIER_DMAINT_bit(a, b) +#define hri_sdhc_clear_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_clear_NISIER_DMAINT_bit(a) +#define hri_sdhc_toggle_NISIER_EMMC_DMAINT_bit(a) hri_sdhc_toggle_NISIER_DMAINT_bit(a) +#define hri_sdhc_set_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_set_NISIER_BWRRDY_bit(a) +#define hri_sdhc_get_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_get_NISIER_BWRRDY_bit(a) +#define hri_sdhc_write_NISIER_EMMC_BWRRDY_bit(a, b) hri_sdhc_write_NISIER_BWRRDY_bit(a, b) +#define hri_sdhc_clear_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_clear_NISIER_BWRRDY_bit(a) +#define hri_sdhc_toggle_NISIER_EMMC_BWRRDY_bit(a) hri_sdhc_toggle_NISIER_BWRRDY_bit(a) +#define hri_sdhc_set_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_set_NISIER_BRDRDY_bit(a) +#define hri_sdhc_get_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_get_NISIER_BRDRDY_bit(a) +#define hri_sdhc_write_NISIER_EMMC_BRDRDY_bit(a, b) hri_sdhc_write_NISIER_BRDRDY_bit(a, b) +#define hri_sdhc_clear_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_clear_NISIER_BRDRDY_bit(a) +#define hri_sdhc_toggle_NISIER_EMMC_BRDRDY_bit(a) hri_sdhc_toggle_NISIER_BRDRDY_bit(a) +#define hri_sdhc_set_NISIER_EMMC_reg(a, b) hri_sdhc_set_NISIER_reg(a, b) +#define hri_sdhc_get_NISIER_EMMC_reg(a, b) hri_sdhc_get_NISIER_reg(a, b) +#define hri_sdhc_write_NISIER_EMMC_reg(a, b) hri_sdhc_write_NISIER_reg(a, b) +#define hri_sdhc_clear_NISIER_EMMC_reg(a, b) hri_sdhc_clear_NISIER_reg(a, b) +#define hri_sdhc_toggle_NISIER_EMMC_reg(a, b) hri_sdhc_toggle_NISIER_reg(a, b) +#define hri_sdhc_read_NISIER_EMMC_reg(a) hri_sdhc_read_NISIER_reg(a) +#define hri_sdhc_set_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_set_EISIER_CMDTEO_bit(a) +#define hri_sdhc_get_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_get_EISIER_CMDTEO_bit(a) +#define hri_sdhc_write_EISIER_EMMC_CMDTEO_bit(a, b) hri_sdhc_write_EISIER_CMDTEO_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_clear_EISIER_CMDTEO_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_CMDTEO_bit(a) hri_sdhc_toggle_EISIER_CMDTEO_bit(a) +#define hri_sdhc_set_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_set_EISIER_CMDCRC_bit(a) +#define hri_sdhc_get_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_get_EISIER_CMDCRC_bit(a) +#define hri_sdhc_write_EISIER_EMMC_CMDCRC_bit(a, b) hri_sdhc_write_EISIER_CMDCRC_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_clear_EISIER_CMDCRC_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_CMDCRC_bit(a) hri_sdhc_toggle_EISIER_CMDCRC_bit(a) +#define hri_sdhc_set_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_set_EISIER_CMDEND_bit(a) +#define hri_sdhc_get_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_get_EISIER_CMDEND_bit(a) +#define hri_sdhc_write_EISIER_EMMC_CMDEND_bit(a, b) hri_sdhc_write_EISIER_CMDEND_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_clear_EISIER_CMDEND_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_CMDEND_bit(a) hri_sdhc_toggle_EISIER_CMDEND_bit(a) +#define hri_sdhc_set_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_set_EISIER_CMDIDX_bit(a) +#define hri_sdhc_get_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_get_EISIER_CMDIDX_bit(a) +#define hri_sdhc_write_EISIER_EMMC_CMDIDX_bit(a, b) hri_sdhc_write_EISIER_CMDIDX_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_clear_EISIER_CMDIDX_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_CMDIDX_bit(a) hri_sdhc_toggle_EISIER_CMDIDX_bit(a) +#define hri_sdhc_set_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_set_EISIER_DATTEO_bit(a) +#define hri_sdhc_get_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_get_EISIER_DATTEO_bit(a) +#define hri_sdhc_write_EISIER_EMMC_DATTEO_bit(a, b) hri_sdhc_write_EISIER_DATTEO_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_clear_EISIER_DATTEO_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_DATTEO_bit(a) hri_sdhc_toggle_EISIER_DATTEO_bit(a) +#define hri_sdhc_set_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_set_EISIER_DATCRC_bit(a) +#define hri_sdhc_get_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_get_EISIER_DATCRC_bit(a) +#define hri_sdhc_write_EISIER_EMMC_DATCRC_bit(a, b) hri_sdhc_write_EISIER_DATCRC_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_clear_EISIER_DATCRC_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_DATCRC_bit(a) hri_sdhc_toggle_EISIER_DATCRC_bit(a) +#define hri_sdhc_set_EISIER_EMMC_DATEND_bit(a) hri_sdhc_set_EISIER_DATEND_bit(a) +#define hri_sdhc_get_EISIER_EMMC_DATEND_bit(a) hri_sdhc_get_EISIER_DATEND_bit(a) +#define hri_sdhc_write_EISIER_EMMC_DATEND_bit(a, b) hri_sdhc_write_EISIER_DATEND_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_DATEND_bit(a) hri_sdhc_clear_EISIER_DATEND_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_DATEND_bit(a) hri_sdhc_toggle_EISIER_DATEND_bit(a) +#define hri_sdhc_set_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_set_EISIER_CURLIM_bit(a) +#define hri_sdhc_get_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_get_EISIER_CURLIM_bit(a) +#define hri_sdhc_write_EISIER_EMMC_CURLIM_bit(a, b) hri_sdhc_write_EISIER_CURLIM_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_clear_EISIER_CURLIM_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_CURLIM_bit(a) hri_sdhc_toggle_EISIER_CURLIM_bit(a) +#define hri_sdhc_set_EISIER_EMMC_ACMD_bit(a) hri_sdhc_set_EISIER_ACMD_bit(a) +#define hri_sdhc_get_EISIER_EMMC_ACMD_bit(a) hri_sdhc_get_EISIER_ACMD_bit(a) +#define hri_sdhc_write_EISIER_EMMC_ACMD_bit(a, b) hri_sdhc_write_EISIER_ACMD_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_ACMD_bit(a) hri_sdhc_clear_EISIER_ACMD_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_ACMD_bit(a) hri_sdhc_toggle_EISIER_ACMD_bit(a) +#define hri_sdhc_set_EISIER_EMMC_ADMA_bit(a) hri_sdhc_set_EISIER_ADMA_bit(a) +#define hri_sdhc_get_EISIER_EMMC_ADMA_bit(a) hri_sdhc_get_EISIER_ADMA_bit(a) +#define hri_sdhc_write_EISIER_EMMC_ADMA_bit(a, b) hri_sdhc_write_EISIER_ADMA_bit(a, b) +#define hri_sdhc_clear_EISIER_EMMC_ADMA_bit(a) hri_sdhc_clear_EISIER_ADMA_bit(a) +#define hri_sdhc_toggle_EISIER_EMMC_ADMA_bit(a) hri_sdhc_toggle_EISIER_ADMA_bit(a) +#define hri_sdhc_set_EISIER_EMMC_reg(a, b) hri_sdhc_set_EISIER_reg(a, b) +#define hri_sdhc_get_EISIER_EMMC_reg(a, b) hri_sdhc_get_EISIER_reg(a, b) +#define hri_sdhc_write_EISIER_EMMC_reg(a, b) hri_sdhc_write_EISIER_reg(a, b) +#define hri_sdhc_clear_EISIER_EMMC_reg(a, b) hri_sdhc_clear_EISIER_reg(a, b) +#define hri_sdhc_toggle_EISIER_EMMC_reg(a, b) hri_sdhc_toggle_EISIER_reg(a, b) +#define hri_sdhc_read_EISIER_EMMC_reg(a) hri_sdhc_read_EISIER_reg(a) +#define hri_sdhc_set_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_set_HC2R_EXTUN_bit(a) +#define hri_sdhc_get_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_get_HC2R_EXTUN_bit(a) +#define hri_sdhc_write_HC2R_EMMC_EXTUN_bit(a, b) hri_sdhc_write_HC2R_EXTUN_bit(a, b) +#define hri_sdhc_clear_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_clear_HC2R_EXTUN_bit(a) +#define hri_sdhc_toggle_HC2R_EMMC_EXTUN_bit(a) hri_sdhc_toggle_HC2R_EXTUN_bit(a) +#define hri_sdhc_set_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_set_HC2R_SLCKSEL_bit(a) +#define hri_sdhc_get_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_get_HC2R_SLCKSEL_bit(a) +#define hri_sdhc_write_HC2R_EMMC_SLCKSEL_bit(a, b) hri_sdhc_write_HC2R_SLCKSEL_bit(a, b) +#define hri_sdhc_clear_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_clear_HC2R_SLCKSEL_bit(a) +#define hri_sdhc_toggle_HC2R_EMMC_SLCKSEL_bit(a) hri_sdhc_toggle_HC2R_SLCKSEL_bit(a) +#define hri_sdhc_set_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_set_HC2R_PVALEN_bit(a) +#define hri_sdhc_get_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_get_HC2R_PVALEN_bit(a) +#define hri_sdhc_write_HC2R_EMMC_PVALEN_bit(a, b) hri_sdhc_write_HC2R_PVALEN_bit(a, b) +#define hri_sdhc_clear_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_clear_HC2R_PVALEN_bit(a) +#define hri_sdhc_toggle_HC2R_EMMC_PVALEN_bit(a) hri_sdhc_toggle_HC2R_PVALEN_bit(a) +#define hri_sdhc_set_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_set_HC2R_DRVSEL_bf(a, b) +#define hri_sdhc_get_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_get_HC2R_DRVSEL_bf(a, b) +#define hri_sdhc_write_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_write_HC2R_DRVSEL_bf(a, b) +#define hri_sdhc_clear_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_clear_HC2R_DRVSEL_bf(a, b) +#define hri_sdhc_toggle_HC2R_EMMC_DRVSEL_bf(a, b) hri_sdhc_toggle_HC2R_DRVSEL_bf(a, b) +#define hri_sdhc_read_HC2R_EMMC_DRVSEL_bf(a) hri_sdhc_read_HC2R_DRVSEL_bf(a) +#define hri_sdhc_set_HC2R_EMMC_reg(a, b) hri_sdhc_set_HC2R_reg(a, b) +#define hri_sdhc_get_HC2R_EMMC_reg(a, b) hri_sdhc_get_HC2R_reg(a, b) +#define hri_sdhc_write_HC2R_EMMC_reg(a, b) hri_sdhc_write_HC2R_reg(a, b) +#define hri_sdhc_clear_HC2R_EMMC_reg(a, b) hri_sdhc_clear_HC2R_reg(a, b) +#define hri_sdhc_toggle_HC2R_EMMC_reg(a, b) hri_sdhc_toggle_HC2R_reg(a, b) +#define hri_sdhc_read_HC2R_EMMC_reg(a) hri_sdhc_read_HC2R_reg(a) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SDHC_E54_H_INCLUDED */ +#endif /* _SAME54_SDHC_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_sercom_e54.h b/software/firmware/oracle_same54n19a/hri/hri_sercom_e54.h new file mode 100644 index 00000000..fed00ff4 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_sercom_e54.h @@ -0,0 +1,8892 @@ +/** + * \file + * + * \brief SAM SERCOM + * + * Copyright (c) 2016-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_SERCOM_COMPONENT_ +#ifndef _HRI_SERCOM_E54_H_INCLUDED_ +#define _HRI_SERCOM_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SERCOM_CRITICAL_SECTIONS) +#define SERCOM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SERCOM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SERCOM_CRITICAL_SECTION_ENTER() +#define SERCOM_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_sercomi2cm_status_reg_t; +typedef uint16_t hri_sercomi2cs_length_reg_t; +typedef uint16_t hri_sercomi2cs_status_reg_t; +typedef uint16_t hri_sercomspi_length_reg_t; +typedef uint16_t hri_sercomspi_status_reg_t; +typedef uint16_t hri_sercomusart_baud_reg_t; +typedef uint16_t hri_sercomusart_length_reg_t; +typedef uint16_t hri_sercomusart_status_reg_t; +typedef uint32_t hri_sercomi2cm_addr_reg_t; +typedef uint32_t hri_sercomi2cm_baud_reg_t; +typedef uint32_t hri_sercomi2cm_ctrla_reg_t; +typedef uint32_t hri_sercomi2cm_ctrlb_reg_t; +typedef uint32_t hri_sercomi2cm_ctrlc_reg_t; +typedef uint32_t hri_sercomi2cm_data_reg_t; +typedef uint32_t hri_sercomi2cm_syncbusy_reg_t; +typedef uint32_t hri_sercomi2cs_addr_reg_t; +typedef uint32_t hri_sercomi2cs_ctrla_reg_t; +typedef uint32_t hri_sercomi2cs_ctrlb_reg_t; +typedef uint32_t hri_sercomi2cs_ctrlc_reg_t; +typedef uint32_t hri_sercomi2cs_data_reg_t; +typedef uint32_t hri_sercomi2cs_syncbusy_reg_t; +typedef uint32_t hri_sercomspi_addr_reg_t; +typedef uint32_t hri_sercomspi_ctrla_reg_t; +typedef uint32_t hri_sercomspi_ctrlb_reg_t; +typedef uint32_t hri_sercomspi_ctrlc_reg_t; +typedef uint32_t hri_sercomspi_data_reg_t; +typedef uint32_t hri_sercomspi_syncbusy_reg_t; +typedef uint32_t hri_sercomusart_ctrla_reg_t; +typedef uint32_t hri_sercomusart_ctrlb_reg_t; +typedef uint32_t hri_sercomusart_ctrlc_reg_t; +typedef uint32_t hri_sercomusart_data_reg_t; +typedef uint32_t hri_sercomusart_syncbusy_reg_t; +typedef uint8_t hri_sercomi2cm_dbgctrl_reg_t; +typedef uint8_t hri_sercomi2cm_intenset_reg_t; +typedef uint8_t hri_sercomi2cm_intflag_reg_t; +typedef uint8_t hri_sercomi2cs_intenset_reg_t; +typedef uint8_t hri_sercomi2cs_intflag_reg_t; +typedef uint8_t hri_sercomspi_baud_reg_t; +typedef uint8_t hri_sercomspi_dbgctrl_reg_t; +typedef uint8_t hri_sercomspi_intenset_reg_t; +typedef uint8_t hri_sercomspi_intflag_reg_t; +typedef uint8_t hri_sercomusart_dbgctrl_reg_t; +typedef uint8_t hri_sercomusart_intenset_reg_t; +typedef uint8_t hri_sercomusart_intflag_reg_t; +typedef uint8_t hri_sercomusart_rxerrcnt_reg_t; +typedef uint8_t hri_sercomusart_rxpl_reg_t; + +static inline void hri_sercomi2cm_wait_for_sync(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomi2cm_is_syncing(const void *const hw, hri_sercomi2cm_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->I2CM.SYNCBUSY.reg & reg; +} + +static inline void hri_sercomi2cs_wait_for_sync(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomi2cs_is_syncing(const void *const hw, hri_sercomi2cs_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->I2CS.SYNCBUSY.reg & reg; +} + +static inline void hri_sercomspi_wait_for_sync(const void *const hw, hri_sercomspi_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->SPI.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomspi_is_syncing(const void *const hw, hri_sercomspi_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->SPI.SYNCBUSY.reg & reg; +} + +static inline void hri_sercomusart_wait_for_sync(const void *const hw, hri_sercomusart_syncbusy_reg_t reg) +{ + while (((Sercom *)hw)->USART.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_sercomusart_is_syncing(const void *const hw, hri_sercomusart_syncbusy_reg_t reg) +{ + return ((Sercom *)hw)->USART.SYNCBUSY.reg & reg; +} + +static inline bool hri_sercomi2cm_get_INTFLAG_MB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; +} + +static inline bool hri_sercomi2cm_get_INTFLAG_SB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; +} + +static inline bool hri_sercomi2cm_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR; +} + +static inline bool hri_sercomi2cm_get_interrupt_MB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_MB) >> SERCOM_I2CM_INTFLAG_MB_Pos; +} + +static inline void hri_sercomi2cm_clear_interrupt_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_MB; +} + +static inline bool hri_sercomi2cm_get_interrupt_SB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_SB) >> SERCOM_I2CM_INTFLAG_SB_Pos; +} + +static inline void hri_sercomi2cm_clear_interrupt_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_SB; +} + +static inline bool hri_sercomi2cm_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTFLAG.reg & SERCOM_I2CM_INTFLAG_ERROR) >> SERCOM_I2CM_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cm_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = SERCOM_I2CM_INTFLAG_ERROR; +} + +static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_get_INTFLAG_reg(const void *const hw, + hri_sercomi2cm_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cm_intflag_reg_t hri_sercomi2cm_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.INTFLAG.reg; +} + +static inline void hri_sercomi2cm_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cm_intflag_reg_t mask) +{ + ((Sercom *)hw)->I2CM.INTFLAG.reg = mask; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_PREC_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_AMATCH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_DRDY_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; +} + +static inline bool hri_sercomi2cs_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR; +} + +static inline bool hri_sercomi2cs_get_interrupt_PREC_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_PREC) >> SERCOM_I2CS_INTFLAG_PREC_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_PREC; +} + +static inline bool hri_sercomi2cs_get_interrupt_AMATCH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_AMATCH) >> SERCOM_I2CS_INTFLAG_AMATCH_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_AMATCH; +} + +static inline bool hri_sercomi2cs_get_interrupt_DRDY_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_DRDY) >> SERCOM_I2CS_INTFLAG_DRDY_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_DRDY; +} + +static inline bool hri_sercomi2cs_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTFLAG.reg & SERCOM_I2CS_INTFLAG_ERROR) >> SERCOM_I2CS_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomi2cs_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = SERCOM_I2CS_INTFLAG_ERROR; +} + +static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_get_INTFLAG_reg(const void *const hw, + hri_sercomi2cs_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cs_intflag_reg_t hri_sercomi2cs_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.INTFLAG.reg; +} + +static inline void hri_sercomi2cs_clear_INTFLAG_reg(const void *const hw, hri_sercomi2cs_intflag_reg_t mask) +{ + ((Sercom *)hw)->I2CS.INTFLAG.reg = mask; +} + +static inline bool hri_sercomspi_get_INTFLAG_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE; +} + +static inline bool hri_sercomspi_get_INTFLAG_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC; +} + +static inline bool hri_sercomspi_get_INTFLAG_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC; +} + +static inline bool hri_sercomspi_get_INTFLAG_SSL_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL; +} + +static inline bool hri_sercomspi_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomspi_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR; +} + +static inline bool hri_sercomspi_get_interrupt_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_DRE) >> SERCOM_SPI_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_DRE; +} + +static inline bool hri_sercomspi_get_interrupt_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_TXC) >> SERCOM_SPI_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_TXC; +} + +static inline bool hri_sercomspi_get_interrupt_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_RXC) >> SERCOM_SPI_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_RXC; +} + +static inline bool hri_sercomspi_get_interrupt_SSL_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_SSL) >> SERCOM_SPI_INTFLAG_SSL_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_SSL; +} + +static inline bool hri_sercomspi_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTFLAG.reg & SERCOM_SPI_INTFLAG_ERROR) >> SERCOM_SPI_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomspi_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = SERCOM_SPI_INTFLAG_ERROR; +} + +static inline hri_sercomspi_intflag_reg_t hri_sercomspi_get_INTFLAG_reg(const void *const hw, + hri_sercomspi_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomspi_intflag_reg_t hri_sercomspi_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.INTFLAG.reg; +} + +static inline void hri_sercomspi_clear_INTFLAG_reg(const void *const hw, hri_sercomspi_intflag_reg_t mask) +{ + ((Sercom *)hw)->SPI.INTFLAG.reg = mask; +} + +static inline bool hri_sercomusart_get_INTFLAG_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE; +} + +static inline bool hri_sercomusart_get_INTFLAG_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; +} + +static inline bool hri_sercomusart_get_INTFLAG_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; +} + +static inline bool hri_sercomusart_get_INTFLAG_RXS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; +} + +static inline bool hri_sercomusart_get_INTFLAG_CTSIC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; +} + +static inline bool hri_sercomusart_get_INTFLAG_RXBRK_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; +} + +static inline bool hri_sercomusart_get_INTFLAG_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomusart_clear_INTFLAG_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; +} + +static inline bool hri_sercomusart_get_interrupt_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_DRE) >> SERCOM_USART_INTFLAG_DRE_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_DRE; +} + +static inline bool hri_sercomusart_get_interrupt_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_TXC) >> SERCOM_USART_INTFLAG_TXC_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_TXC; +} + +static inline bool hri_sercomusart_get_interrupt_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXC) >> SERCOM_USART_INTFLAG_RXC_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXC; +} + +static inline bool hri_sercomusart_get_interrupt_RXS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXS) >> SERCOM_USART_INTFLAG_RXS_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXS; +} + +static inline bool hri_sercomusart_get_interrupt_CTSIC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_CTSIC) >> SERCOM_USART_INTFLAG_CTSIC_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_CTSIC; +} + +static inline bool hri_sercomusart_get_interrupt_RXBRK_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_RXBRK) >> SERCOM_USART_INTFLAG_RXBRK_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_RXBRK; +} + +static inline bool hri_sercomusart_get_interrupt_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTFLAG.reg & SERCOM_USART_INTFLAG_ERROR) >> SERCOM_USART_INTFLAG_ERROR_Pos; +} + +static inline void hri_sercomusart_clear_interrupt_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = SERCOM_USART_INTFLAG_ERROR; +} + +static inline hri_sercomusart_intflag_reg_t hri_sercomusart_get_INTFLAG_reg(const void *const hw, + hri_sercomusart_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_intflag_reg_t hri_sercomusart_read_INTFLAG_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.INTFLAG.reg; +} + +static inline void hri_sercomusart_clear_INTFLAG_reg(const void *const hw, hri_sercomusart_intflag_reg_t mask) +{ + ((Sercom *)hw)->USART.INTFLAG.reg = mask; +} + +static inline void hri_sercomi2cm_set_INTEN_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB; +} + +static inline bool hri_sercomi2cm_get_INTEN_MB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_MB) >> SERCOM_I2CM_INTENSET_MB_Pos; +} + +static inline void hri_sercomi2cm_write_INTEN_MB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB; + } else { + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_MB; + } +} + +static inline void hri_sercomi2cm_clear_INTEN_MB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_MB; +} + +static inline void hri_sercomi2cm_set_INTEN_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB; +} + +static inline bool hri_sercomi2cm_get_INTEN_SB_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_SB) >> SERCOM_I2CM_INTENSET_SB_Pos; +} + +static inline void hri_sercomi2cm_write_INTEN_SB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB; + } else { + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_SB; + } +} + +static inline void hri_sercomi2cm_clear_INTEN_SB_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_SB; +} + +static inline void hri_sercomi2cm_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR; +} + +static inline bool hri_sercomi2cm_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.INTENSET.reg & SERCOM_I2CM_INTENSET_ERROR) >> SERCOM_I2CM_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomi2cm_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR; + } else { + ((Sercom *)hw)->I2CM.INTENSET.reg = SERCOM_I2CM_INTENSET_ERROR; + } +} + +static inline void hri_sercomi2cm_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = SERCOM_I2CM_INTENSET_ERROR; +} + +static inline void hri_sercomi2cm_set_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = mask; +} + +static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_get_INTEN_reg(const void *const hw, + hri_sercomi2cm_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cm_intenset_reg_t hri_sercomi2cm_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.INTENSET.reg; +} + +static inline void hri_sercomi2cm_write_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t data) +{ + ((Sercom *)hw)->I2CM.INTENSET.reg = data; + ((Sercom *)hw)->I2CM.INTENCLR.reg = ~data; +} + +static inline void hri_sercomi2cm_clear_INTEN_reg(const void *const hw, hri_sercomi2cm_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CM.INTENCLR.reg = mask; +} + +static inline void hri_sercomi2cs_set_INTEN_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC; +} + +static inline bool hri_sercomi2cs_get_INTEN_PREC_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_PREC) >> SERCOM_I2CS_INTENSET_PREC_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_PREC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_PREC; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_PREC_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_PREC; +} + +static inline void hri_sercomi2cs_set_INTEN_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH; +} + +static inline bool hri_sercomi2cs_get_INTEN_AMATCH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_AMATCH) >> SERCOM_I2CS_INTENSET_AMATCH_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_AMATCH_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_AMATCH; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_AMATCH_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_AMATCH; +} + +static inline void hri_sercomi2cs_set_INTEN_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY; +} + +static inline bool hri_sercomi2cs_get_INTEN_DRDY_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_DRDY) >> SERCOM_I2CS_INTENSET_DRDY_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_DRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_DRDY; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_DRDY_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_DRDY; +} + +static inline void hri_sercomi2cs_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR; +} + +static inline bool hri_sercomi2cs_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.INTENSET.reg & SERCOM_I2CS_INTENSET_ERROR) >> SERCOM_I2CS_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomi2cs_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR; + } else { + ((Sercom *)hw)->I2CS.INTENSET.reg = SERCOM_I2CS_INTENSET_ERROR; + } +} + +static inline void hri_sercomi2cs_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = SERCOM_I2CS_INTENSET_ERROR; +} + +static inline void hri_sercomi2cs_set_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = mask; +} + +static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_get_INTEN_reg(const void *const hw, + hri_sercomi2cs_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CS.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cs_intenset_reg_t hri_sercomi2cs_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.INTENSET.reg; +} + +static inline void hri_sercomi2cs_write_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t data) +{ + ((Sercom *)hw)->I2CS.INTENSET.reg = data; + ((Sercom *)hw)->I2CS.INTENCLR.reg = ~data; +} + +static inline void hri_sercomi2cs_clear_INTEN_reg(const void *const hw, hri_sercomi2cs_intenset_reg_t mask) +{ + ((Sercom *)hw)->I2CS.INTENCLR.reg = mask; +} + +static inline void hri_sercomspi_set_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE; +} + +static inline bool hri_sercomspi_get_INTEN_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_DRE) >> SERCOM_SPI_INTENSET_DRE_Pos; +} + +static inline void hri_sercomspi_write_INTEN_DRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_DRE; + } +} + +static inline void hri_sercomspi_clear_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_DRE; +} + +static inline void hri_sercomspi_set_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; +} + +static inline bool hri_sercomspi_get_INTEN_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_TXC) >> SERCOM_SPI_INTENSET_TXC_Pos; +} + +static inline void hri_sercomspi_write_INTEN_TXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_TXC; + } +} + +static inline void hri_sercomspi_clear_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_TXC; +} + +static inline void hri_sercomspi_set_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC; +} + +static inline bool hri_sercomspi_get_INTEN_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_RXC) >> SERCOM_SPI_INTENSET_RXC_Pos; +} + +static inline void hri_sercomspi_write_INTEN_RXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_RXC; + } +} + +static inline void hri_sercomspi_clear_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_RXC; +} + +static inline void hri_sercomspi_set_INTEN_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL; +} + +static inline bool hri_sercomspi_get_INTEN_SSL_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_SSL) >> SERCOM_SPI_INTENSET_SSL_Pos; +} + +static inline void hri_sercomspi_write_INTEN_SSL_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_SSL; + } +} + +static inline void hri_sercomspi_clear_INTEN_SSL_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_SSL; +} + +static inline void hri_sercomspi_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR; +} + +static inline bool hri_sercomspi_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.INTENSET.reg & SERCOM_SPI_INTENSET_ERROR) >> SERCOM_SPI_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomspi_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR; + } else { + ((Sercom *)hw)->SPI.INTENSET.reg = SERCOM_SPI_INTENSET_ERROR; + } +} + +static inline void hri_sercomspi_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = SERCOM_SPI_INTENSET_ERROR; +} + +static inline void hri_sercomspi_set_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = mask; +} + +static inline hri_sercomspi_intenset_reg_t hri_sercomspi_get_INTEN_reg(const void *const hw, + hri_sercomspi_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomspi_intenset_reg_t hri_sercomspi_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.INTENSET.reg; +} + +static inline void hri_sercomspi_write_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t data) +{ + ((Sercom *)hw)->SPI.INTENSET.reg = data; + ((Sercom *)hw)->SPI.INTENCLR.reg = ~data; +} + +static inline void hri_sercomspi_clear_INTEN_reg(const void *const hw, hri_sercomspi_intenset_reg_t mask) +{ + ((Sercom *)hw)->SPI.INTENCLR.reg = mask; +} + +static inline void hri_sercomusart_set_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; +} + +static inline bool hri_sercomusart_get_INTEN_DRE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_DRE) >> SERCOM_USART_INTENSET_DRE_Pos; +} + +static inline void hri_sercomusart_write_INTEN_DRE_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_DRE; + } +} + +static inline void hri_sercomusart_clear_INTEN_DRE_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_DRE; +} + +static inline void hri_sercomusart_set_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; +} + +static inline bool hri_sercomusart_get_INTEN_TXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_TXC) >> SERCOM_USART_INTENSET_TXC_Pos; +} + +static inline void hri_sercomusart_write_INTEN_TXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_TXC; + } +} + +static inline void hri_sercomusart_clear_INTEN_TXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_TXC; +} + +static inline void hri_sercomusart_set_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC; +} + +static inline bool hri_sercomusart_get_INTEN_RXC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXC) >> SERCOM_USART_INTENSET_RXC_Pos; +} + +static inline void hri_sercomusart_write_INTEN_RXC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXC; + } +} + +static inline void hri_sercomusart_clear_INTEN_RXC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXC; +} + +static inline void hri_sercomusart_set_INTEN_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS; +} + +static inline bool hri_sercomusart_get_INTEN_RXS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXS) >> SERCOM_USART_INTENSET_RXS_Pos; +} + +static inline void hri_sercomusart_write_INTEN_RXS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXS; + } +} + +static inline void hri_sercomusart_clear_INTEN_RXS_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXS; +} + +static inline void hri_sercomusart_set_INTEN_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC; +} + +static inline bool hri_sercomusart_get_INTEN_CTSIC_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_CTSIC) >> SERCOM_USART_INTENSET_CTSIC_Pos; +} + +static inline void hri_sercomusart_write_INTEN_CTSIC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_CTSIC; + } +} + +static inline void hri_sercomusart_clear_INTEN_CTSIC_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_CTSIC; +} + +static inline void hri_sercomusart_set_INTEN_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK; +} + +static inline bool hri_sercomusart_get_INTEN_RXBRK_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_RXBRK) >> SERCOM_USART_INTENSET_RXBRK_Pos; +} + +static inline void hri_sercomusart_write_INTEN_RXBRK_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_RXBRK; + } +} + +static inline void hri_sercomusart_clear_INTEN_RXBRK_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_RXBRK; +} + +static inline void hri_sercomusart_set_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR; +} + +static inline bool hri_sercomusart_get_INTEN_ERROR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.INTENSET.reg & SERCOM_USART_INTENSET_ERROR) >> SERCOM_USART_INTENSET_ERROR_Pos; +} + +static inline void hri_sercomusart_write_INTEN_ERROR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR; + } else { + ((Sercom *)hw)->USART.INTENSET.reg = SERCOM_USART_INTENSET_ERROR; + } +} + +static inline void hri_sercomusart_clear_INTEN_ERROR_bit(const void *const hw) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = SERCOM_USART_INTENSET_ERROR; +} + +static inline void hri_sercomusart_set_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask) +{ + ((Sercom *)hw)->USART.INTENSET.reg = mask; +} + +static inline hri_sercomusart_intenset_reg_t hri_sercomusart_get_INTEN_reg(const void *const hw, + hri_sercomusart_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_intenset_reg_t hri_sercomusart_read_INTEN_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.INTENSET.reg; +} + +static inline void hri_sercomusart_write_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t data) +{ + ((Sercom *)hw)->USART.INTENSET.reg = data; + ((Sercom *)hw)->USART.INTENCLR.reg = ~data; +} + +static inline void hri_sercomusart_clear_INTEN_reg(const void *const hw, hri_sercomusart_intenset_reg_t mask) +{ + ((Sercom *)hw)->USART.INTENCLR.reg = mask; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SWRST) >> SERCOM_I2CM_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_ENABLE) >> SERCOM_I2CM_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_SYSOP_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_SYSOP) >> SERCOM_I2CM_SYNCBUSY_SYSOP_Pos; +} + +static inline bool hri_sercomi2cm_get_SYNCBUSY_LENGTH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.SYNCBUSY.reg & SERCOM_I2CM_SYNCBUSY_LENGTH) >> SERCOM_I2CM_SYNCBUSY_LENGTH_Pos; +} + +static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_get_SYNCBUSY_reg(const void *const hw, + hri_sercomi2cm_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cm_syncbusy_reg_t hri_sercomi2cm_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.SYNCBUSY.reg; +} + +static inline bool hri_sercomi2cs_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_SWRST) >> SERCOM_I2CS_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomi2cs_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_ENABLE) >> SERCOM_I2CS_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomi2cs_get_SYNCBUSY_LENGTH_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.SYNCBUSY.reg & SERCOM_I2CS_SYNCBUSY_LENGTH) >> SERCOM_I2CS_SYNCBUSY_LENGTH_Pos; +} + +static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_get_SYNCBUSY_reg(const void *const hw, + hri_sercomi2cs_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomi2cs_syncbusy_reg_t hri_sercomi2cs_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.SYNCBUSY.reg; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_SWRST) >> SERCOM_SPI_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_ENABLE) >> SERCOM_SPI_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_CTRLB) >> SERCOM_SPI_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_sercomspi_get_SYNCBUSY_LENGTH_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.SYNCBUSY.reg & SERCOM_SPI_SYNCBUSY_LENGTH) >> SERCOM_SPI_SYNCBUSY_LENGTH_Pos; +} + +static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_get_SYNCBUSY_reg(const void *const hw, + hri_sercomspi_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomspi_syncbusy_reg_t hri_sercomspi_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.SYNCBUSY.reg; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_SWRST) >> SERCOM_USART_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_ENABLE) >> SERCOM_USART_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_CTRLB) >> SERCOM_USART_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_RXERRCNT_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_RXERRCNT) >> SERCOM_USART_SYNCBUSY_RXERRCNT_Pos; +} + +static inline bool hri_sercomusart_get_SYNCBUSY_LENGTH_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.SYNCBUSY.reg & SERCOM_USART_SYNCBUSY_LENGTH) >> SERCOM_USART_SYNCBUSY_LENGTH_Pos; +} + +static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_get_SYNCBUSY_reg(const void *const hw, + hri_sercomusart_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_syncbusy_reg_t hri_sercomusart_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.SYNCBUSY.reg; +} + +static inline hri_sercomusart_rxerrcnt_reg_t hri_sercomusart_get_RXERRCNT_reg(const void *const hw, + hri_sercomusart_rxerrcnt_reg_t mask) +{ + uint8_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.RXERRCNT.reg; + tmp &= mask; + return tmp; +} + +static inline hri_sercomusart_rxerrcnt_reg_t hri_sercomusart_read_RXERRCNT_reg(const void *const hw) +{ + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + return ((Sercom *)hw)->USART.RXERRCNT.reg; +} + +static inline void hri_sercomi2cm_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SWRST; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SWRST) >> SERCOM_I2CM_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_ENABLE; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_ENABLE) >> SERCOM_I2CM_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_ENABLE; + tmp |= value << SERCOM_I2CM_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_ENABLE; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_ENABLE; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_RUNSTDBY; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_RUNSTDBY) >> SERCOM_I2CM_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_I2CM_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_RUNSTDBY; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_RUNSTDBY; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_PINOUT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_PINOUT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_PINOUT) >> SERCOM_I2CM_CTRLA_PINOUT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_PINOUT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_PINOUT; + tmp |= value << SERCOM_I2CM_CTRLA_PINOUT_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_PINOUT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_PINOUT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_MEXTTOEN) >> SERCOM_I2CM_CTRLA_MEXTTOEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_MEXTTOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_MEXTTOEN; + tmp |= value << SERCOM_I2CM_CTRLA_MEXTTOEN_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_MEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SEXTTOEN) >> SERCOM_I2CM_CTRLA_SEXTTOEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SEXTTOEN; + tmp |= value << SERCOM_I2CM_CTRLA_SEXTTOEN_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SEXTTOEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SCLSM; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_SCLSM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SCLSM) >> SERCOM_I2CM_CTRLA_SCLSM_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SCLSM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SCLSM; + tmp |= value << SERCOM_I2CM_CTRLA_SCLSM_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SCLSM; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SCLSM; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_LOWTOUTEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_LOWTOUTEN) >> SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN; + tmp |= value << SERCOM_I2CM_CTRLA_LOWTOUTEN_Pos; + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_LOWTOUTEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_LOWTOUTEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_MODE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_MODE(mask)) >> SERCOM_I2CM_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_MODE_Msk; + tmp |= SERCOM_I2CM_CTRLA_MODE(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_MODE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_MODE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_MODE_Msk) >> SERCOM_I2CM_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SDAHOLD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SDAHOLD_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SDAHOLD_Msk; + tmp |= SERCOM_I2CM_CTRLA_SDAHOLD(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SDAHOLD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SDAHOLD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SDAHOLD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CM_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_SPEED(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_SPEED_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED(mask)) >> SERCOM_I2CM_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_SPEED_Msk; + tmp |= SERCOM_I2CM_CTRLA_SPEED(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_SPEED(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_SPEED(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_SPEED_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_SPEED_Msk) >> SERCOM_I2CM_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= SERCOM_I2CM_CTRLA_INACTOUT(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_INACTOUT_bf(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT(mask)) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= ~SERCOM_I2CM_CTRLA_INACTOUT_Msk; + tmp |= SERCOM_I2CM_CTRLA_INACTOUT(data); + ((Sercom *)hw)->I2CM.CTRLA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~SERCOM_I2CM_CTRLA_INACTOUT(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_INACTOUT_bf(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= SERCOM_I2CM_CTRLA_INACTOUT(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_INACTOUT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp = (tmp & SERCOM_I2CM_CTRLA_INACTOUT_Msk) >> SERCOM_I2CM_CTRLA_INACTOUT_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg |= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_get_CTRLA_reg(const void *const hw, + hri_sercomi2cm_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CM.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg = data; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg &= ~mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cm_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLA.reg ^= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrla_reg_t hri_sercomi2cm_read_CTRLA_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SWRST | SERCOM_I2CM_SYNCBUSY_ENABLE); + return ((Sercom *)hw)->I2CM.CTRLA.reg; +} + +static inline void hri_sercomi2cs_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SWRST; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SWRST) >> SERCOM_I2CS_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_ENABLE; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_ENABLE) >> SERCOM_I2CS_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_ENABLE; + tmp |= value << SERCOM_I2CS_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_ENABLE; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_ENABLE; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_RUNSTDBY; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_RUNSTDBY) >> SERCOM_I2CS_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_I2CS_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_RUNSTDBY; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_RUNSTDBY; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_PINOUT; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_PINOUT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_PINOUT) >> SERCOM_I2CS_CTRLA_PINOUT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_PINOUT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_PINOUT; + tmp |= value << SERCOM_I2CS_CTRLA_PINOUT_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_PINOUT; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_PINOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_PINOUT; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SEXTTOEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SEXTTOEN) >> SERCOM_I2CS_CTRLA_SEXTTOEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SEXTTOEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SEXTTOEN; + tmp |= value << SERCOM_I2CS_CTRLA_SEXTTOEN_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SEXTTOEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SEXTTOEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SEXTTOEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SCLSM; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_SCLSM_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SCLSM) >> SERCOM_I2CS_CTRLA_SCLSM_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SCLSM_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SCLSM; + tmp |= value << SERCOM_I2CS_CTRLA_SCLSM_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SCLSM; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SCLSM_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SCLSM; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_LOWTOUTEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_LOWTOUTEN) >> SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_LOWTOUTEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN; + tmp |= value << SERCOM_I2CS_CTRLA_LOWTOUTEN_Pos; + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_LOWTOUTEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_LOWTOUTEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_LOWTOUTEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_MODE(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_MODE(mask)) >> SERCOM_I2CS_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_MODE_Msk; + tmp |= SERCOM_I2CS_CTRLA_MODE(data); + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_MODE(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_MODE(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_MODE_Msk) >> SERCOM_I2CS_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SDAHOLD(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SDAHOLD_bf(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD(mask)) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SDAHOLD_Msk; + tmp |= SERCOM_I2CS_CTRLA_SDAHOLD(data); + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SDAHOLD(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SDAHOLD_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SDAHOLD(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SDAHOLD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SDAHOLD_Msk) >> SERCOM_I2CS_CTRLA_SDAHOLD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= SERCOM_I2CS_CTRLA_SPEED(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_SPEED_bf(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED(mask)) >> SERCOM_I2CS_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= ~SERCOM_I2CS_CTRLA_SPEED_Msk; + tmp |= SERCOM_I2CS_CTRLA_SPEED(data); + ((Sercom *)hw)->I2CS.CTRLA.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~SERCOM_I2CS_CTRLA_SPEED(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_SPEED_bf(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= SERCOM_I2CS_CTRLA_SPEED(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_SPEED_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp = (tmp & SERCOM_I2CS_CTRLA_SPEED_Msk) >> SERCOM_I2CS_CTRLA_SPEED_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg |= mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_get_CTRLA_reg(const void *const hw, + hri_sercomi2cs_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->I2CS.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg = data; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg &= ~mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLA_reg(const void *const hw, hri_sercomi2cs_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLA.reg ^= mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrla_reg_t hri_sercomi2cs_read_CTRLA_reg(const void *const hw) +{ + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_SWRST | SERCOM_I2CS_SYNCBUSY_ENABLE); + return ((Sercom *)hw)->I2CS.CTRLA.reg; +} + +static inline void hri_sercomspi_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_SWRST; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_SWRST) >> SERCOM_SPI_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_ENABLE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_ENABLE) >> SERCOM_SPI_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_ENABLE; + tmp |= value << SERCOM_SPI_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_ENABLE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_ENABLE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_RUNSTDBY; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_RUNSTDBY) >> SERCOM_SPI_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_SPI_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_RUNSTDBY; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_RUNSTDBY; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_IBON; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_IBON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_IBON) >> SERCOM_SPI_CTRLA_IBON_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_IBON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_IBON; + tmp |= value << SERCOM_SPI_CTRLA_IBON_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_IBON; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_IBON; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_CPHA_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPHA; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_CPHA_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_CPHA) >> SERCOM_SPI_CTRLA_CPHA_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_CPHA_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_CPHA; + tmp |= value << SERCOM_SPI_CTRLA_CPHA_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_CPHA_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPHA; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_CPHA_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPHA; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_CPOL; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_CPOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_CPOL) >> SERCOM_SPI_CTRLA_CPOL_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_CPOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_CPOL; + tmp |= value << SERCOM_SPI_CTRLA_CPOL_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_CPOL; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_CPOL; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DORD; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLA_DORD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DORD) >> SERCOM_SPI_CTRLA_DORD_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLA_DORD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_DORD; + tmp |= value << SERCOM_SPI_CTRLA_DORD_Pos; + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DORD; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DORD; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_MODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_MODE(mask)) >> SERCOM_SPI_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_MODE_Msk; + tmp |= SERCOM_SPI_CTRLA_MODE(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_MODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_MODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_MODE_Msk) >> SERCOM_SPI_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DOPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DOPO_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DOPO(mask)) >> SERCOM_SPI_CTRLA_DOPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_DOPO_Msk; + tmp |= SERCOM_SPI_CTRLA_DOPO(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DOPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_DOPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DOPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DOPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DOPO_Msk) >> SERCOM_SPI_CTRLA_DOPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_DIPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_DIPO_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DIPO(mask)) >> SERCOM_SPI_CTRLA_DIPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_DIPO_Msk; + tmp |= SERCOM_SPI_CTRLA_DIPO(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_DIPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_DIPO_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_DIPO(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_DIPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_DIPO_Msk) >> SERCOM_SPI_CTRLA_DIPO_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= SERCOM_SPI_CTRLA_FORM(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_FORM_bf(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_FORM(mask)) >> SERCOM_SPI_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= ~SERCOM_SPI_CTRLA_FORM_Msk; + tmp |= SERCOM_SPI_CTRLA_FORM(data); + ((Sercom *)hw)->SPI.CTRLA.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~SERCOM_SPI_CTRLA_FORM(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= SERCOM_SPI_CTRLA_FORM(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_FORM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp = (tmp & SERCOM_SPI_CTRLA_FORM_Msk) >> SERCOM_SPI_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg |= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_get_CTRLA_reg(const void *const hw, + hri_sercomspi_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->SPI.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg = data; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg &= ~mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLA_reg(const void *const hw, hri_sercomspi_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLA.reg ^= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrla_reg_t hri_sercomspi_read_CTRLA_reg(const void *const hw) +{ + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_SWRST | SERCOM_SPI_SYNCBUSY_ENABLE); + return ((Sercom *)hw)->SPI.CTRLA.reg; +} + +static inline void hri_sercomusart_set_CTRLA_SWRST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SWRST; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SWRST) >> SERCOM_USART_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_set_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_ENABLE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_ENABLE) >> SERCOM_USART_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_ENABLE; + tmp |= value << SERCOM_USART_CTRLA_ENABLE_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_ENABLE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_ENABLE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RUNSTDBY; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RUNSTDBY) >> SERCOM_USART_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_RUNSTDBY; + tmp |= value << SERCOM_USART_CTRLA_RUNSTDBY_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RUNSTDBY; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RUNSTDBY; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_IBON; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_IBON_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_IBON) >> SERCOM_USART_CTRLA_IBON_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_IBON_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_IBON; + tmp |= value << SERCOM_USART_CTRLA_IBON_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_IBON; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_IBON_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_IBON; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_TXINV_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXINV; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_TXINV_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_TXINV) >> SERCOM_USART_CTRLA_TXINV_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_TXINV_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_TXINV; + tmp |= value << SERCOM_USART_CTRLA_TXINV_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_TXINV_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXINV; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_TXINV_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXINV; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_RXINV_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXINV; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_RXINV_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RXINV) >> SERCOM_USART_CTRLA_RXINV_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_RXINV_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_RXINV; + tmp |= value << SERCOM_USART_CTRLA_RXINV_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_RXINV_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXINV; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_RXINV_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXINV; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_CMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_CMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_CMODE) >> SERCOM_USART_CTRLA_CMODE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_CMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_CMODE; + tmp |= value << SERCOM_USART_CTRLA_CMODE_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_CMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_CMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_CPOL; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_CPOL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_CPOL) >> SERCOM_USART_CTRLA_CPOL_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_CPOL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_CPOL; + tmp |= value << SERCOM_USART_CTRLA_CPOL_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_CPOL; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_CPOL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_CPOL; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_DORD; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLA_DORD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_DORD) >> SERCOM_USART_CTRLA_DORD_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLA_DORD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_DORD; + tmp |= value << SERCOM_USART_CTRLA_DORD_Pos; + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_DORD; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_DORD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_DORD; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_MODE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_MODE_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_MODE(mask)) >> SERCOM_USART_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_MODE_Msk; + tmp |= SERCOM_USART_CTRLA_MODE(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_MODE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_MODE_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_MODE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_MODE_Msk) >> SERCOM_USART_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPR(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPR_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPR(mask)) >> SERCOM_USART_CTRLA_SAMPR_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_SAMPR_Msk; + tmp |= SERCOM_USART_CTRLA_SAMPR(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPR(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_SAMPR_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPR(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPR_Msk) >> SERCOM_USART_CTRLA_SAMPR_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_TXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_TXPO_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_TXPO(mask)) >> SERCOM_USART_CTRLA_TXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_TXPO_Msk; + tmp |= SERCOM_USART_CTRLA_TXPO(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_TXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_TXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_TXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_TXPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_TXPO_Msk) >> SERCOM_USART_CTRLA_TXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_RXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_RXPO_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RXPO(mask)) >> SERCOM_USART_CTRLA_RXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_RXPO_Msk; + tmp |= SERCOM_USART_CTRLA_RXPO(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_RXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_RXPO_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_RXPO(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_RXPO_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_RXPO_Msk) >> SERCOM_USART_CTRLA_RXPO_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_SAMPA(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_SAMPA_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPA(mask)) >> SERCOM_USART_CTRLA_SAMPA_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_SAMPA_Msk; + tmp |= SERCOM_USART_CTRLA_SAMPA(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_SAMPA(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_SAMPA_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_SAMPA(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_SAMPA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_SAMPA_Msk) >> SERCOM_USART_CTRLA_SAMPA_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= SERCOM_USART_CTRLA_FORM(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_FORM_bf(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_FORM(mask)) >> SERCOM_USART_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= ~SERCOM_USART_CTRLA_FORM_Msk; + tmp |= SERCOM_USART_CTRLA_FORM(data); + ((Sercom *)hw)->USART.CTRLA.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~SERCOM_USART_CTRLA_FORM(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_FORM_bf(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= SERCOM_USART_CTRLA_FORM(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_FORM_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp = (tmp & SERCOM_USART_CTRLA_FORM_Msk) >> SERCOM_USART_CTRLA_FORM_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg |= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_get_CTRLA_reg(const void *const hw, + hri_sercomusart_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + tmp = ((Sercom *)hw)->USART.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg = data; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg &= ~mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLA_reg(const void *const hw, hri_sercomusart_ctrla_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLA.reg ^= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrla_reg_t hri_sercomusart_read_CTRLA_reg(const void *const hw) +{ + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_SWRST | SERCOM_USART_SYNCBUSY_ENABLE); + return ((Sercom *)hw)->USART.CTRLA.reg; +} + +static inline void hri_sercomi2cm_set_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_SMEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLB_SMEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_SMEN) >> SERCOM_I2CM_CTRLB_SMEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_SMEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_SMEN; + tmp |= value << SERCOM_I2CM_CTRLB_SMEN_Pos; + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_SMEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_SMEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLB_QCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_QCEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLB_QCEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_QCEN) >> SERCOM_I2CM_CTRLB_QCEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_QCEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_QCEN; + tmp |= value << SERCOM_I2CM_CTRLB_QCEN_Pos; + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_QCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_QCEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_QCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_QCEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_ACKACT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLB_ACKACT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_ACKACT) >> SERCOM_I2CM_CTRLB_ACKACT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_ACKACT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_ACKACT; + tmp |= value << SERCOM_I2CM_CTRLB_ACKACT_Pos; + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_ACKACT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_ACKACT; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= SERCOM_I2CM_CTRLB_CMD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_CMD_bf(const void *const hw, + hri_sercomi2cm_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_CMD(mask)) >> SERCOM_I2CM_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= ~SERCOM_I2CM_CTRLB_CMD_Msk; + tmp |= SERCOM_I2CM_CTRLB_CMD(data); + ((Sercom *)hw)->I2CM.CTRLB.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~SERCOM_I2CM_CTRLB_CMD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= SERCOM_I2CM_CTRLB_CMD(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_CMD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp = (tmp & SERCOM_I2CM_CTRLB_CMD_Msk) >> SERCOM_I2CM_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg |= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_get_CTRLB_reg(const void *const hw, + hri_sercomi2cm_ctrlb_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg = data; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg &= ~mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cm_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLB.reg ^= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlb_reg_t hri_sercomi2cm_read_CTRLB_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return ((Sercom *)hw)->I2CM.CTRLB.reg; +} + +static inline void hri_sercomi2cs_set_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_SMEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_SMEN) >> SERCOM_I2CS_CTRLB_SMEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_SMEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_SMEN; + tmp |= value << SERCOM_I2CS_CTRLB_SMEN_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_SMEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_SMEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_GCMD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_GCMD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_GCMD_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_GCMD) >> SERCOM_I2CS_CTRLB_GCMD_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_GCMD_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_GCMD; + tmp |= value << SERCOM_I2CS_CTRLB_GCMD_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_GCMD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_GCMD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_GCMD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_GCMD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_AACKEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AACKEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_AACKEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_AACKEN) >> SERCOM_I2CS_CTRLB_AACKEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_AACKEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_AACKEN; + tmp |= value << SERCOM_I2CS_CTRLB_AACKEN_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_AACKEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AACKEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_AACKEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AACKEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLB_ACKACT_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_ACKACT) >> SERCOM_I2CS_CTRLB_ACKACT_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_ACKACT_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_ACKACT; + tmp |= value << SERCOM_I2CS_CTRLB_ACKACT_Pos; + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_ACKACT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_ACKACT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_AMODE_bf(const void *const hw, + hri_sercomi2cs_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE(mask)) >> SERCOM_I2CS_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_AMODE_Msk; + tmp |= SERCOM_I2CS_CTRLB_AMODE(data); + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_AMODE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_AMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_AMODE_Msk) >> SERCOM_I2CS_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= SERCOM_I2CS_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_CMD_bf(const void *const hw, + hri_sercomi2cs_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_CMD(mask)) >> SERCOM_I2CS_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= ~SERCOM_I2CS_CTRLB_CMD_Msk; + tmp |= SERCOM_I2CS_CTRLB_CMD(data); + ((Sercom *)hw)->I2CS.CTRLB.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~SERCOM_I2CS_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_CMD_bf(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= SERCOM_I2CS_CTRLB_CMD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_CMD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp = (tmp & SERCOM_I2CS_CTRLB_CMD_Msk) >> SERCOM_I2CS_CTRLB_CMD_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_get_CTRLB_reg(const void *const hw, + hri_sercomi2cs_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLB_reg(const void *const hw, hri_sercomi2cs_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLB.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlb_reg_t hri_sercomi2cs_read_CTRLB_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.CTRLB.reg; +} + +static inline void hri_sercomspi_set_CTRLB_PLOADEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_PLOADEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_PLOADEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_PLOADEN) >> SERCOM_SPI_CTRLB_PLOADEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_PLOADEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_PLOADEN; + tmp |= value << SERCOM_SPI_CTRLB_PLOADEN_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_PLOADEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_PLOADEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_PLOADEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_PLOADEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_SSDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_SSDE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_SSDE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_SSDE) >> SERCOM_SPI_CTRLB_SSDE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_SSDE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_SSDE; + tmp |= value << SERCOM_SPI_CTRLB_SSDE_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_SSDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_SSDE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_SSDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_SSDE; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_MSSEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_MSSEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_MSSEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_MSSEN) >> SERCOM_SPI_CTRLB_MSSEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_MSSEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_MSSEN; + tmp |= value << SERCOM_SPI_CTRLB_MSSEN_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_MSSEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_MSSEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_MSSEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_MSSEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_RXEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLB_RXEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_RXEN) >> SERCOM_SPI_CTRLB_RXEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLB_RXEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_RXEN; + tmp |= value << SERCOM_SPI_CTRLB_RXEN_Pos; + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_RXEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_RXEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_CHSIZE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_CHSIZE_bf(const void *const hw, + hri_sercomspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE(mask)) >> SERCOM_SPI_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_CHSIZE_Msk; + tmp |= SERCOM_SPI_CTRLB_CHSIZE(data); + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_CHSIZE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_CHSIZE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_CHSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_CHSIZE_Msk) >> SERCOM_SPI_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= SERCOM_SPI_CTRLB_AMODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_AMODE_bf(const void *const hw, + hri_sercomspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_AMODE(mask)) >> SERCOM_SPI_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= ~SERCOM_SPI_CTRLB_AMODE_Msk; + tmp |= SERCOM_SPI_CTRLB_AMODE(data); + ((Sercom *)hw)->SPI.CTRLB.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~SERCOM_SPI_CTRLB_AMODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_AMODE_bf(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= SERCOM_SPI_CTRLB_AMODE(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_AMODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp = (tmp & SERCOM_SPI_CTRLB_AMODE_Msk) >> SERCOM_SPI_CTRLB_AMODE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg |= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_get_CTRLB_reg(const void *const hw, + hri_sercomspi_ctrlb_reg_t mask) +{ + uint32_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->SPI.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg = data; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg &= ~mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLB_reg(const void *const hw, hri_sercomspi_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLB.reg ^= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlb_reg_t hri_sercomspi_read_CTRLB_reg(const void *const hw) +{ + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + return ((Sercom *)hw)->SPI.CTRLB.reg; +} + +static inline void hri_sercomusart_set_CTRLB_SBMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SBMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_SBMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_SBMODE) >> SERCOM_USART_CTRLB_SBMODE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_SBMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_SBMODE; + tmp |= value << SERCOM_USART_CTRLB_SBMODE_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_SBMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SBMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_SBMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SBMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_COLDEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_COLDEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_COLDEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_COLDEN) >> SERCOM_USART_CTRLB_COLDEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_COLDEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_COLDEN; + tmp |= value << SERCOM_USART_CTRLB_COLDEN_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_COLDEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_COLDEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_COLDEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_COLDEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_SFDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_SFDE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_SFDE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_SFDE) >> SERCOM_USART_CTRLB_SFDE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_SFDE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_SFDE; + tmp |= value << SERCOM_USART_CTRLB_SFDE_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_SFDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_SFDE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_SFDE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_SFDE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_ENC_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_ENC; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_ENC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_ENC) >> SERCOM_USART_CTRLB_ENC_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_ENC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_ENC; + tmp |= value << SERCOM_USART_CTRLB_ENC_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_ENC_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_ENC; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_ENC_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_ENC; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_PMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_PMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_PMODE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_PMODE) >> SERCOM_USART_CTRLB_PMODE_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_PMODE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_PMODE; + tmp |= value << SERCOM_USART_CTRLB_PMODE_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_PMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_PMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_PMODE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_PMODE; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_TXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_TXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_TXEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_TXEN) >> SERCOM_USART_CTRLB_TXEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_TXEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_TXEN; + tmp |= value << SERCOM_USART_CTRLB_TXEN_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_TXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_TXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_TXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_TXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_RXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLB_RXEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_RXEN) >> SERCOM_USART_CTRLB_RXEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLB_RXEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_RXEN; + tmp |= value << SERCOM_USART_CTRLB_RXEN_Pos; + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_RXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_RXEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_RXEN; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_CHSIZE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_CHSIZE_bf(const void *const hw, + hri_sercomusart_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE(mask)) >> SERCOM_USART_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_CHSIZE_Msk; + tmp |= SERCOM_USART_CTRLB_CHSIZE(data); + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_CHSIZE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_CHSIZE_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_CHSIZE(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_CHSIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_CHSIZE_Msk) >> SERCOM_USART_CTRLB_CHSIZE_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= SERCOM_USART_CTRLB_LINCMD(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_LINCMD_bf(const void *const hw, + hri_sercomusart_ctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_LINCMD(mask)) >> SERCOM_USART_CTRLB_LINCMD_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= ~SERCOM_USART_CTRLB_LINCMD_Msk; + tmp |= SERCOM_USART_CTRLB_LINCMD(data); + ((Sercom *)hw)->USART.CTRLB.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~SERCOM_USART_CTRLB_LINCMD(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_LINCMD_bf(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= SERCOM_USART_CTRLB_LINCMD(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_LINCMD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp = (tmp & SERCOM_USART_CTRLB_LINCMD_Msk) >> SERCOM_USART_CTRLB_LINCMD_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg |= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_get_CTRLB_reg(const void *const hw, + hri_sercomusart_ctrlb_reg_t mask) +{ + uint32_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg = data; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg &= ~mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLB_reg(const void *const hw, hri_sercomusart_ctrlb_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLB.reg ^= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlb_reg_t hri_sercomusart_read_CTRLB_reg(const void *const hw) +{ + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + return ((Sercom *)hw)->USART.CTRLB.reg; +} + +static inline void hri_sercomi2cm_set_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLC.reg |= SERCOM_I2CM_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_CTRLC_DATA32B_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLC.reg; + tmp = (tmp & SERCOM_I2CM_CTRLC_DATA32B) >> SERCOM_I2CM_CTRLC_DATA32B_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_CTRLC_DATA32B_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.CTRLC.reg; + tmp &= ~SERCOM_I2CM_CTRLC_DATA32B; + tmp |= value << SERCOM_I2CM_CTRLC_DATA32B_Pos; + ((Sercom *)hw)->I2CM.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLC.reg &= ~SERCOM_I2CM_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLC.reg ^= SERCOM_I2CM_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLC.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlc_reg_t hri_sercomi2cm_get_CTRLC_reg(const void *const hw, + hri_sercomi2cm_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.CTRLC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLC.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLC.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_CTRLC_reg(const void *const hw, hri_sercomi2cm_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.CTRLC.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_ctrlc_reg_t hri_sercomi2cm_read_CTRLC_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.CTRLC.reg; +} + +static inline void hri_sercomi2cs_set_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg |= SERCOM_I2CS_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_CTRLC_DATA32B_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; + tmp = (tmp & SERCOM_I2CS_CTRLC_DATA32B) >> SERCOM_I2CS_CTRLC_DATA32B_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_CTRLC_DATA32B_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; + tmp &= ~SERCOM_I2CS_CTRLC_DATA32B; + tmp |= value << SERCOM_I2CS_CTRLC_DATA32B_Pos; + ((Sercom *)hw)->I2CS.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg &= ~SERCOM_I2CS_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg ^= SERCOM_I2CS_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg |= SERCOM_I2CS_CTRLC_SDASETUP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_get_CTRLC_SDASETUP_bf(const void *const hw, + hri_sercomi2cs_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; + tmp = (tmp & SERCOM_I2CS_CTRLC_SDASETUP(mask)) >> SERCOM_I2CS_CTRLC_SDASETUP_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; + tmp &= ~SERCOM_I2CS_CTRLC_SDASETUP_Msk; + tmp |= SERCOM_I2CS_CTRLC_SDASETUP(data); + ((Sercom *)hw)->I2CS.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg &= ~SERCOM_I2CS_CTRLC_SDASETUP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLC_SDASETUP_bf(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg ^= SERCOM_I2CS_CTRLC_SDASETUP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_read_CTRLC_SDASETUP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; + tmp = (tmp & SERCOM_I2CS_CTRLC_SDASETUP_Msk) >> SERCOM_I2CS_CTRLC_SDASETUP_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_get_CTRLC_reg(const void *const hw, + hri_sercomi2cs_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.CTRLC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_CTRLC_reg(const void *const hw, hri_sercomi2cs_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.CTRLC.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_ctrlc_reg_t hri_sercomi2cs_read_CTRLC_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.CTRLC.reg; +} + +static inline void hri_sercomspi_set_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg |= SERCOM_SPI_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_CTRLC_DATA32B_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLC.reg; + tmp = (tmp & SERCOM_SPI_CTRLC_DATA32B) >> SERCOM_SPI_CTRLC_DATA32B_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_CTRLC_DATA32B_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLC.reg; + tmp &= ~SERCOM_SPI_CTRLC_DATA32B; + tmp |= value << SERCOM_SPI_CTRLC_DATA32B_Pos; + ((Sercom *)hw)->SPI.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg &= ~SERCOM_SPI_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLC_DATA32B_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg ^= SERCOM_SPI_CTRLC_DATA32B; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg |= SERCOM_SPI_CTRLC_ICSPACE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_get_CTRLC_ICSPACE_bf(const void *const hw, + hri_sercomspi_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLC.reg; + tmp = (tmp & SERCOM_SPI_CTRLC_ICSPACE(mask)) >> SERCOM_SPI_CTRLC_ICSPACE_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.CTRLC.reg; + tmp &= ~SERCOM_SPI_CTRLC_ICSPACE_Msk; + tmp |= SERCOM_SPI_CTRLC_ICSPACE(data); + ((Sercom *)hw)->SPI.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg &= ~SERCOM_SPI_CTRLC_ICSPACE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLC_ICSPACE_bf(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg ^= SERCOM_SPI_CTRLC_ICSPACE(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_read_CTRLC_ICSPACE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLC.reg; + tmp = (tmp & SERCOM_SPI_CTRLC_ICSPACE_Msk) >> SERCOM_SPI_CTRLC_ICSPACE_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_get_CTRLC_reg(const void *const hw, + hri_sercomspi_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.CTRLC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_CTRLC_reg(const void *const hw, hri_sercomspi_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.CTRLC.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_ctrlc_reg_t hri_sercomspi_read_CTRLC_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.CTRLC.reg; +} + +static inline void hri_sercomusart_set_CTRLC_INACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_INACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLC_INACK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_INACK) >> SERCOM_USART_CTRLC_INACK_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLC_INACK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_INACK; + tmp |= value << SERCOM_USART_CTRLC_INACK_Pos; + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_INACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_INACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_INACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_INACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLC_DSNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_DSNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_CTRLC_DSNACK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_DSNACK) >> SERCOM_USART_CTRLC_DSNACK_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_CTRLC_DSNACK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_DSNACK; + tmp |= value << SERCOM_USART_CTRLC_DSNACK_Pos; + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_DSNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_DSNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_DSNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_DSNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_GTIME(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_GTIME_bf(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_GTIME(mask)) >> SERCOM_USART_CTRLC_GTIME_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_GTIME_Msk; + tmp |= SERCOM_USART_CTRLC_GTIME(data); + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_GTIME(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_GTIME_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_GTIME(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_GTIME_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_GTIME_Msk) >> SERCOM_USART_CTRLC_GTIME_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_BRKLEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_BRKLEN_bf(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_BRKLEN(mask)) >> SERCOM_USART_CTRLC_BRKLEN_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_BRKLEN_Msk; + tmp |= SERCOM_USART_CTRLC_BRKLEN(data); + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_BRKLEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_BRKLEN_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_BRKLEN(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_BRKLEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_BRKLEN_Msk) >> SERCOM_USART_CTRLC_BRKLEN_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_HDRDLY(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_HDRDLY_bf(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_HDRDLY(mask)) >> SERCOM_USART_CTRLC_HDRDLY_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_HDRDLY_Msk; + tmp |= SERCOM_USART_CTRLC_HDRDLY(data); + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_HDRDLY(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_HDRDLY_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_HDRDLY(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_HDRDLY_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_HDRDLY_Msk) >> SERCOM_USART_CTRLC_HDRDLY_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_MAXITER(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_MAXITER_bf(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_MAXITER(mask)) >> SERCOM_USART_CTRLC_MAXITER_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_MAXITER_Msk; + tmp |= SERCOM_USART_CTRLC_MAXITER(data); + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_MAXITER(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_MAXITER_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_MAXITER(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_MAXITER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_MAXITER_Msk) >> SERCOM_USART_CTRLC_MAXITER_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= SERCOM_USART_CTRLC_DATA32B(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_DATA32B_bf(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_DATA32B(mask)) >> SERCOM_USART_CTRLC_DATA32B_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= ~SERCOM_USART_CTRLC_DATA32B_Msk; + tmp |= SERCOM_USART_CTRLC_DATA32B(data); + ((Sercom *)hw)->USART.CTRLC.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~SERCOM_USART_CTRLC_DATA32B(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_DATA32B_bf(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= SERCOM_USART_CTRLC_DATA32B(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_DATA32B_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp = (tmp & SERCOM_USART_CTRLC_DATA32B_Msk) >> SERCOM_USART_CTRLC_DATA32B_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_get_CTRLC_reg(const void *const hw, + hri_sercomusart_ctrlc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.CTRLC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_CTRLC_reg(const void *const hw, hri_sercomusart_ctrlc_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.CTRLC.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_ctrlc_reg_t hri_sercomusart_read_CTRLC_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.CTRLC.reg; +} + +static inline void hri_sercomi2cm_set_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUD_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUD(mask)) >> SERCOM_I2CM_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_BAUD_Msk; + tmp |= SERCOM_I2CM_BAUD_BAUD(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUD_Msk) >> SERCOM_I2CM_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_BAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_BAUDLOW_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW(mask)) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_BAUDLOW_Msk; + tmp |= SERCOM_I2CM_BAUD_BAUDLOW(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_BAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_BAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_BAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_BAUDLOW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_BAUDLOW_Msk) >> SERCOM_I2CM_BAUD_BAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUD_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD(mask)) >> SERCOM_I2CM_BAUD_HSBAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_HSBAUD_Msk; + tmp |= SERCOM_I2CM_BAUD_HSBAUD(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_HSBAUD_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUD_Msk) >> SERCOM_I2CM_BAUD_HSBAUD_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= SERCOM_I2CM_BAUD_HSBAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_HSBAUDLOW_bf(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW(mask)) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= ~SERCOM_I2CM_BAUD_HSBAUDLOW_Msk; + tmp |= SERCOM_I2CM_BAUD_HSBAUDLOW(data); + ((Sercom *)hw)->I2CM.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~SERCOM_I2CM_BAUD_HSBAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_HSBAUDLOW_bf(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= SERCOM_I2CM_BAUD_HSBAUDLOW(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_HSBAUDLOW_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp = (tmp & SERCOM_I2CM_BAUD_HSBAUDLOW_Msk) >> SERCOM_I2CM_BAUD_HSBAUDLOW_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_get_BAUD_reg(const void *const hw, + hri_sercomi2cm_baud_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_BAUD_reg(const void *const hw, hri_sercomi2cm_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_baud_reg_t hri_sercomi2cm_read_BAUD_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.BAUD.reg; +} + +static inline void hri_sercomspi_set_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg |= SERCOM_SPI_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_BAUD_bf(const void *const hw, + hri_sercomspi_baud_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp = (tmp & SERCOM_SPI_BAUD_BAUD(mask)) >> SERCOM_SPI_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t data) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp &= ~SERCOM_SPI_BAUD_BAUD_Msk; + tmp |= SERCOM_SPI_BAUD_BAUD(data); + ((Sercom *)hw)->SPI.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg &= ~SERCOM_SPI_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg ^= SERCOM_SPI_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_BAUD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp = (tmp & SERCOM_SPI_BAUD_BAUD_Msk) >> SERCOM_SPI_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_get_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_BAUD_reg(const void *const hw, hri_sercomspi_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_baud_reg_t hri_sercomspi_read_BAUD_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.BAUD.reg; +} + +static inline void hri_sercomusart_set_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_write_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRAC_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRACFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRAC_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_FRACFP_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRAC_FP_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP(mask)) >> SERCOM_USART_BAUD_FRAC_FP_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_FRACFP_FP_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP(mask)) >> SERCOM_USART_BAUD_FRACFP_FP_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_FRAC_FP_Msk; + tmp |= SERCOM_USART_BAUD_FRAC_FP(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_write_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_FRACFP_FP_Msk; + tmp |= SERCOM_USART_BAUD_FRACFP_FP(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRAC_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_FRACFP_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRAC_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRAC_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_FRACFP_FP_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_FRACFP_FP(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRAC_FP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRAC_FP_Msk) >> SERCOM_USART_BAUD_FRAC_FP_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_FRACFP_FP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_FRACFP_FP_Msk) >> SERCOM_USART_BAUD_FRACFP_FP_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_USARTFP_BAUD_bf(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD(mask)) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_write_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= ~SERCOM_USART_BAUD_BAUD_Msk; + tmp |= SERCOM_USART_BAUD_BAUD(data); + ((Sercom *)hw)->USART.BAUD.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_USARTFP_BAUD_bf(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= SERCOM_USART_BAUD_BAUD(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_USARTFP_BAUD_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp = (tmp & SERCOM_USART_BAUD_BAUD_Msk) >> SERCOM_USART_BAUD_BAUD_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_get_BAUD_reg(const void *const hw, + hri_sercomusart_baud_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.BAUD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_BAUD_reg(const void *const hw, hri_sercomusart_baud_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.BAUD.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_baud_reg_t hri_sercomusart_read_BAUD_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.BAUD.reg; +} + +static inline void hri_sercomusart_set_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg |= SERCOM_USART_RXPL_RXPL(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_RXPL_bf(const void *const hw, + hri_sercomusart_rxpl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp = (tmp & SERCOM_USART_RXPL_RXPL(mask)) >> SERCOM_USART_RXPL_RXPL_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t data) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp &= ~SERCOM_USART_RXPL_RXPL_Msk; + tmp |= SERCOM_USART_RXPL_RXPL(data); + ((Sercom *)hw)->USART.RXPL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg &= ~SERCOM_USART_RXPL_RXPL(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_RXPL_RXPL_bf(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg ^= SERCOM_USART_RXPL_RXPL(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_RXPL_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp = (tmp & SERCOM_USART_RXPL_RXPL_Msk) >> SERCOM_USART_RXPL_RXPL_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_get_RXPL_reg(const void *const hw, + hri_sercomusart_rxpl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.RXPL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_RXPL_reg(const void *const hw, hri_sercomusart_rxpl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.RXPL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_rxpl_reg_t hri_sercomusart_read_RXPL_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.RXPL.reg; +} + +static inline void hri_sercomi2cs_set_LENGTH_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg |= SERCOM_I2CS_LENGTH_LENEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_LENGTH_LENEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; + tmp = (tmp & SERCOM_I2CS_LENGTH_LENEN) >> SERCOM_I2CS_LENGTH_LENEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_LENGTH_LENEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; + tmp &= ~SERCOM_I2CS_LENGTH_LENEN; + tmp |= value << SERCOM_I2CS_LENGTH_LENEN_Pos; + ((Sercom *)hw)->I2CS.LENGTH.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_LENGTH_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg &= ~SERCOM_I2CS_LENGTH_LENEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_LENGTH_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg ^= SERCOM_I2CS_LENGTH_LENEN; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg |= SERCOM_I2CS_LENGTH_LEN(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_get_LENGTH_LEN_bf(const void *const hw, + hri_sercomi2cs_length_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; + tmp = (tmp & SERCOM_I2CS_LENGTH_LEN(mask)) >> SERCOM_I2CS_LENGTH_LEN_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; + tmp &= ~SERCOM_I2CS_LENGTH_LEN_Msk; + tmp |= SERCOM_I2CS_LENGTH_LEN(data); + ((Sercom *)hw)->I2CS.LENGTH.reg = tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg &= ~SERCOM_I2CS_LENGTH_LEN(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_LENGTH_LEN_bf(const void *const hw, hri_sercomi2cs_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg ^= SERCOM_I2CS_LENGTH_LEN(mask); + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_read_LENGTH_LEN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; + tmp = (tmp & SERCOM_I2CS_LENGTH_LEN_Msk) >> SERCOM_I2CS_LENGTH_LEN_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg |= mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_get_LENGTH_reg(const void *const hw, + hri_sercomi2cs_length_reg_t mask) +{ + uint16_t tmp; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->I2CS.LENGTH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg = data; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg &= ~mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_LENGTH_reg(const void *const hw, hri_sercomi2cs_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.LENGTH.reg ^= mask; + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_length_reg_t hri_sercomi2cs_read_LENGTH_reg(const void *const hw) +{ + hri_sercomi2cs_wait_for_sync(hw, SERCOM_I2CS_SYNCBUSY_MASK); + return ((Sercom *)hw)->I2CS.LENGTH.reg; +} + +static inline void hri_sercomspi_set_LENGTH_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg |= SERCOM_SPI_LENGTH_LENEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_LENGTH_LENEN_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->SPI.LENGTH.reg; + tmp = (tmp & SERCOM_SPI_LENGTH_LENEN) >> SERCOM_SPI_LENGTH_LENEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_LENGTH_LENEN_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.LENGTH.reg; + tmp &= ~SERCOM_SPI_LENGTH_LENEN; + tmp |= value << SERCOM_SPI_LENGTH_LENEN_Pos; + ((Sercom *)hw)->SPI.LENGTH.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_LENGTH_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg &= ~SERCOM_SPI_LENGTH_LENEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_LENGTH_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg ^= SERCOM_SPI_LENGTH_LENEN; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg |= SERCOM_SPI_LENGTH_LEN(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_length_reg_t hri_sercomspi_get_LENGTH_LEN_bf(const void *const hw, + hri_sercomspi_length_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->SPI.LENGTH.reg; + tmp = (tmp & SERCOM_SPI_LENGTH_LEN(mask)) >> SERCOM_SPI_LENGTH_LEN_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.LENGTH.reg; + tmp &= ~SERCOM_SPI_LENGTH_LEN_Msk; + tmp |= SERCOM_SPI_LENGTH_LEN(data); + ((Sercom *)hw)->SPI.LENGTH.reg = tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg &= ~SERCOM_SPI_LENGTH_LEN(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_LENGTH_LEN_bf(const void *const hw, hri_sercomspi_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg ^= SERCOM_SPI_LENGTH_LEN(mask); + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_length_reg_t hri_sercomspi_read_LENGTH_LEN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->SPI.LENGTH.reg; + tmp = (tmp & SERCOM_SPI_LENGTH_LEN_Msk) >> SERCOM_SPI_LENGTH_LEN_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg |= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_length_reg_t hri_sercomspi_get_LENGTH_reg(const void *const hw, + hri_sercomspi_length_reg_t mask) +{ + uint16_t tmp; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->SPI.LENGTH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg = data; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg &= ~mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_LENGTH_reg(const void *const hw, hri_sercomspi_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.LENGTH.reg ^= mask; + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_length_reg_t hri_sercomspi_read_LENGTH_reg(const void *const hw) +{ + hri_sercomspi_wait_for_sync(hw, SERCOM_SPI_SYNCBUSY_MASK); + return ((Sercom *)hw)->SPI.LENGTH.reg; +} + +static inline void hri_sercomusart_set_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg |= SERCOM_USART_LENGTH_LEN(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_length_reg_t hri_sercomusart_get_LENGTH_LEN_bf(const void *const hw, + hri_sercomusart_length_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.LENGTH.reg; + tmp = (tmp & SERCOM_USART_LENGTH_LEN(mask)) >> SERCOM_USART_LENGTH_LEN_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.LENGTH.reg; + tmp &= ~SERCOM_USART_LENGTH_LEN_Msk; + tmp |= SERCOM_USART_LENGTH_LEN(data); + ((Sercom *)hw)->USART.LENGTH.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg &= ~SERCOM_USART_LENGTH_LEN(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_LENGTH_LEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg ^= SERCOM_USART_LENGTH_LEN(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_length_reg_t hri_sercomusart_read_LENGTH_LEN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.LENGTH.reg; + tmp = (tmp & SERCOM_USART_LENGTH_LEN_Msk) >> SERCOM_USART_LENGTH_LEN_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg |= SERCOM_USART_LENGTH_LENEN(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_length_reg_t hri_sercomusart_get_LENGTH_LENEN_bf(const void *const hw, + hri_sercomusart_length_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.LENGTH.reg; + tmp = (tmp & SERCOM_USART_LENGTH_LENEN(mask)) >> SERCOM_USART_LENGTH_LENEN_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.LENGTH.reg; + tmp &= ~SERCOM_USART_LENGTH_LENEN_Msk; + tmp |= SERCOM_USART_LENGTH_LENEN(data); + ((Sercom *)hw)->USART.LENGTH.reg = tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg &= ~SERCOM_USART_LENGTH_LENEN(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_LENGTH_LENEN_bf(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg ^= SERCOM_USART_LENGTH_LENEN(mask); + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_length_reg_t hri_sercomusart_read_LENGTH_LENEN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.LENGTH.reg; + tmp = (tmp & SERCOM_USART_LENGTH_LENEN_Msk) >> SERCOM_USART_LENGTH_LENEN_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg |= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_length_reg_t hri_sercomusart_get_LENGTH_reg(const void *const hw, + hri_sercomusart_length_reg_t mask) +{ + uint16_t tmp; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + tmp = ((Sercom *)hw)->USART.LENGTH.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg = data; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg &= ~mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_LENGTH_reg(const void *const hw, hri_sercomusart_length_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.LENGTH.reg ^= mask; + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_length_reg_t hri_sercomusart_read_LENGTH_reg(const void *const hw) +{ + hri_sercomusart_wait_for_sync(hw, SERCOM_USART_SYNCBUSY_MASK); + return ((Sercom *)hw)->USART.LENGTH.reg; +} + +static inline void hri_sercomi2cm_set_ADDR_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LENEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_ADDR_LENEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_LENEN) >> SERCOM_I2CM_ADDR_LENEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_LENEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_LENEN; + tmp |= value << SERCOM_I2CM_ADDR_LENEN_Pos; + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LENEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_LENEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LENEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_ADDR_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_HS; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_ADDR_HS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_HS) >> SERCOM_I2CM_ADDR_HS_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_HS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_HS; + tmp |= value << SERCOM_I2CM_ADDR_HS_Pos; + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_HS; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_HS; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_TENBITEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_ADDR_TENBITEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_TENBITEN) >> SERCOM_I2CM_ADDR_TENBITEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_TENBITEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_TENBITEN; + tmp |= value << SERCOM_I2CM_ADDR_TENBITEN_Pos; + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_TENBITEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_TENBITEN; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_ADDR(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_ADDR_bf(const void *const hw, + hri_sercomi2cm_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_ADDR(mask)) >> SERCOM_I2CM_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_ADDR_Msk; + tmp |= SERCOM_I2CM_ADDR_ADDR(data); + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_ADDR(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_ADDR(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_ADDR_Msk) >> SERCOM_I2CM_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= SERCOM_I2CM_ADDR_LEN(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_LEN_bf(const void *const hw, + hri_sercomi2cm_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_LEN(mask)) >> SERCOM_I2CM_ADDR_LEN_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= ~SERCOM_I2CM_ADDR_LEN_Msk; + tmp |= SERCOM_I2CM_ADDR_LEN(data); + ((Sercom *)hw)->I2CM.ADDR.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~SERCOM_I2CM_ADDR_LEN(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_LEN_bf(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= SERCOM_I2CM_ADDR_LEN(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_LEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp = (tmp & SERCOM_I2CM_ADDR_LEN_Msk) >> SERCOM_I2CM_ADDR_LEN_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg |= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_get_ADDR_reg(const void *const hw, + hri_sercomi2cm_addr_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg = data; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg &= ~mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_ADDR_reg(const void *const hw, hri_sercomi2cm_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.ADDR.reg ^= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_addr_reg_t hri_sercomi2cm_read_ADDR_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return ((Sercom *)hw)->I2CM.ADDR.reg; +} + +static inline void hri_sercomi2cs_set_ADDR_GENCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_GENCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_ADDR_GENCEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_GENCEN) >> SERCOM_I2CS_ADDR_GENCEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_GENCEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_GENCEN; + tmp |= value << SERCOM_I2CS_ADDR_GENCEN_Pos; + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_GENCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_GENCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_GENCEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_GENCEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_ADDR_TENBITEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_TENBITEN) >> SERCOM_I2CS_ADDR_TENBITEN_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_TENBITEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_TENBITEN; + tmp |= value << SERCOM_I2CS_ADDR_TENBITEN_Pos; + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_TENBITEN_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_TENBITEN; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_set_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDR_bf(const void *const hw, + hri_sercomi2cs_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDR(mask)) >> SERCOM_I2CS_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_ADDR_Msk; + tmp |= SERCOM_I2CS_ADDR_ADDR(data); + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDR_Msk) >> SERCOM_I2CS_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= SERCOM_I2CS_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_ADDRMASK_bf(const void *const hw, + hri_sercomi2cs_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK(mask)) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= ~SERCOM_I2CS_ADDR_ADDRMASK_Msk; + tmp |= SERCOM_I2CS_ADDR_ADDRMASK(data); + ((Sercom *)hw)->I2CS.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~SERCOM_I2CS_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= SERCOM_I2CS_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_ADDRMASK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp = (tmp & SERCOM_I2CS_ADDR_ADDRMASK_Msk) >> SERCOM_I2CS_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_get_ADDR_reg(const void *const hw, + hri_sercomi2cs_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_ADDR_reg(const void *const hw, hri_sercomi2cs_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.ADDR.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_addr_reg_t hri_sercomi2cs_read_ADDR_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.ADDR.reg; +} + +static inline void hri_sercomspi_set_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDR_bf(const void *const hw, + hri_sercomspi_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDR(mask)) >> SERCOM_SPI_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp &= ~SERCOM_SPI_ADDR_ADDR_Msk; + tmp |= SERCOM_SPI_ADDR_ADDR(data); + ((Sercom *)hw)->SPI.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_ADDR_ADDR_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDR(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDR_Msk) >> SERCOM_SPI_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg |= SERCOM_SPI_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_ADDRMASK_bf(const void *const hw, + hri_sercomspi_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK(mask)) >> SERCOM_SPI_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp &= ~SERCOM_SPI_ADDR_ADDRMASK_Msk; + tmp |= SERCOM_SPI_ADDR_ADDRMASK(data); + ((Sercom *)hw)->SPI.ADDR.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg &= ~SERCOM_SPI_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_ADDR_ADDRMASK_bf(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg ^= SERCOM_SPI_ADDR_ADDRMASK(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_ADDRMASK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp = (tmp & SERCOM_SPI_ADDR_ADDRMASK_Msk) >> SERCOM_SPI_ADDR_ADDRMASK_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_get_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_ADDR_reg(const void *const hw, hri_sercomspi_addr_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.ADDR.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_addr_reg_t hri_sercomspi_read_ADDR_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.ADDR.reg; +} + +static inline void hri_sercomi2cm_set_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg |= SERCOM_I2CM_DATA_DATA(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_get_DATA_DATA_bf(const void *const hw, + hri_sercomi2cm_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp = (tmp & SERCOM_I2CM_DATA_DATA(mask)) >> SERCOM_I2CM_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp &= ~SERCOM_I2CM_DATA_DATA_Msk; + tmp |= SERCOM_I2CM_DATA_DATA(data); + ((Sercom *)hw)->I2CM.DATA.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg &= ~SERCOM_I2CM_DATA_DATA(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DATA_DATA_bf(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg ^= SERCOM_I2CM_DATA_DATA(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp = (tmp & SERCOM_I2CM_DATA_DATA_Msk) >> SERCOM_I2CM_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cm_set_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg |= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_get_DATA_reg(const void *const hw, + hri_sercomi2cm_data_reg_t mask) +{ + uint32_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg = data; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg &= ~mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DATA_reg(const void *const hw, hri_sercomi2cm_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DATA.reg ^= mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_data_reg_t hri_sercomi2cm_read_DATA_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return ((Sercom *)hw)->I2CM.DATA.reg; +} + +static inline void hri_sercomi2cs_set_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg |= SERCOM_I2CS_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_get_DATA_DATA_bf(const void *const hw, + hri_sercomi2cs_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp = (tmp & SERCOM_I2CS_DATA_DATA(mask)) >> SERCOM_I2CS_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_write_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp &= ~SERCOM_I2CS_DATA_DATA_Msk; + tmp |= SERCOM_I2CS_DATA_DATA(data); + ((Sercom *)hw)->I2CS.DATA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg &= ~SERCOM_I2CS_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_DATA_DATA_bf(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg ^= SERCOM_I2CS_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp = (tmp & SERCOM_I2CS_DATA_DATA_Msk) >> SERCOM_I2CS_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomi2cs_set_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_get_DATA_reg(const void *const hw, + hri_sercomi2cs_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->I2CS.DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_write_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_clear_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cs_toggle_DATA_reg(const void *const hw, hri_sercomi2cs_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.DATA.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_data_reg_t hri_sercomi2cs_read_DATA_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.DATA.reg; +} + +static inline void hri_sercomspi_set_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg |= SERCOM_SPI_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_get_DATA_DATA_bf(const void *const hw, + hri_sercomspi_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.DATA.reg; + tmp = (tmp & SERCOM_SPI_DATA_DATA(mask)) >> SERCOM_SPI_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomspi_write_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.DATA.reg; + tmp &= ~SERCOM_SPI_DATA_DATA_Msk; + tmp |= SERCOM_SPI_DATA_DATA(data); + ((Sercom *)hw)->SPI.DATA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg &= ~SERCOM_SPI_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DATA_DATA_bf(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg ^= SERCOM_SPI_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.DATA.reg; + tmp = (tmp & SERCOM_SPI_DATA_DATA_Msk) >> SERCOM_SPI_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomspi_set_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_get_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->SPI.DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DATA_reg(const void *const hw, hri_sercomspi_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DATA.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_data_reg_t hri_sercomspi_read_DATA_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.DATA.reg; +} + +static inline void hri_sercomusart_set_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg |= SERCOM_USART_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_get_DATA_DATA_bf(const void *const hw, + hri_sercomusart_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp = (tmp & SERCOM_USART_DATA_DATA(mask)) >> SERCOM_USART_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomusart_write_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t data) +{ + uint32_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp &= ~SERCOM_USART_DATA_DATA_Msk; + tmp |= SERCOM_USART_DATA_DATA(data); + ((Sercom *)hw)->USART.DATA.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg &= ~SERCOM_USART_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DATA_DATA_bf(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg ^= SERCOM_USART_DATA_DATA(mask); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_DATA_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp = (tmp & SERCOM_USART_DATA_DATA_Msk) >> SERCOM_USART_DATA_DATA_Pos; + return tmp; +} + +static inline void hri_sercomusart_set_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_get_DATA_reg(const void *const hw, + hri_sercomusart_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Sercom *)hw)->USART.DATA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DATA_reg(const void *const hw, hri_sercomusart_data_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DATA.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_data_reg_t hri_sercomusart_read_DATA_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.DATA.reg; +} + +static inline void hri_sercomi2cm_set_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg |= SERCOM_I2CM_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; + tmp = (tmp & SERCOM_I2CM_DBGCTRL_DBGSTOP) >> SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_sercomi2cm_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; + tmp &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP; + tmp |= value << SERCOM_I2CM_DBGCTRL_DBGSTOP_Pos; + ((Sercom *)hw)->I2CM.DBGCTRL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~SERCOM_I2CM_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg ^= SERCOM_I2CM_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_get_DBGCTRL_reg(const void *const hw, + hri_sercomi2cm_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->I2CM.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_write_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_DBGCTRL_reg(const void *const hw, hri_sercomi2cm_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.DBGCTRL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_dbgctrl_reg_t hri_sercomi2cm_read_DBGCTRL_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CM.DBGCTRL.reg; +} + +static inline void hri_sercomspi_set_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg |= SERCOM_SPI_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; + tmp = (tmp & SERCOM_SPI_DBGCTRL_DBGSTOP) >> SERCOM_SPI_DBGCTRL_DBGSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_sercomspi_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; + tmp &= ~SERCOM_SPI_DBGCTRL_DBGSTOP; + tmp |= value << SERCOM_SPI_DBGCTRL_DBGSTOP_Pos; + ((Sercom *)hw)->SPI.DBGCTRL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg &= ~SERCOM_SPI_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg ^= SERCOM_SPI_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_set_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_get_DBGCTRL_reg(const void *const hw, + hri_sercomspi_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->SPI.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_write_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_clear_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomspi_toggle_DBGCTRL_reg(const void *const hw, hri_sercomspi_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.DBGCTRL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_dbgctrl_reg_t hri_sercomspi_read_DBGCTRL_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.DBGCTRL.reg; +} + +static inline void hri_sercomusart_set_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg |= SERCOM_USART_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; + tmp = (tmp & SERCOM_USART_DBGCTRL_DBGSTOP) >> SERCOM_USART_DBGCTRL_DBGSTOP_Pos; + return (bool)tmp; +} + +static inline void hri_sercomusart_write_DBGCTRL_DBGSTOP_bit(const void *const hw, bool value) +{ + uint8_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; + tmp &= ~SERCOM_USART_DBGCTRL_DBGSTOP; + tmp |= value << SERCOM_USART_DBGCTRL_DBGSTOP_Pos; + ((Sercom *)hw)->USART.DBGCTRL.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg &= ~SERCOM_USART_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DBGCTRL_DBGSTOP_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg ^= SERCOM_USART_DBGCTRL_DBGSTOP; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_set_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg |= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_get_DBGCTRL_reg(const void *const hw, + hri_sercomusart_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Sercom *)hw)->USART.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_write_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t data) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg = data; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_clear_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg &= ~mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomusart_toggle_DBGCTRL_reg(const void *const hw, hri_sercomusart_dbgctrl_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.DBGCTRL.reg ^= mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_dbgctrl_reg_t hri_sercomusart_read_DBGCTRL_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.DBGCTRL.reg; +} + +static inline bool hri_sercomi2cs_get_STATUS_BUSERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_BUSERR) >> SERCOM_I2CS_STATUS_BUSERR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_COLL_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_COLL) >> SERCOM_I2CS_STATUS_COLL_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_COLL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_COLL; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_RXNACK_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_RXNACK) >> SERCOM_I2CS_STATUS_RXNACK_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_DIR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_DIR) >> SERCOM_I2CS_STATUS_DIR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_DIR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_DIR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_SR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SR) >> SERCOM_I2CS_STATUS_SR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_SR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_LOWTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_LOWTOUT) >> SERCOM_I2CS_STATUS_LOWTOUT_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_CLKHOLD_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_CLKHOLD) >> SERCOM_I2CS_STATUS_CLKHOLD_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_SEXTTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_SEXTTOUT) >> SERCOM_I2CS_STATUS_SEXTTOUT_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_HS_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_HS) >> SERCOM_I2CS_STATUS_HS_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_HS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_HS; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cs_get_STATUS_LENERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CS.STATUS.reg & SERCOM_I2CS_STATUS_LENERR) >> SERCOM_I2CS_STATUS_LENERR_Pos; +} + +static inline void hri_sercomi2cs_clear_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = SERCOM_I2CS_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_get_STATUS_reg(const void *const hw, + hri_sercomi2cs_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->I2CS.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cs_clear_STATUS_reg(const void *const hw, hri_sercomi2cs_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CS.STATUS.reg = mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cs_status_reg_t hri_sercomi2cs_read_STATUS_reg(const void *const hw) +{ + return ((Sercom *)hw)->I2CS.STATUS.reg; +} + +static inline bool hri_sercomspi_get_STATUS_BUFOVF_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.STATUS.reg & SERCOM_SPI_STATUS_BUFOVF) >> SERCOM_SPI_STATUS_BUFOVF_Pos; +} + +static inline void hri_sercomspi_clear_STATUS_BUFOVF_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.STATUS.reg = SERCOM_SPI_STATUS_BUFOVF; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomspi_get_STATUS_LENERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->SPI.STATUS.reg & SERCOM_SPI_STATUS_LENERR) >> SERCOM_SPI_STATUS_LENERR_Pos; +} + +static inline void hri_sercomspi_clear_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.STATUS.reg = SERCOM_SPI_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_status_reg_t hri_sercomspi_get_STATUS_reg(const void *const hw, + hri_sercomspi_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->SPI.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomspi_clear_STATUS_reg(const void *const hw, hri_sercomspi_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->SPI.STATUS.reg = mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomspi_status_reg_t hri_sercomspi_read_STATUS_reg(const void *const hw) +{ + return ((Sercom *)hw)->SPI.STATUS.reg; +} + +static inline bool hri_sercomusart_get_STATUS_PERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_PERR) >> SERCOM_USART_STATUS_PERR_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_PERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_PERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_FERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_FERR) >> SERCOM_USART_STATUS_FERR_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_FERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_FERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_BUFOVF_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_BUFOVF) >> SERCOM_USART_STATUS_BUFOVF_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_BUFOVF_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_BUFOVF; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_CTS_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_CTS) >> SERCOM_USART_STATUS_CTS_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_CTS_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_CTS; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_ISF_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ISF) >> SERCOM_USART_STATUS_ISF_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_ISF_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ISF; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_COLL_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_COLL) >> SERCOM_USART_STATUS_COLL_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_COLL_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_COLL; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_TXE_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_TXE) >> SERCOM_USART_STATUS_TXE_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_TXE_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_TXE; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomusart_get_STATUS_ITER_bit(const void *const hw) +{ + return (((Sercom *)hw)->USART.STATUS.reg & SERCOM_USART_STATUS_ITER) >> SERCOM_USART_STATUS_ITER_Pos; +} + +static inline void hri_sercomusart_clear_STATUS_ITER_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = SERCOM_USART_STATUS_ITER; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_status_reg_t hri_sercomusart_get_STATUS_reg(const void *const hw, + hri_sercomusart_status_reg_t mask) +{ + uint16_t tmp; + tmp = ((Sercom *)hw)->USART.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomusart_clear_STATUS_reg(const void *const hw, hri_sercomusart_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->USART.STATUS.reg = mask; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomusart_status_reg_t hri_sercomusart_read_STATUS_reg(const void *const hw) +{ + return ((Sercom *)hw)->USART.STATUS.reg; +} + +static inline void hri_sercomi2cm_set_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_BUSERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSERR) >> SERCOM_I2CM_STATUS_BUSERR_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_BUSERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_BUSERR; + tmp |= value << SERCOM_I2CM_STATUS_BUSERR_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_BUSERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_ARBLOST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_ARBLOST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_ARBLOST_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_ARBLOST) >> SERCOM_I2CM_STATUS_ARBLOST_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_ARBLOST_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_ARBLOST; + tmp |= value << SERCOM_I2CM_STATUS_ARBLOST_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_ARBLOST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_ARBLOST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_ARBLOST_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_ARBLOST; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_RXNACK_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_RXNACK) >> SERCOM_I2CM_STATUS_RXNACK_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_RXNACK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_RXNACK; + tmp |= value << SERCOM_I2CM_STATUS_RXNACK_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_RXNACK_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_RXNACK; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_LOWTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LOWTOUT) >> SERCOM_I2CM_STATUS_LOWTOUT_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_LOWTOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_LOWTOUT; + tmp |= value << SERCOM_I2CM_STATUS_LOWTOUT_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_LOWTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LOWTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_CLKHOLD_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_CLKHOLD) >> SERCOM_I2CM_STATUS_CLKHOLD_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_CLKHOLD_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_CLKHOLD; + tmp |= value << SERCOM_I2CM_STATUS_CLKHOLD_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_CLKHOLD_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_CLKHOLD; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_MEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_MEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_MEXTTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_MEXTTOUT) >> SERCOM_I2CM_STATUS_MEXTTOUT_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_MEXTTOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_MEXTTOUT; + tmp |= value << SERCOM_I2CM_STATUS_MEXTTOUT_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_MEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_MEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_MEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_MEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_SEXTTOUT_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_SEXTTOUT) >> SERCOM_I2CM_STATUS_SEXTTOUT_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_SEXTTOUT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_SEXTTOUT; + tmp |= value << SERCOM_I2CM_STATUS_SEXTTOUT_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_SEXTTOUT_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_SEXTTOUT; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_set_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_sercomi2cm_get_STATUS_LENERR_bit(const void *const hw) +{ + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_LENERR) >> SERCOM_I2CM_STATUS_LENERR_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_LENERR_bit(const void *const hw, bool value) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_LENERR; + tmp |= value << SERCOM_I2CM_STATUS_LENERR_Pos; + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_LENERR_bit(const void *const hw) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_LENERR; + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_BUSSTATE_bf(const void *const hw, + hri_sercomi2cm_status_reg_t mask) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE(mask)) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos; +} + +static inline void hri_sercomi2cm_set_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg |= SERCOM_I2CM_STATUS_BUSSTATE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_BUSSTATE_bf(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return (((Sercom *)hw)->I2CM.STATUS.reg & SERCOM_I2CM_STATUS_BUSSTATE_Msk) >> SERCOM_I2CM_STATUS_BUSSTATE_Pos; +} + +static inline void hri_sercomi2cm_write_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t data) +{ + uint16_t tmp; + SERCOM_CRITICAL_SECTION_ENTER(); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= ~SERCOM_I2CM_STATUS_BUSSTATE_Msk; + tmp |= SERCOM_I2CM_STATUS_BUSSTATE(data); + ((Sercom *)hw)->I2CM.STATUS.reg = tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_toggle_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg ^= SERCOM_I2CM_STATUS_BUSSTATE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_sercomi2cm_clear_STATUS_BUSSTATE_bf(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = SERCOM_I2CM_STATUS_BUSSTATE(mask); + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_get_STATUS_reg(const void *const hw, + hri_sercomi2cm_status_reg_t mask) +{ + uint16_t tmp; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + tmp = ((Sercom *)hw)->I2CM.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_sercomi2cm_set_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + ((Sercom *)hw)->I2CM.STATUS.reg |= mask; +} + +static inline hri_sercomi2cm_status_reg_t hri_sercomi2cm_read_STATUS_reg(const void *const hw) +{ + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + return ((Sercom *)hw)->I2CM.STATUS.reg; +} + +static inline void hri_sercomi2cm_write_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t data) +{ + ((Sercom *)hw)->I2CM.STATUS.reg = data; +} + +static inline void hri_sercomi2cm_toggle_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + ((Sercom *)hw)->I2CM.STATUS.reg ^= mask; +} + +static inline void hri_sercomi2cm_clear_STATUS_reg(const void *const hw, hri_sercomi2cm_status_reg_t mask) +{ + SERCOM_CRITICAL_SECTION_ENTER(); + ((Sercom *)hw)->I2CM.STATUS.reg = mask; + hri_sercomi2cm_wait_for_sync(hw, SERCOM_I2CM_SYNCBUSY_SYSOP); + SERCOM_CRITICAL_SECTION_LEAVE(); +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_sercomusart_set_BAUD_FRAC_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b) +#define hri_sercomusart_get_BAUD_FRAC_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b) +#define hri_sercomusart_write_BAUD_FRAC_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b) +#define hri_sercomusart_clear_BAUD_FRAC_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b) +#define hri_sercomusart_toggle_BAUD_FRAC_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b) +#define hri_sercomusart_read_BAUD_FRAC_reg(a) hri_sercomusart_read_BAUD_reg(a) +#define hri_sercomusart_set_BAUD_FRACFP_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b) +#define hri_sercomusart_get_BAUD_FRACFP_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b) +#define hri_sercomusart_write_BAUD_FRACFP_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b) +#define hri_sercomusart_clear_BAUD_FRACFP_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b) +#define hri_sercomusart_toggle_BAUD_FRACFP_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b) +#define hri_sercomusart_read_BAUD_FRACFP_reg(a) hri_sercomusart_read_BAUD_reg(a) +#define hri_sercomusart_set_BAUD_USARTFP_reg(a, b) hri_sercomusart_set_BAUD_reg(a, b) +#define hri_sercomusart_get_BAUD_USARTFP_reg(a, b) hri_sercomusart_get_BAUD_reg(a, b) +#define hri_sercomusart_write_BAUD_USARTFP_reg(a, b) hri_sercomusart_write_BAUD_reg(a, b) +#define hri_sercomusart_clear_BAUD_USARTFP_reg(a, b) hri_sercomusart_clear_BAUD_reg(a, b) +#define hri_sercomusart_toggle_BAUD_USARTFP_reg(a, b) hri_sercomusart_toggle_BAUD_reg(a, b) +#define hri_sercomusart_read_BAUD_USARTFP_reg(a) hri_sercomusart_read_BAUD_reg(a) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SERCOM_E54_H_INCLUDED */ +#endif /* _SAME54_SERCOM_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_supc_e54.h b/software/firmware/oracle_same54n19a/hri/hri_supc_e54.h new file mode 100644 index 00000000..501c36f5 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_supc_e54.h @@ -0,0 +1,1769 @@ +/** + * \file + * + * \brief SAM SUPC + * + * Copyright (c) 2016-2019 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_SUPC_COMPONENT_ +#ifndef _HRI_SUPC_E54_H_INCLUDED_ +#define _HRI_SUPC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_SUPC_CRITICAL_SECTIONS) +#define SUPC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define SUPC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define SUPC_CRITICAL_SECTION_ENTER() +#define SUPC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_supc_bbps_reg_t; +typedef uint32_t hri_supc_bkin_reg_t; +typedef uint32_t hri_supc_bkout_reg_t; +typedef uint32_t hri_supc_bod33_reg_t; +typedef uint32_t hri_supc_intenset_reg_t; +typedef uint32_t hri_supc_intflag_reg_t; +typedef uint32_t hri_supc_status_reg_t; +typedef uint32_t hri_supc_vref_reg_t; +typedef uint32_t hri_supc_vreg_reg_t; + +static inline bool hri_supc_get_INTFLAG_BOD33RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_BOD33RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY; +} + +static inline bool hri_supc_get_INTFLAG_BOD33DET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos; +} + +static inline void hri_supc_clear_INTFLAG_BOD33DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET; +} + +static inline bool hri_supc_get_INTFLAG_B33SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_B33SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY; +} + +static inline bool hri_supc_get_INTFLAG_VREGRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_VREGRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY; +} + +static inline bool hri_supc_get_INTFLAG_VCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos; +} + +static inline void hri_supc_clear_INTFLAG_VCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY; +} + +static inline bool hri_supc_get_interrupt_BOD33RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33RDY) >> SUPC_INTFLAG_BOD33RDY_Pos; +} + +static inline void hri_supc_clear_interrupt_BOD33RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33RDY; +} + +static inline bool hri_supc_get_interrupt_BOD33DET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_BOD33DET) >> SUPC_INTFLAG_BOD33DET_Pos; +} + +static inline void hri_supc_clear_interrupt_BOD33DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_BOD33DET; +} + +static inline bool hri_supc_get_interrupt_B33SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_B33SRDY) >> SUPC_INTFLAG_B33SRDY_Pos; +} + +static inline void hri_supc_clear_interrupt_B33SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_B33SRDY; +} + +static inline bool hri_supc_get_interrupt_VREGRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VREGRDY) >> SUPC_INTFLAG_VREGRDY_Pos; +} + +static inline void hri_supc_clear_interrupt_VREGRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VREGRDY; +} + +static inline bool hri_supc_get_interrupt_VCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTFLAG.reg & SUPC_INTFLAG_VCORERDY) >> SUPC_INTFLAG_VCORERDY_Pos; +} + +static inline void hri_supc_clear_interrupt_VCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTFLAG.reg = SUPC_INTFLAG_VCORERDY; +} + +static inline hri_supc_intflag_reg_t hri_supc_get_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_intflag_reg_t hri_supc_read_INTFLAG_reg(const void *const hw) +{ + return ((Supc *)hw)->INTFLAG.reg; +} + +static inline void hri_supc_clear_INTFLAG_reg(const void *const hw, hri_supc_intflag_reg_t mask) +{ + ((Supc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_supc_set_INTEN_BOD33RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY; +} + +static inline bool hri_supc_get_INTEN_BOD33RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33RDY) >> SUPC_INTENSET_BOD33RDY_Pos; +} + +static inline void hri_supc_write_INTEN_BOD33RDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33RDY; + } +} + +static inline void hri_supc_clear_INTEN_BOD33RDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33RDY; +} + +static inline void hri_supc_set_INTEN_BOD33DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET; +} + +static inline bool hri_supc_get_INTEN_BOD33DET_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_BOD33DET) >> SUPC_INTENSET_BOD33DET_Pos; +} + +static inline void hri_supc_write_INTEN_BOD33DET_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_BOD33DET; + } +} + +static inline void hri_supc_clear_INTEN_BOD33DET_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_BOD33DET; +} + +static inline void hri_supc_set_INTEN_B33SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY; +} + +static inline bool hri_supc_get_INTEN_B33SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_B33SRDY) >> SUPC_INTENSET_B33SRDY_Pos; +} + +static inline void hri_supc_write_INTEN_B33SRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_B33SRDY; + } +} + +static inline void hri_supc_clear_INTEN_B33SRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_B33SRDY; +} + +static inline void hri_supc_set_INTEN_VREGRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY; +} + +static inline bool hri_supc_get_INTEN_VREGRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VREGRDY) >> SUPC_INTENSET_VREGRDY_Pos; +} + +static inline void hri_supc_write_INTEN_VREGRDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VREGRDY; + } +} + +static inline void hri_supc_clear_INTEN_VREGRDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VREGRDY; +} + +static inline void hri_supc_set_INTEN_VCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY; +} + +static inline bool hri_supc_get_INTEN_VCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->INTENSET.reg & SUPC_INTENSET_VCORERDY) >> SUPC_INTENSET_VCORERDY_Pos; +} + +static inline void hri_supc_write_INTEN_VCORERDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY; + } else { + ((Supc *)hw)->INTENSET.reg = SUPC_INTENSET_VCORERDY; + } +} + +static inline void hri_supc_clear_INTEN_VCORERDY_bit(const void *const hw) +{ + ((Supc *)hw)->INTENCLR.reg = SUPC_INTENSET_VCORERDY; +} + +static inline void hri_supc_set_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) +{ + ((Supc *)hw)->INTENSET.reg = mask; +} + +static inline hri_supc_intenset_reg_t hri_supc_get_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_intenset_reg_t hri_supc_read_INTEN_reg(const void *const hw) +{ + return ((Supc *)hw)->INTENSET.reg; +} + +static inline void hri_supc_write_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t data) +{ + ((Supc *)hw)->INTENSET.reg = data; + ((Supc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_supc_clear_INTEN_reg(const void *const hw, hri_supc_intenset_reg_t mask) +{ + ((Supc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_supc_get_STATUS_BOD33RDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33RDY) >> SUPC_STATUS_BOD33RDY_Pos; +} + +static inline bool hri_supc_get_STATUS_BOD33DET_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_BOD33DET) >> SUPC_STATUS_BOD33DET_Pos; +} + +static inline bool hri_supc_get_STATUS_B33SRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_B33SRDY) >> SUPC_STATUS_B33SRDY_Pos; +} + +static inline bool hri_supc_get_STATUS_VREGRDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VREGRDY) >> SUPC_STATUS_VREGRDY_Pos; +} + +static inline bool hri_supc_get_STATUS_VCORERDY_bit(const void *const hw) +{ + return (((Supc *)hw)->STATUS.reg & SUPC_STATUS_VCORERDY) >> SUPC_STATUS_VCORERDY_Pos; +} + +static inline hri_supc_status_reg_t hri_supc_get_STATUS_reg(const void *const hw, hri_supc_status_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_status_reg_t hri_supc_read_STATUS_reg(const void *const hw) +{ + return ((Supc *)hw)->STATUS.reg; +} + +static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_BKIN_bf(const void *const hw, hri_supc_bkin_reg_t mask) +{ + return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN(mask)) >> SUPC_BKIN_BKIN_Pos; +} + +static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_BKIN_bf(const void *const hw) +{ + return (((Supc *)hw)->BKIN.reg & SUPC_BKIN_BKIN_Msk) >> SUPC_BKIN_BKIN_Pos; +} + +static inline hri_supc_bkin_reg_t hri_supc_get_BKIN_reg(const void *const hw, hri_supc_bkin_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKIN.reg; + tmp &= mask; + return tmp; +} + +static inline hri_supc_bkin_reg_t hri_supc_read_BKIN_reg(const void *const hw) +{ + return ((Supc *)hw)->BKIN.reg; +} + +static inline void hri_supc_set_BOD33_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_ENABLE) >> SUPC_BOD33_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_ENABLE; + tmp |= value << SUPC_BOD33_ENABLE_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_STDBYCFG_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_STDBYCFG) >> SUPC_BOD33_STDBYCFG_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_STDBYCFG_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_STDBYCFG; + tmp |= value << SUPC_BOD33_STDBYCFG_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_STDBYCFG_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_STDBYCFG; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_RUNSTDBY) >> SUPC_BOD33_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_RUNSTDBY; + tmp |= value << SUPC_BOD33_RUNSTDBY_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_RUNHIB_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNHIB; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_RUNHIB_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_RUNHIB) >> SUPC_BOD33_RUNHIB_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_RUNHIB_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_RUNHIB; + tmp |= value << SUPC_BOD33_RUNHIB_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_RUNHIB_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNHIB; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_RUNHIB_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNHIB; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BOD33_RUNBKUP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_RUNBKUP) >> SUPC_BOD33_RUNBKUP_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BOD33_RUNBKUP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_RUNBKUP; + tmp |= value << SUPC_BOD33_RUNBKUP_Pos; + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_ACTION(mask)) >> SUPC_BOD33_ACTION_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_ACTION_Msk; + tmp |= SUPC_BOD33_ACTION(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_ACTION_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_ACTION(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_ACTION_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_ACTION_Msk) >> SUPC_BOD33_ACTION_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_HYST(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_HYST(mask)) >> SUPC_BOD33_HYST_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_HYST_Msk; + tmp |= SUPC_BOD33_HYST(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_HYST(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_HYST_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_HYST(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_HYST_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_HYST_Msk) >> SUPC_BOD33_HYST_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_PSEL(mask)) >> SUPC_BOD33_PSEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_PSEL_Msk; + tmp |= SUPC_BOD33_PSEL(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_PSEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_PSEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_PSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_PSEL_Msk) >> SUPC_BOD33_PSEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_LEVEL(mask)) >> SUPC_BOD33_LEVEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_LEVEL_Msk; + tmp |= SUPC_BOD33_LEVEL(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_LEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_LEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_LEVEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_LEVEL_Msk) >> SUPC_BOD33_LEVEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= SUPC_BOD33_VBATLEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_VBATLEVEL(mask)) >> SUPC_BOD33_VBATLEVEL_Pos; + return tmp; +} + +static inline void hri_supc_write_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= ~SUPC_BOD33_VBATLEVEL_Msk; + tmp |= SUPC_BOD33_VBATLEVEL(data); + ((Supc *)hw)->BOD33.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~SUPC_BOD33_VBATLEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_VBATLEVEL_bf(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= SUPC_BOD33_VBATLEVEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_VBATLEVEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp = (tmp & SUPC_BOD33_VBATLEVEL_Msk) >> SUPC_BOD33_VBATLEVEL_Pos; + return tmp; +} + +static inline void hri_supc_set_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_get_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BOD33.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BOD33_reg(const void *const hw, hri_supc_bod33_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BOD33.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bod33_reg_t hri_supc_read_BOD33_reg(const void *const hw) +{ + return ((Supc *)hw)->BOD33.reg; +} + +static inline void hri_supc_set_VREG_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREG_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_ENABLE) >> SUPC_VREG_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREG_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_ENABLE; + tmp |= value << SUPC_VREG_ENABLE_Pos; + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_ENABLE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_ENABLE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREG_SEL_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_SEL; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREG_SEL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_SEL) >> SUPC_VREG_SEL_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREG_SEL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_SEL; + tmp |= value << SUPC_VREG_SEL_Pos; + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_SEL_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_SEL; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_SEL_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_SEL; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREG_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREG_RUNBKUP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_RUNBKUP) >> SUPC_VREG_RUNBKUP_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREG_RUNBKUP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_RUNBKUP; + tmp |= value << SUPC_VREG_RUNBKUP_Pos; + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_RUNBKUP_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_RUNBKUP; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREG_VSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_VSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREG_VSEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_VSEN) >> SUPC_VREG_VSEN_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREG_VSEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_VSEN; + tmp |= value << SUPC_VREG_VSEN_Pos; + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_VSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_VSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= SUPC_VREG_VSPER(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_get_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_VSPER(mask)) >> SUPC_VREG_VSPER_Pos; + return tmp; +} + +static inline void hri_supc_write_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREG.reg; + tmp &= ~SUPC_VREG_VSPER_Msk; + tmp |= SUPC_VREG_VSPER(data); + ((Supc *)hw)->VREG.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~SUPC_VREG_VSPER(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_VSPER_bf(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= SUPC_VREG_VSPER(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_read_VREG_VSPER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp = (tmp & SUPC_VREG_VSPER_Msk) >> SUPC_VREG_VSPER_Pos; + return tmp; +} + +static inline void hri_supc_set_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_get_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_VREG_reg(const void *const hw, hri_supc_vreg_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREG_reg(const void *const hw, hri_supc_vreg_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREG.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vreg_reg_t hri_supc_read_VREG_reg(const void *const hw) +{ + return ((Supc *)hw)->VREG.reg; +} + +static inline void hri_supc_set_VREF_TSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_TSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_TSEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_TSEN) >> SUPC_VREF_TSEN_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_TSEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_TSEN; + tmp |= value << SUPC_VREF_TSEN_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_TSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_TSEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_VREFOE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_VREFOE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_VREFOE_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_VREFOE) >> SUPC_VREF_VREFOE_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_VREFOE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_VREFOE; + tmp |= value << SUPC_VREF_VREFOE_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_VREFOE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_VREFOE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_VREFOE_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_VREFOE; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_TSSEL_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_TSSEL; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_TSSEL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_TSSEL) >> SUPC_VREF_TSSEL_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_TSSEL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_TSSEL; + tmp |= value << SUPC_VREF_TSSEL_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_TSSEL_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_TSSEL; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_TSSEL_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_TSSEL; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_RUNSTDBY) >> SUPC_VREF_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_RUNSTDBY; + tmp |= value << SUPC_VREF_RUNSTDBY_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_RUNSTDBY_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_RUNSTDBY; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_ONDEMAND_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_ONDEMAND; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_VREF_ONDEMAND_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_ONDEMAND) >> SUPC_VREF_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_VREF_ONDEMAND_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_ONDEMAND; + tmp |= value << SUPC_VREF_ONDEMAND_Pos; + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_ONDEMAND_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_ONDEMAND; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_ONDEMAND_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_ONDEMAND; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= SUPC_VREF_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_get_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_SEL(mask)) >> SUPC_VREF_SEL_Pos; + return tmp; +} + +static inline void hri_supc_write_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->VREF.reg; + tmp &= ~SUPC_VREF_SEL_Msk; + tmp |= SUPC_VREF_SEL(data); + ((Supc *)hw)->VREF.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~SUPC_VREF_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_SEL_bf(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= SUPC_VREF_SEL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_read_VREF_SEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp = (tmp & SUPC_VREF_SEL_Msk) >> SUPC_VREF_SEL_Pos; + return tmp; +} + +static inline void hri_supc_set_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_get_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->VREF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_VREF_reg(const void *const hw, hri_supc_vref_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_VREF_reg(const void *const hw, hri_supc_vref_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->VREF.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_vref_reg_t hri_supc_read_VREF_reg(const void *const hw) +{ + return ((Supc *)hw)->VREF.reg; +} + +static inline void hri_supc_set_BBPS_CONF_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg |= SUPC_BBPS_CONF; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BBPS_CONF_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BBPS.reg; + tmp = (tmp & SUPC_BBPS_CONF) >> SUPC_BBPS_CONF_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BBPS_CONF_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BBPS.reg; + tmp &= ~SUPC_BBPS_CONF; + tmp |= value << SUPC_BBPS_CONF_Pos; + ((Supc *)hw)->BBPS.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BBPS_CONF_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_CONF; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BBPS_CONF_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_CONF; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BBPS_WAKEEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg |= SUPC_BBPS_WAKEEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_supc_get_BBPS_WAKEEN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BBPS.reg; + tmp = (tmp & SUPC_BBPS_WAKEEN) >> SUPC_BBPS_WAKEEN_Pos; + return (bool)tmp; +} + +static inline void hri_supc_write_BBPS_WAKEEN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BBPS.reg; + tmp &= ~SUPC_BBPS_WAKEEN; + tmp |= value << SUPC_BBPS_WAKEEN_Pos; + ((Supc *)hw)->BBPS.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BBPS_WAKEEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg &= ~SUPC_BBPS_WAKEEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BBPS_WAKEEN_bit(const void *const hw) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg ^= SUPC_BBPS_WAKEEN; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_set_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bbps_reg_t hri_supc_get_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BBPS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BBPS_reg(const void *const hw, hri_supc_bbps_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BBPS.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bbps_reg_t hri_supc_read_BBPS_reg(const void *const hw) +{ + return ((Supc *)hw)->BBPS.reg; +} + +static inline void hri_supc_set_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_EN(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_EN(mask)) >> SUPC_BKOUT_EN_Pos; + return tmp; +} + +static inline void hri_supc_write_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= ~SUPC_BKOUT_EN_Msk; + tmp |= SUPC_BKOUT_EN(data); + ((Supc *)hw)->BKOUT.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_EN(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_EN_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_EN(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_EN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_EN_Msk) >> SUPC_BKOUT_EN_Pos; + return tmp; +} + +static inline void hri_supc_set_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_CLR(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_CLR(mask)) >> SUPC_BKOUT_CLR_Pos; + return tmp; +} + +static inline void hri_supc_write_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= ~SUPC_BKOUT_CLR_Msk; + tmp |= SUPC_BKOUT_CLR(data); + ((Supc *)hw)->BKOUT.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_CLR(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_CLR_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_CLR(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_CLR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_CLR_Msk) >> SUPC_BKOUT_CLR_Pos; + return tmp; +} + +static inline void hri_supc_set_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_SET(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_SET(mask)) >> SUPC_BKOUT_SET_Pos; + return tmp; +} + +static inline void hri_supc_write_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= ~SUPC_BKOUT_SET_Msk; + tmp |= SUPC_BKOUT_SET(data); + ((Supc *)hw)->BKOUT.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_SET(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_SET_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_SET(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_SET_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_SET_Msk) >> SUPC_BKOUT_SET_Pos; + return tmp; +} + +static inline void hri_supc_set_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= SUPC_BKOUT_RTCTGL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_RTCTGL(mask)) >> SUPC_BKOUT_RTCTGL_Pos; + return tmp; +} + +static inline void hri_supc_write_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t data) +{ + uint32_t tmp; + SUPC_CRITICAL_SECTION_ENTER(); + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= ~SUPC_BKOUT_RTCTGL_Msk; + tmp |= SUPC_BKOUT_RTCTGL(data); + ((Supc *)hw)->BKOUT.reg = tmp; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~SUPC_BKOUT_RTCTGL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_RTCTGL_bf(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= SUPC_BKOUT_RTCTGL(mask); + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_RTCTGL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp = (tmp & SUPC_BKOUT_RTCTGL_Msk) >> SUPC_BKOUT_RTCTGL_Pos; + return tmp; +} + +static inline void hri_supc_set_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg |= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_get_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) +{ + uint32_t tmp; + tmp = ((Supc *)hw)->BKOUT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_supc_write_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t data) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg = data; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_clear_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg &= ~mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_supc_toggle_BKOUT_reg(const void *const hw, hri_supc_bkout_reg_t mask) +{ + SUPC_CRITICAL_SECTION_ENTER(); + ((Supc *)hw)->BKOUT.reg ^= mask; + SUPC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_supc_bkout_reg_t hri_supc_read_BKOUT_reg(const void *const hw) +{ + return ((Supc *)hw)->BKOUT.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_SUPC_E54_H_INCLUDED */ +#endif /* _SAME54_SUPC_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_tc_e54.h b/software/firmware/oracle_same54n19a/hri/hri_tc_e54.h new file mode 100644 index 00000000..a31cb2cf --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_tc_e54.h @@ -0,0 +1,3003 @@ +/** + * \file + * + * \brief SAM TC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_TC_COMPONENT_ +#ifndef _HRI_TC_E54_H_INCLUDED_ +#define _HRI_TC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_TC_CRITICAL_SECTIONS) +#define TC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define TC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define TC_CRITICAL_SECTION_ENTER() +#define TC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_tc_evctrl_reg_t; +typedef uint16_t hri_tccount16_cc_reg_t; +typedef uint16_t hri_tccount16_ccbuf_reg_t; +typedef uint16_t hri_tccount16_count_reg_t; +typedef uint32_t hri_tc_ctrla_reg_t; +typedef uint32_t hri_tc_syncbusy_reg_t; +typedef uint32_t hri_tccount32_cc_reg_t; +typedef uint32_t hri_tccount32_ccbuf_reg_t; +typedef uint32_t hri_tccount32_count_reg_t; +typedef uint8_t hri_tc_ctrlbset_reg_t; +typedef uint8_t hri_tc_dbgctrl_reg_t; +typedef uint8_t hri_tc_drvctrl_reg_t; +typedef uint8_t hri_tc_intenset_reg_t; +typedef uint8_t hri_tc_intflag_reg_t; +typedef uint8_t hri_tc_status_reg_t; +typedef uint8_t hri_tc_wave_reg_t; +typedef uint8_t hri_tccount8_cc_reg_t; +typedef uint8_t hri_tccount8_ccbuf_reg_t; +typedef uint8_t hri_tccount8_count_reg_t; +typedef uint8_t hri_tccount8_per_reg_t; +typedef uint8_t hri_tccount8_perbuf_reg_t; + +static inline void hri_tc_wait_for_sync(const void *const hw, hri_tc_syncbusy_reg_t reg) +{ + while (((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_tc_is_syncing(const void *const hw, hri_tc_syncbusy_reg_t reg) +{ + return ((Tc *)hw)->COUNT8.SYNCBUSY.reg & reg; +} + +static inline bool hri_tc_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; +} + +static inline void hri_tc_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF; +} + +static inline bool hri_tc_get_INTFLAG_ERR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos; +} + +static inline void hri_tc_clear_INTFLAG_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR; +} + +static inline bool hri_tc_get_INTFLAG_MC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos; +} + +static inline void hri_tc_clear_INTFLAG_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC0; +} + +static inline bool hri_tc_get_INTFLAG_MC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos; +} + +static inline void hri_tc_clear_INTFLAG_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC1; +} + +static inline bool hri_tc_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_OVF) >> TC_INTFLAG_OVF_Pos; +} + +static inline void hri_tc_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_OVF; +} + +static inline bool hri_tc_get_interrupt_ERR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_ERR) >> TC_INTFLAG_ERR_Pos; +} + +static inline void hri_tc_clear_interrupt_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_ERR; +} + +static inline bool hri_tc_get_interrupt_MC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC0) >> TC_INTFLAG_MC0_Pos; +} + +static inline void hri_tc_clear_interrupt_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC0; +} + +static inline bool hri_tc_get_interrupt_MC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTFLAG.reg & TC_INTFLAG_MC1) >> TC_INTFLAG_MC1_Pos; +} + +static inline void hri_tc_clear_interrupt_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = TC_INTFLAG_MC1; +} + +static inline hri_tc_intflag_reg_t hri_tc_get_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_intflag_reg_t hri_tc_read_INTFLAG_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.INTFLAG.reg; +} + +static inline void hri_tc_clear_INTFLAG_reg(const void *const hw, hri_tc_intflag_reg_t mask) +{ + ((Tc *)hw)->COUNT16.INTFLAG.reg = mask; +} + +static inline void hri_tc_set_CTRLB_DIR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_DIR; +} + +static inline bool hri_tc_get_CTRLB_DIR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_DIR) >> TC_CTRLBSET_DIR_Pos; +} + +static inline void hri_tc_write_CTRLB_DIR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_DIR; + } else { + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_DIR; + } +} + +static inline void hri_tc_clear_CTRLB_DIR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_DIR; +} + +static inline void hri_tc_set_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_LUPD; +} + +static inline bool hri_tc_get_CTRLB_LUPD_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_LUPD) >> TC_CTRLBSET_LUPD_Pos; +} + +static inline void hri_tc_write_CTRLB_LUPD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_LUPD; + } else { + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_LUPD; + } +} + +static inline void hri_tc_clear_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_LUPD; +} + +static inline void hri_tc_set_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_ONESHOT; +} + +static inline bool hri_tc_get_CTRLB_ONESHOT_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.CTRLBSET.reg & TC_CTRLBSET_ONESHOT) >> TC_CTRLBSET_ONESHOT_Pos; +} + +static inline void hri_tc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT; + } else { + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_ONESHOT; + } +} + +static inline void hri_tc_clear_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_ONESHOT; +} + +static inline void hri_tc_set_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD(mask); +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; + tmp = (tmp & TC_CTRLBSET_CMD(mask)) >> TC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_CMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; + tmp = (tmp & TC_CTRLBSET_CMD_Msk) >> TC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t data) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = TC_CTRLBSET_CMD(data); + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~TC_CTRLBSET_CMD(data); +} + +static inline void hri_tc_clear_CTRLB_CMD_bf(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = TC_CTRLBSET_CMD(mask); +} + +static inline void hri_tc_set_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = mask; +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_get_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLBSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_ctrlbset_reg_t hri_tc_read_CTRLB_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.CTRLBSET.reg; +} + +static inline void hri_tc_write_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t data) +{ + ((Tc *)hw)->COUNT16.CTRLBSET.reg = data; + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = ~data; +} + +static inline void hri_tc_clear_CTRLB_reg(const void *const hw, hri_tc_ctrlbset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.CTRLBCLR.reg = mask; +} + +static inline void hri_tc_set_INTEN_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF; +} + +static inline bool hri_tc_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_OVF) >> TC_INTENSET_OVF_Pos; +} + +static inline void hri_tc_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF; + } else { + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_OVF; + } +} + +static inline void hri_tc_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_OVF; +} + +static inline void hri_tc_set_INTEN_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR; +} + +static inline bool hri_tc_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_ERR) >> TC_INTENSET_ERR_Pos; +} + +static inline void hri_tc_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR; + } else { + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_ERR; + } +} + +static inline void hri_tc_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_ERR; +} + +static inline void hri_tc_set_INTEN_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC0; +} + +static inline bool hri_tc_get_INTEN_MC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_MC0) >> TC_INTENSET_MC0_Pos; +} + +static inline void hri_tc_write_INTEN_MC0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC0; + } else { + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC0; + } +} + +static inline void hri_tc_clear_INTEN_MC0_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC0; +} + +static inline void hri_tc_set_INTEN_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC1; +} + +static inline bool hri_tc_get_INTEN_MC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.INTENSET.reg & TC_INTENSET_MC1) >> TC_INTENSET_MC1_Pos; +} + +static inline void hri_tc_write_INTEN_MC1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC1; + } else { + ((Tc *)hw)->COUNT16.INTENSET.reg = TC_INTENSET_MC1; + } +} + +static inline void hri_tc_clear_INTEN_MC1_bit(const void *const hw) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = TC_INTENSET_MC1; +} + +static inline void hri_tc_set_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = mask; +} + +static inline hri_tc_intenset_reg_t hri_tc_get_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_intenset_reg_t hri_tc_read_INTEN_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.INTENSET.reg; +} + +static inline void hri_tc_write_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t data) +{ + ((Tc *)hw)->COUNT16.INTENSET.reg = data; + ((Tc *)hw)->COUNT16.INTENCLR.reg = ~data; +} + +static inline void hri_tc_clear_INTEN_reg(const void *const hw, hri_tc_intenset_reg_t mask) +{ + ((Tc *)hw)->COUNT16.INTENCLR.reg = mask; +} + +static inline bool hri_tc_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_SWRST) >> TC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_ENABLE) >> TC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CTRLB) >> TC_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_STATUS_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_STATUS) >> TC_SYNCBUSY_STATUS_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_COUNT) >> TC_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_PER_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_PER) >> TC_SYNCBUSY_PER_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_CC0_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CC0) >> TC_SYNCBUSY_CC0_Pos; +} + +static inline bool hri_tc_get_SYNCBUSY_CC1_bit(const void *const hw) +{ + return (((Tc *)hw)->COUNT16.SYNCBUSY.reg & TC_SYNCBUSY_CC1) >> TC_SYNCBUSY_CC1_Pos; +} + +static inline hri_tc_syncbusy_reg_t hri_tc_get_SYNCBUSY_reg(const void *const hw, hri_tc_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tc_syncbusy_reg_t hri_tc_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.SYNCBUSY.reg; +} + +static inline void hri_tc_set_CTRLA_SWRST_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_SWRST; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_SWRST) >> TC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_tc_set_CTRLA_ENABLE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ENABLE; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_ENABLE) >> TC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_ENABLE; + tmp |= value << TC_CTRLA_ENABLE_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ENABLE; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ENABLE; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_RUNSTDBY; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_RUNSTDBY) >> TC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_RUNSTDBY; + tmp |= value << TC_CTRLA_RUNSTDBY_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_RUNSTDBY; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_RUNSTDBY; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_ONDEMAND_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ONDEMAND; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_ONDEMAND_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_ONDEMAND) >> TC_CTRLA_ONDEMAND_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_ONDEMAND_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_ONDEMAND; + tmp |= value << TC_CTRLA_ONDEMAND_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_ONDEMAND_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ONDEMAND; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_ONDEMAND_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ONDEMAND; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_ALOCK_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_ALOCK; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_ALOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_ALOCK) >> TC_CTRLA_ALOCK_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_ALOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_ALOCK; + tmp |= value << TC_CTRLA_ALOCK_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_ALOCK_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_ALOCK; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_ALOCK_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_ALOCK; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_CAPTEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_CAPTEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTEN0) >> TC_CTRLA_CAPTEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_CAPTEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_CAPTEN0; + tmp |= value << TC_CTRLA_CAPTEN0_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_CAPTEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_CAPTEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_CAPTEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_CAPTEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTEN1) >> TC_CTRLA_CAPTEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_CAPTEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_CAPTEN1; + tmp |= value << TC_CTRLA_CAPTEN1_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_CAPTEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_CAPTEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_COPEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_COPEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_COPEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_COPEN0) >> TC_CTRLA_COPEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_COPEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_COPEN0; + tmp |= value << TC_CTRLA_COPEN0_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_COPEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_COPEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_COPEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_COPEN0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_COPEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_COPEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_CTRLA_COPEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_COPEN1) >> TC_CTRLA_COPEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_CTRLA_COPEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_COPEN1; + tmp |= value << TC_CTRLA_COPEN1_Pos; + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_COPEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_COPEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_COPEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_COPEN1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_MODE(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_MODE(mask)) >> TC_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_MODE_Msk; + tmp |= TC_CTRLA_MODE(data); + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_MODE(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_MODE_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_MODE(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_MODE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_MODE_Msk) >> TC_CTRLA_MODE_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCSYNC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCSYNC(mask)) >> TC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_PRESCSYNC_Msk; + tmp |= TC_CTRLA_PRESCSYNC(data); + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_PRESCSYNC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_PRESCSYNC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCSYNC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCSYNC_Msk) >> TC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_PRESCALER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCALER(mask)) >> TC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_PRESCALER_Msk; + tmp |= TC_CTRLA_PRESCALER(data); + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_PRESCALER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_PRESCALER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_PRESCALER_Msk) >> TC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTMODE0(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTMODE0(mask)) >> TC_CTRLA_CAPTMODE0_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_CAPTMODE0_Msk; + tmp |= TC_CTRLA_CAPTMODE0(data); + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTMODE0(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_CAPTMODE0_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTMODE0(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_CAPTMODE0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTMODE0_Msk) >> TC_CTRLA_CAPTMODE0_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= TC_CTRLA_CAPTMODE1(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTMODE1(mask)) >> TC_CTRLA_CAPTMODE1_Pos; + return tmp; +} + +static inline void hri_tc_write_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= ~TC_CTRLA_CAPTMODE1_Msk; + tmp |= TC_CTRLA_CAPTMODE1(data); + ((Tc *)hw)->COUNT16.CTRLA.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~TC_CTRLA_CAPTMODE1(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_CAPTMODE1_bf(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= TC_CTRLA_CAPTMODE1(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_CAPTMODE1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp = (tmp & TC_CTRLA_CAPTMODE1_Msk) >> TC_CTRLA_CAPTMODE1_Pos; + return tmp; +} + +static inline void hri_tc_set_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_get_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + tmp = ((Tc *)hw)->COUNT16.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_CTRLA_reg(const void *const hw, hri_tc_ctrla_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CTRLA.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_ctrla_reg_t hri_tc_read_CTRLA_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_SWRST | TC_SYNCBUSY_ENABLE); + return ((Tc *)hw)->COUNT16.CTRLA.reg; +} + +static inline void hri_tc_set_EVCTRL_TCINV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_TCINV; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_TCINV_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_TCINV) >> TC_EVCTRL_TCINV_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_TCINV_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_TCINV; + tmp |= value << TC_EVCTRL_TCINV_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_TCINV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_TCINV; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_TCINV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_TCINV; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_TCEI_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_TCEI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_TCEI_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_TCEI) >> TC_EVCTRL_TCEI_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_TCEI_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_TCEI; + tmp |= value << TC_EVCTRL_TCEI_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_TCEI_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_TCEI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_TCEI_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_TCEI; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_OVFEO; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_OVFEO) >> TC_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_OVFEO; + tmp |= value << TC_EVCTRL_OVFEO_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_OVFEO; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_OVFEO; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_MCEO0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_MCEO0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_MCEO0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_MCEO0) >> TC_EVCTRL_MCEO0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_MCEO0; + tmp |= value << TC_EVCTRL_MCEO0_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_MCEO0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_MCEO0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_MCEO0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_MCEO0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_MCEO1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_MCEO1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_EVCTRL_MCEO1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_MCEO1) >> TC_EVCTRL_MCEO1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_MCEO1; + tmp |= value << TC_EVCTRL_MCEO1_Pos; + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_MCEO1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_MCEO1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_MCEO1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_MCEO1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= TC_EVCTRL_EVACT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_EVACT(mask)) >> TC_EVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_tc_write_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= ~TC_EVCTRL_EVACT_Msk; + tmp |= TC_EVCTRL_EVACT(data); + ((Tc *)hw)->COUNT16.EVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~TC_EVCTRL_EVACT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_EVACT_bf(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= TC_EVCTRL_EVACT(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_EVACT_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp = (tmp & TC_EVCTRL_EVACT_Msk) >> TC_EVCTRL_EVACT_Pos; + return tmp; +} + +static inline void hri_tc_set_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_get_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_EVCTRL_reg(const void *const hw, hri_tc_evctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.EVCTRL.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_evctrl_reg_t hri_tc_read_EVCTRL_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.EVCTRL.reg; +} + +static inline void hri_tc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg |= TC_WAVE_WAVEGEN(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.WAVE.reg; + tmp = (tmp & TC_WAVE_WAVEGEN(mask)) >> TC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.WAVE.reg; + tmp &= ~TC_WAVE_WAVEGEN_Msk; + tmp |= TC_WAVE_WAVEGEN(data); + ((Tc *)hw)->COUNT16.WAVE.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg &= ~TC_WAVE_WAVEGEN(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg ^= TC_WAVE_WAVEGEN(mask); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_read_WAVE_WAVEGEN_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.WAVE.reg; + tmp = (tmp & TC_WAVE_WAVEGEN_Msk) >> TC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tc_set_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_get_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.WAVE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_WAVE_reg(const void *const hw, hri_tc_wave_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_WAVE_reg(const void *const hw, hri_tc_wave_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.WAVE.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_wave_reg_t hri_tc_read_WAVE_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.WAVE.reg; +} + +static inline void hri_tc_set_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_DRVCTRL_INVEN0_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp = (tmp & TC_DRVCTRL_INVEN0) >> TC_DRVCTRL_INVEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp &= ~TC_DRVCTRL_INVEN0; + tmp |= value << TC_DRVCTRL_INVEN0_Pos; + ((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN0; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg |= TC_DRVCTRL_INVEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_DRVCTRL_INVEN1_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp = (tmp & TC_DRVCTRL_INVEN1) >> TC_DRVCTRL_INVEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp &= ~TC_DRVCTRL_INVEN1; + tmp |= value << TC_DRVCTRL_INVEN1_Pos; + ((Tc *)hw)->COUNT16.DRVCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~TC_DRVCTRL_INVEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= TC_DRVCTRL_INVEN1; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_drvctrl_reg_t hri_tc_get_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DRVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DRVCTRL_reg(const void *const hw, hri_tc_drvctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DRVCTRL.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_drvctrl_reg_t hri_tc_read_DRVCTRL_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.DRVCTRL.reg; +} + +static inline void hri_tc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg |= TC_DBGCTRL_DBGRUN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; + tmp = (tmp & TC_DBGCTRL_DBGRUN) >> TC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_tc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; + tmp &= ~TC_DBGCTRL_DBGRUN; + tmp |= value << TC_DBGCTRL_DBGRUN_Pos; + ((Tc *)hw)->COUNT16.DBGCTRL.reg = tmp; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg &= ~TC_DBGCTRL_DBGRUN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg ^= TC_DBGCTRL_DBGRUN; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_set_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg |= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_dbgctrl_reg_t hri_tc_get_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT16.DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_write_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg = data; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_clear_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg &= ~mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tc_toggle_DBGCTRL_reg(const void *const hw, hri_tc_dbgctrl_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.DBGCTRL.reg ^= mask; + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_dbgctrl_reg_t hri_tc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Tc *)hw)->COUNT16.DBGCTRL.reg; +} + +static inline void hri_tccount8_set_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg |= TC_COUNT8_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_count_reg_t hri_tccount8_get_COUNT_COUNT_bf(const void *const hw, + hri_tccount8_count_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp = (tmp & TC_COUNT8_COUNT_COUNT(mask)) >> TC_COUNT8_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount8_write_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp &= ~TC_COUNT8_COUNT_COUNT_Msk; + tmp |= TC_COUNT8_COUNT_COUNT(data); + ((Tc *)hw)->COUNT8.COUNT.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg &= ~TC_COUNT8_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg ^= TC_COUNT8_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_count_reg_t hri_tccount8_read_COUNT_COUNT_bf(const void *const hw) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp = (tmp & TC_COUNT8_COUNT_COUNT_Msk) >> TC_COUNT8_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount8_set_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_count_reg_t hri_tccount8_get_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT8.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_COUNT_reg(const void *const hw, hri_tccount8_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.COUNT.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_count_reg_t hri_tccount8_read_COUNT_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + return ((Tc *)hw)->COUNT8.COUNT.reg; +} + +static inline void hri_tccount16_set_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg |= TC_COUNT16_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_count_reg_t hri_tccount16_get_COUNT_COUNT_bf(const void *const hw, + hri_tccount16_count_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp = (tmp & TC_COUNT16_COUNT_COUNT(mask)) >> TC_COUNT16_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount16_write_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp &= ~TC_COUNT16_COUNT_COUNT_Msk; + tmp |= TC_COUNT16_COUNT_COUNT(data); + ((Tc *)hw)->COUNT16.COUNT.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg &= ~TC_COUNT16_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg ^= TC_COUNT16_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_count_reg_t hri_tccount16_read_COUNT_COUNT_bf(const void *const hw) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp = (tmp & TC_COUNT16_COUNT_COUNT_Msk) >> TC_COUNT16_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount16_set_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_count_reg_t hri_tccount16_get_COUNT_reg(const void *const hw, + hri_tccount16_count_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT16.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount16_write_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_COUNT_reg(const void *const hw, hri_tccount16_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.COUNT.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_count_reg_t hri_tccount16_read_COUNT_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + return ((Tc *)hw)->COUNT16.COUNT.reg; +} + +static inline void hri_tccount32_set_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg |= TC_COUNT32_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_count_reg_t hri_tccount32_get_COUNT_COUNT_bf(const void *const hw, + hri_tccount32_count_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp = (tmp & TC_COUNT32_COUNT_COUNT(mask)) >> TC_COUNT32_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount32_write_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp &= ~TC_COUNT32_COUNT_COUNT_Msk; + tmp |= TC_COUNT32_COUNT_COUNT(data); + ((Tc *)hw)->COUNT32.COUNT.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg &= ~TC_COUNT32_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_COUNT_COUNT_bf(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg ^= TC_COUNT32_COUNT_COUNT(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_count_reg_t hri_tccount32_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp = (tmp & TC_COUNT32_COUNT_COUNT_Msk) >> TC_COUNT32_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tccount32_set_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_count_reg_t hri_tccount32_get_COUNT_reg(const void *const hw, + hri_tccount32_count_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + tmp = ((Tc *)hw)->COUNT32.COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount32_write_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_COUNT_reg(const void *const hw, hri_tccount32_count_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.COUNT.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_count_reg_t hri_tccount32_read_COUNT_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_COUNT); + return ((Tc *)hw)->COUNT32.COUNT.reg; +} + +static inline void hri_tccount8_set_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg |= TC_COUNT8_PER_PER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_per_reg_t hri_tccount8_get_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp = (tmp & TC_COUNT8_PER_PER(mask)) >> TC_COUNT8_PER_PER_Pos; + return tmp; +} + +static inline void hri_tccount8_write_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp &= ~TC_COUNT8_PER_PER_Msk; + tmp |= TC_COUNT8_PER_PER(data); + ((Tc *)hw)->COUNT8.PER.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg &= ~TC_COUNT8_PER_PER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_PER_PER_bf(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg ^= TC_COUNT8_PER_PER(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_per_reg_t hri_tccount8_read_PER_PER_bf(const void *const hw) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp = (tmp & TC_COUNT8_PER_PER_Msk) >> TC_COUNT8_PER_PER_Pos; + return tmp; +} + +static inline void hri_tccount8_set_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_per_reg_t hri_tccount8_get_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + tmp = ((Tc *)hw)->COUNT8.PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_PER_reg(const void *const hw, hri_tccount8_per_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_PER_reg(const void *const hw, hri_tccount8_per_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PER.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_per_reg_t hri_tccount8_read_PER_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_PER); + return ((Tc *)hw)->COUNT8.PER.reg; +} + +static inline void hri_tccount8_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg |= TC_COUNT8_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_cc_reg_t hri_tccount8_get_CC_CC_bf(const void *const hw, uint8_t index, + hri_tccount8_cc_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp = (tmp & TC_COUNT8_CC_CC(mask)) >> TC_COUNT8_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount8_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp &= ~TC_COUNT8_CC_CC_Msk; + tmp |= TC_COUNT8_CC_CC(data); + ((Tc *)hw)->COUNT8.CC[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg &= ~TC_COUNT8_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg ^= TC_COUNT8_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_cc_reg_t hri_tccount8_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp = (tmp & TC_COUNT8_CC_CC_Msk) >> TC_COUNT8_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount8_set_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_cc_reg_t hri_tccount8_get_CC_reg(const void *const hw, uint8_t index, + hri_tccount8_cc_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT8.CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount8_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CC[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_cc_reg_t hri_tccount8_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + return ((Tc *)hw)->COUNT8.CC[index].reg; +} + +static inline void hri_tccount16_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg |= TC_COUNT16_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_cc_reg_t hri_tccount16_get_CC_CC_bf(const void *const hw, uint8_t index, + hri_tccount16_cc_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp = (tmp & TC_COUNT16_CC_CC(mask)) >> TC_COUNT16_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount16_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp &= ~TC_COUNT16_CC_CC_Msk; + tmp |= TC_COUNT16_CC_CC(data); + ((Tc *)hw)->COUNT16.CC[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg &= ~TC_COUNT16_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg ^= TC_COUNT16_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_cc_reg_t hri_tccount16_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp = (tmp & TC_COUNT16_CC_CC_Msk) >> TC_COUNT16_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount16_set_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_cc_reg_t hri_tccount16_get_CC_reg(const void *const hw, uint8_t index, + hri_tccount16_cc_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT16.CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount16_write_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount16_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CC[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_cc_reg_t hri_tccount16_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + return ((Tc *)hw)->COUNT16.CC[index].reg; +} + +static inline void hri_tccount32_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg |= TC_COUNT32_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_cc_reg_t hri_tccount32_get_CC_CC_bf(const void *const hw, uint8_t index, + hri_tccount32_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp = (tmp & TC_COUNT32_CC_CC(mask)) >> TC_COUNT32_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount32_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp &= ~TC_COUNT32_CC_CC_Msk; + tmp |= TC_COUNT32_CC_CC(data); + ((Tc *)hw)->COUNT32.CC[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg &= ~TC_COUNT32_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg ^= TC_COUNT32_CC_CC(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp = (tmp & TC_COUNT32_CC_CC_Msk) >> TC_COUNT32_CC_CC_Pos; + return tmp; +} + +static inline void hri_tccount32_set_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_cc_reg_t hri_tccount32_get_CC_reg(const void *const hw, uint8_t index, + hri_tccount32_cc_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + tmp = ((Tc *)hw)->COUNT32.CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount32_write_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CC_reg(const void *const hw, uint8_t index, hri_tccount32_cc_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CC[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_cc_reg_t hri_tccount32_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_CC0 | TC_SYNCBUSY_CC1); + return ((Tc *)hw)->COUNT32.CC[index].reg; +} + +static inline void hri_tccount8_set_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg |= TC_COUNT8_PERBUF_PERBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_perbuf_reg_t hri_tccount8_get_PERBUF_PERBUF_bf(const void *const hw, + hri_tccount8_perbuf_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp = (tmp & TC_COUNT8_PERBUF_PERBUF(mask)) >> TC_COUNT8_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_write_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp &= ~TC_COUNT8_PERBUF_PERBUF_Msk; + tmp |= TC_COUNT8_PERBUF_PERBUF(data); + ((Tc *)hw)->COUNT8.PERBUF.reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg &= ~TC_COUNT8_PERBUF_PERBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg ^= TC_COUNT8_PERBUF_PERBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_perbuf_reg_t hri_tccount8_read_PERBUF_PERBUF_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp = (tmp & TC_COUNT8_PERBUF_PERBUF_Msk) >> TC_COUNT8_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_set_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_perbuf_reg_t hri_tccount8_get_PERBUF_reg(const void *const hw, + hri_tccount8_perbuf_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT8.PERBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_PERBUF_reg(const void *const hw, hri_tccount8_perbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.PERBUF.reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_perbuf_reg_t hri_tccount8_read_PERBUF_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT8.PERBUF.reg; +} + +static inline void hri_tccount8_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg |= TC_COUNT8_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_ccbuf_reg_t hri_tccount8_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount8_ccbuf_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp = (tmp & TC_COUNT8_CCBUF_CCBUF(mask)) >> TC_COUNT8_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t data) +{ + uint8_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp &= ~TC_COUNT8_CCBUF_CCBUF_Msk; + tmp |= TC_COUNT8_CCBUF_CCBUF(data); + ((Tc *)hw)->COUNT8.CCBUF[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~TC_COUNT8_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg ^= TC_COUNT8_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_ccbuf_reg_t hri_tccount8_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint8_t tmp; + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp = (tmp & TC_COUNT8_CCBUF_CCBUF_Msk) >> TC_COUNT8_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount8_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_ccbuf_reg_t hri_tccount8_get_CCBUF_reg(const void *const hw, uint8_t index, + hri_tccount8_ccbuf_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT8.CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount8_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount8_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount8_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT8.CCBUF[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount8_ccbuf_reg_t hri_tccount8_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT8.CCBUF[index].reg; +} + +static inline void hri_tccount16_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg |= TC_COUNT16_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_ccbuf_reg_t hri_tccount16_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp = (tmp & TC_COUNT16_CCBUF_CCBUF(mask)) >> TC_COUNT16_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount16_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t data) +{ + uint16_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp &= ~TC_COUNT16_CCBUF_CCBUF_Msk; + tmp |= TC_COUNT16_CCBUF_CCBUF(data); + ((Tc *)hw)->COUNT16.CCBUF[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~TC_COUNT16_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg ^= TC_COUNT16_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_ccbuf_reg_t hri_tccount16_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint16_t tmp; + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp = (tmp & TC_COUNT16_CCBUF_CCBUF_Msk) >> TC_COUNT16_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount16_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_ccbuf_reg_t hri_tccount16_get_CCBUF_reg(const void *const hw, uint8_t index, + hri_tccount16_ccbuf_reg_t mask) +{ + uint16_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT16.CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount16_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount16_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount16_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.CCBUF[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount16_ccbuf_reg_t hri_tccount16_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT16.CCBUF[index].reg; +} + +static inline void hri_tccount32_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg |= TC_COUNT32_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_ccbuf_reg_t hri_tccount32_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp = (tmp & TC_COUNT32_CCBUF_CCBUF(mask)) >> TC_COUNT32_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount32_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t data) +{ + uint32_t tmp; + TC_CRITICAL_SECTION_ENTER(); + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp &= ~TC_COUNT32_CCBUF_CCBUF_Msk; + tmp |= TC_COUNT32_CCBUF_CCBUF(data); + ((Tc *)hw)->COUNT32.CCBUF[index].reg = tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~TC_COUNT32_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg ^= TC_COUNT32_CCBUF_CCBUF(mask); + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_ccbuf_reg_t hri_tccount32_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp = (tmp & TC_COUNT32_CCBUF_CCBUF_Msk) >> TC_COUNT32_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tccount32_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg |= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_ccbuf_reg_t hri_tccount32_get_CCBUF_reg(const void *const hw, uint8_t index, + hri_tccount32_ccbuf_reg_t mask) +{ + uint32_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT32.CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tccount32_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t data) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg = data; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg &= ~mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tccount32_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tccount32_ccbuf_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT32.CCBUF[index].reg ^= mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tccount32_ccbuf_reg_t hri_tccount32_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT32.CCBUF[index].reg; +} + +static inline bool hri_tc_get_STATUS_STOP_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_STOP) >> TC_STATUS_STOP_Pos; +} + +static inline void hri_tc_clear_STATUS_STOP_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_STOP; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_SLAVE_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_SLAVE) >> TC_STATUS_SLAVE_Pos; +} + +static inline void hri_tc_clear_STATUS_SLAVE_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_SLAVE; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_PERBUFV_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_PERBUFV) >> TC_STATUS_PERBUFV_Pos; +} + +static inline void hri_tc_clear_STATUS_PERBUFV_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_PERBUFV; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_CCBUFV0_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_CCBUFV0) >> TC_STATUS_CCBUFV0_Pos; +} + +static inline void hri_tc_clear_STATUS_CCBUFV0_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_CCBUFV0; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tc_get_STATUS_CCBUFV1_bit(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return (((Tc *)hw)->COUNT16.STATUS.reg & TC_STATUS_CCBUFV1) >> TC_STATUS_CCBUFV1_Pos; +} + +static inline void hri_tc_clear_STATUS_CCBUFV1_bit(const void *const hw) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = TC_STATUS_CCBUFV1; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_status_reg_t hri_tc_get_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask) +{ + uint8_t tmp; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + tmp = ((Tc *)hw)->COUNT16.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tc_clear_STATUS_reg(const void *const hw, hri_tc_status_reg_t mask) +{ + TC_CRITICAL_SECTION_ENTER(); + ((Tc *)hw)->COUNT16.STATUS.reg = mask; + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + TC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tc_status_reg_t hri_tc_read_STATUS_reg(const void *const hw) +{ + hri_tc_wait_for_sync(hw, TC_SYNCBUSY_MASK); + return ((Tc *)hw)->COUNT16.STATUS.reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_tc_set_PER_PER_bf(a, b) hri_tccount8_set_PER_PER_bf(a, b) +#define hri_tc_get_PER_PER_bf(a, b) hri_tccount8_get_PER_PER_bf(a, b) +#define hri_tc_write_PER_PER_bf(a, b) hri_tccount8_write_PER_PER_bf(a, b) +#define hri_tc_clear_PER_PER_bf(a, b) hri_tccount8_clear_PER_PER_bf(a, b) +#define hri_tc_toggle_PER_PER_bf(a, b) hri_tccount8_toggle_PER_PER_bf(a, b) +#define hri_tc_read_PER_PER_bf(a) hri_tccount8_read_PER_PER_bf(a) +#define hri_tc_set_PER_reg(a, b) hri_tccount8_set_PER_reg(a, b) +#define hri_tc_get_PER_reg(a, b) hri_tccount8_get_PER_reg(a, b) +#define hri_tc_write_PER_reg(a, b) hri_tccount8_write_PER_reg(a, b) +#define hri_tc_clear_PER_reg(a, b) hri_tccount8_clear_PER_reg(a, b) +#define hri_tc_toggle_PER_reg(a, b) hri_tccount8_toggle_PER_reg(a, b) +#define hri_tc_read_PER_reg(a) hri_tccount8_read_PER_reg(a) +#define hri_tc_set_PERBUF_PERBUF_bf(a, b) hri_tccount8_set_PERBUF_PERBUF_bf(a, b) +#define hri_tc_get_PERBUF_PERBUF_bf(a, b) hri_tccount8_get_PERBUF_PERBUF_bf(a, b) +#define hri_tc_write_PERBUF_PERBUF_bf(a, b) hri_tccount8_write_PERBUF_PERBUF_bf(a, b) +#define hri_tc_clear_PERBUF_PERBUF_bf(a, b) hri_tccount8_clear_PERBUF_PERBUF_bf(a, b) +#define hri_tc_toggle_PERBUF_PERBUF_bf(a, b) hri_tccount8_toggle_PERBUF_PERBUF_bf(a, b) +#define hri_tc_read_PERBUF_PERBUF_bf(a) hri_tccount8_read_PERBUF_PERBUF_bf(a) +#define hri_tc_set_PERBUF_reg(a, b) hri_tccount8_set_PERBUF_reg(a, b) +#define hri_tc_get_PERBUF_reg(a, b) hri_tccount8_get_PERBUF_reg(a, b) +#define hri_tc_write_PERBUF_reg(a, b) hri_tccount8_write_PERBUF_reg(a, b) +#define hri_tc_clear_PERBUF_reg(a, b) hri_tccount8_clear_PERBUF_reg(a, b) +#define hri_tc_toggle_PERBUF_reg(a, b) hri_tccount8_toggle_PERBUF_reg(a, b) +#define hri_tc_read_PERBUF_reg(a) hri_tccount8_read_PERBUF_reg(a) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_TC_E54_H_INCLUDED */ +#endif /* _SAME54_TC_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_tcc_e54.h b/software/firmware/oracle_same54n19a/hri/hri_tcc_e54.h new file mode 100644 index 00000000..55f46bd6 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_tcc_e54.h @@ -0,0 +1,9992 @@ +/** + * \file + * + * \brief SAM TCC + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_TCC_COMPONENT_ +#ifndef _HRI_TCC_E54_H_INCLUDED_ +#define _HRI_TCC_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_TCC_CRITICAL_SECTIONS) +#define TCC_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define TCC_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define TCC_CRITICAL_SECTION_ENTER() +#define TCC_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_tcc_patt_reg_t; +typedef uint16_t hri_tcc_pattbuf_reg_t; +typedef uint32_t hri_tcc_cc_reg_t; +typedef uint32_t hri_tcc_ccbuf_reg_t; +typedef uint32_t hri_tcc_count_reg_t; +typedef uint32_t hri_tcc_ctrla_reg_t; +typedef uint32_t hri_tcc_drvctrl_reg_t; +typedef uint32_t hri_tcc_evctrl_reg_t; +typedef uint32_t hri_tcc_fctrla_reg_t; +typedef uint32_t hri_tcc_fctrlb_reg_t; +typedef uint32_t hri_tcc_intenset_reg_t; +typedef uint32_t hri_tcc_intflag_reg_t; +typedef uint32_t hri_tcc_per_reg_t; +typedef uint32_t hri_tcc_perbuf_reg_t; +typedef uint32_t hri_tcc_status_reg_t; +typedef uint32_t hri_tcc_syncbusy_reg_t; +typedef uint32_t hri_tcc_wave_reg_t; +typedef uint32_t hri_tcc_wexctrl_reg_t; +typedef uint8_t hri_tcc_ctrlbset_reg_t; +typedef uint8_t hri_tcc_dbgctrl_reg_t; + +static inline void hri_tcc_wait_for_sync(const void *const hw, hri_tcc_syncbusy_reg_t reg) +{ + while (((Tcc *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_tcc_is_syncing(const void *const hw, hri_tcc_syncbusy_reg_t reg) +{ + return ((Tcc *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_tcc_get_INTFLAG_OVF_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF; +} + +static inline bool hri_tcc_get_INTFLAG_TRG_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG; +} + +static inline bool hri_tcc_get_INTFLAG_CNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT; +} + +static inline bool hri_tcc_get_INTFLAG_ERR_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR; +} + +static inline bool hri_tcc_get_INTFLAG_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS; +} + +static inline bool hri_tcc_get_INTFLAG_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS; +} + +static inline bool hri_tcc_get_INTFLAG_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA; +} + +static inline bool hri_tcc_get_INTFLAG_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB; +} + +static inline bool hri_tcc_get_INTFLAG_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0; +} + +static inline bool hri_tcc_get_INTFLAG_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1; +} + +static inline bool hri_tcc_get_INTFLAG_MC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0; +} + +static inline bool hri_tcc_get_INTFLAG_MC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1; +} + +static inline bool hri_tcc_get_INTFLAG_MC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2; +} + +static inline bool hri_tcc_get_INTFLAG_MC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3; +} + +static inline bool hri_tcc_get_INTFLAG_MC4_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC4) >> TCC_INTFLAG_MC4_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC4_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC4; +} + +static inline bool hri_tcc_get_INTFLAG_MC5_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC5) >> TCC_INTFLAG_MC5_Pos; +} + +static inline void hri_tcc_clear_INTFLAG_MC5_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC5; +} + +static inline bool hri_tcc_get_interrupt_OVF_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_OVF) >> TCC_INTFLAG_OVF_Pos; +} + +static inline void hri_tcc_clear_interrupt_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_OVF; +} + +static inline bool hri_tcc_get_interrupt_TRG_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_TRG) >> TCC_INTFLAG_TRG_Pos; +} + +static inline void hri_tcc_clear_interrupt_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_TRG; +} + +static inline bool hri_tcc_get_interrupt_CNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_CNT) >> TCC_INTFLAG_CNT_Pos; +} + +static inline void hri_tcc_clear_interrupt_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_CNT; +} + +static inline bool hri_tcc_get_interrupt_ERR_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_ERR) >> TCC_INTFLAG_ERR_Pos; +} + +static inline void hri_tcc_clear_interrupt_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_ERR; +} + +static inline bool hri_tcc_get_interrupt_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_UFS) >> TCC_INTFLAG_UFS_Pos; +} + +static inline void hri_tcc_clear_interrupt_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_UFS; +} + +static inline bool hri_tcc_get_interrupt_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_DFS) >> TCC_INTFLAG_DFS_Pos; +} + +static inline void hri_tcc_clear_interrupt_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_DFS; +} + +static inline bool hri_tcc_get_interrupt_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTA) >> TCC_INTFLAG_FAULTA_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTA; +} + +static inline bool hri_tcc_get_interrupt_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULTB) >> TCC_INTFLAG_FAULTB_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULTB; +} + +static inline bool hri_tcc_get_interrupt_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT0) >> TCC_INTFLAG_FAULT0_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT0; +} + +static inline bool hri_tcc_get_interrupt_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_FAULT1) >> TCC_INTFLAG_FAULT1_Pos; +} + +static inline void hri_tcc_clear_interrupt_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_FAULT1; +} + +static inline bool hri_tcc_get_interrupt_MC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC0) >> TCC_INTFLAG_MC0_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC0; +} + +static inline bool hri_tcc_get_interrupt_MC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC1) >> TCC_INTFLAG_MC1_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC1; +} + +static inline bool hri_tcc_get_interrupt_MC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC2) >> TCC_INTFLAG_MC2_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC2; +} + +static inline bool hri_tcc_get_interrupt_MC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC3) >> TCC_INTFLAG_MC3_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC3; +} + +static inline bool hri_tcc_get_interrupt_MC4_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC4) >> TCC_INTFLAG_MC4_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC4_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC4; +} + +static inline bool hri_tcc_get_interrupt_MC5_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTFLAG.reg & TCC_INTFLAG_MC5) >> TCC_INTFLAG_MC5_Pos; +} + +static inline void hri_tcc_clear_interrupt_MC5_bit(const void *const hw) +{ + ((Tcc *)hw)->INTFLAG.reg = TCC_INTFLAG_MC5; +} + +static inline hri_tcc_intflag_reg_t hri_tcc_get_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_intflag_reg_t hri_tcc_read_INTFLAG_reg(const void *const hw) +{ + return ((Tcc *)hw)->INTFLAG.reg; +} + +static inline void hri_tcc_clear_INTFLAG_reg(const void *const hw, hri_tcc_intflag_reg_t mask) +{ + ((Tcc *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_tcc_set_CTRLB_DIR_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR; +} + +static inline bool hri_tcc_get_CTRLB_DIR_bit(const void *const hw) +{ + return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_DIR) >> TCC_CTRLBSET_DIR_Pos; +} + +static inline void hri_tcc_write_CTRLB_DIR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR; + } else { + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_DIR; + } +} + +static inline void hri_tcc_clear_CTRLB_DIR_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_DIR; +} + +static inline void hri_tcc_set_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD; +} + +static inline bool hri_tcc_get_CTRLB_LUPD_bit(const void *const hw) +{ + return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_LUPD) >> TCC_CTRLBSET_LUPD_Pos; +} + +static inline void hri_tcc_write_CTRLB_LUPD_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD; + } else { + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_LUPD; + } +} + +static inline void hri_tcc_clear_CTRLB_LUPD_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_LUPD; +} + +static inline void hri_tcc_set_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT; +} + +static inline bool hri_tcc_get_CTRLB_ONESHOT_bit(const void *const hw) +{ + return (((Tcc *)hw)->CTRLBSET.reg & TCC_CTRLBSET_ONESHOT) >> TCC_CTRLBSET_ONESHOT_Pos; +} + +static inline void hri_tcc_write_CTRLB_ONESHOT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT; + } else { + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_ONESHOT; + } +} + +static inline void hri_tcc_clear_CTRLB_ONESHOT_bit(const void *const hw) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_ONESHOT; +} + +static inline void hri_tcc_set_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(mask); +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_IDXCMD(mask)) >> TCC_CTRLBSET_IDXCMD_Pos; + return tmp; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_IDXCMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_IDXCMD_Msk) >> TCC_CTRLBSET_IDXCMD_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_IDXCMD(data); + ((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_IDXCMD(data); +} + +static inline void hri_tcc_clear_CTRLB_IDXCMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_IDXCMD(mask); +} + +static inline void hri_tcc_set_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(mask); +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_CMD(mask)) >> TCC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_CMD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp = (tmp & TCC_CTRLBSET_CMD_Msk) >> TCC_CTRLBSET_CMD_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t data) +{ + ((Tcc *)hw)->CTRLBSET.reg = TCC_CTRLBSET_CMD(data); + ((Tcc *)hw)->CTRLBCLR.reg = ~TCC_CTRLBSET_CMD(data); +} + +static inline void hri_tcc_clear_CTRLB_CMD_bf(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBCLR.reg = TCC_CTRLBSET_CMD(mask); +} + +static inline void hri_tcc_set_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBSET.reg = mask; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_get_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->CTRLBSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_ctrlbset_reg_t hri_tcc_read_CTRLB_reg(const void *const hw) +{ + return ((Tcc *)hw)->CTRLBSET.reg; +} + +static inline void hri_tcc_write_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t data) +{ + ((Tcc *)hw)->CTRLBSET.reg = data; + ((Tcc *)hw)->CTRLBCLR.reg = ~data; +} + +static inline void hri_tcc_clear_CTRLB_reg(const void *const hw, hri_tcc_ctrlbset_reg_t mask) +{ + ((Tcc *)hw)->CTRLBCLR.reg = mask; +} + +static inline void hri_tcc_set_INTEN_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF; +} + +static inline bool hri_tcc_get_INTEN_OVF_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_OVF) >> TCC_INTENSET_OVF_Pos; +} + +static inline void hri_tcc_write_INTEN_OVF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_OVF; + } +} + +static inline void hri_tcc_clear_INTEN_OVF_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_OVF; +} + +static inline void hri_tcc_set_INTEN_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG; +} + +static inline bool hri_tcc_get_INTEN_TRG_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_TRG) >> TCC_INTENSET_TRG_Pos; +} + +static inline void hri_tcc_write_INTEN_TRG_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_TRG; + } +} + +static inline void hri_tcc_clear_INTEN_TRG_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_TRG; +} + +static inline void hri_tcc_set_INTEN_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT; +} + +static inline bool hri_tcc_get_INTEN_CNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_CNT) >> TCC_INTENSET_CNT_Pos; +} + +static inline void hri_tcc_write_INTEN_CNT_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_CNT; + } +} + +static inline void hri_tcc_clear_INTEN_CNT_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_CNT; +} + +static inline void hri_tcc_set_INTEN_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR; +} + +static inline bool hri_tcc_get_INTEN_ERR_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_ERR) >> TCC_INTENSET_ERR_Pos; +} + +static inline void hri_tcc_write_INTEN_ERR_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_ERR; + } +} + +static inline void hri_tcc_clear_INTEN_ERR_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_ERR; +} + +static inline void hri_tcc_set_INTEN_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS; +} + +static inline bool hri_tcc_get_INTEN_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_UFS) >> TCC_INTENSET_UFS_Pos; +} + +static inline void hri_tcc_write_INTEN_UFS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_UFS; + } +} + +static inline void hri_tcc_clear_INTEN_UFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_UFS; +} + +static inline void hri_tcc_set_INTEN_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS; +} + +static inline bool hri_tcc_get_INTEN_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_DFS) >> TCC_INTENSET_DFS_Pos; +} + +static inline void hri_tcc_write_INTEN_DFS_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_DFS; + } +} + +static inline void hri_tcc_clear_INTEN_DFS_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_DFS; +} + +static inline void hri_tcc_set_INTEN_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA; +} + +static inline bool hri_tcc_get_INTEN_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTA) >> TCC_INTENSET_FAULTA_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULTA_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTA; + } +} + +static inline void hri_tcc_clear_INTEN_FAULTA_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTA; +} + +static inline void hri_tcc_set_INTEN_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB; +} + +static inline bool hri_tcc_get_INTEN_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULTB) >> TCC_INTENSET_FAULTB_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULTB_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULTB; + } +} + +static inline void hri_tcc_clear_INTEN_FAULTB_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULTB; +} + +static inline void hri_tcc_set_INTEN_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0; +} + +static inline bool hri_tcc_get_INTEN_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT0) >> TCC_INTENSET_FAULT0_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULT0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT0; + } +} + +static inline void hri_tcc_clear_INTEN_FAULT0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT0; +} + +static inline void hri_tcc_set_INTEN_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1; +} + +static inline bool hri_tcc_get_INTEN_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_FAULT1) >> TCC_INTENSET_FAULT1_Pos; +} + +static inline void hri_tcc_write_INTEN_FAULT1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_FAULT1; + } +} + +static inline void hri_tcc_clear_INTEN_FAULT1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_FAULT1; +} + +static inline void hri_tcc_set_INTEN_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0; +} + +static inline bool hri_tcc_get_INTEN_MC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC0) >> TCC_INTENSET_MC0_Pos; +} + +static inline void hri_tcc_write_INTEN_MC0_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC0; + } +} + +static inline void hri_tcc_clear_INTEN_MC0_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC0; +} + +static inline void hri_tcc_set_INTEN_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1; +} + +static inline bool hri_tcc_get_INTEN_MC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC1) >> TCC_INTENSET_MC1_Pos; +} + +static inline void hri_tcc_write_INTEN_MC1_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC1; + } +} + +static inline void hri_tcc_clear_INTEN_MC1_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC1; +} + +static inline void hri_tcc_set_INTEN_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2; +} + +static inline bool hri_tcc_get_INTEN_MC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC2) >> TCC_INTENSET_MC2_Pos; +} + +static inline void hri_tcc_write_INTEN_MC2_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC2; + } +} + +static inline void hri_tcc_clear_INTEN_MC2_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC2; +} + +static inline void hri_tcc_set_INTEN_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3; +} + +static inline bool hri_tcc_get_INTEN_MC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC3) >> TCC_INTENSET_MC3_Pos; +} + +static inline void hri_tcc_write_INTEN_MC3_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC3; + } +} + +static inline void hri_tcc_clear_INTEN_MC3_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC3; +} + +static inline void hri_tcc_set_INTEN_MC4_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC4; +} + +static inline bool hri_tcc_get_INTEN_MC4_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC4) >> TCC_INTENSET_MC4_Pos; +} + +static inline void hri_tcc_write_INTEN_MC4_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC4; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC4; + } +} + +static inline void hri_tcc_clear_INTEN_MC4_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC4; +} + +static inline void hri_tcc_set_INTEN_MC5_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC5; +} + +static inline bool hri_tcc_get_INTEN_MC5_bit(const void *const hw) +{ + return (((Tcc *)hw)->INTENSET.reg & TCC_INTENSET_MC5) >> TCC_INTENSET_MC5_Pos; +} + +static inline void hri_tcc_write_INTEN_MC5_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC5; + } else { + ((Tcc *)hw)->INTENSET.reg = TCC_INTENSET_MC5; + } +} + +static inline void hri_tcc_clear_INTEN_MC5_bit(const void *const hw) +{ + ((Tcc *)hw)->INTENCLR.reg = TCC_INTENSET_MC5; +} + +static inline void hri_tcc_set_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) +{ + ((Tcc *)hw)->INTENSET.reg = mask; +} + +static inline hri_tcc_intenset_reg_t hri_tcc_get_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_intenset_reg_t hri_tcc_read_INTEN_reg(const void *const hw) +{ + return ((Tcc *)hw)->INTENSET.reg; +} + +static inline void hri_tcc_write_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t data) +{ + ((Tcc *)hw)->INTENSET.reg = data; + ((Tcc *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_tcc_clear_INTEN_reg(const void *const hw, hri_tcc_intenset_reg_t mask) +{ + ((Tcc *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_tcc_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_SWRST) >> TCC_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_ENABLE) >> TCC_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CTRLB_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CTRLB) >> TCC_SYNCBUSY_CTRLB_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_STATUS_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_STATUS) >> TCC_SYNCBUSY_STATUS_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_COUNT_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_COUNT) >> TCC_SYNCBUSY_COUNT_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_PATT_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PATT) >> TCC_SYNCBUSY_PATT_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_WAVE_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_WAVE) >> TCC_SYNCBUSY_WAVE_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_PER_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_PER) >> TCC_SYNCBUSY_PER_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC0_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC0) >> TCC_SYNCBUSY_CC0_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC1_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC1) >> TCC_SYNCBUSY_CC1_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC2_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC2) >> TCC_SYNCBUSY_CC2_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC3_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC3) >> TCC_SYNCBUSY_CC3_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC4_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC4) >> TCC_SYNCBUSY_CC4_Pos; +} + +static inline bool hri_tcc_get_SYNCBUSY_CC5_bit(const void *const hw) +{ + return (((Tcc *)hw)->SYNCBUSY.reg & TCC_SYNCBUSY_CC5) >> TCC_SYNCBUSY_CC5_Pos; +} + +static inline hri_tcc_syncbusy_reg_t hri_tcc_get_SYNCBUSY_reg(const void *const hw, hri_tcc_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_tcc_syncbusy_reg_t hri_tcc_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Tcc *)hw)->SYNCBUSY.reg; +} + +static inline void hri_tcc_set_CTRLA_SWRST_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_SWRST; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_SWRST) >> TCC_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_set_CTRLA_ENABLE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ENABLE; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_ENABLE) >> TCC_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_ENABLE; + tmp |= value << TCC_CTRLA_ENABLE_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ENABLE; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ENABLE; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RUNSTDBY; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_RUNSTDBY) >> TCC_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_RUNSTDBY; + tmp |= value << TCC_CTRLA_RUNSTDBY_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RUNSTDBY; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RUNSTDBY; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_ALOCK_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_ALOCK; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_ALOCK_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_ALOCK) >> TCC_CTRLA_ALOCK_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_ALOCK_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_ALOCK; + tmp |= value << TCC_CTRLA_ALOCK_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_ALOCK_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_ALOCK; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_ALOCK_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_ALOCK; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_MSYNC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_MSYNC; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_MSYNC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_MSYNC) >> TCC_CTRLA_MSYNC_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_MSYNC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_MSYNC; + tmp |= value << TCC_CTRLA_MSYNC_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_MSYNC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_MSYNC; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_MSYNC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_MSYNC; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_DMAOS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_DMAOS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_DMAOS_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_DMAOS) >> TCC_CTRLA_DMAOS_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_DMAOS_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_DMAOS; + tmp |= value << TCC_CTRLA_DMAOS_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_DMAOS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_DMAOS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_DMAOS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_DMAOS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN0) >> TCC_CTRLA_CPTEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN0; + tmp |= value << TCC_CTRLA_CPTEN0_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN1) >> TCC_CTRLA_CPTEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN1; + tmp |= value << TCC_CTRLA_CPTEN1_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN2) >> TCC_CTRLA_CPTEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN2; + tmp |= value << TCC_CTRLA_CPTEN2_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN3) >> TCC_CTRLA_CPTEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN3; + tmp |= value << TCC_CTRLA_CPTEN3_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN4) >> TCC_CTRLA_CPTEN4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN4; + tmp |= value << TCC_CTRLA_CPTEN4_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_CPTEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_CPTEN5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_CTRLA_CPTEN5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_CPTEN5) >> TCC_CTRLA_CPTEN5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_CTRLA_CPTEN5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_CPTEN5; + tmp |= value << TCC_CTRLA_CPTEN5_Pos; + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_CPTEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_CPTEN5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_CPTEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_CPTEN5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_RESOLUTION(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_RESOLUTION(mask)) >> TCC_CTRLA_RESOLUTION_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_RESOLUTION_Msk; + tmp |= TCC_CTRLA_RESOLUTION(data); + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_RESOLUTION(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_RESOLUTION_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_RESOLUTION(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_RESOLUTION_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_RESOLUTION_Msk) >> TCC_CTRLA_RESOLUTION_Pos; + return tmp; +} + +static inline void hri_tcc_set_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCALER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCALER(mask)) >> TCC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_PRESCALER_Msk; + tmp |= TCC_CTRLA_PRESCALER(data); + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCALER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_PRESCALER_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCALER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCALER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCALER_Msk) >> TCC_CTRLA_PRESCALER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= TCC_CTRLA_PRESCSYNC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCSYNC(mask)) >> TCC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= ~TCC_CTRLA_PRESCSYNC_Msk; + tmp |= TCC_CTRLA_PRESCSYNC(data); + ((Tcc *)hw)->CTRLA.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~TCC_CTRLA_PRESCSYNC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_PRESCSYNC_bf(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= TCC_CTRLA_PRESCSYNC(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_PRESCSYNC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp = (tmp & TCC_CTRLA_PRESCSYNC_Msk) >> TCC_CTRLA_PRESCSYNC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_get_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + tmp = ((Tcc *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CTRLA_reg(const void *const hw, hri_tcc_ctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CTRLA.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ctrla_reg_t hri_tcc_read_CTRLA_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_SWRST | TCC_SYNCBUSY_ENABLE); + return ((Tcc *)hw)->CTRLA.reg; +} + +static inline void hri_tcc_set_FCTRLA_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_KEEP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_KEEP) >> TCC_FCTRLA_KEEP_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_KEEP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_KEEP; + tmp |= value << TCC_FCTRLA_KEEP_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_QUAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_QUAL) >> TCC_FCTRLA_QUAL_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_QUAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_QUAL; + tmp |= value << TCC_FCTRLA_QUAL_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_RESTART_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_RESTART) >> TCC_FCTRLA_RESTART_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_RESTART_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_RESTART; + tmp |= value << TCC_FCTRLA_RESTART_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANKPRESC) >> TCC_FCTRLA_BLANKPRESC_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLA_BLANKPRESC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_BLANKPRESC; + tmp |= value << TCC_FCTRLA_BLANKPRESC_Pos; + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_SRC(mask)) >> TCC_FCTRLA_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_SRC_Msk; + tmp |= TCC_FCTRLA_SRC(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_SRC_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_SRC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_SRC_Msk) >> TCC_FCTRLA_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANK(mask)) >> TCC_FCTRLA_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_BLANK_Msk; + tmp |= TCC_FCTRLA_BLANK(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_BLANK_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANK_Msk) >> TCC_FCTRLA_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_HALT(mask)) >> TCC_FCTRLA_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_HALT_Msk; + tmp |= TCC_FCTRLA_HALT(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_HALT_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_HALT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_HALT_Msk) >> TCC_FCTRLA_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CHSEL(mask)) >> TCC_FCTRLA_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_CHSEL_Msk; + tmp |= TCC_FCTRLA_CHSEL(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_CHSEL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CHSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CHSEL_Msk) >> TCC_FCTRLA_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CAPTURE(mask)) >> TCC_FCTRLA_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_CAPTURE_Msk; + tmp |= TCC_FCTRLA_CAPTURE(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_CAPTURE_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_CAPTURE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_CAPTURE_Msk) >> TCC_FCTRLA_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANKVAL(mask)) >> TCC_FCTRLA_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_BLANKVAL_Msk; + tmp |= TCC_FCTRLA_BLANKVAL(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_BLANKVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_BLANKVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_BLANKVAL_Msk) >> TCC_FCTRLA_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= TCC_FCTRLA_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_FILTERVAL(mask)) >> TCC_FCTRLA_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= ~TCC_FCTRLA_FILTERVAL_Msk; + tmp |= TCC_FCTRLA_FILTERVAL(data); + ((Tcc *)hw)->FCTRLA.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~TCC_FCTRLA_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_FILTERVAL_bf(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= TCC_FCTRLA_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_FILTERVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp = (tmp & TCC_FCTRLA_FILTERVAL_Msk) >> TCC_FCTRLA_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_get_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLA_reg(const void *const hw, hri_tcc_fctrla_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLA.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrla_reg_t hri_tcc_read_FCTRLA_reg(const void *const hw) +{ + return ((Tcc *)hw)->FCTRLA.reg; +} + +static inline void hri_tcc_set_FCTRLB_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_KEEP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_KEEP) >> TCC_FCTRLB_KEEP_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_KEEP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_KEEP; + tmp |= value << TCC_FCTRLB_KEEP_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_KEEP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_KEEP; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_QUAL_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_QUAL) >> TCC_FCTRLB_QUAL_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_QUAL_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_QUAL; + tmp |= value << TCC_FCTRLB_QUAL_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_QUAL_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_QUAL; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_RESTART_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_RESTART) >> TCC_FCTRLB_RESTART_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_RESTART_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_RESTART; + tmp |= value << TCC_FCTRLB_RESTART_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_RESTART_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_RESTART; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANKPRESC) >> TCC_FCTRLB_BLANKPRESC_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_FCTRLB_BLANKPRESC_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_BLANKPRESC; + tmp |= value << TCC_FCTRLB_BLANKPRESC_Pos; + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_BLANKPRESC_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKPRESC; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_SRC(mask)) >> TCC_FCTRLB_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_SRC_Msk; + tmp |= TCC_FCTRLB_SRC(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_SRC_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_SRC(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_SRC_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_SRC_Msk) >> TCC_FCTRLB_SRC_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANK(mask)) >> TCC_FCTRLB_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_BLANK_Msk; + tmp |= TCC_FCTRLB_BLANK(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_BLANK_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANK(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANK_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANK_Msk) >> TCC_FCTRLB_BLANK_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_HALT(mask)) >> TCC_FCTRLB_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_HALT_Msk; + tmp |= TCC_FCTRLB_HALT(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_HALT_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_HALT(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_HALT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_HALT_Msk) >> TCC_FCTRLB_HALT_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CHSEL(mask)) >> TCC_FCTRLB_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_CHSEL_Msk; + tmp |= TCC_FCTRLB_CHSEL(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_CHSEL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CHSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CHSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CHSEL_Msk) >> TCC_FCTRLB_CHSEL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CAPTURE(mask)) >> TCC_FCTRLB_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_CAPTURE_Msk; + tmp |= TCC_FCTRLB_CAPTURE(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_CAPTURE_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_CAPTURE(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_CAPTURE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_CAPTURE_Msk) >> TCC_FCTRLB_CAPTURE_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANKVAL(mask)) >> TCC_FCTRLB_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_BLANKVAL_Msk; + tmp |= TCC_FCTRLB_BLANKVAL(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_BLANKVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_BLANKVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_BLANKVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_BLANKVAL_Msk) >> TCC_FCTRLB_BLANKVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= TCC_FCTRLB_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_FILTERVAL(mask)) >> TCC_FCTRLB_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= ~TCC_FCTRLB_FILTERVAL_Msk; + tmp |= TCC_FCTRLB_FILTERVAL(data); + ((Tcc *)hw)->FCTRLB.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~TCC_FCTRLB_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_FILTERVAL_bf(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= TCC_FCTRLB_FILTERVAL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_FILTERVAL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp = (tmp & TCC_FCTRLB_FILTERVAL_Msk) >> TCC_FCTRLB_FILTERVAL_Pos; + return tmp; +} + +static inline void hri_tcc_set_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_get_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->FCTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_FCTRLB_reg(const void *const hw, hri_tcc_fctrlb_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->FCTRLB.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_fctrlb_reg_t hri_tcc_read_FCTRLB_reg(const void *const hw) +{ + return ((Tcc *)hw)->FCTRLB.reg; +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN0) >> TCC_WEXCTRL_DTIEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN0; + tmp |= value << TCC_WEXCTRL_DTIEN0_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN1) >> TCC_WEXCTRL_DTIEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN1; + tmp |= value << TCC_WEXCTRL_DTIEN1_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN2) >> TCC_WEXCTRL_DTIEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN2; + tmp |= value << TCC_WEXCTRL_DTIEN2_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTIEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTIEN3) >> TCC_WEXCTRL_DTIEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTIEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTIEN3; + tmp |= value << TCC_WEXCTRL_DTIEN3_Pos; + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTIEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTIEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTIEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_OTMX(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_OTMX(mask)) >> TCC_WEXCTRL_OTMX_Pos; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_OTMX_Msk; + tmp |= TCC_WEXCTRL_OTMX(data); + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_OTMX(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_OTMX_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_OTMX(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_OTMX_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_OTMX_Msk) >> TCC_WEXCTRL_OTMX_Pos; + return tmp; +} + +static inline void hri_tcc_set_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTLS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTLS(mask)) >> TCC_WEXCTRL_DTLS_Pos; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTLS_Msk; + tmp |= TCC_WEXCTRL_DTLS(data); + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTLS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTLS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTLS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTLS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTLS_Msk) >> TCC_WEXCTRL_DTLS_Pos; + return tmp; +} + +static inline void hri_tcc_set_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= TCC_WEXCTRL_DTHS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTHS(mask)) >> TCC_WEXCTRL_DTHS_Pos; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= ~TCC_WEXCTRL_DTHS_Msk; + tmp |= TCC_WEXCTRL_DTHS(data); + ((Tcc *)hw)->WEXCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~TCC_WEXCTRL_DTHS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_DTHS_bf(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= TCC_WEXCTRL_DTHS(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_DTHS_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp = (tmp & TCC_WEXCTRL_DTHS_Msk) >> TCC_WEXCTRL_DTHS_Pos; + return tmp; +} + +static inline void hri_tcc_set_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_get_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WEXCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WEXCTRL_reg(const void *const hw, hri_tcc_wexctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WEXCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wexctrl_reg_t hri_tcc_read_WEXCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->WEXCTRL.reg; +} + +static inline void hri_tcc_set_DRVCTRL_NRE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE0) >> TCC_DRVCTRL_NRE0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE0; + tmp |= value << TCC_DRVCTRL_NRE0_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE1) >> TCC_DRVCTRL_NRE1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE1; + tmp |= value << TCC_DRVCTRL_NRE1_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE2) >> TCC_DRVCTRL_NRE2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE2; + tmp |= value << TCC_DRVCTRL_NRE2_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE3) >> TCC_DRVCTRL_NRE3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE3; + tmp |= value << TCC_DRVCTRL_NRE3_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE4) >> TCC_DRVCTRL_NRE4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE4; + tmp |= value << TCC_DRVCTRL_NRE4_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE5) >> TCC_DRVCTRL_NRE5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE5; + tmp |= value << TCC_DRVCTRL_NRE5_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE6) >> TCC_DRVCTRL_NRE6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE6; + tmp |= value << TCC_DRVCTRL_NRE6_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRE7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRE7) >> TCC_DRVCTRL_NRE7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRE7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRE7; + tmp |= value << TCC_DRVCTRL_NRE7_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRE7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV0) >> TCC_DRVCTRL_NRV0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV0; + tmp |= value << TCC_DRVCTRL_NRV0_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV1) >> TCC_DRVCTRL_NRV1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV1; + tmp |= value << TCC_DRVCTRL_NRV1_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV2) >> TCC_DRVCTRL_NRV2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV2; + tmp |= value << TCC_DRVCTRL_NRV2_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV3) >> TCC_DRVCTRL_NRV3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV3; + tmp |= value << TCC_DRVCTRL_NRV3_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV4) >> TCC_DRVCTRL_NRV4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV4; + tmp |= value << TCC_DRVCTRL_NRV4_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV5) >> TCC_DRVCTRL_NRV5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV5; + tmp |= value << TCC_DRVCTRL_NRV5_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV6) >> TCC_DRVCTRL_NRV6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV6; + tmp |= value << TCC_DRVCTRL_NRV6_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_NRV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_NRV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_NRV7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_NRV7) >> TCC_DRVCTRL_NRV7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_NRV7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_NRV7; + tmp |= value << TCC_DRVCTRL_NRV7_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_NRV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_NRV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_NRV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_NRV7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN0) >> TCC_DRVCTRL_INVEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN0; + tmp |= value << TCC_DRVCTRL_INVEN0_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN1) >> TCC_DRVCTRL_INVEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN1; + tmp |= value << TCC_DRVCTRL_INVEN1_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN2) >> TCC_DRVCTRL_INVEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN2; + tmp |= value << TCC_DRVCTRL_INVEN2_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN3) >> TCC_DRVCTRL_INVEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN3; + tmp |= value << TCC_DRVCTRL_INVEN3_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN4) >> TCC_DRVCTRL_INVEN4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN4; + tmp |= value << TCC_DRVCTRL_INVEN4_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN5) >> TCC_DRVCTRL_INVEN5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN5; + tmp |= value << TCC_DRVCTRL_INVEN5_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN6_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN6) >> TCC_DRVCTRL_INVEN6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN6_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN6; + tmp |= value << TCC_DRVCTRL_INVEN6_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_INVEN7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_INVEN7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DRVCTRL_INVEN7_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_INVEN7) >> TCC_DRVCTRL_INVEN7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DRVCTRL_INVEN7_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_INVEN7; + tmp |= value << TCC_DRVCTRL_INVEN7_Pos; + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_INVEN7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_INVEN7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_INVEN7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_INVEN7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL0(mask)) >> TCC_DRVCTRL_FILTERVAL0_Pos; + return tmp; +} + +static inline void hri_tcc_write_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_FILTERVAL0_Msk; + tmp |= TCC_DRVCTRL_FILTERVAL0(data); + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL0_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL0_Msk) >> TCC_DRVCTRL_FILTERVAL0_Pos; + return tmp; +} + +static inline void hri_tcc_set_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= TCC_DRVCTRL_FILTERVAL1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL1(mask)) >> TCC_DRVCTRL_FILTERVAL1_Pos; + return tmp; +} + +static inline void hri_tcc_write_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= ~TCC_DRVCTRL_FILTERVAL1_Msk; + tmp |= TCC_DRVCTRL_FILTERVAL1(data); + ((Tcc *)hw)->DRVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~TCC_DRVCTRL_FILTERVAL1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_FILTERVAL1_bf(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= TCC_DRVCTRL_FILTERVAL1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_FILTERVAL1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp = (tmp & TCC_DRVCTRL_FILTERVAL1_Msk) >> TCC_DRVCTRL_FILTERVAL1_Pos; + return tmp; +} + +static inline void hri_tcc_set_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_get_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->DRVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DRVCTRL_reg(const void *const hw, hri_tcc_drvctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DRVCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_drvctrl_reg_t hri_tcc_read_DRVCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->DRVCTRL.reg; +} + +static inline void hri_tcc_set_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_DBGRUN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp = (tmp & TCC_DBGCTRL_DBGRUN) >> TCC_DBGCTRL_DBGRUN_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DBGCTRL_DBGRUN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp &= ~TCC_DBGCTRL_DBGRUN; + tmp |= value << TCC_DBGCTRL_DBGRUN_Pos; + ((Tcc *)hw)->DBGCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_DBGRUN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DBGCTRL_DBGRUN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_DBGRUN; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DBGCTRL_FDDBD_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg |= TCC_DBGCTRL_FDDBD; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_DBGCTRL_FDDBD_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp = (tmp & TCC_DBGCTRL_FDDBD) >> TCC_DBGCTRL_FDDBD_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_DBGCTRL_FDDBD_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp &= ~TCC_DBGCTRL_FDDBD; + tmp |= value << TCC_DBGCTRL_FDDBD_Pos; + ((Tcc *)hw)->DBGCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DBGCTRL_FDDBD_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg &= ~TCC_DBGCTRL_FDDBD; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DBGCTRL_FDDBD_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg ^= TCC_DBGCTRL_FDDBD; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_dbgctrl_reg_t hri_tcc_get_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Tcc *)hw)->DBGCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_DBGCTRL_reg(const void *const hw, hri_tcc_dbgctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->DBGCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_dbgctrl_reg_t hri_tcc_read_DBGCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->DBGCTRL.reg; +} + +static inline void hri_tcc_set_EVCTRL_OVFEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_OVFEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_OVFEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_OVFEO) >> TCC_EVCTRL_OVFEO_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_OVFEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_OVFEO; + tmp |= value << TCC_EVCTRL_OVFEO_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_OVFEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_OVFEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_OVFEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_OVFEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TRGEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TRGEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TRGEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TRGEO) >> TCC_EVCTRL_TRGEO_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TRGEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TRGEO; + tmp |= value << TCC_EVCTRL_TRGEO_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TRGEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TRGEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TRGEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TRGEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_CNTEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_CNTEO_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_CNTEO) >> TCC_EVCTRL_CNTEO_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_CNTEO_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_CNTEO; + tmp |= value << TCC_EVCTRL_CNTEO_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_CNTEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_CNTEO_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTEO; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCINV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCINV0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCINV0) >> TCC_EVCTRL_TCINV0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCINV0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCINV0; + tmp |= value << TCC_EVCTRL_TCINV0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCINV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCINV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCINV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCINV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCINV1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCINV1) >> TCC_EVCTRL_TCINV1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCINV1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCINV1; + tmp |= value << TCC_EVCTRL_TCINV1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCINV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCINV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCINV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCINV1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCEI0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCEI0) >> TCC_EVCTRL_TCEI0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCEI0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCEI0; + tmp |= value << TCC_EVCTRL_TCEI0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_TCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_TCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_TCEI1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_TCEI1) >> TCC_EVCTRL_TCEI1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_TCEI1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_TCEI1; + tmp |= value << TCC_EVCTRL_TCEI1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_TCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_TCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_TCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_TCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI0) >> TCC_EVCTRL_MCEI0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI0; + tmp |= value << TCC_EVCTRL_MCEI0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI1) >> TCC_EVCTRL_MCEI1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI1; + tmp |= value << TCC_EVCTRL_MCEI1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI2) >> TCC_EVCTRL_MCEI2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI2; + tmp |= value << TCC_EVCTRL_MCEI2_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI3) >> TCC_EVCTRL_MCEI3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI3; + tmp |= value << TCC_EVCTRL_MCEI3_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI4) >> TCC_EVCTRL_MCEI4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI4; + tmp |= value << TCC_EVCTRL_MCEI4_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEI5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEI5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEI5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEI5) >> TCC_EVCTRL_MCEI5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEI5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEI5; + tmp |= value << TCC_EVCTRL_MCEI5_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEI5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEI5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEI5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEI5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO0) >> TCC_EVCTRL_MCEO0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO0; + tmp |= value << TCC_EVCTRL_MCEO0_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO1) >> TCC_EVCTRL_MCEO1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO1; + tmp |= value << TCC_EVCTRL_MCEO1_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO2) >> TCC_EVCTRL_MCEO2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO2; + tmp |= value << TCC_EVCTRL_MCEO2_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO3) >> TCC_EVCTRL_MCEO3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO3; + tmp |= value << TCC_EVCTRL_MCEO3_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO4) >> TCC_EVCTRL_MCEO4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO4; + tmp |= value << TCC_EVCTRL_MCEO4_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_MCEO5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_MCEO5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_EVCTRL_MCEO5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_MCEO5) >> TCC_EVCTRL_MCEO5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_EVCTRL_MCEO5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_MCEO5; + tmp |= value << TCC_EVCTRL_MCEO5_Pos; + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_MCEO5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_MCEO5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_MCEO5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_MCEO5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT0(mask)) >> TCC_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_EVACT0_Msk; + tmp |= TCC_EVCTRL_EVACT0(data); + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_EVACT0_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT0(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT0_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT0_Msk) >> TCC_EVCTRL_EVACT0_Pos; + return tmp; +} + +static inline void hri_tcc_set_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_EVACT1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT1(mask)) >> TCC_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_EVACT1_Msk; + tmp |= TCC_EVCTRL_EVACT1(data); + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_EVACT1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_EVACT1_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_EVACT1(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_EVACT1_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_EVACT1_Msk) >> TCC_EVCTRL_EVACT1_Pos; + return tmp; +} + +static inline void hri_tcc_set_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= TCC_EVCTRL_CNTSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_CNTSEL(mask)) >> TCC_EVCTRL_CNTSEL_Pos; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= ~TCC_EVCTRL_CNTSEL_Msk; + tmp |= TCC_EVCTRL_CNTSEL(data); + ((Tcc *)hw)->EVCTRL.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~TCC_EVCTRL_CNTSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_CNTSEL_bf(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= TCC_EVCTRL_CNTSEL(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_CNTSEL_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp = (tmp & TCC_EVCTRL_CNTSEL_Msk) >> TCC_EVCTRL_CNTSEL_Pos; + return tmp; +} + +static inline void hri_tcc_set_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_get_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_EVCTRL_reg(const void *const hw, hri_tcc_evctrl_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->EVCTRL.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_evctrl_reg_t hri_tcc_read_EVCTRL_reg(const void *const hw) +{ + return ((Tcc *)hw)->EVCTRL.reg; +} + +static inline void hri_tcc_set_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH6_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH6_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH5_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH5_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_DITH4_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_DITH4_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT(mask)) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_write_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= ~TCC_COUNT_COUNT_Msk; + tmp |= TCC_COUNT_COUNT(data); + ((Tcc *)hw)->COUNT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_COUNT_bf(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= TCC_COUNT_COUNT(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp = (tmp & TCC_COUNT_COUNT_Msk) >> TCC_COUNT_COUNT_Pos; + return tmp; +} + +static inline void hri_tcc_set_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_get_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + tmp = ((Tcc *)hw)->COUNT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_COUNT_reg(const void *const hw, hri_tcc_count_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_COUNT_reg(const void *const hw, hri_tcc_count_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->COUNT.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_count_reg_t hri_tcc_read_COUNT_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_COUNT); + return ((Tcc *)hw)->COUNT.reg; +} + +static inline void hri_tcc_set_PATT_PGE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE0) >> TCC_PATT_PGE0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE0; + tmp |= value << TCC_PATT_PGE0_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE1) >> TCC_PATT_PGE1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE1; + tmp |= value << TCC_PATT_PGE1_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE2) >> TCC_PATT_PGE2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE2; + tmp |= value << TCC_PATT_PGE2_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE3) >> TCC_PATT_PGE3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE3; + tmp |= value << TCC_PATT_PGE3_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE4) >> TCC_PATT_PGE4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE4; + tmp |= value << TCC_PATT_PGE4_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE5) >> TCC_PATT_PGE5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE5; + tmp |= value << TCC_PATT_PGE5_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE6) >> TCC_PATT_PGE6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE6; + tmp |= value << TCC_PATT_PGE6_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGE7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGE7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGE7) >> TCC_PATT_PGE7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGE7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGE7; + tmp |= value << TCC_PATT_PGE7_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGE7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGE7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGE7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV0) >> TCC_PATT_PGV0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV0; + tmp |= value << TCC_PATT_PGV0_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV1) >> TCC_PATT_PGV1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV1; + tmp |= value << TCC_PATT_PGV1_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV2) >> TCC_PATT_PGV2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV2; + tmp |= value << TCC_PATT_PGV2_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV3) >> TCC_PATT_PGV3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV3; + tmp |= value << TCC_PATT_PGV3_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV4) >> TCC_PATT_PGV4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV4; + tmp |= value << TCC_PATT_PGV4_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV5) >> TCC_PATT_PGV5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV5; + tmp |= value << TCC_PATT_PGV5_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV6) >> TCC_PATT_PGV6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV6; + tmp |= value << TCC_PATT_PGV6_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV6; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_PGV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= TCC_PATT_PGV7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATT_PGV7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATT.reg; + tmp = (tmp & TCC_PATT_PGV7) >> TCC_PATT_PGV7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATT_PGV7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= ~TCC_PATT_PGV7; + tmp |= value << TCC_PATT_PGV7_Pos; + ((Tcc *)hw)->PATT.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_PGV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~TCC_PATT_PGV7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_PGV7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= TCC_PATT_PGV7; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_patt_reg_t hri_tcc_get_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + uint16_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->PATT.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PATT_reg(const void *const hw, hri_tcc_patt_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATT_reg(const void *const hw, hri_tcc_patt_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATT.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_patt_reg_t hri_tcc_read_PATT_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + return ((Tcc *)hw)->PATT.reg; +} + +static inline void hri_tcc_set_WAVE_CIPEREN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CIPEREN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CIPEREN_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CIPEREN) >> TCC_WAVE_CIPEREN_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CIPEREN_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CIPEREN; + tmp |= value << TCC_WAVE_CIPEREN_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CIPEREN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CIPEREN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CIPEREN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CIPEREN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN0) >> TCC_WAVE_CICCEN0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN0; + tmp |= value << TCC_WAVE_CICCEN0_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN1) >> TCC_WAVE_CICCEN1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN1; + tmp |= value << TCC_WAVE_CICCEN1_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN2) >> TCC_WAVE_CICCEN2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN2; + tmp |= value << TCC_WAVE_CICCEN2_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_CICCEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_CICCEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_CICCEN3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_CICCEN3) >> TCC_WAVE_CICCEN3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_CICCEN3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_CICCEN3; + tmp |= value << TCC_WAVE_CICCEN3_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_CICCEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_CICCEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_CICCEN3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_CICCEN3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL0) >> TCC_WAVE_POL0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL0; + tmp |= value << TCC_WAVE_POL0_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL1) >> TCC_WAVE_POL1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL1; + tmp |= value << TCC_WAVE_POL1_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL2) >> TCC_WAVE_POL2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL2; + tmp |= value << TCC_WAVE_POL2_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL3) >> TCC_WAVE_POL3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL3; + tmp |= value << TCC_WAVE_POL3_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL4_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL4) >> TCC_WAVE_POL4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL4_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL4; + tmp |= value << TCC_WAVE_POL4_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_POL5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_POL5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_POL5_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_POL5) >> TCC_WAVE_POL5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_POL5_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_POL5; + tmp |= value << TCC_WAVE_POL5_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_POL5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_POL5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_POL5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_POL5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP0_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP0) >> TCC_WAVE_SWAP0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP0_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP0; + tmp |= value << TCC_WAVE_SWAP0_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP1_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP1) >> TCC_WAVE_SWAP1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP1_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP1; + tmp |= value << TCC_WAVE_SWAP1_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP2_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP2) >> TCC_WAVE_SWAP2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP2_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP2; + tmp |= value << TCC_WAVE_SWAP2_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_SWAP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_SWAP3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_WAVE_SWAP3_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_SWAP3) >> TCC_WAVE_SWAP3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_WAVE_SWAP3_bit(const void *const hw, bool value) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_SWAP3; + tmp |= value << TCC_WAVE_SWAP3_Pos; + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_SWAP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_SWAP3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_SWAP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_SWAP3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_WAVEGEN(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_WAVEGEN(mask)) >> TCC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tcc_write_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_WAVEGEN_Msk; + tmp |= TCC_WAVE_WAVEGEN(data); + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_WAVEGEN(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_WAVEGEN_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_WAVEGEN(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_WAVEGEN_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_WAVEGEN_Msk) >> TCC_WAVE_WAVEGEN_Pos; + return tmp; +} + +static inline void hri_tcc_set_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= TCC_WAVE_RAMP(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_RAMP(mask)) >> TCC_WAVE_RAMP_Pos; + return tmp; +} + +static inline void hri_tcc_write_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= ~TCC_WAVE_RAMP_Msk; + tmp |= TCC_WAVE_RAMP(data); + ((Tcc *)hw)->WAVE.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~TCC_WAVE_RAMP(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_RAMP_bf(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= TCC_WAVE_RAMP(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_RAMP_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->WAVE.reg; + tmp = (tmp & TCC_WAVE_RAMP_Msk) >> TCC_WAVE_RAMP_Pos; + return tmp; +} + +static inline void hri_tcc_set_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_get_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->WAVE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_WAVE_reg(const void *const hw, hri_tcc_wave_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->WAVE.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_wave_reg_t hri_tcc_read_WAVE_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + return ((Tcc *)hw)->WAVE.reg; +} + +static inline void hri_tcc_set_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH4_DITHER(mask)) >> TCC_PER_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH4_DITHER_Msk; + tmp |= TCC_PER_DITH4_DITHER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH4_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_DITHER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH4_DITHER_Msk) >> TCC_PER_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH5_DITHER(mask)) >> TCC_PER_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH5_DITHER_Msk; + tmp |= TCC_PER_DITH5_DITHER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH5_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_DITHER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH5_DITHER_Msk) >> TCC_PER_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH6_DITHER(mask)) >> TCC_PER_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_DITH6_DITHER_Msk; + tmp |= TCC_PER_DITH6_DITHER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH6_DITHER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_DITHER_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_DITH6_DITHER_Msk) >> TCC_PER_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH6_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH6_PER_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH5_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH5_PER_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_DITH4_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_DITH4_PER_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER(mask)) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_write_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= ~TCC_PER_PER_Msk; + tmp |= TCC_PER_PER(data); + ((Tcc *)hw)->PER.reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_PER_bf(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= TCC_PER_PER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_PER_bf(const void *const hw) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp = (tmp & TCC_PER_PER_Msk) >> TCC_PER_PER_Pos; + return tmp; +} + +static inline void hri_tcc_set_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg |= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_get_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + tmp = ((Tcc *)hw)->PER.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PER_reg(const void *const hw, hri_tcc_per_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg = data; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg &= ~mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PER_reg(const void *const hw, hri_tcc_per_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PER.reg ^= mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_per_reg_t hri_tcc_read_PER_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_PER); + return ((Tcc *)hw)->PER.reg; +} + +static inline void hri_tcc_set_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, + hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH4_DITHER(mask)) >> TCC_CC_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH4_DITHER_Msk; + tmp |= TCC_CC_DITH4_DITHER(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH4_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_DITHER_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH4_DITHER_Msk) >> TCC_CC_DITH4_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, + hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH5_DITHER(mask)) >> TCC_CC_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH5_DITHER_Msk; + tmp |= TCC_CC_DITH5_DITHER(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH5_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_DITHER_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH5_DITHER_Msk) >> TCC_CC_DITH5_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, + hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH6_DITHER(mask)) >> TCC_CC_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_DITH6_DITHER_Msk; + tmp |= TCC_CC_DITH6_DITHER(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_DITH6_DITHER(mask); + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_DITHER_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_DITH6_DITHER_Msk) >> TCC_CC_DITH6_DITHER_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH6_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH6_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH5_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH5_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_DITH4_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_DITH4_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC(mask)) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_write_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= ~TCC_CC_CC_Msk; + tmp |= TCC_CC_CC(data); + ((Tcc *)hw)->CC[index].reg = tmp; + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_CC_bf(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= TCC_CC_CC(mask); + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_CC_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CC[index].reg; + tmp = (tmp & TCC_CC_CC_Msk) >> TCC_CC_CC_Pos; + return tmp; +} + +static inline void hri_tcc_set_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg |= mask; + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_get_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + tmp = ((Tcc *)hw)->CC[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg = data; + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg &= ~mask; + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CC_reg(const void *const hw, uint8_t index, hri_tcc_cc_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CC[index].reg ^= mask; + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_cc_reg_t hri_tcc_read_CC_reg(const void *const hw, uint8_t index) +{ + hri_tcc_wait_for_sync(hw, + TCC_SYNCBUSY_CC0 | TCC_SYNCBUSY_CC1 | TCC_SYNCBUSY_CC2 | TCC_SYNCBUSY_CC3 | TCC_SYNCBUSY_CC4 + | TCC_SYNCBUSY_CC5); + return ((Tcc *)hw)->CC[index].reg; +} + +static inline void hri_tcc_set_PATTBUF_PGEB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB0) >> TCC_PATTBUF_PGEB0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB0; + tmp |= value << TCC_PATTBUF_PGEB0_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB1) >> TCC_PATTBUF_PGEB1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB1; + tmp |= value << TCC_PATTBUF_PGEB1_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB2) >> TCC_PATTBUF_PGEB2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB2; + tmp |= value << TCC_PATTBUF_PGEB2_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB3) >> TCC_PATTBUF_PGEB3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB3; + tmp |= value << TCC_PATTBUF_PGEB3_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB4) >> TCC_PATTBUF_PGEB4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB4; + tmp |= value << TCC_PATTBUF_PGEB4_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB5) >> TCC_PATTBUF_PGEB5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB5; + tmp |= value << TCC_PATTBUF_PGEB5_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB6) >> TCC_PATTBUF_PGEB6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB6; + tmp |= value << TCC_PATTBUF_PGEB6_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGEB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGEB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGEB7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGEB7) >> TCC_PATTBUF_PGEB7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGEB7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGEB7; + tmp |= value << TCC_PATTBUF_PGEB7_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGEB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGEB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGEB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGEB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB0_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB0) >> TCC_PATTBUF_PGVB0_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB0_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB0; + tmp |= value << TCC_PATTBUF_PGVB0_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB0; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB1_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB1) >> TCC_PATTBUF_PGVB1_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB1_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB1; + tmp |= value << TCC_PATTBUF_PGVB1_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB1; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB2) >> TCC_PATTBUF_PGVB2_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB2; + tmp |= value << TCC_PATTBUF_PGVB2_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB2; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB3_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB3) >> TCC_PATTBUF_PGVB3_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB3_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB3; + tmp |= value << TCC_PATTBUF_PGVB3_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB3; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB4_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB4) >> TCC_PATTBUF_PGVB4_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB4_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB4; + tmp |= value << TCC_PATTBUF_PGVB4_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB4; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB5_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB5) >> TCC_PATTBUF_PGVB5_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB5_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB5; + tmp |= value << TCC_PATTBUF_PGVB5_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB5; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB6_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB6) >> TCC_PATTBUF_PGVB6_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB6_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB6; + tmp |= value << TCC_PATTBUF_PGVB6_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB6_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB6; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_PGVB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= TCC_PATTBUF_PGVB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_PATTBUF_PGVB7_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp = (tmp & TCC_PATTBUF_PGVB7) >> TCC_PATTBUF_PGVB7_Pos; + return (bool)tmp; +} + +static inline void hri_tcc_write_PATTBUF_PGVB7_bit(const void *const hw, bool value) +{ + uint16_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= ~TCC_PATTBUF_PGVB7; + tmp |= value << TCC_PATTBUF_PGVB7_Pos; + ((Tcc *)hw)->PATTBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_PGVB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~TCC_PATTBUF_PGVB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_PGVB7_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= TCC_PATTBUF_PGVB7; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_set_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_pattbuf_reg_t hri_tcc_get_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + uint16_t tmp; + tmp = ((Tcc *)hw)->PATTBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PATTBUF_reg(const void *const hw, hri_tcc_pattbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PATTBUF.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_pattbuf_reg_t hri_tcc_read_PATTBUF_reg(const void *const hw) +{ + return ((Tcc *)hw)->PATTBUF.reg; +} + +static inline void hri_tcc_set_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, + hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF(mask)) >> TCC_PERBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_DITH4_DITHERBUF_Msk; + tmp |= TCC_PERBUF_DITH4_DITHERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH4_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_DITHERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH4_DITHERBUF_Msk) >> TCC_PERBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, + hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF(mask)) >> TCC_PERBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_DITH5_DITHERBUF_Msk; + tmp |= TCC_PERBUF_DITH5_DITHERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH5_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_DITHERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH5_DITHERBUF_Msk) >> TCC_PERBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, + hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF(mask)) >> TCC_PERBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_DITH6_DITHERBUF_Msk; + tmp |= TCC_PERBUF_DITH6_DITHERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH6_DITHERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_DITHERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_DITH6_DITHERBUF_Msk) >> TCC_PERBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH6_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH6_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH5_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH5_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_DITH4_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_DITH4_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF(mask)) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= ~TCC_PERBUF_PERBUF_Msk; + tmp |= TCC_PERBUF_PERBUF(data); + ((Tcc *)hw)->PERBUF.reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_PERBUF_bf(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= TCC_PERBUF_PERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_PERBUF_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp = (tmp & TCC_PERBUF_PERBUF_Msk) >> TCC_PERBUF_PERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_get_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->PERBUF.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_PERBUF_reg(const void *const hw, hri_tcc_perbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->PERBUF.reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_perbuf_reg_t hri_tcc_read_PERBUF_reg(const void *const hw) +{ + return ((Tcc *)hw)->PERBUF.reg; +} + +static inline void hri_tcc_set_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF(mask)) >> TCC_CCBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_DITH5_DITHERBUF_Msk; + tmp |= TCC_CCBUF_DITH5_DITHERBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH5_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_DITHERBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH5_DITHERBUF_Msk) >> TCC_CCBUF_DITH5_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF(mask)) >> TCC_CCBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_DITH6_DITHERBUF_Msk; + tmp |= TCC_CCBUF_DITH6_DITHERBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH6_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_DITHERBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH6_DITHERBUF_Msk) >> TCC_CCBUF_DITH6_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH6_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH5_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF(mask)) >> TCC_CCBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_DITH4_DITHERBUF_Msk; + tmp |= TCC_CCBUF_DITH4_DITHERBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_DITH4_DITHERBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_DITH4_DITHERBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_DITH4_DITHERBUF_Msk) >> TCC_CCBUF_DITH4_DITHERBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, + hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF(mask)) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + uint32_t tmp; + TCC_CRITICAL_SECTION_ENTER(); + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= ~TCC_CCBUF_CCBUF_Msk; + tmp |= TCC_CCBUF_CCBUF(data); + ((Tcc *)hw)->CCBUF[index].reg = tmp; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_CCBUF_bf(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= TCC_CCBUF_CCBUF(mask); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_CCBUF_bf(const void *const hw, uint8_t index) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp = (tmp & TCC_CCBUF_CCBUF_Msk) >> TCC_CCBUF_CCBUF_Pos; + return tmp; +} + +static inline void hri_tcc_set_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg |= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_get_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + uint32_t tmp; + tmp = ((Tcc *)hw)->CCBUF[index].reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_write_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t data) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg = data; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_clear_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg &= ~mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_tcc_toggle_CCBUF_reg(const void *const hw, uint8_t index, hri_tcc_ccbuf_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->CCBUF[index].reg ^= mask; + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_ccbuf_reg_t hri_tcc_read_CCBUF_reg(const void *const hw, uint8_t index) +{ + return ((Tcc *)hw)->CCBUF[index].reg; +} + +static inline bool hri_tcc_get_STATUS_STOP_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_STOP) >> TCC_STATUS_STOP_Pos; +} + +static inline void hri_tcc_clear_STATUS_STOP_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_STOP; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_IDX_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_IDX) >> TCC_STATUS_IDX_Pos; +} + +static inline void hri_tcc_clear_STATUS_IDX_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_IDX; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_UFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_UFS) >> TCC_STATUS_UFS_Pos; +} + +static inline void hri_tcc_clear_STATUS_UFS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_UFS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_DFS_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_DFS) >> TCC_STATUS_DFS_Pos; +} + +static inline void hri_tcc_clear_STATUS_DFS_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_DFS; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_SLAVE_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_SLAVE) >> TCC_STATUS_SLAVE_Pos; +} + +static inline void hri_tcc_clear_STATUS_SLAVE_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_SLAVE; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_PATTBUFV_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PATTBUFV) >> TCC_STATUS_PATTBUFV_Pos; +} + +static inline void hri_tcc_clear_STATUS_PATTBUFV_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_PATTBUFV; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_PERBUFV_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_PERBUFV) >> TCC_STATUS_PERBUFV_Pos; +} + +static inline void hri_tcc_clear_STATUS_PERBUFV_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_PERBUFV; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTAIN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTAIN) >> TCC_STATUS_FAULTAIN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTAIN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTAIN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTBIN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTBIN) >> TCC_STATUS_FAULTBIN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTBIN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTBIN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT0IN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0IN) >> TCC_STATUS_FAULT0IN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT0IN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0IN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT1IN_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1IN) >> TCC_STATUS_FAULT1IN_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT1IN_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1IN; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTA_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTA) >> TCC_STATUS_FAULTA_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTA_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTA; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULTB_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULTB) >> TCC_STATUS_FAULTB_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULTB_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULTB; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT0_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT0) >> TCC_STATUS_FAULT0_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_FAULT1_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_FAULT1) >> TCC_STATUS_FAULT1_Pos; +} + +static inline void hri_tcc_clear_STATUS_FAULT1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_FAULT1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV0_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV0) >> TCC_STATUS_CCBUFV0_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV1_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV1) >> TCC_STATUS_CCBUFV1_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV2_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV2) >> TCC_STATUS_CCBUFV2_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV3_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV3) >> TCC_STATUS_CCBUFV3_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV4_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV4) >> TCC_STATUS_CCBUFV4_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CCBUFV5_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CCBUFV5) >> TCC_STATUS_CCBUFV5_Pos; +} + +static inline void hri_tcc_clear_STATUS_CCBUFV5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CCBUFV5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP0_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP0) >> TCC_STATUS_CMP0_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP0_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP0; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP1_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP1) >> TCC_STATUS_CMP1_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP1_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP1; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP2_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP2) >> TCC_STATUS_CMP2_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP2_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP2; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP3_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP3) >> TCC_STATUS_CMP3_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP3_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP3; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP4_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP4) >> TCC_STATUS_CMP4_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP4_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP4; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_tcc_get_STATUS_CMP5_bit(const void *const hw) +{ + return (((Tcc *)hw)->STATUS.reg & TCC_STATUS_CMP5) >> TCC_STATUS_CMP5_Pos; +} + +static inline void hri_tcc_clear_STATUS_CMP5_bit(const void *const hw) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = TCC_STATUS_CMP5; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_status_reg_t hri_tcc_get_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask) +{ + uint32_t tmp; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + tmp = ((Tcc *)hw)->STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_tcc_clear_STATUS_reg(const void *const hw, hri_tcc_status_reg_t mask) +{ + TCC_CRITICAL_SECTION_ENTER(); + ((Tcc *)hw)->STATUS.reg = mask; + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + TCC_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_tcc_status_reg_t hri_tcc_read_STATUS_reg(const void *const hw) +{ + hri_tcc_wait_for_sync(hw, TCC_SYNCBUSY_MASK); + return ((Tcc *)hw)->STATUS.reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_tcc_set_COUNT_DITH4_reg(a, b) hri_tcc_set_COUNT_reg(a, b) +#define hri_tcc_get_COUNT_DITH4_reg(a, b) hri_tcc_get_COUNT_reg(a, b) +#define hri_tcc_write_COUNT_DITH4_reg(a, b) hri_tcc_write_COUNT_reg(a, b) +#define hri_tcc_clear_COUNT_DITH4_reg(a, b) hri_tcc_clear_COUNT_reg(a, b) +#define hri_tcc_toggle_COUNT_DITH4_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b) +#define hri_tcc_read_COUNT_DITH4_reg(a) hri_tcc_read_COUNT_reg(a) +#define hri_tcc_set_COUNT_DITH5_reg(a, b) hri_tcc_set_COUNT_reg(a, b) +#define hri_tcc_get_COUNT_DITH5_reg(a, b) hri_tcc_get_COUNT_reg(a, b) +#define hri_tcc_write_COUNT_DITH5_reg(a, b) hri_tcc_write_COUNT_reg(a, b) +#define hri_tcc_clear_COUNT_DITH5_reg(a, b) hri_tcc_clear_COUNT_reg(a, b) +#define hri_tcc_toggle_COUNT_DITH5_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b) +#define hri_tcc_read_COUNT_DITH5_reg(a) hri_tcc_read_COUNT_reg(a) +#define hri_tcc_set_COUNT_DITH6_reg(a, b) hri_tcc_set_COUNT_reg(a, b) +#define hri_tcc_get_COUNT_DITH6_reg(a, b) hri_tcc_get_COUNT_reg(a, b) +#define hri_tcc_write_COUNT_DITH6_reg(a, b) hri_tcc_write_COUNT_reg(a, b) +#define hri_tcc_clear_COUNT_DITH6_reg(a, b) hri_tcc_clear_COUNT_reg(a, b) +#define hri_tcc_toggle_COUNT_DITH6_reg(a, b) hri_tcc_toggle_COUNT_reg(a, b) +#define hri_tcc_read_COUNT_DITH6_reg(a) hri_tcc_read_COUNT_reg(a) +#define hri_tcc_set_PER_DITH4_reg(a, b) hri_tcc_set_PER_reg(a, b) +#define hri_tcc_get_PER_DITH4_reg(a, b) hri_tcc_get_PER_reg(a, b) +#define hri_tcc_write_PER_DITH4_reg(a, b) hri_tcc_write_PER_reg(a, b) +#define hri_tcc_clear_PER_DITH4_reg(a, b) hri_tcc_clear_PER_reg(a, b) +#define hri_tcc_toggle_PER_DITH4_reg(a, b) hri_tcc_toggle_PER_reg(a, b) +#define hri_tcc_read_PER_DITH4_reg(a) hri_tcc_read_PER_reg(a) +#define hri_tcc_set_PER_DITH5_reg(a, b) hri_tcc_set_PER_reg(a, b) +#define hri_tcc_get_PER_DITH5_reg(a, b) hri_tcc_get_PER_reg(a, b) +#define hri_tcc_write_PER_DITH5_reg(a, b) hri_tcc_write_PER_reg(a, b) +#define hri_tcc_clear_PER_DITH5_reg(a, b) hri_tcc_clear_PER_reg(a, b) +#define hri_tcc_toggle_PER_DITH5_reg(a, b) hri_tcc_toggle_PER_reg(a, b) +#define hri_tcc_read_PER_DITH5_reg(a) hri_tcc_read_PER_reg(a) +#define hri_tcc_set_PER_DITH6_reg(a, b) hri_tcc_set_PER_reg(a, b) +#define hri_tcc_get_PER_DITH6_reg(a, b) hri_tcc_get_PER_reg(a, b) +#define hri_tcc_write_PER_DITH6_reg(a, b) hri_tcc_write_PER_reg(a, b) +#define hri_tcc_clear_PER_DITH6_reg(a, b) hri_tcc_clear_PER_reg(a, b) +#define hri_tcc_toggle_PER_DITH6_reg(a, b) hri_tcc_toggle_PER_reg(a, b) +#define hri_tcc_read_PER_DITH6_reg(a) hri_tcc_read_PER_reg(a) +#define hri_tcc_set_CC_DITH4_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c) +#define hri_tcc_get_CC_DITH4_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c) +#define hri_tcc_write_CC_DITH4_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c) +#define hri_tcc_clear_CC_DITH4_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c) +#define hri_tcc_toggle_CC_DITH4_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c) +#define hri_tcc_read_CC_DITH4_reg(a, b) hri_tcc_read_CC_reg(a, b) +#define hri_tcc_set_CC_DITH5_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c) +#define hri_tcc_get_CC_DITH5_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c) +#define hri_tcc_write_CC_DITH5_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c) +#define hri_tcc_clear_CC_DITH5_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c) +#define hri_tcc_toggle_CC_DITH5_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c) +#define hri_tcc_read_CC_DITH5_reg(a, b) hri_tcc_read_CC_reg(a, b) +#define hri_tcc_set_CC_DITH6_reg(a, b, c) hri_tcc_set_CC_reg(a, b, c) +#define hri_tcc_get_CC_DITH6_reg(a, b, c) hri_tcc_get_CC_reg(a, b, c) +#define hri_tcc_write_CC_DITH6_reg(a, b, c) hri_tcc_write_CC_reg(a, b, c) +#define hri_tcc_clear_CC_DITH6_reg(a, b, c) hri_tcc_clear_CC_reg(a, b, c) +#define hri_tcc_toggle_CC_DITH6_reg(a, b, c) hri_tcc_toggle_CC_reg(a, b, c) +#define hri_tcc_read_CC_DITH6_reg(a, b) hri_tcc_read_CC_reg(a, b) +#define hri_tcc_set_PERBUF_DITH4_reg(a, b) hri_tcc_set_PERBUF_reg(a, b) +#define hri_tcc_get_PERBUF_DITH4_reg(a, b) hri_tcc_get_PERBUF_reg(a, b) +#define hri_tcc_write_PERBUF_DITH4_reg(a, b) hri_tcc_write_PERBUF_reg(a, b) +#define hri_tcc_clear_PERBUF_DITH4_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b) +#define hri_tcc_toggle_PERBUF_DITH4_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b) +#define hri_tcc_read_PERBUF_DITH4_reg(a) hri_tcc_read_PERBUF_reg(a) +#define hri_tcc_set_PERBUF_DITH5_reg(a, b) hri_tcc_set_PERBUF_reg(a, b) +#define hri_tcc_get_PERBUF_DITH5_reg(a, b) hri_tcc_get_PERBUF_reg(a, b) +#define hri_tcc_write_PERBUF_DITH5_reg(a, b) hri_tcc_write_PERBUF_reg(a, b) +#define hri_tcc_clear_PERBUF_DITH5_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b) +#define hri_tcc_toggle_PERBUF_DITH5_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b) +#define hri_tcc_read_PERBUF_DITH5_reg(a) hri_tcc_read_PERBUF_reg(a) +#define hri_tcc_set_PERBUF_DITH6_reg(a, b) hri_tcc_set_PERBUF_reg(a, b) +#define hri_tcc_get_PERBUF_DITH6_reg(a, b) hri_tcc_get_PERBUF_reg(a, b) +#define hri_tcc_write_PERBUF_DITH6_reg(a, b) hri_tcc_write_PERBUF_reg(a, b) +#define hri_tcc_clear_PERBUF_DITH6_reg(a, b) hri_tcc_clear_PERBUF_reg(a, b) +#define hri_tcc_toggle_PERBUF_DITH6_reg(a, b) hri_tcc_toggle_PERBUF_reg(a, b) +#define hri_tcc_read_PERBUF_DITH6_reg(a) hri_tcc_read_PERBUF_reg(a) +#define hri_tcc_set_CCBUF_DITH4_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c) +#define hri_tcc_get_CCBUF_DITH4_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c) +#define hri_tcc_write_CCBUF_DITH4_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c) +#define hri_tcc_clear_CCBUF_DITH4_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c) +#define hri_tcc_toggle_CCBUF_DITH4_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c) +#define hri_tcc_read_CCBUF_DITH4_reg(a, b) hri_tcc_read_CCBUF_reg(a, b) +#define hri_tcc_set_CCBUF_DITH5_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c) +#define hri_tcc_get_CCBUF_DITH5_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c) +#define hri_tcc_write_CCBUF_DITH5_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c) +#define hri_tcc_clear_CCBUF_DITH5_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c) +#define hri_tcc_toggle_CCBUF_DITH5_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c) +#define hri_tcc_read_CCBUF_DITH5_reg(a, b) hri_tcc_read_CCBUF_reg(a, b) +#define hri_tcc_set_CCBUF_DITH6_reg(a, b, c) hri_tcc_set_CCBUF_reg(a, b, c) +#define hri_tcc_get_CCBUF_DITH6_reg(a, b, c) hri_tcc_get_CCBUF_reg(a, b, c) +#define hri_tcc_write_CCBUF_DITH6_reg(a, b, c) hri_tcc_write_CCBUF_reg(a, b, c) +#define hri_tcc_clear_CCBUF_DITH6_reg(a, b, c) hri_tcc_clear_CCBUF_reg(a, b, c) +#define hri_tcc_toggle_CCBUF_DITH6_reg(a, b, c) hri_tcc_toggle_CCBUF_reg(a, b, c) +#define hri_tcc_read_CCBUF_DITH6_reg(a, b) hri_tcc_read_CCBUF_reg(a, b) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_TCC_E54_H_INCLUDED */ +#endif /* _SAME54_TCC_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_trng_e54.h b/software/firmware/oracle_same54n19a/hri/hri_trng_e54.h new file mode 100644 index 00000000..e42caabc --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_trng_e54.h @@ -0,0 +1,380 @@ +/** + * \file + * + * \brief SAM TRNG + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_TRNG_COMPONENT_ +#ifndef _HRI_TRNG_E54_H_INCLUDED_ +#define _HRI_TRNG_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_TRNG_CRITICAL_SECTIONS) +#define TRNG_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define TRNG_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define TRNG_CRITICAL_SECTION_ENTER() +#define TRNG_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_trng_data_reg_t; +typedef uint8_t hri_trng_ctrla_reg_t; +typedef uint8_t hri_trng_evctrl_reg_t; +typedef uint8_t hri_trng_intenset_reg_t; +typedef uint8_t hri_trng_intflag_reg_t; + +static inline bool hri_trng_get_INTFLAG_DATARDY_bit(const void *const hw) +{ + return (((Trng *)hw)->INTFLAG.reg & TRNG_INTFLAG_DATARDY) >> TRNG_INTFLAG_DATARDY_Pos; +} + +static inline void hri_trng_clear_INTFLAG_DATARDY_bit(const void *const hw) +{ + ((Trng *)hw)->INTFLAG.reg = TRNG_INTFLAG_DATARDY; +} + +static inline bool hri_trng_get_interrupt_DATARDY_bit(const void *const hw) +{ + return (((Trng *)hw)->INTFLAG.reg & TRNG_INTFLAG_DATARDY) >> TRNG_INTFLAG_DATARDY_Pos; +} + +static inline void hri_trng_clear_interrupt_DATARDY_bit(const void *const hw) +{ + ((Trng *)hw)->INTFLAG.reg = TRNG_INTFLAG_DATARDY; +} + +static inline hri_trng_intflag_reg_t hri_trng_get_INTFLAG_reg(const void *const hw, hri_trng_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_trng_intflag_reg_t hri_trng_read_INTFLAG_reg(const void *const hw) +{ + return ((Trng *)hw)->INTFLAG.reg; +} + +static inline void hri_trng_clear_INTFLAG_reg(const void *const hw, hri_trng_intflag_reg_t mask) +{ + ((Trng *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_trng_set_INTEN_DATARDY_bit(const void *const hw) +{ + ((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY; +} + +static inline bool hri_trng_get_INTEN_DATARDY_bit(const void *const hw) +{ + return (((Trng *)hw)->INTENSET.reg & TRNG_INTENSET_DATARDY) >> TRNG_INTENSET_DATARDY_Pos; +} + +static inline void hri_trng_write_INTEN_DATARDY_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY; + } else { + ((Trng *)hw)->INTENSET.reg = TRNG_INTENSET_DATARDY; + } +} + +static inline void hri_trng_clear_INTEN_DATARDY_bit(const void *const hw) +{ + ((Trng *)hw)->INTENCLR.reg = TRNG_INTENSET_DATARDY; +} + +static inline void hri_trng_set_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask) +{ + ((Trng *)hw)->INTENSET.reg = mask; +} + +static inline hri_trng_intenset_reg_t hri_trng_get_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_trng_intenset_reg_t hri_trng_read_INTEN_reg(const void *const hw) +{ + return ((Trng *)hw)->INTENSET.reg; +} + +static inline void hri_trng_write_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t data) +{ + ((Trng *)hw)->INTENSET.reg = data; + ((Trng *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_trng_clear_INTEN_reg(const void *const hw, hri_trng_intenset_reg_t mask) +{ + ((Trng *)hw)->INTENCLR.reg = mask; +} + +static inline hri_trng_data_reg_t hri_trng_get_DATA_DATA_bf(const void *const hw, hri_trng_data_reg_t mask) +{ + return (((Trng *)hw)->DATA.reg & TRNG_DATA_DATA(mask)) >> TRNG_DATA_DATA_Pos; +} + +static inline hri_trng_data_reg_t hri_trng_read_DATA_DATA_bf(const void *const hw) +{ + return (((Trng *)hw)->DATA.reg & TRNG_DATA_DATA_Msk) >> TRNG_DATA_DATA_Pos; +} + +static inline hri_trng_data_reg_t hri_trng_get_DATA_reg(const void *const hw, hri_trng_data_reg_t mask) +{ + uint32_t tmp; + tmp = ((Trng *)hw)->DATA.reg; + tmp &= mask; + return tmp; +} + +static inline hri_trng_data_reg_t hri_trng_read_DATA_reg(const void *const hw) +{ + return ((Trng *)hw)->DATA.reg; +} + +static inline void hri_trng_set_CTRLA_ENABLE_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_ENABLE; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_trng_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->CTRLA.reg; + tmp = (tmp & TRNG_CTRLA_ENABLE) >> TRNG_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_trng_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TRNG_CRITICAL_SECTION_ENTER(); + tmp = ((Trng *)hw)->CTRLA.reg; + tmp &= ~TRNG_CTRLA_ENABLE; + tmp |= value << TRNG_CTRLA_ENABLE_Pos; + ((Trng *)hw)->CTRLA.reg = tmp; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_ENABLE; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_ENABLE; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg |= TRNG_CTRLA_RUNSTDBY; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_trng_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->CTRLA.reg; + tmp = (tmp & TRNG_CTRLA_RUNSTDBY) >> TRNG_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_trng_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TRNG_CRITICAL_SECTION_ENTER(); + tmp = ((Trng *)hw)->CTRLA.reg; + tmp &= ~TRNG_CTRLA_RUNSTDBY; + tmp |= value << TRNG_CTRLA_RUNSTDBY_Pos; + ((Trng *)hw)->CTRLA.reg = tmp; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg &= ~TRNG_CTRLA_RUNSTDBY; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg ^= TRNG_CTRLA_RUNSTDBY; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_set_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg |= mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_trng_ctrla_reg_t hri_trng_get_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_trng_write_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t data) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg = data; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg &= ~mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_CTRLA_reg(const void *const hw, hri_trng_ctrla_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->CTRLA.reg ^= mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_trng_ctrla_reg_t hri_trng_read_CTRLA_reg(const void *const hw) +{ + return ((Trng *)hw)->CTRLA.reg; +} + +static inline void hri_trng_set_EVCTRL_DATARDYEO_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg |= TRNG_EVCTRL_DATARDYEO; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_trng_get_EVCTRL_DATARDYEO_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->EVCTRL.reg; + tmp = (tmp & TRNG_EVCTRL_DATARDYEO) >> TRNG_EVCTRL_DATARDYEO_Pos; + return (bool)tmp; +} + +static inline void hri_trng_write_EVCTRL_DATARDYEO_bit(const void *const hw, bool value) +{ + uint8_t tmp; + TRNG_CRITICAL_SECTION_ENTER(); + tmp = ((Trng *)hw)->EVCTRL.reg; + tmp &= ~TRNG_EVCTRL_DATARDYEO; + tmp |= value << TRNG_EVCTRL_DATARDYEO_Pos; + ((Trng *)hw)->EVCTRL.reg = tmp; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_EVCTRL_DATARDYEO_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg &= ~TRNG_EVCTRL_DATARDYEO; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_EVCTRL_DATARDYEO_bit(const void *const hw) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg ^= TRNG_EVCTRL_DATARDYEO; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_set_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg |= mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_trng_evctrl_reg_t hri_trng_get_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Trng *)hw)->EVCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_trng_write_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t data) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg = data; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_clear_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg &= ~mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_trng_toggle_EVCTRL_reg(const void *const hw, hri_trng_evctrl_reg_t mask) +{ + TRNG_CRITICAL_SECTION_ENTER(); + ((Trng *)hw)->EVCTRL.reg ^= mask; + TRNG_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_trng_evctrl_reg_t hri_trng_read_EVCTRL_reg(const void *const hw) +{ + return ((Trng *)hw)->EVCTRL.reg; +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_TRNG_E54_H_INCLUDED */ +#endif /* _SAME54_TRNG_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_usb_e54.h b/software/firmware/oracle_same54n19a/hri/hri_usb_e54.h new file mode 100644 index 00000000..34b5e02e --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_usb_e54.h @@ -0,0 +1,9335 @@ +/** + * \file + * + * \brief SAM USB + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_USB_COMPONENT_ +#ifndef _HRI_USB_E54_H_INCLUDED_ +#define _HRI_USB_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_USB_CRITICAL_SECTIONS) +#define USB_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define USB_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define USB_CRITICAL_SECTION_ENTER() +#define USB_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint16_t hri_usb_padcal_reg_t; +typedef uint16_t hri_usbdesc_bank_ctrl_pipe_reg_t; +typedef uint16_t hri_usbdesc_bank_extreg_reg_t; +typedef uint16_t hri_usbdesc_bank_status_pipe_reg_t; +typedef uint16_t hri_usbdescriptordevice_extreg_reg_t; +typedef uint16_t hri_usbdescriptorhost_ctrl_pipe_reg_t; +typedef uint16_t hri_usbdescriptorhost_extreg_reg_t; +typedef uint16_t hri_usbdescriptorhost_status_pipe_reg_t; +typedef uint16_t hri_usbdevice_ctrlb_reg_t; +typedef uint16_t hri_usbdevice_epintsmry_reg_t; +typedef uint16_t hri_usbdevice_fnum_reg_t; +typedef uint16_t hri_usbdevice_intenset_reg_t; +typedef uint16_t hri_usbdevice_intflag_reg_t; +typedef uint16_t hri_usbhost_ctrlb_reg_t; +typedef uint16_t hri_usbhost_fnum_reg_t; +typedef uint16_t hri_usbhost_intenset_reg_t; +typedef uint16_t hri_usbhost_intflag_reg_t; +typedef uint16_t hri_usbhost_pintsmry_reg_t; +typedef uint32_t hri_usb_descadd_reg_t; +typedef uint32_t hri_usbdesc_bank_addr_reg_t; +typedef uint32_t hri_usbdesc_bank_pcksize_reg_t; +typedef uint32_t hri_usbdescriptordevice_addr_reg_t; +typedef uint32_t hri_usbdescriptordevice_pcksize_reg_t; +typedef uint32_t hri_usbdescriptorhost_addr_reg_t; +typedef uint32_t hri_usbdescriptorhost_pcksize_reg_t; +typedef uint8_t hri_usb_ctrla_reg_t; +typedef uint8_t hri_usb_fsmstatus_reg_t; +typedef uint8_t hri_usb_qosctrl_reg_t; +typedef uint8_t hri_usb_syncbusy_reg_t; +typedef uint8_t hri_usbdesc_bank_status_bk_reg_t; +typedef uint8_t hri_usbdescriptordevice_status_bk_reg_t; +typedef uint8_t hri_usbdescriptorhost_status_bk_reg_t; +typedef uint8_t hri_usbdevice_dadd_reg_t; +typedef uint8_t hri_usbdevice_epcfg_reg_t; +typedef uint8_t hri_usbdevice_epintenset_reg_t; +typedef uint8_t hri_usbdevice_epintflag_reg_t; +typedef uint8_t hri_usbdevice_epstatus_reg_t; +typedef uint8_t hri_usbdevice_status_reg_t; +typedef uint8_t hri_usbendpoint_epcfg_reg_t; +typedef uint8_t hri_usbendpoint_epintenset_reg_t; +typedef uint8_t hri_usbendpoint_epintflag_reg_t; +typedef uint8_t hri_usbendpoint_epstatus_reg_t; +typedef uint8_t hri_usbhost_binterval_reg_t; +typedef uint8_t hri_usbhost_flenhigh_reg_t; +typedef uint8_t hri_usbhost_hsofc_reg_t; +typedef uint8_t hri_usbhost_pcfg_reg_t; +typedef uint8_t hri_usbhost_pintenset_reg_t; +typedef uint8_t hri_usbhost_pintflag_reg_t; +typedef uint8_t hri_usbhost_pstatus_reg_t; +typedef uint8_t hri_usbhost_status_reg_t; +typedef uint8_t hri_usbpipe_binterval_reg_t; +typedef uint8_t hri_usbpipe_pcfg_reg_t; +typedef uint8_t hri_usbpipe_pintenset_reg_t; +typedef uint8_t hri_usbpipe_pintflag_reg_t; +typedef uint8_t hri_usbpipe_pstatus_reg_t; + +static inline void hri_usb_wait_for_sync(const void *const hw, hri_usb_syncbusy_reg_t reg) +{ + while (((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_usb_is_syncing(const void *const hw, hri_usb_syncbusy_reg_t reg) +{ + return ((Usb *)hw)->DEVICE.SYNCBUSY.reg & reg; +} + +static inline bool hri_usbpipe_get_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) + >> USB_HOST_PINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; +} + +static inline bool hri_usbpipe_get_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) + >> USB_HOST_PINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; +} + +static inline bool hri_usbpipe_get_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) + >> USB_HOST_PINTFLAG_TRFAIL_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; +} + +static inline bool hri_usbpipe_get_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) + >> USB_HOST_PINTFLAG_PERR_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; +} + +static inline bool hri_usbpipe_get_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) + >> USB_HOST_PINTFLAG_TXSTP_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; +} + +static inline bool hri_usbpipe_get_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) + >> USB_HOST_PINTFLAG_STALL_Pos; +} + +static inline void hri_usbpipe_clear_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; +} + +static inline bool hri_usbpipe_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) + >> USB_HOST_PINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; +} + +static inline bool hri_usbpipe_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) + >> USB_HOST_PINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; +} + +static inline bool hri_usbpipe_get_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) + >> USB_HOST_PINTFLAG_TRFAIL_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; +} + +static inline bool hri_usbpipe_get_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) + >> USB_HOST_PINTFLAG_PERR_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; +} + +static inline bool hri_usbpipe_get_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) + >> USB_HOST_PINTFLAG_TXSTP_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; +} + +static inline bool hri_usbpipe_get_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) + >> USB_HOST_PINTFLAG_STALL_Pos; +} + +static inline void hri_usbpipe_clear_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; +} + +static inline hri_usbpipe_pintflag_reg_t hri_usbpipe_get_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbpipe_pintflag_reg_t hri_usbpipe_read_PINTFLAG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg; +} + +static inline void hri_usbpipe_clear_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintflag_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTFLAG.reg = mask; +} + +static inline void hri_usbpipe_set_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; +} + +static inline bool hri_usbpipe_get_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_DTGL) + >> USB_HOST_PSTATUS_DTGL_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; +} + +static inline void hri_usbpipe_set_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; +} + +static inline bool hri_usbpipe_get_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_CURBK) + >> USB_HOST_PSTATUS_CURBK_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; +} + +static inline void hri_usbpipe_set_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; +} + +static inline bool hri_usbpipe_get_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_PFREEZE) + >> USB_HOST_PSTATUS_PFREEZE_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; +} + +static inline void hri_usbpipe_set_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; +} + +static inline bool hri_usbpipe_get_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK0RDY) + >> USB_HOST_PSTATUS_BK0RDY_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; +} + +static inline void hri_usbpipe_set_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; +} + +static inline bool hri_usbpipe_get_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK1RDY) + >> USB_HOST_PSTATUS_BK1RDY_Pos; +} + +static inline void hri_usbpipe_write_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; + } +} + +static inline void hri_usbpipe_clear_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; +} + +static inline void hri_usbpipe_set_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pstatus_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = mask; +} + +static inline hri_usbpipe_pstatus_reg_t hri_usbpipe_get_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbpipe_pstatus_reg_t hri_usbpipe_read_PSTATUS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUS.reg; +} + +static inline void hri_usbpipe_write_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pstatus_reg_t data) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSSET.reg = data; + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = ~data; +} + +static inline void hri_usbpipe_clear_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pstatus_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PSTATUSCLR.reg = mask; +} + +static inline void hri_usbpipe_set_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; +} + +static inline bool hri_usbpipe_get_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT0) + >> USB_HOST_PINTENSET_TRCPT0_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; + } +} + +static inline void hri_usbpipe_clear_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; +} + +static inline void hri_usbpipe_set_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; +} + +static inline bool hri_usbpipe_get_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT1) + >> USB_HOST_PINTENSET_TRCPT1_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; + } +} + +static inline void hri_usbpipe_clear_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; +} + +static inline void hri_usbpipe_set_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; +} + +static inline bool hri_usbpipe_get_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRFAIL) + >> USB_HOST_PINTENSET_TRFAIL_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; + } +} + +static inline void hri_usbpipe_clear_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; +} + +static inline void hri_usbpipe_set_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; +} + +static inline bool hri_usbpipe_get_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_PERR) + >> USB_HOST_PINTENSET_PERR_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; + } +} + +static inline void hri_usbpipe_clear_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; +} + +static inline void hri_usbpipe_set_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; +} + +static inline bool hri_usbpipe_get_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TXSTP) + >> USB_HOST_PINTENSET_TXSTP_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; + } +} + +static inline void hri_usbpipe_clear_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; +} + +static inline void hri_usbpipe_set_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; +} + +static inline bool hri_usbpipe_get_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_STALL) + >> USB_HOST_PINTENSET_STALL_Pos; +} + +static inline void hri_usbpipe_write_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; + } else { + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; + } +} + +static inline void hri_usbpipe_clear_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; +} + +static inline void hri_usbpipe_set_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintenset_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = mask; +} + +static inline hri_usbpipe_pintenset_reg_t hri_usbpipe_get_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbpipe_pintenset_reg_t hri_usbpipe_read_PINTEN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg; +} + +static inline void hri_usbpipe_write_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintenset_reg_t data) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENSET.reg = data; + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = ~data; +} + +static inline void hri_usbpipe_clear_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pintenset_reg_t mask) +{ + ((UsbHost *)hw)->HostPipe[submodule_index].PINTENCLR.reg = mask; +} + +static inline void hri_usbpipe_set_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbpipe_get_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_BK) >> USB_HOST_PCFG_BK_Pos; + return (bool)tmp; +} + +static inline void hri_usbpipe_write_PCFG_BK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_BK; + tmp |= value << USB_HOST_PCFG_BK_Pos; + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_set_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTOKEN(mask)) >> USB_HOST_PCFG_PTOKEN_Pos; + return tmp; +} + +static inline void hri_usbpipe_write_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_PTOKEN_Msk; + tmp |= USB_HOST_PCFG_PTOKEN(data); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTOKEN_Msk) >> USB_HOST_PCFG_PTOKEN_Pos; + return tmp; +} + +static inline void hri_usbpipe_set_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTYPE(mask)) >> USB_HOST_PCFG_PTYPE_Pos; + return tmp; +} + +static inline void hri_usbpipe_write_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_PTYPE_Msk; + tmp |= USB_HOST_PCFG_PTYPE(data); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTYPE_Msk) >> USB_HOST_PCFG_PTYPE_Pos; + return tmp; +} + +static inline void hri_usbpipe_set_PCFG_reg(const void *const hw, uint8_t submodule_index, hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_get_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbpipe_write_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_pcfg_reg_t hri_usbpipe_read_PCFG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].PCFG.reg; +} + +static inline void hri_usbpipe_set_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg |= USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_binterval_reg_t hri_usbpipe_get_BINTERVAL_BITINTERVAL_bf(const void *const hw, + uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; + tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL(mask)) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; + return tmp; +} + +static inline void hri_usbpipe_write_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; + tmp &= ~USB_HOST_BINTERVAL_BITINTERVAL_Msk; + tmp |= USB_HOST_BINTERVAL_BITINTERVAL(data); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg &= ~USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg ^= USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_binterval_reg_t hri_usbpipe_read_BINTERVAL_BITINTERVAL_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; + tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL_Msk) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; + return tmp; +} + +static inline void hri_usbpipe_set_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_binterval_reg_t hri_usbpipe_get_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbpipe_write_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_clear_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbpipe_toggle_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbpipe_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbpipe_binterval_reg_t hri_usbpipe_read_BINTERVAL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHost *)hw)->HostPipe[submodule_index].BINTERVAL.reg; +} + +static inline bool hri_usbhost_get_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) + >> USB_HOST_PINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; +} + +static inline bool hri_usbhost_get_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) + >> USB_HOST_PINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; +} + +static inline bool hri_usbhost_get_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) + >> USB_HOST_PINTFLAG_TRFAIL_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; +} + +static inline bool hri_usbhost_get_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) + >> USB_HOST_PINTFLAG_PERR_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; +} + +static inline bool hri_usbhost_get_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) + >> USB_HOST_PINTFLAG_TXSTP_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; +} + +static inline bool hri_usbhost_get_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) + >> USB_HOST_PINTFLAG_STALL_Pos; +} + +static inline void hri_usbhost_clear_PINTFLAG_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; +} + +static inline bool hri_usbhost_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT0) + >> USB_HOST_PINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbhost_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT0; +} + +static inline bool hri_usbhost_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRCPT1) + >> USB_HOST_PINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbhost_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRCPT1; +} + +static inline bool hri_usbhost_get_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TRFAIL) + >> USB_HOST_PINTFLAG_TRFAIL_Pos; +} + +static inline void hri_usbhost_clear_interrupt_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TRFAIL; +} + +static inline bool hri_usbhost_get_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_PERR) + >> USB_HOST_PINTFLAG_PERR_Pos; +} + +static inline void hri_usbhost_clear_interrupt_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_PERR; +} + +static inline bool hri_usbhost_get_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_TXSTP) + >> USB_HOST_PINTFLAG_TXSTP_Pos; +} + +static inline void hri_usbhost_clear_interrupt_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_TXSTP; +} + +static inline bool hri_usbhost_get_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg & USB_HOST_PINTFLAG_STALL) + >> USB_HOST_PINTFLAG_STALL_Pos; +} + +static inline void hri_usbhost_clear_interrupt_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = USB_HOST_PINTFLAG_STALL; +} + +static inline hri_usbhost_pintflag_reg_t hri_usbhost_get_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_pintflag_reg_t hri_usbhost_read_PINTFLAG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg; +} + +static inline void hri_usbhost_clear_PINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintflag_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTFLAG.reg = mask; +} + +static inline void hri_usbhost_set_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; +} + +static inline bool hri_usbhost_get_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_DTGL) + >> USB_HOST_PSTATUS_DTGL_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_DTGL; + } +} + +static inline void hri_usbhost_clear_PSTATUS_DTGL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_DTGL; +} + +static inline void hri_usbhost_set_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; +} + +static inline bool hri_usbhost_get_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_CURBK) + >> USB_HOST_PSTATUS_CURBK_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_CURBK; + } +} + +static inline void hri_usbhost_clear_PSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_CURBK; +} + +static inline void hri_usbhost_set_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; +} + +static inline bool hri_usbhost_get_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_PFREEZE) + >> USB_HOST_PSTATUS_PFREEZE_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_PFREEZE; + } +} + +static inline void hri_usbhost_clear_PSTATUS_PFREEZE_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_PFREEZE; +} + +static inline void hri_usbhost_set_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; +} + +static inline bool hri_usbhost_get_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK0RDY) + >> USB_HOST_PSTATUS_BK0RDY_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK0RDY; + } +} + +static inline void hri_usbhost_clear_PSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK0RDY; +} + +static inline void hri_usbhost_set_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; +} + +static inline bool hri_usbhost_get_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg & USB_HOST_PSTATUS_BK1RDY) + >> USB_HOST_PSTATUS_BK1RDY_Pos; +} + +static inline void hri_usbhost_write_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = USB_HOST_PSTATUS_BK1RDY; + } +} + +static inline void hri_usbhost_clear_PSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = USB_HOST_PSTATUS_BK1RDY; +} + +static inline void hri_usbhost_set_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pstatus_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = mask; +} + +static inline hri_usbhost_pstatus_reg_t hri_usbhost_get_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_pstatus_reg_t hri_usbhost_read_PSTATUS_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUS.reg; +} + +static inline void hri_usbhost_write_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pstatus_reg_t data) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSSET.reg = data; + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = ~data; +} + +static inline void hri_usbhost_clear_PSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pstatus_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PSTATUSCLR.reg = mask; +} + +static inline void hri_usbhost_set_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; +} + +static inline bool hri_usbhost_get_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT0) + >> USB_HOST_PINTENSET_TRCPT0_Pos; +} + +static inline void hri_usbhost_write_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT0; + } +} + +static inline void hri_usbhost_clear_PINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT0; +} + +static inline void hri_usbhost_set_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; +} + +static inline bool hri_usbhost_get_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRCPT1) + >> USB_HOST_PINTENSET_TRCPT1_Pos; +} + +static inline void hri_usbhost_write_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRCPT1; + } +} + +static inline void hri_usbhost_clear_PINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRCPT1; +} + +static inline void hri_usbhost_set_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; +} + +static inline bool hri_usbhost_get_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TRFAIL) + >> USB_HOST_PINTENSET_TRFAIL_Pos; +} + +static inline void hri_usbhost_write_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TRFAIL; + } +} + +static inline void hri_usbhost_clear_PINTEN_TRFAIL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TRFAIL; +} + +static inline void hri_usbhost_set_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; +} + +static inline bool hri_usbhost_get_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_PERR) + >> USB_HOST_PINTENSET_PERR_Pos; +} + +static inline void hri_usbhost_write_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_PERR; + } +} + +static inline void hri_usbhost_clear_PINTEN_PERR_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_PERR; +} + +static inline void hri_usbhost_set_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; +} + +static inline bool hri_usbhost_get_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_TXSTP) + >> USB_HOST_PINTENSET_TXSTP_Pos; +} + +static inline void hri_usbhost_write_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_TXSTP; + } +} + +static inline void hri_usbhost_clear_PINTEN_TXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_TXSTP; +} + +static inline void hri_usbhost_set_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; +} + +static inline bool hri_usbhost_get_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg & USB_HOST_PINTENSET_STALL) + >> USB_HOST_PINTENSET_STALL_Pos; +} + +static inline void hri_usbhost_write_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; + } else { + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = USB_HOST_PINTENSET_STALL; + } +} + +static inline void hri_usbhost_clear_PINTEN_STALL_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = USB_HOST_PINTENSET_STALL; +} + +static inline void hri_usbhost_set_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintenset_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = mask; +} + +static inline hri_usbhost_pintenset_reg_t hri_usbhost_get_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_pintenset_reg_t hri_usbhost_read_PINTEN_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg; +} + +static inline void hri_usbhost_write_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintenset_reg_t data) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENSET.reg = data; + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = ~data; +} + +static inline void hri_usbhost_clear_PINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pintenset_reg_t mask) +{ + ((Usb *)hw)->HOST.HostPipe[submodule_index].PINTENCLR.reg = mask; +} + +static inline void hri_usbhost_set_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_BK) >> USB_HOST_PCFG_BK_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_PCFG_BK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_BK; + tmp |= value << USB_HOST_PCFG_BK_Pos; + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PCFG_BK_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_BK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTOKEN(mask)) >> USB_HOST_PCFG_PTOKEN_Pos; + return tmp; +} + +static inline void hri_usbhost_write_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_PTOKEN_Msk; + tmp |= USB_HOST_PCFG_PTOKEN(data); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTOKEN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_PTOKEN_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTOKEN_Msk) >> USB_HOST_PCFG_PTOKEN_Pos; + return tmp; +} + +static inline void hri_usbhost_set_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTYPE(mask)) >> USB_HOST_PCFG_PTYPE_Pos; + return tmp; +} + +static inline void hri_usbhost_write_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp &= ~USB_HOST_PCFG_PTYPE_Msk; + tmp |= USB_HOST_PCFG_PTYPE(data); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= USB_HOST_PCFG_PTYPE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_PTYPE_bf(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp = (tmp & USB_HOST_PCFG_PTYPE_Msk) >> USB_HOST_PCFG_PTYPE_Pos; + return tmp; +} + +static inline void hri_usbhost_set_PCFG_reg(const void *const hw, uint8_t submodule_index, hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_get_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_PCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_pcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_pcfg_reg_t hri_usbhost_read_PCFG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].PCFG.reg; +} + +static inline void hri_usbhost_set_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg |= USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_binterval_reg_t hri_usbhost_get_BINTERVAL_BITINTERVAL_bf(const void *const hw, + uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; + tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL(mask)) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; + return tmp; +} + +static inline void hri_usbhost_write_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; + tmp &= ~USB_HOST_BINTERVAL_BITINTERVAL_Msk; + tmp |= USB_HOST_BINTERVAL_BITINTERVAL(data); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg &= ~USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_BINTERVAL_BITINTERVAL_bf(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg ^= USB_HOST_BINTERVAL_BITINTERVAL(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_binterval_reg_t hri_usbhost_read_BINTERVAL_BITINTERVAL_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; + tmp = (tmp & USB_HOST_BINTERVAL_BITINTERVAL_Msk) >> USB_HOST_BINTERVAL_BITINTERVAL_Pos; + return tmp; +} + +static inline void hri_usbhost_set_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_binterval_reg_t hri_usbhost_get_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_BINTERVAL_reg(const void *const hw, uint8_t submodule_index, + hri_usbhost_binterval_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_binterval_reg_t hri_usbhost_read_BINTERVAL_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->HOST.HostPipe[submodule_index].BINTERVAL.reg; +} + +static inline void hri_usbhostdescbank_set_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg |= USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_get_ADDR_ADDR_bf(const void *const hw, + hri_usbdesc_bank_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->ADDR.reg; + tmp = (tmp & USB_HOST_ADDR_ADDR(mask)) >> USB_HOST_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->ADDR.reg; + tmp &= ~USB_HOST_ADDR_ADDR_Msk; + tmp |= USB_HOST_ADDR_ADDR(data); + ((UsbHostDescBank *)hw)->ADDR.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg &= ~USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg ^= USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->ADDR.reg; + tmp = (tmp & USB_HOST_ADDR_ADDR_Msk) >> USB_HOST_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_get_ADDR_reg(const void *const hw, + hri_usbdesc_bank_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_write_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->ADDR.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbhostdescbank_read_ADDR_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->ADDR.reg; +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_AUTO_ZLP) >> USB_HOST_PCKSIZE_AUTO_ZLP_Pos; + return (bool)tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_AUTO_ZLP; + tmp |= value << USB_HOST_PCKSIZE_AUTO_ZLP_Pos; + ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbhostdescbank_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT(mask)) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_BYTE_COUNT_Msk; + tmp |= USB_HOST_PCKSIZE_BYTE_COUNT(data); + ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT_Msk) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbhostdescbank_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk; + tmp |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(data); + ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbhostdescbank_get_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_SIZE(mask)) >> USB_HOST_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_SIZE_Msk; + tmp |= USB_HOST_PCKSIZE_SIZE(data); + ((UsbHostDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_SIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_SIZE_Msk) >> USB_HOST_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_get_PCKSIZE_reg(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescBank *)hw)->PCKSIZE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_write_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->PCKSIZE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbhostdescbank_read_PCKSIZE_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->PCKSIZE.reg; +} + +static inline void hri_usbhostdescbank_set_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg |= USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_get_EXTREG_SUBPID_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_SUBPID(mask)) >> USB_HOST_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp &= ~USB_HOST_EXTREG_SUBPID_Msk; + tmp |= USB_HOST_EXTREG_SUBPID(data); + ((UsbHostDescBank *)hw)->EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg &= ~USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg ^= USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_SUBPID_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_SUBPID_Msk) >> USB_HOST_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg |= USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t +hri_usbhostdescbank_get_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_VARIABLE(mask)) >> USB_HOST_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp &= ~USB_HOST_EXTREG_VARIABLE_Msk; + tmp |= USB_HOST_EXTREG_VARIABLE(data); + ((UsbHostDescBank *)hw)->EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg &= ~USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg ^= USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_VARIABLE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_VARIABLE_Msk) >> USB_HOST_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_get_EXTREG_reg(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->EXTREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_write_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->EXTREG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbhostdescbank_read_EXTREG_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->EXTREG.reg; +} + +static inline void hri_usbhostdescbank_set_CTRL_PIPE_PDADDR_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t +hri_usbhostdescbank_get_CTRL_PIPE_PDADDR_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR(mask)) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_CTRL_PIPE_PDADDR_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PDADDR_Msk; + tmp |= USB_HOST_CTRL_PIPE_PDADDR(data); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PDADDR_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PDADDR_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PDADDR_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR_Msk) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_CTRL_PIPE_PEPNUM_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t +hri_usbhostdescbank_get_CTRL_PIPE_PEPNUM_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM(mask)) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_CTRL_PIPE_PEPNUM_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PEPNUM_Msk; + tmp |= USB_HOST_CTRL_PIPE_PEPNUM(data); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PEPNUM_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PEPNUM_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PEPNUM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM_Msk) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_CTRL_PIPE_PERMAX_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t +hri_usbhostdescbank_get_CTRL_PIPE_PERMAX_bf(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX(mask)) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_write_CTRL_PIPE_PERMAX_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PERMAX_Msk; + tmp |= USB_HOST_CTRL_PIPE_PERMAX(data); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_CTRL_PIPE_PERMAX_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_PERMAX_bf(const void *const hw, + hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_PERMAX_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX_Msk) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; + return tmp; +} + +static inline void hri_usbhostdescbank_set_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t +hri_usbhostdescbank_get_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_write_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_clear_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescbank_toggle_CTRL_PIPE_reg(const void *const hw, hri_usbdesc_bank_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->CTRL_PIPE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_ctrl_pipe_reg_t hri_usbhostdescbank_read_CTRL_PIPE_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->CTRL_PIPE.reg; +} + +static inline bool hri_usbhostdescbank_get_STATUS_BK_CRCERR_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_BK.reg & USB_HOST_STATUS_BK_CRCERR) >> USB_HOST_STATUS_BK_CRCERR_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_BK_CRCERR_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_BK.reg = USB_HOST_STATUS_BK_CRCERR; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_BK_ERRORFLOW_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_BK.reg & USB_HOST_STATUS_BK_ERRORFLOW) >> USB_HOST_STATUS_BK_ERRORFLOW_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_BK.reg = USB_HOST_STATUS_BK_ERRORFLOW; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_bk_reg_t +hri_usbhostdescbank_get_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHostDescBank *)hw)->STATUS_BK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_clear_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_BK.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_bk_reg_t hri_usbhostdescbank_read_STATUS_BK_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->STATUS_BK.reg; +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_DTGLER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DTGLER) >> USB_HOST_STATUS_PIPE_DTGLER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_DTGLER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DTGLER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_DAPIDER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DAPIDER) + >> USB_HOST_STATUS_PIPE_DAPIDER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_DAPIDER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DAPIDER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_PIDER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_PIDER) >> USB_HOST_STATUS_PIPE_PIDER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_PIDER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_PIDER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_TOUTER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_TOUTER) >> USB_HOST_STATUS_PIPE_TOUTER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_TOUTER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_TOUTER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescbank_get_STATUS_PIPE_CRC16ER_bit(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_CRC16ER) + >> USB_HOST_STATUS_PIPE_CRC16ER_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_CRC16ER_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_CRC16ER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_pipe_reg_t +hri_usbhostdescbank_get_STATUS_PIPE_ERCNT_bf(const void *const hw, hri_usbdesc_bank_status_pipe_reg_t mask) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT(mask)) + >> USB_HOST_STATUS_PIPE_ERCNT_Pos; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_ERCNT_bf(const void *const hw, + hri_usbdesc_bank_status_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_ERCNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_pipe_reg_t hri_usbhostdescbank_read_STATUS_PIPE_ERCNT_bf(const void *const hw) +{ + return (((UsbHostDescBank *)hw)->STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT_Msk) + >> USB_HOST_STATUS_PIPE_ERCNT_Pos; +} + +static inline hri_usbdesc_bank_status_pipe_reg_t +hri_usbhostdescbank_get_STATUS_PIPE_reg(const void *const hw, hri_usbdesc_bank_status_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescBank *)hw)->STATUS_PIPE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescbank_clear_STATUS_PIPE_reg(const void *const hw, + hri_usbdesc_bank_status_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescBank *)hw)->STATUS_PIPE.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_pipe_reg_t hri_usbhostdescbank_read_STATUS_PIPE_reg(const void *const hw) +{ + return ((UsbHostDescBank *)hw)->STATUS_PIPE.reg; +} + +static inline void hri_usbhostdescriptor_set_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg |= USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_addr_reg_t +hri_usbhostdescriptor_get_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; + tmp = (tmp & USB_HOST_ADDR_ADDR(mask)) >> USB_HOST_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; + tmp &= ~USB_HOST_ADDR_ADDR_Msk; + tmp |= USB_HOST_ADDR_ADDR(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg &= ~USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg ^= USB_HOST_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_addr_reg_t hri_usbhostdescriptor_read_ADDR_ADDR_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; + tmp = (tmp & USB_HOST_ADDR_ADDR_Msk) >> USB_HOST_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_addr_reg_t +hri_usbhostdescriptor_get_ADDR_reg(const void *const hw, uint8_t submodule_index, hri_usbdescriptorhost_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_addr_reg_t hri_usbhostdescriptor_read_ADDR_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].ADDR.reg; +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_AUTO_ZLP) >> USB_HOST_PCKSIZE_AUTO_ZLP_Pos; + return (bool)tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_AUTO_ZLP; + tmp |= value << USB_HOST_PCKSIZE_AUTO_ZLP_Pos; + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t +hri_usbhostdescriptor_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT(mask)) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_BYTE_COUNT_Msk; + tmp |= USB_HOST_PCKSIZE_BYTE_COUNT(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t +hri_usbhostdescriptor_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_BYTE_COUNT_Msk) >> USB_HOST_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t +hri_usbhostdescriptor_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk; + tmp |= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t +hri_usbhostdescriptor_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_HOST_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t +hri_usbhostdescriptor_get_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_SIZE(mask)) >> USB_HOST_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_HOST_PCKSIZE_SIZE_Msk; + tmp |= USB_HOST_PCKSIZE_SIZE(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= USB_HOST_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t hri_usbhostdescriptor_read_PCKSIZE_SIZE_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_HOST_PCKSIZE_SIZE_Msk) >> USB_HOST_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t +hri_usbhostdescriptor_get_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_pcksize_reg_t hri_usbhostdescriptor_read_PCKSIZE_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].PCKSIZE.reg; +} + +static inline void hri_usbhostdescriptor_set_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_extreg_reg_t +hri_usbhostdescriptor_get_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_SUBPID(mask)) >> USB_HOST_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp &= ~USB_HOST_EXTREG_SUBPID_Msk; + tmp |= USB_HOST_EXTREG_SUBPID(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= USB_HOST_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_SUBPID_bf(const void *const hw, + uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_SUBPID_Msk) >> USB_HOST_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_extreg_reg_t +hri_usbhostdescriptor_get_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_VARIABLE(mask)) >> USB_HOST_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp &= ~USB_HOST_EXTREG_VARIABLE_Msk; + tmp |= USB_HOST_EXTREG_VARIABLE(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= USB_HOST_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_VARIABLE_bf(const void *const hw, + uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_HOST_EXTREG_VARIABLE_Msk) >> USB_HOST_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_extreg_reg_t +hri_usbhostdescriptor_get_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_extreg_reg_t hri_usbhostdescriptor_read_EXTREG_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].EXTREG.reg; +} + +static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_get_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR(mask)) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PDADDR_Msk; + tmp |= USB_HOST_CTRL_PIPE_PDADDR(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PDADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_read_CTRL_PIPE_PDADDR_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PDADDR_Msk) >> USB_HOST_CTRL_PIPE_PDADDR_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_get_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM(mask)) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PEPNUM_Msk; + tmp |= USB_HOST_CTRL_PIPE_PEPNUM(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PEPNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_read_CTRL_PIPE_PEPNUM_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PEPNUM_Msk) >> USB_HOST_CTRL_PIPE_PEPNUM_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_get_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX(mask)) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp &= ~USB_HOST_CTRL_PIPE_PERMAX_Msk; + tmp |= USB_HOST_CTRL_PIPE_PERMAX(data); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= USB_HOST_CTRL_PIPE_PERMAX(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_read_CTRL_PIPE_PERMAX_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp = (tmp & USB_HOST_CTRL_PIPE_PERMAX_Msk) >> USB_HOST_CTRL_PIPE_PERMAX_Pos; + return tmp; +} + +static inline void hri_usbhostdescriptor_set_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t +hri_usbhostdescriptor_get_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_write_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_clear_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhostdescriptor_toggle_CTRL_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_ctrl_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_ctrl_pipe_reg_t hri_usbhostdescriptor_read_CTRL_PIPE_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].CTRL_PIPE.reg; +} + +static inline bool hri_usbhostdescriptor_get_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg & USB_HOST_STATUS_BK_CRCERR) + >> USB_HOST_STATUS_BK_CRCERR_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = USB_HOST_STATUS_BK_CRCERR; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg & USB_HOST_STATUS_BK_ERRORFLOW) + >> USB_HOST_STATUS_BK_ERRORFLOW_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = USB_HOST_STATUS_BK_ERRORFLOW; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_status_bk_reg_t +hri_usbhostdescriptor_get_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_status_bk_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_status_bk_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_status_bk_reg_t hri_usbhostdescriptor_read_STATUS_BK_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_BK.reg; +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_DTGLER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DTGLER) + >> USB_HOST_STATUS_PIPE_DTGLER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_DTGLER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DTGLER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_DAPIDER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_DAPIDER) + >> USB_HOST_STATUS_PIPE_DAPIDER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_DAPIDER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_DAPIDER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_PIDER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_PIDER) + >> USB_HOST_STATUS_PIPE_PIDER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_PIDER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_PIDER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_TOUTER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_TOUTER) + >> USB_HOST_STATUS_PIPE_TOUTER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_TOUTER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_TOUTER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhostdescriptor_get_STATUS_PIPE_CRC16ER_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_CRC16ER) + >> USB_HOST_STATUS_PIPE_CRC16ER_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_CRC16ER_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_CRC16ER; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_status_pipe_reg_t +hri_usbhostdescriptor_get_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_status_pipe_reg_t mask) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT(mask)) + >> USB_HOST_STATUS_PIPE_ERCNT_Pos; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_status_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = USB_HOST_STATUS_PIPE_ERCNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_status_pipe_reg_t +hri_usbhostdescriptor_read_STATUS_PIPE_ERCNT_bf(const void *const hw, uint8_t submodule_index) +{ + return (((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg & USB_HOST_STATUS_PIPE_ERCNT_Msk) + >> USB_HOST_STATUS_PIPE_ERCNT_Pos; +} + +static inline hri_usbdescriptorhost_status_pipe_reg_t +hri_usbhostdescriptor_get_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_status_pipe_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhostdescriptor_clear_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptorhost_status_pipe_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptorhost_status_pipe_reg_t +hri_usbhostdescriptor_read_STATUS_PIPE_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbHostDescriptor *)hw)->HostDescBank[submodule_index].STATUS_PIPE.reg; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) + >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) + >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) + >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) + >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) + >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) + >> USB_DEVICE_EPINTFLAG_STALL0_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; +} + +static inline bool hri_usbendpoint_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) + >> USB_DEVICE_EPINTFLAG_STALL1_Pos; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; +} + +static inline bool hri_usbendpoint_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) + >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; +} + +static inline bool hri_usbendpoint_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) + >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; +} + +static inline bool hri_usbendpoint_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) + >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; +} + +static inline bool hri_usbendpoint_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) + >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; +} + +static inline bool hri_usbendpoint_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) + >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; +} + +static inline bool hri_usbendpoint_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) + >> USB_DEVICE_EPINTFLAG_STALL0_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; +} + +static inline bool hri_usbendpoint_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) + >> USB_DEVICE_EPINTFLAG_STALL1_Pos; +} + +static inline void hri_usbendpoint_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; +} + +static inline hri_usbendpoint_epintflag_reg_t +hri_usbendpoint_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbendpoint_epintflag_reg_t hri_usbendpoint_read_EPINTFLAG_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg; +} + +static inline void hri_usbendpoint_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epintflag_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask; +} + +static inline void hri_usbendpoint_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT) + >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; +} + +static inline void hri_usbendpoint_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN) + >> USB_DEVICE_EPSTATUS_DTGLIN_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; +} + +static inline void hri_usbendpoint_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK) + >> USB_DEVICE_EPSTATUS_CURBK_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; +} + +static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0) + >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; +} + +static inline void hri_usbendpoint_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1) + >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; +} + +static inline void hri_usbendpoint_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY) + >> USB_DEVICE_EPSTATUS_BK0RDY_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; +} + +static inline void hri_usbendpoint_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; +} + +static inline bool hri_usbendpoint_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY) + >> USB_DEVICE_EPSTATUS_BK1RDY_Pos; +} + +static inline void hri_usbendpoint_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; + } +} + +static inline void hri_usbendpoint_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; +} + +static inline void hri_usbendpoint_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epstatus_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask; +} + +static inline hri_usbendpoint_epstatus_reg_t +hri_usbendpoint_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbendpoint_epstatus_reg_t hri_usbendpoint_read_EPSTATUS_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUS.reg; +} + +static inline void hri_usbendpoint_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epstatus_reg_t data) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data; + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data; +} + +static inline void hri_usbendpoint_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epstatus_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask; +} + +static inline void hri_usbendpoint_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; +} + +static inline bool hri_usbendpoint_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0) + >> USB_DEVICE_EPINTENSET_TRCPT0_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; +} + +static inline void hri_usbendpoint_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; +} + +static inline bool hri_usbendpoint_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1) + >> USB_DEVICE_EPINTENSET_TRCPT1_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; +} + +static inline void hri_usbendpoint_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; +} + +static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0) + >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; +} + +static inline void hri_usbendpoint_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; +} + +static inline bool hri_usbendpoint_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1) + >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; +} + +static inline void hri_usbendpoint_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; +} + +static inline bool hri_usbendpoint_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP) + >> USB_DEVICE_EPINTENSET_RXSTP_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; +} + +static inline void hri_usbendpoint_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; +} + +static inline bool hri_usbendpoint_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0) + >> USB_DEVICE_EPINTENSET_STALL0_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; +} + +static inline void hri_usbendpoint_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; +} + +static inline bool hri_usbendpoint_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1) + >> USB_DEVICE_EPINTENSET_STALL1_Pos; +} + +static inline void hri_usbendpoint_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; + } else { + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; + } +} + +static inline void hri_usbendpoint_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; +} + +static inline void hri_usbendpoint_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epintenset_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = mask; +} + +static inline hri_usbendpoint_epintenset_reg_t +hri_usbendpoint_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbendpoint_epintenset_reg_t hri_usbendpoint_read_EPINTEN_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg; +} + +static inline void hri_usbendpoint_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epintenset_reg_t data) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENSET.reg = data; + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data; +} + +static inline void hri_usbendpoint_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epintenset_reg_t mask) +{ + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask; +} + +static inline void hri_usbendpoint_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbendpoint_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos; + return (bool)tmp; +} + +static inline void hri_usbendpoint_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_NYETDIS; + tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos; + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t +hri_usbendpoint_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; + return tmp; +} + +static inline void hri_usbendpoint_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk; + tmp |= USB_DEVICE_EPCFG_EPTYPE0(data); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE0_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; + return tmp; +} + +static inline void hri_usbendpoint_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t +hri_usbendpoint_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbendpoint_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; + return tmp; +} + +static inline void hri_usbendpoint_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk; + tmp |= USB_DEVICE_EPCFG_EPTYPE1(data); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_EPTYPE1_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; + return tmp; +} + +static inline void hri_usbendpoint_set_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_get_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbendpoint_write_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbendpoint_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbendpoint_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbendpoint_epcfg_reg_t hri_usbendpoint_read_EPCFG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbDevice *)hw)->DeviceEndpoint[submodule_index].EPCFG.reg; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) + >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) + >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) + >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) + >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) + >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) + >> USB_DEVICE_EPINTFLAG_STALL0_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; +} + +static inline bool hri_usbdevice_get_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) + >> USB_DEVICE_EPINTFLAG_STALL1_Pos; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; +} + +static inline bool hri_usbdevice_get_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT0) + >> USB_DEVICE_EPINTFLAG_TRCPT0_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT0; +} + +static inline bool hri_usbdevice_get_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRCPT1) + >> USB_DEVICE_EPINTFLAG_TRCPT1_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRCPT1; +} + +static inline bool hri_usbdevice_get_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL0) + >> USB_DEVICE_EPINTFLAG_TRFAIL0_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL0; +} + +static inline bool hri_usbdevice_get_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_TRFAIL1) + >> USB_DEVICE_EPINTFLAG_TRFAIL1_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_TRFAIL1; +} + +static inline bool hri_usbdevice_get_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_RXSTP) + >> USB_DEVICE_EPINTFLAG_RXSTP_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_RXSTP; +} + +static inline bool hri_usbdevice_get_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL0) + >> USB_DEVICE_EPINTFLAG_STALL0_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL0; +} + +static inline bool hri_usbdevice_get_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg & USB_DEVICE_EPINTFLAG_STALL1) + >> USB_DEVICE_EPINTFLAG_STALL1_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = USB_DEVICE_EPINTFLAG_STALL1; +} + +static inline hri_usbdevice_epintflag_reg_t +hri_usbdevice_get_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_epintflag_reg_t hri_usbdevice_read_EPINTFLAG_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg; +} + +static inline void hri_usbdevice_clear_EPINTFLAG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epintflag_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTFLAG.reg = mask; +} + +static inline void hri_usbdevice_set_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; +} + +static inline bool hri_usbdevice_get_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLOUT) + >> USB_DEVICE_EPSTATUS_DTGLOUT_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLOUT; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_DTGLOUT_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLOUT; +} + +static inline void hri_usbdevice_set_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; +} + +static inline bool hri_usbdevice_get_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_DTGLIN) + >> USB_DEVICE_EPSTATUS_DTGLIN_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_DTGLIN; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_DTGLIN_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_DTGLIN; +} + +static inline void hri_usbdevice_set_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; +} + +static inline bool hri_usbdevice_get_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_CURBK) + >> USB_DEVICE_EPSTATUS_CURBK_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_CURBK; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_CURBK_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_CURBK; +} + +static inline void hri_usbdevice_set_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; +} + +static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ0) + >> USB_DEVICE_EPSTATUS_STALLRQ0_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ0; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ0; +} + +static inline void hri_usbdevice_set_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; +} + +static inline bool hri_usbdevice_get_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_STALLRQ1) + >> USB_DEVICE_EPSTATUS_STALLRQ1_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_STALLRQ1; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_STALLRQ1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_STALLRQ1; +} + +static inline void hri_usbdevice_set_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; +} + +static inline bool hri_usbdevice_get_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK0RDY) + >> USB_DEVICE_EPSTATUS_BK0RDY_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK0RDY; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_BK0RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK0RDY; +} + +static inline void hri_usbdevice_set_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; +} + +static inline bool hri_usbdevice_get_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg & USB_DEVICE_EPSTATUS_BK1RDY) + >> USB_DEVICE_EPSTATUS_BK1RDY_Pos; +} + +static inline void hri_usbdevice_write_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = USB_DEVICE_EPSTATUS_BK1RDY; + } +} + +static inline void hri_usbdevice_clear_EPSTATUS_BK1RDY_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = USB_DEVICE_EPSTATUS_BK1RDY; +} + +static inline void hri_usbdevice_set_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epstatus_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = mask; +} + +static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_get_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_epstatus_reg_t hri_usbdevice_read_EPSTATUS_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUS.reg; +} + +static inline void hri_usbdevice_write_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epstatus_reg_t data) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSSET.reg = data; + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = ~data; +} + +static inline void hri_usbdevice_clear_EPSTATUS_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epstatus_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPSTATUSCLR.reg = mask; +} + +static inline void hri_usbdevice_set_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; +} + +static inline bool hri_usbdevice_get_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT0) + >> USB_DEVICE_EPINTENSET_TRCPT0_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT0; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_TRCPT0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT0; +} + +static inline void hri_usbdevice_set_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; +} + +static inline bool hri_usbdevice_get_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRCPT1) + >> USB_DEVICE_EPINTENSET_TRCPT1_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRCPT1; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_TRCPT1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRCPT1; +} + +static inline void hri_usbdevice_set_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; +} + +static inline bool hri_usbdevice_get_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL0) + >> USB_DEVICE_EPINTENSET_TRFAIL0_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL0; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_TRFAIL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL0; +} + +static inline void hri_usbdevice_set_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; +} + +static inline bool hri_usbdevice_get_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_TRFAIL1) + >> USB_DEVICE_EPINTENSET_TRFAIL1_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_TRFAIL1; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_TRFAIL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_TRFAIL1; +} + +static inline void hri_usbdevice_set_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; +} + +static inline bool hri_usbdevice_get_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_RXSTP) + >> USB_DEVICE_EPINTENSET_RXSTP_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_RXSTP; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_RXSTP_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_RXSTP; +} + +static inline void hri_usbdevice_set_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; +} + +static inline bool hri_usbdevice_get_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL0) + >> USB_DEVICE_EPINTENSET_STALL0_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL0; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_STALL0_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL0; +} + +static inline void hri_usbdevice_set_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; +} + +static inline bool hri_usbdevice_get_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + return (((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg & USB_DEVICE_EPINTENSET_STALL1) + >> USB_DEVICE_EPINTENSET_STALL1_Pos; +} + +static inline void hri_usbdevice_write_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; + } else { + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = USB_DEVICE_EPINTENSET_STALL1; + } +} + +static inline void hri_usbdevice_clear_EPINTEN_STALL1_bit(const void *const hw, uint8_t submodule_index) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = USB_DEVICE_EPINTENSET_STALL1; +} + +static inline void hri_usbdevice_set_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epintenset_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = mask; +} + +static inline hri_usbdevice_epintenset_reg_t +hri_usbdevice_get_EPINTEN_reg(const void *const hw, uint8_t submodule_index, hri_usbdevice_epintenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_epintenset_reg_t hri_usbdevice_read_EPINTEN_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg; +} + +static inline void hri_usbdevice_write_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epintenset_reg_t data) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENSET.reg = data; + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = ~data; +} + +static inline void hri_usbdevice_clear_EPINTEN_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epintenset_reg_t mask) +{ + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPINTENCLR.reg = mask; +} + +static inline void hri_usbdevice_set_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_NYETDIS) >> USB_DEVICE_EPCFG_NYETDIS_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_NYETDIS; + tmp |= value << USB_DEVICE_EPCFG_NYETDIS_Pos; + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_EPCFG_NYETDIS_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_NYETDIS; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t +hri_usbdevice_get_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0(mask)) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_EPTYPE0_Msk; + tmp |= USB_DEVICE_EPCFG_EPTYPE0(data); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_EPCFG_EPTYPE0_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE0(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE0_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE0_Msk) >> USB_DEVICE_EPCFG_EPTYPE0_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t +hri_usbdevice_get_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, hri_usbdevice_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1(mask)) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= ~USB_DEVICE_EPCFG_EPTYPE1_Msk; + tmp |= USB_DEVICE_EPCFG_EPTYPE1(data); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_EPCFG_EPTYPE1_bf(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= USB_DEVICE_EPCFG_EPTYPE1(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_EPTYPE1_bf(const void *const hw, + uint8_t submodule_index) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp = (tmp & USB_DEVICE_EPCFG_EPTYPE1_Msk) >> USB_DEVICE_EPCFG_EPTYPE1_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_get_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevice_write_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_EPCFG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdevice_epcfg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_epcfg_reg_t hri_usbdevice_read_EPCFG_reg(const void *const hw, uint8_t submodule_index) +{ + return ((Usb *)hw)->DEVICE.DeviceEndpoint[submodule_index].EPCFG.reg; +} + +static inline bool hri_usbdevice_get_INTFLAG_SUSPEND_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_SUSPEND_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND; +} + +static inline bool hri_usbdevice_get_INTFLAG_MSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_MSOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF; +} + +static inline bool hri_usbdevice_get_INTFLAG_SOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_SOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF; +} + +static inline bool hri_usbdevice_get_INTFLAG_EORST_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_EORST_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST; +} + +static inline bool hri_usbdevice_get_INTFLAG_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP; +} + +static inline bool hri_usbdevice_get_INTFLAG_EORSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_EORSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM; +} + +static inline bool hri_usbdevice_get_INTFLAG_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM; +} + +static inline bool hri_usbdevice_get_INTFLAG_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER; +} + +static inline bool hri_usbdevice_get_INTFLAG_LPMNYET_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_LPMNYET_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET; +} + +static inline bool hri_usbdevice_get_INTFLAG_LPMSUSP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos; +} + +static inline void hri_usbdevice_clear_INTFLAG_LPMSUSP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP; +} + +static inline bool hri_usbdevice_get_interrupt_SUSPEND_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SUSPEND) >> USB_DEVICE_INTFLAG_SUSPEND_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_SUSPEND_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SUSPEND; +} + +static inline bool hri_usbdevice_get_interrupt_MSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_MSOF) >> USB_DEVICE_INTFLAG_MSOF_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_MSOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_MSOF; +} + +static inline bool hri_usbdevice_get_interrupt_SOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_SOF) >> USB_DEVICE_INTFLAG_SOF_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_SOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_SOF; +} + +static inline bool hri_usbdevice_get_interrupt_EORST_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORST) >> USB_DEVICE_INTFLAG_EORST_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_EORST_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORST; +} + +static inline bool hri_usbdevice_get_interrupt_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_WAKEUP) >> USB_DEVICE_INTFLAG_WAKEUP_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_WAKEUP; +} + +static inline bool hri_usbdevice_get_interrupt_EORSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_EORSM) >> USB_DEVICE_INTFLAG_EORSM_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_EORSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_EORSM; +} + +static inline bool hri_usbdevice_get_interrupt_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_UPRSM) >> USB_DEVICE_INTFLAG_UPRSM_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_UPRSM; +} + +static inline bool hri_usbdevice_get_interrupt_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_RAMACER) >> USB_DEVICE_INTFLAG_RAMACER_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_RAMACER; +} + +static inline bool hri_usbdevice_get_interrupt_LPMNYET_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMNYET) >> USB_DEVICE_INTFLAG_LPMNYET_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_LPMNYET_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMNYET; +} + +static inline bool hri_usbdevice_get_interrupt_LPMSUSP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTFLAG.reg & USB_DEVICE_INTFLAG_LPMSUSP) >> USB_DEVICE_INTFLAG_LPMSUSP_Pos; +} + +static inline void hri_usbdevice_clear_interrupt_LPMSUSP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = USB_DEVICE_INTFLAG_LPMSUSP; +} + +static inline hri_usbdevice_intflag_reg_t hri_usbdevice_get_INTFLAG_reg(const void *const hw, + hri_usbdevice_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_intflag_reg_t hri_usbdevice_read_INTFLAG_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.INTFLAG.reg; +} + +static inline void hri_usbdevice_clear_INTFLAG_reg(const void *const hw, hri_usbdevice_intflag_reg_t mask) +{ + ((Usb *)hw)->DEVICE.INTFLAG.reg = mask; +} + +static inline bool hri_usbhost_get_INTFLAG_HSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_HSOF) >> USB_HOST_INTFLAG_HSOF_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_HSOF_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF; +} + +static inline bool hri_usbhost_get_INTFLAG_RST_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RST) >> USB_HOST_INTFLAG_RST_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_RST_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST; +} + +static inline bool hri_usbhost_get_INTFLAG_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_WAKEUP) >> USB_HOST_INTFLAG_WAKEUP_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP; +} + +static inline bool hri_usbhost_get_INTFLAG_DNRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DNRSM) >> USB_HOST_INTFLAG_DNRSM_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_DNRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM; +} + +static inline bool hri_usbhost_get_INTFLAG_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_UPRSM) >> USB_HOST_INTFLAG_UPRSM_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM; +} + +static inline bool hri_usbhost_get_INTFLAG_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RAMACER) >> USB_HOST_INTFLAG_RAMACER_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER; +} + +static inline bool hri_usbhost_get_INTFLAG_DCONN_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DCONN) >> USB_HOST_INTFLAG_DCONN_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_DCONN_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN; +} + +static inline bool hri_usbhost_get_INTFLAG_DDISC_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DDISC) >> USB_HOST_INTFLAG_DDISC_Pos; +} + +static inline void hri_usbhost_clear_INTFLAG_DDISC_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC; +} + +static inline bool hri_usbhost_get_interrupt_HSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_HSOF) >> USB_HOST_INTFLAG_HSOF_Pos; +} + +static inline void hri_usbhost_clear_interrupt_HSOF_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_HSOF; +} + +static inline bool hri_usbhost_get_interrupt_RST_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RST) >> USB_HOST_INTFLAG_RST_Pos; +} + +static inline void hri_usbhost_clear_interrupt_RST_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RST; +} + +static inline bool hri_usbhost_get_interrupt_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_WAKEUP) >> USB_HOST_INTFLAG_WAKEUP_Pos; +} + +static inline void hri_usbhost_clear_interrupt_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_WAKEUP; +} + +static inline bool hri_usbhost_get_interrupt_DNRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DNRSM) >> USB_HOST_INTFLAG_DNRSM_Pos; +} + +static inline void hri_usbhost_clear_interrupt_DNRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DNRSM; +} + +static inline bool hri_usbhost_get_interrupt_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_UPRSM) >> USB_HOST_INTFLAG_UPRSM_Pos; +} + +static inline void hri_usbhost_clear_interrupt_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_UPRSM; +} + +static inline bool hri_usbhost_get_interrupt_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_RAMACER) >> USB_HOST_INTFLAG_RAMACER_Pos; +} + +static inline void hri_usbhost_clear_interrupt_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_RAMACER; +} + +static inline bool hri_usbhost_get_interrupt_DCONN_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DCONN) >> USB_HOST_INTFLAG_DCONN_Pos; +} + +static inline void hri_usbhost_clear_interrupt_DCONN_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DCONN; +} + +static inline bool hri_usbhost_get_interrupt_DDISC_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTFLAG.reg & USB_HOST_INTFLAG_DDISC) >> USB_HOST_INTFLAG_DDISC_Pos; +} + +static inline void hri_usbhost_clear_interrupt_DDISC_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = USB_HOST_INTFLAG_DDISC; +} + +static inline hri_usbhost_intflag_reg_t hri_usbhost_get_INTFLAG_reg(const void *const hw, + hri_usbhost_intflag_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_intflag_reg_t hri_usbhost_read_INTFLAG_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.INTFLAG.reg; +} + +static inline void hri_usbhost_clear_INTFLAG_reg(const void *const hw, hri_usbhost_intflag_reg_t mask) +{ + ((Usb *)hw)->HOST.INTFLAG.reg = mask; +} + +static inline void hri_usbdevice_set_INTEN_SUSPEND_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND; +} + +static inline bool hri_usbdevice_get_INTEN_SUSPEND_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SUSPEND) >> USB_DEVICE_INTENSET_SUSPEND_Pos; +} + +static inline void hri_usbdevice_write_INTEN_SUSPEND_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SUSPEND; + } +} + +static inline void hri_usbdevice_clear_INTEN_SUSPEND_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SUSPEND; +} + +static inline void hri_usbdevice_set_INTEN_MSOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF; +} + +static inline bool hri_usbdevice_get_INTEN_MSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_MSOF) >> USB_DEVICE_INTENSET_MSOF_Pos; +} + +static inline void hri_usbdevice_write_INTEN_MSOF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_MSOF; + } +} + +static inline void hri_usbdevice_clear_INTEN_MSOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_MSOF; +} + +static inline void hri_usbdevice_set_INTEN_SOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF; +} + +static inline bool hri_usbdevice_get_INTEN_SOF_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_SOF) >> USB_DEVICE_INTENSET_SOF_Pos; +} + +static inline void hri_usbdevice_write_INTEN_SOF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_SOF; + } +} + +static inline void hri_usbdevice_clear_INTEN_SOF_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_SOF; +} + +static inline void hri_usbdevice_set_INTEN_EORST_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST; +} + +static inline bool hri_usbdevice_get_INTEN_EORST_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORST) >> USB_DEVICE_INTENSET_EORST_Pos; +} + +static inline void hri_usbdevice_write_INTEN_EORST_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORST; + } +} + +static inline void hri_usbdevice_clear_INTEN_EORST_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORST; +} + +static inline void hri_usbdevice_set_INTEN_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP; +} + +static inline bool hri_usbdevice_get_INTEN_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_WAKEUP) >> USB_DEVICE_INTENSET_WAKEUP_Pos; +} + +static inline void hri_usbdevice_write_INTEN_WAKEUP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_WAKEUP; + } +} + +static inline void hri_usbdevice_clear_INTEN_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_WAKEUP; +} + +static inline void hri_usbdevice_set_INTEN_EORSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM; +} + +static inline bool hri_usbdevice_get_INTEN_EORSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_EORSM) >> USB_DEVICE_INTENSET_EORSM_Pos; +} + +static inline void hri_usbdevice_write_INTEN_EORSM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_EORSM; + } +} + +static inline void hri_usbdevice_clear_INTEN_EORSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_EORSM; +} + +static inline void hri_usbdevice_set_INTEN_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM; +} + +static inline bool hri_usbdevice_get_INTEN_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_UPRSM) >> USB_DEVICE_INTENSET_UPRSM_Pos; +} + +static inline void hri_usbdevice_write_INTEN_UPRSM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_UPRSM; + } +} + +static inline void hri_usbdevice_clear_INTEN_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_UPRSM; +} + +static inline void hri_usbdevice_set_INTEN_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER; +} + +static inline bool hri_usbdevice_get_INTEN_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_RAMACER) >> USB_DEVICE_INTENSET_RAMACER_Pos; +} + +static inline void hri_usbdevice_write_INTEN_RAMACER_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_RAMACER; + } +} + +static inline void hri_usbdevice_clear_INTEN_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_RAMACER; +} + +static inline void hri_usbdevice_set_INTEN_LPMNYET_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET; +} + +static inline bool hri_usbdevice_get_INTEN_LPMNYET_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMNYET) >> USB_DEVICE_INTENSET_LPMNYET_Pos; +} + +static inline void hri_usbdevice_write_INTEN_LPMNYET_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMNYET; + } +} + +static inline void hri_usbdevice_clear_INTEN_LPMNYET_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMNYET; +} + +static inline void hri_usbdevice_set_INTEN_LPMSUSP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP; +} + +static inline bool hri_usbdevice_get_INTEN_LPMSUSP_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.INTENSET.reg & USB_DEVICE_INTENSET_LPMSUSP) >> USB_DEVICE_INTENSET_LPMSUSP_Pos; +} + +static inline void hri_usbdevice_write_INTEN_LPMSUSP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP; + } else { + ((Usb *)hw)->DEVICE.INTENSET.reg = USB_DEVICE_INTENSET_LPMSUSP; + } +} + +static inline void hri_usbdevice_clear_INTEN_LPMSUSP_bit(const void *const hw) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = USB_DEVICE_INTENSET_LPMSUSP; +} + +static inline void hri_usbdevice_set_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = mask; +} + +static inline hri_usbdevice_intenset_reg_t hri_usbdevice_get_INTEN_reg(const void *const hw, + hri_usbdevice_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_intenset_reg_t hri_usbdevice_read_INTEN_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.INTENSET.reg; +} + +static inline void hri_usbdevice_write_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t data) +{ + ((Usb *)hw)->DEVICE.INTENSET.reg = data; + ((Usb *)hw)->DEVICE.INTENCLR.reg = ~data; +} + +static inline void hri_usbdevice_clear_INTEN_reg(const void *const hw, hri_usbdevice_intenset_reg_t mask) +{ + ((Usb *)hw)->DEVICE.INTENCLR.reg = mask; +} + +static inline void hri_usbhost_set_INTEN_HSOF_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF; +} + +static inline bool hri_usbhost_get_INTEN_HSOF_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_HSOF) >> USB_HOST_INTENSET_HSOF_Pos; +} + +static inline void hri_usbhost_write_INTEN_HSOF_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_HSOF; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_HSOF; + } +} + +static inline void hri_usbhost_clear_INTEN_HSOF_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_HSOF; +} + +static inline void hri_usbhost_set_INTEN_RST_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RST; +} + +static inline bool hri_usbhost_get_INTEN_RST_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_RST) >> USB_HOST_INTENSET_RST_Pos; +} + +static inline void hri_usbhost_write_INTEN_RST_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RST; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RST; + } +} + +static inline void hri_usbhost_clear_INTEN_RST_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RST; +} + +static inline void hri_usbhost_set_INTEN_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP; +} + +static inline bool hri_usbhost_get_INTEN_WAKEUP_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_WAKEUP) >> USB_HOST_INTENSET_WAKEUP_Pos; +} + +static inline void hri_usbhost_write_INTEN_WAKEUP_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_WAKEUP; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_WAKEUP; + } +} + +static inline void hri_usbhost_clear_INTEN_WAKEUP_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_WAKEUP; +} + +static inline void hri_usbhost_set_INTEN_DNRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM; +} + +static inline bool hri_usbhost_get_INTEN_DNRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DNRSM) >> USB_HOST_INTENSET_DNRSM_Pos; +} + +static inline void hri_usbhost_write_INTEN_DNRSM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DNRSM; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DNRSM; + } +} + +static inline void hri_usbhost_clear_INTEN_DNRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DNRSM; +} + +static inline void hri_usbhost_set_INTEN_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM; +} + +static inline bool hri_usbhost_get_INTEN_UPRSM_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_UPRSM) >> USB_HOST_INTENSET_UPRSM_Pos; +} + +static inline void hri_usbhost_write_INTEN_UPRSM_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_UPRSM; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_UPRSM; + } +} + +static inline void hri_usbhost_clear_INTEN_UPRSM_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_UPRSM; +} + +static inline void hri_usbhost_set_INTEN_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER; +} + +static inline bool hri_usbhost_get_INTEN_RAMACER_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_RAMACER) >> USB_HOST_INTENSET_RAMACER_Pos; +} + +static inline void hri_usbhost_write_INTEN_RAMACER_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RAMACER; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_RAMACER; + } +} + +static inline void hri_usbhost_clear_INTEN_RAMACER_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_RAMACER; +} + +static inline void hri_usbhost_set_INTEN_DCONN_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN; +} + +static inline bool hri_usbhost_get_INTEN_DCONN_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DCONN) >> USB_HOST_INTENSET_DCONN_Pos; +} + +static inline void hri_usbhost_write_INTEN_DCONN_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DCONN; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DCONN; + } +} + +static inline void hri_usbhost_clear_INTEN_DCONN_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DCONN; +} + +static inline void hri_usbhost_set_INTEN_DDISC_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC; +} + +static inline bool hri_usbhost_get_INTEN_DDISC_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.INTENSET.reg & USB_HOST_INTENSET_DDISC) >> USB_HOST_INTENSET_DDISC_Pos; +} + +static inline void hri_usbhost_write_INTEN_DDISC_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DDISC; + } else { + ((Usb *)hw)->HOST.INTENSET.reg = USB_HOST_INTENSET_DDISC; + } +} + +static inline void hri_usbhost_clear_INTEN_DDISC_bit(const void *const hw) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = USB_HOST_INTENSET_DDISC; +} + +static inline void hri_usbhost_set_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t mask) +{ + ((Usb *)hw)->HOST.INTENSET.reg = mask; +} + +static inline hri_usbhost_intenset_reg_t hri_usbhost_get_INTEN_reg(const void *const hw, + hri_usbhost_intenset_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_intenset_reg_t hri_usbhost_read_INTEN_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.INTENSET.reg; +} + +static inline void hri_usbhost_write_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t data) +{ + ((Usb *)hw)->HOST.INTENSET.reg = data; + ((Usb *)hw)->HOST.INTENCLR.reg = ~data; +} + +static inline void hri_usbhost_clear_INTEN_reg(const void *const hw, hri_usbhost_intenset_reg_t mask) +{ + ((Usb *)hw)->HOST.INTENCLR.reg = mask; +} + +static inline bool hri_usb_get_SYNCBUSY_SWRST_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.SYNCBUSY.reg & USB_SYNCBUSY_SWRST) >> USB_SYNCBUSY_SWRST_Pos; +} + +static inline bool hri_usb_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.SYNCBUSY.reg & USB_SYNCBUSY_ENABLE) >> USB_SYNCBUSY_ENABLE_Pos; +} + +static inline hri_usb_syncbusy_reg_t hri_usb_get_SYNCBUSY_reg(const void *const hw, hri_usb_syncbusy_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usb_syncbusy_reg_t hri_usb_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.SYNCBUSY.reg; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_SPEED_bf(const void *const hw, + hri_usbdevice_status_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED(mask)) >> USB_DEVICE_STATUS_SPEED_Pos; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_SPEED_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_SPEED_Msk) >> USB_DEVICE_STATUS_SPEED_Pos; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_LINESTATE_bf(const void *const hw, + hri_usbdevice_status_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE(mask)) >> USB_DEVICE_STATUS_LINESTATE_Pos; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_LINESTATE_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.STATUS.reg & USB_DEVICE_STATUS_LINESTATE_Msk) >> USB_DEVICE_STATUS_LINESTATE_Pos; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_get_STATUS_reg(const void *const hw, + hri_usbdevice_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_status_reg_t hri_usbdevice_read_STATUS_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.STATUS.reg; +} + +static inline hri_usb_fsmstatus_reg_t hri_usb_get_FSMSTATUS_FSMSTATE_bf(const void *const hw, + hri_usb_fsmstatus_reg_t mask) +{ + return (((Usb *)hw)->HOST.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE(mask)) >> USB_FSMSTATUS_FSMSTATE_Pos; +} + +static inline hri_usb_fsmstatus_reg_t hri_usb_read_FSMSTATUS_FSMSTATE_bf(const void *const hw) +{ + return (((Usb *)hw)->HOST.FSMSTATUS.reg & USB_FSMSTATUS_FSMSTATE_Msk) >> USB_FSMSTATUS_FSMSTATE_Pos; +} + +static inline hri_usb_fsmstatus_reg_t hri_usb_get_FSMSTATUS_reg(const void *const hw, hri_usb_fsmstatus_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.FSMSTATUS.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usb_fsmstatus_reg_t hri_usb_read_FSMSTATUS_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.FSMSTATUS.reg; +} + +static inline bool hri_usbdevice_get_FNUM_FNCERR_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNCERR) >> USB_DEVICE_FNUM_FNCERR_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_MFNUM_bf(const void *const hw, + hri_usbdevice_fnum_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM(mask)) >> USB_DEVICE_FNUM_MFNUM_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_MFNUM_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_MFNUM_Msk) >> USB_DEVICE_FNUM_MFNUM_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_FNUM_bf(const void *const hw, + hri_usbdevice_fnum_reg_t mask) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM(mask)) >> USB_DEVICE_FNUM_FNUM_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_FNUM_bf(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.FNUM.reg & USB_DEVICE_FNUM_FNUM_Msk) >> USB_DEVICE_FNUM_FNUM_Pos; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_get_FNUM_reg(const void *const hw, hri_usbdevice_fnum_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.FNUM.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_fnum_reg_t hri_usbdevice_read_FNUM_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.FNUM.reg; +} + +static inline hri_usbhost_flenhigh_reg_t hri_usbhost_get_FLENHIGH_FLENHIGH_bf(const void *const hw, + hri_usbhost_flenhigh_reg_t mask) +{ + return (((Usb *)hw)->HOST.FLENHIGH.reg & USB_HOST_FLENHIGH_FLENHIGH(mask)) >> USB_HOST_FLENHIGH_FLENHIGH_Pos; +} + +static inline hri_usbhost_flenhigh_reg_t hri_usbhost_read_FLENHIGH_FLENHIGH_bf(const void *const hw) +{ + return (((Usb *)hw)->HOST.FLENHIGH.reg & USB_HOST_FLENHIGH_FLENHIGH_Msk) >> USB_HOST_FLENHIGH_FLENHIGH_Pos; +} + +static inline hri_usbhost_flenhigh_reg_t hri_usbhost_get_FLENHIGH_reg(const void *const hw, + hri_usbhost_flenhigh_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.FLENHIGH.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_flenhigh_reg_t hri_usbhost_read_FLENHIGH_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.FLENHIGH.reg; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT0_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT0) >> USB_DEVICE_EPINTSMRY_EPINT0_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT1_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT1) >> USB_DEVICE_EPINTSMRY_EPINT1_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT2_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT2) >> USB_DEVICE_EPINTSMRY_EPINT2_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT3_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT3) >> USB_DEVICE_EPINTSMRY_EPINT3_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT4_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT4) >> USB_DEVICE_EPINTSMRY_EPINT4_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT5_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT5) >> USB_DEVICE_EPINTSMRY_EPINT5_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT6_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT6) >> USB_DEVICE_EPINTSMRY_EPINT6_Pos; +} + +static inline bool hri_usbdevice_get_EPINTSMRY_EPINT7_bit(const void *const hw) +{ + return (((Usb *)hw)->DEVICE.EPINTSMRY.reg & USB_DEVICE_EPINTSMRY_EPINT7) >> USB_DEVICE_EPINTSMRY_EPINT7_Pos; +} + +static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_get_EPINTSMRY_reg(const void *const hw, + hri_usbdevice_epintsmry_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.EPINTSMRY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbdevice_epintsmry_reg_t hri_usbdevice_read_EPINTSMRY_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.EPINTSMRY.reg; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT0_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT0) >> USB_HOST_PINTSMRY_EPINT0_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT1_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT1) >> USB_HOST_PINTSMRY_EPINT1_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT2_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT2) >> USB_HOST_PINTSMRY_EPINT2_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT3_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT3) >> USB_HOST_PINTSMRY_EPINT3_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT4_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT4) >> USB_HOST_PINTSMRY_EPINT4_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT5_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT5) >> USB_HOST_PINTSMRY_EPINT5_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT6_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT6) >> USB_HOST_PINTSMRY_EPINT6_Pos; +} + +static inline bool hri_usbhost_get_PINTSMRY_EPINT7_bit(const void *const hw) +{ + return (((Usb *)hw)->HOST.PINTSMRY.reg & USB_HOST_PINTSMRY_EPINT7) >> USB_HOST_PINTSMRY_EPINT7_Pos; +} + +static inline hri_usbhost_pintsmry_reg_t hri_usbhost_get_PINTSMRY_reg(const void *const hw, + hri_usbhost_pintsmry_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PINTSMRY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_usbhost_pintsmry_reg_t hri_usbhost_read_PINTSMRY_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.PINTSMRY.reg; +} + +static inline void hri_usb_set_CTRLA_SWRST_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_SWRST; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usb_get_CTRLA_SWRST_bit(const void *const hw) +{ + uint8_t tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp = (tmp & USB_CTRLA_SWRST) >> USB_CTRLA_SWRST_Pos; + return (bool)tmp; +} + +static inline void hri_usb_set_CTRLA_ENABLE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_ENABLE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usb_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp = (tmp & USB_CTRLA_ENABLE) >> USB_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_usb_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp &= ~USB_CTRLA_ENABLE; + tmp |= value << USB_CTRLA_ENABLE_Pos; + ((Usb *)hw)->HOST.CTRLA.reg = tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_ENABLE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_ENABLE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_SWRST | USB_SYNCBUSY_ENABLE); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_set_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_RUNSTDBY; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usb_get_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp = (tmp & USB_CTRLA_RUNSTDBY) >> USB_CTRLA_RUNSTDBY_Pos; + return (bool)tmp; +} + +static inline void hri_usb_write_CTRLA_RUNSTDBY_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp &= ~USB_CTRLA_RUNSTDBY; + tmp |= value << USB_CTRLA_RUNSTDBY_Pos; + ((Usb *)hw)->HOST.CTRLA.reg = tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_RUNSTDBY; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_CTRLA_RUNSTDBY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_RUNSTDBY; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_set_CTRLA_MODE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg |= USB_CTRLA_MODE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usb_get_CTRLA_MODE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp = (tmp & USB_CTRLA_MODE) >> USB_CTRLA_MODE_Pos; + return (bool)tmp; +} + +static inline void hri_usb_write_CTRLA_MODE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp &= ~USB_CTRLA_MODE; + tmp |= value << USB_CTRLA_MODE_Pos; + ((Usb *)hw)->HOST.CTRLA.reg = tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_CTRLA_MODE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg &= ~USB_CTRLA_MODE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_CTRLA_MODE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg ^= USB_CTRLA_MODE; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_set_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg |= mask; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_ctrla_reg_t hri_usb_get_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + tmp = ((Usb *)hw)->HOST.CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usb_write_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg = data; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg &= ~mask; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_CTRLA_reg(const void *const hw, hri_usb_ctrla_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLA.reg ^= mask; + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_ctrla_reg_t hri_usb_read_CTRLA_reg(const void *const hw) +{ + hri_usb_wait_for_sync(hw, USB_SYNCBUSY_MASK); + return ((Usb *)hw)->HOST.CTRLA.reg; +} + +static inline void hri_usb_set_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg |= USB_QOSCTRL_CQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_CQOS(mask)) >> USB_QOSCTRL_CQOS_Pos; + return tmp; +} + +static inline void hri_usb_write_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp &= ~USB_QOSCTRL_CQOS_Msk; + tmp |= USB_QOSCTRL_CQOS(data); + ((Usb *)hw)->HOST.QOSCTRL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg &= ~USB_QOSCTRL_CQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_QOSCTRL_CQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg ^= USB_QOSCTRL_CQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_CQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_CQOS_Msk) >> USB_QOSCTRL_CQOS_Pos; + return tmp; +} + +static inline void hri_usb_set_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg |= USB_QOSCTRL_DQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_DQOS(mask)) >> USB_QOSCTRL_DQOS_Pos; + return tmp; +} + +static inline void hri_usb_write_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp &= ~USB_QOSCTRL_DQOS_Msk; + tmp |= USB_QOSCTRL_DQOS(data); + ((Usb *)hw)->HOST.QOSCTRL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg &= ~USB_QOSCTRL_DQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_QOSCTRL_DQOS_bf(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg ^= USB_QOSCTRL_DQOS(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_DQOS_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp = (tmp & USB_QOSCTRL_DQOS_Msk) >> USB_QOSCTRL_DQOS_Pos; + return tmp; +} + +static inline void hri_usb_set_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_get_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.QOSCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usb_write_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_QOSCTRL_reg(const void *const hw, hri_usb_qosctrl_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.QOSCTRL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_qosctrl_reg_t hri_usb_read_QOSCTRL_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.QOSCTRL.reg; +} + +static inline void hri_usbdevice_set_CTRLB_DETACH_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_DETACH; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_DETACH_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_DETACH) >> USB_DEVICE_CTRLB_DETACH_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_DETACH_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_DETACH; + tmp |= value << USB_DEVICE_CTRLB_DETACH_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_DETACH_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_DETACH; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_DETACH_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_DETACH; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_UPRSM_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_UPRSM; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_UPRSM_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_UPRSM) >> USB_DEVICE_CTRLB_UPRSM_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_UPRSM_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_UPRSM; + tmp |= value << USB_DEVICE_CTRLB_UPRSM_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_UPRSM_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_UPRSM; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_UPRSM_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_UPRSM; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_NREPLY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_NREPLY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_NREPLY_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_NREPLY) >> USB_DEVICE_CTRLB_NREPLY_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_NREPLY_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_NREPLY; + tmp |= value << USB_DEVICE_CTRLB_NREPLY_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_NREPLY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_NREPLY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_NREPLY_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_NREPLY; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_TSTJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_TSTJ) >> USB_DEVICE_CTRLB_TSTJ_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_TSTJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_TSTJ; + tmp |= value << USB_DEVICE_CTRLB_TSTJ_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_TSTK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_TSTK) >> USB_DEVICE_CTRLB_TSTK_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_TSTK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_TSTK; + tmp |= value << USB_DEVICE_CTRLB_TSTK_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_TSTPCKT_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_TSTPCKT; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_TSTPCKT_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_TSTPCKT) >> USB_DEVICE_CTRLB_TSTPCKT_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_TSTPCKT_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_TSTPCKT; + tmp |= value << USB_DEVICE_CTRLB_TSTPCKT_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_TSTPCKT_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_TSTPCKT; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_TSTPCKT_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_TSTPCKT; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_OPMODE2_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_OPMODE2; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_OPMODE2_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_OPMODE2) >> USB_DEVICE_CTRLB_OPMODE2_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_OPMODE2_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_OPMODE2; + tmp |= value << USB_DEVICE_CTRLB_OPMODE2_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_OPMODE2_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_OPMODE2; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_OPMODE2_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_OPMODE2; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_GNAK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_GNAK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_CTRLB_GNAK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_GNAK) >> USB_DEVICE_CTRLB_GNAK_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_CTRLB_GNAK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_GNAK; + tmp |= value << USB_DEVICE_CTRLB_GNAK_Pos; + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_GNAK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_GNAK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_GNAK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_GNAK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_SPDCONF_bf(const void *const hw, + hri_usbdevice_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF(mask)) >> USB_DEVICE_CTRLB_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_SPDCONF_Msk; + tmp |= USB_DEVICE_CTRLB_SPDCONF(data); + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_SPDCONF_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_SPDCONF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_SPDCONF_Msk) >> USB_DEVICE_CTRLB_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= USB_DEVICE_CTRLB_LPMHDSK(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_LPMHDSK_bf(const void *const hw, + hri_usbdevice_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK(mask)) >> USB_DEVICE_CTRLB_LPMHDSK_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= ~USB_DEVICE_CTRLB_LPMHDSK_Msk; + tmp |= USB_DEVICE_CTRLB_LPMHDSK(data); + ((Usb *)hw)->DEVICE.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~USB_DEVICE_CTRLB_LPMHDSK(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_LPMHDSK_bf(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= USB_DEVICE_CTRLB_LPMHDSK(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_LPMHDSK_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp = (tmp & USB_DEVICE_CTRLB_LPMHDSK_Msk) >> USB_DEVICE_CTRLB_LPMHDSK_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_get_CTRLB_reg(const void *const hw, + hri_usbdevice_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->DEVICE.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevice_write_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_CTRLB_reg(const void *const hw, hri_usbdevice_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.CTRLB.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_ctrlb_reg_t hri_usbdevice_read_CTRLB_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.CTRLB.reg; +} + +static inline void hri_usbhost_set_CTRLB_RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_RESUME_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_RESUME) >> USB_HOST_CTRLB_RESUME_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_RESUME_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_RESUME; + tmp |= value << USB_HOST_CTRLB_RESUME_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_AUTORESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_AUTORESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_AUTORESUME_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_AUTORESUME) >> USB_HOST_CTRLB_AUTORESUME_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_AUTORESUME_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_AUTORESUME; + tmp |= value << USB_HOST_CTRLB_AUTORESUME_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_AUTORESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_AUTORESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_AUTORESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_AUTORESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_TSTJ_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_TSTJ) >> USB_HOST_CTRLB_TSTJ_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_TSTJ_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_TSTJ; + tmp |= value << USB_HOST_CTRLB_TSTJ_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_TSTJ_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_TSTJ; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_TSTK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_TSTK) >> USB_HOST_CTRLB_TSTK_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_TSTK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_TSTK; + tmp |= value << USB_HOST_CTRLB_TSTK_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_TSTK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_TSTK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_SOFE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_SOFE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_SOFE_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_SOFE) >> USB_HOST_CTRLB_SOFE_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_SOFE_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_SOFE; + tmp |= value << USB_HOST_CTRLB_SOFE_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_SOFE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_SOFE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_SOFE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_SOFE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_BUSRESET_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_BUSRESET; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_BUSRESET_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_BUSRESET) >> USB_HOST_CTRLB_BUSRESET_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_BUSRESET_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_BUSRESET; + tmp |= value << USB_HOST_CTRLB_BUSRESET_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_BUSRESET_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_BUSRESET; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_BUSRESET_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_BUSRESET; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_VBUSOK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_VBUSOK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_VBUSOK_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_VBUSOK) >> USB_HOST_CTRLB_VBUSOK_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_VBUSOK_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_VBUSOK; + tmp |= value << USB_HOST_CTRLB_VBUSOK_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_VBUSOK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_VBUSOK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_VBUSOK_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_VBUSOK; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_L1RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_L1RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_CTRLB_L1RESUME_bit(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_L1RESUME) >> USB_HOST_CTRLB_L1RESUME_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_CTRLB_L1RESUME_bit(const void *const hw, bool value) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_L1RESUME; + tmp |= value << USB_HOST_CTRLB_L1RESUME_Pos; + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_L1RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_L1RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_L1RESUME_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_L1RESUME; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= USB_HOST_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_ctrlb_reg_t hri_usbhost_get_CTRLB_SPDCONF_bf(const void *const hw, + hri_usbhost_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_SPDCONF(mask)) >> USB_HOST_CTRLB_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbhost_write_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= ~USB_HOST_CTRLB_SPDCONF_Msk; + tmp |= USB_HOST_CTRLB_SPDCONF(data); + ((Usb *)hw)->HOST.CTRLB.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~USB_HOST_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_SPDCONF_bf(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= USB_HOST_CTRLB_SPDCONF(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_ctrlb_reg_t hri_usbhost_read_CTRLB_SPDCONF_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp = (tmp & USB_HOST_CTRLB_SPDCONF_Msk) >> USB_HOST_CTRLB_SPDCONF_Pos; + return tmp; +} + +static inline void hri_usbhost_set_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_ctrlb_reg_t hri_usbhost_get_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.CTRLB.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_CTRLB_reg(const void *const hw, hri_usbhost_ctrlb_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.CTRLB.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_ctrlb_reg_t hri_usbhost_read_CTRLB_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.CTRLB.reg; +} + +static inline void hri_usbdevice_set_DADD_ADDEN_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_ADDEN; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevice_get_DADD_ADDEN_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp = (tmp & USB_DEVICE_DADD_ADDEN) >> USB_DEVICE_DADD_ADDEN_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevice_write_DADD_ADDEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp &= ~USB_DEVICE_DADD_ADDEN; + tmp |= value << USB_DEVICE_DADD_ADDEN_Pos; + ((Usb *)hw)->DEVICE.DADD.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_DADD_ADDEN_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_ADDEN; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_DADD_ADDEN_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_ADDEN; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_set_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg |= USB_DEVICE_DADD_DADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_DADD_bf(const void *const hw, + hri_usbdevice_dadd_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp = (tmp & USB_DEVICE_DADD_DADD(mask)) >> USB_DEVICE_DADD_DADD_Pos; + return tmp; +} + +static inline void hri_usbdevice_write_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp &= ~USB_DEVICE_DADD_DADD_Msk; + tmp |= USB_DEVICE_DADD_DADD(data); + ((Usb *)hw)->DEVICE.DADD.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg &= ~USB_DEVICE_DADD_DADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_DADD_DADD_bf(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg ^= USB_DEVICE_DADD_DADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_DADD_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp = (tmp & USB_DEVICE_DADD_DADD_Msk) >> USB_DEVICE_DADD_DADD_Pos; + return tmp; +} + +static inline void hri_usbdevice_set_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_dadd_reg_t hri_usbdevice_get_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->DEVICE.DADD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevice_write_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_clear_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevice_toggle_DADD_reg(const void *const hw, hri_usbdevice_dadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->DEVICE.DADD.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdevice_dadd_reg_t hri_usbdevice_read_DADD_reg(const void *const hw) +{ + return ((Usb *)hw)->DEVICE.DADD.reg; +} + +static inline void hri_usbhost_set_HSOFC_FLENCE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg |= USB_HOST_HSOFC_FLENCE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbhost_get_HSOFC_FLENCE_bit(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp = (tmp & USB_HOST_HSOFC_FLENCE) >> USB_HOST_HSOFC_FLENCE_Pos; + return (bool)tmp; +} + +static inline void hri_usbhost_write_HSOFC_FLENCE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp &= ~USB_HOST_HSOFC_FLENCE; + tmp |= value << USB_HOST_HSOFC_FLENCE_Pos; + ((Usb *)hw)->HOST.HSOFC.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_HSOFC_FLENCE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg &= ~USB_HOST_HSOFC_FLENCE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_HSOFC_FLENCE_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg ^= USB_HOST_HSOFC_FLENCE; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_set_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg |= USB_HOST_HSOFC_FLENC(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_hsofc_reg_t hri_usbhost_get_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp = (tmp & USB_HOST_HSOFC_FLENC(mask)) >> USB_HOST_HSOFC_FLENC_Pos; + return tmp; +} + +static inline void hri_usbhost_write_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t data) +{ + uint8_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp &= ~USB_HOST_HSOFC_FLENC_Msk; + tmp |= USB_HOST_HSOFC_FLENC(data); + ((Usb *)hw)->HOST.HSOFC.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg &= ~USB_HOST_HSOFC_FLENC(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_HSOFC_FLENC_bf(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg ^= USB_HOST_HSOFC_FLENC(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_hsofc_reg_t hri_usbhost_read_HSOFC_FLENC_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp = (tmp & USB_HOST_HSOFC_FLENC_Msk) >> USB_HOST_HSOFC_FLENC_Pos; + return tmp; +} + +static inline void hri_usbhost_set_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_hsofc_reg_t hri_usbhost_get_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.HSOFC.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_HSOFC_reg(const void *const hw, hri_usbhost_hsofc_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.HSOFC.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_hsofc_reg_t hri_usbhost_read_HSOFC_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.HSOFC.reg; +} + +static inline void hri_usbhost_set_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg |= USB_HOST_FNUM_MFNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp = (tmp & USB_HOST_FNUM_MFNUM(mask)) >> USB_HOST_FNUM_MFNUM_Pos; + return tmp; +} + +static inline void hri_usbhost_write_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp &= ~USB_HOST_FNUM_MFNUM_Msk; + tmp |= USB_HOST_FNUM_MFNUM(data); + ((Usb *)hw)->HOST.FNUM.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg &= ~USB_HOST_FNUM_MFNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_FNUM_MFNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg ^= USB_HOST_FNUM_MFNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_MFNUM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp = (tmp & USB_HOST_FNUM_MFNUM_Msk) >> USB_HOST_FNUM_MFNUM_Pos; + return tmp; +} + +static inline void hri_usbhost_set_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg |= USB_HOST_FNUM_FNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp = (tmp & USB_HOST_FNUM_FNUM(mask)) >> USB_HOST_FNUM_FNUM_Pos; + return tmp; +} + +static inline void hri_usbhost_write_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp &= ~USB_HOST_FNUM_FNUM_Msk; + tmp |= USB_HOST_FNUM_FNUM(data); + ((Usb *)hw)->HOST.FNUM.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg &= ~USB_HOST_FNUM_FNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_FNUM_FNUM_bf(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg ^= USB_HOST_FNUM_FNUM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_FNUM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp = (tmp & USB_HOST_FNUM_FNUM_Msk) >> USB_HOST_FNUM_FNUM_Pos; + return tmp; +} + +static inline void hri_usbhost_set_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_get_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.FNUM.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_write_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_clear_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbhost_toggle_FNUM_reg(const void *const hw, hri_usbhost_fnum_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.FNUM.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_fnum_reg_t hri_usbhost_read_FNUM_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.FNUM.reg; +} + +static inline void hri_usb_set_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg |= USB_DESCADD_DESCADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_descadd_reg_t hri_usb_get_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usb *)hw)->HOST.DESCADD.reg; + tmp = (tmp & USB_DESCADD_DESCADD(mask)) >> USB_DESCADD_DESCADD_Pos; + return tmp; +} + +static inline void hri_usb_write_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.DESCADD.reg; + tmp &= ~USB_DESCADD_DESCADD_Msk; + tmp |= USB_DESCADD_DESCADD(data); + ((Usb *)hw)->HOST.DESCADD.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg &= ~USB_DESCADD_DESCADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_DESCADD_DESCADD_bf(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg ^= USB_DESCADD_DESCADD(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_descadd_reg_t hri_usb_read_DESCADD_DESCADD_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((Usb *)hw)->HOST.DESCADD.reg; + tmp = (tmp & USB_DESCADD_DESCADD_Msk) >> USB_DESCADD_DESCADD_Pos; + return tmp; +} + +static inline void hri_usb_set_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_descadd_reg_t hri_usb_get_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) +{ + uint32_t tmp; + tmp = ((Usb *)hw)->HOST.DESCADD.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usb_write_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_DESCADD_reg(const void *const hw, hri_usb_descadd_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.DESCADD.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_descadd_reg_t hri_usb_read_DESCADD_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.DESCADD.reg; +} + +static inline void hri_usb_set_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRANSP(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSP(mask)) >> USB_PADCAL_TRANSP_Pos; + return tmp; +} + +static inline void hri_usb_write_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp &= ~USB_PADCAL_TRANSP_Msk; + tmp |= USB_PADCAL_TRANSP(data); + ((Usb *)hw)->HOST.PADCAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRANSP(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_PADCAL_TRANSP_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRANSP(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRANSP_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSP_Msk) >> USB_PADCAL_TRANSP_Pos; + return tmp; +} + +static inline void hri_usb_set_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRANSN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSN(mask)) >> USB_PADCAL_TRANSN_Pos; + return tmp; +} + +static inline void hri_usb_write_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp &= ~USB_PADCAL_TRANSN_Msk; + tmp |= USB_PADCAL_TRANSN(data); + ((Usb *)hw)->HOST.PADCAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRANSN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_PADCAL_TRANSN_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRANSN(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRANSN_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRANSN_Msk) >> USB_PADCAL_TRANSN_Pos; + return tmp; +} + +static inline void hri_usb_set_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg |= USB_PADCAL_TRIM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRIM(mask)) >> USB_PADCAL_TRIM_Pos; + return tmp; +} + +static inline void hri_usb_write_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp &= ~USB_PADCAL_TRIM_Msk; + tmp |= USB_PADCAL_TRIM(data); + ((Usb *)hw)->HOST.PADCAL.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg &= ~USB_PADCAL_TRIM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_PADCAL_TRIM_bf(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg ^= USB_PADCAL_TRIM(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_TRIM_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp = (tmp & USB_PADCAL_TRIM_Msk) >> USB_PADCAL_TRIM_Pos; + return tmp; +} + +static inline void hri_usb_set_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_get_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) +{ + uint16_t tmp; + tmp = ((Usb *)hw)->HOST.PADCAL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usb_write_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_clear_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usb_toggle_PADCAL_reg(const void *const hw, hri_usb_padcal_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.PADCAL.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usb_padcal_reg_t hri_usb_read_PADCAL_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.PADCAL.reg; +} + +static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_SPEED_bf(const void *const hw, + hri_usbhost_status_reg_t mask) +{ + return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_SPEED(mask)) >> USB_HOST_STATUS_SPEED_Pos; +} + +static inline void hri_usbhost_clear_STATUS_SPEED_bf(const void *const hw, hri_usbhost_status_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.STATUS.reg = USB_HOST_STATUS_SPEED(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_SPEED_bf(const void *const hw) +{ + return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_SPEED_Msk) >> USB_HOST_STATUS_SPEED_Pos; +} + +static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_LINESTATE_bf(const void *const hw, + hri_usbhost_status_reg_t mask) +{ + return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_LINESTATE(mask)) >> USB_HOST_STATUS_LINESTATE_Pos; +} + +static inline void hri_usbhost_clear_STATUS_LINESTATE_bf(const void *const hw, hri_usbhost_status_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.STATUS.reg = USB_HOST_STATUS_LINESTATE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_LINESTATE_bf(const void *const hw) +{ + return (((Usb *)hw)->HOST.STATUS.reg & USB_HOST_STATUS_LINESTATE_Msk) >> USB_HOST_STATUS_LINESTATE_Pos; +} + +static inline hri_usbhost_status_reg_t hri_usbhost_get_STATUS_reg(const void *const hw, hri_usbhost_status_reg_t mask) +{ + uint8_t tmp; + tmp = ((Usb *)hw)->HOST.STATUS.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbhost_clear_STATUS_reg(const void *const hw, hri_usbhost_status_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((Usb *)hw)->HOST.STATUS.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbhost_status_reg_t hri_usbhost_read_STATUS_reg(const void *const hw) +{ + return ((Usb *)hw)->HOST.STATUS.reg; +} + +static inline void hri_usbdevicedescbank_set_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_get_ADDR_ADDR_bf(const void *const hw, + hri_usbdesc_bank_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; + tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; + tmp &= ~USB_DEVICE_ADDR_ADDR_Msk; + tmp |= USB_DEVICE_ADDR_ADDR(data); + ((UsbDeviceDescBank *)hw)->ADDR.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_ADDR_ADDR_bf(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_read_ADDR_ADDR_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; + tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_get_ADDR_reg(const void *const hw, + hri_usbdesc_bank_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_ADDR_reg(const void *const hw, hri_usbdesc_bank_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->ADDR.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_addr_reg_t hri_usbdevicedescbank_read_ADDR_reg(const void *const hw) +{ + return ((UsbDeviceDescBank *)hw)->ADDR.reg; +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevicedescbank_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, bool value) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; + tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbdevicedescbank_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk; + tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbdevicedescbank_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk; + tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbdevicedescbank_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t +hri_usbdevicedescbank_get_PCKSIZE_SIZE_bf(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk; + tmp |= USB_DEVICE_PCKSIZE_SIZE(data); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_SIZE_bf(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_SIZE_bf(const void *const hw) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_get_PCKSIZE_reg(const void *const hw, + hri_usbdesc_bank_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_PCKSIZE_reg(const void *const hw, hri_usbdesc_bank_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->PCKSIZE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_pcksize_reg_t hri_usbdevicedescbank_read_PCKSIZE_reg(const void *const hw) +{ + return ((UsbDeviceDescBank *)hw)->PCKSIZE.reg; +} + +static inline void hri_usbdevicedescbank_set_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t +hri_usbdevicedescbank_get_EXTREG_SUBPID_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_EXTREG_SUBPID_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk; + tmp |= USB_DEVICE_EXTREG_SUBPID(data); + ((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_EXTREG_SUBPID_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_EXTREG_SUBPID_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_SUBPID_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t +hri_usbdevicedescbank_get_EXTREG_VARIABLE_bf(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk; + tmp |= USB_DEVICE_EXTREG_VARIABLE(data); + ((UsbDeviceDescBank *)hw)->EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_EXTREG_VARIABLE_bf(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_VARIABLE_bf(const void *const hw) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescbank_set_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_get_EXTREG_reg(const void *const hw, + hri_usbdesc_bank_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->EXTREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescbank_write_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_clear_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescbank_toggle_EXTREG_reg(const void *const hw, hri_usbdesc_bank_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->EXTREG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_extreg_reg_t hri_usbdevicedescbank_read_EXTREG_reg(const void *const hw) +{ + return ((UsbDeviceDescBank *)hw)->EXTREG.reg; +} + +static inline bool hri_usbdevicedescbank_get_STATUS_BK_CRCERR_bit(const void *const hw) +{ + return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR) >> USB_DEVICE_STATUS_BK_CRCERR_Pos; +} + +static inline void hri_usbdevicedescbank_clear_STATUS_BK_CRCERR_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevicedescbank_get_STATUS_BK_ERRORFLOW_bit(const void *const hw) +{ + return (((UsbDeviceDescBank *)hw)->STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) + >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos; +} + +static inline void hri_usbdevicedescbank_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_bk_reg_t +hri_usbdevicedescbank_get_STATUS_BK_reg(const void *const hw, hri_usbdesc_bank_status_bk_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDeviceDescBank *)hw)->STATUS_BK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescbank_clear_STATUS_BK_reg(const void *const hw, + hri_usbdesc_bank_status_bk_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescBank *)hw)->STATUS_BK.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdesc_bank_status_bk_reg_t hri_usbdevicedescbank_read_STATUS_BK_reg(const void *const hw) +{ + return ((UsbDeviceDescBank *)hw)->STATUS_BK.reg; +} + +static inline void hri_usbdevicedescriptor_set_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_addr_reg_t +hri_usbdevicedescriptor_get_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; + tmp = (tmp & USB_DEVICE_ADDR_ADDR(mask)) >> USB_DEVICE_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; + tmp &= ~USB_DEVICE_ADDR_ADDR_Msk; + tmp |= USB_DEVICE_ADDR_ADDR(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_ADDR_ADDR_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= USB_DEVICE_ADDR_ADDR(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_addr_reg_t hri_usbdevicedescriptor_read_ADDR_ADDR_bf(const void *const hw, + uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; + tmp = (tmp & USB_DEVICE_ADDR_ADDR_Msk) >> USB_DEVICE_ADDR_ADDR_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_addr_reg_t +hri_usbdevicedescriptor_get_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_ADDR_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_addr_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_addr_reg_t hri_usbdevicedescriptor_read_ADDR_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].ADDR.reg; +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevicedescriptor_get_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_AUTO_ZLP) >> USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; + return (bool)tmp; +} + +static inline void hri_usbdevicedescriptor_write_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index, + bool value) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; + tmp |= value << USB_DEVICE_PCKSIZE_AUTO_ZLP_Pos; + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_AUTO_ZLP_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_AUTO_ZLP; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_get_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT(mask)) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk; + tmp |= USB_DEVICE_PCKSIZE_BYTE_COUNT(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_BYTE_COUNT(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_read_PCKSIZE_BYTE_COUNT_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_BYTE_COUNT_Msk) >> USB_DEVICE_PCKSIZE_BYTE_COUNT_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, + uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg + |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_get_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask)) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void +hri_usbdevicedescriptor_write_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk; + tmp |= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void +hri_usbdevicedescriptor_clear_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg + &= ~USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void +hri_usbdevicedescriptor_toggle_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg + ^= USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_read_PCKSIZE_MULTI_PACKET_SIZE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Msk) >> USB_DEVICE_PCKSIZE_MULTI_PACKET_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_get_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE(mask)) >> USB_DEVICE_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t data) +{ + uint32_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= ~USB_DEVICE_PCKSIZE_SIZE_Msk; + tmp |= USB_DEVICE_PCKSIZE_SIZE(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= USB_DEVICE_PCKSIZE_SIZE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_read_PCKSIZE_SIZE_bf(const void *const hw, uint8_t submodule_index) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp = (tmp & USB_DEVICE_PCKSIZE_SIZE_Msk) >> USB_DEVICE_PCKSIZE_SIZE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t +hri_usbdevicedescriptor_get_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + uint32_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_PCKSIZE_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_pcksize_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_pcksize_reg_t hri_usbdevicedescriptor_read_PCKSIZE_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].PCKSIZE.reg; +} + +static inline void hri_usbdevicedescriptor_set_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t +hri_usbdevicedescriptor_get_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_SUBPID(mask)) >> USB_DEVICE_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp &= ~USB_DEVICE_EXTREG_SUBPID_Msk; + tmp |= USB_DEVICE_EXTREG_SUBPID(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_SUBPID(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t +hri_usbdevicedescriptor_read_EXTREG_SUBPID_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_SUBPID_Msk) >> USB_DEVICE_EXTREG_SUBPID_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t +hri_usbdevicedescriptor_get_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE(mask)) >> USB_DEVICE_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t data) +{ + uint16_t tmp; + USB_CRITICAL_SECTION_ENTER(); + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp &= ~USB_DEVICE_EXTREG_VARIABLE_Msk; + tmp |= USB_DEVICE_EXTREG_VARIABLE(data); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = tmp; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= USB_DEVICE_EXTREG_VARIABLE(mask); + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t +hri_usbdevicedescriptor_read_EXTREG_VARIABLE_bf(const void *const hw, uint8_t submodule_index) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp = (tmp & USB_DEVICE_EXTREG_VARIABLE_Msk) >> USB_DEVICE_EXTREG_VARIABLE_Pos; + return tmp; +} + +static inline void hri_usbdevicedescriptor_set_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg |= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t +hri_usbdevicedescriptor_get_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + uint16_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescriptor_write_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t data) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg = data; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_clear_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg &= ~mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_usbdevicedescriptor_toggle_EXTREG_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_extreg_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg ^= mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_extreg_reg_t hri_usbdevicedescriptor_read_EXTREG_reg(const void *const hw, + uint8_t submodule_index) +{ + return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].EXTREG.reg; +} + +static inline bool hri_usbdevicedescriptor_get_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_CRCERR) + >> USB_DEVICE_STATUS_BK_CRCERR_Pos; +} + +static inline void hri_usbdevicedescriptor_clear_STATUS_BK_CRCERR_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_CRCERR; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_usbdevicedescriptor_get_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) +{ + return (((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg & USB_DEVICE_STATUS_BK_ERRORFLOW) + >> USB_DEVICE_STATUS_BK_ERRORFLOW_Pos; +} + +static inline void hri_usbdevicedescriptor_clear_STATUS_BK_ERRORFLOW_bit(const void *const hw, uint8_t submodule_index) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = USB_DEVICE_STATUS_BK_ERRORFLOW; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_status_bk_reg_t +hri_usbdevicedescriptor_get_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_status_bk_reg_t mask) +{ + uint8_t tmp; + tmp = ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_usbdevicedescriptor_clear_STATUS_BK_reg(const void *const hw, uint8_t submodule_index, + hri_usbdescriptordevice_status_bk_reg_t mask) +{ + USB_CRITICAL_SECTION_ENTER(); + ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg = mask; + USB_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_usbdescriptordevice_status_bk_reg_t +hri_usbdevicedescriptor_read_STATUS_BK_reg(const void *const hw, uint8_t submodule_index) +{ + return ((UsbDeviceDescriptor *)hw)->DeviceDescBank[submodule_index].STATUS_BK.reg; +} + +/* Below section is for legacy hri apis name, not recommended to use below left side apis in application */ +#define hri_usbdevice_wait_for_sync(a, b) hri_usb_wait_for_sync(a, b) +#define hri_usbdevice_is_syncing(a, b) hri_usb_is_syncing(a, b) +#define hri_usbhost_wait_for_sync(a, b) hri_usb_wait_for_sync(a, b) +#define hri_usbhost_is_syncing(a, b) hri_usb_is_syncing(a, b) +#define hri_usbhost_set_CTRLA_SWRST_bit(a) hri_usb_set_CTRLA_SWRST_bit(a) +#define hri_usbhost_get_CTRLA_SWRST_bit(a) hri_usb_get_CTRLA_SWRST_bit(a) +#define hri_usbhost_set_CTRLA_ENABLE_bit(a) hri_usb_set_CTRLA_ENABLE_bit(a) +#define hri_usbhost_get_CTRLA_ENABLE_bit(a) hri_usb_get_CTRLA_ENABLE_bit(a) +#define hri_usbhost_write_CTRLA_ENABLE_bit(a, b) hri_usb_write_CTRLA_ENABLE_bit(a, b) +#define hri_usbhost_clear_CTRLA_ENABLE_bit(a) hri_usb_clear_CTRLA_ENABLE_bit(a) +#define hri_usbhost_toggle_CTRLA_ENABLE_bit(a) hri_usb_toggle_CTRLA_ENABLE_bit(a) +#define hri_usbhost_set_CTRLA_RUNSTDBY_bit(a) hri_usb_set_CTRLA_RUNSTDBY_bit(a) +#define hri_usbhost_get_CTRLA_RUNSTDBY_bit(a) hri_usb_get_CTRLA_RUNSTDBY_bit(a) +#define hri_usbhost_write_CTRLA_RUNSTDBY_bit(a, b) hri_usb_write_CTRLA_RUNSTDBY_bit(a, b) +#define hri_usbhost_clear_CTRLA_RUNSTDBY_bit(a) hri_usb_clear_CTRLA_RUNSTDBY_bit(a) +#define hri_usbhost_toggle_CTRLA_RUNSTDBY_bit(a) hri_usb_toggle_CTRLA_RUNSTDBY_bit(a) +#define hri_usbhost_set_CTRLA_MODE_bit(a) hri_usb_set_CTRLA_MODE_bit(a) +#define hri_usbhost_get_CTRLA_MODE_bit(a) hri_usb_get_CTRLA_MODE_bit(a) +#define hri_usbhost_write_CTRLA_MODE_bit(a, b) hri_usb_write_CTRLA_MODE_bit(a, b) +#define hri_usbhost_clear_CTRLA_MODE_bit(a) hri_usb_clear_CTRLA_MODE_bit(a) +#define hri_usbhost_toggle_CTRLA_MODE_bit(a) hri_usb_toggle_CTRLA_MODE_bit(a) +#define hri_usbhost_set_CTRLA_reg(a, b) hri_usb_set_CTRLA_reg(a, b) +#define hri_usbhost_get_CTRLA_reg(a, b) hri_usb_get_CTRLA_reg(a, b) +#define hri_usbhost_write_CTRLA_reg(a, b) hri_usb_write_CTRLA_reg(a, b) +#define hri_usbhost_clear_CTRLA_reg(a, b) hri_usb_clear_CTRLA_reg(a, b) +#define hri_usbhost_toggle_CTRLA_reg(a, b) hri_usb_toggle_CTRLA_reg(a, b) +#define hri_usbhost_read_CTRLA_reg(a) hri_usb_read_CTRLA_reg(a) +#define hri_usbhost_set_QOSCTRL_CQOS_bf(a, b) hri_usb_set_QOSCTRL_CQOS_bf(a, b) +#define hri_usbhost_get_QOSCTRL_CQOS_bf(a, b) hri_usb_get_QOSCTRL_CQOS_bf(a, b) +#define hri_usbhost_write_QOSCTRL_CQOS_bf(a, b) hri_usb_write_QOSCTRL_CQOS_bf(a, b) +#define hri_usbhost_clear_QOSCTRL_CQOS_bf(a, b) hri_usb_clear_QOSCTRL_CQOS_bf(a, b) +#define hri_usbhost_toggle_QOSCTRL_CQOS_bf(a, b) hri_usb_toggle_QOSCTRL_CQOS_bf(a, b) +#define hri_usbhost_read_QOSCTRL_CQOS_bf(a) hri_usb_read_QOSCTRL_CQOS_bf(a) +#define hri_usbhost_set_QOSCTRL_DQOS_bf(a, b) hri_usb_set_QOSCTRL_DQOS_bf(a, b) +#define hri_usbhost_get_QOSCTRL_DQOS_bf(a, b) hri_usb_get_QOSCTRL_DQOS_bf(a, b) +#define hri_usbhost_write_QOSCTRL_DQOS_bf(a, b) hri_usb_write_QOSCTRL_DQOS_bf(a, b) +#define hri_usbhost_clear_QOSCTRL_DQOS_bf(a, b) hri_usb_clear_QOSCTRL_DQOS_bf(a, b) +#define hri_usbhost_toggle_QOSCTRL_DQOS_bf(a, b) hri_usb_toggle_QOSCTRL_DQOS_bf(a, b) +#define hri_usbhost_read_QOSCTRL_DQOS_bf(a) hri_usb_read_QOSCTRL_DQOS_bf(a) +#define hri_usbhost_set_QOSCTRL_reg(a, b) hri_usb_set_QOSCTRL_reg(a, b) +#define hri_usbhost_get_QOSCTRL_reg(a, b) hri_usb_get_QOSCTRL_reg(a, b) +#define hri_usbhost_write_QOSCTRL_reg(a, b) hri_usb_write_QOSCTRL_reg(a, b) +#define hri_usbhost_clear_QOSCTRL_reg(a, b) hri_usb_clear_QOSCTRL_reg(a, b) +#define hri_usbhost_toggle_QOSCTRL_reg(a, b) hri_usb_toggle_QOSCTRL_reg(a, b) +#define hri_usbhost_read_QOSCTRL_reg(a) hri_usb_read_QOSCTRL_reg(a) +#define hri_usbhost_set_DESCADD_DESCADD_bf(a, b) hri_usb_set_DESCADD_DESCADD_bf(a, b) +#define hri_usbhost_get_DESCADD_DESCADD_bf(a, b) hri_usb_get_DESCADD_DESCADD_bf(a, b) +#define hri_usbhost_write_DESCADD_DESCADD_bf(a, b) hri_usb_write_DESCADD_DESCADD_bf(a, b) +#define hri_usbhost_clear_DESCADD_DESCADD_bf(a, b) hri_usb_clear_DESCADD_DESCADD_bf(a, b) +#define hri_usbhost_toggle_DESCADD_DESCADD_bf(a, b) hri_usb_toggle_DESCADD_DESCADD_bf(a, b) +#define hri_usbhost_read_DESCADD_DESCADD_bf(a) hri_usb_read_DESCADD_DESCADD_bf(a) +#define hri_usbhost_set_DESCADD_reg(a, b) hri_usb_set_DESCADD_reg(a, b) +#define hri_usbhost_get_DESCADD_reg(a, b) hri_usb_get_DESCADD_reg(a, b) +#define hri_usbhost_write_DESCADD_reg(a, b) hri_usb_write_DESCADD_reg(a, b) +#define hri_usbhost_clear_DESCADD_reg(a, b) hri_usb_clear_DESCADD_reg(a, b) +#define hri_usbhost_toggle_DESCADD_reg(a, b) hri_usb_toggle_DESCADD_reg(a, b) +#define hri_usbhost_read_DESCADD_reg(a) hri_usb_read_DESCADD_reg(a) +#define hri_usbhost_set_PADCAL_TRANSP_bf(a, b) hri_usb_set_PADCAL_TRANSP_bf(a, b) +#define hri_usbhost_get_PADCAL_TRANSP_bf(a, b) hri_usb_get_PADCAL_TRANSP_bf(a, b) +#define hri_usbhost_write_PADCAL_TRANSP_bf(a, b) hri_usb_write_PADCAL_TRANSP_bf(a, b) +#define hri_usbhost_clear_PADCAL_TRANSP_bf(a, b) hri_usb_clear_PADCAL_TRANSP_bf(a, b) +#define hri_usbhost_toggle_PADCAL_TRANSP_bf(a, b) hri_usb_toggle_PADCAL_TRANSP_bf(a, b) +#define hri_usbhost_read_PADCAL_TRANSP_bf(a) hri_usb_read_PADCAL_TRANSP_bf(a) +#define hri_usbhost_set_PADCAL_TRANSN_bf(a, b) hri_usb_set_PADCAL_TRANSN_bf(a, b) +#define hri_usbhost_get_PADCAL_TRANSN_bf(a, b) hri_usb_get_PADCAL_TRANSN_bf(a, b) +#define hri_usbhost_write_PADCAL_TRANSN_bf(a, b) hri_usb_write_PADCAL_TRANSN_bf(a, b) +#define hri_usbhost_clear_PADCAL_TRANSN_bf(a, b) hri_usb_clear_PADCAL_TRANSN_bf(a, b) +#define hri_usbhost_toggle_PADCAL_TRANSN_bf(a, b) hri_usb_toggle_PADCAL_TRANSN_bf(a, b) +#define hri_usbhost_read_PADCAL_TRANSN_bf(a) hri_usb_read_PADCAL_TRANSN_bf(a) +#define hri_usbhost_set_PADCAL_TRIM_bf(a, b) hri_usb_set_PADCAL_TRIM_bf(a, b) +#define hri_usbhost_get_PADCAL_TRIM_bf(a, b) hri_usb_get_PADCAL_TRIM_bf(a, b) +#define hri_usbhost_write_PADCAL_TRIM_bf(a, b) hri_usb_write_PADCAL_TRIM_bf(a, b) +#define hri_usbhost_clear_PADCAL_TRIM_bf(a, b) hri_usb_clear_PADCAL_TRIM_bf(a, b) +#define hri_usbhost_toggle_PADCAL_TRIM_bf(a, b) hri_usb_toggle_PADCAL_TRIM_bf(a, b) +#define hri_usbhost_read_PADCAL_TRIM_bf(a) hri_usb_read_PADCAL_TRIM_bf(a) +#define hri_usbhost_set_PADCAL_reg(a, b) hri_usb_set_PADCAL_reg(a, b) +#define hri_usbhost_get_PADCAL_reg(a, b) hri_usb_get_PADCAL_reg(a, b) +#define hri_usbhost_write_PADCAL_reg(a, b) hri_usb_write_PADCAL_reg(a, b) +#define hri_usbhost_clear_PADCAL_reg(a, b) hri_usb_clear_PADCAL_reg(a, b) +#define hri_usbhost_toggle_PADCAL_reg(a, b) hri_usb_toggle_PADCAL_reg(a, b) +#define hri_usbhost_read_PADCAL_reg(a) hri_usb_read_PADCAL_reg(a) +#define hri_usbhost_get_SYNCBUSY_SWRST_bit(a) hri_usb_get_SYNCBUSY_SWRST_bit(a) +#define hri_usbhost_get_SYNCBUSY_ENABLE_bit(a) hri_usb_get_SYNCBUSY_ENABLE_bit(a) +#define hri_usbhost_get_SYNCBUSY_reg(a, b) hri_usb_get_SYNCBUSY_reg(a, b) +#define hri_usbhost_read_SYNCBUSY_reg(a) hri_usb_read_SYNCBUSY_reg(a) +#define hri_usbhost_get_FSMSTATUS_FSMSTATE_bf(a, b) hri_usb_get_FSMSTATUS_FSMSTATE_bf(a, b) +#define hri_usbhost_read_FSMSTATUS_FSMSTATE_bf(a) hri_usb_read_FSMSTATUS_FSMSTATE_bf(a) +#define hri_usbhost_get_FSMSTATUS_reg(a, b) hri_usb_get_FSMSTATUS_reg(a, b) +#define hri_usbhost_read_FSMSTATUS_reg(a) hri_usb_read_FSMSTATUS_reg(a) +#define hri_usbdevice_set_CTRLA_SWRST_bit(a) hri_usb_set_CTRLA_SWRST_bit(a) +#define hri_usbdevice_get_CTRLA_SWRST_bit(a) hri_usb_get_CTRLA_SWRST_bit(a) +#define hri_usbdevice_set_CTRLA_ENABLE_bit(a) hri_usb_set_CTRLA_ENABLE_bit(a) +#define hri_usbdevice_get_CTRLA_ENABLE_bit(a) hri_usb_get_CTRLA_ENABLE_bit(a) +#define hri_usbdevice_write_CTRLA_ENABLE_bit(a, b) hri_usb_write_CTRLA_ENABLE_bit(a, b) +#define hri_usbdevice_clear_CTRLA_ENABLE_bit(a) hri_usb_clear_CTRLA_ENABLE_bit(a) +#define hri_usbdevice_toggle_CTRLA_ENABLE_bit(a) hri_usb_toggle_CTRLA_ENABLE_bit(a) +#define hri_usbdevice_set_CTRLA_RUNSTDBY_bit(a) hri_usb_set_CTRLA_RUNSTDBY_bit(a) +#define hri_usbdevice_get_CTRLA_RUNSTDBY_bit(a) hri_usb_get_CTRLA_RUNSTDBY_bit(a) +#define hri_usbdevice_write_CTRLA_RUNSTDBY_bit(a, b) hri_usb_write_CTRLA_RUNSTDBY_bit(a, b) +#define hri_usbdevice_clear_CTRLA_RUNSTDBY_bit(a) hri_usb_clear_CTRLA_RUNSTDBY_bit(a) +#define hri_usbdevice_toggle_CTRLA_RUNSTDBY_bit(a) hri_usb_toggle_CTRLA_RUNSTDBY_bit(a) +#define hri_usbdevice_set_CTRLA_MODE_bit(a) hri_usb_set_CTRLA_MODE_bit(a) +#define hri_usbdevice_get_CTRLA_MODE_bit(a) hri_usb_get_CTRLA_MODE_bit(a) +#define hri_usbdevice_write_CTRLA_MODE_bit(a, b) hri_usb_write_CTRLA_MODE_bit(a, b) +#define hri_usbdevice_clear_CTRLA_MODE_bit(a) hri_usb_clear_CTRLA_MODE_bit(a) +#define hri_usbdevice_toggle_CTRLA_MODE_bit(a) hri_usb_toggle_CTRLA_MODE_bit(a) +#define hri_usbdevice_set_CTRLA_reg(a, b) hri_usb_set_CTRLA_reg(a, b) +#define hri_usbdevice_get_CTRLA_reg(a, b) hri_usb_get_CTRLA_reg(a, b) +#define hri_usbdevice_write_CTRLA_reg(a, b) hri_usb_write_CTRLA_reg(a, b) +#define hri_usbdevice_clear_CTRLA_reg(a, b) hri_usb_clear_CTRLA_reg(a, b) +#define hri_usbdevice_toggle_CTRLA_reg(a, b) hri_usb_toggle_CTRLA_reg(a, b) +#define hri_usbdevice_read_CTRLA_reg(a) hri_usb_read_CTRLA_reg(a) +#define hri_usbdevice_set_QOSCTRL_CQOS_bf(a, b) hri_usb_set_QOSCTRL_CQOS_bf(a, b) +#define hri_usbdevice_get_QOSCTRL_CQOS_bf(a, b) hri_usb_get_QOSCTRL_CQOS_bf(a, b) +#define hri_usbdevice_write_QOSCTRL_CQOS_bf(a, b) hri_usb_write_QOSCTRL_CQOS_bf(a, b) +#define hri_usbdevice_clear_QOSCTRL_CQOS_bf(a, b) hri_usb_clear_QOSCTRL_CQOS_bf(a, b) +#define hri_usbdevice_toggle_QOSCTRL_CQOS_bf(a, b) hri_usb_toggle_QOSCTRL_CQOS_bf(a, b) +#define hri_usbdevice_read_QOSCTRL_CQOS_bf(a) hri_usb_read_QOSCTRL_CQOS_bf(a) +#define hri_usbdevice_set_QOSCTRL_DQOS_bf(a, b) hri_usb_set_QOSCTRL_DQOS_bf(a, b) +#define hri_usbdevice_get_QOSCTRL_DQOS_bf(a, b) hri_usb_get_QOSCTRL_DQOS_bf(a, b) +#define hri_usbdevice_write_QOSCTRL_DQOS_bf(a, b) hri_usb_write_QOSCTRL_DQOS_bf(a, b) +#define hri_usbdevice_clear_QOSCTRL_DQOS_bf(a, b) hri_usb_clear_QOSCTRL_DQOS_bf(a, b) +#define hri_usbdevice_toggle_QOSCTRL_DQOS_bf(a, b) hri_usb_toggle_QOSCTRL_DQOS_bf(a, b) +#define hri_usbdevice_read_QOSCTRL_DQOS_bf(a) hri_usb_read_QOSCTRL_DQOS_bf(a) +#define hri_usbdevice_set_QOSCTRL_reg(a, b) hri_usb_set_QOSCTRL_reg(a, b) +#define hri_usbdevice_get_QOSCTRL_reg(a, b) hri_usb_get_QOSCTRL_reg(a, b) +#define hri_usbdevice_write_QOSCTRL_reg(a, b) hri_usb_write_QOSCTRL_reg(a, b) +#define hri_usbdevice_clear_QOSCTRL_reg(a, b) hri_usb_clear_QOSCTRL_reg(a, b) +#define hri_usbdevice_toggle_QOSCTRL_reg(a, b) hri_usb_toggle_QOSCTRL_reg(a, b) +#define hri_usbdevice_read_QOSCTRL_reg(a) hri_usb_read_QOSCTRL_reg(a) +#define hri_usbdevice_set_DESCADD_DESCADD_bf(a, b) hri_usb_set_DESCADD_DESCADD_bf(a, b) +#define hri_usbdevice_get_DESCADD_DESCADD_bf(a, b) hri_usb_get_DESCADD_DESCADD_bf(a, b) +#define hri_usbdevice_write_DESCADD_DESCADD_bf(a, b) hri_usb_write_DESCADD_DESCADD_bf(a, b) +#define hri_usbdevice_clear_DESCADD_DESCADD_bf(a, b) hri_usb_clear_DESCADD_DESCADD_bf(a, b) +#define hri_usbdevice_toggle_DESCADD_DESCADD_bf(a, b) hri_usb_toggle_DESCADD_DESCADD_bf(a, b) +#define hri_usbdevice_read_DESCADD_DESCADD_bf(a) hri_usb_read_DESCADD_DESCADD_bf(a) +#define hri_usbdevice_set_DESCADD_reg(a, b) hri_usb_set_DESCADD_reg(a, b) +#define hri_usbdevice_get_DESCADD_reg(a, b) hri_usb_get_DESCADD_reg(a, b) +#define hri_usbdevice_write_DESCADD_reg(a, b) hri_usb_write_DESCADD_reg(a, b) +#define hri_usbdevice_clear_DESCADD_reg(a, b) hri_usb_clear_DESCADD_reg(a, b) +#define hri_usbdevice_toggle_DESCADD_reg(a, b) hri_usb_toggle_DESCADD_reg(a, b) +#define hri_usbdevice_read_DESCADD_reg(a) hri_usb_read_DESCADD_reg(a) +#define hri_usbdevice_set_PADCAL_TRANSP_bf(a, b) hri_usb_set_PADCAL_TRANSP_bf(a, b) +#define hri_usbdevice_get_PADCAL_TRANSP_bf(a, b) hri_usb_get_PADCAL_TRANSP_bf(a, b) +#define hri_usbdevice_write_PADCAL_TRANSP_bf(a, b) hri_usb_write_PADCAL_TRANSP_bf(a, b) +#define hri_usbdevice_clear_PADCAL_TRANSP_bf(a, b) hri_usb_clear_PADCAL_TRANSP_bf(a, b) +#define hri_usbdevice_toggle_PADCAL_TRANSP_bf(a, b) hri_usb_toggle_PADCAL_TRANSP_bf(a, b) +#define hri_usbdevice_read_PADCAL_TRANSP_bf(a) hri_usb_read_PADCAL_TRANSP_bf(a) +#define hri_usbdevice_set_PADCAL_TRANSN_bf(a, b) hri_usb_set_PADCAL_TRANSN_bf(a, b) +#define hri_usbdevice_get_PADCAL_TRANSN_bf(a, b) hri_usb_get_PADCAL_TRANSN_bf(a, b) +#define hri_usbdevice_write_PADCAL_TRANSN_bf(a, b) hri_usb_write_PADCAL_TRANSN_bf(a, b) +#define hri_usbdevice_clear_PADCAL_TRANSN_bf(a, b) hri_usb_clear_PADCAL_TRANSN_bf(a, b) +#define hri_usbdevice_toggle_PADCAL_TRANSN_bf(a, b) hri_usb_toggle_PADCAL_TRANSN_bf(a, b) +#define hri_usbdevice_read_PADCAL_TRANSN_bf(a) hri_usb_read_PADCAL_TRANSN_bf(a) +#define hri_usbdevice_set_PADCAL_TRIM_bf(a, b) hri_usb_set_PADCAL_TRIM_bf(a, b) +#define hri_usbdevice_get_PADCAL_TRIM_bf(a, b) hri_usb_get_PADCAL_TRIM_bf(a, b) +#define hri_usbdevice_write_PADCAL_TRIM_bf(a, b) hri_usb_write_PADCAL_TRIM_bf(a, b) +#define hri_usbdevice_clear_PADCAL_TRIM_bf(a, b) hri_usb_clear_PADCAL_TRIM_bf(a, b) +#define hri_usbdevice_toggle_PADCAL_TRIM_bf(a, b) hri_usb_toggle_PADCAL_TRIM_bf(a, b) +#define hri_usbdevice_read_PADCAL_TRIM_bf(a) hri_usb_read_PADCAL_TRIM_bf(a) +#define hri_usbdevice_set_PADCAL_reg(a, b) hri_usb_set_PADCAL_reg(a, b) +#define hri_usbdevice_get_PADCAL_reg(a, b) hri_usb_get_PADCAL_reg(a, b) +#define hri_usbdevice_write_PADCAL_reg(a, b) hri_usb_write_PADCAL_reg(a, b) +#define hri_usbdevice_clear_PADCAL_reg(a, b) hri_usb_clear_PADCAL_reg(a, b) +#define hri_usbdevice_toggle_PADCAL_reg(a, b) hri_usb_toggle_PADCAL_reg(a, b) +#define hri_usbdevice_read_PADCAL_reg(a) hri_usb_read_PADCAL_reg(a) +#define hri_usbdevice_get_SYNCBUSY_SWRST_bit(a) hri_usb_get_SYNCBUSY_SWRST_bit(a) +#define hri_usbdevice_get_SYNCBUSY_ENABLE_bit(a) hri_usb_get_SYNCBUSY_ENABLE_bit(a) +#define hri_usbdevice_get_SYNCBUSY_reg(a, b) hri_usb_get_SYNCBUSY_reg(a, b) +#define hri_usbdevice_read_SYNCBUSY_reg(a) hri_usb_read_SYNCBUSY_reg(a) +#define hri_usbdevice_get_FSMSTATUS_FSMSTATE_bf(a, b) hri_usb_get_FSMSTATUS_FSMSTATE_bf(a, b) +#define hri_usbdevice_read_FSMSTATUS_FSMSTATE_bf(a) hri_usb_read_FSMSTATUS_FSMSTATE_bf(a) +#define hri_usbdevice_get_FSMSTATUS_reg(a, b) hri_usb_get_FSMSTATUS_reg(a, b) +#define hri_usbdevice_read_FSMSTATUS_reg(a) hri_usb_read_FSMSTATUS_reg(a) + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_USB_E54_H_INCLUDED */ +#endif /* _SAME54_USB_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/hri/hri_wdt_e54.h b/software/firmware/oracle_same54n19a/hri/hri_wdt_e54.h new file mode 100644 index 00000000..3549e2f6 --- /dev/null +++ b/software/firmware/oracle_same54n19a/hri/hri_wdt_e54.h @@ -0,0 +1,617 @@ +/** + * \file + * + * \brief SAM WDT + * + * Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries. + * + * \asf_license_start + * + * \page License + * + * Subject to your compliance with these terms, you may use Microchip + * software and any derivatives exclusively with Microchip products. + * It is your responsibility to comply with third party license terms applicable + * to your use of third party software (including open source software) that + * may accompany Microchip software. + * + * THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES, + * WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE, + * INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY, + * AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE + * LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL + * LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE + * SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE + * POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT + * ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY + * RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, + * THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE. + * + * \asf_license_stop + * + */ + +#ifdef _SAME54_WDT_COMPONENT_ +#ifndef _HRI_WDT_E54_H_INCLUDED_ +#define _HRI_WDT_E54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include + +#if defined(ENABLE_WDT_CRITICAL_SECTIONS) +#define WDT_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER() +#define WDT_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE() +#else +#define WDT_CRITICAL_SECTION_ENTER() +#define WDT_CRITICAL_SECTION_LEAVE() +#endif + +typedef uint32_t hri_wdt_syncbusy_reg_t; +typedef uint8_t hri_wdt_clear_reg_t; +typedef uint8_t hri_wdt_config_reg_t; +typedef uint8_t hri_wdt_ctrla_reg_t; +typedef uint8_t hri_wdt_ewctrl_reg_t; +typedef uint8_t hri_wdt_intenset_reg_t; +typedef uint8_t hri_wdt_intflag_reg_t; + +static inline void hri_wdt_wait_for_sync(const void *const hw, hri_wdt_syncbusy_reg_t reg) +{ + while (((Wdt *)hw)->SYNCBUSY.reg & reg) { + }; +} + +static inline bool hri_wdt_is_syncing(const void *const hw, hri_wdt_syncbusy_reg_t reg) +{ + return ((Wdt *)hw)->SYNCBUSY.reg & reg; +} + +static inline bool hri_wdt_get_INTFLAG_EW_bit(const void *const hw) +{ + return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos; +} + +static inline void hri_wdt_clear_INTFLAG_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW; +} + +static inline bool hri_wdt_get_interrupt_EW_bit(const void *const hw) +{ + return (((Wdt *)hw)->INTFLAG.reg & WDT_INTFLAG_EW) >> WDT_INTFLAG_EW_Pos; +} + +static inline void hri_wdt_clear_interrupt_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTFLAG.reg = WDT_INTFLAG_EW; +} + +static inline hri_wdt_intflag_reg_t hri_wdt_get_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->INTFLAG.reg; + tmp &= mask; + return tmp; +} + +static inline hri_wdt_intflag_reg_t hri_wdt_read_INTFLAG_reg(const void *const hw) +{ + return ((Wdt *)hw)->INTFLAG.reg; +} + +static inline void hri_wdt_clear_INTFLAG_reg(const void *const hw, hri_wdt_intflag_reg_t mask) +{ + ((Wdt *)hw)->INTFLAG.reg = mask; +} + +static inline void hri_wdt_set_INTEN_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; +} + +static inline bool hri_wdt_get_INTEN_EW_bit(const void *const hw) +{ + return (((Wdt *)hw)->INTENSET.reg & WDT_INTENSET_EW) >> WDT_INTENSET_EW_Pos; +} + +static inline void hri_wdt_write_INTEN_EW_bit(const void *const hw, bool value) +{ + if (value == 0x0) { + ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; + } else { + ((Wdt *)hw)->INTENSET.reg = WDT_INTENSET_EW; + } +} + +static inline void hri_wdt_clear_INTEN_EW_bit(const void *const hw) +{ + ((Wdt *)hw)->INTENCLR.reg = WDT_INTENSET_EW; +} + +static inline void hri_wdt_set_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) +{ + ((Wdt *)hw)->INTENSET.reg = mask; +} + +static inline hri_wdt_intenset_reg_t hri_wdt_get_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->INTENSET.reg; + tmp &= mask; + return tmp; +} + +static inline hri_wdt_intenset_reg_t hri_wdt_read_INTEN_reg(const void *const hw) +{ + return ((Wdt *)hw)->INTENSET.reg; +} + +static inline void hri_wdt_write_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t data) +{ + ((Wdt *)hw)->INTENSET.reg = data; + ((Wdt *)hw)->INTENCLR.reg = ~data; +} + +static inline void hri_wdt_clear_INTEN_reg(const void *const hw, hri_wdt_intenset_reg_t mask) +{ + ((Wdt *)hw)->INTENCLR.reg = mask; +} + +static inline bool hri_wdt_get_SYNCBUSY_ENABLE_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ENABLE) >> WDT_SYNCBUSY_ENABLE_Pos; +} + +static inline bool hri_wdt_get_SYNCBUSY_WEN_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_WEN) >> WDT_SYNCBUSY_WEN_Pos; +} + +static inline bool hri_wdt_get_SYNCBUSY_ALWAYSON_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_ALWAYSON) >> WDT_SYNCBUSY_ALWAYSON_Pos; +} + +static inline bool hri_wdt_get_SYNCBUSY_CLEAR_bit(const void *const hw) +{ + return (((Wdt *)hw)->SYNCBUSY.reg & WDT_SYNCBUSY_CLEAR) >> WDT_SYNCBUSY_CLEAR_Pos; +} + +static inline hri_wdt_syncbusy_reg_t hri_wdt_get_SYNCBUSY_reg(const void *const hw, hri_wdt_syncbusy_reg_t mask) +{ + uint32_t tmp; + tmp = ((Wdt *)hw)->SYNCBUSY.reg; + tmp &= mask; + return tmp; +} + +static inline hri_wdt_syncbusy_reg_t hri_wdt_read_SYNCBUSY_reg(const void *const hw) +{ + return ((Wdt *)hw)->SYNCBUSY.reg; +} + +static inline void hri_wdt_set_CTRLA_ENABLE_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ENABLE; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_CTRLA_ENABLE_bit(const void *const hw) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp = (tmp & WDT_CTRLA_ENABLE) >> WDT_CTRLA_ENABLE_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_CTRLA_ENABLE_bit(const void *const hw, bool value) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= ~WDT_CTRLA_ENABLE; + tmp |= value << WDT_CTRLA_ENABLE_Pos; + ((Wdt *)hw)->CTRLA.reg = tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_ENABLE_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ENABLE; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_ENABLE_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ENABLE; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_CTRLA_WEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_WEN; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_CTRLA_WEN_bit(const void *const hw) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp = (tmp & WDT_CTRLA_WEN) >> WDT_CTRLA_WEN_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_CTRLA_WEN_bit(const void *const hw, bool value) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= ~WDT_CTRLA_WEN; + tmp |= value << WDT_CTRLA_WEN_Pos; + ((Wdt *)hw)->CTRLA.reg = tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_WEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_WEN; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_WEN_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_WEN; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_CTRLA_ALWAYSON_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= WDT_CTRLA_ALWAYSON; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline bool hri_wdt_get_CTRLA_ALWAYSON_bit(const void *const hw) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp = (tmp & WDT_CTRLA_ALWAYSON) >> WDT_CTRLA_ALWAYSON_Pos; + return (bool)tmp; +} + +static inline void hri_wdt_write_CTRLA_ALWAYSON_bit(const void *const hw, bool value) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= ~WDT_CTRLA_ALWAYSON; + tmp |= value << WDT_CTRLA_ALWAYSON_Pos; + ((Wdt *)hw)->CTRLA.reg = tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_ALWAYSON_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~WDT_CTRLA_ALWAYSON; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_ALWAYSON_bit(const void *const hw) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= WDT_CTRLA_ALWAYSON; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_set_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg |= mask; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ctrla_reg_t hri_wdt_get_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + uint8_t tmp; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + tmp = ((Wdt *)hw)->CTRLA.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_wdt_write_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg = data; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg &= ~mask; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CTRLA_reg(const void *const hw, hri_wdt_ctrla_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CTRLA.reg ^= mask; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ctrla_reg_t hri_wdt_read_CTRLA_reg(const void *const hw) +{ + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_ENABLE | WDT_SYNCBUSY_WEN | WDT_SYNCBUSY_ALWAYSON); + return ((Wdt *)hw)->CTRLA.reg; +} + +static inline void hri_wdt_set_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_PER(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_PER(mask)) >> WDT_CONFIG_PER_Pos; + return tmp; +} + +static inline void hri_wdt_write_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t data) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp &= ~WDT_CONFIG_PER_Msk; + tmp |= WDT_CONFIG_PER(data); + ((Wdt *)hw)->CONFIG.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_PER(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CONFIG_PER_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_PER(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_PER_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_PER_Msk) >> WDT_CONFIG_PER_Pos; + return tmp; +} + +static inline void hri_wdt_set_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg |= WDT_CONFIG_WINDOW(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_WINDOW(mask)) >> WDT_CONFIG_WINDOW_Pos; + return tmp; +} + +static inline void hri_wdt_write_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t data) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp &= ~WDT_CONFIG_WINDOW_Msk; + tmp |= WDT_CONFIG_WINDOW(data); + ((Wdt *)hw)->CONFIG.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg &= ~WDT_CONFIG_WINDOW(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CONFIG_WINDOW_bf(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg ^= WDT_CONFIG_WINDOW(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_WINDOW_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp = (tmp & WDT_CONFIG_WINDOW_Msk) >> WDT_CONFIG_WINDOW_Pos; + return tmp; +} + +static inline void hri_wdt_set_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg |= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_get_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->CONFIG.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_wdt_write_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg = data; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg &= ~mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_CONFIG_reg(const void *const hw, hri_wdt_config_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CONFIG.reg ^= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_config_reg_t hri_wdt_read_CONFIG_reg(const void *const hw) +{ + return ((Wdt *)hw)->CONFIG.reg; +} + +static inline void hri_wdt_set_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg |= WDT_EWCTRL_EWOFFSET(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp = (tmp & WDT_EWCTRL_EWOFFSET(mask)) >> WDT_EWCTRL_EWOFFSET_Pos; + return tmp; +} + +static inline void hri_wdt_write_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t data) +{ + uint8_t tmp; + WDT_CRITICAL_SECTION_ENTER(); + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp &= ~WDT_EWCTRL_EWOFFSET_Msk; + tmp |= WDT_EWCTRL_EWOFFSET(data); + ((Wdt *)hw)->EWCTRL.reg = tmp; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg &= ~WDT_EWCTRL_EWOFFSET(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_EWCTRL_EWOFFSET_bf(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg ^= WDT_EWCTRL_EWOFFSET(mask); + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_EWOFFSET_bf(const void *const hw) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp = (tmp & WDT_EWCTRL_EWOFFSET_Msk) >> WDT_EWCTRL_EWOFFSET_Pos; + return tmp; +} + +static inline void hri_wdt_set_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg |= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_get_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + uint8_t tmp; + tmp = ((Wdt *)hw)->EWCTRL.reg; + tmp &= mask; + return tmp; +} + +static inline void hri_wdt_write_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg = data; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_clear_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg &= ~mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline void hri_wdt_toggle_EWCTRL_reg(const void *const hw, hri_wdt_ewctrl_reg_t mask) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->EWCTRL.reg ^= mask; + WDT_CRITICAL_SECTION_LEAVE(); +} + +static inline hri_wdt_ewctrl_reg_t hri_wdt_read_EWCTRL_reg(const void *const hw) +{ + return ((Wdt *)hw)->EWCTRL.reg; +} + +static inline void hri_wdt_write_CLEAR_reg(const void *const hw, hri_wdt_clear_reg_t data) +{ + WDT_CRITICAL_SECTION_ENTER(); + ((Wdt *)hw)->CLEAR.reg = data; + hri_wdt_wait_for_sync(hw, WDT_SYNCBUSY_CLEAR); + WDT_CRITICAL_SECTION_LEAVE(); +} + +#ifdef __cplusplus +} +#endif + +#endif /* _HRI_WDT_E54_H_INCLUDED */ +#endif /* _SAME54_WDT_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/include/component-version.h b/software/firmware/oracle_same54n19a/include/component-version.h new file mode 100644 index 00000000..d786d20d --- /dev/null +++ b/software/firmware/oracle_same54n19a/include/component-version.h @@ -0,0 +1,64 @@ +/** + * \file + * + * \brief Component version header file + * + * Copyright (c) 2019 Atmel Corporation, a wholly owned subsidiary of Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#ifndef _COMPONENT_VERSION_H_INCLUDED +#define _COMPONENT_VERSION_H_INCLUDED + +#define COMPONENT_VERSION_MAJOR 1 +#define COMPONENT_VERSION_MINOR 1 + +// +// The COMPONENT_VERSION define is composed of the major and the minor version number. +// +// The last four digits of the COMPONENT_VERSION is the minor version with leading zeros. +// The rest of the COMPONENT_VERSION is the major version. +// +#define COMPONENT_VERSION 10001 + +// +// The build number does not refer to the component, but to the build number +// of the device pack that provides the component. +// +#define BUILD_NUMBER 134 + +// +// The COMPONENT_VERSION_STRING is a string (enclosed in ") that can be used for logging or embedding. +// +#define COMPONENT_VERSION_STRING "1.1" + +// +// The COMPONENT_DATE_STRING contains a timestamp of when the pack was generated. +// +// The COMPONENT_DATE_STRING is written out using the following strftime pattern. +// +// "%Y-%m-%d %H:%M:%S" +// +// +#define COMPONENT_DATE_STRING "2019-04-09 08:16:19" + +#endif/* #ifndef _COMPONENT_VERSION_H_INCLUDED */ + diff --git a/software/firmware/oracle_same54n19a/include/component/ac.h b/software/firmware/oracle_same54n19a/include/component/ac.h new file mode 100644 index 00000000..e8a9fc42 --- /dev/null +++ b/software/firmware/oracle_same54n19a/include/component/ac.h @@ -0,0 +1,598 @@ +/** + * \file + * + * \brief Component description for AC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54_AC_COMPONENT_ +#define _SAME54_AC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR AC */ +/* ========================================================================== */ +/** \addtogroup SAME54_AC Analog Comparators */ +/*@{*/ + +#define AC_U2501 +#define REV_AC 0x100 + +/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_CTRLA_OFFSET 0x00 /**< \brief (AC_CTRLA offset) Control A */ +#define AC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLA reset_value) Control A */ + +#define AC_CTRLA_SWRST_Pos 0 /**< \brief (AC_CTRLA) Software Reset */ +#define AC_CTRLA_SWRST (_U_(0x1) << AC_CTRLA_SWRST_Pos) +#define AC_CTRLA_ENABLE_Pos 1 /**< \brief (AC_CTRLA) Enable */ +#define AC_CTRLA_ENABLE (_U_(0x1) << AC_CTRLA_ENABLE_Pos) +#define AC_CTRLA_MASK _U_(0x03) /**< \brief (AC_CTRLA) MASK Register */ + +/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */ + uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_CTRLB_OFFSET 0x01 /**< \brief (AC_CTRLB offset) Control B */ +#define AC_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AC_CTRLB reset_value) Control B */ + +#define AC_CTRLB_START0_Pos 0 /**< \brief (AC_CTRLB) Comparator 0 Start Comparison */ +#define AC_CTRLB_START0 (_U_(1) << AC_CTRLB_START0_Pos) +#define AC_CTRLB_START1_Pos 1 /**< \brief (AC_CTRLB) Comparator 1 Start Comparison */ +#define AC_CTRLB_START1 (_U_(1) << AC_CTRLB_START1_Pos) +#define AC_CTRLB_START_Pos 0 /**< \brief (AC_CTRLB) Comparator x Start Comparison */ +#define AC_CTRLB_START_Msk (_U_(0x3) << AC_CTRLB_START_Pos) +#define AC_CTRLB_START(value) (AC_CTRLB_START_Msk & ((value) << AC_CTRLB_START_Pos)) +#define AC_CTRLB_MASK _U_(0x03) /**< \brief (AC_CTRLB) MASK Register */ + +/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */ + uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input Enable */ + uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input Enable */ + uint16_t :2; /*!< bit: 10..11 Reserved */ + uint16_t INVEI0:1; /*!< bit: 12 Comparator 0 Input Event Invert Enable */ + uint16_t INVEI1:1; /*!< bit: 13 Comparator 1 Input Event Invert Enable */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */ + uint16_t :2; /*!< bit: 2.. 3 Reserved */ + uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input Enable */ + uint16_t :2; /*!< bit: 10..11 Reserved */ + uint16_t INVEI:2; /*!< bit: 12..13 Comparator x Input Event Invert Enable */ + uint16_t :2; /*!< bit: 14..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} AC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_EVCTRL_OFFSET 0x02 /**< \brief (AC_EVCTRL offset) Event Control */ +#define AC_EVCTRL_RESETVALUE _U_(0x0000) /**< \brief (AC_EVCTRL reset_value) Event Control */ + +#define AC_EVCTRL_COMPEO0_Pos 0 /**< \brief (AC_EVCTRL) Comparator 0 Event Output Enable */ +#define AC_EVCTRL_COMPEO0 (_U_(1) << AC_EVCTRL_COMPEO0_Pos) +#define AC_EVCTRL_COMPEO1_Pos 1 /**< \brief (AC_EVCTRL) Comparator 1 Event Output Enable */ +#define AC_EVCTRL_COMPEO1 (_U_(1) << AC_EVCTRL_COMPEO1_Pos) +#define AC_EVCTRL_COMPEO_Pos 0 /**< \brief (AC_EVCTRL) Comparator x Event Output Enable */ +#define AC_EVCTRL_COMPEO_Msk (_U_(0x3) << AC_EVCTRL_COMPEO_Pos) +#define AC_EVCTRL_COMPEO(value) (AC_EVCTRL_COMPEO_Msk & ((value) << AC_EVCTRL_COMPEO_Pos)) +#define AC_EVCTRL_WINEO0_Pos 4 /**< \brief (AC_EVCTRL) Window 0 Event Output Enable */ +#define AC_EVCTRL_WINEO0 (_U_(1) << AC_EVCTRL_WINEO0_Pos) +#define AC_EVCTRL_WINEO_Pos 4 /**< \brief (AC_EVCTRL) Window x Event Output Enable */ +#define AC_EVCTRL_WINEO_Msk (_U_(0x1) << AC_EVCTRL_WINEO_Pos) +#define AC_EVCTRL_WINEO(value) (AC_EVCTRL_WINEO_Msk & ((value) << AC_EVCTRL_WINEO_Pos)) +#define AC_EVCTRL_COMPEI0_Pos 8 /**< \brief (AC_EVCTRL) Comparator 0 Event Input Enable */ +#define AC_EVCTRL_COMPEI0 (_U_(1) << AC_EVCTRL_COMPEI0_Pos) +#define AC_EVCTRL_COMPEI1_Pos 9 /**< \brief (AC_EVCTRL) Comparator 1 Event Input Enable */ +#define AC_EVCTRL_COMPEI1 (_U_(1) << AC_EVCTRL_COMPEI1_Pos) +#define AC_EVCTRL_COMPEI_Pos 8 /**< \brief (AC_EVCTRL) Comparator x Event Input Enable */ +#define AC_EVCTRL_COMPEI_Msk (_U_(0x3) << AC_EVCTRL_COMPEI_Pos) +#define AC_EVCTRL_COMPEI(value) (AC_EVCTRL_COMPEI_Msk & ((value) << AC_EVCTRL_COMPEI_Pos)) +#define AC_EVCTRL_INVEI0_Pos 12 /**< \brief (AC_EVCTRL) Comparator 0 Input Event Invert Enable */ +#define AC_EVCTRL_INVEI0 (_U_(1) << AC_EVCTRL_INVEI0_Pos) +#define AC_EVCTRL_INVEI1_Pos 13 /**< \brief (AC_EVCTRL) Comparator 1 Input Event Invert Enable */ +#define AC_EVCTRL_INVEI1 (_U_(1) << AC_EVCTRL_INVEI1_Pos) +#define AC_EVCTRL_INVEI_Pos 12 /**< \brief (AC_EVCTRL) Comparator x Input Event Invert Enable */ +#define AC_EVCTRL_INVEI_Msk (_U_(0x3) << AC_EVCTRL_INVEI_Pos) +#define AC_EVCTRL_INVEI(value) (AC_EVCTRL_INVEI_Msk & ((value) << AC_EVCTRL_INVEI_Pos)) +#define AC_EVCTRL_MASK _U_(0x3313) /**< \brief (AC_EVCTRL) MASK Register */ + +/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTENCLR_OFFSET 0x04 /**< \brief (AC_INTENCLR offset) Interrupt Enable Clear */ +#define AC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define AC_INTENCLR_COMP0_Pos 0 /**< \brief (AC_INTENCLR) Comparator 0 Interrupt Enable */ +#define AC_INTENCLR_COMP0 (_U_(1) << AC_INTENCLR_COMP0_Pos) +#define AC_INTENCLR_COMP1_Pos 1 /**< \brief (AC_INTENCLR) Comparator 1 Interrupt Enable */ +#define AC_INTENCLR_COMP1 (_U_(1) << AC_INTENCLR_COMP1_Pos) +#define AC_INTENCLR_COMP_Pos 0 /**< \brief (AC_INTENCLR) Comparator x Interrupt Enable */ +#define AC_INTENCLR_COMP_Msk (_U_(0x3) << AC_INTENCLR_COMP_Pos) +#define AC_INTENCLR_COMP(value) (AC_INTENCLR_COMP_Msk & ((value) << AC_INTENCLR_COMP_Pos)) +#define AC_INTENCLR_WIN0_Pos 4 /**< \brief (AC_INTENCLR) Window 0 Interrupt Enable */ +#define AC_INTENCLR_WIN0 (_U_(1) << AC_INTENCLR_WIN0_Pos) +#define AC_INTENCLR_WIN_Pos 4 /**< \brief (AC_INTENCLR) Window x Interrupt Enable */ +#define AC_INTENCLR_WIN_Msk (_U_(0x1) << AC_INTENCLR_WIN_Pos) +#define AC_INTENCLR_WIN(value) (AC_INTENCLR_WIN_Msk & ((value) << AC_INTENCLR_WIN_Pos)) +#define AC_INTENCLR_MASK _U_(0x13) /**< \brief (AC_INTENCLR) MASK Register */ + +/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */ + uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */ + uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTENSET_OFFSET 0x05 /**< \brief (AC_INTENSET offset) Interrupt Enable Set */ +#define AC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AC_INTENSET reset_value) Interrupt Enable Set */ + +#define AC_INTENSET_COMP0_Pos 0 /**< \brief (AC_INTENSET) Comparator 0 Interrupt Enable */ +#define AC_INTENSET_COMP0 (_U_(1) << AC_INTENSET_COMP0_Pos) +#define AC_INTENSET_COMP1_Pos 1 /**< \brief (AC_INTENSET) Comparator 1 Interrupt Enable */ +#define AC_INTENSET_COMP1 (_U_(1) << AC_INTENSET_COMP1_Pos) +#define AC_INTENSET_COMP_Pos 0 /**< \brief (AC_INTENSET) Comparator x Interrupt Enable */ +#define AC_INTENSET_COMP_Msk (_U_(0x3) << AC_INTENSET_COMP_Pos) +#define AC_INTENSET_COMP(value) (AC_INTENSET_COMP_Msk & ((value) << AC_INTENSET_COMP_Pos)) +#define AC_INTENSET_WIN0_Pos 4 /**< \brief (AC_INTENSET) Window 0 Interrupt Enable */ +#define AC_INTENSET_WIN0 (_U_(1) << AC_INTENSET_WIN0_Pos) +#define AC_INTENSET_WIN_Pos 4 /**< \brief (AC_INTENSET) Window x Interrupt Enable */ +#define AC_INTENSET_WIN_Msk (_U_(0x1) << AC_INTENSET_WIN_Pos) +#define AC_INTENSET_WIN(value) (AC_INTENSET_WIN_Msk & ((value) << AC_INTENSET_WIN_Pos)) +#define AC_INTENSET_MASK _U_(0x13) /**< \brief (AC_INTENSET) MASK Register */ + +/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */ + __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */ + __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ + __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */ + __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */ + __I uint8_t :2; /*!< bit: 2.. 3 Reserved */ + __I uint8_t WIN:1; /*!< bit: 4 Window x */ + __I uint8_t :3; /*!< bit: 5.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_INTFLAG_OFFSET 0x06 /**< \brief (AC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define AC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define AC_INTFLAG_COMP0_Pos 0 /**< \brief (AC_INTFLAG) Comparator 0 */ +#define AC_INTFLAG_COMP0 (_U_(1) << AC_INTFLAG_COMP0_Pos) +#define AC_INTFLAG_COMP1_Pos 1 /**< \brief (AC_INTFLAG) Comparator 1 */ +#define AC_INTFLAG_COMP1 (_U_(1) << AC_INTFLAG_COMP1_Pos) +#define AC_INTFLAG_COMP_Pos 0 /**< \brief (AC_INTFLAG) Comparator x */ +#define AC_INTFLAG_COMP_Msk (_U_(0x3) << AC_INTFLAG_COMP_Pos) +#define AC_INTFLAG_COMP(value) (AC_INTFLAG_COMP_Msk & ((value) << AC_INTFLAG_COMP_Pos)) +#define AC_INTFLAG_WIN0_Pos 4 /**< \brief (AC_INTFLAG) Window 0 */ +#define AC_INTFLAG_WIN0 (_U_(1) << AC_INTFLAG_WIN0_Pos) +#define AC_INTFLAG_WIN_Pos 4 /**< \brief (AC_INTFLAG) Window x */ +#define AC_INTFLAG_WIN_Msk (_U_(0x1) << AC_INTFLAG_WIN_Pos) +#define AC_INTFLAG_WIN(value) (AC_INTFLAG_WIN_Msk & ((value) << AC_INTFLAG_WIN_Pos)) +#define AC_INTFLAG_MASK _U_(0x13) /**< \brief (AC_INTFLAG) MASK Register */ + +/* -------- AC_STATUSA : (AC Offset: 0x07) (R/ 8) Status A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */ + uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */ + uint8_t :2; /*!< bit: 2.. 3 Reserved */ + uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_STATUSA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_STATUSA_OFFSET 0x07 /**< \brief (AC_STATUSA offset) Status A */ +#define AC_STATUSA_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSA reset_value) Status A */ + +#define AC_STATUSA_STATE0_Pos 0 /**< \brief (AC_STATUSA) Comparator 0 Current State */ +#define AC_STATUSA_STATE0 (_U_(1) << AC_STATUSA_STATE0_Pos) +#define AC_STATUSA_STATE1_Pos 1 /**< \brief (AC_STATUSA) Comparator 1 Current State */ +#define AC_STATUSA_STATE1 (_U_(1) << AC_STATUSA_STATE1_Pos) +#define AC_STATUSA_STATE_Pos 0 /**< \brief (AC_STATUSA) Comparator x Current State */ +#define AC_STATUSA_STATE_Msk (_U_(0x3) << AC_STATUSA_STATE_Pos) +#define AC_STATUSA_STATE(value) (AC_STATUSA_STATE_Msk & ((value) << AC_STATUSA_STATE_Pos)) +#define AC_STATUSA_WSTATE0_Pos 4 /**< \brief (AC_STATUSA) Window 0 Current State */ +#define AC_STATUSA_WSTATE0_Msk (_U_(0x3) << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0(value) (AC_STATUSA_WSTATE0_Msk & ((value) << AC_STATUSA_WSTATE0_Pos)) +#define AC_STATUSA_WSTATE0_ABOVE_Val _U_(0x0) /**< \brief (AC_STATUSA) Signal is above window */ +#define AC_STATUSA_WSTATE0_INSIDE_Val _U_(0x1) /**< \brief (AC_STATUSA) Signal is inside window */ +#define AC_STATUSA_WSTATE0_BELOW_Val _U_(0x2) /**< \brief (AC_STATUSA) Signal is below window */ +#define AC_STATUSA_WSTATE0_ABOVE (AC_STATUSA_WSTATE0_ABOVE_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0_INSIDE (AC_STATUSA_WSTATE0_INSIDE_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_WSTATE0_BELOW (AC_STATUSA_WSTATE0_BELOW_Val << AC_STATUSA_WSTATE0_Pos) +#define AC_STATUSA_MASK _U_(0x33) /**< \brief (AC_STATUSA) MASK Register */ + +/* -------- AC_STATUSB : (AC Offset: 0x08) (R/ 8) Status B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */ + uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} AC_STATUSB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_STATUSB_OFFSET 0x08 /**< \brief (AC_STATUSB offset) Status B */ +#define AC_STATUSB_RESETVALUE _U_(0x00) /**< \brief (AC_STATUSB reset_value) Status B */ + +#define AC_STATUSB_READY0_Pos 0 /**< \brief (AC_STATUSB) Comparator 0 Ready */ +#define AC_STATUSB_READY0 (_U_(1) << AC_STATUSB_READY0_Pos) +#define AC_STATUSB_READY1_Pos 1 /**< \brief (AC_STATUSB) Comparator 1 Ready */ +#define AC_STATUSB_READY1 (_U_(1) << AC_STATUSB_READY1_Pos) +#define AC_STATUSB_READY_Pos 0 /**< \brief (AC_STATUSB) Comparator x Ready */ +#define AC_STATUSB_READY_Msk (_U_(0x3) << AC_STATUSB_READY_Pos) +#define AC_STATUSB_READY(value) (AC_STATUSB_READY_Msk & ((value) << AC_STATUSB_READY_Pos)) +#define AC_STATUSB_MASK _U_(0x03) /**< \brief (AC_STATUSB) MASK Register */ + +/* -------- AC_DBGCTRL : (AC Offset: 0x09) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_DBGCTRL_OFFSET 0x09 /**< \brief (AC_DBGCTRL offset) Debug Control */ +#define AC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_DBGCTRL reset_value) Debug Control */ + +#define AC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AC_DBGCTRL) Debug Run */ +#define AC_DBGCTRL_DBGRUN (_U_(0x1) << AC_DBGCTRL_DBGRUN_Pos) +#define AC_DBGCTRL_MASK _U_(0x01) /**< \brief (AC_DBGCTRL) MASK Register */ + +/* -------- AC_WINCTRL : (AC Offset: 0x0A) (R/W 8) Window Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */ + uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_WINCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_WINCTRL_OFFSET 0x0A /**< \brief (AC_WINCTRL offset) Window Control */ +#define AC_WINCTRL_RESETVALUE _U_(0x00) /**< \brief (AC_WINCTRL reset_value) Window Control */ + +#define AC_WINCTRL_WEN0_Pos 0 /**< \brief (AC_WINCTRL) Window 0 Mode Enable */ +#define AC_WINCTRL_WEN0 (_U_(0x1) << AC_WINCTRL_WEN0_Pos) +#define AC_WINCTRL_WINTSEL0_Pos 1 /**< \brief (AC_WINCTRL) Window 0 Interrupt Selection */ +#define AC_WINCTRL_WINTSEL0_Msk (_U_(0x3) << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0(value) (AC_WINCTRL_WINTSEL0_Msk & ((value) << AC_WINCTRL_WINTSEL0_Pos)) +#define AC_WINCTRL_WINTSEL0_ABOVE_Val _U_(0x0) /**< \brief (AC_WINCTRL) Interrupt on signal above window */ +#define AC_WINCTRL_WINTSEL0_INSIDE_Val _U_(0x1) /**< \brief (AC_WINCTRL) Interrupt on signal inside window */ +#define AC_WINCTRL_WINTSEL0_BELOW_Val _U_(0x2) /**< \brief (AC_WINCTRL) Interrupt on signal below window */ +#define AC_WINCTRL_WINTSEL0_OUTSIDE_Val _U_(0x3) /**< \brief (AC_WINCTRL) Interrupt on signal outside window */ +#define AC_WINCTRL_WINTSEL0_ABOVE (AC_WINCTRL_WINTSEL0_ABOVE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_INSIDE (AC_WINCTRL_WINTSEL0_INSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_BELOW (AC_WINCTRL_WINTSEL0_BELOW_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_WINTSEL0_OUTSIDE (AC_WINCTRL_WINTSEL0_OUTSIDE_Val << AC_WINCTRL_WINTSEL0_Pos) +#define AC_WINCTRL_MASK _U_(0x07) /**< \brief (AC_WINCTRL) MASK Register */ + +/* -------- AC_SCALER : (AC Offset: 0x0C) (R/W 8) Scaler n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AC_SCALER_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_SCALER_OFFSET 0x0C /**< \brief (AC_SCALER offset) Scaler n */ +#define AC_SCALER_RESETVALUE _U_(0x00) /**< \brief (AC_SCALER reset_value) Scaler n */ + +#define AC_SCALER_VALUE_Pos 0 /**< \brief (AC_SCALER) Scaler Value */ +#define AC_SCALER_VALUE_Msk (_U_(0x3F) << AC_SCALER_VALUE_Pos) +#define AC_SCALER_VALUE(value) (AC_SCALER_VALUE_Msk & ((value) << AC_SCALER_VALUE_Pos)) +#define AC_SCALER_MASK _U_(0x3F) /**< \brief (AC_SCALER) MASK Register */ + +/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t SINGLE:1; /*!< bit: 2 Single-Shot Mode */ + uint32_t INTSEL:2; /*!< bit: 3.. 4 Interrupt Selection */ + uint32_t :1; /*!< bit: 5 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */ + uint32_t :1; /*!< bit: 11 Reserved */ + uint32_t MUXPOS:3; /*!< bit: 12..14 Positive Input Mux Selection */ + uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */ + uint32_t SPEED:2; /*!< bit: 16..17 Speed Selection */ + uint32_t :1; /*!< bit: 18 Reserved */ + uint32_t HYSTEN:1; /*!< bit: 19 Hysteresis Enable */ + uint32_t HYST:2; /*!< bit: 20..21 Hysteresis Level */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */ + uint32_t :1; /*!< bit: 27 Reserved */ + uint32_t OUT:2; /*!< bit: 28..29 Output */ + uint32_t :2; /*!< bit: 30..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} AC_COMPCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_COMPCTRL_OFFSET 0x10 /**< \brief (AC_COMPCTRL offset) Comparator Control n */ +#define AC_COMPCTRL_RESETVALUE _U_(0x00000000) /**< \brief (AC_COMPCTRL reset_value) Comparator Control n */ + +#define AC_COMPCTRL_ENABLE_Pos 1 /**< \brief (AC_COMPCTRL) Enable */ +#define AC_COMPCTRL_ENABLE (_U_(0x1) << AC_COMPCTRL_ENABLE_Pos) +#define AC_COMPCTRL_SINGLE_Pos 2 /**< \brief (AC_COMPCTRL) Single-Shot Mode */ +#define AC_COMPCTRL_SINGLE (_U_(0x1) << AC_COMPCTRL_SINGLE_Pos) +#define AC_COMPCTRL_INTSEL_Pos 3 /**< \brief (AC_COMPCTRL) Interrupt Selection */ +#define AC_COMPCTRL_INTSEL_Msk (_U_(0x3) << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL(value) (AC_COMPCTRL_INTSEL_Msk & ((value) << AC_COMPCTRL_INTSEL_Pos)) +#define AC_COMPCTRL_INTSEL_TOGGLE_Val _U_(0x0) /**< \brief (AC_COMPCTRL) Interrupt on comparator output toggle */ +#define AC_COMPCTRL_INTSEL_RISING_Val _U_(0x1) /**< \brief (AC_COMPCTRL) Interrupt on comparator output rising */ +#define AC_COMPCTRL_INTSEL_FALLING_Val _U_(0x2) /**< \brief (AC_COMPCTRL) Interrupt on comparator output falling */ +#define AC_COMPCTRL_INTSEL_EOC_Val _U_(0x3) /**< \brief (AC_COMPCTRL) Interrupt on end of comparison (single-shot mode only) */ +#define AC_COMPCTRL_INTSEL_TOGGLE (AC_COMPCTRL_INTSEL_TOGGLE_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_RISING (AC_COMPCTRL_INTSEL_RISING_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_FALLING (AC_COMPCTRL_INTSEL_FALLING_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_INTSEL_EOC (AC_COMPCTRL_INTSEL_EOC_Val << AC_COMPCTRL_INTSEL_Pos) +#define AC_COMPCTRL_RUNSTDBY_Pos 6 /**< \brief (AC_COMPCTRL) Run in Standby */ +#define AC_COMPCTRL_RUNSTDBY (_U_(0x1) << AC_COMPCTRL_RUNSTDBY_Pos) +#define AC_COMPCTRL_MUXNEG_Pos 8 /**< \brief (AC_COMPCTRL) Negative Input Mux Selection */ +#define AC_COMPCTRL_MUXNEG_Msk (_U_(0x7) << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG(value) (AC_COMPCTRL_MUXNEG_Msk & ((value) << AC_COMPCTRL_MUXNEG_Pos)) +#define AC_COMPCTRL_MUXNEG_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXNEG_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXNEG_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXNEG_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXNEG_GND_Val _U_(0x4) /**< \brief (AC_COMPCTRL) Ground */ +#define AC_COMPCTRL_MUXNEG_VSCALE_Val _U_(0x5) /**< \brief (AC_COMPCTRL) VDD scaler */ +#define AC_COMPCTRL_MUXNEG_BANDGAP_Val _U_(0x6) /**< \brief (AC_COMPCTRL) Internal bandgap voltage */ +#define AC_COMPCTRL_MUXNEG_DAC_Val _U_(0x7) /**< \brief (AC_COMPCTRL) DAC output */ +#define AC_COMPCTRL_MUXNEG_PIN0 (AC_COMPCTRL_MUXNEG_PIN0_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN1 (AC_COMPCTRL_MUXNEG_PIN1_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN2 (AC_COMPCTRL_MUXNEG_PIN2_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_PIN3 (AC_COMPCTRL_MUXNEG_PIN3_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_GND (AC_COMPCTRL_MUXNEG_GND_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_VSCALE (AC_COMPCTRL_MUXNEG_VSCALE_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_BANDGAP (AC_COMPCTRL_MUXNEG_BANDGAP_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXNEG_DAC (AC_COMPCTRL_MUXNEG_DAC_Val << AC_COMPCTRL_MUXNEG_Pos) +#define AC_COMPCTRL_MUXPOS_Pos 12 /**< \brief (AC_COMPCTRL) Positive Input Mux Selection */ +#define AC_COMPCTRL_MUXPOS_Msk (_U_(0x7) << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS(value) (AC_COMPCTRL_MUXPOS_Msk & ((value) << AC_COMPCTRL_MUXPOS_Pos)) +#define AC_COMPCTRL_MUXPOS_PIN0_Val _U_(0x0) /**< \brief (AC_COMPCTRL) I/O pin 0 */ +#define AC_COMPCTRL_MUXPOS_PIN1_Val _U_(0x1) /**< \brief (AC_COMPCTRL) I/O pin 1 */ +#define AC_COMPCTRL_MUXPOS_PIN2_Val _U_(0x2) /**< \brief (AC_COMPCTRL) I/O pin 2 */ +#define AC_COMPCTRL_MUXPOS_PIN3_Val _U_(0x3) /**< \brief (AC_COMPCTRL) I/O pin 3 */ +#define AC_COMPCTRL_MUXPOS_VSCALE_Val _U_(0x4) /**< \brief (AC_COMPCTRL) VDD Scaler */ +#define AC_COMPCTRL_MUXPOS_PIN0 (AC_COMPCTRL_MUXPOS_PIN0_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN1 (AC_COMPCTRL_MUXPOS_PIN1_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN2 (AC_COMPCTRL_MUXPOS_PIN2_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_PIN3 (AC_COMPCTRL_MUXPOS_PIN3_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_MUXPOS_VSCALE (AC_COMPCTRL_MUXPOS_VSCALE_Val << AC_COMPCTRL_MUXPOS_Pos) +#define AC_COMPCTRL_SWAP_Pos 15 /**< \brief (AC_COMPCTRL) Swap Inputs and Invert */ +#define AC_COMPCTRL_SWAP (_U_(0x1) << AC_COMPCTRL_SWAP_Pos) +#define AC_COMPCTRL_SPEED_Pos 16 /**< \brief (AC_COMPCTRL) Speed Selection */ +#define AC_COMPCTRL_SPEED_Msk (_U_(0x3) << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_SPEED(value) (AC_COMPCTRL_SPEED_Msk & ((value) << AC_COMPCTRL_SPEED_Pos)) +#define AC_COMPCTRL_SPEED_HIGH_Val _U_(0x3) /**< \brief (AC_COMPCTRL) High speed */ +#define AC_COMPCTRL_SPEED_HIGH (AC_COMPCTRL_SPEED_HIGH_Val << AC_COMPCTRL_SPEED_Pos) +#define AC_COMPCTRL_HYSTEN_Pos 19 /**< \brief (AC_COMPCTRL) Hysteresis Enable */ +#define AC_COMPCTRL_HYSTEN (_U_(0x1) << AC_COMPCTRL_HYSTEN_Pos) +#define AC_COMPCTRL_HYST_Pos 20 /**< \brief (AC_COMPCTRL) Hysteresis Level */ +#define AC_COMPCTRL_HYST_Msk (_U_(0x3) << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_HYST(value) (AC_COMPCTRL_HYST_Msk & ((value) << AC_COMPCTRL_HYST_Pos)) +#define AC_COMPCTRL_HYST_HYST50_Val _U_(0x0) /**< \brief (AC_COMPCTRL) 50mV */ +#define AC_COMPCTRL_HYST_HYST100_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 100mV */ +#define AC_COMPCTRL_HYST_HYST150_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 150mV */ +#define AC_COMPCTRL_HYST_HYST50 (AC_COMPCTRL_HYST_HYST50_Val << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_HYST_HYST100 (AC_COMPCTRL_HYST_HYST100_Val << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_HYST_HYST150 (AC_COMPCTRL_HYST_HYST150_Val << AC_COMPCTRL_HYST_Pos) +#define AC_COMPCTRL_FLEN_Pos 24 /**< \brief (AC_COMPCTRL) Filter Length */ +#define AC_COMPCTRL_FLEN_Msk (_U_(0x7) << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN(value) (AC_COMPCTRL_FLEN_Msk & ((value) << AC_COMPCTRL_FLEN_Pos)) +#define AC_COMPCTRL_FLEN_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) No filtering */ +#define AC_COMPCTRL_FLEN_MAJ3_Val _U_(0x1) /**< \brief (AC_COMPCTRL) 3-bit majority function (2 of 3) */ +#define AC_COMPCTRL_FLEN_MAJ5_Val _U_(0x2) /**< \brief (AC_COMPCTRL) 5-bit majority function (3 of 5) */ +#define AC_COMPCTRL_FLEN_OFF (AC_COMPCTRL_FLEN_OFF_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN_MAJ3 (AC_COMPCTRL_FLEN_MAJ3_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_FLEN_MAJ5 (AC_COMPCTRL_FLEN_MAJ5_Val << AC_COMPCTRL_FLEN_Pos) +#define AC_COMPCTRL_OUT_Pos 28 /**< \brief (AC_COMPCTRL) Output */ +#define AC_COMPCTRL_OUT_Msk (_U_(0x3) << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT(value) (AC_COMPCTRL_OUT_Msk & ((value) << AC_COMPCTRL_OUT_Pos)) +#define AC_COMPCTRL_OUT_OFF_Val _U_(0x0) /**< \brief (AC_COMPCTRL) The output of COMPn is not routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_ASYNC_Val _U_(0x1) /**< \brief (AC_COMPCTRL) The asynchronous output of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_SYNC_Val _U_(0x2) /**< \brief (AC_COMPCTRL) The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port */ +#define AC_COMPCTRL_OUT_OFF (AC_COMPCTRL_OUT_OFF_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT_ASYNC (AC_COMPCTRL_OUT_ASYNC_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_OUT_SYNC (AC_COMPCTRL_OUT_SYNC_Val << AC_COMPCTRL_OUT_Pos) +#define AC_COMPCTRL_MASK _U_(0x373BF75E) /**< \brief (AC_COMPCTRL) MASK Register */ + +/* -------- AC_SYNCBUSY : (AC Offset: 0x20) (R/ 32) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ + uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ + uint32_t WINCTRL:1; /*!< bit: 2 WINCTRL Synchronization Busy */ + uint32_t COMPCTRL0:1; /*!< bit: 3 COMPCTRL 0 Synchronization Busy */ + uint32_t COMPCTRL1:1; /*!< bit: 4 COMPCTRL 1 Synchronization Busy */ + uint32_t :27; /*!< bit: 5..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :3; /*!< bit: 0.. 2 Reserved */ + uint32_t COMPCTRL:2; /*!< bit: 3.. 4 COMPCTRL x Synchronization Busy */ + uint32_t :27; /*!< bit: 5..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} AC_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_SYNCBUSY_OFFSET 0x20 /**< \brief (AC_SYNCBUSY offset) Synchronization Busy */ +#define AC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (AC_SYNCBUSY reset_value) Synchronization Busy */ + +#define AC_SYNCBUSY_SWRST_Pos 0 /**< \brief (AC_SYNCBUSY) Software Reset Synchronization Busy */ +#define AC_SYNCBUSY_SWRST (_U_(0x1) << AC_SYNCBUSY_SWRST_Pos) +#define AC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (AC_SYNCBUSY) Enable Synchronization Busy */ +#define AC_SYNCBUSY_ENABLE (_U_(0x1) << AC_SYNCBUSY_ENABLE_Pos) +#define AC_SYNCBUSY_WINCTRL_Pos 2 /**< \brief (AC_SYNCBUSY) WINCTRL Synchronization Busy */ +#define AC_SYNCBUSY_WINCTRL (_U_(0x1) << AC_SYNCBUSY_WINCTRL_Pos) +#define AC_SYNCBUSY_COMPCTRL0_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL 0 Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL0 (_U_(1) << AC_SYNCBUSY_COMPCTRL0_Pos) +#define AC_SYNCBUSY_COMPCTRL1_Pos 4 /**< \brief (AC_SYNCBUSY) COMPCTRL 1 Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL1 (_U_(1) << AC_SYNCBUSY_COMPCTRL1_Pos) +#define AC_SYNCBUSY_COMPCTRL_Pos 3 /**< \brief (AC_SYNCBUSY) COMPCTRL x Synchronization Busy */ +#define AC_SYNCBUSY_COMPCTRL_Msk (_U_(0x3) << AC_SYNCBUSY_COMPCTRL_Pos) +#define AC_SYNCBUSY_COMPCTRL(value) (AC_SYNCBUSY_COMPCTRL_Msk & ((value) << AC_SYNCBUSY_COMPCTRL_Pos)) +#define AC_SYNCBUSY_MASK _U_(0x0000001F) /**< \brief (AC_SYNCBUSY) MASK Register */ + +/* -------- AC_CALIB : (AC Offset: 0x24) (R/W 16) Calibration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t BIAS0:2; /*!< bit: 0.. 1 COMP0/1 Bias Scaling */ + uint16_t :14; /*!< bit: 2..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} AC_CALIB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AC_CALIB_OFFSET 0x24 /**< \brief (AC_CALIB offset) Calibration */ +#define AC_CALIB_RESETVALUE _U_(0x0101) /**< \brief (AC_CALIB reset_value) Calibration */ + +#define AC_CALIB_BIAS0_Pos 0 /**< \brief (AC_CALIB) COMP0/1 Bias Scaling */ +#define AC_CALIB_BIAS0_Msk (_U_(0x3) << AC_CALIB_BIAS0_Pos) +#define AC_CALIB_BIAS0(value) (AC_CALIB_BIAS0_Msk & ((value) << AC_CALIB_BIAS0_Pos)) +#define AC_CALIB_MASK _U_(0x0003) /**< \brief (AC_CALIB) MASK Register */ + +/** \brief AC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */ + __IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */ + __IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x07 (R/ 8) Status A */ + __I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x08 (R/ 8) Status B */ + __IO AC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug Control */ + __IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0A (R/W 8) Window Control */ + RoReg8 Reserved1[0x1]; + __IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x0C (R/W 8) Scaler n */ + RoReg8 Reserved2[0x2]; + __IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */ + RoReg8 Reserved3[0x8]; + __I AC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x20 (R/ 32) Synchronization Busy */ + __IO AC_CALIB_Type CALIB; /**< \brief Offset: 0x24 (R/W 16) Calibration */ +} Ac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAME54_AC_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/include/component/adc.h b/software/firmware/oracle_same54n19a/include/component/adc.h new file mode 100644 index 00000000..b2fee11e --- /dev/null +++ b/software/firmware/oracle_same54n19a/include/component/adc.h @@ -0,0 +1,871 @@ +/** + * \file + * + * \brief Component description for ADC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54_ADC_COMPONENT_ +#define _SAME54_ADC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR ADC */ +/* ========================================================================== */ +/** \addtogroup SAME54_ADC Analog Digital Converter */ +/*@{*/ + +#define ADC_U2500 +#define REV_ADC 0x100 + +/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 16) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t SWRST:1; /*!< bit: 0 Software Reset */ + uint16_t ENABLE:1; /*!< bit: 1 Enable */ + uint16_t :1; /*!< bit: 2 Reserved */ + uint16_t DUALSEL:2; /*!< bit: 3.. 4 Dual Mode Trigger Selection */ + uint16_t SLAVEEN:1; /*!< bit: 5 Slave Enable */ + uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ + uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */ + uint16_t :4; /*!< bit: 11..14 Reserved */ + uint16_t R2R:1; /*!< bit: 15 Rail to Rail Operation Enable */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CTRLA_OFFSET 0x00 /**< \brief (ADC_CTRLA offset) Control A */ +#define ADC_CTRLA_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLA reset_value) Control A */ + +#define ADC_CTRLA_SWRST_Pos 0 /**< \brief (ADC_CTRLA) Software Reset */ +#define ADC_CTRLA_SWRST (_U_(0x1) << ADC_CTRLA_SWRST_Pos) +#define ADC_CTRLA_ENABLE_Pos 1 /**< \brief (ADC_CTRLA) Enable */ +#define ADC_CTRLA_ENABLE (_U_(0x1) << ADC_CTRLA_ENABLE_Pos) +#define ADC_CTRLA_DUALSEL_Pos 3 /**< \brief (ADC_CTRLA) Dual Mode Trigger Selection */ +#define ADC_CTRLA_DUALSEL_Msk (_U_(0x3) << ADC_CTRLA_DUALSEL_Pos) +#define ADC_CTRLA_DUALSEL(value) (ADC_CTRLA_DUALSEL_Msk & ((value) << ADC_CTRLA_DUALSEL_Pos)) +#define ADC_CTRLA_DUALSEL_BOTH_Val _U_(0x0) /**< \brief (ADC_CTRLA) Start event or software trigger will start a conversion on both ADCs */ +#define ADC_CTRLA_DUALSEL_INTERLEAVE_Val _U_(0x1) /**< \brief (ADC_CTRLA) START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 */ +#define ADC_CTRLA_DUALSEL_BOTH (ADC_CTRLA_DUALSEL_BOTH_Val << ADC_CTRLA_DUALSEL_Pos) +#define ADC_CTRLA_DUALSEL_INTERLEAVE (ADC_CTRLA_DUALSEL_INTERLEAVE_Val << ADC_CTRLA_DUALSEL_Pos) +#define ADC_CTRLA_SLAVEEN_Pos 5 /**< \brief (ADC_CTRLA) Slave Enable */ +#define ADC_CTRLA_SLAVEEN (_U_(0x1) << ADC_CTRLA_SLAVEEN_Pos) +#define ADC_CTRLA_RUNSTDBY_Pos 6 /**< \brief (ADC_CTRLA) Run in Standby */ +#define ADC_CTRLA_RUNSTDBY (_U_(0x1) << ADC_CTRLA_RUNSTDBY_Pos) +#define ADC_CTRLA_ONDEMAND_Pos 7 /**< \brief (ADC_CTRLA) On Demand Control */ +#define ADC_CTRLA_ONDEMAND (_U_(0x1) << ADC_CTRLA_ONDEMAND_Pos) +#define ADC_CTRLA_PRESCALER_Pos 8 /**< \brief (ADC_CTRLA) Prescaler Configuration */ +#define ADC_CTRLA_PRESCALER_Msk (_U_(0x7) << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER(value) (ADC_CTRLA_PRESCALER_Msk & ((value) << ADC_CTRLA_PRESCALER_Pos)) +#define ADC_CTRLA_PRESCALER_DIV2_Val _U_(0x0) /**< \brief (ADC_CTRLA) Peripheral clock divided by 2 */ +#define ADC_CTRLA_PRESCALER_DIV4_Val _U_(0x1) /**< \brief (ADC_CTRLA) Peripheral clock divided by 4 */ +#define ADC_CTRLA_PRESCALER_DIV8_Val _U_(0x2) /**< \brief (ADC_CTRLA) Peripheral clock divided by 8 */ +#define ADC_CTRLA_PRESCALER_DIV16_Val _U_(0x3) /**< \brief (ADC_CTRLA) Peripheral clock divided by 16 */ +#define ADC_CTRLA_PRESCALER_DIV32_Val _U_(0x4) /**< \brief (ADC_CTRLA) Peripheral clock divided by 32 */ +#define ADC_CTRLA_PRESCALER_DIV64_Val _U_(0x5) /**< \brief (ADC_CTRLA) Peripheral clock divided by 64 */ +#define ADC_CTRLA_PRESCALER_DIV128_Val _U_(0x6) /**< \brief (ADC_CTRLA) Peripheral clock divided by 128 */ +#define ADC_CTRLA_PRESCALER_DIV256_Val _U_(0x7) /**< \brief (ADC_CTRLA) Peripheral clock divided by 256 */ +#define ADC_CTRLA_PRESCALER_DIV2 (ADC_CTRLA_PRESCALER_DIV2_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER_DIV4 (ADC_CTRLA_PRESCALER_DIV4_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER_DIV8 (ADC_CTRLA_PRESCALER_DIV8_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER_DIV16 (ADC_CTRLA_PRESCALER_DIV16_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER_DIV32 (ADC_CTRLA_PRESCALER_DIV32_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER_DIV64 (ADC_CTRLA_PRESCALER_DIV64_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER_DIV128 (ADC_CTRLA_PRESCALER_DIV128_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_PRESCALER_DIV256 (ADC_CTRLA_PRESCALER_DIV256_Val << ADC_CTRLA_PRESCALER_Pos) +#define ADC_CTRLA_R2R_Pos 15 /**< \brief (ADC_CTRLA) Rail to Rail Operation Enable */ +#define ADC_CTRLA_R2R (_U_(0x1) << ADC_CTRLA_R2R_Pos) +#define ADC_CTRLA_MASK _U_(0x87FB) /**< \brief (ADC_CTRLA) MASK Register */ + +/* -------- ADC_EVCTRL : (ADC Offset: 0x02) (R/W 8) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t FLUSHEI:1; /*!< bit: 0 Flush Event Input Enable */ + uint8_t STARTEI:1; /*!< bit: 1 Start Conversion Event Input Enable */ + uint8_t FLUSHINV:1; /*!< bit: 2 Flush Event Invert Enable */ + uint8_t STARTINV:1; /*!< bit: 3 Start Conversion Event Invert Enable */ + uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */ + uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */ + uint8_t :2; /*!< bit: 6.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_EVCTRL_OFFSET 0x02 /**< \brief (ADC_EVCTRL offset) Event Control */ +#define ADC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_EVCTRL reset_value) Event Control */ + +#define ADC_EVCTRL_FLUSHEI_Pos 0 /**< \brief (ADC_EVCTRL) Flush Event Input Enable */ +#define ADC_EVCTRL_FLUSHEI (_U_(0x1) << ADC_EVCTRL_FLUSHEI_Pos) +#define ADC_EVCTRL_STARTEI_Pos 1 /**< \brief (ADC_EVCTRL) Start Conversion Event Input Enable */ +#define ADC_EVCTRL_STARTEI (_U_(0x1) << ADC_EVCTRL_STARTEI_Pos) +#define ADC_EVCTRL_FLUSHINV_Pos 2 /**< \brief (ADC_EVCTRL) Flush Event Invert Enable */ +#define ADC_EVCTRL_FLUSHINV (_U_(0x1) << ADC_EVCTRL_FLUSHINV_Pos) +#define ADC_EVCTRL_STARTINV_Pos 3 /**< \brief (ADC_EVCTRL) Start Conversion Event Invert Enable */ +#define ADC_EVCTRL_STARTINV (_U_(0x1) << ADC_EVCTRL_STARTINV_Pos) +#define ADC_EVCTRL_RESRDYEO_Pos 4 /**< \brief (ADC_EVCTRL) Result Ready Event Out */ +#define ADC_EVCTRL_RESRDYEO (_U_(0x1) << ADC_EVCTRL_RESRDYEO_Pos) +#define ADC_EVCTRL_WINMONEO_Pos 5 /**< \brief (ADC_EVCTRL) Window Monitor Event Out */ +#define ADC_EVCTRL_WINMONEO (_U_(0x1) << ADC_EVCTRL_WINMONEO_Pos) +#define ADC_EVCTRL_MASK _U_(0x3F) /**< \brief (ADC_EVCTRL) MASK Register */ + +/* -------- ADC_DBGCTRL : (ADC Offset: 0x03) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_DBGCTRL_OFFSET 0x03 /**< \brief (ADC_DBGCTRL offset) Debug Control */ +#define ADC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_DBGCTRL reset_value) Debug Control */ + +#define ADC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (ADC_DBGCTRL) Debug Run */ +#define ADC_DBGCTRL_DBGRUN (_U_(0x1) << ADC_DBGCTRL_DBGRUN_Pos) +#define ADC_DBGCTRL_MASK _U_(0x01) /**< \brief (ADC_DBGCTRL) MASK Register */ + +/* -------- ADC_INPUTCTRL : (ADC Offset: 0x04) (R/W 16) Input Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */ + uint16_t :2; /*!< bit: 5.. 6 Reserved */ + uint16_t DIFFMODE:1; /*!< bit: 7 Differential Mode */ + uint16_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */ + uint16_t :2; /*!< bit: 13..14 Reserved */ + uint16_t DSEQSTOP:1; /*!< bit: 15 Stop DMA Sequencing */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_INPUTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INPUTCTRL_OFFSET 0x04 /**< \brief (ADC_INPUTCTRL offset) Input Control */ +#define ADC_INPUTCTRL_RESETVALUE _U_(0x0000) /**< \brief (ADC_INPUTCTRL reset_value) Input Control */ + +#define ADC_INPUTCTRL_MUXPOS_Pos 0 /**< \brief (ADC_INPUTCTRL) Positive Mux Input Selection */ +#define ADC_INPUTCTRL_MUXPOS_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS(value) (ADC_INPUTCTRL_MUXPOS_Msk & ((value) << ADC_INPUTCTRL_MUXPOS_Pos)) +#define ADC_INPUTCTRL_MUXPOS_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN8_Val _U_(0x8) /**< \brief (ADC_INPUTCTRL) ADC AIN8 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN9_Val _U_(0x9) /**< \brief (ADC_INPUTCTRL) ADC AIN9 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN10_Val _U_(0xA) /**< \brief (ADC_INPUTCTRL) ADC AIN10 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN11_Val _U_(0xB) /**< \brief (ADC_INPUTCTRL) ADC AIN11 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN12_Val _U_(0xC) /**< \brief (ADC_INPUTCTRL) ADC AIN12 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN13_Val _U_(0xD) /**< \brief (ADC_INPUTCTRL) ADC AIN13 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN14_Val _U_(0xE) /**< \brief (ADC_INPUTCTRL) ADC AIN14 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN15_Val _U_(0xF) /**< \brief (ADC_INPUTCTRL) ADC AIN15 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN16_Val _U_(0x10) /**< \brief (ADC_INPUTCTRL) ADC AIN16 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN17_Val _U_(0x11) /**< \brief (ADC_INPUTCTRL) ADC AIN17 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN18_Val _U_(0x12) /**< \brief (ADC_INPUTCTRL) ADC AIN18 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN19_Val _U_(0x13) /**< \brief (ADC_INPUTCTRL) ADC AIN19 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN20_Val _U_(0x14) /**< \brief (ADC_INPUTCTRL) ADC AIN20 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN21_Val _U_(0x15) /**< \brief (ADC_INPUTCTRL) ADC AIN21 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN22_Val _U_(0x16) /**< \brief (ADC_INPUTCTRL) ADC AIN22 Pin */ +#define ADC_INPUTCTRL_MUXPOS_AIN23_Val _U_(0x17) /**< \brief (ADC_INPUTCTRL) ADC AIN23 Pin */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled Core Supply */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val _U_(0x19) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled VBAT Supply */ +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val _U_(0x1A) /**< \brief (ADC_INPUTCTRL) 1/4 Scaled I/O Supply */ +#define ADC_INPUTCTRL_MUXPOS_BANDGAP_Val _U_(0x1B) /**< \brief (ADC_INPUTCTRL) Bandgap Voltage */ +#define ADC_INPUTCTRL_MUXPOS_PTAT_Val _U_(0x1C) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */ +#define ADC_INPUTCTRL_MUXPOS_CTAT_Val _U_(0x1D) /**< \brief (ADC_INPUTCTRL) Temperature Sensor */ +#define ADC_INPUTCTRL_MUXPOS_DAC_Val _U_(0x1E) /**< \brief (ADC_INPUTCTRL) DAC Output */ +#define ADC_INPUTCTRL_MUXPOS_PTC_Val _U_(0x1F) /**< \brief (ADC_INPUTCTRL) PTC output (only on ADC0) */ +#define ADC_INPUTCTRL_MUXPOS_AIN0 (ADC_INPUTCTRL_MUXPOS_AIN0_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN1 (ADC_INPUTCTRL_MUXPOS_AIN1_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN2 (ADC_INPUTCTRL_MUXPOS_AIN2_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN3 (ADC_INPUTCTRL_MUXPOS_AIN3_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN4 (ADC_INPUTCTRL_MUXPOS_AIN4_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN5 (ADC_INPUTCTRL_MUXPOS_AIN5_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN6 (ADC_INPUTCTRL_MUXPOS_AIN6_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN7 (ADC_INPUTCTRL_MUXPOS_AIN7_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN8 (ADC_INPUTCTRL_MUXPOS_AIN8_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN9 (ADC_INPUTCTRL_MUXPOS_AIN9_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN10 (ADC_INPUTCTRL_MUXPOS_AIN10_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN11 (ADC_INPUTCTRL_MUXPOS_AIN11_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN12 (ADC_INPUTCTRL_MUXPOS_AIN12_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN13 (ADC_INPUTCTRL_MUXPOS_AIN13_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN14 (ADC_INPUTCTRL_MUXPOS_AIN14_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN15 (ADC_INPUTCTRL_MUXPOS_AIN15_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN16 (ADC_INPUTCTRL_MUXPOS_AIN16_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN17 (ADC_INPUTCTRL_MUXPOS_AIN17_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN18 (ADC_INPUTCTRL_MUXPOS_AIN18_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN19 (ADC_INPUTCTRL_MUXPOS_AIN19_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN20 (ADC_INPUTCTRL_MUXPOS_AIN20_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN21 (ADC_INPUTCTRL_MUXPOS_AIN21_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN22 (ADC_INPUTCTRL_MUXPOS_AIN22_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_AIN23 (ADC_INPUTCTRL_MUXPOS_AIN23_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC (ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDVBAT (ADC_INPUTCTRL_MUXPOS_SCALEDVBAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC (ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_BANDGAP (ADC_INPUTCTRL_MUXPOS_BANDGAP_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PTAT (ADC_INPUTCTRL_MUXPOS_PTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_CTAT (ADC_INPUTCTRL_MUXPOS_CTAT_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_DAC (ADC_INPUTCTRL_MUXPOS_DAC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_MUXPOS_PTC (ADC_INPUTCTRL_MUXPOS_PTC_Val << ADC_INPUTCTRL_MUXPOS_Pos) +#define ADC_INPUTCTRL_DIFFMODE_Pos 7 /**< \brief (ADC_INPUTCTRL) Differential Mode */ +#define ADC_INPUTCTRL_DIFFMODE (_U_(0x1) << ADC_INPUTCTRL_DIFFMODE_Pos) +#define ADC_INPUTCTRL_MUXNEG_Pos 8 /**< \brief (ADC_INPUTCTRL) Negative Mux Input Selection */ +#define ADC_INPUTCTRL_MUXNEG_Msk (_U_(0x1F) << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG(value) (ADC_INPUTCTRL_MUXNEG_Msk & ((value) << ADC_INPUTCTRL_MUXNEG_Pos)) +#define ADC_INPUTCTRL_MUXNEG_AIN0_Val _U_(0x0) /**< \brief (ADC_INPUTCTRL) ADC AIN0 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN1_Val _U_(0x1) /**< \brief (ADC_INPUTCTRL) ADC AIN1 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN2_Val _U_(0x2) /**< \brief (ADC_INPUTCTRL) ADC AIN2 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN3_Val _U_(0x3) /**< \brief (ADC_INPUTCTRL) ADC AIN3 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN4_Val _U_(0x4) /**< \brief (ADC_INPUTCTRL) ADC AIN4 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN5_Val _U_(0x5) /**< \brief (ADC_INPUTCTRL) ADC AIN5 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN6_Val _U_(0x6) /**< \brief (ADC_INPUTCTRL) ADC AIN6 Pin */ +#define ADC_INPUTCTRL_MUXNEG_AIN7_Val _U_(0x7) /**< \brief (ADC_INPUTCTRL) ADC AIN7 Pin */ +#define ADC_INPUTCTRL_MUXNEG_GND_Val _U_(0x18) /**< \brief (ADC_INPUTCTRL) Internal Ground */ +#define ADC_INPUTCTRL_MUXNEG_AIN0 (ADC_INPUTCTRL_MUXNEG_AIN0_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN1 (ADC_INPUTCTRL_MUXNEG_AIN1_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN2 (ADC_INPUTCTRL_MUXNEG_AIN2_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN3 (ADC_INPUTCTRL_MUXNEG_AIN3_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN4 (ADC_INPUTCTRL_MUXNEG_AIN4_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN5 (ADC_INPUTCTRL_MUXNEG_AIN5_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN6 (ADC_INPUTCTRL_MUXNEG_AIN6_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_AIN7 (ADC_INPUTCTRL_MUXNEG_AIN7_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_MUXNEG_GND (ADC_INPUTCTRL_MUXNEG_GND_Val << ADC_INPUTCTRL_MUXNEG_Pos) +#define ADC_INPUTCTRL_DSEQSTOP_Pos 15 /**< \brief (ADC_INPUTCTRL) Stop DMA Sequencing */ +#define ADC_INPUTCTRL_DSEQSTOP (_U_(0x1) << ADC_INPUTCTRL_DSEQSTOP_Pos) +#define ADC_INPUTCTRL_MASK _U_(0x9F9F) /**< \brief (ADC_INPUTCTRL) MASK Register */ + +/* -------- ADC_CTRLB : (ADC Offset: 0x06) (R/W 16) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t LEFTADJ:1; /*!< bit: 0 Left-Adjusted Result */ + uint16_t FREERUN:1; /*!< bit: 1 Free Running Mode */ + uint16_t CORREN:1; /*!< bit: 2 Digital Correction Logic Enable */ + uint16_t RESSEL:2; /*!< bit: 3.. 4 Conversion Result Resolution */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t WINMODE:3; /*!< bit: 8..10 Window Monitor Mode */ + uint16_t WINSS:1; /*!< bit: 11 Window Single Sample */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CTRLB_OFFSET 0x06 /**< \brief (ADC_CTRLB offset) Control B */ +#define ADC_CTRLB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CTRLB reset_value) Control B */ + +#define ADC_CTRLB_LEFTADJ_Pos 0 /**< \brief (ADC_CTRLB) Left-Adjusted Result */ +#define ADC_CTRLB_LEFTADJ (_U_(0x1) << ADC_CTRLB_LEFTADJ_Pos) +#define ADC_CTRLB_FREERUN_Pos 1 /**< \brief (ADC_CTRLB) Free Running Mode */ +#define ADC_CTRLB_FREERUN (_U_(0x1) << ADC_CTRLB_FREERUN_Pos) +#define ADC_CTRLB_CORREN_Pos 2 /**< \brief (ADC_CTRLB) Digital Correction Logic Enable */ +#define ADC_CTRLB_CORREN (_U_(0x1) << ADC_CTRLB_CORREN_Pos) +#define ADC_CTRLB_RESSEL_Pos 3 /**< \brief (ADC_CTRLB) Conversion Result Resolution */ +#define ADC_CTRLB_RESSEL_Msk (_U_(0x3) << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL(value) (ADC_CTRLB_RESSEL_Msk & ((value) << ADC_CTRLB_RESSEL_Pos)) +#define ADC_CTRLB_RESSEL_12BIT_Val _U_(0x0) /**< \brief (ADC_CTRLB) 12-bit result */ +#define ADC_CTRLB_RESSEL_16BIT_Val _U_(0x1) /**< \brief (ADC_CTRLB) For averaging mode output */ +#define ADC_CTRLB_RESSEL_10BIT_Val _U_(0x2) /**< \brief (ADC_CTRLB) 10-bit result */ +#define ADC_CTRLB_RESSEL_8BIT_Val _U_(0x3) /**< \brief (ADC_CTRLB) 8-bit result */ +#define ADC_CTRLB_RESSEL_12BIT (ADC_CTRLB_RESSEL_12BIT_Val << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL_16BIT (ADC_CTRLB_RESSEL_16BIT_Val << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL_10BIT (ADC_CTRLB_RESSEL_10BIT_Val << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_RESSEL_8BIT (ADC_CTRLB_RESSEL_8BIT_Val << ADC_CTRLB_RESSEL_Pos) +#define ADC_CTRLB_WINMODE_Pos 8 /**< \brief (ADC_CTRLB) Window Monitor Mode */ +#define ADC_CTRLB_WINMODE_Msk (_U_(0x7) << ADC_CTRLB_WINMODE_Pos) +#define ADC_CTRLB_WINMODE(value) (ADC_CTRLB_WINMODE_Msk & ((value) << ADC_CTRLB_WINMODE_Pos)) +#define ADC_CTRLB_WINMODE_DISABLE_Val _U_(0x0) /**< \brief (ADC_CTRLB) No window mode (default) */ +#define ADC_CTRLB_WINMODE_MODE1_Val _U_(0x1) /**< \brief (ADC_CTRLB) RESULT > WINLT */ +#define ADC_CTRLB_WINMODE_MODE2_Val _U_(0x2) /**< \brief (ADC_CTRLB) RESULT < WINUT */ +#define ADC_CTRLB_WINMODE_MODE3_Val _U_(0x3) /**< \brief (ADC_CTRLB) WINLT < RESULT < WINUT */ +#define ADC_CTRLB_WINMODE_MODE4_Val _U_(0x4) /**< \brief (ADC_CTRLB) !(WINLT < RESULT < WINUT) */ +#define ADC_CTRLB_WINMODE_DISABLE (ADC_CTRLB_WINMODE_DISABLE_Val << ADC_CTRLB_WINMODE_Pos) +#define ADC_CTRLB_WINMODE_MODE1 (ADC_CTRLB_WINMODE_MODE1_Val << ADC_CTRLB_WINMODE_Pos) +#define ADC_CTRLB_WINMODE_MODE2 (ADC_CTRLB_WINMODE_MODE2_Val << ADC_CTRLB_WINMODE_Pos) +#define ADC_CTRLB_WINMODE_MODE3 (ADC_CTRLB_WINMODE_MODE3_Val << ADC_CTRLB_WINMODE_Pos) +#define ADC_CTRLB_WINMODE_MODE4 (ADC_CTRLB_WINMODE_MODE4_Val << ADC_CTRLB_WINMODE_Pos) +#define ADC_CTRLB_WINSS_Pos 11 /**< \brief (ADC_CTRLB) Window Single Sample */ +#define ADC_CTRLB_WINSS (_U_(0x1) << ADC_CTRLB_WINSS_Pos) +#define ADC_CTRLB_MASK _U_(0x0F1F) /**< \brief (ADC_CTRLB) MASK Register */ + +/* -------- ADC_REFCTRL : (ADC Offset: 0x08) (R/W 8) Reference Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */ + uint8_t :3; /*!< bit: 4.. 6 Reserved */ + uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_REFCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_REFCTRL_OFFSET 0x08 /**< \brief (ADC_REFCTRL offset) Reference Control */ +#define ADC_REFCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_REFCTRL reset_value) Reference Control */ + +#define ADC_REFCTRL_REFSEL_Pos 0 /**< \brief (ADC_REFCTRL) Reference Selection */ +#define ADC_REFCTRL_REFSEL_Msk (_U_(0xF) << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL(value) (ADC_REFCTRL_REFSEL_Msk & ((value) << ADC_REFCTRL_REFSEL_Pos)) +#define ADC_REFCTRL_REFSEL_INTREF_Val _U_(0x0) /**< \brief (ADC_REFCTRL) Internal Bandgap Reference */ +#define ADC_REFCTRL_REFSEL_INTVCC0_Val _U_(0x2) /**< \brief (ADC_REFCTRL) 1/2 VDDANA */ +#define ADC_REFCTRL_REFSEL_INTVCC1_Val _U_(0x3) /**< \brief (ADC_REFCTRL) VDDANA */ +#define ADC_REFCTRL_REFSEL_AREFA_Val _U_(0x4) /**< \brief (ADC_REFCTRL) External Reference */ +#define ADC_REFCTRL_REFSEL_AREFB_Val _U_(0x5) /**< \brief (ADC_REFCTRL) External Reference */ +#define ADC_REFCTRL_REFSEL_AREFC_Val _U_(0x6) /**< \brief (ADC_REFCTRL) External Reference (only on ADC1) */ +#define ADC_REFCTRL_REFSEL_INTREF (ADC_REFCTRL_REFSEL_INTREF_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_INTVCC0 (ADC_REFCTRL_REFSEL_INTVCC0_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_INTVCC1 (ADC_REFCTRL_REFSEL_INTVCC1_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_AREFA (ADC_REFCTRL_REFSEL_AREFA_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_AREFB (ADC_REFCTRL_REFSEL_AREFB_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFSEL_AREFC (ADC_REFCTRL_REFSEL_AREFC_Val << ADC_REFCTRL_REFSEL_Pos) +#define ADC_REFCTRL_REFCOMP_Pos 7 /**< \brief (ADC_REFCTRL) Reference Buffer Offset Compensation Enable */ +#define ADC_REFCTRL_REFCOMP (_U_(0x1) << ADC_REFCTRL_REFCOMP_Pos) +#define ADC_REFCTRL_MASK _U_(0x8F) /**< \brief (ADC_REFCTRL) MASK Register */ + +/* -------- ADC_AVGCTRL : (ADC Offset: 0x0A) (R/W 8) Average Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */ + uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_AVGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_AVGCTRL_OFFSET 0x0A /**< \brief (ADC_AVGCTRL offset) Average Control */ +#define ADC_AVGCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_AVGCTRL reset_value) Average Control */ + +#define ADC_AVGCTRL_SAMPLENUM_Pos 0 /**< \brief (ADC_AVGCTRL) Number of Samples to be Collected */ +#define ADC_AVGCTRL_SAMPLENUM_Msk (_U_(0xF) << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM(value) (ADC_AVGCTRL_SAMPLENUM_Msk & ((value) << ADC_AVGCTRL_SAMPLENUM_Pos)) +#define ADC_AVGCTRL_SAMPLENUM_1_Val _U_(0x0) /**< \brief (ADC_AVGCTRL) 1 sample */ +#define ADC_AVGCTRL_SAMPLENUM_2_Val _U_(0x1) /**< \brief (ADC_AVGCTRL) 2 samples */ +#define ADC_AVGCTRL_SAMPLENUM_4_Val _U_(0x2) /**< \brief (ADC_AVGCTRL) 4 samples */ +#define ADC_AVGCTRL_SAMPLENUM_8_Val _U_(0x3) /**< \brief (ADC_AVGCTRL) 8 samples */ +#define ADC_AVGCTRL_SAMPLENUM_16_Val _U_(0x4) /**< \brief (ADC_AVGCTRL) 16 samples */ +#define ADC_AVGCTRL_SAMPLENUM_32_Val _U_(0x5) /**< \brief (ADC_AVGCTRL) 32 samples */ +#define ADC_AVGCTRL_SAMPLENUM_64_Val _U_(0x6) /**< \brief (ADC_AVGCTRL) 64 samples */ +#define ADC_AVGCTRL_SAMPLENUM_128_Val _U_(0x7) /**< \brief (ADC_AVGCTRL) 128 samples */ +#define ADC_AVGCTRL_SAMPLENUM_256_Val _U_(0x8) /**< \brief (ADC_AVGCTRL) 256 samples */ +#define ADC_AVGCTRL_SAMPLENUM_512_Val _U_(0x9) /**< \brief (ADC_AVGCTRL) 512 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1024_Val _U_(0xA) /**< \brief (ADC_AVGCTRL) 1024 samples */ +#define ADC_AVGCTRL_SAMPLENUM_1 (ADC_AVGCTRL_SAMPLENUM_1_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_2 (ADC_AVGCTRL_SAMPLENUM_2_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_4 (ADC_AVGCTRL_SAMPLENUM_4_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_8 (ADC_AVGCTRL_SAMPLENUM_8_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_16 (ADC_AVGCTRL_SAMPLENUM_16_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_32 (ADC_AVGCTRL_SAMPLENUM_32_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_64 (ADC_AVGCTRL_SAMPLENUM_64_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_128 (ADC_AVGCTRL_SAMPLENUM_128_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_256 (ADC_AVGCTRL_SAMPLENUM_256_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_512 (ADC_AVGCTRL_SAMPLENUM_512_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_SAMPLENUM_1024 (ADC_AVGCTRL_SAMPLENUM_1024_Val << ADC_AVGCTRL_SAMPLENUM_Pos) +#define ADC_AVGCTRL_ADJRES_Pos 4 /**< \brief (ADC_AVGCTRL) Adjusting Result / Division Coefficient */ +#define ADC_AVGCTRL_ADJRES_Msk (_U_(0x7) << ADC_AVGCTRL_ADJRES_Pos) +#define ADC_AVGCTRL_ADJRES(value) (ADC_AVGCTRL_ADJRES_Msk & ((value) << ADC_AVGCTRL_ADJRES_Pos)) +#define ADC_AVGCTRL_MASK _U_(0x7F) /**< \brief (ADC_AVGCTRL) MASK Register */ + +/* -------- ADC_SAMPCTRL : (ADC Offset: 0x0B) (R/W 8) Sample Time Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */ + uint8_t :1; /*!< bit: 6 Reserved */ + uint8_t OFFCOMP:1; /*!< bit: 7 Comparator Offset Compensation Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_SAMPCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SAMPCTRL_OFFSET 0x0B /**< \brief (ADC_SAMPCTRL offset) Sample Time Control */ +#define ADC_SAMPCTRL_RESETVALUE _U_(0x00) /**< \brief (ADC_SAMPCTRL reset_value) Sample Time Control */ + +#define ADC_SAMPCTRL_SAMPLEN_Pos 0 /**< \brief (ADC_SAMPCTRL) Sampling Time Length */ +#define ADC_SAMPCTRL_SAMPLEN_Msk (_U_(0x3F) << ADC_SAMPCTRL_SAMPLEN_Pos) +#define ADC_SAMPCTRL_SAMPLEN(value) (ADC_SAMPCTRL_SAMPLEN_Msk & ((value) << ADC_SAMPCTRL_SAMPLEN_Pos)) +#define ADC_SAMPCTRL_OFFCOMP_Pos 7 /**< \brief (ADC_SAMPCTRL) Comparator Offset Compensation Enable */ +#define ADC_SAMPCTRL_OFFCOMP (_U_(0x1) << ADC_SAMPCTRL_OFFCOMP_Pos) +#define ADC_SAMPCTRL_MASK _U_(0xBF) /**< \brief (ADC_SAMPCTRL) MASK Register */ + +/* -------- ADC_WINLT : (ADC Offset: 0x0C) (R/W 16) Window Monitor Lower Threshold -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_WINLT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_WINLT_OFFSET 0x0C /**< \brief (ADC_WINLT offset) Window Monitor Lower Threshold */ +#define ADC_WINLT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINLT reset_value) Window Monitor Lower Threshold */ + +#define ADC_WINLT_WINLT_Pos 0 /**< \brief (ADC_WINLT) Window Lower Threshold */ +#define ADC_WINLT_WINLT_Msk (_U_(0xFFFF) << ADC_WINLT_WINLT_Pos) +#define ADC_WINLT_WINLT(value) (ADC_WINLT_WINLT_Msk & ((value) << ADC_WINLT_WINLT_Pos)) +#define ADC_WINLT_MASK _U_(0xFFFF) /**< \brief (ADC_WINLT) MASK Register */ + +/* -------- ADC_WINUT : (ADC Offset: 0x0E) (R/W 16) Window Monitor Upper Threshold -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_WINUT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_WINUT_OFFSET 0x0E /**< \brief (ADC_WINUT offset) Window Monitor Upper Threshold */ +#define ADC_WINUT_RESETVALUE _U_(0x0000) /**< \brief (ADC_WINUT reset_value) Window Monitor Upper Threshold */ + +#define ADC_WINUT_WINUT_Pos 0 /**< \brief (ADC_WINUT) Window Upper Threshold */ +#define ADC_WINUT_WINUT_Msk (_U_(0xFFFF) << ADC_WINUT_WINUT_Pos) +#define ADC_WINUT_WINUT(value) (ADC_WINUT_WINUT_Msk & ((value) << ADC_WINUT_WINUT_Pos)) +#define ADC_WINUT_MASK _U_(0xFFFF) /**< \brief (ADC_WINUT) MASK Register */ + +/* -------- ADC_GAINCORR : (ADC Offset: 0x10) (R/W 16) Gain Correction -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_GAINCORR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_GAINCORR_OFFSET 0x10 /**< \brief (ADC_GAINCORR offset) Gain Correction */ +#define ADC_GAINCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_GAINCORR reset_value) Gain Correction */ + +#define ADC_GAINCORR_GAINCORR_Pos 0 /**< \brief (ADC_GAINCORR) Gain Correction Value */ +#define ADC_GAINCORR_GAINCORR_Msk (_U_(0xFFF) << ADC_GAINCORR_GAINCORR_Pos) +#define ADC_GAINCORR_GAINCORR(value) (ADC_GAINCORR_GAINCORR_Msk & ((value) << ADC_GAINCORR_GAINCORR_Pos)) +#define ADC_GAINCORR_MASK _U_(0x0FFF) /**< \brief (ADC_GAINCORR) MASK Register */ + +/* -------- ADC_OFFSETCORR : (ADC Offset: 0x12) (R/W 16) Offset Correction -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_OFFSETCORR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_OFFSETCORR_OFFSET 0x12 /**< \brief (ADC_OFFSETCORR offset) Offset Correction */ +#define ADC_OFFSETCORR_RESETVALUE _U_(0x0000) /**< \brief (ADC_OFFSETCORR reset_value) Offset Correction */ + +#define ADC_OFFSETCORR_OFFSETCORR_Pos 0 /**< \brief (ADC_OFFSETCORR) Offset Correction Value */ +#define ADC_OFFSETCORR_OFFSETCORR_Msk (_U_(0xFFF) << ADC_OFFSETCORR_OFFSETCORR_Pos) +#define ADC_OFFSETCORR_OFFSETCORR(value) (ADC_OFFSETCORR_OFFSETCORR_Msk & ((value) << ADC_OFFSETCORR_OFFSETCORR_Pos)) +#define ADC_OFFSETCORR_MASK _U_(0x0FFF) /**< \brief (ADC_OFFSETCORR) MASK Register */ + +/* -------- ADC_SWTRIG : (ADC Offset: 0x14) (R/W 8) Software Trigger -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */ + uint8_t START:1; /*!< bit: 1 Start ADC Conversion */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_SWTRIG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SWTRIG_OFFSET 0x14 /**< \brief (ADC_SWTRIG offset) Software Trigger */ +#define ADC_SWTRIG_RESETVALUE _U_(0x00) /**< \brief (ADC_SWTRIG reset_value) Software Trigger */ + +#define ADC_SWTRIG_FLUSH_Pos 0 /**< \brief (ADC_SWTRIG) ADC Conversion Flush */ +#define ADC_SWTRIG_FLUSH (_U_(0x1) << ADC_SWTRIG_FLUSH_Pos) +#define ADC_SWTRIG_START_Pos 1 /**< \brief (ADC_SWTRIG) Start ADC Conversion */ +#define ADC_SWTRIG_START (_U_(0x1) << ADC_SWTRIG_START_Pos) +#define ADC_SWTRIG_MASK _U_(0x03) /**< \brief (ADC_SWTRIG) MASK Register */ + +/* -------- ADC_INTENCLR : (ADC Offset: 0x2C) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Disable */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Disable */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Disable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTENCLR_OFFSET 0x2C /**< \brief (ADC_INTENCLR offset) Interrupt Enable Clear */ +#define ADC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define ADC_INTENCLR_RESRDY_Pos 0 /**< \brief (ADC_INTENCLR) Result Ready Interrupt Disable */ +#define ADC_INTENCLR_RESRDY (_U_(0x1) << ADC_INTENCLR_RESRDY_Pos) +#define ADC_INTENCLR_OVERRUN_Pos 1 /**< \brief (ADC_INTENCLR) Overrun Interrupt Disable */ +#define ADC_INTENCLR_OVERRUN (_U_(0x1) << ADC_INTENCLR_OVERRUN_Pos) +#define ADC_INTENCLR_WINMON_Pos 2 /**< \brief (ADC_INTENCLR) Window Monitor Interrupt Disable */ +#define ADC_INTENCLR_WINMON (_U_(0x1) << ADC_INTENCLR_WINMON_Pos) +#define ADC_INTENCLR_MASK _U_(0x07) /**< \brief (ADC_INTENCLR) MASK Register */ + +/* -------- ADC_INTENSET : (ADC Offset: 0x2D) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */ + uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */ + uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTENSET_OFFSET 0x2D /**< \brief (ADC_INTENSET offset) Interrupt Enable Set */ +#define ADC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (ADC_INTENSET reset_value) Interrupt Enable Set */ + +#define ADC_INTENSET_RESRDY_Pos 0 /**< \brief (ADC_INTENSET) Result Ready Interrupt Enable */ +#define ADC_INTENSET_RESRDY (_U_(0x1) << ADC_INTENSET_RESRDY_Pos) +#define ADC_INTENSET_OVERRUN_Pos 1 /**< \brief (ADC_INTENSET) Overrun Interrupt Enable */ +#define ADC_INTENSET_OVERRUN (_U_(0x1) << ADC_INTENSET_OVERRUN_Pos) +#define ADC_INTENSET_WINMON_Pos 2 /**< \brief (ADC_INTENSET) Window Monitor Interrupt Enable */ +#define ADC_INTENSET_WINMON (_U_(0x1) << ADC_INTENSET_WINMON_Pos) +#define ADC_INTENSET_MASK _U_(0x07) /**< \brief (ADC_INTENSET) MASK Register */ + +/* -------- ADC_INTFLAG : (ADC Offset: 0x2E) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Flag */ + __I uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Flag */ + __I uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Flag */ + __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_INTFLAG_OFFSET 0x2E /**< \brief (ADC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define ADC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (ADC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define ADC_INTFLAG_RESRDY_Pos 0 /**< \brief (ADC_INTFLAG) Result Ready Interrupt Flag */ +#define ADC_INTFLAG_RESRDY (_U_(0x1) << ADC_INTFLAG_RESRDY_Pos) +#define ADC_INTFLAG_OVERRUN_Pos 1 /**< \brief (ADC_INTFLAG) Overrun Interrupt Flag */ +#define ADC_INTFLAG_OVERRUN (_U_(0x1) << ADC_INTFLAG_OVERRUN_Pos) +#define ADC_INTFLAG_WINMON_Pos 2 /**< \brief (ADC_INTFLAG) Window Monitor Interrupt Flag */ +#define ADC_INTFLAG_WINMON (_U_(0x1) << ADC_INTFLAG_WINMON_Pos) +#define ADC_INTFLAG_MASK _U_(0x07) /**< \brief (ADC_INTFLAG) MASK Register */ + +/* -------- ADC_STATUS : (ADC Offset: 0x2F) (R/ 8) Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ADCBUSY:1; /*!< bit: 0 ADC Busy Status */ + uint8_t :1; /*!< bit: 1 Reserved */ + uint8_t WCC:6; /*!< bit: 2.. 7 Window Comparator Counter */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} ADC_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_STATUS_OFFSET 0x2F /**< \brief (ADC_STATUS offset) Status */ +#define ADC_STATUS_RESETVALUE _U_(0x00) /**< \brief (ADC_STATUS reset_value) Status */ + +#define ADC_STATUS_ADCBUSY_Pos 0 /**< \brief (ADC_STATUS) ADC Busy Status */ +#define ADC_STATUS_ADCBUSY (_U_(0x1) << ADC_STATUS_ADCBUSY_Pos) +#define ADC_STATUS_WCC_Pos 2 /**< \brief (ADC_STATUS) Window Comparator Counter */ +#define ADC_STATUS_WCC_Msk (_U_(0x3F) << ADC_STATUS_WCC_Pos) +#define ADC_STATUS_WCC(value) (ADC_STATUS_WCC_Msk & ((value) << ADC_STATUS_WCC_Pos)) +#define ADC_STATUS_MASK _U_(0xFD) /**< \brief (ADC_STATUS) MASK Register */ + +/* -------- ADC_SYNCBUSY : (ADC Offset: 0x30) (R/ 32) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 SWRST Synchronization Busy */ + uint32_t ENABLE:1; /*!< bit: 1 ENABLE Synchronization Busy */ + uint32_t INPUTCTRL:1; /*!< bit: 2 Input Control Synchronization Busy */ + uint32_t CTRLB:1; /*!< bit: 3 Control B Synchronization Busy */ + uint32_t REFCTRL:1; /*!< bit: 4 Reference Control Synchronization Busy */ + uint32_t AVGCTRL:1; /*!< bit: 5 Average Control Synchronization Busy */ + uint32_t SAMPCTRL:1; /*!< bit: 6 Sampling Time Control Synchronization Busy */ + uint32_t WINLT:1; /*!< bit: 7 Window Monitor Lower Threshold Synchronization Busy */ + uint32_t WINUT:1; /*!< bit: 8 Window Monitor Upper Threshold Synchronization Busy */ + uint32_t GAINCORR:1; /*!< bit: 9 Gain Correction Synchronization Busy */ + uint32_t OFFSETCORR:1; /*!< bit: 10 Offset Correction Synchronization Busy */ + uint32_t SWTRIG:1; /*!< bit: 11 Software Trigger Synchronization Busy */ + uint32_t :20; /*!< bit: 12..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} ADC_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_SYNCBUSY_OFFSET 0x30 /**< \brief (ADC_SYNCBUSY offset) Synchronization Busy */ +#define ADC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (ADC_SYNCBUSY reset_value) Synchronization Busy */ + +#define ADC_SYNCBUSY_SWRST_Pos 0 /**< \brief (ADC_SYNCBUSY) SWRST Synchronization Busy */ +#define ADC_SYNCBUSY_SWRST (_U_(0x1) << ADC_SYNCBUSY_SWRST_Pos) +#define ADC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (ADC_SYNCBUSY) ENABLE Synchronization Busy */ +#define ADC_SYNCBUSY_ENABLE (_U_(0x1) << ADC_SYNCBUSY_ENABLE_Pos) +#define ADC_SYNCBUSY_INPUTCTRL_Pos 2 /**< \brief (ADC_SYNCBUSY) Input Control Synchronization Busy */ +#define ADC_SYNCBUSY_INPUTCTRL (_U_(0x1) << ADC_SYNCBUSY_INPUTCTRL_Pos) +#define ADC_SYNCBUSY_CTRLB_Pos 3 /**< \brief (ADC_SYNCBUSY) Control B Synchronization Busy */ +#define ADC_SYNCBUSY_CTRLB (_U_(0x1) << ADC_SYNCBUSY_CTRLB_Pos) +#define ADC_SYNCBUSY_REFCTRL_Pos 4 /**< \brief (ADC_SYNCBUSY) Reference Control Synchronization Busy */ +#define ADC_SYNCBUSY_REFCTRL (_U_(0x1) << ADC_SYNCBUSY_REFCTRL_Pos) +#define ADC_SYNCBUSY_AVGCTRL_Pos 5 /**< \brief (ADC_SYNCBUSY) Average Control Synchronization Busy */ +#define ADC_SYNCBUSY_AVGCTRL (_U_(0x1) << ADC_SYNCBUSY_AVGCTRL_Pos) +#define ADC_SYNCBUSY_SAMPCTRL_Pos 6 /**< \brief (ADC_SYNCBUSY) Sampling Time Control Synchronization Busy */ +#define ADC_SYNCBUSY_SAMPCTRL (_U_(0x1) << ADC_SYNCBUSY_SAMPCTRL_Pos) +#define ADC_SYNCBUSY_WINLT_Pos 7 /**< \brief (ADC_SYNCBUSY) Window Monitor Lower Threshold Synchronization Busy */ +#define ADC_SYNCBUSY_WINLT (_U_(0x1) << ADC_SYNCBUSY_WINLT_Pos) +#define ADC_SYNCBUSY_WINUT_Pos 8 /**< \brief (ADC_SYNCBUSY) Window Monitor Upper Threshold Synchronization Busy */ +#define ADC_SYNCBUSY_WINUT (_U_(0x1) << ADC_SYNCBUSY_WINUT_Pos) +#define ADC_SYNCBUSY_GAINCORR_Pos 9 /**< \brief (ADC_SYNCBUSY) Gain Correction Synchronization Busy */ +#define ADC_SYNCBUSY_GAINCORR (_U_(0x1) << ADC_SYNCBUSY_GAINCORR_Pos) +#define ADC_SYNCBUSY_OFFSETCORR_Pos 10 /**< \brief (ADC_SYNCBUSY) Offset Correction Synchronization Busy */ +#define ADC_SYNCBUSY_OFFSETCORR (_U_(0x1) << ADC_SYNCBUSY_OFFSETCORR_Pos) +#define ADC_SYNCBUSY_SWTRIG_Pos 11 /**< \brief (ADC_SYNCBUSY) Software Trigger Synchronization Busy */ +#define ADC_SYNCBUSY_SWTRIG (_U_(0x1) << ADC_SYNCBUSY_SWTRIG_Pos) +#define ADC_SYNCBUSY_MASK _U_(0x00000FFF) /**< \brief (ADC_SYNCBUSY) MASK Register */ + +/* -------- ADC_DSEQDATA : (ADC Offset: 0x34) ( /W 32) DMA Sequencial Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DATA:32; /*!< bit: 0..31 DMA Sequential Data */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} ADC_DSEQDATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_DSEQDATA_OFFSET 0x34 /**< \brief (ADC_DSEQDATA offset) DMA Sequencial Data */ +#define ADC_DSEQDATA_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQDATA reset_value) DMA Sequencial Data */ + +#define ADC_DSEQDATA_DATA_Pos 0 /**< \brief (ADC_DSEQDATA) DMA Sequential Data */ +#define ADC_DSEQDATA_DATA_Msk (_U_(0xFFFFFFFF) << ADC_DSEQDATA_DATA_Pos) +#define ADC_DSEQDATA_DATA(value) (ADC_DSEQDATA_DATA_Msk & ((value) << ADC_DSEQDATA_DATA_Pos)) +#define ADC_DSEQDATA_MASK _U_(0xFFFFFFFF) /**< \brief (ADC_DSEQDATA) MASK Register */ + +/* -------- ADC_DSEQCTRL : (ADC Offset: 0x38) (R/W 32) DMA Sequential Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t INPUTCTRL:1; /*!< bit: 0 Input Control */ + uint32_t CTRLB:1; /*!< bit: 1 Control B */ + uint32_t REFCTRL:1; /*!< bit: 2 Reference Control */ + uint32_t AVGCTRL:1; /*!< bit: 3 Average Control */ + uint32_t SAMPCTRL:1; /*!< bit: 4 Sampling Time Control */ + uint32_t WINLT:1; /*!< bit: 5 Window Monitor Lower Threshold */ + uint32_t WINUT:1; /*!< bit: 6 Window Monitor Upper Threshold */ + uint32_t GAINCORR:1; /*!< bit: 7 Gain Correction */ + uint32_t OFFSETCORR:1; /*!< bit: 8 Offset Correction */ + uint32_t :22; /*!< bit: 9..30 Reserved */ + uint32_t AUTOSTART:1; /*!< bit: 31 ADC Auto-Start Conversion */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} ADC_DSEQCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_DSEQCTRL_OFFSET 0x38 /**< \brief (ADC_DSEQCTRL offset) DMA Sequential Control */ +#define ADC_DSEQCTRL_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQCTRL reset_value) DMA Sequential Control */ + +#define ADC_DSEQCTRL_INPUTCTRL_Pos 0 /**< \brief (ADC_DSEQCTRL) Input Control */ +#define ADC_DSEQCTRL_INPUTCTRL (_U_(0x1) << ADC_DSEQCTRL_INPUTCTRL_Pos) +#define ADC_DSEQCTRL_CTRLB_Pos 1 /**< \brief (ADC_DSEQCTRL) Control B */ +#define ADC_DSEQCTRL_CTRLB (_U_(0x1) << ADC_DSEQCTRL_CTRLB_Pos) +#define ADC_DSEQCTRL_REFCTRL_Pos 2 /**< \brief (ADC_DSEQCTRL) Reference Control */ +#define ADC_DSEQCTRL_REFCTRL (_U_(0x1) << ADC_DSEQCTRL_REFCTRL_Pos) +#define ADC_DSEQCTRL_AVGCTRL_Pos 3 /**< \brief (ADC_DSEQCTRL) Average Control */ +#define ADC_DSEQCTRL_AVGCTRL (_U_(0x1) << ADC_DSEQCTRL_AVGCTRL_Pos) +#define ADC_DSEQCTRL_SAMPCTRL_Pos 4 /**< \brief (ADC_DSEQCTRL) Sampling Time Control */ +#define ADC_DSEQCTRL_SAMPCTRL (_U_(0x1) << ADC_DSEQCTRL_SAMPCTRL_Pos) +#define ADC_DSEQCTRL_WINLT_Pos 5 /**< \brief (ADC_DSEQCTRL) Window Monitor Lower Threshold */ +#define ADC_DSEQCTRL_WINLT (_U_(0x1) << ADC_DSEQCTRL_WINLT_Pos) +#define ADC_DSEQCTRL_WINUT_Pos 6 /**< \brief (ADC_DSEQCTRL) Window Monitor Upper Threshold */ +#define ADC_DSEQCTRL_WINUT (_U_(0x1) << ADC_DSEQCTRL_WINUT_Pos) +#define ADC_DSEQCTRL_GAINCORR_Pos 7 /**< \brief (ADC_DSEQCTRL) Gain Correction */ +#define ADC_DSEQCTRL_GAINCORR (_U_(0x1) << ADC_DSEQCTRL_GAINCORR_Pos) +#define ADC_DSEQCTRL_OFFSETCORR_Pos 8 /**< \brief (ADC_DSEQCTRL) Offset Correction */ +#define ADC_DSEQCTRL_OFFSETCORR (_U_(0x1) << ADC_DSEQCTRL_OFFSETCORR_Pos) +#define ADC_DSEQCTRL_AUTOSTART_Pos 31 /**< \brief (ADC_DSEQCTRL) ADC Auto-Start Conversion */ +#define ADC_DSEQCTRL_AUTOSTART (_U_(0x1) << ADC_DSEQCTRL_AUTOSTART_Pos) +#define ADC_DSEQCTRL_MASK _U_(0x800001FF) /**< \brief (ADC_DSEQCTRL) MASK Register */ + +/* -------- ADC_DSEQSTAT : (ADC Offset: 0x3C) (R/ 32) DMA Sequencial Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t INPUTCTRL:1; /*!< bit: 0 Input Control */ + uint32_t CTRLB:1; /*!< bit: 1 Control B */ + uint32_t REFCTRL:1; /*!< bit: 2 Reference Control */ + uint32_t AVGCTRL:1; /*!< bit: 3 Average Control */ + uint32_t SAMPCTRL:1; /*!< bit: 4 Sampling Time Control */ + uint32_t WINLT:1; /*!< bit: 5 Window Monitor Lower Threshold */ + uint32_t WINUT:1; /*!< bit: 6 Window Monitor Upper Threshold */ + uint32_t GAINCORR:1; /*!< bit: 7 Gain Correction */ + uint32_t OFFSETCORR:1; /*!< bit: 8 Offset Correction */ + uint32_t :22; /*!< bit: 9..30 Reserved */ + uint32_t BUSY:1; /*!< bit: 31 DMA Sequencing Busy */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} ADC_DSEQSTAT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_DSEQSTAT_OFFSET 0x3C /**< \brief (ADC_DSEQSTAT offset) DMA Sequencial Status */ +#define ADC_DSEQSTAT_RESETVALUE _U_(0x00000000) /**< \brief (ADC_DSEQSTAT reset_value) DMA Sequencial Status */ + +#define ADC_DSEQSTAT_INPUTCTRL_Pos 0 /**< \brief (ADC_DSEQSTAT) Input Control */ +#define ADC_DSEQSTAT_INPUTCTRL (_U_(0x1) << ADC_DSEQSTAT_INPUTCTRL_Pos) +#define ADC_DSEQSTAT_CTRLB_Pos 1 /**< \brief (ADC_DSEQSTAT) Control B */ +#define ADC_DSEQSTAT_CTRLB (_U_(0x1) << ADC_DSEQSTAT_CTRLB_Pos) +#define ADC_DSEQSTAT_REFCTRL_Pos 2 /**< \brief (ADC_DSEQSTAT) Reference Control */ +#define ADC_DSEQSTAT_REFCTRL (_U_(0x1) << ADC_DSEQSTAT_REFCTRL_Pos) +#define ADC_DSEQSTAT_AVGCTRL_Pos 3 /**< \brief (ADC_DSEQSTAT) Average Control */ +#define ADC_DSEQSTAT_AVGCTRL (_U_(0x1) << ADC_DSEQSTAT_AVGCTRL_Pos) +#define ADC_DSEQSTAT_SAMPCTRL_Pos 4 /**< \brief (ADC_DSEQSTAT) Sampling Time Control */ +#define ADC_DSEQSTAT_SAMPCTRL (_U_(0x1) << ADC_DSEQSTAT_SAMPCTRL_Pos) +#define ADC_DSEQSTAT_WINLT_Pos 5 /**< \brief (ADC_DSEQSTAT) Window Monitor Lower Threshold */ +#define ADC_DSEQSTAT_WINLT (_U_(0x1) << ADC_DSEQSTAT_WINLT_Pos) +#define ADC_DSEQSTAT_WINUT_Pos 6 /**< \brief (ADC_DSEQSTAT) Window Monitor Upper Threshold */ +#define ADC_DSEQSTAT_WINUT (_U_(0x1) << ADC_DSEQSTAT_WINUT_Pos) +#define ADC_DSEQSTAT_GAINCORR_Pos 7 /**< \brief (ADC_DSEQSTAT) Gain Correction */ +#define ADC_DSEQSTAT_GAINCORR (_U_(0x1) << ADC_DSEQSTAT_GAINCORR_Pos) +#define ADC_DSEQSTAT_OFFSETCORR_Pos 8 /**< \brief (ADC_DSEQSTAT) Offset Correction */ +#define ADC_DSEQSTAT_OFFSETCORR (_U_(0x1) << ADC_DSEQSTAT_OFFSETCORR_Pos) +#define ADC_DSEQSTAT_BUSY_Pos 31 /**< \brief (ADC_DSEQSTAT) DMA Sequencing Busy */ +#define ADC_DSEQSTAT_BUSY (_U_(0x1) << ADC_DSEQSTAT_BUSY_Pos) +#define ADC_DSEQSTAT_MASK _U_(0x800001FF) /**< \brief (ADC_DSEQSTAT) MASK Register */ + +/* -------- ADC_RESULT : (ADC Offset: 0x40) (R/ 16) Result Conversion Value -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_RESULT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_RESULT_OFFSET 0x40 /**< \brief (ADC_RESULT offset) Result Conversion Value */ +#define ADC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESULT reset_value) Result Conversion Value */ + +#define ADC_RESULT_RESULT_Pos 0 /**< \brief (ADC_RESULT) Result Conversion Value */ +#define ADC_RESULT_RESULT_Msk (_U_(0xFFFF) << ADC_RESULT_RESULT_Pos) +#define ADC_RESULT_RESULT(value) (ADC_RESULT_RESULT_Msk & ((value) << ADC_RESULT_RESULT_Pos)) +#define ADC_RESULT_MASK _U_(0xFFFF) /**< \brief (ADC_RESULT) MASK Register */ + +/* -------- ADC_RESS : (ADC Offset: 0x44) (R/ 16) Last Sample Result -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t RESS:16; /*!< bit: 0..15 Last ADC conversion result */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_RESS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_RESS_OFFSET 0x44 /**< \brief (ADC_RESS offset) Last Sample Result */ +#define ADC_RESS_RESETVALUE _U_(0x0000) /**< \brief (ADC_RESS reset_value) Last Sample Result */ + +#define ADC_RESS_RESS_Pos 0 /**< \brief (ADC_RESS) Last ADC conversion result */ +#define ADC_RESS_RESS_Msk (_U_(0xFFFF) << ADC_RESS_RESS_Pos) +#define ADC_RESS_RESS(value) (ADC_RESS_RESS_Msk & ((value) << ADC_RESS_RESS_Pos)) +#define ADC_RESS_MASK _U_(0xFFFF) /**< \brief (ADC_RESS) MASK Register */ + +/* -------- ADC_CALIB : (ADC Offset: 0x48) (R/W 16) Calibration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t BIASCOMP:3; /*!< bit: 0.. 2 Bias Comparator Scaling */ + uint16_t :1; /*!< bit: 3 Reserved */ + uint16_t BIASR2R:3; /*!< bit: 4.. 6 Bias R2R Ampli scaling */ + uint16_t :1; /*!< bit: 7 Reserved */ + uint16_t BIASREFBUF:3; /*!< bit: 8..10 Bias Reference Buffer Scaling */ + uint16_t :5; /*!< bit: 11..15 Reserved */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} ADC_CALIB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define ADC_CALIB_OFFSET 0x48 /**< \brief (ADC_CALIB offset) Calibration */ +#define ADC_CALIB_RESETVALUE _U_(0x0000) /**< \brief (ADC_CALIB reset_value) Calibration */ + +#define ADC_CALIB_BIASCOMP_Pos 0 /**< \brief (ADC_CALIB) Bias Comparator Scaling */ +#define ADC_CALIB_BIASCOMP_Msk (_U_(0x7) << ADC_CALIB_BIASCOMP_Pos) +#define ADC_CALIB_BIASCOMP(value) (ADC_CALIB_BIASCOMP_Msk & ((value) << ADC_CALIB_BIASCOMP_Pos)) +#define ADC_CALIB_BIASR2R_Pos 4 /**< \brief (ADC_CALIB) Bias R2R Ampli scaling */ +#define ADC_CALIB_BIASR2R_Msk (_U_(0x7) << ADC_CALIB_BIASR2R_Pos) +#define ADC_CALIB_BIASR2R(value) (ADC_CALIB_BIASR2R_Msk & ((value) << ADC_CALIB_BIASR2R_Pos)) +#define ADC_CALIB_BIASREFBUF_Pos 8 /**< \brief (ADC_CALIB) Bias Reference Buffer Scaling */ +#define ADC_CALIB_BIASREFBUF_Msk (_U_(0x7) << ADC_CALIB_BIASREFBUF_Pos) +#define ADC_CALIB_BIASREFBUF(value) (ADC_CALIB_BIASREFBUF_Msk & ((value) << ADC_CALIB_BIASREFBUF_Pos)) +#define ADC_CALIB_MASK _U_(0x0777) /**< \brief (ADC_CALIB) MASK Register */ + +/** \brief ADC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ + __IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */ + __IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x03 (R/W 8) Debug Control */ + __IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x04 (R/W 16) Input Control */ + __IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x06 (R/W 16) Control B */ + __IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x08 (R/W 8) Reference Control */ + RoReg8 Reserved1[0x1]; + __IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x0A (R/W 8) Average Control */ + __IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x0B (R/W 8) Sample Time Control */ + __IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x0C (R/W 16) Window Monitor Lower Threshold */ + __IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x0E (R/W 16) Window Monitor Upper Threshold */ + __IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x10 (R/W 16) Gain Correction */ + __IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x12 (R/W 16) Offset Correction */ + __IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x14 (R/W 8) Software Trigger */ + RoReg8 Reserved2[0x17]; + __IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x2C (R/W 8) Interrupt Enable Clear */ + __IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x2D (R/W 8) Interrupt Enable Set */ + __IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x2E (R/W 8) Interrupt Flag Status and Clear */ + __I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x2F (R/ 8) Status */ + __I ADC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x30 (R/ 32) Synchronization Busy */ + __O ADC_DSEQDATA_Type DSEQDATA; /**< \brief Offset: 0x34 ( /W 32) DMA Sequencial Data */ + __IO ADC_DSEQCTRL_Type DSEQCTRL; /**< \brief Offset: 0x38 (R/W 32) DMA Sequential Control */ + __I ADC_DSEQSTAT_Type DSEQSTAT; /**< \brief Offset: 0x3C (R/ 32) DMA Sequencial Status */ + __I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x40 (R/ 16) Result Conversion Value */ + RoReg8 Reserved3[0x2]; + __I ADC_RESS_Type RESS; /**< \brief Offset: 0x44 (R/ 16) Last Sample Result */ + RoReg8 Reserved4[0x2]; + __IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x48 (R/W 16) Calibration */ +} Adc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAME54_ADC_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/include/component/aes.h b/software/firmware/oracle_same54n19a/include/component/aes.h new file mode 100644 index 00000000..2831d0db --- /dev/null +++ b/software/firmware/oracle_same54n19a/include/component/aes.h @@ -0,0 +1,375 @@ +/** + * \file + * + * \brief Component description for AES + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54_AES_COMPONENT_ +#define _SAME54_AES_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR AES */ +/* ========================================================================== */ +/** \addtogroup SAME54_AES Advanced Encryption Standard */ +/*@{*/ + +#define AES_U2238 +#define REV_AES 0x220 + +/* -------- AES_CTRLA : (AES Offset: 0x00) (R/W 32) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Enable */ + uint32_t AESMODE:3; /*!< bit: 2.. 4 AES Modes of operation */ + uint32_t CFBS:3; /*!< bit: 5.. 7 Cipher Feedback Block Size */ + uint32_t KEYSIZE:2; /*!< bit: 8.. 9 Encryption Key Size */ + uint32_t CIPHER:1; /*!< bit: 10 Cipher Mode */ + uint32_t STARTMODE:1; /*!< bit: 11 Start Mode Select */ + uint32_t LOD:1; /*!< bit: 12 Last Output Data Mode */ + uint32_t KEYGEN:1; /*!< bit: 13 Last Key Generation */ + uint32_t XORKEY:1; /*!< bit: 14 XOR Key Operation */ + uint32_t :1; /*!< bit: 15 Reserved */ + uint32_t CTYPE:4; /*!< bit: 16..19 Counter Measure Type */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} AES_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_CTRLA_OFFSET 0x00 /**< \brief (AES_CTRLA offset) Control A */ +#define AES_CTRLA_RESETVALUE _U_(0x00000000) /**< \brief (AES_CTRLA reset_value) Control A */ + +#define AES_CTRLA_SWRST_Pos 0 /**< \brief (AES_CTRLA) Software Reset */ +#define AES_CTRLA_SWRST (_U_(0x1) << AES_CTRLA_SWRST_Pos) +#define AES_CTRLA_ENABLE_Pos 1 /**< \brief (AES_CTRLA) Enable */ +#define AES_CTRLA_ENABLE (_U_(0x1) << AES_CTRLA_ENABLE_Pos) +#define AES_CTRLA_AESMODE_Pos 2 /**< \brief (AES_CTRLA) AES Modes of operation */ +#define AES_CTRLA_AESMODE_Msk (_U_(0x7) << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE(value) (AES_CTRLA_AESMODE_Msk & ((value) << AES_CTRLA_AESMODE_Pos)) +#define AES_CTRLA_AESMODE_ECB_Val _U_(0x0) /**< \brief (AES_CTRLA) Electronic code book mode */ +#define AES_CTRLA_AESMODE_CBC_Val _U_(0x1) /**< \brief (AES_CTRLA) Cipher block chaining mode */ +#define AES_CTRLA_AESMODE_OFB_Val _U_(0x2) /**< \brief (AES_CTRLA) Output feedback mode */ +#define AES_CTRLA_AESMODE_CFB_Val _U_(0x3) /**< \brief (AES_CTRLA) Cipher feedback mode */ +#define AES_CTRLA_AESMODE_COUNTER_Val _U_(0x4) /**< \brief (AES_CTRLA) Counter mode */ +#define AES_CTRLA_AESMODE_CCM_Val _U_(0x5) /**< \brief (AES_CTRLA) CCM mode */ +#define AES_CTRLA_AESMODE_GCM_Val _U_(0x6) /**< \brief (AES_CTRLA) Galois counter mode */ +#define AES_CTRLA_AESMODE_ECB (AES_CTRLA_AESMODE_ECB_Val << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE_CBC (AES_CTRLA_AESMODE_CBC_Val << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE_OFB (AES_CTRLA_AESMODE_OFB_Val << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE_CFB (AES_CTRLA_AESMODE_CFB_Val << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE_COUNTER (AES_CTRLA_AESMODE_COUNTER_Val << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE_CCM (AES_CTRLA_AESMODE_CCM_Val << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_AESMODE_GCM (AES_CTRLA_AESMODE_GCM_Val << AES_CTRLA_AESMODE_Pos) +#define AES_CTRLA_CFBS_Pos 5 /**< \brief (AES_CTRLA) Cipher Feedback Block Size */ +#define AES_CTRLA_CFBS_Msk (_U_(0x7) << AES_CTRLA_CFBS_Pos) +#define AES_CTRLA_CFBS(value) (AES_CTRLA_CFBS_Msk & ((value) << AES_CTRLA_CFBS_Pos)) +#define AES_CTRLA_CFBS_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_64BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_32BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_16BIT_Val _U_(0x3) /**< \brief (AES_CTRLA) 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_8BIT_Val _U_(0x4) /**< \brief (AES_CTRLA) 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode */ +#define AES_CTRLA_CFBS_128BIT (AES_CTRLA_CFBS_128BIT_Val << AES_CTRLA_CFBS_Pos) +#define AES_CTRLA_CFBS_64BIT (AES_CTRLA_CFBS_64BIT_Val << AES_CTRLA_CFBS_Pos) +#define AES_CTRLA_CFBS_32BIT (AES_CTRLA_CFBS_32BIT_Val << AES_CTRLA_CFBS_Pos) +#define AES_CTRLA_CFBS_16BIT (AES_CTRLA_CFBS_16BIT_Val << AES_CTRLA_CFBS_Pos) +#define AES_CTRLA_CFBS_8BIT (AES_CTRLA_CFBS_8BIT_Val << AES_CTRLA_CFBS_Pos) +#define AES_CTRLA_KEYSIZE_Pos 8 /**< \brief (AES_CTRLA) Encryption Key Size */ +#define AES_CTRLA_KEYSIZE_Msk (_U_(0x3) << AES_CTRLA_KEYSIZE_Pos) +#define AES_CTRLA_KEYSIZE(value) (AES_CTRLA_KEYSIZE_Msk & ((value) << AES_CTRLA_KEYSIZE_Pos)) +#define AES_CTRLA_KEYSIZE_128BIT_Val _U_(0x0) /**< \brief (AES_CTRLA) 128-bit Key for Encryption / Decryption */ +#define AES_CTRLA_KEYSIZE_192BIT_Val _U_(0x1) /**< \brief (AES_CTRLA) 192-bit Key for Encryption / Decryption */ +#define AES_CTRLA_KEYSIZE_256BIT_Val _U_(0x2) /**< \brief (AES_CTRLA) 256-bit Key for Encryption / Decryption */ +#define AES_CTRLA_KEYSIZE_128BIT (AES_CTRLA_KEYSIZE_128BIT_Val << AES_CTRLA_KEYSIZE_Pos) +#define AES_CTRLA_KEYSIZE_192BIT (AES_CTRLA_KEYSIZE_192BIT_Val << AES_CTRLA_KEYSIZE_Pos) +#define AES_CTRLA_KEYSIZE_256BIT (AES_CTRLA_KEYSIZE_256BIT_Val << AES_CTRLA_KEYSIZE_Pos) +#define AES_CTRLA_CIPHER_Pos 10 /**< \brief (AES_CTRLA) Cipher Mode */ +#define AES_CTRLA_CIPHER (_U_(0x1) << AES_CTRLA_CIPHER_Pos) +#define AES_CTRLA_CIPHER_DEC_Val _U_(0x0) /**< \brief (AES_CTRLA) Decryption */ +#define AES_CTRLA_CIPHER_ENC_Val _U_(0x1) /**< \brief (AES_CTRLA) Encryption */ +#define AES_CTRLA_CIPHER_DEC (AES_CTRLA_CIPHER_DEC_Val << AES_CTRLA_CIPHER_Pos) +#define AES_CTRLA_CIPHER_ENC (AES_CTRLA_CIPHER_ENC_Val << AES_CTRLA_CIPHER_Pos) +#define AES_CTRLA_STARTMODE_Pos 11 /**< \brief (AES_CTRLA) Start Mode Select */ +#define AES_CTRLA_STARTMODE (_U_(0x1) << AES_CTRLA_STARTMODE_Pos) +#define AES_CTRLA_STARTMODE_MANUAL_Val _U_(0x0) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Manual mode */ +#define AES_CTRLA_STARTMODE_AUTO_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Encryption / Decryption in Auto mode */ +#define AES_CTRLA_STARTMODE_MANUAL (AES_CTRLA_STARTMODE_MANUAL_Val << AES_CTRLA_STARTMODE_Pos) +#define AES_CTRLA_STARTMODE_AUTO (AES_CTRLA_STARTMODE_AUTO_Val << AES_CTRLA_STARTMODE_Pos) +#define AES_CTRLA_LOD_Pos 12 /**< \brief (AES_CTRLA) Last Output Data Mode */ +#define AES_CTRLA_LOD (_U_(0x1) << AES_CTRLA_LOD_Pos) +#define AES_CTRLA_LOD_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */ +#define AES_CTRLA_LOD_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start encryption in Last Output Data mode */ +#define AES_CTRLA_LOD_NONE (AES_CTRLA_LOD_NONE_Val << AES_CTRLA_LOD_Pos) +#define AES_CTRLA_LOD_LAST (AES_CTRLA_LOD_LAST_Val << AES_CTRLA_LOD_Pos) +#define AES_CTRLA_KEYGEN_Pos 13 /**< \brief (AES_CTRLA) Last Key Generation */ +#define AES_CTRLA_KEYGEN (_U_(0x1) << AES_CTRLA_KEYGEN_Pos) +#define AES_CTRLA_KEYGEN_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */ +#define AES_CTRLA_KEYGEN_LAST_Val _U_(0x1) /**< \brief (AES_CTRLA) Start Computation of the last NK words of the expanded key */ +#define AES_CTRLA_KEYGEN_NONE (AES_CTRLA_KEYGEN_NONE_Val << AES_CTRLA_KEYGEN_Pos) +#define AES_CTRLA_KEYGEN_LAST (AES_CTRLA_KEYGEN_LAST_Val << AES_CTRLA_KEYGEN_Pos) +#define AES_CTRLA_XORKEY_Pos 14 /**< \brief (AES_CTRLA) XOR Key Operation */ +#define AES_CTRLA_XORKEY (_U_(0x1) << AES_CTRLA_XORKEY_Pos) +#define AES_CTRLA_XORKEY_NONE_Val _U_(0x0) /**< \brief (AES_CTRLA) No effect */ +#define AES_CTRLA_XORKEY_XOR_Val _U_(0x1) /**< \brief (AES_CTRLA) The user keyword gets XORed with the previous keyword register content. */ +#define AES_CTRLA_XORKEY_NONE (AES_CTRLA_XORKEY_NONE_Val << AES_CTRLA_XORKEY_Pos) +#define AES_CTRLA_XORKEY_XOR (AES_CTRLA_XORKEY_XOR_Val << AES_CTRLA_XORKEY_Pos) +#define AES_CTRLA_CTYPE_Pos 16 /**< \brief (AES_CTRLA) Counter Measure Type */ +#define AES_CTRLA_CTYPE_Msk (_U_(0xF) << AES_CTRLA_CTYPE_Pos) +#define AES_CTRLA_CTYPE(value) (AES_CTRLA_CTYPE_Msk & ((value) << AES_CTRLA_CTYPE_Pos)) +#define AES_CTRLA_MASK _U_(0x000F7FFF) /**< \brief (AES_CTRLA) MASK Register */ + +/* -------- AES_CTRLB : (AES Offset: 0x04) (R/W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t START:1; /*!< bit: 0 Start Encryption/Decryption */ + uint8_t NEWMSG:1; /*!< bit: 1 New message */ + uint8_t EOM:1; /*!< bit: 2 End of message */ + uint8_t GFMUL:1; /*!< bit: 3 GF Multiplication */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_CTRLB_OFFSET 0x04 /**< \brief (AES_CTRLB offset) Control B */ +#define AES_CTRLB_RESETVALUE _U_(0x00) /**< \brief (AES_CTRLB reset_value) Control B */ + +#define AES_CTRLB_START_Pos 0 /**< \brief (AES_CTRLB) Start Encryption/Decryption */ +#define AES_CTRLB_START (_U_(0x1) << AES_CTRLB_START_Pos) +#define AES_CTRLB_NEWMSG_Pos 1 /**< \brief (AES_CTRLB) New message */ +#define AES_CTRLB_NEWMSG (_U_(0x1) << AES_CTRLB_NEWMSG_Pos) +#define AES_CTRLB_EOM_Pos 2 /**< \brief (AES_CTRLB) End of message */ +#define AES_CTRLB_EOM (_U_(0x1) << AES_CTRLB_EOM_Pos) +#define AES_CTRLB_GFMUL_Pos 3 /**< \brief (AES_CTRLB) GF Multiplication */ +#define AES_CTRLB_GFMUL (_U_(0x1) << AES_CTRLB_GFMUL_Pos) +#define AES_CTRLB_MASK _U_(0x0F) /**< \brief (AES_CTRLB) MASK Register */ + +/* -------- AES_INTENCLR : (AES Offset: 0x05) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */ + uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTENCLR_OFFSET 0x05 /**< \brief (AES_INTENCLR offset) Interrupt Enable Clear */ +#define AES_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (AES_INTENCLR reset_value) Interrupt Enable Clear */ + +#define AES_INTENCLR_ENCCMP_Pos 0 /**< \brief (AES_INTENCLR) Encryption Complete Interrupt Enable */ +#define AES_INTENCLR_ENCCMP (_U_(0x1) << AES_INTENCLR_ENCCMP_Pos) +#define AES_INTENCLR_GFMCMP_Pos 1 /**< \brief (AES_INTENCLR) GF Multiplication Complete Interrupt Enable */ +#define AES_INTENCLR_GFMCMP (_U_(0x1) << AES_INTENCLR_GFMCMP_Pos) +#define AES_INTENCLR_MASK _U_(0x03) /**< \brief (AES_INTENCLR) MASK Register */ + +/* -------- AES_INTENSET : (AES Offset: 0x06) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete Interrupt Enable */ + uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete Interrupt Enable */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTENSET_OFFSET 0x06 /**< \brief (AES_INTENSET offset) Interrupt Enable Set */ +#define AES_INTENSET_RESETVALUE _U_(0x00) /**< \brief (AES_INTENSET reset_value) Interrupt Enable Set */ + +#define AES_INTENSET_ENCCMP_Pos 0 /**< \brief (AES_INTENSET) Encryption Complete Interrupt Enable */ +#define AES_INTENSET_ENCCMP (_U_(0x1) << AES_INTENSET_ENCCMP_Pos) +#define AES_INTENSET_GFMCMP_Pos 1 /**< \brief (AES_INTENSET) GF Multiplication Complete Interrupt Enable */ +#define AES_INTENSET_GFMCMP (_U_(0x1) << AES_INTENSET_GFMCMP_Pos) +#define AES_INTENSET_MASK _U_(0x03) /**< \brief (AES_INTENSET) MASK Register */ + +/* -------- AES_INTFLAG : (AES Offset: 0x07) (R/W 8) Interrupt Flag Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t ENCCMP:1; /*!< bit: 0 Encryption Complete */ + __I uint8_t GFMCMP:1; /*!< bit: 1 GF Multiplication Complete */ + __I uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTFLAG_OFFSET 0x07 /**< \brief (AES_INTFLAG offset) Interrupt Flag Status */ +#define AES_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (AES_INTFLAG reset_value) Interrupt Flag Status */ + +#define AES_INTFLAG_ENCCMP_Pos 0 /**< \brief (AES_INTFLAG) Encryption Complete */ +#define AES_INTFLAG_ENCCMP (_U_(0x1) << AES_INTFLAG_ENCCMP_Pos) +#define AES_INTFLAG_GFMCMP_Pos 1 /**< \brief (AES_INTFLAG) GF Multiplication Complete */ +#define AES_INTFLAG_GFMCMP (_U_(0x1) << AES_INTFLAG_GFMCMP_Pos) +#define AES_INTFLAG_MASK _U_(0x03) /**< \brief (AES_INTFLAG) MASK Register */ + +/* -------- AES_DATABUFPTR : (AES Offset: 0x08) (R/W 8) Data buffer pointer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t INDATAPTR:2; /*!< bit: 0.. 1 Input Data Pointer */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_DATABUFPTR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_DATABUFPTR_OFFSET 0x08 /**< \brief (AES_DATABUFPTR offset) Data buffer pointer */ +#define AES_DATABUFPTR_RESETVALUE _U_(0x00) /**< \brief (AES_DATABUFPTR reset_value) Data buffer pointer */ + +#define AES_DATABUFPTR_INDATAPTR_Pos 0 /**< \brief (AES_DATABUFPTR) Input Data Pointer */ +#define AES_DATABUFPTR_INDATAPTR_Msk (_U_(0x3) << AES_DATABUFPTR_INDATAPTR_Pos) +#define AES_DATABUFPTR_INDATAPTR(value) (AES_DATABUFPTR_INDATAPTR_Msk & ((value) << AES_DATABUFPTR_INDATAPTR_Pos)) +#define AES_DATABUFPTR_MASK _U_(0x03) /**< \brief (AES_DATABUFPTR) MASK Register */ + +/* -------- AES_DBGCTRL : (AES Offset: 0x09) (R/W 8) Debug control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} AES_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_DBGCTRL_OFFSET 0x09 /**< \brief (AES_DBGCTRL offset) Debug control */ +#define AES_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (AES_DBGCTRL reset_value) Debug control */ + +#define AES_DBGCTRL_DBGRUN_Pos 0 /**< \brief (AES_DBGCTRL) Debug Run */ +#define AES_DBGCTRL_DBGRUN (_U_(0x1) << AES_DBGCTRL_DBGRUN_Pos) +#define AES_DBGCTRL_MASK _U_(0x01) /**< \brief (AES_DBGCTRL) MASK Register */ + +/* -------- AES_KEYWORD : (AES Offset: 0x0C) ( /W 32) Keyword n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_KEYWORD_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_KEYWORD_OFFSET 0x0C /**< \brief (AES_KEYWORD offset) Keyword n */ +#define AES_KEYWORD_RESETVALUE _U_(0x00000000) /**< \brief (AES_KEYWORD reset_value) Keyword n */ +#define AES_KEYWORD_MASK _U_(0xFFFFFFFF) /**< \brief (AES_KEYWORD) MASK Register */ + +/* -------- AES_INDATA : (AES Offset: 0x38) (R/W 32) Indata -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_INDATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INDATA_OFFSET 0x38 /**< \brief (AES_INDATA offset) Indata */ +#define AES_INDATA_RESETVALUE _U_(0x00000000) /**< \brief (AES_INDATA reset_value) Indata */ +#define AES_INDATA_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INDATA) MASK Register */ + +/* -------- AES_INTVECTV : (AES Offset: 0x3C) ( /W 32) Initialisation Vector n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_INTVECTV_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_INTVECTV_OFFSET 0x3C /**< \brief (AES_INTVECTV offset) Initialisation Vector n */ +#define AES_INTVECTV_RESETVALUE _U_(0x00000000) /**< \brief (AES_INTVECTV reset_value) Initialisation Vector n */ +#define AES_INTVECTV_MASK _U_(0xFFFFFFFF) /**< \brief (AES_INTVECTV) MASK Register */ + +/* -------- AES_HASHKEY : (AES Offset: 0x5C) (R/W 32) Hash key n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_HASHKEY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_HASHKEY_OFFSET 0x5C /**< \brief (AES_HASHKEY offset) Hash key n */ +#define AES_HASHKEY_RESETVALUE _U_(0x00000000) /**< \brief (AES_HASHKEY reset_value) Hash key n */ +#define AES_HASHKEY_MASK _U_(0xFFFFFFFF) /**< \brief (AES_HASHKEY) MASK Register */ + +/* -------- AES_GHASH : (AES Offset: 0x6C) (R/W 32) Galois Hash n -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_GHASH_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_GHASH_OFFSET 0x6C /**< \brief (AES_GHASH offset) Galois Hash n */ +#define AES_GHASH_RESETVALUE _U_(0x00000000) /**< \brief (AES_GHASH reset_value) Galois Hash n */ +#define AES_GHASH_MASK _U_(0xFFFFFFFF) /**< \brief (AES_GHASH) MASK Register */ + +/* -------- AES_CIPLEN : (AES Offset: 0x80) (R/W 32) Cipher Length -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_CIPLEN_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_CIPLEN_OFFSET 0x80 /**< \brief (AES_CIPLEN offset) Cipher Length */ +#define AES_CIPLEN_RESETVALUE _U_(0x00000000) /**< \brief (AES_CIPLEN reset_value) Cipher Length */ +#define AES_CIPLEN_MASK _U_(0xFFFFFFFF) /**< \brief (AES_CIPLEN) MASK Register */ + +/* -------- AES_RANDSEED : (AES Offset: 0x84) (R/W 32) Random Seed -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + uint32_t reg; /*!< Type used for register access */ +} AES_RANDSEED_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define AES_RANDSEED_OFFSET 0x84 /**< \brief (AES_RANDSEED offset) Random Seed */ +#define AES_RANDSEED_RESETVALUE _U_(0x00000000) /**< \brief (AES_RANDSEED reset_value) Random Seed */ +#define AES_RANDSEED_MASK _U_(0xFFFFFFFF) /**< \brief (AES_RANDSEED) MASK Register */ + +/** \brief AES hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO AES_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ + __IO AES_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 8) Control B */ + __IO AES_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Clear */ + __IO AES_INTENSET_Type INTENSET; /**< \brief Offset: 0x06 (R/W 8) Interrupt Enable Set */ + __IO AES_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x07 (R/W 8) Interrupt Flag Status */ + __IO AES_DATABUFPTR_Type DATABUFPTR; /**< \brief Offset: 0x08 (R/W 8) Data buffer pointer */ + __IO AES_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x09 (R/W 8) Debug control */ + RoReg8 Reserved1[0x2]; + __O AES_KEYWORD_Type KEYWORD[8]; /**< \brief Offset: 0x0C ( /W 32) Keyword n */ + RoReg8 Reserved2[0xC]; + __IO AES_INDATA_Type INDATA; /**< \brief Offset: 0x38 (R/W 32) Indata */ + __O AES_INTVECTV_Type INTVECTV[4]; /**< \brief Offset: 0x3C ( /W 32) Initialisation Vector n */ + RoReg8 Reserved3[0x10]; + __IO AES_HASHKEY_Type HASHKEY[4]; /**< \brief Offset: 0x5C (R/W 32) Hash key n */ + __IO AES_GHASH_Type GHASH[4]; /**< \brief Offset: 0x6C (R/W 32) Galois Hash n */ + RoReg8 Reserved4[0x4]; + __IO AES_CIPLEN_Type CIPLEN; /**< \brief Offset: 0x80 (R/W 32) Cipher Length */ + __IO AES_RANDSEED_Type RANDSEED; /**< \brief Offset: 0x84 (R/W 32) Random Seed */ +} Aes; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAME54_AES_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/include/component/can.h b/software/firmware/oracle_same54n19a/include/component/can.h new file mode 100644 index 00000000..48b3cab5 --- /dev/null +++ b/software/firmware/oracle_same54n19a/include/component/can.h @@ -0,0 +1,3187 @@ +/** + * \file + * + * \brief Component description for CAN + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54_CAN_COMPONENT_ +#define _SAME54_CAN_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR CAN */ +/* ========================================================================== */ +/** \addtogroup SAME54_CAN Control Area Network */ +/*@{*/ + +#define CAN_U2003 +#define REV_CAN 0x321 + +/* -------- CAN_CREL : (CAN Offset: 0x00) (R/ 32) Core Release -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :20; /*!< bit: 0..19 Reserved */ + uint32_t SUBSTEP:4; /*!< bit: 20..23 Sub-step of Core Release */ + uint32_t STEP:4; /*!< bit: 24..27 Step of Core Release */ + uint32_t REL:4; /*!< bit: 28..31 Core Release */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_CREL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_CREL_OFFSET 0x00 /**< \brief (CAN_CREL offset) Core Release */ +#define CAN_CREL_RESETVALUE _U_(0x32100000) /**< \brief (CAN_CREL reset_value) Core Release */ + +#define CAN_CREL_SUBSTEP_Pos 20 /**< \brief (CAN_CREL) Sub-step of Core Release */ +#define CAN_CREL_SUBSTEP_Msk (_U_(0xF) << CAN_CREL_SUBSTEP_Pos) +#define CAN_CREL_SUBSTEP(value) (CAN_CREL_SUBSTEP_Msk & ((value) << CAN_CREL_SUBSTEP_Pos)) +#define CAN_CREL_STEP_Pos 24 /**< \brief (CAN_CREL) Step of Core Release */ +#define CAN_CREL_STEP_Msk (_U_(0xF) << CAN_CREL_STEP_Pos) +#define CAN_CREL_STEP(value) (CAN_CREL_STEP_Msk & ((value) << CAN_CREL_STEP_Pos)) +#define CAN_CREL_REL_Pos 28 /**< \brief (CAN_CREL) Core Release */ +#define CAN_CREL_REL_Msk (_U_(0xF) << CAN_CREL_REL_Pos) +#define CAN_CREL_REL(value) (CAN_CREL_REL_Msk & ((value) << CAN_CREL_REL_Pos)) +#define CAN_CREL_MASK _U_(0xFFF00000) /**< \brief (CAN_CREL) MASK Register */ + +/* -------- CAN_ENDN : (CAN Offset: 0x04) (R/ 32) Endian -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ETV:32; /*!< bit: 0..31 Endianness Test Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_ENDN_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_ENDN_OFFSET 0x04 /**< \brief (CAN_ENDN offset) Endian */ +#define CAN_ENDN_RESETVALUE _U_(0x87654321) /**< \brief (CAN_ENDN reset_value) Endian */ + +#define CAN_ENDN_ETV_Pos 0 /**< \brief (CAN_ENDN) Endianness Test Value */ +#define CAN_ENDN_ETV_Msk (_U_(0xFFFFFFFF) << CAN_ENDN_ETV_Pos) +#define CAN_ENDN_ETV(value) (CAN_ENDN_ETV_Msk & ((value) << CAN_ENDN_ETV_Pos)) +#define CAN_ENDN_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_ENDN) MASK Register */ + +/* -------- CAN_MRCFG : (CAN Offset: 0x08) (R/W 32) Message RAM Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t QOS:2; /*!< bit: 0.. 1 Quality of Service */ + uint32_t :30; /*!< bit: 2..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_MRCFG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_MRCFG_OFFSET 0x08 /**< \brief (CAN_MRCFG offset) Message RAM Configuration */ +#define CAN_MRCFG_RESETVALUE _U_(0x00000002) /**< \brief (CAN_MRCFG reset_value) Message RAM Configuration */ + +#define CAN_MRCFG_QOS_Pos 0 /**< \brief (CAN_MRCFG) Quality of Service */ +#define CAN_MRCFG_QOS_Msk (_U_(0x3) << CAN_MRCFG_QOS_Pos) +#define CAN_MRCFG_QOS(value) (CAN_MRCFG_QOS_Msk & ((value) << CAN_MRCFG_QOS_Pos)) +#define CAN_MRCFG_QOS_DISABLE_Val _U_(0x0) /**< \brief (CAN_MRCFG) Background (no sensitive operation) */ +#define CAN_MRCFG_QOS_LOW_Val _U_(0x1) /**< \brief (CAN_MRCFG) Sensitive Bandwidth */ +#define CAN_MRCFG_QOS_MEDIUM_Val _U_(0x2) /**< \brief (CAN_MRCFG) Sensitive Latency */ +#define CAN_MRCFG_QOS_HIGH_Val _U_(0x3) /**< \brief (CAN_MRCFG) Critical Latency */ +#define CAN_MRCFG_QOS_DISABLE (CAN_MRCFG_QOS_DISABLE_Val << CAN_MRCFG_QOS_Pos) +#define CAN_MRCFG_QOS_LOW (CAN_MRCFG_QOS_LOW_Val << CAN_MRCFG_QOS_Pos) +#define CAN_MRCFG_QOS_MEDIUM (CAN_MRCFG_QOS_MEDIUM_Val << CAN_MRCFG_QOS_Pos) +#define CAN_MRCFG_QOS_HIGH (CAN_MRCFG_QOS_HIGH_Val << CAN_MRCFG_QOS_Pos) +#define CAN_MRCFG_MASK _U_(0x00000003) /**< \brief (CAN_MRCFG) MASK Register */ + +/* -------- CAN_DBTP : (CAN Offset: 0x0C) (R/W 32) Fast Bit Timing and Prescaler -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DSJW:4; /*!< bit: 0.. 3 Data (Re)Synchronization Jump Width */ + uint32_t DTSEG2:4; /*!< bit: 4.. 7 Data time segment after sample point */ + uint32_t DTSEG1:5; /*!< bit: 8..12 Data time segment before sample point */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t DBRP:5; /*!< bit: 16..20 Data Baud Rate Prescaler */ + uint32_t :2; /*!< bit: 21..22 Reserved */ + uint32_t TDC:1; /*!< bit: 23 Tranceiver Delay Compensation */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_DBTP_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_DBTP_OFFSET 0x0C /**< \brief (CAN_DBTP offset) Fast Bit Timing and Prescaler */ +#define CAN_DBTP_RESETVALUE _U_(0x00000A33) /**< \brief (CAN_DBTP reset_value) Fast Bit Timing and Prescaler */ + +#define CAN_DBTP_DSJW_Pos 0 /**< \brief (CAN_DBTP) Data (Re)Synchronization Jump Width */ +#define CAN_DBTP_DSJW_Msk (_U_(0xF) << CAN_DBTP_DSJW_Pos) +#define CAN_DBTP_DSJW(value) (CAN_DBTP_DSJW_Msk & ((value) << CAN_DBTP_DSJW_Pos)) +#define CAN_DBTP_DTSEG2_Pos 4 /**< \brief (CAN_DBTP) Data time segment after sample point */ +#define CAN_DBTP_DTSEG2_Msk (_U_(0xF) << CAN_DBTP_DTSEG2_Pos) +#define CAN_DBTP_DTSEG2(value) (CAN_DBTP_DTSEG2_Msk & ((value) << CAN_DBTP_DTSEG2_Pos)) +#define CAN_DBTP_DTSEG1_Pos 8 /**< \brief (CAN_DBTP) Data time segment before sample point */ +#define CAN_DBTP_DTSEG1_Msk (_U_(0x1F) << CAN_DBTP_DTSEG1_Pos) +#define CAN_DBTP_DTSEG1(value) (CAN_DBTP_DTSEG1_Msk & ((value) << CAN_DBTP_DTSEG1_Pos)) +#define CAN_DBTP_DBRP_Pos 16 /**< \brief (CAN_DBTP) Data Baud Rate Prescaler */ +#define CAN_DBTP_DBRP_Msk (_U_(0x1F) << CAN_DBTP_DBRP_Pos) +#define CAN_DBTP_DBRP(value) (CAN_DBTP_DBRP_Msk & ((value) << CAN_DBTP_DBRP_Pos)) +#define CAN_DBTP_TDC_Pos 23 /**< \brief (CAN_DBTP) Tranceiver Delay Compensation */ +#define CAN_DBTP_TDC (_U_(0x1) << CAN_DBTP_TDC_Pos) +#define CAN_DBTP_MASK _U_(0x009F1FFF) /**< \brief (CAN_DBTP) MASK Register */ + +/* -------- CAN_TEST : (CAN Offset: 0x10) (R/W 32) Test -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :4; /*!< bit: 0.. 3 Reserved */ + uint32_t LBCK:1; /*!< bit: 4 Loop Back Mode */ + uint32_t TX:2; /*!< bit: 5.. 6 Control of Transmit Pin */ + uint32_t RX:1; /*!< bit: 7 Receive Pin */ + uint32_t :24; /*!< bit: 8..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TEST_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TEST_OFFSET 0x10 /**< \brief (CAN_TEST offset) Test */ +#define CAN_TEST_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TEST reset_value) Test */ + +#define CAN_TEST_LBCK_Pos 4 /**< \brief (CAN_TEST) Loop Back Mode */ +#define CAN_TEST_LBCK (_U_(0x1) << CAN_TEST_LBCK_Pos) +#define CAN_TEST_TX_Pos 5 /**< \brief (CAN_TEST) Control of Transmit Pin */ +#define CAN_TEST_TX_Msk (_U_(0x3) << CAN_TEST_TX_Pos) +#define CAN_TEST_TX(value) (CAN_TEST_TX_Msk & ((value) << CAN_TEST_TX_Pos)) +#define CAN_TEST_TX_CORE_Val _U_(0x0) /**< \brief (CAN_TEST) TX controlled by CAN core */ +#define CAN_TEST_TX_SAMPLE_Val _U_(0x1) /**< \brief (CAN_TEST) TX monitoring sample point */ +#define CAN_TEST_TX_DOMINANT_Val _U_(0x2) /**< \brief (CAN_TEST) Dominant (0) level at pin CAN_TX */ +#define CAN_TEST_TX_RECESSIVE_Val _U_(0x3) /**< \brief (CAN_TEST) Recessive (1) level at pin CAN_TX */ +#define CAN_TEST_TX_CORE (CAN_TEST_TX_CORE_Val << CAN_TEST_TX_Pos) +#define CAN_TEST_TX_SAMPLE (CAN_TEST_TX_SAMPLE_Val << CAN_TEST_TX_Pos) +#define CAN_TEST_TX_DOMINANT (CAN_TEST_TX_DOMINANT_Val << CAN_TEST_TX_Pos) +#define CAN_TEST_TX_RECESSIVE (CAN_TEST_TX_RECESSIVE_Val << CAN_TEST_TX_Pos) +#define CAN_TEST_RX_Pos 7 /**< \brief (CAN_TEST) Receive Pin */ +#define CAN_TEST_RX (_U_(0x1) << CAN_TEST_RX_Pos) +#define CAN_TEST_MASK _U_(0x000000F0) /**< \brief (CAN_TEST) MASK Register */ + +/* -------- CAN_RWD : (CAN Offset: 0x14) (R/W 32) RAM Watchdog -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t WDC:8; /*!< bit: 0.. 7 Watchdog Configuration */ + uint32_t WDV:8; /*!< bit: 8..15 Watchdog Value */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RWD_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RWD_OFFSET 0x14 /**< \brief (CAN_RWD offset) RAM Watchdog */ +#define CAN_RWD_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RWD reset_value) RAM Watchdog */ + +#define CAN_RWD_WDC_Pos 0 /**< \brief (CAN_RWD) Watchdog Configuration */ +#define CAN_RWD_WDC_Msk (_U_(0xFF) << CAN_RWD_WDC_Pos) +#define CAN_RWD_WDC(value) (CAN_RWD_WDC_Msk & ((value) << CAN_RWD_WDC_Pos)) +#define CAN_RWD_WDV_Pos 8 /**< \brief (CAN_RWD) Watchdog Value */ +#define CAN_RWD_WDV_Msk (_U_(0xFF) << CAN_RWD_WDV_Pos) +#define CAN_RWD_WDV(value) (CAN_RWD_WDV_Msk & ((value) << CAN_RWD_WDV_Pos)) +#define CAN_RWD_MASK _U_(0x0000FFFF) /**< \brief (CAN_RWD) MASK Register */ + +/* -------- CAN_CCCR : (CAN Offset: 0x18) (R/W 32) CC Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t INIT:1; /*!< bit: 0 Initialization */ + uint32_t CCE:1; /*!< bit: 1 Configuration Change Enable */ + uint32_t ASM:1; /*!< bit: 2 ASM Restricted Operation Mode */ + uint32_t CSA:1; /*!< bit: 3 Clock Stop Acknowledge */ + uint32_t CSR:1; /*!< bit: 4 Clock Stop Request */ + uint32_t MON:1; /*!< bit: 5 Bus Monitoring Mode */ + uint32_t DAR:1; /*!< bit: 6 Disable Automatic Retransmission */ + uint32_t TEST:1; /*!< bit: 7 Test Mode Enable */ + uint32_t FDOE:1; /*!< bit: 8 FD Operation Enable */ + uint32_t BRSE:1; /*!< bit: 9 Bit Rate Switch Enable */ + uint32_t :2; /*!< bit: 10..11 Reserved */ + uint32_t PXHD:1; /*!< bit: 12 Protocol Exception Handling Disable */ + uint32_t EFBI:1; /*!< bit: 13 Edge Filtering during Bus Integration */ + uint32_t TXP:1; /*!< bit: 14 Transmit Pause */ + uint32_t NISO:1; /*!< bit: 15 Non ISO Operation */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_CCCR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_CCCR_OFFSET 0x18 /**< \brief (CAN_CCCR offset) CC Control */ +#define CAN_CCCR_RESETVALUE _U_(0x00000001) /**< \brief (CAN_CCCR reset_value) CC Control */ + +#define CAN_CCCR_INIT_Pos 0 /**< \brief (CAN_CCCR) Initialization */ +#define CAN_CCCR_INIT (_U_(0x1) << CAN_CCCR_INIT_Pos) +#define CAN_CCCR_CCE_Pos 1 /**< \brief (CAN_CCCR) Configuration Change Enable */ +#define CAN_CCCR_CCE (_U_(0x1) << CAN_CCCR_CCE_Pos) +#define CAN_CCCR_ASM_Pos 2 /**< \brief (CAN_CCCR) ASM Restricted Operation Mode */ +#define CAN_CCCR_ASM (_U_(0x1) << CAN_CCCR_ASM_Pos) +#define CAN_CCCR_CSA_Pos 3 /**< \brief (CAN_CCCR) Clock Stop Acknowledge */ +#define CAN_CCCR_CSA (_U_(0x1) << CAN_CCCR_CSA_Pos) +#define CAN_CCCR_CSR_Pos 4 /**< \brief (CAN_CCCR) Clock Stop Request */ +#define CAN_CCCR_CSR (_U_(0x1) << CAN_CCCR_CSR_Pos) +#define CAN_CCCR_MON_Pos 5 /**< \brief (CAN_CCCR) Bus Monitoring Mode */ +#define CAN_CCCR_MON (_U_(0x1) << CAN_CCCR_MON_Pos) +#define CAN_CCCR_DAR_Pos 6 /**< \brief (CAN_CCCR) Disable Automatic Retransmission */ +#define CAN_CCCR_DAR (_U_(0x1) << CAN_CCCR_DAR_Pos) +#define CAN_CCCR_TEST_Pos 7 /**< \brief (CAN_CCCR) Test Mode Enable */ +#define CAN_CCCR_TEST (_U_(0x1) << CAN_CCCR_TEST_Pos) +#define CAN_CCCR_FDOE_Pos 8 /**< \brief (CAN_CCCR) FD Operation Enable */ +#define CAN_CCCR_FDOE (_U_(0x1) << CAN_CCCR_FDOE_Pos) +#define CAN_CCCR_BRSE_Pos 9 /**< \brief (CAN_CCCR) Bit Rate Switch Enable */ +#define CAN_CCCR_BRSE (_U_(0x1) << CAN_CCCR_BRSE_Pos) +#define CAN_CCCR_PXHD_Pos 12 /**< \brief (CAN_CCCR) Protocol Exception Handling Disable */ +#define CAN_CCCR_PXHD (_U_(0x1) << CAN_CCCR_PXHD_Pos) +#define CAN_CCCR_EFBI_Pos 13 /**< \brief (CAN_CCCR) Edge Filtering during Bus Integration */ +#define CAN_CCCR_EFBI (_U_(0x1) << CAN_CCCR_EFBI_Pos) +#define CAN_CCCR_TXP_Pos 14 /**< \brief (CAN_CCCR) Transmit Pause */ +#define CAN_CCCR_TXP (_U_(0x1) << CAN_CCCR_TXP_Pos) +#define CAN_CCCR_NISO_Pos 15 /**< \brief (CAN_CCCR) Non ISO Operation */ +#define CAN_CCCR_NISO (_U_(0x1) << CAN_CCCR_NISO_Pos) +#define CAN_CCCR_MASK _U_(0x0000F3FF) /**< \brief (CAN_CCCR) MASK Register */ + +/* -------- CAN_NBTP : (CAN Offset: 0x1C) (R/W 32) Nominal Bit Timing and Prescaler -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t NTSEG2:7; /*!< bit: 0.. 6 Nominal Time segment after sample point */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t NTSEG1:8; /*!< bit: 8..15 Nominal Time segment before sample point */ + uint32_t NBRP:9; /*!< bit: 16..24 Nominal Baud Rate Prescaler */ + uint32_t NSJW:7; /*!< bit: 25..31 Nominal (Re)Synchronization Jump Width */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_NBTP_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_NBTP_OFFSET 0x1C /**< \brief (CAN_NBTP offset) Nominal Bit Timing and Prescaler */ +#define CAN_NBTP_RESETVALUE _U_(0x06000A03) /**< \brief (CAN_NBTP reset_value) Nominal Bit Timing and Prescaler */ + +#define CAN_NBTP_NTSEG2_Pos 0 /**< \brief (CAN_NBTP) Nominal Time segment after sample point */ +#define CAN_NBTP_NTSEG2_Msk (_U_(0x7F) << CAN_NBTP_NTSEG2_Pos) +#define CAN_NBTP_NTSEG2(value) (CAN_NBTP_NTSEG2_Msk & ((value) << CAN_NBTP_NTSEG2_Pos)) +#define CAN_NBTP_NTSEG1_Pos 8 /**< \brief (CAN_NBTP) Nominal Time segment before sample point */ +#define CAN_NBTP_NTSEG1_Msk (_U_(0xFF) << CAN_NBTP_NTSEG1_Pos) +#define CAN_NBTP_NTSEG1(value) (CAN_NBTP_NTSEG1_Msk & ((value) << CAN_NBTP_NTSEG1_Pos)) +#define CAN_NBTP_NBRP_Pos 16 /**< \brief (CAN_NBTP) Nominal Baud Rate Prescaler */ +#define CAN_NBTP_NBRP_Msk (_U_(0x1FF) << CAN_NBTP_NBRP_Pos) +#define CAN_NBTP_NBRP(value) (CAN_NBTP_NBRP_Msk & ((value) << CAN_NBTP_NBRP_Pos)) +#define CAN_NBTP_NSJW_Pos 25 /**< \brief (CAN_NBTP) Nominal (Re)Synchronization Jump Width */ +#define CAN_NBTP_NSJW_Msk (_U_(0x7F) << CAN_NBTP_NSJW_Pos) +#define CAN_NBTP_NSJW(value) (CAN_NBTP_NSJW_Msk & ((value) << CAN_NBTP_NSJW_Pos)) +#define CAN_NBTP_MASK _U_(0xFFFFFF7F) /**< \brief (CAN_NBTP) MASK Register */ + +/* -------- CAN_TSCC : (CAN Offset: 0x20) (R/W 32) Timestamp Counter Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TSS:2; /*!< bit: 0.. 1 Timestamp Select */ + uint32_t :14; /*!< bit: 2..15 Reserved */ + uint32_t TCP:4; /*!< bit: 16..19 Timestamp Counter Prescaler */ + uint32_t :12; /*!< bit: 20..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TSCC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TSCC_OFFSET 0x20 /**< \brief (CAN_TSCC offset) Timestamp Counter Configuration */ +#define CAN_TSCC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TSCC reset_value) Timestamp Counter Configuration */ + +#define CAN_TSCC_TSS_Pos 0 /**< \brief (CAN_TSCC) Timestamp Select */ +#define CAN_TSCC_TSS_Msk (_U_(0x3) << CAN_TSCC_TSS_Pos) +#define CAN_TSCC_TSS(value) (CAN_TSCC_TSS_Msk & ((value) << CAN_TSCC_TSS_Pos)) +#define CAN_TSCC_TSS_ZERO_Val _U_(0x0) /**< \brief (CAN_TSCC) Timestamp counter value always 0x0000 */ +#define CAN_TSCC_TSS_INC_Val _U_(0x1) /**< \brief (CAN_TSCC) Timestamp counter value incremented by TCP */ +#define CAN_TSCC_TSS_EXT_Val _U_(0x2) /**< \brief (CAN_TSCC) External timestamp counter value used */ +#define CAN_TSCC_TSS_ZERO (CAN_TSCC_TSS_ZERO_Val << CAN_TSCC_TSS_Pos) +#define CAN_TSCC_TSS_INC (CAN_TSCC_TSS_INC_Val << CAN_TSCC_TSS_Pos) +#define CAN_TSCC_TSS_EXT (CAN_TSCC_TSS_EXT_Val << CAN_TSCC_TSS_Pos) +#define CAN_TSCC_TCP_Pos 16 /**< \brief (CAN_TSCC) Timestamp Counter Prescaler */ +#define CAN_TSCC_TCP_Msk (_U_(0xF) << CAN_TSCC_TCP_Pos) +#define CAN_TSCC_TCP(value) (CAN_TSCC_TCP_Msk & ((value) << CAN_TSCC_TCP_Pos)) +#define CAN_TSCC_MASK _U_(0x000F0003) /**< \brief (CAN_TSCC) MASK Register */ + +/* -------- CAN_TSCV : (CAN Offset: 0x24) (R/ 32) Timestamp Counter Value -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TSC:16; /*!< bit: 0..15 Timestamp Counter */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TSCV_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TSCV_OFFSET 0x24 /**< \brief (CAN_TSCV offset) Timestamp Counter Value */ +#define CAN_TSCV_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TSCV reset_value) Timestamp Counter Value */ + +#define CAN_TSCV_TSC_Pos 0 /**< \brief (CAN_TSCV) Timestamp Counter */ +#define CAN_TSCV_TSC_Msk (_U_(0xFFFF) << CAN_TSCV_TSC_Pos) +#define CAN_TSCV_TSC(value) (CAN_TSCV_TSC_Msk & ((value) << CAN_TSCV_TSC_Pos)) +#define CAN_TSCV_MASK _U_(0x0000FFFF) /**< \brief (CAN_TSCV) MASK Register */ + +/* -------- CAN_TOCC : (CAN Offset: 0x28) (R/W 32) Timeout Counter Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ETOC:1; /*!< bit: 0 Enable Timeout Counter */ + uint32_t TOS:2; /*!< bit: 1.. 2 Timeout Select */ + uint32_t :13; /*!< bit: 3..15 Reserved */ + uint32_t TOP:16; /*!< bit: 16..31 Timeout Period */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TOCC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TOCC_OFFSET 0x28 /**< \brief (CAN_TOCC offset) Timeout Counter Configuration */ +#define CAN_TOCC_RESETVALUE _U_(0xFFFF0000) /**< \brief (CAN_TOCC reset_value) Timeout Counter Configuration */ + +#define CAN_TOCC_ETOC_Pos 0 /**< \brief (CAN_TOCC) Enable Timeout Counter */ +#define CAN_TOCC_ETOC (_U_(0x1) << CAN_TOCC_ETOC_Pos) +#define CAN_TOCC_TOS_Pos 1 /**< \brief (CAN_TOCC) Timeout Select */ +#define CAN_TOCC_TOS_Msk (_U_(0x3) << CAN_TOCC_TOS_Pos) +#define CAN_TOCC_TOS(value) (CAN_TOCC_TOS_Msk & ((value) << CAN_TOCC_TOS_Pos)) +#define CAN_TOCC_TOS_CONT_Val _U_(0x0) /**< \brief (CAN_TOCC) Continuout operation */ +#define CAN_TOCC_TOS_TXEF_Val _U_(0x1) /**< \brief (CAN_TOCC) Timeout controlled by TX Event FIFO */ +#define CAN_TOCC_TOS_RXF0_Val _U_(0x2) /**< \brief (CAN_TOCC) Timeout controlled by Rx FIFO 0 */ +#define CAN_TOCC_TOS_RXF1_Val _U_(0x3) /**< \brief (CAN_TOCC) Timeout controlled by Rx FIFO 1 */ +#define CAN_TOCC_TOS_CONT (CAN_TOCC_TOS_CONT_Val << CAN_TOCC_TOS_Pos) +#define CAN_TOCC_TOS_TXEF (CAN_TOCC_TOS_TXEF_Val << CAN_TOCC_TOS_Pos) +#define CAN_TOCC_TOS_RXF0 (CAN_TOCC_TOS_RXF0_Val << CAN_TOCC_TOS_Pos) +#define CAN_TOCC_TOS_RXF1 (CAN_TOCC_TOS_RXF1_Val << CAN_TOCC_TOS_Pos) +#define CAN_TOCC_TOP_Pos 16 /**< \brief (CAN_TOCC) Timeout Period */ +#define CAN_TOCC_TOP_Msk (_U_(0xFFFF) << CAN_TOCC_TOP_Pos) +#define CAN_TOCC_TOP(value) (CAN_TOCC_TOP_Msk & ((value) << CAN_TOCC_TOP_Pos)) +#define CAN_TOCC_MASK _U_(0xFFFF0007) /**< \brief (CAN_TOCC) MASK Register */ + +/* -------- CAN_TOCV : (CAN Offset: 0x2C) (R/W 32) Timeout Counter Value -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TOC:16; /*!< bit: 0..15 Timeout Counter */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TOCV_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TOCV_OFFSET 0x2C /**< \brief (CAN_TOCV offset) Timeout Counter Value */ +#define CAN_TOCV_RESETVALUE _U_(0x0000FFFF) /**< \brief (CAN_TOCV reset_value) Timeout Counter Value */ + +#define CAN_TOCV_TOC_Pos 0 /**< \brief (CAN_TOCV) Timeout Counter */ +#define CAN_TOCV_TOC_Msk (_U_(0xFFFF) << CAN_TOCV_TOC_Pos) +#define CAN_TOCV_TOC(value) (CAN_TOCV_TOC_Msk & ((value) << CAN_TOCV_TOC_Pos)) +#define CAN_TOCV_MASK _U_(0x0000FFFF) /**< \brief (CAN_TOCV) MASK Register */ + +/* -------- CAN_ECR : (CAN Offset: 0x40) (R/ 32) Error Counter -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TEC:8; /*!< bit: 0.. 7 Transmit Error Counter */ + uint32_t REC:7; /*!< bit: 8..14 Receive Error Counter */ + uint32_t RP:1; /*!< bit: 15 Receive Error Passive */ + uint32_t CEL:8; /*!< bit: 16..23 CAN Error Logging */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_ECR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_ECR_OFFSET 0x40 /**< \brief (CAN_ECR offset) Error Counter */ +#define CAN_ECR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_ECR reset_value) Error Counter */ + +#define CAN_ECR_TEC_Pos 0 /**< \brief (CAN_ECR) Transmit Error Counter */ +#define CAN_ECR_TEC_Msk (_U_(0xFF) << CAN_ECR_TEC_Pos) +#define CAN_ECR_TEC(value) (CAN_ECR_TEC_Msk & ((value) << CAN_ECR_TEC_Pos)) +#define CAN_ECR_REC_Pos 8 /**< \brief (CAN_ECR) Receive Error Counter */ +#define CAN_ECR_REC_Msk (_U_(0x7F) << CAN_ECR_REC_Pos) +#define CAN_ECR_REC(value) (CAN_ECR_REC_Msk & ((value) << CAN_ECR_REC_Pos)) +#define CAN_ECR_RP_Pos 15 /**< \brief (CAN_ECR) Receive Error Passive */ +#define CAN_ECR_RP (_U_(0x1) << CAN_ECR_RP_Pos) +#define CAN_ECR_CEL_Pos 16 /**< \brief (CAN_ECR) CAN Error Logging */ +#define CAN_ECR_CEL_Msk (_U_(0xFF) << CAN_ECR_CEL_Pos) +#define CAN_ECR_CEL(value) (CAN_ECR_CEL_Msk & ((value) << CAN_ECR_CEL_Pos)) +#define CAN_ECR_MASK _U_(0x00FFFFFF) /**< \brief (CAN_ECR) MASK Register */ + +/* -------- CAN_PSR : (CAN Offset: 0x44) (R/ 32) Protocol Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t LEC:3; /*!< bit: 0.. 2 Last Error Code */ + uint32_t ACT:2; /*!< bit: 3.. 4 Activity */ + uint32_t EP:1; /*!< bit: 5 Error Passive */ + uint32_t EW:1; /*!< bit: 6 Warning Status */ + uint32_t BO:1; /*!< bit: 7 Bus_Off Status */ + uint32_t DLEC:3; /*!< bit: 8..10 Data Phase Last Error Code */ + uint32_t RESI:1; /*!< bit: 11 ESI flag of last received CAN FD Message */ + uint32_t RBRS:1; /*!< bit: 12 BRS flag of last received CAN FD Message */ + uint32_t RFDF:1; /*!< bit: 13 Received a CAN FD Message */ + uint32_t PXE:1; /*!< bit: 14 Protocol Exception Event */ + uint32_t :1; /*!< bit: 15 Reserved */ + uint32_t TDCV:7; /*!< bit: 16..22 Transmitter Delay Compensation Value */ + uint32_t :9; /*!< bit: 23..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_PSR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_PSR_OFFSET 0x44 /**< \brief (CAN_PSR offset) Protocol Status */ +#define CAN_PSR_RESETVALUE _U_(0x00000707) /**< \brief (CAN_PSR reset_value) Protocol Status */ + +#define CAN_PSR_LEC_Pos 0 /**< \brief (CAN_PSR) Last Error Code */ +#define CAN_PSR_LEC_Msk (_U_(0x7) << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC(value) (CAN_PSR_LEC_Msk & ((value) << CAN_PSR_LEC_Pos)) +#define CAN_PSR_LEC_NONE_Val _U_(0x0) /**< \brief (CAN_PSR) No Error */ +#define CAN_PSR_LEC_STUFF_Val _U_(0x1) /**< \brief (CAN_PSR) Stuff Error */ +#define CAN_PSR_LEC_FORM_Val _U_(0x2) /**< \brief (CAN_PSR) Form Error */ +#define CAN_PSR_LEC_ACK_Val _U_(0x3) /**< \brief (CAN_PSR) Ack Error */ +#define CAN_PSR_LEC_BIT1_Val _U_(0x4) /**< \brief (CAN_PSR) Bit1 Error */ +#define CAN_PSR_LEC_BIT0_Val _U_(0x5) /**< \brief (CAN_PSR) Bit0 Error */ +#define CAN_PSR_LEC_CRC_Val _U_(0x6) /**< \brief (CAN_PSR) CRC Error */ +#define CAN_PSR_LEC_NC_Val _U_(0x7) /**< \brief (CAN_PSR) No Change */ +#define CAN_PSR_LEC_NONE (CAN_PSR_LEC_NONE_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC_STUFF (CAN_PSR_LEC_STUFF_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC_FORM (CAN_PSR_LEC_FORM_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC_ACK (CAN_PSR_LEC_ACK_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC_BIT1 (CAN_PSR_LEC_BIT1_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC_BIT0 (CAN_PSR_LEC_BIT0_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC_CRC (CAN_PSR_LEC_CRC_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_LEC_NC (CAN_PSR_LEC_NC_Val << CAN_PSR_LEC_Pos) +#define CAN_PSR_ACT_Pos 3 /**< \brief (CAN_PSR) Activity */ +#define CAN_PSR_ACT_Msk (_U_(0x3) << CAN_PSR_ACT_Pos) +#define CAN_PSR_ACT(value) (CAN_PSR_ACT_Msk & ((value) << CAN_PSR_ACT_Pos)) +#define CAN_PSR_ACT_SYNC_Val _U_(0x0) /**< \brief (CAN_PSR) Node is synchronizing on CAN communication */ +#define CAN_PSR_ACT_IDLE_Val _U_(0x1) /**< \brief (CAN_PSR) Node is neither receiver nor transmitter */ +#define CAN_PSR_ACT_RX_Val _U_(0x2) /**< \brief (CAN_PSR) Node is operating as receiver */ +#define CAN_PSR_ACT_TX_Val _U_(0x3) /**< \brief (CAN_PSR) Node is operating as transmitter */ +#define CAN_PSR_ACT_SYNC (CAN_PSR_ACT_SYNC_Val << CAN_PSR_ACT_Pos) +#define CAN_PSR_ACT_IDLE (CAN_PSR_ACT_IDLE_Val << CAN_PSR_ACT_Pos) +#define CAN_PSR_ACT_RX (CAN_PSR_ACT_RX_Val << CAN_PSR_ACT_Pos) +#define CAN_PSR_ACT_TX (CAN_PSR_ACT_TX_Val << CAN_PSR_ACT_Pos) +#define CAN_PSR_EP_Pos 5 /**< \brief (CAN_PSR) Error Passive */ +#define CAN_PSR_EP (_U_(0x1) << CAN_PSR_EP_Pos) +#define CAN_PSR_EW_Pos 6 /**< \brief (CAN_PSR) Warning Status */ +#define CAN_PSR_EW (_U_(0x1) << CAN_PSR_EW_Pos) +#define CAN_PSR_BO_Pos 7 /**< \brief (CAN_PSR) Bus_Off Status */ +#define CAN_PSR_BO (_U_(0x1) << CAN_PSR_BO_Pos) +#define CAN_PSR_DLEC_Pos 8 /**< \brief (CAN_PSR) Data Phase Last Error Code */ +#define CAN_PSR_DLEC_Msk (_U_(0x7) << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC(value) (CAN_PSR_DLEC_Msk & ((value) << CAN_PSR_DLEC_Pos)) +#define CAN_PSR_DLEC_NONE_Val _U_(0x0) /**< \brief (CAN_PSR) No Error */ +#define CAN_PSR_DLEC_STUFF_Val _U_(0x1) /**< \brief (CAN_PSR) Stuff Error */ +#define CAN_PSR_DLEC_FORM_Val _U_(0x2) /**< \brief (CAN_PSR) Form Error */ +#define CAN_PSR_DLEC_ACK_Val _U_(0x3) /**< \brief (CAN_PSR) Ack Error */ +#define CAN_PSR_DLEC_BIT1_Val _U_(0x4) /**< \brief (CAN_PSR) Bit1 Error */ +#define CAN_PSR_DLEC_BIT0_Val _U_(0x5) /**< \brief (CAN_PSR) Bit0 Error */ +#define CAN_PSR_DLEC_CRC_Val _U_(0x6) /**< \brief (CAN_PSR) CRC Error */ +#define CAN_PSR_DLEC_NC_Val _U_(0x7) /**< \brief (CAN_PSR) No Change */ +#define CAN_PSR_DLEC_NONE (CAN_PSR_DLEC_NONE_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC_STUFF (CAN_PSR_DLEC_STUFF_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC_FORM (CAN_PSR_DLEC_FORM_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC_ACK (CAN_PSR_DLEC_ACK_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC_BIT1 (CAN_PSR_DLEC_BIT1_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC_BIT0 (CAN_PSR_DLEC_BIT0_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC_CRC (CAN_PSR_DLEC_CRC_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_DLEC_NC (CAN_PSR_DLEC_NC_Val << CAN_PSR_DLEC_Pos) +#define CAN_PSR_RESI_Pos 11 /**< \brief (CAN_PSR) ESI flag of last received CAN FD Message */ +#define CAN_PSR_RESI (_U_(0x1) << CAN_PSR_RESI_Pos) +#define CAN_PSR_RBRS_Pos 12 /**< \brief (CAN_PSR) BRS flag of last received CAN FD Message */ +#define CAN_PSR_RBRS (_U_(0x1) << CAN_PSR_RBRS_Pos) +#define CAN_PSR_RFDF_Pos 13 /**< \brief (CAN_PSR) Received a CAN FD Message */ +#define CAN_PSR_RFDF (_U_(0x1) << CAN_PSR_RFDF_Pos) +#define CAN_PSR_PXE_Pos 14 /**< \brief (CAN_PSR) Protocol Exception Event */ +#define CAN_PSR_PXE (_U_(0x1) << CAN_PSR_PXE_Pos) +#define CAN_PSR_TDCV_Pos 16 /**< \brief (CAN_PSR) Transmitter Delay Compensation Value */ +#define CAN_PSR_TDCV_Msk (_U_(0x7F) << CAN_PSR_TDCV_Pos) +#define CAN_PSR_TDCV(value) (CAN_PSR_TDCV_Msk & ((value) << CAN_PSR_TDCV_Pos)) +#define CAN_PSR_MASK _U_(0x007F7FFF) /**< \brief (CAN_PSR) MASK Register */ + +/* -------- CAN_TDCR : (CAN Offset: 0x48) (R/W 32) Extended ID Filter Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TDCF:7; /*!< bit: 0.. 6 Transmitter Delay Compensation Filter Length */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t TDCO:7; /*!< bit: 8..14 Transmitter Delay Compensation Offset */ + uint32_t :17; /*!< bit: 15..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TDCR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TDCR_OFFSET 0x48 /**< \brief (CAN_TDCR offset) Extended ID Filter Configuration */ +#define CAN_TDCR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TDCR reset_value) Extended ID Filter Configuration */ + +#define CAN_TDCR_TDCF_Pos 0 /**< \brief (CAN_TDCR) Transmitter Delay Compensation Filter Length */ +#define CAN_TDCR_TDCF_Msk (_U_(0x7F) << CAN_TDCR_TDCF_Pos) +#define CAN_TDCR_TDCF(value) (CAN_TDCR_TDCF_Msk & ((value) << CAN_TDCR_TDCF_Pos)) +#define CAN_TDCR_TDCO_Pos 8 /**< \brief (CAN_TDCR) Transmitter Delay Compensation Offset */ +#define CAN_TDCR_TDCO_Msk (_U_(0x7F) << CAN_TDCR_TDCO_Pos) +#define CAN_TDCR_TDCO(value) (CAN_TDCR_TDCO_Msk & ((value) << CAN_TDCR_TDCO_Pos)) +#define CAN_TDCR_MASK _U_(0x00007F7F) /**< \brief (CAN_TDCR) MASK Register */ + +/* -------- CAN_IR : (CAN Offset: 0x50) (R/W 32) Interrupt -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RF0N:1; /*!< bit: 0 Rx FIFO 0 New Message */ + uint32_t RF0W:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached */ + uint32_t RF0F:1; /*!< bit: 2 Rx FIFO 0 Full */ + uint32_t RF0L:1; /*!< bit: 3 Rx FIFO 0 Message Lost */ + uint32_t RF1N:1; /*!< bit: 4 Rx FIFO 1 New Message */ + uint32_t RF1W:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached */ + uint32_t RF1F:1; /*!< bit: 6 Rx FIFO 1 FIFO Full */ + uint32_t RF1L:1; /*!< bit: 7 Rx FIFO 1 Message Lost */ + uint32_t HPM:1; /*!< bit: 8 High Priority Message */ + uint32_t TC:1; /*!< bit: 9 Timestamp Completed */ + uint32_t TCF:1; /*!< bit: 10 Transmission Cancellation Finished */ + uint32_t TFE:1; /*!< bit: 11 Tx FIFO Empty */ + uint32_t TEFN:1; /*!< bit: 12 Tx Event FIFO New Entry */ + uint32_t TEFW:1; /*!< bit: 13 Tx Event FIFO Watermark Reached */ + uint32_t TEFF:1; /*!< bit: 14 Tx Event FIFO Full */ + uint32_t TEFL:1; /*!< bit: 15 Tx Event FIFO Element Lost */ + uint32_t TSW:1; /*!< bit: 16 Timestamp Wraparound */ + uint32_t MRAF:1; /*!< bit: 17 Message RAM Access Failure */ + uint32_t TOO:1; /*!< bit: 18 Timeout Occurred */ + uint32_t DRX:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer */ + uint32_t BEC:1; /*!< bit: 20 Bit Error Corrected */ + uint32_t BEU:1; /*!< bit: 21 Bit Error Uncorrected */ + uint32_t ELO:1; /*!< bit: 22 Error Logging Overflow */ + uint32_t EP:1; /*!< bit: 23 Error Passive */ + uint32_t EW:1; /*!< bit: 24 Warning Status */ + uint32_t BO:1; /*!< bit: 25 Bus_Off Status */ + uint32_t WDI:1; /*!< bit: 26 Watchdog Interrupt */ + uint32_t PEA:1; /*!< bit: 27 Protocol Error in Arbitration Phase */ + uint32_t PED:1; /*!< bit: 28 Protocol Error in Data Phase */ + uint32_t ARA:1; /*!< bit: 29 Access to Reserved Address */ + uint32_t :2; /*!< bit: 30..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_IR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_IR_OFFSET 0x50 /**< \brief (CAN_IR offset) Interrupt */ +#define CAN_IR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_IR reset_value) Interrupt */ + +#define CAN_IR_RF0N_Pos 0 /**< \brief (CAN_IR) Rx FIFO 0 New Message */ +#define CAN_IR_RF0N (_U_(0x1) << CAN_IR_RF0N_Pos) +#define CAN_IR_RF0W_Pos 1 /**< \brief (CAN_IR) Rx FIFO 0 Watermark Reached */ +#define CAN_IR_RF0W (_U_(0x1) << CAN_IR_RF0W_Pos) +#define CAN_IR_RF0F_Pos 2 /**< \brief (CAN_IR) Rx FIFO 0 Full */ +#define CAN_IR_RF0F (_U_(0x1) << CAN_IR_RF0F_Pos) +#define CAN_IR_RF0L_Pos 3 /**< \brief (CAN_IR) Rx FIFO 0 Message Lost */ +#define CAN_IR_RF0L (_U_(0x1) << CAN_IR_RF0L_Pos) +#define CAN_IR_RF1N_Pos 4 /**< \brief (CAN_IR) Rx FIFO 1 New Message */ +#define CAN_IR_RF1N (_U_(0x1) << CAN_IR_RF1N_Pos) +#define CAN_IR_RF1W_Pos 5 /**< \brief (CAN_IR) Rx FIFO 1 Watermark Reached */ +#define CAN_IR_RF1W (_U_(0x1) << CAN_IR_RF1W_Pos) +#define CAN_IR_RF1F_Pos 6 /**< \brief (CAN_IR) Rx FIFO 1 FIFO Full */ +#define CAN_IR_RF1F (_U_(0x1) << CAN_IR_RF1F_Pos) +#define CAN_IR_RF1L_Pos 7 /**< \brief (CAN_IR) Rx FIFO 1 Message Lost */ +#define CAN_IR_RF1L (_U_(0x1) << CAN_IR_RF1L_Pos) +#define CAN_IR_HPM_Pos 8 /**< \brief (CAN_IR) High Priority Message */ +#define CAN_IR_HPM (_U_(0x1) << CAN_IR_HPM_Pos) +#define CAN_IR_TC_Pos 9 /**< \brief (CAN_IR) Timestamp Completed */ +#define CAN_IR_TC (_U_(0x1) << CAN_IR_TC_Pos) +#define CAN_IR_TCF_Pos 10 /**< \brief (CAN_IR) Transmission Cancellation Finished */ +#define CAN_IR_TCF (_U_(0x1) << CAN_IR_TCF_Pos) +#define CAN_IR_TFE_Pos 11 /**< \brief (CAN_IR) Tx FIFO Empty */ +#define CAN_IR_TFE (_U_(0x1) << CAN_IR_TFE_Pos) +#define CAN_IR_TEFN_Pos 12 /**< \brief (CAN_IR) Tx Event FIFO New Entry */ +#define CAN_IR_TEFN (_U_(0x1) << CAN_IR_TEFN_Pos) +#define CAN_IR_TEFW_Pos 13 /**< \brief (CAN_IR) Tx Event FIFO Watermark Reached */ +#define CAN_IR_TEFW (_U_(0x1) << CAN_IR_TEFW_Pos) +#define CAN_IR_TEFF_Pos 14 /**< \brief (CAN_IR) Tx Event FIFO Full */ +#define CAN_IR_TEFF (_U_(0x1) << CAN_IR_TEFF_Pos) +#define CAN_IR_TEFL_Pos 15 /**< \brief (CAN_IR) Tx Event FIFO Element Lost */ +#define CAN_IR_TEFL (_U_(0x1) << CAN_IR_TEFL_Pos) +#define CAN_IR_TSW_Pos 16 /**< \brief (CAN_IR) Timestamp Wraparound */ +#define CAN_IR_TSW (_U_(0x1) << CAN_IR_TSW_Pos) +#define CAN_IR_MRAF_Pos 17 /**< \brief (CAN_IR) Message RAM Access Failure */ +#define CAN_IR_MRAF (_U_(0x1) << CAN_IR_MRAF_Pos) +#define CAN_IR_TOO_Pos 18 /**< \brief (CAN_IR) Timeout Occurred */ +#define CAN_IR_TOO (_U_(0x1) << CAN_IR_TOO_Pos) +#define CAN_IR_DRX_Pos 19 /**< \brief (CAN_IR) Message stored to Dedicated Rx Buffer */ +#define CAN_IR_DRX (_U_(0x1) << CAN_IR_DRX_Pos) +#define CAN_IR_BEC_Pos 20 /**< \brief (CAN_IR) Bit Error Corrected */ +#define CAN_IR_BEC (_U_(0x1) << CAN_IR_BEC_Pos) +#define CAN_IR_BEU_Pos 21 /**< \brief (CAN_IR) Bit Error Uncorrected */ +#define CAN_IR_BEU (_U_(0x1) << CAN_IR_BEU_Pos) +#define CAN_IR_ELO_Pos 22 /**< \brief (CAN_IR) Error Logging Overflow */ +#define CAN_IR_ELO (_U_(0x1) << CAN_IR_ELO_Pos) +#define CAN_IR_EP_Pos 23 /**< \brief (CAN_IR) Error Passive */ +#define CAN_IR_EP (_U_(0x1) << CAN_IR_EP_Pos) +#define CAN_IR_EW_Pos 24 /**< \brief (CAN_IR) Warning Status */ +#define CAN_IR_EW (_U_(0x1) << CAN_IR_EW_Pos) +#define CAN_IR_BO_Pos 25 /**< \brief (CAN_IR) Bus_Off Status */ +#define CAN_IR_BO (_U_(0x1) << CAN_IR_BO_Pos) +#define CAN_IR_WDI_Pos 26 /**< \brief (CAN_IR) Watchdog Interrupt */ +#define CAN_IR_WDI (_U_(0x1) << CAN_IR_WDI_Pos) +#define CAN_IR_PEA_Pos 27 /**< \brief (CAN_IR) Protocol Error in Arbitration Phase */ +#define CAN_IR_PEA (_U_(0x1) << CAN_IR_PEA_Pos) +#define CAN_IR_PED_Pos 28 /**< \brief (CAN_IR) Protocol Error in Data Phase */ +#define CAN_IR_PED (_U_(0x1) << CAN_IR_PED_Pos) +#define CAN_IR_ARA_Pos 29 /**< \brief (CAN_IR) Access to Reserved Address */ +#define CAN_IR_ARA (_U_(0x1) << CAN_IR_ARA_Pos) +#define CAN_IR_MASK _U_(0x3FFFFFFF) /**< \brief (CAN_IR) MASK Register */ + +/* -------- CAN_IE : (CAN Offset: 0x54) (R/W 32) Interrupt Enable -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RF0NE:1; /*!< bit: 0 Rx FIFO 0 New Message Interrupt Enable */ + uint32_t RF0WE:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached Interrupt Enable */ + uint32_t RF0FE:1; /*!< bit: 2 Rx FIFO 0 Full Interrupt Enable */ + uint32_t RF0LE:1; /*!< bit: 3 Rx FIFO 0 Message Lost Interrupt Enable */ + uint32_t RF1NE:1; /*!< bit: 4 Rx FIFO 1 New Message Interrupt Enable */ + uint32_t RF1WE:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached Interrupt Enable */ + uint32_t RF1FE:1; /*!< bit: 6 Rx FIFO 1 FIFO Full Interrupt Enable */ + uint32_t RF1LE:1; /*!< bit: 7 Rx FIFO 1 Message Lost Interrupt Enable */ + uint32_t HPME:1; /*!< bit: 8 High Priority Message Interrupt Enable */ + uint32_t TCE:1; /*!< bit: 9 Timestamp Completed Interrupt Enable */ + uint32_t TCFE:1; /*!< bit: 10 Transmission Cancellation Finished Interrupt Enable */ + uint32_t TFEE:1; /*!< bit: 11 Tx FIFO Empty Interrupt Enable */ + uint32_t TEFNE:1; /*!< bit: 12 Tx Event FIFO New Entry Interrupt Enable */ + uint32_t TEFWE:1; /*!< bit: 13 Tx Event FIFO Watermark Reached Interrupt Enable */ + uint32_t TEFFE:1; /*!< bit: 14 Tx Event FIFO Full Interrupt Enable */ + uint32_t TEFLE:1; /*!< bit: 15 Tx Event FIFO Element Lost Interrupt Enable */ + uint32_t TSWE:1; /*!< bit: 16 Timestamp Wraparound Interrupt Enable */ + uint32_t MRAFE:1; /*!< bit: 17 Message RAM Access Failure Interrupt Enable */ + uint32_t TOOE:1; /*!< bit: 18 Timeout Occurred Interrupt Enable */ + uint32_t DRXE:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer Interrupt Enable */ + uint32_t BECE:1; /*!< bit: 20 Bit Error Corrected Interrupt Enable */ + uint32_t BEUE:1; /*!< bit: 21 Bit Error Uncorrected Interrupt Enable */ + uint32_t ELOE:1; /*!< bit: 22 Error Logging Overflow Interrupt Enable */ + uint32_t EPE:1; /*!< bit: 23 Error Passive Interrupt Enable */ + uint32_t EWE:1; /*!< bit: 24 Warning Status Interrupt Enable */ + uint32_t BOE:1; /*!< bit: 25 Bus_Off Status Interrupt Enable */ + uint32_t WDIE:1; /*!< bit: 26 Watchdog Interrupt Interrupt Enable */ + uint32_t PEAE:1; /*!< bit: 27 Protocol Error in Arbitration Phase Enable */ + uint32_t PEDE:1; /*!< bit: 28 Protocol Error in Data Phase Enable */ + uint32_t ARAE:1; /*!< bit: 29 Access to Reserved Address Enable */ + uint32_t :2; /*!< bit: 30..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_IE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_IE_OFFSET 0x54 /**< \brief (CAN_IE offset) Interrupt Enable */ +#define CAN_IE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_IE reset_value) Interrupt Enable */ + +#define CAN_IE_RF0NE_Pos 0 /**< \brief (CAN_IE) Rx FIFO 0 New Message Interrupt Enable */ +#define CAN_IE_RF0NE (_U_(0x1) << CAN_IE_RF0NE_Pos) +#define CAN_IE_RF0WE_Pos 1 /**< \brief (CAN_IE) Rx FIFO 0 Watermark Reached Interrupt Enable */ +#define CAN_IE_RF0WE (_U_(0x1) << CAN_IE_RF0WE_Pos) +#define CAN_IE_RF0FE_Pos 2 /**< \brief (CAN_IE) Rx FIFO 0 Full Interrupt Enable */ +#define CAN_IE_RF0FE (_U_(0x1) << CAN_IE_RF0FE_Pos) +#define CAN_IE_RF0LE_Pos 3 /**< \brief (CAN_IE) Rx FIFO 0 Message Lost Interrupt Enable */ +#define CAN_IE_RF0LE (_U_(0x1) << CAN_IE_RF0LE_Pos) +#define CAN_IE_RF1NE_Pos 4 /**< \brief (CAN_IE) Rx FIFO 1 New Message Interrupt Enable */ +#define CAN_IE_RF1NE (_U_(0x1) << CAN_IE_RF1NE_Pos) +#define CAN_IE_RF1WE_Pos 5 /**< \brief (CAN_IE) Rx FIFO 1 Watermark Reached Interrupt Enable */ +#define CAN_IE_RF1WE (_U_(0x1) << CAN_IE_RF1WE_Pos) +#define CAN_IE_RF1FE_Pos 6 /**< \brief (CAN_IE) Rx FIFO 1 FIFO Full Interrupt Enable */ +#define CAN_IE_RF1FE (_U_(0x1) << CAN_IE_RF1FE_Pos) +#define CAN_IE_RF1LE_Pos 7 /**< \brief (CAN_IE) Rx FIFO 1 Message Lost Interrupt Enable */ +#define CAN_IE_RF1LE (_U_(0x1) << CAN_IE_RF1LE_Pos) +#define CAN_IE_HPME_Pos 8 /**< \brief (CAN_IE) High Priority Message Interrupt Enable */ +#define CAN_IE_HPME (_U_(0x1) << CAN_IE_HPME_Pos) +#define CAN_IE_TCE_Pos 9 /**< \brief (CAN_IE) Timestamp Completed Interrupt Enable */ +#define CAN_IE_TCE (_U_(0x1) << CAN_IE_TCE_Pos) +#define CAN_IE_TCFE_Pos 10 /**< \brief (CAN_IE) Transmission Cancellation Finished Interrupt Enable */ +#define CAN_IE_TCFE (_U_(0x1) << CAN_IE_TCFE_Pos) +#define CAN_IE_TFEE_Pos 11 /**< \brief (CAN_IE) Tx FIFO Empty Interrupt Enable */ +#define CAN_IE_TFEE (_U_(0x1) << CAN_IE_TFEE_Pos) +#define CAN_IE_TEFNE_Pos 12 /**< \brief (CAN_IE) Tx Event FIFO New Entry Interrupt Enable */ +#define CAN_IE_TEFNE (_U_(0x1) << CAN_IE_TEFNE_Pos) +#define CAN_IE_TEFWE_Pos 13 /**< \brief (CAN_IE) Tx Event FIFO Watermark Reached Interrupt Enable */ +#define CAN_IE_TEFWE (_U_(0x1) << CAN_IE_TEFWE_Pos) +#define CAN_IE_TEFFE_Pos 14 /**< \brief (CAN_IE) Tx Event FIFO Full Interrupt Enable */ +#define CAN_IE_TEFFE (_U_(0x1) << CAN_IE_TEFFE_Pos) +#define CAN_IE_TEFLE_Pos 15 /**< \brief (CAN_IE) Tx Event FIFO Element Lost Interrupt Enable */ +#define CAN_IE_TEFLE (_U_(0x1) << CAN_IE_TEFLE_Pos) +#define CAN_IE_TSWE_Pos 16 /**< \brief (CAN_IE) Timestamp Wraparound Interrupt Enable */ +#define CAN_IE_TSWE (_U_(0x1) << CAN_IE_TSWE_Pos) +#define CAN_IE_MRAFE_Pos 17 /**< \brief (CAN_IE) Message RAM Access Failure Interrupt Enable */ +#define CAN_IE_MRAFE (_U_(0x1) << CAN_IE_MRAFE_Pos) +#define CAN_IE_TOOE_Pos 18 /**< \brief (CAN_IE) Timeout Occurred Interrupt Enable */ +#define CAN_IE_TOOE (_U_(0x1) << CAN_IE_TOOE_Pos) +#define CAN_IE_DRXE_Pos 19 /**< \brief (CAN_IE) Message stored to Dedicated Rx Buffer Interrupt Enable */ +#define CAN_IE_DRXE (_U_(0x1) << CAN_IE_DRXE_Pos) +#define CAN_IE_BECE_Pos 20 /**< \brief (CAN_IE) Bit Error Corrected Interrupt Enable */ +#define CAN_IE_BECE (_U_(0x1) << CAN_IE_BECE_Pos) +#define CAN_IE_BEUE_Pos 21 /**< \brief (CAN_IE) Bit Error Uncorrected Interrupt Enable */ +#define CAN_IE_BEUE (_U_(0x1) << CAN_IE_BEUE_Pos) +#define CAN_IE_ELOE_Pos 22 /**< \brief (CAN_IE) Error Logging Overflow Interrupt Enable */ +#define CAN_IE_ELOE (_U_(0x1) << CAN_IE_ELOE_Pos) +#define CAN_IE_EPE_Pos 23 /**< \brief (CAN_IE) Error Passive Interrupt Enable */ +#define CAN_IE_EPE (_U_(0x1) << CAN_IE_EPE_Pos) +#define CAN_IE_EWE_Pos 24 /**< \brief (CAN_IE) Warning Status Interrupt Enable */ +#define CAN_IE_EWE (_U_(0x1) << CAN_IE_EWE_Pos) +#define CAN_IE_BOE_Pos 25 /**< \brief (CAN_IE) Bus_Off Status Interrupt Enable */ +#define CAN_IE_BOE (_U_(0x1) << CAN_IE_BOE_Pos) +#define CAN_IE_WDIE_Pos 26 /**< \brief (CAN_IE) Watchdog Interrupt Interrupt Enable */ +#define CAN_IE_WDIE (_U_(0x1) << CAN_IE_WDIE_Pos) +#define CAN_IE_PEAE_Pos 27 /**< \brief (CAN_IE) Protocol Error in Arbitration Phase Enable */ +#define CAN_IE_PEAE (_U_(0x1) << CAN_IE_PEAE_Pos) +#define CAN_IE_PEDE_Pos 28 /**< \brief (CAN_IE) Protocol Error in Data Phase Enable */ +#define CAN_IE_PEDE (_U_(0x1) << CAN_IE_PEDE_Pos) +#define CAN_IE_ARAE_Pos 29 /**< \brief (CAN_IE) Access to Reserved Address Enable */ +#define CAN_IE_ARAE (_U_(0x1) << CAN_IE_ARAE_Pos) +#define CAN_IE_MASK _U_(0x3FFFFFFF) /**< \brief (CAN_IE) MASK Register */ + +/* -------- CAN_ILS : (CAN Offset: 0x58) (R/W 32) Interrupt Line Select -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RF0NL:1; /*!< bit: 0 Rx FIFO 0 New Message Interrupt Line */ + uint32_t RF0WL:1; /*!< bit: 1 Rx FIFO 0 Watermark Reached Interrupt Line */ + uint32_t RF0FL:1; /*!< bit: 2 Rx FIFO 0 Full Interrupt Line */ + uint32_t RF0LL:1; /*!< bit: 3 Rx FIFO 0 Message Lost Interrupt Line */ + uint32_t RF1NL:1; /*!< bit: 4 Rx FIFO 1 New Message Interrupt Line */ + uint32_t RF1WL:1; /*!< bit: 5 Rx FIFO 1 Watermark Reached Interrupt Line */ + uint32_t RF1FL:1; /*!< bit: 6 Rx FIFO 1 FIFO Full Interrupt Line */ + uint32_t RF1LL:1; /*!< bit: 7 Rx FIFO 1 Message Lost Interrupt Line */ + uint32_t HPML:1; /*!< bit: 8 High Priority Message Interrupt Line */ + uint32_t TCL:1; /*!< bit: 9 Timestamp Completed Interrupt Line */ + uint32_t TCFL:1; /*!< bit: 10 Transmission Cancellation Finished Interrupt Line */ + uint32_t TFEL:1; /*!< bit: 11 Tx FIFO Empty Interrupt Line */ + uint32_t TEFNL:1; /*!< bit: 12 Tx Event FIFO New Entry Interrupt Line */ + uint32_t TEFWL:1; /*!< bit: 13 Tx Event FIFO Watermark Reached Interrupt Line */ + uint32_t TEFFL:1; /*!< bit: 14 Tx Event FIFO Full Interrupt Line */ + uint32_t TEFLL:1; /*!< bit: 15 Tx Event FIFO Element Lost Interrupt Line */ + uint32_t TSWL:1; /*!< bit: 16 Timestamp Wraparound Interrupt Line */ + uint32_t MRAFL:1; /*!< bit: 17 Message RAM Access Failure Interrupt Line */ + uint32_t TOOL:1; /*!< bit: 18 Timeout Occurred Interrupt Line */ + uint32_t DRXL:1; /*!< bit: 19 Message stored to Dedicated Rx Buffer Interrupt Line */ + uint32_t BECL:1; /*!< bit: 20 Bit Error Corrected Interrupt Line */ + uint32_t BEUL:1; /*!< bit: 21 Bit Error Uncorrected Interrupt Line */ + uint32_t ELOL:1; /*!< bit: 22 Error Logging Overflow Interrupt Line */ + uint32_t EPL:1; /*!< bit: 23 Error Passive Interrupt Line */ + uint32_t EWL:1; /*!< bit: 24 Warning Status Interrupt Line */ + uint32_t BOL:1; /*!< bit: 25 Bus_Off Status Interrupt Line */ + uint32_t WDIL:1; /*!< bit: 26 Watchdog Interrupt Interrupt Line */ + uint32_t PEAL:1; /*!< bit: 27 Protocol Error in Arbitration Phase Line */ + uint32_t PEDL:1; /*!< bit: 28 Protocol Error in Data Phase Line */ + uint32_t ARAL:1; /*!< bit: 29 Access to Reserved Address Line */ + uint32_t :2; /*!< bit: 30..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_ILS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_ILS_OFFSET 0x58 /**< \brief (CAN_ILS offset) Interrupt Line Select */ +#define CAN_ILS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_ILS reset_value) Interrupt Line Select */ + +#define CAN_ILS_RF0NL_Pos 0 /**< \brief (CAN_ILS) Rx FIFO 0 New Message Interrupt Line */ +#define CAN_ILS_RF0NL (_U_(0x1) << CAN_ILS_RF0NL_Pos) +#define CAN_ILS_RF0WL_Pos 1 /**< \brief (CAN_ILS) Rx FIFO 0 Watermark Reached Interrupt Line */ +#define CAN_ILS_RF0WL (_U_(0x1) << CAN_ILS_RF0WL_Pos) +#define CAN_ILS_RF0FL_Pos 2 /**< \brief (CAN_ILS) Rx FIFO 0 Full Interrupt Line */ +#define CAN_ILS_RF0FL (_U_(0x1) << CAN_ILS_RF0FL_Pos) +#define CAN_ILS_RF0LL_Pos 3 /**< \brief (CAN_ILS) Rx FIFO 0 Message Lost Interrupt Line */ +#define CAN_ILS_RF0LL (_U_(0x1) << CAN_ILS_RF0LL_Pos) +#define CAN_ILS_RF1NL_Pos 4 /**< \brief (CAN_ILS) Rx FIFO 1 New Message Interrupt Line */ +#define CAN_ILS_RF1NL (_U_(0x1) << CAN_ILS_RF1NL_Pos) +#define CAN_ILS_RF1WL_Pos 5 /**< \brief (CAN_ILS) Rx FIFO 1 Watermark Reached Interrupt Line */ +#define CAN_ILS_RF1WL (_U_(0x1) << CAN_ILS_RF1WL_Pos) +#define CAN_ILS_RF1FL_Pos 6 /**< \brief (CAN_ILS) Rx FIFO 1 FIFO Full Interrupt Line */ +#define CAN_ILS_RF1FL (_U_(0x1) << CAN_ILS_RF1FL_Pos) +#define CAN_ILS_RF1LL_Pos 7 /**< \brief (CAN_ILS) Rx FIFO 1 Message Lost Interrupt Line */ +#define CAN_ILS_RF1LL (_U_(0x1) << CAN_ILS_RF1LL_Pos) +#define CAN_ILS_HPML_Pos 8 /**< \brief (CAN_ILS) High Priority Message Interrupt Line */ +#define CAN_ILS_HPML (_U_(0x1) << CAN_ILS_HPML_Pos) +#define CAN_ILS_TCL_Pos 9 /**< \brief (CAN_ILS) Timestamp Completed Interrupt Line */ +#define CAN_ILS_TCL (_U_(0x1) << CAN_ILS_TCL_Pos) +#define CAN_ILS_TCFL_Pos 10 /**< \brief (CAN_ILS) Transmission Cancellation Finished Interrupt Line */ +#define CAN_ILS_TCFL (_U_(0x1) << CAN_ILS_TCFL_Pos) +#define CAN_ILS_TFEL_Pos 11 /**< \brief (CAN_ILS) Tx FIFO Empty Interrupt Line */ +#define CAN_ILS_TFEL (_U_(0x1) << CAN_ILS_TFEL_Pos) +#define CAN_ILS_TEFNL_Pos 12 /**< \brief (CAN_ILS) Tx Event FIFO New Entry Interrupt Line */ +#define CAN_ILS_TEFNL (_U_(0x1) << CAN_ILS_TEFNL_Pos) +#define CAN_ILS_TEFWL_Pos 13 /**< \brief (CAN_ILS) Tx Event FIFO Watermark Reached Interrupt Line */ +#define CAN_ILS_TEFWL (_U_(0x1) << CAN_ILS_TEFWL_Pos) +#define CAN_ILS_TEFFL_Pos 14 /**< \brief (CAN_ILS) Tx Event FIFO Full Interrupt Line */ +#define CAN_ILS_TEFFL (_U_(0x1) << CAN_ILS_TEFFL_Pos) +#define CAN_ILS_TEFLL_Pos 15 /**< \brief (CAN_ILS) Tx Event FIFO Element Lost Interrupt Line */ +#define CAN_ILS_TEFLL (_U_(0x1) << CAN_ILS_TEFLL_Pos) +#define CAN_ILS_TSWL_Pos 16 /**< \brief (CAN_ILS) Timestamp Wraparound Interrupt Line */ +#define CAN_ILS_TSWL (_U_(0x1) << CAN_ILS_TSWL_Pos) +#define CAN_ILS_MRAFL_Pos 17 /**< \brief (CAN_ILS) Message RAM Access Failure Interrupt Line */ +#define CAN_ILS_MRAFL (_U_(0x1) << CAN_ILS_MRAFL_Pos) +#define CAN_ILS_TOOL_Pos 18 /**< \brief (CAN_ILS) Timeout Occurred Interrupt Line */ +#define CAN_ILS_TOOL (_U_(0x1) << CAN_ILS_TOOL_Pos) +#define CAN_ILS_DRXL_Pos 19 /**< \brief (CAN_ILS) Message stored to Dedicated Rx Buffer Interrupt Line */ +#define CAN_ILS_DRXL (_U_(0x1) << CAN_ILS_DRXL_Pos) +#define CAN_ILS_BECL_Pos 20 /**< \brief (CAN_ILS) Bit Error Corrected Interrupt Line */ +#define CAN_ILS_BECL (_U_(0x1) << CAN_ILS_BECL_Pos) +#define CAN_ILS_BEUL_Pos 21 /**< \brief (CAN_ILS) Bit Error Uncorrected Interrupt Line */ +#define CAN_ILS_BEUL (_U_(0x1) << CAN_ILS_BEUL_Pos) +#define CAN_ILS_ELOL_Pos 22 /**< \brief (CAN_ILS) Error Logging Overflow Interrupt Line */ +#define CAN_ILS_ELOL (_U_(0x1) << CAN_ILS_ELOL_Pos) +#define CAN_ILS_EPL_Pos 23 /**< \brief (CAN_ILS) Error Passive Interrupt Line */ +#define CAN_ILS_EPL (_U_(0x1) << CAN_ILS_EPL_Pos) +#define CAN_ILS_EWL_Pos 24 /**< \brief (CAN_ILS) Warning Status Interrupt Line */ +#define CAN_ILS_EWL (_U_(0x1) << CAN_ILS_EWL_Pos) +#define CAN_ILS_BOL_Pos 25 /**< \brief (CAN_ILS) Bus_Off Status Interrupt Line */ +#define CAN_ILS_BOL (_U_(0x1) << CAN_ILS_BOL_Pos) +#define CAN_ILS_WDIL_Pos 26 /**< \brief (CAN_ILS) Watchdog Interrupt Interrupt Line */ +#define CAN_ILS_WDIL (_U_(0x1) << CAN_ILS_WDIL_Pos) +#define CAN_ILS_PEAL_Pos 27 /**< \brief (CAN_ILS) Protocol Error in Arbitration Phase Line */ +#define CAN_ILS_PEAL (_U_(0x1) << CAN_ILS_PEAL_Pos) +#define CAN_ILS_PEDL_Pos 28 /**< \brief (CAN_ILS) Protocol Error in Data Phase Line */ +#define CAN_ILS_PEDL (_U_(0x1) << CAN_ILS_PEDL_Pos) +#define CAN_ILS_ARAL_Pos 29 /**< \brief (CAN_ILS) Access to Reserved Address Line */ +#define CAN_ILS_ARAL (_U_(0x1) << CAN_ILS_ARAL_Pos) +#define CAN_ILS_MASK _U_(0x3FFFFFFF) /**< \brief (CAN_ILS) MASK Register */ + +/* -------- CAN_ILE : (CAN Offset: 0x5C) (R/W 32) Interrupt Line Enable -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EINT0:1; /*!< bit: 0 Enable Interrupt Line 0 */ + uint32_t EINT1:1; /*!< bit: 1 Enable Interrupt Line 1 */ + uint32_t :30; /*!< bit: 2..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_ILE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_ILE_OFFSET 0x5C /**< \brief (CAN_ILE offset) Interrupt Line Enable */ +#define CAN_ILE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_ILE reset_value) Interrupt Line Enable */ + +#define CAN_ILE_EINT0_Pos 0 /**< \brief (CAN_ILE) Enable Interrupt Line 0 */ +#define CAN_ILE_EINT0 (_U_(0x1) << CAN_ILE_EINT0_Pos) +#define CAN_ILE_EINT1_Pos 1 /**< \brief (CAN_ILE) Enable Interrupt Line 1 */ +#define CAN_ILE_EINT1 (_U_(0x1) << CAN_ILE_EINT1_Pos) +#define CAN_ILE_MASK _U_(0x00000003) /**< \brief (CAN_ILE) MASK Register */ + +/* -------- CAN_GFC : (CAN Offset: 0x80) (R/W 32) Global Filter Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RRFE:1; /*!< bit: 0 Reject Remote Frames Extended */ + uint32_t RRFS:1; /*!< bit: 1 Reject Remote Frames Standard */ + uint32_t ANFE:2; /*!< bit: 2.. 3 Accept Non-matching Frames Extended */ + uint32_t ANFS:2; /*!< bit: 4.. 5 Accept Non-matching Frames Standard */ + uint32_t :26; /*!< bit: 6..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_GFC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_GFC_OFFSET 0x80 /**< \brief (CAN_GFC offset) Global Filter Configuration */ +#define CAN_GFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_GFC reset_value) Global Filter Configuration */ + +#define CAN_GFC_RRFE_Pos 0 /**< \brief (CAN_GFC) Reject Remote Frames Extended */ +#define CAN_GFC_RRFE (_U_(0x1) << CAN_GFC_RRFE_Pos) +#define CAN_GFC_RRFS_Pos 1 /**< \brief (CAN_GFC) Reject Remote Frames Standard */ +#define CAN_GFC_RRFS (_U_(0x1) << CAN_GFC_RRFS_Pos) +#define CAN_GFC_ANFE_Pos 2 /**< \brief (CAN_GFC) Accept Non-matching Frames Extended */ +#define CAN_GFC_ANFE_Msk (_U_(0x3) << CAN_GFC_ANFE_Pos) +#define CAN_GFC_ANFE(value) (CAN_GFC_ANFE_Msk & ((value) << CAN_GFC_ANFE_Pos)) +#define CAN_GFC_ANFE_RXF0_Val _U_(0x0) /**< \brief (CAN_GFC) Accept in Rx FIFO 0 */ +#define CAN_GFC_ANFE_RXF1_Val _U_(0x1) /**< \brief (CAN_GFC) Accept in Rx FIFO 1 */ +#define CAN_GFC_ANFE_REJECT_Val _U_(0x2) /**< \brief (CAN_GFC) Reject */ +#define CAN_GFC_ANFE_RXF0 (CAN_GFC_ANFE_RXF0_Val << CAN_GFC_ANFE_Pos) +#define CAN_GFC_ANFE_RXF1 (CAN_GFC_ANFE_RXF1_Val << CAN_GFC_ANFE_Pos) +#define CAN_GFC_ANFE_REJECT (CAN_GFC_ANFE_REJECT_Val << CAN_GFC_ANFE_Pos) +#define CAN_GFC_ANFS_Pos 4 /**< \brief (CAN_GFC) Accept Non-matching Frames Standard */ +#define CAN_GFC_ANFS_Msk (_U_(0x3) << CAN_GFC_ANFS_Pos) +#define CAN_GFC_ANFS(value) (CAN_GFC_ANFS_Msk & ((value) << CAN_GFC_ANFS_Pos)) +#define CAN_GFC_ANFS_RXF0_Val _U_(0x0) /**< \brief (CAN_GFC) Accept in Rx FIFO 0 */ +#define CAN_GFC_ANFS_RXF1_Val _U_(0x1) /**< \brief (CAN_GFC) Accept in Rx FIFO 1 */ +#define CAN_GFC_ANFS_REJECT_Val _U_(0x2) /**< \brief (CAN_GFC) Reject */ +#define CAN_GFC_ANFS_RXF0 (CAN_GFC_ANFS_RXF0_Val << CAN_GFC_ANFS_Pos) +#define CAN_GFC_ANFS_RXF1 (CAN_GFC_ANFS_RXF1_Val << CAN_GFC_ANFS_Pos) +#define CAN_GFC_ANFS_REJECT (CAN_GFC_ANFS_REJECT_Val << CAN_GFC_ANFS_Pos) +#define CAN_GFC_MASK _U_(0x0000003F) /**< \brief (CAN_GFC) MASK Register */ + +/* -------- CAN_SIDFC : (CAN Offset: 0x84) (R/W 32) Standard ID Filter Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t FLSSA:16; /*!< bit: 0..15 Filter List Standard Start Address */ + uint32_t LSS:8; /*!< bit: 16..23 List Size Standard */ + uint32_t :8; /*!< bit: 24..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_SIDFC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_SIDFC_OFFSET 0x84 /**< \brief (CAN_SIDFC offset) Standard ID Filter Configuration */ +#define CAN_SIDFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_SIDFC reset_value) Standard ID Filter Configuration */ + +#define CAN_SIDFC_FLSSA_Pos 0 /**< \brief (CAN_SIDFC) Filter List Standard Start Address */ +#define CAN_SIDFC_FLSSA_Msk (_U_(0xFFFF) << CAN_SIDFC_FLSSA_Pos) +#define CAN_SIDFC_FLSSA(value) (CAN_SIDFC_FLSSA_Msk & ((value) << CAN_SIDFC_FLSSA_Pos)) +#define CAN_SIDFC_LSS_Pos 16 /**< \brief (CAN_SIDFC) List Size Standard */ +#define CAN_SIDFC_LSS_Msk (_U_(0xFF) << CAN_SIDFC_LSS_Pos) +#define CAN_SIDFC_LSS(value) (CAN_SIDFC_LSS_Msk & ((value) << CAN_SIDFC_LSS_Pos)) +#define CAN_SIDFC_MASK _U_(0x00FFFFFF) /**< \brief (CAN_SIDFC) MASK Register */ + +/* -------- CAN_XIDFC : (CAN Offset: 0x88) (R/W 32) Extended ID Filter Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t FLESA:16; /*!< bit: 0..15 Filter List Extended Start Address */ + uint32_t LSE:7; /*!< bit: 16..22 List Size Extended */ + uint32_t :9; /*!< bit: 23..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_XIDFC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_XIDFC_OFFSET 0x88 /**< \brief (CAN_XIDFC offset) Extended ID Filter Configuration */ +#define CAN_XIDFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_XIDFC reset_value) Extended ID Filter Configuration */ + +#define CAN_XIDFC_FLESA_Pos 0 /**< \brief (CAN_XIDFC) Filter List Extended Start Address */ +#define CAN_XIDFC_FLESA_Msk (_U_(0xFFFF) << CAN_XIDFC_FLESA_Pos) +#define CAN_XIDFC_FLESA(value) (CAN_XIDFC_FLESA_Msk & ((value) << CAN_XIDFC_FLESA_Pos)) +#define CAN_XIDFC_LSE_Pos 16 /**< \brief (CAN_XIDFC) List Size Extended */ +#define CAN_XIDFC_LSE_Msk (_U_(0x7F) << CAN_XIDFC_LSE_Pos) +#define CAN_XIDFC_LSE(value) (CAN_XIDFC_LSE_Msk & ((value) << CAN_XIDFC_LSE_Pos)) +#define CAN_XIDFC_MASK _U_(0x007FFFFF) /**< \brief (CAN_XIDFC) MASK Register */ + +/* -------- CAN_XIDAM : (CAN Offset: 0x90) (R/W 32) Extended ID AND Mask -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EIDM:29; /*!< bit: 0..28 Extended ID Mask */ + uint32_t :3; /*!< bit: 29..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_XIDAM_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_XIDAM_OFFSET 0x90 /**< \brief (CAN_XIDAM offset) Extended ID AND Mask */ +#define CAN_XIDAM_RESETVALUE _U_(0x1FFFFFFF) /**< \brief (CAN_XIDAM reset_value) Extended ID AND Mask */ + +#define CAN_XIDAM_EIDM_Pos 0 /**< \brief (CAN_XIDAM) Extended ID Mask */ +#define CAN_XIDAM_EIDM_Msk (_U_(0x1FFFFFFF) << CAN_XIDAM_EIDM_Pos) +#define CAN_XIDAM_EIDM(value) (CAN_XIDAM_EIDM_Msk & ((value) << CAN_XIDAM_EIDM_Pos)) +#define CAN_XIDAM_MASK _U_(0x1FFFFFFF) /**< \brief (CAN_XIDAM) MASK Register */ + +/* -------- CAN_HPMS : (CAN Offset: 0x94) (R/ 32) High Priority Message Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BIDX:6; /*!< bit: 0.. 5 Buffer Index */ + uint32_t MSI:2; /*!< bit: 6.. 7 Message Storage Indicator */ + uint32_t FIDX:7; /*!< bit: 8..14 Filter Index */ + uint32_t FLST:1; /*!< bit: 15 Filter List */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_HPMS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_HPMS_OFFSET 0x94 /**< \brief (CAN_HPMS offset) High Priority Message Status */ +#define CAN_HPMS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_HPMS reset_value) High Priority Message Status */ + +#define CAN_HPMS_BIDX_Pos 0 /**< \brief (CAN_HPMS) Buffer Index */ +#define CAN_HPMS_BIDX_Msk (_U_(0x3F) << CAN_HPMS_BIDX_Pos) +#define CAN_HPMS_BIDX(value) (CAN_HPMS_BIDX_Msk & ((value) << CAN_HPMS_BIDX_Pos)) +#define CAN_HPMS_MSI_Pos 6 /**< \brief (CAN_HPMS) Message Storage Indicator */ +#define CAN_HPMS_MSI_Msk (_U_(0x3) << CAN_HPMS_MSI_Pos) +#define CAN_HPMS_MSI(value) (CAN_HPMS_MSI_Msk & ((value) << CAN_HPMS_MSI_Pos)) +#define CAN_HPMS_MSI_NONE_Val _U_(0x0) /**< \brief (CAN_HPMS) No FIFO selected */ +#define CAN_HPMS_MSI_LOST_Val _U_(0x1) /**< \brief (CAN_HPMS) FIFO message lost */ +#define CAN_HPMS_MSI_FIFO0_Val _U_(0x2) /**< \brief (CAN_HPMS) Message stored in FIFO 0 */ +#define CAN_HPMS_MSI_FIFO1_Val _U_(0x3) /**< \brief (CAN_HPMS) Message stored in FIFO 1 */ +#define CAN_HPMS_MSI_NONE (CAN_HPMS_MSI_NONE_Val << CAN_HPMS_MSI_Pos) +#define CAN_HPMS_MSI_LOST (CAN_HPMS_MSI_LOST_Val << CAN_HPMS_MSI_Pos) +#define CAN_HPMS_MSI_FIFO0 (CAN_HPMS_MSI_FIFO0_Val << CAN_HPMS_MSI_Pos) +#define CAN_HPMS_MSI_FIFO1 (CAN_HPMS_MSI_FIFO1_Val << CAN_HPMS_MSI_Pos) +#define CAN_HPMS_FIDX_Pos 8 /**< \brief (CAN_HPMS) Filter Index */ +#define CAN_HPMS_FIDX_Msk (_U_(0x7F) << CAN_HPMS_FIDX_Pos) +#define CAN_HPMS_FIDX(value) (CAN_HPMS_FIDX_Msk & ((value) << CAN_HPMS_FIDX_Pos)) +#define CAN_HPMS_FLST_Pos 15 /**< \brief (CAN_HPMS) Filter List */ +#define CAN_HPMS_FLST (_U_(0x1) << CAN_HPMS_FLST_Pos) +#define CAN_HPMS_MASK _U_(0x0000FFFF) /**< \brief (CAN_HPMS) MASK Register */ + +/* -------- CAN_NDAT1 : (CAN Offset: 0x98) (R/W 32) New Data 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ND0:1; /*!< bit: 0 New Data 0 */ + uint32_t ND1:1; /*!< bit: 1 New Data 1 */ + uint32_t ND2:1; /*!< bit: 2 New Data 2 */ + uint32_t ND3:1; /*!< bit: 3 New Data 3 */ + uint32_t ND4:1; /*!< bit: 4 New Data 4 */ + uint32_t ND5:1; /*!< bit: 5 New Data 5 */ + uint32_t ND6:1; /*!< bit: 6 New Data 6 */ + uint32_t ND7:1; /*!< bit: 7 New Data 7 */ + uint32_t ND8:1; /*!< bit: 8 New Data 8 */ + uint32_t ND9:1; /*!< bit: 9 New Data 9 */ + uint32_t ND10:1; /*!< bit: 10 New Data 10 */ + uint32_t ND11:1; /*!< bit: 11 New Data 11 */ + uint32_t ND12:1; /*!< bit: 12 New Data 12 */ + uint32_t ND13:1; /*!< bit: 13 New Data 13 */ + uint32_t ND14:1; /*!< bit: 14 New Data 14 */ + uint32_t ND15:1; /*!< bit: 15 New Data 15 */ + uint32_t ND16:1; /*!< bit: 16 New Data 16 */ + uint32_t ND17:1; /*!< bit: 17 New Data 17 */ + uint32_t ND18:1; /*!< bit: 18 New Data 18 */ + uint32_t ND19:1; /*!< bit: 19 New Data 19 */ + uint32_t ND20:1; /*!< bit: 20 New Data 20 */ + uint32_t ND21:1; /*!< bit: 21 New Data 21 */ + uint32_t ND22:1; /*!< bit: 22 New Data 22 */ + uint32_t ND23:1; /*!< bit: 23 New Data 23 */ + uint32_t ND24:1; /*!< bit: 24 New Data 24 */ + uint32_t ND25:1; /*!< bit: 25 New Data 25 */ + uint32_t ND26:1; /*!< bit: 26 New Data 26 */ + uint32_t ND27:1; /*!< bit: 27 New Data 27 */ + uint32_t ND28:1; /*!< bit: 28 New Data 28 */ + uint32_t ND29:1; /*!< bit: 29 New Data 29 */ + uint32_t ND30:1; /*!< bit: 30 New Data 30 */ + uint32_t ND31:1; /*!< bit: 31 New Data 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_NDAT1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_NDAT1_OFFSET 0x98 /**< \brief (CAN_NDAT1 offset) New Data 1 */ +#define CAN_NDAT1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_NDAT1 reset_value) New Data 1 */ + +#define CAN_NDAT1_ND0_Pos 0 /**< \brief (CAN_NDAT1) New Data 0 */ +#define CAN_NDAT1_ND0 (_U_(0x1) << CAN_NDAT1_ND0_Pos) +#define CAN_NDAT1_ND1_Pos 1 /**< \brief (CAN_NDAT1) New Data 1 */ +#define CAN_NDAT1_ND1 (_U_(0x1) << CAN_NDAT1_ND1_Pos) +#define CAN_NDAT1_ND2_Pos 2 /**< \brief (CAN_NDAT1) New Data 2 */ +#define CAN_NDAT1_ND2 (_U_(0x1) << CAN_NDAT1_ND2_Pos) +#define CAN_NDAT1_ND3_Pos 3 /**< \brief (CAN_NDAT1) New Data 3 */ +#define CAN_NDAT1_ND3 (_U_(0x1) << CAN_NDAT1_ND3_Pos) +#define CAN_NDAT1_ND4_Pos 4 /**< \brief (CAN_NDAT1) New Data 4 */ +#define CAN_NDAT1_ND4 (_U_(0x1) << CAN_NDAT1_ND4_Pos) +#define CAN_NDAT1_ND5_Pos 5 /**< \brief (CAN_NDAT1) New Data 5 */ +#define CAN_NDAT1_ND5 (_U_(0x1) << CAN_NDAT1_ND5_Pos) +#define CAN_NDAT1_ND6_Pos 6 /**< \brief (CAN_NDAT1) New Data 6 */ +#define CAN_NDAT1_ND6 (_U_(0x1) << CAN_NDAT1_ND6_Pos) +#define CAN_NDAT1_ND7_Pos 7 /**< \brief (CAN_NDAT1) New Data 7 */ +#define CAN_NDAT1_ND7 (_U_(0x1) << CAN_NDAT1_ND7_Pos) +#define CAN_NDAT1_ND8_Pos 8 /**< \brief (CAN_NDAT1) New Data 8 */ +#define CAN_NDAT1_ND8 (_U_(0x1) << CAN_NDAT1_ND8_Pos) +#define CAN_NDAT1_ND9_Pos 9 /**< \brief (CAN_NDAT1) New Data 9 */ +#define CAN_NDAT1_ND9 (_U_(0x1) << CAN_NDAT1_ND9_Pos) +#define CAN_NDAT1_ND10_Pos 10 /**< \brief (CAN_NDAT1) New Data 10 */ +#define CAN_NDAT1_ND10 (_U_(0x1) << CAN_NDAT1_ND10_Pos) +#define CAN_NDAT1_ND11_Pos 11 /**< \brief (CAN_NDAT1) New Data 11 */ +#define CAN_NDAT1_ND11 (_U_(0x1) << CAN_NDAT1_ND11_Pos) +#define CAN_NDAT1_ND12_Pos 12 /**< \brief (CAN_NDAT1) New Data 12 */ +#define CAN_NDAT1_ND12 (_U_(0x1) << CAN_NDAT1_ND12_Pos) +#define CAN_NDAT1_ND13_Pos 13 /**< \brief (CAN_NDAT1) New Data 13 */ +#define CAN_NDAT1_ND13 (_U_(0x1) << CAN_NDAT1_ND13_Pos) +#define CAN_NDAT1_ND14_Pos 14 /**< \brief (CAN_NDAT1) New Data 14 */ +#define CAN_NDAT1_ND14 (_U_(0x1) << CAN_NDAT1_ND14_Pos) +#define CAN_NDAT1_ND15_Pos 15 /**< \brief (CAN_NDAT1) New Data 15 */ +#define CAN_NDAT1_ND15 (_U_(0x1) << CAN_NDAT1_ND15_Pos) +#define CAN_NDAT1_ND16_Pos 16 /**< \brief (CAN_NDAT1) New Data 16 */ +#define CAN_NDAT1_ND16 (_U_(0x1) << CAN_NDAT1_ND16_Pos) +#define CAN_NDAT1_ND17_Pos 17 /**< \brief (CAN_NDAT1) New Data 17 */ +#define CAN_NDAT1_ND17 (_U_(0x1) << CAN_NDAT1_ND17_Pos) +#define CAN_NDAT1_ND18_Pos 18 /**< \brief (CAN_NDAT1) New Data 18 */ +#define CAN_NDAT1_ND18 (_U_(0x1) << CAN_NDAT1_ND18_Pos) +#define CAN_NDAT1_ND19_Pos 19 /**< \brief (CAN_NDAT1) New Data 19 */ +#define CAN_NDAT1_ND19 (_U_(0x1) << CAN_NDAT1_ND19_Pos) +#define CAN_NDAT1_ND20_Pos 20 /**< \brief (CAN_NDAT1) New Data 20 */ +#define CAN_NDAT1_ND20 (_U_(0x1) << CAN_NDAT1_ND20_Pos) +#define CAN_NDAT1_ND21_Pos 21 /**< \brief (CAN_NDAT1) New Data 21 */ +#define CAN_NDAT1_ND21 (_U_(0x1) << CAN_NDAT1_ND21_Pos) +#define CAN_NDAT1_ND22_Pos 22 /**< \brief (CAN_NDAT1) New Data 22 */ +#define CAN_NDAT1_ND22 (_U_(0x1) << CAN_NDAT1_ND22_Pos) +#define CAN_NDAT1_ND23_Pos 23 /**< \brief (CAN_NDAT1) New Data 23 */ +#define CAN_NDAT1_ND23 (_U_(0x1) << CAN_NDAT1_ND23_Pos) +#define CAN_NDAT1_ND24_Pos 24 /**< \brief (CAN_NDAT1) New Data 24 */ +#define CAN_NDAT1_ND24 (_U_(0x1) << CAN_NDAT1_ND24_Pos) +#define CAN_NDAT1_ND25_Pos 25 /**< \brief (CAN_NDAT1) New Data 25 */ +#define CAN_NDAT1_ND25 (_U_(0x1) << CAN_NDAT1_ND25_Pos) +#define CAN_NDAT1_ND26_Pos 26 /**< \brief (CAN_NDAT1) New Data 26 */ +#define CAN_NDAT1_ND26 (_U_(0x1) << CAN_NDAT1_ND26_Pos) +#define CAN_NDAT1_ND27_Pos 27 /**< \brief (CAN_NDAT1) New Data 27 */ +#define CAN_NDAT1_ND27 (_U_(0x1) << CAN_NDAT1_ND27_Pos) +#define CAN_NDAT1_ND28_Pos 28 /**< \brief (CAN_NDAT1) New Data 28 */ +#define CAN_NDAT1_ND28 (_U_(0x1) << CAN_NDAT1_ND28_Pos) +#define CAN_NDAT1_ND29_Pos 29 /**< \brief (CAN_NDAT1) New Data 29 */ +#define CAN_NDAT1_ND29 (_U_(0x1) << CAN_NDAT1_ND29_Pos) +#define CAN_NDAT1_ND30_Pos 30 /**< \brief (CAN_NDAT1) New Data 30 */ +#define CAN_NDAT1_ND30 (_U_(0x1) << CAN_NDAT1_ND30_Pos) +#define CAN_NDAT1_ND31_Pos 31 /**< \brief (CAN_NDAT1) New Data 31 */ +#define CAN_NDAT1_ND31 (_U_(0x1) << CAN_NDAT1_ND31_Pos) +#define CAN_NDAT1_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_NDAT1) MASK Register */ + +/* -------- CAN_NDAT2 : (CAN Offset: 0x9C) (R/W 32) New Data 2 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ND32:1; /*!< bit: 0 New Data 32 */ + uint32_t ND33:1; /*!< bit: 1 New Data 33 */ + uint32_t ND34:1; /*!< bit: 2 New Data 34 */ + uint32_t ND35:1; /*!< bit: 3 New Data 35 */ + uint32_t ND36:1; /*!< bit: 4 New Data 36 */ + uint32_t ND37:1; /*!< bit: 5 New Data 37 */ + uint32_t ND38:1; /*!< bit: 6 New Data 38 */ + uint32_t ND39:1; /*!< bit: 7 New Data 39 */ + uint32_t ND40:1; /*!< bit: 8 New Data 40 */ + uint32_t ND41:1; /*!< bit: 9 New Data 41 */ + uint32_t ND42:1; /*!< bit: 10 New Data 42 */ + uint32_t ND43:1; /*!< bit: 11 New Data 43 */ + uint32_t ND44:1; /*!< bit: 12 New Data 44 */ + uint32_t ND45:1; /*!< bit: 13 New Data 45 */ + uint32_t ND46:1; /*!< bit: 14 New Data 46 */ + uint32_t ND47:1; /*!< bit: 15 New Data 47 */ + uint32_t ND48:1; /*!< bit: 16 New Data 48 */ + uint32_t ND49:1; /*!< bit: 17 New Data 49 */ + uint32_t ND50:1; /*!< bit: 18 New Data 50 */ + uint32_t ND51:1; /*!< bit: 19 New Data 51 */ + uint32_t ND52:1; /*!< bit: 20 New Data 52 */ + uint32_t ND53:1; /*!< bit: 21 New Data 53 */ + uint32_t ND54:1; /*!< bit: 22 New Data 54 */ + uint32_t ND55:1; /*!< bit: 23 New Data 55 */ + uint32_t ND56:1; /*!< bit: 24 New Data 56 */ + uint32_t ND57:1; /*!< bit: 25 New Data 57 */ + uint32_t ND58:1; /*!< bit: 26 New Data 58 */ + uint32_t ND59:1; /*!< bit: 27 New Data 59 */ + uint32_t ND60:1; /*!< bit: 28 New Data 60 */ + uint32_t ND61:1; /*!< bit: 29 New Data 61 */ + uint32_t ND62:1; /*!< bit: 30 New Data 62 */ + uint32_t ND63:1; /*!< bit: 31 New Data 63 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_NDAT2_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_NDAT2_OFFSET 0x9C /**< \brief (CAN_NDAT2 offset) New Data 2 */ +#define CAN_NDAT2_RESETVALUE _U_(0x00000000) /**< \brief (CAN_NDAT2 reset_value) New Data 2 */ + +#define CAN_NDAT2_ND32_Pos 0 /**< \brief (CAN_NDAT2) New Data 32 */ +#define CAN_NDAT2_ND32 (_U_(0x1) << CAN_NDAT2_ND32_Pos) +#define CAN_NDAT2_ND33_Pos 1 /**< \brief (CAN_NDAT2) New Data 33 */ +#define CAN_NDAT2_ND33 (_U_(0x1) << CAN_NDAT2_ND33_Pos) +#define CAN_NDAT2_ND34_Pos 2 /**< \brief (CAN_NDAT2) New Data 34 */ +#define CAN_NDAT2_ND34 (_U_(0x1) << CAN_NDAT2_ND34_Pos) +#define CAN_NDAT2_ND35_Pos 3 /**< \brief (CAN_NDAT2) New Data 35 */ +#define CAN_NDAT2_ND35 (_U_(0x1) << CAN_NDAT2_ND35_Pos) +#define CAN_NDAT2_ND36_Pos 4 /**< \brief (CAN_NDAT2) New Data 36 */ +#define CAN_NDAT2_ND36 (_U_(0x1) << CAN_NDAT2_ND36_Pos) +#define CAN_NDAT2_ND37_Pos 5 /**< \brief (CAN_NDAT2) New Data 37 */ +#define CAN_NDAT2_ND37 (_U_(0x1) << CAN_NDAT2_ND37_Pos) +#define CAN_NDAT2_ND38_Pos 6 /**< \brief (CAN_NDAT2) New Data 38 */ +#define CAN_NDAT2_ND38 (_U_(0x1) << CAN_NDAT2_ND38_Pos) +#define CAN_NDAT2_ND39_Pos 7 /**< \brief (CAN_NDAT2) New Data 39 */ +#define CAN_NDAT2_ND39 (_U_(0x1) << CAN_NDAT2_ND39_Pos) +#define CAN_NDAT2_ND40_Pos 8 /**< \brief (CAN_NDAT2) New Data 40 */ +#define CAN_NDAT2_ND40 (_U_(0x1) << CAN_NDAT2_ND40_Pos) +#define CAN_NDAT2_ND41_Pos 9 /**< \brief (CAN_NDAT2) New Data 41 */ +#define CAN_NDAT2_ND41 (_U_(0x1) << CAN_NDAT2_ND41_Pos) +#define CAN_NDAT2_ND42_Pos 10 /**< \brief (CAN_NDAT2) New Data 42 */ +#define CAN_NDAT2_ND42 (_U_(0x1) << CAN_NDAT2_ND42_Pos) +#define CAN_NDAT2_ND43_Pos 11 /**< \brief (CAN_NDAT2) New Data 43 */ +#define CAN_NDAT2_ND43 (_U_(0x1) << CAN_NDAT2_ND43_Pos) +#define CAN_NDAT2_ND44_Pos 12 /**< \brief (CAN_NDAT2) New Data 44 */ +#define CAN_NDAT2_ND44 (_U_(0x1) << CAN_NDAT2_ND44_Pos) +#define CAN_NDAT2_ND45_Pos 13 /**< \brief (CAN_NDAT2) New Data 45 */ +#define CAN_NDAT2_ND45 (_U_(0x1) << CAN_NDAT2_ND45_Pos) +#define CAN_NDAT2_ND46_Pos 14 /**< \brief (CAN_NDAT2) New Data 46 */ +#define CAN_NDAT2_ND46 (_U_(0x1) << CAN_NDAT2_ND46_Pos) +#define CAN_NDAT2_ND47_Pos 15 /**< \brief (CAN_NDAT2) New Data 47 */ +#define CAN_NDAT2_ND47 (_U_(0x1) << CAN_NDAT2_ND47_Pos) +#define CAN_NDAT2_ND48_Pos 16 /**< \brief (CAN_NDAT2) New Data 48 */ +#define CAN_NDAT2_ND48 (_U_(0x1) << CAN_NDAT2_ND48_Pos) +#define CAN_NDAT2_ND49_Pos 17 /**< \brief (CAN_NDAT2) New Data 49 */ +#define CAN_NDAT2_ND49 (_U_(0x1) << CAN_NDAT2_ND49_Pos) +#define CAN_NDAT2_ND50_Pos 18 /**< \brief (CAN_NDAT2) New Data 50 */ +#define CAN_NDAT2_ND50 (_U_(0x1) << CAN_NDAT2_ND50_Pos) +#define CAN_NDAT2_ND51_Pos 19 /**< \brief (CAN_NDAT2) New Data 51 */ +#define CAN_NDAT2_ND51 (_U_(0x1) << CAN_NDAT2_ND51_Pos) +#define CAN_NDAT2_ND52_Pos 20 /**< \brief (CAN_NDAT2) New Data 52 */ +#define CAN_NDAT2_ND52 (_U_(0x1) << CAN_NDAT2_ND52_Pos) +#define CAN_NDAT2_ND53_Pos 21 /**< \brief (CAN_NDAT2) New Data 53 */ +#define CAN_NDAT2_ND53 (_U_(0x1) << CAN_NDAT2_ND53_Pos) +#define CAN_NDAT2_ND54_Pos 22 /**< \brief (CAN_NDAT2) New Data 54 */ +#define CAN_NDAT2_ND54 (_U_(0x1) << CAN_NDAT2_ND54_Pos) +#define CAN_NDAT2_ND55_Pos 23 /**< \brief (CAN_NDAT2) New Data 55 */ +#define CAN_NDAT2_ND55 (_U_(0x1) << CAN_NDAT2_ND55_Pos) +#define CAN_NDAT2_ND56_Pos 24 /**< \brief (CAN_NDAT2) New Data 56 */ +#define CAN_NDAT2_ND56 (_U_(0x1) << CAN_NDAT2_ND56_Pos) +#define CAN_NDAT2_ND57_Pos 25 /**< \brief (CAN_NDAT2) New Data 57 */ +#define CAN_NDAT2_ND57 (_U_(0x1) << CAN_NDAT2_ND57_Pos) +#define CAN_NDAT2_ND58_Pos 26 /**< \brief (CAN_NDAT2) New Data 58 */ +#define CAN_NDAT2_ND58 (_U_(0x1) << CAN_NDAT2_ND58_Pos) +#define CAN_NDAT2_ND59_Pos 27 /**< \brief (CAN_NDAT2) New Data 59 */ +#define CAN_NDAT2_ND59 (_U_(0x1) << CAN_NDAT2_ND59_Pos) +#define CAN_NDAT2_ND60_Pos 28 /**< \brief (CAN_NDAT2) New Data 60 */ +#define CAN_NDAT2_ND60 (_U_(0x1) << CAN_NDAT2_ND60_Pos) +#define CAN_NDAT2_ND61_Pos 29 /**< \brief (CAN_NDAT2) New Data 61 */ +#define CAN_NDAT2_ND61 (_U_(0x1) << CAN_NDAT2_ND61_Pos) +#define CAN_NDAT2_ND62_Pos 30 /**< \brief (CAN_NDAT2) New Data 62 */ +#define CAN_NDAT2_ND62 (_U_(0x1) << CAN_NDAT2_ND62_Pos) +#define CAN_NDAT2_ND63_Pos 31 /**< \brief (CAN_NDAT2) New Data 63 */ +#define CAN_NDAT2_ND63 (_U_(0x1) << CAN_NDAT2_ND63_Pos) +#define CAN_NDAT2_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_NDAT2) MASK Register */ + +/* -------- CAN_RXF0C : (CAN Offset: 0xA0) (R/W 32) Rx FIFO 0 Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t F0SA:16; /*!< bit: 0..15 Rx FIFO 0 Start Address */ + uint32_t F0S:7; /*!< bit: 16..22 Rx FIFO 0 Size */ + uint32_t :1; /*!< bit: 23 Reserved */ + uint32_t F0WM:7; /*!< bit: 24..30 Rx FIFO 0 Watermark */ + uint32_t F0OM:1; /*!< bit: 31 FIFO 0 Operation Mode */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF0C_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF0C_OFFSET 0xA0 /**< \brief (CAN_RXF0C offset) Rx FIFO 0 Configuration */ +#define CAN_RXF0C_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0C reset_value) Rx FIFO 0 Configuration */ + +#define CAN_RXF0C_F0SA_Pos 0 /**< \brief (CAN_RXF0C) Rx FIFO 0 Start Address */ +#define CAN_RXF0C_F0SA_Msk (_U_(0xFFFF) << CAN_RXF0C_F0SA_Pos) +#define CAN_RXF0C_F0SA(value) (CAN_RXF0C_F0SA_Msk & ((value) << CAN_RXF0C_F0SA_Pos)) +#define CAN_RXF0C_F0S_Pos 16 /**< \brief (CAN_RXF0C) Rx FIFO 0 Size */ +#define CAN_RXF0C_F0S_Msk (_U_(0x7F) << CAN_RXF0C_F0S_Pos) +#define CAN_RXF0C_F0S(value) (CAN_RXF0C_F0S_Msk & ((value) << CAN_RXF0C_F0S_Pos)) +#define CAN_RXF0C_F0WM_Pos 24 /**< \brief (CAN_RXF0C) Rx FIFO 0 Watermark */ +#define CAN_RXF0C_F0WM_Msk (_U_(0x7F) << CAN_RXF0C_F0WM_Pos) +#define CAN_RXF0C_F0WM(value) (CAN_RXF0C_F0WM_Msk & ((value) << CAN_RXF0C_F0WM_Pos)) +#define CAN_RXF0C_F0OM_Pos 31 /**< \brief (CAN_RXF0C) FIFO 0 Operation Mode */ +#define CAN_RXF0C_F0OM (_U_(0x1) << CAN_RXF0C_F0OM_Pos) +#define CAN_RXF0C_MASK _U_(0xFF7FFFFF) /**< \brief (CAN_RXF0C) MASK Register */ + +/* -------- CAN_RXF0S : (CAN Offset: 0xA4) (R/ 32) Rx FIFO 0 Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t F0FL:7; /*!< bit: 0.. 6 Rx FIFO 0 Fill Level */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t F0GI:6; /*!< bit: 8..13 Rx FIFO 0 Get Index */ + uint32_t :2; /*!< bit: 14..15 Reserved */ + uint32_t F0PI:6; /*!< bit: 16..21 Rx FIFO 0 Put Index */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t F0F:1; /*!< bit: 24 Rx FIFO 0 Full */ + uint32_t RF0L:1; /*!< bit: 25 Rx FIFO 0 Message Lost */ + uint32_t :6; /*!< bit: 26..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF0S_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF0S_OFFSET 0xA4 /**< \brief (CAN_RXF0S offset) Rx FIFO 0 Status */ +#define CAN_RXF0S_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0S reset_value) Rx FIFO 0 Status */ + +#define CAN_RXF0S_F0FL_Pos 0 /**< \brief (CAN_RXF0S) Rx FIFO 0 Fill Level */ +#define CAN_RXF0S_F0FL_Msk (_U_(0x7F) << CAN_RXF0S_F0FL_Pos) +#define CAN_RXF0S_F0FL(value) (CAN_RXF0S_F0FL_Msk & ((value) << CAN_RXF0S_F0FL_Pos)) +#define CAN_RXF0S_F0GI_Pos 8 /**< \brief (CAN_RXF0S) Rx FIFO 0 Get Index */ +#define CAN_RXF0S_F0GI_Msk (_U_(0x3F) << CAN_RXF0S_F0GI_Pos) +#define CAN_RXF0S_F0GI(value) (CAN_RXF0S_F0GI_Msk & ((value) << CAN_RXF0S_F0GI_Pos)) +#define CAN_RXF0S_F0PI_Pos 16 /**< \brief (CAN_RXF0S) Rx FIFO 0 Put Index */ +#define CAN_RXF0S_F0PI_Msk (_U_(0x3F) << CAN_RXF0S_F0PI_Pos) +#define CAN_RXF0S_F0PI(value) (CAN_RXF0S_F0PI_Msk & ((value) << CAN_RXF0S_F0PI_Pos)) +#define CAN_RXF0S_F0F_Pos 24 /**< \brief (CAN_RXF0S) Rx FIFO 0 Full */ +#define CAN_RXF0S_F0F (_U_(0x1) << CAN_RXF0S_F0F_Pos) +#define CAN_RXF0S_RF0L_Pos 25 /**< \brief (CAN_RXF0S) Rx FIFO 0 Message Lost */ +#define CAN_RXF0S_RF0L (_U_(0x1) << CAN_RXF0S_RF0L_Pos) +#define CAN_RXF0S_MASK _U_(0x033F3F7F) /**< \brief (CAN_RXF0S) MASK Register */ + +/* -------- CAN_RXF0A : (CAN Offset: 0xA8) (R/W 32) Rx FIFO 0 Acknowledge -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t F0AI:6; /*!< bit: 0.. 5 Rx FIFO 0 Acknowledge Index */ + uint32_t :26; /*!< bit: 6..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF0A_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF0A_OFFSET 0xA8 /**< \brief (CAN_RXF0A offset) Rx FIFO 0 Acknowledge */ +#define CAN_RXF0A_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0A reset_value) Rx FIFO 0 Acknowledge */ + +#define CAN_RXF0A_F0AI_Pos 0 /**< \brief (CAN_RXF0A) Rx FIFO 0 Acknowledge Index */ +#define CAN_RXF0A_F0AI_Msk (_U_(0x3F) << CAN_RXF0A_F0AI_Pos) +#define CAN_RXF0A_F0AI(value) (CAN_RXF0A_F0AI_Msk & ((value) << CAN_RXF0A_F0AI_Pos)) +#define CAN_RXF0A_MASK _U_(0x0000003F) /**< \brief (CAN_RXF0A) MASK Register */ + +/* -------- CAN_RXBC : (CAN Offset: 0xAC) (R/W 32) Rx Buffer Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RBSA:16; /*!< bit: 0..15 Rx Buffer Start Address */ + uint32_t :16; /*!< bit: 16..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXBC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXBC_OFFSET 0xAC /**< \brief (CAN_RXBC offset) Rx Buffer Configuration */ +#define CAN_RXBC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXBC reset_value) Rx Buffer Configuration */ + +#define CAN_RXBC_RBSA_Pos 0 /**< \brief (CAN_RXBC) Rx Buffer Start Address */ +#define CAN_RXBC_RBSA_Msk (_U_(0xFFFF) << CAN_RXBC_RBSA_Pos) +#define CAN_RXBC_RBSA(value) (CAN_RXBC_RBSA_Msk & ((value) << CAN_RXBC_RBSA_Pos)) +#define CAN_RXBC_MASK _U_(0x0000FFFF) /**< \brief (CAN_RXBC) MASK Register */ + +/* -------- CAN_RXF1C : (CAN Offset: 0xB0) (R/W 32) Rx FIFO 1 Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t F1SA:16; /*!< bit: 0..15 Rx FIFO 1 Start Address */ + uint32_t F1S:7; /*!< bit: 16..22 Rx FIFO 1 Size */ + uint32_t :1; /*!< bit: 23 Reserved */ + uint32_t F1WM:7; /*!< bit: 24..30 Rx FIFO 1 Watermark */ + uint32_t F1OM:1; /*!< bit: 31 FIFO 1 Operation Mode */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF1C_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF1C_OFFSET 0xB0 /**< \brief (CAN_RXF1C offset) Rx FIFO 1 Configuration */ +#define CAN_RXF1C_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1C reset_value) Rx FIFO 1 Configuration */ + +#define CAN_RXF1C_F1SA_Pos 0 /**< \brief (CAN_RXF1C) Rx FIFO 1 Start Address */ +#define CAN_RXF1C_F1SA_Msk (_U_(0xFFFF) << CAN_RXF1C_F1SA_Pos) +#define CAN_RXF1C_F1SA(value) (CAN_RXF1C_F1SA_Msk & ((value) << CAN_RXF1C_F1SA_Pos)) +#define CAN_RXF1C_F1S_Pos 16 /**< \brief (CAN_RXF1C) Rx FIFO 1 Size */ +#define CAN_RXF1C_F1S_Msk (_U_(0x7F) << CAN_RXF1C_F1S_Pos) +#define CAN_RXF1C_F1S(value) (CAN_RXF1C_F1S_Msk & ((value) << CAN_RXF1C_F1S_Pos)) +#define CAN_RXF1C_F1WM_Pos 24 /**< \brief (CAN_RXF1C) Rx FIFO 1 Watermark */ +#define CAN_RXF1C_F1WM_Msk (_U_(0x7F) << CAN_RXF1C_F1WM_Pos) +#define CAN_RXF1C_F1WM(value) (CAN_RXF1C_F1WM_Msk & ((value) << CAN_RXF1C_F1WM_Pos)) +#define CAN_RXF1C_F1OM_Pos 31 /**< \brief (CAN_RXF1C) FIFO 1 Operation Mode */ +#define CAN_RXF1C_F1OM (_U_(0x1) << CAN_RXF1C_F1OM_Pos) +#define CAN_RXF1C_MASK _U_(0xFF7FFFFF) /**< \brief (CAN_RXF1C) MASK Register */ + +/* -------- CAN_RXF1S : (CAN Offset: 0xB4) (R/ 32) Rx FIFO 1 Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t F1FL:7; /*!< bit: 0.. 6 Rx FIFO 1 Fill Level */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t F1GI:6; /*!< bit: 8..13 Rx FIFO 1 Get Index */ + uint32_t :2; /*!< bit: 14..15 Reserved */ + uint32_t F1PI:6; /*!< bit: 16..21 Rx FIFO 1 Put Index */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t F1F:1; /*!< bit: 24 Rx FIFO 1 Full */ + uint32_t RF1L:1; /*!< bit: 25 Rx FIFO 1 Message Lost */ + uint32_t :4; /*!< bit: 26..29 Reserved */ + uint32_t DMS:2; /*!< bit: 30..31 Debug Message Status */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF1S_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF1S_OFFSET 0xB4 /**< \brief (CAN_RXF1S offset) Rx FIFO 1 Status */ +#define CAN_RXF1S_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1S reset_value) Rx FIFO 1 Status */ + +#define CAN_RXF1S_F1FL_Pos 0 /**< \brief (CAN_RXF1S) Rx FIFO 1 Fill Level */ +#define CAN_RXF1S_F1FL_Msk (_U_(0x7F) << CAN_RXF1S_F1FL_Pos) +#define CAN_RXF1S_F1FL(value) (CAN_RXF1S_F1FL_Msk & ((value) << CAN_RXF1S_F1FL_Pos)) +#define CAN_RXF1S_F1GI_Pos 8 /**< \brief (CAN_RXF1S) Rx FIFO 1 Get Index */ +#define CAN_RXF1S_F1GI_Msk (_U_(0x3F) << CAN_RXF1S_F1GI_Pos) +#define CAN_RXF1S_F1GI(value) (CAN_RXF1S_F1GI_Msk & ((value) << CAN_RXF1S_F1GI_Pos)) +#define CAN_RXF1S_F1PI_Pos 16 /**< \brief (CAN_RXF1S) Rx FIFO 1 Put Index */ +#define CAN_RXF1S_F1PI_Msk (_U_(0x3F) << CAN_RXF1S_F1PI_Pos) +#define CAN_RXF1S_F1PI(value) (CAN_RXF1S_F1PI_Msk & ((value) << CAN_RXF1S_F1PI_Pos)) +#define CAN_RXF1S_F1F_Pos 24 /**< \brief (CAN_RXF1S) Rx FIFO 1 Full */ +#define CAN_RXF1S_F1F (_U_(0x1) << CAN_RXF1S_F1F_Pos) +#define CAN_RXF1S_RF1L_Pos 25 /**< \brief (CAN_RXF1S) Rx FIFO 1 Message Lost */ +#define CAN_RXF1S_RF1L (_U_(0x1) << CAN_RXF1S_RF1L_Pos) +#define CAN_RXF1S_DMS_Pos 30 /**< \brief (CAN_RXF1S) Debug Message Status */ +#define CAN_RXF1S_DMS_Msk (_U_(0x3) << CAN_RXF1S_DMS_Pos) +#define CAN_RXF1S_DMS(value) (CAN_RXF1S_DMS_Msk & ((value) << CAN_RXF1S_DMS_Pos)) +#define CAN_RXF1S_DMS_IDLE_Val _U_(0x0) /**< \brief (CAN_RXF1S) Idle state */ +#define CAN_RXF1S_DMS_DBGA_Val _U_(0x1) /**< \brief (CAN_RXF1S) Debug message A received */ +#define CAN_RXF1S_DMS_DBGB_Val _U_(0x2) /**< \brief (CAN_RXF1S) Debug message A/B received */ +#define CAN_RXF1S_DMS_DBGC_Val _U_(0x3) /**< \brief (CAN_RXF1S) Debug message A/B/C received, DMA request set */ +#define CAN_RXF1S_DMS_IDLE (CAN_RXF1S_DMS_IDLE_Val << CAN_RXF1S_DMS_Pos) +#define CAN_RXF1S_DMS_DBGA (CAN_RXF1S_DMS_DBGA_Val << CAN_RXF1S_DMS_Pos) +#define CAN_RXF1S_DMS_DBGB (CAN_RXF1S_DMS_DBGB_Val << CAN_RXF1S_DMS_Pos) +#define CAN_RXF1S_DMS_DBGC (CAN_RXF1S_DMS_DBGC_Val << CAN_RXF1S_DMS_Pos) +#define CAN_RXF1S_MASK _U_(0xC33F3F7F) /**< \brief (CAN_RXF1S) MASK Register */ + +/* -------- CAN_RXF1A : (CAN Offset: 0xB8) (R/W 32) Rx FIFO 1 Acknowledge -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t F1AI:6; /*!< bit: 0.. 5 Rx FIFO 1 Acknowledge Index */ + uint32_t :26; /*!< bit: 6..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF1A_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF1A_OFFSET 0xB8 /**< \brief (CAN_RXF1A offset) Rx FIFO 1 Acknowledge */ +#define CAN_RXF1A_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1A reset_value) Rx FIFO 1 Acknowledge */ + +#define CAN_RXF1A_F1AI_Pos 0 /**< \brief (CAN_RXF1A) Rx FIFO 1 Acknowledge Index */ +#define CAN_RXF1A_F1AI_Msk (_U_(0x3F) << CAN_RXF1A_F1AI_Pos) +#define CAN_RXF1A_F1AI(value) (CAN_RXF1A_F1AI_Msk & ((value) << CAN_RXF1A_F1AI_Pos)) +#define CAN_RXF1A_MASK _U_(0x0000003F) /**< \brief (CAN_RXF1A) MASK Register */ + +/* -------- CAN_RXESC : (CAN Offset: 0xBC) (R/W 32) Rx Buffer / FIFO Element Size Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t F0DS:3; /*!< bit: 0.. 2 Rx FIFO 0 Data Field Size */ + uint32_t :1; /*!< bit: 3 Reserved */ + uint32_t F1DS:3; /*!< bit: 4.. 6 Rx FIFO 1 Data Field Size */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t RBDS:3; /*!< bit: 8..10 Rx Buffer Data Field Size */ + uint32_t :21; /*!< bit: 11..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXESC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXESC_OFFSET 0xBC /**< \brief (CAN_RXESC offset) Rx Buffer / FIFO Element Size Configuration */ +#define CAN_RXESC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXESC reset_value) Rx Buffer / FIFO Element Size Configuration */ + +#define CAN_RXESC_F0DS_Pos 0 /**< \brief (CAN_RXESC) Rx FIFO 0 Data Field Size */ +#define CAN_RXESC_F0DS_Msk (_U_(0x7) << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS(value) (CAN_RXESC_F0DS_Msk & ((value) << CAN_RXESC_F0DS_Pos)) +#define CAN_RXESC_F0DS_DATA8_Val _U_(0x0) /**< \brief (CAN_RXESC) 8 byte data field */ +#define CAN_RXESC_F0DS_DATA12_Val _U_(0x1) /**< \brief (CAN_RXESC) 12 byte data field */ +#define CAN_RXESC_F0DS_DATA16_Val _U_(0x2) /**< \brief (CAN_RXESC) 16 byte data field */ +#define CAN_RXESC_F0DS_DATA20_Val _U_(0x3) /**< \brief (CAN_RXESC) 20 byte data field */ +#define CAN_RXESC_F0DS_DATA24_Val _U_(0x4) /**< \brief (CAN_RXESC) 24 byte data field */ +#define CAN_RXESC_F0DS_DATA32_Val _U_(0x5) /**< \brief (CAN_RXESC) 32 byte data field */ +#define CAN_RXESC_F0DS_DATA48_Val _U_(0x6) /**< \brief (CAN_RXESC) 48 byte data field */ +#define CAN_RXESC_F0DS_DATA64_Val _U_(0x7) /**< \brief (CAN_RXESC) 64 byte data field */ +#define CAN_RXESC_F0DS_DATA8 (CAN_RXESC_F0DS_DATA8_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS_DATA12 (CAN_RXESC_F0DS_DATA12_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS_DATA16 (CAN_RXESC_F0DS_DATA16_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS_DATA20 (CAN_RXESC_F0DS_DATA20_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS_DATA24 (CAN_RXESC_F0DS_DATA24_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS_DATA32 (CAN_RXESC_F0DS_DATA32_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS_DATA48 (CAN_RXESC_F0DS_DATA48_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F0DS_DATA64 (CAN_RXESC_F0DS_DATA64_Val << CAN_RXESC_F0DS_Pos) +#define CAN_RXESC_F1DS_Pos 4 /**< \brief (CAN_RXESC) Rx FIFO 1 Data Field Size */ +#define CAN_RXESC_F1DS_Msk (_U_(0x7) << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS(value) (CAN_RXESC_F1DS_Msk & ((value) << CAN_RXESC_F1DS_Pos)) +#define CAN_RXESC_F1DS_DATA8_Val _U_(0x0) /**< \brief (CAN_RXESC) 8 byte data field */ +#define CAN_RXESC_F1DS_DATA12_Val _U_(0x1) /**< \brief (CAN_RXESC) 12 byte data field */ +#define CAN_RXESC_F1DS_DATA16_Val _U_(0x2) /**< \brief (CAN_RXESC) 16 byte data field */ +#define CAN_RXESC_F1DS_DATA20_Val _U_(0x3) /**< \brief (CAN_RXESC) 20 byte data field */ +#define CAN_RXESC_F1DS_DATA24_Val _U_(0x4) /**< \brief (CAN_RXESC) 24 byte data field */ +#define CAN_RXESC_F1DS_DATA32_Val _U_(0x5) /**< \brief (CAN_RXESC) 32 byte data field */ +#define CAN_RXESC_F1DS_DATA48_Val _U_(0x6) /**< \brief (CAN_RXESC) 48 byte data field */ +#define CAN_RXESC_F1DS_DATA64_Val _U_(0x7) /**< \brief (CAN_RXESC) 64 byte data field */ +#define CAN_RXESC_F1DS_DATA8 (CAN_RXESC_F1DS_DATA8_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS_DATA12 (CAN_RXESC_F1DS_DATA12_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS_DATA16 (CAN_RXESC_F1DS_DATA16_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS_DATA20 (CAN_RXESC_F1DS_DATA20_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS_DATA24 (CAN_RXESC_F1DS_DATA24_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS_DATA32 (CAN_RXESC_F1DS_DATA32_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS_DATA48 (CAN_RXESC_F1DS_DATA48_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_F1DS_DATA64 (CAN_RXESC_F1DS_DATA64_Val << CAN_RXESC_F1DS_Pos) +#define CAN_RXESC_RBDS_Pos 8 /**< \brief (CAN_RXESC) Rx Buffer Data Field Size */ +#define CAN_RXESC_RBDS_Msk (_U_(0x7) << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS(value) (CAN_RXESC_RBDS_Msk & ((value) << CAN_RXESC_RBDS_Pos)) +#define CAN_RXESC_RBDS_DATA8_Val _U_(0x0) /**< \brief (CAN_RXESC) 8 byte data field */ +#define CAN_RXESC_RBDS_DATA12_Val _U_(0x1) /**< \brief (CAN_RXESC) 12 byte data field */ +#define CAN_RXESC_RBDS_DATA16_Val _U_(0x2) /**< \brief (CAN_RXESC) 16 byte data field */ +#define CAN_RXESC_RBDS_DATA20_Val _U_(0x3) /**< \brief (CAN_RXESC) 20 byte data field */ +#define CAN_RXESC_RBDS_DATA24_Val _U_(0x4) /**< \brief (CAN_RXESC) 24 byte data field */ +#define CAN_RXESC_RBDS_DATA32_Val _U_(0x5) /**< \brief (CAN_RXESC) 32 byte data field */ +#define CAN_RXESC_RBDS_DATA48_Val _U_(0x6) /**< \brief (CAN_RXESC) 48 byte data field */ +#define CAN_RXESC_RBDS_DATA64_Val _U_(0x7) /**< \brief (CAN_RXESC) 64 byte data field */ +#define CAN_RXESC_RBDS_DATA8 (CAN_RXESC_RBDS_DATA8_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS_DATA12 (CAN_RXESC_RBDS_DATA12_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS_DATA16 (CAN_RXESC_RBDS_DATA16_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS_DATA20 (CAN_RXESC_RBDS_DATA20_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS_DATA24 (CAN_RXESC_RBDS_DATA24_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS_DATA32 (CAN_RXESC_RBDS_DATA32_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS_DATA48 (CAN_RXESC_RBDS_DATA48_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_RBDS_DATA64 (CAN_RXESC_RBDS_DATA64_Val << CAN_RXESC_RBDS_Pos) +#define CAN_RXESC_MASK _U_(0x00000777) /**< \brief (CAN_RXESC) MASK Register */ + +/* -------- CAN_TXBC : (CAN Offset: 0xC0) (R/W 32) Tx Buffer Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TBSA:16; /*!< bit: 0..15 Tx Buffers Start Address */ + uint32_t NDTB:6; /*!< bit: 16..21 Number of Dedicated Transmit Buffers */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t TFQS:6; /*!< bit: 24..29 Transmit FIFO/Queue Size */ + uint32_t TFQM:1; /*!< bit: 30 Tx FIFO/Queue Mode */ + uint32_t :1; /*!< bit: 31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBC_OFFSET 0xC0 /**< \brief (CAN_TXBC offset) Tx Buffer Configuration */ +#define CAN_TXBC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBC reset_value) Tx Buffer Configuration */ + +#define CAN_TXBC_TBSA_Pos 0 /**< \brief (CAN_TXBC) Tx Buffers Start Address */ +#define CAN_TXBC_TBSA_Msk (_U_(0xFFFF) << CAN_TXBC_TBSA_Pos) +#define CAN_TXBC_TBSA(value) (CAN_TXBC_TBSA_Msk & ((value) << CAN_TXBC_TBSA_Pos)) +#define CAN_TXBC_NDTB_Pos 16 /**< \brief (CAN_TXBC) Number of Dedicated Transmit Buffers */ +#define CAN_TXBC_NDTB_Msk (_U_(0x3F) << CAN_TXBC_NDTB_Pos) +#define CAN_TXBC_NDTB(value) (CAN_TXBC_NDTB_Msk & ((value) << CAN_TXBC_NDTB_Pos)) +#define CAN_TXBC_TFQS_Pos 24 /**< \brief (CAN_TXBC) Transmit FIFO/Queue Size */ +#define CAN_TXBC_TFQS_Msk (_U_(0x3F) << CAN_TXBC_TFQS_Pos) +#define CAN_TXBC_TFQS(value) (CAN_TXBC_TFQS_Msk & ((value) << CAN_TXBC_TFQS_Pos)) +#define CAN_TXBC_TFQM_Pos 30 /**< \brief (CAN_TXBC) Tx FIFO/Queue Mode */ +#define CAN_TXBC_TFQM (_U_(0x1) << CAN_TXBC_TFQM_Pos) +#define CAN_TXBC_MASK _U_(0x7F3FFFFF) /**< \brief (CAN_TXBC) MASK Register */ + +/* -------- CAN_TXFQS : (CAN Offset: 0xC4) (R/ 32) Tx FIFO / Queue Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TFFL:6; /*!< bit: 0.. 5 Tx FIFO Free Level */ + uint32_t :2; /*!< bit: 6.. 7 Reserved */ + uint32_t TFGI:5; /*!< bit: 8..12 Tx FIFO Get Index */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t TFQPI:5; /*!< bit: 16..20 Tx FIFO/Queue Put Index */ + uint32_t TFQF:1; /*!< bit: 21 Tx FIFO/Queue Full */ + uint32_t :10; /*!< bit: 22..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXFQS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXFQS_OFFSET 0xC4 /**< \brief (CAN_TXFQS offset) Tx FIFO / Queue Status */ +#define CAN_TXFQS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXFQS reset_value) Tx FIFO / Queue Status */ + +#define CAN_TXFQS_TFFL_Pos 0 /**< \brief (CAN_TXFQS) Tx FIFO Free Level */ +#define CAN_TXFQS_TFFL_Msk (_U_(0x3F) << CAN_TXFQS_TFFL_Pos) +#define CAN_TXFQS_TFFL(value) (CAN_TXFQS_TFFL_Msk & ((value) << CAN_TXFQS_TFFL_Pos)) +#define CAN_TXFQS_TFGI_Pos 8 /**< \brief (CAN_TXFQS) Tx FIFO Get Index */ +#define CAN_TXFQS_TFGI_Msk (_U_(0x1F) << CAN_TXFQS_TFGI_Pos) +#define CAN_TXFQS_TFGI(value) (CAN_TXFQS_TFGI_Msk & ((value) << CAN_TXFQS_TFGI_Pos)) +#define CAN_TXFQS_TFQPI_Pos 16 /**< \brief (CAN_TXFQS) Tx FIFO/Queue Put Index */ +#define CAN_TXFQS_TFQPI_Msk (_U_(0x1F) << CAN_TXFQS_TFQPI_Pos) +#define CAN_TXFQS_TFQPI(value) (CAN_TXFQS_TFQPI_Msk & ((value) << CAN_TXFQS_TFQPI_Pos)) +#define CAN_TXFQS_TFQF_Pos 21 /**< \brief (CAN_TXFQS) Tx FIFO/Queue Full */ +#define CAN_TXFQS_TFQF (_U_(0x1) << CAN_TXFQS_TFQF_Pos) +#define CAN_TXFQS_MASK _U_(0x003F1F3F) /**< \brief (CAN_TXFQS) MASK Register */ + +/* -------- CAN_TXESC : (CAN Offset: 0xC8) (R/W 32) Tx Buffer Element Size Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TBDS:3; /*!< bit: 0.. 2 Tx Buffer Data Field Size */ + uint32_t :29; /*!< bit: 3..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXESC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXESC_OFFSET 0xC8 /**< \brief (CAN_TXESC offset) Tx Buffer Element Size Configuration */ +#define CAN_TXESC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXESC reset_value) Tx Buffer Element Size Configuration */ + +#define CAN_TXESC_TBDS_Pos 0 /**< \brief (CAN_TXESC) Tx Buffer Data Field Size */ +#define CAN_TXESC_TBDS_Msk (_U_(0x7) << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS(value) (CAN_TXESC_TBDS_Msk & ((value) << CAN_TXESC_TBDS_Pos)) +#define CAN_TXESC_TBDS_DATA8_Val _U_(0x0) /**< \brief (CAN_TXESC) 8 byte data field */ +#define CAN_TXESC_TBDS_DATA12_Val _U_(0x1) /**< \brief (CAN_TXESC) 12 byte data field */ +#define CAN_TXESC_TBDS_DATA16_Val _U_(0x2) /**< \brief (CAN_TXESC) 16 byte data field */ +#define CAN_TXESC_TBDS_DATA20_Val _U_(0x3) /**< \brief (CAN_TXESC) 20 byte data field */ +#define CAN_TXESC_TBDS_DATA24_Val _U_(0x4) /**< \brief (CAN_TXESC) 24 byte data field */ +#define CAN_TXESC_TBDS_DATA32_Val _U_(0x5) /**< \brief (CAN_TXESC) 32 byte data field */ +#define CAN_TXESC_TBDS_DATA48_Val _U_(0x6) /**< \brief (CAN_TXESC) 48 byte data field */ +#define CAN_TXESC_TBDS_DATA64_Val _U_(0x7) /**< \brief (CAN_TXESC) 64 byte data field */ +#define CAN_TXESC_TBDS_DATA8 (CAN_TXESC_TBDS_DATA8_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS_DATA12 (CAN_TXESC_TBDS_DATA12_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS_DATA16 (CAN_TXESC_TBDS_DATA16_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS_DATA20 (CAN_TXESC_TBDS_DATA20_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS_DATA24 (CAN_TXESC_TBDS_DATA24_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS_DATA32 (CAN_TXESC_TBDS_DATA32_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS_DATA48 (CAN_TXESC_TBDS_DATA48_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_TBDS_DATA64 (CAN_TXESC_TBDS_DATA64_Val << CAN_TXESC_TBDS_Pos) +#define CAN_TXESC_MASK _U_(0x00000007) /**< \brief (CAN_TXESC) MASK Register */ + +/* -------- CAN_TXBRP : (CAN Offset: 0xCC) (R/ 32) Tx Buffer Request Pending -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TRP0:1; /*!< bit: 0 Transmission Request Pending 0 */ + uint32_t TRP1:1; /*!< bit: 1 Transmission Request Pending 1 */ + uint32_t TRP2:1; /*!< bit: 2 Transmission Request Pending 2 */ + uint32_t TRP3:1; /*!< bit: 3 Transmission Request Pending 3 */ + uint32_t TRP4:1; /*!< bit: 4 Transmission Request Pending 4 */ + uint32_t TRP5:1; /*!< bit: 5 Transmission Request Pending 5 */ + uint32_t TRP6:1; /*!< bit: 6 Transmission Request Pending 6 */ + uint32_t TRP7:1; /*!< bit: 7 Transmission Request Pending 7 */ + uint32_t TRP8:1; /*!< bit: 8 Transmission Request Pending 8 */ + uint32_t TRP9:1; /*!< bit: 9 Transmission Request Pending 9 */ + uint32_t TRP10:1; /*!< bit: 10 Transmission Request Pending 10 */ + uint32_t TRP11:1; /*!< bit: 11 Transmission Request Pending 11 */ + uint32_t TRP12:1; /*!< bit: 12 Transmission Request Pending 12 */ + uint32_t TRP13:1; /*!< bit: 13 Transmission Request Pending 13 */ + uint32_t TRP14:1; /*!< bit: 14 Transmission Request Pending 14 */ + uint32_t TRP15:1; /*!< bit: 15 Transmission Request Pending 15 */ + uint32_t TRP16:1; /*!< bit: 16 Transmission Request Pending 16 */ + uint32_t TRP17:1; /*!< bit: 17 Transmission Request Pending 17 */ + uint32_t TRP18:1; /*!< bit: 18 Transmission Request Pending 18 */ + uint32_t TRP19:1; /*!< bit: 19 Transmission Request Pending 19 */ + uint32_t TRP20:1; /*!< bit: 20 Transmission Request Pending 20 */ + uint32_t TRP21:1; /*!< bit: 21 Transmission Request Pending 21 */ + uint32_t TRP22:1; /*!< bit: 22 Transmission Request Pending 22 */ + uint32_t TRP23:1; /*!< bit: 23 Transmission Request Pending 23 */ + uint32_t TRP24:1; /*!< bit: 24 Transmission Request Pending 24 */ + uint32_t TRP25:1; /*!< bit: 25 Transmission Request Pending 25 */ + uint32_t TRP26:1; /*!< bit: 26 Transmission Request Pending 26 */ + uint32_t TRP27:1; /*!< bit: 27 Transmission Request Pending 27 */ + uint32_t TRP28:1; /*!< bit: 28 Transmission Request Pending 28 */ + uint32_t TRP29:1; /*!< bit: 29 Transmission Request Pending 29 */ + uint32_t TRP30:1; /*!< bit: 30 Transmission Request Pending 30 */ + uint32_t TRP31:1; /*!< bit: 31 Transmission Request Pending 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBRP_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBRP_OFFSET 0xCC /**< \brief (CAN_TXBRP offset) Tx Buffer Request Pending */ +#define CAN_TXBRP_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBRP reset_value) Tx Buffer Request Pending */ + +#define CAN_TXBRP_TRP0_Pos 0 /**< \brief (CAN_TXBRP) Transmission Request Pending 0 */ +#define CAN_TXBRP_TRP0 (_U_(0x1) << CAN_TXBRP_TRP0_Pos) +#define CAN_TXBRP_TRP1_Pos 1 /**< \brief (CAN_TXBRP) Transmission Request Pending 1 */ +#define CAN_TXBRP_TRP1 (_U_(0x1) << CAN_TXBRP_TRP1_Pos) +#define CAN_TXBRP_TRP2_Pos 2 /**< \brief (CAN_TXBRP) Transmission Request Pending 2 */ +#define CAN_TXBRP_TRP2 (_U_(0x1) << CAN_TXBRP_TRP2_Pos) +#define CAN_TXBRP_TRP3_Pos 3 /**< \brief (CAN_TXBRP) Transmission Request Pending 3 */ +#define CAN_TXBRP_TRP3 (_U_(0x1) << CAN_TXBRP_TRP3_Pos) +#define CAN_TXBRP_TRP4_Pos 4 /**< \brief (CAN_TXBRP) Transmission Request Pending 4 */ +#define CAN_TXBRP_TRP4 (_U_(0x1) << CAN_TXBRP_TRP4_Pos) +#define CAN_TXBRP_TRP5_Pos 5 /**< \brief (CAN_TXBRP) Transmission Request Pending 5 */ +#define CAN_TXBRP_TRP5 (_U_(0x1) << CAN_TXBRP_TRP5_Pos) +#define CAN_TXBRP_TRP6_Pos 6 /**< \brief (CAN_TXBRP) Transmission Request Pending 6 */ +#define CAN_TXBRP_TRP6 (_U_(0x1) << CAN_TXBRP_TRP6_Pos) +#define CAN_TXBRP_TRP7_Pos 7 /**< \brief (CAN_TXBRP) Transmission Request Pending 7 */ +#define CAN_TXBRP_TRP7 (_U_(0x1) << CAN_TXBRP_TRP7_Pos) +#define CAN_TXBRP_TRP8_Pos 8 /**< \brief (CAN_TXBRP) Transmission Request Pending 8 */ +#define CAN_TXBRP_TRP8 (_U_(0x1) << CAN_TXBRP_TRP8_Pos) +#define CAN_TXBRP_TRP9_Pos 9 /**< \brief (CAN_TXBRP) Transmission Request Pending 9 */ +#define CAN_TXBRP_TRP9 (_U_(0x1) << CAN_TXBRP_TRP9_Pos) +#define CAN_TXBRP_TRP10_Pos 10 /**< \brief (CAN_TXBRP) Transmission Request Pending 10 */ +#define CAN_TXBRP_TRP10 (_U_(0x1) << CAN_TXBRP_TRP10_Pos) +#define CAN_TXBRP_TRP11_Pos 11 /**< \brief (CAN_TXBRP) Transmission Request Pending 11 */ +#define CAN_TXBRP_TRP11 (_U_(0x1) << CAN_TXBRP_TRP11_Pos) +#define CAN_TXBRP_TRP12_Pos 12 /**< \brief (CAN_TXBRP) Transmission Request Pending 12 */ +#define CAN_TXBRP_TRP12 (_U_(0x1) << CAN_TXBRP_TRP12_Pos) +#define CAN_TXBRP_TRP13_Pos 13 /**< \brief (CAN_TXBRP) Transmission Request Pending 13 */ +#define CAN_TXBRP_TRP13 (_U_(0x1) << CAN_TXBRP_TRP13_Pos) +#define CAN_TXBRP_TRP14_Pos 14 /**< \brief (CAN_TXBRP) Transmission Request Pending 14 */ +#define CAN_TXBRP_TRP14 (_U_(0x1) << CAN_TXBRP_TRP14_Pos) +#define CAN_TXBRP_TRP15_Pos 15 /**< \brief (CAN_TXBRP) Transmission Request Pending 15 */ +#define CAN_TXBRP_TRP15 (_U_(0x1) << CAN_TXBRP_TRP15_Pos) +#define CAN_TXBRP_TRP16_Pos 16 /**< \brief (CAN_TXBRP) Transmission Request Pending 16 */ +#define CAN_TXBRP_TRP16 (_U_(0x1) << CAN_TXBRP_TRP16_Pos) +#define CAN_TXBRP_TRP17_Pos 17 /**< \brief (CAN_TXBRP) Transmission Request Pending 17 */ +#define CAN_TXBRP_TRP17 (_U_(0x1) << CAN_TXBRP_TRP17_Pos) +#define CAN_TXBRP_TRP18_Pos 18 /**< \brief (CAN_TXBRP) Transmission Request Pending 18 */ +#define CAN_TXBRP_TRP18 (_U_(0x1) << CAN_TXBRP_TRP18_Pos) +#define CAN_TXBRP_TRP19_Pos 19 /**< \brief (CAN_TXBRP) Transmission Request Pending 19 */ +#define CAN_TXBRP_TRP19 (_U_(0x1) << CAN_TXBRP_TRP19_Pos) +#define CAN_TXBRP_TRP20_Pos 20 /**< \brief (CAN_TXBRP) Transmission Request Pending 20 */ +#define CAN_TXBRP_TRP20 (_U_(0x1) << CAN_TXBRP_TRP20_Pos) +#define CAN_TXBRP_TRP21_Pos 21 /**< \brief (CAN_TXBRP) Transmission Request Pending 21 */ +#define CAN_TXBRP_TRP21 (_U_(0x1) << CAN_TXBRP_TRP21_Pos) +#define CAN_TXBRP_TRP22_Pos 22 /**< \brief (CAN_TXBRP) Transmission Request Pending 22 */ +#define CAN_TXBRP_TRP22 (_U_(0x1) << CAN_TXBRP_TRP22_Pos) +#define CAN_TXBRP_TRP23_Pos 23 /**< \brief (CAN_TXBRP) Transmission Request Pending 23 */ +#define CAN_TXBRP_TRP23 (_U_(0x1) << CAN_TXBRP_TRP23_Pos) +#define CAN_TXBRP_TRP24_Pos 24 /**< \brief (CAN_TXBRP) Transmission Request Pending 24 */ +#define CAN_TXBRP_TRP24 (_U_(0x1) << CAN_TXBRP_TRP24_Pos) +#define CAN_TXBRP_TRP25_Pos 25 /**< \brief (CAN_TXBRP) Transmission Request Pending 25 */ +#define CAN_TXBRP_TRP25 (_U_(0x1) << CAN_TXBRP_TRP25_Pos) +#define CAN_TXBRP_TRP26_Pos 26 /**< \brief (CAN_TXBRP) Transmission Request Pending 26 */ +#define CAN_TXBRP_TRP26 (_U_(0x1) << CAN_TXBRP_TRP26_Pos) +#define CAN_TXBRP_TRP27_Pos 27 /**< \brief (CAN_TXBRP) Transmission Request Pending 27 */ +#define CAN_TXBRP_TRP27 (_U_(0x1) << CAN_TXBRP_TRP27_Pos) +#define CAN_TXBRP_TRP28_Pos 28 /**< \brief (CAN_TXBRP) Transmission Request Pending 28 */ +#define CAN_TXBRP_TRP28 (_U_(0x1) << CAN_TXBRP_TRP28_Pos) +#define CAN_TXBRP_TRP29_Pos 29 /**< \brief (CAN_TXBRP) Transmission Request Pending 29 */ +#define CAN_TXBRP_TRP29 (_U_(0x1) << CAN_TXBRP_TRP29_Pos) +#define CAN_TXBRP_TRP30_Pos 30 /**< \brief (CAN_TXBRP) Transmission Request Pending 30 */ +#define CAN_TXBRP_TRP30 (_U_(0x1) << CAN_TXBRP_TRP30_Pos) +#define CAN_TXBRP_TRP31_Pos 31 /**< \brief (CAN_TXBRP) Transmission Request Pending 31 */ +#define CAN_TXBRP_TRP31 (_U_(0x1) << CAN_TXBRP_TRP31_Pos) +#define CAN_TXBRP_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBRP) MASK Register */ + +/* -------- CAN_TXBAR : (CAN Offset: 0xD0) (R/W 32) Tx Buffer Add Request -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t AR0:1; /*!< bit: 0 Add Request 0 */ + uint32_t AR1:1; /*!< bit: 1 Add Request 1 */ + uint32_t AR2:1; /*!< bit: 2 Add Request 2 */ + uint32_t AR3:1; /*!< bit: 3 Add Request 3 */ + uint32_t AR4:1; /*!< bit: 4 Add Request 4 */ + uint32_t AR5:1; /*!< bit: 5 Add Request 5 */ + uint32_t AR6:1; /*!< bit: 6 Add Request 6 */ + uint32_t AR7:1; /*!< bit: 7 Add Request 7 */ + uint32_t AR8:1; /*!< bit: 8 Add Request 8 */ + uint32_t AR9:1; /*!< bit: 9 Add Request 9 */ + uint32_t AR10:1; /*!< bit: 10 Add Request 10 */ + uint32_t AR11:1; /*!< bit: 11 Add Request 11 */ + uint32_t AR12:1; /*!< bit: 12 Add Request 12 */ + uint32_t AR13:1; /*!< bit: 13 Add Request 13 */ + uint32_t AR14:1; /*!< bit: 14 Add Request 14 */ + uint32_t AR15:1; /*!< bit: 15 Add Request 15 */ + uint32_t AR16:1; /*!< bit: 16 Add Request 16 */ + uint32_t AR17:1; /*!< bit: 17 Add Request 17 */ + uint32_t AR18:1; /*!< bit: 18 Add Request 18 */ + uint32_t AR19:1; /*!< bit: 19 Add Request 19 */ + uint32_t AR20:1; /*!< bit: 20 Add Request 20 */ + uint32_t AR21:1; /*!< bit: 21 Add Request 21 */ + uint32_t AR22:1; /*!< bit: 22 Add Request 22 */ + uint32_t AR23:1; /*!< bit: 23 Add Request 23 */ + uint32_t AR24:1; /*!< bit: 24 Add Request 24 */ + uint32_t AR25:1; /*!< bit: 25 Add Request 25 */ + uint32_t AR26:1; /*!< bit: 26 Add Request 26 */ + uint32_t AR27:1; /*!< bit: 27 Add Request 27 */ + uint32_t AR28:1; /*!< bit: 28 Add Request 28 */ + uint32_t AR29:1; /*!< bit: 29 Add Request 29 */ + uint32_t AR30:1; /*!< bit: 30 Add Request 30 */ + uint32_t AR31:1; /*!< bit: 31 Add Request 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBAR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBAR_OFFSET 0xD0 /**< \brief (CAN_TXBAR offset) Tx Buffer Add Request */ +#define CAN_TXBAR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBAR reset_value) Tx Buffer Add Request */ + +#define CAN_TXBAR_AR0_Pos 0 /**< \brief (CAN_TXBAR) Add Request 0 */ +#define CAN_TXBAR_AR0 (_U_(0x1) << CAN_TXBAR_AR0_Pos) +#define CAN_TXBAR_AR1_Pos 1 /**< \brief (CAN_TXBAR) Add Request 1 */ +#define CAN_TXBAR_AR1 (_U_(0x1) << CAN_TXBAR_AR1_Pos) +#define CAN_TXBAR_AR2_Pos 2 /**< \brief (CAN_TXBAR) Add Request 2 */ +#define CAN_TXBAR_AR2 (_U_(0x1) << CAN_TXBAR_AR2_Pos) +#define CAN_TXBAR_AR3_Pos 3 /**< \brief (CAN_TXBAR) Add Request 3 */ +#define CAN_TXBAR_AR3 (_U_(0x1) << CAN_TXBAR_AR3_Pos) +#define CAN_TXBAR_AR4_Pos 4 /**< \brief (CAN_TXBAR) Add Request 4 */ +#define CAN_TXBAR_AR4 (_U_(0x1) << CAN_TXBAR_AR4_Pos) +#define CAN_TXBAR_AR5_Pos 5 /**< \brief (CAN_TXBAR) Add Request 5 */ +#define CAN_TXBAR_AR5 (_U_(0x1) << CAN_TXBAR_AR5_Pos) +#define CAN_TXBAR_AR6_Pos 6 /**< \brief (CAN_TXBAR) Add Request 6 */ +#define CAN_TXBAR_AR6 (_U_(0x1) << CAN_TXBAR_AR6_Pos) +#define CAN_TXBAR_AR7_Pos 7 /**< \brief (CAN_TXBAR) Add Request 7 */ +#define CAN_TXBAR_AR7 (_U_(0x1) << CAN_TXBAR_AR7_Pos) +#define CAN_TXBAR_AR8_Pos 8 /**< \brief (CAN_TXBAR) Add Request 8 */ +#define CAN_TXBAR_AR8 (_U_(0x1) << CAN_TXBAR_AR8_Pos) +#define CAN_TXBAR_AR9_Pos 9 /**< \brief (CAN_TXBAR) Add Request 9 */ +#define CAN_TXBAR_AR9 (_U_(0x1) << CAN_TXBAR_AR9_Pos) +#define CAN_TXBAR_AR10_Pos 10 /**< \brief (CAN_TXBAR) Add Request 10 */ +#define CAN_TXBAR_AR10 (_U_(0x1) << CAN_TXBAR_AR10_Pos) +#define CAN_TXBAR_AR11_Pos 11 /**< \brief (CAN_TXBAR) Add Request 11 */ +#define CAN_TXBAR_AR11 (_U_(0x1) << CAN_TXBAR_AR11_Pos) +#define CAN_TXBAR_AR12_Pos 12 /**< \brief (CAN_TXBAR) Add Request 12 */ +#define CAN_TXBAR_AR12 (_U_(0x1) << CAN_TXBAR_AR12_Pos) +#define CAN_TXBAR_AR13_Pos 13 /**< \brief (CAN_TXBAR) Add Request 13 */ +#define CAN_TXBAR_AR13 (_U_(0x1) << CAN_TXBAR_AR13_Pos) +#define CAN_TXBAR_AR14_Pos 14 /**< \brief (CAN_TXBAR) Add Request 14 */ +#define CAN_TXBAR_AR14 (_U_(0x1) << CAN_TXBAR_AR14_Pos) +#define CAN_TXBAR_AR15_Pos 15 /**< \brief (CAN_TXBAR) Add Request 15 */ +#define CAN_TXBAR_AR15 (_U_(0x1) << CAN_TXBAR_AR15_Pos) +#define CAN_TXBAR_AR16_Pos 16 /**< \brief (CAN_TXBAR) Add Request 16 */ +#define CAN_TXBAR_AR16 (_U_(0x1) << CAN_TXBAR_AR16_Pos) +#define CAN_TXBAR_AR17_Pos 17 /**< \brief (CAN_TXBAR) Add Request 17 */ +#define CAN_TXBAR_AR17 (_U_(0x1) << CAN_TXBAR_AR17_Pos) +#define CAN_TXBAR_AR18_Pos 18 /**< \brief (CAN_TXBAR) Add Request 18 */ +#define CAN_TXBAR_AR18 (_U_(0x1) << CAN_TXBAR_AR18_Pos) +#define CAN_TXBAR_AR19_Pos 19 /**< \brief (CAN_TXBAR) Add Request 19 */ +#define CAN_TXBAR_AR19 (_U_(0x1) << CAN_TXBAR_AR19_Pos) +#define CAN_TXBAR_AR20_Pos 20 /**< \brief (CAN_TXBAR) Add Request 20 */ +#define CAN_TXBAR_AR20 (_U_(0x1) << CAN_TXBAR_AR20_Pos) +#define CAN_TXBAR_AR21_Pos 21 /**< \brief (CAN_TXBAR) Add Request 21 */ +#define CAN_TXBAR_AR21 (_U_(0x1) << CAN_TXBAR_AR21_Pos) +#define CAN_TXBAR_AR22_Pos 22 /**< \brief (CAN_TXBAR) Add Request 22 */ +#define CAN_TXBAR_AR22 (_U_(0x1) << CAN_TXBAR_AR22_Pos) +#define CAN_TXBAR_AR23_Pos 23 /**< \brief (CAN_TXBAR) Add Request 23 */ +#define CAN_TXBAR_AR23 (_U_(0x1) << CAN_TXBAR_AR23_Pos) +#define CAN_TXBAR_AR24_Pos 24 /**< \brief (CAN_TXBAR) Add Request 24 */ +#define CAN_TXBAR_AR24 (_U_(0x1) << CAN_TXBAR_AR24_Pos) +#define CAN_TXBAR_AR25_Pos 25 /**< \brief (CAN_TXBAR) Add Request 25 */ +#define CAN_TXBAR_AR25 (_U_(0x1) << CAN_TXBAR_AR25_Pos) +#define CAN_TXBAR_AR26_Pos 26 /**< \brief (CAN_TXBAR) Add Request 26 */ +#define CAN_TXBAR_AR26 (_U_(0x1) << CAN_TXBAR_AR26_Pos) +#define CAN_TXBAR_AR27_Pos 27 /**< \brief (CAN_TXBAR) Add Request 27 */ +#define CAN_TXBAR_AR27 (_U_(0x1) << CAN_TXBAR_AR27_Pos) +#define CAN_TXBAR_AR28_Pos 28 /**< \brief (CAN_TXBAR) Add Request 28 */ +#define CAN_TXBAR_AR28 (_U_(0x1) << CAN_TXBAR_AR28_Pos) +#define CAN_TXBAR_AR29_Pos 29 /**< \brief (CAN_TXBAR) Add Request 29 */ +#define CAN_TXBAR_AR29 (_U_(0x1) << CAN_TXBAR_AR29_Pos) +#define CAN_TXBAR_AR30_Pos 30 /**< \brief (CAN_TXBAR) Add Request 30 */ +#define CAN_TXBAR_AR30 (_U_(0x1) << CAN_TXBAR_AR30_Pos) +#define CAN_TXBAR_AR31_Pos 31 /**< \brief (CAN_TXBAR) Add Request 31 */ +#define CAN_TXBAR_AR31 (_U_(0x1) << CAN_TXBAR_AR31_Pos) +#define CAN_TXBAR_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBAR) MASK Register */ + +/* -------- CAN_TXBCR : (CAN Offset: 0xD4) (R/W 32) Tx Buffer Cancellation Request -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CR0:1; /*!< bit: 0 Cancellation Request 0 */ + uint32_t CR1:1; /*!< bit: 1 Cancellation Request 1 */ + uint32_t CR2:1; /*!< bit: 2 Cancellation Request 2 */ + uint32_t CR3:1; /*!< bit: 3 Cancellation Request 3 */ + uint32_t CR4:1; /*!< bit: 4 Cancellation Request 4 */ + uint32_t CR5:1; /*!< bit: 5 Cancellation Request 5 */ + uint32_t CR6:1; /*!< bit: 6 Cancellation Request 6 */ + uint32_t CR7:1; /*!< bit: 7 Cancellation Request 7 */ + uint32_t CR8:1; /*!< bit: 8 Cancellation Request 8 */ + uint32_t CR9:1; /*!< bit: 9 Cancellation Request 9 */ + uint32_t CR10:1; /*!< bit: 10 Cancellation Request 10 */ + uint32_t CR11:1; /*!< bit: 11 Cancellation Request 11 */ + uint32_t CR12:1; /*!< bit: 12 Cancellation Request 12 */ + uint32_t CR13:1; /*!< bit: 13 Cancellation Request 13 */ + uint32_t CR14:1; /*!< bit: 14 Cancellation Request 14 */ + uint32_t CR15:1; /*!< bit: 15 Cancellation Request 15 */ + uint32_t CR16:1; /*!< bit: 16 Cancellation Request 16 */ + uint32_t CR17:1; /*!< bit: 17 Cancellation Request 17 */ + uint32_t CR18:1; /*!< bit: 18 Cancellation Request 18 */ + uint32_t CR19:1; /*!< bit: 19 Cancellation Request 19 */ + uint32_t CR20:1; /*!< bit: 20 Cancellation Request 20 */ + uint32_t CR21:1; /*!< bit: 21 Cancellation Request 21 */ + uint32_t CR22:1; /*!< bit: 22 Cancellation Request 22 */ + uint32_t CR23:1; /*!< bit: 23 Cancellation Request 23 */ + uint32_t CR24:1; /*!< bit: 24 Cancellation Request 24 */ + uint32_t CR25:1; /*!< bit: 25 Cancellation Request 25 */ + uint32_t CR26:1; /*!< bit: 26 Cancellation Request 26 */ + uint32_t CR27:1; /*!< bit: 27 Cancellation Request 27 */ + uint32_t CR28:1; /*!< bit: 28 Cancellation Request 28 */ + uint32_t CR29:1; /*!< bit: 29 Cancellation Request 29 */ + uint32_t CR30:1; /*!< bit: 30 Cancellation Request 30 */ + uint32_t CR31:1; /*!< bit: 31 Cancellation Request 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBCR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBCR_OFFSET 0xD4 /**< \brief (CAN_TXBCR offset) Tx Buffer Cancellation Request */ +#define CAN_TXBCR_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBCR reset_value) Tx Buffer Cancellation Request */ + +#define CAN_TXBCR_CR0_Pos 0 /**< \brief (CAN_TXBCR) Cancellation Request 0 */ +#define CAN_TXBCR_CR0 (_U_(0x1) << CAN_TXBCR_CR0_Pos) +#define CAN_TXBCR_CR1_Pos 1 /**< \brief (CAN_TXBCR) Cancellation Request 1 */ +#define CAN_TXBCR_CR1 (_U_(0x1) << CAN_TXBCR_CR1_Pos) +#define CAN_TXBCR_CR2_Pos 2 /**< \brief (CAN_TXBCR) Cancellation Request 2 */ +#define CAN_TXBCR_CR2 (_U_(0x1) << CAN_TXBCR_CR2_Pos) +#define CAN_TXBCR_CR3_Pos 3 /**< \brief (CAN_TXBCR) Cancellation Request 3 */ +#define CAN_TXBCR_CR3 (_U_(0x1) << CAN_TXBCR_CR3_Pos) +#define CAN_TXBCR_CR4_Pos 4 /**< \brief (CAN_TXBCR) Cancellation Request 4 */ +#define CAN_TXBCR_CR4 (_U_(0x1) << CAN_TXBCR_CR4_Pos) +#define CAN_TXBCR_CR5_Pos 5 /**< \brief (CAN_TXBCR) Cancellation Request 5 */ +#define CAN_TXBCR_CR5 (_U_(0x1) << CAN_TXBCR_CR5_Pos) +#define CAN_TXBCR_CR6_Pos 6 /**< \brief (CAN_TXBCR) Cancellation Request 6 */ +#define CAN_TXBCR_CR6 (_U_(0x1) << CAN_TXBCR_CR6_Pos) +#define CAN_TXBCR_CR7_Pos 7 /**< \brief (CAN_TXBCR) Cancellation Request 7 */ +#define CAN_TXBCR_CR7 (_U_(0x1) << CAN_TXBCR_CR7_Pos) +#define CAN_TXBCR_CR8_Pos 8 /**< \brief (CAN_TXBCR) Cancellation Request 8 */ +#define CAN_TXBCR_CR8 (_U_(0x1) << CAN_TXBCR_CR8_Pos) +#define CAN_TXBCR_CR9_Pos 9 /**< \brief (CAN_TXBCR) Cancellation Request 9 */ +#define CAN_TXBCR_CR9 (_U_(0x1) << CAN_TXBCR_CR9_Pos) +#define CAN_TXBCR_CR10_Pos 10 /**< \brief (CAN_TXBCR) Cancellation Request 10 */ +#define CAN_TXBCR_CR10 (_U_(0x1) << CAN_TXBCR_CR10_Pos) +#define CAN_TXBCR_CR11_Pos 11 /**< \brief (CAN_TXBCR) Cancellation Request 11 */ +#define CAN_TXBCR_CR11 (_U_(0x1) << CAN_TXBCR_CR11_Pos) +#define CAN_TXBCR_CR12_Pos 12 /**< \brief (CAN_TXBCR) Cancellation Request 12 */ +#define CAN_TXBCR_CR12 (_U_(0x1) << CAN_TXBCR_CR12_Pos) +#define CAN_TXBCR_CR13_Pos 13 /**< \brief (CAN_TXBCR) Cancellation Request 13 */ +#define CAN_TXBCR_CR13 (_U_(0x1) << CAN_TXBCR_CR13_Pos) +#define CAN_TXBCR_CR14_Pos 14 /**< \brief (CAN_TXBCR) Cancellation Request 14 */ +#define CAN_TXBCR_CR14 (_U_(0x1) << CAN_TXBCR_CR14_Pos) +#define CAN_TXBCR_CR15_Pos 15 /**< \brief (CAN_TXBCR) Cancellation Request 15 */ +#define CAN_TXBCR_CR15 (_U_(0x1) << CAN_TXBCR_CR15_Pos) +#define CAN_TXBCR_CR16_Pos 16 /**< \brief (CAN_TXBCR) Cancellation Request 16 */ +#define CAN_TXBCR_CR16 (_U_(0x1) << CAN_TXBCR_CR16_Pos) +#define CAN_TXBCR_CR17_Pos 17 /**< \brief (CAN_TXBCR) Cancellation Request 17 */ +#define CAN_TXBCR_CR17 (_U_(0x1) << CAN_TXBCR_CR17_Pos) +#define CAN_TXBCR_CR18_Pos 18 /**< \brief (CAN_TXBCR) Cancellation Request 18 */ +#define CAN_TXBCR_CR18 (_U_(0x1) << CAN_TXBCR_CR18_Pos) +#define CAN_TXBCR_CR19_Pos 19 /**< \brief (CAN_TXBCR) Cancellation Request 19 */ +#define CAN_TXBCR_CR19 (_U_(0x1) << CAN_TXBCR_CR19_Pos) +#define CAN_TXBCR_CR20_Pos 20 /**< \brief (CAN_TXBCR) Cancellation Request 20 */ +#define CAN_TXBCR_CR20 (_U_(0x1) << CAN_TXBCR_CR20_Pos) +#define CAN_TXBCR_CR21_Pos 21 /**< \brief (CAN_TXBCR) Cancellation Request 21 */ +#define CAN_TXBCR_CR21 (_U_(0x1) << CAN_TXBCR_CR21_Pos) +#define CAN_TXBCR_CR22_Pos 22 /**< \brief (CAN_TXBCR) Cancellation Request 22 */ +#define CAN_TXBCR_CR22 (_U_(0x1) << CAN_TXBCR_CR22_Pos) +#define CAN_TXBCR_CR23_Pos 23 /**< \brief (CAN_TXBCR) Cancellation Request 23 */ +#define CAN_TXBCR_CR23 (_U_(0x1) << CAN_TXBCR_CR23_Pos) +#define CAN_TXBCR_CR24_Pos 24 /**< \brief (CAN_TXBCR) Cancellation Request 24 */ +#define CAN_TXBCR_CR24 (_U_(0x1) << CAN_TXBCR_CR24_Pos) +#define CAN_TXBCR_CR25_Pos 25 /**< \brief (CAN_TXBCR) Cancellation Request 25 */ +#define CAN_TXBCR_CR25 (_U_(0x1) << CAN_TXBCR_CR25_Pos) +#define CAN_TXBCR_CR26_Pos 26 /**< \brief (CAN_TXBCR) Cancellation Request 26 */ +#define CAN_TXBCR_CR26 (_U_(0x1) << CAN_TXBCR_CR26_Pos) +#define CAN_TXBCR_CR27_Pos 27 /**< \brief (CAN_TXBCR) Cancellation Request 27 */ +#define CAN_TXBCR_CR27 (_U_(0x1) << CAN_TXBCR_CR27_Pos) +#define CAN_TXBCR_CR28_Pos 28 /**< \brief (CAN_TXBCR) Cancellation Request 28 */ +#define CAN_TXBCR_CR28 (_U_(0x1) << CAN_TXBCR_CR28_Pos) +#define CAN_TXBCR_CR29_Pos 29 /**< \brief (CAN_TXBCR) Cancellation Request 29 */ +#define CAN_TXBCR_CR29 (_U_(0x1) << CAN_TXBCR_CR29_Pos) +#define CAN_TXBCR_CR30_Pos 30 /**< \brief (CAN_TXBCR) Cancellation Request 30 */ +#define CAN_TXBCR_CR30 (_U_(0x1) << CAN_TXBCR_CR30_Pos) +#define CAN_TXBCR_CR31_Pos 31 /**< \brief (CAN_TXBCR) Cancellation Request 31 */ +#define CAN_TXBCR_CR31 (_U_(0x1) << CAN_TXBCR_CR31_Pos) +#define CAN_TXBCR_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBCR) MASK Register */ + +/* -------- CAN_TXBTO : (CAN Offset: 0xD8) (R/ 32) Tx Buffer Transmission Occurred -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TO0:1; /*!< bit: 0 Transmission Occurred 0 */ + uint32_t TO1:1; /*!< bit: 1 Transmission Occurred 1 */ + uint32_t TO2:1; /*!< bit: 2 Transmission Occurred 2 */ + uint32_t TO3:1; /*!< bit: 3 Transmission Occurred 3 */ + uint32_t TO4:1; /*!< bit: 4 Transmission Occurred 4 */ + uint32_t TO5:1; /*!< bit: 5 Transmission Occurred 5 */ + uint32_t TO6:1; /*!< bit: 6 Transmission Occurred 6 */ + uint32_t TO7:1; /*!< bit: 7 Transmission Occurred 7 */ + uint32_t TO8:1; /*!< bit: 8 Transmission Occurred 8 */ + uint32_t TO9:1; /*!< bit: 9 Transmission Occurred 9 */ + uint32_t TO10:1; /*!< bit: 10 Transmission Occurred 10 */ + uint32_t TO11:1; /*!< bit: 11 Transmission Occurred 11 */ + uint32_t TO12:1; /*!< bit: 12 Transmission Occurred 12 */ + uint32_t TO13:1; /*!< bit: 13 Transmission Occurred 13 */ + uint32_t TO14:1; /*!< bit: 14 Transmission Occurred 14 */ + uint32_t TO15:1; /*!< bit: 15 Transmission Occurred 15 */ + uint32_t TO16:1; /*!< bit: 16 Transmission Occurred 16 */ + uint32_t TO17:1; /*!< bit: 17 Transmission Occurred 17 */ + uint32_t TO18:1; /*!< bit: 18 Transmission Occurred 18 */ + uint32_t TO19:1; /*!< bit: 19 Transmission Occurred 19 */ + uint32_t TO20:1; /*!< bit: 20 Transmission Occurred 20 */ + uint32_t TO21:1; /*!< bit: 21 Transmission Occurred 21 */ + uint32_t TO22:1; /*!< bit: 22 Transmission Occurred 22 */ + uint32_t TO23:1; /*!< bit: 23 Transmission Occurred 23 */ + uint32_t TO24:1; /*!< bit: 24 Transmission Occurred 24 */ + uint32_t TO25:1; /*!< bit: 25 Transmission Occurred 25 */ + uint32_t TO26:1; /*!< bit: 26 Transmission Occurred 26 */ + uint32_t TO27:1; /*!< bit: 27 Transmission Occurred 27 */ + uint32_t TO28:1; /*!< bit: 28 Transmission Occurred 28 */ + uint32_t TO29:1; /*!< bit: 29 Transmission Occurred 29 */ + uint32_t TO30:1; /*!< bit: 30 Transmission Occurred 30 */ + uint32_t TO31:1; /*!< bit: 31 Transmission Occurred 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBTO_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBTO_OFFSET 0xD8 /**< \brief (CAN_TXBTO offset) Tx Buffer Transmission Occurred */ +#define CAN_TXBTO_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBTO reset_value) Tx Buffer Transmission Occurred */ + +#define CAN_TXBTO_TO0_Pos 0 /**< \brief (CAN_TXBTO) Transmission Occurred 0 */ +#define CAN_TXBTO_TO0 (_U_(0x1) << CAN_TXBTO_TO0_Pos) +#define CAN_TXBTO_TO1_Pos 1 /**< \brief (CAN_TXBTO) Transmission Occurred 1 */ +#define CAN_TXBTO_TO1 (_U_(0x1) << CAN_TXBTO_TO1_Pos) +#define CAN_TXBTO_TO2_Pos 2 /**< \brief (CAN_TXBTO) Transmission Occurred 2 */ +#define CAN_TXBTO_TO2 (_U_(0x1) << CAN_TXBTO_TO2_Pos) +#define CAN_TXBTO_TO3_Pos 3 /**< \brief (CAN_TXBTO) Transmission Occurred 3 */ +#define CAN_TXBTO_TO3 (_U_(0x1) << CAN_TXBTO_TO3_Pos) +#define CAN_TXBTO_TO4_Pos 4 /**< \brief (CAN_TXBTO) Transmission Occurred 4 */ +#define CAN_TXBTO_TO4 (_U_(0x1) << CAN_TXBTO_TO4_Pos) +#define CAN_TXBTO_TO5_Pos 5 /**< \brief (CAN_TXBTO) Transmission Occurred 5 */ +#define CAN_TXBTO_TO5 (_U_(0x1) << CAN_TXBTO_TO5_Pos) +#define CAN_TXBTO_TO6_Pos 6 /**< \brief (CAN_TXBTO) Transmission Occurred 6 */ +#define CAN_TXBTO_TO6 (_U_(0x1) << CAN_TXBTO_TO6_Pos) +#define CAN_TXBTO_TO7_Pos 7 /**< \brief (CAN_TXBTO) Transmission Occurred 7 */ +#define CAN_TXBTO_TO7 (_U_(0x1) << CAN_TXBTO_TO7_Pos) +#define CAN_TXBTO_TO8_Pos 8 /**< \brief (CAN_TXBTO) Transmission Occurred 8 */ +#define CAN_TXBTO_TO8 (_U_(0x1) << CAN_TXBTO_TO8_Pos) +#define CAN_TXBTO_TO9_Pos 9 /**< \brief (CAN_TXBTO) Transmission Occurred 9 */ +#define CAN_TXBTO_TO9 (_U_(0x1) << CAN_TXBTO_TO9_Pos) +#define CAN_TXBTO_TO10_Pos 10 /**< \brief (CAN_TXBTO) Transmission Occurred 10 */ +#define CAN_TXBTO_TO10 (_U_(0x1) << CAN_TXBTO_TO10_Pos) +#define CAN_TXBTO_TO11_Pos 11 /**< \brief (CAN_TXBTO) Transmission Occurred 11 */ +#define CAN_TXBTO_TO11 (_U_(0x1) << CAN_TXBTO_TO11_Pos) +#define CAN_TXBTO_TO12_Pos 12 /**< \brief (CAN_TXBTO) Transmission Occurred 12 */ +#define CAN_TXBTO_TO12 (_U_(0x1) << CAN_TXBTO_TO12_Pos) +#define CAN_TXBTO_TO13_Pos 13 /**< \brief (CAN_TXBTO) Transmission Occurred 13 */ +#define CAN_TXBTO_TO13 (_U_(0x1) << CAN_TXBTO_TO13_Pos) +#define CAN_TXBTO_TO14_Pos 14 /**< \brief (CAN_TXBTO) Transmission Occurred 14 */ +#define CAN_TXBTO_TO14 (_U_(0x1) << CAN_TXBTO_TO14_Pos) +#define CAN_TXBTO_TO15_Pos 15 /**< \brief (CAN_TXBTO) Transmission Occurred 15 */ +#define CAN_TXBTO_TO15 (_U_(0x1) << CAN_TXBTO_TO15_Pos) +#define CAN_TXBTO_TO16_Pos 16 /**< \brief (CAN_TXBTO) Transmission Occurred 16 */ +#define CAN_TXBTO_TO16 (_U_(0x1) << CAN_TXBTO_TO16_Pos) +#define CAN_TXBTO_TO17_Pos 17 /**< \brief (CAN_TXBTO) Transmission Occurred 17 */ +#define CAN_TXBTO_TO17 (_U_(0x1) << CAN_TXBTO_TO17_Pos) +#define CAN_TXBTO_TO18_Pos 18 /**< \brief (CAN_TXBTO) Transmission Occurred 18 */ +#define CAN_TXBTO_TO18 (_U_(0x1) << CAN_TXBTO_TO18_Pos) +#define CAN_TXBTO_TO19_Pos 19 /**< \brief (CAN_TXBTO) Transmission Occurred 19 */ +#define CAN_TXBTO_TO19 (_U_(0x1) << CAN_TXBTO_TO19_Pos) +#define CAN_TXBTO_TO20_Pos 20 /**< \brief (CAN_TXBTO) Transmission Occurred 20 */ +#define CAN_TXBTO_TO20 (_U_(0x1) << CAN_TXBTO_TO20_Pos) +#define CAN_TXBTO_TO21_Pos 21 /**< \brief (CAN_TXBTO) Transmission Occurred 21 */ +#define CAN_TXBTO_TO21 (_U_(0x1) << CAN_TXBTO_TO21_Pos) +#define CAN_TXBTO_TO22_Pos 22 /**< \brief (CAN_TXBTO) Transmission Occurred 22 */ +#define CAN_TXBTO_TO22 (_U_(0x1) << CAN_TXBTO_TO22_Pos) +#define CAN_TXBTO_TO23_Pos 23 /**< \brief (CAN_TXBTO) Transmission Occurred 23 */ +#define CAN_TXBTO_TO23 (_U_(0x1) << CAN_TXBTO_TO23_Pos) +#define CAN_TXBTO_TO24_Pos 24 /**< \brief (CAN_TXBTO) Transmission Occurred 24 */ +#define CAN_TXBTO_TO24 (_U_(0x1) << CAN_TXBTO_TO24_Pos) +#define CAN_TXBTO_TO25_Pos 25 /**< \brief (CAN_TXBTO) Transmission Occurred 25 */ +#define CAN_TXBTO_TO25 (_U_(0x1) << CAN_TXBTO_TO25_Pos) +#define CAN_TXBTO_TO26_Pos 26 /**< \brief (CAN_TXBTO) Transmission Occurred 26 */ +#define CAN_TXBTO_TO26 (_U_(0x1) << CAN_TXBTO_TO26_Pos) +#define CAN_TXBTO_TO27_Pos 27 /**< \brief (CAN_TXBTO) Transmission Occurred 27 */ +#define CAN_TXBTO_TO27 (_U_(0x1) << CAN_TXBTO_TO27_Pos) +#define CAN_TXBTO_TO28_Pos 28 /**< \brief (CAN_TXBTO) Transmission Occurred 28 */ +#define CAN_TXBTO_TO28 (_U_(0x1) << CAN_TXBTO_TO28_Pos) +#define CAN_TXBTO_TO29_Pos 29 /**< \brief (CAN_TXBTO) Transmission Occurred 29 */ +#define CAN_TXBTO_TO29 (_U_(0x1) << CAN_TXBTO_TO29_Pos) +#define CAN_TXBTO_TO30_Pos 30 /**< \brief (CAN_TXBTO) Transmission Occurred 30 */ +#define CAN_TXBTO_TO30 (_U_(0x1) << CAN_TXBTO_TO30_Pos) +#define CAN_TXBTO_TO31_Pos 31 /**< \brief (CAN_TXBTO) Transmission Occurred 31 */ +#define CAN_TXBTO_TO31 (_U_(0x1) << CAN_TXBTO_TO31_Pos) +#define CAN_TXBTO_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBTO) MASK Register */ + +/* -------- CAN_TXBCF : (CAN Offset: 0xDC) (R/ 32) Tx Buffer Cancellation Finished -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CF0:1; /*!< bit: 0 Tx Buffer Cancellation Finished 0 */ + uint32_t CF1:1; /*!< bit: 1 Tx Buffer Cancellation Finished 1 */ + uint32_t CF2:1; /*!< bit: 2 Tx Buffer Cancellation Finished 2 */ + uint32_t CF3:1; /*!< bit: 3 Tx Buffer Cancellation Finished 3 */ + uint32_t CF4:1; /*!< bit: 4 Tx Buffer Cancellation Finished 4 */ + uint32_t CF5:1; /*!< bit: 5 Tx Buffer Cancellation Finished 5 */ + uint32_t CF6:1; /*!< bit: 6 Tx Buffer Cancellation Finished 6 */ + uint32_t CF7:1; /*!< bit: 7 Tx Buffer Cancellation Finished 7 */ + uint32_t CF8:1; /*!< bit: 8 Tx Buffer Cancellation Finished 8 */ + uint32_t CF9:1; /*!< bit: 9 Tx Buffer Cancellation Finished 9 */ + uint32_t CF10:1; /*!< bit: 10 Tx Buffer Cancellation Finished 10 */ + uint32_t CF11:1; /*!< bit: 11 Tx Buffer Cancellation Finished 11 */ + uint32_t CF12:1; /*!< bit: 12 Tx Buffer Cancellation Finished 12 */ + uint32_t CF13:1; /*!< bit: 13 Tx Buffer Cancellation Finished 13 */ + uint32_t CF14:1; /*!< bit: 14 Tx Buffer Cancellation Finished 14 */ + uint32_t CF15:1; /*!< bit: 15 Tx Buffer Cancellation Finished 15 */ + uint32_t CF16:1; /*!< bit: 16 Tx Buffer Cancellation Finished 16 */ + uint32_t CF17:1; /*!< bit: 17 Tx Buffer Cancellation Finished 17 */ + uint32_t CF18:1; /*!< bit: 18 Tx Buffer Cancellation Finished 18 */ + uint32_t CF19:1; /*!< bit: 19 Tx Buffer Cancellation Finished 19 */ + uint32_t CF20:1; /*!< bit: 20 Tx Buffer Cancellation Finished 20 */ + uint32_t CF21:1; /*!< bit: 21 Tx Buffer Cancellation Finished 21 */ + uint32_t CF22:1; /*!< bit: 22 Tx Buffer Cancellation Finished 22 */ + uint32_t CF23:1; /*!< bit: 23 Tx Buffer Cancellation Finished 23 */ + uint32_t CF24:1; /*!< bit: 24 Tx Buffer Cancellation Finished 24 */ + uint32_t CF25:1; /*!< bit: 25 Tx Buffer Cancellation Finished 25 */ + uint32_t CF26:1; /*!< bit: 26 Tx Buffer Cancellation Finished 26 */ + uint32_t CF27:1; /*!< bit: 27 Tx Buffer Cancellation Finished 27 */ + uint32_t CF28:1; /*!< bit: 28 Tx Buffer Cancellation Finished 28 */ + uint32_t CF29:1; /*!< bit: 29 Tx Buffer Cancellation Finished 29 */ + uint32_t CF30:1; /*!< bit: 30 Tx Buffer Cancellation Finished 30 */ + uint32_t CF31:1; /*!< bit: 31 Tx Buffer Cancellation Finished 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBCF_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBCF_OFFSET 0xDC /**< \brief (CAN_TXBCF offset) Tx Buffer Cancellation Finished */ +#define CAN_TXBCF_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBCF reset_value) Tx Buffer Cancellation Finished */ + +#define CAN_TXBCF_CF0_Pos 0 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 0 */ +#define CAN_TXBCF_CF0 (_U_(0x1) << CAN_TXBCF_CF0_Pos) +#define CAN_TXBCF_CF1_Pos 1 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 1 */ +#define CAN_TXBCF_CF1 (_U_(0x1) << CAN_TXBCF_CF1_Pos) +#define CAN_TXBCF_CF2_Pos 2 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 2 */ +#define CAN_TXBCF_CF2 (_U_(0x1) << CAN_TXBCF_CF2_Pos) +#define CAN_TXBCF_CF3_Pos 3 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 3 */ +#define CAN_TXBCF_CF3 (_U_(0x1) << CAN_TXBCF_CF3_Pos) +#define CAN_TXBCF_CF4_Pos 4 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 4 */ +#define CAN_TXBCF_CF4 (_U_(0x1) << CAN_TXBCF_CF4_Pos) +#define CAN_TXBCF_CF5_Pos 5 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 5 */ +#define CAN_TXBCF_CF5 (_U_(0x1) << CAN_TXBCF_CF5_Pos) +#define CAN_TXBCF_CF6_Pos 6 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 6 */ +#define CAN_TXBCF_CF6 (_U_(0x1) << CAN_TXBCF_CF6_Pos) +#define CAN_TXBCF_CF7_Pos 7 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 7 */ +#define CAN_TXBCF_CF7 (_U_(0x1) << CAN_TXBCF_CF7_Pos) +#define CAN_TXBCF_CF8_Pos 8 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 8 */ +#define CAN_TXBCF_CF8 (_U_(0x1) << CAN_TXBCF_CF8_Pos) +#define CAN_TXBCF_CF9_Pos 9 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 9 */ +#define CAN_TXBCF_CF9 (_U_(0x1) << CAN_TXBCF_CF9_Pos) +#define CAN_TXBCF_CF10_Pos 10 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 10 */ +#define CAN_TXBCF_CF10 (_U_(0x1) << CAN_TXBCF_CF10_Pos) +#define CAN_TXBCF_CF11_Pos 11 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 11 */ +#define CAN_TXBCF_CF11 (_U_(0x1) << CAN_TXBCF_CF11_Pos) +#define CAN_TXBCF_CF12_Pos 12 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 12 */ +#define CAN_TXBCF_CF12 (_U_(0x1) << CAN_TXBCF_CF12_Pos) +#define CAN_TXBCF_CF13_Pos 13 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 13 */ +#define CAN_TXBCF_CF13 (_U_(0x1) << CAN_TXBCF_CF13_Pos) +#define CAN_TXBCF_CF14_Pos 14 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 14 */ +#define CAN_TXBCF_CF14 (_U_(0x1) << CAN_TXBCF_CF14_Pos) +#define CAN_TXBCF_CF15_Pos 15 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 15 */ +#define CAN_TXBCF_CF15 (_U_(0x1) << CAN_TXBCF_CF15_Pos) +#define CAN_TXBCF_CF16_Pos 16 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 16 */ +#define CAN_TXBCF_CF16 (_U_(0x1) << CAN_TXBCF_CF16_Pos) +#define CAN_TXBCF_CF17_Pos 17 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 17 */ +#define CAN_TXBCF_CF17 (_U_(0x1) << CAN_TXBCF_CF17_Pos) +#define CAN_TXBCF_CF18_Pos 18 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 18 */ +#define CAN_TXBCF_CF18 (_U_(0x1) << CAN_TXBCF_CF18_Pos) +#define CAN_TXBCF_CF19_Pos 19 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 19 */ +#define CAN_TXBCF_CF19 (_U_(0x1) << CAN_TXBCF_CF19_Pos) +#define CAN_TXBCF_CF20_Pos 20 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 20 */ +#define CAN_TXBCF_CF20 (_U_(0x1) << CAN_TXBCF_CF20_Pos) +#define CAN_TXBCF_CF21_Pos 21 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 21 */ +#define CAN_TXBCF_CF21 (_U_(0x1) << CAN_TXBCF_CF21_Pos) +#define CAN_TXBCF_CF22_Pos 22 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 22 */ +#define CAN_TXBCF_CF22 (_U_(0x1) << CAN_TXBCF_CF22_Pos) +#define CAN_TXBCF_CF23_Pos 23 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 23 */ +#define CAN_TXBCF_CF23 (_U_(0x1) << CAN_TXBCF_CF23_Pos) +#define CAN_TXBCF_CF24_Pos 24 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 24 */ +#define CAN_TXBCF_CF24 (_U_(0x1) << CAN_TXBCF_CF24_Pos) +#define CAN_TXBCF_CF25_Pos 25 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 25 */ +#define CAN_TXBCF_CF25 (_U_(0x1) << CAN_TXBCF_CF25_Pos) +#define CAN_TXBCF_CF26_Pos 26 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 26 */ +#define CAN_TXBCF_CF26 (_U_(0x1) << CAN_TXBCF_CF26_Pos) +#define CAN_TXBCF_CF27_Pos 27 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 27 */ +#define CAN_TXBCF_CF27 (_U_(0x1) << CAN_TXBCF_CF27_Pos) +#define CAN_TXBCF_CF28_Pos 28 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 28 */ +#define CAN_TXBCF_CF28 (_U_(0x1) << CAN_TXBCF_CF28_Pos) +#define CAN_TXBCF_CF29_Pos 29 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 29 */ +#define CAN_TXBCF_CF29 (_U_(0x1) << CAN_TXBCF_CF29_Pos) +#define CAN_TXBCF_CF30_Pos 30 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 30 */ +#define CAN_TXBCF_CF30 (_U_(0x1) << CAN_TXBCF_CF30_Pos) +#define CAN_TXBCF_CF31_Pos 31 /**< \brief (CAN_TXBCF) Tx Buffer Cancellation Finished 31 */ +#define CAN_TXBCF_CF31 (_U_(0x1) << CAN_TXBCF_CF31_Pos) +#define CAN_TXBCF_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBCF) MASK Register */ + +/* -------- CAN_TXBTIE : (CAN Offset: 0xE0) (R/W 32) Tx Buffer Transmission Interrupt Enable -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TIE0:1; /*!< bit: 0 Transmission Interrupt Enable 0 */ + uint32_t TIE1:1; /*!< bit: 1 Transmission Interrupt Enable 1 */ + uint32_t TIE2:1; /*!< bit: 2 Transmission Interrupt Enable 2 */ + uint32_t TIE3:1; /*!< bit: 3 Transmission Interrupt Enable 3 */ + uint32_t TIE4:1; /*!< bit: 4 Transmission Interrupt Enable 4 */ + uint32_t TIE5:1; /*!< bit: 5 Transmission Interrupt Enable 5 */ + uint32_t TIE6:1; /*!< bit: 6 Transmission Interrupt Enable 6 */ + uint32_t TIE7:1; /*!< bit: 7 Transmission Interrupt Enable 7 */ + uint32_t TIE8:1; /*!< bit: 8 Transmission Interrupt Enable 8 */ + uint32_t TIE9:1; /*!< bit: 9 Transmission Interrupt Enable 9 */ + uint32_t TIE10:1; /*!< bit: 10 Transmission Interrupt Enable 10 */ + uint32_t TIE11:1; /*!< bit: 11 Transmission Interrupt Enable 11 */ + uint32_t TIE12:1; /*!< bit: 12 Transmission Interrupt Enable 12 */ + uint32_t TIE13:1; /*!< bit: 13 Transmission Interrupt Enable 13 */ + uint32_t TIE14:1; /*!< bit: 14 Transmission Interrupt Enable 14 */ + uint32_t TIE15:1; /*!< bit: 15 Transmission Interrupt Enable 15 */ + uint32_t TIE16:1; /*!< bit: 16 Transmission Interrupt Enable 16 */ + uint32_t TIE17:1; /*!< bit: 17 Transmission Interrupt Enable 17 */ + uint32_t TIE18:1; /*!< bit: 18 Transmission Interrupt Enable 18 */ + uint32_t TIE19:1; /*!< bit: 19 Transmission Interrupt Enable 19 */ + uint32_t TIE20:1; /*!< bit: 20 Transmission Interrupt Enable 20 */ + uint32_t TIE21:1; /*!< bit: 21 Transmission Interrupt Enable 21 */ + uint32_t TIE22:1; /*!< bit: 22 Transmission Interrupt Enable 22 */ + uint32_t TIE23:1; /*!< bit: 23 Transmission Interrupt Enable 23 */ + uint32_t TIE24:1; /*!< bit: 24 Transmission Interrupt Enable 24 */ + uint32_t TIE25:1; /*!< bit: 25 Transmission Interrupt Enable 25 */ + uint32_t TIE26:1; /*!< bit: 26 Transmission Interrupt Enable 26 */ + uint32_t TIE27:1; /*!< bit: 27 Transmission Interrupt Enable 27 */ + uint32_t TIE28:1; /*!< bit: 28 Transmission Interrupt Enable 28 */ + uint32_t TIE29:1; /*!< bit: 29 Transmission Interrupt Enable 29 */ + uint32_t TIE30:1; /*!< bit: 30 Transmission Interrupt Enable 30 */ + uint32_t TIE31:1; /*!< bit: 31 Transmission Interrupt Enable 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBTIE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBTIE_OFFSET 0xE0 /**< \brief (CAN_TXBTIE offset) Tx Buffer Transmission Interrupt Enable */ +#define CAN_TXBTIE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBTIE reset_value) Tx Buffer Transmission Interrupt Enable */ + +#define CAN_TXBTIE_TIE0_Pos 0 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 0 */ +#define CAN_TXBTIE_TIE0 (_U_(0x1) << CAN_TXBTIE_TIE0_Pos) +#define CAN_TXBTIE_TIE1_Pos 1 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 1 */ +#define CAN_TXBTIE_TIE1 (_U_(0x1) << CAN_TXBTIE_TIE1_Pos) +#define CAN_TXBTIE_TIE2_Pos 2 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 2 */ +#define CAN_TXBTIE_TIE2 (_U_(0x1) << CAN_TXBTIE_TIE2_Pos) +#define CAN_TXBTIE_TIE3_Pos 3 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 3 */ +#define CAN_TXBTIE_TIE3 (_U_(0x1) << CAN_TXBTIE_TIE3_Pos) +#define CAN_TXBTIE_TIE4_Pos 4 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 4 */ +#define CAN_TXBTIE_TIE4 (_U_(0x1) << CAN_TXBTIE_TIE4_Pos) +#define CAN_TXBTIE_TIE5_Pos 5 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 5 */ +#define CAN_TXBTIE_TIE5 (_U_(0x1) << CAN_TXBTIE_TIE5_Pos) +#define CAN_TXBTIE_TIE6_Pos 6 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 6 */ +#define CAN_TXBTIE_TIE6 (_U_(0x1) << CAN_TXBTIE_TIE6_Pos) +#define CAN_TXBTIE_TIE7_Pos 7 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 7 */ +#define CAN_TXBTIE_TIE7 (_U_(0x1) << CAN_TXBTIE_TIE7_Pos) +#define CAN_TXBTIE_TIE8_Pos 8 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 8 */ +#define CAN_TXBTIE_TIE8 (_U_(0x1) << CAN_TXBTIE_TIE8_Pos) +#define CAN_TXBTIE_TIE9_Pos 9 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 9 */ +#define CAN_TXBTIE_TIE9 (_U_(0x1) << CAN_TXBTIE_TIE9_Pos) +#define CAN_TXBTIE_TIE10_Pos 10 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 10 */ +#define CAN_TXBTIE_TIE10 (_U_(0x1) << CAN_TXBTIE_TIE10_Pos) +#define CAN_TXBTIE_TIE11_Pos 11 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 11 */ +#define CAN_TXBTIE_TIE11 (_U_(0x1) << CAN_TXBTIE_TIE11_Pos) +#define CAN_TXBTIE_TIE12_Pos 12 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 12 */ +#define CAN_TXBTIE_TIE12 (_U_(0x1) << CAN_TXBTIE_TIE12_Pos) +#define CAN_TXBTIE_TIE13_Pos 13 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 13 */ +#define CAN_TXBTIE_TIE13 (_U_(0x1) << CAN_TXBTIE_TIE13_Pos) +#define CAN_TXBTIE_TIE14_Pos 14 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 14 */ +#define CAN_TXBTIE_TIE14 (_U_(0x1) << CAN_TXBTIE_TIE14_Pos) +#define CAN_TXBTIE_TIE15_Pos 15 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 15 */ +#define CAN_TXBTIE_TIE15 (_U_(0x1) << CAN_TXBTIE_TIE15_Pos) +#define CAN_TXBTIE_TIE16_Pos 16 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 16 */ +#define CAN_TXBTIE_TIE16 (_U_(0x1) << CAN_TXBTIE_TIE16_Pos) +#define CAN_TXBTIE_TIE17_Pos 17 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 17 */ +#define CAN_TXBTIE_TIE17 (_U_(0x1) << CAN_TXBTIE_TIE17_Pos) +#define CAN_TXBTIE_TIE18_Pos 18 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 18 */ +#define CAN_TXBTIE_TIE18 (_U_(0x1) << CAN_TXBTIE_TIE18_Pos) +#define CAN_TXBTIE_TIE19_Pos 19 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 19 */ +#define CAN_TXBTIE_TIE19 (_U_(0x1) << CAN_TXBTIE_TIE19_Pos) +#define CAN_TXBTIE_TIE20_Pos 20 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 20 */ +#define CAN_TXBTIE_TIE20 (_U_(0x1) << CAN_TXBTIE_TIE20_Pos) +#define CAN_TXBTIE_TIE21_Pos 21 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 21 */ +#define CAN_TXBTIE_TIE21 (_U_(0x1) << CAN_TXBTIE_TIE21_Pos) +#define CAN_TXBTIE_TIE22_Pos 22 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 22 */ +#define CAN_TXBTIE_TIE22 (_U_(0x1) << CAN_TXBTIE_TIE22_Pos) +#define CAN_TXBTIE_TIE23_Pos 23 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 23 */ +#define CAN_TXBTIE_TIE23 (_U_(0x1) << CAN_TXBTIE_TIE23_Pos) +#define CAN_TXBTIE_TIE24_Pos 24 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 24 */ +#define CAN_TXBTIE_TIE24 (_U_(0x1) << CAN_TXBTIE_TIE24_Pos) +#define CAN_TXBTIE_TIE25_Pos 25 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 25 */ +#define CAN_TXBTIE_TIE25 (_U_(0x1) << CAN_TXBTIE_TIE25_Pos) +#define CAN_TXBTIE_TIE26_Pos 26 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 26 */ +#define CAN_TXBTIE_TIE26 (_U_(0x1) << CAN_TXBTIE_TIE26_Pos) +#define CAN_TXBTIE_TIE27_Pos 27 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 27 */ +#define CAN_TXBTIE_TIE27 (_U_(0x1) << CAN_TXBTIE_TIE27_Pos) +#define CAN_TXBTIE_TIE28_Pos 28 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 28 */ +#define CAN_TXBTIE_TIE28 (_U_(0x1) << CAN_TXBTIE_TIE28_Pos) +#define CAN_TXBTIE_TIE29_Pos 29 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 29 */ +#define CAN_TXBTIE_TIE29 (_U_(0x1) << CAN_TXBTIE_TIE29_Pos) +#define CAN_TXBTIE_TIE30_Pos 30 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 30 */ +#define CAN_TXBTIE_TIE30 (_U_(0x1) << CAN_TXBTIE_TIE30_Pos) +#define CAN_TXBTIE_TIE31_Pos 31 /**< \brief (CAN_TXBTIE) Transmission Interrupt Enable 31 */ +#define CAN_TXBTIE_TIE31 (_U_(0x1) << CAN_TXBTIE_TIE31_Pos) +#define CAN_TXBTIE_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBTIE) MASK Register */ + +/* -------- CAN_TXBCIE : (CAN Offset: 0xE4) (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CFIE0:1; /*!< bit: 0 Cancellation Finished Interrupt Enable 0 */ + uint32_t CFIE1:1; /*!< bit: 1 Cancellation Finished Interrupt Enable 1 */ + uint32_t CFIE2:1; /*!< bit: 2 Cancellation Finished Interrupt Enable 2 */ + uint32_t CFIE3:1; /*!< bit: 3 Cancellation Finished Interrupt Enable 3 */ + uint32_t CFIE4:1; /*!< bit: 4 Cancellation Finished Interrupt Enable 4 */ + uint32_t CFIE5:1; /*!< bit: 5 Cancellation Finished Interrupt Enable 5 */ + uint32_t CFIE6:1; /*!< bit: 6 Cancellation Finished Interrupt Enable 6 */ + uint32_t CFIE7:1; /*!< bit: 7 Cancellation Finished Interrupt Enable 7 */ + uint32_t CFIE8:1; /*!< bit: 8 Cancellation Finished Interrupt Enable 8 */ + uint32_t CFIE9:1; /*!< bit: 9 Cancellation Finished Interrupt Enable 9 */ + uint32_t CFIE10:1; /*!< bit: 10 Cancellation Finished Interrupt Enable 10 */ + uint32_t CFIE11:1; /*!< bit: 11 Cancellation Finished Interrupt Enable 11 */ + uint32_t CFIE12:1; /*!< bit: 12 Cancellation Finished Interrupt Enable 12 */ + uint32_t CFIE13:1; /*!< bit: 13 Cancellation Finished Interrupt Enable 13 */ + uint32_t CFIE14:1; /*!< bit: 14 Cancellation Finished Interrupt Enable 14 */ + uint32_t CFIE15:1; /*!< bit: 15 Cancellation Finished Interrupt Enable 15 */ + uint32_t CFIE16:1; /*!< bit: 16 Cancellation Finished Interrupt Enable 16 */ + uint32_t CFIE17:1; /*!< bit: 17 Cancellation Finished Interrupt Enable 17 */ + uint32_t CFIE18:1; /*!< bit: 18 Cancellation Finished Interrupt Enable 18 */ + uint32_t CFIE19:1; /*!< bit: 19 Cancellation Finished Interrupt Enable 19 */ + uint32_t CFIE20:1; /*!< bit: 20 Cancellation Finished Interrupt Enable 20 */ + uint32_t CFIE21:1; /*!< bit: 21 Cancellation Finished Interrupt Enable 21 */ + uint32_t CFIE22:1; /*!< bit: 22 Cancellation Finished Interrupt Enable 22 */ + uint32_t CFIE23:1; /*!< bit: 23 Cancellation Finished Interrupt Enable 23 */ + uint32_t CFIE24:1; /*!< bit: 24 Cancellation Finished Interrupt Enable 24 */ + uint32_t CFIE25:1; /*!< bit: 25 Cancellation Finished Interrupt Enable 25 */ + uint32_t CFIE26:1; /*!< bit: 26 Cancellation Finished Interrupt Enable 26 */ + uint32_t CFIE27:1; /*!< bit: 27 Cancellation Finished Interrupt Enable 27 */ + uint32_t CFIE28:1; /*!< bit: 28 Cancellation Finished Interrupt Enable 28 */ + uint32_t CFIE29:1; /*!< bit: 29 Cancellation Finished Interrupt Enable 29 */ + uint32_t CFIE30:1; /*!< bit: 30 Cancellation Finished Interrupt Enable 30 */ + uint32_t CFIE31:1; /*!< bit: 31 Cancellation Finished Interrupt Enable 31 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBCIE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBCIE_OFFSET 0xE4 /**< \brief (CAN_TXBCIE offset) Tx Buffer Cancellation Finished Interrupt Enable */ +#define CAN_TXBCIE_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBCIE reset_value) Tx Buffer Cancellation Finished Interrupt Enable */ + +#define CAN_TXBCIE_CFIE0_Pos 0 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 0 */ +#define CAN_TXBCIE_CFIE0 (_U_(0x1) << CAN_TXBCIE_CFIE0_Pos) +#define CAN_TXBCIE_CFIE1_Pos 1 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 1 */ +#define CAN_TXBCIE_CFIE1 (_U_(0x1) << CAN_TXBCIE_CFIE1_Pos) +#define CAN_TXBCIE_CFIE2_Pos 2 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 2 */ +#define CAN_TXBCIE_CFIE2 (_U_(0x1) << CAN_TXBCIE_CFIE2_Pos) +#define CAN_TXBCIE_CFIE3_Pos 3 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 3 */ +#define CAN_TXBCIE_CFIE3 (_U_(0x1) << CAN_TXBCIE_CFIE3_Pos) +#define CAN_TXBCIE_CFIE4_Pos 4 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 4 */ +#define CAN_TXBCIE_CFIE4 (_U_(0x1) << CAN_TXBCIE_CFIE4_Pos) +#define CAN_TXBCIE_CFIE5_Pos 5 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 5 */ +#define CAN_TXBCIE_CFIE5 (_U_(0x1) << CAN_TXBCIE_CFIE5_Pos) +#define CAN_TXBCIE_CFIE6_Pos 6 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 6 */ +#define CAN_TXBCIE_CFIE6 (_U_(0x1) << CAN_TXBCIE_CFIE6_Pos) +#define CAN_TXBCIE_CFIE7_Pos 7 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 7 */ +#define CAN_TXBCIE_CFIE7 (_U_(0x1) << CAN_TXBCIE_CFIE7_Pos) +#define CAN_TXBCIE_CFIE8_Pos 8 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 8 */ +#define CAN_TXBCIE_CFIE8 (_U_(0x1) << CAN_TXBCIE_CFIE8_Pos) +#define CAN_TXBCIE_CFIE9_Pos 9 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 9 */ +#define CAN_TXBCIE_CFIE9 (_U_(0x1) << CAN_TXBCIE_CFIE9_Pos) +#define CAN_TXBCIE_CFIE10_Pos 10 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 10 */ +#define CAN_TXBCIE_CFIE10 (_U_(0x1) << CAN_TXBCIE_CFIE10_Pos) +#define CAN_TXBCIE_CFIE11_Pos 11 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 11 */ +#define CAN_TXBCIE_CFIE11 (_U_(0x1) << CAN_TXBCIE_CFIE11_Pos) +#define CAN_TXBCIE_CFIE12_Pos 12 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 12 */ +#define CAN_TXBCIE_CFIE12 (_U_(0x1) << CAN_TXBCIE_CFIE12_Pos) +#define CAN_TXBCIE_CFIE13_Pos 13 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 13 */ +#define CAN_TXBCIE_CFIE13 (_U_(0x1) << CAN_TXBCIE_CFIE13_Pos) +#define CAN_TXBCIE_CFIE14_Pos 14 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 14 */ +#define CAN_TXBCIE_CFIE14 (_U_(0x1) << CAN_TXBCIE_CFIE14_Pos) +#define CAN_TXBCIE_CFIE15_Pos 15 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 15 */ +#define CAN_TXBCIE_CFIE15 (_U_(0x1) << CAN_TXBCIE_CFIE15_Pos) +#define CAN_TXBCIE_CFIE16_Pos 16 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 16 */ +#define CAN_TXBCIE_CFIE16 (_U_(0x1) << CAN_TXBCIE_CFIE16_Pos) +#define CAN_TXBCIE_CFIE17_Pos 17 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 17 */ +#define CAN_TXBCIE_CFIE17 (_U_(0x1) << CAN_TXBCIE_CFIE17_Pos) +#define CAN_TXBCIE_CFIE18_Pos 18 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 18 */ +#define CAN_TXBCIE_CFIE18 (_U_(0x1) << CAN_TXBCIE_CFIE18_Pos) +#define CAN_TXBCIE_CFIE19_Pos 19 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 19 */ +#define CAN_TXBCIE_CFIE19 (_U_(0x1) << CAN_TXBCIE_CFIE19_Pos) +#define CAN_TXBCIE_CFIE20_Pos 20 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 20 */ +#define CAN_TXBCIE_CFIE20 (_U_(0x1) << CAN_TXBCIE_CFIE20_Pos) +#define CAN_TXBCIE_CFIE21_Pos 21 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 21 */ +#define CAN_TXBCIE_CFIE21 (_U_(0x1) << CAN_TXBCIE_CFIE21_Pos) +#define CAN_TXBCIE_CFIE22_Pos 22 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 22 */ +#define CAN_TXBCIE_CFIE22 (_U_(0x1) << CAN_TXBCIE_CFIE22_Pos) +#define CAN_TXBCIE_CFIE23_Pos 23 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 23 */ +#define CAN_TXBCIE_CFIE23 (_U_(0x1) << CAN_TXBCIE_CFIE23_Pos) +#define CAN_TXBCIE_CFIE24_Pos 24 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 24 */ +#define CAN_TXBCIE_CFIE24 (_U_(0x1) << CAN_TXBCIE_CFIE24_Pos) +#define CAN_TXBCIE_CFIE25_Pos 25 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 25 */ +#define CAN_TXBCIE_CFIE25 (_U_(0x1) << CAN_TXBCIE_CFIE25_Pos) +#define CAN_TXBCIE_CFIE26_Pos 26 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 26 */ +#define CAN_TXBCIE_CFIE26 (_U_(0x1) << CAN_TXBCIE_CFIE26_Pos) +#define CAN_TXBCIE_CFIE27_Pos 27 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 27 */ +#define CAN_TXBCIE_CFIE27 (_U_(0x1) << CAN_TXBCIE_CFIE27_Pos) +#define CAN_TXBCIE_CFIE28_Pos 28 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 28 */ +#define CAN_TXBCIE_CFIE28 (_U_(0x1) << CAN_TXBCIE_CFIE28_Pos) +#define CAN_TXBCIE_CFIE29_Pos 29 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 29 */ +#define CAN_TXBCIE_CFIE29 (_U_(0x1) << CAN_TXBCIE_CFIE29_Pos) +#define CAN_TXBCIE_CFIE30_Pos 30 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 30 */ +#define CAN_TXBCIE_CFIE30 (_U_(0x1) << CAN_TXBCIE_CFIE30_Pos) +#define CAN_TXBCIE_CFIE31_Pos 31 /**< \brief (CAN_TXBCIE) Cancellation Finished Interrupt Enable 31 */ +#define CAN_TXBCIE_CFIE31 (_U_(0x1) << CAN_TXBCIE_CFIE31_Pos) +#define CAN_TXBCIE_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBCIE) MASK Register */ + +/* -------- CAN_TXEFC : (CAN Offset: 0xF0) (R/W 32) Tx Event FIFO Configuration -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EFSA:16; /*!< bit: 0..15 Event FIFO Start Address */ + uint32_t EFS:6; /*!< bit: 16..21 Event FIFO Size */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t EFWM:6; /*!< bit: 24..29 Event FIFO Watermark */ + uint32_t :2; /*!< bit: 30..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXEFC_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXEFC_OFFSET 0xF0 /**< \brief (CAN_TXEFC offset) Tx Event FIFO Configuration */ +#define CAN_TXEFC_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFC reset_value) Tx Event FIFO Configuration */ + +#define CAN_TXEFC_EFSA_Pos 0 /**< \brief (CAN_TXEFC) Event FIFO Start Address */ +#define CAN_TXEFC_EFSA_Msk (_U_(0xFFFF) << CAN_TXEFC_EFSA_Pos) +#define CAN_TXEFC_EFSA(value) (CAN_TXEFC_EFSA_Msk & ((value) << CAN_TXEFC_EFSA_Pos)) +#define CAN_TXEFC_EFS_Pos 16 /**< \brief (CAN_TXEFC) Event FIFO Size */ +#define CAN_TXEFC_EFS_Msk (_U_(0x3F) << CAN_TXEFC_EFS_Pos) +#define CAN_TXEFC_EFS(value) (CAN_TXEFC_EFS_Msk & ((value) << CAN_TXEFC_EFS_Pos)) +#define CAN_TXEFC_EFWM_Pos 24 /**< \brief (CAN_TXEFC) Event FIFO Watermark */ +#define CAN_TXEFC_EFWM_Msk (_U_(0x3F) << CAN_TXEFC_EFWM_Pos) +#define CAN_TXEFC_EFWM(value) (CAN_TXEFC_EFWM_Msk & ((value) << CAN_TXEFC_EFWM_Pos)) +#define CAN_TXEFC_MASK _U_(0x3F3FFFFF) /**< \brief (CAN_TXEFC) MASK Register */ + +/* -------- CAN_TXEFS : (CAN Offset: 0xF4) (R/ 32) Tx Event FIFO Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EFFL:6; /*!< bit: 0.. 5 Event FIFO Fill Level */ + uint32_t :2; /*!< bit: 6.. 7 Reserved */ + uint32_t EFGI:5; /*!< bit: 8..12 Event FIFO Get Index */ + uint32_t :3; /*!< bit: 13..15 Reserved */ + uint32_t EFPI:5; /*!< bit: 16..20 Event FIFO Put Index */ + uint32_t :3; /*!< bit: 21..23 Reserved */ + uint32_t EFF:1; /*!< bit: 24 Event FIFO Full */ + uint32_t TEFL:1; /*!< bit: 25 Tx Event FIFO Element Lost */ + uint32_t :6; /*!< bit: 26..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXEFS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXEFS_OFFSET 0xF4 /**< \brief (CAN_TXEFS offset) Tx Event FIFO Status */ +#define CAN_TXEFS_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFS reset_value) Tx Event FIFO Status */ + +#define CAN_TXEFS_EFFL_Pos 0 /**< \brief (CAN_TXEFS) Event FIFO Fill Level */ +#define CAN_TXEFS_EFFL_Msk (_U_(0x3F) << CAN_TXEFS_EFFL_Pos) +#define CAN_TXEFS_EFFL(value) (CAN_TXEFS_EFFL_Msk & ((value) << CAN_TXEFS_EFFL_Pos)) +#define CAN_TXEFS_EFGI_Pos 8 /**< \brief (CAN_TXEFS) Event FIFO Get Index */ +#define CAN_TXEFS_EFGI_Msk (_U_(0x1F) << CAN_TXEFS_EFGI_Pos) +#define CAN_TXEFS_EFGI(value) (CAN_TXEFS_EFGI_Msk & ((value) << CAN_TXEFS_EFGI_Pos)) +#define CAN_TXEFS_EFPI_Pos 16 /**< \brief (CAN_TXEFS) Event FIFO Put Index */ +#define CAN_TXEFS_EFPI_Msk (_U_(0x1F) << CAN_TXEFS_EFPI_Pos) +#define CAN_TXEFS_EFPI(value) (CAN_TXEFS_EFPI_Msk & ((value) << CAN_TXEFS_EFPI_Pos)) +#define CAN_TXEFS_EFF_Pos 24 /**< \brief (CAN_TXEFS) Event FIFO Full */ +#define CAN_TXEFS_EFF (_U_(0x1) << CAN_TXEFS_EFF_Pos) +#define CAN_TXEFS_TEFL_Pos 25 /**< \brief (CAN_TXEFS) Tx Event FIFO Element Lost */ +#define CAN_TXEFS_TEFL (_U_(0x1) << CAN_TXEFS_TEFL_Pos) +#define CAN_TXEFS_MASK _U_(0x031F1F3F) /**< \brief (CAN_TXEFS) MASK Register */ + +/* -------- CAN_TXEFA : (CAN Offset: 0xF8) (R/W 32) Tx Event FIFO Acknowledge -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EFAI:5; /*!< bit: 0.. 4 Event FIFO Acknowledge Index */ + uint32_t :27; /*!< bit: 5..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXEFA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXEFA_OFFSET 0xF8 /**< \brief (CAN_TXEFA offset) Tx Event FIFO Acknowledge */ +#define CAN_TXEFA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFA reset_value) Tx Event FIFO Acknowledge */ + +#define CAN_TXEFA_EFAI_Pos 0 /**< \brief (CAN_TXEFA) Event FIFO Acknowledge Index */ +#define CAN_TXEFA_EFAI_Msk (_U_(0x1F) << CAN_TXEFA_EFAI_Pos) +#define CAN_TXEFA_EFAI(value) (CAN_TXEFA_EFAI_Msk & ((value) << CAN_TXEFA_EFAI_Pos)) +#define CAN_TXEFA_MASK _U_(0x0000001F) /**< \brief (CAN_TXEFA) MASK Register */ + +/* -------- CAN_RXBE_0 : (CAN Offset: 0x00) (R/W 32) Rx Buffer Element 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ID:29; /*!< bit: 0..28 Identifier */ + uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ + uint32_t XTD:1; /*!< bit: 30 Extended Identifier */ + uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXBE_0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXBE_0_OFFSET 0x00 /**< \brief (CAN_RXBE_0 offset) Rx Buffer Element 0 */ +#define CAN_RXBE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXBE_0 reset_value) Rx Buffer Element 0 */ + +#define CAN_RXBE_0_ID_Pos 0 /**< \brief (CAN_RXBE_0) Identifier */ +#define CAN_RXBE_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_RXBE_0_ID_Pos) +#define CAN_RXBE_0_ID(value) (CAN_RXBE_0_ID_Msk & ((value) << CAN_RXBE_0_ID_Pos)) +#define CAN_RXBE_0_RTR_Pos 29 /**< \brief (CAN_RXBE_0) Remote Transmission Request */ +#define CAN_RXBE_0_RTR (_U_(0x1) << CAN_RXBE_0_RTR_Pos) +#define CAN_RXBE_0_XTD_Pos 30 /**< \brief (CAN_RXBE_0) Extended Identifier */ +#define CAN_RXBE_0_XTD (_U_(0x1) << CAN_RXBE_0_XTD_Pos) +#define CAN_RXBE_0_ESI_Pos 31 /**< \brief (CAN_RXBE_0) Error State Indicator */ +#define CAN_RXBE_0_ESI (_U_(0x1) << CAN_RXBE_0_ESI_Pos) +#define CAN_RXBE_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXBE_0) MASK Register */ + +/* -------- CAN_RXBE_1 : (CAN Offset: 0x04) (R/W 32) Rx Buffer Element 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */ + uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */ + uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ + uint32_t FDF:1; /*!< bit: 21 FD Format */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */ + uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXBE_1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXBE_1_OFFSET 0x04 /**< \brief (CAN_RXBE_1 offset) Rx Buffer Element 1 */ +#define CAN_RXBE_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXBE_1 reset_value) Rx Buffer Element 1 */ + +#define CAN_RXBE_1_RXTS_Pos 0 /**< \brief (CAN_RXBE_1) Rx Timestamp */ +#define CAN_RXBE_1_RXTS_Msk (_U_(0xFFFF) << CAN_RXBE_1_RXTS_Pos) +#define CAN_RXBE_1_RXTS(value) (CAN_RXBE_1_RXTS_Msk & ((value) << CAN_RXBE_1_RXTS_Pos)) +#define CAN_RXBE_1_DLC_Pos 16 /**< \brief (CAN_RXBE_1) Data Length Code */ +#define CAN_RXBE_1_DLC_Msk (_U_(0xF) << CAN_RXBE_1_DLC_Pos) +#define CAN_RXBE_1_DLC(value) (CAN_RXBE_1_DLC_Msk & ((value) << CAN_RXBE_1_DLC_Pos)) +#define CAN_RXBE_1_BRS_Pos 20 /**< \brief (CAN_RXBE_1) Bit Rate Search */ +#define CAN_RXBE_1_BRS (_U_(0x1) << CAN_RXBE_1_BRS_Pos) +#define CAN_RXBE_1_FDF_Pos 21 /**< \brief (CAN_RXBE_1) FD Format */ +#define CAN_RXBE_1_FDF (_U_(0x1) << CAN_RXBE_1_FDF_Pos) +#define CAN_RXBE_1_FIDX_Pos 24 /**< \brief (CAN_RXBE_1) Filter Index */ +#define CAN_RXBE_1_FIDX_Msk (_U_(0x7F) << CAN_RXBE_1_FIDX_Pos) +#define CAN_RXBE_1_FIDX(value) (CAN_RXBE_1_FIDX_Msk & ((value) << CAN_RXBE_1_FIDX_Pos)) +#define CAN_RXBE_1_ANMF_Pos 31 /**< \brief (CAN_RXBE_1) Accepted Non-matching Frame */ +#define CAN_RXBE_1_ANMF (_U_(0x1) << CAN_RXBE_1_ANMF_Pos) +#define CAN_RXBE_1_MASK _U_(0xFF3FFFFF) /**< \brief (CAN_RXBE_1) MASK Register */ + +/* -------- CAN_RXBE_DATA : (CAN Offset: 0x08) (R/W 32) Rx Buffer Element Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */ + uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */ + uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */ + uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXBE_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXBE_DATA_OFFSET 0x08 /**< \brief (CAN_RXBE_DATA offset) Rx Buffer Element Data */ +#define CAN_RXBE_DATA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXBE_DATA reset_value) Rx Buffer Element Data */ + +#define CAN_RXBE_DATA_DB0_Pos 0 /**< \brief (CAN_RXBE_DATA) Data Byte 0 */ +#define CAN_RXBE_DATA_DB0_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB0_Pos) +#define CAN_RXBE_DATA_DB0(value) (CAN_RXBE_DATA_DB0_Msk & ((value) << CAN_RXBE_DATA_DB0_Pos)) +#define CAN_RXBE_DATA_DB1_Pos 8 /**< \brief (CAN_RXBE_DATA) Data Byte 1 */ +#define CAN_RXBE_DATA_DB1_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB1_Pos) +#define CAN_RXBE_DATA_DB1(value) (CAN_RXBE_DATA_DB1_Msk & ((value) << CAN_RXBE_DATA_DB1_Pos)) +#define CAN_RXBE_DATA_DB2_Pos 16 /**< \brief (CAN_RXBE_DATA) Data Byte 2 */ +#define CAN_RXBE_DATA_DB2_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB2_Pos) +#define CAN_RXBE_DATA_DB2(value) (CAN_RXBE_DATA_DB2_Msk & ((value) << CAN_RXBE_DATA_DB2_Pos)) +#define CAN_RXBE_DATA_DB3_Pos 24 /**< \brief (CAN_RXBE_DATA) Data Byte 3 */ +#define CAN_RXBE_DATA_DB3_Msk (_U_(0xFF) << CAN_RXBE_DATA_DB3_Pos) +#define CAN_RXBE_DATA_DB3(value) (CAN_RXBE_DATA_DB3_Msk & ((value) << CAN_RXBE_DATA_DB3_Pos)) +#define CAN_RXBE_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXBE_DATA) MASK Register */ + +/* -------- CAN_RXF0E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 0 Element 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ID:29; /*!< bit: 0..28 Identifier */ + uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ + uint32_t XTD:1; /*!< bit: 30 Extended Identifier */ + uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF0E_0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF0E_0_OFFSET 0x00 /**< \brief (CAN_RXF0E_0 offset) Rx FIFO 0 Element 0 */ +#define CAN_RXF0E_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0E_0 reset_value) Rx FIFO 0 Element 0 */ + +#define CAN_RXF0E_0_ID_Pos 0 /**< \brief (CAN_RXF0E_0) Identifier */ +#define CAN_RXF0E_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_RXF0E_0_ID_Pos) +#define CAN_RXF0E_0_ID(value) (CAN_RXF0E_0_ID_Msk & ((value) << CAN_RXF0E_0_ID_Pos)) +#define CAN_RXF0E_0_RTR_Pos 29 /**< \brief (CAN_RXF0E_0) Remote Transmission Request */ +#define CAN_RXF0E_0_RTR (_U_(0x1) << CAN_RXF0E_0_RTR_Pos) +#define CAN_RXF0E_0_XTD_Pos 30 /**< \brief (CAN_RXF0E_0) Extended Identifier */ +#define CAN_RXF0E_0_XTD (_U_(0x1) << CAN_RXF0E_0_XTD_Pos) +#define CAN_RXF0E_0_ESI_Pos 31 /**< \brief (CAN_RXF0E_0) Error State Indicator */ +#define CAN_RXF0E_0_ESI (_U_(0x1) << CAN_RXF0E_0_ESI_Pos) +#define CAN_RXF0E_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXF0E_0) MASK Register */ + +/* -------- CAN_RXF0E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 0 Element 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */ + uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */ + uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ + uint32_t FDF:1; /*!< bit: 21 FD Format */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */ + uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF0E_1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF0E_1_OFFSET 0x04 /**< \brief (CAN_RXF0E_1 offset) Rx FIFO 0 Element 1 */ +#define CAN_RXF0E_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0E_1 reset_value) Rx FIFO 0 Element 1 */ + +#define CAN_RXF0E_1_RXTS_Pos 0 /**< \brief (CAN_RXF0E_1) Rx Timestamp */ +#define CAN_RXF0E_1_RXTS_Msk (_U_(0xFFFF) << CAN_RXF0E_1_RXTS_Pos) +#define CAN_RXF0E_1_RXTS(value) (CAN_RXF0E_1_RXTS_Msk & ((value) << CAN_RXF0E_1_RXTS_Pos)) +#define CAN_RXF0E_1_DLC_Pos 16 /**< \brief (CAN_RXF0E_1) Data Length Code */ +#define CAN_RXF0E_1_DLC_Msk (_U_(0xF) << CAN_RXF0E_1_DLC_Pos) +#define CAN_RXF0E_1_DLC(value) (CAN_RXF0E_1_DLC_Msk & ((value) << CAN_RXF0E_1_DLC_Pos)) +#define CAN_RXF0E_1_BRS_Pos 20 /**< \brief (CAN_RXF0E_1) Bit Rate Search */ +#define CAN_RXF0E_1_BRS (_U_(0x1) << CAN_RXF0E_1_BRS_Pos) +#define CAN_RXF0E_1_FDF_Pos 21 /**< \brief (CAN_RXF0E_1) FD Format */ +#define CAN_RXF0E_1_FDF (_U_(0x1) << CAN_RXF0E_1_FDF_Pos) +#define CAN_RXF0E_1_FIDX_Pos 24 /**< \brief (CAN_RXF0E_1) Filter Index */ +#define CAN_RXF0E_1_FIDX_Msk (_U_(0x7F) << CAN_RXF0E_1_FIDX_Pos) +#define CAN_RXF0E_1_FIDX(value) (CAN_RXF0E_1_FIDX_Msk & ((value) << CAN_RXF0E_1_FIDX_Pos)) +#define CAN_RXF0E_1_ANMF_Pos 31 /**< \brief (CAN_RXF0E_1) Accepted Non-matching Frame */ +#define CAN_RXF0E_1_ANMF (_U_(0x1) << CAN_RXF0E_1_ANMF_Pos) +#define CAN_RXF0E_1_MASK _U_(0xFF3FFFFF) /**< \brief (CAN_RXF0E_1) MASK Register */ + +/* -------- CAN_RXF0E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 0 Element Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */ + uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */ + uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */ + uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF0E_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF0E_DATA_OFFSET 0x08 /**< \brief (CAN_RXF0E_DATA offset) Rx FIFO 0 Element Data */ +#define CAN_RXF0E_DATA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF0E_DATA reset_value) Rx FIFO 0 Element Data */ + +#define CAN_RXF0E_DATA_DB0_Pos 0 /**< \brief (CAN_RXF0E_DATA) Data Byte 0 */ +#define CAN_RXF0E_DATA_DB0_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB0_Pos) +#define CAN_RXF0E_DATA_DB0(value) (CAN_RXF0E_DATA_DB0_Msk & ((value) << CAN_RXF0E_DATA_DB0_Pos)) +#define CAN_RXF0E_DATA_DB1_Pos 8 /**< \brief (CAN_RXF0E_DATA) Data Byte 1 */ +#define CAN_RXF0E_DATA_DB1_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB1_Pos) +#define CAN_RXF0E_DATA_DB1(value) (CAN_RXF0E_DATA_DB1_Msk & ((value) << CAN_RXF0E_DATA_DB1_Pos)) +#define CAN_RXF0E_DATA_DB2_Pos 16 /**< \brief (CAN_RXF0E_DATA) Data Byte 2 */ +#define CAN_RXF0E_DATA_DB2_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB2_Pos) +#define CAN_RXF0E_DATA_DB2(value) (CAN_RXF0E_DATA_DB2_Msk & ((value) << CAN_RXF0E_DATA_DB2_Pos)) +#define CAN_RXF0E_DATA_DB3_Pos 24 /**< \brief (CAN_RXF0E_DATA) Data Byte 3 */ +#define CAN_RXF0E_DATA_DB3_Msk (_U_(0xFF) << CAN_RXF0E_DATA_DB3_Pos) +#define CAN_RXF0E_DATA_DB3(value) (CAN_RXF0E_DATA_DB3_Msk & ((value) << CAN_RXF0E_DATA_DB3_Pos)) +#define CAN_RXF0E_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXF0E_DATA) MASK Register */ + +/* -------- CAN_RXF1E_0 : (CAN Offset: 0x00) (R/W 32) Rx FIFO 1 Element 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ID:29; /*!< bit: 0..28 Identifier */ + uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ + uint32_t XTD:1; /*!< bit: 30 Extended Identifier */ + uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF1E_0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF1E_0_OFFSET 0x00 /**< \brief (CAN_RXF1E_0 offset) Rx FIFO 1 Element 0 */ +#define CAN_RXF1E_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1E_0 reset_value) Rx FIFO 1 Element 0 */ + +#define CAN_RXF1E_0_ID_Pos 0 /**< \brief (CAN_RXF1E_0) Identifier */ +#define CAN_RXF1E_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_RXF1E_0_ID_Pos) +#define CAN_RXF1E_0_ID(value) (CAN_RXF1E_0_ID_Msk & ((value) << CAN_RXF1E_0_ID_Pos)) +#define CAN_RXF1E_0_RTR_Pos 29 /**< \brief (CAN_RXF1E_0) Remote Transmission Request */ +#define CAN_RXF1E_0_RTR (_U_(0x1) << CAN_RXF1E_0_RTR_Pos) +#define CAN_RXF1E_0_XTD_Pos 30 /**< \brief (CAN_RXF1E_0) Extended Identifier */ +#define CAN_RXF1E_0_XTD (_U_(0x1) << CAN_RXF1E_0_XTD_Pos) +#define CAN_RXF1E_0_ESI_Pos 31 /**< \brief (CAN_RXF1E_0) Error State Indicator */ +#define CAN_RXF1E_0_ESI (_U_(0x1) << CAN_RXF1E_0_ESI_Pos) +#define CAN_RXF1E_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXF1E_0) MASK Register */ + +/* -------- CAN_RXF1E_1 : (CAN Offset: 0x04) (R/W 32) Rx FIFO 1 Element 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t RXTS:16; /*!< bit: 0..15 Rx Timestamp */ + uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */ + uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ + uint32_t FDF:1; /*!< bit: 21 FD Format */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t FIDX:7; /*!< bit: 24..30 Filter Index */ + uint32_t ANMF:1; /*!< bit: 31 Accepted Non-matching Frame */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF1E_1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF1E_1_OFFSET 0x04 /**< \brief (CAN_RXF1E_1 offset) Rx FIFO 1 Element 1 */ +#define CAN_RXF1E_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1E_1 reset_value) Rx FIFO 1 Element 1 */ + +#define CAN_RXF1E_1_RXTS_Pos 0 /**< \brief (CAN_RXF1E_1) Rx Timestamp */ +#define CAN_RXF1E_1_RXTS_Msk (_U_(0xFFFF) << CAN_RXF1E_1_RXTS_Pos) +#define CAN_RXF1E_1_RXTS(value) (CAN_RXF1E_1_RXTS_Msk & ((value) << CAN_RXF1E_1_RXTS_Pos)) +#define CAN_RXF1E_1_DLC_Pos 16 /**< \brief (CAN_RXF1E_1) Data Length Code */ +#define CAN_RXF1E_1_DLC_Msk (_U_(0xF) << CAN_RXF1E_1_DLC_Pos) +#define CAN_RXF1E_1_DLC(value) (CAN_RXF1E_1_DLC_Msk & ((value) << CAN_RXF1E_1_DLC_Pos)) +#define CAN_RXF1E_1_BRS_Pos 20 /**< \brief (CAN_RXF1E_1) Bit Rate Search */ +#define CAN_RXF1E_1_BRS (_U_(0x1) << CAN_RXF1E_1_BRS_Pos) +#define CAN_RXF1E_1_FDF_Pos 21 /**< \brief (CAN_RXF1E_1) FD Format */ +#define CAN_RXF1E_1_FDF (_U_(0x1) << CAN_RXF1E_1_FDF_Pos) +#define CAN_RXF1E_1_FIDX_Pos 24 /**< \brief (CAN_RXF1E_1) Filter Index */ +#define CAN_RXF1E_1_FIDX_Msk (_U_(0x7F) << CAN_RXF1E_1_FIDX_Pos) +#define CAN_RXF1E_1_FIDX(value) (CAN_RXF1E_1_FIDX_Msk & ((value) << CAN_RXF1E_1_FIDX_Pos)) +#define CAN_RXF1E_1_ANMF_Pos 31 /**< \brief (CAN_RXF1E_1) Accepted Non-matching Frame */ +#define CAN_RXF1E_1_ANMF (_U_(0x1) << CAN_RXF1E_1_ANMF_Pos) +#define CAN_RXF1E_1_MASK _U_(0xFF3FFFFF) /**< \brief (CAN_RXF1E_1) MASK Register */ + +/* -------- CAN_RXF1E_DATA : (CAN Offset: 0x08) (R/W 32) Rx FIFO 1 Element Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */ + uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */ + uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */ + uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_RXF1E_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_RXF1E_DATA_OFFSET 0x08 /**< \brief (CAN_RXF1E_DATA offset) Rx FIFO 1 Element Data */ +#define CAN_RXF1E_DATA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_RXF1E_DATA reset_value) Rx FIFO 1 Element Data */ + +#define CAN_RXF1E_DATA_DB0_Pos 0 /**< \brief (CAN_RXF1E_DATA) Data Byte 0 */ +#define CAN_RXF1E_DATA_DB0_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB0_Pos) +#define CAN_RXF1E_DATA_DB0(value) (CAN_RXF1E_DATA_DB0_Msk & ((value) << CAN_RXF1E_DATA_DB0_Pos)) +#define CAN_RXF1E_DATA_DB1_Pos 8 /**< \brief (CAN_RXF1E_DATA) Data Byte 1 */ +#define CAN_RXF1E_DATA_DB1_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB1_Pos) +#define CAN_RXF1E_DATA_DB1(value) (CAN_RXF1E_DATA_DB1_Msk & ((value) << CAN_RXF1E_DATA_DB1_Pos)) +#define CAN_RXF1E_DATA_DB2_Pos 16 /**< \brief (CAN_RXF1E_DATA) Data Byte 2 */ +#define CAN_RXF1E_DATA_DB2_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB2_Pos) +#define CAN_RXF1E_DATA_DB2(value) (CAN_RXF1E_DATA_DB2_Msk & ((value) << CAN_RXF1E_DATA_DB2_Pos)) +#define CAN_RXF1E_DATA_DB3_Pos 24 /**< \brief (CAN_RXF1E_DATA) Data Byte 3 */ +#define CAN_RXF1E_DATA_DB3_Msk (_U_(0xFF) << CAN_RXF1E_DATA_DB3_Pos) +#define CAN_RXF1E_DATA_DB3(value) (CAN_RXF1E_DATA_DB3_Msk & ((value) << CAN_RXF1E_DATA_DB3_Pos)) +#define CAN_RXF1E_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_RXF1E_DATA) MASK Register */ + +/* -------- CAN_SIDFE_0 : (CAN Offset: 0x00) (R/W 32) Standard Message ID Filter Element -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SFID2:11; /*!< bit: 0..10 Standard Filter ID 2 */ + uint32_t :5; /*!< bit: 11..15 Reserved */ + uint32_t SFID1:11; /*!< bit: 16..26 Standard Filter ID 1 */ + uint32_t SFEC:3; /*!< bit: 27..29 Standard Filter Element Configuration */ + uint32_t SFT:2; /*!< bit: 30..31 Standard Filter Type */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_SIDFE_0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_SIDFE_0_OFFSET 0x00 /**< \brief (CAN_SIDFE_0 offset) Standard Message ID Filter Element */ +#define CAN_SIDFE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_SIDFE_0 reset_value) Standard Message ID Filter Element */ + +#define CAN_SIDFE_0_SFID2_Pos 0 /**< \brief (CAN_SIDFE_0) Standard Filter ID 2 */ +#define CAN_SIDFE_0_SFID2_Msk (_U_(0x7FF) << CAN_SIDFE_0_SFID2_Pos) +#define CAN_SIDFE_0_SFID2(value) (CAN_SIDFE_0_SFID2_Msk & ((value) << CAN_SIDFE_0_SFID2_Pos)) +#define CAN_SIDFE_0_SFID1_Pos 16 /**< \brief (CAN_SIDFE_0) Standard Filter ID 1 */ +#define CAN_SIDFE_0_SFID1_Msk (_U_(0x7FF) << CAN_SIDFE_0_SFID1_Pos) +#define CAN_SIDFE_0_SFID1(value) (CAN_SIDFE_0_SFID1_Msk & ((value) << CAN_SIDFE_0_SFID1_Pos)) +#define CAN_SIDFE_0_SFEC_Pos 27 /**< \brief (CAN_SIDFE_0) Standard Filter Element Configuration */ +#define CAN_SIDFE_0_SFEC_Msk (_U_(0x7) << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC(value) (CAN_SIDFE_0_SFEC_Msk & ((value) << CAN_SIDFE_0_SFEC_Pos)) +#define CAN_SIDFE_0_SFEC_DISABLE_Val _U_(0x0) /**< \brief (CAN_SIDFE_0) Disable filter element */ +#define CAN_SIDFE_0_SFEC_STF0M_Val _U_(0x1) /**< \brief (CAN_SIDFE_0) Store in Rx FIFO 0 if filter match */ +#define CAN_SIDFE_0_SFEC_STF1M_Val _U_(0x2) /**< \brief (CAN_SIDFE_0) Store in Rx FIFO 1 if filter match */ +#define CAN_SIDFE_0_SFEC_REJECT_Val _U_(0x3) /**< \brief (CAN_SIDFE_0) Reject ID if filter match */ +#define CAN_SIDFE_0_SFEC_PRIORITY_Val _U_(0x4) /**< \brief (CAN_SIDFE_0) Set priority if filter match */ +#define CAN_SIDFE_0_SFEC_PRIF0M_Val _U_(0x5) /**< \brief (CAN_SIDFE_0) Set priority and store in FIFO 0 if filter match */ +#define CAN_SIDFE_0_SFEC_PRIF1M_Val _U_(0x6) /**< \brief (CAN_SIDFE_0) Set priority and store in FIFO 1 if filter match */ +#define CAN_SIDFE_0_SFEC_STRXBUF_Val _U_(0x7) /**< \brief (CAN_SIDFE_0) Store into Rx Buffer */ +#define CAN_SIDFE_0_SFEC_DISABLE (CAN_SIDFE_0_SFEC_DISABLE_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC_STF0M (CAN_SIDFE_0_SFEC_STF0M_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC_STF1M (CAN_SIDFE_0_SFEC_STF1M_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC_REJECT (CAN_SIDFE_0_SFEC_REJECT_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC_PRIORITY (CAN_SIDFE_0_SFEC_PRIORITY_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC_PRIF0M (CAN_SIDFE_0_SFEC_PRIF0M_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC_PRIF1M (CAN_SIDFE_0_SFEC_PRIF1M_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFEC_STRXBUF (CAN_SIDFE_0_SFEC_STRXBUF_Val << CAN_SIDFE_0_SFEC_Pos) +#define CAN_SIDFE_0_SFT_Pos 30 /**< \brief (CAN_SIDFE_0) Standard Filter Type */ +#define CAN_SIDFE_0_SFT_Msk (_U_(0x3) << CAN_SIDFE_0_SFT_Pos) +#define CAN_SIDFE_0_SFT(value) (CAN_SIDFE_0_SFT_Msk & ((value) << CAN_SIDFE_0_SFT_Pos)) +#define CAN_SIDFE_0_SFT_RANGE_Val _U_(0x0) /**< \brief (CAN_SIDFE_0) Range filter from SFID1 to SFID2 */ +#define CAN_SIDFE_0_SFT_DUAL_Val _U_(0x1) /**< \brief (CAN_SIDFE_0) Dual ID filter for SFID1 or SFID2 */ +#define CAN_SIDFE_0_SFT_CLASSIC_Val _U_(0x2) /**< \brief (CAN_SIDFE_0) Classic filter */ +#define CAN_SIDFE_0_SFT_RANGE (CAN_SIDFE_0_SFT_RANGE_Val << CAN_SIDFE_0_SFT_Pos) +#define CAN_SIDFE_0_SFT_DUAL (CAN_SIDFE_0_SFT_DUAL_Val << CAN_SIDFE_0_SFT_Pos) +#define CAN_SIDFE_0_SFT_CLASSIC (CAN_SIDFE_0_SFT_CLASSIC_Val << CAN_SIDFE_0_SFT_Pos) +#define CAN_SIDFE_0_MASK _U_(0xFFFF07FF) /**< \brief (CAN_SIDFE_0) MASK Register */ + +/* -------- CAN_TXBE_0 : (CAN Offset: 0x00) (R/W 32) Tx Buffer Element 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ID:29; /*!< bit: 0..28 Identifier */ + uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ + uint32_t XTD:1; /*!< bit: 30 Extended Identifier */ + uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBE_0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBE_0_OFFSET 0x00 /**< \brief (CAN_TXBE_0 offset) Tx Buffer Element 0 */ +#define CAN_TXBE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBE_0 reset_value) Tx Buffer Element 0 */ + +#define CAN_TXBE_0_ID_Pos 0 /**< \brief (CAN_TXBE_0) Identifier */ +#define CAN_TXBE_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_TXBE_0_ID_Pos) +#define CAN_TXBE_0_ID(value) (CAN_TXBE_0_ID_Msk & ((value) << CAN_TXBE_0_ID_Pos)) +#define CAN_TXBE_0_RTR_Pos 29 /**< \brief (CAN_TXBE_0) Remote Transmission Request */ +#define CAN_TXBE_0_RTR (_U_(0x1) << CAN_TXBE_0_RTR_Pos) +#define CAN_TXBE_0_XTD_Pos 30 /**< \brief (CAN_TXBE_0) Extended Identifier */ +#define CAN_TXBE_0_XTD (_U_(0x1) << CAN_TXBE_0_XTD_Pos) +#define CAN_TXBE_0_ESI_Pos 31 /**< \brief (CAN_TXBE_0) Error State Indicator */ +#define CAN_TXBE_0_ESI (_U_(0x1) << CAN_TXBE_0_ESI_Pos) +#define CAN_TXBE_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBE_0) MASK Register */ + +/* -------- CAN_TXBE_1 : (CAN Offset: 0x04) (R/W 32) Tx Buffer Element 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :16; /*!< bit: 0..15 Reserved */ + uint32_t DLC:4; /*!< bit: 16..19 Identifier */ + uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ + uint32_t FDF:1; /*!< bit: 21 FD Format */ + uint32_t :1; /*!< bit: 22 Reserved */ + uint32_t EFC:1; /*!< bit: 23 Event FIFO Control */ + uint32_t MM:8; /*!< bit: 24..31 Message Marker */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBE_1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBE_1_OFFSET 0x04 /**< \brief (CAN_TXBE_1 offset) Tx Buffer Element 1 */ +#define CAN_TXBE_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBE_1 reset_value) Tx Buffer Element 1 */ + +#define CAN_TXBE_1_DLC_Pos 16 /**< \brief (CAN_TXBE_1) Identifier */ +#define CAN_TXBE_1_DLC_Msk (_U_(0xF) << CAN_TXBE_1_DLC_Pos) +#define CAN_TXBE_1_DLC(value) (CAN_TXBE_1_DLC_Msk & ((value) << CAN_TXBE_1_DLC_Pos)) +#define CAN_TXBE_1_BRS_Pos 20 /**< \brief (CAN_TXBE_1) Bit Rate Search */ +#define CAN_TXBE_1_BRS (_U_(0x1) << CAN_TXBE_1_BRS_Pos) +#define CAN_TXBE_1_FDF_Pos 21 /**< \brief (CAN_TXBE_1) FD Format */ +#define CAN_TXBE_1_FDF (_U_(0x1) << CAN_TXBE_1_FDF_Pos) +#define CAN_TXBE_1_EFC_Pos 23 /**< \brief (CAN_TXBE_1) Event FIFO Control */ +#define CAN_TXBE_1_EFC (_U_(0x1) << CAN_TXBE_1_EFC_Pos) +#define CAN_TXBE_1_MM_Pos 24 /**< \brief (CAN_TXBE_1) Message Marker */ +#define CAN_TXBE_1_MM_Msk (_U_(0xFF) << CAN_TXBE_1_MM_Pos) +#define CAN_TXBE_1_MM(value) (CAN_TXBE_1_MM_Msk & ((value) << CAN_TXBE_1_MM_Pos)) +#define CAN_TXBE_1_MASK _U_(0xFFBF0000) /**< \brief (CAN_TXBE_1) MASK Register */ + +/* -------- CAN_TXBE_DATA : (CAN Offset: 0x08) (R/W 32) Tx Buffer Element Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t DB0:8; /*!< bit: 0.. 7 Data Byte 0 */ + uint32_t DB1:8; /*!< bit: 8..15 Data Byte 1 */ + uint32_t DB2:8; /*!< bit: 16..23 Data Byte 2 */ + uint32_t DB3:8; /*!< bit: 24..31 Data Byte 3 */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXBE_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXBE_DATA_OFFSET 0x08 /**< \brief (CAN_TXBE_DATA offset) Tx Buffer Element Data */ +#define CAN_TXBE_DATA_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXBE_DATA reset_value) Tx Buffer Element Data */ + +#define CAN_TXBE_DATA_DB0_Pos 0 /**< \brief (CAN_TXBE_DATA) Data Byte 0 */ +#define CAN_TXBE_DATA_DB0_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB0_Pos) +#define CAN_TXBE_DATA_DB0(value) (CAN_TXBE_DATA_DB0_Msk & ((value) << CAN_TXBE_DATA_DB0_Pos)) +#define CAN_TXBE_DATA_DB1_Pos 8 /**< \brief (CAN_TXBE_DATA) Data Byte 1 */ +#define CAN_TXBE_DATA_DB1_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB1_Pos) +#define CAN_TXBE_DATA_DB1(value) (CAN_TXBE_DATA_DB1_Msk & ((value) << CAN_TXBE_DATA_DB1_Pos)) +#define CAN_TXBE_DATA_DB2_Pos 16 /**< \brief (CAN_TXBE_DATA) Data Byte 2 */ +#define CAN_TXBE_DATA_DB2_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB2_Pos) +#define CAN_TXBE_DATA_DB2(value) (CAN_TXBE_DATA_DB2_Msk & ((value) << CAN_TXBE_DATA_DB2_Pos)) +#define CAN_TXBE_DATA_DB3_Pos 24 /**< \brief (CAN_TXBE_DATA) Data Byte 3 */ +#define CAN_TXBE_DATA_DB3_Msk (_U_(0xFF) << CAN_TXBE_DATA_DB3_Pos) +#define CAN_TXBE_DATA_DB3(value) (CAN_TXBE_DATA_DB3_Msk & ((value) << CAN_TXBE_DATA_DB3_Pos)) +#define CAN_TXBE_DATA_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXBE_DATA) MASK Register */ + +/* -------- CAN_TXEFE_0 : (CAN Offset: 0x00) (R/W 32) Tx Event FIFO Element 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t ID:29; /*!< bit: 0..28 Identifier */ + uint32_t RTR:1; /*!< bit: 29 Remote Transmission Request */ + uint32_t XTD:1; /*!< bit: 30 Extended Indentifier */ + uint32_t ESI:1; /*!< bit: 31 Error State Indicator */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXEFE_0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXEFE_0_OFFSET 0x00 /**< \brief (CAN_TXEFE_0 offset) Tx Event FIFO Element 0 */ +#define CAN_TXEFE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFE_0 reset_value) Tx Event FIFO Element 0 */ + +#define CAN_TXEFE_0_ID_Pos 0 /**< \brief (CAN_TXEFE_0) Identifier */ +#define CAN_TXEFE_0_ID_Msk (_U_(0x1FFFFFFF) << CAN_TXEFE_0_ID_Pos) +#define CAN_TXEFE_0_ID(value) (CAN_TXEFE_0_ID_Msk & ((value) << CAN_TXEFE_0_ID_Pos)) +#define CAN_TXEFE_0_RTR_Pos 29 /**< \brief (CAN_TXEFE_0) Remote Transmission Request */ +#define CAN_TXEFE_0_RTR (_U_(0x1) << CAN_TXEFE_0_RTR_Pos) +#define CAN_TXEFE_0_XTD_Pos 30 /**< \brief (CAN_TXEFE_0) Extended Indentifier */ +#define CAN_TXEFE_0_XTD (_U_(0x1) << CAN_TXEFE_0_XTD_Pos) +#define CAN_TXEFE_0_ESI_Pos 31 /**< \brief (CAN_TXEFE_0) Error State Indicator */ +#define CAN_TXEFE_0_ESI (_U_(0x1) << CAN_TXEFE_0_ESI_Pos) +#define CAN_TXEFE_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXEFE_0) MASK Register */ + +/* -------- CAN_TXEFE_1 : (CAN Offset: 0x04) (R/W 32) Tx Event FIFO Element 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t TXTS:16; /*!< bit: 0..15 Tx Timestamp */ + uint32_t DLC:4; /*!< bit: 16..19 Data Length Code */ + uint32_t BRS:1; /*!< bit: 20 Bit Rate Search */ + uint32_t FDF:1; /*!< bit: 21 FD Format */ + uint32_t ET:2; /*!< bit: 22..23 Event Type */ + uint32_t MM:8; /*!< bit: 24..31 Message Marker */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_TXEFE_1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_TXEFE_1_OFFSET 0x04 /**< \brief (CAN_TXEFE_1 offset) Tx Event FIFO Element 1 */ +#define CAN_TXEFE_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_TXEFE_1 reset_value) Tx Event FIFO Element 1 */ + +#define CAN_TXEFE_1_TXTS_Pos 0 /**< \brief (CAN_TXEFE_1) Tx Timestamp */ +#define CAN_TXEFE_1_TXTS_Msk (_U_(0xFFFF) << CAN_TXEFE_1_TXTS_Pos) +#define CAN_TXEFE_1_TXTS(value) (CAN_TXEFE_1_TXTS_Msk & ((value) << CAN_TXEFE_1_TXTS_Pos)) +#define CAN_TXEFE_1_DLC_Pos 16 /**< \brief (CAN_TXEFE_1) Data Length Code */ +#define CAN_TXEFE_1_DLC_Msk (_U_(0xF) << CAN_TXEFE_1_DLC_Pos) +#define CAN_TXEFE_1_DLC(value) (CAN_TXEFE_1_DLC_Msk & ((value) << CAN_TXEFE_1_DLC_Pos)) +#define CAN_TXEFE_1_BRS_Pos 20 /**< \brief (CAN_TXEFE_1) Bit Rate Search */ +#define CAN_TXEFE_1_BRS (_U_(0x1) << CAN_TXEFE_1_BRS_Pos) +#define CAN_TXEFE_1_FDF_Pos 21 /**< \brief (CAN_TXEFE_1) FD Format */ +#define CAN_TXEFE_1_FDF (_U_(0x1) << CAN_TXEFE_1_FDF_Pos) +#define CAN_TXEFE_1_ET_Pos 22 /**< \brief (CAN_TXEFE_1) Event Type */ +#define CAN_TXEFE_1_ET_Msk (_U_(0x3) << CAN_TXEFE_1_ET_Pos) +#define CAN_TXEFE_1_ET(value) (CAN_TXEFE_1_ET_Msk & ((value) << CAN_TXEFE_1_ET_Pos)) +#define CAN_TXEFE_1_ET_TXE_Val _U_(0x1) /**< \brief (CAN_TXEFE_1) Tx event */ +#define CAN_TXEFE_1_ET_TXC_Val _U_(0x2) /**< \brief (CAN_TXEFE_1) Transmission in spite of cancellation */ +#define CAN_TXEFE_1_ET_TXE (CAN_TXEFE_1_ET_TXE_Val << CAN_TXEFE_1_ET_Pos) +#define CAN_TXEFE_1_ET_TXC (CAN_TXEFE_1_ET_TXC_Val << CAN_TXEFE_1_ET_Pos) +#define CAN_TXEFE_1_MM_Pos 24 /**< \brief (CAN_TXEFE_1) Message Marker */ +#define CAN_TXEFE_1_MM_Msk (_U_(0xFF) << CAN_TXEFE_1_MM_Pos) +#define CAN_TXEFE_1_MM(value) (CAN_TXEFE_1_MM_Msk & ((value) << CAN_TXEFE_1_MM_Pos)) +#define CAN_TXEFE_1_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_TXEFE_1) MASK Register */ + +/* -------- CAN_XIDFE_0 : (CAN Offset: 0x00) (R/W 32) Extended Message ID Filter Element 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EFID1:29; /*!< bit: 0..28 Extended Filter ID 1 */ + uint32_t EFEC:3; /*!< bit: 29..31 Extended Filter Element Configuration */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_XIDFE_0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_XIDFE_0_OFFSET 0x00 /**< \brief (CAN_XIDFE_0 offset) Extended Message ID Filter Element 0 */ +#define CAN_XIDFE_0_RESETVALUE _U_(0x00000000) /**< \brief (CAN_XIDFE_0 reset_value) Extended Message ID Filter Element 0 */ + +#define CAN_XIDFE_0_EFID1_Pos 0 /**< \brief (CAN_XIDFE_0) Extended Filter ID 1 */ +#define CAN_XIDFE_0_EFID1_Msk (_U_(0x1FFFFFFF) << CAN_XIDFE_0_EFID1_Pos) +#define CAN_XIDFE_0_EFID1(value) (CAN_XIDFE_0_EFID1_Msk & ((value) << CAN_XIDFE_0_EFID1_Pos)) +#define CAN_XIDFE_0_EFEC_Pos 29 /**< \brief (CAN_XIDFE_0) Extended Filter Element Configuration */ +#define CAN_XIDFE_0_EFEC_Msk (_U_(0x7) << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC(value) (CAN_XIDFE_0_EFEC_Msk & ((value) << CAN_XIDFE_0_EFEC_Pos)) +#define CAN_XIDFE_0_EFEC_DISABLE_Val _U_(0x0) /**< \brief (CAN_XIDFE_0) Disable filter element */ +#define CAN_XIDFE_0_EFEC_STF0M_Val _U_(0x1) /**< \brief (CAN_XIDFE_0) Store in Rx FIFO 0 if filter match */ +#define CAN_XIDFE_0_EFEC_STF1M_Val _U_(0x2) /**< \brief (CAN_XIDFE_0) Store in Rx FIFO 1 if filter match */ +#define CAN_XIDFE_0_EFEC_REJECT_Val _U_(0x3) /**< \brief (CAN_XIDFE_0) Reject ID if filter match */ +#define CAN_XIDFE_0_EFEC_PRIORITY_Val _U_(0x4) /**< \brief (CAN_XIDFE_0) Set priority if filter match */ +#define CAN_XIDFE_0_EFEC_PRIF0M_Val _U_(0x5) /**< \brief (CAN_XIDFE_0) Set priority and store in FIFO 0 if filter match */ +#define CAN_XIDFE_0_EFEC_PRIF1M_Val _U_(0x6) /**< \brief (CAN_XIDFE_0) Set priority and store in FIFO 1 if filter match */ +#define CAN_XIDFE_0_EFEC_STRXBUF_Val _U_(0x7) /**< \brief (CAN_XIDFE_0) Store into Rx Buffer */ +#define CAN_XIDFE_0_EFEC_DISABLE (CAN_XIDFE_0_EFEC_DISABLE_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC_STF0M (CAN_XIDFE_0_EFEC_STF0M_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC_STF1M (CAN_XIDFE_0_EFEC_STF1M_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC_REJECT (CAN_XIDFE_0_EFEC_REJECT_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC_PRIORITY (CAN_XIDFE_0_EFEC_PRIORITY_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC_PRIF0M (CAN_XIDFE_0_EFEC_PRIF0M_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC_PRIF1M (CAN_XIDFE_0_EFEC_PRIF1M_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_EFEC_STRXBUF (CAN_XIDFE_0_EFEC_STRXBUF_Val << CAN_XIDFE_0_EFEC_Pos) +#define CAN_XIDFE_0_MASK _U_(0xFFFFFFFF) /**< \brief (CAN_XIDFE_0) MASK Register */ + +/* -------- CAN_XIDFE_1 : (CAN Offset: 0x04) (R/W 32) Extended Message ID Filter Element 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EFID2:29; /*!< bit: 0..28 Extended Filter ID 2 */ + uint32_t :1; /*!< bit: 29 Reserved */ + uint32_t EFT:2; /*!< bit: 30..31 Extended Filter Type */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CAN_XIDFE_1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CAN_XIDFE_1_OFFSET 0x04 /**< \brief (CAN_XIDFE_1 offset) Extended Message ID Filter Element 1 */ +#define CAN_XIDFE_1_RESETVALUE _U_(0x00000000) /**< \brief (CAN_XIDFE_1 reset_value) Extended Message ID Filter Element 1 */ + +#define CAN_XIDFE_1_EFID2_Pos 0 /**< \brief (CAN_XIDFE_1) Extended Filter ID 2 */ +#define CAN_XIDFE_1_EFID2_Msk (_U_(0x1FFFFFFF) << CAN_XIDFE_1_EFID2_Pos) +#define CAN_XIDFE_1_EFID2(value) (CAN_XIDFE_1_EFID2_Msk & ((value) << CAN_XIDFE_1_EFID2_Pos)) +#define CAN_XIDFE_1_EFT_Pos 30 /**< \brief (CAN_XIDFE_1) Extended Filter Type */ +#define CAN_XIDFE_1_EFT_Msk (_U_(0x3) << CAN_XIDFE_1_EFT_Pos) +#define CAN_XIDFE_1_EFT(value) (CAN_XIDFE_1_EFT_Msk & ((value) << CAN_XIDFE_1_EFT_Pos)) +#define CAN_XIDFE_1_EFT_RANGEM_Val _U_(0x0) /**< \brief (CAN_XIDFE_1) Range filter from EFID1 to EFID2 */ +#define CAN_XIDFE_1_EFT_DUAL_Val _U_(0x1) /**< \brief (CAN_XIDFE_1) Dual ID filter for EFID1 or EFID2 */ +#define CAN_XIDFE_1_EFT_CLASSIC_Val _U_(0x2) /**< \brief (CAN_XIDFE_1) Classic filter */ +#define CAN_XIDFE_1_EFT_RANGE_Val _U_(0x3) /**< \brief (CAN_XIDFE_1) Range filter from EFID1 to EFID2 with no XIDAM mask */ +#define CAN_XIDFE_1_EFT_RANGEM (CAN_XIDFE_1_EFT_RANGEM_Val << CAN_XIDFE_1_EFT_Pos) +#define CAN_XIDFE_1_EFT_DUAL (CAN_XIDFE_1_EFT_DUAL_Val << CAN_XIDFE_1_EFT_Pos) +#define CAN_XIDFE_1_EFT_CLASSIC (CAN_XIDFE_1_EFT_CLASSIC_Val << CAN_XIDFE_1_EFT_Pos) +#define CAN_XIDFE_1_EFT_RANGE (CAN_XIDFE_1_EFT_RANGE_Val << CAN_XIDFE_1_EFT_Pos) +#define CAN_XIDFE_1_MASK _U_(0xDFFFFFFF) /**< \brief (CAN_XIDFE_1) MASK Register */ + +/** \brief CAN APB hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __I CAN_CREL_Type CREL; /**< \brief Offset: 0x00 (R/ 32) Core Release */ + __I CAN_ENDN_Type ENDN; /**< \brief Offset: 0x04 (R/ 32) Endian */ + __IO CAN_MRCFG_Type MRCFG; /**< \brief Offset: 0x08 (R/W 32) Message RAM Configuration */ + __IO CAN_DBTP_Type DBTP; /**< \brief Offset: 0x0C (R/W 32) Fast Bit Timing and Prescaler */ + __IO CAN_TEST_Type TEST; /**< \brief Offset: 0x10 (R/W 32) Test */ + __IO CAN_RWD_Type RWD; /**< \brief Offset: 0x14 (R/W 32) RAM Watchdog */ + __IO CAN_CCCR_Type CCCR; /**< \brief Offset: 0x18 (R/W 32) CC Control */ + __IO CAN_NBTP_Type NBTP; /**< \brief Offset: 0x1C (R/W 32) Nominal Bit Timing and Prescaler */ + __IO CAN_TSCC_Type TSCC; /**< \brief Offset: 0x20 (R/W 32) Timestamp Counter Configuration */ + __I CAN_TSCV_Type TSCV; /**< \brief Offset: 0x24 (R/ 32) Timestamp Counter Value */ + __IO CAN_TOCC_Type TOCC; /**< \brief Offset: 0x28 (R/W 32) Timeout Counter Configuration */ + __IO CAN_TOCV_Type TOCV; /**< \brief Offset: 0x2C (R/W 32) Timeout Counter Value */ + RoReg8 Reserved1[0x10]; + __I CAN_ECR_Type ECR; /**< \brief Offset: 0x40 (R/ 32) Error Counter */ + __I CAN_PSR_Type PSR; /**< \brief Offset: 0x44 (R/ 32) Protocol Status */ + __IO CAN_TDCR_Type TDCR; /**< \brief Offset: 0x48 (R/W 32) Extended ID Filter Configuration */ + RoReg8 Reserved2[0x4]; + __IO CAN_IR_Type IR; /**< \brief Offset: 0x50 (R/W 32) Interrupt */ + __IO CAN_IE_Type IE; /**< \brief Offset: 0x54 (R/W 32) Interrupt Enable */ + __IO CAN_ILS_Type ILS; /**< \brief Offset: 0x58 (R/W 32) Interrupt Line Select */ + __IO CAN_ILE_Type ILE; /**< \brief Offset: 0x5C (R/W 32) Interrupt Line Enable */ + RoReg8 Reserved3[0x20]; + __IO CAN_GFC_Type GFC; /**< \brief Offset: 0x80 (R/W 32) Global Filter Configuration */ + __IO CAN_SIDFC_Type SIDFC; /**< \brief Offset: 0x84 (R/W 32) Standard ID Filter Configuration */ + __IO CAN_XIDFC_Type XIDFC; /**< \brief Offset: 0x88 (R/W 32) Extended ID Filter Configuration */ + RoReg8 Reserved4[0x4]; + __IO CAN_XIDAM_Type XIDAM; /**< \brief Offset: 0x90 (R/W 32) Extended ID AND Mask */ + __I CAN_HPMS_Type HPMS; /**< \brief Offset: 0x94 (R/ 32) High Priority Message Status */ + __IO CAN_NDAT1_Type NDAT1; /**< \brief Offset: 0x98 (R/W 32) New Data 1 */ + __IO CAN_NDAT2_Type NDAT2; /**< \brief Offset: 0x9C (R/W 32) New Data 2 */ + __IO CAN_RXF0C_Type RXF0C; /**< \brief Offset: 0xA0 (R/W 32) Rx FIFO 0 Configuration */ + __I CAN_RXF0S_Type RXF0S; /**< \brief Offset: 0xA4 (R/ 32) Rx FIFO 0 Status */ + __IO CAN_RXF0A_Type RXF0A; /**< \brief Offset: 0xA8 (R/W 32) Rx FIFO 0 Acknowledge */ + __IO CAN_RXBC_Type RXBC; /**< \brief Offset: 0xAC (R/W 32) Rx Buffer Configuration */ + __IO CAN_RXF1C_Type RXF1C; /**< \brief Offset: 0xB0 (R/W 32) Rx FIFO 1 Configuration */ + __I CAN_RXF1S_Type RXF1S; /**< \brief Offset: 0xB4 (R/ 32) Rx FIFO 1 Status */ + __IO CAN_RXF1A_Type RXF1A; /**< \brief Offset: 0xB8 (R/W 32) Rx FIFO 1 Acknowledge */ + __IO CAN_RXESC_Type RXESC; /**< \brief Offset: 0xBC (R/W 32) Rx Buffer / FIFO Element Size Configuration */ + __IO CAN_TXBC_Type TXBC; /**< \brief Offset: 0xC0 (R/W 32) Tx Buffer Configuration */ + __I CAN_TXFQS_Type TXFQS; /**< \brief Offset: 0xC4 (R/ 32) Tx FIFO / Queue Status */ + __IO CAN_TXESC_Type TXESC; /**< \brief Offset: 0xC8 (R/W 32) Tx Buffer Element Size Configuration */ + __I CAN_TXBRP_Type TXBRP; /**< \brief Offset: 0xCC (R/ 32) Tx Buffer Request Pending */ + __IO CAN_TXBAR_Type TXBAR; /**< \brief Offset: 0xD0 (R/W 32) Tx Buffer Add Request */ + __IO CAN_TXBCR_Type TXBCR; /**< \brief Offset: 0xD4 (R/W 32) Tx Buffer Cancellation Request */ + __I CAN_TXBTO_Type TXBTO; /**< \brief Offset: 0xD8 (R/ 32) Tx Buffer Transmission Occurred */ + __I CAN_TXBCF_Type TXBCF; /**< \brief Offset: 0xDC (R/ 32) Tx Buffer Cancellation Finished */ + __IO CAN_TXBTIE_Type TXBTIE; /**< \brief Offset: 0xE0 (R/W 32) Tx Buffer Transmission Interrupt Enable */ + __IO CAN_TXBCIE_Type TXBCIE; /**< \brief Offset: 0xE4 (R/W 32) Tx Buffer Cancellation Finished Interrupt Enable */ + RoReg8 Reserved5[0x8]; + __IO CAN_TXEFC_Type TXEFC; /**< \brief Offset: 0xF0 (R/W 32) Tx Event FIFO Configuration */ + __I CAN_TXEFS_Type TXEFS; /**< \brief Offset: 0xF4 (R/ 32) Tx Event FIFO Status */ + __IO CAN_TXEFA_Type TXEFA; /**< \brief Offset: 0xF8 (R/W 32) Tx Event FIFO Acknowledge */ +} Can; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief CAN Mram_rxbe hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CAN_RXBE_0_Type RXBE_0; /**< \brief Offset: 0x00 (R/W 32) Rx Buffer Element 0 */ + __IO CAN_RXBE_1_Type RXBE_1; /**< \brief Offset: 0x04 (R/W 32) Rx Buffer Element 1 */ + __IO CAN_RXBE_DATA_Type RXBE_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx Buffer Element Data */ +} CanMramRxbe +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief CAN Mram_rxf0e hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CAN_RXF0E_0_Type RXF0E_0; /**< \brief Offset: 0x00 (R/W 32) Rx FIFO 0 Element 0 */ + __IO CAN_RXF0E_1_Type RXF0E_1; /**< \brief Offset: 0x04 (R/W 32) Rx FIFO 0 Element 1 */ + __IO CAN_RXF0E_DATA_Type RXF0E_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx FIFO 0 Element Data */ +} CanMramRxf0e +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief CAN Mram_rxf1e hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CAN_RXF1E_0_Type RXF1E_0; /**< \brief Offset: 0x00 (R/W 32) Rx FIFO 1 Element 0 */ + __IO CAN_RXF1E_1_Type RXF1E_1; /**< \brief Offset: 0x04 (R/W 32) Rx FIFO 1 Element 1 */ + __IO CAN_RXF1E_DATA_Type RXF1E_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Rx FIFO 1 Element Data */ +} CanMramRxf1e +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief CAN Mram_sidfe hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CAN_SIDFE_0_Type SIDFE_0; /**< \brief Offset: 0x00 (R/W 32) Standard Message ID Filter Element */ +} CanMramSidfe +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief CAN Mram_txbe hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CAN_TXBE_0_Type TXBE_0; /**< \brief Offset: 0x00 (R/W 32) Tx Buffer Element 0 */ + __IO CAN_TXBE_1_Type TXBE_1; /**< \brief Offset: 0x04 (R/W 32) Tx Buffer Element 1 */ + __IO CAN_TXBE_DATA_Type TXBE_DATA[16]; /**< \brief Offset: 0x08 (R/W 32) Tx Buffer Element Data */ +} CanMramTxbe +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief CAN Mram_txefe hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CAN_TXEFE_0_Type TXEFE_0; /**< \brief Offset: 0x00 (R/W 32) Tx Event FIFO Element 0 */ + __IO CAN_TXEFE_1_Type TXEFE_1; /**< \brief Offset: 0x04 (R/W 32) Tx Event FIFO Element 1 */ +} CanMramTxefe +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/** \brief CAN Mram_xifde hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CAN_XIDFE_0_Type XIDFE_0; /**< \brief Offset: 0x00 (R/W 32) Extended Message ID Filter Element 0 */ + __IO CAN_XIDFE_1_Type XIDFE_1; /**< \brief Offset: 0x04 (R/W 32) Extended Message ID Filter Element 1 */ +} CanMramXifde +#ifdef __GNUC__ + __attribute__ ((aligned (4))) +#endif +; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define SECTION_CAN_MRAM_RXBE +#define SECTION_CAN_MRAM_RXF0E +#define SECTION_CAN_MRAM_RXF1E +#define SECTION_CAN_MRAM_SIDFE +#define SECTION_CAN_MRAM_TXBE +#define SECTION_CAN_MRAM_TXEFE +#define SECTION_CAN_MRAM_XIFDE + +/*@}*/ + +#endif /* _SAME54_CAN_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/include/component/ccl.h b/software/firmware/oracle_same54n19a/include/component/ccl.h new file mode 100644 index 00000000..b5dbb9ab --- /dev/null +++ b/software/firmware/oracle_same54n19a/include/component/ccl.h @@ -0,0 +1,228 @@ +/** + * \file + * + * \brief Component description for CCL + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54_CCL_COMPONENT_ +#define _SAME54_CCL_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR CCL */ +/* ========================================================================== */ +/** \addtogroup SAME54_CCL Configurable Custom Logic */ +/*@{*/ + +#define CCL_U2225 +#define REV_CCL 0x110 + +/* -------- CCL_CTRL : (CCL Offset: 0x0) (R/W 8) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable */ + uint8_t :4; /*!< bit: 2.. 5 Reserved */ + uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint8_t :1; /*!< bit: 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} CCL_CTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCL_CTRL_OFFSET 0x0 /**< \brief (CCL_CTRL offset) Control */ +#define CCL_CTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_CTRL reset_value) Control */ + +#define CCL_CTRL_SWRST_Pos 0 /**< \brief (CCL_CTRL) Software Reset */ +#define CCL_CTRL_SWRST (_U_(0x1) << CCL_CTRL_SWRST_Pos) +#define CCL_CTRL_ENABLE_Pos 1 /**< \brief (CCL_CTRL) Enable */ +#define CCL_CTRL_ENABLE (_U_(0x1) << CCL_CTRL_ENABLE_Pos) +#define CCL_CTRL_RUNSTDBY_Pos 6 /**< \brief (CCL_CTRL) Run in Standby */ +#define CCL_CTRL_RUNSTDBY (_U_(0x1) << CCL_CTRL_RUNSTDBY_Pos) +#define CCL_CTRL_MASK _U_(0x43) /**< \brief (CCL_CTRL) MASK Register */ + +/* -------- CCL_SEQCTRL : (CCL Offset: 0x4) (R/W 8) SEQ Control x -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SEQSEL:4; /*!< bit: 0.. 3 Sequential Selection */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} CCL_SEQCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCL_SEQCTRL_OFFSET 0x4 /**< \brief (CCL_SEQCTRL offset) SEQ Control x */ +#define CCL_SEQCTRL_RESETVALUE _U_(0x00) /**< \brief (CCL_SEQCTRL reset_value) SEQ Control x */ + +#define CCL_SEQCTRL_SEQSEL_Pos 0 /**< \brief (CCL_SEQCTRL) Sequential Selection */ +#define CCL_SEQCTRL_SEQSEL_Msk (_U_(0xF) << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL(value) (CCL_SEQCTRL_SEQSEL_Msk & ((value) << CCL_SEQCTRL_SEQSEL_Pos)) +#define CCL_SEQCTRL_SEQSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_SEQCTRL) Sequential logic is disabled */ +#define CCL_SEQCTRL_SEQSEL_DFF_Val _U_(0x1) /**< \brief (CCL_SEQCTRL) D flip flop */ +#define CCL_SEQCTRL_SEQSEL_JK_Val _U_(0x2) /**< \brief (CCL_SEQCTRL) JK flip flop */ +#define CCL_SEQCTRL_SEQSEL_LATCH_Val _U_(0x3) /**< \brief (CCL_SEQCTRL) D latch */ +#define CCL_SEQCTRL_SEQSEL_RS_Val _U_(0x4) /**< \brief (CCL_SEQCTRL) RS latch */ +#define CCL_SEQCTRL_SEQSEL_DISABLE (CCL_SEQCTRL_SEQSEL_DISABLE_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_DFF (CCL_SEQCTRL_SEQSEL_DFF_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_JK (CCL_SEQCTRL_SEQSEL_JK_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_LATCH (CCL_SEQCTRL_SEQSEL_LATCH_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_SEQSEL_RS (CCL_SEQCTRL_SEQSEL_RS_Val << CCL_SEQCTRL_SEQSEL_Pos) +#define CCL_SEQCTRL_MASK _U_(0x0F) /**< \brief (CCL_SEQCTRL) MASK Register */ + +/* -------- CCL_LUTCTRL : (CCL Offset: 0x8) (R/W 32) LUT Control x -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ENABLE:1; /*!< bit: 1 LUT Enable */ + uint32_t :2; /*!< bit: 2.. 3 Reserved */ + uint32_t FILTSEL:2; /*!< bit: 4.. 5 Filter Selection */ + uint32_t :1; /*!< bit: 6 Reserved */ + uint32_t EDGESEL:1; /*!< bit: 7 Edge Selection */ + uint32_t INSEL0:4; /*!< bit: 8..11 Input Selection 0 */ + uint32_t INSEL1:4; /*!< bit: 12..15 Input Selection 1 */ + uint32_t INSEL2:4; /*!< bit: 16..19 Input Selection 2 */ + uint32_t INVEI:1; /*!< bit: 20 Inverted Event Input Enable */ + uint32_t LUTEI:1; /*!< bit: 21 LUT Event Input Enable */ + uint32_t LUTEO:1; /*!< bit: 22 LUT Event Output Enable */ + uint32_t :1; /*!< bit: 23 Reserved */ + uint32_t TRUTH:8; /*!< bit: 24..31 Truth Value */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CCL_LUTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CCL_LUTCTRL_OFFSET 0x8 /**< \brief (CCL_LUTCTRL offset) LUT Control x */ +#define CCL_LUTCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CCL_LUTCTRL reset_value) LUT Control x */ + +#define CCL_LUTCTRL_ENABLE_Pos 1 /**< \brief (CCL_LUTCTRL) LUT Enable */ +#define CCL_LUTCTRL_ENABLE (_U_(0x1) << CCL_LUTCTRL_ENABLE_Pos) +#define CCL_LUTCTRL_FILTSEL_Pos 4 /**< \brief (CCL_LUTCTRL) Filter Selection */ +#define CCL_LUTCTRL_FILTSEL_Msk (_U_(0x3) << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_FILTSEL(value) (CCL_LUTCTRL_FILTSEL_Msk & ((value) << CCL_LUTCTRL_FILTSEL_Pos)) +#define CCL_LUTCTRL_FILTSEL_DISABLE_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Filter disabled */ +#define CCL_LUTCTRL_FILTSEL_SYNCH_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Synchronizer enabled */ +#define CCL_LUTCTRL_FILTSEL_FILTER_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Filter enabled */ +#define CCL_LUTCTRL_FILTSEL_DISABLE (CCL_LUTCTRL_FILTSEL_DISABLE_Val << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_FILTSEL_SYNCH (CCL_LUTCTRL_FILTSEL_SYNCH_Val << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_FILTSEL_FILTER (CCL_LUTCTRL_FILTSEL_FILTER_Val << CCL_LUTCTRL_FILTSEL_Pos) +#define CCL_LUTCTRL_EDGESEL_Pos 7 /**< \brief (CCL_LUTCTRL) Edge Selection */ +#define CCL_LUTCTRL_EDGESEL (_U_(0x1) << CCL_LUTCTRL_EDGESEL_Pos) +#define CCL_LUTCTRL_INSEL0_Pos 8 /**< \brief (CCL_LUTCTRL) Input Selection 0 */ +#define CCL_LUTCTRL_INSEL0_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0(value) (CCL_LUTCTRL_INSEL0_Msk & ((value) << CCL_LUTCTRL_INSEL0_Pos)) +#define CCL_LUTCTRL_INSEL0_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL0_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL0_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL0_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL0_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL0_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL0_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL0_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL0_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ +#define CCL_LUTCTRL_INSEL0_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL0_MASK (CCL_LUTCTRL_INSEL0_MASK_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_FEEDBACK (CCL_LUTCTRL_INSEL0_FEEDBACK_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_LINK (CCL_LUTCTRL_INSEL0_LINK_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_EVENT (CCL_LUTCTRL_INSEL0_EVENT_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_IO (CCL_LUTCTRL_INSEL0_IO_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_AC (CCL_LUTCTRL_INSEL0_AC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_TC (CCL_LUTCTRL_INSEL0_TC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_ALTTC (CCL_LUTCTRL_INSEL0_ALTTC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_TCC (CCL_LUTCTRL_INSEL0_TCC_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL0_SERCOM (CCL_LUTCTRL_INSEL0_SERCOM_Val << CCL_LUTCTRL_INSEL0_Pos) +#define CCL_LUTCTRL_INSEL1_Pos 12 /**< \brief (CCL_LUTCTRL) Input Selection 1 */ +#define CCL_LUTCTRL_INSEL1_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1(value) (CCL_LUTCTRL_INSEL1_Msk & ((value) << CCL_LUTCTRL_INSEL1_Pos)) +#define CCL_LUTCTRL_INSEL1_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL1_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL1_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL1_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL1_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL1_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL1_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL1_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL1_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ +#define CCL_LUTCTRL_INSEL1_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL1_MASK (CCL_LUTCTRL_INSEL1_MASK_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_FEEDBACK (CCL_LUTCTRL_INSEL1_FEEDBACK_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_LINK (CCL_LUTCTRL_INSEL1_LINK_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_EVENT (CCL_LUTCTRL_INSEL1_EVENT_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_IO (CCL_LUTCTRL_INSEL1_IO_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_AC (CCL_LUTCTRL_INSEL1_AC_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_TC (CCL_LUTCTRL_INSEL1_TC_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_ALTTC (CCL_LUTCTRL_INSEL1_ALTTC_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_TCC (CCL_LUTCTRL_INSEL1_TCC_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL1_SERCOM (CCL_LUTCTRL_INSEL1_SERCOM_Val << CCL_LUTCTRL_INSEL1_Pos) +#define CCL_LUTCTRL_INSEL2_Pos 16 /**< \brief (CCL_LUTCTRL) Input Selection 2 */ +#define CCL_LUTCTRL_INSEL2_Msk (_U_(0xF) << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2(value) (CCL_LUTCTRL_INSEL2_Msk & ((value) << CCL_LUTCTRL_INSEL2_Pos)) +#define CCL_LUTCTRL_INSEL2_MASK_Val _U_(0x0) /**< \brief (CCL_LUTCTRL) Masked input */ +#define CCL_LUTCTRL_INSEL2_FEEDBACK_Val _U_(0x1) /**< \brief (CCL_LUTCTRL) Feedback input source */ +#define CCL_LUTCTRL_INSEL2_LINK_Val _U_(0x2) /**< \brief (CCL_LUTCTRL) Linked LUT input source */ +#define CCL_LUTCTRL_INSEL2_EVENT_Val _U_(0x3) /**< \brief (CCL_LUTCTRL) Event input source */ +#define CCL_LUTCTRL_INSEL2_IO_Val _U_(0x4) /**< \brief (CCL_LUTCTRL) I/O pin input source */ +#define CCL_LUTCTRL_INSEL2_AC_Val _U_(0x5) /**< \brief (CCL_LUTCTRL) AC input source */ +#define CCL_LUTCTRL_INSEL2_TC_Val _U_(0x6) /**< \brief (CCL_LUTCTRL) TC input source */ +#define CCL_LUTCTRL_INSEL2_ALTTC_Val _U_(0x7) /**< \brief (CCL_LUTCTRL) Alternate TC input source */ +#define CCL_LUTCTRL_INSEL2_TCC_Val _U_(0x8) /**< \brief (CCL_LUTCTRL) TCC input source */ +#define CCL_LUTCTRL_INSEL2_SERCOM_Val _U_(0x9) /**< \brief (CCL_LUTCTRL) SERCOM input source */ +#define CCL_LUTCTRL_INSEL2_MASK (CCL_LUTCTRL_INSEL2_MASK_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_FEEDBACK (CCL_LUTCTRL_INSEL2_FEEDBACK_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_LINK (CCL_LUTCTRL_INSEL2_LINK_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_EVENT (CCL_LUTCTRL_INSEL2_EVENT_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_IO (CCL_LUTCTRL_INSEL2_IO_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_AC (CCL_LUTCTRL_INSEL2_AC_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_TC (CCL_LUTCTRL_INSEL2_TC_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_ALTTC (CCL_LUTCTRL_INSEL2_ALTTC_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_TCC (CCL_LUTCTRL_INSEL2_TCC_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INSEL2_SERCOM (CCL_LUTCTRL_INSEL2_SERCOM_Val << CCL_LUTCTRL_INSEL2_Pos) +#define CCL_LUTCTRL_INVEI_Pos 20 /**< \brief (CCL_LUTCTRL) Inverted Event Input Enable */ +#define CCL_LUTCTRL_INVEI (_U_(0x1) << CCL_LUTCTRL_INVEI_Pos) +#define CCL_LUTCTRL_LUTEI_Pos 21 /**< \brief (CCL_LUTCTRL) LUT Event Input Enable */ +#define CCL_LUTCTRL_LUTEI (_U_(0x1) << CCL_LUTCTRL_LUTEI_Pos) +#define CCL_LUTCTRL_LUTEO_Pos 22 /**< \brief (CCL_LUTCTRL) LUT Event Output Enable */ +#define CCL_LUTCTRL_LUTEO (_U_(0x1) << CCL_LUTCTRL_LUTEO_Pos) +#define CCL_LUTCTRL_TRUTH_Pos 24 /**< \brief (CCL_LUTCTRL) Truth Value */ +#define CCL_LUTCTRL_TRUTH_Msk (_U_(0xFF) << CCL_LUTCTRL_TRUTH_Pos) +#define CCL_LUTCTRL_TRUTH(value) (CCL_LUTCTRL_TRUTH_Msk & ((value) << CCL_LUTCTRL_TRUTH_Pos)) +#define CCL_LUTCTRL_MASK _U_(0xFF7FFFB2) /**< \brief (CCL_LUTCTRL) MASK Register */ + +/** \brief CCL hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO CCL_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */ + RoReg8 Reserved1[0x3]; + __IO CCL_SEQCTRL_Type SEQCTRL[2]; /**< \brief Offset: 0x4 (R/W 8) SEQ Control x */ + RoReg8 Reserved2[0x2]; + __IO CCL_LUTCTRL_Type LUTCTRL[4]; /**< \brief Offset: 0x8 (R/W 32) LUT Control x */ +} Ccl; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAME54_CCL_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/include/component/cmcc.h b/software/firmware/oracle_same54n19a/include/component/cmcc.h new file mode 100644 index 00000000..55799b5c --- /dev/null +++ b/software/firmware/oracle_same54n19a/include/component/cmcc.h @@ -0,0 +1,357 @@ +/** + * \file + * + * \brief Component description for CMCC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54_CMCC_COMPONENT_ +#define _SAME54_CMCC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR CMCC */ +/* ========================================================================== */ +/** \addtogroup SAME54_CMCC Cortex M Cache Controller */ +/*@{*/ + +#define CMCC_U2015 +#define REV_CMCC 0x600 + +/* -------- CMCC_TYPE : (CMCC Offset: 0x00) (R/ 32) Cache Type Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t GCLK:1; /*!< bit: 1 dynamic Clock Gating supported */ + uint32_t :2; /*!< bit: 2.. 3 Reserved */ + uint32_t RRP:1; /*!< bit: 4 Round Robin Policy supported */ + uint32_t WAYNUM:2; /*!< bit: 5.. 6 Number of Way */ + uint32_t LCKDOWN:1; /*!< bit: 7 Lock Down supported */ + uint32_t CSIZE:3; /*!< bit: 8..10 Cache Size */ + uint32_t CLSIZE:3; /*!< bit: 11..13 Cache Line Size */ + uint32_t :18; /*!< bit: 14..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_TYPE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_TYPE_OFFSET 0x00 /**< \brief (CMCC_TYPE offset) Cache Type Register */ +#define CMCC_TYPE_RESETVALUE _U_(0x000012D2) /**< \brief (CMCC_TYPE reset_value) Cache Type Register */ + +#define CMCC_TYPE_GCLK_Pos 1 /**< \brief (CMCC_TYPE) dynamic Clock Gating supported */ +#define CMCC_TYPE_GCLK (_U_(0x1) << CMCC_TYPE_GCLK_Pos) +#define CMCC_TYPE_RRP_Pos 4 /**< \brief (CMCC_TYPE) Round Robin Policy supported */ +#define CMCC_TYPE_RRP (_U_(0x1) << CMCC_TYPE_RRP_Pos) +#define CMCC_TYPE_WAYNUM_Pos 5 /**< \brief (CMCC_TYPE) Number of Way */ +#define CMCC_TYPE_WAYNUM_Msk (_U_(0x3) << CMCC_TYPE_WAYNUM_Pos) +#define CMCC_TYPE_WAYNUM(value) (CMCC_TYPE_WAYNUM_Msk & ((value) << CMCC_TYPE_WAYNUM_Pos)) +#define CMCC_TYPE_WAYNUM_DMAPPED_Val _U_(0x0) /**< \brief (CMCC_TYPE) Direct Mapped Cache */ +#define CMCC_TYPE_WAYNUM_ARCH2WAY_Val _U_(0x1) /**< \brief (CMCC_TYPE) 2-WAY set associative */ +#define CMCC_TYPE_WAYNUM_ARCH4WAY_Val _U_(0x2) /**< \brief (CMCC_TYPE) 4-WAY set associative */ +#define CMCC_TYPE_WAYNUM_DMAPPED (CMCC_TYPE_WAYNUM_DMAPPED_Val << CMCC_TYPE_WAYNUM_Pos) +#define CMCC_TYPE_WAYNUM_ARCH2WAY (CMCC_TYPE_WAYNUM_ARCH2WAY_Val << CMCC_TYPE_WAYNUM_Pos) +#define CMCC_TYPE_WAYNUM_ARCH4WAY (CMCC_TYPE_WAYNUM_ARCH4WAY_Val << CMCC_TYPE_WAYNUM_Pos) +#define CMCC_TYPE_LCKDOWN_Pos 7 /**< \brief (CMCC_TYPE) Lock Down supported */ +#define CMCC_TYPE_LCKDOWN (_U_(0x1) << CMCC_TYPE_LCKDOWN_Pos) +#define CMCC_TYPE_CSIZE_Pos 8 /**< \brief (CMCC_TYPE) Cache Size */ +#define CMCC_TYPE_CSIZE_Msk (_U_(0x7) << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CSIZE(value) (CMCC_TYPE_CSIZE_Msk & ((value) << CMCC_TYPE_CSIZE_Pos)) +#define CMCC_TYPE_CSIZE_CSIZE_1KB_Val _U_(0x0) /**< \brief (CMCC_TYPE) Cache Size is 1 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_2KB_Val _U_(0x1) /**< \brief (CMCC_TYPE) Cache Size is 2 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_4KB_Val _U_(0x2) /**< \brief (CMCC_TYPE) Cache Size is 4 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_8KB_Val _U_(0x3) /**< \brief (CMCC_TYPE) Cache Size is 8 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_16KB_Val _U_(0x4) /**< \brief (CMCC_TYPE) Cache Size is 16 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_32KB_Val _U_(0x5) /**< \brief (CMCC_TYPE) Cache Size is 32 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_64KB_Val _U_(0x6) /**< \brief (CMCC_TYPE) Cache Size is 64 KB */ +#define CMCC_TYPE_CSIZE_CSIZE_1KB (CMCC_TYPE_CSIZE_CSIZE_1KB_Val << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CSIZE_CSIZE_2KB (CMCC_TYPE_CSIZE_CSIZE_2KB_Val << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CSIZE_CSIZE_4KB (CMCC_TYPE_CSIZE_CSIZE_4KB_Val << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CSIZE_CSIZE_8KB (CMCC_TYPE_CSIZE_CSIZE_8KB_Val << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CSIZE_CSIZE_16KB (CMCC_TYPE_CSIZE_CSIZE_16KB_Val << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CSIZE_CSIZE_32KB (CMCC_TYPE_CSIZE_CSIZE_32KB_Val << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CSIZE_CSIZE_64KB (CMCC_TYPE_CSIZE_CSIZE_64KB_Val << CMCC_TYPE_CSIZE_Pos) +#define CMCC_TYPE_CLSIZE_Pos 11 /**< \brief (CMCC_TYPE) Cache Line Size */ +#define CMCC_TYPE_CLSIZE_Msk (_U_(0x7) << CMCC_TYPE_CLSIZE_Pos) +#define CMCC_TYPE_CLSIZE(value) (CMCC_TYPE_CLSIZE_Msk & ((value) << CMCC_TYPE_CLSIZE_Pos)) +#define CMCC_TYPE_CLSIZE_CLSIZE_4B_Val _U_(0x0) /**< \brief (CMCC_TYPE) Cache Line Size is 4 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_8B_Val _U_(0x1) /**< \brief (CMCC_TYPE) Cache Line Size is 8 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_16B_Val _U_(0x2) /**< \brief (CMCC_TYPE) Cache Line Size is 16 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_32B_Val _U_(0x3) /**< \brief (CMCC_TYPE) Cache Line Size is 32 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_64B_Val _U_(0x4) /**< \brief (CMCC_TYPE) Cache Line Size is 64 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_128B_Val _U_(0x5) /**< \brief (CMCC_TYPE) Cache Line Size is 128 bytes */ +#define CMCC_TYPE_CLSIZE_CLSIZE_4B (CMCC_TYPE_CLSIZE_CLSIZE_4B_Val << CMCC_TYPE_CLSIZE_Pos) +#define CMCC_TYPE_CLSIZE_CLSIZE_8B (CMCC_TYPE_CLSIZE_CLSIZE_8B_Val << CMCC_TYPE_CLSIZE_Pos) +#define CMCC_TYPE_CLSIZE_CLSIZE_16B (CMCC_TYPE_CLSIZE_CLSIZE_16B_Val << CMCC_TYPE_CLSIZE_Pos) +#define CMCC_TYPE_CLSIZE_CLSIZE_32B (CMCC_TYPE_CLSIZE_CLSIZE_32B_Val << CMCC_TYPE_CLSIZE_Pos) +#define CMCC_TYPE_CLSIZE_CLSIZE_64B (CMCC_TYPE_CLSIZE_CLSIZE_64B_Val << CMCC_TYPE_CLSIZE_Pos) +#define CMCC_TYPE_CLSIZE_CLSIZE_128B (CMCC_TYPE_CLSIZE_CLSIZE_128B_Val << CMCC_TYPE_CLSIZE_Pos) +#define CMCC_TYPE_MASK _U_(0x00003FF2) /**< \brief (CMCC_TYPE) MASK Register */ + +/* -------- CMCC_CFG : (CMCC Offset: 0x04) (R/W 32) Cache Configuration Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :1; /*!< bit: 0 Reserved */ + uint32_t ICDIS:1; /*!< bit: 1 Instruction Cache Disable */ + uint32_t DCDIS:1; /*!< bit: 2 Data Cache Disable */ + uint32_t :1; /*!< bit: 3 Reserved */ + uint32_t CSIZESW:3; /*!< bit: 4.. 6 Cache size configured by software */ + uint32_t :25; /*!< bit: 7..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_CFG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_CFG_OFFSET 0x04 /**< \brief (CMCC_CFG offset) Cache Configuration Register */ +#define CMCC_CFG_RESETVALUE _U_(0x00000020) /**< \brief (CMCC_CFG reset_value) Cache Configuration Register */ + +#define CMCC_CFG_ICDIS_Pos 1 /**< \brief (CMCC_CFG) Instruction Cache Disable */ +#define CMCC_CFG_ICDIS (_U_(0x1) << CMCC_CFG_ICDIS_Pos) +#define CMCC_CFG_DCDIS_Pos 2 /**< \brief (CMCC_CFG) Data Cache Disable */ +#define CMCC_CFG_DCDIS (_U_(0x1) << CMCC_CFG_DCDIS_Pos) +#define CMCC_CFG_CSIZESW_Pos 4 /**< \brief (CMCC_CFG) Cache size configured by software */ +#define CMCC_CFG_CSIZESW_Msk (_U_(0x7) << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_CSIZESW(value) (CMCC_CFG_CSIZESW_Msk & ((value) << CMCC_CFG_CSIZESW_Pos)) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val _U_(0x0) /**< \brief (CMCC_CFG) the Cache Size is configured to 1KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val _U_(0x1) /**< \brief (CMCC_CFG) the Cache Size is configured to 2KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val _U_(0x2) /**< \brief (CMCC_CFG) the Cache Size is configured to 4KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val _U_(0x3) /**< \brief (CMCC_CFG) the Cache Size is configured to 8KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val _U_(0x4) /**< \brief (CMCC_CFG) the Cache Size is configured to 16KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val _U_(0x5) /**< \brief (CMCC_CFG) the Cache Size is configured to 32KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val _U_(0x6) /**< \brief (CMCC_CFG) the Cache Size is configured to 64KB */ +#define CMCC_CFG_CSIZESW_CONF_CSIZE_1KB (CMCC_CFG_CSIZESW_CONF_CSIZE_1KB_Val << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_2KB (CMCC_CFG_CSIZESW_CONF_CSIZE_2KB_Val << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_4KB (CMCC_CFG_CSIZESW_CONF_CSIZE_4KB_Val << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_8KB (CMCC_CFG_CSIZESW_CONF_CSIZE_8KB_Val << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_16KB (CMCC_CFG_CSIZESW_CONF_CSIZE_16KB_Val << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_32KB (CMCC_CFG_CSIZESW_CONF_CSIZE_32KB_Val << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_CSIZESW_CONF_CSIZE_64KB (CMCC_CFG_CSIZESW_CONF_CSIZE_64KB_Val << CMCC_CFG_CSIZESW_Pos) +#define CMCC_CFG_MASK _U_(0x00000076) /**< \brief (CMCC_CFG) MASK Register */ + +/* -------- CMCC_CTRL : (CMCC Offset: 0x08) ( /W 32) Cache Control Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CEN:1; /*!< bit: 0 Cache Controller Enable */ + uint32_t :31; /*!< bit: 1..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_CTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_CTRL_OFFSET 0x08 /**< \brief (CMCC_CTRL offset) Cache Control Register */ +#define CMCC_CTRL_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_CTRL reset_value) Cache Control Register */ + +#define CMCC_CTRL_CEN_Pos 0 /**< \brief (CMCC_CTRL) Cache Controller Enable */ +#define CMCC_CTRL_CEN (_U_(0x1) << CMCC_CTRL_CEN_Pos) +#define CMCC_CTRL_MASK _U_(0x00000001) /**< \brief (CMCC_CTRL) MASK Register */ + +/* -------- CMCC_SR : (CMCC Offset: 0x0C) (R/ 32) Cache Status Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CSTS:1; /*!< bit: 0 Cache Controller Status */ + uint32_t :31; /*!< bit: 1..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_SR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_SR_OFFSET 0x0C /**< \brief (CMCC_SR offset) Cache Status Register */ +#define CMCC_SR_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_SR reset_value) Cache Status Register */ + +#define CMCC_SR_CSTS_Pos 0 /**< \brief (CMCC_SR) Cache Controller Status */ +#define CMCC_SR_CSTS (_U_(0x1) << CMCC_SR_CSTS_Pos) +#define CMCC_SR_MASK _U_(0x00000001) /**< \brief (CMCC_SR) MASK Register */ + +/* -------- CMCC_LCKWAY : (CMCC Offset: 0x10) (R/W 32) Cache Lock per Way Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t LCKWAY:4; /*!< bit: 0.. 3 Lockdown way Register */ + uint32_t :28; /*!< bit: 4..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_LCKWAY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_LCKWAY_OFFSET 0x10 /**< \brief (CMCC_LCKWAY offset) Cache Lock per Way Register */ +#define CMCC_LCKWAY_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_LCKWAY reset_value) Cache Lock per Way Register */ + +#define CMCC_LCKWAY_LCKWAY_Pos 0 /**< \brief (CMCC_LCKWAY) Lockdown way Register */ +#define CMCC_LCKWAY_LCKWAY_Msk (_U_(0xF) << CMCC_LCKWAY_LCKWAY_Pos) +#define CMCC_LCKWAY_LCKWAY(value) (CMCC_LCKWAY_LCKWAY_Msk & ((value) << CMCC_LCKWAY_LCKWAY_Pos)) +#define CMCC_LCKWAY_MASK _U_(0x0000000F) /**< \brief (CMCC_LCKWAY) MASK Register */ + +/* -------- CMCC_MAINT0 : (CMCC Offset: 0x20) ( /W 32) Cache Maintenance Register 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t INVALL:1; /*!< bit: 0 Cache Controller invalidate All */ + uint32_t :31; /*!< bit: 1..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_MAINT0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_MAINT0_OFFSET 0x20 /**< \brief (CMCC_MAINT0 offset) Cache Maintenance Register 0 */ +#define CMCC_MAINT0_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MAINT0 reset_value) Cache Maintenance Register 0 */ + +#define CMCC_MAINT0_INVALL_Pos 0 /**< \brief (CMCC_MAINT0) Cache Controller invalidate All */ +#define CMCC_MAINT0_INVALL (_U_(0x1) << CMCC_MAINT0_INVALL_Pos) +#define CMCC_MAINT0_MASK _U_(0x00000001) /**< \brief (CMCC_MAINT0) MASK Register */ + +/* -------- CMCC_MAINT1 : (CMCC Offset: 0x24) ( /W 32) Cache Maintenance Register 1 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t :4; /*!< bit: 0.. 3 Reserved */ + uint32_t INDEX:8; /*!< bit: 4..11 Invalidate Index */ + uint32_t :16; /*!< bit: 12..27 Reserved */ + uint32_t WAY:4; /*!< bit: 28..31 Invalidate Way */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_MAINT1_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_MAINT1_OFFSET 0x24 /**< \brief (CMCC_MAINT1 offset) Cache Maintenance Register 1 */ +#define CMCC_MAINT1_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MAINT1 reset_value) Cache Maintenance Register 1 */ + +#define CMCC_MAINT1_INDEX_Pos 4 /**< \brief (CMCC_MAINT1) Invalidate Index */ +#define CMCC_MAINT1_INDEX_Msk (_U_(0xFF) << CMCC_MAINT1_INDEX_Pos) +#define CMCC_MAINT1_INDEX(value) (CMCC_MAINT1_INDEX_Msk & ((value) << CMCC_MAINT1_INDEX_Pos)) +#define CMCC_MAINT1_WAY_Pos 28 /**< \brief (CMCC_MAINT1) Invalidate Way */ +#define CMCC_MAINT1_WAY_Msk (_U_(0xF) << CMCC_MAINT1_WAY_Pos) +#define CMCC_MAINT1_WAY(value) (CMCC_MAINT1_WAY_Msk & ((value) << CMCC_MAINT1_WAY_Pos)) +#define CMCC_MAINT1_WAY_WAY0_Val _U_(0x0) /**< \brief (CMCC_MAINT1) Way 0 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY1_Val _U_(0x1) /**< \brief (CMCC_MAINT1) Way 1 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY2_Val _U_(0x2) /**< \brief (CMCC_MAINT1) Way 2 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY3_Val _U_(0x3) /**< \brief (CMCC_MAINT1) Way 3 is selection for index invalidation */ +#define CMCC_MAINT1_WAY_WAY0 (CMCC_MAINT1_WAY_WAY0_Val << CMCC_MAINT1_WAY_Pos) +#define CMCC_MAINT1_WAY_WAY1 (CMCC_MAINT1_WAY_WAY1_Val << CMCC_MAINT1_WAY_Pos) +#define CMCC_MAINT1_WAY_WAY2 (CMCC_MAINT1_WAY_WAY2_Val << CMCC_MAINT1_WAY_Pos) +#define CMCC_MAINT1_WAY_WAY3 (CMCC_MAINT1_WAY_WAY3_Val << CMCC_MAINT1_WAY_Pos) +#define CMCC_MAINT1_MASK _U_(0xF0000FF0) /**< \brief (CMCC_MAINT1) MASK Register */ + +/* -------- CMCC_MCFG : (CMCC Offset: 0x28) (R/W 32) Cache Monitor Configuration Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t MODE:2; /*!< bit: 0.. 1 Cache Controller Monitor Counter Mode */ + uint32_t :30; /*!< bit: 2..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_MCFG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_MCFG_OFFSET 0x28 /**< \brief (CMCC_MCFG offset) Cache Monitor Configuration Register */ +#define CMCC_MCFG_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MCFG reset_value) Cache Monitor Configuration Register */ + +#define CMCC_MCFG_MODE_Pos 0 /**< \brief (CMCC_MCFG) Cache Controller Monitor Counter Mode */ +#define CMCC_MCFG_MODE_Msk (_U_(0x3) << CMCC_MCFG_MODE_Pos) +#define CMCC_MCFG_MODE(value) (CMCC_MCFG_MODE_Msk & ((value) << CMCC_MCFG_MODE_Pos)) +#define CMCC_MCFG_MODE_CYCLE_COUNT_Val _U_(0x0) /**< \brief (CMCC_MCFG) cycle counter */ +#define CMCC_MCFG_MODE_IHIT_COUNT_Val _U_(0x1) /**< \brief (CMCC_MCFG) instruction hit counter */ +#define CMCC_MCFG_MODE_DHIT_COUNT_Val _U_(0x2) /**< \brief (CMCC_MCFG) data hit counter */ +#define CMCC_MCFG_MODE_CYCLE_COUNT (CMCC_MCFG_MODE_CYCLE_COUNT_Val << CMCC_MCFG_MODE_Pos) +#define CMCC_MCFG_MODE_IHIT_COUNT (CMCC_MCFG_MODE_IHIT_COUNT_Val << CMCC_MCFG_MODE_Pos) +#define CMCC_MCFG_MODE_DHIT_COUNT (CMCC_MCFG_MODE_DHIT_COUNT_Val << CMCC_MCFG_MODE_Pos) +#define CMCC_MCFG_MASK _U_(0x00000003) /**< \brief (CMCC_MCFG) MASK Register */ + +/* -------- CMCC_MEN : (CMCC Offset: 0x2C) (R/W 32) Cache Monitor Enable Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t MENABLE:1; /*!< bit: 0 Cache Controller Monitor Enable */ + uint32_t :31; /*!< bit: 1..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_MEN_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_MEN_OFFSET 0x2C /**< \brief (CMCC_MEN offset) Cache Monitor Enable Register */ +#define CMCC_MEN_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MEN reset_value) Cache Monitor Enable Register */ + +#define CMCC_MEN_MENABLE_Pos 0 /**< \brief (CMCC_MEN) Cache Controller Monitor Enable */ +#define CMCC_MEN_MENABLE (_U_(0x1) << CMCC_MEN_MENABLE_Pos) +#define CMCC_MEN_MASK _U_(0x00000001) /**< \brief (CMCC_MEN) MASK Register */ + +/* -------- CMCC_MCTRL : (CMCC Offset: 0x30) ( /W 32) Cache Monitor Control Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Cache Controller Software Reset */ + uint32_t :31; /*!< bit: 1..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_MCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_MCTRL_OFFSET 0x30 /**< \brief (CMCC_MCTRL offset) Cache Monitor Control Register */ +#define CMCC_MCTRL_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MCTRL reset_value) Cache Monitor Control Register */ + +#define CMCC_MCTRL_SWRST_Pos 0 /**< \brief (CMCC_MCTRL) Cache Controller Software Reset */ +#define CMCC_MCTRL_SWRST (_U_(0x1) << CMCC_MCTRL_SWRST_Pos) +#define CMCC_MCTRL_MASK _U_(0x00000001) /**< \brief (CMCC_MCTRL) MASK Register */ + +/* -------- CMCC_MSR : (CMCC Offset: 0x34) (R/ 32) Cache Monitor Status Register -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t EVENT_CNT:32; /*!< bit: 0..31 Monitor Event Counter */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} CMCC_MSR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define CMCC_MSR_OFFSET 0x34 /**< \brief (CMCC_MSR offset) Cache Monitor Status Register */ +#define CMCC_MSR_RESETVALUE _U_(0x00000000) /**< \brief (CMCC_MSR reset_value) Cache Monitor Status Register */ + +#define CMCC_MSR_EVENT_CNT_Pos 0 /**< \brief (CMCC_MSR) Monitor Event Counter */ +#define CMCC_MSR_EVENT_CNT_Msk (_U_(0xFFFFFFFF) << CMCC_MSR_EVENT_CNT_Pos) +#define CMCC_MSR_EVENT_CNT(value) (CMCC_MSR_EVENT_CNT_Msk & ((value) << CMCC_MSR_EVENT_CNT_Pos)) +#define CMCC_MSR_MASK _U_(0xFFFFFFFF) /**< \brief (CMCC_MSR) MASK Register */ + +/** \brief CMCC APB hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __I CMCC_TYPE_Type TYPE; /**< \brief Offset: 0x00 (R/ 32) Cache Type Register */ + __IO CMCC_CFG_Type CFG; /**< \brief Offset: 0x04 (R/W 32) Cache Configuration Register */ + __O CMCC_CTRL_Type CTRL; /**< \brief Offset: 0x08 ( /W 32) Cache Control Register */ + __I CMCC_SR_Type SR; /**< \brief Offset: 0x0C (R/ 32) Cache Status Register */ + __IO CMCC_LCKWAY_Type LCKWAY; /**< \brief Offset: 0x10 (R/W 32) Cache Lock per Way Register */ + RoReg8 Reserved1[0xC]; + __O CMCC_MAINT0_Type MAINT0; /**< \brief Offset: 0x20 ( /W 32) Cache Maintenance Register 0 */ + __O CMCC_MAINT1_Type MAINT1; /**< \brief Offset: 0x24 ( /W 32) Cache Maintenance Register 1 */ + __IO CMCC_MCFG_Type MCFG; /**< \brief Offset: 0x28 (R/W 32) Cache Monitor Configuration Register */ + __IO CMCC_MEN_Type MEN; /**< \brief Offset: 0x2C (R/W 32) Cache Monitor Enable Register */ + __O CMCC_MCTRL_Type MCTRL; /**< \brief Offset: 0x30 ( /W 32) Cache Monitor Control Register */ + __I CMCC_MSR_Type MSR; /**< \brief Offset: 0x34 (R/ 32) Cache Monitor Status Register */ +} Cmcc; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAME54_CMCC_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/include/component/dac.h b/software/firmware/oracle_same54n19a/include/component/dac.h new file mode 100644 index 00000000..60f28c0b --- /dev/null +++ b/software/firmware/oracle_same54n19a/include/component/dac.h @@ -0,0 +1,544 @@ +/** + * \file + * + * \brief Component description for DAC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54_DAC_COMPONENT_ +#define _SAME54_DAC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR DAC */ +/* ========================================================================== */ +/** \addtogroup SAME54_DAC Digital-to-Analog Converter */ +/*@{*/ + +#define DAC_U2502 +#define REV_DAC 0x100 + +/* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t SWRST:1; /*!< bit: 0 Software Reset */ + uint8_t ENABLE:1; /*!< bit: 1 Enable DAC Controller */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_CTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_CTRLA_OFFSET 0x00 /**< \brief (DAC_CTRLA offset) Control A */ +#define DAC_CTRLA_RESETVALUE _U_(0x00) /**< \brief (DAC_CTRLA reset_value) Control A */ + +#define DAC_CTRLA_SWRST_Pos 0 /**< \brief (DAC_CTRLA) Software Reset */ +#define DAC_CTRLA_SWRST (_U_(0x1) << DAC_CTRLA_SWRST_Pos) +#define DAC_CTRLA_ENABLE_Pos 1 /**< \brief (DAC_CTRLA) Enable DAC Controller */ +#define DAC_CTRLA_ENABLE (_U_(0x1) << DAC_CTRLA_ENABLE_Pos) +#define DAC_CTRLA_MASK _U_(0x03) /**< \brief (DAC_CTRLA) MASK Register */ + +/* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DIFF:1; /*!< bit: 0 Differential mode enable */ + uint8_t REFSEL:2; /*!< bit: 1.. 2 Reference Selection for DAC0/1 */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_CTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_CTRLB_OFFSET 0x01 /**< \brief (DAC_CTRLB offset) Control B */ +#define DAC_CTRLB_RESETVALUE _U_(0x02) /**< \brief (DAC_CTRLB reset_value) Control B */ + +#define DAC_CTRLB_DIFF_Pos 0 /**< \brief (DAC_CTRLB) Differential mode enable */ +#define DAC_CTRLB_DIFF (_U_(0x1) << DAC_CTRLB_DIFF_Pos) +#define DAC_CTRLB_REFSEL_Pos 1 /**< \brief (DAC_CTRLB) Reference Selection for DAC0/1 */ +#define DAC_CTRLB_REFSEL_Msk (_U_(0x3) << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL(value) (DAC_CTRLB_REFSEL_Msk & ((value) << DAC_CTRLB_REFSEL_Pos)) +#define DAC_CTRLB_REFSEL_VREFPU_Val _U_(0x0) /**< \brief (DAC_CTRLB) External reference unbuffered */ +#define DAC_CTRLB_REFSEL_VDDANA_Val _U_(0x1) /**< \brief (DAC_CTRLB) Analog supply */ +#define DAC_CTRLB_REFSEL_VREFPB_Val _U_(0x2) /**< \brief (DAC_CTRLB) External reference buffered */ +#define DAC_CTRLB_REFSEL_INTREF_Val _U_(0x3) /**< \brief (DAC_CTRLB) Internal bandgap reference */ +#define DAC_CTRLB_REFSEL_VREFPU (DAC_CTRLB_REFSEL_VREFPU_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL_VDDANA (DAC_CTRLB_REFSEL_VDDANA_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL_VREFPB (DAC_CTRLB_REFSEL_VREFPB_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_REFSEL_INTREF (DAC_CTRLB_REFSEL_INTREF_Val << DAC_CTRLB_REFSEL_Pos) +#define DAC_CTRLB_MASK _U_(0x07) /**< \brief (DAC_CTRLB) MASK Register */ + +/* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t STARTEI0:1; /*!< bit: 0 Start Conversion Event Input DAC 0 */ + uint8_t STARTEI1:1; /*!< bit: 1 Start Conversion Event Input DAC 1 */ + uint8_t EMPTYEO0:1; /*!< bit: 2 Data Buffer Empty Event Output DAC 0 */ + uint8_t EMPTYEO1:1; /*!< bit: 3 Data Buffer Empty Event Output DAC 1 */ + uint8_t INVEI0:1; /*!< bit: 4 Enable Invertion of DAC 0 input event */ + uint8_t INVEI1:1; /*!< bit: 5 Enable Invertion of DAC 1 input event */ + uint8_t RESRDYEO0:1; /*!< bit: 6 Result Ready Event Output 0 */ + uint8_t RESRDYEO1:1; /*!< bit: 7 Result Ready Event Output 1 */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t STARTEI:2; /*!< bit: 0.. 1 Start Conversion Event Input DAC x */ + uint8_t EMPTYEO:2; /*!< bit: 2.. 3 Data Buffer Empty Event Output DAC x */ + uint8_t INVEI:2; /*!< bit: 4.. 5 Enable Invertion of DAC x input event */ + uint8_t RESRDYEO:2; /*!< bit: 6.. 7 Result Ready Event Output x */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_EVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_EVCTRL_OFFSET 0x02 /**< \brief (DAC_EVCTRL offset) Event Control */ +#define DAC_EVCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_EVCTRL reset_value) Event Control */ + +#define DAC_EVCTRL_STARTEI0_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 0 */ +#define DAC_EVCTRL_STARTEI0 (_U_(1) << DAC_EVCTRL_STARTEI0_Pos) +#define DAC_EVCTRL_STARTEI1_Pos 1 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC 1 */ +#define DAC_EVCTRL_STARTEI1 (_U_(1) << DAC_EVCTRL_STARTEI1_Pos) +#define DAC_EVCTRL_STARTEI_Pos 0 /**< \brief (DAC_EVCTRL) Start Conversion Event Input DAC x */ +#define DAC_EVCTRL_STARTEI_Msk (_U_(0x3) << DAC_EVCTRL_STARTEI_Pos) +#define DAC_EVCTRL_STARTEI(value) (DAC_EVCTRL_STARTEI_Msk & ((value) << DAC_EVCTRL_STARTEI_Pos)) +#define DAC_EVCTRL_EMPTYEO0_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 0 */ +#define DAC_EVCTRL_EMPTYEO0 (_U_(1) << DAC_EVCTRL_EMPTYEO0_Pos) +#define DAC_EVCTRL_EMPTYEO1_Pos 3 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC 1 */ +#define DAC_EVCTRL_EMPTYEO1 (_U_(1) << DAC_EVCTRL_EMPTYEO1_Pos) +#define DAC_EVCTRL_EMPTYEO_Pos 2 /**< \brief (DAC_EVCTRL) Data Buffer Empty Event Output DAC x */ +#define DAC_EVCTRL_EMPTYEO_Msk (_U_(0x3) << DAC_EVCTRL_EMPTYEO_Pos) +#define DAC_EVCTRL_EMPTYEO(value) (DAC_EVCTRL_EMPTYEO_Msk & ((value) << DAC_EVCTRL_EMPTYEO_Pos)) +#define DAC_EVCTRL_INVEI0_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 0 input event */ +#define DAC_EVCTRL_INVEI0 (_U_(1) << DAC_EVCTRL_INVEI0_Pos) +#define DAC_EVCTRL_INVEI1_Pos 5 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC 1 input event */ +#define DAC_EVCTRL_INVEI1 (_U_(1) << DAC_EVCTRL_INVEI1_Pos) +#define DAC_EVCTRL_INVEI_Pos 4 /**< \brief (DAC_EVCTRL) Enable Invertion of DAC x input event */ +#define DAC_EVCTRL_INVEI_Msk (_U_(0x3) << DAC_EVCTRL_INVEI_Pos) +#define DAC_EVCTRL_INVEI(value) (DAC_EVCTRL_INVEI_Msk & ((value) << DAC_EVCTRL_INVEI_Pos)) +#define DAC_EVCTRL_RESRDYEO0_Pos 6 /**< \brief (DAC_EVCTRL) Result Ready Event Output 0 */ +#define DAC_EVCTRL_RESRDYEO0 (_U_(1) << DAC_EVCTRL_RESRDYEO0_Pos) +#define DAC_EVCTRL_RESRDYEO1_Pos 7 /**< \brief (DAC_EVCTRL) Result Ready Event Output 1 */ +#define DAC_EVCTRL_RESRDYEO1 (_U_(1) << DAC_EVCTRL_RESRDYEO1_Pos) +#define DAC_EVCTRL_RESRDYEO_Pos 6 /**< \brief (DAC_EVCTRL) Result Ready Event Output x */ +#define DAC_EVCTRL_RESRDYEO_Msk (_U_(0x3) << DAC_EVCTRL_RESRDYEO_Pos) +#define DAC_EVCTRL_RESRDYEO(value) (DAC_EVCTRL_RESRDYEO_Msk & ((value) << DAC_EVCTRL_RESRDYEO_Pos)) +#define DAC_EVCTRL_MASK _U_(0xFF) /**< \brief (DAC_EVCTRL) MASK Register */ + +/* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun 0 Interrupt Enable */ + uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun 1 Interrupt Enable */ + uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */ + uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */ + uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready Interrupt Enable */ + uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready Interrupt Enable */ + uint8_t OVERRUN0:1; /*!< bit: 6 Overrun 0 Interrupt Enable */ + uint8_t OVERRUN1:1; /*!< bit: 7 Overrun 1 Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun x Interrupt Enable */ + uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */ + uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready Interrupt Enable */ + uint8_t OVERRUN:2; /*!< bit: 6.. 7 Overrun x Interrupt Enable */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_INTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_INTENCLR_OFFSET 0x04 /**< \brief (DAC_INTENCLR offset) Interrupt Enable Clear */ +#define DAC_INTENCLR_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENCLR reset_value) Interrupt Enable Clear */ + +#define DAC_INTENCLR_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENCLR) Underrun 0 Interrupt Enable */ +#define DAC_INTENCLR_UNDERRUN0 (_U_(1) << DAC_INTENCLR_UNDERRUN0_Pos) +#define DAC_INTENCLR_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENCLR) Underrun 1 Interrupt Enable */ +#define DAC_INTENCLR_UNDERRUN1 (_U_(1) << DAC_INTENCLR_UNDERRUN1_Pos) +#define DAC_INTENCLR_UNDERRUN_Pos 0 /**< \brief (DAC_INTENCLR) Underrun x Interrupt Enable */ +#define DAC_INTENCLR_UNDERRUN_Msk (_U_(0x3) << DAC_INTENCLR_UNDERRUN_Pos) +#define DAC_INTENCLR_UNDERRUN(value) (DAC_INTENCLR_UNDERRUN_Msk & ((value) << DAC_INTENCLR_UNDERRUN_Pos)) +#define DAC_INTENCLR_EMPTY0_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer 0 Empty Interrupt Enable */ +#define DAC_INTENCLR_EMPTY0 (_U_(1) << DAC_INTENCLR_EMPTY0_Pos) +#define DAC_INTENCLR_EMPTY1_Pos 3 /**< \brief (DAC_INTENCLR) Data Buffer 1 Empty Interrupt Enable */ +#define DAC_INTENCLR_EMPTY1 (_U_(1) << DAC_INTENCLR_EMPTY1_Pos) +#define DAC_INTENCLR_EMPTY_Pos 2 /**< \brief (DAC_INTENCLR) Data Buffer x Empty Interrupt Enable */ +#define DAC_INTENCLR_EMPTY_Msk (_U_(0x3) << DAC_INTENCLR_EMPTY_Pos) +#define DAC_INTENCLR_EMPTY(value) (DAC_INTENCLR_EMPTY_Msk & ((value) << DAC_INTENCLR_EMPTY_Pos)) +#define DAC_INTENCLR_RESRDY0_Pos 4 /**< \brief (DAC_INTENCLR) Result 0 Ready Interrupt Enable */ +#define DAC_INTENCLR_RESRDY0 (_U_(1) << DAC_INTENCLR_RESRDY0_Pos) +#define DAC_INTENCLR_RESRDY1_Pos 5 /**< \brief (DAC_INTENCLR) Result 1 Ready Interrupt Enable */ +#define DAC_INTENCLR_RESRDY1 (_U_(1) << DAC_INTENCLR_RESRDY1_Pos) +#define DAC_INTENCLR_RESRDY_Pos 4 /**< \brief (DAC_INTENCLR) Result x Ready Interrupt Enable */ +#define DAC_INTENCLR_RESRDY_Msk (_U_(0x3) << DAC_INTENCLR_RESRDY_Pos) +#define DAC_INTENCLR_RESRDY(value) (DAC_INTENCLR_RESRDY_Msk & ((value) << DAC_INTENCLR_RESRDY_Pos)) +#define DAC_INTENCLR_OVERRUN0_Pos 6 /**< \brief (DAC_INTENCLR) Overrun 0 Interrupt Enable */ +#define DAC_INTENCLR_OVERRUN0 (_U_(1) << DAC_INTENCLR_OVERRUN0_Pos) +#define DAC_INTENCLR_OVERRUN1_Pos 7 /**< \brief (DAC_INTENCLR) Overrun 1 Interrupt Enable */ +#define DAC_INTENCLR_OVERRUN1 (_U_(1) << DAC_INTENCLR_OVERRUN1_Pos) +#define DAC_INTENCLR_OVERRUN_Pos 6 /**< \brief (DAC_INTENCLR) Overrun x Interrupt Enable */ +#define DAC_INTENCLR_OVERRUN_Msk (_U_(0x3) << DAC_INTENCLR_OVERRUN_Pos) +#define DAC_INTENCLR_OVERRUN(value) (DAC_INTENCLR_OVERRUN_Msk & ((value) << DAC_INTENCLR_OVERRUN_Pos)) +#define DAC_INTENCLR_MASK _U_(0xFF) /**< \brief (DAC_INTENCLR) MASK Register */ + +/* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun 0 Interrupt Enable */ + uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun 1 Interrupt Enable */ + uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */ + uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */ + uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready Interrupt Enable */ + uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready Interrupt Enable */ + uint8_t OVERRUN0:1; /*!< bit: 6 Overrun 0 Interrupt Enable */ + uint8_t OVERRUN1:1; /*!< bit: 7 Overrun 1 Interrupt Enable */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun x Interrupt Enable */ + uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */ + uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready Interrupt Enable */ + uint8_t OVERRUN:2; /*!< bit: 6.. 7 Overrun x Interrupt Enable */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_INTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_INTENSET_OFFSET 0x05 /**< \brief (DAC_INTENSET offset) Interrupt Enable Set */ +#define DAC_INTENSET_RESETVALUE _U_(0x00) /**< \brief (DAC_INTENSET reset_value) Interrupt Enable Set */ + +#define DAC_INTENSET_UNDERRUN0_Pos 0 /**< \brief (DAC_INTENSET) Underrun 0 Interrupt Enable */ +#define DAC_INTENSET_UNDERRUN0 (_U_(1) << DAC_INTENSET_UNDERRUN0_Pos) +#define DAC_INTENSET_UNDERRUN1_Pos 1 /**< \brief (DAC_INTENSET) Underrun 1 Interrupt Enable */ +#define DAC_INTENSET_UNDERRUN1 (_U_(1) << DAC_INTENSET_UNDERRUN1_Pos) +#define DAC_INTENSET_UNDERRUN_Pos 0 /**< \brief (DAC_INTENSET) Underrun x Interrupt Enable */ +#define DAC_INTENSET_UNDERRUN_Msk (_U_(0x3) << DAC_INTENSET_UNDERRUN_Pos) +#define DAC_INTENSET_UNDERRUN(value) (DAC_INTENSET_UNDERRUN_Msk & ((value) << DAC_INTENSET_UNDERRUN_Pos)) +#define DAC_INTENSET_EMPTY0_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer 0 Empty Interrupt Enable */ +#define DAC_INTENSET_EMPTY0 (_U_(1) << DAC_INTENSET_EMPTY0_Pos) +#define DAC_INTENSET_EMPTY1_Pos 3 /**< \brief (DAC_INTENSET) Data Buffer 1 Empty Interrupt Enable */ +#define DAC_INTENSET_EMPTY1 (_U_(1) << DAC_INTENSET_EMPTY1_Pos) +#define DAC_INTENSET_EMPTY_Pos 2 /**< \brief (DAC_INTENSET) Data Buffer x Empty Interrupt Enable */ +#define DAC_INTENSET_EMPTY_Msk (_U_(0x3) << DAC_INTENSET_EMPTY_Pos) +#define DAC_INTENSET_EMPTY(value) (DAC_INTENSET_EMPTY_Msk & ((value) << DAC_INTENSET_EMPTY_Pos)) +#define DAC_INTENSET_RESRDY0_Pos 4 /**< \brief (DAC_INTENSET) Result 0 Ready Interrupt Enable */ +#define DAC_INTENSET_RESRDY0 (_U_(1) << DAC_INTENSET_RESRDY0_Pos) +#define DAC_INTENSET_RESRDY1_Pos 5 /**< \brief (DAC_INTENSET) Result 1 Ready Interrupt Enable */ +#define DAC_INTENSET_RESRDY1 (_U_(1) << DAC_INTENSET_RESRDY1_Pos) +#define DAC_INTENSET_RESRDY_Pos 4 /**< \brief (DAC_INTENSET) Result x Ready Interrupt Enable */ +#define DAC_INTENSET_RESRDY_Msk (_U_(0x3) << DAC_INTENSET_RESRDY_Pos) +#define DAC_INTENSET_RESRDY(value) (DAC_INTENSET_RESRDY_Msk & ((value) << DAC_INTENSET_RESRDY_Pos)) +#define DAC_INTENSET_OVERRUN0_Pos 6 /**< \brief (DAC_INTENSET) Overrun 0 Interrupt Enable */ +#define DAC_INTENSET_OVERRUN0 (_U_(1) << DAC_INTENSET_OVERRUN0_Pos) +#define DAC_INTENSET_OVERRUN1_Pos 7 /**< \brief (DAC_INTENSET) Overrun 1 Interrupt Enable */ +#define DAC_INTENSET_OVERRUN1 (_U_(1) << DAC_INTENSET_OVERRUN1_Pos) +#define DAC_INTENSET_OVERRUN_Pos 6 /**< \brief (DAC_INTENSET) Overrun x Interrupt Enable */ +#define DAC_INTENSET_OVERRUN_Msk (_U_(0x3) << DAC_INTENSET_OVERRUN_Pos) +#define DAC_INTENSET_OVERRUN(value) (DAC_INTENSET_OVERRUN_Msk & ((value) << DAC_INTENSET_OVERRUN_Pos)) +#define DAC_INTENSET_MASK _U_(0xFF) /**< \brief (DAC_INTENSET) MASK Register */ + +/* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t UNDERRUN0:1; /*!< bit: 0 Result 0 Underrun */ + __I uint8_t UNDERRUN1:1; /*!< bit: 1 Result 1 Underrun */ + __I uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty */ + __I uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty */ + __I uint8_t RESRDY0:1; /*!< bit: 4 Result 0 Ready */ + __I uint8_t RESRDY1:1; /*!< bit: 5 Result 1 Ready */ + __I uint8_t OVERRUN0:1; /*!< bit: 6 Result 0 Overrun */ + __I uint8_t OVERRUN1:1; /*!< bit: 7 Result 1 Overrun */ + } bit; /*!< Structure used for bit access */ + struct { + __I uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Result x Underrun */ + __I uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty */ + __I uint8_t RESRDY:2; /*!< bit: 4.. 5 Result x Ready */ + __I uint8_t OVERRUN:2; /*!< bit: 6.. 7 Result x Overrun */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_INTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_INTFLAG_OFFSET 0x06 /**< \brief (DAC_INTFLAG offset) Interrupt Flag Status and Clear */ +#define DAC_INTFLAG_RESETVALUE _U_(0x00) /**< \brief (DAC_INTFLAG reset_value) Interrupt Flag Status and Clear */ + +#define DAC_INTFLAG_UNDERRUN0_Pos 0 /**< \brief (DAC_INTFLAG) Result 0 Underrun */ +#define DAC_INTFLAG_UNDERRUN0 (_U_(1) << DAC_INTFLAG_UNDERRUN0_Pos) +#define DAC_INTFLAG_UNDERRUN1_Pos 1 /**< \brief (DAC_INTFLAG) Result 1 Underrun */ +#define DAC_INTFLAG_UNDERRUN1 (_U_(1) << DAC_INTFLAG_UNDERRUN1_Pos) +#define DAC_INTFLAG_UNDERRUN_Pos 0 /**< \brief (DAC_INTFLAG) Result x Underrun */ +#define DAC_INTFLAG_UNDERRUN_Msk (_U_(0x3) << DAC_INTFLAG_UNDERRUN_Pos) +#define DAC_INTFLAG_UNDERRUN(value) (DAC_INTFLAG_UNDERRUN_Msk & ((value) << DAC_INTFLAG_UNDERRUN_Pos)) +#define DAC_INTFLAG_EMPTY0_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer 0 Empty */ +#define DAC_INTFLAG_EMPTY0 (_U_(1) << DAC_INTFLAG_EMPTY0_Pos) +#define DAC_INTFLAG_EMPTY1_Pos 3 /**< \brief (DAC_INTFLAG) Data Buffer 1 Empty */ +#define DAC_INTFLAG_EMPTY1 (_U_(1) << DAC_INTFLAG_EMPTY1_Pos) +#define DAC_INTFLAG_EMPTY_Pos 2 /**< \brief (DAC_INTFLAG) Data Buffer x Empty */ +#define DAC_INTFLAG_EMPTY_Msk (_U_(0x3) << DAC_INTFLAG_EMPTY_Pos) +#define DAC_INTFLAG_EMPTY(value) (DAC_INTFLAG_EMPTY_Msk & ((value) << DAC_INTFLAG_EMPTY_Pos)) +#define DAC_INTFLAG_RESRDY0_Pos 4 /**< \brief (DAC_INTFLAG) Result 0 Ready */ +#define DAC_INTFLAG_RESRDY0 (_U_(1) << DAC_INTFLAG_RESRDY0_Pos) +#define DAC_INTFLAG_RESRDY1_Pos 5 /**< \brief (DAC_INTFLAG) Result 1 Ready */ +#define DAC_INTFLAG_RESRDY1 (_U_(1) << DAC_INTFLAG_RESRDY1_Pos) +#define DAC_INTFLAG_RESRDY_Pos 4 /**< \brief (DAC_INTFLAG) Result x Ready */ +#define DAC_INTFLAG_RESRDY_Msk (_U_(0x3) << DAC_INTFLAG_RESRDY_Pos) +#define DAC_INTFLAG_RESRDY(value) (DAC_INTFLAG_RESRDY_Msk & ((value) << DAC_INTFLAG_RESRDY_Pos)) +#define DAC_INTFLAG_OVERRUN0_Pos 6 /**< \brief (DAC_INTFLAG) Result 0 Overrun */ +#define DAC_INTFLAG_OVERRUN0 (_U_(1) << DAC_INTFLAG_OVERRUN0_Pos) +#define DAC_INTFLAG_OVERRUN1_Pos 7 /**< \brief (DAC_INTFLAG) Result 1 Overrun */ +#define DAC_INTFLAG_OVERRUN1 (_U_(1) << DAC_INTFLAG_OVERRUN1_Pos) +#define DAC_INTFLAG_OVERRUN_Pos 6 /**< \brief (DAC_INTFLAG) Result x Overrun */ +#define DAC_INTFLAG_OVERRUN_Msk (_U_(0x3) << DAC_INTFLAG_OVERRUN_Pos) +#define DAC_INTFLAG_OVERRUN(value) (DAC_INTFLAG_OVERRUN_Msk & ((value) << DAC_INTFLAG_OVERRUN_Pos)) +#define DAC_INTFLAG_MASK _U_(0xFF) /**< \brief (DAC_INTFLAG) MASK Register */ + +/* -------- DAC_STATUS : (DAC Offset: 0x07) (R/ 8) Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t READY0:1; /*!< bit: 0 DAC 0 Startup Ready */ + uint8_t READY1:1; /*!< bit: 1 DAC 1 Startup Ready */ + uint8_t EOC0:1; /*!< bit: 2 DAC 0 End of Conversion */ + uint8_t EOC1:1; /*!< bit: 3 DAC 1 End of Conversion */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint8_t READY:2; /*!< bit: 0.. 1 DAC x Startup Ready */ + uint8_t EOC:2; /*!< bit: 2.. 3 DAC x End of Conversion */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } vec; /*!< Structure used for vec access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_STATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_STATUS_OFFSET 0x07 /**< \brief (DAC_STATUS offset) Status */ +#define DAC_STATUS_RESETVALUE _U_(0x00) /**< \brief (DAC_STATUS reset_value) Status */ + +#define DAC_STATUS_READY0_Pos 0 /**< \brief (DAC_STATUS) DAC 0 Startup Ready */ +#define DAC_STATUS_READY0 (_U_(1) << DAC_STATUS_READY0_Pos) +#define DAC_STATUS_READY1_Pos 1 /**< \brief (DAC_STATUS) DAC 1 Startup Ready */ +#define DAC_STATUS_READY1 (_U_(1) << DAC_STATUS_READY1_Pos) +#define DAC_STATUS_READY_Pos 0 /**< \brief (DAC_STATUS) DAC x Startup Ready */ +#define DAC_STATUS_READY_Msk (_U_(0x3) << DAC_STATUS_READY_Pos) +#define DAC_STATUS_READY(value) (DAC_STATUS_READY_Msk & ((value) << DAC_STATUS_READY_Pos)) +#define DAC_STATUS_EOC0_Pos 2 /**< \brief (DAC_STATUS) DAC 0 End of Conversion */ +#define DAC_STATUS_EOC0 (_U_(1) << DAC_STATUS_EOC0_Pos) +#define DAC_STATUS_EOC1_Pos 3 /**< \brief (DAC_STATUS) DAC 1 End of Conversion */ +#define DAC_STATUS_EOC1 (_U_(1) << DAC_STATUS_EOC1_Pos) +#define DAC_STATUS_EOC_Pos 2 /**< \brief (DAC_STATUS) DAC x End of Conversion */ +#define DAC_STATUS_EOC_Msk (_U_(0x3) << DAC_STATUS_EOC_Pos) +#define DAC_STATUS_EOC(value) (DAC_STATUS_EOC_Msk & ((value) << DAC_STATUS_EOC_Pos)) +#define DAC_STATUS_MASK _U_(0x0F) /**< \brief (DAC_STATUS) MASK Register */ + +/* -------- DAC_SYNCBUSY : (DAC Offset: 0x08) (R/ 32) Synchronization Busy -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 DAC Enable Status */ + uint32_t DATA0:1; /*!< bit: 2 Data DAC 0 */ + uint32_t DATA1:1; /*!< bit: 3 Data DAC 1 */ + uint32_t DATABUF0:1; /*!< bit: 4 Data Buffer DAC 0 */ + uint32_t DATABUF1:1; /*!< bit: 5 Data Buffer DAC 1 */ + uint32_t :26; /*!< bit: 6..31 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t :2; /*!< bit: 0.. 1 Reserved */ + uint32_t DATA:2; /*!< bit: 2.. 3 Data DAC x */ + uint32_t DATABUF:2; /*!< bit: 4.. 5 Data Buffer DAC x */ + uint32_t :26; /*!< bit: 6..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DAC_SYNCBUSY_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_SYNCBUSY_OFFSET 0x08 /**< \brief (DAC_SYNCBUSY offset) Synchronization Busy */ +#define DAC_SYNCBUSY_RESETVALUE _U_(0x00000000) /**< \brief (DAC_SYNCBUSY reset_value) Synchronization Busy */ + +#define DAC_SYNCBUSY_SWRST_Pos 0 /**< \brief (DAC_SYNCBUSY) Software Reset */ +#define DAC_SYNCBUSY_SWRST (_U_(0x1) << DAC_SYNCBUSY_SWRST_Pos) +#define DAC_SYNCBUSY_ENABLE_Pos 1 /**< \brief (DAC_SYNCBUSY) DAC Enable Status */ +#define DAC_SYNCBUSY_ENABLE (_U_(0x1) << DAC_SYNCBUSY_ENABLE_Pos) +#define DAC_SYNCBUSY_DATA0_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC 0 */ +#define DAC_SYNCBUSY_DATA0 (_U_(1) << DAC_SYNCBUSY_DATA0_Pos) +#define DAC_SYNCBUSY_DATA1_Pos 3 /**< \brief (DAC_SYNCBUSY) Data DAC 1 */ +#define DAC_SYNCBUSY_DATA1 (_U_(1) << DAC_SYNCBUSY_DATA1_Pos) +#define DAC_SYNCBUSY_DATA_Pos 2 /**< \brief (DAC_SYNCBUSY) Data DAC x */ +#define DAC_SYNCBUSY_DATA_Msk (_U_(0x3) << DAC_SYNCBUSY_DATA_Pos) +#define DAC_SYNCBUSY_DATA(value) (DAC_SYNCBUSY_DATA_Msk & ((value) << DAC_SYNCBUSY_DATA_Pos)) +#define DAC_SYNCBUSY_DATABUF0_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 0 */ +#define DAC_SYNCBUSY_DATABUF0 (_U_(1) << DAC_SYNCBUSY_DATABUF0_Pos) +#define DAC_SYNCBUSY_DATABUF1_Pos 5 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC 1 */ +#define DAC_SYNCBUSY_DATABUF1 (_U_(1) << DAC_SYNCBUSY_DATABUF1_Pos) +#define DAC_SYNCBUSY_DATABUF_Pos 4 /**< \brief (DAC_SYNCBUSY) Data Buffer DAC x */ +#define DAC_SYNCBUSY_DATABUF_Msk (_U_(0x3) << DAC_SYNCBUSY_DATABUF_Pos) +#define DAC_SYNCBUSY_DATABUF(value) (DAC_SYNCBUSY_DATABUF_Msk & ((value) << DAC_SYNCBUSY_DATABUF_Pos)) +#define DAC_SYNCBUSY_MASK _U_(0x0000003F) /**< \brief (DAC_SYNCBUSY) MASK Register */ + +/* -------- DAC_DACCTRL : (DAC Offset: 0x0C) (R/W 16) DAC n Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t LEFTADJ:1; /*!< bit: 0 Left Adjusted Data */ + uint16_t ENABLE:1; /*!< bit: 1 Enable DAC0 */ + uint16_t CCTRL:2; /*!< bit: 2.. 3 Current Control */ + uint16_t :1; /*!< bit: 4 Reserved */ + uint16_t FEXT:1; /*!< bit: 5 Standalone Filter */ + uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ + uint16_t DITHER:1; /*!< bit: 7 Dithering Mode */ + uint16_t REFRESH:4; /*!< bit: 8..11 Refresh period */ + uint16_t :1; /*!< bit: 12 Reserved */ + uint16_t OSR:3; /*!< bit: 13..15 Sampling Rate */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DAC_DACCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_DACCTRL_OFFSET 0x0C /**< \brief (DAC_DACCTRL offset) DAC n Control */ +#define DAC_DACCTRL_RESETVALUE _U_(0x0000) /**< \brief (DAC_DACCTRL reset_value) DAC n Control */ + +#define DAC_DACCTRL_LEFTADJ_Pos 0 /**< \brief (DAC_DACCTRL) Left Adjusted Data */ +#define DAC_DACCTRL_LEFTADJ (_U_(0x1) << DAC_DACCTRL_LEFTADJ_Pos) +#define DAC_DACCTRL_ENABLE_Pos 1 /**< \brief (DAC_DACCTRL) Enable DAC0 */ +#define DAC_DACCTRL_ENABLE (_U_(0x1) << DAC_DACCTRL_ENABLE_Pos) +#define DAC_DACCTRL_CCTRL_Pos 2 /**< \brief (DAC_DACCTRL) Current Control */ +#define DAC_DACCTRL_CCTRL_Msk (_U_(0x3) << DAC_DACCTRL_CCTRL_Pos) +#define DAC_DACCTRL_CCTRL(value) (DAC_DACCTRL_CCTRL_Msk & ((value) << DAC_DACCTRL_CCTRL_Pos)) +#define DAC_DACCTRL_CCTRL_CC100K_Val _U_(0x0) /**< \brief (DAC_DACCTRL) GCLK_DAC ≤ 1.2MHz (100kSPS) */ +#define DAC_DACCTRL_CCTRL_CC1M_Val _U_(0x1) /**< \brief (DAC_DACCTRL) 1.2MHz < GCLK_DAC ≤ 6MHz (500kSPS) */ +#define DAC_DACCTRL_CCTRL_CC12M_Val _U_(0x2) /**< \brief (DAC_DACCTRL) 6MHz < GCLK_DAC ≤ 12MHz (1MSPS) */ +#define DAC_DACCTRL_CCTRL_CC100K (DAC_DACCTRL_CCTRL_CC100K_Val << DAC_DACCTRL_CCTRL_Pos) +#define DAC_DACCTRL_CCTRL_CC1M (DAC_DACCTRL_CCTRL_CC1M_Val << DAC_DACCTRL_CCTRL_Pos) +#define DAC_DACCTRL_CCTRL_CC12M (DAC_DACCTRL_CCTRL_CC12M_Val << DAC_DACCTRL_CCTRL_Pos) +#define DAC_DACCTRL_FEXT_Pos 5 /**< \brief (DAC_DACCTRL) Standalone Filter */ +#define DAC_DACCTRL_FEXT (_U_(0x1) << DAC_DACCTRL_FEXT_Pos) +#define DAC_DACCTRL_RUNSTDBY_Pos 6 /**< \brief (DAC_DACCTRL) Run in Standby */ +#define DAC_DACCTRL_RUNSTDBY (_U_(0x1) << DAC_DACCTRL_RUNSTDBY_Pos) +#define DAC_DACCTRL_DITHER_Pos 7 /**< \brief (DAC_DACCTRL) Dithering Mode */ +#define DAC_DACCTRL_DITHER (_U_(0x1) << DAC_DACCTRL_DITHER_Pos) +#define DAC_DACCTRL_REFRESH_Pos 8 /**< \brief (DAC_DACCTRL) Refresh period */ +#define DAC_DACCTRL_REFRESH_Msk (_U_(0xF) << DAC_DACCTRL_REFRESH_Pos) +#define DAC_DACCTRL_REFRESH(value) (DAC_DACCTRL_REFRESH_Msk & ((value) << DAC_DACCTRL_REFRESH_Pos)) +#define DAC_DACCTRL_OSR_Pos 13 /**< \brief (DAC_DACCTRL) Sampling Rate */ +#define DAC_DACCTRL_OSR_Msk (_U_(0x7) << DAC_DACCTRL_OSR_Pos) +#define DAC_DACCTRL_OSR(value) (DAC_DACCTRL_OSR_Msk & ((value) << DAC_DACCTRL_OSR_Pos)) +#define DAC_DACCTRL_MASK _U_(0xEFEF) /**< \brief (DAC_DACCTRL) MASK Register */ + +/* -------- DAC_DATA : (DAC Offset: 0x10) ( /W 16) DAC n Data -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DATA:16; /*!< bit: 0..15 DAC0 Data */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DAC_DATA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_DATA_OFFSET 0x10 /**< \brief (DAC_DATA offset) DAC n Data */ +#define DAC_DATA_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATA reset_value) DAC n Data */ + +#define DAC_DATA_DATA_Pos 0 /**< \brief (DAC_DATA) DAC0 Data */ +#define DAC_DATA_DATA_Msk (_U_(0xFFFF) << DAC_DATA_DATA_Pos) +#define DAC_DATA_DATA(value) (DAC_DATA_DATA_Msk & ((value) << DAC_DATA_DATA_Pos)) +#define DAC_DATA_MASK _U_(0xFFFF) /**< \brief (DAC_DATA) MASK Register */ + +/* -------- DAC_DATABUF : (DAC Offset: 0x14) ( /W 16) DAC n Data Buffer -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t DATABUF:16; /*!< bit: 0..15 DAC0 Data Buffer */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DAC_DATABUF_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_DATABUF_OFFSET 0x14 /**< \brief (DAC_DATABUF offset) DAC n Data Buffer */ +#define DAC_DATABUF_RESETVALUE _U_(0x0000) /**< \brief (DAC_DATABUF reset_value) DAC n Data Buffer */ + +#define DAC_DATABUF_DATABUF_Pos 0 /**< \brief (DAC_DATABUF) DAC0 Data Buffer */ +#define DAC_DATABUF_DATABUF_Msk (_U_(0xFFFF) << DAC_DATABUF_DATABUF_Pos) +#define DAC_DATABUF_DATABUF(value) (DAC_DATABUF_DATABUF_Msk & ((value) << DAC_DATABUF_DATABUF_Pos)) +#define DAC_DATABUF_MASK _U_(0xFFFF) /**< \brief (DAC_DATABUF) MASK Register */ + +/* -------- DAC_DBGCTRL : (DAC Offset: 0x18) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DAC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_DBGCTRL_OFFSET 0x18 /**< \brief (DAC_DBGCTRL offset) Debug Control */ +#define DAC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (DAC_DBGCTRL reset_value) Debug Control */ + +#define DAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DAC_DBGCTRL) Debug Run */ +#define DAC_DBGCTRL_DBGRUN (_U_(0x1) << DAC_DBGCTRL_DBGRUN_Pos) +#define DAC_DBGCTRL_MASK _U_(0x01) /**< \brief (DAC_DBGCTRL) MASK Register */ + +/* -------- DAC_RESULT : (DAC Offset: 0x1C) (R/ 16) Filter Result -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t RESULT:16; /*!< bit: 0..15 Filter Result */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DAC_RESULT_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DAC_RESULT_OFFSET 0x1C /**< \brief (DAC_RESULT offset) Filter Result */ +#define DAC_RESULT_RESETVALUE _U_(0x0000) /**< \brief (DAC_RESULT reset_value) Filter Result */ + +#define DAC_RESULT_RESULT_Pos 0 /**< \brief (DAC_RESULT) Filter Result */ +#define DAC_RESULT_RESULT_Msk (_U_(0xFFFF) << DAC_RESULT_RESULT_Pos) +#define DAC_RESULT_RESULT(value) (DAC_RESULT_RESULT_Msk & ((value) << DAC_RESULT_RESULT_Pos)) +#define DAC_RESULT_MASK _U_(0xFFFF) /**< \brief (DAC_RESULT) MASK Register */ + +/** \brief DAC hardware registers */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef struct { + __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ + __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 (R/W 8) Control B */ + __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */ + RoReg8 Reserved1[0x1]; + __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ + __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ + __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ + __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x07 (R/ 8) Status */ + __I DAC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */ + __IO DAC_DACCTRL_Type DACCTRL[2]; /**< \brief Offset: 0x0C (R/W 16) DAC n Control */ + __O DAC_DATA_Type DATA[2]; /**< \brief Offset: 0x10 ( /W 16) DAC n Data */ + __O DAC_DATABUF_Type DATABUF[2]; /**< \brief Offset: 0x14 ( /W 16) DAC n Data Buffer */ + __IO DAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x18 (R/W 8) Debug Control */ + RoReg8 Reserved2[0x3]; + __I DAC_RESULT_Type RESULT[2]; /**< \brief Offset: 0x1C (R/ 16) Filter Result */ +} Dac; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +/*@}*/ + +#endif /* _SAME54_DAC_COMPONENT_ */ diff --git a/software/firmware/oracle_same54n19a/include/component/dmac.h b/software/firmware/oracle_same54n19a/include/component/dmac.h new file mode 100644 index 00000000..a611b79d --- /dev/null +++ b/software/firmware/oracle_same54n19a/include/component/dmac.h @@ -0,0 +1,1416 @@ +/** + * \file + * + * \brief Component description for DMAC + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54_DMAC_COMPONENT_ +#define _SAME54_DMAC_COMPONENT_ + +/* ========================================================================== */ +/** SOFTWARE API DEFINITION FOR DMAC */ +/* ========================================================================== */ +/** \addtogroup SAME54_DMAC Direct Memory Access Controller */ +/*@{*/ + +#define DMAC_U2503 +#define REV_DMAC 0x101 + +/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t SWRST:1; /*!< bit: 0 Software Reset */ + uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */ + uint16_t :6; /*!< bit: 2.. 7 Reserved */ + uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */ + uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */ + uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */ + uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } bit; /*!< Structure used for bit access */ + struct { + uint16_t :8; /*!< bit: 0.. 7 Reserved */ + uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */ + uint16_t :4; /*!< bit: 12..15 Reserved */ + } vec; /*!< Structure used for vec access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_CTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CTRL_OFFSET 0x00 /**< \brief (DMAC_CTRL offset) Control */ +#define DMAC_CTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_CTRL reset_value) Control */ + +#define DMAC_CTRL_SWRST_Pos 0 /**< \brief (DMAC_CTRL) Software Reset */ +#define DMAC_CTRL_SWRST (_U_(0x1) << DMAC_CTRL_SWRST_Pos) +#define DMAC_CTRL_DMAENABLE_Pos 1 /**< \brief (DMAC_CTRL) DMA Enable */ +#define DMAC_CTRL_DMAENABLE (_U_(0x1) << DMAC_CTRL_DMAENABLE_Pos) +#define DMAC_CTRL_LVLEN0_Pos 8 /**< \brief (DMAC_CTRL) Priority Level 0 Enable */ +#define DMAC_CTRL_LVLEN0 (_U_(1) << DMAC_CTRL_LVLEN0_Pos) +#define DMAC_CTRL_LVLEN1_Pos 9 /**< \brief (DMAC_CTRL) Priority Level 1 Enable */ +#define DMAC_CTRL_LVLEN1 (_U_(1) << DMAC_CTRL_LVLEN1_Pos) +#define DMAC_CTRL_LVLEN2_Pos 10 /**< \brief (DMAC_CTRL) Priority Level 2 Enable */ +#define DMAC_CTRL_LVLEN2 (_U_(1) << DMAC_CTRL_LVLEN2_Pos) +#define DMAC_CTRL_LVLEN3_Pos 11 /**< \brief (DMAC_CTRL) Priority Level 3 Enable */ +#define DMAC_CTRL_LVLEN3 (_U_(1) << DMAC_CTRL_LVLEN3_Pos) +#define DMAC_CTRL_LVLEN_Pos 8 /**< \brief (DMAC_CTRL) Priority Level x Enable */ +#define DMAC_CTRL_LVLEN_Msk (_U_(0xF) << DMAC_CTRL_LVLEN_Pos) +#define DMAC_CTRL_LVLEN(value) (DMAC_CTRL_LVLEN_Msk & ((value) << DMAC_CTRL_LVLEN_Pos)) +#define DMAC_CTRL_MASK _U_(0x0F03) /**< \brief (DMAC_CTRL) MASK Register */ + +/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */ + uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */ + uint16_t :4; /*!< bit: 4.. 7 Reserved */ + uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */ + uint16_t CRCMODE:2; /*!< bit: 14..15 CRC Operating Mode */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_CRCCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCCTRL_OFFSET 0x02 /**< \brief (DMAC_CRCCTRL offset) CRC Control */ +#define DMAC_CRCCTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_CRCCTRL reset_value) CRC Control */ + +#define DMAC_CRCCTRL_CRCBEATSIZE_Pos 0 /**< \brief (DMAC_CRCCTRL) CRC Beat Size */ +#define DMAC_CRCCTRL_CRCBEATSIZE_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCBEATSIZE(value) (DMAC_CRCCTRL_CRCBEATSIZE_Msk & ((value) << DMAC_CRCCTRL_CRCBEATSIZE_Pos)) +#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) 8-bit bus transfer */ +#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) 16-bit bus transfer */ +#define DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val _U_(0x2) /**< \brief (DMAC_CRCCTRL) 32-bit bus transfer */ +#define DMAC_CRCCTRL_CRCBEATSIZE_BYTE (DMAC_CRCCTRL_CRCBEATSIZE_BYTE_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCBEATSIZE_HWORD (DMAC_CRCCTRL_CRCBEATSIZE_HWORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCBEATSIZE_WORD (DMAC_CRCCTRL_CRCBEATSIZE_WORD_Val << DMAC_CRCCTRL_CRCBEATSIZE_Pos) +#define DMAC_CRCCTRL_CRCPOLY_Pos 2 /**< \brief (DMAC_CRCCTRL) CRC Polynomial Type */ +#define DMAC_CRCCTRL_CRCPOLY_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCPOLY_Pos) +#define DMAC_CRCCTRL_CRCPOLY(value) (DMAC_CRCCTRL_CRCPOLY_Msk & ((value) << DMAC_CRCCTRL_CRCPOLY_Pos)) +#define DMAC_CRCCTRL_CRCPOLY_CRC16_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) CRC-16 (CRC-CCITT) */ +#define DMAC_CRCCTRL_CRCPOLY_CRC32_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) CRC32 (IEEE 802.3) */ +#define DMAC_CRCCTRL_CRCPOLY_CRC16 (DMAC_CRCCTRL_CRCPOLY_CRC16_Val << DMAC_CRCCTRL_CRCPOLY_Pos) +#define DMAC_CRCCTRL_CRCPOLY_CRC32 (DMAC_CRCCTRL_CRCPOLY_CRC32_Val << DMAC_CRCCTRL_CRCPOLY_Pos) +#define DMAC_CRCCTRL_CRCSRC_Pos 8 /**< \brief (DMAC_CRCCTRL) CRC Input Source */ +#define DMAC_CRCCTRL_CRCSRC_Msk (_U_(0x3F) << DMAC_CRCCTRL_CRCSRC_Pos) +#define DMAC_CRCCTRL_CRCSRC(value) (DMAC_CRCCTRL_CRCSRC_Msk & ((value) << DMAC_CRCCTRL_CRCSRC_Pos)) +#define DMAC_CRCCTRL_CRCSRC_DISABLE_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) CRC Disabled */ +#define DMAC_CRCCTRL_CRCSRC_IO_Val _U_(0x1) /**< \brief (DMAC_CRCCTRL) I/O interface */ +#define DMAC_CRCCTRL_CRCSRC_DISABLE (DMAC_CRCCTRL_CRCSRC_DISABLE_Val << DMAC_CRCCTRL_CRCSRC_Pos) +#define DMAC_CRCCTRL_CRCSRC_IO (DMAC_CRCCTRL_CRCSRC_IO_Val << DMAC_CRCCTRL_CRCSRC_Pos) +#define DMAC_CRCCTRL_CRCMODE_Pos 14 /**< \brief (DMAC_CRCCTRL) CRC Operating Mode */ +#define DMAC_CRCCTRL_CRCMODE_Msk (_U_(0x3) << DMAC_CRCCTRL_CRCMODE_Pos) +#define DMAC_CRCCTRL_CRCMODE(value) (DMAC_CRCCTRL_CRCMODE_Msk & ((value) << DMAC_CRCCTRL_CRCMODE_Pos)) +#define DMAC_CRCCTRL_CRCMODE_DEFAULT_Val _U_(0x0) /**< \brief (DMAC_CRCCTRL) Default operating mode */ +#define DMAC_CRCCTRL_CRCMODE_CRCMON_Val _U_(0x2) /**< \brief (DMAC_CRCCTRL) Memory CRC monitor operating mode */ +#define DMAC_CRCCTRL_CRCMODE_CRCGEN_Val _U_(0x3) /**< \brief (DMAC_CRCCTRL) Memory CRC generation operating mode */ +#define DMAC_CRCCTRL_CRCMODE_DEFAULT (DMAC_CRCCTRL_CRCMODE_DEFAULT_Val << DMAC_CRCCTRL_CRCMODE_Pos) +#define DMAC_CRCCTRL_CRCMODE_CRCMON (DMAC_CRCCTRL_CRCMODE_CRCMON_Val << DMAC_CRCCTRL_CRCMODE_Pos) +#define DMAC_CRCCTRL_CRCMODE_CRCGEN (DMAC_CRCCTRL_CRCMODE_CRCGEN_Val << DMAC_CRCCTRL_CRCMODE_Pos) +#define DMAC_CRCCTRL_MASK _U_(0xFF0F) /**< \brief (DMAC_CRCCTRL) MASK Register */ + +/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_CRCDATAIN_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCDATAIN_OFFSET 0x04 /**< \brief (DMAC_CRCDATAIN offset) CRC Data Input */ +#define DMAC_CRCDATAIN_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CRCDATAIN reset_value) CRC Data Input */ + +#define DMAC_CRCDATAIN_CRCDATAIN_Pos 0 /**< \brief (DMAC_CRCDATAIN) CRC Data Input */ +#define DMAC_CRCDATAIN_CRCDATAIN_Msk (_U_(0xFFFFFFFF) << DMAC_CRCDATAIN_CRCDATAIN_Pos) +#define DMAC_CRCDATAIN_CRCDATAIN(value) (DMAC_CRCDATAIN_CRCDATAIN_Msk & ((value) << DMAC_CRCDATAIN_CRCDATAIN_Pos)) +#define DMAC_CRCDATAIN_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCDATAIN) MASK Register */ + +/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_CRCCHKSUM_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCCHKSUM_OFFSET 0x08 /**< \brief (DMAC_CRCCHKSUM offset) CRC Checksum */ +#define DMAC_CRCCHKSUM_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CRCCHKSUM reset_value) CRC Checksum */ + +#define DMAC_CRCCHKSUM_CRCCHKSUM_Pos 0 /**< \brief (DMAC_CRCCHKSUM) CRC Checksum */ +#define DMAC_CRCCHKSUM_CRCCHKSUM_Msk (_U_(0xFFFFFFFF) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos) +#define DMAC_CRCCHKSUM_CRCCHKSUM(value) (DMAC_CRCCHKSUM_CRCCHKSUM_Msk & ((value) << DMAC_CRCCHKSUM_CRCCHKSUM_Pos)) +#define DMAC_CRCCHKSUM_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_CRCCHKSUM) MASK Register */ + +/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */ + uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */ + uint8_t CRCERR:1; /*!< bit: 2 CRC Error */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CRCSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CRCSTATUS_OFFSET 0x0C /**< \brief (DMAC_CRCSTATUS offset) CRC Status */ +#define DMAC_CRCSTATUS_RESETVALUE _U_(0x00) /**< \brief (DMAC_CRCSTATUS reset_value) CRC Status */ + +#define DMAC_CRCSTATUS_CRCBUSY_Pos 0 /**< \brief (DMAC_CRCSTATUS) CRC Module Busy */ +#define DMAC_CRCSTATUS_CRCBUSY (_U_(0x1) << DMAC_CRCSTATUS_CRCBUSY_Pos) +#define DMAC_CRCSTATUS_CRCZERO_Pos 1 /**< \brief (DMAC_CRCSTATUS) CRC Zero */ +#define DMAC_CRCSTATUS_CRCZERO (_U_(0x1) << DMAC_CRCSTATUS_CRCZERO_Pos) +#define DMAC_CRCSTATUS_CRCERR_Pos 2 /**< \brief (DMAC_CRCSTATUS) CRC Error */ +#define DMAC_CRCSTATUS_CRCERR (_U_(0x1) << DMAC_CRCSTATUS_CRCERR_Pos) +#define DMAC_CRCSTATUS_MASK _U_(0x07) /**< \brief (DMAC_CRCSTATUS) MASK Register */ + +/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ + uint8_t :7; /*!< bit: 1.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_DBGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_DBGCTRL_OFFSET 0x0D /**< \brief (DMAC_DBGCTRL offset) Debug Control */ +#define DMAC_DBGCTRL_RESETVALUE _U_(0x00) /**< \brief (DMAC_DBGCTRL reset_value) Debug Control */ + +#define DMAC_DBGCTRL_DBGRUN_Pos 0 /**< \brief (DMAC_DBGCTRL) Debug Run */ +#define DMAC_DBGCTRL_DBGRUN (_U_(0x1) << DMAC_DBGCTRL_DBGRUN_Pos) +#define DMAC_DBGCTRL_MASK _U_(0x01) /**< \brief (DMAC_DBGCTRL) MASK Register */ + +/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */ + uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */ + uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */ + uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */ + uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */ + uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */ + uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */ + uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */ + uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */ + uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */ + uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */ + uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */ + uint32_t SWTRIG12:1; /*!< bit: 12 Channel 12 Software Trigger */ + uint32_t SWTRIG13:1; /*!< bit: 13 Channel 13 Software Trigger */ + uint32_t SWTRIG14:1; /*!< bit: 14 Channel 14 Software Trigger */ + uint32_t SWTRIG15:1; /*!< bit: 15 Channel 15 Software Trigger */ + uint32_t SWTRIG16:1; /*!< bit: 16 Channel 16 Software Trigger */ + uint32_t SWTRIG17:1; /*!< bit: 17 Channel 17 Software Trigger */ + uint32_t SWTRIG18:1; /*!< bit: 18 Channel 18 Software Trigger */ + uint32_t SWTRIG19:1; /*!< bit: 19 Channel 19 Software Trigger */ + uint32_t SWTRIG20:1; /*!< bit: 20 Channel 20 Software Trigger */ + uint32_t SWTRIG21:1; /*!< bit: 21 Channel 21 Software Trigger */ + uint32_t SWTRIG22:1; /*!< bit: 22 Channel 22 Software Trigger */ + uint32_t SWTRIG23:1; /*!< bit: 23 Channel 23 Software Trigger */ + uint32_t SWTRIG24:1; /*!< bit: 24 Channel 24 Software Trigger */ + uint32_t SWTRIG25:1; /*!< bit: 25 Channel 25 Software Trigger */ + uint32_t SWTRIG26:1; /*!< bit: 26 Channel 26 Software Trigger */ + uint32_t SWTRIG27:1; /*!< bit: 27 Channel 27 Software Trigger */ + uint32_t SWTRIG28:1; /*!< bit: 28 Channel 28 Software Trigger */ + uint32_t SWTRIG29:1; /*!< bit: 29 Channel 29 Software Trigger */ + uint32_t SWTRIG30:1; /*!< bit: 30 Channel 30 Software Trigger */ + uint32_t SWTRIG31:1; /*!< bit: 31 Channel 31 Software Trigger */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t SWTRIG:32; /*!< bit: 0..31 Channel x Software Trigger */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_SWTRIGCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_SWTRIGCTRL_OFFSET 0x10 /**< \brief (DMAC_SWTRIGCTRL offset) Software Trigger Control */ +#define DMAC_SWTRIGCTRL_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_SWTRIGCTRL reset_value) Software Trigger Control */ + +#define DMAC_SWTRIGCTRL_SWTRIG0_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel 0 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG0 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG0_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG1_Pos 1 /**< \brief (DMAC_SWTRIGCTRL) Channel 1 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG1 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG1_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG2_Pos 2 /**< \brief (DMAC_SWTRIGCTRL) Channel 2 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG2 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG2_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG3_Pos 3 /**< \brief (DMAC_SWTRIGCTRL) Channel 3 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG3 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG3_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG4_Pos 4 /**< \brief (DMAC_SWTRIGCTRL) Channel 4 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG4 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG4_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG5_Pos 5 /**< \brief (DMAC_SWTRIGCTRL) Channel 5 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG5 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG5_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG6_Pos 6 /**< \brief (DMAC_SWTRIGCTRL) Channel 6 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG6 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG6_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG7_Pos 7 /**< \brief (DMAC_SWTRIGCTRL) Channel 7 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG7 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG7_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG8_Pos 8 /**< \brief (DMAC_SWTRIGCTRL) Channel 8 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG8 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG8_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG9_Pos 9 /**< \brief (DMAC_SWTRIGCTRL) Channel 9 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG9 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG9_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG10_Pos 10 /**< \brief (DMAC_SWTRIGCTRL) Channel 10 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG10 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG10_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG11_Pos 11 /**< \brief (DMAC_SWTRIGCTRL) Channel 11 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG11 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG11_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG12_Pos 12 /**< \brief (DMAC_SWTRIGCTRL) Channel 12 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG12 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG12_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG13_Pos 13 /**< \brief (DMAC_SWTRIGCTRL) Channel 13 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG13 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG13_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG14_Pos 14 /**< \brief (DMAC_SWTRIGCTRL) Channel 14 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG14 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG14_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG15_Pos 15 /**< \brief (DMAC_SWTRIGCTRL) Channel 15 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG15 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG15_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG16_Pos 16 /**< \brief (DMAC_SWTRIGCTRL) Channel 16 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG16 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG16_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG17_Pos 17 /**< \brief (DMAC_SWTRIGCTRL) Channel 17 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG17 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG17_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG18_Pos 18 /**< \brief (DMAC_SWTRIGCTRL) Channel 18 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG18 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG18_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG19_Pos 19 /**< \brief (DMAC_SWTRIGCTRL) Channel 19 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG19 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG19_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG20_Pos 20 /**< \brief (DMAC_SWTRIGCTRL) Channel 20 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG20 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG20_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG21_Pos 21 /**< \brief (DMAC_SWTRIGCTRL) Channel 21 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG21 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG21_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG22_Pos 22 /**< \brief (DMAC_SWTRIGCTRL) Channel 22 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG22 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG22_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG23_Pos 23 /**< \brief (DMAC_SWTRIGCTRL) Channel 23 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG23 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG23_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG24_Pos 24 /**< \brief (DMAC_SWTRIGCTRL) Channel 24 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG24 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG24_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG25_Pos 25 /**< \brief (DMAC_SWTRIGCTRL) Channel 25 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG25 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG25_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG26_Pos 26 /**< \brief (DMAC_SWTRIGCTRL) Channel 26 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG26 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG26_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG27_Pos 27 /**< \brief (DMAC_SWTRIGCTRL) Channel 27 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG27 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG27_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG28_Pos 28 /**< \brief (DMAC_SWTRIGCTRL) Channel 28 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG28 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG28_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG29_Pos 29 /**< \brief (DMAC_SWTRIGCTRL) Channel 29 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG29 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG29_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG30_Pos 30 /**< \brief (DMAC_SWTRIGCTRL) Channel 30 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG30 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG30_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG31_Pos 31 /**< \brief (DMAC_SWTRIGCTRL) Channel 31 Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG31 (_U_(1) << DMAC_SWTRIGCTRL_SWTRIG31_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG_Pos 0 /**< \brief (DMAC_SWTRIGCTRL) Channel x Software Trigger */ +#define DMAC_SWTRIGCTRL_SWTRIG_Msk (_U_(0xFFFFFFFF) << DMAC_SWTRIGCTRL_SWTRIG_Pos) +#define DMAC_SWTRIGCTRL_SWTRIG(value) (DMAC_SWTRIGCTRL_SWTRIG_Msk & ((value) << DMAC_SWTRIGCTRL_SWTRIG_Pos)) +#define DMAC_SWTRIGCTRL_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_SWTRIGCTRL) MASK Register */ + +/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t LVLPRI0:5; /*!< bit: 0.. 4 Level 0 Channel Priority Number */ + uint32_t QOS0:2; /*!< bit: 5.. 6 Level 0 Quality of Service */ + uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */ + uint32_t LVLPRI1:5; /*!< bit: 8..12 Level 1 Channel Priority Number */ + uint32_t QOS1:2; /*!< bit: 13..14 Level 1 Quality of Service */ + uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */ + uint32_t LVLPRI2:5; /*!< bit: 16..20 Level 2 Channel Priority Number */ + uint32_t QOS2:2; /*!< bit: 21..22 Level 2 Quality of Service */ + uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */ + uint32_t LVLPRI3:5; /*!< bit: 24..28 Level 3 Channel Priority Number */ + uint32_t QOS3:2; /*!< bit: 29..30 Level 3 Quality of Service */ + uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_PRICTRL0_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_PRICTRL0_OFFSET 0x14 /**< \brief (DMAC_PRICTRL0 offset) Priority Control 0 */ +#define DMAC_PRICTRL0_RESETVALUE _U_(0x40404040) /**< \brief (DMAC_PRICTRL0 reset_value) Priority Control 0 */ + +#define DMAC_PRICTRL0_LVLPRI0_Pos 0 /**< \brief (DMAC_PRICTRL0) Level 0 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI0_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI0_Pos) +#define DMAC_PRICTRL0_LVLPRI0(value) (DMAC_PRICTRL0_LVLPRI0_Msk & ((value) << DMAC_PRICTRL0_LVLPRI0_Pos)) +#define DMAC_PRICTRL0_QOS0_Pos 5 /**< \brief (DMAC_PRICTRL0) Level 0 Quality of Service */ +#define DMAC_PRICTRL0_QOS0_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS0_Pos) +#define DMAC_PRICTRL0_QOS0(value) (DMAC_PRICTRL0_QOS0_Msk & ((value) << DMAC_PRICTRL0_QOS0_Pos)) +#define DMAC_PRICTRL0_QOS0_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */ +#define DMAC_PRICTRL0_QOS0_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */ +#define DMAC_PRICTRL0_QOS0_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */ +#define DMAC_PRICTRL0_QOS0_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */ +#define DMAC_PRICTRL0_QOS0_REGULAR (DMAC_PRICTRL0_QOS0_REGULAR_Val << DMAC_PRICTRL0_QOS0_Pos) +#define DMAC_PRICTRL0_QOS0_SHORTAGE (DMAC_PRICTRL0_QOS0_SHORTAGE_Val << DMAC_PRICTRL0_QOS0_Pos) +#define DMAC_PRICTRL0_QOS0_SENSITIVE (DMAC_PRICTRL0_QOS0_SENSITIVE_Val << DMAC_PRICTRL0_QOS0_Pos) +#define DMAC_PRICTRL0_QOS0_CRITICAL (DMAC_PRICTRL0_QOS0_CRITICAL_Val << DMAC_PRICTRL0_QOS0_Pos) +#define DMAC_PRICTRL0_RRLVLEN0_Pos 7 /**< \brief (DMAC_PRICTRL0) Level 0 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN0 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN0_Pos) +#define DMAC_PRICTRL0_LVLPRI1_Pos 8 /**< \brief (DMAC_PRICTRL0) Level 1 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI1_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI1_Pos) +#define DMAC_PRICTRL0_LVLPRI1(value) (DMAC_PRICTRL0_LVLPRI1_Msk & ((value) << DMAC_PRICTRL0_LVLPRI1_Pos)) +#define DMAC_PRICTRL0_QOS1_Pos 13 /**< \brief (DMAC_PRICTRL0) Level 1 Quality of Service */ +#define DMAC_PRICTRL0_QOS1_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS1_Pos) +#define DMAC_PRICTRL0_QOS1(value) (DMAC_PRICTRL0_QOS1_Msk & ((value) << DMAC_PRICTRL0_QOS1_Pos)) +#define DMAC_PRICTRL0_QOS1_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */ +#define DMAC_PRICTRL0_QOS1_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */ +#define DMAC_PRICTRL0_QOS1_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */ +#define DMAC_PRICTRL0_QOS1_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */ +#define DMAC_PRICTRL0_QOS1_REGULAR (DMAC_PRICTRL0_QOS1_REGULAR_Val << DMAC_PRICTRL0_QOS1_Pos) +#define DMAC_PRICTRL0_QOS1_SHORTAGE (DMAC_PRICTRL0_QOS1_SHORTAGE_Val << DMAC_PRICTRL0_QOS1_Pos) +#define DMAC_PRICTRL0_QOS1_SENSITIVE (DMAC_PRICTRL0_QOS1_SENSITIVE_Val << DMAC_PRICTRL0_QOS1_Pos) +#define DMAC_PRICTRL0_QOS1_CRITICAL (DMAC_PRICTRL0_QOS1_CRITICAL_Val << DMAC_PRICTRL0_QOS1_Pos) +#define DMAC_PRICTRL0_RRLVLEN1_Pos 15 /**< \brief (DMAC_PRICTRL0) Level 1 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN1 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN1_Pos) +#define DMAC_PRICTRL0_LVLPRI2_Pos 16 /**< \brief (DMAC_PRICTRL0) Level 2 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI2_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI2_Pos) +#define DMAC_PRICTRL0_LVLPRI2(value) (DMAC_PRICTRL0_LVLPRI2_Msk & ((value) << DMAC_PRICTRL0_LVLPRI2_Pos)) +#define DMAC_PRICTRL0_QOS2_Pos 21 /**< \brief (DMAC_PRICTRL0) Level 2 Quality of Service */ +#define DMAC_PRICTRL0_QOS2_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS2_Pos) +#define DMAC_PRICTRL0_QOS2(value) (DMAC_PRICTRL0_QOS2_Msk & ((value) << DMAC_PRICTRL0_QOS2_Pos)) +#define DMAC_PRICTRL0_QOS2_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */ +#define DMAC_PRICTRL0_QOS2_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */ +#define DMAC_PRICTRL0_QOS2_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */ +#define DMAC_PRICTRL0_QOS2_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */ +#define DMAC_PRICTRL0_QOS2_REGULAR (DMAC_PRICTRL0_QOS2_REGULAR_Val << DMAC_PRICTRL0_QOS2_Pos) +#define DMAC_PRICTRL0_QOS2_SHORTAGE (DMAC_PRICTRL0_QOS2_SHORTAGE_Val << DMAC_PRICTRL0_QOS2_Pos) +#define DMAC_PRICTRL0_QOS2_SENSITIVE (DMAC_PRICTRL0_QOS2_SENSITIVE_Val << DMAC_PRICTRL0_QOS2_Pos) +#define DMAC_PRICTRL0_QOS2_CRITICAL (DMAC_PRICTRL0_QOS2_CRITICAL_Val << DMAC_PRICTRL0_QOS2_Pos) +#define DMAC_PRICTRL0_RRLVLEN2_Pos 23 /**< \brief (DMAC_PRICTRL0) Level 2 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN2 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN2_Pos) +#define DMAC_PRICTRL0_LVLPRI3_Pos 24 /**< \brief (DMAC_PRICTRL0) Level 3 Channel Priority Number */ +#define DMAC_PRICTRL0_LVLPRI3_Msk (_U_(0x1F) << DMAC_PRICTRL0_LVLPRI3_Pos) +#define DMAC_PRICTRL0_LVLPRI3(value) (DMAC_PRICTRL0_LVLPRI3_Msk & ((value) << DMAC_PRICTRL0_LVLPRI3_Pos)) +#define DMAC_PRICTRL0_QOS3_Pos 29 /**< \brief (DMAC_PRICTRL0) Level 3 Quality of Service */ +#define DMAC_PRICTRL0_QOS3_Msk (_U_(0x3) << DMAC_PRICTRL0_QOS3_Pos) +#define DMAC_PRICTRL0_QOS3(value) (DMAC_PRICTRL0_QOS3_Msk & ((value) << DMAC_PRICTRL0_QOS3_Pos)) +#define DMAC_PRICTRL0_QOS3_REGULAR_Val _U_(0x0) /**< \brief (DMAC_PRICTRL0) Regular delivery */ +#define DMAC_PRICTRL0_QOS3_SHORTAGE_Val _U_(0x1) /**< \brief (DMAC_PRICTRL0) Bandwidth shortage */ +#define DMAC_PRICTRL0_QOS3_SENSITIVE_Val _U_(0x2) /**< \brief (DMAC_PRICTRL0) Latency sensitive */ +#define DMAC_PRICTRL0_QOS3_CRITICAL_Val _U_(0x3) /**< \brief (DMAC_PRICTRL0) Latency critical */ +#define DMAC_PRICTRL0_QOS3_REGULAR (DMAC_PRICTRL0_QOS3_REGULAR_Val << DMAC_PRICTRL0_QOS3_Pos) +#define DMAC_PRICTRL0_QOS3_SHORTAGE (DMAC_PRICTRL0_QOS3_SHORTAGE_Val << DMAC_PRICTRL0_QOS3_Pos) +#define DMAC_PRICTRL0_QOS3_SENSITIVE (DMAC_PRICTRL0_QOS3_SENSITIVE_Val << DMAC_PRICTRL0_QOS3_Pos) +#define DMAC_PRICTRL0_QOS3_CRITICAL (DMAC_PRICTRL0_QOS3_CRITICAL_Val << DMAC_PRICTRL0_QOS3_Pos) +#define DMAC_PRICTRL0_RRLVLEN3_Pos 31 /**< \brief (DMAC_PRICTRL0) Level 3 Round-Robin Scheduling Enable */ +#define DMAC_PRICTRL0_RRLVLEN3 (_U_(0x1) << DMAC_PRICTRL0_RRLVLEN3_Pos) +#define DMAC_PRICTRL0_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_PRICTRL0) MASK Register */ + +/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t ID:5; /*!< bit: 0.. 4 Channel ID */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t TERR:1; /*!< bit: 8 Transfer Error */ + uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */ + uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */ + uint16_t :1; /*!< bit: 11 Reserved */ + uint16_t CRCERR:1; /*!< bit: 12 CRC Error */ + uint16_t FERR:1; /*!< bit: 13 Fetch Error */ + uint16_t BUSY:1; /*!< bit: 14 Busy */ + uint16_t PEND:1; /*!< bit: 15 Pending */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_INTPEND_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_INTPEND_OFFSET 0x20 /**< \brief (DMAC_INTPEND offset) Interrupt Pending */ +#define DMAC_INTPEND_RESETVALUE _U_(0x0000) /**< \brief (DMAC_INTPEND reset_value) Interrupt Pending */ + +#define DMAC_INTPEND_ID_Pos 0 /**< \brief (DMAC_INTPEND) Channel ID */ +#define DMAC_INTPEND_ID_Msk (_U_(0x1F) << DMAC_INTPEND_ID_Pos) +#define DMAC_INTPEND_ID(value) (DMAC_INTPEND_ID_Msk & ((value) << DMAC_INTPEND_ID_Pos)) +#define DMAC_INTPEND_TERR_Pos 8 /**< \brief (DMAC_INTPEND) Transfer Error */ +#define DMAC_INTPEND_TERR (_U_(0x1) << DMAC_INTPEND_TERR_Pos) +#define DMAC_INTPEND_TCMPL_Pos 9 /**< \brief (DMAC_INTPEND) Transfer Complete */ +#define DMAC_INTPEND_TCMPL (_U_(0x1) << DMAC_INTPEND_TCMPL_Pos) +#define DMAC_INTPEND_SUSP_Pos 10 /**< \brief (DMAC_INTPEND) Channel Suspend */ +#define DMAC_INTPEND_SUSP (_U_(0x1) << DMAC_INTPEND_SUSP_Pos) +#define DMAC_INTPEND_CRCERR_Pos 12 /**< \brief (DMAC_INTPEND) CRC Error */ +#define DMAC_INTPEND_CRCERR (_U_(0x1) << DMAC_INTPEND_CRCERR_Pos) +#define DMAC_INTPEND_FERR_Pos 13 /**< \brief (DMAC_INTPEND) Fetch Error */ +#define DMAC_INTPEND_FERR (_U_(0x1) << DMAC_INTPEND_FERR_Pos) +#define DMAC_INTPEND_BUSY_Pos 14 /**< \brief (DMAC_INTPEND) Busy */ +#define DMAC_INTPEND_BUSY (_U_(0x1) << DMAC_INTPEND_BUSY_Pos) +#define DMAC_INTPEND_PEND_Pos 15 /**< \brief (DMAC_INTPEND) Pending */ +#define DMAC_INTPEND_PEND (_U_(0x1) << DMAC_INTPEND_PEND_Pos) +#define DMAC_INTPEND_MASK _U_(0xF71F) /**< \brief (DMAC_INTPEND) MASK Register */ + +/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */ + uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */ + uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */ + uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */ + uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */ + uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */ + uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */ + uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */ + uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */ + uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */ + uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */ + uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */ + uint32_t CHINT12:1; /*!< bit: 12 Channel 12 Pending Interrupt */ + uint32_t CHINT13:1; /*!< bit: 13 Channel 13 Pending Interrupt */ + uint32_t CHINT14:1; /*!< bit: 14 Channel 14 Pending Interrupt */ + uint32_t CHINT15:1; /*!< bit: 15 Channel 15 Pending Interrupt */ + uint32_t CHINT16:1; /*!< bit: 16 Channel 16 Pending Interrupt */ + uint32_t CHINT17:1; /*!< bit: 17 Channel 17 Pending Interrupt */ + uint32_t CHINT18:1; /*!< bit: 18 Channel 18 Pending Interrupt */ + uint32_t CHINT19:1; /*!< bit: 19 Channel 19 Pending Interrupt */ + uint32_t CHINT20:1; /*!< bit: 20 Channel 20 Pending Interrupt */ + uint32_t CHINT21:1; /*!< bit: 21 Channel 21 Pending Interrupt */ + uint32_t CHINT22:1; /*!< bit: 22 Channel 22 Pending Interrupt */ + uint32_t CHINT23:1; /*!< bit: 23 Channel 23 Pending Interrupt */ + uint32_t CHINT24:1; /*!< bit: 24 Channel 24 Pending Interrupt */ + uint32_t CHINT25:1; /*!< bit: 25 Channel 25 Pending Interrupt */ + uint32_t CHINT26:1; /*!< bit: 26 Channel 26 Pending Interrupt */ + uint32_t CHINT27:1; /*!< bit: 27 Channel 27 Pending Interrupt */ + uint32_t CHINT28:1; /*!< bit: 28 Channel 28 Pending Interrupt */ + uint32_t CHINT29:1; /*!< bit: 29 Channel 29 Pending Interrupt */ + uint32_t CHINT30:1; /*!< bit: 30 Channel 30 Pending Interrupt */ + uint32_t CHINT31:1; /*!< bit: 31 Channel 31 Pending Interrupt */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t CHINT:32; /*!< bit: 0..31 Channel x Pending Interrupt */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_INTSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_INTSTATUS_OFFSET 0x24 /**< \brief (DMAC_INTSTATUS offset) Interrupt Status */ +#define DMAC_INTSTATUS_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_INTSTATUS reset_value) Interrupt Status */ + +#define DMAC_INTSTATUS_CHINT0_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel 0 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT0 (_U_(1) << DMAC_INTSTATUS_CHINT0_Pos) +#define DMAC_INTSTATUS_CHINT1_Pos 1 /**< \brief (DMAC_INTSTATUS) Channel 1 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT1 (_U_(1) << DMAC_INTSTATUS_CHINT1_Pos) +#define DMAC_INTSTATUS_CHINT2_Pos 2 /**< \brief (DMAC_INTSTATUS) Channel 2 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT2 (_U_(1) << DMAC_INTSTATUS_CHINT2_Pos) +#define DMAC_INTSTATUS_CHINT3_Pos 3 /**< \brief (DMAC_INTSTATUS) Channel 3 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT3 (_U_(1) << DMAC_INTSTATUS_CHINT3_Pos) +#define DMAC_INTSTATUS_CHINT4_Pos 4 /**< \brief (DMAC_INTSTATUS) Channel 4 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT4 (_U_(1) << DMAC_INTSTATUS_CHINT4_Pos) +#define DMAC_INTSTATUS_CHINT5_Pos 5 /**< \brief (DMAC_INTSTATUS) Channel 5 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT5 (_U_(1) << DMAC_INTSTATUS_CHINT5_Pos) +#define DMAC_INTSTATUS_CHINT6_Pos 6 /**< \brief (DMAC_INTSTATUS) Channel 6 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT6 (_U_(1) << DMAC_INTSTATUS_CHINT6_Pos) +#define DMAC_INTSTATUS_CHINT7_Pos 7 /**< \brief (DMAC_INTSTATUS) Channel 7 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT7 (_U_(1) << DMAC_INTSTATUS_CHINT7_Pos) +#define DMAC_INTSTATUS_CHINT8_Pos 8 /**< \brief (DMAC_INTSTATUS) Channel 8 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT8 (_U_(1) << DMAC_INTSTATUS_CHINT8_Pos) +#define DMAC_INTSTATUS_CHINT9_Pos 9 /**< \brief (DMAC_INTSTATUS) Channel 9 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT9 (_U_(1) << DMAC_INTSTATUS_CHINT9_Pos) +#define DMAC_INTSTATUS_CHINT10_Pos 10 /**< \brief (DMAC_INTSTATUS) Channel 10 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT10 (_U_(1) << DMAC_INTSTATUS_CHINT10_Pos) +#define DMAC_INTSTATUS_CHINT11_Pos 11 /**< \brief (DMAC_INTSTATUS) Channel 11 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT11 (_U_(1) << DMAC_INTSTATUS_CHINT11_Pos) +#define DMAC_INTSTATUS_CHINT12_Pos 12 /**< \brief (DMAC_INTSTATUS) Channel 12 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT12 (_U_(1) << DMAC_INTSTATUS_CHINT12_Pos) +#define DMAC_INTSTATUS_CHINT13_Pos 13 /**< \brief (DMAC_INTSTATUS) Channel 13 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT13 (_U_(1) << DMAC_INTSTATUS_CHINT13_Pos) +#define DMAC_INTSTATUS_CHINT14_Pos 14 /**< \brief (DMAC_INTSTATUS) Channel 14 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT14 (_U_(1) << DMAC_INTSTATUS_CHINT14_Pos) +#define DMAC_INTSTATUS_CHINT15_Pos 15 /**< \brief (DMAC_INTSTATUS) Channel 15 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT15 (_U_(1) << DMAC_INTSTATUS_CHINT15_Pos) +#define DMAC_INTSTATUS_CHINT16_Pos 16 /**< \brief (DMAC_INTSTATUS) Channel 16 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT16 (_U_(1) << DMAC_INTSTATUS_CHINT16_Pos) +#define DMAC_INTSTATUS_CHINT17_Pos 17 /**< \brief (DMAC_INTSTATUS) Channel 17 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT17 (_U_(1) << DMAC_INTSTATUS_CHINT17_Pos) +#define DMAC_INTSTATUS_CHINT18_Pos 18 /**< \brief (DMAC_INTSTATUS) Channel 18 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT18 (_U_(1) << DMAC_INTSTATUS_CHINT18_Pos) +#define DMAC_INTSTATUS_CHINT19_Pos 19 /**< \brief (DMAC_INTSTATUS) Channel 19 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT19 (_U_(1) << DMAC_INTSTATUS_CHINT19_Pos) +#define DMAC_INTSTATUS_CHINT20_Pos 20 /**< \brief (DMAC_INTSTATUS) Channel 20 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT20 (_U_(1) << DMAC_INTSTATUS_CHINT20_Pos) +#define DMAC_INTSTATUS_CHINT21_Pos 21 /**< \brief (DMAC_INTSTATUS) Channel 21 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT21 (_U_(1) << DMAC_INTSTATUS_CHINT21_Pos) +#define DMAC_INTSTATUS_CHINT22_Pos 22 /**< \brief (DMAC_INTSTATUS) Channel 22 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT22 (_U_(1) << DMAC_INTSTATUS_CHINT22_Pos) +#define DMAC_INTSTATUS_CHINT23_Pos 23 /**< \brief (DMAC_INTSTATUS) Channel 23 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT23 (_U_(1) << DMAC_INTSTATUS_CHINT23_Pos) +#define DMAC_INTSTATUS_CHINT24_Pos 24 /**< \brief (DMAC_INTSTATUS) Channel 24 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT24 (_U_(1) << DMAC_INTSTATUS_CHINT24_Pos) +#define DMAC_INTSTATUS_CHINT25_Pos 25 /**< \brief (DMAC_INTSTATUS) Channel 25 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT25 (_U_(1) << DMAC_INTSTATUS_CHINT25_Pos) +#define DMAC_INTSTATUS_CHINT26_Pos 26 /**< \brief (DMAC_INTSTATUS) Channel 26 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT26 (_U_(1) << DMAC_INTSTATUS_CHINT26_Pos) +#define DMAC_INTSTATUS_CHINT27_Pos 27 /**< \brief (DMAC_INTSTATUS) Channel 27 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT27 (_U_(1) << DMAC_INTSTATUS_CHINT27_Pos) +#define DMAC_INTSTATUS_CHINT28_Pos 28 /**< \brief (DMAC_INTSTATUS) Channel 28 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT28 (_U_(1) << DMAC_INTSTATUS_CHINT28_Pos) +#define DMAC_INTSTATUS_CHINT29_Pos 29 /**< \brief (DMAC_INTSTATUS) Channel 29 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT29 (_U_(1) << DMAC_INTSTATUS_CHINT29_Pos) +#define DMAC_INTSTATUS_CHINT30_Pos 30 /**< \brief (DMAC_INTSTATUS) Channel 30 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT30 (_U_(1) << DMAC_INTSTATUS_CHINT30_Pos) +#define DMAC_INTSTATUS_CHINT31_Pos 31 /**< \brief (DMAC_INTSTATUS) Channel 31 Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT31 (_U_(1) << DMAC_INTSTATUS_CHINT31_Pos) +#define DMAC_INTSTATUS_CHINT_Pos 0 /**< \brief (DMAC_INTSTATUS) Channel x Pending Interrupt */ +#define DMAC_INTSTATUS_CHINT_Msk (_U_(0xFFFFFFFF) << DMAC_INTSTATUS_CHINT_Pos) +#define DMAC_INTSTATUS_CHINT(value) (DMAC_INTSTATUS_CHINT_Msk & ((value) << DMAC_INTSTATUS_CHINT_Pos)) +#define DMAC_INTSTATUS_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_INTSTATUS) MASK Register */ + +/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */ + uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */ + uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */ + uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */ + uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */ + uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */ + uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */ + uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */ + uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */ + uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */ + uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */ + uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */ + uint32_t BUSYCH12:1; /*!< bit: 12 Busy Channel 12 */ + uint32_t BUSYCH13:1; /*!< bit: 13 Busy Channel 13 */ + uint32_t BUSYCH14:1; /*!< bit: 14 Busy Channel 14 */ + uint32_t BUSYCH15:1; /*!< bit: 15 Busy Channel 15 */ + uint32_t BUSYCH16:1; /*!< bit: 16 Busy Channel 16 */ + uint32_t BUSYCH17:1; /*!< bit: 17 Busy Channel 17 */ + uint32_t BUSYCH18:1; /*!< bit: 18 Busy Channel 18 */ + uint32_t BUSYCH19:1; /*!< bit: 19 Busy Channel 19 */ + uint32_t BUSYCH20:1; /*!< bit: 20 Busy Channel 20 */ + uint32_t BUSYCH21:1; /*!< bit: 21 Busy Channel 21 */ + uint32_t BUSYCH22:1; /*!< bit: 22 Busy Channel 22 */ + uint32_t BUSYCH23:1; /*!< bit: 23 Busy Channel 23 */ + uint32_t BUSYCH24:1; /*!< bit: 24 Busy Channel 24 */ + uint32_t BUSYCH25:1; /*!< bit: 25 Busy Channel 25 */ + uint32_t BUSYCH26:1; /*!< bit: 26 Busy Channel 26 */ + uint32_t BUSYCH27:1; /*!< bit: 27 Busy Channel 27 */ + uint32_t BUSYCH28:1; /*!< bit: 28 Busy Channel 28 */ + uint32_t BUSYCH29:1; /*!< bit: 29 Busy Channel 29 */ + uint32_t BUSYCH30:1; /*!< bit: 30 Busy Channel 30 */ + uint32_t BUSYCH31:1; /*!< bit: 31 Busy Channel 31 */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t BUSYCH:32; /*!< bit: 0..31 Busy Channel x */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_BUSYCH_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_BUSYCH_OFFSET 0x28 /**< \brief (DMAC_BUSYCH offset) Busy Channels */ +#define DMAC_BUSYCH_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_BUSYCH reset_value) Busy Channels */ + +#define DMAC_BUSYCH_BUSYCH0_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel 0 */ +#define DMAC_BUSYCH_BUSYCH0 (_U_(1) << DMAC_BUSYCH_BUSYCH0_Pos) +#define DMAC_BUSYCH_BUSYCH1_Pos 1 /**< \brief (DMAC_BUSYCH) Busy Channel 1 */ +#define DMAC_BUSYCH_BUSYCH1 (_U_(1) << DMAC_BUSYCH_BUSYCH1_Pos) +#define DMAC_BUSYCH_BUSYCH2_Pos 2 /**< \brief (DMAC_BUSYCH) Busy Channel 2 */ +#define DMAC_BUSYCH_BUSYCH2 (_U_(1) << DMAC_BUSYCH_BUSYCH2_Pos) +#define DMAC_BUSYCH_BUSYCH3_Pos 3 /**< \brief (DMAC_BUSYCH) Busy Channel 3 */ +#define DMAC_BUSYCH_BUSYCH3 (_U_(1) << DMAC_BUSYCH_BUSYCH3_Pos) +#define DMAC_BUSYCH_BUSYCH4_Pos 4 /**< \brief (DMAC_BUSYCH) Busy Channel 4 */ +#define DMAC_BUSYCH_BUSYCH4 (_U_(1) << DMAC_BUSYCH_BUSYCH4_Pos) +#define DMAC_BUSYCH_BUSYCH5_Pos 5 /**< \brief (DMAC_BUSYCH) Busy Channel 5 */ +#define DMAC_BUSYCH_BUSYCH5 (_U_(1) << DMAC_BUSYCH_BUSYCH5_Pos) +#define DMAC_BUSYCH_BUSYCH6_Pos 6 /**< \brief (DMAC_BUSYCH) Busy Channel 6 */ +#define DMAC_BUSYCH_BUSYCH6 (_U_(1) << DMAC_BUSYCH_BUSYCH6_Pos) +#define DMAC_BUSYCH_BUSYCH7_Pos 7 /**< \brief (DMAC_BUSYCH) Busy Channel 7 */ +#define DMAC_BUSYCH_BUSYCH7 (_U_(1) << DMAC_BUSYCH_BUSYCH7_Pos) +#define DMAC_BUSYCH_BUSYCH8_Pos 8 /**< \brief (DMAC_BUSYCH) Busy Channel 8 */ +#define DMAC_BUSYCH_BUSYCH8 (_U_(1) << DMAC_BUSYCH_BUSYCH8_Pos) +#define DMAC_BUSYCH_BUSYCH9_Pos 9 /**< \brief (DMAC_BUSYCH) Busy Channel 9 */ +#define DMAC_BUSYCH_BUSYCH9 (_U_(1) << DMAC_BUSYCH_BUSYCH9_Pos) +#define DMAC_BUSYCH_BUSYCH10_Pos 10 /**< \brief (DMAC_BUSYCH) Busy Channel 10 */ +#define DMAC_BUSYCH_BUSYCH10 (_U_(1) << DMAC_BUSYCH_BUSYCH10_Pos) +#define DMAC_BUSYCH_BUSYCH11_Pos 11 /**< \brief (DMAC_BUSYCH) Busy Channel 11 */ +#define DMAC_BUSYCH_BUSYCH11 (_U_(1) << DMAC_BUSYCH_BUSYCH11_Pos) +#define DMAC_BUSYCH_BUSYCH12_Pos 12 /**< \brief (DMAC_BUSYCH) Busy Channel 12 */ +#define DMAC_BUSYCH_BUSYCH12 (_U_(1) << DMAC_BUSYCH_BUSYCH12_Pos) +#define DMAC_BUSYCH_BUSYCH13_Pos 13 /**< \brief (DMAC_BUSYCH) Busy Channel 13 */ +#define DMAC_BUSYCH_BUSYCH13 (_U_(1) << DMAC_BUSYCH_BUSYCH13_Pos) +#define DMAC_BUSYCH_BUSYCH14_Pos 14 /**< \brief (DMAC_BUSYCH) Busy Channel 14 */ +#define DMAC_BUSYCH_BUSYCH14 (_U_(1) << DMAC_BUSYCH_BUSYCH14_Pos) +#define DMAC_BUSYCH_BUSYCH15_Pos 15 /**< \brief (DMAC_BUSYCH) Busy Channel 15 */ +#define DMAC_BUSYCH_BUSYCH15 (_U_(1) << DMAC_BUSYCH_BUSYCH15_Pos) +#define DMAC_BUSYCH_BUSYCH16_Pos 16 /**< \brief (DMAC_BUSYCH) Busy Channel 16 */ +#define DMAC_BUSYCH_BUSYCH16 (_U_(1) << DMAC_BUSYCH_BUSYCH16_Pos) +#define DMAC_BUSYCH_BUSYCH17_Pos 17 /**< \brief (DMAC_BUSYCH) Busy Channel 17 */ +#define DMAC_BUSYCH_BUSYCH17 (_U_(1) << DMAC_BUSYCH_BUSYCH17_Pos) +#define DMAC_BUSYCH_BUSYCH18_Pos 18 /**< \brief (DMAC_BUSYCH) Busy Channel 18 */ +#define DMAC_BUSYCH_BUSYCH18 (_U_(1) << DMAC_BUSYCH_BUSYCH18_Pos) +#define DMAC_BUSYCH_BUSYCH19_Pos 19 /**< \brief (DMAC_BUSYCH) Busy Channel 19 */ +#define DMAC_BUSYCH_BUSYCH19 (_U_(1) << DMAC_BUSYCH_BUSYCH19_Pos) +#define DMAC_BUSYCH_BUSYCH20_Pos 20 /**< \brief (DMAC_BUSYCH) Busy Channel 20 */ +#define DMAC_BUSYCH_BUSYCH20 (_U_(1) << DMAC_BUSYCH_BUSYCH20_Pos) +#define DMAC_BUSYCH_BUSYCH21_Pos 21 /**< \brief (DMAC_BUSYCH) Busy Channel 21 */ +#define DMAC_BUSYCH_BUSYCH21 (_U_(1) << DMAC_BUSYCH_BUSYCH21_Pos) +#define DMAC_BUSYCH_BUSYCH22_Pos 22 /**< \brief (DMAC_BUSYCH) Busy Channel 22 */ +#define DMAC_BUSYCH_BUSYCH22 (_U_(1) << DMAC_BUSYCH_BUSYCH22_Pos) +#define DMAC_BUSYCH_BUSYCH23_Pos 23 /**< \brief (DMAC_BUSYCH) Busy Channel 23 */ +#define DMAC_BUSYCH_BUSYCH23 (_U_(1) << DMAC_BUSYCH_BUSYCH23_Pos) +#define DMAC_BUSYCH_BUSYCH24_Pos 24 /**< \brief (DMAC_BUSYCH) Busy Channel 24 */ +#define DMAC_BUSYCH_BUSYCH24 (_U_(1) << DMAC_BUSYCH_BUSYCH24_Pos) +#define DMAC_BUSYCH_BUSYCH25_Pos 25 /**< \brief (DMAC_BUSYCH) Busy Channel 25 */ +#define DMAC_BUSYCH_BUSYCH25 (_U_(1) << DMAC_BUSYCH_BUSYCH25_Pos) +#define DMAC_BUSYCH_BUSYCH26_Pos 26 /**< \brief (DMAC_BUSYCH) Busy Channel 26 */ +#define DMAC_BUSYCH_BUSYCH26 (_U_(1) << DMAC_BUSYCH_BUSYCH26_Pos) +#define DMAC_BUSYCH_BUSYCH27_Pos 27 /**< \brief (DMAC_BUSYCH) Busy Channel 27 */ +#define DMAC_BUSYCH_BUSYCH27 (_U_(1) << DMAC_BUSYCH_BUSYCH27_Pos) +#define DMAC_BUSYCH_BUSYCH28_Pos 28 /**< \brief (DMAC_BUSYCH) Busy Channel 28 */ +#define DMAC_BUSYCH_BUSYCH28 (_U_(1) << DMAC_BUSYCH_BUSYCH28_Pos) +#define DMAC_BUSYCH_BUSYCH29_Pos 29 /**< \brief (DMAC_BUSYCH) Busy Channel 29 */ +#define DMAC_BUSYCH_BUSYCH29 (_U_(1) << DMAC_BUSYCH_BUSYCH29_Pos) +#define DMAC_BUSYCH_BUSYCH30_Pos 30 /**< \brief (DMAC_BUSYCH) Busy Channel 30 */ +#define DMAC_BUSYCH_BUSYCH30 (_U_(1) << DMAC_BUSYCH_BUSYCH30_Pos) +#define DMAC_BUSYCH_BUSYCH31_Pos 31 /**< \brief (DMAC_BUSYCH) Busy Channel 31 */ +#define DMAC_BUSYCH_BUSYCH31 (_U_(1) << DMAC_BUSYCH_BUSYCH31_Pos) +#define DMAC_BUSYCH_BUSYCH_Pos 0 /**< \brief (DMAC_BUSYCH) Busy Channel x */ +#define DMAC_BUSYCH_BUSYCH_Msk (_U_(0xFFFFFFFF) << DMAC_BUSYCH_BUSYCH_Pos) +#define DMAC_BUSYCH_BUSYCH(value) (DMAC_BUSYCH_BUSYCH_Msk & ((value) << DMAC_BUSYCH_BUSYCH_Pos)) +#define DMAC_BUSYCH_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_BUSYCH) MASK Register */ + +/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */ + uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */ + uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */ + uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */ + uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */ + uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */ + uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */ + uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */ + uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */ + uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */ + uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */ + uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */ + uint32_t PENDCH12:1; /*!< bit: 12 Pending Channel 12 */ + uint32_t PENDCH13:1; /*!< bit: 13 Pending Channel 13 */ + uint32_t PENDCH14:1; /*!< bit: 14 Pending Channel 14 */ + uint32_t PENDCH15:1; /*!< bit: 15 Pending Channel 15 */ + uint32_t PENDCH16:1; /*!< bit: 16 Pending Channel 16 */ + uint32_t PENDCH17:1; /*!< bit: 17 Pending Channel 17 */ + uint32_t PENDCH18:1; /*!< bit: 18 Pending Channel 18 */ + uint32_t PENDCH19:1; /*!< bit: 19 Pending Channel 19 */ + uint32_t PENDCH20:1; /*!< bit: 20 Pending Channel 20 */ + uint32_t PENDCH21:1; /*!< bit: 21 Pending Channel 21 */ + uint32_t PENDCH22:1; /*!< bit: 22 Pending Channel 22 */ + uint32_t PENDCH23:1; /*!< bit: 23 Pending Channel 23 */ + uint32_t PENDCH24:1; /*!< bit: 24 Pending Channel 24 */ + uint32_t PENDCH25:1; /*!< bit: 25 Pending Channel 25 */ + uint32_t PENDCH26:1; /*!< bit: 26 Pending Channel 26 */ + uint32_t PENDCH27:1; /*!< bit: 27 Pending Channel 27 */ + uint32_t PENDCH28:1; /*!< bit: 28 Pending Channel 28 */ + uint32_t PENDCH29:1; /*!< bit: 29 Pending Channel 29 */ + uint32_t PENDCH30:1; /*!< bit: 30 Pending Channel 30 */ + uint32_t PENDCH31:1; /*!< bit: 31 Pending Channel 31 */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t PENDCH:32; /*!< bit: 0..31 Pending Channel x */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_PENDCH_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_PENDCH_OFFSET 0x2C /**< \brief (DMAC_PENDCH offset) Pending Channels */ +#define DMAC_PENDCH_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_PENDCH reset_value) Pending Channels */ + +#define DMAC_PENDCH_PENDCH0_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel 0 */ +#define DMAC_PENDCH_PENDCH0 (_U_(1) << DMAC_PENDCH_PENDCH0_Pos) +#define DMAC_PENDCH_PENDCH1_Pos 1 /**< \brief (DMAC_PENDCH) Pending Channel 1 */ +#define DMAC_PENDCH_PENDCH1 (_U_(1) << DMAC_PENDCH_PENDCH1_Pos) +#define DMAC_PENDCH_PENDCH2_Pos 2 /**< \brief (DMAC_PENDCH) Pending Channel 2 */ +#define DMAC_PENDCH_PENDCH2 (_U_(1) << DMAC_PENDCH_PENDCH2_Pos) +#define DMAC_PENDCH_PENDCH3_Pos 3 /**< \brief (DMAC_PENDCH) Pending Channel 3 */ +#define DMAC_PENDCH_PENDCH3 (_U_(1) << DMAC_PENDCH_PENDCH3_Pos) +#define DMAC_PENDCH_PENDCH4_Pos 4 /**< \brief (DMAC_PENDCH) Pending Channel 4 */ +#define DMAC_PENDCH_PENDCH4 (_U_(1) << DMAC_PENDCH_PENDCH4_Pos) +#define DMAC_PENDCH_PENDCH5_Pos 5 /**< \brief (DMAC_PENDCH) Pending Channel 5 */ +#define DMAC_PENDCH_PENDCH5 (_U_(1) << DMAC_PENDCH_PENDCH5_Pos) +#define DMAC_PENDCH_PENDCH6_Pos 6 /**< \brief (DMAC_PENDCH) Pending Channel 6 */ +#define DMAC_PENDCH_PENDCH6 (_U_(1) << DMAC_PENDCH_PENDCH6_Pos) +#define DMAC_PENDCH_PENDCH7_Pos 7 /**< \brief (DMAC_PENDCH) Pending Channel 7 */ +#define DMAC_PENDCH_PENDCH7 (_U_(1) << DMAC_PENDCH_PENDCH7_Pos) +#define DMAC_PENDCH_PENDCH8_Pos 8 /**< \brief (DMAC_PENDCH) Pending Channel 8 */ +#define DMAC_PENDCH_PENDCH8 (_U_(1) << DMAC_PENDCH_PENDCH8_Pos) +#define DMAC_PENDCH_PENDCH9_Pos 9 /**< \brief (DMAC_PENDCH) Pending Channel 9 */ +#define DMAC_PENDCH_PENDCH9 (_U_(1) << DMAC_PENDCH_PENDCH9_Pos) +#define DMAC_PENDCH_PENDCH10_Pos 10 /**< \brief (DMAC_PENDCH) Pending Channel 10 */ +#define DMAC_PENDCH_PENDCH10 (_U_(1) << DMAC_PENDCH_PENDCH10_Pos) +#define DMAC_PENDCH_PENDCH11_Pos 11 /**< \brief (DMAC_PENDCH) Pending Channel 11 */ +#define DMAC_PENDCH_PENDCH11 (_U_(1) << DMAC_PENDCH_PENDCH11_Pos) +#define DMAC_PENDCH_PENDCH12_Pos 12 /**< \brief (DMAC_PENDCH) Pending Channel 12 */ +#define DMAC_PENDCH_PENDCH12 (_U_(1) << DMAC_PENDCH_PENDCH12_Pos) +#define DMAC_PENDCH_PENDCH13_Pos 13 /**< \brief (DMAC_PENDCH) Pending Channel 13 */ +#define DMAC_PENDCH_PENDCH13 (_U_(1) << DMAC_PENDCH_PENDCH13_Pos) +#define DMAC_PENDCH_PENDCH14_Pos 14 /**< \brief (DMAC_PENDCH) Pending Channel 14 */ +#define DMAC_PENDCH_PENDCH14 (_U_(1) << DMAC_PENDCH_PENDCH14_Pos) +#define DMAC_PENDCH_PENDCH15_Pos 15 /**< \brief (DMAC_PENDCH) Pending Channel 15 */ +#define DMAC_PENDCH_PENDCH15 (_U_(1) << DMAC_PENDCH_PENDCH15_Pos) +#define DMAC_PENDCH_PENDCH16_Pos 16 /**< \brief (DMAC_PENDCH) Pending Channel 16 */ +#define DMAC_PENDCH_PENDCH16 (_U_(1) << DMAC_PENDCH_PENDCH16_Pos) +#define DMAC_PENDCH_PENDCH17_Pos 17 /**< \brief (DMAC_PENDCH) Pending Channel 17 */ +#define DMAC_PENDCH_PENDCH17 (_U_(1) << DMAC_PENDCH_PENDCH17_Pos) +#define DMAC_PENDCH_PENDCH18_Pos 18 /**< \brief (DMAC_PENDCH) Pending Channel 18 */ +#define DMAC_PENDCH_PENDCH18 (_U_(1) << DMAC_PENDCH_PENDCH18_Pos) +#define DMAC_PENDCH_PENDCH19_Pos 19 /**< \brief (DMAC_PENDCH) Pending Channel 19 */ +#define DMAC_PENDCH_PENDCH19 (_U_(1) << DMAC_PENDCH_PENDCH19_Pos) +#define DMAC_PENDCH_PENDCH20_Pos 20 /**< \brief (DMAC_PENDCH) Pending Channel 20 */ +#define DMAC_PENDCH_PENDCH20 (_U_(1) << DMAC_PENDCH_PENDCH20_Pos) +#define DMAC_PENDCH_PENDCH21_Pos 21 /**< \brief (DMAC_PENDCH) Pending Channel 21 */ +#define DMAC_PENDCH_PENDCH21 (_U_(1) << DMAC_PENDCH_PENDCH21_Pos) +#define DMAC_PENDCH_PENDCH22_Pos 22 /**< \brief (DMAC_PENDCH) Pending Channel 22 */ +#define DMAC_PENDCH_PENDCH22 (_U_(1) << DMAC_PENDCH_PENDCH22_Pos) +#define DMAC_PENDCH_PENDCH23_Pos 23 /**< \brief (DMAC_PENDCH) Pending Channel 23 */ +#define DMAC_PENDCH_PENDCH23 (_U_(1) << DMAC_PENDCH_PENDCH23_Pos) +#define DMAC_PENDCH_PENDCH24_Pos 24 /**< \brief (DMAC_PENDCH) Pending Channel 24 */ +#define DMAC_PENDCH_PENDCH24 (_U_(1) << DMAC_PENDCH_PENDCH24_Pos) +#define DMAC_PENDCH_PENDCH25_Pos 25 /**< \brief (DMAC_PENDCH) Pending Channel 25 */ +#define DMAC_PENDCH_PENDCH25 (_U_(1) << DMAC_PENDCH_PENDCH25_Pos) +#define DMAC_PENDCH_PENDCH26_Pos 26 /**< \brief (DMAC_PENDCH) Pending Channel 26 */ +#define DMAC_PENDCH_PENDCH26 (_U_(1) << DMAC_PENDCH_PENDCH26_Pos) +#define DMAC_PENDCH_PENDCH27_Pos 27 /**< \brief (DMAC_PENDCH) Pending Channel 27 */ +#define DMAC_PENDCH_PENDCH27 (_U_(1) << DMAC_PENDCH_PENDCH27_Pos) +#define DMAC_PENDCH_PENDCH28_Pos 28 /**< \brief (DMAC_PENDCH) Pending Channel 28 */ +#define DMAC_PENDCH_PENDCH28 (_U_(1) << DMAC_PENDCH_PENDCH28_Pos) +#define DMAC_PENDCH_PENDCH29_Pos 29 /**< \brief (DMAC_PENDCH) Pending Channel 29 */ +#define DMAC_PENDCH_PENDCH29 (_U_(1) << DMAC_PENDCH_PENDCH29_Pos) +#define DMAC_PENDCH_PENDCH30_Pos 30 /**< \brief (DMAC_PENDCH) Pending Channel 30 */ +#define DMAC_PENDCH_PENDCH30 (_U_(1) << DMAC_PENDCH_PENDCH30_Pos) +#define DMAC_PENDCH_PENDCH31_Pos 31 /**< \brief (DMAC_PENDCH) Pending Channel 31 */ +#define DMAC_PENDCH_PENDCH31 (_U_(1) << DMAC_PENDCH_PENDCH31_Pos) +#define DMAC_PENDCH_PENDCH_Pos 0 /**< \brief (DMAC_PENDCH) Pending Channel x */ +#define DMAC_PENDCH_PENDCH_Msk (_U_(0xFFFFFFFF) << DMAC_PENDCH_PENDCH_Pos) +#define DMAC_PENDCH_PENDCH(value) (DMAC_PENDCH_PENDCH_Msk & ((value) << DMAC_PENDCH_PENDCH_Pos)) +#define DMAC_PENDCH_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_PENDCH) MASK Register */ + +/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */ + uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */ + uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */ + uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */ + uint32_t :4; /*!< bit: 4.. 7 Reserved */ + uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */ + uint32_t :2; /*!< bit: 13..14 Reserved */ + uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */ + uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */ + } bit; /*!< Structure used for bit access */ + struct { + uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */ + uint32_t :28; /*!< bit: 4..31 Reserved */ + } vec; /*!< Structure used for vec access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_ACTIVE_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_ACTIVE_OFFSET 0x30 /**< \brief (DMAC_ACTIVE offset) Active Channel and Levels */ +#define DMAC_ACTIVE_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_ACTIVE reset_value) Active Channel and Levels */ + +#define DMAC_ACTIVE_LVLEX0_Pos 0 /**< \brief (DMAC_ACTIVE) Level 0 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX0 (_U_(1) << DMAC_ACTIVE_LVLEX0_Pos) +#define DMAC_ACTIVE_LVLEX1_Pos 1 /**< \brief (DMAC_ACTIVE) Level 1 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX1 (_U_(1) << DMAC_ACTIVE_LVLEX1_Pos) +#define DMAC_ACTIVE_LVLEX2_Pos 2 /**< \brief (DMAC_ACTIVE) Level 2 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX2 (_U_(1) << DMAC_ACTIVE_LVLEX2_Pos) +#define DMAC_ACTIVE_LVLEX3_Pos 3 /**< \brief (DMAC_ACTIVE) Level 3 Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX3 (_U_(1) << DMAC_ACTIVE_LVLEX3_Pos) +#define DMAC_ACTIVE_LVLEX_Pos 0 /**< \brief (DMAC_ACTIVE) Level x Channel Trigger Request Executing */ +#define DMAC_ACTIVE_LVLEX_Msk (_U_(0xF) << DMAC_ACTIVE_LVLEX_Pos) +#define DMAC_ACTIVE_LVLEX(value) (DMAC_ACTIVE_LVLEX_Msk & ((value) << DMAC_ACTIVE_LVLEX_Pos)) +#define DMAC_ACTIVE_ID_Pos 8 /**< \brief (DMAC_ACTIVE) Active Channel ID */ +#define DMAC_ACTIVE_ID_Msk (_U_(0x1F) << DMAC_ACTIVE_ID_Pos) +#define DMAC_ACTIVE_ID(value) (DMAC_ACTIVE_ID_Msk & ((value) << DMAC_ACTIVE_ID_Pos)) +#define DMAC_ACTIVE_ABUSY_Pos 15 /**< \brief (DMAC_ACTIVE) Active Channel Busy */ +#define DMAC_ACTIVE_ABUSY (_U_(0x1) << DMAC_ACTIVE_ABUSY_Pos) +#define DMAC_ACTIVE_BTCNT_Pos 16 /**< \brief (DMAC_ACTIVE) Active Channel Block Transfer Count */ +#define DMAC_ACTIVE_BTCNT_Msk (_U_(0xFFFF) << DMAC_ACTIVE_BTCNT_Pos) +#define DMAC_ACTIVE_BTCNT(value) (DMAC_ACTIVE_BTCNT_Msk & ((value) << DMAC_ACTIVE_BTCNT_Pos)) +#define DMAC_ACTIVE_MASK _U_(0xFFFF9F0F) /**< \brief (DMAC_ACTIVE) MASK Register */ + +/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_BASEADDR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_BASEADDR_OFFSET 0x34 /**< \brief (DMAC_BASEADDR offset) Descriptor Memory Section Base Address */ +#define DMAC_BASEADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_BASEADDR reset_value) Descriptor Memory Section Base Address */ + +#define DMAC_BASEADDR_BASEADDR_Pos 0 /**< \brief (DMAC_BASEADDR) Descriptor Memory Base Address */ +#define DMAC_BASEADDR_BASEADDR_Msk (_U_(0xFFFFFFFF) << DMAC_BASEADDR_BASEADDR_Pos) +#define DMAC_BASEADDR_BASEADDR(value) (DMAC_BASEADDR_BASEADDR_Msk & ((value) << DMAC_BASEADDR_BASEADDR_Pos)) +#define DMAC_BASEADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_BASEADDR) MASK Register */ + +/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_WRBADDR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_WRBADDR_OFFSET 0x38 /**< \brief (DMAC_WRBADDR offset) Write-Back Memory Section Base Address */ +#define DMAC_WRBADDR_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_WRBADDR reset_value) Write-Back Memory Section Base Address */ + +#define DMAC_WRBADDR_WRBADDR_Pos 0 /**< \brief (DMAC_WRBADDR) Write-Back Memory Base Address */ +#define DMAC_WRBADDR_WRBADDR_Msk (_U_(0xFFFFFFFF) << DMAC_WRBADDR_WRBADDR_Pos) +#define DMAC_WRBADDR_WRBADDR(value) (DMAC_WRBADDR_WRBADDR_Msk & ((value) << DMAC_WRBADDR_WRBADDR_Pos)) +#define DMAC_WRBADDR_MASK _U_(0xFFFFFFFF) /**< \brief (DMAC_WRBADDR) MASK Register */ + +/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 32) CHANNEL Channel n Control A -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint32_t SWRST:1; /*!< bit: 0 Channel Software Reset */ + uint32_t ENABLE:1; /*!< bit: 1 Channel Enable */ + uint32_t :4; /*!< bit: 2.. 5 Reserved */ + uint32_t RUNSTDBY:1; /*!< bit: 6 Channel Run in Standby */ + uint32_t :1; /*!< bit: 7 Reserved */ + uint32_t TRIGSRC:7; /*!< bit: 8..14 Trigger Source */ + uint32_t :5; /*!< bit: 15..19 Reserved */ + uint32_t TRIGACT:2; /*!< bit: 20..21 Trigger Action */ + uint32_t :2; /*!< bit: 22..23 Reserved */ + uint32_t BURSTLEN:4; /*!< bit: 24..27 Burst Length */ + uint32_t THRESHOLD:2; /*!< bit: 28..29 FIFO Threshold */ + uint32_t :2; /*!< bit: 30..31 Reserved */ + } bit; /*!< Structure used for bit access */ + uint32_t reg; /*!< Type used for register access */ +} DMAC_CHCTRLA_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHCTRLA_OFFSET 0x40 /**< \brief (DMAC_CHCTRLA offset) Channel n Control A */ +#define DMAC_CHCTRLA_RESETVALUE _U_(0x00000000) /**< \brief (DMAC_CHCTRLA reset_value) Channel n Control A */ + +#define DMAC_CHCTRLA_SWRST_Pos 0 /**< \brief (DMAC_CHCTRLA) Channel Software Reset */ +#define DMAC_CHCTRLA_SWRST (_U_(0x1) << DMAC_CHCTRLA_SWRST_Pos) +#define DMAC_CHCTRLA_ENABLE_Pos 1 /**< \brief (DMAC_CHCTRLA) Channel Enable */ +#define DMAC_CHCTRLA_ENABLE (_U_(0x1) << DMAC_CHCTRLA_ENABLE_Pos) +#define DMAC_CHCTRLA_RUNSTDBY_Pos 6 /**< \brief (DMAC_CHCTRLA) Channel Run in Standby */ +#define DMAC_CHCTRLA_RUNSTDBY (_U_(0x1) << DMAC_CHCTRLA_RUNSTDBY_Pos) +#define DMAC_CHCTRLA_TRIGSRC_Pos 8 /**< \brief (DMAC_CHCTRLA) Trigger Source */ +#define DMAC_CHCTRLA_TRIGSRC_Msk (_U_(0x7F) << DMAC_CHCTRLA_TRIGSRC_Pos) +#define DMAC_CHCTRLA_TRIGSRC(value) (DMAC_CHCTRLA_TRIGSRC_Msk & ((value) << DMAC_CHCTRLA_TRIGSRC_Pos)) +#define DMAC_CHCTRLA_TRIGSRC_DISABLE_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) Only software/event triggers */ +#define DMAC_CHCTRLA_TRIGSRC_DISABLE (DMAC_CHCTRLA_TRIGSRC_DISABLE_Val << DMAC_CHCTRLA_TRIGSRC_Pos) +#define DMAC_CHCTRLA_TRIGACT_Pos 20 /**< \brief (DMAC_CHCTRLA) Trigger Action */ +#define DMAC_CHCTRLA_TRIGACT_Msk (_U_(0x3) << DMAC_CHCTRLA_TRIGACT_Pos) +#define DMAC_CHCTRLA_TRIGACT(value) (DMAC_CHCTRLA_TRIGACT_Msk & ((value) << DMAC_CHCTRLA_TRIGACT_Pos)) +#define DMAC_CHCTRLA_TRIGACT_BLOCK_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) One trigger required for each block transfer */ +#define DMAC_CHCTRLA_TRIGACT_BURST_Val _U_(0x2) /**< \brief (DMAC_CHCTRLA) One trigger required for each burst transfer */ +#define DMAC_CHCTRLA_TRIGACT_TRANSACTION_Val _U_(0x3) /**< \brief (DMAC_CHCTRLA) One trigger required for each transaction */ +#define DMAC_CHCTRLA_TRIGACT_BLOCK (DMAC_CHCTRLA_TRIGACT_BLOCK_Val << DMAC_CHCTRLA_TRIGACT_Pos) +#define DMAC_CHCTRLA_TRIGACT_BURST (DMAC_CHCTRLA_TRIGACT_BURST_Val << DMAC_CHCTRLA_TRIGACT_Pos) +#define DMAC_CHCTRLA_TRIGACT_TRANSACTION (DMAC_CHCTRLA_TRIGACT_TRANSACTION_Val << DMAC_CHCTRLA_TRIGACT_Pos) +#define DMAC_CHCTRLA_BURSTLEN_Pos 24 /**< \brief (DMAC_CHCTRLA) Burst Length */ +#define DMAC_CHCTRLA_BURSTLEN_Msk (_U_(0xF) << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN(value) (DMAC_CHCTRLA_BURSTLEN_Msk & ((value) << DMAC_CHCTRLA_BURSTLEN_Pos)) +#define DMAC_CHCTRLA_BURSTLEN_SINGLE_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) Single-beat burst length */ +#define DMAC_CHCTRLA_BURSTLEN_2BEAT_Val _U_(0x1) /**< \brief (DMAC_CHCTRLA) 2-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_3BEAT_Val _U_(0x2) /**< \brief (DMAC_CHCTRLA) 3-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_4BEAT_Val _U_(0x3) /**< \brief (DMAC_CHCTRLA) 4-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_5BEAT_Val _U_(0x4) /**< \brief (DMAC_CHCTRLA) 5-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_6BEAT_Val _U_(0x5) /**< \brief (DMAC_CHCTRLA) 6-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_7BEAT_Val _U_(0x6) /**< \brief (DMAC_CHCTRLA) 7-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_8BEAT_Val _U_(0x7) /**< \brief (DMAC_CHCTRLA) 8-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_9BEAT_Val _U_(0x8) /**< \brief (DMAC_CHCTRLA) 9-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_10BEAT_Val _U_(0x9) /**< \brief (DMAC_CHCTRLA) 10-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_11BEAT_Val _U_(0xA) /**< \brief (DMAC_CHCTRLA) 11-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_12BEAT_Val _U_(0xB) /**< \brief (DMAC_CHCTRLA) 12-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_13BEAT_Val _U_(0xC) /**< \brief (DMAC_CHCTRLA) 13-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_14BEAT_Val _U_(0xD) /**< \brief (DMAC_CHCTRLA) 14-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_15BEAT_Val _U_(0xE) /**< \brief (DMAC_CHCTRLA) 15-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_16BEAT_Val _U_(0xF) /**< \brief (DMAC_CHCTRLA) 16-beats burst length */ +#define DMAC_CHCTRLA_BURSTLEN_SINGLE (DMAC_CHCTRLA_BURSTLEN_SINGLE_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_2BEAT (DMAC_CHCTRLA_BURSTLEN_2BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_3BEAT (DMAC_CHCTRLA_BURSTLEN_3BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_4BEAT (DMAC_CHCTRLA_BURSTLEN_4BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_5BEAT (DMAC_CHCTRLA_BURSTLEN_5BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_6BEAT (DMAC_CHCTRLA_BURSTLEN_6BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_7BEAT (DMAC_CHCTRLA_BURSTLEN_7BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_8BEAT (DMAC_CHCTRLA_BURSTLEN_8BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_9BEAT (DMAC_CHCTRLA_BURSTLEN_9BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_10BEAT (DMAC_CHCTRLA_BURSTLEN_10BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_11BEAT (DMAC_CHCTRLA_BURSTLEN_11BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_12BEAT (DMAC_CHCTRLA_BURSTLEN_12BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_13BEAT (DMAC_CHCTRLA_BURSTLEN_13BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_14BEAT (DMAC_CHCTRLA_BURSTLEN_14BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_15BEAT (DMAC_CHCTRLA_BURSTLEN_15BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_BURSTLEN_16BEAT (DMAC_CHCTRLA_BURSTLEN_16BEAT_Val << DMAC_CHCTRLA_BURSTLEN_Pos) +#define DMAC_CHCTRLA_THRESHOLD_Pos 28 /**< \brief (DMAC_CHCTRLA) FIFO Threshold */ +#define DMAC_CHCTRLA_THRESHOLD_Msk (_U_(0x3) << DMAC_CHCTRLA_THRESHOLD_Pos) +#define DMAC_CHCTRLA_THRESHOLD(value) (DMAC_CHCTRLA_THRESHOLD_Msk & ((value) << DMAC_CHCTRLA_THRESHOLD_Pos)) +#define DMAC_CHCTRLA_THRESHOLD_1BEAT_Val _U_(0x0) /**< \brief (DMAC_CHCTRLA) Destination write starts after each beat source address read */ +#define DMAC_CHCTRLA_THRESHOLD_2BEATS_Val _U_(0x1) /**< \brief (DMAC_CHCTRLA) Destination write starts after 2-beats source address read */ +#define DMAC_CHCTRLA_THRESHOLD_4BEATS_Val _U_(0x2) /**< \brief (DMAC_CHCTRLA) Destination write starts after 4-beats source address read */ +#define DMAC_CHCTRLA_THRESHOLD_8BEATS_Val _U_(0x3) /**< \brief (DMAC_CHCTRLA) Destination write starts after 8-beats source address read */ +#define DMAC_CHCTRLA_THRESHOLD_1BEAT (DMAC_CHCTRLA_THRESHOLD_1BEAT_Val << DMAC_CHCTRLA_THRESHOLD_Pos) +#define DMAC_CHCTRLA_THRESHOLD_2BEATS (DMAC_CHCTRLA_THRESHOLD_2BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos) +#define DMAC_CHCTRLA_THRESHOLD_4BEATS (DMAC_CHCTRLA_THRESHOLD_4BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos) +#define DMAC_CHCTRLA_THRESHOLD_8BEATS (DMAC_CHCTRLA_THRESHOLD_8BEATS_Val << DMAC_CHCTRLA_THRESHOLD_Pos) +#define DMAC_CHCTRLA_MASK _U_(0x3F307F43) /**< \brief (DMAC_CHCTRLA) MASK Register */ + +/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 8) CHANNEL Channel n Control B -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t CMD:2; /*!< bit: 0.. 1 Software Command */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHCTRLB_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHCTRLB_OFFSET 0x44 /**< \brief (DMAC_CHCTRLB offset) Channel n Control B */ +#define DMAC_CHCTRLB_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHCTRLB reset_value) Channel n Control B */ + +#define DMAC_CHCTRLB_CMD_Pos 0 /**< \brief (DMAC_CHCTRLB) Software Command */ +#define DMAC_CHCTRLB_CMD_Msk (_U_(0x3) << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_CMD(value) (DMAC_CHCTRLB_CMD_Msk & ((value) << DMAC_CHCTRLB_CMD_Pos)) +#define DMAC_CHCTRLB_CMD_NOACT_Val _U_(0x0) /**< \brief (DMAC_CHCTRLB) No action */ +#define DMAC_CHCTRLB_CMD_SUSPEND_Val _U_(0x1) /**< \brief (DMAC_CHCTRLB) Channel suspend operation */ +#define DMAC_CHCTRLB_CMD_RESUME_Val _U_(0x2) /**< \brief (DMAC_CHCTRLB) Channel resume operation */ +#define DMAC_CHCTRLB_CMD_NOACT (DMAC_CHCTRLB_CMD_NOACT_Val << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_CMD_SUSPEND (DMAC_CHCTRLB_CMD_SUSPEND_Val << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_CMD_RESUME (DMAC_CHCTRLB_CMD_RESUME_Val << DMAC_CHCTRLB_CMD_Pos) +#define DMAC_CHCTRLB_MASK _U_(0x03) /**< \brief (DMAC_CHCTRLB) MASK Register */ + +/* -------- DMAC_CHPRILVL : (DMAC Offset: 0x45) (R/W 8) CHANNEL Channel n Priority Level -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PRILVL:2; /*!< bit: 0.. 1 Channel Priority Level */ + uint8_t :6; /*!< bit: 2.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHPRILVL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHPRILVL_OFFSET 0x45 /**< \brief (DMAC_CHPRILVL offset) Channel n Priority Level */ +#define DMAC_CHPRILVL_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHPRILVL reset_value) Channel n Priority Level */ + +#define DMAC_CHPRILVL_PRILVL_Pos 0 /**< \brief (DMAC_CHPRILVL) Channel Priority Level */ +#define DMAC_CHPRILVL_PRILVL_Msk (_U_(0x3) << DMAC_CHPRILVL_PRILVL_Pos) +#define DMAC_CHPRILVL_PRILVL(value) (DMAC_CHPRILVL_PRILVL_Msk & ((value) << DMAC_CHPRILVL_PRILVL_Pos)) +#define DMAC_CHPRILVL_PRILVL_LVL0_Val _U_(0x0) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 0 (Lowest Level) */ +#define DMAC_CHPRILVL_PRILVL_LVL1_Val _U_(0x1) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 1 */ +#define DMAC_CHPRILVL_PRILVL_LVL2_Val _U_(0x2) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 2 */ +#define DMAC_CHPRILVL_PRILVL_LVL3_Val _U_(0x3) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 3 */ +#define DMAC_CHPRILVL_PRILVL_LVL4_Val _U_(0x4) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 4 */ +#define DMAC_CHPRILVL_PRILVL_LVL5_Val _U_(0x5) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 5 */ +#define DMAC_CHPRILVL_PRILVL_LVL6_Val _U_(0x6) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 6 */ +#define DMAC_CHPRILVL_PRILVL_LVL7_Val _U_(0x7) /**< \brief (DMAC_CHPRILVL) Channel Priority Level 7 (Highest Level) */ +#define DMAC_CHPRILVL_PRILVL_LVL0 (DMAC_CHPRILVL_PRILVL_LVL0_Val << DMAC_CHPRILVL_PRILVL_Pos) +#define DMAC_CHPRILVL_PRILVL_LVL1 (DMAC_CHPRILVL_PRILVL_LVL1_Val << DMAC_CHPRILVL_PRILVL_Pos) +#define DMAC_CHPRILVL_PRILVL_LVL2 (DMAC_CHPRILVL_PRILVL_LVL2_Val << DMAC_CHPRILVL_PRILVL_Pos) +#define DMAC_CHPRILVL_PRILVL_LVL3 (DMAC_CHPRILVL_PRILVL_LVL3_Val << DMAC_CHPRILVL_PRILVL_Pos) +#define DMAC_CHPRILVL_PRILVL_LVL4 (DMAC_CHPRILVL_PRILVL_LVL4_Val << DMAC_CHPRILVL_PRILVL_Pos) +#define DMAC_CHPRILVL_PRILVL_LVL5 (DMAC_CHPRILVL_PRILVL_LVL5_Val << DMAC_CHPRILVL_PRILVL_Pos) +#define DMAC_CHPRILVL_PRILVL_LVL6 (DMAC_CHPRILVL_PRILVL_LVL6_Val << DMAC_CHPRILVL_PRILVL_Pos) +#define DMAC_CHPRILVL_PRILVL_LVL7 (DMAC_CHPRILVL_PRILVL_LVL7_Val << DMAC_CHPRILVL_PRILVL_Pos) +#define DMAC_CHPRILVL_MASK _U_(0x03) /**< \brief (DMAC_CHPRILVL) MASK Register */ + +/* -------- DMAC_CHEVCTRL : (DMAC Offset: 0x46) (R/W 8) CHANNEL Channel n Event Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t EVACT:3; /*!< bit: 0.. 2 Channel Event Input Action */ + uint8_t :1; /*!< bit: 3 Reserved */ + uint8_t EVOMODE:2; /*!< bit: 4.. 5 Channel Event Output Mode */ + uint8_t EVIE:1; /*!< bit: 6 Channel Event Input Enable */ + uint8_t EVOE:1; /*!< bit: 7 Channel Event Output Enable */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHEVCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHEVCTRL_OFFSET 0x46 /**< \brief (DMAC_CHEVCTRL offset) Channel n Event Control */ +#define DMAC_CHEVCTRL_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHEVCTRL reset_value) Channel n Event Control */ + +#define DMAC_CHEVCTRL_EVACT_Pos 0 /**< \brief (DMAC_CHEVCTRL) Channel Event Input Action */ +#define DMAC_CHEVCTRL_EVACT_Msk (_U_(0x7) << DMAC_CHEVCTRL_EVACT_Pos) +#define DMAC_CHEVCTRL_EVACT(value) (DMAC_CHEVCTRL_EVACT_Msk & ((value) << DMAC_CHEVCTRL_EVACT_Pos)) +#define DMAC_CHEVCTRL_EVACT_NOACT_Val _U_(0x0) /**< \brief (DMAC_CHEVCTRL) No action */ +#define DMAC_CHEVCTRL_EVACT_TRIG_Val _U_(0x1) /**< \brief (DMAC_CHEVCTRL) Transfer and periodic transfer trigger */ +#define DMAC_CHEVCTRL_EVACT_CTRIG_Val _U_(0x2) /**< \brief (DMAC_CHEVCTRL) Conditional transfer trigger */ +#define DMAC_CHEVCTRL_EVACT_CBLOCK_Val _U_(0x3) /**< \brief (DMAC_CHEVCTRL) Conditional block transfer */ +#define DMAC_CHEVCTRL_EVACT_SUSPEND_Val _U_(0x4) /**< \brief (DMAC_CHEVCTRL) Channel suspend operation */ +#define DMAC_CHEVCTRL_EVACT_RESUME_Val _U_(0x5) /**< \brief (DMAC_CHEVCTRL) Channel resume operation */ +#define DMAC_CHEVCTRL_EVACT_SSKIP_Val _U_(0x6) /**< \brief (DMAC_CHEVCTRL) Skip next block suspend action */ +#define DMAC_CHEVCTRL_EVACT_INCPRI_Val _U_(0x7) /**< \brief (DMAC_CHEVCTRL) Increase priority */ +#define DMAC_CHEVCTRL_EVACT_NOACT (DMAC_CHEVCTRL_EVACT_NOACT_Val << DMAC_CHEVCTRL_EVACT_Pos) +#define DMAC_CHEVCTRL_EVACT_TRIG (DMAC_CHEVCTRL_EVACT_TRIG_Val << DMAC_CHEVCTRL_EVACT_Pos) +#define DMAC_CHEVCTRL_EVACT_CTRIG (DMAC_CHEVCTRL_EVACT_CTRIG_Val << DMAC_CHEVCTRL_EVACT_Pos) +#define DMAC_CHEVCTRL_EVACT_CBLOCK (DMAC_CHEVCTRL_EVACT_CBLOCK_Val << DMAC_CHEVCTRL_EVACT_Pos) +#define DMAC_CHEVCTRL_EVACT_SUSPEND (DMAC_CHEVCTRL_EVACT_SUSPEND_Val << DMAC_CHEVCTRL_EVACT_Pos) +#define DMAC_CHEVCTRL_EVACT_RESUME (DMAC_CHEVCTRL_EVACT_RESUME_Val << DMAC_CHEVCTRL_EVACT_Pos) +#define DMAC_CHEVCTRL_EVACT_SSKIP (DMAC_CHEVCTRL_EVACT_SSKIP_Val << DMAC_CHEVCTRL_EVACT_Pos) +#define DMAC_CHEVCTRL_EVACT_INCPRI (DMAC_CHEVCTRL_EVACT_INCPRI_Val << DMAC_CHEVCTRL_EVACT_Pos) +#define DMAC_CHEVCTRL_EVOMODE_Pos 4 /**< \brief (DMAC_CHEVCTRL) Channel Event Output Mode */ +#define DMAC_CHEVCTRL_EVOMODE_Msk (_U_(0x3) << DMAC_CHEVCTRL_EVOMODE_Pos) +#define DMAC_CHEVCTRL_EVOMODE(value) (DMAC_CHEVCTRL_EVOMODE_Msk & ((value) << DMAC_CHEVCTRL_EVOMODE_Pos)) +#define DMAC_CHEVCTRL_EVOMODE_DEFAULT_Val _U_(0x0) /**< \brief (DMAC_CHEVCTRL) Block event output selection. Refer to BTCTRL.EVOSEL for available selections. */ +#define DMAC_CHEVCTRL_EVOMODE_TRIGACT_Val _U_(0x1) /**< \brief (DMAC_CHEVCTRL) Ongoing trigger action */ +#define DMAC_CHEVCTRL_EVOMODE_DEFAULT (DMAC_CHEVCTRL_EVOMODE_DEFAULT_Val << DMAC_CHEVCTRL_EVOMODE_Pos) +#define DMAC_CHEVCTRL_EVOMODE_TRIGACT (DMAC_CHEVCTRL_EVOMODE_TRIGACT_Val << DMAC_CHEVCTRL_EVOMODE_Pos) +#define DMAC_CHEVCTRL_EVIE_Pos 6 /**< \brief (DMAC_CHEVCTRL) Channel Event Input Enable */ +#define DMAC_CHEVCTRL_EVIE (_U_(0x1) << DMAC_CHEVCTRL_EVIE_Pos) +#define DMAC_CHEVCTRL_EVOE_Pos 7 /**< \brief (DMAC_CHEVCTRL) Channel Event Output Enable */ +#define DMAC_CHEVCTRL_EVOE (_U_(0x1) << DMAC_CHEVCTRL_EVOE_Pos) +#define DMAC_CHEVCTRL_MASK _U_(0xF7) /**< \brief (DMAC_CHEVCTRL) MASK Register */ + +/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) CHANNEL Channel n Interrupt Enable Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ + uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ + uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHINTENCLR_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHINTENCLR_OFFSET 0x4C /**< \brief (DMAC_CHINTENCLR offset) Channel n Interrupt Enable Clear */ +#define DMAC_CHINTENCLR_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTENCLR reset_value) Channel n Interrupt Enable Clear */ + +#define DMAC_CHINTENCLR_TERR_Pos 0 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Error Interrupt Enable */ +#define DMAC_CHINTENCLR_TERR (_U_(0x1) << DMAC_CHINTENCLR_TERR_Pos) +#define DMAC_CHINTENCLR_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENCLR) Channel Transfer Complete Interrupt Enable */ +#define DMAC_CHINTENCLR_TCMPL (_U_(0x1) << DMAC_CHINTENCLR_TCMPL_Pos) +#define DMAC_CHINTENCLR_SUSP_Pos 2 /**< \brief (DMAC_CHINTENCLR) Channel Suspend Interrupt Enable */ +#define DMAC_CHINTENCLR_SUSP (_U_(0x1) << DMAC_CHINTENCLR_SUSP_Pos) +#define DMAC_CHINTENCLR_MASK _U_(0x07) /**< \brief (DMAC_CHINTENCLR) MASK Register */ + +/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) CHANNEL Channel n Interrupt Enable Set -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */ + uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */ + uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */ + uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHINTENSET_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHINTENSET_OFFSET 0x4D /**< \brief (DMAC_CHINTENSET offset) Channel n Interrupt Enable Set */ +#define DMAC_CHINTENSET_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTENSET reset_value) Channel n Interrupt Enable Set */ + +#define DMAC_CHINTENSET_TERR_Pos 0 /**< \brief (DMAC_CHINTENSET) Channel Transfer Error Interrupt Enable */ +#define DMAC_CHINTENSET_TERR (_U_(0x1) << DMAC_CHINTENSET_TERR_Pos) +#define DMAC_CHINTENSET_TCMPL_Pos 1 /**< \brief (DMAC_CHINTENSET) Channel Transfer Complete Interrupt Enable */ +#define DMAC_CHINTENSET_TCMPL (_U_(0x1) << DMAC_CHINTENSET_TCMPL_Pos) +#define DMAC_CHINTENSET_SUSP_Pos 2 /**< \brief (DMAC_CHINTENSET) Channel Suspend Interrupt Enable */ +#define DMAC_CHINTENSET_SUSP (_U_(0x1) << DMAC_CHINTENSET_SUSP_Pos) +#define DMAC_CHINTENSET_MASK _U_(0x07) /**< \brief (DMAC_CHINTENSET) MASK Register */ + +/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) CHANNEL Channel n Interrupt Flag Status and Clear -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { // __I to avoid read-modify-write on write-to-clear register + struct { + __I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */ + __I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */ + __I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */ + __I uint8_t :5; /*!< bit: 3.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHINTFLAG_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHINTFLAG_OFFSET 0x4E /**< \brief (DMAC_CHINTFLAG offset) Channel n Interrupt Flag Status and Clear */ +#define DMAC_CHINTFLAG_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHINTFLAG reset_value) Channel n Interrupt Flag Status and Clear */ + +#define DMAC_CHINTFLAG_TERR_Pos 0 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Error */ +#define DMAC_CHINTFLAG_TERR (_U_(0x1) << DMAC_CHINTFLAG_TERR_Pos) +#define DMAC_CHINTFLAG_TCMPL_Pos 1 /**< \brief (DMAC_CHINTFLAG) Channel Transfer Complete */ +#define DMAC_CHINTFLAG_TCMPL (_U_(0x1) << DMAC_CHINTFLAG_TCMPL_Pos) +#define DMAC_CHINTFLAG_SUSP_Pos 2 /**< \brief (DMAC_CHINTFLAG) Channel Suspend */ +#define DMAC_CHINTFLAG_SUSP (_U_(0x1) << DMAC_CHINTFLAG_SUSP_Pos) +#define DMAC_CHINTFLAG_MASK _U_(0x07) /**< \brief (DMAC_CHINTFLAG) MASK Register */ + +/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/W 8) CHANNEL Channel n Status -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint8_t PEND:1; /*!< bit: 0 Channel Pending */ + uint8_t BUSY:1; /*!< bit: 1 Channel Busy */ + uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */ + uint8_t CRCERR:1; /*!< bit: 3 Channel CRC Error */ + uint8_t :4; /*!< bit: 4.. 7 Reserved */ + } bit; /*!< Structure used for bit access */ + uint8_t reg; /*!< Type used for register access */ +} DMAC_CHSTATUS_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_CHSTATUS_OFFSET 0x4F /**< \brief (DMAC_CHSTATUS offset) Channel n Status */ +#define DMAC_CHSTATUS_RESETVALUE _U_(0x00) /**< \brief (DMAC_CHSTATUS reset_value) Channel n Status */ + +#define DMAC_CHSTATUS_PEND_Pos 0 /**< \brief (DMAC_CHSTATUS) Channel Pending */ +#define DMAC_CHSTATUS_PEND (_U_(0x1) << DMAC_CHSTATUS_PEND_Pos) +#define DMAC_CHSTATUS_BUSY_Pos 1 /**< \brief (DMAC_CHSTATUS) Channel Busy */ +#define DMAC_CHSTATUS_BUSY (_U_(0x1) << DMAC_CHSTATUS_BUSY_Pos) +#define DMAC_CHSTATUS_FERR_Pos 2 /**< \brief (DMAC_CHSTATUS) Channel Fetch Error */ +#define DMAC_CHSTATUS_FERR (_U_(0x1) << DMAC_CHSTATUS_FERR_Pos) +#define DMAC_CHSTATUS_CRCERR_Pos 3 /**< \brief (DMAC_CHSTATUS) Channel CRC Error */ +#define DMAC_CHSTATUS_CRCERR (_U_(0x1) << DMAC_CHSTATUS_CRCERR_Pos) +#define DMAC_CHSTATUS_MASK _U_(0x0F) /**< \brief (DMAC_CHSTATUS) MASK Register */ + +/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */ +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +typedef union { + struct { + uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */ + uint16_t EVOSEL:2; /*!< bit: 1.. 2 Block Event Output Selection */ + uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */ + uint16_t :3; /*!< bit: 5.. 7 Reserved */ + uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */ + uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */ + uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */ + uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */ + uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */ + } bit; /*!< Structure used for bit access */ + uint16_t reg; /*!< Type used for register access */ +} DMAC_BTCTRL_Type; +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + +#define DMAC_BTCTRL_OFFSET 0x00 /**< \brief (DMAC_BTCTRL offset) Block Transfer Control */ +#define DMAC_BTCTRL_RESETVALUE _U_(0x0000) /**< \brief (DMAC_BTCTRL reset_value) Block Transfer Control */ + +#define DMAC_BTCTRL_VALID_Pos 0 /**< \brief (DMAC_BTCTRL) Descriptor Valid */ +#define DMAC_BTCTRL_VALID (_U_(0x1) << DMAC_BTCTRL_VALID_Pos) +#define DMAC_BTCTRL_EVOSEL_Pos 1 /**< \brief (DMAC_BTCTRL) Block Event Output Selection */ +#define DMAC_BTCTRL_EVOSEL_Msk (_U_(0x3) << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_EVOSEL(value) (DMAC_BTCTRL_EVOSEL_Msk & ((value) << DMAC_BTCTRL_EVOSEL_Pos)) +#define DMAC_BTCTRL_EVOSEL_DISABLE_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Event generation disabled */ +#define DMAC_BTCTRL_EVOSEL_BLOCK_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Block event strobe */ +#define DMAC_BTCTRL_EVOSEL_BURST_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Burst event strobe */ +#define DMAC_BTCTRL_EVOSEL_DISABLE (DMAC_BTCTRL_EVOSEL_DISABLE_Val << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_EVOSEL_BLOCK (DMAC_BTCTRL_EVOSEL_BLOCK_Val << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_EVOSEL_BURST (DMAC_BTCTRL_EVOSEL_BURST_Val << DMAC_BTCTRL_EVOSEL_Pos) +#define DMAC_BTCTRL_BLOCKACT_Pos 3 /**< \brief (DMAC_BTCTRL) Block Action */ +#define DMAC_BTCTRL_BLOCKACT_Msk (_U_(0x3) << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT(value) (DMAC_BTCTRL_BLOCKACT_Msk & ((value) << DMAC_BTCTRL_BLOCKACT_Pos)) +#define DMAC_BTCTRL_BLOCKACT_NOACT_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction */ +#define DMAC_BTCTRL_BLOCKACT_INT_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Channel will be disabled if it is the last block transfer in the transaction and block interrupt */ +#define DMAC_BTCTRL_BLOCKACT_SUSPEND_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) Channel suspend operation is completed */ +#define DMAC_BTCTRL_BLOCKACT_BOTH_Val _U_(0x3) /**< \brief (DMAC_BTCTRL) Both channel suspend operation and block interrupt */ +#define DMAC_BTCTRL_BLOCKACT_NOACT (DMAC_BTCTRL_BLOCKACT_NOACT_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT_INT (DMAC_BTCTRL_BLOCKACT_INT_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT_SUSPEND (DMAC_BTCTRL_BLOCKACT_SUSPEND_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BLOCKACT_BOTH (DMAC_BTCTRL_BLOCKACT_BOTH_Val << DMAC_BTCTRL_BLOCKACT_Pos) +#define DMAC_BTCTRL_BEATSIZE_Pos 8 /**< \brief (DMAC_BTCTRL) Beat Size */ +#define DMAC_BTCTRL_BEATSIZE_Msk (_U_(0x3) << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_BEATSIZE(value) (DMAC_BTCTRL_BEATSIZE_Msk & ((value) << DMAC_BTCTRL_BEATSIZE_Pos)) +#define DMAC_BTCTRL_BEATSIZE_BYTE_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) 8-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_HWORD_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) 16-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_WORD_Val _U_(0x2) /**< \brief (DMAC_BTCTRL) 32-bit bus transfer */ +#define DMAC_BTCTRL_BEATSIZE_BYTE (DMAC_BTCTRL_BEATSIZE_BYTE_Val << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_BEATSIZE_HWORD (DMAC_BTCTRL_BEATSIZE_HWORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_BEATSIZE_WORD (DMAC_BTCTRL_BEATSIZE_WORD_Val << DMAC_BTCTRL_BEATSIZE_Pos) +#define DMAC_BTCTRL_SRCINC_Pos 10 /**< \brief (DMAC_BTCTRL) Source Address Increment Enable */ +#define DMAC_BTCTRL_SRCINC (_U_(0x1) << DMAC_BTCTRL_SRCINC_Pos) +#define DMAC_BTCTRL_DSTINC_Pos 11 /**< \brief (DMAC_BTCTRL) Destination Address Increment Enable */ +#define DMAC_BTCTRL_DSTINC (_U_(0x1) << DMAC_BTCTRL_DSTINC_Pos) +#define DMAC_BTCTRL_STEPSEL_Pos 12 /**< \brief (DMAC_BTCTRL) Step Selection */ +#define DMAC_BTCTRL_STEPSEL (_U_(0x1) << DMAC_BTCTRL_STEPSEL_Pos) +#define DMAC_BTCTRL_STEPSEL_DST_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Step size settings apply to the destination address */ +#define DMAC_BTCTRL_STEPSEL_SRC_Val _U_(0x1) /**< \brief (DMAC_BTCTRL) Step size settings apply to the source address */ +#define DMAC_BTCTRL_STEPSEL_DST (DMAC_BTCTRL_STEPSEL_DST_Val << DMAC_BTCTRL_STEPSEL_Pos) +#define DMAC_BTCTRL_STEPSEL_SRC (DMAC_BTCTRL_STEPSEL_SRC_Val << DMAC_BTCTRL_STEPSEL_Pos) +#define DMAC_BTCTRL_STEPSIZE_Pos 13 /**< \brief (DMAC_BTCTRL) Address Increment Step Size */ +#define DMAC_BTCTRL_STEPSIZE_Msk (_U_(0x7) << DMAC_BTCTRL_STEPSIZE_Pos) +#define DMAC_BTCTRL_STEPSIZE(value) (DMAC_BTCTRL_STEPSIZE_Msk & ((value) << DMAC_BTCTRL_STEPSIZE_Pos)) +#define DMAC_BTCTRL_STEPSIZE_X1_Val _U_(0x0) /**< \brief (DMAC_BTCTRL) Next ADDR = ADDR + (1< 8 bits, 1 -> 16 bits +#define USB_EPNUM 8 // parameter for rtl : max of ENDPOINT and PIPE NUM +#define USB_EPT_NUM 8 // Number of USB end points +#define USB_GCLK_ID 10 // Index of Generic Clock +#define USB_INITIAL_CONTROL_QOS 3 // CONTROL QOS RESET value +#define USB_INITIAL_DATA_QOS 3 // DATA QOS RESET value +#define USB_MISSING_SOF_DET_IMPLEMENTED 1 // 48 mHz xPLL feature implemented +#define USB_PIPE_NUM 8 // Number of USB pipes +#define USB_SYSTEM_CLOCK_IS_CKUSB 0 // Dual (1'b0) or Single (1'b1) clock system +#define USB_USB_2_AHB_FIFO_DEPTH 4 // bytes number, should be at least 2, and 2^n (4,8,16 ...) +#define USB_USB_2_AHB_RD_DATA_BITS 16 // 8, 16 or 32, here : 8-bits is required as UTMI interface should work in 8-bits mode +#define USB_USB_2_AHB_RD_THRESHOLD 2 // as soon as there are 16 bytes-free inside the fifo, ahb read transfer is requested +#define USB_USB_2_AHB_WR_DATA_BITS 8 // 8, 16 or 32 : here : 8-bits is required as UTMI interface should work in 8-bits mode + +#endif /* _SAME54_USB_INSTANCE_ */ diff --git a/software/firmware/oracle_same54n19a/include/instance/wdt.h b/software/firmware/oracle_same54n19a/include/instance/wdt.h new file mode 100644 index 00000000..c96d7705 --- /dev/null +++ b/software/firmware/oracle_same54n19a/include/instance/wdt.h @@ -0,0 +1,55 @@ +/** + * \file + * + * \brief Instance description for WDT + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54_WDT_INSTANCE_ +#define _SAME54_WDT_INSTANCE_ + +/* ========== Register definition for WDT peripheral ========== */ +#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#define REG_WDT_CTRLA (0x40002000) /**< \brief (WDT) Control */ +#define REG_WDT_CONFIG (0x40002001) /**< \brief (WDT) Configuration */ +#define REG_WDT_EWCTRL (0x40002002) /**< \brief (WDT) Early Warning Interrupt Control */ +#define REG_WDT_INTENCLR (0x40002004) /**< \brief (WDT) Interrupt Enable Clear */ +#define REG_WDT_INTENSET (0x40002005) /**< \brief (WDT) Interrupt Enable Set */ +#define REG_WDT_INTFLAG (0x40002006) /**< \brief (WDT) Interrupt Flag Status and Clear */ +#define REG_WDT_SYNCBUSY (0x40002008) /**< \brief (WDT) Synchronization Busy */ +#define REG_WDT_CLEAR (0x4000200C) /**< \brief (WDT) Clear */ +#else +#define REG_WDT_CTRLA (*(RwReg8 *)0x40002000UL) /**< \brief (WDT) Control */ +#define REG_WDT_CONFIG (*(RwReg8 *)0x40002001UL) /**< \brief (WDT) Configuration */ +#define REG_WDT_EWCTRL (*(RwReg8 *)0x40002002UL) /**< \brief (WDT) Early Warning Interrupt Control */ +#define REG_WDT_INTENCLR (*(RwReg8 *)0x40002004UL) /**< \brief (WDT) Interrupt Enable Clear */ +#define REG_WDT_INTENSET (*(RwReg8 *)0x40002005UL) /**< \brief (WDT) Interrupt Enable Set */ +#define REG_WDT_INTFLAG (*(RwReg8 *)0x40002006UL) /**< \brief (WDT) Interrupt Flag Status and Clear */ +#define REG_WDT_SYNCBUSY (*(RoReg *)0x40002008UL) /**< \brief (WDT) Synchronization Busy */ +#define REG_WDT_CLEAR (*(WoReg8 *)0x4000200CUL) /**< \brief (WDT) Clear */ +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ + + +#endif /* _SAME54_WDT_INSTANCE_ */ diff --git a/software/firmware/oracle_same54n19a/include/oracle.h b/software/firmware/oracle_same54n19a/include/oracle.h new file mode 100644 index 00000000..56381a49 --- /dev/null +++ b/software/firmware/oracle_same54n19a/include/oracle.h @@ -0,0 +1,53 @@ +/* + * oracle.h + * + * Created: 5/3/2020 7:05:17 PM + * Author: Penguin + */ +#ifndef _ORACLE_H_ +#define _ORACLE_H_ +#include "pc_board.h" +#include "pc_master.h" +#include +#include +#include +#include +#include +#include + +#include + +#include + +#include +#include +#include + +#include +#include + +#include +#include +#include +#include + + +typedef enum p_err +{ + PE_GOOD = 0x0, // + PE_BAD = 0x1 // +}p_err; + +typedef enum p_log_level +{ + PE_LOG_NONE = 0 +}p_log_level; +void oracle_init(void); + +int p_qprint(const char* str, ...); + +int p_lprint(const char* str, ...); + +void oracle_service(void); + +#endif diff --git a/software/firmware/oracle_same54n19a/include/pio/same54n19a.h b/software/firmware/oracle_same54n19a/include/pio/same54n19a.h new file mode 100644 index 00000000..8d51a313 --- /dev/null +++ b/software/firmware/oracle_same54n19a/include/pio/same54n19a.h @@ -0,0 +1,2688 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAME54N19A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54N19A_PIO_ +#define _SAME54N19A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ +#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ +#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ +#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ +#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ +#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ +#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ +#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ +#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ +#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ +#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ +#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ +#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ +#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ +#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ +#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ +#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ +#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ +#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ +#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ +#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ +#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ +#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ +#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ +#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ +#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ +#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ +#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ +#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ +#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ +#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ +#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ +#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ +#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ +#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ +#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ +#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ +#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ +#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ +#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ +#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ +#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ +#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ +#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ +#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ +#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ +#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ +#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ +#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ +#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ +#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ +#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ +#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ +#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ +#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ +#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ +#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ +#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ +#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ +/* ========== PORT definition for CM4 peripheral ========== */ +#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ +#define MUX_PA30H_CM4_SWCLK _L_(7) +#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) +#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) +#define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */ +#define MUX_PC27M_CM4_SWO _L_(12) +#define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO) +#define PORT_PC27M_CM4_SWO (_UL_(1) << 27) +#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ +#define MUX_PB30H_CM4_SWO _L_(7) +#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) +#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) +#define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */ +#define MUX_PC27H_CM4_TRACECLK _L_(7) +#define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK) +#define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27) +#define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */ +#define MUX_PC28H_CM4_TRACEDATA0 _L_(7) +#define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0) +#define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28) +#define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */ +#define MUX_PC26H_CM4_TRACEDATA1 _L_(7) +#define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1) +#define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26) +#define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */ +#define MUX_PC25H_CM4_TRACEDATA2 _L_(7) +#define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2) +#define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25) +#define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */ +#define MUX_PC24H_CM4_TRACEDATA3 _L_(7) +#define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3) +#define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24) +/* ========== PORT definition for ANAREF peripheral ========== */ +#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ +#define MUX_PA03B_ANAREF_VREF0 _L_(1) +#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) +#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) +#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ +#define MUX_PA04B_ANAREF_VREF1 _L_(1) +#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) +#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) +#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ +#define MUX_PA06B_ANAREF_VREF2 _L_(1) +#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) +#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ +#define MUX_PA30M_GCLK_IO0 _L_(12) +#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) +#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ +#define MUX_PB14M_GCLK_IO0 _L_(12) +#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) +#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ +#define MUX_PA14M_GCLK_IO0 _L_(12) +#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) +#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ +#define MUX_PB22M_GCLK_IO0 _L_(12) +#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) +#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ +#define MUX_PB15M_GCLK_IO1 _L_(12) +#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) +#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ +#define MUX_PA15M_GCLK_IO1 _L_(12) +#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) +#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ +#define MUX_PB23M_GCLK_IO1 _L_(12) +#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) +#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ +#define MUX_PA27M_GCLK_IO1 _L_(12) +#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) +#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) +#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ +#define MUX_PA16M_GCLK_IO2 _L_(12) +#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) +#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ +#define MUX_PB16M_GCLK_IO2 _L_(12) +#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) +#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ +#define MUX_PA17M_GCLK_IO3 _L_(12) +#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) +#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ +#define MUX_PB17M_GCLK_IO3 _L_(12) +#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) +#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ +#define MUX_PA10M_GCLK_IO4 _L_(12) +#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) +#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ +#define MUX_PB10M_GCLK_IO4 _L_(12) +#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) +#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */ +#define MUX_PB18M_GCLK_IO4 _L_(12) +#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) +#define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18) +#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ +#define MUX_PA11M_GCLK_IO5 _L_(12) +#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) +#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ +#define MUX_PB11M_GCLK_IO5 _L_(12) +#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) +#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */ +#define MUX_PB19M_GCLK_IO5 _L_(12) +#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) +#define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19) +#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ +#define MUX_PB12M_GCLK_IO6 _L_(12) +#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) +#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) +#define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */ +#define MUX_PB20M_GCLK_IO6 _L_(12) +#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) +#define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20) +#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ +#define MUX_PB13M_GCLK_IO7 _L_(12) +#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) +#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) +#define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */ +#define MUX_PB21M_GCLK_IO7 _L_(12) +#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) +#define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ +#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ +#define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */ +#define MUX_PC00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) +#define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ +#define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */ +#define MUX_PC16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) +#define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ +#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ +#define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */ +#define MUX_PC01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) +#define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ +#define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */ +#define MUX_PC17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) +#define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ +#define MUX_PB18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) +#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ +#define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */ +#define MUX_PC02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) +#define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ +#define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */ +#define MUX_PC18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) +#define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ +#define MUX_PB19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) +#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ +#define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */ +#define MUX_PC03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) +#define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ +#define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */ +#define MUX_PC19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) +#define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ +#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ +#define MUX_PB20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) +#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ +#define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */ +#define MUX_PC20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) +#define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ +#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ +#define MUX_PB21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) +#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ +#define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */ +#define MUX_PC05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) +#define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ +#define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */ +#define MUX_PC21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) +#define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */ +#define MUX_PC06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) +#define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) +#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ +#define MUX_PB24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) +#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ +#define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */ +#define MUX_PC24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) +#define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) +#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ +#define MUX_PB25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) +#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ +#define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */ +#define MUX_PC07A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) +#define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7) +#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ +#define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */ +#define MUX_PC25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) +#define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ +#define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */ +#define MUX_PC10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) +#define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ +#define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */ +#define MUX_PC26A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) +#define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26) +#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) +#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */ +#define MUX_PC11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) +#define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ +#define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */ +#define MUX_PC27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) +#define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ +#define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */ +#define MUX_PC12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) +#define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ +#define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */ +#define MUX_PC28A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) +#define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28) +#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ +#define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */ +#define MUX_PC13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) +#define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) +#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ +#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ +#define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */ +#define MUX_PC14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) +#define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) +#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ +#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ +#define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */ +#define MUX_PC15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) +#define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */ +#define MUX_PC17D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) +#define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ +#define MUX_PB24C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) +#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */ +#define MUX_PC16D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) +#define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ +#define MUX_PB25C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) +#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */ +#define MUX_PC18D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) +#define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ +#define MUX_PC24C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) +#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */ +#define MUX_PC19D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) +#define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ +#define MUX_PC25C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) +#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */ +#define MUX_PC27C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) +#define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */ +#define MUX_PC28C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) +#define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) +#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) +#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TC0_WO0 _L_(4) +#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) +#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TC0_WO0 _L_(4) +#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) +#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TC0_WO0 _L_(4) +#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) +#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) +#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TC0_WO1 _L_(4) +#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) +#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TC0_WO1 _L_(4) +#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) +#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) +#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TC0_WO1 _L_(4) +#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) +#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TC1_WO0 _L_(4) +#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) +#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) +#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TC1_WO0 _L_(4) +#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) +#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) +#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TC1_WO1 _L_(4) +#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) +#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) +#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TC1_WO1 _L_(4) +#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) +#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ +#define MUX_PA24H_USB_DM _L_(7) +#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) +#define PORT_PA24H_USB_DM (_UL_(1) << 24) +#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ +#define MUX_PA25H_USB_DP _L_(7) +#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) +#define PORT_PA25H_USB_DP (_UL_(1) << 25) +#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ +#define MUX_PA23H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) +#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ +#define MUX_PB22H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) +#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) +#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) +#define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */ +#define MUX_PB25D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) +#define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25) +#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) +#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) +#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) +#define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */ +#define MUX_PB24D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) +#define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24) +#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) +#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) +#define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */ +#define MUX_PC24D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) +#define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24) +#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) +#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) +#define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */ +#define MUX_PC25D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) +#define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25) +#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) +#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) +#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) +#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ +#define MUX_PB20C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) +#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) +#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) +#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) +#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) +#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ +#define MUX_PB21C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) +#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) +#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ +#define MUX_PA20G_TCC0_WO0 _L_(6) +#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) +#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) +#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ +#define MUX_PB12G_TCC0_WO0 _L_(6) +#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) +#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) +#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ +#define MUX_PA08F_TCC0_WO0 _L_(5) +#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) +#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */ +#define MUX_PC10F_TCC0_WO0 _L_(5) +#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) +#define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10) +#define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */ +#define MUX_PC16F_TCC0_WO0 _L_(5) +#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) +#define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16) +#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ +#define MUX_PA21G_TCC0_WO1 _L_(6) +#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) +#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) +#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ +#define MUX_PB13G_TCC0_WO1 _L_(6) +#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) +#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) +#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ +#define MUX_PA09F_TCC0_WO1 _L_(5) +#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) +#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */ +#define MUX_PC11F_TCC0_WO1 _L_(5) +#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) +#define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11) +#define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */ +#define MUX_PC17F_TCC0_WO1 _L_(5) +#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) +#define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17) +#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ +#define MUX_PA22G_TCC0_WO2 _L_(6) +#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) +#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ +#define MUX_PB14G_TCC0_WO2 _L_(6) +#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) +#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */ +#define MUX_PC12F_TCC0_WO2 _L_(5) +#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) +#define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12) +#define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */ +#define MUX_PC18F_TCC0_WO2 _L_(5) +#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) +#define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18) +#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ +#define MUX_PA23G_TCC0_WO3 _L_(6) +#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) +#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ +#define MUX_PB15G_TCC0_WO3 _L_(6) +#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) +#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */ +#define MUX_PC13F_TCC0_WO3 _L_(5) +#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) +#define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13) +#define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */ +#define MUX_PC19F_TCC0_WO3 _L_(5) +#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) +#define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19) +#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ +#define MUX_PA16G_TCC0_WO4 _L_(6) +#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) +#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ +#define MUX_PB16G_TCC0_WO4 _L_(6) +#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) +#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 _L_(5) +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) +#define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */ +#define MUX_PC14F_TCC0_WO4 _L_(5) +#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) +#define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14) +#define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */ +#define MUX_PC20F_TCC0_WO4 _L_(5) +#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) +#define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20) +#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ +#define MUX_PA17G_TCC0_WO5 _L_(6) +#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) +#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ +#define MUX_PB17G_TCC0_WO5 _L_(6) +#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) +#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */ +#define MUX_PC15F_TCC0_WO5 _L_(5) +#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) +#define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15) +#define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */ +#define MUX_PC21F_TCC0_WO5 _L_(5) +#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) +#define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21) +#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ +#define MUX_PA18G_TCC0_WO6 _L_(6) +#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) +#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) +#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ +#define MUX_PB30G_TCC0_WO6 _L_(6) +#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) +#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ +#define MUX_PA19G_TCC0_WO7 _L_(6) +#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) +#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) +#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ +#define MUX_PB31G_TCC0_WO7 _L_(6) +#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) +#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ +#define MUX_PB10G_TCC1_WO0 _L_(6) +#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) +#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) +#define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */ +#define MUX_PC14G_TCC1_WO0 _L_(6) +#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) +#define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14) +#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC1_WO0 _L_(5) +#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) +#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) +#define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */ +#define MUX_PB18F_TCC1_WO0 _L_(5) +#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) +#define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18) +#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ +#define MUX_PB11G_TCC1_WO1 _L_(6) +#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) +#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) +#define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */ +#define MUX_PC15G_TCC1_WO1 _L_(6) +#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) +#define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15) +#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC1_WO1 _L_(5) +#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) +#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) +#define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */ +#define MUX_PB19F_TCC1_WO1 _L_(5) +#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) +#define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19) +#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ +#define MUX_PA12G_TCC1_WO2 _L_(6) +#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) +#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) +#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ +#define MUX_PA14G_TCC1_WO2 _L_(6) +#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) +#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) +#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC1_WO2 _L_(5) +#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) +#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) +#define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */ +#define MUX_PB20F_TCC1_WO2 _L_(5) +#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) +#define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20) +#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ +#define MUX_PA13G_TCC1_WO3 _L_(6) +#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) +#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) +#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ +#define MUX_PA15G_TCC1_WO3 _L_(6) +#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) +#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) +#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC1_WO3 _L_(5) +#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) +#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) +#define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */ +#define MUX_PB21F_TCC1_WO3 _L_(5) +#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) +#define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21) +#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ +#define MUX_PA08G_TCC1_WO4 _L_(6) +#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) +#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) +#define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */ +#define MUX_PC10G_TCC1_WO4 _L_(6) +#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) +#define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10) +#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ +#define MUX_PA20F_TCC1_WO4 _L_(5) +#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) +#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) +#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ +#define MUX_PA09G_TCC1_WO5 _L_(6) +#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) +#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) +#define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */ +#define MUX_PC11G_TCC1_WO5 _L_(6) +#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) +#define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11) +#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ +#define MUX_PA21F_TCC1_WO5 _L_(5) +#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) +#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) +#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ +#define MUX_PA10G_TCC1_WO6 _L_(6) +#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) +#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) +#define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */ +#define MUX_PC12G_TCC1_WO6 _L_(6) +#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) +#define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12) +#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ +#define MUX_PA22F_TCC1_WO6 _L_(5) +#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) +#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) +#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ +#define MUX_PA11G_TCC1_WO7 _L_(6) +#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) +#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) +#define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */ +#define MUX_PC13G_TCC1_WO7 _L_(6) +#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) +#define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13) +#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ +#define MUX_PA23F_TCC1_WO7 _L_(5) +#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) +#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TC2_WO0 _L_(4) +#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) +#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) +#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TC2_WO0 _L_(4) +#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) +#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) +#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TC2_WO0 _L_(4) +#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) +#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) +#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TC2_WO1 _L_(4) +#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) +#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) +#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TC2_WO1 _L_(4) +#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) +#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) +#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TC2_WO1 _L_(4) +#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) +#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC3_WO0 _L_(4) +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) +#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC3_WO0 _L_(4) +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) +#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC3_WO1 _L_(4) +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) +#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC3_WO1 _L_(4) +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) +/* ========== PORT definition for CAN0 peripheral ========== */ +#define PIN_PA23I_CAN0_RX _L_(23) /**< \brief CAN0 signal: RX on PA23 mux I */ +#define MUX_PA23I_CAN0_RX _L_(8) +#define PINMUX_PA23I_CAN0_RX ((PIN_PA23I_CAN0_RX << 16) | MUX_PA23I_CAN0_RX) +#define PORT_PA23I_CAN0_RX (_UL_(1) << 23) +#define PIN_PA25I_CAN0_RX _L_(25) /**< \brief CAN0 signal: RX on PA25 mux I */ +#define MUX_PA25I_CAN0_RX _L_(8) +#define PINMUX_PA25I_CAN0_RX ((PIN_PA25I_CAN0_RX << 16) | MUX_PA25I_CAN0_RX) +#define PORT_PA25I_CAN0_RX (_UL_(1) << 25) +#define PIN_PA22I_CAN0_TX _L_(22) /**< \brief CAN0 signal: TX on PA22 mux I */ +#define MUX_PA22I_CAN0_TX _L_(8) +#define PINMUX_PA22I_CAN0_TX ((PIN_PA22I_CAN0_TX << 16) | MUX_PA22I_CAN0_TX) +#define PORT_PA22I_CAN0_TX (_UL_(1) << 22) +#define PIN_PA24I_CAN0_TX _L_(24) /**< \brief CAN0 signal: TX on PA24 mux I */ +#define MUX_PA24I_CAN0_TX _L_(8) +#define PINMUX_PA24I_CAN0_TX ((PIN_PA24I_CAN0_TX << 16) | MUX_PA24I_CAN0_TX) +#define PORT_PA24I_CAN0_TX (_UL_(1) << 24) +/* ========== PORT definition for CAN1 peripheral ========== */ +#define PIN_PB13H_CAN1_RX _L_(45) /**< \brief CAN1 signal: RX on PB13 mux H */ +#define MUX_PB13H_CAN1_RX _L_(7) +#define PINMUX_PB13H_CAN1_RX ((PIN_PB13H_CAN1_RX << 16) | MUX_PB13H_CAN1_RX) +#define PORT_PB13H_CAN1_RX (_UL_(1) << 13) +#define PIN_PB15H_CAN1_RX _L_(47) /**< \brief CAN1 signal: RX on PB15 mux H */ +#define MUX_PB15H_CAN1_RX _L_(7) +#define PINMUX_PB15H_CAN1_RX ((PIN_PB15H_CAN1_RX << 16) | MUX_PB15H_CAN1_RX) +#define PORT_PB15H_CAN1_RX (_UL_(1) << 15) +#define PIN_PB12H_CAN1_TX _L_(44) /**< \brief CAN1 signal: TX on PB12 mux H */ +#define MUX_PB12H_CAN1_TX _L_(7) +#define PINMUX_PB12H_CAN1_TX ((PIN_PB12H_CAN1_TX << 16) | MUX_PB12H_CAN1_TX) +#define PORT_PB12H_CAN1_TX (_UL_(1) << 12) +#define PIN_PB14H_CAN1_TX _L_(46) /**< \brief CAN1 signal: TX on PB14 mux H */ +#define MUX_PB14H_CAN1_TX _L_(7) +#define PINMUX_PB14H_CAN1_TX ((PIN_PB14H_CAN1_TX << 16) | MUX_PB14H_CAN1_TX) +#define PORT_PB14H_CAN1_TX (_UL_(1) << 14) +/* ========== PORT definition for GMAC peripheral ========== */ +#define PIN_PC21L_GMAC_GCOL _L_(85) /**< \brief GMAC signal: GCOL on PC21 mux L */ +#define MUX_PC21L_GMAC_GCOL _L_(11) +#define PINMUX_PC21L_GMAC_GCOL ((PIN_PC21L_GMAC_GCOL << 16) | MUX_PC21L_GMAC_GCOL) +#define PORT_PC21L_GMAC_GCOL (_UL_(1) << 21) +#define PIN_PA16L_GMAC_GCRS _L_(16) /**< \brief GMAC signal: GCRS on PA16 mux L */ +#define MUX_PA16L_GMAC_GCRS _L_(11) +#define PINMUX_PA16L_GMAC_GCRS ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS) +#define PORT_PA16L_GMAC_GCRS (_UL_(1) << 16) +#define PIN_PA20L_GMAC_GMDC _L_(20) /**< \brief GMAC signal: GMDC on PA20 mux L */ +#define MUX_PA20L_GMAC_GMDC _L_(11) +#define PINMUX_PA20L_GMAC_GMDC ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC) +#define PORT_PA20L_GMAC_GMDC (_UL_(1) << 20) +#define PIN_PB14L_GMAC_GMDC _L_(46) /**< \brief GMAC signal: GMDC on PB14 mux L */ +#define MUX_PB14L_GMAC_GMDC _L_(11) +#define PINMUX_PB14L_GMAC_GMDC ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC) +#define PORT_PB14L_GMAC_GMDC (_UL_(1) << 14) +#define PIN_PC11L_GMAC_GMDC _L_(75) /**< \brief GMAC signal: GMDC on PC11 mux L */ +#define MUX_PC11L_GMAC_GMDC _L_(11) +#define PINMUX_PC11L_GMAC_GMDC ((PIN_PC11L_GMAC_GMDC << 16) | MUX_PC11L_GMAC_GMDC) +#define PORT_PC11L_GMAC_GMDC (_UL_(1) << 11) +#define PIN_PA21L_GMAC_GMDIO _L_(21) /**< \brief GMAC signal: GMDIO on PA21 mux L */ +#define MUX_PA21L_GMAC_GMDIO _L_(11) +#define PINMUX_PA21L_GMAC_GMDIO ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO) +#define PORT_PA21L_GMAC_GMDIO (_UL_(1) << 21) +#define PIN_PB15L_GMAC_GMDIO _L_(47) /**< \brief GMAC signal: GMDIO on PB15 mux L */ +#define MUX_PB15L_GMAC_GMDIO _L_(11) +#define PINMUX_PB15L_GMAC_GMDIO ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO) +#define PORT_PB15L_GMAC_GMDIO (_UL_(1) << 15) +#define PIN_PC12L_GMAC_GMDIO _L_(76) /**< \brief GMAC signal: GMDIO on PC12 mux L */ +#define MUX_PC12L_GMAC_GMDIO _L_(11) +#define PINMUX_PC12L_GMAC_GMDIO ((PIN_PC12L_GMAC_GMDIO << 16) | MUX_PC12L_GMAC_GMDIO) +#define PORT_PC12L_GMAC_GMDIO (_UL_(1) << 12) +#define PIN_PA13L_GMAC_GRX0 _L_(13) /**< \brief GMAC signal: GRX0 on PA13 mux L */ +#define MUX_PA13L_GMAC_GRX0 _L_(11) +#define PINMUX_PA13L_GMAC_GRX0 ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0) +#define PORT_PA13L_GMAC_GRX0 (_UL_(1) << 13) +#define PIN_PA12L_GMAC_GRX1 _L_(12) /**< \brief GMAC signal: GRX1 on PA12 mux L */ +#define MUX_PA12L_GMAC_GRX1 _L_(11) +#define PINMUX_PA12L_GMAC_GRX1 ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1) +#define PORT_PA12L_GMAC_GRX1 (_UL_(1) << 12) +#define PIN_PC15L_GMAC_GRX2 _L_(79) /**< \brief GMAC signal: GRX2 on PC15 mux L */ +#define MUX_PC15L_GMAC_GRX2 _L_(11) +#define PINMUX_PC15L_GMAC_GRX2 ((PIN_PC15L_GMAC_GRX2 << 16) | MUX_PC15L_GMAC_GRX2) +#define PORT_PC15L_GMAC_GRX2 (_UL_(1) << 15) +#define PIN_PC14L_GMAC_GRX3 _L_(78) /**< \brief GMAC signal: GRX3 on PC14 mux L */ +#define MUX_PC14L_GMAC_GRX3 _L_(11) +#define PINMUX_PC14L_GMAC_GRX3 ((PIN_PC14L_GMAC_GRX3 << 16) | MUX_PC14L_GMAC_GRX3) +#define PORT_PC14L_GMAC_GRX3 (_UL_(1) << 14) +#define PIN_PC18L_GMAC_GRXCK _L_(82) /**< \brief GMAC signal: GRXCK on PC18 mux L */ +#define MUX_PC18L_GMAC_GRXCK _L_(11) +#define PINMUX_PC18L_GMAC_GRXCK ((PIN_PC18L_GMAC_GRXCK << 16) | MUX_PC18L_GMAC_GRXCK) +#define PORT_PC18L_GMAC_GRXCK (_UL_(1) << 18) +#define PIN_PC20L_GMAC_GRXDV _L_(84) /**< \brief GMAC signal: GRXDV on PC20 mux L */ +#define MUX_PC20L_GMAC_GRXDV _L_(11) +#define PINMUX_PC20L_GMAC_GRXDV ((PIN_PC20L_GMAC_GRXDV << 16) | MUX_PC20L_GMAC_GRXDV) +#define PORT_PC20L_GMAC_GRXDV (_UL_(1) << 20) +#define PIN_PA15L_GMAC_GRXER _L_(15) /**< \brief GMAC signal: GRXER on PA15 mux L */ +#define MUX_PA15L_GMAC_GRXER _L_(11) +#define PINMUX_PA15L_GMAC_GRXER ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER) +#define PORT_PA15L_GMAC_GRXER (_UL_(1) << 15) +#define PIN_PA18L_GMAC_GTX0 _L_(18) /**< \brief GMAC signal: GTX0 on PA18 mux L */ +#define MUX_PA18L_GMAC_GTX0 _L_(11) +#define PINMUX_PA18L_GMAC_GTX0 ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0) +#define PORT_PA18L_GMAC_GTX0 (_UL_(1) << 18) +#define PIN_PA19L_GMAC_GTX1 _L_(19) /**< \brief GMAC signal: GTX1 on PA19 mux L */ +#define MUX_PA19L_GMAC_GTX1 _L_(11) +#define PINMUX_PA19L_GMAC_GTX1 ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1) +#define PORT_PA19L_GMAC_GTX1 (_UL_(1) << 19) +#define PIN_PC16L_GMAC_GTX2 _L_(80) /**< \brief GMAC signal: GTX2 on PC16 mux L */ +#define MUX_PC16L_GMAC_GTX2 _L_(11) +#define PINMUX_PC16L_GMAC_GTX2 ((PIN_PC16L_GMAC_GTX2 << 16) | MUX_PC16L_GMAC_GTX2) +#define PORT_PC16L_GMAC_GTX2 (_UL_(1) << 16) +#define PIN_PC17L_GMAC_GTX3 _L_(81) /**< \brief GMAC signal: GTX3 on PC17 mux L */ +#define MUX_PC17L_GMAC_GTX3 _L_(11) +#define PINMUX_PC17L_GMAC_GTX3 ((PIN_PC17L_GMAC_GTX3 << 16) | MUX_PC17L_GMAC_GTX3) +#define PORT_PC17L_GMAC_GTX3 (_UL_(1) << 17) +#define PIN_PA14L_GMAC_GTXCK _L_(14) /**< \brief GMAC signal: GTXCK on PA14 mux L */ +#define MUX_PA14L_GMAC_GTXCK _L_(11) +#define PINMUX_PA14L_GMAC_GTXCK ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK) +#define PORT_PA14L_GMAC_GTXCK (_UL_(1) << 14) +#define PIN_PA17L_GMAC_GTXEN _L_(17) /**< \brief GMAC signal: GTXEN on PA17 mux L */ +#define MUX_PA17L_GMAC_GTXEN _L_(11) +#define PINMUX_PA17L_GMAC_GTXEN ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN) +#define PORT_PA17L_GMAC_GTXEN (_UL_(1) << 17) +#define PIN_PC19L_GMAC_GTXER _L_(83) /**< \brief GMAC signal: GTXER on PC19 mux L */ +#define MUX_PC19L_GMAC_GTXER _L_(11) +#define PINMUX_PC19L_GMAC_GTXER ((PIN_PC19L_GMAC_GTXER << 16) | MUX_PC19L_GMAC_GTXER) +#define PORT_PC19L_GMAC_GTXER (_UL_(1) << 19) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ +#define MUX_PA14F_TCC2_WO0 _L_(5) +#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) +#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) +#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ +#define MUX_PA30F_TCC2_WO0 _L_(5) +#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) +#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) +#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ +#define MUX_PA15F_TCC2_WO1 _L_(5) +#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) +#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) +#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ +#define MUX_PA31F_TCC2_WO1 _L_(5) +#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) +#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) +#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC2_WO2 _L_(5) +#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) +#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) +#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ +#define MUX_PB02F_TCC2_WO2 _L_(5) +#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) +#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) +/* ========== PORT definition for TCC3 peripheral ========== */ +#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ +#define MUX_PB12F_TCC3_WO0 _L_(5) +#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) +#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) +#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ +#define MUX_PB16F_TCC3_WO0 _L_(5) +#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) +#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) +#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ +#define MUX_PB13F_TCC3_WO1 _L_(5) +#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) +#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) +#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ +#define MUX_PB17F_TCC3_WO1 _L_(5) +#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) +#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC4_WO0 _L_(4) +#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) +#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) +#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC4_WO0 _L_(4) +#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) +#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) +#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC4_WO0 _L_(4) +#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) +#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) +#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC4_WO1 _L_(4) +#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) +#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) +#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC4_WO1 _L_(4) +#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) +#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) +#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC4_WO1 _L_(4) +#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) +#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) +/* ========== PORT definition for TC5 peripheral ========== */ +#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC5_WO0 _L_(4) +#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) +#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) +#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ +#define MUX_PB10E_TC5_WO0 _L_(4) +#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) +#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) +#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC5_WO0 _L_(4) +#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) +#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) +#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC5_WO1 _L_(4) +#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) +#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) +#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC5_WO1 _L_(4) +#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) +#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) +#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC5_WO1 _L_(4) +#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) +#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) +/* ========== PORT definition for PDEC peripheral ========== */ +#define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */ +#define MUX_PB18G_PDEC_QDI0 _L_(6) +#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) +#define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18) +#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ +#define MUX_PB23G_PDEC_QDI0 _L_(6) +#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) +#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) +#define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */ +#define MUX_PC16G_PDEC_QDI0 _L_(6) +#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) +#define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16) +#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ +#define MUX_PA24G_PDEC_QDI0 _L_(6) +#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) +#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) +#define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */ +#define MUX_PB19G_PDEC_QDI1 _L_(6) +#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) +#define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19) +#define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */ +#define MUX_PB24G_PDEC_QDI1 _L_(6) +#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) +#define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24) +#define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */ +#define MUX_PC17G_PDEC_QDI1 _L_(6) +#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) +#define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17) +#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ +#define MUX_PA25G_PDEC_QDI1 _L_(6) +#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) +#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) +#define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */ +#define MUX_PB20G_PDEC_QDI2 _L_(6) +#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) +#define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20) +#define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */ +#define MUX_PB25G_PDEC_QDI2 _L_(6) +#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) +#define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25) +#define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */ +#define MUX_PC18G_PDEC_QDI2 _L_(6) +#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) +#define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18) +#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ +#define MUX_PB22G_PDEC_QDI2 _L_(6) +#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) +#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 _L_(1) +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) +#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 _L_(1) +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) +#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 _L_(1) +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) +#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 _L_(1) +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) +#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ +#define MUX_PA12M_AC_CMP0 _L_(12) +#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) +#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ +#define MUX_PA18M_AC_CMP0 _L_(12) +#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) +#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) +#define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */ +#define MUX_PB24M_AC_CMP0 _L_(12) +#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) +#define PORT_PB24M_AC_CMP0 (_UL_(1) << 24) +#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ +#define MUX_PA13M_AC_CMP1 _L_(12) +#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) +#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ +#define MUX_PA19M_AC_CMP1 _L_(12) +#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) +#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) +#define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */ +#define MUX_PB25M_AC_CMP1 _L_(12) +#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) +#define PORT_PB25M_AC_CMP1 (_UL_(1) << 25) +/* ========== PORT definition for QSPI peripheral ========== */ +#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ +#define MUX_PB11H_QSPI_CS _L_(7) +#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) +#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) +#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ +#define MUX_PA08H_QSPI_DATA0 _L_(7) +#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) +#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) +#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ +#define MUX_PA09H_QSPI_DATA1 _L_(7) +#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) +#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) +#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ +#define MUX_PA10H_QSPI_DATA2 _L_(7) +#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) +#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) +#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ +#define MUX_PA11H_QSPI_DATA3 _L_(7) +#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) +#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) +#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ +#define MUX_PB10H_QSPI_SCK _L_(7) +#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) +#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ +#define MUX_PA04N_CCL_IN0 _L_(13) +#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) +#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ +#define MUX_PA16N_CCL_IN0 _L_(13) +#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) +#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ +#define MUX_PB22N_CCL_IN0 _L_(13) +#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) +#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ +#define MUX_PA05N_CCL_IN1 _L_(13) +#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) +#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ +#define MUX_PA17N_CCL_IN1 _L_(13) +#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) +#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) +#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ +#define MUX_PB00N_CCL_IN1 _L_(13) +#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) +#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) +#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ +#define MUX_PA06N_CCL_IN2 _L_(13) +#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) +#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ +#define MUX_PA18N_CCL_IN2 _L_(13) +#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) +#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) +#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ +#define MUX_PB01N_CCL_IN2 _L_(13) +#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) +#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) +#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ +#define MUX_PA08N_CCL_IN3 _L_(13) +#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) +#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ +#define MUX_PA30N_CCL_IN3 _L_(13) +#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) +#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ +#define MUX_PA09N_CCL_IN4 _L_(13) +#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) +#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) +#define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */ +#define MUX_PC27N_CCL_IN4 _L_(13) +#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) +#define PORT_PC27N_CCL_IN4 (_UL_(1) << 27) +#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ +#define MUX_PA10N_CCL_IN5 _L_(13) +#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) +#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) +#define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */ +#define MUX_PC28N_CCL_IN5 _L_(13) +#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) +#define PORT_PC28N_CCL_IN5 (_UL_(1) << 28) +#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ +#define MUX_PA22N_CCL_IN6 _L_(13) +#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) +#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) +#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ +#define MUX_PB06N_CCL_IN6 _L_(13) +#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) +#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) +#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ +#define MUX_PA23N_CCL_IN7 _L_(13) +#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) +#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) +#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ +#define MUX_PB07N_CCL_IN7 _L_(13) +#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) +#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) +#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ +#define MUX_PA24N_CCL_IN8 _L_(13) +#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) +#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ +#define MUX_PB08N_CCL_IN8 _L_(13) +#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) +#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) +#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ +#define MUX_PB14N_CCL_IN9 _L_(13) +#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) +#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) +#define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */ +#define MUX_PC20N_CCL_IN9 _L_(13) +#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) +#define PORT_PC20N_CCL_IN9 (_UL_(1) << 20) +#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ +#define MUX_PB15N_CCL_IN10 _L_(13) +#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) +#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) +#define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */ +#define MUX_PC21N_CCL_IN10 _L_(13) +#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) +#define PORT_PC21N_CCL_IN10 (_UL_(1) << 21) +#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ +#define MUX_PB10N_CCL_IN11 _L_(13) +#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) +#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) +#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ +#define MUX_PB16N_CCL_IN11 _L_(13) +#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) +#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) +#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ +#define MUX_PA07N_CCL_OUT0 _L_(13) +#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) +#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ +#define MUX_PA19N_CCL_OUT0 _L_(13) +#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) +#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ +#define MUX_PB02N_CCL_OUT0 _L_(13) +#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) +#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ +#define MUX_PB23N_CCL_OUT0 _L_(13) +#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) +#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ +#define MUX_PA11N_CCL_OUT1 _L_(13) +#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) +#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ +#define MUX_PA31N_CCL_OUT1 _L_(13) +#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) +#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ +#define MUX_PB11N_CCL_OUT1 _L_(13) +#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) +#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ +#define MUX_PA25N_CCL_OUT2 _L_(13) +#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) +#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ +#define MUX_PB09N_CCL_OUT2 _L_(13) +#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) +#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) +#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ +#define MUX_PB17N_CCL_OUT3 _L_(13) +#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) +#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) +#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) +#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) +#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM4_PAD0 _L_(2) +#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) +#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) +#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) +#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) +#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) +#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM4_PAD1 _L_(2) +#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) +#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) +#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) +#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM4_PAD2 _L_(2) +#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) +#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) +#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) +#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM4_PAD3 _L_(2) +#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) +#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) +#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) +#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) +#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) +#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) +#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 _L_(2) +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) +#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) +#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) +#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) +#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) +#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) +#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 _L_(2) +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) +#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) +#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) +#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) +#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) +#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ +#define MUX_PB18C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) +#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) +#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) +#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ +#define MUX_PB01D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) +#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) +#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) +#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ +#define MUX_PB19C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) +#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM6 peripheral ========== */ +#define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */ +#define MUX_PC13D_SERCOM6_PAD0 _L_(3) +#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) +#define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13) +#define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */ +#define MUX_PC16C_SERCOM6_PAD0 _L_(2) +#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) +#define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16) +#define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */ +#define MUX_PC12D_SERCOM6_PAD1 _L_(3) +#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) +#define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12) +#define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */ +#define MUX_PC05C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) +#define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5) +#define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */ +#define MUX_PC17C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) +#define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17) +#define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */ +#define MUX_PC14D_SERCOM6_PAD2 _L_(3) +#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) +#define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14) +#define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */ +#define MUX_PC06C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) +#define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6) +#define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */ +#define MUX_PC10C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) +#define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10) +#define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */ +#define MUX_PC18C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) +#define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18) +#define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */ +#define MUX_PC15D_SERCOM6_PAD3 _L_(3) +#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) +#define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15) +#define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */ +#define MUX_PC07C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) +#define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7) +#define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */ +#define MUX_PC11C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) +#define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11) +#define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */ +#define MUX_PC19C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) +#define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM7 peripheral ========== */ +#define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */ +#define MUX_PB21D_SERCOM7_PAD0 _L_(3) +#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) +#define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21) +#define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */ +#define MUX_PB30C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) +#define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30) +#define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */ +#define MUX_PC12C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) +#define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12) +#define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */ +#define MUX_PB20D_SERCOM7_PAD1 _L_(3) +#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) +#define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20) +#define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */ +#define MUX_PB31C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) +#define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31) +#define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */ +#define MUX_PC13C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) +#define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13) +#define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */ +#define MUX_PB18D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) +#define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18) +#define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */ +#define MUX_PC10D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) +#define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10) +#define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */ +#define MUX_PC14C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) +#define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14) +#define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */ +#define MUX_PA30C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) +#define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30) +#define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */ +#define MUX_PB19D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) +#define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19) +#define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */ +#define MUX_PC11D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) +#define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11) +#define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */ +#define MUX_PC15C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) +#define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15) +#define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */ +#define MUX_PA31C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) +#define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31) +/* ========== PORT definition for TCC4 peripheral ========== */ +#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ +#define MUX_PB14F_TCC4_WO0 _L_(5) +#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) +#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) +#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ +#define MUX_PB30F_TCC4_WO0 _L_(5) +#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) +#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) +#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ +#define MUX_PB15F_TCC4_WO1 _L_(5) +#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) +#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) +#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ +#define MUX_PB31F_TCC4_WO1 _L_(5) +#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) +#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC6 peripheral ========== */ +#define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */ +#define MUX_PA30E_TC6_WO0 _L_(4) +#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) +#define PORT_PA30E_TC6_WO0 (_UL_(1) << 30) +#define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC6_WO0 _L_(4) +#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) +#define PORT_PB02E_TC6_WO0 (_UL_(1) << 2) +#define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */ +#define MUX_PB16E_TC6_WO0 _L_(4) +#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) +#define PORT_PB16E_TC6_WO0 (_UL_(1) << 16) +#define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */ +#define MUX_PA31E_TC6_WO1 _L_(4) +#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) +#define PORT_PA31E_TC6_WO1 (_UL_(1) << 31) +#define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC6_WO1 _L_(4) +#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) +#define PORT_PB03E_TC6_WO1 (_UL_(1) << 3) +#define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */ +#define MUX_PB17E_TC6_WO1 _L_(4) +#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) +#define PORT_PB17E_TC6_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC7 peripheral ========== */ +#define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC7_WO0 _L_(4) +#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) +#define PORT_PA20E_TC7_WO0 (_UL_(1) << 20) +#define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */ +#define MUX_PB00E_TC7_WO0 _L_(4) +#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) +#define PORT_PB00E_TC7_WO0 (_UL_(1) << 0) +#define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC7_WO0 _L_(4) +#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) +#define PORT_PB22E_TC7_WO0 (_UL_(1) << 22) +#define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC7_WO1 _L_(4) +#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) +#define PORT_PA21E_TC7_WO1 (_UL_(1) << 21) +#define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */ +#define MUX_PB01E_TC7_WO1 _L_(4) +#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) +#define PORT_PB01E_TC7_WO1 (_UL_(1) << 1) +#define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC7_WO1 _L_(4) +#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) +#define PORT_PB23E_TC7_WO1 (_UL_(1) << 23) +/* ========== PORT definition for ADC0 peripheral ========== */ +#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC0_AIN0 _L_(1) +#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) +#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC0_AIN1 _L_(1) +#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) +#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC0_AIN2 _L_(1) +#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) +#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC0_AIN3 _L_(1) +#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) +#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC0_AIN4 _L_(1) +#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) +#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC0_AIN5 _L_(1) +#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) +#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC0_AIN6 _L_(1) +#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) +#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC0_AIN7 _L_(1) +#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) +#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ +#define MUX_PA08B_ADC0_AIN8 _L_(1) +#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) +#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ +#define MUX_PA09B_ADC0_AIN9 _L_(1) +#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) +#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ +#define MUX_PA10B_ADC0_AIN10 _L_(1) +#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) +#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ +#define MUX_PA11B_ADC0_AIN11 _L_(1) +#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) +#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) +#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ +#define MUX_PB00B_ADC0_AIN12 _L_(1) +#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) +#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ +#define MUX_PB01B_ADC0_AIN13 _L_(1) +#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) +#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) +#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ +#define MUX_PB02B_ADC0_AIN14 _L_(1) +#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) +#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ +#define MUX_PB03B_ADC0_AIN15 _L_(1) +#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) +#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) +#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ +#define MUX_PA03O_ADC0_DRV0 _L_(14) +#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) +#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) +#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ +#define MUX_PB08O_ADC0_DRV1 _L_(14) +#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) +#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) +#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ +#define MUX_PB09O_ADC0_DRV2 _L_(14) +#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) +#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) +#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ +#define MUX_PA04O_ADC0_DRV3 _L_(14) +#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) +#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) +#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ +#define MUX_PA06O_ADC0_DRV4 _L_(14) +#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) +#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) +#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ +#define MUX_PA07O_ADC0_DRV5 _L_(14) +#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) +#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) +#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ +#define MUX_PA08O_ADC0_DRV6 _L_(14) +#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) +#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) +#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ +#define MUX_PA09O_ADC0_DRV7 _L_(14) +#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) +#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) +#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ +#define MUX_PA10O_ADC0_DRV8 _L_(14) +#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) +#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) +#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ +#define MUX_PA11O_ADC0_DRV9 _L_(14) +#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) +#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) +#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ +#define MUX_PA16O_ADC0_DRV10 _L_(14) +#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) +#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) +#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ +#define MUX_PA17O_ADC0_DRV11 _L_(14) +#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) +#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) +#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ +#define MUX_PA18O_ADC0_DRV12 _L_(14) +#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) +#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) +#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ +#define MUX_PA19O_ADC0_DRV13 _L_(14) +#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) +#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) +#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ +#define MUX_PA20O_ADC0_DRV14 _L_(14) +#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) +#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) +#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ +#define MUX_PA21O_ADC0_DRV15 _L_(14) +#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) +#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) +#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ +#define MUX_PA22O_ADC0_DRV16 _L_(14) +#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) +#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) +#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ +#define MUX_PA23O_ADC0_DRV17 _L_(14) +#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) +#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) +#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ +#define MUX_PA27O_ADC0_DRV18 _L_(14) +#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) +#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) +#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ +#define MUX_PA30O_ADC0_DRV19 _L_(14) +#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) +#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) +#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ +#define MUX_PB02O_ADC0_DRV20 _L_(14) +#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) +#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) +#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ +#define MUX_PB03O_ADC0_DRV21 _L_(14) +#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) +#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) +#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ +#define MUX_PB04O_ADC0_DRV22 _L_(14) +#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) +#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) +#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ +#define MUX_PB05O_ADC0_DRV23 _L_(14) +#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) +#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) +#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ +#define MUX_PB06O_ADC0_DRV24 _L_(14) +#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) +#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) +#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ +#define MUX_PB07O_ADC0_DRV25 _L_(14) +#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) +#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) +#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ +#define MUX_PB12O_ADC0_DRV26 _L_(14) +#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) +#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) +#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ +#define MUX_PB13O_ADC0_DRV27 _L_(14) +#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) +#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) +#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ +#define MUX_PB14O_ADC0_DRV28 _L_(14) +#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) +#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) +#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ +#define MUX_PB15O_ADC0_DRV29 _L_(14) +#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) +#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) +#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ +#define MUX_PB00O_ADC0_DRV30 _L_(14) +#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) +#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) +#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ +#define MUX_PB01O_ADC0_DRV31 _L_(14) +#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) +#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) +#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ +#define MUX_PA03B_ADC0_PTCXY0 _L_(1) +#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) +#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ +#define MUX_PB08B_ADC0_PTCXY1 _L_(1) +#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) +#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ +#define MUX_PB09B_ADC0_PTCXY2 _L_(1) +#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) +#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ +#define MUX_PA04B_ADC0_PTCXY3 _L_(1) +#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) +#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) +#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ +#define MUX_PA06B_ADC0_PTCXY4 _L_(1) +#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) +#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ +#define MUX_PA07B_ADC0_PTCXY5 _L_(1) +#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) +#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ +#define MUX_PA08B_ADC0_PTCXY6 _L_(1) +#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) +#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ +#define MUX_PA09B_ADC0_PTCXY7 _L_(1) +#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) +#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ +#define MUX_PA10B_ADC0_PTCXY8 _L_(1) +#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) +#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ +#define MUX_PA11B_ADC0_PTCXY9 _L_(1) +#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) +#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) +#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ +#define MUX_PA16B_ADC0_PTCXY10 _L_(1) +#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) +#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) +#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ +#define MUX_PA17B_ADC0_PTCXY11 _L_(1) +#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) +#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) +#define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */ +#define MUX_PA18B_ADC0_PTCXY12 _L_(1) +#define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12) +#define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18) +#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ +#define MUX_PA19B_ADC0_PTCXY13 _L_(1) +#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) +#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) +#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ +#define MUX_PA20B_ADC0_PTCXY14 _L_(1) +#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) +#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) +#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ +#define MUX_PA21B_ADC0_PTCXY15 _L_(1) +#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) +#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) +#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ +#define MUX_PA22B_ADC0_PTCXY16 _L_(1) +#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) +#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) +#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ +#define MUX_PA23B_ADC0_PTCXY17 _L_(1) +#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) +#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) +#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ +#define MUX_PA27B_ADC0_PTCXY18 _L_(1) +#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) +#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) +#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ +#define MUX_PA30B_ADC0_PTCXY19 _L_(1) +#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) +#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) +#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ +#define MUX_PB02B_ADC0_PTCXY20 _L_(1) +#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) +#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ +#define MUX_PB03B_ADC0_PTCXY21 _L_(1) +#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) +#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) +#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ +#define MUX_PB04B_ADC0_PTCXY22 _L_(1) +#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) +#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) +#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ +#define MUX_PB05B_ADC0_PTCXY23 _L_(1) +#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) +#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) +#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ +#define MUX_PB06B_ADC0_PTCXY24 _L_(1) +#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) +#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) +#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ +#define MUX_PB07B_ADC0_PTCXY25 _L_(1) +#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) +#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) +#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ +#define MUX_PB12B_ADC0_PTCXY26 _L_(1) +#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) +#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) +#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ +#define MUX_PB13B_ADC0_PTCXY27 _L_(1) +#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) +#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) +#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ +#define MUX_PB14B_ADC0_PTCXY28 _L_(1) +#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) +#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) +#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ +#define MUX_PB15B_ADC0_PTCXY29 _L_(1) +#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) +#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) +#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ +#define MUX_PB00B_ADC0_PTCXY30 _L_(1) +#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) +#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ +#define MUX_PB01B_ADC0_PTCXY31 _L_(1) +#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) +#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) +/* ========== PORT definition for ADC1 peripheral ========== */ +#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ +#define MUX_PB08B_ADC1_AIN0 _L_(1) +#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) +#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) +#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ +#define MUX_PB09B_ADC1_AIN1 _L_(1) +#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) +#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) +#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ +#define MUX_PA08B_ADC1_AIN2 _L_(1) +#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) +#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) +#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ +#define MUX_PA09B_ADC1_AIN3 _L_(1) +#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) +#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) +#define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */ +#define MUX_PC02B_ADC1_AIN4 _L_(1) +#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) +#define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2) +#define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */ +#define MUX_PC03B_ADC1_AIN5 _L_(1) +#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) +#define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3) +#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ +#define MUX_PB04B_ADC1_AIN6 _L_(1) +#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) +#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) +#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ +#define MUX_PB05B_ADC1_AIN7 _L_(1) +#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) +#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) +#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ +#define MUX_PB06B_ADC1_AIN8 _L_(1) +#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) +#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) +#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ +#define MUX_PB07B_ADC1_AIN9 _L_(1) +#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) +#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) +#define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */ +#define MUX_PC00B_ADC1_AIN10 _L_(1) +#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) +#define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0) +#define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */ +#define MUX_PC01B_ADC1_AIN11 _L_(1) +#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) +#define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 _L_(1) +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) +#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 _L_(1) +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) +/* ========== PORT definition for I2S peripheral ========== */ +#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ +#define MUX_PA09J_I2S_FS0 _L_(9) +#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) +#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) +#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ +#define MUX_PA20J_I2S_FS0 _L_(9) +#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) +#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) +#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ +#define MUX_PA23J_I2S_FS1 _L_(9) +#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) +#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) +#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ +#define MUX_PB11J_I2S_FS1 _L_(9) +#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) +#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) +#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ +#define MUX_PA08J_I2S_MCK0 _L_(9) +#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) +#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) +#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ +#define MUX_PB17J_I2S_MCK0 _L_(9) +#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) +#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) +#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ +#define MUX_PB13J_I2S_MCK1 _L_(9) +#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) +#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) +#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ +#define MUX_PA10J_I2S_SCK0 _L_(9) +#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) +#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) +#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ +#define MUX_PB16J_I2S_SCK0 _L_(9) +#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) +#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) +#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ +#define MUX_PB12J_I2S_SCK1 _L_(9) +#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) +#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) +#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ +#define MUX_PA22J_I2S_SDI _L_(9) +#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) +#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) +#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ +#define MUX_PB10J_I2S_SDI _L_(9) +#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) +#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) +#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ +#define MUX_PA11J_I2S_SDO _L_(9) +#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) +#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) +#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ +#define MUX_PA21J_I2S_SDO _L_(9) +#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) +#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) +/* ========== PORT definition for PCC peripheral ========== */ +#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ +#define MUX_PA14K_PCC_CLK _L_(10) +#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) +#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) +#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ +#define MUX_PA16K_PCC_DATA0 _L_(10) +#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) +#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) +#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ +#define MUX_PA17K_PCC_DATA1 _L_(10) +#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) +#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) +#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ +#define MUX_PA18K_PCC_DATA2 _L_(10) +#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) +#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) +#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ +#define MUX_PA19K_PCC_DATA3 _L_(10) +#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) +#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) +#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ +#define MUX_PA20K_PCC_DATA4 _L_(10) +#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) +#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) +#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ +#define MUX_PA21K_PCC_DATA5 _L_(10) +#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) +#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) +#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ +#define MUX_PA22K_PCC_DATA6 _L_(10) +#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) +#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) +#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ +#define MUX_PA23K_PCC_DATA7 _L_(10) +#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) +#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) +#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ +#define MUX_PB14K_PCC_DATA8 _L_(10) +#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) +#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) +#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ +#define MUX_PB15K_PCC_DATA9 _L_(10) +#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) +#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) +#define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */ +#define MUX_PC12K_PCC_DATA10 _L_(10) +#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) +#define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12) +#define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */ +#define MUX_PC13K_PCC_DATA11 _L_(10) +#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) +#define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13) +#define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */ +#define MUX_PC14K_PCC_DATA12 _L_(10) +#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) +#define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14) +#define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */ +#define MUX_PC15K_PCC_DATA13 _L_(10) +#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) +#define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15) +#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ +#define MUX_PA12K_PCC_DEN1 _L_(10) +#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) +#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) +#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ +#define MUX_PA13K_PCC_DEN2 _L_(10) +#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) +#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) +/* ========== PORT definition for SDHC0 peripheral ========== */ +#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ +#define MUX_PA06I_SDHC0_SDCD _L_(8) +#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) +#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ +#define MUX_PA12I_SDHC0_SDCD _L_(8) +#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) +#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ +#define MUX_PB12I_SDHC0_SDCD _L_(8) +#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) +#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */ +#define MUX_PC06I_SDHC0_SDCD _L_(8) +#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) +#define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ +#define MUX_PB11I_SDHC0_SDCK _L_(8) +#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) +#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) +#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ +#define MUX_PA08I_SDHC0_SDCMD _L_(8) +#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) +#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) +#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ +#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) +#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) +#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) +#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ +#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) +#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) +#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) +#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ +#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) +#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) +#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) +#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ +#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) +#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) +#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) +#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ +#define MUX_PA07I_SDHC0_SDWP _L_(8) +#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) +#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) +#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ +#define MUX_PA13I_SDHC0_SDWP _L_(8) +#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) +#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ +#define MUX_PB13I_SDHC0_SDWP _L_(8) +#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) +#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */ +#define MUX_PC07I_SDHC0_SDWP _L_(8) +#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) +#define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7) +/* ========== PORT definition for SDHC1 peripheral ========== */ +#define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */ +#define MUX_PB16I_SDHC1_SDCD _L_(8) +#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) +#define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16) +#define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */ +#define MUX_PC20I_SDHC1_SDCD _L_(8) +#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) +#define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20) +#define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */ +#define MUX_PA21I_SDHC1_SDCK _L_(8) +#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) +#define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21) +#define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */ +#define MUX_PA20I_SDHC1_SDCMD _L_(8) +#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) +#define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20) +#define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */ +#define MUX_PB18I_SDHC1_SDDAT0 _L_(8) +#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) +#define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18) +#define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */ +#define MUX_PB19I_SDHC1_SDDAT1 _L_(8) +#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) +#define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19) +#define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */ +#define MUX_PB20I_SDHC1_SDDAT2 _L_(8) +#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) +#define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20) +#define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */ +#define MUX_PB21I_SDHC1_SDDAT3 _L_(8) +#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) +#define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21) +#define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */ +#define MUX_PB17I_SDHC1_SDWP _L_(8) +#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) +#define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17) +#define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */ +#define MUX_PC21I_SDHC1_SDWP _L_(8) +#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) +#define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21) + +#endif /* _SAME54N19A_PIO_ */ diff --git a/software/firmware/oracle_same54n19a/include/pio/same54n20a.h b/software/firmware/oracle_same54n19a/include/pio/same54n20a.h new file mode 100644 index 00000000..d8a7ac4b --- /dev/null +++ b/software/firmware/oracle_same54n19a/include/pio/same54n20a.h @@ -0,0 +1,2688 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAME54N20A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54N20A_PIO_ +#define _SAME54N20A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ +#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ +#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ +#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ +#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ +#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ +#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ +#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ +#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ +#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ +#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ +#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ +#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ +#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ +#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ +#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ +#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ +#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ +#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ +#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ +#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ +#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ +#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ +#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ +#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ +#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ +#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ +#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ +#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ +#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ +#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ +#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ +#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ +#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ +#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ +#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ +#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ +#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ +#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ +#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ +#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ +#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ +#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ +#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ +#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ +#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ +#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ +#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ +#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ +#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ +#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ +#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ +#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ +#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ +#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ +#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ +#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ +#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ +#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ +/* ========== PORT definition for CM4 peripheral ========== */ +#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ +#define MUX_PA30H_CM4_SWCLK _L_(7) +#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) +#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) +#define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */ +#define MUX_PC27M_CM4_SWO _L_(12) +#define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO) +#define PORT_PC27M_CM4_SWO (_UL_(1) << 27) +#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ +#define MUX_PB30H_CM4_SWO _L_(7) +#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) +#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) +#define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */ +#define MUX_PC27H_CM4_TRACECLK _L_(7) +#define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK) +#define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27) +#define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */ +#define MUX_PC28H_CM4_TRACEDATA0 _L_(7) +#define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0) +#define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28) +#define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */ +#define MUX_PC26H_CM4_TRACEDATA1 _L_(7) +#define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1) +#define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26) +#define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */ +#define MUX_PC25H_CM4_TRACEDATA2 _L_(7) +#define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2) +#define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25) +#define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */ +#define MUX_PC24H_CM4_TRACEDATA3 _L_(7) +#define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3) +#define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24) +/* ========== PORT definition for ANAREF peripheral ========== */ +#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ +#define MUX_PA03B_ANAREF_VREF0 _L_(1) +#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) +#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) +#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ +#define MUX_PA04B_ANAREF_VREF1 _L_(1) +#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) +#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) +#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ +#define MUX_PA06B_ANAREF_VREF2 _L_(1) +#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) +#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ +#define MUX_PA30M_GCLK_IO0 _L_(12) +#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) +#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ +#define MUX_PB14M_GCLK_IO0 _L_(12) +#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) +#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ +#define MUX_PA14M_GCLK_IO0 _L_(12) +#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) +#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ +#define MUX_PB22M_GCLK_IO0 _L_(12) +#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) +#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ +#define MUX_PB15M_GCLK_IO1 _L_(12) +#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) +#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ +#define MUX_PA15M_GCLK_IO1 _L_(12) +#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) +#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ +#define MUX_PB23M_GCLK_IO1 _L_(12) +#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) +#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ +#define MUX_PA27M_GCLK_IO1 _L_(12) +#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) +#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) +#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ +#define MUX_PA16M_GCLK_IO2 _L_(12) +#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) +#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ +#define MUX_PB16M_GCLK_IO2 _L_(12) +#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) +#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ +#define MUX_PA17M_GCLK_IO3 _L_(12) +#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) +#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ +#define MUX_PB17M_GCLK_IO3 _L_(12) +#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) +#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ +#define MUX_PA10M_GCLK_IO4 _L_(12) +#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) +#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ +#define MUX_PB10M_GCLK_IO4 _L_(12) +#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) +#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */ +#define MUX_PB18M_GCLK_IO4 _L_(12) +#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) +#define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18) +#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ +#define MUX_PA11M_GCLK_IO5 _L_(12) +#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) +#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ +#define MUX_PB11M_GCLK_IO5 _L_(12) +#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) +#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */ +#define MUX_PB19M_GCLK_IO5 _L_(12) +#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) +#define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19) +#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ +#define MUX_PB12M_GCLK_IO6 _L_(12) +#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) +#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) +#define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */ +#define MUX_PB20M_GCLK_IO6 _L_(12) +#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) +#define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20) +#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ +#define MUX_PB13M_GCLK_IO7 _L_(12) +#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) +#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) +#define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */ +#define MUX_PB21M_GCLK_IO7 _L_(12) +#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) +#define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ +#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ +#define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */ +#define MUX_PC00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) +#define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ +#define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */ +#define MUX_PC16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) +#define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ +#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ +#define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */ +#define MUX_PC01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) +#define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ +#define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */ +#define MUX_PC17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) +#define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ +#define MUX_PB18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) +#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ +#define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */ +#define MUX_PC02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) +#define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ +#define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */ +#define MUX_PC18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) +#define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ +#define MUX_PB19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) +#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ +#define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */ +#define MUX_PC03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) +#define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ +#define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */ +#define MUX_PC19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) +#define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ +#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ +#define MUX_PB20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) +#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ +#define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */ +#define MUX_PC20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) +#define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ +#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ +#define MUX_PB21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) +#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ +#define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */ +#define MUX_PC05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) +#define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ +#define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */ +#define MUX_PC21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) +#define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */ +#define MUX_PC06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) +#define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) +#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ +#define MUX_PB24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) +#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ +#define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */ +#define MUX_PC24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) +#define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) +#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ +#define MUX_PB25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) +#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ +#define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */ +#define MUX_PC07A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) +#define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7) +#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ +#define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */ +#define MUX_PC25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) +#define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ +#define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */ +#define MUX_PC10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) +#define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ +#define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */ +#define MUX_PC26A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) +#define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26) +#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) +#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */ +#define MUX_PC11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) +#define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ +#define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */ +#define MUX_PC27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) +#define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ +#define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */ +#define MUX_PC12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) +#define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ +#define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */ +#define MUX_PC28A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) +#define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28) +#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ +#define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */ +#define MUX_PC13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) +#define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) +#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ +#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ +#define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */ +#define MUX_PC14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) +#define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) +#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ +#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ +#define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */ +#define MUX_PC15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) +#define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */ +#define MUX_PC17D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) +#define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ +#define MUX_PB24C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) +#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */ +#define MUX_PC16D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) +#define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ +#define MUX_PB25C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) +#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */ +#define MUX_PC18D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) +#define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ +#define MUX_PC24C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) +#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */ +#define MUX_PC19D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) +#define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ +#define MUX_PC25C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) +#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */ +#define MUX_PC27C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) +#define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */ +#define MUX_PC28C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) +#define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) +#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) +#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TC0_WO0 _L_(4) +#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) +#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TC0_WO0 _L_(4) +#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) +#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TC0_WO0 _L_(4) +#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) +#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) +#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TC0_WO1 _L_(4) +#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) +#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TC0_WO1 _L_(4) +#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) +#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) +#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TC0_WO1 _L_(4) +#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) +#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TC1_WO0 _L_(4) +#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) +#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) +#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TC1_WO0 _L_(4) +#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) +#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) +#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TC1_WO1 _L_(4) +#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) +#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) +#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TC1_WO1 _L_(4) +#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) +#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ +#define MUX_PA24H_USB_DM _L_(7) +#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) +#define PORT_PA24H_USB_DM (_UL_(1) << 24) +#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ +#define MUX_PA25H_USB_DP _L_(7) +#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) +#define PORT_PA25H_USB_DP (_UL_(1) << 25) +#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ +#define MUX_PA23H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) +#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ +#define MUX_PB22H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) +#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) +#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) +#define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */ +#define MUX_PB25D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) +#define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25) +#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) +#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) +#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) +#define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */ +#define MUX_PB24D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) +#define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24) +#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) +#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) +#define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */ +#define MUX_PC24D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) +#define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24) +#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) +#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) +#define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */ +#define MUX_PC25D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) +#define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25) +#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) +#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) +#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) +#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ +#define MUX_PB20C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) +#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) +#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) +#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) +#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) +#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ +#define MUX_PB21C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) +#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) +#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ +#define MUX_PA20G_TCC0_WO0 _L_(6) +#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) +#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) +#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ +#define MUX_PB12G_TCC0_WO0 _L_(6) +#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) +#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) +#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ +#define MUX_PA08F_TCC0_WO0 _L_(5) +#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) +#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */ +#define MUX_PC10F_TCC0_WO0 _L_(5) +#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) +#define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10) +#define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */ +#define MUX_PC16F_TCC0_WO0 _L_(5) +#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) +#define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16) +#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ +#define MUX_PA21G_TCC0_WO1 _L_(6) +#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) +#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) +#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ +#define MUX_PB13G_TCC0_WO1 _L_(6) +#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) +#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) +#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ +#define MUX_PA09F_TCC0_WO1 _L_(5) +#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) +#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */ +#define MUX_PC11F_TCC0_WO1 _L_(5) +#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) +#define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11) +#define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */ +#define MUX_PC17F_TCC0_WO1 _L_(5) +#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) +#define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17) +#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ +#define MUX_PA22G_TCC0_WO2 _L_(6) +#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) +#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ +#define MUX_PB14G_TCC0_WO2 _L_(6) +#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) +#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */ +#define MUX_PC12F_TCC0_WO2 _L_(5) +#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) +#define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12) +#define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */ +#define MUX_PC18F_TCC0_WO2 _L_(5) +#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) +#define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18) +#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ +#define MUX_PA23G_TCC0_WO3 _L_(6) +#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) +#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ +#define MUX_PB15G_TCC0_WO3 _L_(6) +#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) +#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */ +#define MUX_PC13F_TCC0_WO3 _L_(5) +#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) +#define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13) +#define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */ +#define MUX_PC19F_TCC0_WO3 _L_(5) +#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) +#define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19) +#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ +#define MUX_PA16G_TCC0_WO4 _L_(6) +#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) +#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ +#define MUX_PB16G_TCC0_WO4 _L_(6) +#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) +#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 _L_(5) +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) +#define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */ +#define MUX_PC14F_TCC0_WO4 _L_(5) +#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) +#define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14) +#define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */ +#define MUX_PC20F_TCC0_WO4 _L_(5) +#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) +#define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20) +#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ +#define MUX_PA17G_TCC0_WO5 _L_(6) +#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) +#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ +#define MUX_PB17G_TCC0_WO5 _L_(6) +#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) +#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */ +#define MUX_PC15F_TCC0_WO5 _L_(5) +#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) +#define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15) +#define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */ +#define MUX_PC21F_TCC0_WO5 _L_(5) +#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) +#define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21) +#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ +#define MUX_PA18G_TCC0_WO6 _L_(6) +#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) +#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) +#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ +#define MUX_PB30G_TCC0_WO6 _L_(6) +#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) +#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ +#define MUX_PA19G_TCC0_WO7 _L_(6) +#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) +#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) +#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ +#define MUX_PB31G_TCC0_WO7 _L_(6) +#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) +#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ +#define MUX_PB10G_TCC1_WO0 _L_(6) +#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) +#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) +#define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */ +#define MUX_PC14G_TCC1_WO0 _L_(6) +#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) +#define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14) +#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC1_WO0 _L_(5) +#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) +#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) +#define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */ +#define MUX_PB18F_TCC1_WO0 _L_(5) +#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) +#define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18) +#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ +#define MUX_PB11G_TCC1_WO1 _L_(6) +#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) +#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) +#define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */ +#define MUX_PC15G_TCC1_WO1 _L_(6) +#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) +#define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15) +#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC1_WO1 _L_(5) +#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) +#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) +#define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */ +#define MUX_PB19F_TCC1_WO1 _L_(5) +#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) +#define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19) +#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ +#define MUX_PA12G_TCC1_WO2 _L_(6) +#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) +#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) +#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ +#define MUX_PA14G_TCC1_WO2 _L_(6) +#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) +#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) +#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC1_WO2 _L_(5) +#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) +#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) +#define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */ +#define MUX_PB20F_TCC1_WO2 _L_(5) +#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) +#define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20) +#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ +#define MUX_PA13G_TCC1_WO3 _L_(6) +#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) +#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) +#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ +#define MUX_PA15G_TCC1_WO3 _L_(6) +#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) +#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) +#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC1_WO3 _L_(5) +#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) +#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) +#define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */ +#define MUX_PB21F_TCC1_WO3 _L_(5) +#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) +#define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21) +#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ +#define MUX_PA08G_TCC1_WO4 _L_(6) +#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) +#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) +#define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */ +#define MUX_PC10G_TCC1_WO4 _L_(6) +#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) +#define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10) +#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ +#define MUX_PA20F_TCC1_WO4 _L_(5) +#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) +#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) +#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ +#define MUX_PA09G_TCC1_WO5 _L_(6) +#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) +#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) +#define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */ +#define MUX_PC11G_TCC1_WO5 _L_(6) +#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) +#define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11) +#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ +#define MUX_PA21F_TCC1_WO5 _L_(5) +#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) +#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) +#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ +#define MUX_PA10G_TCC1_WO6 _L_(6) +#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) +#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) +#define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */ +#define MUX_PC12G_TCC1_WO6 _L_(6) +#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) +#define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12) +#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ +#define MUX_PA22F_TCC1_WO6 _L_(5) +#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) +#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) +#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ +#define MUX_PA11G_TCC1_WO7 _L_(6) +#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) +#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) +#define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */ +#define MUX_PC13G_TCC1_WO7 _L_(6) +#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) +#define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13) +#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ +#define MUX_PA23F_TCC1_WO7 _L_(5) +#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) +#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TC2_WO0 _L_(4) +#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) +#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) +#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TC2_WO0 _L_(4) +#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) +#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) +#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TC2_WO0 _L_(4) +#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) +#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) +#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TC2_WO1 _L_(4) +#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) +#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) +#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TC2_WO1 _L_(4) +#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) +#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) +#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TC2_WO1 _L_(4) +#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) +#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC3_WO0 _L_(4) +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) +#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC3_WO0 _L_(4) +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) +#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC3_WO1 _L_(4) +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) +#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC3_WO1 _L_(4) +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) +/* ========== PORT definition for CAN0 peripheral ========== */ +#define PIN_PA23I_CAN0_RX _L_(23) /**< \brief CAN0 signal: RX on PA23 mux I */ +#define MUX_PA23I_CAN0_RX _L_(8) +#define PINMUX_PA23I_CAN0_RX ((PIN_PA23I_CAN0_RX << 16) | MUX_PA23I_CAN0_RX) +#define PORT_PA23I_CAN0_RX (_UL_(1) << 23) +#define PIN_PA25I_CAN0_RX _L_(25) /**< \brief CAN0 signal: RX on PA25 mux I */ +#define MUX_PA25I_CAN0_RX _L_(8) +#define PINMUX_PA25I_CAN0_RX ((PIN_PA25I_CAN0_RX << 16) | MUX_PA25I_CAN0_RX) +#define PORT_PA25I_CAN0_RX (_UL_(1) << 25) +#define PIN_PA22I_CAN0_TX _L_(22) /**< \brief CAN0 signal: TX on PA22 mux I */ +#define MUX_PA22I_CAN0_TX _L_(8) +#define PINMUX_PA22I_CAN0_TX ((PIN_PA22I_CAN0_TX << 16) | MUX_PA22I_CAN0_TX) +#define PORT_PA22I_CAN0_TX (_UL_(1) << 22) +#define PIN_PA24I_CAN0_TX _L_(24) /**< \brief CAN0 signal: TX on PA24 mux I */ +#define MUX_PA24I_CAN0_TX _L_(8) +#define PINMUX_PA24I_CAN0_TX ((PIN_PA24I_CAN0_TX << 16) | MUX_PA24I_CAN0_TX) +#define PORT_PA24I_CAN0_TX (_UL_(1) << 24) +/* ========== PORT definition for CAN1 peripheral ========== */ +#define PIN_PB13H_CAN1_RX _L_(45) /**< \brief CAN1 signal: RX on PB13 mux H */ +#define MUX_PB13H_CAN1_RX _L_(7) +#define PINMUX_PB13H_CAN1_RX ((PIN_PB13H_CAN1_RX << 16) | MUX_PB13H_CAN1_RX) +#define PORT_PB13H_CAN1_RX (_UL_(1) << 13) +#define PIN_PB15H_CAN1_RX _L_(47) /**< \brief CAN1 signal: RX on PB15 mux H */ +#define MUX_PB15H_CAN1_RX _L_(7) +#define PINMUX_PB15H_CAN1_RX ((PIN_PB15H_CAN1_RX << 16) | MUX_PB15H_CAN1_RX) +#define PORT_PB15H_CAN1_RX (_UL_(1) << 15) +#define PIN_PB12H_CAN1_TX _L_(44) /**< \brief CAN1 signal: TX on PB12 mux H */ +#define MUX_PB12H_CAN1_TX _L_(7) +#define PINMUX_PB12H_CAN1_TX ((PIN_PB12H_CAN1_TX << 16) | MUX_PB12H_CAN1_TX) +#define PORT_PB12H_CAN1_TX (_UL_(1) << 12) +#define PIN_PB14H_CAN1_TX _L_(46) /**< \brief CAN1 signal: TX on PB14 mux H */ +#define MUX_PB14H_CAN1_TX _L_(7) +#define PINMUX_PB14H_CAN1_TX ((PIN_PB14H_CAN1_TX << 16) | MUX_PB14H_CAN1_TX) +#define PORT_PB14H_CAN1_TX (_UL_(1) << 14) +/* ========== PORT definition for GMAC peripheral ========== */ +#define PIN_PC21L_GMAC_GCOL _L_(85) /**< \brief GMAC signal: GCOL on PC21 mux L */ +#define MUX_PC21L_GMAC_GCOL _L_(11) +#define PINMUX_PC21L_GMAC_GCOL ((PIN_PC21L_GMAC_GCOL << 16) | MUX_PC21L_GMAC_GCOL) +#define PORT_PC21L_GMAC_GCOL (_UL_(1) << 21) +#define PIN_PA16L_GMAC_GCRS _L_(16) /**< \brief GMAC signal: GCRS on PA16 mux L */ +#define MUX_PA16L_GMAC_GCRS _L_(11) +#define PINMUX_PA16L_GMAC_GCRS ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS) +#define PORT_PA16L_GMAC_GCRS (_UL_(1) << 16) +#define PIN_PA20L_GMAC_GMDC _L_(20) /**< \brief GMAC signal: GMDC on PA20 mux L */ +#define MUX_PA20L_GMAC_GMDC _L_(11) +#define PINMUX_PA20L_GMAC_GMDC ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC) +#define PORT_PA20L_GMAC_GMDC (_UL_(1) << 20) +#define PIN_PB14L_GMAC_GMDC _L_(46) /**< \brief GMAC signal: GMDC on PB14 mux L */ +#define MUX_PB14L_GMAC_GMDC _L_(11) +#define PINMUX_PB14L_GMAC_GMDC ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC) +#define PORT_PB14L_GMAC_GMDC (_UL_(1) << 14) +#define PIN_PC11L_GMAC_GMDC _L_(75) /**< \brief GMAC signal: GMDC on PC11 mux L */ +#define MUX_PC11L_GMAC_GMDC _L_(11) +#define PINMUX_PC11L_GMAC_GMDC ((PIN_PC11L_GMAC_GMDC << 16) | MUX_PC11L_GMAC_GMDC) +#define PORT_PC11L_GMAC_GMDC (_UL_(1) << 11) +#define PIN_PA21L_GMAC_GMDIO _L_(21) /**< \brief GMAC signal: GMDIO on PA21 mux L */ +#define MUX_PA21L_GMAC_GMDIO _L_(11) +#define PINMUX_PA21L_GMAC_GMDIO ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO) +#define PORT_PA21L_GMAC_GMDIO (_UL_(1) << 21) +#define PIN_PB15L_GMAC_GMDIO _L_(47) /**< \brief GMAC signal: GMDIO on PB15 mux L */ +#define MUX_PB15L_GMAC_GMDIO _L_(11) +#define PINMUX_PB15L_GMAC_GMDIO ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO) +#define PORT_PB15L_GMAC_GMDIO (_UL_(1) << 15) +#define PIN_PC12L_GMAC_GMDIO _L_(76) /**< \brief GMAC signal: GMDIO on PC12 mux L */ +#define MUX_PC12L_GMAC_GMDIO _L_(11) +#define PINMUX_PC12L_GMAC_GMDIO ((PIN_PC12L_GMAC_GMDIO << 16) | MUX_PC12L_GMAC_GMDIO) +#define PORT_PC12L_GMAC_GMDIO (_UL_(1) << 12) +#define PIN_PA13L_GMAC_GRX0 _L_(13) /**< \brief GMAC signal: GRX0 on PA13 mux L */ +#define MUX_PA13L_GMAC_GRX0 _L_(11) +#define PINMUX_PA13L_GMAC_GRX0 ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0) +#define PORT_PA13L_GMAC_GRX0 (_UL_(1) << 13) +#define PIN_PA12L_GMAC_GRX1 _L_(12) /**< \brief GMAC signal: GRX1 on PA12 mux L */ +#define MUX_PA12L_GMAC_GRX1 _L_(11) +#define PINMUX_PA12L_GMAC_GRX1 ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1) +#define PORT_PA12L_GMAC_GRX1 (_UL_(1) << 12) +#define PIN_PC15L_GMAC_GRX2 _L_(79) /**< \brief GMAC signal: GRX2 on PC15 mux L */ +#define MUX_PC15L_GMAC_GRX2 _L_(11) +#define PINMUX_PC15L_GMAC_GRX2 ((PIN_PC15L_GMAC_GRX2 << 16) | MUX_PC15L_GMAC_GRX2) +#define PORT_PC15L_GMAC_GRX2 (_UL_(1) << 15) +#define PIN_PC14L_GMAC_GRX3 _L_(78) /**< \brief GMAC signal: GRX3 on PC14 mux L */ +#define MUX_PC14L_GMAC_GRX3 _L_(11) +#define PINMUX_PC14L_GMAC_GRX3 ((PIN_PC14L_GMAC_GRX3 << 16) | MUX_PC14L_GMAC_GRX3) +#define PORT_PC14L_GMAC_GRX3 (_UL_(1) << 14) +#define PIN_PC18L_GMAC_GRXCK _L_(82) /**< \brief GMAC signal: GRXCK on PC18 mux L */ +#define MUX_PC18L_GMAC_GRXCK _L_(11) +#define PINMUX_PC18L_GMAC_GRXCK ((PIN_PC18L_GMAC_GRXCK << 16) | MUX_PC18L_GMAC_GRXCK) +#define PORT_PC18L_GMAC_GRXCK (_UL_(1) << 18) +#define PIN_PC20L_GMAC_GRXDV _L_(84) /**< \brief GMAC signal: GRXDV on PC20 mux L */ +#define MUX_PC20L_GMAC_GRXDV _L_(11) +#define PINMUX_PC20L_GMAC_GRXDV ((PIN_PC20L_GMAC_GRXDV << 16) | MUX_PC20L_GMAC_GRXDV) +#define PORT_PC20L_GMAC_GRXDV (_UL_(1) << 20) +#define PIN_PA15L_GMAC_GRXER _L_(15) /**< \brief GMAC signal: GRXER on PA15 mux L */ +#define MUX_PA15L_GMAC_GRXER _L_(11) +#define PINMUX_PA15L_GMAC_GRXER ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER) +#define PORT_PA15L_GMAC_GRXER (_UL_(1) << 15) +#define PIN_PA18L_GMAC_GTX0 _L_(18) /**< \brief GMAC signal: GTX0 on PA18 mux L */ +#define MUX_PA18L_GMAC_GTX0 _L_(11) +#define PINMUX_PA18L_GMAC_GTX0 ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0) +#define PORT_PA18L_GMAC_GTX0 (_UL_(1) << 18) +#define PIN_PA19L_GMAC_GTX1 _L_(19) /**< \brief GMAC signal: GTX1 on PA19 mux L */ +#define MUX_PA19L_GMAC_GTX1 _L_(11) +#define PINMUX_PA19L_GMAC_GTX1 ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1) +#define PORT_PA19L_GMAC_GTX1 (_UL_(1) << 19) +#define PIN_PC16L_GMAC_GTX2 _L_(80) /**< \brief GMAC signal: GTX2 on PC16 mux L */ +#define MUX_PC16L_GMAC_GTX2 _L_(11) +#define PINMUX_PC16L_GMAC_GTX2 ((PIN_PC16L_GMAC_GTX2 << 16) | MUX_PC16L_GMAC_GTX2) +#define PORT_PC16L_GMAC_GTX2 (_UL_(1) << 16) +#define PIN_PC17L_GMAC_GTX3 _L_(81) /**< \brief GMAC signal: GTX3 on PC17 mux L */ +#define MUX_PC17L_GMAC_GTX3 _L_(11) +#define PINMUX_PC17L_GMAC_GTX3 ((PIN_PC17L_GMAC_GTX3 << 16) | MUX_PC17L_GMAC_GTX3) +#define PORT_PC17L_GMAC_GTX3 (_UL_(1) << 17) +#define PIN_PA14L_GMAC_GTXCK _L_(14) /**< \brief GMAC signal: GTXCK on PA14 mux L */ +#define MUX_PA14L_GMAC_GTXCK _L_(11) +#define PINMUX_PA14L_GMAC_GTXCK ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK) +#define PORT_PA14L_GMAC_GTXCK (_UL_(1) << 14) +#define PIN_PA17L_GMAC_GTXEN _L_(17) /**< \brief GMAC signal: GTXEN on PA17 mux L */ +#define MUX_PA17L_GMAC_GTXEN _L_(11) +#define PINMUX_PA17L_GMAC_GTXEN ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN) +#define PORT_PA17L_GMAC_GTXEN (_UL_(1) << 17) +#define PIN_PC19L_GMAC_GTXER _L_(83) /**< \brief GMAC signal: GTXER on PC19 mux L */ +#define MUX_PC19L_GMAC_GTXER _L_(11) +#define PINMUX_PC19L_GMAC_GTXER ((PIN_PC19L_GMAC_GTXER << 16) | MUX_PC19L_GMAC_GTXER) +#define PORT_PC19L_GMAC_GTXER (_UL_(1) << 19) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ +#define MUX_PA14F_TCC2_WO0 _L_(5) +#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) +#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) +#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ +#define MUX_PA30F_TCC2_WO0 _L_(5) +#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) +#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) +#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ +#define MUX_PA15F_TCC2_WO1 _L_(5) +#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) +#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) +#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ +#define MUX_PA31F_TCC2_WO1 _L_(5) +#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) +#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) +#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC2_WO2 _L_(5) +#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) +#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) +#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ +#define MUX_PB02F_TCC2_WO2 _L_(5) +#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) +#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) +/* ========== PORT definition for TCC3 peripheral ========== */ +#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ +#define MUX_PB12F_TCC3_WO0 _L_(5) +#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) +#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) +#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ +#define MUX_PB16F_TCC3_WO0 _L_(5) +#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) +#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) +#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ +#define MUX_PB13F_TCC3_WO1 _L_(5) +#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) +#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) +#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ +#define MUX_PB17F_TCC3_WO1 _L_(5) +#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) +#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC4_WO0 _L_(4) +#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) +#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) +#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC4_WO0 _L_(4) +#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) +#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) +#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC4_WO0 _L_(4) +#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) +#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) +#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC4_WO1 _L_(4) +#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) +#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) +#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC4_WO1 _L_(4) +#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) +#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) +#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC4_WO1 _L_(4) +#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) +#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) +/* ========== PORT definition for TC5 peripheral ========== */ +#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC5_WO0 _L_(4) +#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) +#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) +#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ +#define MUX_PB10E_TC5_WO0 _L_(4) +#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) +#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) +#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC5_WO0 _L_(4) +#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) +#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) +#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC5_WO1 _L_(4) +#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) +#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) +#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC5_WO1 _L_(4) +#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) +#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) +#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC5_WO1 _L_(4) +#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) +#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) +/* ========== PORT definition for PDEC peripheral ========== */ +#define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */ +#define MUX_PB18G_PDEC_QDI0 _L_(6) +#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) +#define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18) +#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ +#define MUX_PB23G_PDEC_QDI0 _L_(6) +#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) +#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) +#define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */ +#define MUX_PC16G_PDEC_QDI0 _L_(6) +#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) +#define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16) +#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ +#define MUX_PA24G_PDEC_QDI0 _L_(6) +#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) +#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) +#define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */ +#define MUX_PB19G_PDEC_QDI1 _L_(6) +#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) +#define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19) +#define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */ +#define MUX_PB24G_PDEC_QDI1 _L_(6) +#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) +#define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24) +#define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */ +#define MUX_PC17G_PDEC_QDI1 _L_(6) +#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) +#define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17) +#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ +#define MUX_PA25G_PDEC_QDI1 _L_(6) +#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) +#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) +#define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */ +#define MUX_PB20G_PDEC_QDI2 _L_(6) +#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) +#define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20) +#define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */ +#define MUX_PB25G_PDEC_QDI2 _L_(6) +#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) +#define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25) +#define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */ +#define MUX_PC18G_PDEC_QDI2 _L_(6) +#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) +#define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18) +#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ +#define MUX_PB22G_PDEC_QDI2 _L_(6) +#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) +#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 _L_(1) +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) +#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 _L_(1) +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) +#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 _L_(1) +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) +#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 _L_(1) +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) +#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ +#define MUX_PA12M_AC_CMP0 _L_(12) +#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) +#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ +#define MUX_PA18M_AC_CMP0 _L_(12) +#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) +#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) +#define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */ +#define MUX_PB24M_AC_CMP0 _L_(12) +#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) +#define PORT_PB24M_AC_CMP0 (_UL_(1) << 24) +#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ +#define MUX_PA13M_AC_CMP1 _L_(12) +#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) +#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ +#define MUX_PA19M_AC_CMP1 _L_(12) +#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) +#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) +#define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */ +#define MUX_PB25M_AC_CMP1 _L_(12) +#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) +#define PORT_PB25M_AC_CMP1 (_UL_(1) << 25) +/* ========== PORT definition for QSPI peripheral ========== */ +#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ +#define MUX_PB11H_QSPI_CS _L_(7) +#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) +#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) +#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ +#define MUX_PA08H_QSPI_DATA0 _L_(7) +#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) +#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) +#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ +#define MUX_PA09H_QSPI_DATA1 _L_(7) +#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) +#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) +#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ +#define MUX_PA10H_QSPI_DATA2 _L_(7) +#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) +#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) +#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ +#define MUX_PA11H_QSPI_DATA3 _L_(7) +#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) +#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) +#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ +#define MUX_PB10H_QSPI_SCK _L_(7) +#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) +#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ +#define MUX_PA04N_CCL_IN0 _L_(13) +#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) +#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ +#define MUX_PA16N_CCL_IN0 _L_(13) +#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) +#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ +#define MUX_PB22N_CCL_IN0 _L_(13) +#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) +#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ +#define MUX_PA05N_CCL_IN1 _L_(13) +#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) +#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ +#define MUX_PA17N_CCL_IN1 _L_(13) +#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) +#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) +#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ +#define MUX_PB00N_CCL_IN1 _L_(13) +#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) +#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) +#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ +#define MUX_PA06N_CCL_IN2 _L_(13) +#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) +#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ +#define MUX_PA18N_CCL_IN2 _L_(13) +#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) +#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) +#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ +#define MUX_PB01N_CCL_IN2 _L_(13) +#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) +#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) +#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ +#define MUX_PA08N_CCL_IN3 _L_(13) +#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) +#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ +#define MUX_PA30N_CCL_IN3 _L_(13) +#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) +#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ +#define MUX_PA09N_CCL_IN4 _L_(13) +#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) +#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) +#define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */ +#define MUX_PC27N_CCL_IN4 _L_(13) +#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) +#define PORT_PC27N_CCL_IN4 (_UL_(1) << 27) +#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ +#define MUX_PA10N_CCL_IN5 _L_(13) +#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) +#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) +#define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */ +#define MUX_PC28N_CCL_IN5 _L_(13) +#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) +#define PORT_PC28N_CCL_IN5 (_UL_(1) << 28) +#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ +#define MUX_PA22N_CCL_IN6 _L_(13) +#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) +#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) +#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ +#define MUX_PB06N_CCL_IN6 _L_(13) +#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) +#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) +#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ +#define MUX_PA23N_CCL_IN7 _L_(13) +#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) +#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) +#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ +#define MUX_PB07N_CCL_IN7 _L_(13) +#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) +#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) +#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ +#define MUX_PA24N_CCL_IN8 _L_(13) +#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) +#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ +#define MUX_PB08N_CCL_IN8 _L_(13) +#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) +#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) +#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ +#define MUX_PB14N_CCL_IN9 _L_(13) +#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) +#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) +#define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */ +#define MUX_PC20N_CCL_IN9 _L_(13) +#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) +#define PORT_PC20N_CCL_IN9 (_UL_(1) << 20) +#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ +#define MUX_PB15N_CCL_IN10 _L_(13) +#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) +#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) +#define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */ +#define MUX_PC21N_CCL_IN10 _L_(13) +#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) +#define PORT_PC21N_CCL_IN10 (_UL_(1) << 21) +#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ +#define MUX_PB10N_CCL_IN11 _L_(13) +#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) +#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) +#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ +#define MUX_PB16N_CCL_IN11 _L_(13) +#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) +#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) +#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ +#define MUX_PA07N_CCL_OUT0 _L_(13) +#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) +#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ +#define MUX_PA19N_CCL_OUT0 _L_(13) +#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) +#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ +#define MUX_PB02N_CCL_OUT0 _L_(13) +#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) +#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ +#define MUX_PB23N_CCL_OUT0 _L_(13) +#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) +#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ +#define MUX_PA11N_CCL_OUT1 _L_(13) +#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) +#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ +#define MUX_PA31N_CCL_OUT1 _L_(13) +#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) +#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ +#define MUX_PB11N_CCL_OUT1 _L_(13) +#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) +#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ +#define MUX_PA25N_CCL_OUT2 _L_(13) +#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) +#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ +#define MUX_PB09N_CCL_OUT2 _L_(13) +#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) +#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) +#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ +#define MUX_PB17N_CCL_OUT3 _L_(13) +#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) +#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) +#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) +#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) +#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM4_PAD0 _L_(2) +#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) +#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) +#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) +#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) +#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) +#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM4_PAD1 _L_(2) +#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) +#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) +#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) +#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM4_PAD2 _L_(2) +#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) +#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) +#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) +#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM4_PAD3 _L_(2) +#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) +#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) +#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) +#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) +#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) +#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) +#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 _L_(2) +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) +#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) +#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) +#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) +#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) +#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) +#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 _L_(2) +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) +#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) +#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) +#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) +#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) +#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ +#define MUX_PB18C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) +#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) +#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) +#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ +#define MUX_PB01D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) +#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) +#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) +#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ +#define MUX_PB19C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) +#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM6 peripheral ========== */ +#define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */ +#define MUX_PC13D_SERCOM6_PAD0 _L_(3) +#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) +#define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13) +#define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */ +#define MUX_PC16C_SERCOM6_PAD0 _L_(2) +#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) +#define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16) +#define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */ +#define MUX_PC12D_SERCOM6_PAD1 _L_(3) +#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) +#define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12) +#define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */ +#define MUX_PC05C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) +#define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5) +#define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */ +#define MUX_PC17C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) +#define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17) +#define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */ +#define MUX_PC14D_SERCOM6_PAD2 _L_(3) +#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) +#define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14) +#define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */ +#define MUX_PC06C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) +#define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6) +#define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */ +#define MUX_PC10C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) +#define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10) +#define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */ +#define MUX_PC18C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) +#define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18) +#define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */ +#define MUX_PC15D_SERCOM6_PAD3 _L_(3) +#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) +#define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15) +#define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */ +#define MUX_PC07C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) +#define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7) +#define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */ +#define MUX_PC11C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) +#define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11) +#define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */ +#define MUX_PC19C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) +#define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM7 peripheral ========== */ +#define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */ +#define MUX_PB21D_SERCOM7_PAD0 _L_(3) +#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) +#define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21) +#define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */ +#define MUX_PB30C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) +#define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30) +#define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */ +#define MUX_PC12C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) +#define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12) +#define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */ +#define MUX_PB20D_SERCOM7_PAD1 _L_(3) +#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) +#define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20) +#define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */ +#define MUX_PB31C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) +#define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31) +#define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */ +#define MUX_PC13C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) +#define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13) +#define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */ +#define MUX_PB18D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) +#define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18) +#define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */ +#define MUX_PC10D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) +#define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10) +#define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */ +#define MUX_PC14C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) +#define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14) +#define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */ +#define MUX_PA30C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) +#define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30) +#define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */ +#define MUX_PB19D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) +#define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19) +#define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */ +#define MUX_PC11D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) +#define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11) +#define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */ +#define MUX_PC15C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) +#define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15) +#define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */ +#define MUX_PA31C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) +#define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31) +/* ========== PORT definition for TCC4 peripheral ========== */ +#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ +#define MUX_PB14F_TCC4_WO0 _L_(5) +#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) +#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) +#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ +#define MUX_PB30F_TCC4_WO0 _L_(5) +#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) +#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) +#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ +#define MUX_PB15F_TCC4_WO1 _L_(5) +#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) +#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) +#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ +#define MUX_PB31F_TCC4_WO1 _L_(5) +#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) +#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC6 peripheral ========== */ +#define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */ +#define MUX_PA30E_TC6_WO0 _L_(4) +#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) +#define PORT_PA30E_TC6_WO0 (_UL_(1) << 30) +#define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC6_WO0 _L_(4) +#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) +#define PORT_PB02E_TC6_WO0 (_UL_(1) << 2) +#define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */ +#define MUX_PB16E_TC6_WO0 _L_(4) +#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) +#define PORT_PB16E_TC6_WO0 (_UL_(1) << 16) +#define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */ +#define MUX_PA31E_TC6_WO1 _L_(4) +#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) +#define PORT_PA31E_TC6_WO1 (_UL_(1) << 31) +#define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC6_WO1 _L_(4) +#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) +#define PORT_PB03E_TC6_WO1 (_UL_(1) << 3) +#define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */ +#define MUX_PB17E_TC6_WO1 _L_(4) +#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) +#define PORT_PB17E_TC6_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC7 peripheral ========== */ +#define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC7_WO0 _L_(4) +#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) +#define PORT_PA20E_TC7_WO0 (_UL_(1) << 20) +#define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */ +#define MUX_PB00E_TC7_WO0 _L_(4) +#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) +#define PORT_PB00E_TC7_WO0 (_UL_(1) << 0) +#define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC7_WO0 _L_(4) +#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) +#define PORT_PB22E_TC7_WO0 (_UL_(1) << 22) +#define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC7_WO1 _L_(4) +#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) +#define PORT_PA21E_TC7_WO1 (_UL_(1) << 21) +#define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */ +#define MUX_PB01E_TC7_WO1 _L_(4) +#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) +#define PORT_PB01E_TC7_WO1 (_UL_(1) << 1) +#define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC7_WO1 _L_(4) +#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) +#define PORT_PB23E_TC7_WO1 (_UL_(1) << 23) +/* ========== PORT definition for ADC0 peripheral ========== */ +#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC0_AIN0 _L_(1) +#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) +#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC0_AIN1 _L_(1) +#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) +#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC0_AIN2 _L_(1) +#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) +#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC0_AIN3 _L_(1) +#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) +#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC0_AIN4 _L_(1) +#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) +#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC0_AIN5 _L_(1) +#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) +#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC0_AIN6 _L_(1) +#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) +#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC0_AIN7 _L_(1) +#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) +#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ +#define MUX_PA08B_ADC0_AIN8 _L_(1) +#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) +#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ +#define MUX_PA09B_ADC0_AIN9 _L_(1) +#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) +#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ +#define MUX_PA10B_ADC0_AIN10 _L_(1) +#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) +#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ +#define MUX_PA11B_ADC0_AIN11 _L_(1) +#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) +#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) +#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ +#define MUX_PB00B_ADC0_AIN12 _L_(1) +#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) +#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ +#define MUX_PB01B_ADC0_AIN13 _L_(1) +#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) +#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) +#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ +#define MUX_PB02B_ADC0_AIN14 _L_(1) +#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) +#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ +#define MUX_PB03B_ADC0_AIN15 _L_(1) +#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) +#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) +#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ +#define MUX_PA03O_ADC0_DRV0 _L_(14) +#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) +#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) +#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ +#define MUX_PB08O_ADC0_DRV1 _L_(14) +#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) +#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) +#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ +#define MUX_PB09O_ADC0_DRV2 _L_(14) +#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) +#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) +#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ +#define MUX_PA04O_ADC0_DRV3 _L_(14) +#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) +#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) +#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ +#define MUX_PA06O_ADC0_DRV4 _L_(14) +#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) +#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) +#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ +#define MUX_PA07O_ADC0_DRV5 _L_(14) +#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) +#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) +#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ +#define MUX_PA08O_ADC0_DRV6 _L_(14) +#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) +#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) +#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ +#define MUX_PA09O_ADC0_DRV7 _L_(14) +#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) +#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) +#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ +#define MUX_PA10O_ADC0_DRV8 _L_(14) +#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) +#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) +#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ +#define MUX_PA11O_ADC0_DRV9 _L_(14) +#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) +#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) +#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ +#define MUX_PA16O_ADC0_DRV10 _L_(14) +#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) +#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) +#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ +#define MUX_PA17O_ADC0_DRV11 _L_(14) +#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) +#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) +#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ +#define MUX_PA18O_ADC0_DRV12 _L_(14) +#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) +#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) +#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ +#define MUX_PA19O_ADC0_DRV13 _L_(14) +#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) +#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) +#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ +#define MUX_PA20O_ADC0_DRV14 _L_(14) +#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) +#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) +#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ +#define MUX_PA21O_ADC0_DRV15 _L_(14) +#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) +#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) +#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ +#define MUX_PA22O_ADC0_DRV16 _L_(14) +#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) +#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) +#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ +#define MUX_PA23O_ADC0_DRV17 _L_(14) +#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) +#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) +#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ +#define MUX_PA27O_ADC0_DRV18 _L_(14) +#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) +#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) +#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ +#define MUX_PA30O_ADC0_DRV19 _L_(14) +#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) +#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) +#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ +#define MUX_PB02O_ADC0_DRV20 _L_(14) +#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) +#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) +#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ +#define MUX_PB03O_ADC0_DRV21 _L_(14) +#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) +#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) +#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ +#define MUX_PB04O_ADC0_DRV22 _L_(14) +#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) +#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) +#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ +#define MUX_PB05O_ADC0_DRV23 _L_(14) +#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) +#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) +#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ +#define MUX_PB06O_ADC0_DRV24 _L_(14) +#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) +#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) +#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ +#define MUX_PB07O_ADC0_DRV25 _L_(14) +#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) +#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) +#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ +#define MUX_PB12O_ADC0_DRV26 _L_(14) +#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) +#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) +#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ +#define MUX_PB13O_ADC0_DRV27 _L_(14) +#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) +#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) +#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ +#define MUX_PB14O_ADC0_DRV28 _L_(14) +#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) +#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) +#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ +#define MUX_PB15O_ADC0_DRV29 _L_(14) +#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) +#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) +#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ +#define MUX_PB00O_ADC0_DRV30 _L_(14) +#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) +#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) +#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ +#define MUX_PB01O_ADC0_DRV31 _L_(14) +#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) +#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) +#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ +#define MUX_PA03B_ADC0_PTCXY0 _L_(1) +#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) +#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ +#define MUX_PB08B_ADC0_PTCXY1 _L_(1) +#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) +#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ +#define MUX_PB09B_ADC0_PTCXY2 _L_(1) +#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) +#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ +#define MUX_PA04B_ADC0_PTCXY3 _L_(1) +#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) +#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) +#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ +#define MUX_PA06B_ADC0_PTCXY4 _L_(1) +#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) +#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ +#define MUX_PA07B_ADC0_PTCXY5 _L_(1) +#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) +#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ +#define MUX_PA08B_ADC0_PTCXY6 _L_(1) +#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) +#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ +#define MUX_PA09B_ADC0_PTCXY7 _L_(1) +#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) +#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ +#define MUX_PA10B_ADC0_PTCXY8 _L_(1) +#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) +#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ +#define MUX_PA11B_ADC0_PTCXY9 _L_(1) +#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) +#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) +#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ +#define MUX_PA16B_ADC0_PTCXY10 _L_(1) +#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) +#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) +#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ +#define MUX_PA17B_ADC0_PTCXY11 _L_(1) +#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) +#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) +#define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */ +#define MUX_PA18B_ADC0_PTCXY12 _L_(1) +#define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12) +#define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18) +#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ +#define MUX_PA19B_ADC0_PTCXY13 _L_(1) +#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) +#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) +#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ +#define MUX_PA20B_ADC0_PTCXY14 _L_(1) +#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) +#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) +#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ +#define MUX_PA21B_ADC0_PTCXY15 _L_(1) +#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) +#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) +#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ +#define MUX_PA22B_ADC0_PTCXY16 _L_(1) +#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) +#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) +#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ +#define MUX_PA23B_ADC0_PTCXY17 _L_(1) +#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) +#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) +#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ +#define MUX_PA27B_ADC0_PTCXY18 _L_(1) +#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) +#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) +#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ +#define MUX_PA30B_ADC0_PTCXY19 _L_(1) +#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) +#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) +#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ +#define MUX_PB02B_ADC0_PTCXY20 _L_(1) +#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) +#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ +#define MUX_PB03B_ADC0_PTCXY21 _L_(1) +#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) +#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) +#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ +#define MUX_PB04B_ADC0_PTCXY22 _L_(1) +#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) +#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) +#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ +#define MUX_PB05B_ADC0_PTCXY23 _L_(1) +#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) +#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) +#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ +#define MUX_PB06B_ADC0_PTCXY24 _L_(1) +#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) +#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) +#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ +#define MUX_PB07B_ADC0_PTCXY25 _L_(1) +#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) +#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) +#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ +#define MUX_PB12B_ADC0_PTCXY26 _L_(1) +#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) +#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) +#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ +#define MUX_PB13B_ADC0_PTCXY27 _L_(1) +#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) +#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) +#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ +#define MUX_PB14B_ADC0_PTCXY28 _L_(1) +#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) +#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) +#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ +#define MUX_PB15B_ADC0_PTCXY29 _L_(1) +#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) +#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) +#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ +#define MUX_PB00B_ADC0_PTCXY30 _L_(1) +#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) +#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ +#define MUX_PB01B_ADC0_PTCXY31 _L_(1) +#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) +#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) +/* ========== PORT definition for ADC1 peripheral ========== */ +#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ +#define MUX_PB08B_ADC1_AIN0 _L_(1) +#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) +#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) +#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ +#define MUX_PB09B_ADC1_AIN1 _L_(1) +#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) +#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) +#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ +#define MUX_PA08B_ADC1_AIN2 _L_(1) +#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) +#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) +#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ +#define MUX_PA09B_ADC1_AIN3 _L_(1) +#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) +#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) +#define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */ +#define MUX_PC02B_ADC1_AIN4 _L_(1) +#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) +#define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2) +#define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */ +#define MUX_PC03B_ADC1_AIN5 _L_(1) +#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) +#define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3) +#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ +#define MUX_PB04B_ADC1_AIN6 _L_(1) +#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) +#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) +#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ +#define MUX_PB05B_ADC1_AIN7 _L_(1) +#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) +#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) +#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ +#define MUX_PB06B_ADC1_AIN8 _L_(1) +#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) +#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) +#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ +#define MUX_PB07B_ADC1_AIN9 _L_(1) +#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) +#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) +#define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */ +#define MUX_PC00B_ADC1_AIN10 _L_(1) +#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) +#define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0) +#define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */ +#define MUX_PC01B_ADC1_AIN11 _L_(1) +#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) +#define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 _L_(1) +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) +#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 _L_(1) +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) +/* ========== PORT definition for I2S peripheral ========== */ +#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ +#define MUX_PA09J_I2S_FS0 _L_(9) +#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) +#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) +#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ +#define MUX_PA20J_I2S_FS0 _L_(9) +#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) +#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) +#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ +#define MUX_PA23J_I2S_FS1 _L_(9) +#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) +#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) +#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ +#define MUX_PB11J_I2S_FS1 _L_(9) +#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) +#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) +#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ +#define MUX_PA08J_I2S_MCK0 _L_(9) +#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) +#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) +#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ +#define MUX_PB17J_I2S_MCK0 _L_(9) +#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) +#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) +#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ +#define MUX_PB13J_I2S_MCK1 _L_(9) +#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) +#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) +#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ +#define MUX_PA10J_I2S_SCK0 _L_(9) +#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) +#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) +#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ +#define MUX_PB16J_I2S_SCK0 _L_(9) +#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) +#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) +#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ +#define MUX_PB12J_I2S_SCK1 _L_(9) +#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) +#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) +#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ +#define MUX_PA22J_I2S_SDI _L_(9) +#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) +#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) +#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ +#define MUX_PB10J_I2S_SDI _L_(9) +#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) +#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) +#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ +#define MUX_PA11J_I2S_SDO _L_(9) +#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) +#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) +#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ +#define MUX_PA21J_I2S_SDO _L_(9) +#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) +#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) +/* ========== PORT definition for PCC peripheral ========== */ +#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ +#define MUX_PA14K_PCC_CLK _L_(10) +#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) +#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) +#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ +#define MUX_PA16K_PCC_DATA0 _L_(10) +#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) +#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) +#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ +#define MUX_PA17K_PCC_DATA1 _L_(10) +#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) +#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) +#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ +#define MUX_PA18K_PCC_DATA2 _L_(10) +#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) +#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) +#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ +#define MUX_PA19K_PCC_DATA3 _L_(10) +#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) +#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) +#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ +#define MUX_PA20K_PCC_DATA4 _L_(10) +#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) +#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) +#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ +#define MUX_PA21K_PCC_DATA5 _L_(10) +#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) +#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) +#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ +#define MUX_PA22K_PCC_DATA6 _L_(10) +#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) +#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) +#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ +#define MUX_PA23K_PCC_DATA7 _L_(10) +#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) +#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) +#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ +#define MUX_PB14K_PCC_DATA8 _L_(10) +#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) +#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) +#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ +#define MUX_PB15K_PCC_DATA9 _L_(10) +#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) +#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) +#define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */ +#define MUX_PC12K_PCC_DATA10 _L_(10) +#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) +#define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12) +#define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */ +#define MUX_PC13K_PCC_DATA11 _L_(10) +#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) +#define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13) +#define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */ +#define MUX_PC14K_PCC_DATA12 _L_(10) +#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) +#define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14) +#define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */ +#define MUX_PC15K_PCC_DATA13 _L_(10) +#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) +#define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15) +#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ +#define MUX_PA12K_PCC_DEN1 _L_(10) +#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) +#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) +#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ +#define MUX_PA13K_PCC_DEN2 _L_(10) +#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) +#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) +/* ========== PORT definition for SDHC0 peripheral ========== */ +#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ +#define MUX_PA06I_SDHC0_SDCD _L_(8) +#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) +#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ +#define MUX_PA12I_SDHC0_SDCD _L_(8) +#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) +#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ +#define MUX_PB12I_SDHC0_SDCD _L_(8) +#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) +#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */ +#define MUX_PC06I_SDHC0_SDCD _L_(8) +#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) +#define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ +#define MUX_PB11I_SDHC0_SDCK _L_(8) +#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) +#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) +#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ +#define MUX_PA08I_SDHC0_SDCMD _L_(8) +#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) +#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) +#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ +#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) +#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) +#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) +#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ +#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) +#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) +#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) +#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ +#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) +#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) +#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) +#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ +#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) +#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) +#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) +#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ +#define MUX_PA07I_SDHC0_SDWP _L_(8) +#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) +#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) +#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ +#define MUX_PA13I_SDHC0_SDWP _L_(8) +#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) +#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ +#define MUX_PB13I_SDHC0_SDWP _L_(8) +#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) +#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */ +#define MUX_PC07I_SDHC0_SDWP _L_(8) +#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) +#define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7) +/* ========== PORT definition for SDHC1 peripheral ========== */ +#define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */ +#define MUX_PB16I_SDHC1_SDCD _L_(8) +#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) +#define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16) +#define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */ +#define MUX_PC20I_SDHC1_SDCD _L_(8) +#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) +#define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20) +#define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */ +#define MUX_PA21I_SDHC1_SDCK _L_(8) +#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) +#define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21) +#define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */ +#define MUX_PA20I_SDHC1_SDCMD _L_(8) +#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) +#define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20) +#define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */ +#define MUX_PB18I_SDHC1_SDDAT0 _L_(8) +#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) +#define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18) +#define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */ +#define MUX_PB19I_SDHC1_SDDAT1 _L_(8) +#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) +#define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19) +#define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */ +#define MUX_PB20I_SDHC1_SDDAT2 _L_(8) +#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) +#define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20) +#define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */ +#define MUX_PB21I_SDHC1_SDDAT3 _L_(8) +#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) +#define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21) +#define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */ +#define MUX_PB17I_SDHC1_SDWP _L_(8) +#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) +#define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17) +#define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */ +#define MUX_PC21I_SDHC1_SDWP _L_(8) +#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) +#define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21) + +#endif /* _SAME54N20A_PIO_ */ diff --git a/software/firmware/oracle_same54n19a/include/pio/same54p19a.h b/software/firmware/oracle_same54n19a/include/pio/same54p19a.h new file mode 100644 index 00000000..93afbcc8 --- /dev/null +++ b/software/firmware/oracle_same54n19a/include/pio/same54p19a.h @@ -0,0 +1,3010 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAME54P19A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54P19A_PIO_ +#define _SAME54P19A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ +#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ +#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ +#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ +#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ +#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ +#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ +#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ +#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ +#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ +#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ +#define PIN_PB26 58 /**< \brief Pin Number for PB26 */ +#define PORT_PB26 (_UL_(1) << 26) /**< \brief PORT Mask for PB26 */ +#define PIN_PB27 59 /**< \brief Pin Number for PB27 */ +#define PORT_PB27 (_UL_(1) << 27) /**< \brief PORT Mask for PB27 */ +#define PIN_PB28 60 /**< \brief Pin Number for PB28 */ +#define PORT_PB28 (_UL_(1) << 28) /**< \brief PORT Mask for PB28 */ +#define PIN_PB29 61 /**< \brief Pin Number for PB29 */ +#define PORT_PB29 (_UL_(1) << 29) /**< \brief PORT Mask for PB29 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ +#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ +#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ +#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ +#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ +#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ +#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ +#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ +#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ +#define PIN_PC04 68 /**< \brief Pin Number for PC04 */ +#define PORT_PC04 (_UL_(1) << 4) /**< \brief PORT Mask for PC04 */ +#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ +#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ +#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ +#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ +#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ +#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ +#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ +#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ +#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ +#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ +#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ +#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ +#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ +#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ +#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ +#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ +#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ +#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ +#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ +#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ +#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ +#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ +#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ +#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ +#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ +#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ +#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ +#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ +#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ +#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ +#define PIN_PC22 86 /**< \brief Pin Number for PC22 */ +#define PORT_PC22 (_UL_(1) << 22) /**< \brief PORT Mask for PC22 */ +#define PIN_PC23 87 /**< \brief Pin Number for PC23 */ +#define PORT_PC23 (_UL_(1) << 23) /**< \brief PORT Mask for PC23 */ +#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ +#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ +#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ +#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ +#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ +#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ +#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ +#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ +#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ +#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ +#define PIN_PC30 94 /**< \brief Pin Number for PC30 */ +#define PORT_PC30 (_UL_(1) << 30) /**< \brief PORT Mask for PC30 */ +#define PIN_PC31 95 /**< \brief Pin Number for PC31 */ +#define PORT_PC31 (_UL_(1) << 31) /**< \brief PORT Mask for PC31 */ +#define PIN_PD00 96 /**< \brief Pin Number for PD00 */ +#define PORT_PD00 (_UL_(1) << 0) /**< \brief PORT Mask for PD00 */ +#define PIN_PD01 97 /**< \brief Pin Number for PD01 */ +#define PORT_PD01 (_UL_(1) << 1) /**< \brief PORT Mask for PD01 */ +#define PIN_PD08 104 /**< \brief Pin Number for PD08 */ +#define PORT_PD08 (_UL_(1) << 8) /**< \brief PORT Mask for PD08 */ +#define PIN_PD09 105 /**< \brief Pin Number for PD09 */ +#define PORT_PD09 (_UL_(1) << 9) /**< \brief PORT Mask for PD09 */ +#define PIN_PD10 106 /**< \brief Pin Number for PD10 */ +#define PORT_PD10 (_UL_(1) << 10) /**< \brief PORT Mask for PD10 */ +#define PIN_PD11 107 /**< \brief Pin Number for PD11 */ +#define PORT_PD11 (_UL_(1) << 11) /**< \brief PORT Mask for PD11 */ +#define PIN_PD12 108 /**< \brief Pin Number for PD12 */ +#define PORT_PD12 (_UL_(1) << 12) /**< \brief PORT Mask for PD12 */ +#define PIN_PD20 116 /**< \brief Pin Number for PD20 */ +#define PORT_PD20 (_UL_(1) << 20) /**< \brief PORT Mask for PD20 */ +#define PIN_PD21 117 /**< \brief Pin Number for PD21 */ +#define PORT_PD21 (_UL_(1) << 21) /**< \brief PORT Mask for PD21 */ +/* ========== PORT definition for CM4 peripheral ========== */ +#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ +#define MUX_PA30H_CM4_SWCLK _L_(7) +#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) +#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) +#define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */ +#define MUX_PC27M_CM4_SWO _L_(12) +#define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO) +#define PORT_PC27M_CM4_SWO (_UL_(1) << 27) +#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ +#define MUX_PB30H_CM4_SWO _L_(7) +#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) +#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) +#define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */ +#define MUX_PC27H_CM4_TRACECLK _L_(7) +#define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK) +#define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27) +#define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */ +#define MUX_PC28H_CM4_TRACEDATA0 _L_(7) +#define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0) +#define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28) +#define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */ +#define MUX_PC26H_CM4_TRACEDATA1 _L_(7) +#define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1) +#define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26) +#define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */ +#define MUX_PC25H_CM4_TRACEDATA2 _L_(7) +#define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2) +#define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25) +#define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */ +#define MUX_PC24H_CM4_TRACEDATA3 _L_(7) +#define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3) +#define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24) +/* ========== PORT definition for ANAREF peripheral ========== */ +#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ +#define MUX_PA03B_ANAREF_VREF0 _L_(1) +#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) +#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) +#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ +#define MUX_PA04B_ANAREF_VREF1 _L_(1) +#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) +#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) +#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ +#define MUX_PA06B_ANAREF_VREF2 _L_(1) +#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) +#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ +#define MUX_PA30M_GCLK_IO0 _L_(12) +#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) +#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ +#define MUX_PB14M_GCLK_IO0 _L_(12) +#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) +#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ +#define MUX_PA14M_GCLK_IO0 _L_(12) +#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) +#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ +#define MUX_PB22M_GCLK_IO0 _L_(12) +#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) +#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ +#define MUX_PB15M_GCLK_IO1 _L_(12) +#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) +#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ +#define MUX_PA15M_GCLK_IO1 _L_(12) +#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) +#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ +#define MUX_PB23M_GCLK_IO1 _L_(12) +#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) +#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ +#define MUX_PA27M_GCLK_IO1 _L_(12) +#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) +#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) +#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ +#define MUX_PA16M_GCLK_IO2 _L_(12) +#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) +#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ +#define MUX_PB16M_GCLK_IO2 _L_(12) +#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) +#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ +#define MUX_PA17M_GCLK_IO3 _L_(12) +#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) +#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ +#define MUX_PB17M_GCLK_IO3 _L_(12) +#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) +#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ +#define MUX_PA10M_GCLK_IO4 _L_(12) +#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) +#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ +#define MUX_PB10M_GCLK_IO4 _L_(12) +#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) +#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */ +#define MUX_PB18M_GCLK_IO4 _L_(12) +#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) +#define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18) +#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ +#define MUX_PA11M_GCLK_IO5 _L_(12) +#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) +#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ +#define MUX_PB11M_GCLK_IO5 _L_(12) +#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) +#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */ +#define MUX_PB19M_GCLK_IO5 _L_(12) +#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) +#define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19) +#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ +#define MUX_PB12M_GCLK_IO6 _L_(12) +#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) +#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) +#define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */ +#define MUX_PB20M_GCLK_IO6 _L_(12) +#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) +#define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20) +#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ +#define MUX_PB13M_GCLK_IO7 _L_(12) +#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) +#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) +#define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */ +#define MUX_PB21M_GCLK_IO7 _L_(12) +#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) +#define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ +#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ +#define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */ +#define MUX_PC00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) +#define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ +#define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */ +#define MUX_PC16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) +#define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ +#define PIN_PD00A_EIC_EXTINT0 _L_(96) /**< \brief EIC signal: EXTINT0 on PD00 mux A */ +#define MUX_PD00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PD00A_EIC_EXTINT0 ((PIN_PD00A_EIC_EXTINT0 << 16) | MUX_PD00A_EIC_EXTINT0) +#define PORT_PD00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PD00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PD00 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ +#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ +#define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */ +#define MUX_PC01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) +#define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ +#define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */ +#define MUX_PC17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) +#define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ +#define PIN_PD01A_EIC_EXTINT1 _L_(97) /**< \brief EIC signal: EXTINT1 on PD01 mux A */ +#define MUX_PD01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PD01A_EIC_EXTINT1 ((PIN_PD01A_EIC_EXTINT1 << 16) | MUX_PD01A_EIC_EXTINT1) +#define PORT_PD01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PD01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PD01 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ +#define MUX_PB18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) +#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ +#define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */ +#define MUX_PC02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) +#define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ +#define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */ +#define MUX_PC18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) +#define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ +#define MUX_PB19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) +#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ +#define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */ +#define MUX_PC03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) +#define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ +#define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */ +#define MUX_PC19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) +#define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ +#define PIN_PD08A_EIC_EXTINT3 _L_(104) /**< \brief EIC signal: EXTINT3 on PD08 mux A */ +#define MUX_PD08A_EIC_EXTINT3 _L_(0) +#define PINMUX_PD08A_EIC_EXTINT3 ((PIN_PD08A_EIC_EXTINT3 << 16) | MUX_PD08A_EIC_EXTINT3) +#define PORT_PD08A_EIC_EXTINT3 (_UL_(1) << 8) +#define PIN_PD08A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PD08 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ +#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ +#define MUX_PB20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) +#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ +#define PIN_PC04A_EIC_EXTINT4 _L_(68) /**< \brief EIC signal: EXTINT4 on PC04 mux A */ +#define MUX_PC04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PC04A_EIC_EXTINT4 ((PIN_PC04A_EIC_EXTINT4 << 16) | MUX_PC04A_EIC_EXTINT4) +#define PORT_PC04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PC04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC04 External Interrupt Line */ +#define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */ +#define MUX_PC20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) +#define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ +#define PIN_PD09A_EIC_EXTINT4 _L_(105) /**< \brief EIC signal: EXTINT4 on PD09 mux A */ +#define MUX_PD09A_EIC_EXTINT4 _L_(0) +#define PINMUX_PD09A_EIC_EXTINT4 ((PIN_PD09A_EIC_EXTINT4 << 16) | MUX_PD09A_EIC_EXTINT4) +#define PORT_PD09A_EIC_EXTINT4 (_UL_(1) << 9) +#define PIN_PD09A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PD09 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ +#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ +#define MUX_PB21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) +#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ +#define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */ +#define MUX_PC05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) +#define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ +#define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */ +#define MUX_PC21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) +#define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ +#define PIN_PD10A_EIC_EXTINT5 _L_(106) /**< \brief EIC signal: EXTINT5 on PD10 mux A */ +#define MUX_PD10A_EIC_EXTINT5 _L_(0) +#define PINMUX_PD10A_EIC_EXTINT5 ((PIN_PD10A_EIC_EXTINT5 << 16) | MUX_PD10A_EIC_EXTINT5) +#define PORT_PD10A_EIC_EXTINT5 (_UL_(1) << 10) +#define PIN_PD10A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PD10 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */ +#define MUX_PC06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) +#define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ +#define PIN_PC22A_EIC_EXTINT6 _L_(86) /**< \brief EIC signal: EXTINT6 on PC22 mux A */ +#define MUX_PC22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PC22A_EIC_EXTINT6 ((PIN_PC22A_EIC_EXTINT6 << 16) | MUX_PC22A_EIC_EXTINT6) +#define PORT_PC22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PC22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC22 External Interrupt Line */ +#define PIN_PD11A_EIC_EXTINT6 _L_(107) /**< \brief EIC signal: EXTINT6 on PD11 mux A */ +#define MUX_PD11A_EIC_EXTINT6 _L_(0) +#define PINMUX_PD11A_EIC_EXTINT6 ((PIN_PD11A_EIC_EXTINT6 << 16) | MUX_PD11A_EIC_EXTINT6) +#define PORT_PD11A_EIC_EXTINT6 (_UL_(1) << 11) +#define PIN_PD11A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PD11 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PC23A_EIC_EXTINT7 _L_(87) /**< \brief EIC signal: EXTINT7 on PC23 mux A */ +#define MUX_PC23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PC23A_EIC_EXTINT7 ((PIN_PC23A_EIC_EXTINT7 << 16) | MUX_PC23A_EIC_EXTINT7) +#define PORT_PC23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PC23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PC23 External Interrupt Line */ +#define PIN_PD12A_EIC_EXTINT7 _L_(108) /**< \brief EIC signal: EXTINT7 on PD12 mux A */ +#define MUX_PD12A_EIC_EXTINT7 _L_(0) +#define PINMUX_PD12A_EIC_EXTINT7 ((PIN_PD12A_EIC_EXTINT7 << 16) | MUX_PD12A_EIC_EXTINT7) +#define PORT_PD12A_EIC_EXTINT7 (_UL_(1) << 12) +#define PIN_PD12A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PD12 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) +#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ +#define MUX_PB24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) +#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ +#define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */ +#define MUX_PC24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) +#define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) +#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ +#define MUX_PB25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) +#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ +#define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */ +#define MUX_PC07A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) +#define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7) +#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ +#define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */ +#define MUX_PC25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) +#define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ +#define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */ +#define MUX_PC10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) +#define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ +#define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */ +#define MUX_PC26A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) +#define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26) +#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ +#define PIN_PD20A_EIC_EXTINT10 _L_(116) /**< \brief EIC signal: EXTINT10 on PD20 mux A */ +#define MUX_PD20A_EIC_EXTINT10 _L_(0) +#define PINMUX_PD20A_EIC_EXTINT10 ((PIN_PD20A_EIC_EXTINT10 << 16) | MUX_PD20A_EIC_EXTINT10) +#define PORT_PD20A_EIC_EXTINT10 (_UL_(1) << 20) +#define PIN_PD20A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PD20 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) +#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */ +#define MUX_PC11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) +#define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ +#define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */ +#define MUX_PC27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) +#define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ +#define PIN_PD21A_EIC_EXTINT11 _L_(117) /**< \brief EIC signal: EXTINT11 on PD21 mux A */ +#define MUX_PD21A_EIC_EXTINT11 _L_(0) +#define PINMUX_PD21A_EIC_EXTINT11 ((PIN_PD21A_EIC_EXTINT11 << 16) | MUX_PD21A_EIC_EXTINT11) +#define PORT_PD21A_EIC_EXTINT11 (_UL_(1) << 21) +#define PIN_PD21A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PD21 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ +#define PIN_PB26A_EIC_EXTINT12 _L_(58) /**< \brief EIC signal: EXTINT12 on PB26 mux A */ +#define MUX_PB26A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB26A_EIC_EXTINT12 ((PIN_PB26A_EIC_EXTINT12 << 16) | MUX_PB26A_EIC_EXTINT12) +#define PORT_PB26A_EIC_EXTINT12 (_UL_(1) << 26) +#define PIN_PB26A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB26 External Interrupt Line */ +#define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */ +#define MUX_PC12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) +#define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ +#define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */ +#define MUX_PC28A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) +#define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28) +#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ +#define PIN_PB27A_EIC_EXTINT13 _L_(59) /**< \brief EIC signal: EXTINT13 on PB27 mux A */ +#define MUX_PB27A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB27A_EIC_EXTINT13 ((PIN_PB27A_EIC_EXTINT13 << 16) | MUX_PB27A_EIC_EXTINT13) +#define PORT_PB27A_EIC_EXTINT13 (_UL_(1) << 27) +#define PIN_PB27A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB27 External Interrupt Line */ +#define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */ +#define MUX_PC13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) +#define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) +#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ +#define PIN_PB28A_EIC_EXTINT14 _L_(60) /**< \brief EIC signal: EXTINT14 on PB28 mux A */ +#define MUX_PB28A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB28A_EIC_EXTINT14 ((PIN_PB28A_EIC_EXTINT14 << 16) | MUX_PB28A_EIC_EXTINT14) +#define PORT_PB28A_EIC_EXTINT14 (_UL_(1) << 28) +#define PIN_PB28A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB28 External Interrupt Line */ +#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ +#define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */ +#define MUX_PC14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) +#define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ +#define PIN_PC30A_EIC_EXTINT14 _L_(94) /**< \brief EIC signal: EXTINT14 on PC30 mux A */ +#define MUX_PC30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PC30A_EIC_EXTINT14 ((PIN_PC30A_EIC_EXTINT14 << 16) | MUX_PC30A_EIC_EXTINT14) +#define PORT_PC30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PC30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC30 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) +#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ +#define PIN_PB29A_EIC_EXTINT15 _L_(61) /**< \brief EIC signal: EXTINT15 on PB29 mux A */ +#define MUX_PB29A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB29A_EIC_EXTINT15 ((PIN_PB29A_EIC_EXTINT15 << 16) | MUX_PB29A_EIC_EXTINT15) +#define PORT_PB29A_EIC_EXTINT15 (_UL_(1) << 29) +#define PIN_PB29A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB29 External Interrupt Line */ +#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ +#define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */ +#define MUX_PC15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) +#define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ +#define PIN_PC31A_EIC_EXTINT15 _L_(95) /**< \brief EIC signal: EXTINT15 on PC31 mux A */ +#define MUX_PC31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PC31A_EIC_EXTINT15 ((PIN_PC31A_EIC_EXTINT15 << 16) | MUX_PC31A_EIC_EXTINT15) +#define PORT_PC31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PC31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC31 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */ +#define MUX_PC17D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) +#define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ +#define MUX_PB24C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) +#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */ +#define MUX_PC16D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) +#define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ +#define MUX_PB25C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) +#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */ +#define MUX_PC18D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) +#define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ +#define MUX_PC24C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) +#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */ +#define MUX_PC19D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) +#define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ +#define MUX_PC25C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) +#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PC22C_SERCOM1_PAD0 _L_(86) /**< \brief SERCOM1 signal: PAD0 on PC22 mux C */ +#define MUX_PC22C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PC22C_SERCOM1_PAD0 ((PIN_PC22C_SERCOM1_PAD0 << 16) | MUX_PC22C_SERCOM1_PAD0) +#define PORT_PC22C_SERCOM1_PAD0 (_UL_(1) << 22) +#define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */ +#define MUX_PC27C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) +#define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PC23C_SERCOM1_PAD1 _L_(87) /**< \brief SERCOM1 signal: PAD1 on PC23 mux C */ +#define MUX_PC23C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PC23C_SERCOM1_PAD1 ((PIN_PC23C_SERCOM1_PAD1 << 16) | MUX_PC23C_SERCOM1_PAD1) +#define PORT_PC23C_SERCOM1_PAD1 (_UL_(1) << 23) +#define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */ +#define MUX_PC28C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) +#define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) +#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) +#define PIN_PD20C_SERCOM1_PAD2 _L_(116) /**< \brief SERCOM1 signal: PAD2 on PD20 mux C */ +#define MUX_PD20C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PD20C_SERCOM1_PAD2 ((PIN_PD20C_SERCOM1_PAD2 << 16) | MUX_PD20C_SERCOM1_PAD2) +#define PORT_PD20C_SERCOM1_PAD2 (_UL_(1) << 20) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) +#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) +#define PIN_PD21C_SERCOM1_PAD3 _L_(117) /**< \brief SERCOM1 signal: PAD3 on PD21 mux C */ +#define MUX_PD21C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PD21C_SERCOM1_PAD3 ((PIN_PD21C_SERCOM1_PAD3 << 16) | MUX_PD21C_SERCOM1_PAD3) +#define PORT_PD21C_SERCOM1_PAD3 (_UL_(1) << 21) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TC0_WO0 _L_(4) +#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) +#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TC0_WO0 _L_(4) +#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) +#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TC0_WO0 _L_(4) +#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) +#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) +#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TC0_WO1 _L_(4) +#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) +#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TC0_WO1 _L_(4) +#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) +#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) +#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TC0_WO1 _L_(4) +#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) +#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TC1_WO0 _L_(4) +#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) +#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) +#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TC1_WO0 _L_(4) +#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) +#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) +#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TC1_WO1 _L_(4) +#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) +#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) +#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TC1_WO1 _L_(4) +#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) +#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ +#define MUX_PA24H_USB_DM _L_(7) +#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) +#define PORT_PA24H_USB_DM (_UL_(1) << 24) +#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ +#define MUX_PA25H_USB_DP _L_(7) +#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) +#define PORT_PA25H_USB_DP (_UL_(1) << 25) +#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ +#define MUX_PA23H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) +#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ +#define MUX_PB22H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) +#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) +#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) +#define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */ +#define MUX_PB25D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) +#define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25) +#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) +#define PIN_PB26C_SERCOM2_PAD0 _L_(58) /**< \brief SERCOM2 signal: PAD0 on PB26 mux C */ +#define MUX_PB26C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PB26C_SERCOM2_PAD0 ((PIN_PB26C_SERCOM2_PAD0 << 16) | MUX_PB26C_SERCOM2_PAD0) +#define PORT_PB26C_SERCOM2_PAD0 (_UL_(1) << 26) +#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) +#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) +#define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */ +#define MUX_PB24D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) +#define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24) +#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) +#define PIN_PB27C_SERCOM2_PAD1 _L_(59) /**< \brief SERCOM2 signal: PAD1 on PB27 mux C */ +#define MUX_PB27C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PB27C_SERCOM2_PAD1 ((PIN_PB27C_SERCOM2_PAD1 << 16) | MUX_PB27C_SERCOM2_PAD1) +#define PORT_PB27C_SERCOM2_PAD1 (_UL_(1) << 27) +#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) +#define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */ +#define MUX_PC24D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) +#define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24) +#define PIN_PB28C_SERCOM2_PAD2 _L_(60) /**< \brief SERCOM2 signal: PAD2 on PB28 mux C */ +#define MUX_PB28C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PB28C_SERCOM2_PAD2 ((PIN_PB28C_SERCOM2_PAD2 << 16) | MUX_PB28C_SERCOM2_PAD2) +#define PORT_PB28C_SERCOM2_PAD2 (_UL_(1) << 28) +#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) +#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) +#define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */ +#define MUX_PC25D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) +#define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25) +#define PIN_PB29C_SERCOM2_PAD3 _L_(61) /**< \brief SERCOM2 signal: PAD3 on PB29 mux C */ +#define MUX_PB29C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PB29C_SERCOM2_PAD3 ((PIN_PB29C_SERCOM2_PAD3 << 16) | MUX_PB29C_SERCOM2_PAD3) +#define PORT_PB29C_SERCOM2_PAD3 (_UL_(1) << 29) +#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) +#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) +#define PIN_PC23D_SERCOM3_PAD0 _L_(87) /**< \brief SERCOM3 signal: PAD0 on PC23 mux D */ +#define MUX_PC23D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PC23D_SERCOM3_PAD0 ((PIN_PC23D_SERCOM3_PAD0 << 16) | MUX_PC23D_SERCOM3_PAD0) +#define PORT_PC23D_SERCOM3_PAD0 (_UL_(1) << 23) +#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) +#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ +#define MUX_PB20C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) +#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) +#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) +#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) +#define PIN_PC22D_SERCOM3_PAD1 _L_(86) /**< \brief SERCOM3 signal: PAD1 on PC22 mux D */ +#define MUX_PC22D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PC22D_SERCOM3_PAD1 ((PIN_PC22D_SERCOM3_PAD1 << 16) | MUX_PC22D_SERCOM3_PAD1) +#define PORT_PC22D_SERCOM3_PAD1 (_UL_(1) << 22) +#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) +#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ +#define MUX_PB21C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) +#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) +#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PD20D_SERCOM3_PAD2 _L_(116) /**< \brief SERCOM3 signal: PAD2 on PD20 mux D */ +#define MUX_PD20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PD20D_SERCOM3_PAD2 ((PIN_PD20D_SERCOM3_PAD2 << 16) | MUX_PD20D_SERCOM3_PAD2) +#define PORT_PD20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PD21D_SERCOM3_PAD3 _L_(117) /**< \brief SERCOM3 signal: PAD3 on PD21 mux D */ +#define MUX_PD21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PD21D_SERCOM3_PAD3 ((PIN_PD21D_SERCOM3_PAD3 << 16) | MUX_PD21D_SERCOM3_PAD3) +#define PORT_PD21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ +#define MUX_PA20G_TCC0_WO0 _L_(6) +#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) +#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) +#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ +#define MUX_PB12G_TCC0_WO0 _L_(6) +#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) +#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) +#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ +#define MUX_PA08F_TCC0_WO0 _L_(5) +#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) +#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PC04F_TCC0_WO0 _L_(68) /**< \brief TCC0 signal: WO0 on PC04 mux F */ +#define MUX_PC04F_TCC0_WO0 _L_(5) +#define PINMUX_PC04F_TCC0_WO0 ((PIN_PC04F_TCC0_WO0 << 16) | MUX_PC04F_TCC0_WO0) +#define PORT_PC04F_TCC0_WO0 (_UL_(1) << 4) +#define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */ +#define MUX_PC10F_TCC0_WO0 _L_(5) +#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) +#define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10) +#define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */ +#define MUX_PC16F_TCC0_WO0 _L_(5) +#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) +#define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16) +#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ +#define MUX_PA21G_TCC0_WO1 _L_(6) +#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) +#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) +#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ +#define MUX_PB13G_TCC0_WO1 _L_(6) +#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) +#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) +#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ +#define MUX_PA09F_TCC0_WO1 _L_(5) +#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) +#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */ +#define MUX_PC11F_TCC0_WO1 _L_(5) +#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) +#define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11) +#define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */ +#define MUX_PC17F_TCC0_WO1 _L_(5) +#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) +#define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17) +#define PIN_PD08F_TCC0_WO1 _L_(104) /**< \brief TCC0 signal: WO1 on PD08 mux F */ +#define MUX_PD08F_TCC0_WO1 _L_(5) +#define PINMUX_PD08F_TCC0_WO1 ((PIN_PD08F_TCC0_WO1 << 16) | MUX_PD08F_TCC0_WO1) +#define PORT_PD08F_TCC0_WO1 (_UL_(1) << 8) +#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ +#define MUX_PA22G_TCC0_WO2 _L_(6) +#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) +#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ +#define MUX_PB14G_TCC0_WO2 _L_(6) +#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) +#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */ +#define MUX_PC12F_TCC0_WO2 _L_(5) +#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) +#define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12) +#define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */ +#define MUX_PC18F_TCC0_WO2 _L_(5) +#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) +#define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18) +#define PIN_PD09F_TCC0_WO2 _L_(105) /**< \brief TCC0 signal: WO2 on PD09 mux F */ +#define MUX_PD09F_TCC0_WO2 _L_(5) +#define PINMUX_PD09F_TCC0_WO2 ((PIN_PD09F_TCC0_WO2 << 16) | MUX_PD09F_TCC0_WO2) +#define PORT_PD09F_TCC0_WO2 (_UL_(1) << 9) +#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ +#define MUX_PA23G_TCC0_WO3 _L_(6) +#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) +#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ +#define MUX_PB15G_TCC0_WO3 _L_(6) +#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) +#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */ +#define MUX_PC13F_TCC0_WO3 _L_(5) +#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) +#define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13) +#define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */ +#define MUX_PC19F_TCC0_WO3 _L_(5) +#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) +#define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19) +#define PIN_PD10F_TCC0_WO3 _L_(106) /**< \brief TCC0 signal: WO3 on PD10 mux F */ +#define MUX_PD10F_TCC0_WO3 _L_(5) +#define PINMUX_PD10F_TCC0_WO3 ((PIN_PD10F_TCC0_WO3 << 16) | MUX_PD10F_TCC0_WO3) +#define PORT_PD10F_TCC0_WO3 (_UL_(1) << 10) +#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ +#define MUX_PA16G_TCC0_WO4 _L_(6) +#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) +#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ +#define MUX_PB16G_TCC0_WO4 _L_(6) +#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) +#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 _L_(5) +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) +#define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */ +#define MUX_PC14F_TCC0_WO4 _L_(5) +#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) +#define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14) +#define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */ +#define MUX_PC20F_TCC0_WO4 _L_(5) +#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) +#define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20) +#define PIN_PD11F_TCC0_WO4 _L_(107) /**< \brief TCC0 signal: WO4 on PD11 mux F */ +#define MUX_PD11F_TCC0_WO4 _L_(5) +#define PINMUX_PD11F_TCC0_WO4 ((PIN_PD11F_TCC0_WO4 << 16) | MUX_PD11F_TCC0_WO4) +#define PORT_PD11F_TCC0_WO4 (_UL_(1) << 11) +#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ +#define MUX_PA17G_TCC0_WO5 _L_(6) +#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) +#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ +#define MUX_PB17G_TCC0_WO5 _L_(6) +#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) +#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */ +#define MUX_PC15F_TCC0_WO5 _L_(5) +#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) +#define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15) +#define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */ +#define MUX_PC21F_TCC0_WO5 _L_(5) +#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) +#define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21) +#define PIN_PD12F_TCC0_WO5 _L_(108) /**< \brief TCC0 signal: WO5 on PD12 mux F */ +#define MUX_PD12F_TCC0_WO5 _L_(5) +#define PINMUX_PD12F_TCC0_WO5 ((PIN_PD12F_TCC0_WO5 << 16) | MUX_PD12F_TCC0_WO5) +#define PORT_PD12F_TCC0_WO5 (_UL_(1) << 12) +#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ +#define MUX_PA18G_TCC0_WO6 _L_(6) +#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) +#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) +#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ +#define MUX_PB30G_TCC0_WO6 _L_(6) +#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) +#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PC22F_TCC0_WO6 _L_(86) /**< \brief TCC0 signal: WO6 on PC22 mux F */ +#define MUX_PC22F_TCC0_WO6 _L_(5) +#define PINMUX_PC22F_TCC0_WO6 ((PIN_PC22F_TCC0_WO6 << 16) | MUX_PC22F_TCC0_WO6) +#define PORT_PC22F_TCC0_WO6 (_UL_(1) << 22) +#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ +#define MUX_PA19G_TCC0_WO7 _L_(6) +#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) +#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) +#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ +#define MUX_PB31G_TCC0_WO7 _L_(6) +#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) +#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +#define PIN_PC23F_TCC0_WO7 _L_(87) /**< \brief TCC0 signal: WO7 on PC23 mux F */ +#define MUX_PC23F_TCC0_WO7 _L_(5) +#define PINMUX_PC23F_TCC0_WO7 ((PIN_PC23F_TCC0_WO7 << 16) | MUX_PC23F_TCC0_WO7) +#define PORT_PC23F_TCC0_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ +#define MUX_PB10G_TCC1_WO0 _L_(6) +#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) +#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) +#define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */ +#define MUX_PC14G_TCC1_WO0 _L_(6) +#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) +#define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14) +#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC1_WO0 _L_(5) +#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) +#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) +#define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */ +#define MUX_PB18F_TCC1_WO0 _L_(5) +#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) +#define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18) +#define PIN_PD20F_TCC1_WO0 _L_(116) /**< \brief TCC1 signal: WO0 on PD20 mux F */ +#define MUX_PD20F_TCC1_WO0 _L_(5) +#define PINMUX_PD20F_TCC1_WO0 ((PIN_PD20F_TCC1_WO0 << 16) | MUX_PD20F_TCC1_WO0) +#define PORT_PD20F_TCC1_WO0 (_UL_(1) << 20) +#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ +#define MUX_PB11G_TCC1_WO1 _L_(6) +#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) +#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) +#define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */ +#define MUX_PC15G_TCC1_WO1 _L_(6) +#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) +#define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15) +#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC1_WO1 _L_(5) +#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) +#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) +#define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */ +#define MUX_PB19F_TCC1_WO1 _L_(5) +#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) +#define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19) +#define PIN_PD21F_TCC1_WO1 _L_(117) /**< \brief TCC1 signal: WO1 on PD21 mux F */ +#define MUX_PD21F_TCC1_WO1 _L_(5) +#define PINMUX_PD21F_TCC1_WO1 ((PIN_PD21F_TCC1_WO1 << 16) | MUX_PD21F_TCC1_WO1) +#define PORT_PD21F_TCC1_WO1 (_UL_(1) << 21) +#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ +#define MUX_PA12G_TCC1_WO2 _L_(6) +#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) +#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) +#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ +#define MUX_PA14G_TCC1_WO2 _L_(6) +#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) +#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) +#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC1_WO2 _L_(5) +#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) +#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) +#define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */ +#define MUX_PB20F_TCC1_WO2 _L_(5) +#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) +#define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20) +#define PIN_PB26F_TCC1_WO2 _L_(58) /**< \brief TCC1 signal: WO2 on PB26 mux F */ +#define MUX_PB26F_TCC1_WO2 _L_(5) +#define PINMUX_PB26F_TCC1_WO2 ((PIN_PB26F_TCC1_WO2 << 16) | MUX_PB26F_TCC1_WO2) +#define PORT_PB26F_TCC1_WO2 (_UL_(1) << 26) +#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ +#define MUX_PA13G_TCC1_WO3 _L_(6) +#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) +#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) +#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ +#define MUX_PA15G_TCC1_WO3 _L_(6) +#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) +#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) +#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC1_WO3 _L_(5) +#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) +#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) +#define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */ +#define MUX_PB21F_TCC1_WO3 _L_(5) +#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) +#define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21) +#define PIN_PB27F_TCC1_WO3 _L_(59) /**< \brief TCC1 signal: WO3 on PB27 mux F */ +#define MUX_PB27F_TCC1_WO3 _L_(5) +#define PINMUX_PB27F_TCC1_WO3 ((PIN_PB27F_TCC1_WO3 << 16) | MUX_PB27F_TCC1_WO3) +#define PORT_PB27F_TCC1_WO3 (_UL_(1) << 27) +#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ +#define MUX_PA08G_TCC1_WO4 _L_(6) +#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) +#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) +#define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */ +#define MUX_PC10G_TCC1_WO4 _L_(6) +#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) +#define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10) +#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ +#define MUX_PA20F_TCC1_WO4 _L_(5) +#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) +#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) +#define PIN_PB28F_TCC1_WO4 _L_(60) /**< \brief TCC1 signal: WO4 on PB28 mux F */ +#define MUX_PB28F_TCC1_WO4 _L_(5) +#define PINMUX_PB28F_TCC1_WO4 ((PIN_PB28F_TCC1_WO4 << 16) | MUX_PB28F_TCC1_WO4) +#define PORT_PB28F_TCC1_WO4 (_UL_(1) << 28) +#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ +#define MUX_PA09G_TCC1_WO5 _L_(6) +#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) +#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) +#define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */ +#define MUX_PC11G_TCC1_WO5 _L_(6) +#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) +#define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11) +#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ +#define MUX_PA21F_TCC1_WO5 _L_(5) +#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) +#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) +#define PIN_PB29F_TCC1_WO5 _L_(61) /**< \brief TCC1 signal: WO5 on PB29 mux F */ +#define MUX_PB29F_TCC1_WO5 _L_(5) +#define PINMUX_PB29F_TCC1_WO5 ((PIN_PB29F_TCC1_WO5 << 16) | MUX_PB29F_TCC1_WO5) +#define PORT_PB29F_TCC1_WO5 (_UL_(1) << 29) +#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ +#define MUX_PA10G_TCC1_WO6 _L_(6) +#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) +#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) +#define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */ +#define MUX_PC12G_TCC1_WO6 _L_(6) +#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) +#define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12) +#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ +#define MUX_PA22F_TCC1_WO6 _L_(5) +#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) +#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) +#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ +#define MUX_PA11G_TCC1_WO7 _L_(6) +#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) +#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) +#define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */ +#define MUX_PC13G_TCC1_WO7 _L_(6) +#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) +#define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13) +#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ +#define MUX_PA23F_TCC1_WO7 _L_(5) +#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) +#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TC2_WO0 _L_(4) +#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) +#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) +#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TC2_WO0 _L_(4) +#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) +#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) +#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TC2_WO0 _L_(4) +#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) +#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) +#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TC2_WO1 _L_(4) +#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) +#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) +#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TC2_WO1 _L_(4) +#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) +#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) +#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TC2_WO1 _L_(4) +#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) +#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC3_WO0 _L_(4) +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) +#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC3_WO0 _L_(4) +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) +#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC3_WO1 _L_(4) +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) +#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC3_WO1 _L_(4) +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) +/* ========== PORT definition for CAN0 peripheral ========== */ +#define PIN_PA23I_CAN0_RX _L_(23) /**< \brief CAN0 signal: RX on PA23 mux I */ +#define MUX_PA23I_CAN0_RX _L_(8) +#define PINMUX_PA23I_CAN0_RX ((PIN_PA23I_CAN0_RX << 16) | MUX_PA23I_CAN0_RX) +#define PORT_PA23I_CAN0_RX (_UL_(1) << 23) +#define PIN_PA25I_CAN0_RX _L_(25) /**< \brief CAN0 signal: RX on PA25 mux I */ +#define MUX_PA25I_CAN0_RX _L_(8) +#define PINMUX_PA25I_CAN0_RX ((PIN_PA25I_CAN0_RX << 16) | MUX_PA25I_CAN0_RX) +#define PORT_PA25I_CAN0_RX (_UL_(1) << 25) +#define PIN_PA22I_CAN0_TX _L_(22) /**< \brief CAN0 signal: TX on PA22 mux I */ +#define MUX_PA22I_CAN0_TX _L_(8) +#define PINMUX_PA22I_CAN0_TX ((PIN_PA22I_CAN0_TX << 16) | MUX_PA22I_CAN0_TX) +#define PORT_PA22I_CAN0_TX (_UL_(1) << 22) +#define PIN_PA24I_CAN0_TX _L_(24) /**< \brief CAN0 signal: TX on PA24 mux I */ +#define MUX_PA24I_CAN0_TX _L_(8) +#define PINMUX_PA24I_CAN0_TX ((PIN_PA24I_CAN0_TX << 16) | MUX_PA24I_CAN0_TX) +#define PORT_PA24I_CAN0_TX (_UL_(1) << 24) +/* ========== PORT definition for CAN1 peripheral ========== */ +#define PIN_PB13H_CAN1_RX _L_(45) /**< \brief CAN1 signal: RX on PB13 mux H */ +#define MUX_PB13H_CAN1_RX _L_(7) +#define PINMUX_PB13H_CAN1_RX ((PIN_PB13H_CAN1_RX << 16) | MUX_PB13H_CAN1_RX) +#define PORT_PB13H_CAN1_RX (_UL_(1) << 13) +#define PIN_PB15H_CAN1_RX _L_(47) /**< \brief CAN1 signal: RX on PB15 mux H */ +#define MUX_PB15H_CAN1_RX _L_(7) +#define PINMUX_PB15H_CAN1_RX ((PIN_PB15H_CAN1_RX << 16) | MUX_PB15H_CAN1_RX) +#define PORT_PB15H_CAN1_RX (_UL_(1) << 15) +#define PIN_PB12H_CAN1_TX _L_(44) /**< \brief CAN1 signal: TX on PB12 mux H */ +#define MUX_PB12H_CAN1_TX _L_(7) +#define PINMUX_PB12H_CAN1_TX ((PIN_PB12H_CAN1_TX << 16) | MUX_PB12H_CAN1_TX) +#define PORT_PB12H_CAN1_TX (_UL_(1) << 12) +#define PIN_PB14H_CAN1_TX _L_(46) /**< \brief CAN1 signal: TX on PB14 mux H */ +#define MUX_PB14H_CAN1_TX _L_(7) +#define PINMUX_PB14H_CAN1_TX ((PIN_PB14H_CAN1_TX << 16) | MUX_PB14H_CAN1_TX) +#define PORT_PB14H_CAN1_TX (_UL_(1) << 14) +/* ========== PORT definition for GMAC peripheral ========== */ +#define PIN_PC21L_GMAC_GCOL _L_(85) /**< \brief GMAC signal: GCOL on PC21 mux L */ +#define MUX_PC21L_GMAC_GCOL _L_(11) +#define PINMUX_PC21L_GMAC_GCOL ((PIN_PC21L_GMAC_GCOL << 16) | MUX_PC21L_GMAC_GCOL) +#define PORT_PC21L_GMAC_GCOL (_UL_(1) << 21) +#define PIN_PA16L_GMAC_GCRS _L_(16) /**< \brief GMAC signal: GCRS on PA16 mux L */ +#define MUX_PA16L_GMAC_GCRS _L_(11) +#define PINMUX_PA16L_GMAC_GCRS ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS) +#define PORT_PA16L_GMAC_GCRS (_UL_(1) << 16) +#define PIN_PA20L_GMAC_GMDC _L_(20) /**< \brief GMAC signal: GMDC on PA20 mux L */ +#define MUX_PA20L_GMAC_GMDC _L_(11) +#define PINMUX_PA20L_GMAC_GMDC ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC) +#define PORT_PA20L_GMAC_GMDC (_UL_(1) << 20) +#define PIN_PB14L_GMAC_GMDC _L_(46) /**< \brief GMAC signal: GMDC on PB14 mux L */ +#define MUX_PB14L_GMAC_GMDC _L_(11) +#define PINMUX_PB14L_GMAC_GMDC ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC) +#define PORT_PB14L_GMAC_GMDC (_UL_(1) << 14) +#define PIN_PC11L_GMAC_GMDC _L_(75) /**< \brief GMAC signal: GMDC on PC11 mux L */ +#define MUX_PC11L_GMAC_GMDC _L_(11) +#define PINMUX_PC11L_GMAC_GMDC ((PIN_PC11L_GMAC_GMDC << 16) | MUX_PC11L_GMAC_GMDC) +#define PORT_PC11L_GMAC_GMDC (_UL_(1) << 11) +#define PIN_PC22L_GMAC_GMDC _L_(86) /**< \brief GMAC signal: GMDC on PC22 mux L */ +#define MUX_PC22L_GMAC_GMDC _L_(11) +#define PINMUX_PC22L_GMAC_GMDC ((PIN_PC22L_GMAC_GMDC << 16) | MUX_PC22L_GMAC_GMDC) +#define PORT_PC22L_GMAC_GMDC (_UL_(1) << 22) +#define PIN_PA21L_GMAC_GMDIO _L_(21) /**< \brief GMAC signal: GMDIO on PA21 mux L */ +#define MUX_PA21L_GMAC_GMDIO _L_(11) +#define PINMUX_PA21L_GMAC_GMDIO ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO) +#define PORT_PA21L_GMAC_GMDIO (_UL_(1) << 21) +#define PIN_PB15L_GMAC_GMDIO _L_(47) /**< \brief GMAC signal: GMDIO on PB15 mux L */ +#define MUX_PB15L_GMAC_GMDIO _L_(11) +#define PINMUX_PB15L_GMAC_GMDIO ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO) +#define PORT_PB15L_GMAC_GMDIO (_UL_(1) << 15) +#define PIN_PC12L_GMAC_GMDIO _L_(76) /**< \brief GMAC signal: GMDIO on PC12 mux L */ +#define MUX_PC12L_GMAC_GMDIO _L_(11) +#define PINMUX_PC12L_GMAC_GMDIO ((PIN_PC12L_GMAC_GMDIO << 16) | MUX_PC12L_GMAC_GMDIO) +#define PORT_PC12L_GMAC_GMDIO (_UL_(1) << 12) +#define PIN_PC23L_GMAC_GMDIO _L_(87) /**< \brief GMAC signal: GMDIO on PC23 mux L */ +#define MUX_PC23L_GMAC_GMDIO _L_(11) +#define PINMUX_PC23L_GMAC_GMDIO ((PIN_PC23L_GMAC_GMDIO << 16) | MUX_PC23L_GMAC_GMDIO) +#define PORT_PC23L_GMAC_GMDIO (_UL_(1) << 23) +#define PIN_PA13L_GMAC_GRX0 _L_(13) /**< \brief GMAC signal: GRX0 on PA13 mux L */ +#define MUX_PA13L_GMAC_GRX0 _L_(11) +#define PINMUX_PA13L_GMAC_GRX0 ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0) +#define PORT_PA13L_GMAC_GRX0 (_UL_(1) << 13) +#define PIN_PA12L_GMAC_GRX1 _L_(12) /**< \brief GMAC signal: GRX1 on PA12 mux L */ +#define MUX_PA12L_GMAC_GRX1 _L_(11) +#define PINMUX_PA12L_GMAC_GRX1 ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1) +#define PORT_PA12L_GMAC_GRX1 (_UL_(1) << 12) +#define PIN_PC15L_GMAC_GRX2 _L_(79) /**< \brief GMAC signal: GRX2 on PC15 mux L */ +#define MUX_PC15L_GMAC_GRX2 _L_(11) +#define PINMUX_PC15L_GMAC_GRX2 ((PIN_PC15L_GMAC_GRX2 << 16) | MUX_PC15L_GMAC_GRX2) +#define PORT_PC15L_GMAC_GRX2 (_UL_(1) << 15) +#define PIN_PC14L_GMAC_GRX3 _L_(78) /**< \brief GMAC signal: GRX3 on PC14 mux L */ +#define MUX_PC14L_GMAC_GRX3 _L_(11) +#define PINMUX_PC14L_GMAC_GRX3 ((PIN_PC14L_GMAC_GRX3 << 16) | MUX_PC14L_GMAC_GRX3) +#define PORT_PC14L_GMAC_GRX3 (_UL_(1) << 14) +#define PIN_PC18L_GMAC_GRXCK _L_(82) /**< \brief GMAC signal: GRXCK on PC18 mux L */ +#define MUX_PC18L_GMAC_GRXCK _L_(11) +#define PINMUX_PC18L_GMAC_GRXCK ((PIN_PC18L_GMAC_GRXCK << 16) | MUX_PC18L_GMAC_GRXCK) +#define PORT_PC18L_GMAC_GRXCK (_UL_(1) << 18) +#define PIN_PC20L_GMAC_GRXDV _L_(84) /**< \brief GMAC signal: GRXDV on PC20 mux L */ +#define MUX_PC20L_GMAC_GRXDV _L_(11) +#define PINMUX_PC20L_GMAC_GRXDV ((PIN_PC20L_GMAC_GRXDV << 16) | MUX_PC20L_GMAC_GRXDV) +#define PORT_PC20L_GMAC_GRXDV (_UL_(1) << 20) +#define PIN_PA15L_GMAC_GRXER _L_(15) /**< \brief GMAC signal: GRXER on PA15 mux L */ +#define MUX_PA15L_GMAC_GRXER _L_(11) +#define PINMUX_PA15L_GMAC_GRXER ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER) +#define PORT_PA15L_GMAC_GRXER (_UL_(1) << 15) +#define PIN_PA18L_GMAC_GTX0 _L_(18) /**< \brief GMAC signal: GTX0 on PA18 mux L */ +#define MUX_PA18L_GMAC_GTX0 _L_(11) +#define PINMUX_PA18L_GMAC_GTX0 ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0) +#define PORT_PA18L_GMAC_GTX0 (_UL_(1) << 18) +#define PIN_PA19L_GMAC_GTX1 _L_(19) /**< \brief GMAC signal: GTX1 on PA19 mux L */ +#define MUX_PA19L_GMAC_GTX1 _L_(11) +#define PINMUX_PA19L_GMAC_GTX1 ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1) +#define PORT_PA19L_GMAC_GTX1 (_UL_(1) << 19) +#define PIN_PC16L_GMAC_GTX2 _L_(80) /**< \brief GMAC signal: GTX2 on PC16 mux L */ +#define MUX_PC16L_GMAC_GTX2 _L_(11) +#define PINMUX_PC16L_GMAC_GTX2 ((PIN_PC16L_GMAC_GTX2 << 16) | MUX_PC16L_GMAC_GTX2) +#define PORT_PC16L_GMAC_GTX2 (_UL_(1) << 16) +#define PIN_PC17L_GMAC_GTX3 _L_(81) /**< \brief GMAC signal: GTX3 on PC17 mux L */ +#define MUX_PC17L_GMAC_GTX3 _L_(11) +#define PINMUX_PC17L_GMAC_GTX3 ((PIN_PC17L_GMAC_GTX3 << 16) | MUX_PC17L_GMAC_GTX3) +#define PORT_PC17L_GMAC_GTX3 (_UL_(1) << 17) +#define PIN_PA14L_GMAC_GTXCK _L_(14) /**< \brief GMAC signal: GTXCK on PA14 mux L */ +#define MUX_PA14L_GMAC_GTXCK _L_(11) +#define PINMUX_PA14L_GMAC_GTXCK ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK) +#define PORT_PA14L_GMAC_GTXCK (_UL_(1) << 14) +#define PIN_PA17L_GMAC_GTXEN _L_(17) /**< \brief GMAC signal: GTXEN on PA17 mux L */ +#define MUX_PA17L_GMAC_GTXEN _L_(11) +#define PINMUX_PA17L_GMAC_GTXEN ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN) +#define PORT_PA17L_GMAC_GTXEN (_UL_(1) << 17) +#define PIN_PC19L_GMAC_GTXER _L_(83) /**< \brief GMAC signal: GTXER on PC19 mux L */ +#define MUX_PC19L_GMAC_GTXER _L_(11) +#define PINMUX_PC19L_GMAC_GTXER ((PIN_PC19L_GMAC_GTXER << 16) | MUX_PC19L_GMAC_GTXER) +#define PORT_PC19L_GMAC_GTXER (_UL_(1) << 19) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ +#define MUX_PA14F_TCC2_WO0 _L_(5) +#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) +#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) +#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ +#define MUX_PA30F_TCC2_WO0 _L_(5) +#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) +#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) +#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ +#define MUX_PA15F_TCC2_WO1 _L_(5) +#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) +#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) +#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ +#define MUX_PA31F_TCC2_WO1 _L_(5) +#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) +#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) +#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC2_WO2 _L_(5) +#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) +#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) +#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ +#define MUX_PB02F_TCC2_WO2 _L_(5) +#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) +#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) +/* ========== PORT definition for TCC3 peripheral ========== */ +#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ +#define MUX_PB12F_TCC3_WO0 _L_(5) +#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) +#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) +#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ +#define MUX_PB16F_TCC3_WO0 _L_(5) +#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) +#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) +#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ +#define MUX_PB13F_TCC3_WO1 _L_(5) +#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) +#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) +#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ +#define MUX_PB17F_TCC3_WO1 _L_(5) +#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) +#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC4_WO0 _L_(4) +#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) +#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) +#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC4_WO0 _L_(4) +#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) +#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) +#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC4_WO0 _L_(4) +#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) +#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) +#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC4_WO1 _L_(4) +#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) +#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) +#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC4_WO1 _L_(4) +#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) +#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) +#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC4_WO1 _L_(4) +#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) +#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) +/* ========== PORT definition for TC5 peripheral ========== */ +#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC5_WO0 _L_(4) +#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) +#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) +#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ +#define MUX_PB10E_TC5_WO0 _L_(4) +#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) +#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) +#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC5_WO0 _L_(4) +#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) +#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) +#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC5_WO1 _L_(4) +#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) +#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) +#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC5_WO1 _L_(4) +#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) +#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) +#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC5_WO1 _L_(4) +#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) +#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) +/* ========== PORT definition for PDEC peripheral ========== */ +#define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */ +#define MUX_PB18G_PDEC_QDI0 _L_(6) +#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) +#define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18) +#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ +#define MUX_PB23G_PDEC_QDI0 _L_(6) +#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) +#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) +#define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */ +#define MUX_PC16G_PDEC_QDI0 _L_(6) +#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) +#define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16) +#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ +#define MUX_PA24G_PDEC_QDI0 _L_(6) +#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) +#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) +#define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */ +#define MUX_PB19G_PDEC_QDI1 _L_(6) +#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) +#define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19) +#define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */ +#define MUX_PB24G_PDEC_QDI1 _L_(6) +#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) +#define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24) +#define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */ +#define MUX_PC17G_PDEC_QDI1 _L_(6) +#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) +#define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17) +#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ +#define MUX_PA25G_PDEC_QDI1 _L_(6) +#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) +#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) +#define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */ +#define MUX_PB20G_PDEC_QDI2 _L_(6) +#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) +#define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20) +#define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */ +#define MUX_PB25G_PDEC_QDI2 _L_(6) +#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) +#define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25) +#define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */ +#define MUX_PC18G_PDEC_QDI2 _L_(6) +#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) +#define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18) +#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ +#define MUX_PB22G_PDEC_QDI2 _L_(6) +#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) +#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 _L_(1) +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) +#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 _L_(1) +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) +#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 _L_(1) +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) +#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 _L_(1) +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) +#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ +#define MUX_PA12M_AC_CMP0 _L_(12) +#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) +#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ +#define MUX_PA18M_AC_CMP0 _L_(12) +#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) +#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) +#define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */ +#define MUX_PB24M_AC_CMP0 _L_(12) +#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) +#define PORT_PB24M_AC_CMP0 (_UL_(1) << 24) +#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ +#define MUX_PA13M_AC_CMP1 _L_(12) +#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) +#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ +#define MUX_PA19M_AC_CMP1 _L_(12) +#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) +#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) +#define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */ +#define MUX_PB25M_AC_CMP1 _L_(12) +#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) +#define PORT_PB25M_AC_CMP1 (_UL_(1) << 25) +/* ========== PORT definition for QSPI peripheral ========== */ +#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ +#define MUX_PB11H_QSPI_CS _L_(7) +#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) +#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) +#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ +#define MUX_PA08H_QSPI_DATA0 _L_(7) +#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) +#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) +#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ +#define MUX_PA09H_QSPI_DATA1 _L_(7) +#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) +#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) +#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ +#define MUX_PA10H_QSPI_DATA2 _L_(7) +#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) +#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) +#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ +#define MUX_PA11H_QSPI_DATA3 _L_(7) +#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) +#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) +#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ +#define MUX_PB10H_QSPI_SCK _L_(7) +#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) +#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ +#define MUX_PA04N_CCL_IN0 _L_(13) +#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) +#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ +#define MUX_PA16N_CCL_IN0 _L_(13) +#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) +#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ +#define MUX_PB22N_CCL_IN0 _L_(13) +#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) +#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ +#define MUX_PA05N_CCL_IN1 _L_(13) +#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) +#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ +#define MUX_PA17N_CCL_IN1 _L_(13) +#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) +#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) +#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ +#define MUX_PB00N_CCL_IN1 _L_(13) +#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) +#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) +#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ +#define MUX_PA06N_CCL_IN2 _L_(13) +#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) +#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ +#define MUX_PA18N_CCL_IN2 _L_(13) +#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) +#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) +#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ +#define MUX_PB01N_CCL_IN2 _L_(13) +#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) +#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) +#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ +#define MUX_PA08N_CCL_IN3 _L_(13) +#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) +#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ +#define MUX_PA30N_CCL_IN3 _L_(13) +#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) +#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ +#define MUX_PA09N_CCL_IN4 _L_(13) +#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) +#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) +#define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */ +#define MUX_PC27N_CCL_IN4 _L_(13) +#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) +#define PORT_PC27N_CCL_IN4 (_UL_(1) << 27) +#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ +#define MUX_PA10N_CCL_IN5 _L_(13) +#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) +#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) +#define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */ +#define MUX_PC28N_CCL_IN5 _L_(13) +#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) +#define PORT_PC28N_CCL_IN5 (_UL_(1) << 28) +#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ +#define MUX_PA22N_CCL_IN6 _L_(13) +#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) +#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) +#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ +#define MUX_PB06N_CCL_IN6 _L_(13) +#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) +#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) +#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ +#define MUX_PA23N_CCL_IN7 _L_(13) +#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) +#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) +#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ +#define MUX_PB07N_CCL_IN7 _L_(13) +#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) +#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) +#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ +#define MUX_PA24N_CCL_IN8 _L_(13) +#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) +#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ +#define MUX_PB08N_CCL_IN8 _L_(13) +#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) +#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) +#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ +#define MUX_PB14N_CCL_IN9 _L_(13) +#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) +#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) +#define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */ +#define MUX_PC20N_CCL_IN9 _L_(13) +#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) +#define PORT_PC20N_CCL_IN9 (_UL_(1) << 20) +#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ +#define MUX_PB15N_CCL_IN10 _L_(13) +#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) +#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) +#define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */ +#define MUX_PC21N_CCL_IN10 _L_(13) +#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) +#define PORT_PC21N_CCL_IN10 (_UL_(1) << 21) +#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ +#define MUX_PB10N_CCL_IN11 _L_(13) +#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) +#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) +#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ +#define MUX_PB16N_CCL_IN11 _L_(13) +#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) +#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) +#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ +#define MUX_PA07N_CCL_OUT0 _L_(13) +#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) +#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ +#define MUX_PA19N_CCL_OUT0 _L_(13) +#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) +#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ +#define MUX_PB02N_CCL_OUT0 _L_(13) +#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) +#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ +#define MUX_PB23N_CCL_OUT0 _L_(13) +#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) +#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ +#define MUX_PA11N_CCL_OUT1 _L_(13) +#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) +#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ +#define MUX_PA31N_CCL_OUT1 _L_(13) +#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) +#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ +#define MUX_PB11N_CCL_OUT1 _L_(13) +#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) +#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ +#define MUX_PA25N_CCL_OUT2 _L_(13) +#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) +#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ +#define MUX_PB09N_CCL_OUT2 _L_(13) +#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) +#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) +#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ +#define MUX_PB17N_CCL_OUT3 _L_(13) +#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) +#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) +#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) +#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) +#define PIN_PB27D_SERCOM4_PAD0 _L_(59) /**< \brief SERCOM4 signal: PAD0 on PB27 mux D */ +#define MUX_PB27D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB27D_SERCOM4_PAD0 ((PIN_PB27D_SERCOM4_PAD0 << 16) | MUX_PB27D_SERCOM4_PAD0) +#define PORT_PB27D_SERCOM4_PAD0 (_UL_(1) << 27) +#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM4_PAD0 _L_(2) +#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) +#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) +#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) +#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) +#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) +#define PIN_PB26D_SERCOM4_PAD1 _L_(58) /**< \brief SERCOM4 signal: PAD1 on PB26 mux D */ +#define MUX_PB26D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB26D_SERCOM4_PAD1 ((PIN_PB26D_SERCOM4_PAD1 << 16) | MUX_PB26D_SERCOM4_PAD1) +#define PORT_PB26D_SERCOM4_PAD1 (_UL_(1) << 26) +#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM4_PAD1 _L_(2) +#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) +#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) +#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) +#define PIN_PB28D_SERCOM4_PAD2 _L_(60) /**< \brief SERCOM4 signal: PAD2 on PB28 mux D */ +#define MUX_PB28D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB28D_SERCOM4_PAD2 ((PIN_PB28D_SERCOM4_PAD2 << 16) | MUX_PB28D_SERCOM4_PAD2) +#define PORT_PB28D_SERCOM4_PAD2 (_UL_(1) << 28) +#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM4_PAD2 _L_(2) +#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) +#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) +#define PIN_PB29D_SERCOM4_PAD3 _L_(61) /**< \brief SERCOM4 signal: PAD3 on PB29 mux D */ +#define MUX_PB29D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB29D_SERCOM4_PAD3 ((PIN_PB29D_SERCOM4_PAD3 << 16) | MUX_PB29D_SERCOM4_PAD3) +#define PORT_PB29D_SERCOM4_PAD3 (_UL_(1) << 29) +#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) +#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM4_PAD3 _L_(2) +#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) +#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) +#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) +#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) +#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) +#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) +#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 _L_(2) +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) +#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) +#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) +#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) +#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) +#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) +#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 _L_(2) +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) +#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) +#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) +#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) +#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) +#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ +#define MUX_PB18C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) +#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) +#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) +#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ +#define MUX_PB01D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) +#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) +#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) +#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ +#define MUX_PB19C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) +#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM6 peripheral ========== */ +#define PIN_PD09D_SERCOM6_PAD0 _L_(105) /**< \brief SERCOM6 signal: PAD0 on PD09 mux D */ +#define MUX_PD09D_SERCOM6_PAD0 _L_(3) +#define PINMUX_PD09D_SERCOM6_PAD0 ((PIN_PD09D_SERCOM6_PAD0 << 16) | MUX_PD09D_SERCOM6_PAD0) +#define PORT_PD09D_SERCOM6_PAD0 (_UL_(1) << 9) +#define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */ +#define MUX_PC13D_SERCOM6_PAD0 _L_(3) +#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) +#define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13) +#define PIN_PC04C_SERCOM6_PAD0 _L_(68) /**< \brief SERCOM6 signal: PAD0 on PC04 mux C */ +#define MUX_PC04C_SERCOM6_PAD0 _L_(2) +#define PINMUX_PC04C_SERCOM6_PAD0 ((PIN_PC04C_SERCOM6_PAD0 << 16) | MUX_PC04C_SERCOM6_PAD0) +#define PORT_PC04C_SERCOM6_PAD0 (_UL_(1) << 4) +#define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */ +#define MUX_PC16C_SERCOM6_PAD0 _L_(2) +#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) +#define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16) +#define PIN_PD08D_SERCOM6_PAD1 _L_(104) /**< \brief SERCOM6 signal: PAD1 on PD08 mux D */ +#define MUX_PD08D_SERCOM6_PAD1 _L_(3) +#define PINMUX_PD08D_SERCOM6_PAD1 ((PIN_PD08D_SERCOM6_PAD1 << 16) | MUX_PD08D_SERCOM6_PAD1) +#define PORT_PD08D_SERCOM6_PAD1 (_UL_(1) << 8) +#define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */ +#define MUX_PC12D_SERCOM6_PAD1 _L_(3) +#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) +#define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12) +#define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */ +#define MUX_PC05C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) +#define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5) +#define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */ +#define MUX_PC17C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) +#define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17) +#define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */ +#define MUX_PC14D_SERCOM6_PAD2 _L_(3) +#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) +#define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14) +#define PIN_PD10D_SERCOM6_PAD2 _L_(106) /**< \brief SERCOM6 signal: PAD2 on PD10 mux D */ +#define MUX_PD10D_SERCOM6_PAD2 _L_(3) +#define PINMUX_PD10D_SERCOM6_PAD2 ((PIN_PD10D_SERCOM6_PAD2 << 16) | MUX_PD10D_SERCOM6_PAD2) +#define PORT_PD10D_SERCOM6_PAD2 (_UL_(1) << 10) +#define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */ +#define MUX_PC06C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) +#define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6) +#define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */ +#define MUX_PC10C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) +#define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10) +#define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */ +#define MUX_PC18C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) +#define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18) +#define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */ +#define MUX_PC15D_SERCOM6_PAD3 _L_(3) +#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) +#define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15) +#define PIN_PD11D_SERCOM6_PAD3 _L_(107) /**< \brief SERCOM6 signal: PAD3 on PD11 mux D */ +#define MUX_PD11D_SERCOM6_PAD3 _L_(3) +#define PINMUX_PD11D_SERCOM6_PAD3 ((PIN_PD11D_SERCOM6_PAD3 << 16) | MUX_PD11D_SERCOM6_PAD3) +#define PORT_PD11D_SERCOM6_PAD3 (_UL_(1) << 11) +#define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */ +#define MUX_PC07C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) +#define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7) +#define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */ +#define MUX_PC11C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) +#define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11) +#define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */ +#define MUX_PC19C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) +#define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM7 peripheral ========== */ +#define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */ +#define MUX_PB21D_SERCOM7_PAD0 _L_(3) +#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) +#define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21) +#define PIN_PD08C_SERCOM7_PAD0 _L_(104) /**< \brief SERCOM7 signal: PAD0 on PD08 mux C */ +#define MUX_PD08C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PD08C_SERCOM7_PAD0 ((PIN_PD08C_SERCOM7_PAD0 << 16) | MUX_PD08C_SERCOM7_PAD0) +#define PORT_PD08C_SERCOM7_PAD0 (_UL_(1) << 8) +#define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */ +#define MUX_PB30C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) +#define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30) +#define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */ +#define MUX_PC12C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) +#define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12) +#define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */ +#define MUX_PB20D_SERCOM7_PAD1 _L_(3) +#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) +#define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20) +#define PIN_PD09C_SERCOM7_PAD1 _L_(105) /**< \brief SERCOM7 signal: PAD1 on PD09 mux C */ +#define MUX_PD09C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PD09C_SERCOM7_PAD1 ((PIN_PD09C_SERCOM7_PAD1 << 16) | MUX_PD09C_SERCOM7_PAD1) +#define PORT_PD09C_SERCOM7_PAD1 (_UL_(1) << 9) +#define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */ +#define MUX_PB31C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) +#define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31) +#define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */ +#define MUX_PC13C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) +#define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13) +#define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */ +#define MUX_PB18D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) +#define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18) +#define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */ +#define MUX_PC10D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) +#define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10) +#define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */ +#define MUX_PC14C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) +#define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14) +#define PIN_PD10C_SERCOM7_PAD2 _L_(106) /**< \brief SERCOM7 signal: PAD2 on PD10 mux C */ +#define MUX_PD10C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PD10C_SERCOM7_PAD2 ((PIN_PD10C_SERCOM7_PAD2 << 16) | MUX_PD10C_SERCOM7_PAD2) +#define PORT_PD10C_SERCOM7_PAD2 (_UL_(1) << 10) +#define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */ +#define MUX_PA30C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) +#define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30) +#define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */ +#define MUX_PB19D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) +#define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19) +#define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */ +#define MUX_PC11D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) +#define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11) +#define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */ +#define MUX_PC15C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) +#define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15) +#define PIN_PD11C_SERCOM7_PAD3 _L_(107) /**< \brief SERCOM7 signal: PAD3 on PD11 mux C */ +#define MUX_PD11C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PD11C_SERCOM7_PAD3 ((PIN_PD11C_SERCOM7_PAD3 << 16) | MUX_PD11C_SERCOM7_PAD3) +#define PORT_PD11C_SERCOM7_PAD3 (_UL_(1) << 11) +#define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */ +#define MUX_PA31C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) +#define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31) +/* ========== PORT definition for TCC4 peripheral ========== */ +#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ +#define MUX_PB14F_TCC4_WO0 _L_(5) +#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) +#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) +#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ +#define MUX_PB30F_TCC4_WO0 _L_(5) +#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) +#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) +#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ +#define MUX_PB15F_TCC4_WO1 _L_(5) +#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) +#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) +#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ +#define MUX_PB31F_TCC4_WO1 _L_(5) +#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) +#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC6 peripheral ========== */ +#define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */ +#define MUX_PA30E_TC6_WO0 _L_(4) +#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) +#define PORT_PA30E_TC6_WO0 (_UL_(1) << 30) +#define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC6_WO0 _L_(4) +#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) +#define PORT_PB02E_TC6_WO0 (_UL_(1) << 2) +#define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */ +#define MUX_PB16E_TC6_WO0 _L_(4) +#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) +#define PORT_PB16E_TC6_WO0 (_UL_(1) << 16) +#define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */ +#define MUX_PA31E_TC6_WO1 _L_(4) +#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) +#define PORT_PA31E_TC6_WO1 (_UL_(1) << 31) +#define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC6_WO1 _L_(4) +#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) +#define PORT_PB03E_TC6_WO1 (_UL_(1) << 3) +#define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */ +#define MUX_PB17E_TC6_WO1 _L_(4) +#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) +#define PORT_PB17E_TC6_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC7 peripheral ========== */ +#define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC7_WO0 _L_(4) +#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) +#define PORT_PA20E_TC7_WO0 (_UL_(1) << 20) +#define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */ +#define MUX_PB00E_TC7_WO0 _L_(4) +#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) +#define PORT_PB00E_TC7_WO0 (_UL_(1) << 0) +#define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC7_WO0 _L_(4) +#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) +#define PORT_PB22E_TC7_WO0 (_UL_(1) << 22) +#define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC7_WO1 _L_(4) +#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) +#define PORT_PA21E_TC7_WO1 (_UL_(1) << 21) +#define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */ +#define MUX_PB01E_TC7_WO1 _L_(4) +#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) +#define PORT_PB01E_TC7_WO1 (_UL_(1) << 1) +#define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC7_WO1 _L_(4) +#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) +#define PORT_PB23E_TC7_WO1 (_UL_(1) << 23) +/* ========== PORT definition for ADC0 peripheral ========== */ +#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC0_AIN0 _L_(1) +#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) +#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC0_AIN1 _L_(1) +#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) +#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC0_AIN2 _L_(1) +#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) +#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC0_AIN3 _L_(1) +#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) +#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC0_AIN4 _L_(1) +#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) +#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC0_AIN5 _L_(1) +#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) +#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC0_AIN6 _L_(1) +#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) +#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC0_AIN7 _L_(1) +#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) +#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ +#define MUX_PA08B_ADC0_AIN8 _L_(1) +#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) +#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ +#define MUX_PA09B_ADC0_AIN9 _L_(1) +#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) +#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ +#define MUX_PA10B_ADC0_AIN10 _L_(1) +#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) +#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ +#define MUX_PA11B_ADC0_AIN11 _L_(1) +#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) +#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) +#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ +#define MUX_PB00B_ADC0_AIN12 _L_(1) +#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) +#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ +#define MUX_PB01B_ADC0_AIN13 _L_(1) +#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) +#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) +#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ +#define MUX_PB02B_ADC0_AIN14 _L_(1) +#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) +#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ +#define MUX_PB03B_ADC0_AIN15 _L_(1) +#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) +#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) +#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ +#define MUX_PA03O_ADC0_DRV0 _L_(14) +#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) +#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) +#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ +#define MUX_PB08O_ADC0_DRV1 _L_(14) +#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) +#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) +#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ +#define MUX_PB09O_ADC0_DRV2 _L_(14) +#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) +#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) +#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ +#define MUX_PA04O_ADC0_DRV3 _L_(14) +#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) +#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) +#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ +#define MUX_PA06O_ADC0_DRV4 _L_(14) +#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) +#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) +#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ +#define MUX_PA07O_ADC0_DRV5 _L_(14) +#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) +#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) +#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ +#define MUX_PA08O_ADC0_DRV6 _L_(14) +#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) +#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) +#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ +#define MUX_PA09O_ADC0_DRV7 _L_(14) +#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) +#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) +#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ +#define MUX_PA10O_ADC0_DRV8 _L_(14) +#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) +#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) +#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ +#define MUX_PA11O_ADC0_DRV9 _L_(14) +#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) +#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) +#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ +#define MUX_PA16O_ADC0_DRV10 _L_(14) +#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) +#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) +#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ +#define MUX_PA17O_ADC0_DRV11 _L_(14) +#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) +#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) +#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ +#define MUX_PA18O_ADC0_DRV12 _L_(14) +#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) +#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) +#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ +#define MUX_PA19O_ADC0_DRV13 _L_(14) +#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) +#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) +#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ +#define MUX_PA20O_ADC0_DRV14 _L_(14) +#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) +#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) +#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ +#define MUX_PA21O_ADC0_DRV15 _L_(14) +#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) +#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) +#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ +#define MUX_PA22O_ADC0_DRV16 _L_(14) +#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) +#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) +#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ +#define MUX_PA23O_ADC0_DRV17 _L_(14) +#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) +#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) +#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ +#define MUX_PA27O_ADC0_DRV18 _L_(14) +#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) +#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) +#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ +#define MUX_PA30O_ADC0_DRV19 _L_(14) +#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) +#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) +#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ +#define MUX_PB02O_ADC0_DRV20 _L_(14) +#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) +#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) +#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ +#define MUX_PB03O_ADC0_DRV21 _L_(14) +#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) +#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) +#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ +#define MUX_PB04O_ADC0_DRV22 _L_(14) +#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) +#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) +#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ +#define MUX_PB05O_ADC0_DRV23 _L_(14) +#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) +#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) +#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ +#define MUX_PB06O_ADC0_DRV24 _L_(14) +#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) +#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) +#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ +#define MUX_PB07O_ADC0_DRV25 _L_(14) +#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) +#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) +#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ +#define MUX_PB12O_ADC0_DRV26 _L_(14) +#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) +#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) +#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ +#define MUX_PB13O_ADC0_DRV27 _L_(14) +#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) +#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) +#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ +#define MUX_PB14O_ADC0_DRV28 _L_(14) +#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) +#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) +#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ +#define MUX_PB15O_ADC0_DRV29 _L_(14) +#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) +#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) +#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ +#define MUX_PB00O_ADC0_DRV30 _L_(14) +#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) +#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) +#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ +#define MUX_PB01O_ADC0_DRV31 _L_(14) +#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) +#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) +#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ +#define MUX_PA03B_ADC0_PTCXY0 _L_(1) +#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) +#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ +#define MUX_PB08B_ADC0_PTCXY1 _L_(1) +#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) +#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ +#define MUX_PB09B_ADC0_PTCXY2 _L_(1) +#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) +#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ +#define MUX_PA04B_ADC0_PTCXY3 _L_(1) +#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) +#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) +#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ +#define MUX_PA06B_ADC0_PTCXY4 _L_(1) +#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) +#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ +#define MUX_PA07B_ADC0_PTCXY5 _L_(1) +#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) +#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ +#define MUX_PA08B_ADC0_PTCXY6 _L_(1) +#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) +#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ +#define MUX_PA09B_ADC0_PTCXY7 _L_(1) +#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) +#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ +#define MUX_PA10B_ADC0_PTCXY8 _L_(1) +#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) +#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ +#define MUX_PA11B_ADC0_PTCXY9 _L_(1) +#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) +#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) +#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ +#define MUX_PA16B_ADC0_PTCXY10 _L_(1) +#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) +#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) +#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ +#define MUX_PA17B_ADC0_PTCXY11 _L_(1) +#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) +#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) +#define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */ +#define MUX_PA18B_ADC0_PTCXY12 _L_(1) +#define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12) +#define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18) +#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ +#define MUX_PA19B_ADC0_PTCXY13 _L_(1) +#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) +#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) +#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ +#define MUX_PA20B_ADC0_PTCXY14 _L_(1) +#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) +#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) +#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ +#define MUX_PA21B_ADC0_PTCXY15 _L_(1) +#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) +#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) +#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ +#define MUX_PA22B_ADC0_PTCXY16 _L_(1) +#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) +#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) +#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ +#define MUX_PA23B_ADC0_PTCXY17 _L_(1) +#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) +#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) +#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ +#define MUX_PA27B_ADC0_PTCXY18 _L_(1) +#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) +#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) +#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ +#define MUX_PA30B_ADC0_PTCXY19 _L_(1) +#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) +#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) +#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ +#define MUX_PB02B_ADC0_PTCXY20 _L_(1) +#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) +#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ +#define MUX_PB03B_ADC0_PTCXY21 _L_(1) +#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) +#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) +#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ +#define MUX_PB04B_ADC0_PTCXY22 _L_(1) +#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) +#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) +#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ +#define MUX_PB05B_ADC0_PTCXY23 _L_(1) +#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) +#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) +#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ +#define MUX_PB06B_ADC0_PTCXY24 _L_(1) +#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) +#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) +#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ +#define MUX_PB07B_ADC0_PTCXY25 _L_(1) +#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) +#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) +#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ +#define MUX_PB12B_ADC0_PTCXY26 _L_(1) +#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) +#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) +#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ +#define MUX_PB13B_ADC0_PTCXY27 _L_(1) +#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) +#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) +#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ +#define MUX_PB14B_ADC0_PTCXY28 _L_(1) +#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) +#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) +#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ +#define MUX_PB15B_ADC0_PTCXY29 _L_(1) +#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) +#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) +#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ +#define MUX_PB00B_ADC0_PTCXY30 _L_(1) +#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) +#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ +#define MUX_PB01B_ADC0_PTCXY31 _L_(1) +#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) +#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) +/* ========== PORT definition for ADC1 peripheral ========== */ +#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ +#define MUX_PB08B_ADC1_AIN0 _L_(1) +#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) +#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) +#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ +#define MUX_PB09B_ADC1_AIN1 _L_(1) +#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) +#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) +#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ +#define MUX_PA08B_ADC1_AIN2 _L_(1) +#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) +#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) +#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ +#define MUX_PA09B_ADC1_AIN3 _L_(1) +#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) +#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) +#define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */ +#define MUX_PC02B_ADC1_AIN4 _L_(1) +#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) +#define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2) +#define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */ +#define MUX_PC03B_ADC1_AIN5 _L_(1) +#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) +#define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3) +#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ +#define MUX_PB04B_ADC1_AIN6 _L_(1) +#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) +#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) +#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ +#define MUX_PB05B_ADC1_AIN7 _L_(1) +#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) +#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) +#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ +#define MUX_PB06B_ADC1_AIN8 _L_(1) +#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) +#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) +#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ +#define MUX_PB07B_ADC1_AIN9 _L_(1) +#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) +#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) +#define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */ +#define MUX_PC00B_ADC1_AIN10 _L_(1) +#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) +#define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0) +#define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */ +#define MUX_PC01B_ADC1_AIN11 _L_(1) +#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) +#define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1) +#define PIN_PC30B_ADC1_AIN12 _L_(94) /**< \brief ADC1 signal: AIN12 on PC30 mux B */ +#define MUX_PC30B_ADC1_AIN12 _L_(1) +#define PINMUX_PC30B_ADC1_AIN12 ((PIN_PC30B_ADC1_AIN12 << 16) | MUX_PC30B_ADC1_AIN12) +#define PORT_PC30B_ADC1_AIN12 (_UL_(1) << 30) +#define PIN_PC31B_ADC1_AIN13 _L_(95) /**< \brief ADC1 signal: AIN13 on PC31 mux B */ +#define MUX_PC31B_ADC1_AIN13 _L_(1) +#define PINMUX_PC31B_ADC1_AIN13 ((PIN_PC31B_ADC1_AIN13 << 16) | MUX_PC31B_ADC1_AIN13) +#define PORT_PC31B_ADC1_AIN13 (_UL_(1) << 31) +#define PIN_PD00B_ADC1_AIN14 _L_(96) /**< \brief ADC1 signal: AIN14 on PD00 mux B */ +#define MUX_PD00B_ADC1_AIN14 _L_(1) +#define PINMUX_PD00B_ADC1_AIN14 ((PIN_PD00B_ADC1_AIN14 << 16) | MUX_PD00B_ADC1_AIN14) +#define PORT_PD00B_ADC1_AIN14 (_UL_(1) << 0) +#define PIN_PD01B_ADC1_AIN15 _L_(97) /**< \brief ADC1 signal: AIN15 on PD01 mux B */ +#define MUX_PD01B_ADC1_AIN15 _L_(1) +#define PINMUX_PD01B_ADC1_AIN15 ((PIN_PD01B_ADC1_AIN15 << 16) | MUX_PD01B_ADC1_AIN15) +#define PORT_PD01B_ADC1_AIN15 (_UL_(1) << 1) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 _L_(1) +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) +#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 _L_(1) +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) +/* ========== PORT definition for I2S peripheral ========== */ +#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ +#define MUX_PA09J_I2S_FS0 _L_(9) +#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) +#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) +#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ +#define MUX_PA20J_I2S_FS0 _L_(9) +#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) +#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) +#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ +#define MUX_PA23J_I2S_FS1 _L_(9) +#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) +#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) +#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ +#define MUX_PB11J_I2S_FS1 _L_(9) +#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) +#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) +#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ +#define MUX_PA08J_I2S_MCK0 _L_(9) +#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) +#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) +#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ +#define MUX_PB17J_I2S_MCK0 _L_(9) +#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) +#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) +#define PIN_PB29J_I2S_MCK1 _L_(61) /**< \brief I2S signal: MCK1 on PB29 mux J */ +#define MUX_PB29J_I2S_MCK1 _L_(9) +#define PINMUX_PB29J_I2S_MCK1 ((PIN_PB29J_I2S_MCK1 << 16) | MUX_PB29J_I2S_MCK1) +#define PORT_PB29J_I2S_MCK1 (_UL_(1) << 29) +#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ +#define MUX_PB13J_I2S_MCK1 _L_(9) +#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) +#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) +#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ +#define MUX_PA10J_I2S_SCK0 _L_(9) +#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) +#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) +#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ +#define MUX_PB16J_I2S_SCK0 _L_(9) +#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) +#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) +#define PIN_PB28J_I2S_SCK1 _L_(60) /**< \brief I2S signal: SCK1 on PB28 mux J */ +#define MUX_PB28J_I2S_SCK1 _L_(9) +#define PINMUX_PB28J_I2S_SCK1 ((PIN_PB28J_I2S_SCK1 << 16) | MUX_PB28J_I2S_SCK1) +#define PORT_PB28J_I2S_SCK1 (_UL_(1) << 28) +#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ +#define MUX_PB12J_I2S_SCK1 _L_(9) +#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) +#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) +#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ +#define MUX_PA22J_I2S_SDI _L_(9) +#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) +#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) +#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ +#define MUX_PB10J_I2S_SDI _L_(9) +#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) +#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) +#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ +#define MUX_PA11J_I2S_SDO _L_(9) +#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) +#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) +#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ +#define MUX_PA21J_I2S_SDO _L_(9) +#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) +#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) +/* ========== PORT definition for PCC peripheral ========== */ +#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ +#define MUX_PA14K_PCC_CLK _L_(10) +#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) +#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) +#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ +#define MUX_PA16K_PCC_DATA0 _L_(10) +#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) +#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) +#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ +#define MUX_PA17K_PCC_DATA1 _L_(10) +#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) +#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) +#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ +#define MUX_PA18K_PCC_DATA2 _L_(10) +#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) +#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) +#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ +#define MUX_PA19K_PCC_DATA3 _L_(10) +#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) +#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) +#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ +#define MUX_PA20K_PCC_DATA4 _L_(10) +#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) +#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) +#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ +#define MUX_PA21K_PCC_DATA5 _L_(10) +#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) +#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) +#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ +#define MUX_PA22K_PCC_DATA6 _L_(10) +#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) +#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) +#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ +#define MUX_PA23K_PCC_DATA7 _L_(10) +#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) +#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) +#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ +#define MUX_PB14K_PCC_DATA8 _L_(10) +#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) +#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) +#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ +#define MUX_PB15K_PCC_DATA9 _L_(10) +#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) +#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) +#define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */ +#define MUX_PC12K_PCC_DATA10 _L_(10) +#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) +#define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12) +#define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */ +#define MUX_PC13K_PCC_DATA11 _L_(10) +#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) +#define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13) +#define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */ +#define MUX_PC14K_PCC_DATA12 _L_(10) +#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) +#define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14) +#define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */ +#define MUX_PC15K_PCC_DATA13 _L_(10) +#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) +#define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15) +#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ +#define MUX_PA12K_PCC_DEN1 _L_(10) +#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) +#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) +#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ +#define MUX_PA13K_PCC_DEN2 _L_(10) +#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) +#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) +/* ========== PORT definition for SDHC0 peripheral ========== */ +#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ +#define MUX_PA06I_SDHC0_SDCD _L_(8) +#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) +#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ +#define MUX_PA12I_SDHC0_SDCD _L_(8) +#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) +#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ +#define MUX_PB12I_SDHC0_SDCD _L_(8) +#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) +#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */ +#define MUX_PC06I_SDHC0_SDCD _L_(8) +#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) +#define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ +#define MUX_PB11I_SDHC0_SDCK _L_(8) +#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) +#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) +#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ +#define MUX_PA08I_SDHC0_SDCMD _L_(8) +#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) +#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) +#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ +#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) +#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) +#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) +#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ +#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) +#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) +#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) +#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ +#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) +#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) +#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) +#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ +#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) +#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) +#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) +#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ +#define MUX_PA07I_SDHC0_SDWP _L_(8) +#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) +#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) +#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ +#define MUX_PA13I_SDHC0_SDWP _L_(8) +#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) +#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ +#define MUX_PB13I_SDHC0_SDWP _L_(8) +#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) +#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */ +#define MUX_PC07I_SDHC0_SDWP _L_(8) +#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) +#define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7) +/* ========== PORT definition for SDHC1 peripheral ========== */ +#define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */ +#define MUX_PB16I_SDHC1_SDCD _L_(8) +#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) +#define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16) +#define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */ +#define MUX_PC20I_SDHC1_SDCD _L_(8) +#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) +#define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20) +#define PIN_PD20I_SDHC1_SDCD _L_(116) /**< \brief SDHC1 signal: SDCD on PD20 mux I */ +#define MUX_PD20I_SDHC1_SDCD _L_(8) +#define PINMUX_PD20I_SDHC1_SDCD ((PIN_PD20I_SDHC1_SDCD << 16) | MUX_PD20I_SDHC1_SDCD) +#define PORT_PD20I_SDHC1_SDCD (_UL_(1) << 20) +#define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */ +#define MUX_PA21I_SDHC1_SDCK _L_(8) +#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) +#define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21) +#define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */ +#define MUX_PA20I_SDHC1_SDCMD _L_(8) +#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) +#define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20) +#define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */ +#define MUX_PB18I_SDHC1_SDDAT0 _L_(8) +#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) +#define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18) +#define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */ +#define MUX_PB19I_SDHC1_SDDAT1 _L_(8) +#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) +#define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19) +#define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */ +#define MUX_PB20I_SDHC1_SDDAT2 _L_(8) +#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) +#define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20) +#define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */ +#define MUX_PB21I_SDHC1_SDDAT3 _L_(8) +#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) +#define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21) +#define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */ +#define MUX_PB17I_SDHC1_SDWP _L_(8) +#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) +#define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17) +#define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */ +#define MUX_PC21I_SDHC1_SDWP _L_(8) +#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) +#define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21) +#define PIN_PD21I_SDHC1_SDWP _L_(117) /**< \brief SDHC1 signal: SDWP on PD21 mux I */ +#define MUX_PD21I_SDHC1_SDWP _L_(8) +#define PINMUX_PD21I_SDHC1_SDWP ((PIN_PD21I_SDHC1_SDWP << 16) | MUX_PD21I_SDHC1_SDWP) +#define PORT_PD21I_SDHC1_SDWP (_UL_(1) << 21) + +#endif /* _SAME54P19A_PIO_ */ diff --git a/software/firmware/oracle_same54n19a/include/pio/same54p20a.h b/software/firmware/oracle_same54n19a/include/pio/same54p20a.h new file mode 100644 index 00000000..cc046809 --- /dev/null +++ b/software/firmware/oracle_same54n19a/include/pio/same54p20a.h @@ -0,0 +1,3010 @@ +/** + * \file + * + * \brief Peripheral I/O description for SAME54P20A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54P20A_PIO_ +#define _SAME54P20A_PIO_ + +#define PIN_PA00 0 /**< \brief Pin Number for PA00 */ +#define PORT_PA00 (_UL_(1) << 0) /**< \brief PORT Mask for PA00 */ +#define PIN_PA01 1 /**< \brief Pin Number for PA01 */ +#define PORT_PA01 (_UL_(1) << 1) /**< \brief PORT Mask for PA01 */ +#define PIN_PA02 2 /**< \brief Pin Number for PA02 */ +#define PORT_PA02 (_UL_(1) << 2) /**< \brief PORT Mask for PA02 */ +#define PIN_PA03 3 /**< \brief Pin Number for PA03 */ +#define PORT_PA03 (_UL_(1) << 3) /**< \brief PORT Mask for PA03 */ +#define PIN_PA04 4 /**< \brief Pin Number for PA04 */ +#define PORT_PA04 (_UL_(1) << 4) /**< \brief PORT Mask for PA04 */ +#define PIN_PA05 5 /**< \brief Pin Number for PA05 */ +#define PORT_PA05 (_UL_(1) << 5) /**< \brief PORT Mask for PA05 */ +#define PIN_PA06 6 /**< \brief Pin Number for PA06 */ +#define PORT_PA06 (_UL_(1) << 6) /**< \brief PORT Mask for PA06 */ +#define PIN_PA07 7 /**< \brief Pin Number for PA07 */ +#define PORT_PA07 (_UL_(1) << 7) /**< \brief PORT Mask for PA07 */ +#define PIN_PA08 8 /**< \brief Pin Number for PA08 */ +#define PORT_PA08 (_UL_(1) << 8) /**< \brief PORT Mask for PA08 */ +#define PIN_PA09 9 /**< \brief Pin Number for PA09 */ +#define PORT_PA09 (_UL_(1) << 9) /**< \brief PORT Mask for PA09 */ +#define PIN_PA10 10 /**< \brief Pin Number for PA10 */ +#define PORT_PA10 (_UL_(1) << 10) /**< \brief PORT Mask for PA10 */ +#define PIN_PA11 11 /**< \brief Pin Number for PA11 */ +#define PORT_PA11 (_UL_(1) << 11) /**< \brief PORT Mask for PA11 */ +#define PIN_PA12 12 /**< \brief Pin Number for PA12 */ +#define PORT_PA12 (_UL_(1) << 12) /**< \brief PORT Mask for PA12 */ +#define PIN_PA13 13 /**< \brief Pin Number for PA13 */ +#define PORT_PA13 (_UL_(1) << 13) /**< \brief PORT Mask for PA13 */ +#define PIN_PA14 14 /**< \brief Pin Number for PA14 */ +#define PORT_PA14 (_UL_(1) << 14) /**< \brief PORT Mask for PA14 */ +#define PIN_PA15 15 /**< \brief Pin Number for PA15 */ +#define PORT_PA15 (_UL_(1) << 15) /**< \brief PORT Mask for PA15 */ +#define PIN_PA16 16 /**< \brief Pin Number for PA16 */ +#define PORT_PA16 (_UL_(1) << 16) /**< \brief PORT Mask for PA16 */ +#define PIN_PA17 17 /**< \brief Pin Number for PA17 */ +#define PORT_PA17 (_UL_(1) << 17) /**< \brief PORT Mask for PA17 */ +#define PIN_PA18 18 /**< \brief Pin Number for PA18 */ +#define PORT_PA18 (_UL_(1) << 18) /**< \brief PORT Mask for PA18 */ +#define PIN_PA19 19 /**< \brief Pin Number for PA19 */ +#define PORT_PA19 (_UL_(1) << 19) /**< \brief PORT Mask for PA19 */ +#define PIN_PA20 20 /**< \brief Pin Number for PA20 */ +#define PORT_PA20 (_UL_(1) << 20) /**< \brief PORT Mask for PA20 */ +#define PIN_PA21 21 /**< \brief Pin Number for PA21 */ +#define PORT_PA21 (_UL_(1) << 21) /**< \brief PORT Mask for PA21 */ +#define PIN_PA22 22 /**< \brief Pin Number for PA22 */ +#define PORT_PA22 (_UL_(1) << 22) /**< \brief PORT Mask for PA22 */ +#define PIN_PA23 23 /**< \brief Pin Number for PA23 */ +#define PORT_PA23 (_UL_(1) << 23) /**< \brief PORT Mask for PA23 */ +#define PIN_PA24 24 /**< \brief Pin Number for PA24 */ +#define PORT_PA24 (_UL_(1) << 24) /**< \brief PORT Mask for PA24 */ +#define PIN_PA25 25 /**< \brief Pin Number for PA25 */ +#define PORT_PA25 (_UL_(1) << 25) /**< \brief PORT Mask for PA25 */ +#define PIN_PA27 27 /**< \brief Pin Number for PA27 */ +#define PORT_PA27 (_UL_(1) << 27) /**< \brief PORT Mask for PA27 */ +#define PIN_PA30 30 /**< \brief Pin Number for PA30 */ +#define PORT_PA30 (_UL_(1) << 30) /**< \brief PORT Mask for PA30 */ +#define PIN_PA31 31 /**< \brief Pin Number for PA31 */ +#define PORT_PA31 (_UL_(1) << 31) /**< \brief PORT Mask for PA31 */ +#define PIN_PB00 32 /**< \brief Pin Number for PB00 */ +#define PORT_PB00 (_UL_(1) << 0) /**< \brief PORT Mask for PB00 */ +#define PIN_PB01 33 /**< \brief Pin Number for PB01 */ +#define PORT_PB01 (_UL_(1) << 1) /**< \brief PORT Mask for PB01 */ +#define PIN_PB02 34 /**< \brief Pin Number for PB02 */ +#define PORT_PB02 (_UL_(1) << 2) /**< \brief PORT Mask for PB02 */ +#define PIN_PB03 35 /**< \brief Pin Number for PB03 */ +#define PORT_PB03 (_UL_(1) << 3) /**< \brief PORT Mask for PB03 */ +#define PIN_PB04 36 /**< \brief Pin Number for PB04 */ +#define PORT_PB04 (_UL_(1) << 4) /**< \brief PORT Mask for PB04 */ +#define PIN_PB05 37 /**< \brief Pin Number for PB05 */ +#define PORT_PB05 (_UL_(1) << 5) /**< \brief PORT Mask for PB05 */ +#define PIN_PB06 38 /**< \brief Pin Number for PB06 */ +#define PORT_PB06 (_UL_(1) << 6) /**< \brief PORT Mask for PB06 */ +#define PIN_PB07 39 /**< \brief Pin Number for PB07 */ +#define PORT_PB07 (_UL_(1) << 7) /**< \brief PORT Mask for PB07 */ +#define PIN_PB08 40 /**< \brief Pin Number for PB08 */ +#define PORT_PB08 (_UL_(1) << 8) /**< \brief PORT Mask for PB08 */ +#define PIN_PB09 41 /**< \brief Pin Number for PB09 */ +#define PORT_PB09 (_UL_(1) << 9) /**< \brief PORT Mask for PB09 */ +#define PIN_PB10 42 /**< \brief Pin Number for PB10 */ +#define PORT_PB10 (_UL_(1) << 10) /**< \brief PORT Mask for PB10 */ +#define PIN_PB11 43 /**< \brief Pin Number for PB11 */ +#define PORT_PB11 (_UL_(1) << 11) /**< \brief PORT Mask for PB11 */ +#define PIN_PB12 44 /**< \brief Pin Number for PB12 */ +#define PORT_PB12 (_UL_(1) << 12) /**< \brief PORT Mask for PB12 */ +#define PIN_PB13 45 /**< \brief Pin Number for PB13 */ +#define PORT_PB13 (_UL_(1) << 13) /**< \brief PORT Mask for PB13 */ +#define PIN_PB14 46 /**< \brief Pin Number for PB14 */ +#define PORT_PB14 (_UL_(1) << 14) /**< \brief PORT Mask for PB14 */ +#define PIN_PB15 47 /**< \brief Pin Number for PB15 */ +#define PORT_PB15 (_UL_(1) << 15) /**< \brief PORT Mask for PB15 */ +#define PIN_PB16 48 /**< \brief Pin Number for PB16 */ +#define PORT_PB16 (_UL_(1) << 16) /**< \brief PORT Mask for PB16 */ +#define PIN_PB17 49 /**< \brief Pin Number for PB17 */ +#define PORT_PB17 (_UL_(1) << 17) /**< \brief PORT Mask for PB17 */ +#define PIN_PB18 50 /**< \brief Pin Number for PB18 */ +#define PORT_PB18 (_UL_(1) << 18) /**< \brief PORT Mask for PB18 */ +#define PIN_PB19 51 /**< \brief Pin Number for PB19 */ +#define PORT_PB19 (_UL_(1) << 19) /**< \brief PORT Mask for PB19 */ +#define PIN_PB20 52 /**< \brief Pin Number for PB20 */ +#define PORT_PB20 (_UL_(1) << 20) /**< \brief PORT Mask for PB20 */ +#define PIN_PB21 53 /**< \brief Pin Number for PB21 */ +#define PORT_PB21 (_UL_(1) << 21) /**< \brief PORT Mask for PB21 */ +#define PIN_PB22 54 /**< \brief Pin Number for PB22 */ +#define PORT_PB22 (_UL_(1) << 22) /**< \brief PORT Mask for PB22 */ +#define PIN_PB23 55 /**< \brief Pin Number for PB23 */ +#define PORT_PB23 (_UL_(1) << 23) /**< \brief PORT Mask for PB23 */ +#define PIN_PB24 56 /**< \brief Pin Number for PB24 */ +#define PORT_PB24 (_UL_(1) << 24) /**< \brief PORT Mask for PB24 */ +#define PIN_PB25 57 /**< \brief Pin Number for PB25 */ +#define PORT_PB25 (_UL_(1) << 25) /**< \brief PORT Mask for PB25 */ +#define PIN_PB26 58 /**< \brief Pin Number for PB26 */ +#define PORT_PB26 (_UL_(1) << 26) /**< \brief PORT Mask for PB26 */ +#define PIN_PB27 59 /**< \brief Pin Number for PB27 */ +#define PORT_PB27 (_UL_(1) << 27) /**< \brief PORT Mask for PB27 */ +#define PIN_PB28 60 /**< \brief Pin Number for PB28 */ +#define PORT_PB28 (_UL_(1) << 28) /**< \brief PORT Mask for PB28 */ +#define PIN_PB29 61 /**< \brief Pin Number for PB29 */ +#define PORT_PB29 (_UL_(1) << 29) /**< \brief PORT Mask for PB29 */ +#define PIN_PB30 62 /**< \brief Pin Number for PB30 */ +#define PORT_PB30 (_UL_(1) << 30) /**< \brief PORT Mask for PB30 */ +#define PIN_PB31 63 /**< \brief Pin Number for PB31 */ +#define PORT_PB31 (_UL_(1) << 31) /**< \brief PORT Mask for PB31 */ +#define PIN_PC00 64 /**< \brief Pin Number for PC00 */ +#define PORT_PC00 (_UL_(1) << 0) /**< \brief PORT Mask for PC00 */ +#define PIN_PC01 65 /**< \brief Pin Number for PC01 */ +#define PORT_PC01 (_UL_(1) << 1) /**< \brief PORT Mask for PC01 */ +#define PIN_PC02 66 /**< \brief Pin Number for PC02 */ +#define PORT_PC02 (_UL_(1) << 2) /**< \brief PORT Mask for PC02 */ +#define PIN_PC03 67 /**< \brief Pin Number for PC03 */ +#define PORT_PC03 (_UL_(1) << 3) /**< \brief PORT Mask for PC03 */ +#define PIN_PC04 68 /**< \brief Pin Number for PC04 */ +#define PORT_PC04 (_UL_(1) << 4) /**< \brief PORT Mask for PC04 */ +#define PIN_PC05 69 /**< \brief Pin Number for PC05 */ +#define PORT_PC05 (_UL_(1) << 5) /**< \brief PORT Mask for PC05 */ +#define PIN_PC06 70 /**< \brief Pin Number for PC06 */ +#define PORT_PC06 (_UL_(1) << 6) /**< \brief PORT Mask for PC06 */ +#define PIN_PC07 71 /**< \brief Pin Number for PC07 */ +#define PORT_PC07 (_UL_(1) << 7) /**< \brief PORT Mask for PC07 */ +#define PIN_PC10 74 /**< \brief Pin Number for PC10 */ +#define PORT_PC10 (_UL_(1) << 10) /**< \brief PORT Mask for PC10 */ +#define PIN_PC11 75 /**< \brief Pin Number for PC11 */ +#define PORT_PC11 (_UL_(1) << 11) /**< \brief PORT Mask for PC11 */ +#define PIN_PC12 76 /**< \brief Pin Number for PC12 */ +#define PORT_PC12 (_UL_(1) << 12) /**< \brief PORT Mask for PC12 */ +#define PIN_PC13 77 /**< \brief Pin Number for PC13 */ +#define PORT_PC13 (_UL_(1) << 13) /**< \brief PORT Mask for PC13 */ +#define PIN_PC14 78 /**< \brief Pin Number for PC14 */ +#define PORT_PC14 (_UL_(1) << 14) /**< \brief PORT Mask for PC14 */ +#define PIN_PC15 79 /**< \brief Pin Number for PC15 */ +#define PORT_PC15 (_UL_(1) << 15) /**< \brief PORT Mask for PC15 */ +#define PIN_PC16 80 /**< \brief Pin Number for PC16 */ +#define PORT_PC16 (_UL_(1) << 16) /**< \brief PORT Mask for PC16 */ +#define PIN_PC17 81 /**< \brief Pin Number for PC17 */ +#define PORT_PC17 (_UL_(1) << 17) /**< \brief PORT Mask for PC17 */ +#define PIN_PC18 82 /**< \brief Pin Number for PC18 */ +#define PORT_PC18 (_UL_(1) << 18) /**< \brief PORT Mask for PC18 */ +#define PIN_PC19 83 /**< \brief Pin Number for PC19 */ +#define PORT_PC19 (_UL_(1) << 19) /**< \brief PORT Mask for PC19 */ +#define PIN_PC20 84 /**< \brief Pin Number for PC20 */ +#define PORT_PC20 (_UL_(1) << 20) /**< \brief PORT Mask for PC20 */ +#define PIN_PC21 85 /**< \brief Pin Number for PC21 */ +#define PORT_PC21 (_UL_(1) << 21) /**< \brief PORT Mask for PC21 */ +#define PIN_PC22 86 /**< \brief Pin Number for PC22 */ +#define PORT_PC22 (_UL_(1) << 22) /**< \brief PORT Mask for PC22 */ +#define PIN_PC23 87 /**< \brief Pin Number for PC23 */ +#define PORT_PC23 (_UL_(1) << 23) /**< \brief PORT Mask for PC23 */ +#define PIN_PC24 88 /**< \brief Pin Number for PC24 */ +#define PORT_PC24 (_UL_(1) << 24) /**< \brief PORT Mask for PC24 */ +#define PIN_PC25 89 /**< \brief Pin Number for PC25 */ +#define PORT_PC25 (_UL_(1) << 25) /**< \brief PORT Mask for PC25 */ +#define PIN_PC26 90 /**< \brief Pin Number for PC26 */ +#define PORT_PC26 (_UL_(1) << 26) /**< \brief PORT Mask for PC26 */ +#define PIN_PC27 91 /**< \brief Pin Number for PC27 */ +#define PORT_PC27 (_UL_(1) << 27) /**< \brief PORT Mask for PC27 */ +#define PIN_PC28 92 /**< \brief Pin Number for PC28 */ +#define PORT_PC28 (_UL_(1) << 28) /**< \brief PORT Mask for PC28 */ +#define PIN_PC30 94 /**< \brief Pin Number for PC30 */ +#define PORT_PC30 (_UL_(1) << 30) /**< \brief PORT Mask for PC30 */ +#define PIN_PC31 95 /**< \brief Pin Number for PC31 */ +#define PORT_PC31 (_UL_(1) << 31) /**< \brief PORT Mask for PC31 */ +#define PIN_PD00 96 /**< \brief Pin Number for PD00 */ +#define PORT_PD00 (_UL_(1) << 0) /**< \brief PORT Mask for PD00 */ +#define PIN_PD01 97 /**< \brief Pin Number for PD01 */ +#define PORT_PD01 (_UL_(1) << 1) /**< \brief PORT Mask for PD01 */ +#define PIN_PD08 104 /**< \brief Pin Number for PD08 */ +#define PORT_PD08 (_UL_(1) << 8) /**< \brief PORT Mask for PD08 */ +#define PIN_PD09 105 /**< \brief Pin Number for PD09 */ +#define PORT_PD09 (_UL_(1) << 9) /**< \brief PORT Mask for PD09 */ +#define PIN_PD10 106 /**< \brief Pin Number for PD10 */ +#define PORT_PD10 (_UL_(1) << 10) /**< \brief PORT Mask for PD10 */ +#define PIN_PD11 107 /**< \brief Pin Number for PD11 */ +#define PORT_PD11 (_UL_(1) << 11) /**< \brief PORT Mask for PD11 */ +#define PIN_PD12 108 /**< \brief Pin Number for PD12 */ +#define PORT_PD12 (_UL_(1) << 12) /**< \brief PORT Mask for PD12 */ +#define PIN_PD20 116 /**< \brief Pin Number for PD20 */ +#define PORT_PD20 (_UL_(1) << 20) /**< \brief PORT Mask for PD20 */ +#define PIN_PD21 117 /**< \brief Pin Number for PD21 */ +#define PORT_PD21 (_UL_(1) << 21) /**< \brief PORT Mask for PD21 */ +/* ========== PORT definition for CM4 peripheral ========== */ +#define PIN_PA30H_CM4_SWCLK _L_(30) /**< \brief CM4 signal: SWCLK on PA30 mux H */ +#define MUX_PA30H_CM4_SWCLK _L_(7) +#define PINMUX_PA30H_CM4_SWCLK ((PIN_PA30H_CM4_SWCLK << 16) | MUX_PA30H_CM4_SWCLK) +#define PORT_PA30H_CM4_SWCLK (_UL_(1) << 30) +#define PIN_PC27M_CM4_SWO _L_(91) /**< \brief CM4 signal: SWO on PC27 mux M */ +#define MUX_PC27M_CM4_SWO _L_(12) +#define PINMUX_PC27M_CM4_SWO ((PIN_PC27M_CM4_SWO << 16) | MUX_PC27M_CM4_SWO) +#define PORT_PC27M_CM4_SWO (_UL_(1) << 27) +#define PIN_PB30H_CM4_SWO _L_(62) /**< \brief CM4 signal: SWO on PB30 mux H */ +#define MUX_PB30H_CM4_SWO _L_(7) +#define PINMUX_PB30H_CM4_SWO ((PIN_PB30H_CM4_SWO << 16) | MUX_PB30H_CM4_SWO) +#define PORT_PB30H_CM4_SWO (_UL_(1) << 30) +#define PIN_PC27H_CM4_TRACECLK _L_(91) /**< \brief CM4 signal: TRACECLK on PC27 mux H */ +#define MUX_PC27H_CM4_TRACECLK _L_(7) +#define PINMUX_PC27H_CM4_TRACECLK ((PIN_PC27H_CM4_TRACECLK << 16) | MUX_PC27H_CM4_TRACECLK) +#define PORT_PC27H_CM4_TRACECLK (_UL_(1) << 27) +#define PIN_PC28H_CM4_TRACEDATA0 _L_(92) /**< \brief CM4 signal: TRACEDATA0 on PC28 mux H */ +#define MUX_PC28H_CM4_TRACEDATA0 _L_(7) +#define PINMUX_PC28H_CM4_TRACEDATA0 ((PIN_PC28H_CM4_TRACEDATA0 << 16) | MUX_PC28H_CM4_TRACEDATA0) +#define PORT_PC28H_CM4_TRACEDATA0 (_UL_(1) << 28) +#define PIN_PC26H_CM4_TRACEDATA1 _L_(90) /**< \brief CM4 signal: TRACEDATA1 on PC26 mux H */ +#define MUX_PC26H_CM4_TRACEDATA1 _L_(7) +#define PINMUX_PC26H_CM4_TRACEDATA1 ((PIN_PC26H_CM4_TRACEDATA1 << 16) | MUX_PC26H_CM4_TRACEDATA1) +#define PORT_PC26H_CM4_TRACEDATA1 (_UL_(1) << 26) +#define PIN_PC25H_CM4_TRACEDATA2 _L_(89) /**< \brief CM4 signal: TRACEDATA2 on PC25 mux H */ +#define MUX_PC25H_CM4_TRACEDATA2 _L_(7) +#define PINMUX_PC25H_CM4_TRACEDATA2 ((PIN_PC25H_CM4_TRACEDATA2 << 16) | MUX_PC25H_CM4_TRACEDATA2) +#define PORT_PC25H_CM4_TRACEDATA2 (_UL_(1) << 25) +#define PIN_PC24H_CM4_TRACEDATA3 _L_(88) /**< \brief CM4 signal: TRACEDATA3 on PC24 mux H */ +#define MUX_PC24H_CM4_TRACEDATA3 _L_(7) +#define PINMUX_PC24H_CM4_TRACEDATA3 ((PIN_PC24H_CM4_TRACEDATA3 << 16) | MUX_PC24H_CM4_TRACEDATA3) +#define PORT_PC24H_CM4_TRACEDATA3 (_UL_(1) << 24) +/* ========== PORT definition for ANAREF peripheral ========== */ +#define PIN_PA03B_ANAREF_VREF0 _L_(3) /**< \brief ANAREF signal: VREF0 on PA03 mux B */ +#define MUX_PA03B_ANAREF_VREF0 _L_(1) +#define PINMUX_PA03B_ANAREF_VREF0 ((PIN_PA03B_ANAREF_VREF0 << 16) | MUX_PA03B_ANAREF_VREF0) +#define PORT_PA03B_ANAREF_VREF0 (_UL_(1) << 3) +#define PIN_PA04B_ANAREF_VREF1 _L_(4) /**< \brief ANAREF signal: VREF1 on PA04 mux B */ +#define MUX_PA04B_ANAREF_VREF1 _L_(1) +#define PINMUX_PA04B_ANAREF_VREF1 ((PIN_PA04B_ANAREF_VREF1 << 16) | MUX_PA04B_ANAREF_VREF1) +#define PORT_PA04B_ANAREF_VREF1 (_UL_(1) << 4) +#define PIN_PA06B_ANAREF_VREF2 _L_(6) /**< \brief ANAREF signal: VREF2 on PA06 mux B */ +#define MUX_PA06B_ANAREF_VREF2 _L_(1) +#define PINMUX_PA06B_ANAREF_VREF2 ((PIN_PA06B_ANAREF_VREF2 << 16) | MUX_PA06B_ANAREF_VREF2) +#define PORT_PA06B_ANAREF_VREF2 (_UL_(1) << 6) +/* ========== PORT definition for GCLK peripheral ========== */ +#define PIN_PA30M_GCLK_IO0 _L_(30) /**< \brief GCLK signal: IO0 on PA30 mux M */ +#define MUX_PA30M_GCLK_IO0 _L_(12) +#define PINMUX_PA30M_GCLK_IO0 ((PIN_PA30M_GCLK_IO0 << 16) | MUX_PA30M_GCLK_IO0) +#define PORT_PA30M_GCLK_IO0 (_UL_(1) << 30) +#define PIN_PB14M_GCLK_IO0 _L_(46) /**< \brief GCLK signal: IO0 on PB14 mux M */ +#define MUX_PB14M_GCLK_IO0 _L_(12) +#define PINMUX_PB14M_GCLK_IO0 ((PIN_PB14M_GCLK_IO0 << 16) | MUX_PB14M_GCLK_IO0) +#define PORT_PB14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PA14M_GCLK_IO0 _L_(14) /**< \brief GCLK signal: IO0 on PA14 mux M */ +#define MUX_PA14M_GCLK_IO0 _L_(12) +#define PINMUX_PA14M_GCLK_IO0 ((PIN_PA14M_GCLK_IO0 << 16) | MUX_PA14M_GCLK_IO0) +#define PORT_PA14M_GCLK_IO0 (_UL_(1) << 14) +#define PIN_PB22M_GCLK_IO0 _L_(54) /**< \brief GCLK signal: IO0 on PB22 mux M */ +#define MUX_PB22M_GCLK_IO0 _L_(12) +#define PINMUX_PB22M_GCLK_IO0 ((PIN_PB22M_GCLK_IO0 << 16) | MUX_PB22M_GCLK_IO0) +#define PORT_PB22M_GCLK_IO0 (_UL_(1) << 22) +#define PIN_PB15M_GCLK_IO1 _L_(47) /**< \brief GCLK signal: IO1 on PB15 mux M */ +#define MUX_PB15M_GCLK_IO1 _L_(12) +#define PINMUX_PB15M_GCLK_IO1 ((PIN_PB15M_GCLK_IO1 << 16) | MUX_PB15M_GCLK_IO1) +#define PORT_PB15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PA15M_GCLK_IO1 _L_(15) /**< \brief GCLK signal: IO1 on PA15 mux M */ +#define MUX_PA15M_GCLK_IO1 _L_(12) +#define PINMUX_PA15M_GCLK_IO1 ((PIN_PA15M_GCLK_IO1 << 16) | MUX_PA15M_GCLK_IO1) +#define PORT_PA15M_GCLK_IO1 (_UL_(1) << 15) +#define PIN_PB23M_GCLK_IO1 _L_(55) /**< \brief GCLK signal: IO1 on PB23 mux M */ +#define MUX_PB23M_GCLK_IO1 _L_(12) +#define PINMUX_PB23M_GCLK_IO1 ((PIN_PB23M_GCLK_IO1 << 16) | MUX_PB23M_GCLK_IO1) +#define PORT_PB23M_GCLK_IO1 (_UL_(1) << 23) +#define PIN_PA27M_GCLK_IO1 _L_(27) /**< \brief GCLK signal: IO1 on PA27 mux M */ +#define MUX_PA27M_GCLK_IO1 _L_(12) +#define PINMUX_PA27M_GCLK_IO1 ((PIN_PA27M_GCLK_IO1 << 16) | MUX_PA27M_GCLK_IO1) +#define PORT_PA27M_GCLK_IO1 (_UL_(1) << 27) +#define PIN_PA16M_GCLK_IO2 _L_(16) /**< \brief GCLK signal: IO2 on PA16 mux M */ +#define MUX_PA16M_GCLK_IO2 _L_(12) +#define PINMUX_PA16M_GCLK_IO2 ((PIN_PA16M_GCLK_IO2 << 16) | MUX_PA16M_GCLK_IO2) +#define PORT_PA16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PB16M_GCLK_IO2 _L_(48) /**< \brief GCLK signal: IO2 on PB16 mux M */ +#define MUX_PB16M_GCLK_IO2 _L_(12) +#define PINMUX_PB16M_GCLK_IO2 ((PIN_PB16M_GCLK_IO2 << 16) | MUX_PB16M_GCLK_IO2) +#define PORT_PB16M_GCLK_IO2 (_UL_(1) << 16) +#define PIN_PA17M_GCLK_IO3 _L_(17) /**< \brief GCLK signal: IO3 on PA17 mux M */ +#define MUX_PA17M_GCLK_IO3 _L_(12) +#define PINMUX_PA17M_GCLK_IO3 ((PIN_PA17M_GCLK_IO3 << 16) | MUX_PA17M_GCLK_IO3) +#define PORT_PA17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PB17M_GCLK_IO3 _L_(49) /**< \brief GCLK signal: IO3 on PB17 mux M */ +#define MUX_PB17M_GCLK_IO3 _L_(12) +#define PINMUX_PB17M_GCLK_IO3 ((PIN_PB17M_GCLK_IO3 << 16) | MUX_PB17M_GCLK_IO3) +#define PORT_PB17M_GCLK_IO3 (_UL_(1) << 17) +#define PIN_PA10M_GCLK_IO4 _L_(10) /**< \brief GCLK signal: IO4 on PA10 mux M */ +#define MUX_PA10M_GCLK_IO4 _L_(12) +#define PINMUX_PA10M_GCLK_IO4 ((PIN_PA10M_GCLK_IO4 << 16) | MUX_PA10M_GCLK_IO4) +#define PORT_PA10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB10M_GCLK_IO4 _L_(42) /**< \brief GCLK signal: IO4 on PB10 mux M */ +#define MUX_PB10M_GCLK_IO4 _L_(12) +#define PINMUX_PB10M_GCLK_IO4 ((PIN_PB10M_GCLK_IO4 << 16) | MUX_PB10M_GCLK_IO4) +#define PORT_PB10M_GCLK_IO4 (_UL_(1) << 10) +#define PIN_PB18M_GCLK_IO4 _L_(50) /**< \brief GCLK signal: IO4 on PB18 mux M */ +#define MUX_PB18M_GCLK_IO4 _L_(12) +#define PINMUX_PB18M_GCLK_IO4 ((PIN_PB18M_GCLK_IO4 << 16) | MUX_PB18M_GCLK_IO4) +#define PORT_PB18M_GCLK_IO4 (_UL_(1) << 18) +#define PIN_PA11M_GCLK_IO5 _L_(11) /**< \brief GCLK signal: IO5 on PA11 mux M */ +#define MUX_PA11M_GCLK_IO5 _L_(12) +#define PINMUX_PA11M_GCLK_IO5 ((PIN_PA11M_GCLK_IO5 << 16) | MUX_PA11M_GCLK_IO5) +#define PORT_PA11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB11M_GCLK_IO5 _L_(43) /**< \brief GCLK signal: IO5 on PB11 mux M */ +#define MUX_PB11M_GCLK_IO5 _L_(12) +#define PINMUX_PB11M_GCLK_IO5 ((PIN_PB11M_GCLK_IO5 << 16) | MUX_PB11M_GCLK_IO5) +#define PORT_PB11M_GCLK_IO5 (_UL_(1) << 11) +#define PIN_PB19M_GCLK_IO5 _L_(51) /**< \brief GCLK signal: IO5 on PB19 mux M */ +#define MUX_PB19M_GCLK_IO5 _L_(12) +#define PINMUX_PB19M_GCLK_IO5 ((PIN_PB19M_GCLK_IO5 << 16) | MUX_PB19M_GCLK_IO5) +#define PORT_PB19M_GCLK_IO5 (_UL_(1) << 19) +#define PIN_PB12M_GCLK_IO6 _L_(44) /**< \brief GCLK signal: IO6 on PB12 mux M */ +#define MUX_PB12M_GCLK_IO6 _L_(12) +#define PINMUX_PB12M_GCLK_IO6 ((PIN_PB12M_GCLK_IO6 << 16) | MUX_PB12M_GCLK_IO6) +#define PORT_PB12M_GCLK_IO6 (_UL_(1) << 12) +#define PIN_PB20M_GCLK_IO6 _L_(52) /**< \brief GCLK signal: IO6 on PB20 mux M */ +#define MUX_PB20M_GCLK_IO6 _L_(12) +#define PINMUX_PB20M_GCLK_IO6 ((PIN_PB20M_GCLK_IO6 << 16) | MUX_PB20M_GCLK_IO6) +#define PORT_PB20M_GCLK_IO6 (_UL_(1) << 20) +#define PIN_PB13M_GCLK_IO7 _L_(45) /**< \brief GCLK signal: IO7 on PB13 mux M */ +#define MUX_PB13M_GCLK_IO7 _L_(12) +#define PINMUX_PB13M_GCLK_IO7 ((PIN_PB13M_GCLK_IO7 << 16) | MUX_PB13M_GCLK_IO7) +#define PORT_PB13M_GCLK_IO7 (_UL_(1) << 13) +#define PIN_PB21M_GCLK_IO7 _L_(53) /**< \brief GCLK signal: IO7 on PB21 mux M */ +#define MUX_PB21M_GCLK_IO7 _L_(12) +#define PINMUX_PB21M_GCLK_IO7 ((PIN_PB21M_GCLK_IO7 << 16) | MUX_PB21M_GCLK_IO7) +#define PORT_PB21M_GCLK_IO7 (_UL_(1) << 21) +/* ========== PORT definition for EIC peripheral ========== */ +#define PIN_PA00A_EIC_EXTINT0 _L_(0) /**< \brief EIC signal: EXTINT0 on PA00 mux A */ +#define MUX_PA00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA00A_EIC_EXTINT0 ((PIN_PA00A_EIC_EXTINT0 << 16) | MUX_PA00A_EIC_EXTINT0) +#define PORT_PA00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PA00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA00 External Interrupt Line */ +#define PIN_PA16A_EIC_EXTINT0 _L_(16) /**< \brief EIC signal: EXTINT0 on PA16 mux A */ +#define MUX_PA16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PA16A_EIC_EXTINT0 ((PIN_PA16A_EIC_EXTINT0 << 16) | MUX_PA16A_EIC_EXTINT0) +#define PORT_PA16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PA16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PA16 External Interrupt Line */ +#define PIN_PB00A_EIC_EXTINT0 _L_(32) /**< \brief EIC signal: EXTINT0 on PB00 mux A */ +#define MUX_PB00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB00A_EIC_EXTINT0 ((PIN_PB00A_EIC_EXTINT0 << 16) | MUX_PB00A_EIC_EXTINT0) +#define PORT_PB00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PB00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB00 External Interrupt Line */ +#define PIN_PB16A_EIC_EXTINT0 _L_(48) /**< \brief EIC signal: EXTINT0 on PB16 mux A */ +#define MUX_PB16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PB16A_EIC_EXTINT0 ((PIN_PB16A_EIC_EXTINT0 << 16) | MUX_PB16A_EIC_EXTINT0) +#define PORT_PB16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PB16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PB16 External Interrupt Line */ +#define PIN_PC00A_EIC_EXTINT0 _L_(64) /**< \brief EIC signal: EXTINT0 on PC00 mux A */ +#define MUX_PC00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC00A_EIC_EXTINT0 ((PIN_PC00A_EIC_EXTINT0 << 16) | MUX_PC00A_EIC_EXTINT0) +#define PORT_PC00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PC00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC00 External Interrupt Line */ +#define PIN_PC16A_EIC_EXTINT0 _L_(80) /**< \brief EIC signal: EXTINT0 on PC16 mux A */ +#define MUX_PC16A_EIC_EXTINT0 _L_(0) +#define PINMUX_PC16A_EIC_EXTINT0 ((PIN_PC16A_EIC_EXTINT0 << 16) | MUX_PC16A_EIC_EXTINT0) +#define PORT_PC16A_EIC_EXTINT0 (_UL_(1) << 16) +#define PIN_PC16A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PC16 External Interrupt Line */ +#define PIN_PD00A_EIC_EXTINT0 _L_(96) /**< \brief EIC signal: EXTINT0 on PD00 mux A */ +#define MUX_PD00A_EIC_EXTINT0 _L_(0) +#define PINMUX_PD00A_EIC_EXTINT0 ((PIN_PD00A_EIC_EXTINT0 << 16) | MUX_PD00A_EIC_EXTINT0) +#define PORT_PD00A_EIC_EXTINT0 (_UL_(1) << 0) +#define PIN_PD00A_EIC_EXTINT_NUM _L_(0) /**< \brief EIC signal: PIN_PD00 External Interrupt Line */ +#define PIN_PA01A_EIC_EXTINT1 _L_(1) /**< \brief EIC signal: EXTINT1 on PA01 mux A */ +#define MUX_PA01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA01A_EIC_EXTINT1 ((PIN_PA01A_EIC_EXTINT1 << 16) | MUX_PA01A_EIC_EXTINT1) +#define PORT_PA01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PA01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA01 External Interrupt Line */ +#define PIN_PA17A_EIC_EXTINT1 _L_(17) /**< \brief EIC signal: EXTINT1 on PA17 mux A */ +#define MUX_PA17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PA17A_EIC_EXTINT1 ((PIN_PA17A_EIC_EXTINT1 << 16) | MUX_PA17A_EIC_EXTINT1) +#define PORT_PA17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PA17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PA17 External Interrupt Line */ +#define PIN_PB01A_EIC_EXTINT1 _L_(33) /**< \brief EIC signal: EXTINT1 on PB01 mux A */ +#define MUX_PB01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB01A_EIC_EXTINT1 ((PIN_PB01A_EIC_EXTINT1 << 16) | MUX_PB01A_EIC_EXTINT1) +#define PORT_PB01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PB01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB01 External Interrupt Line */ +#define PIN_PB17A_EIC_EXTINT1 _L_(49) /**< \brief EIC signal: EXTINT1 on PB17 mux A */ +#define MUX_PB17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PB17A_EIC_EXTINT1 ((PIN_PB17A_EIC_EXTINT1 << 16) | MUX_PB17A_EIC_EXTINT1) +#define PORT_PB17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PB17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PB17 External Interrupt Line */ +#define PIN_PC01A_EIC_EXTINT1 _L_(65) /**< \brief EIC signal: EXTINT1 on PC01 mux A */ +#define MUX_PC01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC01A_EIC_EXTINT1 ((PIN_PC01A_EIC_EXTINT1 << 16) | MUX_PC01A_EIC_EXTINT1) +#define PORT_PC01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PC01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC01 External Interrupt Line */ +#define PIN_PC17A_EIC_EXTINT1 _L_(81) /**< \brief EIC signal: EXTINT1 on PC17 mux A */ +#define MUX_PC17A_EIC_EXTINT1 _L_(0) +#define PINMUX_PC17A_EIC_EXTINT1 ((PIN_PC17A_EIC_EXTINT1 << 16) | MUX_PC17A_EIC_EXTINT1) +#define PORT_PC17A_EIC_EXTINT1 (_UL_(1) << 17) +#define PIN_PC17A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PC17 External Interrupt Line */ +#define PIN_PD01A_EIC_EXTINT1 _L_(97) /**< \brief EIC signal: EXTINT1 on PD01 mux A */ +#define MUX_PD01A_EIC_EXTINT1 _L_(0) +#define PINMUX_PD01A_EIC_EXTINT1 ((PIN_PD01A_EIC_EXTINT1 << 16) | MUX_PD01A_EIC_EXTINT1) +#define PORT_PD01A_EIC_EXTINT1 (_UL_(1) << 1) +#define PIN_PD01A_EIC_EXTINT_NUM _L_(1) /**< \brief EIC signal: PIN_PD01 External Interrupt Line */ +#define PIN_PA02A_EIC_EXTINT2 _L_(2) /**< \brief EIC signal: EXTINT2 on PA02 mux A */ +#define MUX_PA02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA02A_EIC_EXTINT2 ((PIN_PA02A_EIC_EXTINT2 << 16) | MUX_PA02A_EIC_EXTINT2) +#define PORT_PA02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PA02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA02 External Interrupt Line */ +#define PIN_PA18A_EIC_EXTINT2 _L_(18) /**< \brief EIC signal: EXTINT2 on PA18 mux A */ +#define MUX_PA18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PA18A_EIC_EXTINT2 ((PIN_PA18A_EIC_EXTINT2 << 16) | MUX_PA18A_EIC_EXTINT2) +#define PORT_PA18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PA18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PA18 External Interrupt Line */ +#define PIN_PB02A_EIC_EXTINT2 _L_(34) /**< \brief EIC signal: EXTINT2 on PB02 mux A */ +#define MUX_PB02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB02A_EIC_EXTINT2 ((PIN_PB02A_EIC_EXTINT2 << 16) | MUX_PB02A_EIC_EXTINT2) +#define PORT_PB02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PB02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB02 External Interrupt Line */ +#define PIN_PB18A_EIC_EXTINT2 _L_(50) /**< \brief EIC signal: EXTINT2 on PB18 mux A */ +#define MUX_PB18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PB18A_EIC_EXTINT2 ((PIN_PB18A_EIC_EXTINT2 << 16) | MUX_PB18A_EIC_EXTINT2) +#define PORT_PB18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PB18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PB18 External Interrupt Line */ +#define PIN_PC02A_EIC_EXTINT2 _L_(66) /**< \brief EIC signal: EXTINT2 on PC02 mux A */ +#define MUX_PC02A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC02A_EIC_EXTINT2 ((PIN_PC02A_EIC_EXTINT2 << 16) | MUX_PC02A_EIC_EXTINT2) +#define PORT_PC02A_EIC_EXTINT2 (_UL_(1) << 2) +#define PIN_PC02A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC02 External Interrupt Line */ +#define PIN_PC18A_EIC_EXTINT2 _L_(82) /**< \brief EIC signal: EXTINT2 on PC18 mux A */ +#define MUX_PC18A_EIC_EXTINT2 _L_(0) +#define PINMUX_PC18A_EIC_EXTINT2 ((PIN_PC18A_EIC_EXTINT2 << 16) | MUX_PC18A_EIC_EXTINT2) +#define PORT_PC18A_EIC_EXTINT2 (_UL_(1) << 18) +#define PIN_PC18A_EIC_EXTINT_NUM _L_(2) /**< \brief EIC signal: PIN_PC18 External Interrupt Line */ +#define PIN_PA03A_EIC_EXTINT3 _L_(3) /**< \brief EIC signal: EXTINT3 on PA03 mux A */ +#define MUX_PA03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA03A_EIC_EXTINT3 ((PIN_PA03A_EIC_EXTINT3 << 16) | MUX_PA03A_EIC_EXTINT3) +#define PORT_PA03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PA03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA03 External Interrupt Line */ +#define PIN_PA19A_EIC_EXTINT3 _L_(19) /**< \brief EIC signal: EXTINT3 on PA19 mux A */ +#define MUX_PA19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PA19A_EIC_EXTINT3 ((PIN_PA19A_EIC_EXTINT3 << 16) | MUX_PA19A_EIC_EXTINT3) +#define PORT_PA19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PA19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PA19 External Interrupt Line */ +#define PIN_PB03A_EIC_EXTINT3 _L_(35) /**< \brief EIC signal: EXTINT3 on PB03 mux A */ +#define MUX_PB03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB03A_EIC_EXTINT3 ((PIN_PB03A_EIC_EXTINT3 << 16) | MUX_PB03A_EIC_EXTINT3) +#define PORT_PB03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PB03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB03 External Interrupt Line */ +#define PIN_PB19A_EIC_EXTINT3 _L_(51) /**< \brief EIC signal: EXTINT3 on PB19 mux A */ +#define MUX_PB19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PB19A_EIC_EXTINT3 ((PIN_PB19A_EIC_EXTINT3 << 16) | MUX_PB19A_EIC_EXTINT3) +#define PORT_PB19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PB19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PB19 External Interrupt Line */ +#define PIN_PC03A_EIC_EXTINT3 _L_(67) /**< \brief EIC signal: EXTINT3 on PC03 mux A */ +#define MUX_PC03A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC03A_EIC_EXTINT3 ((PIN_PC03A_EIC_EXTINT3 << 16) | MUX_PC03A_EIC_EXTINT3) +#define PORT_PC03A_EIC_EXTINT3 (_UL_(1) << 3) +#define PIN_PC03A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC03 External Interrupt Line */ +#define PIN_PC19A_EIC_EXTINT3 _L_(83) /**< \brief EIC signal: EXTINT3 on PC19 mux A */ +#define MUX_PC19A_EIC_EXTINT3 _L_(0) +#define PINMUX_PC19A_EIC_EXTINT3 ((PIN_PC19A_EIC_EXTINT3 << 16) | MUX_PC19A_EIC_EXTINT3) +#define PORT_PC19A_EIC_EXTINT3 (_UL_(1) << 19) +#define PIN_PC19A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PC19 External Interrupt Line */ +#define PIN_PD08A_EIC_EXTINT3 _L_(104) /**< \brief EIC signal: EXTINT3 on PD08 mux A */ +#define MUX_PD08A_EIC_EXTINT3 _L_(0) +#define PINMUX_PD08A_EIC_EXTINT3 ((PIN_PD08A_EIC_EXTINT3 << 16) | MUX_PD08A_EIC_EXTINT3) +#define PORT_PD08A_EIC_EXTINT3 (_UL_(1) << 8) +#define PIN_PD08A_EIC_EXTINT_NUM _L_(3) /**< \brief EIC signal: PIN_PD08 External Interrupt Line */ +#define PIN_PA04A_EIC_EXTINT4 _L_(4) /**< \brief EIC signal: EXTINT4 on PA04 mux A */ +#define MUX_PA04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA04A_EIC_EXTINT4 ((PIN_PA04A_EIC_EXTINT4 << 16) | MUX_PA04A_EIC_EXTINT4) +#define PORT_PA04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PA04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA04 External Interrupt Line */ +#define PIN_PA20A_EIC_EXTINT4 _L_(20) /**< \brief EIC signal: EXTINT4 on PA20 mux A */ +#define MUX_PA20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PA20A_EIC_EXTINT4 ((PIN_PA20A_EIC_EXTINT4 << 16) | MUX_PA20A_EIC_EXTINT4) +#define PORT_PA20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PA20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PA20 External Interrupt Line */ +#define PIN_PB04A_EIC_EXTINT4 _L_(36) /**< \brief EIC signal: EXTINT4 on PB04 mux A */ +#define MUX_PB04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB04A_EIC_EXTINT4 ((PIN_PB04A_EIC_EXTINT4 << 16) | MUX_PB04A_EIC_EXTINT4) +#define PORT_PB04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PB04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB04 External Interrupt Line */ +#define PIN_PB20A_EIC_EXTINT4 _L_(52) /**< \brief EIC signal: EXTINT4 on PB20 mux A */ +#define MUX_PB20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PB20A_EIC_EXTINT4 ((PIN_PB20A_EIC_EXTINT4 << 16) | MUX_PB20A_EIC_EXTINT4) +#define PORT_PB20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PB20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PB20 External Interrupt Line */ +#define PIN_PC04A_EIC_EXTINT4 _L_(68) /**< \brief EIC signal: EXTINT4 on PC04 mux A */ +#define MUX_PC04A_EIC_EXTINT4 _L_(0) +#define PINMUX_PC04A_EIC_EXTINT4 ((PIN_PC04A_EIC_EXTINT4 << 16) | MUX_PC04A_EIC_EXTINT4) +#define PORT_PC04A_EIC_EXTINT4 (_UL_(1) << 4) +#define PIN_PC04A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC04 External Interrupt Line */ +#define PIN_PC20A_EIC_EXTINT4 _L_(84) /**< \brief EIC signal: EXTINT4 on PC20 mux A */ +#define MUX_PC20A_EIC_EXTINT4 _L_(0) +#define PINMUX_PC20A_EIC_EXTINT4 ((PIN_PC20A_EIC_EXTINT4 << 16) | MUX_PC20A_EIC_EXTINT4) +#define PORT_PC20A_EIC_EXTINT4 (_UL_(1) << 20) +#define PIN_PC20A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PC20 External Interrupt Line */ +#define PIN_PD09A_EIC_EXTINT4 _L_(105) /**< \brief EIC signal: EXTINT4 on PD09 mux A */ +#define MUX_PD09A_EIC_EXTINT4 _L_(0) +#define PINMUX_PD09A_EIC_EXTINT4 ((PIN_PD09A_EIC_EXTINT4 << 16) | MUX_PD09A_EIC_EXTINT4) +#define PORT_PD09A_EIC_EXTINT4 (_UL_(1) << 9) +#define PIN_PD09A_EIC_EXTINT_NUM _L_(4) /**< \brief EIC signal: PIN_PD09 External Interrupt Line */ +#define PIN_PA05A_EIC_EXTINT5 _L_(5) /**< \brief EIC signal: EXTINT5 on PA05 mux A */ +#define MUX_PA05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA05A_EIC_EXTINT5 ((PIN_PA05A_EIC_EXTINT5 << 16) | MUX_PA05A_EIC_EXTINT5) +#define PORT_PA05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PA05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA05 External Interrupt Line */ +#define PIN_PA21A_EIC_EXTINT5 _L_(21) /**< \brief EIC signal: EXTINT5 on PA21 mux A */ +#define MUX_PA21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PA21A_EIC_EXTINT5 ((PIN_PA21A_EIC_EXTINT5 << 16) | MUX_PA21A_EIC_EXTINT5) +#define PORT_PA21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PA21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PA21 External Interrupt Line */ +#define PIN_PB05A_EIC_EXTINT5 _L_(37) /**< \brief EIC signal: EXTINT5 on PB05 mux A */ +#define MUX_PB05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB05A_EIC_EXTINT5 ((PIN_PB05A_EIC_EXTINT5 << 16) | MUX_PB05A_EIC_EXTINT5) +#define PORT_PB05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PB05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB05 External Interrupt Line */ +#define PIN_PB21A_EIC_EXTINT5 _L_(53) /**< \brief EIC signal: EXTINT5 on PB21 mux A */ +#define MUX_PB21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PB21A_EIC_EXTINT5 ((PIN_PB21A_EIC_EXTINT5 << 16) | MUX_PB21A_EIC_EXTINT5) +#define PORT_PB21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PB21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PB21 External Interrupt Line */ +#define PIN_PC05A_EIC_EXTINT5 _L_(69) /**< \brief EIC signal: EXTINT5 on PC05 mux A */ +#define MUX_PC05A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC05A_EIC_EXTINT5 ((PIN_PC05A_EIC_EXTINT5 << 16) | MUX_PC05A_EIC_EXTINT5) +#define PORT_PC05A_EIC_EXTINT5 (_UL_(1) << 5) +#define PIN_PC05A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC05 External Interrupt Line */ +#define PIN_PC21A_EIC_EXTINT5 _L_(85) /**< \brief EIC signal: EXTINT5 on PC21 mux A */ +#define MUX_PC21A_EIC_EXTINT5 _L_(0) +#define PINMUX_PC21A_EIC_EXTINT5 ((PIN_PC21A_EIC_EXTINT5 << 16) | MUX_PC21A_EIC_EXTINT5) +#define PORT_PC21A_EIC_EXTINT5 (_UL_(1) << 21) +#define PIN_PC21A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PC21 External Interrupt Line */ +#define PIN_PD10A_EIC_EXTINT5 _L_(106) /**< \brief EIC signal: EXTINT5 on PD10 mux A */ +#define MUX_PD10A_EIC_EXTINT5 _L_(0) +#define PINMUX_PD10A_EIC_EXTINT5 ((PIN_PD10A_EIC_EXTINT5 << 16) | MUX_PD10A_EIC_EXTINT5) +#define PORT_PD10A_EIC_EXTINT5 (_UL_(1) << 10) +#define PIN_PD10A_EIC_EXTINT_NUM _L_(5) /**< \brief EIC signal: PIN_PD10 External Interrupt Line */ +#define PIN_PA06A_EIC_EXTINT6 _L_(6) /**< \brief EIC signal: EXTINT6 on PA06 mux A */ +#define MUX_PA06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA06A_EIC_EXTINT6 ((PIN_PA06A_EIC_EXTINT6 << 16) | MUX_PA06A_EIC_EXTINT6) +#define PORT_PA06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PA06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA06 External Interrupt Line */ +#define PIN_PA22A_EIC_EXTINT6 _L_(22) /**< \brief EIC signal: EXTINT6 on PA22 mux A */ +#define MUX_PA22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PA22A_EIC_EXTINT6 ((PIN_PA22A_EIC_EXTINT6 << 16) | MUX_PA22A_EIC_EXTINT6) +#define PORT_PA22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PA22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PA22 External Interrupt Line */ +#define PIN_PB06A_EIC_EXTINT6 _L_(38) /**< \brief EIC signal: EXTINT6 on PB06 mux A */ +#define MUX_PB06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB06A_EIC_EXTINT6 ((PIN_PB06A_EIC_EXTINT6 << 16) | MUX_PB06A_EIC_EXTINT6) +#define PORT_PB06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PB06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB06 External Interrupt Line */ +#define PIN_PB22A_EIC_EXTINT6 _L_(54) /**< \brief EIC signal: EXTINT6 on PB22 mux A */ +#define MUX_PB22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PB22A_EIC_EXTINT6 ((PIN_PB22A_EIC_EXTINT6 << 16) | MUX_PB22A_EIC_EXTINT6) +#define PORT_PB22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PB22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PB22 External Interrupt Line */ +#define PIN_PC06A_EIC_EXTINT6 _L_(70) /**< \brief EIC signal: EXTINT6 on PC06 mux A */ +#define MUX_PC06A_EIC_EXTINT6 _L_(0) +#define PINMUX_PC06A_EIC_EXTINT6 ((PIN_PC06A_EIC_EXTINT6 << 16) | MUX_PC06A_EIC_EXTINT6) +#define PORT_PC06A_EIC_EXTINT6 (_UL_(1) << 6) +#define PIN_PC06A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC06 External Interrupt Line */ +#define PIN_PC22A_EIC_EXTINT6 _L_(86) /**< \brief EIC signal: EXTINT6 on PC22 mux A */ +#define MUX_PC22A_EIC_EXTINT6 _L_(0) +#define PINMUX_PC22A_EIC_EXTINT6 ((PIN_PC22A_EIC_EXTINT6 << 16) | MUX_PC22A_EIC_EXTINT6) +#define PORT_PC22A_EIC_EXTINT6 (_UL_(1) << 22) +#define PIN_PC22A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PC22 External Interrupt Line */ +#define PIN_PD11A_EIC_EXTINT6 _L_(107) /**< \brief EIC signal: EXTINT6 on PD11 mux A */ +#define MUX_PD11A_EIC_EXTINT6 _L_(0) +#define PINMUX_PD11A_EIC_EXTINT6 ((PIN_PD11A_EIC_EXTINT6 << 16) | MUX_PD11A_EIC_EXTINT6) +#define PORT_PD11A_EIC_EXTINT6 (_UL_(1) << 11) +#define PIN_PD11A_EIC_EXTINT_NUM _L_(6) /**< \brief EIC signal: PIN_PD11 External Interrupt Line */ +#define PIN_PA07A_EIC_EXTINT7 _L_(7) /**< \brief EIC signal: EXTINT7 on PA07 mux A */ +#define MUX_PA07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA07A_EIC_EXTINT7 ((PIN_PA07A_EIC_EXTINT7 << 16) | MUX_PA07A_EIC_EXTINT7) +#define PORT_PA07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PA07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA07 External Interrupt Line */ +#define PIN_PA23A_EIC_EXTINT7 _L_(23) /**< \brief EIC signal: EXTINT7 on PA23 mux A */ +#define MUX_PA23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PA23A_EIC_EXTINT7 ((PIN_PA23A_EIC_EXTINT7 << 16) | MUX_PA23A_EIC_EXTINT7) +#define PORT_PA23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PA23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PA23 External Interrupt Line */ +#define PIN_PB07A_EIC_EXTINT7 _L_(39) /**< \brief EIC signal: EXTINT7 on PB07 mux A */ +#define MUX_PB07A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB07A_EIC_EXTINT7 ((PIN_PB07A_EIC_EXTINT7 << 16) | MUX_PB07A_EIC_EXTINT7) +#define PORT_PB07A_EIC_EXTINT7 (_UL_(1) << 7) +#define PIN_PB07A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB07 External Interrupt Line */ +#define PIN_PB23A_EIC_EXTINT7 _L_(55) /**< \brief EIC signal: EXTINT7 on PB23 mux A */ +#define MUX_PB23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PB23A_EIC_EXTINT7 ((PIN_PB23A_EIC_EXTINT7 << 16) | MUX_PB23A_EIC_EXTINT7) +#define PORT_PB23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PB23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PB23 External Interrupt Line */ +#define PIN_PC23A_EIC_EXTINT7 _L_(87) /**< \brief EIC signal: EXTINT7 on PC23 mux A */ +#define MUX_PC23A_EIC_EXTINT7 _L_(0) +#define PINMUX_PC23A_EIC_EXTINT7 ((PIN_PC23A_EIC_EXTINT7 << 16) | MUX_PC23A_EIC_EXTINT7) +#define PORT_PC23A_EIC_EXTINT7 (_UL_(1) << 23) +#define PIN_PC23A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PC23 External Interrupt Line */ +#define PIN_PD12A_EIC_EXTINT7 _L_(108) /**< \brief EIC signal: EXTINT7 on PD12 mux A */ +#define MUX_PD12A_EIC_EXTINT7 _L_(0) +#define PINMUX_PD12A_EIC_EXTINT7 ((PIN_PD12A_EIC_EXTINT7 << 16) | MUX_PD12A_EIC_EXTINT7) +#define PORT_PD12A_EIC_EXTINT7 (_UL_(1) << 12) +#define PIN_PD12A_EIC_EXTINT_NUM _L_(7) /**< \brief EIC signal: PIN_PD12 External Interrupt Line */ +#define PIN_PA24A_EIC_EXTINT8 _L_(24) /**< \brief EIC signal: EXTINT8 on PA24 mux A */ +#define MUX_PA24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PA24A_EIC_EXTINT8 ((PIN_PA24A_EIC_EXTINT8 << 16) | MUX_PA24A_EIC_EXTINT8) +#define PORT_PA24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PA24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PA24 External Interrupt Line */ +#define PIN_PB08A_EIC_EXTINT8 _L_(40) /**< \brief EIC signal: EXTINT8 on PB08 mux A */ +#define MUX_PB08A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB08A_EIC_EXTINT8 ((PIN_PB08A_EIC_EXTINT8 << 16) | MUX_PB08A_EIC_EXTINT8) +#define PORT_PB08A_EIC_EXTINT8 (_UL_(1) << 8) +#define PIN_PB08A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB08 External Interrupt Line */ +#define PIN_PB24A_EIC_EXTINT8 _L_(56) /**< \brief EIC signal: EXTINT8 on PB24 mux A */ +#define MUX_PB24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PB24A_EIC_EXTINT8 ((PIN_PB24A_EIC_EXTINT8 << 16) | MUX_PB24A_EIC_EXTINT8) +#define PORT_PB24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PB24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PB24 External Interrupt Line */ +#define PIN_PC24A_EIC_EXTINT8 _L_(88) /**< \brief EIC signal: EXTINT8 on PC24 mux A */ +#define MUX_PC24A_EIC_EXTINT8 _L_(0) +#define PINMUX_PC24A_EIC_EXTINT8 ((PIN_PC24A_EIC_EXTINT8 << 16) | MUX_PC24A_EIC_EXTINT8) +#define PORT_PC24A_EIC_EXTINT8 (_UL_(1) << 24) +#define PIN_PC24A_EIC_EXTINT_NUM _L_(8) /**< \brief EIC signal: PIN_PC24 External Interrupt Line */ +#define PIN_PA09A_EIC_EXTINT9 _L_(9) /**< \brief EIC signal: EXTINT9 on PA09 mux A */ +#define MUX_PA09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA09A_EIC_EXTINT9 ((PIN_PA09A_EIC_EXTINT9 << 16) | MUX_PA09A_EIC_EXTINT9) +#define PORT_PA09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PA09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA09 External Interrupt Line */ +#define PIN_PA25A_EIC_EXTINT9 _L_(25) /**< \brief EIC signal: EXTINT9 on PA25 mux A */ +#define MUX_PA25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PA25A_EIC_EXTINT9 ((PIN_PA25A_EIC_EXTINT9 << 16) | MUX_PA25A_EIC_EXTINT9) +#define PORT_PA25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PA25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PA25 External Interrupt Line */ +#define PIN_PB09A_EIC_EXTINT9 _L_(41) /**< \brief EIC signal: EXTINT9 on PB09 mux A */ +#define MUX_PB09A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB09A_EIC_EXTINT9 ((PIN_PB09A_EIC_EXTINT9 << 16) | MUX_PB09A_EIC_EXTINT9) +#define PORT_PB09A_EIC_EXTINT9 (_UL_(1) << 9) +#define PIN_PB09A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB09 External Interrupt Line */ +#define PIN_PB25A_EIC_EXTINT9 _L_(57) /**< \brief EIC signal: EXTINT9 on PB25 mux A */ +#define MUX_PB25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PB25A_EIC_EXTINT9 ((PIN_PB25A_EIC_EXTINT9 << 16) | MUX_PB25A_EIC_EXTINT9) +#define PORT_PB25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PB25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PB25 External Interrupt Line */ +#define PIN_PC07A_EIC_EXTINT9 _L_(71) /**< \brief EIC signal: EXTINT9 on PC07 mux A */ +#define MUX_PC07A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC07A_EIC_EXTINT9 ((PIN_PC07A_EIC_EXTINT9 << 16) | MUX_PC07A_EIC_EXTINT9) +#define PORT_PC07A_EIC_EXTINT9 (_UL_(1) << 7) +#define PIN_PC07A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC07 External Interrupt Line */ +#define PIN_PC25A_EIC_EXTINT9 _L_(89) /**< \brief EIC signal: EXTINT9 on PC25 mux A */ +#define MUX_PC25A_EIC_EXTINT9 _L_(0) +#define PINMUX_PC25A_EIC_EXTINT9 ((PIN_PC25A_EIC_EXTINT9 << 16) | MUX_PC25A_EIC_EXTINT9) +#define PORT_PC25A_EIC_EXTINT9 (_UL_(1) << 25) +#define PIN_PC25A_EIC_EXTINT_NUM _L_(9) /**< \brief EIC signal: PIN_PC25 External Interrupt Line */ +#define PIN_PA10A_EIC_EXTINT10 _L_(10) /**< \brief EIC signal: EXTINT10 on PA10 mux A */ +#define MUX_PA10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PA10A_EIC_EXTINT10 ((PIN_PA10A_EIC_EXTINT10 << 16) | MUX_PA10A_EIC_EXTINT10) +#define PORT_PA10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PA10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PA10 External Interrupt Line */ +#define PIN_PB10A_EIC_EXTINT10 _L_(42) /**< \brief EIC signal: EXTINT10 on PB10 mux A */ +#define MUX_PB10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PB10A_EIC_EXTINT10 ((PIN_PB10A_EIC_EXTINT10 << 16) | MUX_PB10A_EIC_EXTINT10) +#define PORT_PB10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PB10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PB10 External Interrupt Line */ +#define PIN_PC10A_EIC_EXTINT10 _L_(74) /**< \brief EIC signal: EXTINT10 on PC10 mux A */ +#define MUX_PC10A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC10A_EIC_EXTINT10 ((PIN_PC10A_EIC_EXTINT10 << 16) | MUX_PC10A_EIC_EXTINT10) +#define PORT_PC10A_EIC_EXTINT10 (_UL_(1) << 10) +#define PIN_PC10A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC10 External Interrupt Line */ +#define PIN_PC26A_EIC_EXTINT10 _L_(90) /**< \brief EIC signal: EXTINT10 on PC26 mux A */ +#define MUX_PC26A_EIC_EXTINT10 _L_(0) +#define PINMUX_PC26A_EIC_EXTINT10 ((PIN_PC26A_EIC_EXTINT10 << 16) | MUX_PC26A_EIC_EXTINT10) +#define PORT_PC26A_EIC_EXTINT10 (_UL_(1) << 26) +#define PIN_PC26A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PC26 External Interrupt Line */ +#define PIN_PD20A_EIC_EXTINT10 _L_(116) /**< \brief EIC signal: EXTINT10 on PD20 mux A */ +#define MUX_PD20A_EIC_EXTINT10 _L_(0) +#define PINMUX_PD20A_EIC_EXTINT10 ((PIN_PD20A_EIC_EXTINT10 << 16) | MUX_PD20A_EIC_EXTINT10) +#define PORT_PD20A_EIC_EXTINT10 (_UL_(1) << 20) +#define PIN_PD20A_EIC_EXTINT_NUM _L_(10) /**< \brief EIC signal: PIN_PD20 External Interrupt Line */ +#define PIN_PA11A_EIC_EXTINT11 _L_(11) /**< \brief EIC signal: EXTINT11 on PA11 mux A */ +#define MUX_PA11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA11A_EIC_EXTINT11 ((PIN_PA11A_EIC_EXTINT11 << 16) | MUX_PA11A_EIC_EXTINT11) +#define PORT_PA11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PA11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA11 External Interrupt Line */ +#define PIN_PA27A_EIC_EXTINT11 _L_(27) /**< \brief EIC signal: EXTINT11 on PA27 mux A */ +#define MUX_PA27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PA27A_EIC_EXTINT11 ((PIN_PA27A_EIC_EXTINT11 << 16) | MUX_PA27A_EIC_EXTINT11) +#define PORT_PA27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PA27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PA27 External Interrupt Line */ +#define PIN_PB11A_EIC_EXTINT11 _L_(43) /**< \brief EIC signal: EXTINT11 on PB11 mux A */ +#define MUX_PB11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PB11A_EIC_EXTINT11 ((PIN_PB11A_EIC_EXTINT11 << 16) | MUX_PB11A_EIC_EXTINT11) +#define PORT_PB11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PB11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PB11 External Interrupt Line */ +#define PIN_PC11A_EIC_EXTINT11 _L_(75) /**< \brief EIC signal: EXTINT11 on PC11 mux A */ +#define MUX_PC11A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC11A_EIC_EXTINT11 ((PIN_PC11A_EIC_EXTINT11 << 16) | MUX_PC11A_EIC_EXTINT11) +#define PORT_PC11A_EIC_EXTINT11 (_UL_(1) << 11) +#define PIN_PC11A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC11 External Interrupt Line */ +#define PIN_PC27A_EIC_EXTINT11 _L_(91) /**< \brief EIC signal: EXTINT11 on PC27 mux A */ +#define MUX_PC27A_EIC_EXTINT11 _L_(0) +#define PINMUX_PC27A_EIC_EXTINT11 ((PIN_PC27A_EIC_EXTINT11 << 16) | MUX_PC27A_EIC_EXTINT11) +#define PORT_PC27A_EIC_EXTINT11 (_UL_(1) << 27) +#define PIN_PC27A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PC27 External Interrupt Line */ +#define PIN_PD21A_EIC_EXTINT11 _L_(117) /**< \brief EIC signal: EXTINT11 on PD21 mux A */ +#define MUX_PD21A_EIC_EXTINT11 _L_(0) +#define PINMUX_PD21A_EIC_EXTINT11 ((PIN_PD21A_EIC_EXTINT11 << 16) | MUX_PD21A_EIC_EXTINT11) +#define PORT_PD21A_EIC_EXTINT11 (_UL_(1) << 21) +#define PIN_PD21A_EIC_EXTINT_NUM _L_(11) /**< \brief EIC signal: PIN_PD21 External Interrupt Line */ +#define PIN_PA12A_EIC_EXTINT12 _L_(12) /**< \brief EIC signal: EXTINT12 on PA12 mux A */ +#define MUX_PA12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PA12A_EIC_EXTINT12 ((PIN_PA12A_EIC_EXTINT12 << 16) | MUX_PA12A_EIC_EXTINT12) +#define PORT_PA12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PA12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PA12 External Interrupt Line */ +#define PIN_PB12A_EIC_EXTINT12 _L_(44) /**< \brief EIC signal: EXTINT12 on PB12 mux A */ +#define MUX_PB12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB12A_EIC_EXTINT12 ((PIN_PB12A_EIC_EXTINT12 << 16) | MUX_PB12A_EIC_EXTINT12) +#define PORT_PB12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PB12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB12 External Interrupt Line */ +#define PIN_PB26A_EIC_EXTINT12 _L_(58) /**< \brief EIC signal: EXTINT12 on PB26 mux A */ +#define MUX_PB26A_EIC_EXTINT12 _L_(0) +#define PINMUX_PB26A_EIC_EXTINT12 ((PIN_PB26A_EIC_EXTINT12 << 16) | MUX_PB26A_EIC_EXTINT12) +#define PORT_PB26A_EIC_EXTINT12 (_UL_(1) << 26) +#define PIN_PB26A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PB26 External Interrupt Line */ +#define PIN_PC12A_EIC_EXTINT12 _L_(76) /**< \brief EIC signal: EXTINT12 on PC12 mux A */ +#define MUX_PC12A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC12A_EIC_EXTINT12 ((PIN_PC12A_EIC_EXTINT12 << 16) | MUX_PC12A_EIC_EXTINT12) +#define PORT_PC12A_EIC_EXTINT12 (_UL_(1) << 12) +#define PIN_PC12A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC12 External Interrupt Line */ +#define PIN_PC28A_EIC_EXTINT12 _L_(92) /**< \brief EIC signal: EXTINT12 on PC28 mux A */ +#define MUX_PC28A_EIC_EXTINT12 _L_(0) +#define PINMUX_PC28A_EIC_EXTINT12 ((PIN_PC28A_EIC_EXTINT12 << 16) | MUX_PC28A_EIC_EXTINT12) +#define PORT_PC28A_EIC_EXTINT12 (_UL_(1) << 28) +#define PIN_PC28A_EIC_EXTINT_NUM _L_(12) /**< \brief EIC signal: PIN_PC28 External Interrupt Line */ +#define PIN_PA13A_EIC_EXTINT13 _L_(13) /**< \brief EIC signal: EXTINT13 on PA13 mux A */ +#define MUX_PA13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PA13A_EIC_EXTINT13 ((PIN_PA13A_EIC_EXTINT13 << 16) | MUX_PA13A_EIC_EXTINT13) +#define PORT_PA13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PA13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PA13 External Interrupt Line */ +#define PIN_PB13A_EIC_EXTINT13 _L_(45) /**< \brief EIC signal: EXTINT13 on PB13 mux A */ +#define MUX_PB13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB13A_EIC_EXTINT13 ((PIN_PB13A_EIC_EXTINT13 << 16) | MUX_PB13A_EIC_EXTINT13) +#define PORT_PB13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PB13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB13 External Interrupt Line */ +#define PIN_PB27A_EIC_EXTINT13 _L_(59) /**< \brief EIC signal: EXTINT13 on PB27 mux A */ +#define MUX_PB27A_EIC_EXTINT13 _L_(0) +#define PINMUX_PB27A_EIC_EXTINT13 ((PIN_PB27A_EIC_EXTINT13 << 16) | MUX_PB27A_EIC_EXTINT13) +#define PORT_PB27A_EIC_EXTINT13 (_UL_(1) << 27) +#define PIN_PB27A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PB27 External Interrupt Line */ +#define PIN_PC13A_EIC_EXTINT13 _L_(77) /**< \brief EIC signal: EXTINT13 on PC13 mux A */ +#define MUX_PC13A_EIC_EXTINT13 _L_(0) +#define PINMUX_PC13A_EIC_EXTINT13 ((PIN_PC13A_EIC_EXTINT13 << 16) | MUX_PC13A_EIC_EXTINT13) +#define PORT_PC13A_EIC_EXTINT13 (_UL_(1) << 13) +#define PIN_PC13A_EIC_EXTINT_NUM _L_(13) /**< \brief EIC signal: PIN_PC13 External Interrupt Line */ +#define PIN_PA30A_EIC_EXTINT14 _L_(30) /**< \brief EIC signal: EXTINT14 on PA30 mux A */ +#define MUX_PA30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA30A_EIC_EXTINT14 ((PIN_PA30A_EIC_EXTINT14 << 16) | MUX_PA30A_EIC_EXTINT14) +#define PORT_PA30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PA30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA30 External Interrupt Line */ +#define PIN_PB14A_EIC_EXTINT14 _L_(46) /**< \brief EIC signal: EXTINT14 on PB14 mux A */ +#define MUX_PB14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB14A_EIC_EXTINT14 ((PIN_PB14A_EIC_EXTINT14 << 16) | MUX_PB14A_EIC_EXTINT14) +#define PORT_PB14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PB14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB14 External Interrupt Line */ +#define PIN_PB28A_EIC_EXTINT14 _L_(60) /**< \brief EIC signal: EXTINT14 on PB28 mux A */ +#define MUX_PB28A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB28A_EIC_EXTINT14 ((PIN_PB28A_EIC_EXTINT14 << 16) | MUX_PB28A_EIC_EXTINT14) +#define PORT_PB28A_EIC_EXTINT14 (_UL_(1) << 28) +#define PIN_PB28A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB28 External Interrupt Line */ +#define PIN_PB30A_EIC_EXTINT14 _L_(62) /**< \brief EIC signal: EXTINT14 on PB30 mux A */ +#define MUX_PB30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PB30A_EIC_EXTINT14 ((PIN_PB30A_EIC_EXTINT14 << 16) | MUX_PB30A_EIC_EXTINT14) +#define PORT_PB30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PB30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PB30 External Interrupt Line */ +#define PIN_PC14A_EIC_EXTINT14 _L_(78) /**< \brief EIC signal: EXTINT14 on PC14 mux A */ +#define MUX_PC14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PC14A_EIC_EXTINT14 ((PIN_PC14A_EIC_EXTINT14 << 16) | MUX_PC14A_EIC_EXTINT14) +#define PORT_PC14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PC14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC14 External Interrupt Line */ +#define PIN_PC30A_EIC_EXTINT14 _L_(94) /**< \brief EIC signal: EXTINT14 on PC30 mux A */ +#define MUX_PC30A_EIC_EXTINT14 _L_(0) +#define PINMUX_PC30A_EIC_EXTINT14 ((PIN_PC30A_EIC_EXTINT14 << 16) | MUX_PC30A_EIC_EXTINT14) +#define PORT_PC30A_EIC_EXTINT14 (_UL_(1) << 30) +#define PIN_PC30A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PC30 External Interrupt Line */ +#define PIN_PA14A_EIC_EXTINT14 _L_(14) /**< \brief EIC signal: EXTINT14 on PA14 mux A */ +#define MUX_PA14A_EIC_EXTINT14 _L_(0) +#define PINMUX_PA14A_EIC_EXTINT14 ((PIN_PA14A_EIC_EXTINT14 << 16) | MUX_PA14A_EIC_EXTINT14) +#define PORT_PA14A_EIC_EXTINT14 (_UL_(1) << 14) +#define PIN_PA14A_EIC_EXTINT_NUM _L_(14) /**< \brief EIC signal: PIN_PA14 External Interrupt Line */ +#define PIN_PA15A_EIC_EXTINT15 _L_(15) /**< \brief EIC signal: EXTINT15 on PA15 mux A */ +#define MUX_PA15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA15A_EIC_EXTINT15 ((PIN_PA15A_EIC_EXTINT15 << 16) | MUX_PA15A_EIC_EXTINT15) +#define PORT_PA15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PA15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA15 External Interrupt Line */ +#define PIN_PA31A_EIC_EXTINT15 _L_(31) /**< \brief EIC signal: EXTINT15 on PA31 mux A */ +#define MUX_PA31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PA31A_EIC_EXTINT15 ((PIN_PA31A_EIC_EXTINT15 << 16) | MUX_PA31A_EIC_EXTINT15) +#define PORT_PA31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PA31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PA31 External Interrupt Line */ +#define PIN_PB15A_EIC_EXTINT15 _L_(47) /**< \brief EIC signal: EXTINT15 on PB15 mux A */ +#define MUX_PB15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB15A_EIC_EXTINT15 ((PIN_PB15A_EIC_EXTINT15 << 16) | MUX_PB15A_EIC_EXTINT15) +#define PORT_PB15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PB15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB15 External Interrupt Line */ +#define PIN_PB29A_EIC_EXTINT15 _L_(61) /**< \brief EIC signal: EXTINT15 on PB29 mux A */ +#define MUX_PB29A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB29A_EIC_EXTINT15 ((PIN_PB29A_EIC_EXTINT15 << 16) | MUX_PB29A_EIC_EXTINT15) +#define PORT_PB29A_EIC_EXTINT15 (_UL_(1) << 29) +#define PIN_PB29A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB29 External Interrupt Line */ +#define PIN_PB31A_EIC_EXTINT15 _L_(63) /**< \brief EIC signal: EXTINT15 on PB31 mux A */ +#define MUX_PB31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PB31A_EIC_EXTINT15 ((PIN_PB31A_EIC_EXTINT15 << 16) | MUX_PB31A_EIC_EXTINT15) +#define PORT_PB31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PB31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PB31 External Interrupt Line */ +#define PIN_PC15A_EIC_EXTINT15 _L_(79) /**< \brief EIC signal: EXTINT15 on PC15 mux A */ +#define MUX_PC15A_EIC_EXTINT15 _L_(0) +#define PINMUX_PC15A_EIC_EXTINT15 ((PIN_PC15A_EIC_EXTINT15 << 16) | MUX_PC15A_EIC_EXTINT15) +#define PORT_PC15A_EIC_EXTINT15 (_UL_(1) << 15) +#define PIN_PC15A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC15 External Interrupt Line */ +#define PIN_PC31A_EIC_EXTINT15 _L_(95) /**< \brief EIC signal: EXTINT15 on PC31 mux A */ +#define MUX_PC31A_EIC_EXTINT15 _L_(0) +#define PINMUX_PC31A_EIC_EXTINT15 ((PIN_PC31A_EIC_EXTINT15 << 16) | MUX_PC31A_EIC_EXTINT15) +#define PORT_PC31A_EIC_EXTINT15 (_UL_(1) << 31) +#define PIN_PC31A_EIC_EXTINT_NUM _L_(15) /**< \brief EIC signal: PIN_PC31 External Interrupt Line */ +#define PIN_PA08A_EIC_NMI _L_(8) /**< \brief EIC signal: NMI on PA08 mux A */ +#define MUX_PA08A_EIC_NMI _L_(0) +#define PINMUX_PA08A_EIC_NMI ((PIN_PA08A_EIC_NMI << 16) | MUX_PA08A_EIC_NMI) +#define PORT_PA08A_EIC_NMI (_UL_(1) << 8) +/* ========== PORT definition for SERCOM0 peripheral ========== */ +#define PIN_PA04D_SERCOM0_PAD0 _L_(4) /**< \brief SERCOM0 signal: PAD0 on PA04 mux D */ +#define MUX_PA04D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PA04D_SERCOM0_PAD0 ((PIN_PA04D_SERCOM0_PAD0 << 16) | MUX_PA04D_SERCOM0_PAD0) +#define PORT_PA04D_SERCOM0_PAD0 (_UL_(1) << 4) +#define PIN_PC17D_SERCOM0_PAD0 _L_(81) /**< \brief SERCOM0 signal: PAD0 on PC17 mux D */ +#define MUX_PC17D_SERCOM0_PAD0 _L_(3) +#define PINMUX_PC17D_SERCOM0_PAD0 ((PIN_PC17D_SERCOM0_PAD0 << 16) | MUX_PC17D_SERCOM0_PAD0) +#define PORT_PC17D_SERCOM0_PAD0 (_UL_(1) << 17) +#define PIN_PA08C_SERCOM0_PAD0 _L_(8) /**< \brief SERCOM0 signal: PAD0 on PA08 mux C */ +#define MUX_PA08C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PA08C_SERCOM0_PAD0 ((PIN_PA08C_SERCOM0_PAD0 << 16) | MUX_PA08C_SERCOM0_PAD0) +#define PORT_PA08C_SERCOM0_PAD0 (_UL_(1) << 8) +#define PIN_PB24C_SERCOM0_PAD0 _L_(56) /**< \brief SERCOM0 signal: PAD0 on PB24 mux C */ +#define MUX_PB24C_SERCOM0_PAD0 _L_(2) +#define PINMUX_PB24C_SERCOM0_PAD0 ((PIN_PB24C_SERCOM0_PAD0 << 16) | MUX_PB24C_SERCOM0_PAD0) +#define PORT_PB24C_SERCOM0_PAD0 (_UL_(1) << 24) +#define PIN_PA05D_SERCOM0_PAD1 _L_(5) /**< \brief SERCOM0 signal: PAD1 on PA05 mux D */ +#define MUX_PA05D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PA05D_SERCOM0_PAD1 ((PIN_PA05D_SERCOM0_PAD1 << 16) | MUX_PA05D_SERCOM0_PAD1) +#define PORT_PA05D_SERCOM0_PAD1 (_UL_(1) << 5) +#define PIN_PC16D_SERCOM0_PAD1 _L_(80) /**< \brief SERCOM0 signal: PAD1 on PC16 mux D */ +#define MUX_PC16D_SERCOM0_PAD1 _L_(3) +#define PINMUX_PC16D_SERCOM0_PAD1 ((PIN_PC16D_SERCOM0_PAD1 << 16) | MUX_PC16D_SERCOM0_PAD1) +#define PORT_PC16D_SERCOM0_PAD1 (_UL_(1) << 16) +#define PIN_PA09C_SERCOM0_PAD1 _L_(9) /**< \brief SERCOM0 signal: PAD1 on PA09 mux C */ +#define MUX_PA09C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PA09C_SERCOM0_PAD1 ((PIN_PA09C_SERCOM0_PAD1 << 16) | MUX_PA09C_SERCOM0_PAD1) +#define PORT_PA09C_SERCOM0_PAD1 (_UL_(1) << 9) +#define PIN_PB25C_SERCOM0_PAD1 _L_(57) /**< \brief SERCOM0 signal: PAD1 on PB25 mux C */ +#define MUX_PB25C_SERCOM0_PAD1 _L_(2) +#define PINMUX_PB25C_SERCOM0_PAD1 ((PIN_PB25C_SERCOM0_PAD1 << 16) | MUX_PB25C_SERCOM0_PAD1) +#define PORT_PB25C_SERCOM0_PAD1 (_UL_(1) << 25) +#define PIN_PA06D_SERCOM0_PAD2 _L_(6) /**< \brief SERCOM0 signal: PAD2 on PA06 mux D */ +#define MUX_PA06D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PA06D_SERCOM0_PAD2 ((PIN_PA06D_SERCOM0_PAD2 << 16) | MUX_PA06D_SERCOM0_PAD2) +#define PORT_PA06D_SERCOM0_PAD2 (_UL_(1) << 6) +#define PIN_PC18D_SERCOM0_PAD2 _L_(82) /**< \brief SERCOM0 signal: PAD2 on PC18 mux D */ +#define MUX_PC18D_SERCOM0_PAD2 _L_(3) +#define PINMUX_PC18D_SERCOM0_PAD2 ((PIN_PC18D_SERCOM0_PAD2 << 16) | MUX_PC18D_SERCOM0_PAD2) +#define PORT_PC18D_SERCOM0_PAD2 (_UL_(1) << 18) +#define PIN_PA10C_SERCOM0_PAD2 _L_(10) /**< \brief SERCOM0 signal: PAD2 on PA10 mux C */ +#define MUX_PA10C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PA10C_SERCOM0_PAD2 ((PIN_PA10C_SERCOM0_PAD2 << 16) | MUX_PA10C_SERCOM0_PAD2) +#define PORT_PA10C_SERCOM0_PAD2 (_UL_(1) << 10) +#define PIN_PC24C_SERCOM0_PAD2 _L_(88) /**< \brief SERCOM0 signal: PAD2 on PC24 mux C */ +#define MUX_PC24C_SERCOM0_PAD2 _L_(2) +#define PINMUX_PC24C_SERCOM0_PAD2 ((PIN_PC24C_SERCOM0_PAD2 << 16) | MUX_PC24C_SERCOM0_PAD2) +#define PORT_PC24C_SERCOM0_PAD2 (_UL_(1) << 24) +#define PIN_PA07D_SERCOM0_PAD3 _L_(7) /**< \brief SERCOM0 signal: PAD3 on PA07 mux D */ +#define MUX_PA07D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PA07D_SERCOM0_PAD3 ((PIN_PA07D_SERCOM0_PAD3 << 16) | MUX_PA07D_SERCOM0_PAD3) +#define PORT_PA07D_SERCOM0_PAD3 (_UL_(1) << 7) +#define PIN_PC19D_SERCOM0_PAD3 _L_(83) /**< \brief SERCOM0 signal: PAD3 on PC19 mux D */ +#define MUX_PC19D_SERCOM0_PAD3 _L_(3) +#define PINMUX_PC19D_SERCOM0_PAD3 ((PIN_PC19D_SERCOM0_PAD3 << 16) | MUX_PC19D_SERCOM0_PAD3) +#define PORT_PC19D_SERCOM0_PAD3 (_UL_(1) << 19) +#define PIN_PA11C_SERCOM0_PAD3 _L_(11) /**< \brief SERCOM0 signal: PAD3 on PA11 mux C */ +#define MUX_PA11C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PA11C_SERCOM0_PAD3 ((PIN_PA11C_SERCOM0_PAD3 << 16) | MUX_PA11C_SERCOM0_PAD3) +#define PORT_PA11C_SERCOM0_PAD3 (_UL_(1) << 11) +#define PIN_PC25C_SERCOM0_PAD3 _L_(89) /**< \brief SERCOM0 signal: PAD3 on PC25 mux C */ +#define MUX_PC25C_SERCOM0_PAD3 _L_(2) +#define PINMUX_PC25C_SERCOM0_PAD3 ((PIN_PC25C_SERCOM0_PAD3 << 16) | MUX_PC25C_SERCOM0_PAD3) +#define PORT_PC25C_SERCOM0_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for SERCOM1 peripheral ========== */ +#define PIN_PA00D_SERCOM1_PAD0 _L_(0) /**< \brief SERCOM1 signal: PAD0 on PA00 mux D */ +#define MUX_PA00D_SERCOM1_PAD0 _L_(3) +#define PINMUX_PA00D_SERCOM1_PAD0 ((PIN_PA00D_SERCOM1_PAD0 << 16) | MUX_PA00D_SERCOM1_PAD0) +#define PORT_PA00D_SERCOM1_PAD0 (_UL_(1) << 0) +#define PIN_PA16C_SERCOM1_PAD0 _L_(16) /**< \brief SERCOM1 signal: PAD0 on PA16 mux C */ +#define MUX_PA16C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PA16C_SERCOM1_PAD0 ((PIN_PA16C_SERCOM1_PAD0 << 16) | MUX_PA16C_SERCOM1_PAD0) +#define PORT_PA16C_SERCOM1_PAD0 (_UL_(1) << 16) +#define PIN_PC22C_SERCOM1_PAD0 _L_(86) /**< \brief SERCOM1 signal: PAD0 on PC22 mux C */ +#define MUX_PC22C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PC22C_SERCOM1_PAD0 ((PIN_PC22C_SERCOM1_PAD0 << 16) | MUX_PC22C_SERCOM1_PAD0) +#define PORT_PC22C_SERCOM1_PAD0 (_UL_(1) << 22) +#define PIN_PC27C_SERCOM1_PAD0 _L_(91) /**< \brief SERCOM1 signal: PAD0 on PC27 mux C */ +#define MUX_PC27C_SERCOM1_PAD0 _L_(2) +#define PINMUX_PC27C_SERCOM1_PAD0 ((PIN_PC27C_SERCOM1_PAD0 << 16) | MUX_PC27C_SERCOM1_PAD0) +#define PORT_PC27C_SERCOM1_PAD0 (_UL_(1) << 27) +#define PIN_PA01D_SERCOM1_PAD1 _L_(1) /**< \brief SERCOM1 signal: PAD1 on PA01 mux D */ +#define MUX_PA01D_SERCOM1_PAD1 _L_(3) +#define PINMUX_PA01D_SERCOM1_PAD1 ((PIN_PA01D_SERCOM1_PAD1 << 16) | MUX_PA01D_SERCOM1_PAD1) +#define PORT_PA01D_SERCOM1_PAD1 (_UL_(1) << 1) +#define PIN_PA17C_SERCOM1_PAD1 _L_(17) /**< \brief SERCOM1 signal: PAD1 on PA17 mux C */ +#define MUX_PA17C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PA17C_SERCOM1_PAD1 ((PIN_PA17C_SERCOM1_PAD1 << 16) | MUX_PA17C_SERCOM1_PAD1) +#define PORT_PA17C_SERCOM1_PAD1 (_UL_(1) << 17) +#define PIN_PC23C_SERCOM1_PAD1 _L_(87) /**< \brief SERCOM1 signal: PAD1 on PC23 mux C */ +#define MUX_PC23C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PC23C_SERCOM1_PAD1 ((PIN_PC23C_SERCOM1_PAD1 << 16) | MUX_PC23C_SERCOM1_PAD1) +#define PORT_PC23C_SERCOM1_PAD1 (_UL_(1) << 23) +#define PIN_PC28C_SERCOM1_PAD1 _L_(92) /**< \brief SERCOM1 signal: PAD1 on PC28 mux C */ +#define MUX_PC28C_SERCOM1_PAD1 _L_(2) +#define PINMUX_PC28C_SERCOM1_PAD1 ((PIN_PC28C_SERCOM1_PAD1 << 16) | MUX_PC28C_SERCOM1_PAD1) +#define PORT_PC28C_SERCOM1_PAD1 (_UL_(1) << 28) +#define PIN_PA30D_SERCOM1_PAD2 _L_(30) /**< \brief SERCOM1 signal: PAD2 on PA30 mux D */ +#define MUX_PA30D_SERCOM1_PAD2 _L_(3) +#define PINMUX_PA30D_SERCOM1_PAD2 ((PIN_PA30D_SERCOM1_PAD2 << 16) | MUX_PA30D_SERCOM1_PAD2) +#define PORT_PA30D_SERCOM1_PAD2 (_UL_(1) << 30) +#define PIN_PA18C_SERCOM1_PAD2 _L_(18) /**< \brief SERCOM1 signal: PAD2 on PA18 mux C */ +#define MUX_PA18C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PA18C_SERCOM1_PAD2 ((PIN_PA18C_SERCOM1_PAD2 << 16) | MUX_PA18C_SERCOM1_PAD2) +#define PORT_PA18C_SERCOM1_PAD2 (_UL_(1) << 18) +#define PIN_PB22C_SERCOM1_PAD2 _L_(54) /**< \brief SERCOM1 signal: PAD2 on PB22 mux C */ +#define MUX_PB22C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PB22C_SERCOM1_PAD2 ((PIN_PB22C_SERCOM1_PAD2 << 16) | MUX_PB22C_SERCOM1_PAD2) +#define PORT_PB22C_SERCOM1_PAD2 (_UL_(1) << 22) +#define PIN_PD20C_SERCOM1_PAD2 _L_(116) /**< \brief SERCOM1 signal: PAD2 on PD20 mux C */ +#define MUX_PD20C_SERCOM1_PAD2 _L_(2) +#define PINMUX_PD20C_SERCOM1_PAD2 ((PIN_PD20C_SERCOM1_PAD2 << 16) | MUX_PD20C_SERCOM1_PAD2) +#define PORT_PD20C_SERCOM1_PAD2 (_UL_(1) << 20) +#define PIN_PA31D_SERCOM1_PAD3 _L_(31) /**< \brief SERCOM1 signal: PAD3 on PA31 mux D */ +#define MUX_PA31D_SERCOM1_PAD3 _L_(3) +#define PINMUX_PA31D_SERCOM1_PAD3 ((PIN_PA31D_SERCOM1_PAD3 << 16) | MUX_PA31D_SERCOM1_PAD3) +#define PORT_PA31D_SERCOM1_PAD3 (_UL_(1) << 31) +#define PIN_PA19C_SERCOM1_PAD3 _L_(19) /**< \brief SERCOM1 signal: PAD3 on PA19 mux C */ +#define MUX_PA19C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PA19C_SERCOM1_PAD3 ((PIN_PA19C_SERCOM1_PAD3 << 16) | MUX_PA19C_SERCOM1_PAD3) +#define PORT_PA19C_SERCOM1_PAD3 (_UL_(1) << 19) +#define PIN_PB23C_SERCOM1_PAD3 _L_(55) /**< \brief SERCOM1 signal: PAD3 on PB23 mux C */ +#define MUX_PB23C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PB23C_SERCOM1_PAD3 ((PIN_PB23C_SERCOM1_PAD3 << 16) | MUX_PB23C_SERCOM1_PAD3) +#define PORT_PB23C_SERCOM1_PAD3 (_UL_(1) << 23) +#define PIN_PD21C_SERCOM1_PAD3 _L_(117) /**< \brief SERCOM1 signal: PAD3 on PD21 mux C */ +#define MUX_PD21C_SERCOM1_PAD3 _L_(2) +#define PINMUX_PD21C_SERCOM1_PAD3 ((PIN_PD21C_SERCOM1_PAD3 << 16) | MUX_PD21C_SERCOM1_PAD3) +#define PORT_PD21C_SERCOM1_PAD3 (_UL_(1) << 21) +/* ========== PORT definition for TC0 peripheral ========== */ +#define PIN_PA04E_TC0_WO0 _L_(4) /**< \brief TC0 signal: WO0 on PA04 mux E */ +#define MUX_PA04E_TC0_WO0 _L_(4) +#define PINMUX_PA04E_TC0_WO0 ((PIN_PA04E_TC0_WO0 << 16) | MUX_PA04E_TC0_WO0) +#define PORT_PA04E_TC0_WO0 (_UL_(1) << 4) +#define PIN_PA08E_TC0_WO0 _L_(8) /**< \brief TC0 signal: WO0 on PA08 mux E */ +#define MUX_PA08E_TC0_WO0 _L_(4) +#define PINMUX_PA08E_TC0_WO0 ((PIN_PA08E_TC0_WO0 << 16) | MUX_PA08E_TC0_WO0) +#define PORT_PA08E_TC0_WO0 (_UL_(1) << 8) +#define PIN_PB30E_TC0_WO0 _L_(62) /**< \brief TC0 signal: WO0 on PB30 mux E */ +#define MUX_PB30E_TC0_WO0 _L_(4) +#define PINMUX_PB30E_TC0_WO0 ((PIN_PB30E_TC0_WO0 << 16) | MUX_PB30E_TC0_WO0) +#define PORT_PB30E_TC0_WO0 (_UL_(1) << 30) +#define PIN_PA05E_TC0_WO1 _L_(5) /**< \brief TC0 signal: WO1 on PA05 mux E */ +#define MUX_PA05E_TC0_WO1 _L_(4) +#define PINMUX_PA05E_TC0_WO1 ((PIN_PA05E_TC0_WO1 << 16) | MUX_PA05E_TC0_WO1) +#define PORT_PA05E_TC0_WO1 (_UL_(1) << 5) +#define PIN_PA09E_TC0_WO1 _L_(9) /**< \brief TC0 signal: WO1 on PA09 mux E */ +#define MUX_PA09E_TC0_WO1 _L_(4) +#define PINMUX_PA09E_TC0_WO1 ((PIN_PA09E_TC0_WO1 << 16) | MUX_PA09E_TC0_WO1) +#define PORT_PA09E_TC0_WO1 (_UL_(1) << 9) +#define PIN_PB31E_TC0_WO1 _L_(63) /**< \brief TC0 signal: WO1 on PB31 mux E */ +#define MUX_PB31E_TC0_WO1 _L_(4) +#define PINMUX_PB31E_TC0_WO1 ((PIN_PB31E_TC0_WO1 << 16) | MUX_PB31E_TC0_WO1) +#define PORT_PB31E_TC0_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC1 peripheral ========== */ +#define PIN_PA06E_TC1_WO0 _L_(6) /**< \brief TC1 signal: WO0 on PA06 mux E */ +#define MUX_PA06E_TC1_WO0 _L_(4) +#define PINMUX_PA06E_TC1_WO0 ((PIN_PA06E_TC1_WO0 << 16) | MUX_PA06E_TC1_WO0) +#define PORT_PA06E_TC1_WO0 (_UL_(1) << 6) +#define PIN_PA10E_TC1_WO0 _L_(10) /**< \brief TC1 signal: WO0 on PA10 mux E */ +#define MUX_PA10E_TC1_WO0 _L_(4) +#define PINMUX_PA10E_TC1_WO0 ((PIN_PA10E_TC1_WO0 << 16) | MUX_PA10E_TC1_WO0) +#define PORT_PA10E_TC1_WO0 (_UL_(1) << 10) +#define PIN_PA07E_TC1_WO1 _L_(7) /**< \brief TC1 signal: WO1 on PA07 mux E */ +#define MUX_PA07E_TC1_WO1 _L_(4) +#define PINMUX_PA07E_TC1_WO1 ((PIN_PA07E_TC1_WO1 << 16) | MUX_PA07E_TC1_WO1) +#define PORT_PA07E_TC1_WO1 (_UL_(1) << 7) +#define PIN_PA11E_TC1_WO1 _L_(11) /**< \brief TC1 signal: WO1 on PA11 mux E */ +#define MUX_PA11E_TC1_WO1 _L_(4) +#define PINMUX_PA11E_TC1_WO1 ((PIN_PA11E_TC1_WO1 << 16) | MUX_PA11E_TC1_WO1) +#define PORT_PA11E_TC1_WO1 (_UL_(1) << 11) +/* ========== PORT definition for USB peripheral ========== */ +#define PIN_PA24H_USB_DM _L_(24) /**< \brief USB signal: DM on PA24 mux H */ +#define MUX_PA24H_USB_DM _L_(7) +#define PINMUX_PA24H_USB_DM ((PIN_PA24H_USB_DM << 16) | MUX_PA24H_USB_DM) +#define PORT_PA24H_USB_DM (_UL_(1) << 24) +#define PIN_PA25H_USB_DP _L_(25) /**< \brief USB signal: DP on PA25 mux H */ +#define MUX_PA25H_USB_DP _L_(7) +#define PINMUX_PA25H_USB_DP ((PIN_PA25H_USB_DP << 16) | MUX_PA25H_USB_DP) +#define PORT_PA25H_USB_DP (_UL_(1) << 25) +#define PIN_PA23H_USB_SOF_1KHZ _L_(23) /**< \brief USB signal: SOF_1KHZ on PA23 mux H */ +#define MUX_PA23H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PA23H_USB_SOF_1KHZ ((PIN_PA23H_USB_SOF_1KHZ << 16) | MUX_PA23H_USB_SOF_1KHZ) +#define PORT_PA23H_USB_SOF_1KHZ (_UL_(1) << 23) +#define PIN_PB22H_USB_SOF_1KHZ _L_(54) /**< \brief USB signal: SOF_1KHZ on PB22 mux H */ +#define MUX_PB22H_USB_SOF_1KHZ _L_(7) +#define PINMUX_PB22H_USB_SOF_1KHZ ((PIN_PB22H_USB_SOF_1KHZ << 16) | MUX_PB22H_USB_SOF_1KHZ) +#define PORT_PB22H_USB_SOF_1KHZ (_UL_(1) << 22) +/* ========== PORT definition for SERCOM2 peripheral ========== */ +#define PIN_PA09D_SERCOM2_PAD0 _L_(9) /**< \brief SERCOM2 signal: PAD0 on PA09 mux D */ +#define MUX_PA09D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PA09D_SERCOM2_PAD0 ((PIN_PA09D_SERCOM2_PAD0 << 16) | MUX_PA09D_SERCOM2_PAD0) +#define PORT_PA09D_SERCOM2_PAD0 (_UL_(1) << 9) +#define PIN_PB25D_SERCOM2_PAD0 _L_(57) /**< \brief SERCOM2 signal: PAD0 on PB25 mux D */ +#define MUX_PB25D_SERCOM2_PAD0 _L_(3) +#define PINMUX_PB25D_SERCOM2_PAD0 ((PIN_PB25D_SERCOM2_PAD0 << 16) | MUX_PB25D_SERCOM2_PAD0) +#define PORT_PB25D_SERCOM2_PAD0 (_UL_(1) << 25) +#define PIN_PA12C_SERCOM2_PAD0 _L_(12) /**< \brief SERCOM2 signal: PAD0 on PA12 mux C */ +#define MUX_PA12C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PA12C_SERCOM2_PAD0 ((PIN_PA12C_SERCOM2_PAD0 << 16) | MUX_PA12C_SERCOM2_PAD0) +#define PORT_PA12C_SERCOM2_PAD0 (_UL_(1) << 12) +#define PIN_PB26C_SERCOM2_PAD0 _L_(58) /**< \brief SERCOM2 signal: PAD0 on PB26 mux C */ +#define MUX_PB26C_SERCOM2_PAD0 _L_(2) +#define PINMUX_PB26C_SERCOM2_PAD0 ((PIN_PB26C_SERCOM2_PAD0 << 16) | MUX_PB26C_SERCOM2_PAD0) +#define PORT_PB26C_SERCOM2_PAD0 (_UL_(1) << 26) +#define PIN_PA08D_SERCOM2_PAD1 _L_(8) /**< \brief SERCOM2 signal: PAD1 on PA08 mux D */ +#define MUX_PA08D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PA08D_SERCOM2_PAD1 ((PIN_PA08D_SERCOM2_PAD1 << 16) | MUX_PA08D_SERCOM2_PAD1) +#define PORT_PA08D_SERCOM2_PAD1 (_UL_(1) << 8) +#define PIN_PB24D_SERCOM2_PAD1 _L_(56) /**< \brief SERCOM2 signal: PAD1 on PB24 mux D */ +#define MUX_PB24D_SERCOM2_PAD1 _L_(3) +#define PINMUX_PB24D_SERCOM2_PAD1 ((PIN_PB24D_SERCOM2_PAD1 << 16) | MUX_PB24D_SERCOM2_PAD1) +#define PORT_PB24D_SERCOM2_PAD1 (_UL_(1) << 24) +#define PIN_PA13C_SERCOM2_PAD1 _L_(13) /**< \brief SERCOM2 signal: PAD1 on PA13 mux C */ +#define MUX_PA13C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PA13C_SERCOM2_PAD1 ((PIN_PA13C_SERCOM2_PAD1 << 16) | MUX_PA13C_SERCOM2_PAD1) +#define PORT_PA13C_SERCOM2_PAD1 (_UL_(1) << 13) +#define PIN_PB27C_SERCOM2_PAD1 _L_(59) /**< \brief SERCOM2 signal: PAD1 on PB27 mux C */ +#define MUX_PB27C_SERCOM2_PAD1 _L_(2) +#define PINMUX_PB27C_SERCOM2_PAD1 ((PIN_PB27C_SERCOM2_PAD1 << 16) | MUX_PB27C_SERCOM2_PAD1) +#define PORT_PB27C_SERCOM2_PAD1 (_UL_(1) << 27) +#define PIN_PA10D_SERCOM2_PAD2 _L_(10) /**< \brief SERCOM2 signal: PAD2 on PA10 mux D */ +#define MUX_PA10D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PA10D_SERCOM2_PAD2 ((PIN_PA10D_SERCOM2_PAD2 << 16) | MUX_PA10D_SERCOM2_PAD2) +#define PORT_PA10D_SERCOM2_PAD2 (_UL_(1) << 10) +#define PIN_PC24D_SERCOM2_PAD2 _L_(88) /**< \brief SERCOM2 signal: PAD2 on PC24 mux D */ +#define MUX_PC24D_SERCOM2_PAD2 _L_(3) +#define PINMUX_PC24D_SERCOM2_PAD2 ((PIN_PC24D_SERCOM2_PAD2 << 16) | MUX_PC24D_SERCOM2_PAD2) +#define PORT_PC24D_SERCOM2_PAD2 (_UL_(1) << 24) +#define PIN_PB28C_SERCOM2_PAD2 _L_(60) /**< \brief SERCOM2 signal: PAD2 on PB28 mux C */ +#define MUX_PB28C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PB28C_SERCOM2_PAD2 ((PIN_PB28C_SERCOM2_PAD2 << 16) | MUX_PB28C_SERCOM2_PAD2) +#define PORT_PB28C_SERCOM2_PAD2 (_UL_(1) << 28) +#define PIN_PA14C_SERCOM2_PAD2 _L_(14) /**< \brief SERCOM2 signal: PAD2 on PA14 mux C */ +#define MUX_PA14C_SERCOM2_PAD2 _L_(2) +#define PINMUX_PA14C_SERCOM2_PAD2 ((PIN_PA14C_SERCOM2_PAD2 << 16) | MUX_PA14C_SERCOM2_PAD2) +#define PORT_PA14C_SERCOM2_PAD2 (_UL_(1) << 14) +#define PIN_PA11D_SERCOM2_PAD3 _L_(11) /**< \brief SERCOM2 signal: PAD3 on PA11 mux D */ +#define MUX_PA11D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PA11D_SERCOM2_PAD3 ((PIN_PA11D_SERCOM2_PAD3 << 16) | MUX_PA11D_SERCOM2_PAD3) +#define PORT_PA11D_SERCOM2_PAD3 (_UL_(1) << 11) +#define PIN_PC25D_SERCOM2_PAD3 _L_(89) /**< \brief SERCOM2 signal: PAD3 on PC25 mux D */ +#define MUX_PC25D_SERCOM2_PAD3 _L_(3) +#define PINMUX_PC25D_SERCOM2_PAD3 ((PIN_PC25D_SERCOM2_PAD3 << 16) | MUX_PC25D_SERCOM2_PAD3) +#define PORT_PC25D_SERCOM2_PAD3 (_UL_(1) << 25) +#define PIN_PB29C_SERCOM2_PAD3 _L_(61) /**< \brief SERCOM2 signal: PAD3 on PB29 mux C */ +#define MUX_PB29C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PB29C_SERCOM2_PAD3 ((PIN_PB29C_SERCOM2_PAD3 << 16) | MUX_PB29C_SERCOM2_PAD3) +#define PORT_PB29C_SERCOM2_PAD3 (_UL_(1) << 29) +#define PIN_PA15C_SERCOM2_PAD3 _L_(15) /**< \brief SERCOM2 signal: PAD3 on PA15 mux C */ +#define MUX_PA15C_SERCOM2_PAD3 _L_(2) +#define PINMUX_PA15C_SERCOM2_PAD3 ((PIN_PA15C_SERCOM2_PAD3 << 16) | MUX_PA15C_SERCOM2_PAD3) +#define PORT_PA15C_SERCOM2_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM3 peripheral ========== */ +#define PIN_PA17D_SERCOM3_PAD0 _L_(17) /**< \brief SERCOM3 signal: PAD0 on PA17 mux D */ +#define MUX_PA17D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PA17D_SERCOM3_PAD0 ((PIN_PA17D_SERCOM3_PAD0 << 16) | MUX_PA17D_SERCOM3_PAD0) +#define PORT_PA17D_SERCOM3_PAD0 (_UL_(1) << 17) +#define PIN_PC23D_SERCOM3_PAD0 _L_(87) /**< \brief SERCOM3 signal: PAD0 on PC23 mux D */ +#define MUX_PC23D_SERCOM3_PAD0 _L_(3) +#define PINMUX_PC23D_SERCOM3_PAD0 ((PIN_PC23D_SERCOM3_PAD0 << 16) | MUX_PC23D_SERCOM3_PAD0) +#define PORT_PC23D_SERCOM3_PAD0 (_UL_(1) << 23) +#define PIN_PA22C_SERCOM3_PAD0 _L_(22) /**< \brief SERCOM3 signal: PAD0 on PA22 mux C */ +#define MUX_PA22C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PA22C_SERCOM3_PAD0 ((PIN_PA22C_SERCOM3_PAD0 << 16) | MUX_PA22C_SERCOM3_PAD0) +#define PORT_PA22C_SERCOM3_PAD0 (_UL_(1) << 22) +#define PIN_PB20C_SERCOM3_PAD0 _L_(52) /**< \brief SERCOM3 signal: PAD0 on PB20 mux C */ +#define MUX_PB20C_SERCOM3_PAD0 _L_(2) +#define PINMUX_PB20C_SERCOM3_PAD0 ((PIN_PB20C_SERCOM3_PAD0 << 16) | MUX_PB20C_SERCOM3_PAD0) +#define PORT_PB20C_SERCOM3_PAD0 (_UL_(1) << 20) +#define PIN_PA16D_SERCOM3_PAD1 _L_(16) /**< \brief SERCOM3 signal: PAD1 on PA16 mux D */ +#define MUX_PA16D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PA16D_SERCOM3_PAD1 ((PIN_PA16D_SERCOM3_PAD1 << 16) | MUX_PA16D_SERCOM3_PAD1) +#define PORT_PA16D_SERCOM3_PAD1 (_UL_(1) << 16) +#define PIN_PC22D_SERCOM3_PAD1 _L_(86) /**< \brief SERCOM3 signal: PAD1 on PC22 mux D */ +#define MUX_PC22D_SERCOM3_PAD1 _L_(3) +#define PINMUX_PC22D_SERCOM3_PAD1 ((PIN_PC22D_SERCOM3_PAD1 << 16) | MUX_PC22D_SERCOM3_PAD1) +#define PORT_PC22D_SERCOM3_PAD1 (_UL_(1) << 22) +#define PIN_PA23C_SERCOM3_PAD1 _L_(23) /**< \brief SERCOM3 signal: PAD1 on PA23 mux C */ +#define MUX_PA23C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PA23C_SERCOM3_PAD1 ((PIN_PA23C_SERCOM3_PAD1 << 16) | MUX_PA23C_SERCOM3_PAD1) +#define PORT_PA23C_SERCOM3_PAD1 (_UL_(1) << 23) +#define PIN_PB21C_SERCOM3_PAD1 _L_(53) /**< \brief SERCOM3 signal: PAD1 on PB21 mux C */ +#define MUX_PB21C_SERCOM3_PAD1 _L_(2) +#define PINMUX_PB21C_SERCOM3_PAD1 ((PIN_PB21C_SERCOM3_PAD1 << 16) | MUX_PB21C_SERCOM3_PAD1) +#define PORT_PB21C_SERCOM3_PAD1 (_UL_(1) << 21) +#define PIN_PA18D_SERCOM3_PAD2 _L_(18) /**< \brief SERCOM3 signal: PAD2 on PA18 mux D */ +#define MUX_PA18D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA18D_SERCOM3_PAD2 ((PIN_PA18D_SERCOM3_PAD2 << 16) | MUX_PA18D_SERCOM3_PAD2) +#define PORT_PA18D_SERCOM3_PAD2 (_UL_(1) << 18) +#define PIN_PA20D_SERCOM3_PAD2 _L_(20) /**< \brief SERCOM3 signal: PAD2 on PA20 mux D */ +#define MUX_PA20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PA20D_SERCOM3_PAD2 ((PIN_PA20D_SERCOM3_PAD2 << 16) | MUX_PA20D_SERCOM3_PAD2) +#define PORT_PA20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PD20D_SERCOM3_PAD2 _L_(116) /**< \brief SERCOM3 signal: PAD2 on PD20 mux D */ +#define MUX_PD20D_SERCOM3_PAD2 _L_(3) +#define PINMUX_PD20D_SERCOM3_PAD2 ((PIN_PD20D_SERCOM3_PAD2 << 16) | MUX_PD20D_SERCOM3_PAD2) +#define PORT_PD20D_SERCOM3_PAD2 (_UL_(1) << 20) +#define PIN_PA24C_SERCOM3_PAD2 _L_(24) /**< \brief SERCOM3 signal: PAD2 on PA24 mux C */ +#define MUX_PA24C_SERCOM3_PAD2 _L_(2) +#define PINMUX_PA24C_SERCOM3_PAD2 ((PIN_PA24C_SERCOM3_PAD2 << 16) | MUX_PA24C_SERCOM3_PAD2) +#define PORT_PA24C_SERCOM3_PAD2 (_UL_(1) << 24) +#define PIN_PA19D_SERCOM3_PAD3 _L_(19) /**< \brief SERCOM3 signal: PAD3 on PA19 mux D */ +#define MUX_PA19D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA19D_SERCOM3_PAD3 ((PIN_PA19D_SERCOM3_PAD3 << 16) | MUX_PA19D_SERCOM3_PAD3) +#define PORT_PA19D_SERCOM3_PAD3 (_UL_(1) << 19) +#define PIN_PA21D_SERCOM3_PAD3 _L_(21) /**< \brief SERCOM3 signal: PAD3 on PA21 mux D */ +#define MUX_PA21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PA21D_SERCOM3_PAD3 ((PIN_PA21D_SERCOM3_PAD3 << 16) | MUX_PA21D_SERCOM3_PAD3) +#define PORT_PA21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PD21D_SERCOM3_PAD3 _L_(117) /**< \brief SERCOM3 signal: PAD3 on PD21 mux D */ +#define MUX_PD21D_SERCOM3_PAD3 _L_(3) +#define PINMUX_PD21D_SERCOM3_PAD3 ((PIN_PD21D_SERCOM3_PAD3 << 16) | MUX_PD21D_SERCOM3_PAD3) +#define PORT_PD21D_SERCOM3_PAD3 (_UL_(1) << 21) +#define PIN_PA25C_SERCOM3_PAD3 _L_(25) /**< \brief SERCOM3 signal: PAD3 on PA25 mux C */ +#define MUX_PA25C_SERCOM3_PAD3 _L_(2) +#define PINMUX_PA25C_SERCOM3_PAD3 ((PIN_PA25C_SERCOM3_PAD3 << 16) | MUX_PA25C_SERCOM3_PAD3) +#define PORT_PA25C_SERCOM3_PAD3 (_UL_(1) << 25) +/* ========== PORT definition for TCC0 peripheral ========== */ +#define PIN_PA20G_TCC0_WO0 _L_(20) /**< \brief TCC0 signal: WO0 on PA20 mux G */ +#define MUX_PA20G_TCC0_WO0 _L_(6) +#define PINMUX_PA20G_TCC0_WO0 ((PIN_PA20G_TCC0_WO0 << 16) | MUX_PA20G_TCC0_WO0) +#define PORT_PA20G_TCC0_WO0 (_UL_(1) << 20) +#define PIN_PB12G_TCC0_WO0 _L_(44) /**< \brief TCC0 signal: WO0 on PB12 mux G */ +#define MUX_PB12G_TCC0_WO0 _L_(6) +#define PINMUX_PB12G_TCC0_WO0 ((PIN_PB12G_TCC0_WO0 << 16) | MUX_PB12G_TCC0_WO0) +#define PORT_PB12G_TCC0_WO0 (_UL_(1) << 12) +#define PIN_PA08F_TCC0_WO0 _L_(8) /**< \brief TCC0 signal: WO0 on PA08 mux F */ +#define MUX_PA08F_TCC0_WO0 _L_(5) +#define PINMUX_PA08F_TCC0_WO0 ((PIN_PA08F_TCC0_WO0 << 16) | MUX_PA08F_TCC0_WO0) +#define PORT_PA08F_TCC0_WO0 (_UL_(1) << 8) +#define PIN_PC04F_TCC0_WO0 _L_(68) /**< \brief TCC0 signal: WO0 on PC04 mux F */ +#define MUX_PC04F_TCC0_WO0 _L_(5) +#define PINMUX_PC04F_TCC0_WO0 ((PIN_PC04F_TCC0_WO0 << 16) | MUX_PC04F_TCC0_WO0) +#define PORT_PC04F_TCC0_WO0 (_UL_(1) << 4) +#define PIN_PC10F_TCC0_WO0 _L_(74) /**< \brief TCC0 signal: WO0 on PC10 mux F */ +#define MUX_PC10F_TCC0_WO0 _L_(5) +#define PINMUX_PC10F_TCC0_WO0 ((PIN_PC10F_TCC0_WO0 << 16) | MUX_PC10F_TCC0_WO0) +#define PORT_PC10F_TCC0_WO0 (_UL_(1) << 10) +#define PIN_PC16F_TCC0_WO0 _L_(80) /**< \brief TCC0 signal: WO0 on PC16 mux F */ +#define MUX_PC16F_TCC0_WO0 _L_(5) +#define PINMUX_PC16F_TCC0_WO0 ((PIN_PC16F_TCC0_WO0 << 16) | MUX_PC16F_TCC0_WO0) +#define PORT_PC16F_TCC0_WO0 (_UL_(1) << 16) +#define PIN_PA21G_TCC0_WO1 _L_(21) /**< \brief TCC0 signal: WO1 on PA21 mux G */ +#define MUX_PA21G_TCC0_WO1 _L_(6) +#define PINMUX_PA21G_TCC0_WO1 ((PIN_PA21G_TCC0_WO1 << 16) | MUX_PA21G_TCC0_WO1) +#define PORT_PA21G_TCC0_WO1 (_UL_(1) << 21) +#define PIN_PB13G_TCC0_WO1 _L_(45) /**< \brief TCC0 signal: WO1 on PB13 mux G */ +#define MUX_PB13G_TCC0_WO1 _L_(6) +#define PINMUX_PB13G_TCC0_WO1 ((PIN_PB13G_TCC0_WO1 << 16) | MUX_PB13G_TCC0_WO1) +#define PORT_PB13G_TCC0_WO1 (_UL_(1) << 13) +#define PIN_PA09F_TCC0_WO1 _L_(9) /**< \brief TCC0 signal: WO1 on PA09 mux F */ +#define MUX_PA09F_TCC0_WO1 _L_(5) +#define PINMUX_PA09F_TCC0_WO1 ((PIN_PA09F_TCC0_WO1 << 16) | MUX_PA09F_TCC0_WO1) +#define PORT_PA09F_TCC0_WO1 (_UL_(1) << 9) +#define PIN_PC11F_TCC0_WO1 _L_(75) /**< \brief TCC0 signal: WO1 on PC11 mux F */ +#define MUX_PC11F_TCC0_WO1 _L_(5) +#define PINMUX_PC11F_TCC0_WO1 ((PIN_PC11F_TCC0_WO1 << 16) | MUX_PC11F_TCC0_WO1) +#define PORT_PC11F_TCC0_WO1 (_UL_(1) << 11) +#define PIN_PC17F_TCC0_WO1 _L_(81) /**< \brief TCC0 signal: WO1 on PC17 mux F */ +#define MUX_PC17F_TCC0_WO1 _L_(5) +#define PINMUX_PC17F_TCC0_WO1 ((PIN_PC17F_TCC0_WO1 << 16) | MUX_PC17F_TCC0_WO1) +#define PORT_PC17F_TCC0_WO1 (_UL_(1) << 17) +#define PIN_PD08F_TCC0_WO1 _L_(104) /**< \brief TCC0 signal: WO1 on PD08 mux F */ +#define MUX_PD08F_TCC0_WO1 _L_(5) +#define PINMUX_PD08F_TCC0_WO1 ((PIN_PD08F_TCC0_WO1 << 16) | MUX_PD08F_TCC0_WO1) +#define PORT_PD08F_TCC0_WO1 (_UL_(1) << 8) +#define PIN_PA22G_TCC0_WO2 _L_(22) /**< \brief TCC0 signal: WO2 on PA22 mux G */ +#define MUX_PA22G_TCC0_WO2 _L_(6) +#define PINMUX_PA22G_TCC0_WO2 ((PIN_PA22G_TCC0_WO2 << 16) | MUX_PA22G_TCC0_WO2) +#define PORT_PA22G_TCC0_WO2 (_UL_(1) << 22) +#define PIN_PB14G_TCC0_WO2 _L_(46) /**< \brief TCC0 signal: WO2 on PB14 mux G */ +#define MUX_PB14G_TCC0_WO2 _L_(6) +#define PINMUX_PB14G_TCC0_WO2 ((PIN_PB14G_TCC0_WO2 << 16) | MUX_PB14G_TCC0_WO2) +#define PORT_PB14G_TCC0_WO2 (_UL_(1) << 14) +#define PIN_PA10F_TCC0_WO2 _L_(10) /**< \brief TCC0 signal: WO2 on PA10 mux F */ +#define MUX_PA10F_TCC0_WO2 _L_(5) +#define PINMUX_PA10F_TCC0_WO2 ((PIN_PA10F_TCC0_WO2 << 16) | MUX_PA10F_TCC0_WO2) +#define PORT_PA10F_TCC0_WO2 (_UL_(1) << 10) +#define PIN_PC12F_TCC0_WO2 _L_(76) /**< \brief TCC0 signal: WO2 on PC12 mux F */ +#define MUX_PC12F_TCC0_WO2 _L_(5) +#define PINMUX_PC12F_TCC0_WO2 ((PIN_PC12F_TCC0_WO2 << 16) | MUX_PC12F_TCC0_WO2) +#define PORT_PC12F_TCC0_WO2 (_UL_(1) << 12) +#define PIN_PC18F_TCC0_WO2 _L_(82) /**< \brief TCC0 signal: WO2 on PC18 mux F */ +#define MUX_PC18F_TCC0_WO2 _L_(5) +#define PINMUX_PC18F_TCC0_WO2 ((PIN_PC18F_TCC0_WO2 << 16) | MUX_PC18F_TCC0_WO2) +#define PORT_PC18F_TCC0_WO2 (_UL_(1) << 18) +#define PIN_PD09F_TCC0_WO2 _L_(105) /**< \brief TCC0 signal: WO2 on PD09 mux F */ +#define MUX_PD09F_TCC0_WO2 _L_(5) +#define PINMUX_PD09F_TCC0_WO2 ((PIN_PD09F_TCC0_WO2 << 16) | MUX_PD09F_TCC0_WO2) +#define PORT_PD09F_TCC0_WO2 (_UL_(1) << 9) +#define PIN_PA23G_TCC0_WO3 _L_(23) /**< \brief TCC0 signal: WO3 on PA23 mux G */ +#define MUX_PA23G_TCC0_WO3 _L_(6) +#define PINMUX_PA23G_TCC0_WO3 ((PIN_PA23G_TCC0_WO3 << 16) | MUX_PA23G_TCC0_WO3) +#define PORT_PA23G_TCC0_WO3 (_UL_(1) << 23) +#define PIN_PB15G_TCC0_WO3 _L_(47) /**< \brief TCC0 signal: WO3 on PB15 mux G */ +#define MUX_PB15G_TCC0_WO3 _L_(6) +#define PINMUX_PB15G_TCC0_WO3 ((PIN_PB15G_TCC0_WO3 << 16) | MUX_PB15G_TCC0_WO3) +#define PORT_PB15G_TCC0_WO3 (_UL_(1) << 15) +#define PIN_PA11F_TCC0_WO3 _L_(11) /**< \brief TCC0 signal: WO3 on PA11 mux F */ +#define MUX_PA11F_TCC0_WO3 _L_(5) +#define PINMUX_PA11F_TCC0_WO3 ((PIN_PA11F_TCC0_WO3 << 16) | MUX_PA11F_TCC0_WO3) +#define PORT_PA11F_TCC0_WO3 (_UL_(1) << 11) +#define PIN_PC13F_TCC0_WO3 _L_(77) /**< \brief TCC0 signal: WO3 on PC13 mux F */ +#define MUX_PC13F_TCC0_WO3 _L_(5) +#define PINMUX_PC13F_TCC0_WO3 ((PIN_PC13F_TCC0_WO3 << 16) | MUX_PC13F_TCC0_WO3) +#define PORT_PC13F_TCC0_WO3 (_UL_(1) << 13) +#define PIN_PC19F_TCC0_WO3 _L_(83) /**< \brief TCC0 signal: WO3 on PC19 mux F */ +#define MUX_PC19F_TCC0_WO3 _L_(5) +#define PINMUX_PC19F_TCC0_WO3 ((PIN_PC19F_TCC0_WO3 << 16) | MUX_PC19F_TCC0_WO3) +#define PORT_PC19F_TCC0_WO3 (_UL_(1) << 19) +#define PIN_PD10F_TCC0_WO3 _L_(106) /**< \brief TCC0 signal: WO3 on PD10 mux F */ +#define MUX_PD10F_TCC0_WO3 _L_(5) +#define PINMUX_PD10F_TCC0_WO3 ((PIN_PD10F_TCC0_WO3 << 16) | MUX_PD10F_TCC0_WO3) +#define PORT_PD10F_TCC0_WO3 (_UL_(1) << 10) +#define PIN_PA16G_TCC0_WO4 _L_(16) /**< \brief TCC0 signal: WO4 on PA16 mux G */ +#define MUX_PA16G_TCC0_WO4 _L_(6) +#define PINMUX_PA16G_TCC0_WO4 ((PIN_PA16G_TCC0_WO4 << 16) | MUX_PA16G_TCC0_WO4) +#define PORT_PA16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB16G_TCC0_WO4 _L_(48) /**< \brief TCC0 signal: WO4 on PB16 mux G */ +#define MUX_PB16G_TCC0_WO4 _L_(6) +#define PINMUX_PB16G_TCC0_WO4 ((PIN_PB16G_TCC0_WO4 << 16) | MUX_PB16G_TCC0_WO4) +#define PORT_PB16G_TCC0_WO4 (_UL_(1) << 16) +#define PIN_PB10F_TCC0_WO4 _L_(42) /**< \brief TCC0 signal: WO4 on PB10 mux F */ +#define MUX_PB10F_TCC0_WO4 _L_(5) +#define PINMUX_PB10F_TCC0_WO4 ((PIN_PB10F_TCC0_WO4 << 16) | MUX_PB10F_TCC0_WO4) +#define PORT_PB10F_TCC0_WO4 (_UL_(1) << 10) +#define PIN_PC14F_TCC0_WO4 _L_(78) /**< \brief TCC0 signal: WO4 on PC14 mux F */ +#define MUX_PC14F_TCC0_WO4 _L_(5) +#define PINMUX_PC14F_TCC0_WO4 ((PIN_PC14F_TCC0_WO4 << 16) | MUX_PC14F_TCC0_WO4) +#define PORT_PC14F_TCC0_WO4 (_UL_(1) << 14) +#define PIN_PC20F_TCC0_WO4 _L_(84) /**< \brief TCC0 signal: WO4 on PC20 mux F */ +#define MUX_PC20F_TCC0_WO4 _L_(5) +#define PINMUX_PC20F_TCC0_WO4 ((PIN_PC20F_TCC0_WO4 << 16) | MUX_PC20F_TCC0_WO4) +#define PORT_PC20F_TCC0_WO4 (_UL_(1) << 20) +#define PIN_PD11F_TCC0_WO4 _L_(107) /**< \brief TCC0 signal: WO4 on PD11 mux F */ +#define MUX_PD11F_TCC0_WO4 _L_(5) +#define PINMUX_PD11F_TCC0_WO4 ((PIN_PD11F_TCC0_WO4 << 16) | MUX_PD11F_TCC0_WO4) +#define PORT_PD11F_TCC0_WO4 (_UL_(1) << 11) +#define PIN_PA17G_TCC0_WO5 _L_(17) /**< \brief TCC0 signal: WO5 on PA17 mux G */ +#define MUX_PA17G_TCC0_WO5 _L_(6) +#define PINMUX_PA17G_TCC0_WO5 ((PIN_PA17G_TCC0_WO5 << 16) | MUX_PA17G_TCC0_WO5) +#define PORT_PA17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB17G_TCC0_WO5 _L_(49) /**< \brief TCC0 signal: WO5 on PB17 mux G */ +#define MUX_PB17G_TCC0_WO5 _L_(6) +#define PINMUX_PB17G_TCC0_WO5 ((PIN_PB17G_TCC0_WO5 << 16) | MUX_PB17G_TCC0_WO5) +#define PORT_PB17G_TCC0_WO5 (_UL_(1) << 17) +#define PIN_PB11F_TCC0_WO5 _L_(43) /**< \brief TCC0 signal: WO5 on PB11 mux F */ +#define MUX_PB11F_TCC0_WO5 _L_(5) +#define PINMUX_PB11F_TCC0_WO5 ((PIN_PB11F_TCC0_WO5 << 16) | MUX_PB11F_TCC0_WO5) +#define PORT_PB11F_TCC0_WO5 (_UL_(1) << 11) +#define PIN_PC15F_TCC0_WO5 _L_(79) /**< \brief TCC0 signal: WO5 on PC15 mux F */ +#define MUX_PC15F_TCC0_WO5 _L_(5) +#define PINMUX_PC15F_TCC0_WO5 ((PIN_PC15F_TCC0_WO5 << 16) | MUX_PC15F_TCC0_WO5) +#define PORT_PC15F_TCC0_WO5 (_UL_(1) << 15) +#define PIN_PC21F_TCC0_WO5 _L_(85) /**< \brief TCC0 signal: WO5 on PC21 mux F */ +#define MUX_PC21F_TCC0_WO5 _L_(5) +#define PINMUX_PC21F_TCC0_WO5 ((PIN_PC21F_TCC0_WO5 << 16) | MUX_PC21F_TCC0_WO5) +#define PORT_PC21F_TCC0_WO5 (_UL_(1) << 21) +#define PIN_PD12F_TCC0_WO5 _L_(108) /**< \brief TCC0 signal: WO5 on PD12 mux F */ +#define MUX_PD12F_TCC0_WO5 _L_(5) +#define PINMUX_PD12F_TCC0_WO5 ((PIN_PD12F_TCC0_WO5 << 16) | MUX_PD12F_TCC0_WO5) +#define PORT_PD12F_TCC0_WO5 (_UL_(1) << 12) +#define PIN_PA18G_TCC0_WO6 _L_(18) /**< \brief TCC0 signal: WO6 on PA18 mux G */ +#define MUX_PA18G_TCC0_WO6 _L_(6) +#define PINMUX_PA18G_TCC0_WO6 ((PIN_PA18G_TCC0_WO6 << 16) | MUX_PA18G_TCC0_WO6) +#define PORT_PA18G_TCC0_WO6 (_UL_(1) << 18) +#define PIN_PB30G_TCC0_WO6 _L_(62) /**< \brief TCC0 signal: WO6 on PB30 mux G */ +#define MUX_PB30G_TCC0_WO6 _L_(6) +#define PINMUX_PB30G_TCC0_WO6 ((PIN_PB30G_TCC0_WO6 << 16) | MUX_PB30G_TCC0_WO6) +#define PORT_PB30G_TCC0_WO6 (_UL_(1) << 30) +#define PIN_PA12F_TCC0_WO6 _L_(12) /**< \brief TCC0 signal: WO6 on PA12 mux F */ +#define MUX_PA12F_TCC0_WO6 _L_(5) +#define PINMUX_PA12F_TCC0_WO6 ((PIN_PA12F_TCC0_WO6 << 16) | MUX_PA12F_TCC0_WO6) +#define PORT_PA12F_TCC0_WO6 (_UL_(1) << 12) +#define PIN_PC22F_TCC0_WO6 _L_(86) /**< \brief TCC0 signal: WO6 on PC22 mux F */ +#define MUX_PC22F_TCC0_WO6 _L_(5) +#define PINMUX_PC22F_TCC0_WO6 ((PIN_PC22F_TCC0_WO6 << 16) | MUX_PC22F_TCC0_WO6) +#define PORT_PC22F_TCC0_WO6 (_UL_(1) << 22) +#define PIN_PA19G_TCC0_WO7 _L_(19) /**< \brief TCC0 signal: WO7 on PA19 mux G */ +#define MUX_PA19G_TCC0_WO7 _L_(6) +#define PINMUX_PA19G_TCC0_WO7 ((PIN_PA19G_TCC0_WO7 << 16) | MUX_PA19G_TCC0_WO7) +#define PORT_PA19G_TCC0_WO7 (_UL_(1) << 19) +#define PIN_PB31G_TCC0_WO7 _L_(63) /**< \brief TCC0 signal: WO7 on PB31 mux G */ +#define MUX_PB31G_TCC0_WO7 _L_(6) +#define PINMUX_PB31G_TCC0_WO7 ((PIN_PB31G_TCC0_WO7 << 16) | MUX_PB31G_TCC0_WO7) +#define PORT_PB31G_TCC0_WO7 (_UL_(1) << 31) +#define PIN_PA13F_TCC0_WO7 _L_(13) /**< \brief TCC0 signal: WO7 on PA13 mux F */ +#define MUX_PA13F_TCC0_WO7 _L_(5) +#define PINMUX_PA13F_TCC0_WO7 ((PIN_PA13F_TCC0_WO7 << 16) | MUX_PA13F_TCC0_WO7) +#define PORT_PA13F_TCC0_WO7 (_UL_(1) << 13) +#define PIN_PC23F_TCC0_WO7 _L_(87) /**< \brief TCC0 signal: WO7 on PC23 mux F */ +#define MUX_PC23F_TCC0_WO7 _L_(5) +#define PINMUX_PC23F_TCC0_WO7 ((PIN_PC23F_TCC0_WO7 << 16) | MUX_PC23F_TCC0_WO7) +#define PORT_PC23F_TCC0_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TCC1 peripheral ========== */ +#define PIN_PB10G_TCC1_WO0 _L_(42) /**< \brief TCC1 signal: WO0 on PB10 mux G */ +#define MUX_PB10G_TCC1_WO0 _L_(6) +#define PINMUX_PB10G_TCC1_WO0 ((PIN_PB10G_TCC1_WO0 << 16) | MUX_PB10G_TCC1_WO0) +#define PORT_PB10G_TCC1_WO0 (_UL_(1) << 10) +#define PIN_PC14G_TCC1_WO0 _L_(78) /**< \brief TCC1 signal: WO0 on PC14 mux G */ +#define MUX_PC14G_TCC1_WO0 _L_(6) +#define PINMUX_PC14G_TCC1_WO0 ((PIN_PC14G_TCC1_WO0 << 16) | MUX_PC14G_TCC1_WO0) +#define PORT_PC14G_TCC1_WO0 (_UL_(1) << 14) +#define PIN_PA16F_TCC1_WO0 _L_(16) /**< \brief TCC1 signal: WO0 on PA16 mux F */ +#define MUX_PA16F_TCC1_WO0 _L_(5) +#define PINMUX_PA16F_TCC1_WO0 ((PIN_PA16F_TCC1_WO0 << 16) | MUX_PA16F_TCC1_WO0) +#define PORT_PA16F_TCC1_WO0 (_UL_(1) << 16) +#define PIN_PB18F_TCC1_WO0 _L_(50) /**< \brief TCC1 signal: WO0 on PB18 mux F */ +#define MUX_PB18F_TCC1_WO0 _L_(5) +#define PINMUX_PB18F_TCC1_WO0 ((PIN_PB18F_TCC1_WO0 << 16) | MUX_PB18F_TCC1_WO0) +#define PORT_PB18F_TCC1_WO0 (_UL_(1) << 18) +#define PIN_PD20F_TCC1_WO0 _L_(116) /**< \brief TCC1 signal: WO0 on PD20 mux F */ +#define MUX_PD20F_TCC1_WO0 _L_(5) +#define PINMUX_PD20F_TCC1_WO0 ((PIN_PD20F_TCC1_WO0 << 16) | MUX_PD20F_TCC1_WO0) +#define PORT_PD20F_TCC1_WO0 (_UL_(1) << 20) +#define PIN_PB11G_TCC1_WO1 _L_(43) /**< \brief TCC1 signal: WO1 on PB11 mux G */ +#define MUX_PB11G_TCC1_WO1 _L_(6) +#define PINMUX_PB11G_TCC1_WO1 ((PIN_PB11G_TCC1_WO1 << 16) | MUX_PB11G_TCC1_WO1) +#define PORT_PB11G_TCC1_WO1 (_UL_(1) << 11) +#define PIN_PC15G_TCC1_WO1 _L_(79) /**< \brief TCC1 signal: WO1 on PC15 mux G */ +#define MUX_PC15G_TCC1_WO1 _L_(6) +#define PINMUX_PC15G_TCC1_WO1 ((PIN_PC15G_TCC1_WO1 << 16) | MUX_PC15G_TCC1_WO1) +#define PORT_PC15G_TCC1_WO1 (_UL_(1) << 15) +#define PIN_PA17F_TCC1_WO1 _L_(17) /**< \brief TCC1 signal: WO1 on PA17 mux F */ +#define MUX_PA17F_TCC1_WO1 _L_(5) +#define PINMUX_PA17F_TCC1_WO1 ((PIN_PA17F_TCC1_WO1 << 16) | MUX_PA17F_TCC1_WO1) +#define PORT_PA17F_TCC1_WO1 (_UL_(1) << 17) +#define PIN_PB19F_TCC1_WO1 _L_(51) /**< \brief TCC1 signal: WO1 on PB19 mux F */ +#define MUX_PB19F_TCC1_WO1 _L_(5) +#define PINMUX_PB19F_TCC1_WO1 ((PIN_PB19F_TCC1_WO1 << 16) | MUX_PB19F_TCC1_WO1) +#define PORT_PB19F_TCC1_WO1 (_UL_(1) << 19) +#define PIN_PD21F_TCC1_WO1 _L_(117) /**< \brief TCC1 signal: WO1 on PD21 mux F */ +#define MUX_PD21F_TCC1_WO1 _L_(5) +#define PINMUX_PD21F_TCC1_WO1 ((PIN_PD21F_TCC1_WO1 << 16) | MUX_PD21F_TCC1_WO1) +#define PORT_PD21F_TCC1_WO1 (_UL_(1) << 21) +#define PIN_PA12G_TCC1_WO2 _L_(12) /**< \brief TCC1 signal: WO2 on PA12 mux G */ +#define MUX_PA12G_TCC1_WO2 _L_(6) +#define PINMUX_PA12G_TCC1_WO2 ((PIN_PA12G_TCC1_WO2 << 16) | MUX_PA12G_TCC1_WO2) +#define PORT_PA12G_TCC1_WO2 (_UL_(1) << 12) +#define PIN_PA14G_TCC1_WO2 _L_(14) /**< \brief TCC1 signal: WO2 on PA14 mux G */ +#define MUX_PA14G_TCC1_WO2 _L_(6) +#define PINMUX_PA14G_TCC1_WO2 ((PIN_PA14G_TCC1_WO2 << 16) | MUX_PA14G_TCC1_WO2) +#define PORT_PA14G_TCC1_WO2 (_UL_(1) << 14) +#define PIN_PA18F_TCC1_WO2 _L_(18) /**< \brief TCC1 signal: WO2 on PA18 mux F */ +#define MUX_PA18F_TCC1_WO2 _L_(5) +#define PINMUX_PA18F_TCC1_WO2 ((PIN_PA18F_TCC1_WO2 << 16) | MUX_PA18F_TCC1_WO2) +#define PORT_PA18F_TCC1_WO2 (_UL_(1) << 18) +#define PIN_PB20F_TCC1_WO2 _L_(52) /**< \brief TCC1 signal: WO2 on PB20 mux F */ +#define MUX_PB20F_TCC1_WO2 _L_(5) +#define PINMUX_PB20F_TCC1_WO2 ((PIN_PB20F_TCC1_WO2 << 16) | MUX_PB20F_TCC1_WO2) +#define PORT_PB20F_TCC1_WO2 (_UL_(1) << 20) +#define PIN_PB26F_TCC1_WO2 _L_(58) /**< \brief TCC1 signal: WO2 on PB26 mux F */ +#define MUX_PB26F_TCC1_WO2 _L_(5) +#define PINMUX_PB26F_TCC1_WO2 ((PIN_PB26F_TCC1_WO2 << 16) | MUX_PB26F_TCC1_WO2) +#define PORT_PB26F_TCC1_WO2 (_UL_(1) << 26) +#define PIN_PA13G_TCC1_WO3 _L_(13) /**< \brief TCC1 signal: WO3 on PA13 mux G */ +#define MUX_PA13G_TCC1_WO3 _L_(6) +#define PINMUX_PA13G_TCC1_WO3 ((PIN_PA13G_TCC1_WO3 << 16) | MUX_PA13G_TCC1_WO3) +#define PORT_PA13G_TCC1_WO3 (_UL_(1) << 13) +#define PIN_PA15G_TCC1_WO3 _L_(15) /**< \brief TCC1 signal: WO3 on PA15 mux G */ +#define MUX_PA15G_TCC1_WO3 _L_(6) +#define PINMUX_PA15G_TCC1_WO3 ((PIN_PA15G_TCC1_WO3 << 16) | MUX_PA15G_TCC1_WO3) +#define PORT_PA15G_TCC1_WO3 (_UL_(1) << 15) +#define PIN_PA19F_TCC1_WO3 _L_(19) /**< \brief TCC1 signal: WO3 on PA19 mux F */ +#define MUX_PA19F_TCC1_WO3 _L_(5) +#define PINMUX_PA19F_TCC1_WO3 ((PIN_PA19F_TCC1_WO3 << 16) | MUX_PA19F_TCC1_WO3) +#define PORT_PA19F_TCC1_WO3 (_UL_(1) << 19) +#define PIN_PB21F_TCC1_WO3 _L_(53) /**< \brief TCC1 signal: WO3 on PB21 mux F */ +#define MUX_PB21F_TCC1_WO3 _L_(5) +#define PINMUX_PB21F_TCC1_WO3 ((PIN_PB21F_TCC1_WO3 << 16) | MUX_PB21F_TCC1_WO3) +#define PORT_PB21F_TCC1_WO3 (_UL_(1) << 21) +#define PIN_PB27F_TCC1_WO3 _L_(59) /**< \brief TCC1 signal: WO3 on PB27 mux F */ +#define MUX_PB27F_TCC1_WO3 _L_(5) +#define PINMUX_PB27F_TCC1_WO3 ((PIN_PB27F_TCC1_WO3 << 16) | MUX_PB27F_TCC1_WO3) +#define PORT_PB27F_TCC1_WO3 (_UL_(1) << 27) +#define PIN_PA08G_TCC1_WO4 _L_(8) /**< \brief TCC1 signal: WO4 on PA08 mux G */ +#define MUX_PA08G_TCC1_WO4 _L_(6) +#define PINMUX_PA08G_TCC1_WO4 ((PIN_PA08G_TCC1_WO4 << 16) | MUX_PA08G_TCC1_WO4) +#define PORT_PA08G_TCC1_WO4 (_UL_(1) << 8) +#define PIN_PC10G_TCC1_WO4 _L_(74) /**< \brief TCC1 signal: WO4 on PC10 mux G */ +#define MUX_PC10G_TCC1_WO4 _L_(6) +#define PINMUX_PC10G_TCC1_WO4 ((PIN_PC10G_TCC1_WO4 << 16) | MUX_PC10G_TCC1_WO4) +#define PORT_PC10G_TCC1_WO4 (_UL_(1) << 10) +#define PIN_PA20F_TCC1_WO4 _L_(20) /**< \brief TCC1 signal: WO4 on PA20 mux F */ +#define MUX_PA20F_TCC1_WO4 _L_(5) +#define PINMUX_PA20F_TCC1_WO4 ((PIN_PA20F_TCC1_WO4 << 16) | MUX_PA20F_TCC1_WO4) +#define PORT_PA20F_TCC1_WO4 (_UL_(1) << 20) +#define PIN_PB28F_TCC1_WO4 _L_(60) /**< \brief TCC1 signal: WO4 on PB28 mux F */ +#define MUX_PB28F_TCC1_WO4 _L_(5) +#define PINMUX_PB28F_TCC1_WO4 ((PIN_PB28F_TCC1_WO4 << 16) | MUX_PB28F_TCC1_WO4) +#define PORT_PB28F_TCC1_WO4 (_UL_(1) << 28) +#define PIN_PA09G_TCC1_WO5 _L_(9) /**< \brief TCC1 signal: WO5 on PA09 mux G */ +#define MUX_PA09G_TCC1_WO5 _L_(6) +#define PINMUX_PA09G_TCC1_WO5 ((PIN_PA09G_TCC1_WO5 << 16) | MUX_PA09G_TCC1_WO5) +#define PORT_PA09G_TCC1_WO5 (_UL_(1) << 9) +#define PIN_PC11G_TCC1_WO5 _L_(75) /**< \brief TCC1 signal: WO5 on PC11 mux G */ +#define MUX_PC11G_TCC1_WO5 _L_(6) +#define PINMUX_PC11G_TCC1_WO5 ((PIN_PC11G_TCC1_WO5 << 16) | MUX_PC11G_TCC1_WO5) +#define PORT_PC11G_TCC1_WO5 (_UL_(1) << 11) +#define PIN_PA21F_TCC1_WO5 _L_(21) /**< \brief TCC1 signal: WO5 on PA21 mux F */ +#define MUX_PA21F_TCC1_WO5 _L_(5) +#define PINMUX_PA21F_TCC1_WO5 ((PIN_PA21F_TCC1_WO5 << 16) | MUX_PA21F_TCC1_WO5) +#define PORT_PA21F_TCC1_WO5 (_UL_(1) << 21) +#define PIN_PB29F_TCC1_WO5 _L_(61) /**< \brief TCC1 signal: WO5 on PB29 mux F */ +#define MUX_PB29F_TCC1_WO5 _L_(5) +#define PINMUX_PB29F_TCC1_WO5 ((PIN_PB29F_TCC1_WO5 << 16) | MUX_PB29F_TCC1_WO5) +#define PORT_PB29F_TCC1_WO5 (_UL_(1) << 29) +#define PIN_PA10G_TCC1_WO6 _L_(10) /**< \brief TCC1 signal: WO6 on PA10 mux G */ +#define MUX_PA10G_TCC1_WO6 _L_(6) +#define PINMUX_PA10G_TCC1_WO6 ((PIN_PA10G_TCC1_WO6 << 16) | MUX_PA10G_TCC1_WO6) +#define PORT_PA10G_TCC1_WO6 (_UL_(1) << 10) +#define PIN_PC12G_TCC1_WO6 _L_(76) /**< \brief TCC1 signal: WO6 on PC12 mux G */ +#define MUX_PC12G_TCC1_WO6 _L_(6) +#define PINMUX_PC12G_TCC1_WO6 ((PIN_PC12G_TCC1_WO6 << 16) | MUX_PC12G_TCC1_WO6) +#define PORT_PC12G_TCC1_WO6 (_UL_(1) << 12) +#define PIN_PA22F_TCC1_WO6 _L_(22) /**< \brief TCC1 signal: WO6 on PA22 mux F */ +#define MUX_PA22F_TCC1_WO6 _L_(5) +#define PINMUX_PA22F_TCC1_WO6 ((PIN_PA22F_TCC1_WO6 << 16) | MUX_PA22F_TCC1_WO6) +#define PORT_PA22F_TCC1_WO6 (_UL_(1) << 22) +#define PIN_PA11G_TCC1_WO7 _L_(11) /**< \brief TCC1 signal: WO7 on PA11 mux G */ +#define MUX_PA11G_TCC1_WO7 _L_(6) +#define PINMUX_PA11G_TCC1_WO7 ((PIN_PA11G_TCC1_WO7 << 16) | MUX_PA11G_TCC1_WO7) +#define PORT_PA11G_TCC1_WO7 (_UL_(1) << 11) +#define PIN_PC13G_TCC1_WO7 _L_(77) /**< \brief TCC1 signal: WO7 on PC13 mux G */ +#define MUX_PC13G_TCC1_WO7 _L_(6) +#define PINMUX_PC13G_TCC1_WO7 ((PIN_PC13G_TCC1_WO7 << 16) | MUX_PC13G_TCC1_WO7) +#define PORT_PC13G_TCC1_WO7 (_UL_(1) << 13) +#define PIN_PA23F_TCC1_WO7 _L_(23) /**< \brief TCC1 signal: WO7 on PA23 mux F */ +#define MUX_PA23F_TCC1_WO7 _L_(5) +#define PINMUX_PA23F_TCC1_WO7 ((PIN_PA23F_TCC1_WO7 << 16) | MUX_PA23F_TCC1_WO7) +#define PORT_PA23F_TCC1_WO7 (_UL_(1) << 23) +/* ========== PORT definition for TC2 peripheral ========== */ +#define PIN_PA12E_TC2_WO0 _L_(12) /**< \brief TC2 signal: WO0 on PA12 mux E */ +#define MUX_PA12E_TC2_WO0 _L_(4) +#define PINMUX_PA12E_TC2_WO0 ((PIN_PA12E_TC2_WO0 << 16) | MUX_PA12E_TC2_WO0) +#define PORT_PA12E_TC2_WO0 (_UL_(1) << 12) +#define PIN_PA16E_TC2_WO0 _L_(16) /**< \brief TC2 signal: WO0 on PA16 mux E */ +#define MUX_PA16E_TC2_WO0 _L_(4) +#define PINMUX_PA16E_TC2_WO0 ((PIN_PA16E_TC2_WO0 << 16) | MUX_PA16E_TC2_WO0) +#define PORT_PA16E_TC2_WO0 (_UL_(1) << 16) +#define PIN_PA00E_TC2_WO0 _L_(0) /**< \brief TC2 signal: WO0 on PA00 mux E */ +#define MUX_PA00E_TC2_WO0 _L_(4) +#define PINMUX_PA00E_TC2_WO0 ((PIN_PA00E_TC2_WO0 << 16) | MUX_PA00E_TC2_WO0) +#define PORT_PA00E_TC2_WO0 (_UL_(1) << 0) +#define PIN_PA01E_TC2_WO1 _L_(1) /**< \brief TC2 signal: WO1 on PA01 mux E */ +#define MUX_PA01E_TC2_WO1 _L_(4) +#define PINMUX_PA01E_TC2_WO1 ((PIN_PA01E_TC2_WO1 << 16) | MUX_PA01E_TC2_WO1) +#define PORT_PA01E_TC2_WO1 (_UL_(1) << 1) +#define PIN_PA13E_TC2_WO1 _L_(13) /**< \brief TC2 signal: WO1 on PA13 mux E */ +#define MUX_PA13E_TC2_WO1 _L_(4) +#define PINMUX_PA13E_TC2_WO1 ((PIN_PA13E_TC2_WO1 << 16) | MUX_PA13E_TC2_WO1) +#define PORT_PA13E_TC2_WO1 (_UL_(1) << 13) +#define PIN_PA17E_TC2_WO1 _L_(17) /**< \brief TC2 signal: WO1 on PA17 mux E */ +#define MUX_PA17E_TC2_WO1 _L_(4) +#define PINMUX_PA17E_TC2_WO1 ((PIN_PA17E_TC2_WO1 << 16) | MUX_PA17E_TC2_WO1) +#define PORT_PA17E_TC2_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC3 peripheral ========== */ +#define PIN_PA18E_TC3_WO0 _L_(18) /**< \brief TC3 signal: WO0 on PA18 mux E */ +#define MUX_PA18E_TC3_WO0 _L_(4) +#define PINMUX_PA18E_TC3_WO0 ((PIN_PA18E_TC3_WO0 << 16) | MUX_PA18E_TC3_WO0) +#define PORT_PA18E_TC3_WO0 (_UL_(1) << 18) +#define PIN_PA14E_TC3_WO0 _L_(14) /**< \brief TC3 signal: WO0 on PA14 mux E */ +#define MUX_PA14E_TC3_WO0 _L_(4) +#define PINMUX_PA14E_TC3_WO0 ((PIN_PA14E_TC3_WO0 << 16) | MUX_PA14E_TC3_WO0) +#define PORT_PA14E_TC3_WO0 (_UL_(1) << 14) +#define PIN_PA15E_TC3_WO1 _L_(15) /**< \brief TC3 signal: WO1 on PA15 mux E */ +#define MUX_PA15E_TC3_WO1 _L_(4) +#define PINMUX_PA15E_TC3_WO1 ((PIN_PA15E_TC3_WO1 << 16) | MUX_PA15E_TC3_WO1) +#define PORT_PA15E_TC3_WO1 (_UL_(1) << 15) +#define PIN_PA19E_TC3_WO1 _L_(19) /**< \brief TC3 signal: WO1 on PA19 mux E */ +#define MUX_PA19E_TC3_WO1 _L_(4) +#define PINMUX_PA19E_TC3_WO1 ((PIN_PA19E_TC3_WO1 << 16) | MUX_PA19E_TC3_WO1) +#define PORT_PA19E_TC3_WO1 (_UL_(1) << 19) +/* ========== PORT definition for CAN0 peripheral ========== */ +#define PIN_PA23I_CAN0_RX _L_(23) /**< \brief CAN0 signal: RX on PA23 mux I */ +#define MUX_PA23I_CAN0_RX _L_(8) +#define PINMUX_PA23I_CAN0_RX ((PIN_PA23I_CAN0_RX << 16) | MUX_PA23I_CAN0_RX) +#define PORT_PA23I_CAN0_RX (_UL_(1) << 23) +#define PIN_PA25I_CAN0_RX _L_(25) /**< \brief CAN0 signal: RX on PA25 mux I */ +#define MUX_PA25I_CAN0_RX _L_(8) +#define PINMUX_PA25I_CAN0_RX ((PIN_PA25I_CAN0_RX << 16) | MUX_PA25I_CAN0_RX) +#define PORT_PA25I_CAN0_RX (_UL_(1) << 25) +#define PIN_PA22I_CAN0_TX _L_(22) /**< \brief CAN0 signal: TX on PA22 mux I */ +#define MUX_PA22I_CAN0_TX _L_(8) +#define PINMUX_PA22I_CAN0_TX ((PIN_PA22I_CAN0_TX << 16) | MUX_PA22I_CAN0_TX) +#define PORT_PA22I_CAN0_TX (_UL_(1) << 22) +#define PIN_PA24I_CAN0_TX _L_(24) /**< \brief CAN0 signal: TX on PA24 mux I */ +#define MUX_PA24I_CAN0_TX _L_(8) +#define PINMUX_PA24I_CAN0_TX ((PIN_PA24I_CAN0_TX << 16) | MUX_PA24I_CAN0_TX) +#define PORT_PA24I_CAN0_TX (_UL_(1) << 24) +/* ========== PORT definition for CAN1 peripheral ========== */ +#define PIN_PB13H_CAN1_RX _L_(45) /**< \brief CAN1 signal: RX on PB13 mux H */ +#define MUX_PB13H_CAN1_RX _L_(7) +#define PINMUX_PB13H_CAN1_RX ((PIN_PB13H_CAN1_RX << 16) | MUX_PB13H_CAN1_RX) +#define PORT_PB13H_CAN1_RX (_UL_(1) << 13) +#define PIN_PB15H_CAN1_RX _L_(47) /**< \brief CAN1 signal: RX on PB15 mux H */ +#define MUX_PB15H_CAN1_RX _L_(7) +#define PINMUX_PB15H_CAN1_RX ((PIN_PB15H_CAN1_RX << 16) | MUX_PB15H_CAN1_RX) +#define PORT_PB15H_CAN1_RX (_UL_(1) << 15) +#define PIN_PB12H_CAN1_TX _L_(44) /**< \brief CAN1 signal: TX on PB12 mux H */ +#define MUX_PB12H_CAN1_TX _L_(7) +#define PINMUX_PB12H_CAN1_TX ((PIN_PB12H_CAN1_TX << 16) | MUX_PB12H_CAN1_TX) +#define PORT_PB12H_CAN1_TX (_UL_(1) << 12) +#define PIN_PB14H_CAN1_TX _L_(46) /**< \brief CAN1 signal: TX on PB14 mux H */ +#define MUX_PB14H_CAN1_TX _L_(7) +#define PINMUX_PB14H_CAN1_TX ((PIN_PB14H_CAN1_TX << 16) | MUX_PB14H_CAN1_TX) +#define PORT_PB14H_CAN1_TX (_UL_(1) << 14) +/* ========== PORT definition for GMAC peripheral ========== */ +#define PIN_PC21L_GMAC_GCOL _L_(85) /**< \brief GMAC signal: GCOL on PC21 mux L */ +#define MUX_PC21L_GMAC_GCOL _L_(11) +#define PINMUX_PC21L_GMAC_GCOL ((PIN_PC21L_GMAC_GCOL << 16) | MUX_PC21L_GMAC_GCOL) +#define PORT_PC21L_GMAC_GCOL (_UL_(1) << 21) +#define PIN_PA16L_GMAC_GCRS _L_(16) /**< \brief GMAC signal: GCRS on PA16 mux L */ +#define MUX_PA16L_GMAC_GCRS _L_(11) +#define PINMUX_PA16L_GMAC_GCRS ((PIN_PA16L_GMAC_GCRS << 16) | MUX_PA16L_GMAC_GCRS) +#define PORT_PA16L_GMAC_GCRS (_UL_(1) << 16) +#define PIN_PA20L_GMAC_GMDC _L_(20) /**< \brief GMAC signal: GMDC on PA20 mux L */ +#define MUX_PA20L_GMAC_GMDC _L_(11) +#define PINMUX_PA20L_GMAC_GMDC ((PIN_PA20L_GMAC_GMDC << 16) | MUX_PA20L_GMAC_GMDC) +#define PORT_PA20L_GMAC_GMDC (_UL_(1) << 20) +#define PIN_PB14L_GMAC_GMDC _L_(46) /**< \brief GMAC signal: GMDC on PB14 mux L */ +#define MUX_PB14L_GMAC_GMDC _L_(11) +#define PINMUX_PB14L_GMAC_GMDC ((PIN_PB14L_GMAC_GMDC << 16) | MUX_PB14L_GMAC_GMDC) +#define PORT_PB14L_GMAC_GMDC (_UL_(1) << 14) +#define PIN_PC11L_GMAC_GMDC _L_(75) /**< \brief GMAC signal: GMDC on PC11 mux L */ +#define MUX_PC11L_GMAC_GMDC _L_(11) +#define PINMUX_PC11L_GMAC_GMDC ((PIN_PC11L_GMAC_GMDC << 16) | MUX_PC11L_GMAC_GMDC) +#define PORT_PC11L_GMAC_GMDC (_UL_(1) << 11) +#define PIN_PC22L_GMAC_GMDC _L_(86) /**< \brief GMAC signal: GMDC on PC22 mux L */ +#define MUX_PC22L_GMAC_GMDC _L_(11) +#define PINMUX_PC22L_GMAC_GMDC ((PIN_PC22L_GMAC_GMDC << 16) | MUX_PC22L_GMAC_GMDC) +#define PORT_PC22L_GMAC_GMDC (_UL_(1) << 22) +#define PIN_PA21L_GMAC_GMDIO _L_(21) /**< \brief GMAC signal: GMDIO on PA21 mux L */ +#define MUX_PA21L_GMAC_GMDIO _L_(11) +#define PINMUX_PA21L_GMAC_GMDIO ((PIN_PA21L_GMAC_GMDIO << 16) | MUX_PA21L_GMAC_GMDIO) +#define PORT_PA21L_GMAC_GMDIO (_UL_(1) << 21) +#define PIN_PB15L_GMAC_GMDIO _L_(47) /**< \brief GMAC signal: GMDIO on PB15 mux L */ +#define MUX_PB15L_GMAC_GMDIO _L_(11) +#define PINMUX_PB15L_GMAC_GMDIO ((PIN_PB15L_GMAC_GMDIO << 16) | MUX_PB15L_GMAC_GMDIO) +#define PORT_PB15L_GMAC_GMDIO (_UL_(1) << 15) +#define PIN_PC12L_GMAC_GMDIO _L_(76) /**< \brief GMAC signal: GMDIO on PC12 mux L */ +#define MUX_PC12L_GMAC_GMDIO _L_(11) +#define PINMUX_PC12L_GMAC_GMDIO ((PIN_PC12L_GMAC_GMDIO << 16) | MUX_PC12L_GMAC_GMDIO) +#define PORT_PC12L_GMAC_GMDIO (_UL_(1) << 12) +#define PIN_PC23L_GMAC_GMDIO _L_(87) /**< \brief GMAC signal: GMDIO on PC23 mux L */ +#define MUX_PC23L_GMAC_GMDIO _L_(11) +#define PINMUX_PC23L_GMAC_GMDIO ((PIN_PC23L_GMAC_GMDIO << 16) | MUX_PC23L_GMAC_GMDIO) +#define PORT_PC23L_GMAC_GMDIO (_UL_(1) << 23) +#define PIN_PA13L_GMAC_GRX0 _L_(13) /**< \brief GMAC signal: GRX0 on PA13 mux L */ +#define MUX_PA13L_GMAC_GRX0 _L_(11) +#define PINMUX_PA13L_GMAC_GRX0 ((PIN_PA13L_GMAC_GRX0 << 16) | MUX_PA13L_GMAC_GRX0) +#define PORT_PA13L_GMAC_GRX0 (_UL_(1) << 13) +#define PIN_PA12L_GMAC_GRX1 _L_(12) /**< \brief GMAC signal: GRX1 on PA12 mux L */ +#define MUX_PA12L_GMAC_GRX1 _L_(11) +#define PINMUX_PA12L_GMAC_GRX1 ((PIN_PA12L_GMAC_GRX1 << 16) | MUX_PA12L_GMAC_GRX1) +#define PORT_PA12L_GMAC_GRX1 (_UL_(1) << 12) +#define PIN_PC15L_GMAC_GRX2 _L_(79) /**< \brief GMAC signal: GRX2 on PC15 mux L */ +#define MUX_PC15L_GMAC_GRX2 _L_(11) +#define PINMUX_PC15L_GMAC_GRX2 ((PIN_PC15L_GMAC_GRX2 << 16) | MUX_PC15L_GMAC_GRX2) +#define PORT_PC15L_GMAC_GRX2 (_UL_(1) << 15) +#define PIN_PC14L_GMAC_GRX3 _L_(78) /**< \brief GMAC signal: GRX3 on PC14 mux L */ +#define MUX_PC14L_GMAC_GRX3 _L_(11) +#define PINMUX_PC14L_GMAC_GRX3 ((PIN_PC14L_GMAC_GRX3 << 16) | MUX_PC14L_GMAC_GRX3) +#define PORT_PC14L_GMAC_GRX3 (_UL_(1) << 14) +#define PIN_PC18L_GMAC_GRXCK _L_(82) /**< \brief GMAC signal: GRXCK on PC18 mux L */ +#define MUX_PC18L_GMAC_GRXCK _L_(11) +#define PINMUX_PC18L_GMAC_GRXCK ((PIN_PC18L_GMAC_GRXCK << 16) | MUX_PC18L_GMAC_GRXCK) +#define PORT_PC18L_GMAC_GRXCK (_UL_(1) << 18) +#define PIN_PC20L_GMAC_GRXDV _L_(84) /**< \brief GMAC signal: GRXDV on PC20 mux L */ +#define MUX_PC20L_GMAC_GRXDV _L_(11) +#define PINMUX_PC20L_GMAC_GRXDV ((PIN_PC20L_GMAC_GRXDV << 16) | MUX_PC20L_GMAC_GRXDV) +#define PORT_PC20L_GMAC_GRXDV (_UL_(1) << 20) +#define PIN_PA15L_GMAC_GRXER _L_(15) /**< \brief GMAC signal: GRXER on PA15 mux L */ +#define MUX_PA15L_GMAC_GRXER _L_(11) +#define PINMUX_PA15L_GMAC_GRXER ((PIN_PA15L_GMAC_GRXER << 16) | MUX_PA15L_GMAC_GRXER) +#define PORT_PA15L_GMAC_GRXER (_UL_(1) << 15) +#define PIN_PA18L_GMAC_GTX0 _L_(18) /**< \brief GMAC signal: GTX0 on PA18 mux L */ +#define MUX_PA18L_GMAC_GTX0 _L_(11) +#define PINMUX_PA18L_GMAC_GTX0 ((PIN_PA18L_GMAC_GTX0 << 16) | MUX_PA18L_GMAC_GTX0) +#define PORT_PA18L_GMAC_GTX0 (_UL_(1) << 18) +#define PIN_PA19L_GMAC_GTX1 _L_(19) /**< \brief GMAC signal: GTX1 on PA19 mux L */ +#define MUX_PA19L_GMAC_GTX1 _L_(11) +#define PINMUX_PA19L_GMAC_GTX1 ((PIN_PA19L_GMAC_GTX1 << 16) | MUX_PA19L_GMAC_GTX1) +#define PORT_PA19L_GMAC_GTX1 (_UL_(1) << 19) +#define PIN_PC16L_GMAC_GTX2 _L_(80) /**< \brief GMAC signal: GTX2 on PC16 mux L */ +#define MUX_PC16L_GMAC_GTX2 _L_(11) +#define PINMUX_PC16L_GMAC_GTX2 ((PIN_PC16L_GMAC_GTX2 << 16) | MUX_PC16L_GMAC_GTX2) +#define PORT_PC16L_GMAC_GTX2 (_UL_(1) << 16) +#define PIN_PC17L_GMAC_GTX3 _L_(81) /**< \brief GMAC signal: GTX3 on PC17 mux L */ +#define MUX_PC17L_GMAC_GTX3 _L_(11) +#define PINMUX_PC17L_GMAC_GTX3 ((PIN_PC17L_GMAC_GTX3 << 16) | MUX_PC17L_GMAC_GTX3) +#define PORT_PC17L_GMAC_GTX3 (_UL_(1) << 17) +#define PIN_PA14L_GMAC_GTXCK _L_(14) /**< \brief GMAC signal: GTXCK on PA14 mux L */ +#define MUX_PA14L_GMAC_GTXCK _L_(11) +#define PINMUX_PA14L_GMAC_GTXCK ((PIN_PA14L_GMAC_GTXCK << 16) | MUX_PA14L_GMAC_GTXCK) +#define PORT_PA14L_GMAC_GTXCK (_UL_(1) << 14) +#define PIN_PA17L_GMAC_GTXEN _L_(17) /**< \brief GMAC signal: GTXEN on PA17 mux L */ +#define MUX_PA17L_GMAC_GTXEN _L_(11) +#define PINMUX_PA17L_GMAC_GTXEN ((PIN_PA17L_GMAC_GTXEN << 16) | MUX_PA17L_GMAC_GTXEN) +#define PORT_PA17L_GMAC_GTXEN (_UL_(1) << 17) +#define PIN_PC19L_GMAC_GTXER _L_(83) /**< \brief GMAC signal: GTXER on PC19 mux L */ +#define MUX_PC19L_GMAC_GTXER _L_(11) +#define PINMUX_PC19L_GMAC_GTXER ((PIN_PC19L_GMAC_GTXER << 16) | MUX_PC19L_GMAC_GTXER) +#define PORT_PC19L_GMAC_GTXER (_UL_(1) << 19) +/* ========== PORT definition for TCC2 peripheral ========== */ +#define PIN_PA14F_TCC2_WO0 _L_(14) /**< \brief TCC2 signal: WO0 on PA14 mux F */ +#define MUX_PA14F_TCC2_WO0 _L_(5) +#define PINMUX_PA14F_TCC2_WO0 ((PIN_PA14F_TCC2_WO0 << 16) | MUX_PA14F_TCC2_WO0) +#define PORT_PA14F_TCC2_WO0 (_UL_(1) << 14) +#define PIN_PA30F_TCC2_WO0 _L_(30) /**< \brief TCC2 signal: WO0 on PA30 mux F */ +#define MUX_PA30F_TCC2_WO0 _L_(5) +#define PINMUX_PA30F_TCC2_WO0 ((PIN_PA30F_TCC2_WO0 << 16) | MUX_PA30F_TCC2_WO0) +#define PORT_PA30F_TCC2_WO0 (_UL_(1) << 30) +#define PIN_PA15F_TCC2_WO1 _L_(15) /**< \brief TCC2 signal: WO1 on PA15 mux F */ +#define MUX_PA15F_TCC2_WO1 _L_(5) +#define PINMUX_PA15F_TCC2_WO1 ((PIN_PA15F_TCC2_WO1 << 16) | MUX_PA15F_TCC2_WO1) +#define PORT_PA15F_TCC2_WO1 (_UL_(1) << 15) +#define PIN_PA31F_TCC2_WO1 _L_(31) /**< \brief TCC2 signal: WO1 on PA31 mux F */ +#define MUX_PA31F_TCC2_WO1 _L_(5) +#define PINMUX_PA31F_TCC2_WO1 ((PIN_PA31F_TCC2_WO1 << 16) | MUX_PA31F_TCC2_WO1) +#define PORT_PA31F_TCC2_WO1 (_UL_(1) << 31) +#define PIN_PA24F_TCC2_WO2 _L_(24) /**< \brief TCC2 signal: WO2 on PA24 mux F */ +#define MUX_PA24F_TCC2_WO2 _L_(5) +#define PINMUX_PA24F_TCC2_WO2 ((PIN_PA24F_TCC2_WO2 << 16) | MUX_PA24F_TCC2_WO2) +#define PORT_PA24F_TCC2_WO2 (_UL_(1) << 24) +#define PIN_PB02F_TCC2_WO2 _L_(34) /**< \brief TCC2 signal: WO2 on PB02 mux F */ +#define MUX_PB02F_TCC2_WO2 _L_(5) +#define PINMUX_PB02F_TCC2_WO2 ((PIN_PB02F_TCC2_WO2 << 16) | MUX_PB02F_TCC2_WO2) +#define PORT_PB02F_TCC2_WO2 (_UL_(1) << 2) +/* ========== PORT definition for TCC3 peripheral ========== */ +#define PIN_PB12F_TCC3_WO0 _L_(44) /**< \brief TCC3 signal: WO0 on PB12 mux F */ +#define MUX_PB12F_TCC3_WO0 _L_(5) +#define PINMUX_PB12F_TCC3_WO0 ((PIN_PB12F_TCC3_WO0 << 16) | MUX_PB12F_TCC3_WO0) +#define PORT_PB12F_TCC3_WO0 (_UL_(1) << 12) +#define PIN_PB16F_TCC3_WO0 _L_(48) /**< \brief TCC3 signal: WO0 on PB16 mux F */ +#define MUX_PB16F_TCC3_WO0 _L_(5) +#define PINMUX_PB16F_TCC3_WO0 ((PIN_PB16F_TCC3_WO0 << 16) | MUX_PB16F_TCC3_WO0) +#define PORT_PB16F_TCC3_WO0 (_UL_(1) << 16) +#define PIN_PB13F_TCC3_WO1 _L_(45) /**< \brief TCC3 signal: WO1 on PB13 mux F */ +#define MUX_PB13F_TCC3_WO1 _L_(5) +#define PINMUX_PB13F_TCC3_WO1 ((PIN_PB13F_TCC3_WO1 << 16) | MUX_PB13F_TCC3_WO1) +#define PORT_PB13F_TCC3_WO1 (_UL_(1) << 13) +#define PIN_PB17F_TCC3_WO1 _L_(49) /**< \brief TCC3 signal: WO1 on PB17 mux F */ +#define MUX_PB17F_TCC3_WO1 _L_(5) +#define PINMUX_PB17F_TCC3_WO1 ((PIN_PB17F_TCC3_WO1 << 16) | MUX_PB17F_TCC3_WO1) +#define PORT_PB17F_TCC3_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC4 peripheral ========== */ +#define PIN_PA22E_TC4_WO0 _L_(22) /**< \brief TC4 signal: WO0 on PA22 mux E */ +#define MUX_PA22E_TC4_WO0 _L_(4) +#define PINMUX_PA22E_TC4_WO0 ((PIN_PA22E_TC4_WO0 << 16) | MUX_PA22E_TC4_WO0) +#define PORT_PA22E_TC4_WO0 (_UL_(1) << 22) +#define PIN_PB08E_TC4_WO0 _L_(40) /**< \brief TC4 signal: WO0 on PB08 mux E */ +#define MUX_PB08E_TC4_WO0 _L_(4) +#define PINMUX_PB08E_TC4_WO0 ((PIN_PB08E_TC4_WO0 << 16) | MUX_PB08E_TC4_WO0) +#define PORT_PB08E_TC4_WO0 (_UL_(1) << 8) +#define PIN_PB12E_TC4_WO0 _L_(44) /**< \brief TC4 signal: WO0 on PB12 mux E */ +#define MUX_PB12E_TC4_WO0 _L_(4) +#define PINMUX_PB12E_TC4_WO0 ((PIN_PB12E_TC4_WO0 << 16) | MUX_PB12E_TC4_WO0) +#define PORT_PB12E_TC4_WO0 (_UL_(1) << 12) +#define PIN_PA23E_TC4_WO1 _L_(23) /**< \brief TC4 signal: WO1 on PA23 mux E */ +#define MUX_PA23E_TC4_WO1 _L_(4) +#define PINMUX_PA23E_TC4_WO1 ((PIN_PA23E_TC4_WO1 << 16) | MUX_PA23E_TC4_WO1) +#define PORT_PA23E_TC4_WO1 (_UL_(1) << 23) +#define PIN_PB09E_TC4_WO1 _L_(41) /**< \brief TC4 signal: WO1 on PB09 mux E */ +#define MUX_PB09E_TC4_WO1 _L_(4) +#define PINMUX_PB09E_TC4_WO1 ((PIN_PB09E_TC4_WO1 << 16) | MUX_PB09E_TC4_WO1) +#define PORT_PB09E_TC4_WO1 (_UL_(1) << 9) +#define PIN_PB13E_TC4_WO1 _L_(45) /**< \brief TC4 signal: WO1 on PB13 mux E */ +#define MUX_PB13E_TC4_WO1 _L_(4) +#define PINMUX_PB13E_TC4_WO1 ((PIN_PB13E_TC4_WO1 << 16) | MUX_PB13E_TC4_WO1) +#define PORT_PB13E_TC4_WO1 (_UL_(1) << 13) +/* ========== PORT definition for TC5 peripheral ========== */ +#define PIN_PA24E_TC5_WO0 _L_(24) /**< \brief TC5 signal: WO0 on PA24 mux E */ +#define MUX_PA24E_TC5_WO0 _L_(4) +#define PINMUX_PA24E_TC5_WO0 ((PIN_PA24E_TC5_WO0 << 16) | MUX_PA24E_TC5_WO0) +#define PORT_PA24E_TC5_WO0 (_UL_(1) << 24) +#define PIN_PB10E_TC5_WO0 _L_(42) /**< \brief TC5 signal: WO0 on PB10 mux E */ +#define MUX_PB10E_TC5_WO0 _L_(4) +#define PINMUX_PB10E_TC5_WO0 ((PIN_PB10E_TC5_WO0 << 16) | MUX_PB10E_TC5_WO0) +#define PORT_PB10E_TC5_WO0 (_UL_(1) << 10) +#define PIN_PB14E_TC5_WO0 _L_(46) /**< \brief TC5 signal: WO0 on PB14 mux E */ +#define MUX_PB14E_TC5_WO0 _L_(4) +#define PINMUX_PB14E_TC5_WO0 ((PIN_PB14E_TC5_WO0 << 16) | MUX_PB14E_TC5_WO0) +#define PORT_PB14E_TC5_WO0 (_UL_(1) << 14) +#define PIN_PA25E_TC5_WO1 _L_(25) /**< \brief TC5 signal: WO1 on PA25 mux E */ +#define MUX_PA25E_TC5_WO1 _L_(4) +#define PINMUX_PA25E_TC5_WO1 ((PIN_PA25E_TC5_WO1 << 16) | MUX_PA25E_TC5_WO1) +#define PORT_PA25E_TC5_WO1 (_UL_(1) << 25) +#define PIN_PB11E_TC5_WO1 _L_(43) /**< \brief TC5 signal: WO1 on PB11 mux E */ +#define MUX_PB11E_TC5_WO1 _L_(4) +#define PINMUX_PB11E_TC5_WO1 ((PIN_PB11E_TC5_WO1 << 16) | MUX_PB11E_TC5_WO1) +#define PORT_PB11E_TC5_WO1 (_UL_(1) << 11) +#define PIN_PB15E_TC5_WO1 _L_(47) /**< \brief TC5 signal: WO1 on PB15 mux E */ +#define MUX_PB15E_TC5_WO1 _L_(4) +#define PINMUX_PB15E_TC5_WO1 ((PIN_PB15E_TC5_WO1 << 16) | MUX_PB15E_TC5_WO1) +#define PORT_PB15E_TC5_WO1 (_UL_(1) << 15) +/* ========== PORT definition for PDEC peripheral ========== */ +#define PIN_PB18G_PDEC_QDI0 _L_(50) /**< \brief PDEC signal: QDI0 on PB18 mux G */ +#define MUX_PB18G_PDEC_QDI0 _L_(6) +#define PINMUX_PB18G_PDEC_QDI0 ((PIN_PB18G_PDEC_QDI0 << 16) | MUX_PB18G_PDEC_QDI0) +#define PORT_PB18G_PDEC_QDI0 (_UL_(1) << 18) +#define PIN_PB23G_PDEC_QDI0 _L_(55) /**< \brief PDEC signal: QDI0 on PB23 mux G */ +#define MUX_PB23G_PDEC_QDI0 _L_(6) +#define PINMUX_PB23G_PDEC_QDI0 ((PIN_PB23G_PDEC_QDI0 << 16) | MUX_PB23G_PDEC_QDI0) +#define PORT_PB23G_PDEC_QDI0 (_UL_(1) << 23) +#define PIN_PC16G_PDEC_QDI0 _L_(80) /**< \brief PDEC signal: QDI0 on PC16 mux G */ +#define MUX_PC16G_PDEC_QDI0 _L_(6) +#define PINMUX_PC16G_PDEC_QDI0 ((PIN_PC16G_PDEC_QDI0 << 16) | MUX_PC16G_PDEC_QDI0) +#define PORT_PC16G_PDEC_QDI0 (_UL_(1) << 16) +#define PIN_PA24G_PDEC_QDI0 _L_(24) /**< \brief PDEC signal: QDI0 on PA24 mux G */ +#define MUX_PA24G_PDEC_QDI0 _L_(6) +#define PINMUX_PA24G_PDEC_QDI0 ((PIN_PA24G_PDEC_QDI0 << 16) | MUX_PA24G_PDEC_QDI0) +#define PORT_PA24G_PDEC_QDI0 (_UL_(1) << 24) +#define PIN_PB19G_PDEC_QDI1 _L_(51) /**< \brief PDEC signal: QDI1 on PB19 mux G */ +#define MUX_PB19G_PDEC_QDI1 _L_(6) +#define PINMUX_PB19G_PDEC_QDI1 ((PIN_PB19G_PDEC_QDI1 << 16) | MUX_PB19G_PDEC_QDI1) +#define PORT_PB19G_PDEC_QDI1 (_UL_(1) << 19) +#define PIN_PB24G_PDEC_QDI1 _L_(56) /**< \brief PDEC signal: QDI1 on PB24 mux G */ +#define MUX_PB24G_PDEC_QDI1 _L_(6) +#define PINMUX_PB24G_PDEC_QDI1 ((PIN_PB24G_PDEC_QDI1 << 16) | MUX_PB24G_PDEC_QDI1) +#define PORT_PB24G_PDEC_QDI1 (_UL_(1) << 24) +#define PIN_PC17G_PDEC_QDI1 _L_(81) /**< \brief PDEC signal: QDI1 on PC17 mux G */ +#define MUX_PC17G_PDEC_QDI1 _L_(6) +#define PINMUX_PC17G_PDEC_QDI1 ((PIN_PC17G_PDEC_QDI1 << 16) | MUX_PC17G_PDEC_QDI1) +#define PORT_PC17G_PDEC_QDI1 (_UL_(1) << 17) +#define PIN_PA25G_PDEC_QDI1 _L_(25) /**< \brief PDEC signal: QDI1 on PA25 mux G */ +#define MUX_PA25G_PDEC_QDI1 _L_(6) +#define PINMUX_PA25G_PDEC_QDI1 ((PIN_PA25G_PDEC_QDI1 << 16) | MUX_PA25G_PDEC_QDI1) +#define PORT_PA25G_PDEC_QDI1 (_UL_(1) << 25) +#define PIN_PB20G_PDEC_QDI2 _L_(52) /**< \brief PDEC signal: QDI2 on PB20 mux G */ +#define MUX_PB20G_PDEC_QDI2 _L_(6) +#define PINMUX_PB20G_PDEC_QDI2 ((PIN_PB20G_PDEC_QDI2 << 16) | MUX_PB20G_PDEC_QDI2) +#define PORT_PB20G_PDEC_QDI2 (_UL_(1) << 20) +#define PIN_PB25G_PDEC_QDI2 _L_(57) /**< \brief PDEC signal: QDI2 on PB25 mux G */ +#define MUX_PB25G_PDEC_QDI2 _L_(6) +#define PINMUX_PB25G_PDEC_QDI2 ((PIN_PB25G_PDEC_QDI2 << 16) | MUX_PB25G_PDEC_QDI2) +#define PORT_PB25G_PDEC_QDI2 (_UL_(1) << 25) +#define PIN_PC18G_PDEC_QDI2 _L_(82) /**< \brief PDEC signal: QDI2 on PC18 mux G */ +#define MUX_PC18G_PDEC_QDI2 _L_(6) +#define PINMUX_PC18G_PDEC_QDI2 ((PIN_PC18G_PDEC_QDI2 << 16) | MUX_PC18G_PDEC_QDI2) +#define PORT_PC18G_PDEC_QDI2 (_UL_(1) << 18) +#define PIN_PB22G_PDEC_QDI2 _L_(54) /**< \brief PDEC signal: QDI2 on PB22 mux G */ +#define MUX_PB22G_PDEC_QDI2 _L_(6) +#define PINMUX_PB22G_PDEC_QDI2 ((PIN_PB22G_PDEC_QDI2 << 16) | MUX_PB22G_PDEC_QDI2) +#define PORT_PB22G_PDEC_QDI2 (_UL_(1) << 22) +/* ========== PORT definition for AC peripheral ========== */ +#define PIN_PA04B_AC_AIN0 _L_(4) /**< \brief AC signal: AIN0 on PA04 mux B */ +#define MUX_PA04B_AC_AIN0 _L_(1) +#define PINMUX_PA04B_AC_AIN0 ((PIN_PA04B_AC_AIN0 << 16) | MUX_PA04B_AC_AIN0) +#define PORT_PA04B_AC_AIN0 (_UL_(1) << 4) +#define PIN_PA05B_AC_AIN1 _L_(5) /**< \brief AC signal: AIN1 on PA05 mux B */ +#define MUX_PA05B_AC_AIN1 _L_(1) +#define PINMUX_PA05B_AC_AIN1 ((PIN_PA05B_AC_AIN1 << 16) | MUX_PA05B_AC_AIN1) +#define PORT_PA05B_AC_AIN1 (_UL_(1) << 5) +#define PIN_PA06B_AC_AIN2 _L_(6) /**< \brief AC signal: AIN2 on PA06 mux B */ +#define MUX_PA06B_AC_AIN2 _L_(1) +#define PINMUX_PA06B_AC_AIN2 ((PIN_PA06B_AC_AIN2 << 16) | MUX_PA06B_AC_AIN2) +#define PORT_PA06B_AC_AIN2 (_UL_(1) << 6) +#define PIN_PA07B_AC_AIN3 _L_(7) /**< \brief AC signal: AIN3 on PA07 mux B */ +#define MUX_PA07B_AC_AIN3 _L_(1) +#define PINMUX_PA07B_AC_AIN3 ((PIN_PA07B_AC_AIN3 << 16) | MUX_PA07B_AC_AIN3) +#define PORT_PA07B_AC_AIN3 (_UL_(1) << 7) +#define PIN_PA12M_AC_CMP0 _L_(12) /**< \brief AC signal: CMP0 on PA12 mux M */ +#define MUX_PA12M_AC_CMP0 _L_(12) +#define PINMUX_PA12M_AC_CMP0 ((PIN_PA12M_AC_CMP0 << 16) | MUX_PA12M_AC_CMP0) +#define PORT_PA12M_AC_CMP0 (_UL_(1) << 12) +#define PIN_PA18M_AC_CMP0 _L_(18) /**< \brief AC signal: CMP0 on PA18 mux M */ +#define MUX_PA18M_AC_CMP0 _L_(12) +#define PINMUX_PA18M_AC_CMP0 ((PIN_PA18M_AC_CMP0 << 16) | MUX_PA18M_AC_CMP0) +#define PORT_PA18M_AC_CMP0 (_UL_(1) << 18) +#define PIN_PB24M_AC_CMP0 _L_(56) /**< \brief AC signal: CMP0 on PB24 mux M */ +#define MUX_PB24M_AC_CMP0 _L_(12) +#define PINMUX_PB24M_AC_CMP0 ((PIN_PB24M_AC_CMP0 << 16) | MUX_PB24M_AC_CMP0) +#define PORT_PB24M_AC_CMP0 (_UL_(1) << 24) +#define PIN_PA13M_AC_CMP1 _L_(13) /**< \brief AC signal: CMP1 on PA13 mux M */ +#define MUX_PA13M_AC_CMP1 _L_(12) +#define PINMUX_PA13M_AC_CMP1 ((PIN_PA13M_AC_CMP1 << 16) | MUX_PA13M_AC_CMP1) +#define PORT_PA13M_AC_CMP1 (_UL_(1) << 13) +#define PIN_PA19M_AC_CMP1 _L_(19) /**< \brief AC signal: CMP1 on PA19 mux M */ +#define MUX_PA19M_AC_CMP1 _L_(12) +#define PINMUX_PA19M_AC_CMP1 ((PIN_PA19M_AC_CMP1 << 16) | MUX_PA19M_AC_CMP1) +#define PORT_PA19M_AC_CMP1 (_UL_(1) << 19) +#define PIN_PB25M_AC_CMP1 _L_(57) /**< \brief AC signal: CMP1 on PB25 mux M */ +#define MUX_PB25M_AC_CMP1 _L_(12) +#define PINMUX_PB25M_AC_CMP1 ((PIN_PB25M_AC_CMP1 << 16) | MUX_PB25M_AC_CMP1) +#define PORT_PB25M_AC_CMP1 (_UL_(1) << 25) +/* ========== PORT definition for QSPI peripheral ========== */ +#define PIN_PB11H_QSPI_CS _L_(43) /**< \brief QSPI signal: CS on PB11 mux H */ +#define MUX_PB11H_QSPI_CS _L_(7) +#define PINMUX_PB11H_QSPI_CS ((PIN_PB11H_QSPI_CS << 16) | MUX_PB11H_QSPI_CS) +#define PORT_PB11H_QSPI_CS (_UL_(1) << 11) +#define PIN_PA08H_QSPI_DATA0 _L_(8) /**< \brief QSPI signal: DATA0 on PA08 mux H */ +#define MUX_PA08H_QSPI_DATA0 _L_(7) +#define PINMUX_PA08H_QSPI_DATA0 ((PIN_PA08H_QSPI_DATA0 << 16) | MUX_PA08H_QSPI_DATA0) +#define PORT_PA08H_QSPI_DATA0 (_UL_(1) << 8) +#define PIN_PA09H_QSPI_DATA1 _L_(9) /**< \brief QSPI signal: DATA1 on PA09 mux H */ +#define MUX_PA09H_QSPI_DATA1 _L_(7) +#define PINMUX_PA09H_QSPI_DATA1 ((PIN_PA09H_QSPI_DATA1 << 16) | MUX_PA09H_QSPI_DATA1) +#define PORT_PA09H_QSPI_DATA1 (_UL_(1) << 9) +#define PIN_PA10H_QSPI_DATA2 _L_(10) /**< \brief QSPI signal: DATA2 on PA10 mux H */ +#define MUX_PA10H_QSPI_DATA2 _L_(7) +#define PINMUX_PA10H_QSPI_DATA2 ((PIN_PA10H_QSPI_DATA2 << 16) | MUX_PA10H_QSPI_DATA2) +#define PORT_PA10H_QSPI_DATA2 (_UL_(1) << 10) +#define PIN_PA11H_QSPI_DATA3 _L_(11) /**< \brief QSPI signal: DATA3 on PA11 mux H */ +#define MUX_PA11H_QSPI_DATA3 _L_(7) +#define PINMUX_PA11H_QSPI_DATA3 ((PIN_PA11H_QSPI_DATA3 << 16) | MUX_PA11H_QSPI_DATA3) +#define PORT_PA11H_QSPI_DATA3 (_UL_(1) << 11) +#define PIN_PB10H_QSPI_SCK _L_(42) /**< \brief QSPI signal: SCK on PB10 mux H */ +#define MUX_PB10H_QSPI_SCK _L_(7) +#define PINMUX_PB10H_QSPI_SCK ((PIN_PB10H_QSPI_SCK << 16) | MUX_PB10H_QSPI_SCK) +#define PORT_PB10H_QSPI_SCK (_UL_(1) << 10) +/* ========== PORT definition for CCL peripheral ========== */ +#define PIN_PA04N_CCL_IN0 _L_(4) /**< \brief CCL signal: IN0 on PA04 mux N */ +#define MUX_PA04N_CCL_IN0 _L_(13) +#define PINMUX_PA04N_CCL_IN0 ((PIN_PA04N_CCL_IN0 << 16) | MUX_PA04N_CCL_IN0) +#define PORT_PA04N_CCL_IN0 (_UL_(1) << 4) +#define PIN_PA16N_CCL_IN0 _L_(16) /**< \brief CCL signal: IN0 on PA16 mux N */ +#define MUX_PA16N_CCL_IN0 _L_(13) +#define PINMUX_PA16N_CCL_IN0 ((PIN_PA16N_CCL_IN0 << 16) | MUX_PA16N_CCL_IN0) +#define PORT_PA16N_CCL_IN0 (_UL_(1) << 16) +#define PIN_PB22N_CCL_IN0 _L_(54) /**< \brief CCL signal: IN0 on PB22 mux N */ +#define MUX_PB22N_CCL_IN0 _L_(13) +#define PINMUX_PB22N_CCL_IN0 ((PIN_PB22N_CCL_IN0 << 16) | MUX_PB22N_CCL_IN0) +#define PORT_PB22N_CCL_IN0 (_UL_(1) << 22) +#define PIN_PA05N_CCL_IN1 _L_(5) /**< \brief CCL signal: IN1 on PA05 mux N */ +#define MUX_PA05N_CCL_IN1 _L_(13) +#define PINMUX_PA05N_CCL_IN1 ((PIN_PA05N_CCL_IN1 << 16) | MUX_PA05N_CCL_IN1) +#define PORT_PA05N_CCL_IN1 (_UL_(1) << 5) +#define PIN_PA17N_CCL_IN1 _L_(17) /**< \brief CCL signal: IN1 on PA17 mux N */ +#define MUX_PA17N_CCL_IN1 _L_(13) +#define PINMUX_PA17N_CCL_IN1 ((PIN_PA17N_CCL_IN1 << 16) | MUX_PA17N_CCL_IN1) +#define PORT_PA17N_CCL_IN1 (_UL_(1) << 17) +#define PIN_PB00N_CCL_IN1 _L_(32) /**< \brief CCL signal: IN1 on PB00 mux N */ +#define MUX_PB00N_CCL_IN1 _L_(13) +#define PINMUX_PB00N_CCL_IN1 ((PIN_PB00N_CCL_IN1 << 16) | MUX_PB00N_CCL_IN1) +#define PORT_PB00N_CCL_IN1 (_UL_(1) << 0) +#define PIN_PA06N_CCL_IN2 _L_(6) /**< \brief CCL signal: IN2 on PA06 mux N */ +#define MUX_PA06N_CCL_IN2 _L_(13) +#define PINMUX_PA06N_CCL_IN2 ((PIN_PA06N_CCL_IN2 << 16) | MUX_PA06N_CCL_IN2) +#define PORT_PA06N_CCL_IN2 (_UL_(1) << 6) +#define PIN_PA18N_CCL_IN2 _L_(18) /**< \brief CCL signal: IN2 on PA18 mux N */ +#define MUX_PA18N_CCL_IN2 _L_(13) +#define PINMUX_PA18N_CCL_IN2 ((PIN_PA18N_CCL_IN2 << 16) | MUX_PA18N_CCL_IN2) +#define PORT_PA18N_CCL_IN2 (_UL_(1) << 18) +#define PIN_PB01N_CCL_IN2 _L_(33) /**< \brief CCL signal: IN2 on PB01 mux N */ +#define MUX_PB01N_CCL_IN2 _L_(13) +#define PINMUX_PB01N_CCL_IN2 ((PIN_PB01N_CCL_IN2 << 16) | MUX_PB01N_CCL_IN2) +#define PORT_PB01N_CCL_IN2 (_UL_(1) << 1) +#define PIN_PA08N_CCL_IN3 _L_(8) /**< \brief CCL signal: IN3 on PA08 mux N */ +#define MUX_PA08N_CCL_IN3 _L_(13) +#define PINMUX_PA08N_CCL_IN3 ((PIN_PA08N_CCL_IN3 << 16) | MUX_PA08N_CCL_IN3) +#define PORT_PA08N_CCL_IN3 (_UL_(1) << 8) +#define PIN_PA30N_CCL_IN3 _L_(30) /**< \brief CCL signal: IN3 on PA30 mux N */ +#define MUX_PA30N_CCL_IN3 _L_(13) +#define PINMUX_PA30N_CCL_IN3 ((PIN_PA30N_CCL_IN3 << 16) | MUX_PA30N_CCL_IN3) +#define PORT_PA30N_CCL_IN3 (_UL_(1) << 30) +#define PIN_PA09N_CCL_IN4 _L_(9) /**< \brief CCL signal: IN4 on PA09 mux N */ +#define MUX_PA09N_CCL_IN4 _L_(13) +#define PINMUX_PA09N_CCL_IN4 ((PIN_PA09N_CCL_IN4 << 16) | MUX_PA09N_CCL_IN4) +#define PORT_PA09N_CCL_IN4 (_UL_(1) << 9) +#define PIN_PC27N_CCL_IN4 _L_(91) /**< \brief CCL signal: IN4 on PC27 mux N */ +#define MUX_PC27N_CCL_IN4 _L_(13) +#define PINMUX_PC27N_CCL_IN4 ((PIN_PC27N_CCL_IN4 << 16) | MUX_PC27N_CCL_IN4) +#define PORT_PC27N_CCL_IN4 (_UL_(1) << 27) +#define PIN_PA10N_CCL_IN5 _L_(10) /**< \brief CCL signal: IN5 on PA10 mux N */ +#define MUX_PA10N_CCL_IN5 _L_(13) +#define PINMUX_PA10N_CCL_IN5 ((PIN_PA10N_CCL_IN5 << 16) | MUX_PA10N_CCL_IN5) +#define PORT_PA10N_CCL_IN5 (_UL_(1) << 10) +#define PIN_PC28N_CCL_IN5 _L_(92) /**< \brief CCL signal: IN5 on PC28 mux N */ +#define MUX_PC28N_CCL_IN5 _L_(13) +#define PINMUX_PC28N_CCL_IN5 ((PIN_PC28N_CCL_IN5 << 16) | MUX_PC28N_CCL_IN5) +#define PORT_PC28N_CCL_IN5 (_UL_(1) << 28) +#define PIN_PA22N_CCL_IN6 _L_(22) /**< \brief CCL signal: IN6 on PA22 mux N */ +#define MUX_PA22N_CCL_IN6 _L_(13) +#define PINMUX_PA22N_CCL_IN6 ((PIN_PA22N_CCL_IN6 << 16) | MUX_PA22N_CCL_IN6) +#define PORT_PA22N_CCL_IN6 (_UL_(1) << 22) +#define PIN_PB06N_CCL_IN6 _L_(38) /**< \brief CCL signal: IN6 on PB06 mux N */ +#define MUX_PB06N_CCL_IN6 _L_(13) +#define PINMUX_PB06N_CCL_IN6 ((PIN_PB06N_CCL_IN6 << 16) | MUX_PB06N_CCL_IN6) +#define PORT_PB06N_CCL_IN6 (_UL_(1) << 6) +#define PIN_PA23N_CCL_IN7 _L_(23) /**< \brief CCL signal: IN7 on PA23 mux N */ +#define MUX_PA23N_CCL_IN7 _L_(13) +#define PINMUX_PA23N_CCL_IN7 ((PIN_PA23N_CCL_IN7 << 16) | MUX_PA23N_CCL_IN7) +#define PORT_PA23N_CCL_IN7 (_UL_(1) << 23) +#define PIN_PB07N_CCL_IN7 _L_(39) /**< \brief CCL signal: IN7 on PB07 mux N */ +#define MUX_PB07N_CCL_IN7 _L_(13) +#define PINMUX_PB07N_CCL_IN7 ((PIN_PB07N_CCL_IN7 << 16) | MUX_PB07N_CCL_IN7) +#define PORT_PB07N_CCL_IN7 (_UL_(1) << 7) +#define PIN_PA24N_CCL_IN8 _L_(24) /**< \brief CCL signal: IN8 on PA24 mux N */ +#define MUX_PA24N_CCL_IN8 _L_(13) +#define PINMUX_PA24N_CCL_IN8 ((PIN_PA24N_CCL_IN8 << 16) | MUX_PA24N_CCL_IN8) +#define PORT_PA24N_CCL_IN8 (_UL_(1) << 24) +#define PIN_PB08N_CCL_IN8 _L_(40) /**< \brief CCL signal: IN8 on PB08 mux N */ +#define MUX_PB08N_CCL_IN8 _L_(13) +#define PINMUX_PB08N_CCL_IN8 ((PIN_PB08N_CCL_IN8 << 16) | MUX_PB08N_CCL_IN8) +#define PORT_PB08N_CCL_IN8 (_UL_(1) << 8) +#define PIN_PB14N_CCL_IN9 _L_(46) /**< \brief CCL signal: IN9 on PB14 mux N */ +#define MUX_PB14N_CCL_IN9 _L_(13) +#define PINMUX_PB14N_CCL_IN9 ((PIN_PB14N_CCL_IN9 << 16) | MUX_PB14N_CCL_IN9) +#define PORT_PB14N_CCL_IN9 (_UL_(1) << 14) +#define PIN_PC20N_CCL_IN9 _L_(84) /**< \brief CCL signal: IN9 on PC20 mux N */ +#define MUX_PC20N_CCL_IN9 _L_(13) +#define PINMUX_PC20N_CCL_IN9 ((PIN_PC20N_CCL_IN9 << 16) | MUX_PC20N_CCL_IN9) +#define PORT_PC20N_CCL_IN9 (_UL_(1) << 20) +#define PIN_PB15N_CCL_IN10 _L_(47) /**< \brief CCL signal: IN10 on PB15 mux N */ +#define MUX_PB15N_CCL_IN10 _L_(13) +#define PINMUX_PB15N_CCL_IN10 ((PIN_PB15N_CCL_IN10 << 16) | MUX_PB15N_CCL_IN10) +#define PORT_PB15N_CCL_IN10 (_UL_(1) << 15) +#define PIN_PC21N_CCL_IN10 _L_(85) /**< \brief CCL signal: IN10 on PC21 mux N */ +#define MUX_PC21N_CCL_IN10 _L_(13) +#define PINMUX_PC21N_CCL_IN10 ((PIN_PC21N_CCL_IN10 << 16) | MUX_PC21N_CCL_IN10) +#define PORT_PC21N_CCL_IN10 (_UL_(1) << 21) +#define PIN_PB10N_CCL_IN11 _L_(42) /**< \brief CCL signal: IN11 on PB10 mux N */ +#define MUX_PB10N_CCL_IN11 _L_(13) +#define PINMUX_PB10N_CCL_IN11 ((PIN_PB10N_CCL_IN11 << 16) | MUX_PB10N_CCL_IN11) +#define PORT_PB10N_CCL_IN11 (_UL_(1) << 10) +#define PIN_PB16N_CCL_IN11 _L_(48) /**< \brief CCL signal: IN11 on PB16 mux N */ +#define MUX_PB16N_CCL_IN11 _L_(13) +#define PINMUX_PB16N_CCL_IN11 ((PIN_PB16N_CCL_IN11 << 16) | MUX_PB16N_CCL_IN11) +#define PORT_PB16N_CCL_IN11 (_UL_(1) << 16) +#define PIN_PA07N_CCL_OUT0 _L_(7) /**< \brief CCL signal: OUT0 on PA07 mux N */ +#define MUX_PA07N_CCL_OUT0 _L_(13) +#define PINMUX_PA07N_CCL_OUT0 ((PIN_PA07N_CCL_OUT0 << 16) | MUX_PA07N_CCL_OUT0) +#define PORT_PA07N_CCL_OUT0 (_UL_(1) << 7) +#define PIN_PA19N_CCL_OUT0 _L_(19) /**< \brief CCL signal: OUT0 on PA19 mux N */ +#define MUX_PA19N_CCL_OUT0 _L_(13) +#define PINMUX_PA19N_CCL_OUT0 ((PIN_PA19N_CCL_OUT0 << 16) | MUX_PA19N_CCL_OUT0) +#define PORT_PA19N_CCL_OUT0 (_UL_(1) << 19) +#define PIN_PB02N_CCL_OUT0 _L_(34) /**< \brief CCL signal: OUT0 on PB02 mux N */ +#define MUX_PB02N_CCL_OUT0 _L_(13) +#define PINMUX_PB02N_CCL_OUT0 ((PIN_PB02N_CCL_OUT0 << 16) | MUX_PB02N_CCL_OUT0) +#define PORT_PB02N_CCL_OUT0 (_UL_(1) << 2) +#define PIN_PB23N_CCL_OUT0 _L_(55) /**< \brief CCL signal: OUT0 on PB23 mux N */ +#define MUX_PB23N_CCL_OUT0 _L_(13) +#define PINMUX_PB23N_CCL_OUT0 ((PIN_PB23N_CCL_OUT0 << 16) | MUX_PB23N_CCL_OUT0) +#define PORT_PB23N_CCL_OUT0 (_UL_(1) << 23) +#define PIN_PA11N_CCL_OUT1 _L_(11) /**< \brief CCL signal: OUT1 on PA11 mux N */ +#define MUX_PA11N_CCL_OUT1 _L_(13) +#define PINMUX_PA11N_CCL_OUT1 ((PIN_PA11N_CCL_OUT1 << 16) | MUX_PA11N_CCL_OUT1) +#define PORT_PA11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA31N_CCL_OUT1 _L_(31) /**< \brief CCL signal: OUT1 on PA31 mux N */ +#define MUX_PA31N_CCL_OUT1 _L_(13) +#define PINMUX_PA31N_CCL_OUT1 ((PIN_PA31N_CCL_OUT1 << 16) | MUX_PA31N_CCL_OUT1) +#define PORT_PA31N_CCL_OUT1 (_UL_(1) << 31) +#define PIN_PB11N_CCL_OUT1 _L_(43) /**< \brief CCL signal: OUT1 on PB11 mux N */ +#define MUX_PB11N_CCL_OUT1 _L_(13) +#define PINMUX_PB11N_CCL_OUT1 ((PIN_PB11N_CCL_OUT1 << 16) | MUX_PB11N_CCL_OUT1) +#define PORT_PB11N_CCL_OUT1 (_UL_(1) << 11) +#define PIN_PA25N_CCL_OUT2 _L_(25) /**< \brief CCL signal: OUT2 on PA25 mux N */ +#define MUX_PA25N_CCL_OUT2 _L_(13) +#define PINMUX_PA25N_CCL_OUT2 ((PIN_PA25N_CCL_OUT2 << 16) | MUX_PA25N_CCL_OUT2) +#define PORT_PA25N_CCL_OUT2 (_UL_(1) << 25) +#define PIN_PB09N_CCL_OUT2 _L_(41) /**< \brief CCL signal: OUT2 on PB09 mux N */ +#define MUX_PB09N_CCL_OUT2 _L_(13) +#define PINMUX_PB09N_CCL_OUT2 ((PIN_PB09N_CCL_OUT2 << 16) | MUX_PB09N_CCL_OUT2) +#define PORT_PB09N_CCL_OUT2 (_UL_(1) << 9) +#define PIN_PB17N_CCL_OUT3 _L_(49) /**< \brief CCL signal: OUT3 on PB17 mux N */ +#define MUX_PB17N_CCL_OUT3 _L_(13) +#define PINMUX_PB17N_CCL_OUT3 ((PIN_PB17N_CCL_OUT3 << 16) | MUX_PB17N_CCL_OUT3) +#define PORT_PB17N_CCL_OUT3 (_UL_(1) << 17) +/* ========== PORT definition for SERCOM4 peripheral ========== */ +#define PIN_PA13D_SERCOM4_PAD0 _L_(13) /**< \brief SERCOM4 signal: PAD0 on PA13 mux D */ +#define MUX_PA13D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PA13D_SERCOM4_PAD0 ((PIN_PA13D_SERCOM4_PAD0 << 16) | MUX_PA13D_SERCOM4_PAD0) +#define PORT_PA13D_SERCOM4_PAD0 (_UL_(1) << 13) +#define PIN_PB08D_SERCOM4_PAD0 _L_(40) /**< \brief SERCOM4 signal: PAD0 on PB08 mux D */ +#define MUX_PB08D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB08D_SERCOM4_PAD0 ((PIN_PB08D_SERCOM4_PAD0 << 16) | MUX_PB08D_SERCOM4_PAD0) +#define PORT_PB08D_SERCOM4_PAD0 (_UL_(1) << 8) +#define PIN_PB27D_SERCOM4_PAD0 _L_(59) /**< \brief SERCOM4 signal: PAD0 on PB27 mux D */ +#define MUX_PB27D_SERCOM4_PAD0 _L_(3) +#define PINMUX_PB27D_SERCOM4_PAD0 ((PIN_PB27D_SERCOM4_PAD0 << 16) | MUX_PB27D_SERCOM4_PAD0) +#define PORT_PB27D_SERCOM4_PAD0 (_UL_(1) << 27) +#define PIN_PB12C_SERCOM4_PAD0 _L_(44) /**< \brief SERCOM4 signal: PAD0 on PB12 mux C */ +#define MUX_PB12C_SERCOM4_PAD0 _L_(2) +#define PINMUX_PB12C_SERCOM4_PAD0 ((PIN_PB12C_SERCOM4_PAD0 << 16) | MUX_PB12C_SERCOM4_PAD0) +#define PORT_PB12C_SERCOM4_PAD0 (_UL_(1) << 12) +#define PIN_PA12D_SERCOM4_PAD1 _L_(12) /**< \brief SERCOM4 signal: PAD1 on PA12 mux D */ +#define MUX_PA12D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PA12D_SERCOM4_PAD1 ((PIN_PA12D_SERCOM4_PAD1 << 16) | MUX_PA12D_SERCOM4_PAD1) +#define PORT_PA12D_SERCOM4_PAD1 (_UL_(1) << 12) +#define PIN_PB09D_SERCOM4_PAD1 _L_(41) /**< \brief SERCOM4 signal: PAD1 on PB09 mux D */ +#define MUX_PB09D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB09D_SERCOM4_PAD1 ((PIN_PB09D_SERCOM4_PAD1 << 16) | MUX_PB09D_SERCOM4_PAD1) +#define PORT_PB09D_SERCOM4_PAD1 (_UL_(1) << 9) +#define PIN_PB26D_SERCOM4_PAD1 _L_(58) /**< \brief SERCOM4 signal: PAD1 on PB26 mux D */ +#define MUX_PB26D_SERCOM4_PAD1 _L_(3) +#define PINMUX_PB26D_SERCOM4_PAD1 ((PIN_PB26D_SERCOM4_PAD1 << 16) | MUX_PB26D_SERCOM4_PAD1) +#define PORT_PB26D_SERCOM4_PAD1 (_UL_(1) << 26) +#define PIN_PB13C_SERCOM4_PAD1 _L_(45) /**< \brief SERCOM4 signal: PAD1 on PB13 mux C */ +#define MUX_PB13C_SERCOM4_PAD1 _L_(2) +#define PINMUX_PB13C_SERCOM4_PAD1 ((PIN_PB13C_SERCOM4_PAD1 << 16) | MUX_PB13C_SERCOM4_PAD1) +#define PORT_PB13C_SERCOM4_PAD1 (_UL_(1) << 13) +#define PIN_PA14D_SERCOM4_PAD2 _L_(14) /**< \brief SERCOM4 signal: PAD2 on PA14 mux D */ +#define MUX_PA14D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PA14D_SERCOM4_PAD2 ((PIN_PA14D_SERCOM4_PAD2 << 16) | MUX_PA14D_SERCOM4_PAD2) +#define PORT_PA14D_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB10D_SERCOM4_PAD2 _L_(42) /**< \brief SERCOM4 signal: PAD2 on PB10 mux D */ +#define MUX_PB10D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB10D_SERCOM4_PAD2 ((PIN_PB10D_SERCOM4_PAD2 << 16) | MUX_PB10D_SERCOM4_PAD2) +#define PORT_PB10D_SERCOM4_PAD2 (_UL_(1) << 10) +#define PIN_PB28D_SERCOM4_PAD2 _L_(60) /**< \brief SERCOM4 signal: PAD2 on PB28 mux D */ +#define MUX_PB28D_SERCOM4_PAD2 _L_(3) +#define PINMUX_PB28D_SERCOM4_PAD2 ((PIN_PB28D_SERCOM4_PAD2 << 16) | MUX_PB28D_SERCOM4_PAD2) +#define PORT_PB28D_SERCOM4_PAD2 (_UL_(1) << 28) +#define PIN_PB14C_SERCOM4_PAD2 _L_(46) /**< \brief SERCOM4 signal: PAD2 on PB14 mux C */ +#define MUX_PB14C_SERCOM4_PAD2 _L_(2) +#define PINMUX_PB14C_SERCOM4_PAD2 ((PIN_PB14C_SERCOM4_PAD2 << 16) | MUX_PB14C_SERCOM4_PAD2) +#define PORT_PB14C_SERCOM4_PAD2 (_UL_(1) << 14) +#define PIN_PB11D_SERCOM4_PAD3 _L_(43) /**< \brief SERCOM4 signal: PAD3 on PB11 mux D */ +#define MUX_PB11D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB11D_SERCOM4_PAD3 ((PIN_PB11D_SERCOM4_PAD3 << 16) | MUX_PB11D_SERCOM4_PAD3) +#define PORT_PB11D_SERCOM4_PAD3 (_UL_(1) << 11) +#define PIN_PB29D_SERCOM4_PAD3 _L_(61) /**< \brief SERCOM4 signal: PAD3 on PB29 mux D */ +#define MUX_PB29D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PB29D_SERCOM4_PAD3 ((PIN_PB29D_SERCOM4_PAD3 << 16) | MUX_PB29D_SERCOM4_PAD3) +#define PORT_PB29D_SERCOM4_PAD3 (_UL_(1) << 29) +#define PIN_PA15D_SERCOM4_PAD3 _L_(15) /**< \brief SERCOM4 signal: PAD3 on PA15 mux D */ +#define MUX_PA15D_SERCOM4_PAD3 _L_(3) +#define PINMUX_PA15D_SERCOM4_PAD3 ((PIN_PA15D_SERCOM4_PAD3 << 16) | MUX_PA15D_SERCOM4_PAD3) +#define PORT_PA15D_SERCOM4_PAD3 (_UL_(1) << 15) +#define PIN_PB15C_SERCOM4_PAD3 _L_(47) /**< \brief SERCOM4 signal: PAD3 on PB15 mux C */ +#define MUX_PB15C_SERCOM4_PAD3 _L_(2) +#define PINMUX_PB15C_SERCOM4_PAD3 ((PIN_PB15C_SERCOM4_PAD3 << 16) | MUX_PB15C_SERCOM4_PAD3) +#define PORT_PB15C_SERCOM4_PAD3 (_UL_(1) << 15) +/* ========== PORT definition for SERCOM5 peripheral ========== */ +#define PIN_PA23D_SERCOM5_PAD0 _L_(23) /**< \brief SERCOM5 signal: PAD0 on PA23 mux D */ +#define MUX_PA23D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PA23D_SERCOM5_PAD0 ((PIN_PA23D_SERCOM5_PAD0 << 16) | MUX_PA23D_SERCOM5_PAD0) +#define PORT_PA23D_SERCOM5_PAD0 (_UL_(1) << 23) +#define PIN_PB02D_SERCOM5_PAD0 _L_(34) /**< \brief SERCOM5 signal: PAD0 on PB02 mux D */ +#define MUX_PB02D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB02D_SERCOM5_PAD0 ((PIN_PB02D_SERCOM5_PAD0 << 16) | MUX_PB02D_SERCOM5_PAD0) +#define PORT_PB02D_SERCOM5_PAD0 (_UL_(1) << 2) +#define PIN_PB31D_SERCOM5_PAD0 _L_(63) /**< \brief SERCOM5 signal: PAD0 on PB31 mux D */ +#define MUX_PB31D_SERCOM5_PAD0 _L_(3) +#define PINMUX_PB31D_SERCOM5_PAD0 ((PIN_PB31D_SERCOM5_PAD0 << 16) | MUX_PB31D_SERCOM5_PAD0) +#define PORT_PB31D_SERCOM5_PAD0 (_UL_(1) << 31) +#define PIN_PB16C_SERCOM5_PAD0 _L_(48) /**< \brief SERCOM5 signal: PAD0 on PB16 mux C */ +#define MUX_PB16C_SERCOM5_PAD0 _L_(2) +#define PINMUX_PB16C_SERCOM5_PAD0 ((PIN_PB16C_SERCOM5_PAD0 << 16) | MUX_PB16C_SERCOM5_PAD0) +#define PORT_PB16C_SERCOM5_PAD0 (_UL_(1) << 16) +#define PIN_PA22D_SERCOM5_PAD1 _L_(22) /**< \brief SERCOM5 signal: PAD1 on PA22 mux D */ +#define MUX_PA22D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PA22D_SERCOM5_PAD1 ((PIN_PA22D_SERCOM5_PAD1 << 16) | MUX_PA22D_SERCOM5_PAD1) +#define PORT_PA22D_SERCOM5_PAD1 (_UL_(1) << 22) +#define PIN_PB03D_SERCOM5_PAD1 _L_(35) /**< \brief SERCOM5 signal: PAD1 on PB03 mux D */ +#define MUX_PB03D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB03D_SERCOM5_PAD1 ((PIN_PB03D_SERCOM5_PAD1 << 16) | MUX_PB03D_SERCOM5_PAD1) +#define PORT_PB03D_SERCOM5_PAD1 (_UL_(1) << 3) +#define PIN_PB30D_SERCOM5_PAD1 _L_(62) /**< \brief SERCOM5 signal: PAD1 on PB30 mux D */ +#define MUX_PB30D_SERCOM5_PAD1 _L_(3) +#define PINMUX_PB30D_SERCOM5_PAD1 ((PIN_PB30D_SERCOM5_PAD1 << 16) | MUX_PB30D_SERCOM5_PAD1) +#define PORT_PB30D_SERCOM5_PAD1 (_UL_(1) << 30) +#define PIN_PB17C_SERCOM5_PAD1 _L_(49) /**< \brief SERCOM5 signal: PAD1 on PB17 mux C */ +#define MUX_PB17C_SERCOM5_PAD1 _L_(2) +#define PINMUX_PB17C_SERCOM5_PAD1 ((PIN_PB17C_SERCOM5_PAD1 << 16) | MUX_PB17C_SERCOM5_PAD1) +#define PORT_PB17C_SERCOM5_PAD1 (_UL_(1) << 17) +#define PIN_PA24D_SERCOM5_PAD2 _L_(24) /**< \brief SERCOM5 signal: PAD2 on PA24 mux D */ +#define MUX_PA24D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PA24D_SERCOM5_PAD2 ((PIN_PA24D_SERCOM5_PAD2 << 16) | MUX_PA24D_SERCOM5_PAD2) +#define PORT_PA24D_SERCOM5_PAD2 (_UL_(1) << 24) +#define PIN_PB00D_SERCOM5_PAD2 _L_(32) /**< \brief SERCOM5 signal: PAD2 on PB00 mux D */ +#define MUX_PB00D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB00D_SERCOM5_PAD2 ((PIN_PB00D_SERCOM5_PAD2 << 16) | MUX_PB00D_SERCOM5_PAD2) +#define PORT_PB00D_SERCOM5_PAD2 (_UL_(1) << 0) +#define PIN_PB22D_SERCOM5_PAD2 _L_(54) /**< \brief SERCOM5 signal: PAD2 on PB22 mux D */ +#define MUX_PB22D_SERCOM5_PAD2 _L_(3) +#define PINMUX_PB22D_SERCOM5_PAD2 ((PIN_PB22D_SERCOM5_PAD2 << 16) | MUX_PB22D_SERCOM5_PAD2) +#define PORT_PB22D_SERCOM5_PAD2 (_UL_(1) << 22) +#define PIN_PA20C_SERCOM5_PAD2 _L_(20) /**< \brief SERCOM5 signal: PAD2 on PA20 mux C */ +#define MUX_PA20C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PA20C_SERCOM5_PAD2 ((PIN_PA20C_SERCOM5_PAD2 << 16) | MUX_PA20C_SERCOM5_PAD2) +#define PORT_PA20C_SERCOM5_PAD2 (_UL_(1) << 20) +#define PIN_PB18C_SERCOM5_PAD2 _L_(50) /**< \brief SERCOM5 signal: PAD2 on PB18 mux C */ +#define MUX_PB18C_SERCOM5_PAD2 _L_(2) +#define PINMUX_PB18C_SERCOM5_PAD2 ((PIN_PB18C_SERCOM5_PAD2 << 16) | MUX_PB18C_SERCOM5_PAD2) +#define PORT_PB18C_SERCOM5_PAD2 (_UL_(1) << 18) +#define PIN_PA25D_SERCOM5_PAD3 _L_(25) /**< \brief SERCOM5 signal: PAD3 on PA25 mux D */ +#define MUX_PA25D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PA25D_SERCOM5_PAD3 ((PIN_PA25D_SERCOM5_PAD3 << 16) | MUX_PA25D_SERCOM5_PAD3) +#define PORT_PA25D_SERCOM5_PAD3 (_UL_(1) << 25) +#define PIN_PB01D_SERCOM5_PAD3 _L_(33) /**< \brief SERCOM5 signal: PAD3 on PB01 mux D */ +#define MUX_PB01D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB01D_SERCOM5_PAD3 ((PIN_PB01D_SERCOM5_PAD3 << 16) | MUX_PB01D_SERCOM5_PAD3) +#define PORT_PB01D_SERCOM5_PAD3 (_UL_(1) << 1) +#define PIN_PB23D_SERCOM5_PAD3 _L_(55) /**< \brief SERCOM5 signal: PAD3 on PB23 mux D */ +#define MUX_PB23D_SERCOM5_PAD3 _L_(3) +#define PINMUX_PB23D_SERCOM5_PAD3 ((PIN_PB23D_SERCOM5_PAD3 << 16) | MUX_PB23D_SERCOM5_PAD3) +#define PORT_PB23D_SERCOM5_PAD3 (_UL_(1) << 23) +#define PIN_PA21C_SERCOM5_PAD3 _L_(21) /**< \brief SERCOM5 signal: PAD3 on PA21 mux C */ +#define MUX_PA21C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PA21C_SERCOM5_PAD3 ((PIN_PA21C_SERCOM5_PAD3 << 16) | MUX_PA21C_SERCOM5_PAD3) +#define PORT_PA21C_SERCOM5_PAD3 (_UL_(1) << 21) +#define PIN_PB19C_SERCOM5_PAD3 _L_(51) /**< \brief SERCOM5 signal: PAD3 on PB19 mux C */ +#define MUX_PB19C_SERCOM5_PAD3 _L_(2) +#define PINMUX_PB19C_SERCOM5_PAD3 ((PIN_PB19C_SERCOM5_PAD3 << 16) | MUX_PB19C_SERCOM5_PAD3) +#define PORT_PB19C_SERCOM5_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM6 peripheral ========== */ +#define PIN_PD09D_SERCOM6_PAD0 _L_(105) /**< \brief SERCOM6 signal: PAD0 on PD09 mux D */ +#define MUX_PD09D_SERCOM6_PAD0 _L_(3) +#define PINMUX_PD09D_SERCOM6_PAD0 ((PIN_PD09D_SERCOM6_PAD0 << 16) | MUX_PD09D_SERCOM6_PAD0) +#define PORT_PD09D_SERCOM6_PAD0 (_UL_(1) << 9) +#define PIN_PC13D_SERCOM6_PAD0 _L_(77) /**< \brief SERCOM6 signal: PAD0 on PC13 mux D */ +#define MUX_PC13D_SERCOM6_PAD0 _L_(3) +#define PINMUX_PC13D_SERCOM6_PAD0 ((PIN_PC13D_SERCOM6_PAD0 << 16) | MUX_PC13D_SERCOM6_PAD0) +#define PORT_PC13D_SERCOM6_PAD0 (_UL_(1) << 13) +#define PIN_PC04C_SERCOM6_PAD0 _L_(68) /**< \brief SERCOM6 signal: PAD0 on PC04 mux C */ +#define MUX_PC04C_SERCOM6_PAD0 _L_(2) +#define PINMUX_PC04C_SERCOM6_PAD0 ((PIN_PC04C_SERCOM6_PAD0 << 16) | MUX_PC04C_SERCOM6_PAD0) +#define PORT_PC04C_SERCOM6_PAD0 (_UL_(1) << 4) +#define PIN_PC16C_SERCOM6_PAD0 _L_(80) /**< \brief SERCOM6 signal: PAD0 on PC16 mux C */ +#define MUX_PC16C_SERCOM6_PAD0 _L_(2) +#define PINMUX_PC16C_SERCOM6_PAD0 ((PIN_PC16C_SERCOM6_PAD0 << 16) | MUX_PC16C_SERCOM6_PAD0) +#define PORT_PC16C_SERCOM6_PAD0 (_UL_(1) << 16) +#define PIN_PD08D_SERCOM6_PAD1 _L_(104) /**< \brief SERCOM6 signal: PAD1 on PD08 mux D */ +#define MUX_PD08D_SERCOM6_PAD1 _L_(3) +#define PINMUX_PD08D_SERCOM6_PAD1 ((PIN_PD08D_SERCOM6_PAD1 << 16) | MUX_PD08D_SERCOM6_PAD1) +#define PORT_PD08D_SERCOM6_PAD1 (_UL_(1) << 8) +#define PIN_PC12D_SERCOM6_PAD1 _L_(76) /**< \brief SERCOM6 signal: PAD1 on PC12 mux D */ +#define MUX_PC12D_SERCOM6_PAD1 _L_(3) +#define PINMUX_PC12D_SERCOM6_PAD1 ((PIN_PC12D_SERCOM6_PAD1 << 16) | MUX_PC12D_SERCOM6_PAD1) +#define PORT_PC12D_SERCOM6_PAD1 (_UL_(1) << 12) +#define PIN_PC05C_SERCOM6_PAD1 _L_(69) /**< \brief SERCOM6 signal: PAD1 on PC05 mux C */ +#define MUX_PC05C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC05C_SERCOM6_PAD1 ((PIN_PC05C_SERCOM6_PAD1 << 16) | MUX_PC05C_SERCOM6_PAD1) +#define PORT_PC05C_SERCOM6_PAD1 (_UL_(1) << 5) +#define PIN_PC17C_SERCOM6_PAD1 _L_(81) /**< \brief SERCOM6 signal: PAD1 on PC17 mux C */ +#define MUX_PC17C_SERCOM6_PAD1 _L_(2) +#define PINMUX_PC17C_SERCOM6_PAD1 ((PIN_PC17C_SERCOM6_PAD1 << 16) | MUX_PC17C_SERCOM6_PAD1) +#define PORT_PC17C_SERCOM6_PAD1 (_UL_(1) << 17) +#define PIN_PC14D_SERCOM6_PAD2 _L_(78) /**< \brief SERCOM6 signal: PAD2 on PC14 mux D */ +#define MUX_PC14D_SERCOM6_PAD2 _L_(3) +#define PINMUX_PC14D_SERCOM6_PAD2 ((PIN_PC14D_SERCOM6_PAD2 << 16) | MUX_PC14D_SERCOM6_PAD2) +#define PORT_PC14D_SERCOM6_PAD2 (_UL_(1) << 14) +#define PIN_PD10D_SERCOM6_PAD2 _L_(106) /**< \brief SERCOM6 signal: PAD2 on PD10 mux D */ +#define MUX_PD10D_SERCOM6_PAD2 _L_(3) +#define PINMUX_PD10D_SERCOM6_PAD2 ((PIN_PD10D_SERCOM6_PAD2 << 16) | MUX_PD10D_SERCOM6_PAD2) +#define PORT_PD10D_SERCOM6_PAD2 (_UL_(1) << 10) +#define PIN_PC06C_SERCOM6_PAD2 _L_(70) /**< \brief SERCOM6 signal: PAD2 on PC06 mux C */ +#define MUX_PC06C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC06C_SERCOM6_PAD2 ((PIN_PC06C_SERCOM6_PAD2 << 16) | MUX_PC06C_SERCOM6_PAD2) +#define PORT_PC06C_SERCOM6_PAD2 (_UL_(1) << 6) +#define PIN_PC10C_SERCOM6_PAD2 _L_(74) /**< \brief SERCOM6 signal: PAD2 on PC10 mux C */ +#define MUX_PC10C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC10C_SERCOM6_PAD2 ((PIN_PC10C_SERCOM6_PAD2 << 16) | MUX_PC10C_SERCOM6_PAD2) +#define PORT_PC10C_SERCOM6_PAD2 (_UL_(1) << 10) +#define PIN_PC18C_SERCOM6_PAD2 _L_(82) /**< \brief SERCOM6 signal: PAD2 on PC18 mux C */ +#define MUX_PC18C_SERCOM6_PAD2 _L_(2) +#define PINMUX_PC18C_SERCOM6_PAD2 ((PIN_PC18C_SERCOM6_PAD2 << 16) | MUX_PC18C_SERCOM6_PAD2) +#define PORT_PC18C_SERCOM6_PAD2 (_UL_(1) << 18) +#define PIN_PC15D_SERCOM6_PAD3 _L_(79) /**< \brief SERCOM6 signal: PAD3 on PC15 mux D */ +#define MUX_PC15D_SERCOM6_PAD3 _L_(3) +#define PINMUX_PC15D_SERCOM6_PAD3 ((PIN_PC15D_SERCOM6_PAD3 << 16) | MUX_PC15D_SERCOM6_PAD3) +#define PORT_PC15D_SERCOM6_PAD3 (_UL_(1) << 15) +#define PIN_PD11D_SERCOM6_PAD3 _L_(107) /**< \brief SERCOM6 signal: PAD3 on PD11 mux D */ +#define MUX_PD11D_SERCOM6_PAD3 _L_(3) +#define PINMUX_PD11D_SERCOM6_PAD3 ((PIN_PD11D_SERCOM6_PAD3 << 16) | MUX_PD11D_SERCOM6_PAD3) +#define PORT_PD11D_SERCOM6_PAD3 (_UL_(1) << 11) +#define PIN_PC07C_SERCOM6_PAD3 _L_(71) /**< \brief SERCOM6 signal: PAD3 on PC07 mux C */ +#define MUX_PC07C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC07C_SERCOM6_PAD3 ((PIN_PC07C_SERCOM6_PAD3 << 16) | MUX_PC07C_SERCOM6_PAD3) +#define PORT_PC07C_SERCOM6_PAD3 (_UL_(1) << 7) +#define PIN_PC11C_SERCOM6_PAD3 _L_(75) /**< \brief SERCOM6 signal: PAD3 on PC11 mux C */ +#define MUX_PC11C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC11C_SERCOM6_PAD3 ((PIN_PC11C_SERCOM6_PAD3 << 16) | MUX_PC11C_SERCOM6_PAD3) +#define PORT_PC11C_SERCOM6_PAD3 (_UL_(1) << 11) +#define PIN_PC19C_SERCOM6_PAD3 _L_(83) /**< \brief SERCOM6 signal: PAD3 on PC19 mux C */ +#define MUX_PC19C_SERCOM6_PAD3 _L_(2) +#define PINMUX_PC19C_SERCOM6_PAD3 ((PIN_PC19C_SERCOM6_PAD3 << 16) | MUX_PC19C_SERCOM6_PAD3) +#define PORT_PC19C_SERCOM6_PAD3 (_UL_(1) << 19) +/* ========== PORT definition for SERCOM7 peripheral ========== */ +#define PIN_PB21D_SERCOM7_PAD0 _L_(53) /**< \brief SERCOM7 signal: PAD0 on PB21 mux D */ +#define MUX_PB21D_SERCOM7_PAD0 _L_(3) +#define PINMUX_PB21D_SERCOM7_PAD0 ((PIN_PB21D_SERCOM7_PAD0 << 16) | MUX_PB21D_SERCOM7_PAD0) +#define PORT_PB21D_SERCOM7_PAD0 (_UL_(1) << 21) +#define PIN_PD08C_SERCOM7_PAD0 _L_(104) /**< \brief SERCOM7 signal: PAD0 on PD08 mux C */ +#define MUX_PD08C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PD08C_SERCOM7_PAD0 ((PIN_PD08C_SERCOM7_PAD0 << 16) | MUX_PD08C_SERCOM7_PAD0) +#define PORT_PD08C_SERCOM7_PAD0 (_UL_(1) << 8) +#define PIN_PB30C_SERCOM7_PAD0 _L_(62) /**< \brief SERCOM7 signal: PAD0 on PB30 mux C */ +#define MUX_PB30C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PB30C_SERCOM7_PAD0 ((PIN_PB30C_SERCOM7_PAD0 << 16) | MUX_PB30C_SERCOM7_PAD0) +#define PORT_PB30C_SERCOM7_PAD0 (_UL_(1) << 30) +#define PIN_PC12C_SERCOM7_PAD0 _L_(76) /**< \brief SERCOM7 signal: PAD0 on PC12 mux C */ +#define MUX_PC12C_SERCOM7_PAD0 _L_(2) +#define PINMUX_PC12C_SERCOM7_PAD0 ((PIN_PC12C_SERCOM7_PAD0 << 16) | MUX_PC12C_SERCOM7_PAD0) +#define PORT_PC12C_SERCOM7_PAD0 (_UL_(1) << 12) +#define PIN_PB20D_SERCOM7_PAD1 _L_(52) /**< \brief SERCOM7 signal: PAD1 on PB20 mux D */ +#define MUX_PB20D_SERCOM7_PAD1 _L_(3) +#define PINMUX_PB20D_SERCOM7_PAD1 ((PIN_PB20D_SERCOM7_PAD1 << 16) | MUX_PB20D_SERCOM7_PAD1) +#define PORT_PB20D_SERCOM7_PAD1 (_UL_(1) << 20) +#define PIN_PD09C_SERCOM7_PAD1 _L_(105) /**< \brief SERCOM7 signal: PAD1 on PD09 mux C */ +#define MUX_PD09C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PD09C_SERCOM7_PAD1 ((PIN_PD09C_SERCOM7_PAD1 << 16) | MUX_PD09C_SERCOM7_PAD1) +#define PORT_PD09C_SERCOM7_PAD1 (_UL_(1) << 9) +#define PIN_PB31C_SERCOM7_PAD1 _L_(63) /**< \brief SERCOM7 signal: PAD1 on PB31 mux C */ +#define MUX_PB31C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PB31C_SERCOM7_PAD1 ((PIN_PB31C_SERCOM7_PAD1 << 16) | MUX_PB31C_SERCOM7_PAD1) +#define PORT_PB31C_SERCOM7_PAD1 (_UL_(1) << 31) +#define PIN_PC13C_SERCOM7_PAD1 _L_(77) /**< \brief SERCOM7 signal: PAD1 on PC13 mux C */ +#define MUX_PC13C_SERCOM7_PAD1 _L_(2) +#define PINMUX_PC13C_SERCOM7_PAD1 ((PIN_PC13C_SERCOM7_PAD1 << 16) | MUX_PC13C_SERCOM7_PAD1) +#define PORT_PC13C_SERCOM7_PAD1 (_UL_(1) << 13) +#define PIN_PB18D_SERCOM7_PAD2 _L_(50) /**< \brief SERCOM7 signal: PAD2 on PB18 mux D */ +#define MUX_PB18D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PB18D_SERCOM7_PAD2 ((PIN_PB18D_SERCOM7_PAD2 << 16) | MUX_PB18D_SERCOM7_PAD2) +#define PORT_PB18D_SERCOM7_PAD2 (_UL_(1) << 18) +#define PIN_PC10D_SERCOM7_PAD2 _L_(74) /**< \brief SERCOM7 signal: PAD2 on PC10 mux D */ +#define MUX_PC10D_SERCOM7_PAD2 _L_(3) +#define PINMUX_PC10D_SERCOM7_PAD2 ((PIN_PC10D_SERCOM7_PAD2 << 16) | MUX_PC10D_SERCOM7_PAD2) +#define PORT_PC10D_SERCOM7_PAD2 (_UL_(1) << 10) +#define PIN_PC14C_SERCOM7_PAD2 _L_(78) /**< \brief SERCOM7 signal: PAD2 on PC14 mux C */ +#define MUX_PC14C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PC14C_SERCOM7_PAD2 ((PIN_PC14C_SERCOM7_PAD2 << 16) | MUX_PC14C_SERCOM7_PAD2) +#define PORT_PC14C_SERCOM7_PAD2 (_UL_(1) << 14) +#define PIN_PD10C_SERCOM7_PAD2 _L_(106) /**< \brief SERCOM7 signal: PAD2 on PD10 mux C */ +#define MUX_PD10C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PD10C_SERCOM7_PAD2 ((PIN_PD10C_SERCOM7_PAD2 << 16) | MUX_PD10C_SERCOM7_PAD2) +#define PORT_PD10C_SERCOM7_PAD2 (_UL_(1) << 10) +#define PIN_PA30C_SERCOM7_PAD2 _L_(30) /**< \brief SERCOM7 signal: PAD2 on PA30 mux C */ +#define MUX_PA30C_SERCOM7_PAD2 _L_(2) +#define PINMUX_PA30C_SERCOM7_PAD2 ((PIN_PA30C_SERCOM7_PAD2 << 16) | MUX_PA30C_SERCOM7_PAD2) +#define PORT_PA30C_SERCOM7_PAD2 (_UL_(1) << 30) +#define PIN_PB19D_SERCOM7_PAD3 _L_(51) /**< \brief SERCOM7 signal: PAD3 on PB19 mux D */ +#define MUX_PB19D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PB19D_SERCOM7_PAD3 ((PIN_PB19D_SERCOM7_PAD3 << 16) | MUX_PB19D_SERCOM7_PAD3) +#define PORT_PB19D_SERCOM7_PAD3 (_UL_(1) << 19) +#define PIN_PC11D_SERCOM7_PAD3 _L_(75) /**< \brief SERCOM7 signal: PAD3 on PC11 mux D */ +#define MUX_PC11D_SERCOM7_PAD3 _L_(3) +#define PINMUX_PC11D_SERCOM7_PAD3 ((PIN_PC11D_SERCOM7_PAD3 << 16) | MUX_PC11D_SERCOM7_PAD3) +#define PORT_PC11D_SERCOM7_PAD3 (_UL_(1) << 11) +#define PIN_PC15C_SERCOM7_PAD3 _L_(79) /**< \brief SERCOM7 signal: PAD3 on PC15 mux C */ +#define MUX_PC15C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PC15C_SERCOM7_PAD3 ((PIN_PC15C_SERCOM7_PAD3 << 16) | MUX_PC15C_SERCOM7_PAD3) +#define PORT_PC15C_SERCOM7_PAD3 (_UL_(1) << 15) +#define PIN_PD11C_SERCOM7_PAD3 _L_(107) /**< \brief SERCOM7 signal: PAD3 on PD11 mux C */ +#define MUX_PD11C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PD11C_SERCOM7_PAD3 ((PIN_PD11C_SERCOM7_PAD3 << 16) | MUX_PD11C_SERCOM7_PAD3) +#define PORT_PD11C_SERCOM7_PAD3 (_UL_(1) << 11) +#define PIN_PA31C_SERCOM7_PAD3 _L_(31) /**< \brief SERCOM7 signal: PAD3 on PA31 mux C */ +#define MUX_PA31C_SERCOM7_PAD3 _L_(2) +#define PINMUX_PA31C_SERCOM7_PAD3 ((PIN_PA31C_SERCOM7_PAD3 << 16) | MUX_PA31C_SERCOM7_PAD3) +#define PORT_PA31C_SERCOM7_PAD3 (_UL_(1) << 31) +/* ========== PORT definition for TCC4 peripheral ========== */ +#define PIN_PB14F_TCC4_WO0 _L_(46) /**< \brief TCC4 signal: WO0 on PB14 mux F */ +#define MUX_PB14F_TCC4_WO0 _L_(5) +#define PINMUX_PB14F_TCC4_WO0 ((PIN_PB14F_TCC4_WO0 << 16) | MUX_PB14F_TCC4_WO0) +#define PORT_PB14F_TCC4_WO0 (_UL_(1) << 14) +#define PIN_PB30F_TCC4_WO0 _L_(62) /**< \brief TCC4 signal: WO0 on PB30 mux F */ +#define MUX_PB30F_TCC4_WO0 _L_(5) +#define PINMUX_PB30F_TCC4_WO0 ((PIN_PB30F_TCC4_WO0 << 16) | MUX_PB30F_TCC4_WO0) +#define PORT_PB30F_TCC4_WO0 (_UL_(1) << 30) +#define PIN_PB15F_TCC4_WO1 _L_(47) /**< \brief TCC4 signal: WO1 on PB15 mux F */ +#define MUX_PB15F_TCC4_WO1 _L_(5) +#define PINMUX_PB15F_TCC4_WO1 ((PIN_PB15F_TCC4_WO1 << 16) | MUX_PB15F_TCC4_WO1) +#define PORT_PB15F_TCC4_WO1 (_UL_(1) << 15) +#define PIN_PB31F_TCC4_WO1 _L_(63) /**< \brief TCC4 signal: WO1 on PB31 mux F */ +#define MUX_PB31F_TCC4_WO1 _L_(5) +#define PINMUX_PB31F_TCC4_WO1 ((PIN_PB31F_TCC4_WO1 << 16) | MUX_PB31F_TCC4_WO1) +#define PORT_PB31F_TCC4_WO1 (_UL_(1) << 31) +/* ========== PORT definition for TC6 peripheral ========== */ +#define PIN_PA30E_TC6_WO0 _L_(30) /**< \brief TC6 signal: WO0 on PA30 mux E */ +#define MUX_PA30E_TC6_WO0 _L_(4) +#define PINMUX_PA30E_TC6_WO0 ((PIN_PA30E_TC6_WO0 << 16) | MUX_PA30E_TC6_WO0) +#define PORT_PA30E_TC6_WO0 (_UL_(1) << 30) +#define PIN_PB02E_TC6_WO0 _L_(34) /**< \brief TC6 signal: WO0 on PB02 mux E */ +#define MUX_PB02E_TC6_WO0 _L_(4) +#define PINMUX_PB02E_TC6_WO0 ((PIN_PB02E_TC6_WO0 << 16) | MUX_PB02E_TC6_WO0) +#define PORT_PB02E_TC6_WO0 (_UL_(1) << 2) +#define PIN_PB16E_TC6_WO0 _L_(48) /**< \brief TC6 signal: WO0 on PB16 mux E */ +#define MUX_PB16E_TC6_WO0 _L_(4) +#define PINMUX_PB16E_TC6_WO0 ((PIN_PB16E_TC6_WO0 << 16) | MUX_PB16E_TC6_WO0) +#define PORT_PB16E_TC6_WO0 (_UL_(1) << 16) +#define PIN_PA31E_TC6_WO1 _L_(31) /**< \brief TC6 signal: WO1 on PA31 mux E */ +#define MUX_PA31E_TC6_WO1 _L_(4) +#define PINMUX_PA31E_TC6_WO1 ((PIN_PA31E_TC6_WO1 << 16) | MUX_PA31E_TC6_WO1) +#define PORT_PA31E_TC6_WO1 (_UL_(1) << 31) +#define PIN_PB03E_TC6_WO1 _L_(35) /**< \brief TC6 signal: WO1 on PB03 mux E */ +#define MUX_PB03E_TC6_WO1 _L_(4) +#define PINMUX_PB03E_TC6_WO1 ((PIN_PB03E_TC6_WO1 << 16) | MUX_PB03E_TC6_WO1) +#define PORT_PB03E_TC6_WO1 (_UL_(1) << 3) +#define PIN_PB17E_TC6_WO1 _L_(49) /**< \brief TC6 signal: WO1 on PB17 mux E */ +#define MUX_PB17E_TC6_WO1 _L_(4) +#define PINMUX_PB17E_TC6_WO1 ((PIN_PB17E_TC6_WO1 << 16) | MUX_PB17E_TC6_WO1) +#define PORT_PB17E_TC6_WO1 (_UL_(1) << 17) +/* ========== PORT definition for TC7 peripheral ========== */ +#define PIN_PA20E_TC7_WO0 _L_(20) /**< \brief TC7 signal: WO0 on PA20 mux E */ +#define MUX_PA20E_TC7_WO0 _L_(4) +#define PINMUX_PA20E_TC7_WO0 ((PIN_PA20E_TC7_WO0 << 16) | MUX_PA20E_TC7_WO0) +#define PORT_PA20E_TC7_WO0 (_UL_(1) << 20) +#define PIN_PB00E_TC7_WO0 _L_(32) /**< \brief TC7 signal: WO0 on PB00 mux E */ +#define MUX_PB00E_TC7_WO0 _L_(4) +#define PINMUX_PB00E_TC7_WO0 ((PIN_PB00E_TC7_WO0 << 16) | MUX_PB00E_TC7_WO0) +#define PORT_PB00E_TC7_WO0 (_UL_(1) << 0) +#define PIN_PB22E_TC7_WO0 _L_(54) /**< \brief TC7 signal: WO0 on PB22 mux E */ +#define MUX_PB22E_TC7_WO0 _L_(4) +#define PINMUX_PB22E_TC7_WO0 ((PIN_PB22E_TC7_WO0 << 16) | MUX_PB22E_TC7_WO0) +#define PORT_PB22E_TC7_WO0 (_UL_(1) << 22) +#define PIN_PA21E_TC7_WO1 _L_(21) /**< \brief TC7 signal: WO1 on PA21 mux E */ +#define MUX_PA21E_TC7_WO1 _L_(4) +#define PINMUX_PA21E_TC7_WO1 ((PIN_PA21E_TC7_WO1 << 16) | MUX_PA21E_TC7_WO1) +#define PORT_PA21E_TC7_WO1 (_UL_(1) << 21) +#define PIN_PB01E_TC7_WO1 _L_(33) /**< \brief TC7 signal: WO1 on PB01 mux E */ +#define MUX_PB01E_TC7_WO1 _L_(4) +#define PINMUX_PB01E_TC7_WO1 ((PIN_PB01E_TC7_WO1 << 16) | MUX_PB01E_TC7_WO1) +#define PORT_PB01E_TC7_WO1 (_UL_(1) << 1) +#define PIN_PB23E_TC7_WO1 _L_(55) /**< \brief TC7 signal: WO1 on PB23 mux E */ +#define MUX_PB23E_TC7_WO1 _L_(4) +#define PINMUX_PB23E_TC7_WO1 ((PIN_PB23E_TC7_WO1 << 16) | MUX_PB23E_TC7_WO1) +#define PORT_PB23E_TC7_WO1 (_UL_(1) << 23) +/* ========== PORT definition for ADC0 peripheral ========== */ +#define PIN_PA02B_ADC0_AIN0 _L_(2) /**< \brief ADC0 signal: AIN0 on PA02 mux B */ +#define MUX_PA02B_ADC0_AIN0 _L_(1) +#define PINMUX_PA02B_ADC0_AIN0 ((PIN_PA02B_ADC0_AIN0 << 16) | MUX_PA02B_ADC0_AIN0) +#define PORT_PA02B_ADC0_AIN0 (_UL_(1) << 2) +#define PIN_PA03B_ADC0_AIN1 _L_(3) /**< \brief ADC0 signal: AIN1 on PA03 mux B */ +#define MUX_PA03B_ADC0_AIN1 _L_(1) +#define PINMUX_PA03B_ADC0_AIN1 ((PIN_PA03B_ADC0_AIN1 << 16) | MUX_PA03B_ADC0_AIN1) +#define PORT_PA03B_ADC0_AIN1 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_AIN2 _L_(40) /**< \brief ADC0 signal: AIN2 on PB08 mux B */ +#define MUX_PB08B_ADC0_AIN2 _L_(1) +#define PINMUX_PB08B_ADC0_AIN2 ((PIN_PB08B_ADC0_AIN2 << 16) | MUX_PB08B_ADC0_AIN2) +#define PORT_PB08B_ADC0_AIN2 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_AIN3 _L_(41) /**< \brief ADC0 signal: AIN3 on PB09 mux B */ +#define MUX_PB09B_ADC0_AIN3 _L_(1) +#define PINMUX_PB09B_ADC0_AIN3 ((PIN_PB09B_ADC0_AIN3 << 16) | MUX_PB09B_ADC0_AIN3) +#define PORT_PB09B_ADC0_AIN3 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_AIN4 _L_(4) /**< \brief ADC0 signal: AIN4 on PA04 mux B */ +#define MUX_PA04B_ADC0_AIN4 _L_(1) +#define PINMUX_PA04B_ADC0_AIN4 ((PIN_PA04B_ADC0_AIN4 << 16) | MUX_PA04B_ADC0_AIN4) +#define PORT_PA04B_ADC0_AIN4 (_UL_(1) << 4) +#define PIN_PA05B_ADC0_AIN5 _L_(5) /**< \brief ADC0 signal: AIN5 on PA05 mux B */ +#define MUX_PA05B_ADC0_AIN5 _L_(1) +#define PINMUX_PA05B_ADC0_AIN5 ((PIN_PA05B_ADC0_AIN5 << 16) | MUX_PA05B_ADC0_AIN5) +#define PORT_PA05B_ADC0_AIN5 (_UL_(1) << 5) +#define PIN_PA06B_ADC0_AIN6 _L_(6) /**< \brief ADC0 signal: AIN6 on PA06 mux B */ +#define MUX_PA06B_ADC0_AIN6 _L_(1) +#define PINMUX_PA06B_ADC0_AIN6 ((PIN_PA06B_ADC0_AIN6 << 16) | MUX_PA06B_ADC0_AIN6) +#define PORT_PA06B_ADC0_AIN6 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_AIN7 _L_(7) /**< \brief ADC0 signal: AIN7 on PA07 mux B */ +#define MUX_PA07B_ADC0_AIN7 _L_(1) +#define PINMUX_PA07B_ADC0_AIN7 ((PIN_PA07B_ADC0_AIN7 << 16) | MUX_PA07B_ADC0_AIN7) +#define PORT_PA07B_ADC0_AIN7 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_AIN8 _L_(8) /**< \brief ADC0 signal: AIN8 on PA08 mux B */ +#define MUX_PA08B_ADC0_AIN8 _L_(1) +#define PINMUX_PA08B_ADC0_AIN8 ((PIN_PA08B_ADC0_AIN8 << 16) | MUX_PA08B_ADC0_AIN8) +#define PORT_PA08B_ADC0_AIN8 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_AIN9 _L_(9) /**< \brief ADC0 signal: AIN9 on PA09 mux B */ +#define MUX_PA09B_ADC0_AIN9 _L_(1) +#define PINMUX_PA09B_ADC0_AIN9 ((PIN_PA09B_ADC0_AIN9 << 16) | MUX_PA09B_ADC0_AIN9) +#define PORT_PA09B_ADC0_AIN9 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_AIN10 _L_(10) /**< \brief ADC0 signal: AIN10 on PA10 mux B */ +#define MUX_PA10B_ADC0_AIN10 _L_(1) +#define PINMUX_PA10B_ADC0_AIN10 ((PIN_PA10B_ADC0_AIN10 << 16) | MUX_PA10B_ADC0_AIN10) +#define PORT_PA10B_ADC0_AIN10 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_AIN11 _L_(11) /**< \brief ADC0 signal: AIN11 on PA11 mux B */ +#define MUX_PA11B_ADC0_AIN11 _L_(1) +#define PINMUX_PA11B_ADC0_AIN11 ((PIN_PA11B_ADC0_AIN11 << 16) | MUX_PA11B_ADC0_AIN11) +#define PORT_PA11B_ADC0_AIN11 (_UL_(1) << 11) +#define PIN_PB00B_ADC0_AIN12 _L_(32) /**< \brief ADC0 signal: AIN12 on PB00 mux B */ +#define MUX_PB00B_ADC0_AIN12 _L_(1) +#define PINMUX_PB00B_ADC0_AIN12 ((PIN_PB00B_ADC0_AIN12 << 16) | MUX_PB00B_ADC0_AIN12) +#define PORT_PB00B_ADC0_AIN12 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_AIN13 _L_(33) /**< \brief ADC0 signal: AIN13 on PB01 mux B */ +#define MUX_PB01B_ADC0_AIN13 _L_(1) +#define PINMUX_PB01B_ADC0_AIN13 ((PIN_PB01B_ADC0_AIN13 << 16) | MUX_PB01B_ADC0_AIN13) +#define PORT_PB01B_ADC0_AIN13 (_UL_(1) << 1) +#define PIN_PB02B_ADC0_AIN14 _L_(34) /**< \brief ADC0 signal: AIN14 on PB02 mux B */ +#define MUX_PB02B_ADC0_AIN14 _L_(1) +#define PINMUX_PB02B_ADC0_AIN14 ((PIN_PB02B_ADC0_AIN14 << 16) | MUX_PB02B_ADC0_AIN14) +#define PORT_PB02B_ADC0_AIN14 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_AIN15 _L_(35) /**< \brief ADC0 signal: AIN15 on PB03 mux B */ +#define MUX_PB03B_ADC0_AIN15 _L_(1) +#define PINMUX_PB03B_ADC0_AIN15 ((PIN_PB03B_ADC0_AIN15 << 16) | MUX_PB03B_ADC0_AIN15) +#define PORT_PB03B_ADC0_AIN15 (_UL_(1) << 3) +#define PIN_PA03O_ADC0_DRV0 _L_(3) /**< \brief ADC0 signal: DRV0 on PA03 mux O */ +#define MUX_PA03O_ADC0_DRV0 _L_(14) +#define PINMUX_PA03O_ADC0_DRV0 ((PIN_PA03O_ADC0_DRV0 << 16) | MUX_PA03O_ADC0_DRV0) +#define PORT_PA03O_ADC0_DRV0 (_UL_(1) << 3) +#define PIN_PB08O_ADC0_DRV1 _L_(40) /**< \brief ADC0 signal: DRV1 on PB08 mux O */ +#define MUX_PB08O_ADC0_DRV1 _L_(14) +#define PINMUX_PB08O_ADC0_DRV1 ((PIN_PB08O_ADC0_DRV1 << 16) | MUX_PB08O_ADC0_DRV1) +#define PORT_PB08O_ADC0_DRV1 (_UL_(1) << 8) +#define PIN_PB09O_ADC0_DRV2 _L_(41) /**< \brief ADC0 signal: DRV2 on PB09 mux O */ +#define MUX_PB09O_ADC0_DRV2 _L_(14) +#define PINMUX_PB09O_ADC0_DRV2 ((PIN_PB09O_ADC0_DRV2 << 16) | MUX_PB09O_ADC0_DRV2) +#define PORT_PB09O_ADC0_DRV2 (_UL_(1) << 9) +#define PIN_PA04O_ADC0_DRV3 _L_(4) /**< \brief ADC0 signal: DRV3 on PA04 mux O */ +#define MUX_PA04O_ADC0_DRV3 _L_(14) +#define PINMUX_PA04O_ADC0_DRV3 ((PIN_PA04O_ADC0_DRV3 << 16) | MUX_PA04O_ADC0_DRV3) +#define PORT_PA04O_ADC0_DRV3 (_UL_(1) << 4) +#define PIN_PA06O_ADC0_DRV4 _L_(6) /**< \brief ADC0 signal: DRV4 on PA06 mux O */ +#define MUX_PA06O_ADC0_DRV4 _L_(14) +#define PINMUX_PA06O_ADC0_DRV4 ((PIN_PA06O_ADC0_DRV4 << 16) | MUX_PA06O_ADC0_DRV4) +#define PORT_PA06O_ADC0_DRV4 (_UL_(1) << 6) +#define PIN_PA07O_ADC0_DRV5 _L_(7) /**< \brief ADC0 signal: DRV5 on PA07 mux O */ +#define MUX_PA07O_ADC0_DRV5 _L_(14) +#define PINMUX_PA07O_ADC0_DRV5 ((PIN_PA07O_ADC0_DRV5 << 16) | MUX_PA07O_ADC0_DRV5) +#define PORT_PA07O_ADC0_DRV5 (_UL_(1) << 7) +#define PIN_PA08O_ADC0_DRV6 _L_(8) /**< \brief ADC0 signal: DRV6 on PA08 mux O */ +#define MUX_PA08O_ADC0_DRV6 _L_(14) +#define PINMUX_PA08O_ADC0_DRV6 ((PIN_PA08O_ADC0_DRV6 << 16) | MUX_PA08O_ADC0_DRV6) +#define PORT_PA08O_ADC0_DRV6 (_UL_(1) << 8) +#define PIN_PA09O_ADC0_DRV7 _L_(9) /**< \brief ADC0 signal: DRV7 on PA09 mux O */ +#define MUX_PA09O_ADC0_DRV7 _L_(14) +#define PINMUX_PA09O_ADC0_DRV7 ((PIN_PA09O_ADC0_DRV7 << 16) | MUX_PA09O_ADC0_DRV7) +#define PORT_PA09O_ADC0_DRV7 (_UL_(1) << 9) +#define PIN_PA10O_ADC0_DRV8 _L_(10) /**< \brief ADC0 signal: DRV8 on PA10 mux O */ +#define MUX_PA10O_ADC0_DRV8 _L_(14) +#define PINMUX_PA10O_ADC0_DRV8 ((PIN_PA10O_ADC0_DRV8 << 16) | MUX_PA10O_ADC0_DRV8) +#define PORT_PA10O_ADC0_DRV8 (_UL_(1) << 10) +#define PIN_PA11O_ADC0_DRV9 _L_(11) /**< \brief ADC0 signal: DRV9 on PA11 mux O */ +#define MUX_PA11O_ADC0_DRV9 _L_(14) +#define PINMUX_PA11O_ADC0_DRV9 ((PIN_PA11O_ADC0_DRV9 << 16) | MUX_PA11O_ADC0_DRV9) +#define PORT_PA11O_ADC0_DRV9 (_UL_(1) << 11) +#define PIN_PA16O_ADC0_DRV10 _L_(16) /**< \brief ADC0 signal: DRV10 on PA16 mux O */ +#define MUX_PA16O_ADC0_DRV10 _L_(14) +#define PINMUX_PA16O_ADC0_DRV10 ((PIN_PA16O_ADC0_DRV10 << 16) | MUX_PA16O_ADC0_DRV10) +#define PORT_PA16O_ADC0_DRV10 (_UL_(1) << 16) +#define PIN_PA17O_ADC0_DRV11 _L_(17) /**< \brief ADC0 signal: DRV11 on PA17 mux O */ +#define MUX_PA17O_ADC0_DRV11 _L_(14) +#define PINMUX_PA17O_ADC0_DRV11 ((PIN_PA17O_ADC0_DRV11 << 16) | MUX_PA17O_ADC0_DRV11) +#define PORT_PA17O_ADC0_DRV11 (_UL_(1) << 17) +#define PIN_PA18O_ADC0_DRV12 _L_(18) /**< \brief ADC0 signal: DRV12 on PA18 mux O */ +#define MUX_PA18O_ADC0_DRV12 _L_(14) +#define PINMUX_PA18O_ADC0_DRV12 ((PIN_PA18O_ADC0_DRV12 << 16) | MUX_PA18O_ADC0_DRV12) +#define PORT_PA18O_ADC0_DRV12 (_UL_(1) << 18) +#define PIN_PA19O_ADC0_DRV13 _L_(19) /**< \brief ADC0 signal: DRV13 on PA19 mux O */ +#define MUX_PA19O_ADC0_DRV13 _L_(14) +#define PINMUX_PA19O_ADC0_DRV13 ((PIN_PA19O_ADC0_DRV13 << 16) | MUX_PA19O_ADC0_DRV13) +#define PORT_PA19O_ADC0_DRV13 (_UL_(1) << 19) +#define PIN_PA20O_ADC0_DRV14 _L_(20) /**< \brief ADC0 signal: DRV14 on PA20 mux O */ +#define MUX_PA20O_ADC0_DRV14 _L_(14) +#define PINMUX_PA20O_ADC0_DRV14 ((PIN_PA20O_ADC0_DRV14 << 16) | MUX_PA20O_ADC0_DRV14) +#define PORT_PA20O_ADC0_DRV14 (_UL_(1) << 20) +#define PIN_PA21O_ADC0_DRV15 _L_(21) /**< \brief ADC0 signal: DRV15 on PA21 mux O */ +#define MUX_PA21O_ADC0_DRV15 _L_(14) +#define PINMUX_PA21O_ADC0_DRV15 ((PIN_PA21O_ADC0_DRV15 << 16) | MUX_PA21O_ADC0_DRV15) +#define PORT_PA21O_ADC0_DRV15 (_UL_(1) << 21) +#define PIN_PA22O_ADC0_DRV16 _L_(22) /**< \brief ADC0 signal: DRV16 on PA22 mux O */ +#define MUX_PA22O_ADC0_DRV16 _L_(14) +#define PINMUX_PA22O_ADC0_DRV16 ((PIN_PA22O_ADC0_DRV16 << 16) | MUX_PA22O_ADC0_DRV16) +#define PORT_PA22O_ADC0_DRV16 (_UL_(1) << 22) +#define PIN_PA23O_ADC0_DRV17 _L_(23) /**< \brief ADC0 signal: DRV17 on PA23 mux O */ +#define MUX_PA23O_ADC0_DRV17 _L_(14) +#define PINMUX_PA23O_ADC0_DRV17 ((PIN_PA23O_ADC0_DRV17 << 16) | MUX_PA23O_ADC0_DRV17) +#define PORT_PA23O_ADC0_DRV17 (_UL_(1) << 23) +#define PIN_PA27O_ADC0_DRV18 _L_(27) /**< \brief ADC0 signal: DRV18 on PA27 mux O */ +#define MUX_PA27O_ADC0_DRV18 _L_(14) +#define PINMUX_PA27O_ADC0_DRV18 ((PIN_PA27O_ADC0_DRV18 << 16) | MUX_PA27O_ADC0_DRV18) +#define PORT_PA27O_ADC0_DRV18 (_UL_(1) << 27) +#define PIN_PA30O_ADC0_DRV19 _L_(30) /**< \brief ADC0 signal: DRV19 on PA30 mux O */ +#define MUX_PA30O_ADC0_DRV19 _L_(14) +#define PINMUX_PA30O_ADC0_DRV19 ((PIN_PA30O_ADC0_DRV19 << 16) | MUX_PA30O_ADC0_DRV19) +#define PORT_PA30O_ADC0_DRV19 (_UL_(1) << 30) +#define PIN_PB02O_ADC0_DRV20 _L_(34) /**< \brief ADC0 signal: DRV20 on PB02 mux O */ +#define MUX_PB02O_ADC0_DRV20 _L_(14) +#define PINMUX_PB02O_ADC0_DRV20 ((PIN_PB02O_ADC0_DRV20 << 16) | MUX_PB02O_ADC0_DRV20) +#define PORT_PB02O_ADC0_DRV20 (_UL_(1) << 2) +#define PIN_PB03O_ADC0_DRV21 _L_(35) /**< \brief ADC0 signal: DRV21 on PB03 mux O */ +#define MUX_PB03O_ADC0_DRV21 _L_(14) +#define PINMUX_PB03O_ADC0_DRV21 ((PIN_PB03O_ADC0_DRV21 << 16) | MUX_PB03O_ADC0_DRV21) +#define PORT_PB03O_ADC0_DRV21 (_UL_(1) << 3) +#define PIN_PB04O_ADC0_DRV22 _L_(36) /**< \brief ADC0 signal: DRV22 on PB04 mux O */ +#define MUX_PB04O_ADC0_DRV22 _L_(14) +#define PINMUX_PB04O_ADC0_DRV22 ((PIN_PB04O_ADC0_DRV22 << 16) | MUX_PB04O_ADC0_DRV22) +#define PORT_PB04O_ADC0_DRV22 (_UL_(1) << 4) +#define PIN_PB05O_ADC0_DRV23 _L_(37) /**< \brief ADC0 signal: DRV23 on PB05 mux O */ +#define MUX_PB05O_ADC0_DRV23 _L_(14) +#define PINMUX_PB05O_ADC0_DRV23 ((PIN_PB05O_ADC0_DRV23 << 16) | MUX_PB05O_ADC0_DRV23) +#define PORT_PB05O_ADC0_DRV23 (_UL_(1) << 5) +#define PIN_PB06O_ADC0_DRV24 _L_(38) /**< \brief ADC0 signal: DRV24 on PB06 mux O */ +#define MUX_PB06O_ADC0_DRV24 _L_(14) +#define PINMUX_PB06O_ADC0_DRV24 ((PIN_PB06O_ADC0_DRV24 << 16) | MUX_PB06O_ADC0_DRV24) +#define PORT_PB06O_ADC0_DRV24 (_UL_(1) << 6) +#define PIN_PB07O_ADC0_DRV25 _L_(39) /**< \brief ADC0 signal: DRV25 on PB07 mux O */ +#define MUX_PB07O_ADC0_DRV25 _L_(14) +#define PINMUX_PB07O_ADC0_DRV25 ((PIN_PB07O_ADC0_DRV25 << 16) | MUX_PB07O_ADC0_DRV25) +#define PORT_PB07O_ADC0_DRV25 (_UL_(1) << 7) +#define PIN_PB12O_ADC0_DRV26 _L_(44) /**< \brief ADC0 signal: DRV26 on PB12 mux O */ +#define MUX_PB12O_ADC0_DRV26 _L_(14) +#define PINMUX_PB12O_ADC0_DRV26 ((PIN_PB12O_ADC0_DRV26 << 16) | MUX_PB12O_ADC0_DRV26) +#define PORT_PB12O_ADC0_DRV26 (_UL_(1) << 12) +#define PIN_PB13O_ADC0_DRV27 _L_(45) /**< \brief ADC0 signal: DRV27 on PB13 mux O */ +#define MUX_PB13O_ADC0_DRV27 _L_(14) +#define PINMUX_PB13O_ADC0_DRV27 ((PIN_PB13O_ADC0_DRV27 << 16) | MUX_PB13O_ADC0_DRV27) +#define PORT_PB13O_ADC0_DRV27 (_UL_(1) << 13) +#define PIN_PB14O_ADC0_DRV28 _L_(46) /**< \brief ADC0 signal: DRV28 on PB14 mux O */ +#define MUX_PB14O_ADC0_DRV28 _L_(14) +#define PINMUX_PB14O_ADC0_DRV28 ((PIN_PB14O_ADC0_DRV28 << 16) | MUX_PB14O_ADC0_DRV28) +#define PORT_PB14O_ADC0_DRV28 (_UL_(1) << 14) +#define PIN_PB15O_ADC0_DRV29 _L_(47) /**< \brief ADC0 signal: DRV29 on PB15 mux O */ +#define MUX_PB15O_ADC0_DRV29 _L_(14) +#define PINMUX_PB15O_ADC0_DRV29 ((PIN_PB15O_ADC0_DRV29 << 16) | MUX_PB15O_ADC0_DRV29) +#define PORT_PB15O_ADC0_DRV29 (_UL_(1) << 15) +#define PIN_PB00O_ADC0_DRV30 _L_(32) /**< \brief ADC0 signal: DRV30 on PB00 mux O */ +#define MUX_PB00O_ADC0_DRV30 _L_(14) +#define PINMUX_PB00O_ADC0_DRV30 ((PIN_PB00O_ADC0_DRV30 << 16) | MUX_PB00O_ADC0_DRV30) +#define PORT_PB00O_ADC0_DRV30 (_UL_(1) << 0) +#define PIN_PB01O_ADC0_DRV31 _L_(33) /**< \brief ADC0 signal: DRV31 on PB01 mux O */ +#define MUX_PB01O_ADC0_DRV31 _L_(14) +#define PINMUX_PB01O_ADC0_DRV31 ((PIN_PB01O_ADC0_DRV31 << 16) | MUX_PB01O_ADC0_DRV31) +#define PORT_PB01O_ADC0_DRV31 (_UL_(1) << 1) +#define PIN_PA03B_ADC0_PTCXY0 _L_(3) /**< \brief ADC0 signal: PTCXY0 on PA03 mux B */ +#define MUX_PA03B_ADC0_PTCXY0 _L_(1) +#define PINMUX_PA03B_ADC0_PTCXY0 ((PIN_PA03B_ADC0_PTCXY0 << 16) | MUX_PA03B_ADC0_PTCXY0) +#define PORT_PA03B_ADC0_PTCXY0 (_UL_(1) << 3) +#define PIN_PB08B_ADC0_PTCXY1 _L_(40) /**< \brief ADC0 signal: PTCXY1 on PB08 mux B */ +#define MUX_PB08B_ADC0_PTCXY1 _L_(1) +#define PINMUX_PB08B_ADC0_PTCXY1 ((PIN_PB08B_ADC0_PTCXY1 << 16) | MUX_PB08B_ADC0_PTCXY1) +#define PORT_PB08B_ADC0_PTCXY1 (_UL_(1) << 8) +#define PIN_PB09B_ADC0_PTCXY2 _L_(41) /**< \brief ADC0 signal: PTCXY2 on PB09 mux B */ +#define MUX_PB09B_ADC0_PTCXY2 _L_(1) +#define PINMUX_PB09B_ADC0_PTCXY2 ((PIN_PB09B_ADC0_PTCXY2 << 16) | MUX_PB09B_ADC0_PTCXY2) +#define PORT_PB09B_ADC0_PTCXY2 (_UL_(1) << 9) +#define PIN_PA04B_ADC0_PTCXY3 _L_(4) /**< \brief ADC0 signal: PTCXY3 on PA04 mux B */ +#define MUX_PA04B_ADC0_PTCXY3 _L_(1) +#define PINMUX_PA04B_ADC0_PTCXY3 ((PIN_PA04B_ADC0_PTCXY3 << 16) | MUX_PA04B_ADC0_PTCXY3) +#define PORT_PA04B_ADC0_PTCXY3 (_UL_(1) << 4) +#define PIN_PA06B_ADC0_PTCXY4 _L_(6) /**< \brief ADC0 signal: PTCXY4 on PA06 mux B */ +#define MUX_PA06B_ADC0_PTCXY4 _L_(1) +#define PINMUX_PA06B_ADC0_PTCXY4 ((PIN_PA06B_ADC0_PTCXY4 << 16) | MUX_PA06B_ADC0_PTCXY4) +#define PORT_PA06B_ADC0_PTCXY4 (_UL_(1) << 6) +#define PIN_PA07B_ADC0_PTCXY5 _L_(7) /**< \brief ADC0 signal: PTCXY5 on PA07 mux B */ +#define MUX_PA07B_ADC0_PTCXY5 _L_(1) +#define PINMUX_PA07B_ADC0_PTCXY5 ((PIN_PA07B_ADC0_PTCXY5 << 16) | MUX_PA07B_ADC0_PTCXY5) +#define PORT_PA07B_ADC0_PTCXY5 (_UL_(1) << 7) +#define PIN_PA08B_ADC0_PTCXY6 _L_(8) /**< \brief ADC0 signal: PTCXY6 on PA08 mux B */ +#define MUX_PA08B_ADC0_PTCXY6 _L_(1) +#define PINMUX_PA08B_ADC0_PTCXY6 ((PIN_PA08B_ADC0_PTCXY6 << 16) | MUX_PA08B_ADC0_PTCXY6) +#define PORT_PA08B_ADC0_PTCXY6 (_UL_(1) << 8) +#define PIN_PA09B_ADC0_PTCXY7 _L_(9) /**< \brief ADC0 signal: PTCXY7 on PA09 mux B */ +#define MUX_PA09B_ADC0_PTCXY7 _L_(1) +#define PINMUX_PA09B_ADC0_PTCXY7 ((PIN_PA09B_ADC0_PTCXY7 << 16) | MUX_PA09B_ADC0_PTCXY7) +#define PORT_PA09B_ADC0_PTCXY7 (_UL_(1) << 9) +#define PIN_PA10B_ADC0_PTCXY8 _L_(10) /**< \brief ADC0 signal: PTCXY8 on PA10 mux B */ +#define MUX_PA10B_ADC0_PTCXY8 _L_(1) +#define PINMUX_PA10B_ADC0_PTCXY8 ((PIN_PA10B_ADC0_PTCXY8 << 16) | MUX_PA10B_ADC0_PTCXY8) +#define PORT_PA10B_ADC0_PTCXY8 (_UL_(1) << 10) +#define PIN_PA11B_ADC0_PTCXY9 _L_(11) /**< \brief ADC0 signal: PTCXY9 on PA11 mux B */ +#define MUX_PA11B_ADC0_PTCXY9 _L_(1) +#define PINMUX_PA11B_ADC0_PTCXY9 ((PIN_PA11B_ADC0_PTCXY9 << 16) | MUX_PA11B_ADC0_PTCXY9) +#define PORT_PA11B_ADC0_PTCXY9 (_UL_(1) << 11) +#define PIN_PA16B_ADC0_PTCXY10 _L_(16) /**< \brief ADC0 signal: PTCXY10 on PA16 mux B */ +#define MUX_PA16B_ADC0_PTCXY10 _L_(1) +#define PINMUX_PA16B_ADC0_PTCXY10 ((PIN_PA16B_ADC0_PTCXY10 << 16) | MUX_PA16B_ADC0_PTCXY10) +#define PORT_PA16B_ADC0_PTCXY10 (_UL_(1) << 16) +#define PIN_PA17B_ADC0_PTCXY11 _L_(17) /**< \brief ADC0 signal: PTCXY11 on PA17 mux B */ +#define MUX_PA17B_ADC0_PTCXY11 _L_(1) +#define PINMUX_PA17B_ADC0_PTCXY11 ((PIN_PA17B_ADC0_PTCXY11 << 16) | MUX_PA17B_ADC0_PTCXY11) +#define PORT_PA17B_ADC0_PTCXY11 (_UL_(1) << 17) +#define PIN_PA18B_ADC0_PTCXY12 _L_(18) /**< \brief ADC0 signal: PTCXY12 on PA18 mux B */ +#define MUX_PA18B_ADC0_PTCXY12 _L_(1) +#define PINMUX_PA18B_ADC0_PTCXY12 ((PIN_PA18B_ADC0_PTCXY12 << 16) | MUX_PA18B_ADC0_PTCXY12) +#define PORT_PA18B_ADC0_PTCXY12 (_UL_(1) << 18) +#define PIN_PA19B_ADC0_PTCXY13 _L_(19) /**< \brief ADC0 signal: PTCXY13 on PA19 mux B */ +#define MUX_PA19B_ADC0_PTCXY13 _L_(1) +#define PINMUX_PA19B_ADC0_PTCXY13 ((PIN_PA19B_ADC0_PTCXY13 << 16) | MUX_PA19B_ADC0_PTCXY13) +#define PORT_PA19B_ADC0_PTCXY13 (_UL_(1) << 19) +#define PIN_PA20B_ADC0_PTCXY14 _L_(20) /**< \brief ADC0 signal: PTCXY14 on PA20 mux B */ +#define MUX_PA20B_ADC0_PTCXY14 _L_(1) +#define PINMUX_PA20B_ADC0_PTCXY14 ((PIN_PA20B_ADC0_PTCXY14 << 16) | MUX_PA20B_ADC0_PTCXY14) +#define PORT_PA20B_ADC0_PTCXY14 (_UL_(1) << 20) +#define PIN_PA21B_ADC0_PTCXY15 _L_(21) /**< \brief ADC0 signal: PTCXY15 on PA21 mux B */ +#define MUX_PA21B_ADC0_PTCXY15 _L_(1) +#define PINMUX_PA21B_ADC0_PTCXY15 ((PIN_PA21B_ADC0_PTCXY15 << 16) | MUX_PA21B_ADC0_PTCXY15) +#define PORT_PA21B_ADC0_PTCXY15 (_UL_(1) << 21) +#define PIN_PA22B_ADC0_PTCXY16 _L_(22) /**< \brief ADC0 signal: PTCXY16 on PA22 mux B */ +#define MUX_PA22B_ADC0_PTCXY16 _L_(1) +#define PINMUX_PA22B_ADC0_PTCXY16 ((PIN_PA22B_ADC0_PTCXY16 << 16) | MUX_PA22B_ADC0_PTCXY16) +#define PORT_PA22B_ADC0_PTCXY16 (_UL_(1) << 22) +#define PIN_PA23B_ADC0_PTCXY17 _L_(23) /**< \brief ADC0 signal: PTCXY17 on PA23 mux B */ +#define MUX_PA23B_ADC0_PTCXY17 _L_(1) +#define PINMUX_PA23B_ADC0_PTCXY17 ((PIN_PA23B_ADC0_PTCXY17 << 16) | MUX_PA23B_ADC0_PTCXY17) +#define PORT_PA23B_ADC0_PTCXY17 (_UL_(1) << 23) +#define PIN_PA27B_ADC0_PTCXY18 _L_(27) /**< \brief ADC0 signal: PTCXY18 on PA27 mux B */ +#define MUX_PA27B_ADC0_PTCXY18 _L_(1) +#define PINMUX_PA27B_ADC0_PTCXY18 ((PIN_PA27B_ADC0_PTCXY18 << 16) | MUX_PA27B_ADC0_PTCXY18) +#define PORT_PA27B_ADC0_PTCXY18 (_UL_(1) << 27) +#define PIN_PA30B_ADC0_PTCXY19 _L_(30) /**< \brief ADC0 signal: PTCXY19 on PA30 mux B */ +#define MUX_PA30B_ADC0_PTCXY19 _L_(1) +#define PINMUX_PA30B_ADC0_PTCXY19 ((PIN_PA30B_ADC0_PTCXY19 << 16) | MUX_PA30B_ADC0_PTCXY19) +#define PORT_PA30B_ADC0_PTCXY19 (_UL_(1) << 30) +#define PIN_PB02B_ADC0_PTCXY20 _L_(34) /**< \brief ADC0 signal: PTCXY20 on PB02 mux B */ +#define MUX_PB02B_ADC0_PTCXY20 _L_(1) +#define PINMUX_PB02B_ADC0_PTCXY20 ((PIN_PB02B_ADC0_PTCXY20 << 16) | MUX_PB02B_ADC0_PTCXY20) +#define PORT_PB02B_ADC0_PTCXY20 (_UL_(1) << 2) +#define PIN_PB03B_ADC0_PTCXY21 _L_(35) /**< \brief ADC0 signal: PTCXY21 on PB03 mux B */ +#define MUX_PB03B_ADC0_PTCXY21 _L_(1) +#define PINMUX_PB03B_ADC0_PTCXY21 ((PIN_PB03B_ADC0_PTCXY21 << 16) | MUX_PB03B_ADC0_PTCXY21) +#define PORT_PB03B_ADC0_PTCXY21 (_UL_(1) << 3) +#define PIN_PB04B_ADC0_PTCXY22 _L_(36) /**< \brief ADC0 signal: PTCXY22 on PB04 mux B */ +#define MUX_PB04B_ADC0_PTCXY22 _L_(1) +#define PINMUX_PB04B_ADC0_PTCXY22 ((PIN_PB04B_ADC0_PTCXY22 << 16) | MUX_PB04B_ADC0_PTCXY22) +#define PORT_PB04B_ADC0_PTCXY22 (_UL_(1) << 4) +#define PIN_PB05B_ADC0_PTCXY23 _L_(37) /**< \brief ADC0 signal: PTCXY23 on PB05 mux B */ +#define MUX_PB05B_ADC0_PTCXY23 _L_(1) +#define PINMUX_PB05B_ADC0_PTCXY23 ((PIN_PB05B_ADC0_PTCXY23 << 16) | MUX_PB05B_ADC0_PTCXY23) +#define PORT_PB05B_ADC0_PTCXY23 (_UL_(1) << 5) +#define PIN_PB06B_ADC0_PTCXY24 _L_(38) /**< \brief ADC0 signal: PTCXY24 on PB06 mux B */ +#define MUX_PB06B_ADC0_PTCXY24 _L_(1) +#define PINMUX_PB06B_ADC0_PTCXY24 ((PIN_PB06B_ADC0_PTCXY24 << 16) | MUX_PB06B_ADC0_PTCXY24) +#define PORT_PB06B_ADC0_PTCXY24 (_UL_(1) << 6) +#define PIN_PB07B_ADC0_PTCXY25 _L_(39) /**< \brief ADC0 signal: PTCXY25 on PB07 mux B */ +#define MUX_PB07B_ADC0_PTCXY25 _L_(1) +#define PINMUX_PB07B_ADC0_PTCXY25 ((PIN_PB07B_ADC0_PTCXY25 << 16) | MUX_PB07B_ADC0_PTCXY25) +#define PORT_PB07B_ADC0_PTCXY25 (_UL_(1) << 7) +#define PIN_PB12B_ADC0_PTCXY26 _L_(44) /**< \brief ADC0 signal: PTCXY26 on PB12 mux B */ +#define MUX_PB12B_ADC0_PTCXY26 _L_(1) +#define PINMUX_PB12B_ADC0_PTCXY26 ((PIN_PB12B_ADC0_PTCXY26 << 16) | MUX_PB12B_ADC0_PTCXY26) +#define PORT_PB12B_ADC0_PTCXY26 (_UL_(1) << 12) +#define PIN_PB13B_ADC0_PTCXY27 _L_(45) /**< \brief ADC0 signal: PTCXY27 on PB13 mux B */ +#define MUX_PB13B_ADC0_PTCXY27 _L_(1) +#define PINMUX_PB13B_ADC0_PTCXY27 ((PIN_PB13B_ADC0_PTCXY27 << 16) | MUX_PB13B_ADC0_PTCXY27) +#define PORT_PB13B_ADC0_PTCXY27 (_UL_(1) << 13) +#define PIN_PB14B_ADC0_PTCXY28 _L_(46) /**< \brief ADC0 signal: PTCXY28 on PB14 mux B */ +#define MUX_PB14B_ADC0_PTCXY28 _L_(1) +#define PINMUX_PB14B_ADC0_PTCXY28 ((PIN_PB14B_ADC0_PTCXY28 << 16) | MUX_PB14B_ADC0_PTCXY28) +#define PORT_PB14B_ADC0_PTCXY28 (_UL_(1) << 14) +#define PIN_PB15B_ADC0_PTCXY29 _L_(47) /**< \brief ADC0 signal: PTCXY29 on PB15 mux B */ +#define MUX_PB15B_ADC0_PTCXY29 _L_(1) +#define PINMUX_PB15B_ADC0_PTCXY29 ((PIN_PB15B_ADC0_PTCXY29 << 16) | MUX_PB15B_ADC0_PTCXY29) +#define PORT_PB15B_ADC0_PTCXY29 (_UL_(1) << 15) +#define PIN_PB00B_ADC0_PTCXY30 _L_(32) /**< \brief ADC0 signal: PTCXY30 on PB00 mux B */ +#define MUX_PB00B_ADC0_PTCXY30 _L_(1) +#define PINMUX_PB00B_ADC0_PTCXY30 ((PIN_PB00B_ADC0_PTCXY30 << 16) | MUX_PB00B_ADC0_PTCXY30) +#define PORT_PB00B_ADC0_PTCXY30 (_UL_(1) << 0) +#define PIN_PB01B_ADC0_PTCXY31 _L_(33) /**< \brief ADC0 signal: PTCXY31 on PB01 mux B */ +#define MUX_PB01B_ADC0_PTCXY31 _L_(1) +#define PINMUX_PB01B_ADC0_PTCXY31 ((PIN_PB01B_ADC0_PTCXY31 << 16) | MUX_PB01B_ADC0_PTCXY31) +#define PORT_PB01B_ADC0_PTCXY31 (_UL_(1) << 1) +/* ========== PORT definition for ADC1 peripheral ========== */ +#define PIN_PB08B_ADC1_AIN0 _L_(40) /**< \brief ADC1 signal: AIN0 on PB08 mux B */ +#define MUX_PB08B_ADC1_AIN0 _L_(1) +#define PINMUX_PB08B_ADC1_AIN0 ((PIN_PB08B_ADC1_AIN0 << 16) | MUX_PB08B_ADC1_AIN0) +#define PORT_PB08B_ADC1_AIN0 (_UL_(1) << 8) +#define PIN_PB09B_ADC1_AIN1 _L_(41) /**< \brief ADC1 signal: AIN1 on PB09 mux B */ +#define MUX_PB09B_ADC1_AIN1 _L_(1) +#define PINMUX_PB09B_ADC1_AIN1 ((PIN_PB09B_ADC1_AIN1 << 16) | MUX_PB09B_ADC1_AIN1) +#define PORT_PB09B_ADC1_AIN1 (_UL_(1) << 9) +#define PIN_PA08B_ADC1_AIN2 _L_(8) /**< \brief ADC1 signal: AIN2 on PA08 mux B */ +#define MUX_PA08B_ADC1_AIN2 _L_(1) +#define PINMUX_PA08B_ADC1_AIN2 ((PIN_PA08B_ADC1_AIN2 << 16) | MUX_PA08B_ADC1_AIN2) +#define PORT_PA08B_ADC1_AIN2 (_UL_(1) << 8) +#define PIN_PA09B_ADC1_AIN3 _L_(9) /**< \brief ADC1 signal: AIN3 on PA09 mux B */ +#define MUX_PA09B_ADC1_AIN3 _L_(1) +#define PINMUX_PA09B_ADC1_AIN3 ((PIN_PA09B_ADC1_AIN3 << 16) | MUX_PA09B_ADC1_AIN3) +#define PORT_PA09B_ADC1_AIN3 (_UL_(1) << 9) +#define PIN_PC02B_ADC1_AIN4 _L_(66) /**< \brief ADC1 signal: AIN4 on PC02 mux B */ +#define MUX_PC02B_ADC1_AIN4 _L_(1) +#define PINMUX_PC02B_ADC1_AIN4 ((PIN_PC02B_ADC1_AIN4 << 16) | MUX_PC02B_ADC1_AIN4) +#define PORT_PC02B_ADC1_AIN4 (_UL_(1) << 2) +#define PIN_PC03B_ADC1_AIN5 _L_(67) /**< \brief ADC1 signal: AIN5 on PC03 mux B */ +#define MUX_PC03B_ADC1_AIN5 _L_(1) +#define PINMUX_PC03B_ADC1_AIN5 ((PIN_PC03B_ADC1_AIN5 << 16) | MUX_PC03B_ADC1_AIN5) +#define PORT_PC03B_ADC1_AIN5 (_UL_(1) << 3) +#define PIN_PB04B_ADC1_AIN6 _L_(36) /**< \brief ADC1 signal: AIN6 on PB04 mux B */ +#define MUX_PB04B_ADC1_AIN6 _L_(1) +#define PINMUX_PB04B_ADC1_AIN6 ((PIN_PB04B_ADC1_AIN6 << 16) | MUX_PB04B_ADC1_AIN6) +#define PORT_PB04B_ADC1_AIN6 (_UL_(1) << 4) +#define PIN_PB05B_ADC1_AIN7 _L_(37) /**< \brief ADC1 signal: AIN7 on PB05 mux B */ +#define MUX_PB05B_ADC1_AIN7 _L_(1) +#define PINMUX_PB05B_ADC1_AIN7 ((PIN_PB05B_ADC1_AIN7 << 16) | MUX_PB05B_ADC1_AIN7) +#define PORT_PB05B_ADC1_AIN7 (_UL_(1) << 5) +#define PIN_PB06B_ADC1_AIN8 _L_(38) /**< \brief ADC1 signal: AIN8 on PB06 mux B */ +#define MUX_PB06B_ADC1_AIN8 _L_(1) +#define PINMUX_PB06B_ADC1_AIN8 ((PIN_PB06B_ADC1_AIN8 << 16) | MUX_PB06B_ADC1_AIN8) +#define PORT_PB06B_ADC1_AIN8 (_UL_(1) << 6) +#define PIN_PB07B_ADC1_AIN9 _L_(39) /**< \brief ADC1 signal: AIN9 on PB07 mux B */ +#define MUX_PB07B_ADC1_AIN9 _L_(1) +#define PINMUX_PB07B_ADC1_AIN9 ((PIN_PB07B_ADC1_AIN9 << 16) | MUX_PB07B_ADC1_AIN9) +#define PORT_PB07B_ADC1_AIN9 (_UL_(1) << 7) +#define PIN_PC00B_ADC1_AIN10 _L_(64) /**< \brief ADC1 signal: AIN10 on PC00 mux B */ +#define MUX_PC00B_ADC1_AIN10 _L_(1) +#define PINMUX_PC00B_ADC1_AIN10 ((PIN_PC00B_ADC1_AIN10 << 16) | MUX_PC00B_ADC1_AIN10) +#define PORT_PC00B_ADC1_AIN10 (_UL_(1) << 0) +#define PIN_PC01B_ADC1_AIN11 _L_(65) /**< \brief ADC1 signal: AIN11 on PC01 mux B */ +#define MUX_PC01B_ADC1_AIN11 _L_(1) +#define PINMUX_PC01B_ADC1_AIN11 ((PIN_PC01B_ADC1_AIN11 << 16) | MUX_PC01B_ADC1_AIN11) +#define PORT_PC01B_ADC1_AIN11 (_UL_(1) << 1) +#define PIN_PC30B_ADC1_AIN12 _L_(94) /**< \brief ADC1 signal: AIN12 on PC30 mux B */ +#define MUX_PC30B_ADC1_AIN12 _L_(1) +#define PINMUX_PC30B_ADC1_AIN12 ((PIN_PC30B_ADC1_AIN12 << 16) | MUX_PC30B_ADC1_AIN12) +#define PORT_PC30B_ADC1_AIN12 (_UL_(1) << 30) +#define PIN_PC31B_ADC1_AIN13 _L_(95) /**< \brief ADC1 signal: AIN13 on PC31 mux B */ +#define MUX_PC31B_ADC1_AIN13 _L_(1) +#define PINMUX_PC31B_ADC1_AIN13 ((PIN_PC31B_ADC1_AIN13 << 16) | MUX_PC31B_ADC1_AIN13) +#define PORT_PC31B_ADC1_AIN13 (_UL_(1) << 31) +#define PIN_PD00B_ADC1_AIN14 _L_(96) /**< \brief ADC1 signal: AIN14 on PD00 mux B */ +#define MUX_PD00B_ADC1_AIN14 _L_(1) +#define PINMUX_PD00B_ADC1_AIN14 ((PIN_PD00B_ADC1_AIN14 << 16) | MUX_PD00B_ADC1_AIN14) +#define PORT_PD00B_ADC1_AIN14 (_UL_(1) << 0) +#define PIN_PD01B_ADC1_AIN15 _L_(97) /**< \brief ADC1 signal: AIN15 on PD01 mux B */ +#define MUX_PD01B_ADC1_AIN15 _L_(1) +#define PINMUX_PD01B_ADC1_AIN15 ((PIN_PD01B_ADC1_AIN15 << 16) | MUX_PD01B_ADC1_AIN15) +#define PORT_PD01B_ADC1_AIN15 (_UL_(1) << 1) +/* ========== PORT definition for DAC peripheral ========== */ +#define PIN_PA02B_DAC_VOUT0 _L_(2) /**< \brief DAC signal: VOUT0 on PA02 mux B */ +#define MUX_PA02B_DAC_VOUT0 _L_(1) +#define PINMUX_PA02B_DAC_VOUT0 ((PIN_PA02B_DAC_VOUT0 << 16) | MUX_PA02B_DAC_VOUT0) +#define PORT_PA02B_DAC_VOUT0 (_UL_(1) << 2) +#define PIN_PA05B_DAC_VOUT1 _L_(5) /**< \brief DAC signal: VOUT1 on PA05 mux B */ +#define MUX_PA05B_DAC_VOUT1 _L_(1) +#define PINMUX_PA05B_DAC_VOUT1 ((PIN_PA05B_DAC_VOUT1 << 16) | MUX_PA05B_DAC_VOUT1) +#define PORT_PA05B_DAC_VOUT1 (_UL_(1) << 5) +/* ========== PORT definition for I2S peripheral ========== */ +#define PIN_PA09J_I2S_FS0 _L_(9) /**< \brief I2S signal: FS0 on PA09 mux J */ +#define MUX_PA09J_I2S_FS0 _L_(9) +#define PINMUX_PA09J_I2S_FS0 ((PIN_PA09J_I2S_FS0 << 16) | MUX_PA09J_I2S_FS0) +#define PORT_PA09J_I2S_FS0 (_UL_(1) << 9) +#define PIN_PA20J_I2S_FS0 _L_(20) /**< \brief I2S signal: FS0 on PA20 mux J */ +#define MUX_PA20J_I2S_FS0 _L_(9) +#define PINMUX_PA20J_I2S_FS0 ((PIN_PA20J_I2S_FS0 << 16) | MUX_PA20J_I2S_FS0) +#define PORT_PA20J_I2S_FS0 (_UL_(1) << 20) +#define PIN_PA23J_I2S_FS1 _L_(23) /**< \brief I2S signal: FS1 on PA23 mux J */ +#define MUX_PA23J_I2S_FS1 _L_(9) +#define PINMUX_PA23J_I2S_FS1 ((PIN_PA23J_I2S_FS1 << 16) | MUX_PA23J_I2S_FS1) +#define PORT_PA23J_I2S_FS1 (_UL_(1) << 23) +#define PIN_PB11J_I2S_FS1 _L_(43) /**< \brief I2S signal: FS1 on PB11 mux J */ +#define MUX_PB11J_I2S_FS1 _L_(9) +#define PINMUX_PB11J_I2S_FS1 ((PIN_PB11J_I2S_FS1 << 16) | MUX_PB11J_I2S_FS1) +#define PORT_PB11J_I2S_FS1 (_UL_(1) << 11) +#define PIN_PA08J_I2S_MCK0 _L_(8) /**< \brief I2S signal: MCK0 on PA08 mux J */ +#define MUX_PA08J_I2S_MCK0 _L_(9) +#define PINMUX_PA08J_I2S_MCK0 ((PIN_PA08J_I2S_MCK0 << 16) | MUX_PA08J_I2S_MCK0) +#define PORT_PA08J_I2S_MCK0 (_UL_(1) << 8) +#define PIN_PB17J_I2S_MCK0 _L_(49) /**< \brief I2S signal: MCK0 on PB17 mux J */ +#define MUX_PB17J_I2S_MCK0 _L_(9) +#define PINMUX_PB17J_I2S_MCK0 ((PIN_PB17J_I2S_MCK0 << 16) | MUX_PB17J_I2S_MCK0) +#define PORT_PB17J_I2S_MCK0 (_UL_(1) << 17) +#define PIN_PB29J_I2S_MCK1 _L_(61) /**< \brief I2S signal: MCK1 on PB29 mux J */ +#define MUX_PB29J_I2S_MCK1 _L_(9) +#define PINMUX_PB29J_I2S_MCK1 ((PIN_PB29J_I2S_MCK1 << 16) | MUX_PB29J_I2S_MCK1) +#define PORT_PB29J_I2S_MCK1 (_UL_(1) << 29) +#define PIN_PB13J_I2S_MCK1 _L_(45) /**< \brief I2S signal: MCK1 on PB13 mux J */ +#define MUX_PB13J_I2S_MCK1 _L_(9) +#define PINMUX_PB13J_I2S_MCK1 ((PIN_PB13J_I2S_MCK1 << 16) | MUX_PB13J_I2S_MCK1) +#define PORT_PB13J_I2S_MCK1 (_UL_(1) << 13) +#define PIN_PA10J_I2S_SCK0 _L_(10) /**< \brief I2S signal: SCK0 on PA10 mux J */ +#define MUX_PA10J_I2S_SCK0 _L_(9) +#define PINMUX_PA10J_I2S_SCK0 ((PIN_PA10J_I2S_SCK0 << 16) | MUX_PA10J_I2S_SCK0) +#define PORT_PA10J_I2S_SCK0 (_UL_(1) << 10) +#define PIN_PB16J_I2S_SCK0 _L_(48) /**< \brief I2S signal: SCK0 on PB16 mux J */ +#define MUX_PB16J_I2S_SCK0 _L_(9) +#define PINMUX_PB16J_I2S_SCK0 ((PIN_PB16J_I2S_SCK0 << 16) | MUX_PB16J_I2S_SCK0) +#define PORT_PB16J_I2S_SCK0 (_UL_(1) << 16) +#define PIN_PB28J_I2S_SCK1 _L_(60) /**< \brief I2S signal: SCK1 on PB28 mux J */ +#define MUX_PB28J_I2S_SCK1 _L_(9) +#define PINMUX_PB28J_I2S_SCK1 ((PIN_PB28J_I2S_SCK1 << 16) | MUX_PB28J_I2S_SCK1) +#define PORT_PB28J_I2S_SCK1 (_UL_(1) << 28) +#define PIN_PB12J_I2S_SCK1 _L_(44) /**< \brief I2S signal: SCK1 on PB12 mux J */ +#define MUX_PB12J_I2S_SCK1 _L_(9) +#define PINMUX_PB12J_I2S_SCK1 ((PIN_PB12J_I2S_SCK1 << 16) | MUX_PB12J_I2S_SCK1) +#define PORT_PB12J_I2S_SCK1 (_UL_(1) << 12) +#define PIN_PA22J_I2S_SDI _L_(22) /**< \brief I2S signal: SDI on PA22 mux J */ +#define MUX_PA22J_I2S_SDI _L_(9) +#define PINMUX_PA22J_I2S_SDI ((PIN_PA22J_I2S_SDI << 16) | MUX_PA22J_I2S_SDI) +#define PORT_PA22J_I2S_SDI (_UL_(1) << 22) +#define PIN_PB10J_I2S_SDI _L_(42) /**< \brief I2S signal: SDI on PB10 mux J */ +#define MUX_PB10J_I2S_SDI _L_(9) +#define PINMUX_PB10J_I2S_SDI ((PIN_PB10J_I2S_SDI << 16) | MUX_PB10J_I2S_SDI) +#define PORT_PB10J_I2S_SDI (_UL_(1) << 10) +#define PIN_PA11J_I2S_SDO _L_(11) /**< \brief I2S signal: SDO on PA11 mux J */ +#define MUX_PA11J_I2S_SDO _L_(9) +#define PINMUX_PA11J_I2S_SDO ((PIN_PA11J_I2S_SDO << 16) | MUX_PA11J_I2S_SDO) +#define PORT_PA11J_I2S_SDO (_UL_(1) << 11) +#define PIN_PA21J_I2S_SDO _L_(21) /**< \brief I2S signal: SDO on PA21 mux J */ +#define MUX_PA21J_I2S_SDO _L_(9) +#define PINMUX_PA21J_I2S_SDO ((PIN_PA21J_I2S_SDO << 16) | MUX_PA21J_I2S_SDO) +#define PORT_PA21J_I2S_SDO (_UL_(1) << 21) +/* ========== PORT definition for PCC peripheral ========== */ +#define PIN_PA14K_PCC_CLK _L_(14) /**< \brief PCC signal: CLK on PA14 mux K */ +#define MUX_PA14K_PCC_CLK _L_(10) +#define PINMUX_PA14K_PCC_CLK ((PIN_PA14K_PCC_CLK << 16) | MUX_PA14K_PCC_CLK) +#define PORT_PA14K_PCC_CLK (_UL_(1) << 14) +#define PIN_PA16K_PCC_DATA0 _L_(16) /**< \brief PCC signal: DATA0 on PA16 mux K */ +#define MUX_PA16K_PCC_DATA0 _L_(10) +#define PINMUX_PA16K_PCC_DATA0 ((PIN_PA16K_PCC_DATA0 << 16) | MUX_PA16K_PCC_DATA0) +#define PORT_PA16K_PCC_DATA0 (_UL_(1) << 16) +#define PIN_PA17K_PCC_DATA1 _L_(17) /**< \brief PCC signal: DATA1 on PA17 mux K */ +#define MUX_PA17K_PCC_DATA1 _L_(10) +#define PINMUX_PA17K_PCC_DATA1 ((PIN_PA17K_PCC_DATA1 << 16) | MUX_PA17K_PCC_DATA1) +#define PORT_PA17K_PCC_DATA1 (_UL_(1) << 17) +#define PIN_PA18K_PCC_DATA2 _L_(18) /**< \brief PCC signal: DATA2 on PA18 mux K */ +#define MUX_PA18K_PCC_DATA2 _L_(10) +#define PINMUX_PA18K_PCC_DATA2 ((PIN_PA18K_PCC_DATA2 << 16) | MUX_PA18K_PCC_DATA2) +#define PORT_PA18K_PCC_DATA2 (_UL_(1) << 18) +#define PIN_PA19K_PCC_DATA3 _L_(19) /**< \brief PCC signal: DATA3 on PA19 mux K */ +#define MUX_PA19K_PCC_DATA3 _L_(10) +#define PINMUX_PA19K_PCC_DATA3 ((PIN_PA19K_PCC_DATA3 << 16) | MUX_PA19K_PCC_DATA3) +#define PORT_PA19K_PCC_DATA3 (_UL_(1) << 19) +#define PIN_PA20K_PCC_DATA4 _L_(20) /**< \brief PCC signal: DATA4 on PA20 mux K */ +#define MUX_PA20K_PCC_DATA4 _L_(10) +#define PINMUX_PA20K_PCC_DATA4 ((PIN_PA20K_PCC_DATA4 << 16) | MUX_PA20K_PCC_DATA4) +#define PORT_PA20K_PCC_DATA4 (_UL_(1) << 20) +#define PIN_PA21K_PCC_DATA5 _L_(21) /**< \brief PCC signal: DATA5 on PA21 mux K */ +#define MUX_PA21K_PCC_DATA5 _L_(10) +#define PINMUX_PA21K_PCC_DATA5 ((PIN_PA21K_PCC_DATA5 << 16) | MUX_PA21K_PCC_DATA5) +#define PORT_PA21K_PCC_DATA5 (_UL_(1) << 21) +#define PIN_PA22K_PCC_DATA6 _L_(22) /**< \brief PCC signal: DATA6 on PA22 mux K */ +#define MUX_PA22K_PCC_DATA6 _L_(10) +#define PINMUX_PA22K_PCC_DATA6 ((PIN_PA22K_PCC_DATA6 << 16) | MUX_PA22K_PCC_DATA6) +#define PORT_PA22K_PCC_DATA6 (_UL_(1) << 22) +#define PIN_PA23K_PCC_DATA7 _L_(23) /**< \brief PCC signal: DATA7 on PA23 mux K */ +#define MUX_PA23K_PCC_DATA7 _L_(10) +#define PINMUX_PA23K_PCC_DATA7 ((PIN_PA23K_PCC_DATA7 << 16) | MUX_PA23K_PCC_DATA7) +#define PORT_PA23K_PCC_DATA7 (_UL_(1) << 23) +#define PIN_PB14K_PCC_DATA8 _L_(46) /**< \brief PCC signal: DATA8 on PB14 mux K */ +#define MUX_PB14K_PCC_DATA8 _L_(10) +#define PINMUX_PB14K_PCC_DATA8 ((PIN_PB14K_PCC_DATA8 << 16) | MUX_PB14K_PCC_DATA8) +#define PORT_PB14K_PCC_DATA8 (_UL_(1) << 14) +#define PIN_PB15K_PCC_DATA9 _L_(47) /**< \brief PCC signal: DATA9 on PB15 mux K */ +#define MUX_PB15K_PCC_DATA9 _L_(10) +#define PINMUX_PB15K_PCC_DATA9 ((PIN_PB15K_PCC_DATA9 << 16) | MUX_PB15K_PCC_DATA9) +#define PORT_PB15K_PCC_DATA9 (_UL_(1) << 15) +#define PIN_PC12K_PCC_DATA10 _L_(76) /**< \brief PCC signal: DATA10 on PC12 mux K */ +#define MUX_PC12K_PCC_DATA10 _L_(10) +#define PINMUX_PC12K_PCC_DATA10 ((PIN_PC12K_PCC_DATA10 << 16) | MUX_PC12K_PCC_DATA10) +#define PORT_PC12K_PCC_DATA10 (_UL_(1) << 12) +#define PIN_PC13K_PCC_DATA11 _L_(77) /**< \brief PCC signal: DATA11 on PC13 mux K */ +#define MUX_PC13K_PCC_DATA11 _L_(10) +#define PINMUX_PC13K_PCC_DATA11 ((PIN_PC13K_PCC_DATA11 << 16) | MUX_PC13K_PCC_DATA11) +#define PORT_PC13K_PCC_DATA11 (_UL_(1) << 13) +#define PIN_PC14K_PCC_DATA12 _L_(78) /**< \brief PCC signal: DATA12 on PC14 mux K */ +#define MUX_PC14K_PCC_DATA12 _L_(10) +#define PINMUX_PC14K_PCC_DATA12 ((PIN_PC14K_PCC_DATA12 << 16) | MUX_PC14K_PCC_DATA12) +#define PORT_PC14K_PCC_DATA12 (_UL_(1) << 14) +#define PIN_PC15K_PCC_DATA13 _L_(79) /**< \brief PCC signal: DATA13 on PC15 mux K */ +#define MUX_PC15K_PCC_DATA13 _L_(10) +#define PINMUX_PC15K_PCC_DATA13 ((PIN_PC15K_PCC_DATA13 << 16) | MUX_PC15K_PCC_DATA13) +#define PORT_PC15K_PCC_DATA13 (_UL_(1) << 15) +#define PIN_PA12K_PCC_DEN1 _L_(12) /**< \brief PCC signal: DEN1 on PA12 mux K */ +#define MUX_PA12K_PCC_DEN1 _L_(10) +#define PINMUX_PA12K_PCC_DEN1 ((PIN_PA12K_PCC_DEN1 << 16) | MUX_PA12K_PCC_DEN1) +#define PORT_PA12K_PCC_DEN1 (_UL_(1) << 12) +#define PIN_PA13K_PCC_DEN2 _L_(13) /**< \brief PCC signal: DEN2 on PA13 mux K */ +#define MUX_PA13K_PCC_DEN2 _L_(10) +#define PINMUX_PA13K_PCC_DEN2 ((PIN_PA13K_PCC_DEN2 << 16) | MUX_PA13K_PCC_DEN2) +#define PORT_PA13K_PCC_DEN2 (_UL_(1) << 13) +/* ========== PORT definition for SDHC0 peripheral ========== */ +#define PIN_PA06I_SDHC0_SDCD _L_(6) /**< \brief SDHC0 signal: SDCD on PA06 mux I */ +#define MUX_PA06I_SDHC0_SDCD _L_(8) +#define PINMUX_PA06I_SDHC0_SDCD ((PIN_PA06I_SDHC0_SDCD << 16) | MUX_PA06I_SDHC0_SDCD) +#define PORT_PA06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PA12I_SDHC0_SDCD _L_(12) /**< \brief SDHC0 signal: SDCD on PA12 mux I */ +#define MUX_PA12I_SDHC0_SDCD _L_(8) +#define PINMUX_PA12I_SDHC0_SDCD ((PIN_PA12I_SDHC0_SDCD << 16) | MUX_PA12I_SDHC0_SDCD) +#define PORT_PA12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PB12I_SDHC0_SDCD _L_(44) /**< \brief SDHC0 signal: SDCD on PB12 mux I */ +#define MUX_PB12I_SDHC0_SDCD _L_(8) +#define PINMUX_PB12I_SDHC0_SDCD ((PIN_PB12I_SDHC0_SDCD << 16) | MUX_PB12I_SDHC0_SDCD) +#define PORT_PB12I_SDHC0_SDCD (_UL_(1) << 12) +#define PIN_PC06I_SDHC0_SDCD _L_(70) /**< \brief SDHC0 signal: SDCD on PC06 mux I */ +#define MUX_PC06I_SDHC0_SDCD _L_(8) +#define PINMUX_PC06I_SDHC0_SDCD ((PIN_PC06I_SDHC0_SDCD << 16) | MUX_PC06I_SDHC0_SDCD) +#define PORT_PC06I_SDHC0_SDCD (_UL_(1) << 6) +#define PIN_PB11I_SDHC0_SDCK _L_(43) /**< \brief SDHC0 signal: SDCK on PB11 mux I */ +#define MUX_PB11I_SDHC0_SDCK _L_(8) +#define PINMUX_PB11I_SDHC0_SDCK ((PIN_PB11I_SDHC0_SDCK << 16) | MUX_PB11I_SDHC0_SDCK) +#define PORT_PB11I_SDHC0_SDCK (_UL_(1) << 11) +#define PIN_PA08I_SDHC0_SDCMD _L_(8) /**< \brief SDHC0 signal: SDCMD on PA08 mux I */ +#define MUX_PA08I_SDHC0_SDCMD _L_(8) +#define PINMUX_PA08I_SDHC0_SDCMD ((PIN_PA08I_SDHC0_SDCMD << 16) | MUX_PA08I_SDHC0_SDCMD) +#define PORT_PA08I_SDHC0_SDCMD (_UL_(1) << 8) +#define PIN_PA09I_SDHC0_SDDAT0 _L_(9) /**< \brief SDHC0 signal: SDDAT0 on PA09 mux I */ +#define MUX_PA09I_SDHC0_SDDAT0 _L_(8) +#define PINMUX_PA09I_SDHC0_SDDAT0 ((PIN_PA09I_SDHC0_SDDAT0 << 16) | MUX_PA09I_SDHC0_SDDAT0) +#define PORT_PA09I_SDHC0_SDDAT0 (_UL_(1) << 9) +#define PIN_PA10I_SDHC0_SDDAT1 _L_(10) /**< \brief SDHC0 signal: SDDAT1 on PA10 mux I */ +#define MUX_PA10I_SDHC0_SDDAT1 _L_(8) +#define PINMUX_PA10I_SDHC0_SDDAT1 ((PIN_PA10I_SDHC0_SDDAT1 << 16) | MUX_PA10I_SDHC0_SDDAT1) +#define PORT_PA10I_SDHC0_SDDAT1 (_UL_(1) << 10) +#define PIN_PA11I_SDHC0_SDDAT2 _L_(11) /**< \brief SDHC0 signal: SDDAT2 on PA11 mux I */ +#define MUX_PA11I_SDHC0_SDDAT2 _L_(8) +#define PINMUX_PA11I_SDHC0_SDDAT2 ((PIN_PA11I_SDHC0_SDDAT2 << 16) | MUX_PA11I_SDHC0_SDDAT2) +#define PORT_PA11I_SDHC0_SDDAT2 (_UL_(1) << 11) +#define PIN_PB10I_SDHC0_SDDAT3 _L_(42) /**< \brief SDHC0 signal: SDDAT3 on PB10 mux I */ +#define MUX_PB10I_SDHC0_SDDAT3 _L_(8) +#define PINMUX_PB10I_SDHC0_SDDAT3 ((PIN_PB10I_SDHC0_SDDAT3 << 16) | MUX_PB10I_SDHC0_SDDAT3) +#define PORT_PB10I_SDHC0_SDDAT3 (_UL_(1) << 10) +#define PIN_PA07I_SDHC0_SDWP _L_(7) /**< \brief SDHC0 signal: SDWP on PA07 mux I */ +#define MUX_PA07I_SDHC0_SDWP _L_(8) +#define PINMUX_PA07I_SDHC0_SDWP ((PIN_PA07I_SDHC0_SDWP << 16) | MUX_PA07I_SDHC0_SDWP) +#define PORT_PA07I_SDHC0_SDWP (_UL_(1) << 7) +#define PIN_PA13I_SDHC0_SDWP _L_(13) /**< \brief SDHC0 signal: SDWP on PA13 mux I */ +#define MUX_PA13I_SDHC0_SDWP _L_(8) +#define PINMUX_PA13I_SDHC0_SDWP ((PIN_PA13I_SDHC0_SDWP << 16) | MUX_PA13I_SDHC0_SDWP) +#define PORT_PA13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PB13I_SDHC0_SDWP _L_(45) /**< \brief SDHC0 signal: SDWP on PB13 mux I */ +#define MUX_PB13I_SDHC0_SDWP _L_(8) +#define PINMUX_PB13I_SDHC0_SDWP ((PIN_PB13I_SDHC0_SDWP << 16) | MUX_PB13I_SDHC0_SDWP) +#define PORT_PB13I_SDHC0_SDWP (_UL_(1) << 13) +#define PIN_PC07I_SDHC0_SDWP _L_(71) /**< \brief SDHC0 signal: SDWP on PC07 mux I */ +#define MUX_PC07I_SDHC0_SDWP _L_(8) +#define PINMUX_PC07I_SDHC0_SDWP ((PIN_PC07I_SDHC0_SDWP << 16) | MUX_PC07I_SDHC0_SDWP) +#define PORT_PC07I_SDHC0_SDWP (_UL_(1) << 7) +/* ========== PORT definition for SDHC1 peripheral ========== */ +#define PIN_PB16I_SDHC1_SDCD _L_(48) /**< \brief SDHC1 signal: SDCD on PB16 mux I */ +#define MUX_PB16I_SDHC1_SDCD _L_(8) +#define PINMUX_PB16I_SDHC1_SDCD ((PIN_PB16I_SDHC1_SDCD << 16) | MUX_PB16I_SDHC1_SDCD) +#define PORT_PB16I_SDHC1_SDCD (_UL_(1) << 16) +#define PIN_PC20I_SDHC1_SDCD _L_(84) /**< \brief SDHC1 signal: SDCD on PC20 mux I */ +#define MUX_PC20I_SDHC1_SDCD _L_(8) +#define PINMUX_PC20I_SDHC1_SDCD ((PIN_PC20I_SDHC1_SDCD << 16) | MUX_PC20I_SDHC1_SDCD) +#define PORT_PC20I_SDHC1_SDCD (_UL_(1) << 20) +#define PIN_PD20I_SDHC1_SDCD _L_(116) /**< \brief SDHC1 signal: SDCD on PD20 mux I */ +#define MUX_PD20I_SDHC1_SDCD _L_(8) +#define PINMUX_PD20I_SDHC1_SDCD ((PIN_PD20I_SDHC1_SDCD << 16) | MUX_PD20I_SDHC1_SDCD) +#define PORT_PD20I_SDHC1_SDCD (_UL_(1) << 20) +#define PIN_PA21I_SDHC1_SDCK _L_(21) /**< \brief SDHC1 signal: SDCK on PA21 mux I */ +#define MUX_PA21I_SDHC1_SDCK _L_(8) +#define PINMUX_PA21I_SDHC1_SDCK ((PIN_PA21I_SDHC1_SDCK << 16) | MUX_PA21I_SDHC1_SDCK) +#define PORT_PA21I_SDHC1_SDCK (_UL_(1) << 21) +#define PIN_PA20I_SDHC1_SDCMD _L_(20) /**< \brief SDHC1 signal: SDCMD on PA20 mux I */ +#define MUX_PA20I_SDHC1_SDCMD _L_(8) +#define PINMUX_PA20I_SDHC1_SDCMD ((PIN_PA20I_SDHC1_SDCMD << 16) | MUX_PA20I_SDHC1_SDCMD) +#define PORT_PA20I_SDHC1_SDCMD (_UL_(1) << 20) +#define PIN_PB18I_SDHC1_SDDAT0 _L_(50) /**< \brief SDHC1 signal: SDDAT0 on PB18 mux I */ +#define MUX_PB18I_SDHC1_SDDAT0 _L_(8) +#define PINMUX_PB18I_SDHC1_SDDAT0 ((PIN_PB18I_SDHC1_SDDAT0 << 16) | MUX_PB18I_SDHC1_SDDAT0) +#define PORT_PB18I_SDHC1_SDDAT0 (_UL_(1) << 18) +#define PIN_PB19I_SDHC1_SDDAT1 _L_(51) /**< \brief SDHC1 signal: SDDAT1 on PB19 mux I */ +#define MUX_PB19I_SDHC1_SDDAT1 _L_(8) +#define PINMUX_PB19I_SDHC1_SDDAT1 ((PIN_PB19I_SDHC1_SDDAT1 << 16) | MUX_PB19I_SDHC1_SDDAT1) +#define PORT_PB19I_SDHC1_SDDAT1 (_UL_(1) << 19) +#define PIN_PB20I_SDHC1_SDDAT2 _L_(52) /**< \brief SDHC1 signal: SDDAT2 on PB20 mux I */ +#define MUX_PB20I_SDHC1_SDDAT2 _L_(8) +#define PINMUX_PB20I_SDHC1_SDDAT2 ((PIN_PB20I_SDHC1_SDDAT2 << 16) | MUX_PB20I_SDHC1_SDDAT2) +#define PORT_PB20I_SDHC1_SDDAT2 (_UL_(1) << 20) +#define PIN_PB21I_SDHC1_SDDAT3 _L_(53) /**< \brief SDHC1 signal: SDDAT3 on PB21 mux I */ +#define MUX_PB21I_SDHC1_SDDAT3 _L_(8) +#define PINMUX_PB21I_SDHC1_SDDAT3 ((PIN_PB21I_SDHC1_SDDAT3 << 16) | MUX_PB21I_SDHC1_SDDAT3) +#define PORT_PB21I_SDHC1_SDDAT3 (_UL_(1) << 21) +#define PIN_PB17I_SDHC1_SDWP _L_(49) /**< \brief SDHC1 signal: SDWP on PB17 mux I */ +#define MUX_PB17I_SDHC1_SDWP _L_(8) +#define PINMUX_PB17I_SDHC1_SDWP ((PIN_PB17I_SDHC1_SDWP << 16) | MUX_PB17I_SDHC1_SDWP) +#define PORT_PB17I_SDHC1_SDWP (_UL_(1) << 17) +#define PIN_PC21I_SDHC1_SDWP _L_(85) /**< \brief SDHC1 signal: SDWP on PC21 mux I */ +#define MUX_PC21I_SDHC1_SDWP _L_(8) +#define PINMUX_PC21I_SDHC1_SDWP ((PIN_PC21I_SDHC1_SDWP << 16) | MUX_PC21I_SDHC1_SDWP) +#define PORT_PC21I_SDHC1_SDWP (_UL_(1) << 21) +#define PIN_PD21I_SDHC1_SDWP _L_(117) /**< \brief SDHC1 signal: SDWP on PD21 mux I */ +#define MUX_PD21I_SDHC1_SDWP _L_(8) +#define PINMUX_PD21I_SDHC1_SDWP ((PIN_PD21I_SDHC1_SDWP << 16) | MUX_PD21I_SDHC1_SDWP) +#define PORT_PD21I_SDHC1_SDWP (_UL_(1) << 21) + +#endif /* _SAME54P20A_PIO_ */ diff --git a/software/firmware/oracle_same54n19a/include/sam.h b/software/firmware/oracle_same54n19a/include/sam.h new file mode 100644 index 00000000..3fa3b5f2 --- /dev/null +++ b/software/firmware/oracle_same54n19a/include/sam.h @@ -0,0 +1,45 @@ +/** + * \file + * + * \brief Top level header file + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \license_stop + * + */ + +#ifndef _SAM_ +#define _SAM_ + +#if defined(__SAME54N19A__) || defined(__ATSAME54N19A__) +#include "same54n19a.h" +#elif defined(__SAME54N20A__) || defined(__ATSAME54N20A__) +#include "same54n20a.h" +#elif defined(__SAME54P19A__) || defined(__ATSAME54P19A__) +#include "same54p19a.h" +#elif defined(__SAME54P20A__) || defined(__ATSAME54P20A__) +#include "same54p20a.h" +#else +#error Library does not support the specified device +#endif + +#endif /* _SAM_ */ diff --git a/software/firmware/oracle_same54n19a/include/same54.h b/software/firmware/oracle_same54n19a/include/same54.h new file mode 100644 index 00000000..7da756eb --- /dev/null +++ b/software/firmware/oracle_same54n19a/include/same54.h @@ -0,0 +1,50 @@ +/** + * \file + * + * \brief Top header file for SAME54 + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54_ +#define _SAME54_ + +/** + * \defgroup SAME54_definitions SAME54 Device Definitions + * \brief SAME54 CMSIS Definitions. + */ + +#if defined(__SAME54N19A__) || defined(__ATSAME54N19A__) + #include "same54n19a.h" +#elif defined(__SAME54N20A__) || defined(__ATSAME54N20A__) + #include "same54n20a.h" +#elif defined(__SAME54P19A__) || defined(__ATSAME54P19A__) + #include "same54p19a.h" +#elif defined(__SAME54P20A__) || defined(__ATSAME54P20A__) + #include "same54p20a.h" +#else + #error Library does not support the specified device. +#endif + +#endif /* _SAME54_ */ diff --git a/software/firmware/oracle_same54n19a/include/same54n19a.h b/software/firmware/oracle_same54n19a/include/same54n19a.h new file mode 100644 index 00000000..cb183bb9 --- /dev/null +++ b/software/firmware/oracle_same54n19a/include/same54n19a.h @@ -0,0 +1,1085 @@ +/** + * \file + * + * \brief Header file for SAME54N19A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54N19A_ +#define _SAME54N19A_ + +/** + * \ingroup SAME54_definitions + * \addtogroup SAME54N19A_definitions SAME54N19A definitions + * This file defines all structures and symbols for SAME54N19A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAME54N19A */ +/* ************************************************************************** */ +/** \defgroup SAME54N19A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */ + BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAME54N19A-specific Interrupt Numbers *********************/ + PM_IRQn = 0, /**< 0 SAME54N19A Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 SAME54N19A Main Clock (MCLK) */ + OSCCTRL_0_IRQn = 2, /**< 2 SAME54N19A Oscillators Control (OSCCTRL) IRQ 0 */ + OSCCTRL_1_IRQn = 3, /**< 3 SAME54N19A Oscillators Control (OSCCTRL) IRQ 1 */ + OSCCTRL_2_IRQn = 4, /**< 4 SAME54N19A Oscillators Control (OSCCTRL) IRQ 2 */ + OSCCTRL_3_IRQn = 5, /**< 5 SAME54N19A Oscillators Control (OSCCTRL) IRQ 3 */ + OSCCTRL_4_IRQn = 6, /**< 6 SAME54N19A Oscillators Control (OSCCTRL) IRQ 4 */ + OSC32KCTRL_IRQn = 7, /**< 7 SAME54N19A 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_0_IRQn = 8, /**< 8 SAME54N19A Supply Controller (SUPC) IRQ 0 */ + SUPC_1_IRQn = 9, /**< 9 SAME54N19A Supply Controller (SUPC) IRQ 1 */ + WDT_IRQn = 10, /**< 10 SAME54N19A Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 SAME54N19A Real-Time Counter (RTC) */ + EIC_0_IRQn = 12, /**< 12 SAME54N19A External Interrupt Controller (EIC) IRQ 0 */ + EIC_1_IRQn = 13, /**< 13 SAME54N19A External Interrupt Controller (EIC) IRQ 1 */ + EIC_2_IRQn = 14, /**< 14 SAME54N19A External Interrupt Controller (EIC) IRQ 2 */ + EIC_3_IRQn = 15, /**< 15 SAME54N19A External Interrupt Controller (EIC) IRQ 3 */ + EIC_4_IRQn = 16, /**< 16 SAME54N19A External Interrupt Controller (EIC) IRQ 4 */ + EIC_5_IRQn = 17, /**< 17 SAME54N19A External Interrupt Controller (EIC) IRQ 5 */ + EIC_6_IRQn = 18, /**< 18 SAME54N19A External Interrupt Controller (EIC) IRQ 6 */ + EIC_7_IRQn = 19, /**< 19 SAME54N19A External Interrupt Controller (EIC) IRQ 7 */ + EIC_8_IRQn = 20, /**< 20 SAME54N19A External Interrupt Controller (EIC) IRQ 8 */ + EIC_9_IRQn = 21, /**< 21 SAME54N19A External Interrupt Controller (EIC) IRQ 9 */ + EIC_10_IRQn = 22, /**< 22 SAME54N19A External Interrupt Controller (EIC) IRQ 10 */ + EIC_11_IRQn = 23, /**< 23 SAME54N19A External Interrupt Controller (EIC) IRQ 11 */ + EIC_12_IRQn = 24, /**< 24 SAME54N19A External Interrupt Controller (EIC) IRQ 12 */ + EIC_13_IRQn = 25, /**< 25 SAME54N19A External Interrupt Controller (EIC) IRQ 13 */ + EIC_14_IRQn = 26, /**< 26 SAME54N19A External Interrupt Controller (EIC) IRQ 14 */ + EIC_15_IRQn = 27, /**< 27 SAME54N19A External Interrupt Controller (EIC) IRQ 15 */ + FREQM_IRQn = 28, /**< 28 SAME54N19A Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 SAME54N19A Non-Volatile Memory Controller (NVMCTRL) IRQ 0 */ + NVMCTRL_1_IRQn = 30, /**< 30 SAME54N19A Non-Volatile Memory Controller (NVMCTRL) IRQ 1 */ + DMAC_0_IRQn = 31, /**< 31 SAME54N19A Direct Memory Access Controller (DMAC) IRQ 0 */ + DMAC_1_IRQn = 32, /**< 32 SAME54N19A Direct Memory Access Controller (DMAC) IRQ 1 */ + DMAC_2_IRQn = 33, /**< 33 SAME54N19A Direct Memory Access Controller (DMAC) IRQ 2 */ + DMAC_3_IRQn = 34, /**< 34 SAME54N19A Direct Memory Access Controller (DMAC) IRQ 3 */ + DMAC_4_IRQn = 35, /**< 35 SAME54N19A Direct Memory Access Controller (DMAC) IRQ 4 */ + EVSYS_0_IRQn = 36, /**< 36 SAME54N19A Event System Interface (EVSYS) IRQ 0 */ + EVSYS_1_IRQn = 37, /**< 37 SAME54N19A Event System Interface (EVSYS) IRQ 1 */ + EVSYS_2_IRQn = 38, /**< 38 SAME54N19A Event System Interface (EVSYS) IRQ 2 */ + EVSYS_3_IRQn = 39, /**< 39 SAME54N19A Event System Interface (EVSYS) IRQ 3 */ + EVSYS_4_IRQn = 40, /**< 40 SAME54N19A Event System Interface (EVSYS) IRQ 4 */ + PAC_IRQn = 41, /**< 41 SAME54N19A Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /**< 45 SAME54N19A RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 SAME54N19A Serial Communication Interface 0 (SERCOM0) IRQ 0 */ + SERCOM0_1_IRQn = 47, /**< 47 SAME54N19A Serial Communication Interface 0 (SERCOM0) IRQ 1 */ + SERCOM0_2_IRQn = 48, /**< 48 SAME54N19A Serial Communication Interface 0 (SERCOM0) IRQ 2 */ + SERCOM0_3_IRQn = 49, /**< 49 SAME54N19A Serial Communication Interface 0 (SERCOM0) IRQ 3 */ + SERCOM1_0_IRQn = 50, /**< 50 SAME54N19A Serial Communication Interface 1 (SERCOM1) IRQ 0 */ + SERCOM1_1_IRQn = 51, /**< 51 SAME54N19A Serial Communication Interface 1 (SERCOM1) IRQ 1 */ + SERCOM1_2_IRQn = 52, /**< 52 SAME54N19A Serial Communication Interface 1 (SERCOM1) IRQ 2 */ + SERCOM1_3_IRQn = 53, /**< 53 SAME54N19A Serial Communication Interface 1 (SERCOM1) IRQ 3 */ + SERCOM2_0_IRQn = 54, /**< 54 SAME54N19A Serial Communication Interface 2 (SERCOM2) IRQ 0 */ + SERCOM2_1_IRQn = 55, /**< 55 SAME54N19A Serial Communication Interface 2 (SERCOM2) IRQ 1 */ + SERCOM2_2_IRQn = 56, /**< 56 SAME54N19A Serial Communication Interface 2 (SERCOM2) IRQ 2 */ + SERCOM2_3_IRQn = 57, /**< 57 SAME54N19A Serial Communication Interface 2 (SERCOM2) IRQ 3 */ + SERCOM3_0_IRQn = 58, /**< 58 SAME54N19A Serial Communication Interface 3 (SERCOM3) IRQ 0 */ + SERCOM3_1_IRQn = 59, /**< 59 SAME54N19A Serial Communication Interface 3 (SERCOM3) IRQ 1 */ + SERCOM3_2_IRQn = 60, /**< 60 SAME54N19A Serial Communication Interface 3 (SERCOM3) IRQ 2 */ + SERCOM3_3_IRQn = 61, /**< 61 SAME54N19A Serial Communication Interface 3 (SERCOM3) IRQ 3 */ + SERCOM4_0_IRQn = 62, /**< 62 SAME54N19A Serial Communication Interface 4 (SERCOM4) IRQ 0 */ + SERCOM4_1_IRQn = 63, /**< 63 SAME54N19A Serial Communication Interface 4 (SERCOM4) IRQ 1 */ + SERCOM4_2_IRQn = 64, /**< 64 SAME54N19A Serial Communication Interface 4 (SERCOM4) IRQ 2 */ + SERCOM4_3_IRQn = 65, /**< 65 SAME54N19A Serial Communication Interface 4 (SERCOM4) IRQ 3 */ + SERCOM5_0_IRQn = 66, /**< 66 SAME54N19A Serial Communication Interface 5 (SERCOM5) IRQ 0 */ + SERCOM5_1_IRQn = 67, /**< 67 SAME54N19A Serial Communication Interface 5 (SERCOM5) IRQ 1 */ + SERCOM5_2_IRQn = 68, /**< 68 SAME54N19A Serial Communication Interface 5 (SERCOM5) IRQ 2 */ + SERCOM5_3_IRQn = 69, /**< 69 SAME54N19A Serial Communication Interface 5 (SERCOM5) IRQ 3 */ + SERCOM6_0_IRQn = 70, /**< 70 SAME54N19A Serial Communication Interface 6 (SERCOM6) IRQ 0 */ + SERCOM6_1_IRQn = 71, /**< 71 SAME54N19A Serial Communication Interface 6 (SERCOM6) IRQ 1 */ + SERCOM6_2_IRQn = 72, /**< 72 SAME54N19A Serial Communication Interface 6 (SERCOM6) IRQ 2 */ + SERCOM6_3_IRQn = 73, /**< 73 SAME54N19A Serial Communication Interface 6 (SERCOM6) IRQ 3 */ + SERCOM7_0_IRQn = 74, /**< 74 SAME54N19A Serial Communication Interface 7 (SERCOM7) IRQ 0 */ + SERCOM7_1_IRQn = 75, /**< 75 SAME54N19A Serial Communication Interface 7 (SERCOM7) IRQ 1 */ + SERCOM7_2_IRQn = 76, /**< 76 SAME54N19A Serial Communication Interface 7 (SERCOM7) IRQ 2 */ + SERCOM7_3_IRQn = 77, /**< 77 SAME54N19A Serial Communication Interface 7 (SERCOM7) IRQ 3 */ + CAN0_IRQn = 78, /**< 78 SAME54N19A Control Area Network 0 (CAN0) */ + CAN1_IRQn = 79, /**< 79 SAME54N19A Control Area Network 1 (CAN1) */ + USB_0_IRQn = 80, /**< 80 SAME54N19A Universal Serial Bus (USB) IRQ 0 */ + USB_1_IRQn = 81, /**< 81 SAME54N19A Universal Serial Bus (USB) IRQ 1 */ + USB_2_IRQn = 82, /**< 82 SAME54N19A Universal Serial Bus (USB) IRQ 2 */ + USB_3_IRQn = 83, /**< 83 SAME54N19A Universal Serial Bus (USB) IRQ 3 */ + GMAC_IRQn = 84, /**< 84 SAME54N19A Ethernet MAC (GMAC) */ + TCC0_0_IRQn = 85, /**< 85 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 0 */ + TCC0_1_IRQn = 86, /**< 86 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 1 */ + TCC0_2_IRQn = 87, /**< 87 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 2 */ + TCC0_3_IRQn = 88, /**< 88 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 3 */ + TCC0_4_IRQn = 89, /**< 89 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 4 */ + TCC0_5_IRQn = 90, /**< 90 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 5 */ + TCC0_6_IRQn = 91, /**< 91 SAME54N19A Timer Counter Control 0 (TCC0) IRQ 6 */ + TCC1_0_IRQn = 92, /**< 92 SAME54N19A Timer Counter Control 1 (TCC1) IRQ 0 */ + TCC1_1_IRQn = 93, /**< 93 SAME54N19A Timer Counter Control 1 (TCC1) IRQ 1 */ + TCC1_2_IRQn = 94, /**< 94 SAME54N19A Timer Counter Control 1 (TCC1) IRQ 2 */ + TCC1_3_IRQn = 95, /**< 95 SAME54N19A Timer Counter Control 1 (TCC1) IRQ 3 */ + TCC1_4_IRQn = 96, /**< 96 SAME54N19A Timer Counter Control 1 (TCC1) IRQ 4 */ + TCC2_0_IRQn = 97, /**< 97 SAME54N19A Timer Counter Control 2 (TCC2) IRQ 0 */ + TCC2_1_IRQn = 98, /**< 98 SAME54N19A Timer Counter Control 2 (TCC2) IRQ 1 */ + TCC2_2_IRQn = 99, /**< 99 SAME54N19A Timer Counter Control 2 (TCC2) IRQ 2 */ + TCC2_3_IRQn = 100, /**< 100 SAME54N19A Timer Counter Control 2 (TCC2) IRQ 3 */ + TCC3_0_IRQn = 101, /**< 101 SAME54N19A Timer Counter Control 3 (TCC3) IRQ 0 */ + TCC3_1_IRQn = 102, /**< 102 SAME54N19A Timer Counter Control 3 (TCC3) IRQ 1 */ + TCC3_2_IRQn = 103, /**< 103 SAME54N19A Timer Counter Control 3 (TCC3) IRQ 2 */ + TCC4_0_IRQn = 104, /**< 104 SAME54N19A Timer Counter Control 4 (TCC4) IRQ 0 */ + TCC4_1_IRQn = 105, /**< 105 SAME54N19A Timer Counter Control 4 (TCC4) IRQ 1 */ + TCC4_2_IRQn = 106, /**< 106 SAME54N19A Timer Counter Control 4 (TCC4) IRQ 2 */ + TC0_IRQn = 107, /**< 107 SAME54N19A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 108, /**< 108 SAME54N19A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 109, /**< 109 SAME54N19A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 110, /**< 110 SAME54N19A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 111, /**< 111 SAME54N19A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 112, /**< 112 SAME54N19A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 113, /**< 113 SAME54N19A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 114, /**< 114 SAME54N19A Basic Timer Counter 7 (TC7) */ + PDEC_0_IRQn = 115, /**< 115 SAME54N19A Quadrature Decodeur (PDEC) IRQ 0 */ + PDEC_1_IRQn = 116, /**< 116 SAME54N19A Quadrature Decodeur (PDEC) IRQ 1 */ + PDEC_2_IRQn = 117, /**< 117 SAME54N19A Quadrature Decodeur (PDEC) IRQ 2 */ + ADC0_0_IRQn = 118, /**< 118 SAME54N19A Analog Digital Converter 0 (ADC0) IRQ 0 */ + ADC0_1_IRQn = 119, /**< 119 SAME54N19A Analog Digital Converter 0 (ADC0) IRQ 1 */ + ADC1_0_IRQn = 120, /**< 120 SAME54N19A Analog Digital Converter 1 (ADC1) IRQ 0 */ + ADC1_1_IRQn = 121, /**< 121 SAME54N19A Analog Digital Converter 1 (ADC1) IRQ 1 */ + AC_IRQn = 122, /**< 122 SAME54N19A Analog Comparators (AC) */ + DAC_0_IRQn = 123, /**< 123 SAME54N19A Digital-to-Analog Converter (DAC) IRQ 0 */ + DAC_1_IRQn = 124, /**< 124 SAME54N19A Digital-to-Analog Converter (DAC) IRQ 1 */ + DAC_2_IRQn = 125, /**< 125 SAME54N19A Digital-to-Analog Converter (DAC) IRQ 2 */ + DAC_3_IRQn = 126, /**< 126 SAME54N19A Digital-to-Analog Converter (DAC) IRQ 3 */ + DAC_4_IRQn = 127, /**< 127 SAME54N19A Digital-to-Analog Converter (DAC) IRQ 4 */ + I2S_IRQn = 128, /**< 128 SAME54N19A Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 SAME54N19A Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 SAME54N19A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 SAME54N19A True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 SAME54N19A Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 SAME54N19A PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 SAME54N19A Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SAME54N19A SD/MMC Host Controller 0 (SDHC0) */ + SDHC1_IRQn = 136, /**< 136 SAME54N19A SD/MMC Host Controller 1 (SDHC1) */ + + PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pfnMemManagement_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pfnDebugMonitor_Handler; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnMCLK_Handler; /* 1 Main Clock */ + void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ + void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ + void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ + void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ + void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ + void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ + void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ + void* pfnWDT_Handler; /* 10 Watchdog Timer */ + void* pfnRTC_Handler; /* 11 Real-Time Counter */ + void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ + void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ + void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ + void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ + void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ + void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ + void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ + void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ + void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ + void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ + void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ + void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ + void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ + void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ + void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ + void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ + void* pfnFREQM_Handler; /* 28 Frequency Meter */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ + void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ + void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ + void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ + void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ + void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ + void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ + void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ + void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ + void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */ + void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */ + void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */ + void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */ + void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */ + void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */ + void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */ + void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */ + void* pfnCAN0_Handler; /* 78 Control Area Network 0 */ + void* pfnCAN1_Handler; /* 79 Control Area Network 1 */ + void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ + void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ + void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ + void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ + void* pfnGMAC_Handler; /* 84 Ethernet MAC */ + void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ + void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ + void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ + void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ + void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ + void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ + void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ + void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ + void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ + void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ + void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ + void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ + void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ + void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ + void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ + void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ + void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ + void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ + void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ + void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ + void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ + void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */ + void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ + void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ + void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ + void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ + void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ + void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ + void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ + void* pfnAC_Handler; /* 122 Analog Comparators */ + void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ + void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ + void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ + void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ + void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 131 True Random Generator */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ + void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */ +} DeviceVectors; + +/* Cortex-M4 processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_0_Handler ( void ); +void OSCCTRL_1_Handler ( void ); +void OSCCTRL_2_Handler ( void ); +void OSCCTRL_3_Handler ( void ); +void OSCCTRL_4_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_0_Handler ( void ); +void SUPC_1_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_0_Handler ( void ); +void EIC_1_Handler ( void ); +void EIC_2_Handler ( void ); +void EIC_3_Handler ( void ); +void EIC_4_Handler ( void ); +void EIC_5_Handler ( void ); +void EIC_6_Handler ( void ); +void EIC_7_Handler ( void ); +void EIC_8_Handler ( void ); +void EIC_9_Handler ( void ); +void EIC_10_Handler ( void ); +void EIC_11_Handler ( void ); +void EIC_12_Handler ( void ); +void EIC_13_Handler ( void ); +void EIC_14_Handler ( void ); +void EIC_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_4_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_4_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_3_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_3_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_3_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_3_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_3_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_3_Handler ( void ); +void SERCOM6_0_Handler ( void ); +void SERCOM6_1_Handler ( void ); +void SERCOM6_2_Handler ( void ); +void SERCOM6_3_Handler ( void ); +void SERCOM7_0_Handler ( void ); +void SERCOM7_1_Handler ( void ); +void SERCOM7_2_Handler ( void ); +void SERCOM7_3_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void USB_0_Handler ( void ); +void USB_1_Handler ( void ); +void USB_2_Handler ( void ); +void USB_3_Handler ( void ); +void GMAC_Handler ( void ); +void TCC0_0_Handler ( void ); +void TCC0_1_Handler ( void ); +void TCC0_2_Handler ( void ); +void TCC0_3_Handler ( void ); +void TCC0_4_Handler ( void ); +void TCC0_5_Handler ( void ); +void TCC0_6_Handler ( void ); +void TCC1_0_Handler ( void ); +void TCC1_1_Handler ( void ); +void TCC1_2_Handler ( void ); +void TCC1_3_Handler ( void ); +void TCC1_4_Handler ( void ); +void TCC2_0_Handler ( void ); +void TCC2_1_Handler ( void ); +void TCC2_2_Handler ( void ); +void TCC2_3_Handler ( void ); +void TCC3_0_Handler ( void ); +void TCC3_1_Handler ( void ); +void TCC3_2_Handler ( void ); +void TCC4_0_Handler ( void ); +void TCC4_1_Handler ( void ); +void TCC4_2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void PDEC_0_Handler ( void ); +void PDEC_1_Handler ( void ); +void PDEC_2_Handler ( void ); +void ADC0_0_Handler ( void ); +void ADC0_1_Handler ( void ); +void ADC1_0_Handler ( void ); +void ADC1_1_Handler ( void ); +void AC_Handler ( void ); +void DAC_0_Handler ( void ); +void DAC_1_Handler ( void ); +void DAC_2_Handler ( void ); +void DAC_3_Handler ( void ); +void DAC_4_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +void SDHC1_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +#define __CM4_REV 1 /*!< Core revision r0p1 */ +#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ +#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same54.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME54N19A */ +/* ************************************************************************** */ +/** \defgroup SAME54N19A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/gmac.h" +#include "component/hmatrixb.h" +#include "component/icm.h" +#include "component/i2s.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAME54N19A */ +/* ************************************************************************** */ +/** \defgroup SAME54N19A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/aes.h" +#include "instance/can0.h" +#include "instance/can1.h" +#include "instance/ccl.h" +#include "instance/cmcc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/gmac.h" +#include "instance/hmatrix.h" +#include "instance/icm.h" +#include "instance/i2s.h" +#include "instance/mclk.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pcc.h" +#include "instance/pdec.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/pukcc.h" +#include "instance/qspi.h" +#include "instance/ramecc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdhc0.h" +#include "instance/sdhc1.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sercom6.h" +#include "instance/sercom7.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tcc3.h" +#include "instance/tcc4.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAME54N19A */ +/* ************************************************************************** */ +/** \defgroup SAME54N19A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT 36 /**< \brief Port Module (PORT) */ +#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ + +// Peripheral instances on HPB2 bridge +#define ID_CAN0 64 /**< \brief Control Area Network 0 (CAN0) */ +#define ID_CAN1 65 /**< \brief Control Area Network 1 (CAN1) */ +#define ID_GMAC 66 /**< \brief Ethernet MAC (GMAC) */ +#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ +#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC 72 /**< \brief Analog Comparators (AC) */ +#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ +#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB3 bridge +#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */ +#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */ +#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ +#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ + +// Peripheral instances on AHB (as if on bridge 4) +#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ +#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAME54N19A */ +/* ************************************************************************** */ +/** \defgroup SAME54N19A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42002000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ +#define AES (0x42002400) /**< \brief (AES) APB Base Address */ +#define CAN0 (0x42000000) /**< \brief (CAN0) APB Base Address */ +#define CAN1 (0x42000400) /**< \brief (CAN1) APB Base Address */ +#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ +#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ +#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define GMAC (0x42000800) /**< \brief (GMAC) APB Base Address */ +#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ +#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ +#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ +#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ +#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ +#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ +#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */ +#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ +#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ +#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ +#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CAN0 ((Can *)0x42000000UL) /**< \brief (CAN0) APB Base Address */ +#define CAN1 ((Can *)0x42000400UL) /**< \brief (CAN1) APB Base Address */ +#define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */ +#define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */ + +#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ +#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ +#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ + +#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define GMAC ((Gmac *)0x42000800UL) /**< \brief (GMAC) APB Base Address */ +#define GMAC_INST_NUM 1 /**< \brief (GMAC) Number of instances */ +#define GMAC_INSTS { GMAC } /**< \brief (GMAC) Instances List */ + +#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ + +#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ +#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ +#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ + +#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ +#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ +#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ +#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ +#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ + +#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ + +#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ +#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ +#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */ +#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */ +#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */ + +#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */ +#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ +#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ +#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAME54N19A */ +/* ************************************************************************** */ +/** \defgroup SAME54N19A_port PORT Definitions */ +/*@{*/ + +#include "pio/same54n19a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAME54N19A */ +/* ************************************************************************** */ + +#define HSRAM_SIZE _UL_(0x00030000) /* 192 kB */ +#define FLASH_SIZE _UL_(0x00080000) /* 512 kB */ +#define FLASH_PAGE_SIZE 512 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 512 +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x61840303) +#define ADC0_TOUCH_LINES_NUM 32 +#define PORT_GROUPS 3 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME54N19A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAME54N19A_H */ diff --git a/software/firmware/oracle_same54n19a/include/same54n20a.h b/software/firmware/oracle_same54n19a/include/same54n20a.h new file mode 100644 index 00000000..4d4e23d6 --- /dev/null +++ b/software/firmware/oracle_same54n19a/include/same54n20a.h @@ -0,0 +1,1085 @@ +/** + * \file + * + * \brief Header file for SAME54N20A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54N20A_ +#define _SAME54N20A_ + +/** + * \ingroup SAME54_definitions + * \addtogroup SAME54N20A_definitions SAME54N20A definitions + * This file defines all structures and symbols for SAME54N20A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAME54N20A */ +/* ************************************************************************** */ +/** \defgroup SAME54N20A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */ + BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAME54N20A-specific Interrupt Numbers *********************/ + PM_IRQn = 0, /**< 0 SAME54N20A Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 SAME54N20A Main Clock (MCLK) */ + OSCCTRL_0_IRQn = 2, /**< 2 SAME54N20A Oscillators Control (OSCCTRL) IRQ 0 */ + OSCCTRL_1_IRQn = 3, /**< 3 SAME54N20A Oscillators Control (OSCCTRL) IRQ 1 */ + OSCCTRL_2_IRQn = 4, /**< 4 SAME54N20A Oscillators Control (OSCCTRL) IRQ 2 */ + OSCCTRL_3_IRQn = 5, /**< 5 SAME54N20A Oscillators Control (OSCCTRL) IRQ 3 */ + OSCCTRL_4_IRQn = 6, /**< 6 SAME54N20A Oscillators Control (OSCCTRL) IRQ 4 */ + OSC32KCTRL_IRQn = 7, /**< 7 SAME54N20A 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_0_IRQn = 8, /**< 8 SAME54N20A Supply Controller (SUPC) IRQ 0 */ + SUPC_1_IRQn = 9, /**< 9 SAME54N20A Supply Controller (SUPC) IRQ 1 */ + WDT_IRQn = 10, /**< 10 SAME54N20A Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 SAME54N20A Real-Time Counter (RTC) */ + EIC_0_IRQn = 12, /**< 12 SAME54N20A External Interrupt Controller (EIC) IRQ 0 */ + EIC_1_IRQn = 13, /**< 13 SAME54N20A External Interrupt Controller (EIC) IRQ 1 */ + EIC_2_IRQn = 14, /**< 14 SAME54N20A External Interrupt Controller (EIC) IRQ 2 */ + EIC_3_IRQn = 15, /**< 15 SAME54N20A External Interrupt Controller (EIC) IRQ 3 */ + EIC_4_IRQn = 16, /**< 16 SAME54N20A External Interrupt Controller (EIC) IRQ 4 */ + EIC_5_IRQn = 17, /**< 17 SAME54N20A External Interrupt Controller (EIC) IRQ 5 */ + EIC_6_IRQn = 18, /**< 18 SAME54N20A External Interrupt Controller (EIC) IRQ 6 */ + EIC_7_IRQn = 19, /**< 19 SAME54N20A External Interrupt Controller (EIC) IRQ 7 */ + EIC_8_IRQn = 20, /**< 20 SAME54N20A External Interrupt Controller (EIC) IRQ 8 */ + EIC_9_IRQn = 21, /**< 21 SAME54N20A External Interrupt Controller (EIC) IRQ 9 */ + EIC_10_IRQn = 22, /**< 22 SAME54N20A External Interrupt Controller (EIC) IRQ 10 */ + EIC_11_IRQn = 23, /**< 23 SAME54N20A External Interrupt Controller (EIC) IRQ 11 */ + EIC_12_IRQn = 24, /**< 24 SAME54N20A External Interrupt Controller (EIC) IRQ 12 */ + EIC_13_IRQn = 25, /**< 25 SAME54N20A External Interrupt Controller (EIC) IRQ 13 */ + EIC_14_IRQn = 26, /**< 26 SAME54N20A External Interrupt Controller (EIC) IRQ 14 */ + EIC_15_IRQn = 27, /**< 27 SAME54N20A External Interrupt Controller (EIC) IRQ 15 */ + FREQM_IRQn = 28, /**< 28 SAME54N20A Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 SAME54N20A Non-Volatile Memory Controller (NVMCTRL) IRQ 0 */ + NVMCTRL_1_IRQn = 30, /**< 30 SAME54N20A Non-Volatile Memory Controller (NVMCTRL) IRQ 1 */ + DMAC_0_IRQn = 31, /**< 31 SAME54N20A Direct Memory Access Controller (DMAC) IRQ 0 */ + DMAC_1_IRQn = 32, /**< 32 SAME54N20A Direct Memory Access Controller (DMAC) IRQ 1 */ + DMAC_2_IRQn = 33, /**< 33 SAME54N20A Direct Memory Access Controller (DMAC) IRQ 2 */ + DMAC_3_IRQn = 34, /**< 34 SAME54N20A Direct Memory Access Controller (DMAC) IRQ 3 */ + DMAC_4_IRQn = 35, /**< 35 SAME54N20A Direct Memory Access Controller (DMAC) IRQ 4 */ + EVSYS_0_IRQn = 36, /**< 36 SAME54N20A Event System Interface (EVSYS) IRQ 0 */ + EVSYS_1_IRQn = 37, /**< 37 SAME54N20A Event System Interface (EVSYS) IRQ 1 */ + EVSYS_2_IRQn = 38, /**< 38 SAME54N20A Event System Interface (EVSYS) IRQ 2 */ + EVSYS_3_IRQn = 39, /**< 39 SAME54N20A Event System Interface (EVSYS) IRQ 3 */ + EVSYS_4_IRQn = 40, /**< 40 SAME54N20A Event System Interface (EVSYS) IRQ 4 */ + PAC_IRQn = 41, /**< 41 SAME54N20A Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /**< 45 SAME54N20A RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 SAME54N20A Serial Communication Interface 0 (SERCOM0) IRQ 0 */ + SERCOM0_1_IRQn = 47, /**< 47 SAME54N20A Serial Communication Interface 0 (SERCOM0) IRQ 1 */ + SERCOM0_2_IRQn = 48, /**< 48 SAME54N20A Serial Communication Interface 0 (SERCOM0) IRQ 2 */ + SERCOM0_3_IRQn = 49, /**< 49 SAME54N20A Serial Communication Interface 0 (SERCOM0) IRQ 3 */ + SERCOM1_0_IRQn = 50, /**< 50 SAME54N20A Serial Communication Interface 1 (SERCOM1) IRQ 0 */ + SERCOM1_1_IRQn = 51, /**< 51 SAME54N20A Serial Communication Interface 1 (SERCOM1) IRQ 1 */ + SERCOM1_2_IRQn = 52, /**< 52 SAME54N20A Serial Communication Interface 1 (SERCOM1) IRQ 2 */ + SERCOM1_3_IRQn = 53, /**< 53 SAME54N20A Serial Communication Interface 1 (SERCOM1) IRQ 3 */ + SERCOM2_0_IRQn = 54, /**< 54 SAME54N20A Serial Communication Interface 2 (SERCOM2) IRQ 0 */ + SERCOM2_1_IRQn = 55, /**< 55 SAME54N20A Serial Communication Interface 2 (SERCOM2) IRQ 1 */ + SERCOM2_2_IRQn = 56, /**< 56 SAME54N20A Serial Communication Interface 2 (SERCOM2) IRQ 2 */ + SERCOM2_3_IRQn = 57, /**< 57 SAME54N20A Serial Communication Interface 2 (SERCOM2) IRQ 3 */ + SERCOM3_0_IRQn = 58, /**< 58 SAME54N20A Serial Communication Interface 3 (SERCOM3) IRQ 0 */ + SERCOM3_1_IRQn = 59, /**< 59 SAME54N20A Serial Communication Interface 3 (SERCOM3) IRQ 1 */ + SERCOM3_2_IRQn = 60, /**< 60 SAME54N20A Serial Communication Interface 3 (SERCOM3) IRQ 2 */ + SERCOM3_3_IRQn = 61, /**< 61 SAME54N20A Serial Communication Interface 3 (SERCOM3) IRQ 3 */ + SERCOM4_0_IRQn = 62, /**< 62 SAME54N20A Serial Communication Interface 4 (SERCOM4) IRQ 0 */ + SERCOM4_1_IRQn = 63, /**< 63 SAME54N20A Serial Communication Interface 4 (SERCOM4) IRQ 1 */ + SERCOM4_2_IRQn = 64, /**< 64 SAME54N20A Serial Communication Interface 4 (SERCOM4) IRQ 2 */ + SERCOM4_3_IRQn = 65, /**< 65 SAME54N20A Serial Communication Interface 4 (SERCOM4) IRQ 3 */ + SERCOM5_0_IRQn = 66, /**< 66 SAME54N20A Serial Communication Interface 5 (SERCOM5) IRQ 0 */ + SERCOM5_1_IRQn = 67, /**< 67 SAME54N20A Serial Communication Interface 5 (SERCOM5) IRQ 1 */ + SERCOM5_2_IRQn = 68, /**< 68 SAME54N20A Serial Communication Interface 5 (SERCOM5) IRQ 2 */ + SERCOM5_3_IRQn = 69, /**< 69 SAME54N20A Serial Communication Interface 5 (SERCOM5) IRQ 3 */ + SERCOM6_0_IRQn = 70, /**< 70 SAME54N20A Serial Communication Interface 6 (SERCOM6) IRQ 0 */ + SERCOM6_1_IRQn = 71, /**< 71 SAME54N20A Serial Communication Interface 6 (SERCOM6) IRQ 1 */ + SERCOM6_2_IRQn = 72, /**< 72 SAME54N20A Serial Communication Interface 6 (SERCOM6) IRQ 2 */ + SERCOM6_3_IRQn = 73, /**< 73 SAME54N20A Serial Communication Interface 6 (SERCOM6) IRQ 3 */ + SERCOM7_0_IRQn = 74, /**< 74 SAME54N20A Serial Communication Interface 7 (SERCOM7) IRQ 0 */ + SERCOM7_1_IRQn = 75, /**< 75 SAME54N20A Serial Communication Interface 7 (SERCOM7) IRQ 1 */ + SERCOM7_2_IRQn = 76, /**< 76 SAME54N20A Serial Communication Interface 7 (SERCOM7) IRQ 2 */ + SERCOM7_3_IRQn = 77, /**< 77 SAME54N20A Serial Communication Interface 7 (SERCOM7) IRQ 3 */ + CAN0_IRQn = 78, /**< 78 SAME54N20A Control Area Network 0 (CAN0) */ + CAN1_IRQn = 79, /**< 79 SAME54N20A Control Area Network 1 (CAN1) */ + USB_0_IRQn = 80, /**< 80 SAME54N20A Universal Serial Bus (USB) IRQ 0 */ + USB_1_IRQn = 81, /**< 81 SAME54N20A Universal Serial Bus (USB) IRQ 1 */ + USB_2_IRQn = 82, /**< 82 SAME54N20A Universal Serial Bus (USB) IRQ 2 */ + USB_3_IRQn = 83, /**< 83 SAME54N20A Universal Serial Bus (USB) IRQ 3 */ + GMAC_IRQn = 84, /**< 84 SAME54N20A Ethernet MAC (GMAC) */ + TCC0_0_IRQn = 85, /**< 85 SAME54N20A Timer Counter Control 0 (TCC0) IRQ 0 */ + TCC0_1_IRQn = 86, /**< 86 SAME54N20A Timer Counter Control 0 (TCC0) IRQ 1 */ + TCC0_2_IRQn = 87, /**< 87 SAME54N20A Timer Counter Control 0 (TCC0) IRQ 2 */ + TCC0_3_IRQn = 88, /**< 88 SAME54N20A Timer Counter Control 0 (TCC0) IRQ 3 */ + TCC0_4_IRQn = 89, /**< 89 SAME54N20A Timer Counter Control 0 (TCC0) IRQ 4 */ + TCC0_5_IRQn = 90, /**< 90 SAME54N20A Timer Counter Control 0 (TCC0) IRQ 5 */ + TCC0_6_IRQn = 91, /**< 91 SAME54N20A Timer Counter Control 0 (TCC0) IRQ 6 */ + TCC1_0_IRQn = 92, /**< 92 SAME54N20A Timer Counter Control 1 (TCC1) IRQ 0 */ + TCC1_1_IRQn = 93, /**< 93 SAME54N20A Timer Counter Control 1 (TCC1) IRQ 1 */ + TCC1_2_IRQn = 94, /**< 94 SAME54N20A Timer Counter Control 1 (TCC1) IRQ 2 */ + TCC1_3_IRQn = 95, /**< 95 SAME54N20A Timer Counter Control 1 (TCC1) IRQ 3 */ + TCC1_4_IRQn = 96, /**< 96 SAME54N20A Timer Counter Control 1 (TCC1) IRQ 4 */ + TCC2_0_IRQn = 97, /**< 97 SAME54N20A Timer Counter Control 2 (TCC2) IRQ 0 */ + TCC2_1_IRQn = 98, /**< 98 SAME54N20A Timer Counter Control 2 (TCC2) IRQ 1 */ + TCC2_2_IRQn = 99, /**< 99 SAME54N20A Timer Counter Control 2 (TCC2) IRQ 2 */ + TCC2_3_IRQn = 100, /**< 100 SAME54N20A Timer Counter Control 2 (TCC2) IRQ 3 */ + TCC3_0_IRQn = 101, /**< 101 SAME54N20A Timer Counter Control 3 (TCC3) IRQ 0 */ + TCC3_1_IRQn = 102, /**< 102 SAME54N20A Timer Counter Control 3 (TCC3) IRQ 1 */ + TCC3_2_IRQn = 103, /**< 103 SAME54N20A Timer Counter Control 3 (TCC3) IRQ 2 */ + TCC4_0_IRQn = 104, /**< 104 SAME54N20A Timer Counter Control 4 (TCC4) IRQ 0 */ + TCC4_1_IRQn = 105, /**< 105 SAME54N20A Timer Counter Control 4 (TCC4) IRQ 1 */ + TCC4_2_IRQn = 106, /**< 106 SAME54N20A Timer Counter Control 4 (TCC4) IRQ 2 */ + TC0_IRQn = 107, /**< 107 SAME54N20A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 108, /**< 108 SAME54N20A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 109, /**< 109 SAME54N20A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 110, /**< 110 SAME54N20A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 111, /**< 111 SAME54N20A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 112, /**< 112 SAME54N20A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 113, /**< 113 SAME54N20A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 114, /**< 114 SAME54N20A Basic Timer Counter 7 (TC7) */ + PDEC_0_IRQn = 115, /**< 115 SAME54N20A Quadrature Decodeur (PDEC) IRQ 0 */ + PDEC_1_IRQn = 116, /**< 116 SAME54N20A Quadrature Decodeur (PDEC) IRQ 1 */ + PDEC_2_IRQn = 117, /**< 117 SAME54N20A Quadrature Decodeur (PDEC) IRQ 2 */ + ADC0_0_IRQn = 118, /**< 118 SAME54N20A Analog Digital Converter 0 (ADC0) IRQ 0 */ + ADC0_1_IRQn = 119, /**< 119 SAME54N20A Analog Digital Converter 0 (ADC0) IRQ 1 */ + ADC1_0_IRQn = 120, /**< 120 SAME54N20A Analog Digital Converter 1 (ADC1) IRQ 0 */ + ADC1_1_IRQn = 121, /**< 121 SAME54N20A Analog Digital Converter 1 (ADC1) IRQ 1 */ + AC_IRQn = 122, /**< 122 SAME54N20A Analog Comparators (AC) */ + DAC_0_IRQn = 123, /**< 123 SAME54N20A Digital-to-Analog Converter (DAC) IRQ 0 */ + DAC_1_IRQn = 124, /**< 124 SAME54N20A Digital-to-Analog Converter (DAC) IRQ 1 */ + DAC_2_IRQn = 125, /**< 125 SAME54N20A Digital-to-Analog Converter (DAC) IRQ 2 */ + DAC_3_IRQn = 126, /**< 126 SAME54N20A Digital-to-Analog Converter (DAC) IRQ 3 */ + DAC_4_IRQn = 127, /**< 127 SAME54N20A Digital-to-Analog Converter (DAC) IRQ 4 */ + I2S_IRQn = 128, /**< 128 SAME54N20A Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 SAME54N20A Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 SAME54N20A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 SAME54N20A True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 SAME54N20A Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 SAME54N20A PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 SAME54N20A Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SAME54N20A SD/MMC Host Controller 0 (SDHC0) */ + SDHC1_IRQn = 136, /**< 136 SAME54N20A SD/MMC Host Controller 1 (SDHC1) */ + + PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pfnMemManagement_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pfnDebugMonitor_Handler; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnMCLK_Handler; /* 1 Main Clock */ + void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ + void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ + void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ + void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ + void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ + void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ + void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ + void* pfnWDT_Handler; /* 10 Watchdog Timer */ + void* pfnRTC_Handler; /* 11 Real-Time Counter */ + void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ + void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ + void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ + void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ + void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ + void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ + void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ + void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ + void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ + void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ + void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ + void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ + void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ + void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ + void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ + void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ + void* pfnFREQM_Handler; /* 28 Frequency Meter */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ + void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ + void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ + void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ + void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ + void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ + void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ + void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ + void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ + void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */ + void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */ + void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */ + void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */ + void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */ + void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */ + void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */ + void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */ + void* pfnCAN0_Handler; /* 78 Control Area Network 0 */ + void* pfnCAN1_Handler; /* 79 Control Area Network 1 */ + void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ + void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ + void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ + void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ + void* pfnGMAC_Handler; /* 84 Ethernet MAC */ + void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ + void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ + void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ + void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ + void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ + void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ + void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ + void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ + void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ + void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ + void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ + void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ + void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ + void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ + void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ + void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ + void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ + void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ + void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ + void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ + void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ + void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */ + void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ + void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ + void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ + void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ + void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ + void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ + void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ + void* pfnAC_Handler; /* 122 Analog Comparators */ + void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ + void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ + void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ + void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ + void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 131 True Random Generator */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ + void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */ +} DeviceVectors; + +/* Cortex-M4 processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_0_Handler ( void ); +void OSCCTRL_1_Handler ( void ); +void OSCCTRL_2_Handler ( void ); +void OSCCTRL_3_Handler ( void ); +void OSCCTRL_4_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_0_Handler ( void ); +void SUPC_1_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_0_Handler ( void ); +void EIC_1_Handler ( void ); +void EIC_2_Handler ( void ); +void EIC_3_Handler ( void ); +void EIC_4_Handler ( void ); +void EIC_5_Handler ( void ); +void EIC_6_Handler ( void ); +void EIC_7_Handler ( void ); +void EIC_8_Handler ( void ); +void EIC_9_Handler ( void ); +void EIC_10_Handler ( void ); +void EIC_11_Handler ( void ); +void EIC_12_Handler ( void ); +void EIC_13_Handler ( void ); +void EIC_14_Handler ( void ); +void EIC_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_4_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_4_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_3_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_3_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_3_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_3_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_3_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_3_Handler ( void ); +void SERCOM6_0_Handler ( void ); +void SERCOM6_1_Handler ( void ); +void SERCOM6_2_Handler ( void ); +void SERCOM6_3_Handler ( void ); +void SERCOM7_0_Handler ( void ); +void SERCOM7_1_Handler ( void ); +void SERCOM7_2_Handler ( void ); +void SERCOM7_3_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void USB_0_Handler ( void ); +void USB_1_Handler ( void ); +void USB_2_Handler ( void ); +void USB_3_Handler ( void ); +void GMAC_Handler ( void ); +void TCC0_0_Handler ( void ); +void TCC0_1_Handler ( void ); +void TCC0_2_Handler ( void ); +void TCC0_3_Handler ( void ); +void TCC0_4_Handler ( void ); +void TCC0_5_Handler ( void ); +void TCC0_6_Handler ( void ); +void TCC1_0_Handler ( void ); +void TCC1_1_Handler ( void ); +void TCC1_2_Handler ( void ); +void TCC1_3_Handler ( void ); +void TCC1_4_Handler ( void ); +void TCC2_0_Handler ( void ); +void TCC2_1_Handler ( void ); +void TCC2_2_Handler ( void ); +void TCC2_3_Handler ( void ); +void TCC3_0_Handler ( void ); +void TCC3_1_Handler ( void ); +void TCC3_2_Handler ( void ); +void TCC4_0_Handler ( void ); +void TCC4_1_Handler ( void ); +void TCC4_2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void PDEC_0_Handler ( void ); +void PDEC_1_Handler ( void ); +void PDEC_2_Handler ( void ); +void ADC0_0_Handler ( void ); +void ADC0_1_Handler ( void ); +void ADC1_0_Handler ( void ); +void ADC1_1_Handler ( void ); +void AC_Handler ( void ); +void DAC_0_Handler ( void ); +void DAC_1_Handler ( void ); +void DAC_2_Handler ( void ); +void DAC_3_Handler ( void ); +void DAC_4_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +void SDHC1_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +#define __CM4_REV 1 /*!< Core revision r0p1 */ +#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ +#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same54.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME54N20A */ +/* ************************************************************************** */ +/** \defgroup SAME54N20A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/gmac.h" +#include "component/hmatrixb.h" +#include "component/icm.h" +#include "component/i2s.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAME54N20A */ +/* ************************************************************************** */ +/** \defgroup SAME54N20A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/aes.h" +#include "instance/can0.h" +#include "instance/can1.h" +#include "instance/ccl.h" +#include "instance/cmcc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/gmac.h" +#include "instance/hmatrix.h" +#include "instance/icm.h" +#include "instance/i2s.h" +#include "instance/mclk.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pcc.h" +#include "instance/pdec.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/pukcc.h" +#include "instance/qspi.h" +#include "instance/ramecc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdhc0.h" +#include "instance/sdhc1.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sercom6.h" +#include "instance/sercom7.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tcc3.h" +#include "instance/tcc4.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAME54N20A */ +/* ************************************************************************** */ +/** \defgroup SAME54N20A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT 36 /**< \brief Port Module (PORT) */ +#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ + +// Peripheral instances on HPB2 bridge +#define ID_CAN0 64 /**< \brief Control Area Network 0 (CAN0) */ +#define ID_CAN1 65 /**< \brief Control Area Network 1 (CAN1) */ +#define ID_GMAC 66 /**< \brief Ethernet MAC (GMAC) */ +#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ +#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC 72 /**< \brief Analog Comparators (AC) */ +#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ +#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB3 bridge +#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */ +#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */ +#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ +#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ + +// Peripheral instances on AHB (as if on bridge 4) +#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ +#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAME54N20A */ +/* ************************************************************************** */ +/** \defgroup SAME54N20A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42002000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ +#define AES (0x42002400) /**< \brief (AES) APB Base Address */ +#define CAN0 (0x42000000) /**< \brief (CAN0) APB Base Address */ +#define CAN1 (0x42000400) /**< \brief (CAN1) APB Base Address */ +#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ +#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ +#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define GMAC (0x42000800) /**< \brief (GMAC) APB Base Address */ +#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ +#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ +#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ +#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ +#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ +#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ +#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */ +#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ +#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ +#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ +#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CAN0 ((Can *)0x42000000UL) /**< \brief (CAN0) APB Base Address */ +#define CAN1 ((Can *)0x42000400UL) /**< \brief (CAN1) APB Base Address */ +#define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */ +#define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */ + +#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ +#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ +#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ + +#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define GMAC ((Gmac *)0x42000800UL) /**< \brief (GMAC) APB Base Address */ +#define GMAC_INST_NUM 1 /**< \brief (GMAC) Number of instances */ +#define GMAC_INSTS { GMAC } /**< \brief (GMAC) Instances List */ + +#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ + +#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ +#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ +#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ + +#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ +#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ +#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ +#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ +#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ + +#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ + +#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ +#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ +#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */ +#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */ +#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */ + +#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */ +#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ +#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ +#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAME54N20A */ +/* ************************************************************************** */ +/** \defgroup SAME54N20A_port PORT Definitions */ +/*@{*/ + +#include "pio/same54n20a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAME54N20A */ +/* ************************************************************************** */ + +#define HSRAM_SIZE _UL_(0x00040000) /* 256 kB */ +#define FLASH_SIZE _UL_(0x00100000) /* 1024 kB */ +#define FLASH_PAGE_SIZE 512 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 512 +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x61840302) +#define ADC0_TOUCH_LINES_NUM 32 +#define PORT_GROUPS 3 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME54N20A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAME54N20A_H */ diff --git a/software/firmware/oracle_same54n19a/include/same54p19a.h b/software/firmware/oracle_same54n19a/include/same54p19a.h new file mode 100644 index 00000000..ed3ae044 --- /dev/null +++ b/software/firmware/oracle_same54n19a/include/same54p19a.h @@ -0,0 +1,1085 @@ +/** + * \file + * + * \brief Header file for SAME54P19A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54P19A_ +#define _SAME54P19A_ + +/** + * \ingroup SAME54_definitions + * \addtogroup SAME54P19A_definitions SAME54P19A definitions + * This file defines all structures and symbols for SAME54P19A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAME54P19A */ +/* ************************************************************************** */ +/** \defgroup SAME54P19A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */ + BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAME54P19A-specific Interrupt Numbers *********************/ + PM_IRQn = 0, /**< 0 SAME54P19A Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 SAME54P19A Main Clock (MCLK) */ + OSCCTRL_0_IRQn = 2, /**< 2 SAME54P19A Oscillators Control (OSCCTRL) IRQ 0 */ + OSCCTRL_1_IRQn = 3, /**< 3 SAME54P19A Oscillators Control (OSCCTRL) IRQ 1 */ + OSCCTRL_2_IRQn = 4, /**< 4 SAME54P19A Oscillators Control (OSCCTRL) IRQ 2 */ + OSCCTRL_3_IRQn = 5, /**< 5 SAME54P19A Oscillators Control (OSCCTRL) IRQ 3 */ + OSCCTRL_4_IRQn = 6, /**< 6 SAME54P19A Oscillators Control (OSCCTRL) IRQ 4 */ + OSC32KCTRL_IRQn = 7, /**< 7 SAME54P19A 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_0_IRQn = 8, /**< 8 SAME54P19A Supply Controller (SUPC) IRQ 0 */ + SUPC_1_IRQn = 9, /**< 9 SAME54P19A Supply Controller (SUPC) IRQ 1 */ + WDT_IRQn = 10, /**< 10 SAME54P19A Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 SAME54P19A Real-Time Counter (RTC) */ + EIC_0_IRQn = 12, /**< 12 SAME54P19A External Interrupt Controller (EIC) IRQ 0 */ + EIC_1_IRQn = 13, /**< 13 SAME54P19A External Interrupt Controller (EIC) IRQ 1 */ + EIC_2_IRQn = 14, /**< 14 SAME54P19A External Interrupt Controller (EIC) IRQ 2 */ + EIC_3_IRQn = 15, /**< 15 SAME54P19A External Interrupt Controller (EIC) IRQ 3 */ + EIC_4_IRQn = 16, /**< 16 SAME54P19A External Interrupt Controller (EIC) IRQ 4 */ + EIC_5_IRQn = 17, /**< 17 SAME54P19A External Interrupt Controller (EIC) IRQ 5 */ + EIC_6_IRQn = 18, /**< 18 SAME54P19A External Interrupt Controller (EIC) IRQ 6 */ + EIC_7_IRQn = 19, /**< 19 SAME54P19A External Interrupt Controller (EIC) IRQ 7 */ + EIC_8_IRQn = 20, /**< 20 SAME54P19A External Interrupt Controller (EIC) IRQ 8 */ + EIC_9_IRQn = 21, /**< 21 SAME54P19A External Interrupt Controller (EIC) IRQ 9 */ + EIC_10_IRQn = 22, /**< 22 SAME54P19A External Interrupt Controller (EIC) IRQ 10 */ + EIC_11_IRQn = 23, /**< 23 SAME54P19A External Interrupt Controller (EIC) IRQ 11 */ + EIC_12_IRQn = 24, /**< 24 SAME54P19A External Interrupt Controller (EIC) IRQ 12 */ + EIC_13_IRQn = 25, /**< 25 SAME54P19A External Interrupt Controller (EIC) IRQ 13 */ + EIC_14_IRQn = 26, /**< 26 SAME54P19A External Interrupt Controller (EIC) IRQ 14 */ + EIC_15_IRQn = 27, /**< 27 SAME54P19A External Interrupt Controller (EIC) IRQ 15 */ + FREQM_IRQn = 28, /**< 28 SAME54P19A Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 SAME54P19A Non-Volatile Memory Controller (NVMCTRL) IRQ 0 */ + NVMCTRL_1_IRQn = 30, /**< 30 SAME54P19A Non-Volatile Memory Controller (NVMCTRL) IRQ 1 */ + DMAC_0_IRQn = 31, /**< 31 SAME54P19A Direct Memory Access Controller (DMAC) IRQ 0 */ + DMAC_1_IRQn = 32, /**< 32 SAME54P19A Direct Memory Access Controller (DMAC) IRQ 1 */ + DMAC_2_IRQn = 33, /**< 33 SAME54P19A Direct Memory Access Controller (DMAC) IRQ 2 */ + DMAC_3_IRQn = 34, /**< 34 SAME54P19A Direct Memory Access Controller (DMAC) IRQ 3 */ + DMAC_4_IRQn = 35, /**< 35 SAME54P19A Direct Memory Access Controller (DMAC) IRQ 4 */ + EVSYS_0_IRQn = 36, /**< 36 SAME54P19A Event System Interface (EVSYS) IRQ 0 */ + EVSYS_1_IRQn = 37, /**< 37 SAME54P19A Event System Interface (EVSYS) IRQ 1 */ + EVSYS_2_IRQn = 38, /**< 38 SAME54P19A Event System Interface (EVSYS) IRQ 2 */ + EVSYS_3_IRQn = 39, /**< 39 SAME54P19A Event System Interface (EVSYS) IRQ 3 */ + EVSYS_4_IRQn = 40, /**< 40 SAME54P19A Event System Interface (EVSYS) IRQ 4 */ + PAC_IRQn = 41, /**< 41 SAME54P19A Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /**< 45 SAME54P19A RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 SAME54P19A Serial Communication Interface 0 (SERCOM0) IRQ 0 */ + SERCOM0_1_IRQn = 47, /**< 47 SAME54P19A Serial Communication Interface 0 (SERCOM0) IRQ 1 */ + SERCOM0_2_IRQn = 48, /**< 48 SAME54P19A Serial Communication Interface 0 (SERCOM0) IRQ 2 */ + SERCOM0_3_IRQn = 49, /**< 49 SAME54P19A Serial Communication Interface 0 (SERCOM0) IRQ 3 */ + SERCOM1_0_IRQn = 50, /**< 50 SAME54P19A Serial Communication Interface 1 (SERCOM1) IRQ 0 */ + SERCOM1_1_IRQn = 51, /**< 51 SAME54P19A Serial Communication Interface 1 (SERCOM1) IRQ 1 */ + SERCOM1_2_IRQn = 52, /**< 52 SAME54P19A Serial Communication Interface 1 (SERCOM1) IRQ 2 */ + SERCOM1_3_IRQn = 53, /**< 53 SAME54P19A Serial Communication Interface 1 (SERCOM1) IRQ 3 */ + SERCOM2_0_IRQn = 54, /**< 54 SAME54P19A Serial Communication Interface 2 (SERCOM2) IRQ 0 */ + SERCOM2_1_IRQn = 55, /**< 55 SAME54P19A Serial Communication Interface 2 (SERCOM2) IRQ 1 */ + SERCOM2_2_IRQn = 56, /**< 56 SAME54P19A Serial Communication Interface 2 (SERCOM2) IRQ 2 */ + SERCOM2_3_IRQn = 57, /**< 57 SAME54P19A Serial Communication Interface 2 (SERCOM2) IRQ 3 */ + SERCOM3_0_IRQn = 58, /**< 58 SAME54P19A Serial Communication Interface 3 (SERCOM3) IRQ 0 */ + SERCOM3_1_IRQn = 59, /**< 59 SAME54P19A Serial Communication Interface 3 (SERCOM3) IRQ 1 */ + SERCOM3_2_IRQn = 60, /**< 60 SAME54P19A Serial Communication Interface 3 (SERCOM3) IRQ 2 */ + SERCOM3_3_IRQn = 61, /**< 61 SAME54P19A Serial Communication Interface 3 (SERCOM3) IRQ 3 */ + SERCOM4_0_IRQn = 62, /**< 62 SAME54P19A Serial Communication Interface 4 (SERCOM4) IRQ 0 */ + SERCOM4_1_IRQn = 63, /**< 63 SAME54P19A Serial Communication Interface 4 (SERCOM4) IRQ 1 */ + SERCOM4_2_IRQn = 64, /**< 64 SAME54P19A Serial Communication Interface 4 (SERCOM4) IRQ 2 */ + SERCOM4_3_IRQn = 65, /**< 65 SAME54P19A Serial Communication Interface 4 (SERCOM4) IRQ 3 */ + SERCOM5_0_IRQn = 66, /**< 66 SAME54P19A Serial Communication Interface 5 (SERCOM5) IRQ 0 */ + SERCOM5_1_IRQn = 67, /**< 67 SAME54P19A Serial Communication Interface 5 (SERCOM5) IRQ 1 */ + SERCOM5_2_IRQn = 68, /**< 68 SAME54P19A Serial Communication Interface 5 (SERCOM5) IRQ 2 */ + SERCOM5_3_IRQn = 69, /**< 69 SAME54P19A Serial Communication Interface 5 (SERCOM5) IRQ 3 */ + SERCOM6_0_IRQn = 70, /**< 70 SAME54P19A Serial Communication Interface 6 (SERCOM6) IRQ 0 */ + SERCOM6_1_IRQn = 71, /**< 71 SAME54P19A Serial Communication Interface 6 (SERCOM6) IRQ 1 */ + SERCOM6_2_IRQn = 72, /**< 72 SAME54P19A Serial Communication Interface 6 (SERCOM6) IRQ 2 */ + SERCOM6_3_IRQn = 73, /**< 73 SAME54P19A Serial Communication Interface 6 (SERCOM6) IRQ 3 */ + SERCOM7_0_IRQn = 74, /**< 74 SAME54P19A Serial Communication Interface 7 (SERCOM7) IRQ 0 */ + SERCOM7_1_IRQn = 75, /**< 75 SAME54P19A Serial Communication Interface 7 (SERCOM7) IRQ 1 */ + SERCOM7_2_IRQn = 76, /**< 76 SAME54P19A Serial Communication Interface 7 (SERCOM7) IRQ 2 */ + SERCOM7_3_IRQn = 77, /**< 77 SAME54P19A Serial Communication Interface 7 (SERCOM7) IRQ 3 */ + CAN0_IRQn = 78, /**< 78 SAME54P19A Control Area Network 0 (CAN0) */ + CAN1_IRQn = 79, /**< 79 SAME54P19A Control Area Network 1 (CAN1) */ + USB_0_IRQn = 80, /**< 80 SAME54P19A Universal Serial Bus (USB) IRQ 0 */ + USB_1_IRQn = 81, /**< 81 SAME54P19A Universal Serial Bus (USB) IRQ 1 */ + USB_2_IRQn = 82, /**< 82 SAME54P19A Universal Serial Bus (USB) IRQ 2 */ + USB_3_IRQn = 83, /**< 83 SAME54P19A Universal Serial Bus (USB) IRQ 3 */ + GMAC_IRQn = 84, /**< 84 SAME54P19A Ethernet MAC (GMAC) */ + TCC0_0_IRQn = 85, /**< 85 SAME54P19A Timer Counter Control 0 (TCC0) IRQ 0 */ + TCC0_1_IRQn = 86, /**< 86 SAME54P19A Timer Counter Control 0 (TCC0) IRQ 1 */ + TCC0_2_IRQn = 87, /**< 87 SAME54P19A Timer Counter Control 0 (TCC0) IRQ 2 */ + TCC0_3_IRQn = 88, /**< 88 SAME54P19A Timer Counter Control 0 (TCC0) IRQ 3 */ + TCC0_4_IRQn = 89, /**< 89 SAME54P19A Timer Counter Control 0 (TCC0) IRQ 4 */ + TCC0_5_IRQn = 90, /**< 90 SAME54P19A Timer Counter Control 0 (TCC0) IRQ 5 */ + TCC0_6_IRQn = 91, /**< 91 SAME54P19A Timer Counter Control 0 (TCC0) IRQ 6 */ + TCC1_0_IRQn = 92, /**< 92 SAME54P19A Timer Counter Control 1 (TCC1) IRQ 0 */ + TCC1_1_IRQn = 93, /**< 93 SAME54P19A Timer Counter Control 1 (TCC1) IRQ 1 */ + TCC1_2_IRQn = 94, /**< 94 SAME54P19A Timer Counter Control 1 (TCC1) IRQ 2 */ + TCC1_3_IRQn = 95, /**< 95 SAME54P19A Timer Counter Control 1 (TCC1) IRQ 3 */ + TCC1_4_IRQn = 96, /**< 96 SAME54P19A Timer Counter Control 1 (TCC1) IRQ 4 */ + TCC2_0_IRQn = 97, /**< 97 SAME54P19A Timer Counter Control 2 (TCC2) IRQ 0 */ + TCC2_1_IRQn = 98, /**< 98 SAME54P19A Timer Counter Control 2 (TCC2) IRQ 1 */ + TCC2_2_IRQn = 99, /**< 99 SAME54P19A Timer Counter Control 2 (TCC2) IRQ 2 */ + TCC2_3_IRQn = 100, /**< 100 SAME54P19A Timer Counter Control 2 (TCC2) IRQ 3 */ + TCC3_0_IRQn = 101, /**< 101 SAME54P19A Timer Counter Control 3 (TCC3) IRQ 0 */ + TCC3_1_IRQn = 102, /**< 102 SAME54P19A Timer Counter Control 3 (TCC3) IRQ 1 */ + TCC3_2_IRQn = 103, /**< 103 SAME54P19A Timer Counter Control 3 (TCC3) IRQ 2 */ + TCC4_0_IRQn = 104, /**< 104 SAME54P19A Timer Counter Control 4 (TCC4) IRQ 0 */ + TCC4_1_IRQn = 105, /**< 105 SAME54P19A Timer Counter Control 4 (TCC4) IRQ 1 */ + TCC4_2_IRQn = 106, /**< 106 SAME54P19A Timer Counter Control 4 (TCC4) IRQ 2 */ + TC0_IRQn = 107, /**< 107 SAME54P19A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 108, /**< 108 SAME54P19A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 109, /**< 109 SAME54P19A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 110, /**< 110 SAME54P19A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 111, /**< 111 SAME54P19A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 112, /**< 112 SAME54P19A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 113, /**< 113 SAME54P19A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 114, /**< 114 SAME54P19A Basic Timer Counter 7 (TC7) */ + PDEC_0_IRQn = 115, /**< 115 SAME54P19A Quadrature Decodeur (PDEC) IRQ 0 */ + PDEC_1_IRQn = 116, /**< 116 SAME54P19A Quadrature Decodeur (PDEC) IRQ 1 */ + PDEC_2_IRQn = 117, /**< 117 SAME54P19A Quadrature Decodeur (PDEC) IRQ 2 */ + ADC0_0_IRQn = 118, /**< 118 SAME54P19A Analog Digital Converter 0 (ADC0) IRQ 0 */ + ADC0_1_IRQn = 119, /**< 119 SAME54P19A Analog Digital Converter 0 (ADC0) IRQ 1 */ + ADC1_0_IRQn = 120, /**< 120 SAME54P19A Analog Digital Converter 1 (ADC1) IRQ 0 */ + ADC1_1_IRQn = 121, /**< 121 SAME54P19A Analog Digital Converter 1 (ADC1) IRQ 1 */ + AC_IRQn = 122, /**< 122 SAME54P19A Analog Comparators (AC) */ + DAC_0_IRQn = 123, /**< 123 SAME54P19A Digital-to-Analog Converter (DAC) IRQ 0 */ + DAC_1_IRQn = 124, /**< 124 SAME54P19A Digital-to-Analog Converter (DAC) IRQ 1 */ + DAC_2_IRQn = 125, /**< 125 SAME54P19A Digital-to-Analog Converter (DAC) IRQ 2 */ + DAC_3_IRQn = 126, /**< 126 SAME54P19A Digital-to-Analog Converter (DAC) IRQ 3 */ + DAC_4_IRQn = 127, /**< 127 SAME54P19A Digital-to-Analog Converter (DAC) IRQ 4 */ + I2S_IRQn = 128, /**< 128 SAME54P19A Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 SAME54P19A Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 SAME54P19A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 SAME54P19A True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 SAME54P19A Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 SAME54P19A PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 SAME54P19A Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SAME54P19A SD/MMC Host Controller 0 (SDHC0) */ + SDHC1_IRQn = 136, /**< 136 SAME54P19A SD/MMC Host Controller 1 (SDHC1) */ + + PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pfnMemManagement_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pfnDebugMonitor_Handler; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnMCLK_Handler; /* 1 Main Clock */ + void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ + void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ + void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ + void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ + void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ + void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ + void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ + void* pfnWDT_Handler; /* 10 Watchdog Timer */ + void* pfnRTC_Handler; /* 11 Real-Time Counter */ + void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ + void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ + void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ + void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ + void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ + void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ + void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ + void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ + void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ + void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ + void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ + void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ + void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ + void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ + void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ + void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ + void* pfnFREQM_Handler; /* 28 Frequency Meter */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ + void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ + void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ + void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ + void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ + void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ + void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ + void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ + void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ + void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */ + void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */ + void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */ + void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */ + void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */ + void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */ + void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */ + void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */ + void* pfnCAN0_Handler; /* 78 Control Area Network 0 */ + void* pfnCAN1_Handler; /* 79 Control Area Network 1 */ + void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ + void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ + void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ + void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ + void* pfnGMAC_Handler; /* 84 Ethernet MAC */ + void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ + void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ + void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ + void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ + void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ + void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ + void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ + void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ + void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ + void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ + void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ + void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ + void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ + void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ + void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ + void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ + void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ + void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ + void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ + void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ + void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ + void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */ + void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ + void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ + void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ + void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ + void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ + void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ + void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ + void* pfnAC_Handler; /* 122 Analog Comparators */ + void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ + void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ + void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ + void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ + void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 131 True Random Generator */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ + void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */ +} DeviceVectors; + +/* Cortex-M4 processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_0_Handler ( void ); +void OSCCTRL_1_Handler ( void ); +void OSCCTRL_2_Handler ( void ); +void OSCCTRL_3_Handler ( void ); +void OSCCTRL_4_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_0_Handler ( void ); +void SUPC_1_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_0_Handler ( void ); +void EIC_1_Handler ( void ); +void EIC_2_Handler ( void ); +void EIC_3_Handler ( void ); +void EIC_4_Handler ( void ); +void EIC_5_Handler ( void ); +void EIC_6_Handler ( void ); +void EIC_7_Handler ( void ); +void EIC_8_Handler ( void ); +void EIC_9_Handler ( void ); +void EIC_10_Handler ( void ); +void EIC_11_Handler ( void ); +void EIC_12_Handler ( void ); +void EIC_13_Handler ( void ); +void EIC_14_Handler ( void ); +void EIC_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_4_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_4_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_3_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_3_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_3_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_3_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_3_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_3_Handler ( void ); +void SERCOM6_0_Handler ( void ); +void SERCOM6_1_Handler ( void ); +void SERCOM6_2_Handler ( void ); +void SERCOM6_3_Handler ( void ); +void SERCOM7_0_Handler ( void ); +void SERCOM7_1_Handler ( void ); +void SERCOM7_2_Handler ( void ); +void SERCOM7_3_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void USB_0_Handler ( void ); +void USB_1_Handler ( void ); +void USB_2_Handler ( void ); +void USB_3_Handler ( void ); +void GMAC_Handler ( void ); +void TCC0_0_Handler ( void ); +void TCC0_1_Handler ( void ); +void TCC0_2_Handler ( void ); +void TCC0_3_Handler ( void ); +void TCC0_4_Handler ( void ); +void TCC0_5_Handler ( void ); +void TCC0_6_Handler ( void ); +void TCC1_0_Handler ( void ); +void TCC1_1_Handler ( void ); +void TCC1_2_Handler ( void ); +void TCC1_3_Handler ( void ); +void TCC1_4_Handler ( void ); +void TCC2_0_Handler ( void ); +void TCC2_1_Handler ( void ); +void TCC2_2_Handler ( void ); +void TCC2_3_Handler ( void ); +void TCC3_0_Handler ( void ); +void TCC3_1_Handler ( void ); +void TCC3_2_Handler ( void ); +void TCC4_0_Handler ( void ); +void TCC4_1_Handler ( void ); +void TCC4_2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void PDEC_0_Handler ( void ); +void PDEC_1_Handler ( void ); +void PDEC_2_Handler ( void ); +void ADC0_0_Handler ( void ); +void ADC0_1_Handler ( void ); +void ADC1_0_Handler ( void ); +void ADC1_1_Handler ( void ); +void AC_Handler ( void ); +void DAC_0_Handler ( void ); +void DAC_1_Handler ( void ); +void DAC_2_Handler ( void ); +void DAC_3_Handler ( void ); +void DAC_4_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +void SDHC1_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +#define __CM4_REV 1 /*!< Core revision r0p1 */ +#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ +#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same54.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME54P19A */ +/* ************************************************************************** */ +/** \defgroup SAME54P19A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/gmac.h" +#include "component/hmatrixb.h" +#include "component/icm.h" +#include "component/i2s.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAME54P19A */ +/* ************************************************************************** */ +/** \defgroup SAME54P19A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/aes.h" +#include "instance/can0.h" +#include "instance/can1.h" +#include "instance/ccl.h" +#include "instance/cmcc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/gmac.h" +#include "instance/hmatrix.h" +#include "instance/icm.h" +#include "instance/i2s.h" +#include "instance/mclk.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pcc.h" +#include "instance/pdec.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/pukcc.h" +#include "instance/qspi.h" +#include "instance/ramecc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdhc0.h" +#include "instance/sdhc1.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sercom6.h" +#include "instance/sercom7.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tcc3.h" +#include "instance/tcc4.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAME54P19A */ +/* ************************************************************************** */ +/** \defgroup SAME54P19A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT 36 /**< \brief Port Module (PORT) */ +#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ + +// Peripheral instances on HPB2 bridge +#define ID_CAN0 64 /**< \brief Control Area Network 0 (CAN0) */ +#define ID_CAN1 65 /**< \brief Control Area Network 1 (CAN1) */ +#define ID_GMAC 66 /**< \brief Ethernet MAC (GMAC) */ +#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ +#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC 72 /**< \brief Analog Comparators (AC) */ +#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ +#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB3 bridge +#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */ +#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */ +#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ +#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ + +// Peripheral instances on AHB (as if on bridge 4) +#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ +#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAME54P19A */ +/* ************************************************************************** */ +/** \defgroup SAME54P19A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42002000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ +#define AES (0x42002400) /**< \brief (AES) APB Base Address */ +#define CAN0 (0x42000000) /**< \brief (CAN0) APB Base Address */ +#define CAN1 (0x42000400) /**< \brief (CAN1) APB Base Address */ +#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ +#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ +#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define GMAC (0x42000800) /**< \brief (GMAC) APB Base Address */ +#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ +#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ +#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ +#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ +#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ +#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ +#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */ +#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ +#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ +#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ +#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CAN0 ((Can *)0x42000000UL) /**< \brief (CAN0) APB Base Address */ +#define CAN1 ((Can *)0x42000400UL) /**< \brief (CAN1) APB Base Address */ +#define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */ +#define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */ + +#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ +#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ +#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ + +#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define GMAC ((Gmac *)0x42000800UL) /**< \brief (GMAC) APB Base Address */ +#define GMAC_INST_NUM 1 /**< \brief (GMAC) Number of instances */ +#define GMAC_INSTS { GMAC } /**< \brief (GMAC) Instances List */ + +#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ + +#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ +#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ +#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ + +#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ +#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ +#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ +#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ +#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ + +#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ + +#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ +#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ +#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */ +#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */ +#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */ + +#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */ +#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ +#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ +#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAME54P19A */ +/* ************************************************************************** */ +/** \defgroup SAME54P19A_port PORT Definitions */ +/*@{*/ + +#include "pio/same54p19a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAME54P19A */ +/* ************************************************************************** */ + +#define HSRAM_SIZE _UL_(0x00030000) /* 192 kB */ +#define FLASH_SIZE _UL_(0x00080000) /* 512 kB */ +#define FLASH_PAGE_SIZE 512 +#define FLASH_NB_OF_PAGES 1024 +#define FLASH_USER_PAGE_SIZE 512 +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x61840301) +#define ADC0_TOUCH_LINES_NUM 32 +#define PORT_GROUPS 4 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME54P19A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAME54P19A_H */ diff --git a/software/firmware/oracle_same54n19a/include/same54p20a.h b/software/firmware/oracle_same54n19a/include/same54p20a.h new file mode 100644 index 00000000..2446095b --- /dev/null +++ b/software/firmware/oracle_same54n19a/include/same54p20a.h @@ -0,0 +1,1085 @@ +/** + * \file + * + * \brief Header file for SAME54P20A + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SAME54P20A_ +#define _SAME54P20A_ + +/** + * \ingroup SAME54_definitions + * \addtogroup SAME54P20A_definitions SAME54P20A definitions + * This file defines all structures and symbols for SAME54P20A: + * - registers and bitfields + * - peripheral base address + * - peripheral ID + * - PIO definitions +*/ +/*@{*/ + +#ifdef __cplusplus + extern "C" { +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +#include +#ifndef __cplusplus +typedef volatile const uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile const uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile const uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#else +typedef volatile uint32_t RoReg; /**< Read only 32-bit register (volatile const unsigned int) */ +typedef volatile uint16_t RoReg16; /**< Read only 16-bit register (volatile const unsigned int) */ +typedef volatile uint8_t RoReg8; /**< Read only 8-bit register (volatile const unsigned int) */ +#endif +typedef volatile uint32_t WoReg; /**< Write only 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t WoReg16; /**< Write only 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t WoReg8; /**< Write only 8-bit register (volatile unsigned int) */ +typedef volatile uint32_t RwReg; /**< Read-Write 32-bit register (volatile unsigned int) */ +typedef volatile uint16_t RwReg16; /**< Read-Write 16-bit register (volatile unsigned int) */ +typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volatile unsigned int) */ +#endif + +#if !defined(SKIP_INTEGER_LITERALS) +#if defined(_U_) || defined(_L_) || defined(_UL_) + #error "Integer Literals macros already defined elsewhere" +#endif + +#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) +/* Macros that deal with adding suffixes to integer literal constants for C/C++ */ +#define _U_(x) x ## U /**< C code: Unsigned integer literal constant value */ +#define _L_(x) x ## L /**< C code: Long integer literal constant value */ +#define _UL_(x) x ## UL /**< C code: Unsigned Long integer literal constant value */ +#else /* Assembler */ +#define _U_(x) x /**< Assembler: Unsigned integer literal constant value */ +#define _L_(x) x /**< Assembler: Long integer literal constant value */ +#define _UL_(x) x /**< Assembler: Unsigned Long integer literal constant value */ +#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +#endif /* SKIP_INTEGER_LITERALS */ + +/* ************************************************************************** */ +/** CMSIS DEFINITIONS FOR SAME54P20A */ +/* ************************************************************************** */ +/** \defgroup SAME54P20A_cmsis CMSIS Definitions */ +/*@{*/ + +/** Interrupt Number Definition */ +typedef enum IRQn +{ + /****** Cortex-M4 Processor Exceptions Numbers *******************/ + NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13,/**< 3 Hard Fault Interrupt */ + MemoryManagement_IRQn = -12,/**< 4 Memory Management Interrupt */ + BusFault_IRQn = -11,/**< 5 Bus Fault Interrupt */ + UsageFault_IRQn = -10,/**< 6 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< 11 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< 12 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< 14 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< 15 System Tick Interrupt */ + /****** SAME54P20A-specific Interrupt Numbers *********************/ + PM_IRQn = 0, /**< 0 SAME54P20A Power Manager (PM) */ + MCLK_IRQn = 1, /**< 1 SAME54P20A Main Clock (MCLK) */ + OSCCTRL_0_IRQn = 2, /**< 2 SAME54P20A Oscillators Control (OSCCTRL) IRQ 0 */ + OSCCTRL_1_IRQn = 3, /**< 3 SAME54P20A Oscillators Control (OSCCTRL) IRQ 1 */ + OSCCTRL_2_IRQn = 4, /**< 4 SAME54P20A Oscillators Control (OSCCTRL) IRQ 2 */ + OSCCTRL_3_IRQn = 5, /**< 5 SAME54P20A Oscillators Control (OSCCTRL) IRQ 3 */ + OSCCTRL_4_IRQn = 6, /**< 6 SAME54P20A Oscillators Control (OSCCTRL) IRQ 4 */ + OSC32KCTRL_IRQn = 7, /**< 7 SAME54P20A 32kHz Oscillators Control (OSC32KCTRL) */ + SUPC_0_IRQn = 8, /**< 8 SAME54P20A Supply Controller (SUPC) IRQ 0 */ + SUPC_1_IRQn = 9, /**< 9 SAME54P20A Supply Controller (SUPC) IRQ 1 */ + WDT_IRQn = 10, /**< 10 SAME54P20A Watchdog Timer (WDT) */ + RTC_IRQn = 11, /**< 11 SAME54P20A Real-Time Counter (RTC) */ + EIC_0_IRQn = 12, /**< 12 SAME54P20A External Interrupt Controller (EIC) IRQ 0 */ + EIC_1_IRQn = 13, /**< 13 SAME54P20A External Interrupt Controller (EIC) IRQ 1 */ + EIC_2_IRQn = 14, /**< 14 SAME54P20A External Interrupt Controller (EIC) IRQ 2 */ + EIC_3_IRQn = 15, /**< 15 SAME54P20A External Interrupt Controller (EIC) IRQ 3 */ + EIC_4_IRQn = 16, /**< 16 SAME54P20A External Interrupt Controller (EIC) IRQ 4 */ + EIC_5_IRQn = 17, /**< 17 SAME54P20A External Interrupt Controller (EIC) IRQ 5 */ + EIC_6_IRQn = 18, /**< 18 SAME54P20A External Interrupt Controller (EIC) IRQ 6 */ + EIC_7_IRQn = 19, /**< 19 SAME54P20A External Interrupt Controller (EIC) IRQ 7 */ + EIC_8_IRQn = 20, /**< 20 SAME54P20A External Interrupt Controller (EIC) IRQ 8 */ + EIC_9_IRQn = 21, /**< 21 SAME54P20A External Interrupt Controller (EIC) IRQ 9 */ + EIC_10_IRQn = 22, /**< 22 SAME54P20A External Interrupt Controller (EIC) IRQ 10 */ + EIC_11_IRQn = 23, /**< 23 SAME54P20A External Interrupt Controller (EIC) IRQ 11 */ + EIC_12_IRQn = 24, /**< 24 SAME54P20A External Interrupt Controller (EIC) IRQ 12 */ + EIC_13_IRQn = 25, /**< 25 SAME54P20A External Interrupt Controller (EIC) IRQ 13 */ + EIC_14_IRQn = 26, /**< 26 SAME54P20A External Interrupt Controller (EIC) IRQ 14 */ + EIC_15_IRQn = 27, /**< 27 SAME54P20A External Interrupt Controller (EIC) IRQ 15 */ + FREQM_IRQn = 28, /**< 28 SAME54P20A Frequency Meter (FREQM) */ + NVMCTRL_0_IRQn = 29, /**< 29 SAME54P20A Non-Volatile Memory Controller (NVMCTRL) IRQ 0 */ + NVMCTRL_1_IRQn = 30, /**< 30 SAME54P20A Non-Volatile Memory Controller (NVMCTRL) IRQ 1 */ + DMAC_0_IRQn = 31, /**< 31 SAME54P20A Direct Memory Access Controller (DMAC) IRQ 0 */ + DMAC_1_IRQn = 32, /**< 32 SAME54P20A Direct Memory Access Controller (DMAC) IRQ 1 */ + DMAC_2_IRQn = 33, /**< 33 SAME54P20A Direct Memory Access Controller (DMAC) IRQ 2 */ + DMAC_3_IRQn = 34, /**< 34 SAME54P20A Direct Memory Access Controller (DMAC) IRQ 3 */ + DMAC_4_IRQn = 35, /**< 35 SAME54P20A Direct Memory Access Controller (DMAC) IRQ 4 */ + EVSYS_0_IRQn = 36, /**< 36 SAME54P20A Event System Interface (EVSYS) IRQ 0 */ + EVSYS_1_IRQn = 37, /**< 37 SAME54P20A Event System Interface (EVSYS) IRQ 1 */ + EVSYS_2_IRQn = 38, /**< 38 SAME54P20A Event System Interface (EVSYS) IRQ 2 */ + EVSYS_3_IRQn = 39, /**< 39 SAME54P20A Event System Interface (EVSYS) IRQ 3 */ + EVSYS_4_IRQn = 40, /**< 40 SAME54P20A Event System Interface (EVSYS) IRQ 4 */ + PAC_IRQn = 41, /**< 41 SAME54P20A Peripheral Access Controller (PAC) */ + RAMECC_IRQn = 45, /**< 45 SAME54P20A RAM ECC (RAMECC) */ + SERCOM0_0_IRQn = 46, /**< 46 SAME54P20A Serial Communication Interface 0 (SERCOM0) IRQ 0 */ + SERCOM0_1_IRQn = 47, /**< 47 SAME54P20A Serial Communication Interface 0 (SERCOM0) IRQ 1 */ + SERCOM0_2_IRQn = 48, /**< 48 SAME54P20A Serial Communication Interface 0 (SERCOM0) IRQ 2 */ + SERCOM0_3_IRQn = 49, /**< 49 SAME54P20A Serial Communication Interface 0 (SERCOM0) IRQ 3 */ + SERCOM1_0_IRQn = 50, /**< 50 SAME54P20A Serial Communication Interface 1 (SERCOM1) IRQ 0 */ + SERCOM1_1_IRQn = 51, /**< 51 SAME54P20A Serial Communication Interface 1 (SERCOM1) IRQ 1 */ + SERCOM1_2_IRQn = 52, /**< 52 SAME54P20A Serial Communication Interface 1 (SERCOM1) IRQ 2 */ + SERCOM1_3_IRQn = 53, /**< 53 SAME54P20A Serial Communication Interface 1 (SERCOM1) IRQ 3 */ + SERCOM2_0_IRQn = 54, /**< 54 SAME54P20A Serial Communication Interface 2 (SERCOM2) IRQ 0 */ + SERCOM2_1_IRQn = 55, /**< 55 SAME54P20A Serial Communication Interface 2 (SERCOM2) IRQ 1 */ + SERCOM2_2_IRQn = 56, /**< 56 SAME54P20A Serial Communication Interface 2 (SERCOM2) IRQ 2 */ + SERCOM2_3_IRQn = 57, /**< 57 SAME54P20A Serial Communication Interface 2 (SERCOM2) IRQ 3 */ + SERCOM3_0_IRQn = 58, /**< 58 SAME54P20A Serial Communication Interface 3 (SERCOM3) IRQ 0 */ + SERCOM3_1_IRQn = 59, /**< 59 SAME54P20A Serial Communication Interface 3 (SERCOM3) IRQ 1 */ + SERCOM3_2_IRQn = 60, /**< 60 SAME54P20A Serial Communication Interface 3 (SERCOM3) IRQ 2 */ + SERCOM3_3_IRQn = 61, /**< 61 SAME54P20A Serial Communication Interface 3 (SERCOM3) IRQ 3 */ + SERCOM4_0_IRQn = 62, /**< 62 SAME54P20A Serial Communication Interface 4 (SERCOM4) IRQ 0 */ + SERCOM4_1_IRQn = 63, /**< 63 SAME54P20A Serial Communication Interface 4 (SERCOM4) IRQ 1 */ + SERCOM4_2_IRQn = 64, /**< 64 SAME54P20A Serial Communication Interface 4 (SERCOM4) IRQ 2 */ + SERCOM4_3_IRQn = 65, /**< 65 SAME54P20A Serial Communication Interface 4 (SERCOM4) IRQ 3 */ + SERCOM5_0_IRQn = 66, /**< 66 SAME54P20A Serial Communication Interface 5 (SERCOM5) IRQ 0 */ + SERCOM5_1_IRQn = 67, /**< 67 SAME54P20A Serial Communication Interface 5 (SERCOM5) IRQ 1 */ + SERCOM5_2_IRQn = 68, /**< 68 SAME54P20A Serial Communication Interface 5 (SERCOM5) IRQ 2 */ + SERCOM5_3_IRQn = 69, /**< 69 SAME54P20A Serial Communication Interface 5 (SERCOM5) IRQ 3 */ + SERCOM6_0_IRQn = 70, /**< 70 SAME54P20A Serial Communication Interface 6 (SERCOM6) IRQ 0 */ + SERCOM6_1_IRQn = 71, /**< 71 SAME54P20A Serial Communication Interface 6 (SERCOM6) IRQ 1 */ + SERCOM6_2_IRQn = 72, /**< 72 SAME54P20A Serial Communication Interface 6 (SERCOM6) IRQ 2 */ + SERCOM6_3_IRQn = 73, /**< 73 SAME54P20A Serial Communication Interface 6 (SERCOM6) IRQ 3 */ + SERCOM7_0_IRQn = 74, /**< 74 SAME54P20A Serial Communication Interface 7 (SERCOM7) IRQ 0 */ + SERCOM7_1_IRQn = 75, /**< 75 SAME54P20A Serial Communication Interface 7 (SERCOM7) IRQ 1 */ + SERCOM7_2_IRQn = 76, /**< 76 SAME54P20A Serial Communication Interface 7 (SERCOM7) IRQ 2 */ + SERCOM7_3_IRQn = 77, /**< 77 SAME54P20A Serial Communication Interface 7 (SERCOM7) IRQ 3 */ + CAN0_IRQn = 78, /**< 78 SAME54P20A Control Area Network 0 (CAN0) */ + CAN1_IRQn = 79, /**< 79 SAME54P20A Control Area Network 1 (CAN1) */ + USB_0_IRQn = 80, /**< 80 SAME54P20A Universal Serial Bus (USB) IRQ 0 */ + USB_1_IRQn = 81, /**< 81 SAME54P20A Universal Serial Bus (USB) IRQ 1 */ + USB_2_IRQn = 82, /**< 82 SAME54P20A Universal Serial Bus (USB) IRQ 2 */ + USB_3_IRQn = 83, /**< 83 SAME54P20A Universal Serial Bus (USB) IRQ 3 */ + GMAC_IRQn = 84, /**< 84 SAME54P20A Ethernet MAC (GMAC) */ + TCC0_0_IRQn = 85, /**< 85 SAME54P20A Timer Counter Control 0 (TCC0) IRQ 0 */ + TCC0_1_IRQn = 86, /**< 86 SAME54P20A Timer Counter Control 0 (TCC0) IRQ 1 */ + TCC0_2_IRQn = 87, /**< 87 SAME54P20A Timer Counter Control 0 (TCC0) IRQ 2 */ + TCC0_3_IRQn = 88, /**< 88 SAME54P20A Timer Counter Control 0 (TCC0) IRQ 3 */ + TCC0_4_IRQn = 89, /**< 89 SAME54P20A Timer Counter Control 0 (TCC0) IRQ 4 */ + TCC0_5_IRQn = 90, /**< 90 SAME54P20A Timer Counter Control 0 (TCC0) IRQ 5 */ + TCC0_6_IRQn = 91, /**< 91 SAME54P20A Timer Counter Control 0 (TCC0) IRQ 6 */ + TCC1_0_IRQn = 92, /**< 92 SAME54P20A Timer Counter Control 1 (TCC1) IRQ 0 */ + TCC1_1_IRQn = 93, /**< 93 SAME54P20A Timer Counter Control 1 (TCC1) IRQ 1 */ + TCC1_2_IRQn = 94, /**< 94 SAME54P20A Timer Counter Control 1 (TCC1) IRQ 2 */ + TCC1_3_IRQn = 95, /**< 95 SAME54P20A Timer Counter Control 1 (TCC1) IRQ 3 */ + TCC1_4_IRQn = 96, /**< 96 SAME54P20A Timer Counter Control 1 (TCC1) IRQ 4 */ + TCC2_0_IRQn = 97, /**< 97 SAME54P20A Timer Counter Control 2 (TCC2) IRQ 0 */ + TCC2_1_IRQn = 98, /**< 98 SAME54P20A Timer Counter Control 2 (TCC2) IRQ 1 */ + TCC2_2_IRQn = 99, /**< 99 SAME54P20A Timer Counter Control 2 (TCC2) IRQ 2 */ + TCC2_3_IRQn = 100, /**< 100 SAME54P20A Timer Counter Control 2 (TCC2) IRQ 3 */ + TCC3_0_IRQn = 101, /**< 101 SAME54P20A Timer Counter Control 3 (TCC3) IRQ 0 */ + TCC3_1_IRQn = 102, /**< 102 SAME54P20A Timer Counter Control 3 (TCC3) IRQ 1 */ + TCC3_2_IRQn = 103, /**< 103 SAME54P20A Timer Counter Control 3 (TCC3) IRQ 2 */ + TCC4_0_IRQn = 104, /**< 104 SAME54P20A Timer Counter Control 4 (TCC4) IRQ 0 */ + TCC4_1_IRQn = 105, /**< 105 SAME54P20A Timer Counter Control 4 (TCC4) IRQ 1 */ + TCC4_2_IRQn = 106, /**< 106 SAME54P20A Timer Counter Control 4 (TCC4) IRQ 2 */ + TC0_IRQn = 107, /**< 107 SAME54P20A Basic Timer Counter 0 (TC0) */ + TC1_IRQn = 108, /**< 108 SAME54P20A Basic Timer Counter 1 (TC1) */ + TC2_IRQn = 109, /**< 109 SAME54P20A Basic Timer Counter 2 (TC2) */ + TC3_IRQn = 110, /**< 110 SAME54P20A Basic Timer Counter 3 (TC3) */ + TC4_IRQn = 111, /**< 111 SAME54P20A Basic Timer Counter 4 (TC4) */ + TC5_IRQn = 112, /**< 112 SAME54P20A Basic Timer Counter 5 (TC5) */ + TC6_IRQn = 113, /**< 113 SAME54P20A Basic Timer Counter 6 (TC6) */ + TC7_IRQn = 114, /**< 114 SAME54P20A Basic Timer Counter 7 (TC7) */ + PDEC_0_IRQn = 115, /**< 115 SAME54P20A Quadrature Decodeur (PDEC) IRQ 0 */ + PDEC_1_IRQn = 116, /**< 116 SAME54P20A Quadrature Decodeur (PDEC) IRQ 1 */ + PDEC_2_IRQn = 117, /**< 117 SAME54P20A Quadrature Decodeur (PDEC) IRQ 2 */ + ADC0_0_IRQn = 118, /**< 118 SAME54P20A Analog Digital Converter 0 (ADC0) IRQ 0 */ + ADC0_1_IRQn = 119, /**< 119 SAME54P20A Analog Digital Converter 0 (ADC0) IRQ 1 */ + ADC1_0_IRQn = 120, /**< 120 SAME54P20A Analog Digital Converter 1 (ADC1) IRQ 0 */ + ADC1_1_IRQn = 121, /**< 121 SAME54P20A Analog Digital Converter 1 (ADC1) IRQ 1 */ + AC_IRQn = 122, /**< 122 SAME54P20A Analog Comparators (AC) */ + DAC_0_IRQn = 123, /**< 123 SAME54P20A Digital-to-Analog Converter (DAC) IRQ 0 */ + DAC_1_IRQn = 124, /**< 124 SAME54P20A Digital-to-Analog Converter (DAC) IRQ 1 */ + DAC_2_IRQn = 125, /**< 125 SAME54P20A Digital-to-Analog Converter (DAC) IRQ 2 */ + DAC_3_IRQn = 126, /**< 126 SAME54P20A Digital-to-Analog Converter (DAC) IRQ 3 */ + DAC_4_IRQn = 127, /**< 127 SAME54P20A Digital-to-Analog Converter (DAC) IRQ 4 */ + I2S_IRQn = 128, /**< 128 SAME54P20A Inter-IC Sound Interface (I2S) */ + PCC_IRQn = 129, /**< 129 SAME54P20A Parallel Capture Controller (PCC) */ + AES_IRQn = 130, /**< 130 SAME54P20A Advanced Encryption Standard (AES) */ + TRNG_IRQn = 131, /**< 131 SAME54P20A True Random Generator (TRNG) */ + ICM_IRQn = 132, /**< 132 SAME54P20A Integrity Check Monitor (ICM) */ + PUKCC_IRQn = 133, /**< 133 SAME54P20A PUblic-Key Cryptography Controller (PUKCC) */ + QSPI_IRQn = 134, /**< 134 SAME54P20A Quad SPI interface (QSPI) */ + SDHC0_IRQn = 135, /**< 135 SAME54P20A SD/MMC Host Controller 0 (SDHC0) */ + SDHC1_IRQn = 136, /**< 136 SAME54P20A SD/MMC Host Controller 1 (SDHC1) */ + + PERIPH_COUNT_IRQn = 137 /**< Number of peripheral IDs */ +} IRQn_Type; + +typedef struct _DeviceVectors +{ + /* Stack pointer */ + void* pvStack; + + /* Cortex-M handlers */ + void* pfnReset_Handler; + void* pfnNonMaskableInt_Handler; + void* pfnHardFault_Handler; + void* pfnMemManagement_Handler; + void* pfnBusFault_Handler; + void* pfnUsageFault_Handler; + void* pvReservedM9; + void* pvReservedM8; + void* pvReservedM7; + void* pvReservedM6; + void* pfnSVCall_Handler; + void* pfnDebugMonitor_Handler; + void* pvReservedM3; + void* pfnPendSV_Handler; + void* pfnSysTick_Handler; + + /* Peripheral handlers */ + void* pfnPM_Handler; /* 0 Power Manager */ + void* pfnMCLK_Handler; /* 1 Main Clock */ + void* pfnOSCCTRL_0_Handler; /* 2 Oscillators Control IRQ 0 */ + void* pfnOSCCTRL_1_Handler; /* 3 Oscillators Control IRQ 1 */ + void* pfnOSCCTRL_2_Handler; /* 4 Oscillators Control IRQ 2 */ + void* pfnOSCCTRL_3_Handler; /* 5 Oscillators Control IRQ 3 */ + void* pfnOSCCTRL_4_Handler; /* 6 Oscillators Control IRQ 4 */ + void* pfnOSC32KCTRL_Handler; /* 7 32kHz Oscillators Control */ + void* pfnSUPC_0_Handler; /* 8 Supply Controller IRQ 0 */ + void* pfnSUPC_1_Handler; /* 9 Supply Controller IRQ 1 */ + void* pfnWDT_Handler; /* 10 Watchdog Timer */ + void* pfnRTC_Handler; /* 11 Real-Time Counter */ + void* pfnEIC_0_Handler; /* 12 External Interrupt Controller IRQ 0 */ + void* pfnEIC_1_Handler; /* 13 External Interrupt Controller IRQ 1 */ + void* pfnEIC_2_Handler; /* 14 External Interrupt Controller IRQ 2 */ + void* pfnEIC_3_Handler; /* 15 External Interrupt Controller IRQ 3 */ + void* pfnEIC_4_Handler; /* 16 External Interrupt Controller IRQ 4 */ + void* pfnEIC_5_Handler; /* 17 External Interrupt Controller IRQ 5 */ + void* pfnEIC_6_Handler; /* 18 External Interrupt Controller IRQ 6 */ + void* pfnEIC_7_Handler; /* 19 External Interrupt Controller IRQ 7 */ + void* pfnEIC_8_Handler; /* 20 External Interrupt Controller IRQ 8 */ + void* pfnEIC_9_Handler; /* 21 External Interrupt Controller IRQ 9 */ + void* pfnEIC_10_Handler; /* 22 External Interrupt Controller IRQ 10 */ + void* pfnEIC_11_Handler; /* 23 External Interrupt Controller IRQ 11 */ + void* pfnEIC_12_Handler; /* 24 External Interrupt Controller IRQ 12 */ + void* pfnEIC_13_Handler; /* 25 External Interrupt Controller IRQ 13 */ + void* pfnEIC_14_Handler; /* 26 External Interrupt Controller IRQ 14 */ + void* pfnEIC_15_Handler; /* 27 External Interrupt Controller IRQ 15 */ + void* pfnFREQM_Handler; /* 28 Frequency Meter */ + void* pfnNVMCTRL_0_Handler; /* 29 Non-Volatile Memory Controller IRQ 0 */ + void* pfnNVMCTRL_1_Handler; /* 30 Non-Volatile Memory Controller IRQ 1 */ + void* pfnDMAC_0_Handler; /* 31 Direct Memory Access Controller IRQ 0 */ + void* pfnDMAC_1_Handler; /* 32 Direct Memory Access Controller IRQ 1 */ + void* pfnDMAC_2_Handler; /* 33 Direct Memory Access Controller IRQ 2 */ + void* pfnDMAC_3_Handler; /* 34 Direct Memory Access Controller IRQ 3 */ + void* pfnDMAC_4_Handler; /* 35 Direct Memory Access Controller IRQ 4 */ + void* pfnEVSYS_0_Handler; /* 36 Event System Interface IRQ 0 */ + void* pfnEVSYS_1_Handler; /* 37 Event System Interface IRQ 1 */ + void* pfnEVSYS_2_Handler; /* 38 Event System Interface IRQ 2 */ + void* pfnEVSYS_3_Handler; /* 39 Event System Interface IRQ 3 */ + void* pfnEVSYS_4_Handler; /* 40 Event System Interface IRQ 4 */ + void* pfnPAC_Handler; /* 41 Peripheral Access Controller */ + void* pvReserved42; + void* pvReserved43; + void* pvReserved44; + void* pfnRAMECC_Handler; /* 45 RAM ECC */ + void* pfnSERCOM0_0_Handler; /* 46 Serial Communication Interface 0 IRQ 0 */ + void* pfnSERCOM0_1_Handler; /* 47 Serial Communication Interface 0 IRQ 1 */ + void* pfnSERCOM0_2_Handler; /* 48 Serial Communication Interface 0 IRQ 2 */ + void* pfnSERCOM0_3_Handler; /* 49 Serial Communication Interface 0 IRQ 3 */ + void* pfnSERCOM1_0_Handler; /* 50 Serial Communication Interface 1 IRQ 0 */ + void* pfnSERCOM1_1_Handler; /* 51 Serial Communication Interface 1 IRQ 1 */ + void* pfnSERCOM1_2_Handler; /* 52 Serial Communication Interface 1 IRQ 2 */ + void* pfnSERCOM1_3_Handler; /* 53 Serial Communication Interface 1 IRQ 3 */ + void* pfnSERCOM2_0_Handler; /* 54 Serial Communication Interface 2 IRQ 0 */ + void* pfnSERCOM2_1_Handler; /* 55 Serial Communication Interface 2 IRQ 1 */ + void* pfnSERCOM2_2_Handler; /* 56 Serial Communication Interface 2 IRQ 2 */ + void* pfnSERCOM2_3_Handler; /* 57 Serial Communication Interface 2 IRQ 3 */ + void* pfnSERCOM3_0_Handler; /* 58 Serial Communication Interface 3 IRQ 0 */ + void* pfnSERCOM3_1_Handler; /* 59 Serial Communication Interface 3 IRQ 1 */ + void* pfnSERCOM3_2_Handler; /* 60 Serial Communication Interface 3 IRQ 2 */ + void* pfnSERCOM3_3_Handler; /* 61 Serial Communication Interface 3 IRQ 3 */ + void* pfnSERCOM4_0_Handler; /* 62 Serial Communication Interface 4 IRQ 0 */ + void* pfnSERCOM4_1_Handler; /* 63 Serial Communication Interface 4 IRQ 1 */ + void* pfnSERCOM4_2_Handler; /* 64 Serial Communication Interface 4 IRQ 2 */ + void* pfnSERCOM4_3_Handler; /* 65 Serial Communication Interface 4 IRQ 3 */ + void* pfnSERCOM5_0_Handler; /* 66 Serial Communication Interface 5 IRQ 0 */ + void* pfnSERCOM5_1_Handler; /* 67 Serial Communication Interface 5 IRQ 1 */ + void* pfnSERCOM5_2_Handler; /* 68 Serial Communication Interface 5 IRQ 2 */ + void* pfnSERCOM5_3_Handler; /* 69 Serial Communication Interface 5 IRQ 3 */ + void* pfnSERCOM6_0_Handler; /* 70 Serial Communication Interface 6 IRQ 0 */ + void* pfnSERCOM6_1_Handler; /* 71 Serial Communication Interface 6 IRQ 1 */ + void* pfnSERCOM6_2_Handler; /* 72 Serial Communication Interface 6 IRQ 2 */ + void* pfnSERCOM6_3_Handler; /* 73 Serial Communication Interface 6 IRQ 3 */ + void* pfnSERCOM7_0_Handler; /* 74 Serial Communication Interface 7 IRQ 0 */ + void* pfnSERCOM7_1_Handler; /* 75 Serial Communication Interface 7 IRQ 1 */ + void* pfnSERCOM7_2_Handler; /* 76 Serial Communication Interface 7 IRQ 2 */ + void* pfnSERCOM7_3_Handler; /* 77 Serial Communication Interface 7 IRQ 3 */ + void* pfnCAN0_Handler; /* 78 Control Area Network 0 */ + void* pfnCAN1_Handler; /* 79 Control Area Network 1 */ + void* pfnUSB_0_Handler; /* 80 Universal Serial Bus IRQ 0 */ + void* pfnUSB_1_Handler; /* 81 Universal Serial Bus IRQ 1 */ + void* pfnUSB_2_Handler; /* 82 Universal Serial Bus IRQ 2 */ + void* pfnUSB_3_Handler; /* 83 Universal Serial Bus IRQ 3 */ + void* pfnGMAC_Handler; /* 84 Ethernet MAC */ + void* pfnTCC0_0_Handler; /* 85 Timer Counter Control 0 IRQ 0 */ + void* pfnTCC0_1_Handler; /* 86 Timer Counter Control 0 IRQ 1 */ + void* pfnTCC0_2_Handler; /* 87 Timer Counter Control 0 IRQ 2 */ + void* pfnTCC0_3_Handler; /* 88 Timer Counter Control 0 IRQ 3 */ + void* pfnTCC0_4_Handler; /* 89 Timer Counter Control 0 IRQ 4 */ + void* pfnTCC0_5_Handler; /* 90 Timer Counter Control 0 IRQ 5 */ + void* pfnTCC0_6_Handler; /* 91 Timer Counter Control 0 IRQ 6 */ + void* pfnTCC1_0_Handler; /* 92 Timer Counter Control 1 IRQ 0 */ + void* pfnTCC1_1_Handler; /* 93 Timer Counter Control 1 IRQ 1 */ + void* pfnTCC1_2_Handler; /* 94 Timer Counter Control 1 IRQ 2 */ + void* pfnTCC1_3_Handler; /* 95 Timer Counter Control 1 IRQ 3 */ + void* pfnTCC1_4_Handler; /* 96 Timer Counter Control 1 IRQ 4 */ + void* pfnTCC2_0_Handler; /* 97 Timer Counter Control 2 IRQ 0 */ + void* pfnTCC2_1_Handler; /* 98 Timer Counter Control 2 IRQ 1 */ + void* pfnTCC2_2_Handler; /* 99 Timer Counter Control 2 IRQ 2 */ + void* pfnTCC2_3_Handler; /* 100 Timer Counter Control 2 IRQ 3 */ + void* pfnTCC3_0_Handler; /* 101 Timer Counter Control 3 IRQ 0 */ + void* pfnTCC3_1_Handler; /* 102 Timer Counter Control 3 IRQ 1 */ + void* pfnTCC3_2_Handler; /* 103 Timer Counter Control 3 IRQ 2 */ + void* pfnTCC4_0_Handler; /* 104 Timer Counter Control 4 IRQ 0 */ + void* pfnTCC4_1_Handler; /* 105 Timer Counter Control 4 IRQ 1 */ + void* pfnTCC4_2_Handler; /* 106 Timer Counter Control 4 IRQ 2 */ + void* pfnTC0_Handler; /* 107 Basic Timer Counter 0 */ + void* pfnTC1_Handler; /* 108 Basic Timer Counter 1 */ + void* pfnTC2_Handler; /* 109 Basic Timer Counter 2 */ + void* pfnTC3_Handler; /* 110 Basic Timer Counter 3 */ + void* pfnTC4_Handler; /* 111 Basic Timer Counter 4 */ + void* pfnTC5_Handler; /* 112 Basic Timer Counter 5 */ + void* pfnTC6_Handler; /* 113 Basic Timer Counter 6 */ + void* pfnTC7_Handler; /* 114 Basic Timer Counter 7 */ + void* pfnPDEC_0_Handler; /* 115 Quadrature Decodeur IRQ 0 */ + void* pfnPDEC_1_Handler; /* 116 Quadrature Decodeur IRQ 1 */ + void* pfnPDEC_2_Handler; /* 117 Quadrature Decodeur IRQ 2 */ + void* pfnADC0_0_Handler; /* 118 Analog Digital Converter 0 IRQ 0 */ + void* pfnADC0_1_Handler; /* 119 Analog Digital Converter 0 IRQ 1 */ + void* pfnADC1_0_Handler; /* 120 Analog Digital Converter 1 IRQ 0 */ + void* pfnADC1_1_Handler; /* 121 Analog Digital Converter 1 IRQ 1 */ + void* pfnAC_Handler; /* 122 Analog Comparators */ + void* pfnDAC_0_Handler; /* 123 Digital-to-Analog Converter IRQ 0 */ + void* pfnDAC_1_Handler; /* 124 Digital-to-Analog Converter IRQ 1 */ + void* pfnDAC_2_Handler; /* 125 Digital-to-Analog Converter IRQ 2 */ + void* pfnDAC_3_Handler; /* 126 Digital-to-Analog Converter IRQ 3 */ + void* pfnDAC_4_Handler; /* 127 Digital-to-Analog Converter IRQ 4 */ + void* pfnI2S_Handler; /* 128 Inter-IC Sound Interface */ + void* pfnPCC_Handler; /* 129 Parallel Capture Controller */ + void* pfnAES_Handler; /* 130 Advanced Encryption Standard */ + void* pfnTRNG_Handler; /* 131 True Random Generator */ + void* pfnICM_Handler; /* 132 Integrity Check Monitor */ + void* pfnPUKCC_Handler; /* 133 PUblic-Key Cryptography Controller */ + void* pfnQSPI_Handler; /* 134 Quad SPI interface */ + void* pfnSDHC0_Handler; /* 135 SD/MMC Host Controller 0 */ + void* pfnSDHC1_Handler; /* 136 SD/MMC Host Controller 1 */ +} DeviceVectors; + +/* Cortex-M4 processor handlers */ +void Reset_Handler ( void ); +void NonMaskableInt_Handler ( void ); +void HardFault_Handler ( void ); +void MemManagement_Handler ( void ); +void BusFault_Handler ( void ); +void UsageFault_Handler ( void ); +void SVCall_Handler ( void ); +void DebugMonitor_Handler ( void ); +void PendSV_Handler ( void ); +void SysTick_Handler ( void ); + +/* Peripherals handlers */ +void PM_Handler ( void ); +void MCLK_Handler ( void ); +void OSCCTRL_0_Handler ( void ); +void OSCCTRL_1_Handler ( void ); +void OSCCTRL_2_Handler ( void ); +void OSCCTRL_3_Handler ( void ); +void OSCCTRL_4_Handler ( void ); +void OSC32KCTRL_Handler ( void ); +void SUPC_0_Handler ( void ); +void SUPC_1_Handler ( void ); +void WDT_Handler ( void ); +void RTC_Handler ( void ); +void EIC_0_Handler ( void ); +void EIC_1_Handler ( void ); +void EIC_2_Handler ( void ); +void EIC_3_Handler ( void ); +void EIC_4_Handler ( void ); +void EIC_5_Handler ( void ); +void EIC_6_Handler ( void ); +void EIC_7_Handler ( void ); +void EIC_8_Handler ( void ); +void EIC_9_Handler ( void ); +void EIC_10_Handler ( void ); +void EIC_11_Handler ( void ); +void EIC_12_Handler ( void ); +void EIC_13_Handler ( void ); +void EIC_14_Handler ( void ); +void EIC_15_Handler ( void ); +void FREQM_Handler ( void ); +void NVMCTRL_0_Handler ( void ); +void NVMCTRL_1_Handler ( void ); +void DMAC_0_Handler ( void ); +void DMAC_1_Handler ( void ); +void DMAC_2_Handler ( void ); +void DMAC_3_Handler ( void ); +void DMAC_4_Handler ( void ); +void EVSYS_0_Handler ( void ); +void EVSYS_1_Handler ( void ); +void EVSYS_2_Handler ( void ); +void EVSYS_3_Handler ( void ); +void EVSYS_4_Handler ( void ); +void PAC_Handler ( void ); +void RAMECC_Handler ( void ); +void SERCOM0_0_Handler ( void ); +void SERCOM0_1_Handler ( void ); +void SERCOM0_2_Handler ( void ); +void SERCOM0_3_Handler ( void ); +void SERCOM1_0_Handler ( void ); +void SERCOM1_1_Handler ( void ); +void SERCOM1_2_Handler ( void ); +void SERCOM1_3_Handler ( void ); +void SERCOM2_0_Handler ( void ); +void SERCOM2_1_Handler ( void ); +void SERCOM2_2_Handler ( void ); +void SERCOM2_3_Handler ( void ); +void SERCOM3_0_Handler ( void ); +void SERCOM3_1_Handler ( void ); +void SERCOM3_2_Handler ( void ); +void SERCOM3_3_Handler ( void ); +void SERCOM4_0_Handler ( void ); +void SERCOM4_1_Handler ( void ); +void SERCOM4_2_Handler ( void ); +void SERCOM4_3_Handler ( void ); +void SERCOM5_0_Handler ( void ); +void SERCOM5_1_Handler ( void ); +void SERCOM5_2_Handler ( void ); +void SERCOM5_3_Handler ( void ); +void SERCOM6_0_Handler ( void ); +void SERCOM6_1_Handler ( void ); +void SERCOM6_2_Handler ( void ); +void SERCOM6_3_Handler ( void ); +void SERCOM7_0_Handler ( void ); +void SERCOM7_1_Handler ( void ); +void SERCOM7_2_Handler ( void ); +void SERCOM7_3_Handler ( void ); +void CAN0_Handler ( void ); +void CAN1_Handler ( void ); +void USB_0_Handler ( void ); +void USB_1_Handler ( void ); +void USB_2_Handler ( void ); +void USB_3_Handler ( void ); +void GMAC_Handler ( void ); +void TCC0_0_Handler ( void ); +void TCC0_1_Handler ( void ); +void TCC0_2_Handler ( void ); +void TCC0_3_Handler ( void ); +void TCC0_4_Handler ( void ); +void TCC0_5_Handler ( void ); +void TCC0_6_Handler ( void ); +void TCC1_0_Handler ( void ); +void TCC1_1_Handler ( void ); +void TCC1_2_Handler ( void ); +void TCC1_3_Handler ( void ); +void TCC1_4_Handler ( void ); +void TCC2_0_Handler ( void ); +void TCC2_1_Handler ( void ); +void TCC2_2_Handler ( void ); +void TCC2_3_Handler ( void ); +void TCC3_0_Handler ( void ); +void TCC3_1_Handler ( void ); +void TCC3_2_Handler ( void ); +void TCC4_0_Handler ( void ); +void TCC4_1_Handler ( void ); +void TCC4_2_Handler ( void ); +void TC0_Handler ( void ); +void TC1_Handler ( void ); +void TC2_Handler ( void ); +void TC3_Handler ( void ); +void TC4_Handler ( void ); +void TC5_Handler ( void ); +void TC6_Handler ( void ); +void TC7_Handler ( void ); +void PDEC_0_Handler ( void ); +void PDEC_1_Handler ( void ); +void PDEC_2_Handler ( void ); +void ADC0_0_Handler ( void ); +void ADC0_1_Handler ( void ); +void ADC1_0_Handler ( void ); +void ADC1_1_Handler ( void ); +void AC_Handler ( void ); +void DAC_0_Handler ( void ); +void DAC_1_Handler ( void ); +void DAC_2_Handler ( void ); +void DAC_3_Handler ( void ); +void DAC_4_Handler ( void ); +void I2S_Handler ( void ); +void PCC_Handler ( void ); +void AES_Handler ( void ); +void TRNG_Handler ( void ); +void ICM_Handler ( void ); +void PUKCC_Handler ( void ); +void QSPI_Handler ( void ); +void SDHC0_Handler ( void ); +void SDHC1_Handler ( void ); + +/* + * \brief Configuration of the Cortex-M4 Processor and Core Peripherals + */ + +#define __CM4_REV 1 /*!< Core revision r0p1 */ +#define __DEBUG_LVL 3 /*!< Full debug plus DWT data matching */ +#define __FPU_PRESENT 1 /*!< FPU present or not */ +#define __MPU_PRESENT 1 /*!< MPU present or not */ +#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */ +#define __TRACE_LVL 2 /*!< Full trace: ITM, DWT triggers and counters, ETM */ +#define __VTOR_PRESENT 1 /*!< VTOR present or not */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * \brief CMSIS includes + */ + +#include +#if !defined DONT_USE_CMSIS_INIT +#include "system_same54.h" +#endif /* DONT_USE_CMSIS_INIT */ + +/*@}*/ + +/* ************************************************************************** */ +/** SOFTWARE PERIPHERAL API DEFINITION FOR SAME54P20A */ +/* ************************************************************************** */ +/** \defgroup SAME54P20A_api Peripheral Software API */ +/*@{*/ + +#include "component/ac.h" +#include "component/adc.h" +#include "component/aes.h" +#include "component/can.h" +#include "component/ccl.h" +#include "component/cmcc.h" +#include "component/dac.h" +#include "component/dmac.h" +#include "component/dsu.h" +#include "component/eic.h" +#include "component/evsys.h" +#include "component/freqm.h" +#include "component/gclk.h" +#include "component/gmac.h" +#include "component/hmatrixb.h" +#include "component/icm.h" +#include "component/i2s.h" +#include "component/mclk.h" +#include "component/nvmctrl.h" +#include "component/oscctrl.h" +#include "component/osc32kctrl.h" +#include "component/pac.h" +#include "component/pcc.h" +#include "component/pdec.h" +#include "component/pm.h" +#include "component/port.h" +#include "component/qspi.h" +#include "component/ramecc.h" +#include "component/rstc.h" +#include "component/rtc.h" +#include "component/sdhc.h" +#include "component/sercom.h" +#include "component/supc.h" +#include "component/tc.h" +#include "component/tcc.h" +#include "component/trng.h" +#include "component/usb.h" +#include "component/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** REGISTERS ACCESS DEFINITIONS FOR SAME54P20A */ +/* ************************************************************************** */ +/** \defgroup SAME54P20A_reg Registers Access Definitions */ +/*@{*/ + +#include "instance/ac.h" +#include "instance/adc0.h" +#include "instance/adc1.h" +#include "instance/aes.h" +#include "instance/can0.h" +#include "instance/can1.h" +#include "instance/ccl.h" +#include "instance/cmcc.h" +#include "instance/dac.h" +#include "instance/dmac.h" +#include "instance/dsu.h" +#include "instance/eic.h" +#include "instance/evsys.h" +#include "instance/freqm.h" +#include "instance/gclk.h" +#include "instance/gmac.h" +#include "instance/hmatrix.h" +#include "instance/icm.h" +#include "instance/i2s.h" +#include "instance/mclk.h" +#include "instance/nvmctrl.h" +#include "instance/oscctrl.h" +#include "instance/osc32kctrl.h" +#include "instance/pac.h" +#include "instance/pcc.h" +#include "instance/pdec.h" +#include "instance/pm.h" +#include "instance/port.h" +#include "instance/pukcc.h" +#include "instance/qspi.h" +#include "instance/ramecc.h" +#include "instance/rstc.h" +#include "instance/rtc.h" +#include "instance/sdhc0.h" +#include "instance/sdhc1.h" +#include "instance/sercom0.h" +#include "instance/sercom1.h" +#include "instance/sercom2.h" +#include "instance/sercom3.h" +#include "instance/sercom4.h" +#include "instance/sercom5.h" +#include "instance/sercom6.h" +#include "instance/sercom7.h" +#include "instance/supc.h" +#include "instance/tc0.h" +#include "instance/tc1.h" +#include "instance/tc2.h" +#include "instance/tc3.h" +#include "instance/tc4.h" +#include "instance/tc5.h" +#include "instance/tc6.h" +#include "instance/tc7.h" +#include "instance/tcc0.h" +#include "instance/tcc1.h" +#include "instance/tcc2.h" +#include "instance/tcc3.h" +#include "instance/tcc4.h" +#include "instance/trng.h" +#include "instance/usb.h" +#include "instance/wdt.h" +/*@}*/ + +/* ************************************************************************** */ +/** PERIPHERAL ID DEFINITIONS FOR SAME54P20A */ +/* ************************************************************************** */ +/** \defgroup SAME54P20A_id Peripheral Ids Definitions */ +/*@{*/ + +// Peripheral instances on HPB0 bridge +#define ID_PAC 0 /**< \brief Peripheral Access Controller (PAC) */ +#define ID_PM 1 /**< \brief Power Manager (PM) */ +#define ID_MCLK 2 /**< \brief Main Clock (MCLK) */ +#define ID_RSTC 3 /**< \brief Reset Controller (RSTC) */ +#define ID_OSCCTRL 4 /**< \brief Oscillators Control (OSCCTRL) */ +#define ID_OSC32KCTRL 5 /**< \brief 32kHz Oscillators Control (OSC32KCTRL) */ +#define ID_SUPC 6 /**< \brief Supply Controller (SUPC) */ +#define ID_GCLK 7 /**< \brief Generic Clock Generator (GCLK) */ +#define ID_WDT 8 /**< \brief Watchdog Timer (WDT) */ +#define ID_RTC 9 /**< \brief Real-Time Counter (RTC) */ +#define ID_EIC 10 /**< \brief External Interrupt Controller (EIC) */ +#define ID_FREQM 11 /**< \brief Frequency Meter (FREQM) */ +#define ID_SERCOM0 12 /**< \brief Serial Communication Interface 0 (SERCOM0) */ +#define ID_SERCOM1 13 /**< \brief Serial Communication Interface 1 (SERCOM1) */ +#define ID_TC0 14 /**< \brief Basic Timer Counter 0 (TC0) */ +#define ID_TC1 15 /**< \brief Basic Timer Counter 1 (TC1) */ + +// Peripheral instances on HPB1 bridge +#define ID_USB 32 /**< \brief Universal Serial Bus (USB) */ +#define ID_DSU 33 /**< \brief Device Service Unit (DSU) */ +#define ID_NVMCTRL 34 /**< \brief Non-Volatile Memory Controller (NVMCTRL) */ +#define ID_CMCC 35 /**< \brief Cortex M Cache Controller (CMCC) */ +#define ID_PORT 36 /**< \brief Port Module (PORT) */ +#define ID_DMAC 37 /**< \brief Direct Memory Access Controller (DMAC) */ +#define ID_HMATRIX 38 /**< \brief HSB Matrix (HMATRIX) */ +#define ID_EVSYS 39 /**< \brief Event System Interface (EVSYS) */ +#define ID_SERCOM2 41 /**< \brief Serial Communication Interface 2 (SERCOM2) */ +#define ID_SERCOM3 42 /**< \brief Serial Communication Interface 3 (SERCOM3) */ +#define ID_TCC0 43 /**< \brief Timer Counter Control 0 (TCC0) */ +#define ID_TCC1 44 /**< \brief Timer Counter Control 1 (TCC1) */ +#define ID_TC2 45 /**< \brief Basic Timer Counter 2 (TC2) */ +#define ID_TC3 46 /**< \brief Basic Timer Counter 3 (TC3) */ +#define ID_RAMECC 48 /**< \brief RAM ECC (RAMECC) */ + +// Peripheral instances on HPB2 bridge +#define ID_CAN0 64 /**< \brief Control Area Network 0 (CAN0) */ +#define ID_CAN1 65 /**< \brief Control Area Network 1 (CAN1) */ +#define ID_GMAC 66 /**< \brief Ethernet MAC (GMAC) */ +#define ID_TCC2 67 /**< \brief Timer Counter Control 2 (TCC2) */ +#define ID_TCC3 68 /**< \brief Timer Counter Control 3 (TCC3) */ +#define ID_TC4 69 /**< \brief Basic Timer Counter 4 (TC4) */ +#define ID_TC5 70 /**< \brief Basic Timer Counter 5 (TC5) */ +#define ID_PDEC 71 /**< \brief Quadrature Decodeur (PDEC) */ +#define ID_AC 72 /**< \brief Analog Comparators (AC) */ +#define ID_AES 73 /**< \brief Advanced Encryption Standard (AES) */ +#define ID_TRNG 74 /**< \brief True Random Generator (TRNG) */ +#define ID_ICM 75 /**< \brief Integrity Check Monitor (ICM) */ +#define ID_PUKCC 76 /**< \brief PUblic-Key Cryptography Controller (PUKCC) */ +#define ID_QSPI 77 /**< \brief Quad SPI interface (QSPI) */ +#define ID_CCL 78 /**< \brief Configurable Custom Logic (CCL) */ + +// Peripheral instances on HPB3 bridge +#define ID_SERCOM4 96 /**< \brief Serial Communication Interface 4 (SERCOM4) */ +#define ID_SERCOM5 97 /**< \brief Serial Communication Interface 5 (SERCOM5) */ +#define ID_SERCOM6 98 /**< \brief Serial Communication Interface 6 (SERCOM6) */ +#define ID_SERCOM7 99 /**< \brief Serial Communication Interface 7 (SERCOM7) */ +#define ID_TCC4 100 /**< \brief Timer Counter Control 4 (TCC4) */ +#define ID_TC6 101 /**< \brief Basic Timer Counter 6 (TC6) */ +#define ID_TC7 102 /**< \brief Basic Timer Counter 7 (TC7) */ +#define ID_ADC0 103 /**< \brief Analog Digital Converter 0 (ADC0) */ +#define ID_ADC1 104 /**< \brief Analog Digital Converter 1 (ADC1) */ +#define ID_DAC 105 /**< \brief Digital-to-Analog Converter (DAC) */ +#define ID_I2S 106 /**< \brief Inter-IC Sound Interface (I2S) */ +#define ID_PCC 107 /**< \brief Parallel Capture Controller (PCC) */ + +// Peripheral instances on AHB (as if on bridge 4) +#define ID_SDHC0 128 /**< \brief SD/MMC Host Controller (SDHC0) */ +#define ID_SDHC1 129 /**< \brief SD/MMC Host Controller (SDHC1) */ + +#define ID_PERIPH_COUNT 130 /**< \brief Max number of peripheral IDs */ +/*@}*/ + +/* ************************************************************************** */ +/** BASE ADDRESS DEFINITIONS FOR SAME54P20A */ +/* ************************************************************************** */ +/** \defgroup SAME54P20A_base Peripheral Base Address Definitions */ +/*@{*/ + +#if defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__) +#define AC (0x42002000) /**< \brief (AC) APB Base Address */ +#define ADC0 (0x43001C00) /**< \brief (ADC0) APB Base Address */ +#define ADC1 (0x43002000) /**< \brief (ADC1) APB Base Address */ +#define AES (0x42002400) /**< \brief (AES) APB Base Address */ +#define CAN0 (0x42000000) /**< \brief (CAN0) APB Base Address */ +#define CAN1 (0x42000400) /**< \brief (CAN1) APB Base Address */ +#define CCL (0x42003800) /**< \brief (CCL) APB Base Address */ +#define CMCC (0x41006000) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000) /**< \brief (CMCC) AHB Base Address */ +#define DAC (0x43002400) /**< \brief (DAC) APB Base Address */ +#define DMAC (0x4100A000) /**< \brief (DMAC) APB Base Address */ +#define DSU (0x41002000) /**< \brief (DSU) APB Base Address */ +#define EIC (0x40002800) /**< \brief (EIC) APB Base Address */ +#define EVSYS (0x4100E000) /**< \brief (EVSYS) APB Base Address */ +#define FREQM (0x40002C00) /**< \brief (FREQM) APB Base Address */ +#define GCLK (0x40001C00) /**< \brief (GCLK) APB Base Address */ +#define GMAC (0x42000800) /**< \brief (GMAC) APB Base Address */ +#define HMATRIX (0x4100C000) /**< \brief (HMATRIX) APB Base Address */ +#define ICM (0x42002C00) /**< \brief (ICM) APB Base Address */ +#define I2S (0x43002800) /**< \brief (I2S) APB Base Address */ +#define MCLK (0x40000800) /**< \brief (MCLK) APB Base Address */ +#define NVMCTRL (0x41004000) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000) /**< \brief (NVMCTRL) USER Base Address */ +#define OSCCTRL (0x40001000) /**< \brief (OSCCTRL) APB Base Address */ +#define OSC32KCTRL (0x40001400) /**< \brief (OSC32KCTRL) APB Base Address */ +#define PAC (0x40000000) /**< \brief (PAC) APB Base Address */ +#define PCC (0x43002C00) /**< \brief (PCC) APB Base Address */ +#define PDEC (0x42001C00) /**< \brief (PDEC) APB Base Address */ +#define PM (0x40000400) /**< \brief (PM) APB Base Address */ +#define PORT (0x41008000) /**< \brief (PORT) APB Base Address */ +#define PUKCC (0x42003000) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB (0x02000000) /**< \brief (PUKCC) AHB Base Address */ +#define QSPI (0x42003400) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000) /**< \brief (QSPI) AHB Base Address */ +#define RAMECC (0x41020000) /**< \brief (RAMECC) APB Base Address */ +#define RSTC (0x40000C00) /**< \brief (RSTC) APB Base Address */ +#define RTC (0x40002400) /**< \brief (RTC) APB Base Address */ +#define SDHC0 (0x45000000) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 (0x46000000) /**< \brief (SDHC1) AHB Base Address */ +#define SERCOM0 (0x40003000) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 (0x40003400) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 (0x41012000) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 (0x41014000) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 (0x43000000) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 (0x43000400) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 (0x43000800) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 (0x43000C00) /**< \brief (SERCOM7) APB Base Address */ +#define SUPC (0x40001800) /**< \brief (SUPC) APB Base Address */ +#define TC0 (0x40003800) /**< \brief (TC0) APB Base Address */ +#define TC1 (0x40003C00) /**< \brief (TC1) APB Base Address */ +#define TC2 (0x4101A000) /**< \brief (TC2) APB Base Address */ +#define TC3 (0x4101C000) /**< \brief (TC3) APB Base Address */ +#define TC4 (0x42001400) /**< \brief (TC4) APB Base Address */ +#define TC5 (0x42001800) /**< \brief (TC5) APB Base Address */ +#define TC6 (0x43001400) /**< \brief (TC6) APB Base Address */ +#define TC7 (0x43001800) /**< \brief (TC7) APB Base Address */ +#define TCC0 (0x41016000) /**< \brief (TCC0) APB Base Address */ +#define TCC1 (0x41018000) /**< \brief (TCC1) APB Base Address */ +#define TCC2 (0x42000C00) /**< \brief (TCC2) APB Base Address */ +#define TCC3 (0x42001000) /**< \brief (TCC3) APB Base Address */ +#define TCC4 (0x43001000) /**< \brief (TCC4) APB Base Address */ +#define TRNG (0x42002800) /**< \brief (TRNG) APB Base Address */ +#define USB (0x41000000) /**< \brief (USB) APB Base Address */ +#define WDT (0x40002000) /**< \brief (WDT) APB Base Address */ +#else +#define AC ((Ac *)0x42002000UL) /**< \brief (AC) APB Base Address */ +#define AC_INST_NUM 1 /**< \brief (AC) Number of instances */ +#define AC_INSTS { AC } /**< \brief (AC) Instances List */ + +#define ADC0 ((Adc *)0x43001C00UL) /**< \brief (ADC0) APB Base Address */ +#define ADC1 ((Adc *)0x43002000UL) /**< \brief (ADC1) APB Base Address */ +#define ADC_INST_NUM 2 /**< \brief (ADC) Number of instances */ +#define ADC_INSTS { ADC0, ADC1 } /**< \brief (ADC) Instances List */ + +#define AES ((Aes *)0x42002400UL) /**< \brief (AES) APB Base Address */ +#define AES_INST_NUM 1 /**< \brief (AES) Number of instances */ +#define AES_INSTS { AES } /**< \brief (AES) Instances List */ + +#define CAN0 ((Can *)0x42000000UL) /**< \brief (CAN0) APB Base Address */ +#define CAN1 ((Can *)0x42000400UL) /**< \brief (CAN1) APB Base Address */ +#define CAN_INST_NUM 2 /**< \brief (CAN) Number of instances */ +#define CAN_INSTS { CAN0, CAN1 } /**< \brief (CAN) Instances List */ + +#define CCL ((Ccl *)0x42003800UL) /**< \brief (CCL) APB Base Address */ +#define CCL_INST_NUM 1 /**< \brief (CCL) Number of instances */ +#define CCL_INSTS { CCL } /**< \brief (CCL) Instances List */ + +#define CMCC ((Cmcc *)0x41006000UL) /**< \brief (CMCC) APB Base Address */ +#define CMCC_AHB (0x03000000UL) /**< \brief (CMCC) AHB Base Address */ +#define CMCC_INST_NUM 1 /**< \brief (CMCC) Number of instances */ +#define CMCC_INSTS { CMCC } /**< \brief (CMCC) Instances List */ + +#define DAC ((Dac *)0x43002400UL) /**< \brief (DAC) APB Base Address */ +#define DAC_INST_NUM 1 /**< \brief (DAC) Number of instances */ +#define DAC_INSTS { DAC } /**< \brief (DAC) Instances List */ + +#define DMAC ((Dmac *)0x4100A000UL) /**< \brief (DMAC) APB Base Address */ +#define DMAC_INST_NUM 1 /**< \brief (DMAC) Number of instances */ +#define DMAC_INSTS { DMAC } /**< \brief (DMAC) Instances List */ + +#define DSU ((Dsu *)0x41002000UL) /**< \brief (DSU) APB Base Address */ +#define DSU_INST_NUM 1 /**< \brief (DSU) Number of instances */ +#define DSU_INSTS { DSU } /**< \brief (DSU) Instances List */ + +#define EIC ((Eic *)0x40002800UL) /**< \brief (EIC) APB Base Address */ +#define EIC_INST_NUM 1 /**< \brief (EIC) Number of instances */ +#define EIC_INSTS { EIC } /**< \brief (EIC) Instances List */ + +#define EVSYS ((Evsys *)0x4100E000UL) /**< \brief (EVSYS) APB Base Address */ +#define EVSYS_INST_NUM 1 /**< \brief (EVSYS) Number of instances */ +#define EVSYS_INSTS { EVSYS } /**< \brief (EVSYS) Instances List */ + +#define FREQM ((Freqm *)0x40002C00UL) /**< \brief (FREQM) APB Base Address */ +#define FREQM_INST_NUM 1 /**< \brief (FREQM) Number of instances */ +#define FREQM_INSTS { FREQM } /**< \brief (FREQM) Instances List */ + +#define GCLK ((Gclk *)0x40001C00UL) /**< \brief (GCLK) APB Base Address */ +#define GCLK_INST_NUM 1 /**< \brief (GCLK) Number of instances */ +#define GCLK_INSTS { GCLK } /**< \brief (GCLK) Instances List */ + +#define GMAC ((Gmac *)0x42000800UL) /**< \brief (GMAC) APB Base Address */ +#define GMAC_INST_NUM 1 /**< \brief (GMAC) Number of instances */ +#define GMAC_INSTS { GMAC } /**< \brief (GMAC) Instances List */ + +#define HMATRIX ((Hmatrixb *)0x4100C000UL) /**< \brief (HMATRIX) APB Base Address */ +#define HMATRIXB_INST_NUM 1 /**< \brief (HMATRIXB) Number of instances */ +#define HMATRIXB_INSTS { HMATRIX } /**< \brief (HMATRIXB) Instances List */ + +#define ICM ((Icm *)0x42002C00UL) /**< \brief (ICM) APB Base Address */ +#define ICM_INST_NUM 1 /**< \brief (ICM) Number of instances */ +#define ICM_INSTS { ICM } /**< \brief (ICM) Instances List */ + +#define I2S ((I2s *)0x43002800UL) /**< \brief (I2S) APB Base Address */ +#define I2S_INST_NUM 1 /**< \brief (I2S) Number of instances */ +#define I2S_INSTS { I2S } /**< \brief (I2S) Instances List */ + +#define MCLK ((Mclk *)0x40000800UL) /**< \brief (MCLK) APB Base Address */ +#define MCLK_INST_NUM 1 /**< \brief (MCLK) Number of instances */ +#define MCLK_INSTS { MCLK } /**< \brief (MCLK) Instances List */ + +#define NVMCTRL ((Nvmctrl *)0x41004000UL) /**< \brief (NVMCTRL) APB Base Address */ +#define NVMCTRL_SW0 (0x00800080UL) /**< \brief (NVMCTRL) SW0 Base Address */ +#define NVMCTRL_TEMP_LOG (0x00800100UL) /**< \brief (NVMCTRL) TEMP_LOG Base Address */ +#define NVMCTRL_USER (0x00804000UL) /**< \brief (NVMCTRL) USER Base Address */ +#define NVMCTRL_INST_NUM 1 /**< \brief (NVMCTRL) Number of instances */ +#define NVMCTRL_INSTS { NVMCTRL } /**< \brief (NVMCTRL) Instances List */ + +#define OSCCTRL ((Oscctrl *)0x40001000UL) /**< \brief (OSCCTRL) APB Base Address */ +#define OSCCTRL_INST_NUM 1 /**< \brief (OSCCTRL) Number of instances */ +#define OSCCTRL_INSTS { OSCCTRL } /**< \brief (OSCCTRL) Instances List */ + +#define OSC32KCTRL ((Osc32kctrl *)0x40001400UL) /**< \brief (OSC32KCTRL) APB Base Address */ +#define OSC32KCTRL_INST_NUM 1 /**< \brief (OSC32KCTRL) Number of instances */ +#define OSC32KCTRL_INSTS { OSC32KCTRL } /**< \brief (OSC32KCTRL) Instances List */ + +#define PAC ((Pac *)0x40000000UL) /**< \brief (PAC) APB Base Address */ +#define PAC_INST_NUM 1 /**< \brief (PAC) Number of instances */ +#define PAC_INSTS { PAC } /**< \brief (PAC) Instances List */ + +#define PCC ((Pcc *)0x43002C00UL) /**< \brief (PCC) APB Base Address */ +#define PCC_INST_NUM 1 /**< \brief (PCC) Number of instances */ +#define PCC_INSTS { PCC } /**< \brief (PCC) Instances List */ + +#define PDEC ((Pdec *)0x42001C00UL) /**< \brief (PDEC) APB Base Address */ +#define PDEC_INST_NUM 1 /**< \brief (PDEC) Number of instances */ +#define PDEC_INSTS { PDEC } /**< \brief (PDEC) Instances List */ + +#define PM ((Pm *)0x40000400UL) /**< \brief (PM) APB Base Address */ +#define PM_INST_NUM 1 /**< \brief (PM) Number of instances */ +#define PM_INSTS { PM } /**< \brief (PM) Instances List */ + +#define PORT ((Port *)0x41008000UL) /**< \brief (PORT) APB Base Address */ +#define PORT_INST_NUM 1 /**< \brief (PORT) Number of instances */ +#define PORT_INSTS { PORT } /**< \brief (PORT) Instances List */ + +#define PUKCC ((void *)0x42003000UL) /**< \brief (PUKCC) APB Base Address */ +#define PUKCC_AHB ((void *)0x02000000UL) /**< \brief (PUKCC) AHB Base Address */ +#define PUKCC_INST_NUM 1 /**< \brief (PUKCC) Number of instances */ +#define PUKCC_INSTS { PUKCC } /**< \brief (PUKCC) Instances List */ + +#define QSPI ((Qspi *)0x42003400UL) /**< \brief (QSPI) APB Base Address */ +#define QSPI_AHB (0x04000000UL) /**< \brief (QSPI) AHB Base Address */ +#define QSPI_INST_NUM 1 /**< \brief (QSPI) Number of instances */ +#define QSPI_INSTS { QSPI } /**< \brief (QSPI) Instances List */ + +#define RAMECC ((Ramecc *)0x41020000UL) /**< \brief (RAMECC) APB Base Address */ +#define RAMECC_INST_NUM 1 /**< \brief (RAMECC) Number of instances */ +#define RAMECC_INSTS { RAMECC } /**< \brief (RAMECC) Instances List */ + +#define RSTC ((Rstc *)0x40000C00UL) /**< \brief (RSTC) APB Base Address */ +#define RSTC_INST_NUM 1 /**< \brief (RSTC) Number of instances */ +#define RSTC_INSTS { RSTC } /**< \brief (RSTC) Instances List */ + +#define RTC ((Rtc *)0x40002400UL) /**< \brief (RTC) APB Base Address */ +#define RTC_INST_NUM 1 /**< \brief (RTC) Number of instances */ +#define RTC_INSTS { RTC } /**< \brief (RTC) Instances List */ + +#define SDHC0 ((Sdhc *)0x45000000UL) /**< \brief (SDHC0) AHB Base Address */ +#define SDHC1 ((Sdhc *)0x46000000UL) /**< \brief (SDHC1) AHB Base Address */ +#define SDHC_INST_NUM 2 /**< \brief (SDHC) Number of instances */ +#define SDHC_INSTS { SDHC0, SDHC1 } /**< \brief (SDHC) Instances List */ + +#define SERCOM0 ((Sercom *)0x40003000UL) /**< \brief (SERCOM0) APB Base Address */ +#define SERCOM1 ((Sercom *)0x40003400UL) /**< \brief (SERCOM1) APB Base Address */ +#define SERCOM2 ((Sercom *)0x41012000UL) /**< \brief (SERCOM2) APB Base Address */ +#define SERCOM3 ((Sercom *)0x41014000UL) /**< \brief (SERCOM3) APB Base Address */ +#define SERCOM4 ((Sercom *)0x43000000UL) /**< \brief (SERCOM4) APB Base Address */ +#define SERCOM5 ((Sercom *)0x43000400UL) /**< \brief (SERCOM5) APB Base Address */ +#define SERCOM6 ((Sercom *)0x43000800UL) /**< \brief (SERCOM6) APB Base Address */ +#define SERCOM7 ((Sercom *)0x43000C00UL) /**< \brief (SERCOM7) APB Base Address */ +#define SERCOM_INST_NUM 8 /**< \brief (SERCOM) Number of instances */ +#define SERCOM_INSTS { SERCOM0, SERCOM1, SERCOM2, SERCOM3, SERCOM4, SERCOM5, SERCOM6, SERCOM7 } /**< \brief (SERCOM) Instances List */ + +#define SUPC ((Supc *)0x40001800UL) /**< \brief (SUPC) APB Base Address */ +#define SUPC_INST_NUM 1 /**< \brief (SUPC) Number of instances */ +#define SUPC_INSTS { SUPC } /**< \brief (SUPC) Instances List */ + +#define TC0 ((Tc *)0x40003800UL) /**< \brief (TC0) APB Base Address */ +#define TC1 ((Tc *)0x40003C00UL) /**< \brief (TC1) APB Base Address */ +#define TC2 ((Tc *)0x4101A000UL) /**< \brief (TC2) APB Base Address */ +#define TC3 ((Tc *)0x4101C000UL) /**< \brief (TC3) APB Base Address */ +#define TC4 ((Tc *)0x42001400UL) /**< \brief (TC4) APB Base Address */ +#define TC5 ((Tc *)0x42001800UL) /**< \brief (TC5) APB Base Address */ +#define TC6 ((Tc *)0x43001400UL) /**< \brief (TC6) APB Base Address */ +#define TC7 ((Tc *)0x43001800UL) /**< \brief (TC7) APB Base Address */ +#define TC_INST_NUM 8 /**< \brief (TC) Number of instances */ +#define TC_INSTS { TC0, TC1, TC2, TC3, TC4, TC5, TC6, TC7 } /**< \brief (TC) Instances List */ + +#define TCC0 ((Tcc *)0x41016000UL) /**< \brief (TCC0) APB Base Address */ +#define TCC1 ((Tcc *)0x41018000UL) /**< \brief (TCC1) APB Base Address */ +#define TCC2 ((Tcc *)0x42000C00UL) /**< \brief (TCC2) APB Base Address */ +#define TCC3 ((Tcc *)0x42001000UL) /**< \brief (TCC3) APB Base Address */ +#define TCC4 ((Tcc *)0x43001000UL) /**< \brief (TCC4) APB Base Address */ +#define TCC_INST_NUM 5 /**< \brief (TCC) Number of instances */ +#define TCC_INSTS { TCC0, TCC1, TCC2, TCC3, TCC4 } /**< \brief (TCC) Instances List */ + +#define TRNG ((Trng *)0x42002800UL) /**< \brief (TRNG) APB Base Address */ +#define TRNG_INST_NUM 1 /**< \brief (TRNG) Number of instances */ +#define TRNG_INSTS { TRNG } /**< \brief (TRNG) Instances List */ + +#define USB ((Usb *)0x41000000UL) /**< \brief (USB) APB Base Address */ +#define USB_INST_NUM 1 /**< \brief (USB) Number of instances */ +#define USB_INSTS { USB } /**< \brief (USB) Instances List */ + +#define WDT ((Wdt *)0x40002000UL) /**< \brief (WDT) APB Base Address */ +#define WDT_INST_NUM 1 /**< \brief (WDT) Number of instances */ +#define WDT_INSTS { WDT } /**< \brief (WDT) Instances List */ + +#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ +/*@}*/ + +/* ************************************************************************** */ +/** PORT DEFINITIONS FOR SAME54P20A */ +/* ************************************************************************** */ +/** \defgroup SAME54P20A_port PORT Definitions */ +/*@{*/ + +#include "pio/same54p20a.h" +/*@}*/ + +/* ************************************************************************** */ +/** MEMORY MAPPING DEFINITIONS FOR SAME54P20A */ +/* ************************************************************************** */ + +#define HSRAM_SIZE _UL_(0x00040000) /* 256 kB */ +#define FLASH_SIZE _UL_(0x00100000) /* 1024 kB */ +#define FLASH_PAGE_SIZE 512 +#define FLASH_NB_OF_PAGES 2048 +#define FLASH_USER_PAGE_SIZE 512 +#define BKUPRAM_SIZE _UL_(0x00002000) /* 8 kB */ +#define QSPI_SIZE _UL_(0x01000000) /* 16384 kB */ + +#define FLASH_ADDR _UL_(0x00000000) /**< FLASH base address */ +#define CMCC_DATARAM_ADDR _UL_(0x03000000) /**< CMCC_DATARAM base address */ +#define CMCC_DATARAM_SIZE _UL_(0x00001000) /**< CMCC_DATARAM size */ +#define CMCC_TAGRAM_ADDR _UL_(0x03001000) /**< CMCC_TAGRAM base address */ +#define CMCC_TAGRAM_SIZE _UL_(0x00000400) /**< CMCC_TAGRAM size */ +#define CMCC_VALIDRAM_ADDR _UL_(0x03002000) /**< CMCC_VALIDRAM base address */ +#define CMCC_VALIDRAM_SIZE _UL_(0x00000040) /**< CMCC_VALIDRAM size */ +#define HSRAM_ADDR _UL_(0x20000000) /**< HSRAM base address */ +#define HSRAM_ETB_ADDR _UL_(0x20000000) /**< HSRAM_ETB base address */ +#define HSRAM_ETB_SIZE _UL_(0x00008000) /**< HSRAM_ETB size */ +#define HSRAM_RET1_ADDR _UL_(0x20000000) /**< HSRAM_RET1 base address */ +#define HSRAM_RET1_SIZE _UL_(0x00008000) /**< HSRAM_RET1 size */ +#define HPB0_ADDR _UL_(0x40000000) /**< HPB0 base address */ +#define HPB1_ADDR _UL_(0x41000000) /**< HPB1 base address */ +#define HPB2_ADDR _UL_(0x42000000) /**< HPB2 base address */ +#define HPB3_ADDR _UL_(0x43000000) /**< HPB3 base address */ +#define SEEPROM_ADDR _UL_(0x44000000) /**< SEEPROM base address */ +#define BKUPRAM_ADDR _UL_(0x47000000) /**< BKUPRAM base address */ +#define PPB_ADDR _UL_(0xE0000000) /**< PPB base address */ + +#define DSU_DID_RESETVALUE _UL_(0x61840300) +#define ADC0_TOUCH_LINES_NUM 32 +#define PORT_GROUPS 4 + +/* ************************************************************************** */ +/** ELECTRICAL DEFINITIONS FOR SAME54P20A */ +/* ************************************************************************** */ + + +#ifdef __cplusplus +} +#endif + +/*@}*/ + +#endif /* SAME54P20A_H */ diff --git a/software/firmware/oracle_same54n19a/include/system_same54.h b/software/firmware/oracle_same54n19a/include/system_same54.h new file mode 100644 index 00000000..e4535de1 --- /dev/null +++ b/software/firmware/oracle_same54n19a/include/system_same54.h @@ -0,0 +1,48 @@ +/** + * \file + * + * \brief Low-level initialization functions called upon chip startup + * + * Copyright (c) 2019 Microchip Technology Inc. + * + * \asf_license_start + * + * \page License + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the Licence at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * \asf_license_stop + * + */ + +#ifndef _SYSTEM_SAME54_H_INCLUDED_ +#define _SYSTEM_SAME54_H_INCLUDED_ + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +void SystemInit(void); +void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_SAME54_H_INCLUDED */ diff --git a/software/firmware/oracle_same54n19a/main.c b/software/firmware/oracle_same54n19a/main.c new file mode 100644 index 00000000..9f91f4d0 --- /dev/null +++ b/software/firmware/oracle_same54n19a/main.c @@ -0,0 +1,12 @@ +#include "oracle.h" + + +int main(void) +{ + oracle_init(); + + for(;;) + { + oracle_service(); + } +} diff --git a/software/firmware/oracle_same54n19a/oracle.c b/software/firmware/oracle_same54n19a/oracle.c new file mode 100644 index 00000000..bec91351 --- /dev/null +++ b/software/firmware/oracle_same54n19a/oracle.c @@ -0,0 +1,36 @@ +/* + * oracle.c + * + * Created: 5/3/2020 7:24:09 PM + * Author: Penguin + */ +#include "oracle.h" +#include "p_usart.h" +#include "p_gpio.h" +#include "p_i2c.h" +#include "p_tcc.h" +#include "lvgl/lvgl.h" +#include "p_ssd1963.h" +#include "p_screen.h" + + +void oracle_init(void) +{ + // init mcu + init_mcu(); + // uart init + p_usart_init(); + // i2c init + p_i2c_init(); + // gpio init + p_gpio_init(); + // time init + p_tcc_init(); + + p_screen_init(); +} + +void oracle_service(void) +{ + p_screen_service(); +} \ No newline at end of file diff --git a/software/firmware/oracle_same54n19a/oracle_same54n19a.zip b/software/firmware/oracle_same54n19a/oracle_same54n19a.zip new file mode 100644 index 00000000..57c7ac8d Binary files /dev/null and b/software/firmware/oracle_same54n19a/oracle_same54n19a.zip differ diff --git a/software/firmware/oracle_same54n19a/shared/devices/display/p_ssd1963.c b/software/firmware/oracle_same54n19a/shared/devices/display/p_ssd1963.c new file mode 100644 index 00000000..48aefdd1 --- /dev/null +++ b/software/firmware/oracle_same54n19a/shared/devices/display/p_ssd1963.c @@ -0,0 +1,295 @@ +#include "p_ssd1963.h" +#include "p_gpio.h" +#define LV_DRV_DELAY_MS(x) delay_ms(x) +#define LV_DRV_DISP_CMD_DATA(x) gpio_set_pin_level(SSD1963_TFT_RSDC, x) +#define LV_DRV_DISP_RST(x) gpio_set_pin_level(SSD1963_TFT_nRST, x) +#define LV_DRV_DISP_PAR_WR_WORD(x) p_gpio_parallel_write(SSD1963_TFT_DATA_PORT_GROUP, SSD1963_TFT_DATA_MASK, x) +#define LV_DRV_DISP_PAR_WR_ARRAY(x, n) p_gpio_parallel_write_arr(SSD1963_TFT_DATA_PORT_GROUP, SSD1963_TFT_DATA_MASK, x, n) +#define LV_DRV_DISP_PAR_CS(x) gpio_set_pin_level(SSD1963_TFT_CS, x) +/** + * @file SSD1963.c + * + */ + +/********************* + * INCLUDES + *********************/ +#include "p_ssd1963.h" +#if USE_SSD1963 + +#include +/********************* + * DEFINES + *********************/ +#define SSD1963_CMD_MODE 0 +#define SSD1963_DATA_MODE 1 + +/********************** + * TYPEDEFS + **********************/ + +/********************** + * STATIC PROTOTYPES + **********************/ +static inline void ssd1963_cmd_mode(void); +static inline void ssd1963_data_mode(void); +static inline void ssd1963_rd(uint8_t reg, uint16_t* data, uint16_t len); +static inline void ssd1963_wr_bytes(uint8_t reg, const uint16_t* data, uint16_t len); +static inline void ssd1963_cmd(uint8_t cmd); +static inline void ssd1963_data(uint8_t data); +static void ssd1963_io_init(void); +static void ssd1963_reset(void); +static void ssd1963_set_clk(void); +static void ssd1963_set_tft_spec(void); +static void ssd1963_init_bl(void); + +/********************** + * STATIC VARIABLES + **********************/ +static bool cmd_mode = true; + +/********************** + * MACROS + **********************/ + +/********************** + * GLOBAL FUNCTIONS + **********************/ + +void ssd1963_init(void) +{ + ssd1963_reset(); + LV_DRV_DISP_PAR_CS(0); + ssd1963_cmd(0xE2); //PLL multiplier, set PLL clock to 120M + //ssd1963_data(0x23); //N=0x36 for 6.5M, 0x23 for 10M crystal + //ssd1963_data(0x02); + //ssd1963_data(0x54); + ssd1963_data(0x2F); //N=0x36 for 6.5M, 0x23 for 10M crystal + ssd1963_data(0x03); + ssd1963_data(0x54); + + ssd1963_cmd(0xE0); // PLL enable + ssd1963_data(0x01); + delay_us(100); + ssd1963_cmd(0xE0); + ssd1963_data(0x03); // now, use PLL output as system clock + delay_ms(1); + ssd1963_cmd(0x01); + delay_ms(1); + + ssd1963_cmd(0xE6); //PLL setting for PCLK, depends on resolution + //ssd1963_data(0x04); + //ssd1963_data(0x3A); + //ssd1963_data(0xB6); + //ssd1963_data(0x01); + //ssd1963_data(0x55); + //ssd1963_data(0x54); + ssd1963_data(0x01); + ssd1963_data(0xCC); + ssd1963_data(0xCC); + ssd1963_cmd(0xB0); + ssd1963_data(0x28); // set 18-bit for 7" panel TY700TFT800480 + ssd1963_data(0x80); // set TTL mode + ssd1963_data((SSD1963_HOR_RES-1)>>8); //Set panel size + ssd1963_data(SSD1963_HOR_RES-1); + ssd1963_data((SSD1963_VER_RES-1)>>8); + ssd1963_data(SSD1963_VER_RES-1); + ssd1963_data(0x00); + + ssd1963_cmd(0xF0); //Pixel Data Interface Format + ssd1963_data(0x03); //16-bit(565 format) data + + + ssd1963_cmd(0x3A); //Set the current pixel format for RGB image data + ssd1963_data(0x55); //16-bit/pixel + + ssd1963_cmd(0xb4); //SET HBP, + ssd1963_data(0x02); //SET HSYNC Tatol 525 + ssd1963_data(0x0d); + ssd1963_data(0x00); //SET HBP 43 + ssd1963_data(0x2b); + ssd1963_data(0x28); //SET VBP 41=40+1 + ssd1963_data(0x00); //SET Hsync pulse start position + ssd1963_data(0x00); + ssd1963_data(0x00); //SET Hsync pulse subpixel start position + + ssd1963_cmd(0xb6); //SET VBP, + ssd1963_data(0x01); //SET Vsync total 286=285+1 + ssd1963_data(0x1d); + ssd1963_data(0x00); //SET VBP=12 + ssd1963_data(0x0c); + ssd1963_data(0x09); //SET Vsync pulse 10=9+1 + ssd1963_data(0x00); //SET Vsync pulse start position + ssd1963_data(0x00); + + + ssd1963_cmd(0x2a); //SET column address + ssd1963_data(0x00); //SET start column address=0 + ssd1963_data(0x00); + ssd1963_data(0x01); //SET end column address=479 + ssd1963_data(0xDF); + + ssd1963_cmd(0x2b); //SET page address + ssd1963_data(0x00); //SET start page address=0 + ssd1963_data(0x00); + ssd1963_data(0x01); //SET end page address=271 + ssd1963_data(0x0F); + + ssd1963_cmd(0x29); //display on + ssd1963_cmd(0xBE); + ssd1963_data(0x06); + ssd1963_data(0xFF); + ssd1963_data(0x01); + ssd1963_data(0xFF); + ssd1963_data(0x00); + ssd1963_data(0x01); + + LV_DRV_DISP_PAR_CS(1); +} + +void ssd1963_flush(lv_disp_drv_t * disp_drv, const lv_area_t * area, lv_color_t * color_p) +{ + + /*Return if the area is out the screen*/ + if(area->x2 < 0) return; + if(area->y2 < 0) return; + if(area->x1 > SSD1963_HOR_RES - 1) return; + if(area->y1 > SSD1963_VER_RES - 1) return; + + /*Truncate the area to the screen*/ + int32_t act_x1 = area->x1 < 0 ? 0 : area->x1; + int32_t act_y1 = area->y1 < 0 ? 0 : area->y1; + int32_t act_x2 = area->x2 > SSD1963_HOR_RES - 1 ? SSD1963_HOR_RES - 1 : area->x2; + int32_t act_y2 = area->y2 > SSD1963_VER_RES - 1 ? SSD1963_VER_RES - 1 : area->y2; + + //Set the rectangular area + ssd1963_cmd(0x002A); + ssd1963_data(act_x1 >> 8); + ssd1963_data(0x00FF & act_x1); + ssd1963_data(act_x2 >> 8); + ssd1963_data(0x00FF & act_x2); + + ssd1963_cmd(0x002B); + ssd1963_data(act_y1 >> 8); + ssd1963_data(0x00FF & act_y1); + ssd1963_data(act_y2 >> 8); + ssd1963_data(0x00FF & act_y2); + + ssd1963_cmd(0x2c); + int16_t i; + uint16_t full_w = area->x2 - area->x1 + 1; + + ssd1963_data_mode(); + LV_DRV_DISP_PAR_CS(0); +#if LV_COLOR_DEPTH == 16 + uint16_t act_w = act_x2 - act_x1 + 1; + for(i = act_y1; i <= act_y2; i++) { + LV_DRV_DISP_PAR_WR_ARRAY((uint16_t *)color_p, act_w); + color_p += full_w; + } + LV_DRV_DISP_PAR_CS(1); +#else + int16_t j; + for(i = act_y1; i <= act_y2; i++) { + for(j = 0; j <= act_x2 - act_x1 + 1; j++) { + LV_DRV_DISP_PAR_WR_WORD(color_p[j]); + color_p += full_w; + } + } +#endif + + lv_disp_flush_ready(disp_drv); +} + +/********************** + * STATIC FUNCTIONS + **********************/ + +static void ssd1963_io_init(void) +{ + LV_DRV_DISP_CMD_DATA(SSD1963_CMD_MODE); + cmd_mode = true; +} + +static void ssd1963_reset(void) +{ + /*Hardware reset*/ + asm volatile("nop"); + LV_DRV_DISP_RST(1); + LV_DRV_DELAY_MS(50); + LV_DRV_DISP_RST(0); + asm volatile("nop"); + LV_DRV_DELAY_MS(50); + LV_DRV_DISP_RST(1); + LV_DRV_DELAY_MS(50); + + asm volatile("nop"); + /*Chip enable*/ + LV_DRV_DISP_PAR_CS(0); + LV_DRV_DELAY_MS(10); + LV_DRV_DISP_PAR_CS(1); + LV_DRV_DELAY_MS(5); + + /*Software reset*/ + ssd1963_cmd(0x01); + LV_DRV_DELAY_MS(20); + + ssd1963_cmd(0x01); + LV_DRV_DELAY_MS(20); + + ssd1963_cmd(0x01); + LV_DRV_DELAY_MS(20); + +} + +/** + * Command mode + */ +static inline void ssd1963_cmd_mode(void) +{ + if(cmd_mode == false) { + LV_DRV_DISP_CMD_DATA(SSD1963_CMD_MODE); + cmd_mode = true; + } +} + +/** + * Data mode + */ +static inline void ssd1963_data_mode(void) +{ + if(cmd_mode != false) { + LV_DRV_DISP_CMD_DATA(SSD1963_DATA_MODE); + cmd_mode = false; + } +} + +/** + * Write command + * @param cmd the command + */ +static inline void ssd1963_cmd(uint8_t cmd) +{ + + LV_DRV_DISP_PAR_CS(0); + ssd1963_cmd_mode(); + LV_DRV_DISP_PAR_WR_WORD(cmd); + LV_DRV_DISP_PAR_CS(1); + +} + +/** + * Write data + * @param data the data + */ +static inline void ssd1963_data(uint8_t data) +{ + + LV_DRV_DISP_PAR_CS(0); + ssd1963_data_mode(); + LV_DRV_DISP_PAR_WR_WORD(data); + LV_DRV_DISP_PAR_CS(1); + +} + +#endif \ No newline at end of file diff --git a/software/firmware/oracle_same54n19a/shared/devices/display/p_ssd1963.h b/software/firmware/oracle_same54n19a/shared/devices/display/p_ssd1963.h new file mode 100644 index 00000000..3d7eaecf --- /dev/null +++ b/software/firmware/oracle_same54n19a/shared/devices/display/p_ssd1963.h @@ -0,0 +1,166 @@ +/** + * @file SSD1963.h + * + * Source: https://github.com/lvgl/lv_drivers/tree/master/display + */ + +#ifndef SSD1963_H +#define SSD1963_H +#include "oracle.h" +#ifdef __cplusplus +extern "C" { +#endif + +/*---------------- + * SSD1963 + *--------------*/ +#ifndef USE_SSD1963 +# define USE_SSD1963 1 +#endif + +#if USE_SSD1963 +# define SSD1963_HOR_RES LV_HOR_RES +# define SSD1963_VER_RES LV_VER_RES +# define SSD1963_HT 525 // horizontal total period +# define SSD1963_HPS 480 // non-display period between the start of the hori sync (LLINE) signal +# define SSD1963_LPS 40 // horizontal sync pulse (LLINE) start location +# define SSD1963_HPW 5 // horizontal pulse width +# define SSD1963_VT 288 // vertical total (period) +# define SSD1963_VPS 272 // vertical period start ( non-display period in lines between the start of the frame and the first display data in line.) +# define SSD1963_FPS 8 // vertical sync pulse (LFRAME) start location in lines +# define SSD1963_VPW 8 // vertical sync pulse width +# define SSD1963_HS_NEG 0 /*Negative hsync*/ +# define SSD1963_VS_NEG 0 /*Negative vsync*/ +# define SSD1963_ORI 0 /*0, 90, 180, 270*/ +# define SSD1963_COLOR_DEPTH 16 +#endif + +#if USE_SSD1963 + +#ifdef LV_LVGL_H_INCLUDE_SIMPLE +#include "lvgl.h" +#else +#include "lvgl/lvgl.h" +#endif + + + +/********************* + * DEFINES + *********************/ +// SSD1963 command table +#define CMD_NOP 0x00 //No operation +#define CMD_SOFT_RESET 0x01 //Software reset +#define CMD_GET_PWR_MODE 0x0A //Get the current power mode +#define CMD_GET_ADDR_MODE 0x0B //Get the frame memory to the display panel read order +#define CMD_GET_PIXEL_FORMAT 0x0C //Get the current pixel format +#define CMD_GET_DISPLAY_MODE 0x0D //Returns the display mode +#define CMD_GET_SIGNAL_MODE 0x0E // +#define CMD_GET_DIAGNOSTIC 0x0F +#define CMD_ENT_SLEEP 0x10 +#define CMD_EXIT_SLEEP 0x11 +#define CMD_ENT_PARTIAL_MODE 0x12 +#define CMD_ENT_NORMAL_MODE 0x13 +#define CMD_EXIT_INVERT_MODE 0x20 +#define CMD_ENT_INVERT_MODE 0x21 +#define CMD_SET_GAMMA 0x26 +#define CMD_BLANK_DISPLAY 0x28 +#define CMD_ON_DISPLAY 0x29 +#define CMD_SET_COLUMN 0x2A +#define CMD_SET_PAGE 0x2B +#define CMD_WR_MEMSTART 0x2C +#define CMD_RD_MEMSTART 0x2E +#define CMD_SET_PARTIAL_AREA 0x30 +#define CMD_SET_SCROLL_AREA 0x33 +#define CMD_SET_TEAR_OFF 0x34 //synchronization information is not sent from the display +#define CMD_SET_TEAR_ON 0x35 //sync. information is sent from the display +#define CMD_SET_ADDR_MODE 0x36 //set fram buffer read order to the display panel +#define CMD_SET_SCROLL_START 0x37 +#define CMD_EXIT_IDLE_MODE 0x38 +#define CMD_ENT_IDLE_MODE 0x39 +#define CMD_SET_PIXEL_FORMAT 0x3A //defines how many bits per pixel is used +#define CMD_WR_MEM_AUTO 0x3C +#define CMD_RD_MEM_AUTO 0x3E +#define CMD_SET_TEAR_SCANLINE 0x44 +#define CMD_GET_SCANLINE 0x45 +#define CMD_RD_DDB_START 0xA1 +#define CMD_RD_DDB_AUTO 0xA8 +#define CMD_SET_PANEL_MODE 0xB0 +#define CMD_GET_PANEL_MODE 0xB1 +#define CMD_SET_HOR_PERIOD 0xB4 +#define CMD_GET_HOR_PERIOD 0xB5 +#define CMD_SET_VER_PERIOD 0xB6 +#define CMD_GET_VER_PERIOD 0xB7 +#define CMD_SET_GPIO_CONF 0xB8 +#define CMD_GET_GPIO_CONF 0xB9 +#define CMD_SET_GPIO_VAL 0xBA +#define CMD_GET_GPIO_STATUS 0xBB +#define CMD_SET_POST_PROC 0xBC +#define CMD_GET_POST_PROC 0xBD +#define CMD_SET_PWM_CONF 0xBE +#define CMD_GET_PWM_CONF 0xBF +#define CMD_SET_LCD_GEN0 0xC0 +#define CMD_GET_LCD_GEN0 0xC1 +#define CMD_SET_LCD_GEN1 0xC2 +#define CMD_GET_LCD_GEN1 0xC3 +#define CMD_SET_LCD_GEN2 0xC4 +#define CMD_GET_LCD_GEN2 0xC5 +#define CMD_SET_LCD_GEN3 0xC6 +#define CMD_GET_LCD_GEN3 0xC7 +#define CMD_SET_GPIO0_ROP 0xC8 +#define CMD_GET_GPIO0_ROP 0xC9 +#define CMD_SET_GPIO1_ROP 0xCA +#define CMD_GET_GPIO1_ROP 0xCB +#define CMD_SET_GPIO2_ROP 0xCC +#define CMD_GET_GPIO2_ROP 0xCD +#define CMD_SET_GPIO3_ROP 0xCE +#define CMD_GET_GPIO3_ROP 0xCF +#define CMD_SET_ABC_DBC_CONF 0xD0 +#define CMD_GET_ABC_DBC_CONF 0xD1 +#define CMD_SET_DBC_HISTO_PTR 0xD2 +#define CMD_GET_DBC_HISTO_PTR 0xD3 +#define CMD_SET_DBC_THRES 0xD4 +#define CMD_GET_DBC_THRES 0xD5 +#define CMD_SET_ABM_TMR 0xD6 +#define CMD_GET_ABM_TMR 0xD7 +#define CMD_SET_AMB_LVL0 0xD8 +#define CMD_GET_AMB_LVL0 0xD9 +#define CMD_SET_AMB_LVL1 0xDA +#define CMD_GET_AMB_LVL1 0xDB +#define CMD_SET_AMB_LVL2 0xDC +#define CMD_GET_AMB_LVL2 0xDD +#define CMD_SET_AMB_LVL3 0xDE +#define CMD_GET_AMB_LVL3 0xDF +#define CMD_PLL_START 0xE0 //start the PLL +#define CMD_PLL_STOP 0xE1 //disable the PLL +#define CMD_SET_PLL_MN 0xE2 +#define CMD_GET_PLL_MN 0xE3 +#define CMD_GET_PLL_STATUS 0xE4 //get the current PLL status +#define CMD_ENT_DEEP_SLEEP 0xE5 +#define CMD_SET_PCLK 0xE6 //set pixel clock (LSHIFT signal) frequency +#define CMD_GET_PCLK 0xE7 //get pixel clock (LSHIFT signal) freq. settings +#define CMD_SET_DATA_INTERFACE 0xF0 +#define CMD_GET_DATA_INTERFACE 0xF1 + + +/********************** + * TYPEDEFS + **********************/ + +/********************** + * GLOBAL PROTOTYPES + **********************/ +void ssd1963_init(void); +void ssd1963_flush(lv_disp_drv_t * disp_drv, const lv_area_t * area, lv_color_t * color_p); + +/********************** + * MACROS + **********************/ + +#endif /* USE_SSD1963 */ + +#ifdef __cplusplus +} extern "C" +#endif + +#endif /* SSD1963_H */ \ No newline at end of file diff --git a/software/firmware/oracle_same54n19a/shared/devices/p_screen.c b/software/firmware/oracle_same54n19a/shared/devices/p_screen.c new file mode 100644 index 00000000..778b4b40 --- /dev/null +++ b/software/firmware/oracle_same54n19a/shared/devices/p_screen.c @@ -0,0 +1,44 @@ +/* + * p_screen.c + * + * Created: 5/28/2020 3:41:15 AM + * Author: Penguin + */ +#include "p_screen.h" +#include "p_ssd1963.h" +#include "lvgl/lvgl.h" +#include "hornet.h" + +static lv_disp_buf_t disp_buf; +static lv_color_t buf[LV_HOR_RES_MAX * 34]; /*Declare a buffer for 10 lines*/ + +void p_screen_init(void) +{ + // devices init + lv_init(); + + ssd1963_init(); + + + lv_disp_buf_init(&disp_buf, buf, NULL, LV_HOR_RES_MAX * 34); /*Initialize the display buffer*/ + lv_disp_drv_t disp_drv; /*Descriptor of a display driver*/ + lv_disp_drv_init(&disp_drv); /*Basic initialization*/ + disp_drv.flush_cb = ssd1963_flush; /*Set your driver function*/ + disp_drv.buffer = &disp_buf; /*Assign the buffer to the display*/ + lv_disp_drv_register(&disp_drv); /*Finally register the driver*/ + + lv_obj_t* scr = lv_disp_get_scr_act(NULL); + + lv_obj_t* hornet_image = lv_img_create(scr, NULL); + lv_img_set_src(hornet_image, &hornet); + lv_obj_set_pos(hornet_image, 0, 0); + + lv_obj_t* random_text = lv_label_create(scr, NULL); + lv_obj_set_pos(random_text, 90, 35); + lv_label_set_text(random_text, "Hello World"); +} + +void p_screen_service(void) +{ + lv_task_handler(); +} \ No newline at end of file diff --git a/software/firmware/oracle_same54n19a/shared/devices/p_screen.h b/software/firmware/oracle_same54n19a/shared/devices/p_screen.h new file mode 100644 index 00000000..ffc402f7 --- /dev/null +++ b/software/firmware/oracle_same54n19a/shared/devices/p_screen.h @@ -0,0 +1,15 @@ +/* + * p_screen.h + * + * Created: 5/28/2020 3:40:40 AM + * Author: Penguin + */ +#ifndef _P_SCREEN_H_ +#define _P_SCREEN_H_ + +#include "oracle.h" + +void p_screen_init(void); + +void p_screen_service(void); +#endif \ No newline at end of file diff --git a/software/firmware/oracle_same54n19a/shared/drivers/p_gpio.c b/software/firmware/oracle_same54n19a/shared/drivers/p_gpio.c new file mode 100644 index 00000000..ab0757ea --- /dev/null +++ b/software/firmware/oracle_same54n19a/shared/drivers/p_gpio.c @@ -0,0 +1,103 @@ +#include "p_gpio.h" + +static void p_weird_delay(void) +{ + for(int x = 0; x < 8; x++) + { + asm volatile("nop"); + } +} +void p_gpio_init(void) +{ + // set data port config + p_port_config data_config; + memset(&data_config, 0, sizeof(data_config)); + data_config.direction = GPIO_DIRECTION_OUT; + data_config.pull_mode = GPIO_PULL_OFF; + data_config.function = GPIO_PIN_FUNCTION_OFF; + p_gpio_set_port_group_config(SSD1963_TFT_DATA_PORT, SSD1963_TFT_DATA_MASK, &data_config); + + // set lcd control pin configs + // Chip select + gpio_set_pin_direction(SSD1963_TFT_CS, GPIO_DIRECTION_OUT); + gpio_set_pin_pull_mode(SSD1963_TFT_CS, GPIO_PULL_OFF); + gpio_set_pin_function(SSD1963_TFT_CS, GPIO_PIN_FUNCTION_OFF); + + // Reset pin + gpio_set_pin_direction(SSD1963_TFT_nRST, GPIO_DIRECTION_OUT); + gpio_set_pin_pull_mode(SSD1963_TFT_nRST, GPIO_PULL_OFF); + gpio_set_pin_function(SSD1963_TFT_nRST, GPIO_PIN_FUNCTION_OFF); + + // Read pin + gpio_set_pin_direction(SSD1963_TFT_RD, GPIO_DIRECTION_OUT); + gpio_set_pin_pull_mode(SSD1963_TFT_RD, GPIO_PULL_OFF); + gpio_set_pin_function(SSD1963_TFT_RD, GPIO_PIN_FUNCTION_OFF); + + + // RSDC pin, aka Read/Send Data/Command pin + gpio_set_pin_direction(SSD1963_TFT_RSDC, GPIO_DIRECTION_OUT); + gpio_set_pin_pull_mode(SSD1963_TFT_RSDC, GPIO_PULL_OFF); + gpio_set_pin_function(SSD1963_TFT_RSDC, GPIO_PIN_FUNCTION_OFF); + + + // Write Pin + gpio_set_pin_direction(SSD1963_TFT_WR, GPIO_DIRECTION_OUT); + gpio_set_pin_pull_mode(SSD1963_TFT_WR, GPIO_PULL_OFF); + gpio_set_pin_function(SSD1963_TFT_WR, GPIO_PIN_FUNCTION_OFF); + + // TE, tear enable, aka frame sync + gpio_set_pin_direction(SSD1963_TFT_TE, GPIO_DIRECTION_IN); + gpio_set_pin_pull_mode(SSD1963_TFT_TE, GPIO_PULL_DOWN); + gpio_set_pin_function(SSD1963_TFT_TE, GPIO_PIN_FUNCTION_OFF); + + gpio_set_pin_level(SSD1963_TFT_CS, 1); + gpio_set_pin_level(SSD1963_TFT_nRST, 1); + gpio_set_pin_level(SSD1963_TFT_RD, 1); + gpio_set_pin_level(SSD1963_TFT_WR, 1); + + + +} + +void p_gpio_parallel_write(PortGroup* group, uint32_t mask, uint16_t data) +{ + gpio_set_pin_level(SSD1963_TFT_CS, 0); + p_gpio_set_port_data(group, mask, (uint32_t)data); + gpio_set_pin_level(SSD1963_TFT_WR, 0); + gpio_set_pin_level(SSD1963_TFT_WR, 1); + + gpio_set_pin_level(SSD1963_TFT_CS, 1); +} + +void p_gpio_parallel_write_arr(PortGroup* group, uint32_t mask, uint16_t* data, uint16_t len) +{ + for(int ind = 0; ind < len; ind++) + { + p_gpio_parallel_write(group, mask, data[ind]); + } +} + +void p_gpio_set_port_data(PortGroup* const port, const uint32_t mask, const uint32_t data) +{ + uint32_t dword = (uint32_t)(SSD1963_TFT_DATA_FIX(data)); + port->OUTSET.reg = (mask & dword); + port->OUTCLR.reg = (mask & ~dword); +} + +void p_gpio_set_port_group_config(enum gpio_port port, const uint32_t mask, p_port_config* config) +{ + for(uint8_t i = 0; i < 32; i++) + { + if(mask & (1UL << i)) + { + uint32_t _gpio_pin = GPIO(port, i); + gpio_set_pin_direction(_gpio_pin, config->direction); + gpio_set_pin_pull_mode(_gpio_pin, config->pull_mode); + gpio_set_pin_function(_gpio_pin, config->function); + gpio_set_pin_level(_gpio_pin, 0); + } + + } +} + + diff --git a/software/firmware/oracle_same54n19a/shared/drivers/p_gpio.h b/software/firmware/oracle_same54n19a/shared/drivers/p_gpio.h new file mode 100644 index 00000000..b473bb12 --- /dev/null +++ b/software/firmware/oracle_same54n19a/shared/drivers/p_gpio.h @@ -0,0 +1,27 @@ +#ifndef _P_GPIO_H_ +#define _P_GPIO_H_ + +#include "oracle.h" + +#define SSD1963_TFT_DATA_FIX(x) ((x & 0x07) | \ + ((x & 0x1F8) << 1) | \ + ((x & 0x1E00) << 5) | \ + ((x & 0xE000) << 13)) + +typedef struct p_port_config +{ + enum gpio_pull_mode pull_mode; + enum gpio_direction direction; + uint32_t function; +}p_port_config; + +void p_gpio_init(void); + +void p_gpio_parallel_write(PortGroup* group, uint32_t mask, uint16_t data); + +void p_gpio_parallel_write_arr(PortGroup* group, uint32_t mask, uint16_t* data, uint16_t len); + +void p_gpio_set_port_data(PortGroup* const port, const uint32_t mask, const uint32_t data); + +void p_gpio_set_port_group_config(enum gpio_port port, const uint32_t mask, p_port_config* config); +#endif diff --git a/software/firmware/oracle_same54n19a/shared/drivers/p_i2c.c b/software/firmware/oracle_same54n19a/shared/drivers/p_i2c.c new file mode 100644 index 00000000..09bd8a63 --- /dev/null +++ b/software/firmware/oracle_same54n19a/shared/drivers/p_i2c.c @@ -0,0 +1,32 @@ +#include "p_i2c.h" + +struct i2c_m_sync_desc p_i2c_master; + +void p_i2c_init(void) +{ + //// clock init + //hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM3_GCLK_ID_CORE, CONF_GCLK_SERCOM3_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + //hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM3_GCLK_ID_SLOW, CONF_GCLK_SERCOM3_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); +// + //hri_mclk_set_APBBMASK_SERCOM3_bit(MCLK); + // + //i2c_m_sync_init(&p_i2c_master, I2C_MASTER_SERCOM); + // + //// port init + //gpio_set_pin_pull_mode(I2C_MASTER_SDA, GPIO_PULL_OFF); + //gpio_set_pin_function(I2C_MASTER_SDA, I2C_MASTER_SDA_MUX); + //gpio_set_pin_pull_mode(I2C_MASTER_SCL, GPIO_PULL_OFF); + //gpio_set_pin_function(I2C_MASTER_SCL, I2C_MASTER_SCL_MUX); +} + +// +//void I2C_0_example(void) +//{ + //struct io_descriptor *I2C_0_io; +// + //i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_0_io); + //i2c_m_sync_enable(&I2C_0); + //i2c_m_sync_set_slaveaddr(&I2C_0, 0x12, I2C_M_SEVEN); + //io_write(I2C_0_io, (uint8_t *)"Hello World!", 12); +//} +// diff --git a/software/firmware/oracle_same54n19a/shared/drivers/p_i2c.h b/software/firmware/oracle_same54n19a/shared/drivers/p_i2c.h new file mode 100644 index 00000000..ed3a0d0b --- /dev/null +++ b/software/firmware/oracle_same54n19a/shared/drivers/p_i2c.h @@ -0,0 +1,10 @@ +#ifndef _P_I2C_H_ +#define _P_I2C_H_ + +#include "oracle.h" + +extern struct i2c_m_sync_desc p_i2c_master; + +void p_i2c_init(void); + +#endif \ No newline at end of file diff --git a/software/firmware/oracle_same54n19a/shared/drivers/p_tcc.c b/software/firmware/oracle_same54n19a/shared/drivers/p_tcc.c new file mode 100644 index 00000000..17d7d0b2 --- /dev/null +++ b/software/firmware/oracle_same54n19a/shared/drivers/p_tcc.c @@ -0,0 +1,52 @@ +#include "p_tcc.h" +#include "lvgl/lvgl.h" +static struct timer_task TIMER_0_task1, TIMER_0_task2; +struct timer_descriptor p_tcc_inst; + +static volatile uint64_t sys_time = 0; +/** + * Example of using TIMER_0. + */ +static void TIMER_0_task1_cb(const struct timer_task *const timer_task) +{ + sys_time++; + lv_tick_inc(1); +} + +static void TIMER_0_task2_cb(const struct timer_task *const timer_task) +{ +} + +void TIMER_0_example(void) +{ + TIMER_0_task1.interval = 1; + TIMER_0_task1.cb = TIMER_0_task1_cb; + TIMER_0_task1.mode = TIMER_TASK_REPEAT; + //TIMER_0_task2.interval = 200; + //TIMER_0_task2.cb = TIMER_0_task2_cb; + //TIMER_0_task2.mode = TIMER_TASK_REPEAT; + + timer_add_task(&p_tcc_inst, &TIMER_0_task1); + //timer_add_task(&p_tcc_inst, &TIMER_0_task2); + timer_start(&p_tcc_inst); +} + +void p_tcc_init(void) +{ + delay_init(SysTick); + hri_mclk_set_APBAMASK_TC0_bit(MCLK); + hri_gclk_write_PCHCTRL_reg(GCLK, TC0_GCLK_ID, CONF_GCLK_TC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + + timer_init(&p_tcc_inst, TC0, _tc_get_timer()); + + TIMER_0_task1.interval = 1; + TIMER_0_task1.cb = TIMER_0_task1_cb; + TIMER_0_task1.mode = TIMER_TASK_REPEAT; + //TIMER_0_task2.interval = 200; + //TIMER_0_task2.cb = TIMER_0_task2_cb; + //TIMER_0_task2.mode = TIMER_TASK_REPEAT; + + timer_add_task(&p_tcc_inst, &TIMER_0_task1); + //timer_add_task(&p_tcc_inst, &TIMER_0_task2); + timer_start(&p_tcc_inst); +} diff --git a/software/firmware/oracle_same54n19a/shared/drivers/p_tcc.h b/software/firmware/oracle_same54n19a/shared/drivers/p_tcc.h new file mode 100644 index 00000000..5b0295ab --- /dev/null +++ b/software/firmware/oracle_same54n19a/shared/drivers/p_tcc.h @@ -0,0 +1,10 @@ +#ifndef _P_TCC_H_ +#define _P_TCC_H_ + +#include "oracle.h" +extern struct timer_descriptor p_tcc_inst; + +void p_tcc_init(void); + + +#endif \ No newline at end of file diff --git a/software/firmware/oracle_same54n19a/shared/drivers/p_usart.c b/software/firmware/oracle_same54n19a/shared/drivers/p_usart.c new file mode 100644 index 00000000..0c7f1588 --- /dev/null +++ b/software/firmware/oracle_same54n19a/shared/drivers/p_usart.c @@ -0,0 +1,67 @@ +#include "p_usart.h" + +#define DEBUG_USART_EX_BUFF_SIZE 16 +struct usart_async_descriptor p_usart_debug_inst; + +static uint8_t example_USART_0[12] = "Hello World!"; + +static uint8_t debug_buffer[DEBUG_MAX_BUFFER_SIZE]; +static uint8_t debug_rx_buff[DEBUG_USART_EX_BUFF_SIZE]; +void p_usart_init(void) +{ + // clock init + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_CORE, CONF_GCLK_SERCOM0_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM0_GCLK_ID_SLOW, CONF_GCLK_SERCOM0_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos)); + + hri_mclk_set_APBAMASK_SERCOM0_bit(MCLK); + + usart_async_init(&p_usart_debug_inst, USART_DEBUG_SERCOM, debug_rx_buff, DEBUG_USART_EX_BUFF_SIZE, (void*)NULL); + + // port init + gpio_set_pin_function(USART_DEBUG_RX, USART_DEBUG_RX_MUX); + gpio_set_pin_function(USART_DEBUG_TX, USART_DEBUG_TX_MUX); + + usart_async_enable(&p_usart_debug_inst); + + io_write(&p_usart_debug_inst.io, example_USART_0, 12); + + +} + +void p_write(struct usart_async_descriptor* const inst, const uint8_t* data, uint16_t len) +{ + +} + +void p_debug(const char* str, ...) +{ + +} + + + +/** + * Example of using USART_0 to write "Hello World" using the IO abstraction. + * + * Since the driver is asynchronous we need to use statically allocated memory for string + * because driver initiates transfer and then returns before the transmission is completed. + * + * Once transfer has been completed the tx_cb function will be called. + */ +static void tx_cb_USART_0(const struct usart_async_descriptor *const io_descr) +{ + /* Transfer completed */ +} +// +//void USART_0_example(void) +//{ + //struct io_descriptor *io; +// + //usart_async_register_callback(&USART_0, USART_ASYNC_TXC_CB, tx_cb_USART_0); + ///*usart_async_register_callback(&USART_0, USART_ASYNC_RXC_CB, rx_cb); + //usart_async_register_callback(&USART_0, USART_ASYNC_ERROR_CB, err_cb);*/ + //usart_async_get_io_descriptor(&USART_0, &io); + //usart_async_enable(&USART_0); +// + //io_write(io, example_USART_0, 12); +//} diff --git a/software/firmware/oracle_same54n19a/shared/drivers/p_usart.h b/software/firmware/oracle_same54n19a/shared/drivers/p_usart.h new file mode 100644 index 00000000..5da95775 --- /dev/null +++ b/software/firmware/oracle_same54n19a/shared/drivers/p_usart.h @@ -0,0 +1,14 @@ +#ifndef _P_USART_H_ +#define _P_USART_H_ + +#include "oracle.h" + +extern struct usart_async_descriptor p_usart_debug_inst; + +void p_usart_init(void); + +void p_write(struct usart_async_descriptor* const inst, const uint8_t* data, uint16_t len); + +void p_debug(const char* str, ...); + +#endif \ No newline at end of file diff --git a/software/firmware/oracle_same54n19a/shared/thirdparty b/software/firmware/oracle_same54n19a/shared/thirdparty new file mode 120000 index 00000000..41848cf6 --- /dev/null +++ b/software/firmware/oracle_same54n19a/shared/thirdparty @@ -0,0 +1 @@ +/home/penguin/Projects/Embedded-Graphics-Learning/software/thirdparty \ No newline at end of file