// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/* Copyright (c) 2020-2021 Microchip Technology Inc */

#include "dt-bindings/mailbox/miv-ihc.h"

/ {
	compatible = "microchip,mpfs-icicle-reference-rtlv2210";

	fabric-bus@40000000 {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>, /* FIC3-FAB */
			 <0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>, /* FIC0, LO */
			 <0x0 0xe0000000 0x0 0xe0000000 0x0 0x20000000>, /* FIC1, LO */
			 <0x20 0x0 0x20 0x0 0x10 0x0>, /* FIC0,HI */
			 <0x30 0x0 0x30 0x0 0x10 0x0>; /* FIC1,HI */

//		core_pwm0: pwm@40000000 {
//			compatible = "microchip,corepwm-rtl-v4";
//			reg = <0x0 0x40000000 0x0 0xF0>;
//			microchip,sync-update-mask = /bits/ 32 <0>;
//			#pwm-cells = <2>;
//			clocks = <&fabric_clk3>;
//			status = "disabled";
//		};

		fabric_clk3: fabric-clk3 {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <50000000>;
		};

		fabric_clk1: fabric-clk1 {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <125000000>;
		};

		cape_gpios_p8: gpio@41100000 {
			compatible = "microchip,core-gpio";
			reg = <0x0 0x41100000 0x0 0x1000>;
			clocks = <&fabric_clk3>;
			gpio-controller;
			#gpio-cells = <2>;
			ngpios=<16>;
			gpio-line-names = "P8_PIN31", "P8_PIN32", "P8_PIN33", "P8_PIN34",
			                  "P8_PIN35", "P8_PIN36", "P8_PIN37", "P8_PIN38",
			                  "P8_PIN39", "P8_PIN40", "P8_PIN41", "P8_PIN42",
							  "P8_PIN43", "P8_PIN44", "P8_PIN45", "P8_PIN46";
		};

		cape_gpios_p9: gpio@41200000 {
			compatible = "microchip,core-gpio";
			reg = <0x0 0x41200000 0x0 0x1000>;
			clocks = <&fabric_clk3>;
			gpio-controller;
			#gpio-cells = <2>;
			ngpios=<21>;
			gpio-line-names = "P9_PIN11", "P9_PIN12", "P9_PIN13", "P9_PIN14",
			                  "P9_PIN15", "P9_PIN16", "P9_PIN17", "P9_PIN18",
			                  "P9_PIN21", "P9_PIN22", "P9_PIN23", "P9_PIN24",
			                  "P9_PIN25", "P9_PIN26", "P9_PIN27", "P9_PIN28",
							  "P9_PIN29", "P9_PIN31", "P9_PIN41", "P9_PIN42";
		};

		hsi_gpios: gpio@44000000 {
			compatible = "microchip,core-gpio";
			reg = <0x0 0x44000000 0x0 0x1000>;
			clocks = <&fabric_clk3>;
			gpio-controller;
			#gpio-cells = <2>;
			ngpios=<20>;
			gpio-line-names = "B0_HSIO70N", "B0_HSIO71N", "B0_HSIO83N", "B0_HSIO73N_C2P_CLKN",
			                  "B0_HSIO70P", "B0_HSIO71P", "B0_HSIO83P", "B0_HSIO73N_C2P_CLKP",
			                  "XCVR1_RX_VALID", "XCVR1_LOCK", "XCVR1_ERROR",
							  "XCVR2_RX_VALID", "XCVR2_LOCK", "XCVR2_ERROR",
							  "XCVR3_RX_VALID", "XCVR3_LOCK", "XCVR3_ERROR", 
							  "XCVR_0B_REF_CLK_PLL_LOCK", "XCVR_0C_REF_CLK_PLL_LOCK", "B0_HSIO81N";
		};
	};

	ihc: mailbox {
		compatible = "microchip,miv-ihc";
		interrupt-parent = <&plic>;
		interrupts = <IHC_HART1_INT>;
		microchip,miv-ihc-remote-context-id = <IHC_CONTEXT_B>;
		#mbox-cells = <1>;
		status = "disabled";
	};

	fabric-pcie-bus@3000000000 {
		compatible = "simple-bus";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>,
			 <0x30 0x0 0x30 0x0 0x10 0x0>;
		dma-ranges = <0x0 0x0 0x0 0x80000000 0x0 0x4000000>,
			     <0x0 0x4000000 0x0 0xc4000000 0x0 0x6000000>,
			     <0x0 0xa000000 0x0 0x8a000000 0x0 0x8000000>,
			     <0x0 0x12000000 0x14 0x12000000 0x0 0x10000000>,
			     <0x0 0x22000000 0x10 0x22000000 0x0 0x5e000000>;

		pcie: pcie@3000000000 {
			compatible = "microchip,pcie-host-1.0";
			#address-cells = <0x3>;
			#interrupt-cells = <0x1>;
			#size-cells = <0x2>;
			device_type = "pci";
			dma-noncoherent;
			reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>;
			reg-names = "cfg", "apb";
			bus-range = <0x0 0x7f>;
			interrupt-parent = <&plic>;
			interrupts = <119>;
			interrupt-map = <0 0 0 1 &pcie_intc 0>,
					<0 0 0 2 &pcie_intc 1>,
					<0 0 0 3 &pcie_intc 2>,
					<0 0 0 4 &pcie_intc 3>;
			interrupt-map-mask = <0 0 0 7>;
			clocks = <&ccc_nw CLK_CCC_PLL0_OUT1>, <&ccc_nw CLK_CCC_PLL0_OUT3>;
			clock-names = "fic1", "fic3";
			ranges = <0x43000000 0x0 0x9000000 0x30 0x9000000 0x0 0xf000000>,
				 <0x1000000 0x0 0x8000000 0x30 0x8000000 0x0 0x1000000>,
				 <0x3000000 0x0 0x18000000 0x30 0x18000000 0x0 0x70000000>;
			dma-ranges = <0x3000000 0x0 0x80000000 0x0 0x0 0x0 0x4000000>,
				     <0x3000000 0x0 0x84000000 0x0 0x4000000 0x0 0x6000000>,
				     <0x3000000 0x0 0x8a000000 0x0 0xa000000 0x0 0x8000000>,
				     <0x3000000 0x0 0x92000000 0x0 0x12000000 0x0 0x10000000>,
				     <0x3000000 0x0 0xa2000000 0x0 0x22000000 0x0 0x5e000000>;
			msi-parent = <&pcie>;
			msi-controller;
			status = "disabled";

			pcie_intc: interrupt-controller {
				#address-cells = <0>;
				#interrupt-cells = <1>;
				interrupt-controller;
			};
		};
	};

	refclk_ccc: cccrefclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
	};
};

&ccc_nw {
	clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>,
		 <&refclk_ccc>, <&refclk_ccc>;
	clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1",
		      "dll0_ref", "dll1_ref";
	status = "okay";
};