From d13d0732b25a64b328da6bea3ca20936fc863d39 Mon Sep 17 00:00:00 2001 From: Robert Nelson Date: Tue, 15 Aug 2023 12:43:43 -0500 Subject: [PATCH] linux: make it easlier to compare dts and build mainline Signed-off-by: Robert Nelson --- 01_git_sync.sh | 3 + 04_build_linux.sh | 43 +- .../linux/dts/mpfs-beaglev-fire-fabric.dtsi | 156 +++++++ patches/linux/dts/mpfs-beaglev-fire.dts | 380 ++++++++++++++++++ patches/linux/mainline/Makefile | 8 + .../dts/mpfs-beaglev-fire-fabric.dtsi | 71 ++++ .../linux/mainline/dts/mpfs-beaglev-fire.dts | 363 +++++++++++++++++ 7 files changed, 1014 insertions(+), 10 deletions(-) create mode 100644 patches/linux/dts/mpfs-beaglev-fire-fabric.dtsi create mode 100644 patches/linux/dts/mpfs-beaglev-fire.dts create mode 100644 patches/linux/mainline/Makefile create mode 100644 patches/linux/mainline/dts/mpfs-beaglev-fire-fabric.dtsi create mode 100644 patches/linux/mainline/dts/mpfs-beaglev-fire.dts diff --git a/01_git_sync.sh b/01_git_sync.sh index 95664a9..c39cda5 100755 --- a/01_git_sync.sh +++ b/01_git_sync.sh @@ -10,6 +10,9 @@ UBOOT_REPO="https://github.com/polarfire-soc/u-boot.git" LINUX_BRANCH="linux4microchip+fpga-2023.06" LINUX_REPO="https://github.com/linux4microchip/linux.git" +#LINUX_BRANCH="master" +#LINUX_REPO="https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git" + GIT_DEPTH="20" if [ ! -f ./mirror/x86_64-gcc-11.4.0-nolibc-riscv64-linux.tar.xz ] ; then diff --git a/04_build_linux.sh b/04_build_linux.sh index f112ffb..ba99a2b 100755 --- a/04_build_linux.sh +++ b/04_build_linux.sh @@ -7,20 +7,35 @@ CC=${CC:-"${wdir}/riscv-toolchain/bin/riscv64-linux-"} cd ./linux/ if [ ! -f ./.patched ] ; then - patch -p1 < ../patches/linux/0001-Add-BeagleV-Fire-device-tree.patch - patch -p1 < ../patches/linux/0001-PCIe-Change-controller-and-bridge-base-address.patch - patch -p1 < ../patches/linux/0001-GPIO-Add-Microchip-CoreGPIO-driver.patch - patch -p1 < ../patches/linux/0001-ADC-Add-Microchip-MCP356X-driver.patch - patch -p1 < ../patches/linux/0001-Microchip-QSPI-Add-regular-transfers.patch - patch -p1 < ../patches/linux/0001-BeagleV-Fire-Add-printk-to-IM219-driver-for-board-te.patch - patch -p1 < ../patches/linux/0001-MMC-SPI-Hack-to-support-non-DMA-capable-SPI-ctrl.patch + if [ -f arch/riscv/configs/mpfs_defconfig ] ; then + patch -p1 < ../patches/linux/0001-Add-BeagleV-Fire-device-tree.patch + patch -p1 < ../patches/linux/0001-PCIe-Change-controller-and-bridge-base-address.patch + patch -p1 < ../patches/linux/0001-GPIO-Add-Microchip-CoreGPIO-driver.patch + patch -p1 < ../patches/linux/0001-ADC-Add-Microchip-MCP356X-driver.patch + patch -p1 < ../patches/linux/0001-Microchip-QSPI-Add-regular-transfers.patch + patch -p1 < ../patches/linux/0001-BeagleV-Fire-Add-printk-to-IM219-driver-for-board-te.patch + patch -p1 < ../patches/linux/0001-MMC-SPI-Hack-to-support-non-DMA-capable-SPI-ctrl.patch + fi touch .patched fi -cp -v ../patches/linux/Makefile arch/riscv/boot/dts/microchip/ +if [ -f arch/riscv/configs/mpfs_defconfig ] ; then + cp -v ../patches/linux/Makefile arch/riscv/boot/dts/microchip/Makefile + cp -v ../patches/linux/dts/mpfs-beaglev-fire.dts arch/riscv/boot/dts/microchip/ + cp -v ../patches/linux/dts/mpfs-beaglev-fire-fabric.dtsi arch/riscv/boot/dts/microchip/ +else + cp -v ../patches/linux/mainline/Makefile arch/riscv/boot/dts/microchip/Makefile + cp -v ../patches/linux/mainline/dts/mpfs-beaglev-fire.dts arch/riscv/boot/dts/microchip/ + cp -v ../patches/linux/mainline/dts/mpfs-beaglev-fire-fabric.dtsi arch/riscv/boot/dts/microchip/ +fi make ARCH=riscv CROSS_COMPILE=${CC} clean -make ARCH=riscv CROSS_COMPILE=${CC} mpfs_defconfig + +if [ -f arch/riscv/configs/mpfs_defconfig ] ; then + make ARCH=riscv CROSS_COMPILE=${CC} mpfs_defconfig +else + make ARCH=riscv CROSS_COMPILE=${CC} defconfig +fi # # Scheduler features @@ -134,7 +149,15 @@ tar --create --gzip --file "../${KERNEL_UTS}-modules.tar.gz" ./* cd "${wdir}/linux/" || exit rm -rf "${wdir}/deploy/tmp" || true -cp -v ./.config ../patches/linux/mpfs_defconfig +if [ -f arch/riscv/configs/mpfs_defconfig ] ; then + cp -v ./.config ../patches/linux/mpfs_defconfig + cp -v ./arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts ../patches/linux/dts/mpfs-beaglev-fire.dts + cp -v ./arch/riscv/boot/dts/microchip/mpfs-beaglev-fire-fabric.dtsi ../patches/linux/dts/mpfs-beaglev-fire-fabric.dtsi +else + cp -v ./.config ../patches/linux/mainline/defconfig + cp -v ./arch/riscv/boot/dts/microchip/mpfs-beaglev-fire.dts ../patches/linux/mainline/dts/mpfs-beaglev-fire.dts + cp -v ./arch/riscv/boot/dts/microchip/mpfs-beaglev-fire-fabric.dtsi ../patches/linux/mainline/dts/mpfs-beaglev-fire-fabric.dtsi +fi if [ ! -d ../deploy/input/ ] ; then mkdir -p ../deploy/input/ || true fi diff --git a/patches/linux/dts/mpfs-beaglev-fire-fabric.dtsi b/patches/linux/dts/mpfs-beaglev-fire-fabric.dtsi new file mode 100644 index 0000000..c6f2c7e --- /dev/null +++ b/patches/linux/dts/mpfs-beaglev-fire-fabric.dtsi @@ -0,0 +1,156 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2021 Microchip Technology Inc */ + +#include "dt-bindings/mailbox/miv-ihc.h" + +/ { + compatible = "microchip,mpfs-icicle-reference-rtlv2210"; + + fabric-bus@40000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>, /* FIC3-FAB */ + <0x0 0x60000000 0x0 0x60000000 0x0 0x20000000>, /* FIC0, LO */ + <0x0 0xe0000000 0x0 0xe0000000 0x0 0x20000000>, /* FIC1, LO */ + <0x20 0x0 0x20 0x0 0x10 0x0>, /* FIC0,HI */ + <0x30 0x0 0x30 0x0 0x10 0x0>; /* FIC1,HI */ + +// core_pwm0: pwm@40000000 { +// compatible = "microchip,corepwm-rtl-v4"; +// reg = <0x0 0x40000000 0x0 0xF0>; +// microchip,sync-update-mask = /bits/ 32 <0>; +// #pwm-cells = <2>; +// clocks = <&fabric_clk3>; +// status = "disabled"; +// }; + + fabric_clk3: fabric-clk3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <50000000>; + }; + + fabric_clk1: fabric-clk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + cape_gpios_p8: gpio@41100000 { + compatible = "microchip,core-gpio"; + reg = <0x0 0x41100000 0x0 0x1000>; + clocks = <&fabric_clk3>; + gpio-controller; + #gpio-cells = <2>; + ngpios=<16>; + gpio-line-names = "P8_PIN31", "P8_PIN32", "P8_PIN33", "P8_PIN34", + "P8_PIN35", "P8_PIN36", "P8_PIN37", "P8_PIN38", + "P8_PIN39", "P8_PIN40", "P8_PIN41", "P8_PIN42", + "P8_PIN43", "P8_PIN44", "P8_PIN45", "P8_PIN46"; + }; + + cape_gpios_p9: gpio@41200000 { + compatible = "microchip,core-gpio"; + reg = <0x0 0x41200000 0x0 0x1000>; + clocks = <&fabric_clk3>; + gpio-controller; + #gpio-cells = <2>; + ngpios=<21>; + gpio-line-names = "P9_PIN11", "P9_PIN12", "P9_PIN13", "P9_PIN14", + "P9_PIN15", "P9_PIN16", "P9_PIN17", "P9_PIN18", + "P9_PIN21", "P9_PIN22", "P9_PIN23", "P9_PIN24", + "P9_PIN25", "P9_PIN26", "P9_PIN27", "P9_PIN28", + "P9_PIN29", "P9_PIN31", "P9_PIN41", "P9_PIN42"; + }; + + hsi_gpios: gpio@44000000 { + compatible = "microchip,core-gpio"; + reg = <0x0 0x44000000 0x0 0x1000>; + clocks = <&fabric_clk3>; + gpio-controller; + #gpio-cells = <2>; + ngpios=<20>; + gpio-line-names = "B0_HSIO70N", "B0_HSIO71N", "B0_HSIO83N", "B0_HSIO73N_C2P_CLKN", + "B0_HSIO70P", "B0_HSIO71P", "B0_HSIO83P", "B0_HSIO73N_C2P_CLKP", + "XCVR1_RX_VALID", "XCVR1_LOCK", "XCVR1_ERROR", + "XCVR2_RX_VALID", "XCVR2_LOCK", "XCVR2_ERROR", + "XCVR3_RX_VALID", "XCVR3_LOCK", "XCVR3_ERROR", + "XCVR_0B_REF_CLK_PLL_LOCK", "XCVR_0C_REF_CLK_PLL_LOCK", "B0_HSIO81N"; + }; + }; + + ihc: mailbox { + compatible = "microchip,miv-ihc"; + interrupt-parent = <&plic>; + interrupts = ; + microchip,miv-ihc-remote-context-id = ; + #mbox-cells = <1>; + status = "disabled"; + }; + + fabric-pcie-bus@3000000000 { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x0 0x40000000 0x0 0x40000000 0x0 0x20000000>, + <0x30 0x0 0x30 0x0 0x10 0x0>; + dma-ranges = <0x0 0x0 0x0 0x80000000 0x0 0x4000000>, + <0x0 0x4000000 0x0 0xc4000000 0x0 0x6000000>, + <0x0 0xa000000 0x0 0x8a000000 0x0 0x8000000>, + <0x0 0x12000000 0x14 0x12000000 0x0 0x10000000>, + <0x0 0x22000000 0x10 0x22000000 0x0 0x5e000000>; + + pcie: pcie@3000000000 { + compatible = "microchip,pcie-host-1.0"; + #address-cells = <0x3>; + #interrupt-cells = <0x1>; + #size-cells = <0x2>; + device_type = "pci"; + dma-noncoherent; + reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; + reg-names = "cfg", "apb"; + bus-range = <0x0 0x7f>; + interrupt-parent = <&plic>; + interrupts = <119>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask = <0 0 0 7>; + clocks = <&ccc_nw CLK_CCC_PLL0_OUT1>, <&ccc_nw CLK_CCC_PLL0_OUT3>; + clock-names = "fic1", "fic3"; + ranges = <0x43000000 0x0 0x9000000 0x30 0x9000000 0x0 0xf000000>, + <0x1000000 0x0 0x8000000 0x30 0x8000000 0x0 0x1000000>, + <0x3000000 0x0 0x18000000 0x30 0x18000000 0x0 0x70000000>; + dma-ranges = <0x3000000 0x0 0x80000000 0x0 0x0 0x0 0x4000000>, + <0x3000000 0x0 0x84000000 0x0 0x4000000 0x0 0x6000000>, + <0x3000000 0x0 0x8a000000 0x0 0xa000000 0x0 0x8000000>, + <0x3000000 0x0 0x92000000 0x0 0x12000000 0x0 0x10000000>, + <0x3000000 0x0 0xa2000000 0x0 0x22000000 0x0 0x5e000000>; + msi-parent = <&pcie>; + msi-controller; + status = "disabled"; + + pcie_intc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + }; + + refclk_ccc: cccrefclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; +}; + +&ccc_nw { + clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, + <&refclk_ccc>, <&refclk_ccc>; + clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1", + "dll0_ref", "dll1_ref"; + status = "okay"; +}; + diff --git a/patches/linux/dts/mpfs-beaglev-fire.dts b/patches/linux/dts/mpfs-beaglev-fire.dts new file mode 100644 index 0000000..0c60892 --- /dev/null +++ b/patches/linux/dts/mpfs-beaglev-fire.dts @@ -0,0 +1,380 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2021 Microchip Technology Inc */ + +/dts-v1/; + +#include +#include "mpfs.dtsi" +#include "mpfs-beaglev-fire-fabric.dtsi" + +/* Clock frequency (in Hz) of the rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "BeagleBoard BeagleV-Fire"; + compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs"; + + soc { + dma-ranges = <0x14 0x0 0x0 0x80000000 0x0 0x4000000>, + <0x14 0x4000000 0x0 0xc4000000 0x0 0x6000000>, + <0x14 0xa000000 0x0 0x8a000000 0x0 0x8000000>, + <0x14 0x12000000 0x14 0x12000000 0x0 0x10000000>, + <0x14 0x22000000 0x10 0x22000000 0x0 0x5e000000>; + }; + + aliases { + ethernet0 = &mac1; + serial0 = &mmuart0; + serial1 = &mmuart1; + serial2 = &mmuart2; + serial3 = &mmuart3; + serial4 = &mmuart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + timebase-frequency = ; + }; + + kernel: memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x4000000>; + }; + + ddr_cached_low: memory@8a000000 { + device_type = "memory"; + reg = <0x0 0x8a000000 0x0 0x8000000>; + }; + + ddr_non_cached_low: memory@c4000000 { + device_type = "memory"; + reg = <0x0 0xc4000000 0x0 0x6000000>; + }; + + ddr_cached_high: memory@1022000000 { + device_type = "memory"; + reg = <0x10 0x22000000 0x0 0x5e000000>; + }; + + ddr_non_cached_high: memory@1412000000 { + device_type = "memory"; + reg = <0x14 0x12000000 0x0 0x10000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hss: hss-buffer@103fc00000 { + compatible = "shared-dma-pool"; + reg = <0x10 0x3fc00000 0x0 0x400000>; + no-map; + }; + + dma_non_cached_low: non-cached-low-buffer { + compatible = "shared-dma-pool"; + size = <0x0 0x4000000>; + no-map; + linux,dma-default; + alloc-ranges = <0x0 0xc4000000 0x0 0x4000000>; + }; + + dma_non_cached_high: non-cached-high-buffer { + compatible = "shared-dma-pool"; + size = <0x0 0x10000000>; + no-map; + linux,dma-default; + alloc-ranges = <0x14 0x12000000 0x0 0x10000000>; + }; + }; + + imx219_vana: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "imx219_vana"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + imx219_vdig: fixedregulator@1 { + compatible = "regulator-fixed"; + regulator-name = "imx219_vdig"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + imx219_vddl: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "imx219_vddl"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + + imx219_clk: camera-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + +}; + +&gpio0 { + ngpios=<14>; + gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "", "SD_CARD_CS", "USER_BUTTON"; + status = "okay"; + + sd_card_cs { + gpio-hog; + gpios = <12 12>; + output_high; + line-name = "SD_CARD_CS"; + }; + + user_button { + gpio-hog; + gpios = <13 13>; + input; + line-name = "USER_BUTTON"; + }; +}; + +&gpio1 { + ngpios=<24>; + gpio-line-names = "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "ADC_IRQn", "", "", "USB_OCn"; + status = "okay"; + + adc_irqn { + gpio-hog; + gpios = <20 20>; + input; + line-name = "ADC_IRQn"; + }; + + user_button { + gpio-hog; + gpios = <23 23>; + input; + line-name = "USB_OCn"; + }; + +}; + +&gpio2 { + interrupts = <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>; + gpio-line-names = "P8_PIN3_USER_LED_0", "P8_PIN4_USER_LED_1", "P8_PIN5_USER_LED_2", + "P8_PIN6_USER_LED_3", "P8_PIN7_USER_LED_4", "P8_PIN8_USER_LED_5", + "P8_PIN9_USER_LED_6", "P8_PIN10_USER_LED_7", "P8_PIN11_USER_LED_8", + "P8_PIN12_USER_LED_9", "P8_PIN13_USER_LED_10", "P8_PIN14_USER_LED_11", + "P8_PIN15", "P8_PIN16", "P8_PIN17", "P8_PIN18", "P8_PIN19", + "P8_PIN20", "P8_PIN21", "P8_PIN22", "P8_PIN23", "P8_PIN24", + "P8_PIN25", "P8_PIN26", "P8_PIN27", "P8_PIN28", "P8_PIN29", + "P8_PIN30", + "M2_W_DISABLE1", "M2_W_DISABLE2", + "VIO_ENABLE", "SD_DET"; + status = "okay"; + + vio_enable { + gpio-hog; + gpios = <30 30>; + output_high; + line-name = "VIO_ENABLE"; + }; + + sd_det { + gpio-hog; + gpios = <31 31>; + input; + line-name = "SD_DET"; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + eeprom: eeprom@50 { + compatible = "at,24c32"; + reg = <0x50>; + }; + + imx219: sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + clocks = <&imx219_clk>; + VANA-supply = <&imx219_vana>; /* 2.8v */ + VDIG-supply = <&imx219_vdig>; /* 1.8v */ + VDDL-supply = <&imx219_vddl>; /* 1.2v */ + + port { + imx219_0: endpoint { +// remote-endpoint = <&csi1_ep>; + data-lanes = <1 2>; + clock-noncontinuous; + link-frequencies = /bits/ 64 <456000000>; + }; + }; + }; + + + +}; + +&mac0 { + dma-noncoherent; + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&phy0>; + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&mac1 { + dma-noncoherent; + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&phy1>; + phy1: ethernet-phy@0 { + reg = <0>; + }; +}; + +&mbox { + status = "okay"; +}; + +//&mmc { +// status = "okay"; +// bus-width = <8>; +// disable-wp; +// cap-mmc-highspeed; +// mmc-ddr-1_8v; +// mmc-hs200-1_8v; +//}; + +&mmc { + dma-noncoherent; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + + +&mmuart0 { + status = "okay"; +}; + +&mmuart1 { + status = "okay"; +}; + +//&mmuart2 { +// status = "okay"; +//}; + +//&mmuart3 //{ +// statu//s = "okay"; +//};// +// +//&mmuart4 { +// status = "okay"; +//}; + +//&pcie { +// status = "okay"; +//}; + +&qspi { + status = "okay"; + cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>, <&gpio0 12 GPIO_ACTIVE_LOW>; + num-cs = <2>; + + + mcp3464: mcp3464@0 { + compatible = "microchip,mcp3464r"; + reg = <0>; /* CE0 */ + spi-cpol; + spi-cpha; + spi-max-frequency = <15000000>; + status = "okay"; + microchip,hw-device-address = <1>; + }; + + mmc-slot@1 { + compatible = "mmc-spi-slot"; + reg = <1>; + gpios = <&gpio2 31 1>; + voltage-ranges = <3300 3300>; + spi-max-frequency = <15000000>; + disable-wp; + }; +}; + +&refclk { + clock-frequency = <125000000>; +}; + +&refclk_ccc { + clock-frequency = <50000000>; +}; + +&rtc { + status = "okay"; +}; + +&spi0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + +&syscontroller { + microchip,bitstream-flash = <&sys_ctrl_flash>; + status = "okay"; +}; + +&syscontroller_qspi { + status = "okay"; + + sys_ctrl_flash: flash@0 { // MT25QL01GBBB8ESF-0SIT + compatible = "jedec,spi-nor"; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <20000000>; + spi-rx-bus-width = <1>; + reg = <0>; + }; +}; + + +&usb { + dma-noncoherent; + status = "okay"; + dr_mode = "otg"; +}; diff --git a/patches/linux/mainline/Makefile b/patches/linux/mainline/Makefile new file mode 100644 index 0000000..65af281 --- /dev/null +++ b/patches/linux/mainline/Makefile @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb +dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb +dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb +dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-sev-kit.dtb +dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-tysom-m.dtb +dtb-$(CONFIG_ARCH_MICROCHIP_POLARFIRE) += mpfs-beaglev-fire.dtb +obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/patches/linux/mainline/dts/mpfs-beaglev-fire-fabric.dtsi b/patches/linux/mainline/dts/mpfs-beaglev-fire-fabric.dtsi new file mode 100644 index 0000000..1069134 --- /dev/null +++ b/patches/linux/mainline/dts/mpfs-beaglev-fire-fabric.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2021 Microchip Technology Inc */ + +/ { + compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit", + "microchip,mpfs"; + + core_pwm0: pwm@40000000 { + compatible = "microchip,corepwm-rtl-v4"; + reg = <0x0 0x40000000 0x0 0xF0>; + microchip,sync-update-mask = /bits/ 32 <0>; + #pwm-cells = <3>; + clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>; + status = "disabled"; + }; + + i2c2: i2c@40000200 { + compatible = "microchip,corei2c-rtl-v7"; + reg = <0x0 0x40000200 0x0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&ccc_nw CLK_CCC_PLL0_OUT3>; + interrupt-parent = <&plic>; + interrupts = <122>; + clock-frequency = <100000>; + status = "disabled"; + }; + + pcie: pcie@3000000000 { + compatible = "microchip,pcie-host-1.0"; + #address-cells = <0x3>; + #interrupt-cells = <0x1>; + #size-cells = <0x2>; + device_type = "pci"; + reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; + reg-names = "cfg", "apb"; + bus-range = <0x0 0x7f>; + interrupt-parent = <&plic>; + interrupts = <119>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask = <0 0 0 7>; + clocks = <&ccc_nw CLK_CCC_PLL0_OUT1>, <&ccc_nw CLK_CCC_PLL0_OUT3>; + clock-names = "fic1", "fic3"; + ranges = <0x3000000 0x0 0x8000000 0x30 0x8000000 0x0 0x80000000>; + dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>; + msi-parent = <&pcie>; + msi-controller; + status = "disabled"; + pcie_intc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + refclk_ccc: cccrefclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; +}; + +&ccc_nw { + clocks = <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, <&refclk_ccc>, + <&refclk_ccc>, <&refclk_ccc>; + clock-names = "pll0_ref0", "pll0_ref1", "pll1_ref0", "pll1_ref1", + "dll0_ref", "dll1_ref"; + status = "okay"; +}; diff --git a/patches/linux/mainline/dts/mpfs-beaglev-fire.dts b/patches/linux/mainline/dts/mpfs-beaglev-fire.dts new file mode 100644 index 0000000..451ae70 --- /dev/null +++ b/patches/linux/mainline/dts/mpfs-beaglev-fire.dts @@ -0,0 +1,363 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2020-2021 Microchip Technology Inc */ + +/dts-v1/; + +#include "mpfs.dtsi" +#include "mpfs-beaglev-fire-fabric.dtsi" +#include +#include + +/* Clock frequency (in Hz) of the rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "BeagleBoard BeagleV-Fire"; + compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs"; + + soc { + dma-ranges = <0x14 0x0 0x0 0x80000000 0x0 0x4000000>, + <0x14 0x4000000 0x0 0xc4000000 0x0 0x6000000>, + <0x14 0xa000000 0x0 0x8a000000 0x0 0x8000000>, + <0x14 0x12000000 0x14 0x12000000 0x0 0x10000000>, + <0x14 0x22000000 0x10 0x22000000 0x0 0x5e000000>; + }; + + aliases { + ethernet0 = &mac1; + serial0 = &mmuart0; + serial1 = &mmuart1; + serial2 = &mmuart2; + serial3 = &mmuart3; + serial4 = &mmuart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + cpus { + timebase-frequency = ; + }; + + kernel: memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x4000000>; + }; + + ddr_cached_low: memory@8a000000 { + device_type = "memory"; + reg = <0x0 0x8a000000 0x0 0x8000000>; + }; + + ddr_non_cached_low: memory@c4000000 { + device_type = "memory"; + reg = <0x0 0xc4000000 0x0 0x6000000>; + }; + + ddr_cached_high: memory@1022000000 { + device_type = "memory"; + reg = <0x10 0x22000000 0x0 0x5e000000>; + }; + + ddr_non_cached_high: memory@1412000000 { + device_type = "memory"; + reg = <0x14 0x12000000 0x0 0x10000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + hss: hss-buffer@103fc00000 { + compatible = "shared-dma-pool"; + reg = <0x10 0x3fc00000 0x0 0x400000>; + no-map; + }; + + dma_non_cached_low: non-cached-low-buffer { + compatible = "shared-dma-pool"; + size = <0x0 0x4000000>; + no-map; + linux,dma-default; + alloc-ranges = <0x0 0xc4000000 0x0 0x4000000>; + }; + + dma_non_cached_high: non-cached-high-buffer { + compatible = "shared-dma-pool"; + size = <0x0 0x10000000>; + no-map; + linux,dma-default; + alloc-ranges = <0x14 0x12000000 0x0 0x10000000>; + }; + }; + + imx219_vana: fixedregulator@0 { + compatible = "regulator-fixed"; + regulator-name = "imx219_vana"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + imx219_vdig: fixedregulator@1 { + compatible = "regulator-fixed"; + regulator-name = "imx219_vdig"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + imx219_vddl: fixedregulator@2 { + compatible = "regulator-fixed"; + regulator-name = "imx219_vddl"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + + imx219_clk: camera-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + +}; + +&gpio0 { + ngpios=<14>; + gpio-line-names = "", "", "", "", "", "", "", "", "", "", "", "", "SD_CARD_CS", "USER_BUTTON"; + status = "okay"; + + sd_card_cs { + gpio-hog; + gpios = <12 12>; + output_high; + line-name = "SD_CARD_CS"; + }; + + user_button { + gpio-hog; + gpios = <13 13>; + input; + line-name = "USER_BUTTON"; + }; +}; + +&gpio1 { + ngpios=<24>; + gpio-line-names = "", "", "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", "", "", + "ADC_IRQn", "", "", "USB_OCn"; + status = "okay"; + + adc_irqn { + gpio-hog; + gpios = <20 20>; + input; + line-name = "ADC_IRQn"; + }; + + user_button { + gpio-hog; + gpios = <23 23>; + input; + line-name = "USB_OCn"; + }; + +}; + +&gpio2 { + interrupts = <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>; + gpio-line-names = "P8_PIN3_USER_LED_0", "P8_PIN4_USER_LED_1", "P8_PIN5_USER_LED_2", + "P8_PIN6_USER_LED_3", "P8_PIN7_USER_LED_4", "P8_PIN8_USER_LED_5", + "P8_PIN9_USER_LED_6", "P8_PIN10_USER_LED_7", "P8_PIN11_USER_LED_8", + "P8_PIN12_USER_LED_9", "P8_PIN13_USER_LED_10", "P8_PIN14_USER_LED_11", + "P8_PIN15", "P8_PIN16", "P8_PIN17", "P8_PIN18", "P8_PIN19", + "P8_PIN20", "P8_PIN21", "P8_PIN22", "P8_PIN23", "P8_PIN24", + "P8_PIN25", "P8_PIN26", "P8_PIN27", "P8_PIN28", "P8_PIN29", + "P8_PIN30", + "M2_W_DISABLE1", "M2_W_DISABLE2", + "VIO_ENABLE", "SD_DET"; + status = "okay"; + + vio_enable { + gpio-hog; + gpios = <30 30>; + output_high; + line-name = "VIO_ENABLE"; + }; + + sd_det { + gpio-hog; + gpios = <31 31>; + input; + line-name = "SD_DET"; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + eeprom: eeprom@50 { + compatible = "at,24c32"; + reg = <0x50>; + }; + + imx219: sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + clocks = <&imx219_clk>; + VANA-supply = <&imx219_vana>; /* 2.8v */ + VDIG-supply = <&imx219_vdig>; /* 1.8v */ + VDDL-supply = <&imx219_vddl>; /* 1.2v */ + + port { + imx219_0: endpoint { +// remote-endpoint = <&csi1_ep>; + data-lanes = <1 2>; + clock-noncontinuous; + link-frequencies = /bits/ 64 <456000000>; + }; + }; + }; +}; + +&mac0 { + phy-mode = "sgmii"; + phy-handle = <&phy0>; + status = "okay"; + + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&mac1 { + phy-mode = "sgmii"; + phy-handle = <&phy1>; + status = "okay"; + + phy1: ethernet-phy@0 { + reg = <0>; + }; +}; + +&mbox { + status = "okay"; +}; + +//&mmc { +// status = "okay"; +// bus-width = <8>; +// disable-wp; +// cap-mmc-highspeed; +// mmc-ddr-1_8v; +// mmc-hs200-1_8v; +//}; + +&mmc { + //dma-noncoherent; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + status = "okay"; +}; + + +&mmuart0 { + status = "okay"; +}; + +&mmuart1 { + status = "okay"; +}; + +//&mmuart2 { +// status = "okay"; +//}; + +//&mmuart3 //{ +// statu//s = "okay"; +//};// +// +//&mmuart4 { +// status = "okay"; +//}; + +//&pcie { +// status = "okay"; +//}; + +&qspi { + status = "okay"; + cs-gpios = <&gpio1 17 GPIO_ACTIVE_LOW>, <&gpio0 12 GPIO_ACTIVE_LOW>; + num-cs = <2>; + + + mcp3464: mcp3464@0 { + compatible = "microchip,mcp3464r"; + reg = <0>; /* CE0 */ + spi-cpol; + spi-cpha; + spi-max-frequency = <15000000>; + status = "okay"; + microchip,hw-device-address = <1>; + }; + + mmc-slot@1 { + compatible = "mmc-spi-slot"; + reg = <1>; + gpios = <&gpio2 31 1>; + voltage-ranges = <3300 3300>; + spi-max-frequency = <15000000>; + disable-wp; + }; +}; + +&refclk { + clock-frequency = <125000000>; +}; + +&refclk_ccc { + clock-frequency = <50000000>; +}; + +&rtc { + status = "okay"; +}; + +&spi0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + +&syscontroller { + status = "okay"; +}; + +&usb { + dma-noncoherent; + status = "okay"; + dr_mode = "otg"; +};