diff --git a/.gitignore b/.gitignore
index b49a76d..ea14a5a 100644
--- a/.gitignore
+++ b/.gitignore
@@ -6,3 +6,4 @@ deploy/u-boot.bin
 mirror/
 riscv-toolchain/
 hart-software-services/
+u-boot/
diff --git a/01_git_sync.sh b/01_git_sync.sh
index 526b7ec..6e49ae9 100755
--- a/01_git_sync.sh
+++ b/01_git_sync.sh
@@ -3,19 +3,32 @@
 HSS_BRANCH="v2023.02"
 HSS_REPO="https://github.com/polarfire-soc/hart-software-services.git"
 
+#UBOOT_BRANCH="mpfs-uboot-2022.01"
+UBOOT_BRANCH="linux4microchip+fpga-2023.02"
+UBOOT_REPO="https://github.com/polarfire-soc/u-boot.git"
+
 GIT_DEPTH="20"
 
-if [ ! -f ./mirror/x86_64-gcc-13.2.0-nolibc-riscv64-linux.tar.xz ] ; then
-	###FIXME, move to public when released...
-	echo "wget -c --directory-prefix=./mirror/ https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-riscv64-linux.tar.xz"
-	wget -c --directory-prefix=./mirror/ https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-riscv64-linux.tar.xz
+if [ ! -f ./mirror/x86_64-gcc-11.4.0-nolibc-riscv64-linux.tar.xz ] ; then
+	echo "wget -c --directory-prefix=./mirror/ https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/11.4.0/x86_64-gcc-11.4.0-nolibc-riscv64-linux.tar.xz"
+	wget -c --directory-prefix=./mirror/ https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/11.4.0/x86_64-gcc-11.4.0-nolibc-riscv64-linux.tar.xz
 fi
 
-if [ ! -f ./riscv-toolchain/bin/riscv64-linux-gcc-13.2.0 ] ; then
-	echo "tar xf ./mirror/x86_64-gcc-13.2.0-nolibc-riscv64-linux.tar.xz --strip-components=2 -C ./riscv-toolchain/"
-	tar xf ./mirror/x86_64-gcc-13.2.0-nolibc-riscv64-linux.tar.xz --strip-components=2 -C ./riscv-toolchain/
+if [ ! -f ./riscv-toolchain/bin/riscv64-linux-gcc-11.4.0 ] ; then
+	echo "tar xf ./mirror/x86_64-gcc-11.4.0-nolibc-riscv64-linux.tar.xz --strip-components=2 -C ./riscv-toolchain/"
+	tar xf ./mirror/x86_64-gcc-11.4.0-nolibc-riscv64-linux.tar.xz --strip-components=2 -C ./riscv-toolchain/
 fi
 
+#if [ ! -f ./mirror/x86_64-gcc-13.2.0-nolibc-riscv64-linux.tar.xz ] ; then
+#	echo "wget -c --directory-prefix=./mirror/ https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-riscv64-linux.tar.xz"
+#	wget -c --directory-prefix=./mirror/ https://mirrors.edge.kernel.org/pub/tools/crosstool/files/bin/x86_64/13.2.0/x86_64-gcc-13.2.0-nolibc-riscv64-linux.tar.xz
+#fi
+
+#if [ ! -f ./riscv-toolchain/bin/riscv64-linux-gcc-13.2.0 ] ; then
+#	echo "tar xf ./mirror/x86_64-gcc-13.2.0-nolibc-riscv64-linux.tar.xz --strip-components=2 -C ./riscv-toolchain/"
+#	tar xf ./mirror/x86_64-gcc-13.2.0-nolibc-riscv64-linux.tar.xz --strip-components=2 -C ./riscv-toolchain/
+#fi
+
 if [ -d ./hart-software-services/ ] ; then
 	rm -rf ./hart-software-services/ || true
 fi
@@ -23,8 +36,14 @@ fi
 echo "git clone -b ${HSS_BRANCH} ${HSS_REPO} ./hart-software-services/ --depth=${GIT_DEPTH}"
 git clone -b ${HSS_BRANCH} ${HSS_REPO} ./hart-software-services/ --depth=${GIT_DEPTH}
 
-exit 2
+if [ -d ./u-boot ] ; then
+	rm -rf ./u-boot || true
+fi
 
+echo "git clone -b ${UBOOT_BRANCH} ${UBOOT_REPO} ./u-boot/ --depth=${GIT_DEPTH}"
+git clone -b ${UBOOT_BRANCH} ${UBOOT_REPO} ./u-boot/ --depth=${GIT_DEPTH}
+
+exit 2
 
 if [ -d ./opensbi ] ; then
 	rm -rf ./opensbi || true
@@ -33,18 +52,6 @@ fi
 echo "git clone -b ${OPENSBI_BRANCH} https://github.com/riscv-software-src/opensbi.git ./opensbi/ --depth=${GIT_DEPTH}"
 git clone -b ${OPENSBI_BRANCH} https://github.com/riscv-software-src/opensbi.git ./opensbi/ --depth=${GIT_DEPTH}
 
-if [ -d ./u-boot ] ; then
-	rm -rf ./u-boot || true
-fi
-
-if [ -f ./.gitlab-runner ] ; then
-	echo "git clone --reference-if-able /mnt/yocto-cache/git/beaglev-ahead-u-boot/ -b ${UBOOT_BRANCH} https://github.com/beagleboard/beaglev-ahead-u-boot.git ./u-boot/ --depth=1"
-	git clone --reference-if-able /mnt/yocto-cache/git/beaglev-ahead-u-boot/ -b ${UBOOT_BRANCH} https://github.com/beagleboard/beaglev-ahead-u-boot.git ./u-boot/ --depth=1
-else
-	echo "git clone -b ${UBOOT_BRANCH} https://github.com/beagleboard/beaglev-ahead-u-boot.git ./u-boot/ --depth=${GIT_DEPTH}"
-	git clone -b ${UBOOT_BRANCH} https://github.com/beagleboard/beaglev-ahead-u-boot.git ./u-boot/ --depth=${GIT_DEPTH}
-fi
-
 if [ -d ./BeagleBoard-DeviceTrees ] ; then
 	rm -rf ./BeagleBoard-DeviceTrees || true
 fi
diff --git a/build_u-boot.sh b/build_u-boot.sh
new file mode 100755
index 0000000..44ee5ce
--- /dev/null
+++ b/build_u-boot.sh
@@ -0,0 +1,32 @@
+#!/bin/bash
+
+CORES=$(getconf _NPROCESSORS_ONLN)
+wdir=`pwd`
+CC=${CC:-"${wdir}/riscv-toolchain/bin/riscv64-linux-"}
+
+make -C u-boot ARCH=riscv CROSS_COMPILE=${CC} distclean
+
+cd ./u-boot/
+#patch -p1 < ../patches/u-boot/0001-Use-MMUART0-for-stdout.patch
+#exit 2
+cp -v ../patches/u-boot/microchip-mpfs-icicle-kit.dts arch/riscv/dts/
+cp -v ../patches/u-boot/uboot_smode_defconfig .config
+cd ../
+
+#make -C u-boot ARCH=riscv CROSS_COMPILE=${CC} microchip_mpfs_icicle
+#make -C u-boot ARCH=riscv CROSS_COMPILE=${CC} olddefconfig
+#make -C u-boot ARCH=riscv CROSS_COMPILE=${CC} menuconfig
+#make -C u-boot ARCH=riscv CROSS_COMPILE=${CC} savedefconfig
+#cp -v ./u-boot/defconfig ./u-boot/configs/microchip_mpfs_icicle_defconfig
+#make -C u-boot ARCH=riscv CROSS_COMPILE=${CC} distclean
+
+make -C u-boot -j${CORES} ARCH=riscv CROSS_COMPILE=${CC} olddefconfig
+make -C u-boot ARCH=riscv CROSS_COMPILE=${CC} savedefconfig
+cp -v ./u-boot/defconfig ./u-boot/configs/microchip_mpfs_icicle_defconfig
+
+echo "make -C u-boot -j${CORES} ARCH=riscv CROSS_COMPILE=${CC} all"
+make -C u-boot -j${CORES} ARCH=riscv CROSS_COMPILE=${CC} all
+
+cp -v ./u-boot/u-boot.bin ./deploy/
+cp -v ./u-boot/u-boot.bin ./deploy/src.bin
+
diff --git a/generate_payload.bin.sh b/generate_payload.bin.sh
index 1dcbbe9..7067b42 100755
--- a/generate_payload.bin.sh
+++ b/generate_payload.bin.sh
@@ -1,7 +1,6 @@
 #!/bin/bash
 
 cd ./deploy/
-cp -v ./u-boot.bin ./src.bin
 ./hss-payload-generator -c config.yaml -v ./input/payload.bin
 sha256sum ./input/payload.bin
 
diff --git a/patches/u-boot/0001-Use-MMUART0-for-stdout.patch b/patches/u-boot/0001-Use-MMUART0-for-stdout.patch
new file mode 100644
index 0000000..dd0824c
--- /dev/null
+++ b/patches/u-boot/0001-Use-MMUART0-for-stdout.patch
@@ -0,0 +1,32 @@
+From 01d9d0ce7fc7f4c7adc8ec878d0be69ab23bcf9e Mon Sep 17 00:00:00 2001
+From: vauban353 <vauban353@gmail.com>
+Date: Sun, 16 Apr 2023 11:19:34 +0100
+Subject: [PATCH] Use MMUART0 for stdout.
+
+---
+ arch/riscv/dts/microchip-mpfs-icicle-kit.dts | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
+index 09722a02a4..d6535df577 100644
+--- a/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
++++ b/arch/riscv/dts/microchip-mpfs-icicle-kit.dts
+@@ -17,13 +17,13 @@
+ 		     "microchip,mpfs";
+ 
+ 	aliases {
+-		serial1 = &uart1;
++		serial0 = &uart0;
+ 		ethernet0 = &mac1;
+ 		spi0 = &qspi;
+ 	};
+ 
+ 	chosen {
+-		stdout-path = "serial1";
++		stdout-path = "serial0";
+ 	};
+ 
+ 	cpus {
+-- 
+2.25.1
+
diff --git a/patches/u-boot/microchip-mpfs-icicle-kit.dts b/patches/u-boot/microchip-mpfs-icicle-kit.dts
new file mode 100644
index 0000000..d6535df
--- /dev/null
+++ b/patches/u-boot/microchip-mpfs-icicle-kit.dts
@@ -0,0 +1,215 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) 2021 Microchip Technology Inc.
+ * Padmarao Begari <padmarao.begari@microchip.com>
+ */
+
+/dts-v1/;
+
+#include "microchip-mpfs.dtsi"
+
+/* Clock frequency (in Hz) of the rtcclk */
+#define RTCCLK_FREQ		1000000
+
+/ {
+	model = "Microchip PolarFire-SoC Icicle Kit";
+	compatible = "microchip,mpfs-icicle-reference-rtlv2210", "microchip,mpfs-icicle-kit",
+		     "microchip,mpfs";
+
+	aliases {
+		serial0 = &uart0;
+		ethernet0 = &mac1;
+		spi0 = &qspi;
+	};
+
+	chosen {
+		stdout-path = "serial0";
+	};
+
+	cpus {
+		timebase-frequency = <RTCCLK_FREQ>;
+	};
+
+	kernel: memory@80000000 {
+		device_type = "memory";
+		reg = <0x0 0x80000000 0x0 0x4000000>;
+		label = "kernel";
+	};
+
+	ddr_cached_low: memory@8a000000 {
+		device_type = "memory";
+		reg = <0x0 0x8a000000 0x0 0x8000000>;
+		label = "cached-low";
+	};
+
+	ddr_non_cached_low: memory@c4000000 {
+		device_type = "memory";
+		reg = <0x0 0xc4000000 0x0 0x6000000>;
+		label = "non-cached-low";
+	};
+
+	ddr_cached_high: memory@1022000000 {
+		device_type = "memory";
+		reg = <0x10 0x22000000 0x0 0x5e000000>;
+		label = "cached-high";
+	};
+
+	ddr_non_cached_high: memory@1412000000 {
+		device_type = "memory";
+		reg = <0x14 0x12000000 0x0 0x10000000>;
+		label = "non-cached-high";
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		hss: hss-buffer {
+			compatible = "shared-dma-pool";
+			reg = <0x10 0x3fc00000 0x0 0x400000>;
+			no-map;
+		};
+
+		dma_non_cached_low: non-cached-low-buffer {
+			compatible = "shared-dma-pool";
+			size = <0x0 0x4000000>;
+			no-map;
+			linux,dma-default;
+			alloc-ranges = <0x0 0xc4000000 0x0 0x4000000>;
+			dma-ranges = <0x0 0xc4000000 0x0 0xc4000000 0x0 0x4000000>;
+		};
+
+		dma_non_cached_high: non-cached-high-buffer {
+			compatible = "shared-dma-pool";
+			size = <0x0 0x10000000>;
+			no-map;
+			linux,dma-default;
+			alloc-ranges = <0x14 0x12000000 0x0 0x10000000>;
+			dma-ranges = <0x14 0x12000000 0x14 0x12000000 0x0 0x10000000>;
+		};
+
+		fabricbuf0ddrc: buffer@88000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x0 0x88000000 0x0 0x2000000>;
+			no-map;
+		};
+
+		fabricbuf1ddrnc: buffer@c8000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x0 0xc8000000 0x0 0x2000000>;
+			no-map;
+		};
+
+		fabricbuf2ddrncwcb: buffer@d8000000 {
+			compatible = "shared-dma-pool";
+			reg = <0x0 0xd8000000 0x0 0x2000000>;
+			no-map;
+		};
+	};
+
+	udmabuf0 {
+		compatible = "ikwzm,u-dma-buf";
+		device-name = "udmabuf-ddr-c0";
+		minor-number = <0>;
+		size = <0x0 0x2000000>;
+		memory-region = <&fabricbuf0ddrc>;
+		sync-mode = <3>;
+	};
+
+	udmabuf1 {
+		compatible = "ikwzm,u-dma-buf";
+		device-name = "udmabuf-ddr-nc0";
+		minor-number = <1>;
+		size = <0x0 0x2000000>;
+		memory-region = <&fabricbuf1ddrnc>;
+		sync-mode = <3>;
+	};
+
+	udmabuf2 {
+		compatible = "ikwzm,u-dma-buf";
+		device-name = "udmabuf-ddr-nc-wcb0";
+		minor-number = <2>;
+		size = <0x0 0x2000000>;
+		memory-region = <&fabricbuf2ddrncwcb>;
+		sync-mode = <3>;
+	};
+};
+
+&refclk {
+	clock-frequency = <125000000>;
+};
+
+&uart1 {
+	status = "okay";
+};
+
+&mmc {
+	status = "okay";
+	bus-width = <4>;
+	disable-wp;
+	cap-mmc-highspeed;
+	cap-sd-highspeed;
+	card-detect-delay = <200>;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+};
+
+&i2c1 {
+	status = "okay";
+	clock-frequency = <100000>;
+
+	pac193x: pac193x@10 {
+		compatible = "microchip,pac1934";
+		reg = <0x10>;
+		samp-rate = <64>;
+		status = "okay";
+		ch1: channel0 {
+			uohms-shunt-res = <10000>;
+			rail-name = "VDDREG";
+			channel_enabled;
+		};
+		ch2: channel1 {
+			uohms-shunt-res = <10000>;
+			rail-name = "VDDA25";
+			channel_enabled;
+		};
+		ch3: channel2 {
+			uohms-shunt-res = <10000>;
+			rail-name = "VDD25";
+			channel_enabled;
+		};
+		ch4: channel3 {
+			uohms-shunt-res = <10000>;
+			rail-name = "VDDA_REG";
+			channel_enabled;
+		};
+	};
+};
+
+&mac1 {
+	status = "okay";
+	phy-mode = "sgmii";
+	phy-handle = <&phy1>;
+	phy1: ethernet-phy@9 {
+		reg = <9>;
+	};
+};
+
+&qspi {
+	status = "okay";
+	num-cs = <1>;
+	flash0: spi-nand@0 {
+		compatible = "spi-nand";
+		reg = <0x0>;
+		spi-tx-bus-width = <4>;
+		spi-rx-bus-width = <4>;
+		spi-max-frequency = <20000000>;
+		spi-cpol;
+		spi-cpha;
+	};
+};
diff --git a/patches/u-boot/uboot_smode_defconfig b/patches/u-boot/uboot_smode_defconfig
new file mode 100644
index 0000000..c14624b
--- /dev/null
+++ b/patches/u-boot/uboot_smode_defconfig
@@ -0,0 +1,23 @@
+CONFIG_RISCV=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_ENV_SIZE=0x2000
+CONFIG_DEFAULT_DEVICE_TREE="microchip-mpfs-icicle-kit"
+CONFIG_TARGET_MICROCHIP_ICICLE=y
+CONFIG_ARCH_RV64I=y
+CONFIG_RISCV_SMODE=y
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_FIT=y
+CONFIG_DISPLAY_CPUINFO=y
+CONFIG_DISPLAY_BOARDINFO=y
+CONFIG_SYS_PROMPT="RISC-V # "
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_BOOTP_SEND_HOSTNAME=y
+CONFIG_DM_MTD=y
+CONFIG_BOOTCOMMAND="setenv fileaddr 0x1030000000; setenv mmcbootpart 2; setenv scriptname boot.scr; run mmcbootenv;"
+CONFIG_SYS_BOOT_RAMDISK_HIGH=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MICROCHIP=y
+CONFIG_CMD_I2C=y
+CONFIG_SYS_I2C_SPEED=100000
+CONFIG_SYS_LOAD_ADDR=0x100200000
+CONFIG_MTDPARTS_DEFAULT="mtdparts=spi-nand0:8m(payload),128k(env),48m(fitimage)"