doc/html/tcc3_8h_source.html

#ifndef _SAME54_TCC3_INSTANCE_

#define _SAME54_TCC3_INSTANCE_


/* ========== Register definition for TCC3 peripheral ========== */

#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

#define REG_TCC3_CTRLA             (0x42001000)

#define REG_TCC3_CTRLBCLR          (0x42001004)

#define REG_TCC3_CTRLBSET          (0x42001005)

#define REG_TCC3_SYNCBUSY          (0x42001008)

#define REG_TCC3_FCTRLA            (0x4200100C)

#define REG_TCC3_FCTRLB            (0x42001010)

#define REG_TCC3_DRVCTRL           (0x42001018)

#define REG_TCC3_DBGCTRL           (0x4200101E)

#define REG_TCC3_EVCTRL            (0x42001020)

#define REG_TCC3_INTENCLR          (0x42001024)

#define REG_TCC3_INTENSET          (0x42001028)

#define REG_TCC3_INTFLAG           (0x4200102C)

#define REG_TCC3_STATUS            (0x42001030)

#define REG_TCC3_COUNT             (0x42001034)

#define REG_TCC3_WAVE              (0x4200103C)

#define REG_TCC3_PER               (0x42001040)

#define REG_TCC3_CC0               (0x42001044)

#define REG_TCC3_CC1               (0x42001048)

#define REG_TCC3_PERBUF            (0x4200106C)

#define REG_TCC3_CCBUF0            (0x42001070)

#define REG_TCC3_CCBUF1            (0x42001074)

#else

#define REG_TCC3_CTRLA             (*(RwReg  *)0x42001000UL)

#define REG_TCC3_CTRLBCLR          (*(RwReg8 *)0x42001004UL)

#define REG_TCC3_CTRLBSET          (*(RwReg8 *)0x42001005UL)

#define REG_TCC3_SYNCBUSY          (*(RoReg  *)0x42001008UL)

#define REG_TCC3_FCTRLA            (*(RwReg  *)0x4200100CUL)

#define REG_TCC3_FCTRLB            (*(RwReg  *)0x42001010UL)

#define REG_TCC3_DRVCTRL           (*(RwReg  *)0x42001018UL)

#define REG_TCC3_DBGCTRL           (*(RwReg8 *)0x4200101EUL)

#define REG_TCC3_EVCTRL            (*(RwReg  *)0x42001020UL)

#define REG_TCC3_INTENCLR          (*(RwReg  *)0x42001024UL)

#define REG_TCC3_INTENSET          (*(RwReg  *)0x42001028UL)

#define REG_TCC3_INTFLAG           (*(RwReg  *)0x4200102CUL)

#define REG_TCC3_STATUS            (*(RwReg  *)0x42001030UL)

#define REG_TCC3_COUNT             (*(RwReg  *)0x42001034UL)

#define REG_TCC3_WAVE              (*(RwReg  *)0x4200103CUL)

#define REG_TCC3_PER               (*(RwReg  *)0x42001040UL)

#define REG_TCC3_CC0               (*(RwReg  *)0x42001044UL)

#define REG_TCC3_CC1               (*(RwReg  *)0x42001048UL)

#define REG_TCC3_PERBUF            (*(RwReg  *)0x4200106CUL)

#define REG_TCC3_CCBUF0            (*(RwReg  *)0x42001070UL)

#define REG_TCC3_CCBUF1            (*(RwReg  *)0x42001074UL)

#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


/* ========== Instance parameters for TCC3 peripheral ========== */

#define TCC3_CC_NUM                 2        // Number of Compare/Capture units

#define TCC3_DITHERING              0        // Dithering feature implemented

#define TCC3_DMAC_ID_MC_0           39

#define TCC3_DMAC_ID_MC_1           40

#define TCC3_DMAC_ID_MC_LSB         39

#define TCC3_DMAC_ID_MC_MSB         40

#define TCC3_DMAC_ID_MC_SIZE        2

#define TCC3_DMAC_ID_OVF            38       // DMA overflow/underflow/retrigger trigger

#define TCC3_DTI                    0        // Dead-Time-Insertion feature implemented

#define TCC3_EXT                    0        // Coding of implemented extended features

#define TCC3_GCLK_ID                29       // Index of Generic Clock

#define TCC3_MASTER_SLAVE_MODE      0        // TCC type 0 : NA, 1 : Master, 2 : Slave

#define TCC3_OTMX                   0        // Output Matrix feature implemented

#define TCC3_OW_NUM                 2        // Number of Output Waveforms

#define TCC3_PG                     0        // Pattern Generation feature implemented

#define TCC3_SIZE                   16

#define TCC3_SWAP                   0        // DTI outputs swap feature implemented


#endif /* _SAME54_TCC3_INSTANCE_ */