SAME54P20A Test Project
tc6.h
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1 
30 #ifndef _SAME54_TC6_INSTANCE_
31 #define _SAME54_TC6_INSTANCE_
32 
33 /* ========== Register definition for TC6 peripheral ========== */
34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
35 #define REG_TC6_CTRLA (0x43001400)
36 #define REG_TC6_CTRLBCLR (0x43001404)
37 #define REG_TC6_CTRLBSET (0x43001405)
38 #define REG_TC6_EVCTRL (0x43001406)
39 #define REG_TC6_INTENCLR (0x43001408)
40 #define REG_TC6_INTENSET (0x43001409)
41 #define REG_TC6_INTFLAG (0x4300140A)
42 #define REG_TC6_STATUS (0x4300140B)
43 #define REG_TC6_WAVE (0x4300140C)
44 #define REG_TC6_DRVCTRL (0x4300140D)
45 #define REG_TC6_DBGCTRL (0x4300140F)
46 #define REG_TC6_SYNCBUSY (0x43001410)
47 #define REG_TC6_COUNT16_COUNT (0x43001414)
48 #define REG_TC6_COUNT16_CC0 (0x4300141C)
49 #define REG_TC6_COUNT16_CC1 (0x4300141E)
50 #define REG_TC6_COUNT16_CCBUF0 (0x43001430)
51 #define REG_TC6_COUNT16_CCBUF1 (0x43001432)
52 #define REG_TC6_COUNT32_COUNT (0x43001414)
53 #define REG_TC6_COUNT32_CC0 (0x4300141C)
54 #define REG_TC6_COUNT32_CC1 (0x43001420)
55 #define REG_TC6_COUNT32_CCBUF0 (0x43001430)
56 #define REG_TC6_COUNT32_CCBUF1 (0x43001434)
57 #define REG_TC6_COUNT8_COUNT (0x43001414)
58 #define REG_TC6_COUNT8_PER (0x4300141B)
59 #define REG_TC6_COUNT8_CC0 (0x4300141C)
60 #define REG_TC6_COUNT8_CC1 (0x4300141D)
61 #define REG_TC6_COUNT8_PERBUF (0x4300142F)
62 #define REG_TC6_COUNT8_CCBUF0 (0x43001430)
63 #define REG_TC6_COUNT8_CCBUF1 (0x43001431)
64 #else
65 #define REG_TC6_CTRLA (*(RwReg *)0x43001400UL)
66 #define REG_TC6_CTRLBCLR (*(RwReg8 *)0x43001404UL)
67 #define REG_TC6_CTRLBSET (*(RwReg8 *)0x43001405UL)
68 #define REG_TC6_EVCTRL (*(RwReg16*)0x43001406UL)
69 #define REG_TC6_INTENCLR (*(RwReg8 *)0x43001408UL)
70 #define REG_TC6_INTENSET (*(RwReg8 *)0x43001409UL)
71 #define REG_TC6_INTFLAG (*(RwReg8 *)0x4300140AUL)
72 #define REG_TC6_STATUS (*(RwReg8 *)0x4300140BUL)
73 #define REG_TC6_WAVE (*(RwReg8 *)0x4300140CUL)
74 #define REG_TC6_DRVCTRL (*(RwReg8 *)0x4300140DUL)
75 #define REG_TC6_DBGCTRL (*(RwReg8 *)0x4300140FUL)
76 #define REG_TC6_SYNCBUSY (*(RoReg *)0x43001410UL)
77 #define REG_TC6_COUNT16_COUNT (*(RwReg16*)0x43001414UL)
78 #define REG_TC6_COUNT16_CC0 (*(RwReg16*)0x4300141CUL)
79 #define REG_TC6_COUNT16_CC1 (*(RwReg16*)0x4300141EUL)
80 #define REG_TC6_COUNT16_CCBUF0 (*(RwReg16*)0x43001430UL)
81 #define REG_TC6_COUNT16_CCBUF1 (*(RwReg16*)0x43001432UL)
82 #define REG_TC6_COUNT32_COUNT (*(RwReg *)0x43001414UL)
83 #define REG_TC6_COUNT32_CC0 (*(RwReg *)0x4300141CUL)
84 #define REG_TC6_COUNT32_CC1 (*(RwReg *)0x43001420UL)
85 #define REG_TC6_COUNT32_CCBUF0 (*(RwReg *)0x43001430UL)
86 #define REG_TC6_COUNT32_CCBUF1 (*(RwReg *)0x43001434UL)
87 #define REG_TC6_COUNT8_COUNT (*(RwReg8 *)0x43001414UL)
88 #define REG_TC6_COUNT8_PER (*(RwReg8 *)0x4300141BUL)
89 #define REG_TC6_COUNT8_CC0 (*(RwReg8 *)0x4300141CUL)
90 #define REG_TC6_COUNT8_CC1 (*(RwReg8 *)0x4300141DUL)
91 #define REG_TC6_COUNT8_PERBUF (*(RwReg8 *)0x4300142FUL)
92 #define REG_TC6_COUNT8_CCBUF0 (*(RwReg8 *)0x43001430UL)
93 #define REG_TC6_COUNT8_CCBUF1 (*(RwReg8 *)0x43001431UL)
94 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
95 
96 /* ========== Instance parameters for TC6 peripheral ========== */
97 #define TC6_CC_NUM 2
98 #define TC6_DMAC_ID_MC_0 63
99 #define TC6_DMAC_ID_MC_1 64
100 #define TC6_DMAC_ID_MC_LSB 63
101 #define TC6_DMAC_ID_MC_MSB 64
102 #define TC6_DMAC_ID_MC_SIZE 2
103 #define TC6_DMAC_ID_OVF 62 // Indexes of DMA Overflow trigger
104 #define TC6_EXT 0 // Coding of implemented extended features (keep 0 value)
105 #define TC6_GCLK_ID 39 // Index of Generic Clock
106 #define TC6_MASTER_SLAVE_MODE 1 // TC type 0 : NA, 1 : Master, 2 : Slave
107 #define TC6_OW_NUM 2 // Number of Output Waveforms
108 
109 #endif /* _SAME54_TC6_INSTANCE_ */