doc/html/tcc4_8h_source.html

#ifndef _SAME54_TCC4_INSTANCE_

#define _SAME54_TCC4_INSTANCE_


/* ========== Register definition for TCC4 peripheral ========== */

#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

#define REG_TCC4_CTRLA             (0x43001000)

#define REG_TCC4_CTRLBCLR          (0x43001004)

#define REG_TCC4_CTRLBSET          (0x43001005)

#define REG_TCC4_SYNCBUSY          (0x43001008)

#define REG_TCC4_FCTRLA            (0x4300100C)

#define REG_TCC4_FCTRLB            (0x43001010)

#define REG_TCC4_DRVCTRL           (0x43001018)

#define REG_TCC4_DBGCTRL           (0x4300101E)

#define REG_TCC4_EVCTRL            (0x43001020)

#define REG_TCC4_INTENCLR          (0x43001024)

#define REG_TCC4_INTENSET          (0x43001028)

#define REG_TCC4_INTFLAG           (0x4300102C)

#define REG_TCC4_STATUS            (0x43001030)

#define REG_TCC4_COUNT             (0x43001034)

#define REG_TCC4_WAVE              (0x4300103C)

#define REG_TCC4_PER               (0x43001040)

#define REG_TCC4_CC0               (0x43001044)

#define REG_TCC4_CC1               (0x43001048)

#define REG_TCC4_PERBUF            (0x4300106C)

#define REG_TCC4_CCBUF0            (0x43001070)

#define REG_TCC4_CCBUF1            (0x43001074)

#else

#define REG_TCC4_CTRLA             (*(RwReg  *)0x43001000UL)

#define REG_TCC4_CTRLBCLR          (*(RwReg8 *)0x43001004UL)

#define REG_TCC4_CTRLBSET          (*(RwReg8 *)0x43001005UL)

#define REG_TCC4_SYNCBUSY          (*(RoReg  *)0x43001008UL)

#define REG_TCC4_FCTRLA            (*(RwReg  *)0x4300100CUL)

#define REG_TCC4_FCTRLB            (*(RwReg  *)0x43001010UL)

#define REG_TCC4_DRVCTRL           (*(RwReg  *)0x43001018UL)

#define REG_TCC4_DBGCTRL           (*(RwReg8 *)0x4300101EUL)

#define REG_TCC4_EVCTRL            (*(RwReg  *)0x43001020UL)

#define REG_TCC4_INTENCLR          (*(RwReg  *)0x43001024UL)

#define REG_TCC4_INTENSET          (*(RwReg  *)0x43001028UL)

#define REG_TCC4_INTFLAG           (*(RwReg  *)0x4300102CUL)

#define REG_TCC4_STATUS            (*(RwReg  *)0x43001030UL)

#define REG_TCC4_COUNT             (*(RwReg  *)0x43001034UL)

#define REG_TCC4_WAVE              (*(RwReg  *)0x4300103CUL)

#define REG_TCC4_PER               (*(RwReg  *)0x43001040UL)

#define REG_TCC4_CC0               (*(RwReg  *)0x43001044UL)

#define REG_TCC4_CC1               (*(RwReg  *)0x43001048UL)

#define REG_TCC4_PERBUF            (*(RwReg  *)0x4300106CUL)

#define REG_TCC4_CCBUF0            (*(RwReg  *)0x43001070UL)

#define REG_TCC4_CCBUF1            (*(RwReg  *)0x43001074UL)

#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


/* ========== Instance parameters for TCC4 peripheral ========== */

#define TCC4_CC_NUM                 2        // Number of Compare/Capture units

#define TCC4_DITHERING              0        // Dithering feature implemented

#define TCC4_DMAC_ID_MC_0           42

#define TCC4_DMAC_ID_MC_1           43

#define TCC4_DMAC_ID_MC_LSB         42

#define TCC4_DMAC_ID_MC_MSB         43

#define TCC4_DMAC_ID_MC_SIZE        2

#define TCC4_DMAC_ID_OVF            41       // DMA overflow/underflow/retrigger trigger

#define TCC4_DTI                    0        // Dead-Time-Insertion feature implemented

#define TCC4_EXT                    0        // Coding of implemented extended features

#define TCC4_GCLK_ID                38       // Index of Generic Clock

#define TCC4_MASTER_SLAVE_MODE      0        // TCC type 0 : NA, 1 : Master, 2 : Slave

#define TCC4_OTMX                   0        // Output Matrix feature implemented

#define TCC4_OW_NUM                 2        // Number of Output Waveforms

#define TCC4_PG                     0        // Pattern Generation feature implemented

#define TCC4_SIZE                   16

#define TCC4_SWAP                   0        // DTI outputs swap feature implemented


#endif /* _SAME54_TCC4_INSTANCE_ */