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30 #ifndef _SAME54_TCC1_INSTANCE_
31 #define _SAME54_TCC1_INSTANCE_
34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
35 #define REG_TCC1_CTRLA (0x41018000)
36 #define REG_TCC1_CTRLBCLR (0x41018004)
37 #define REG_TCC1_CTRLBSET (0x41018005)
38 #define REG_TCC1_SYNCBUSY (0x41018008)
39 #define REG_TCC1_FCTRLA (0x4101800C)
40 #define REG_TCC1_FCTRLB (0x41018010)
41 #define REG_TCC1_WEXCTRL (0x41018014)
42 #define REG_TCC1_DRVCTRL (0x41018018)
43 #define REG_TCC1_DBGCTRL (0x4101801E)
44 #define REG_TCC1_EVCTRL (0x41018020)
45 #define REG_TCC1_INTENCLR (0x41018024)
46 #define REG_TCC1_INTENSET (0x41018028)
47 #define REG_TCC1_INTFLAG (0x4101802C)
48 #define REG_TCC1_STATUS (0x41018030)
49 #define REG_TCC1_COUNT (0x41018034)
50 #define REG_TCC1_PATT (0x41018038)
51 #define REG_TCC1_WAVE (0x4101803C)
52 #define REG_TCC1_PER (0x41018040)
53 #define REG_TCC1_CC0 (0x41018044)
54 #define REG_TCC1_CC1 (0x41018048)
55 #define REG_TCC1_CC2 (0x4101804C)
56 #define REG_TCC1_CC3 (0x41018050)
57 #define REG_TCC1_PATTBUF (0x41018064)
58 #define REG_TCC1_PERBUF (0x4101806C)
59 #define REG_TCC1_CCBUF0 (0x41018070)
60 #define REG_TCC1_CCBUF1 (0x41018074)
61 #define REG_TCC1_CCBUF2 (0x41018078)
62 #define REG_TCC1_CCBUF3 (0x4101807C)
64 #define REG_TCC1_CTRLA (*(RwReg *)0x41018000UL)
65 #define REG_TCC1_CTRLBCLR (*(RwReg8 *)0x41018004UL)
66 #define REG_TCC1_CTRLBSET (*(RwReg8 *)0x41018005UL)
67 #define REG_TCC1_SYNCBUSY (*(RoReg *)0x41018008UL)
68 #define REG_TCC1_FCTRLA (*(RwReg *)0x4101800CUL)
69 #define REG_TCC1_FCTRLB (*(RwReg *)0x41018010UL)
70 #define REG_TCC1_WEXCTRL (*(RwReg *)0x41018014UL)
71 #define REG_TCC1_DRVCTRL (*(RwReg *)0x41018018UL)
72 #define REG_TCC1_DBGCTRL (*(RwReg8 *)0x4101801EUL)
73 #define REG_TCC1_EVCTRL (*(RwReg *)0x41018020UL)
74 #define REG_TCC1_INTENCLR (*(RwReg *)0x41018024UL)
75 #define REG_TCC1_INTENSET (*(RwReg *)0x41018028UL)
76 #define REG_TCC1_INTFLAG (*(RwReg *)0x4101802CUL)
77 #define REG_TCC1_STATUS (*(RwReg *)0x41018030UL)
78 #define REG_TCC1_COUNT (*(RwReg *)0x41018034UL)
79 #define REG_TCC1_PATT (*(RwReg16*)0x41018038UL)
80 #define REG_TCC1_WAVE (*(RwReg *)0x4101803CUL)
81 #define REG_TCC1_PER (*(RwReg *)0x41018040UL)
82 #define REG_TCC1_CC0 (*(RwReg *)0x41018044UL)
83 #define REG_TCC1_CC1 (*(RwReg *)0x41018048UL)
84 #define REG_TCC1_CC2 (*(RwReg *)0x4101804CUL)
85 #define REG_TCC1_CC3 (*(RwReg *)0x41018050UL)
86 #define REG_TCC1_PATTBUF (*(RwReg16*)0x41018064UL)
87 #define REG_TCC1_PERBUF (*(RwReg *)0x4101806CUL)
88 #define REG_TCC1_CCBUF0 (*(RwReg *)0x41018070UL)
89 #define REG_TCC1_CCBUF1 (*(RwReg *)0x41018074UL)
90 #define REG_TCC1_CCBUF2 (*(RwReg *)0x41018078UL)
91 #define REG_TCC1_CCBUF3 (*(RwReg *)0x4101807CUL)
95 #define TCC1_CC_NUM 4 // Number of Compare/Capture units
96 #define TCC1_DITHERING 1 // Dithering feature implemented
97 #define TCC1_DMAC_ID_MC_0 30
98 #define TCC1_DMAC_ID_MC_1 31
99 #define TCC1_DMAC_ID_MC_2 32
100 #define TCC1_DMAC_ID_MC_3 33
101 #define TCC1_DMAC_ID_MC_LSB 30
102 #define TCC1_DMAC_ID_MC_MSB 33
103 #define TCC1_DMAC_ID_MC_SIZE 4
104 #define TCC1_DMAC_ID_OVF 29 // DMA overflow/underflow/retrigger trigger
105 #define TCC1_DTI 1 // Dead-Time-Insertion feature implemented
106 #define TCC1_EXT 31 // Coding of implemented extended features
107 #define TCC1_GCLK_ID 25 // Index of Generic Clock
108 #define TCC1_MASTER_SLAVE_MODE 2 // TCC type 0 : NA, 1 : Master, 2 : Slave
109 #define TCC1_OTMX 1 // Output Matrix feature implemented
110 #define TCC1_OW_NUM 8 // Number of Output Waveforms
111 #define TCC1_PG 1 // Pattern Generation feature implemented
113 #define TCC1_SWAP 1 // DTI outputs swap feature implemented
