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30 #ifndef _SAME54_SERCOM0_INSTANCE_
31 #define _SAME54_SERCOM0_INSTANCE_
34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
35 #define REG_SERCOM0_I2CM_CTRLA (0x40003000)
36 #define REG_SERCOM0_I2CM_CTRLB (0x40003004)
37 #define REG_SERCOM0_I2CM_CTRLC (0x40003008)
38 #define REG_SERCOM0_I2CM_BAUD (0x4000300C)
39 #define REG_SERCOM0_I2CM_INTENCLR (0x40003014)
40 #define REG_SERCOM0_I2CM_INTENSET (0x40003016)
41 #define REG_SERCOM0_I2CM_INTFLAG (0x40003018)
42 #define REG_SERCOM0_I2CM_STATUS (0x4000301A)
43 #define REG_SERCOM0_I2CM_SYNCBUSY (0x4000301C)
44 #define REG_SERCOM0_I2CM_ADDR (0x40003024)
45 #define REG_SERCOM0_I2CM_DATA (0x40003028)
46 #define REG_SERCOM0_I2CM_DBGCTRL (0x40003030)
47 #define REG_SERCOM0_I2CS_CTRLA (0x40003000)
48 #define REG_SERCOM0_I2CS_CTRLB (0x40003004)
49 #define REG_SERCOM0_I2CS_CTRLC (0x40003008)
50 #define REG_SERCOM0_I2CS_INTENCLR (0x40003014)
51 #define REG_SERCOM0_I2CS_INTENSET (0x40003016)
52 #define REG_SERCOM0_I2CS_INTFLAG (0x40003018)
53 #define REG_SERCOM0_I2CS_STATUS (0x4000301A)
54 #define REG_SERCOM0_I2CS_SYNCBUSY (0x4000301C)
55 #define REG_SERCOM0_I2CS_LENGTH (0x40003022)
56 #define REG_SERCOM0_I2CS_ADDR (0x40003024)
57 #define REG_SERCOM0_I2CS_DATA (0x40003028)
58 #define REG_SERCOM0_SPI_CTRLA (0x40003000)
59 #define REG_SERCOM0_SPI_CTRLB (0x40003004)
60 #define REG_SERCOM0_SPI_CTRLC (0x40003008)
61 #define REG_SERCOM0_SPI_BAUD (0x4000300C)
62 #define REG_SERCOM0_SPI_INTENCLR (0x40003014)
63 #define REG_SERCOM0_SPI_INTENSET (0x40003016)
64 #define REG_SERCOM0_SPI_INTFLAG (0x40003018)
65 #define REG_SERCOM0_SPI_STATUS (0x4000301A)
66 #define REG_SERCOM0_SPI_SYNCBUSY (0x4000301C)
67 #define REG_SERCOM0_SPI_LENGTH (0x40003022)
68 #define REG_SERCOM0_SPI_ADDR (0x40003024)
69 #define REG_SERCOM0_SPI_DATA (0x40003028)
70 #define REG_SERCOM0_SPI_DBGCTRL (0x40003030)
71 #define REG_SERCOM0_USART_CTRLA (0x40003000)
72 #define REG_SERCOM0_USART_CTRLB (0x40003004)
73 #define REG_SERCOM0_USART_CTRLC (0x40003008)
74 #define REG_SERCOM0_USART_BAUD (0x4000300C)
75 #define REG_SERCOM0_USART_RXPL (0x4000300E)
76 #define REG_SERCOM0_USART_INTENCLR (0x40003014)
77 #define REG_SERCOM0_USART_INTENSET (0x40003016)
78 #define REG_SERCOM0_USART_INTFLAG (0x40003018)
79 #define REG_SERCOM0_USART_STATUS (0x4000301A)
80 #define REG_SERCOM0_USART_SYNCBUSY (0x4000301C)
81 #define REG_SERCOM0_USART_RXERRCNT (0x40003020)
82 #define REG_SERCOM0_USART_LENGTH (0x40003022)
83 #define REG_SERCOM0_USART_DATA (0x40003028)
84 #define REG_SERCOM0_USART_DBGCTRL (0x40003030)
86 #define REG_SERCOM0_I2CM_CTRLA (*(RwReg *)0x40003000UL)
87 #define REG_SERCOM0_I2CM_CTRLB (*(RwReg *)0x40003004UL)
88 #define REG_SERCOM0_I2CM_CTRLC (*(RwReg *)0x40003008UL)
89 #define REG_SERCOM0_I2CM_BAUD (*(RwReg *)0x4000300CUL)
90 #define REG_SERCOM0_I2CM_INTENCLR (*(RwReg8 *)0x40003014UL)
91 #define REG_SERCOM0_I2CM_INTENSET (*(RwReg8 *)0x40003016UL)
92 #define REG_SERCOM0_I2CM_INTFLAG (*(RwReg8 *)0x40003018UL)
93 #define REG_SERCOM0_I2CM_STATUS (*(RwReg16*)0x4000301AUL)
94 #define REG_SERCOM0_I2CM_SYNCBUSY (*(RoReg *)0x4000301CUL)
95 #define REG_SERCOM0_I2CM_ADDR (*(RwReg *)0x40003024UL)
96 #define REG_SERCOM0_I2CM_DATA (*(RwReg *)0x40003028UL)
97 #define REG_SERCOM0_I2CM_DBGCTRL (*(RwReg8 *)0x40003030UL)
98 #define REG_SERCOM0_I2CS_CTRLA (*(RwReg *)0x40003000UL)
99 #define REG_SERCOM0_I2CS_CTRLB (*(RwReg *)0x40003004UL)
100 #define REG_SERCOM0_I2CS_CTRLC (*(RwReg *)0x40003008UL)
101 #define REG_SERCOM0_I2CS_INTENCLR (*(RwReg8 *)0x40003014UL)
102 #define REG_SERCOM0_I2CS_INTENSET (*(RwReg8 *)0x40003016UL)
103 #define REG_SERCOM0_I2CS_INTFLAG (*(RwReg8 *)0x40003018UL)
104 #define REG_SERCOM0_I2CS_STATUS (*(RwReg16*)0x4000301AUL)
105 #define REG_SERCOM0_I2CS_SYNCBUSY (*(RoReg *)0x4000301CUL)
106 #define REG_SERCOM0_I2CS_LENGTH (*(RwReg16*)0x40003022UL)
107 #define REG_SERCOM0_I2CS_ADDR (*(RwReg *)0x40003024UL)
108 #define REG_SERCOM0_I2CS_DATA (*(RwReg *)0x40003028UL)
109 #define REG_SERCOM0_SPI_CTRLA (*(RwReg *)0x40003000UL)
110 #define REG_SERCOM0_SPI_CTRLB (*(RwReg *)0x40003004UL)
111 #define REG_SERCOM0_SPI_CTRLC (*(RwReg *)0x40003008UL)
112 #define REG_SERCOM0_SPI_BAUD (*(RwReg8 *)0x4000300CUL)
113 #define REG_SERCOM0_SPI_INTENCLR (*(RwReg8 *)0x40003014UL)
114 #define REG_SERCOM0_SPI_INTENSET (*(RwReg8 *)0x40003016UL)
115 #define REG_SERCOM0_SPI_INTFLAG (*(RwReg8 *)0x40003018UL)
116 #define REG_SERCOM0_SPI_STATUS (*(RwReg16*)0x4000301AUL)
117 #define REG_SERCOM0_SPI_SYNCBUSY (*(RoReg *)0x4000301CUL)
118 #define REG_SERCOM0_SPI_LENGTH (*(RwReg16*)0x40003022UL)
119 #define REG_SERCOM0_SPI_ADDR (*(RwReg *)0x40003024UL)
120 #define REG_SERCOM0_SPI_DATA (*(RwReg *)0x40003028UL)
121 #define REG_SERCOM0_SPI_DBGCTRL (*(RwReg8 *)0x40003030UL)
122 #define REG_SERCOM0_USART_CTRLA (*(RwReg *)0x40003000UL)
123 #define REG_SERCOM0_USART_CTRLB (*(RwReg *)0x40003004UL)
124 #define REG_SERCOM0_USART_CTRLC (*(RwReg *)0x40003008UL)
125 #define REG_SERCOM0_USART_BAUD (*(RwReg16*)0x4000300CUL)
126 #define REG_SERCOM0_USART_RXPL (*(RwReg8 *)0x4000300EUL)
127 #define REG_SERCOM0_USART_INTENCLR (*(RwReg8 *)0x40003014UL)
128 #define REG_SERCOM0_USART_INTENSET (*(RwReg8 *)0x40003016UL)
129 #define REG_SERCOM0_USART_INTFLAG (*(RwReg8 *)0x40003018UL)
130 #define REG_SERCOM0_USART_STATUS (*(RwReg16*)0x4000301AUL)
131 #define REG_SERCOM0_USART_SYNCBUSY (*(RoReg *)0x4000301CUL)
132 #define REG_SERCOM0_USART_RXERRCNT (*(RoReg8 *)0x40003020UL)
133 #define REG_SERCOM0_USART_LENGTH (*(RwReg16*)0x40003022UL)
134 #define REG_SERCOM0_USART_DATA (*(RwReg *)0x40003028UL)
135 #define REG_SERCOM0_USART_DBGCTRL (*(RwReg8 *)0x40003030UL)
139 #define SERCOM0_CLK_REDUCTION 1 // Reduce clock options to pin 1 for SPI and USART
140 #define SERCOM0_DLY_COMPENSATION 1 // Compensates for a fast DLY50 element. Assuming 20ns
141 #define SERCOM0_DMA 1 // DMA support implemented?
142 #define SERCOM0_DMAC_ID_RX 4 // Index of DMA RX trigger
143 #define SERCOM0_DMAC_ID_TX 5 // Index of DMA TX trigger
144 #define SERCOM0_FIFO_DEPTH_POWER 1 // 2^FIFO_DEPTH_POWER gives rx FIFO depth.
145 #define SERCOM0_GCLK_ID_CORE 7
146 #define SERCOM0_GCLK_ID_SLOW 3
147 #define SERCOM0_INT_MSB 6
148 #define SERCOM0_I2CM 1 // I2C Master mode implemented?
149 #define SERCOM0_I2CS 1 // I2C Slave mode implemented?
150 #define SERCOM0_I2CS_AUTO_ACK 1 // I2C slave automatic acknowledge implemented?
151 #define SERCOM0_I2CS_GROUP_CMD 1 // I2C slave group command implemented?
152 #define SERCOM0_I2CS_SDASETUP_CNT_SIZE 8 // I2CS sda setup count size
153 #define SERCOM0_I2CS_SDASETUP_SIZE 4 // I2CS sda setup size
154 #define SERCOM0_I2CS_SUDAT 1 // I2C slave SDA setup implemented?
155 #define SERCOM0_I2C_FASTMP 1 // I2C fast mode plus implemented?
156 #define SERCOM0_I2C_HSMODE 1 // USART mode implemented?
157 #define SERCOM0_I2C_SCLSM_MODE 1 // I2C SCL clock stretch mode implemented?
158 #define SERCOM0_I2C_SMB_TIMEOUTS 1 // I2C SMBus timeouts implemented?
159 #define SERCOM0_I2C_TENBIT_ADR 1 // I2C ten bit enabled?
160 #define SERCOM0_PMSB 3
161 #define SERCOM0_RETENTION_SUPPORT 0 // Retention supported?
162 #define SERCOM0_SE_CNT 1 // SE counter included?
163 #define SERCOM0_SPI 1 // SPI mode implemented?
164 #define SERCOM0_SPI_HW_SS_CTRL 1 // Master _SS hardware control implemented?
165 #define SERCOM0_SPI_ICSPACE_EXT 1 // SPI inter character space implemented?
166 #define SERCOM0_SPI_OZMO 0 // OZMO features implemented?
167 #define SERCOM0_SPI_WAKE_ON_SSL 1 // _SS low detect implemented?
168 #define SERCOM0_TTBIT_EXTENSION 1 // 32-bit extension implemented?
169 #define SERCOM0_USART 1 // USART mode implemented?
170 #define SERCOM0_USART_AUTOBAUD 1 // USART autobaud implemented?
171 #define SERCOM0_USART_COLDET 1 // USART collision detection implemented?
172 #define SERCOM0_USART_FLOW_CTRL 1 // USART flow control implemented?
173 #define SERCOM0_USART_FRAC_BAUD 1 // USART fractional BAUD implemented?
174 #define SERCOM0_USART_IRDA 1 // USART IrDA implemented?
175 #define SERCOM0_USART_ISO7816 1 // USART ISO7816 mode implemented?
176 #define SERCOM0_USART_LIN_MASTER 1 // USART LIN Master mode implemented?
177 #define SERCOM0_USART_RS485 1 // USART RS485 mode implemented?
178 #define SERCOM0_USART_SAMPA_EXT 1 // USART sample adjust implemented?
179 #define SERCOM0_USART_SAMPR_EXT 1 // USART oversampling adjustment implemented?