SAME54P20A Test Project
sercom1.h
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1 
30 #ifndef _SAME54_SERCOM1_INSTANCE_
31 #define _SAME54_SERCOM1_INSTANCE_
32 
33 /* ========== Register definition for SERCOM1 peripheral ========== */
34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
35 #define REG_SERCOM1_I2CM_CTRLA (0x40003400)
36 #define REG_SERCOM1_I2CM_CTRLB (0x40003404)
37 #define REG_SERCOM1_I2CM_CTRLC (0x40003408)
38 #define REG_SERCOM1_I2CM_BAUD (0x4000340C)
39 #define REG_SERCOM1_I2CM_INTENCLR (0x40003414)
40 #define REG_SERCOM1_I2CM_INTENSET (0x40003416)
41 #define REG_SERCOM1_I2CM_INTFLAG (0x40003418)
42 #define REG_SERCOM1_I2CM_STATUS (0x4000341A)
43 #define REG_SERCOM1_I2CM_SYNCBUSY (0x4000341C)
44 #define REG_SERCOM1_I2CM_ADDR (0x40003424)
45 #define REG_SERCOM1_I2CM_DATA (0x40003428)
46 #define REG_SERCOM1_I2CM_DBGCTRL (0x40003430)
47 #define REG_SERCOM1_I2CS_CTRLA (0x40003400)
48 #define REG_SERCOM1_I2CS_CTRLB (0x40003404)
49 #define REG_SERCOM1_I2CS_CTRLC (0x40003408)
50 #define REG_SERCOM1_I2CS_INTENCLR (0x40003414)
51 #define REG_SERCOM1_I2CS_INTENSET (0x40003416)
52 #define REG_SERCOM1_I2CS_INTFLAG (0x40003418)
53 #define REG_SERCOM1_I2CS_STATUS (0x4000341A)
54 #define REG_SERCOM1_I2CS_SYNCBUSY (0x4000341C)
55 #define REG_SERCOM1_I2CS_LENGTH (0x40003422)
56 #define REG_SERCOM1_I2CS_ADDR (0x40003424)
57 #define REG_SERCOM1_I2CS_DATA (0x40003428)
58 #define REG_SERCOM1_SPI_CTRLA (0x40003400)
59 #define REG_SERCOM1_SPI_CTRLB (0x40003404)
60 #define REG_SERCOM1_SPI_CTRLC (0x40003408)
61 #define REG_SERCOM1_SPI_BAUD (0x4000340C)
62 #define REG_SERCOM1_SPI_INTENCLR (0x40003414)
63 #define REG_SERCOM1_SPI_INTENSET (0x40003416)
64 #define REG_SERCOM1_SPI_INTFLAG (0x40003418)
65 #define REG_SERCOM1_SPI_STATUS (0x4000341A)
66 #define REG_SERCOM1_SPI_SYNCBUSY (0x4000341C)
67 #define REG_SERCOM1_SPI_LENGTH (0x40003422)
68 #define REG_SERCOM1_SPI_ADDR (0x40003424)
69 #define REG_SERCOM1_SPI_DATA (0x40003428)
70 #define REG_SERCOM1_SPI_DBGCTRL (0x40003430)
71 #define REG_SERCOM1_USART_CTRLA (0x40003400)
72 #define REG_SERCOM1_USART_CTRLB (0x40003404)
73 #define REG_SERCOM1_USART_CTRLC (0x40003408)
74 #define REG_SERCOM1_USART_BAUD (0x4000340C)
75 #define REG_SERCOM1_USART_RXPL (0x4000340E)
76 #define REG_SERCOM1_USART_INTENCLR (0x40003414)
77 #define REG_SERCOM1_USART_INTENSET (0x40003416)
78 #define REG_SERCOM1_USART_INTFLAG (0x40003418)
79 #define REG_SERCOM1_USART_STATUS (0x4000341A)
80 #define REG_SERCOM1_USART_SYNCBUSY (0x4000341C)
81 #define REG_SERCOM1_USART_RXERRCNT (0x40003420)
82 #define REG_SERCOM1_USART_LENGTH (0x40003422)
83 #define REG_SERCOM1_USART_DATA (0x40003428)
84 #define REG_SERCOM1_USART_DBGCTRL (0x40003430)
85 #else
86 #define REG_SERCOM1_I2CM_CTRLA (*(RwReg *)0x40003400UL)
87 #define REG_SERCOM1_I2CM_CTRLB (*(RwReg *)0x40003404UL)
88 #define REG_SERCOM1_I2CM_CTRLC (*(RwReg *)0x40003408UL)
89 #define REG_SERCOM1_I2CM_BAUD (*(RwReg *)0x4000340CUL)
90 #define REG_SERCOM1_I2CM_INTENCLR (*(RwReg8 *)0x40003414UL)
91 #define REG_SERCOM1_I2CM_INTENSET (*(RwReg8 *)0x40003416UL)
92 #define REG_SERCOM1_I2CM_INTFLAG (*(RwReg8 *)0x40003418UL)
93 #define REG_SERCOM1_I2CM_STATUS (*(RwReg16*)0x4000341AUL)
94 #define REG_SERCOM1_I2CM_SYNCBUSY (*(RoReg *)0x4000341CUL)
95 #define REG_SERCOM1_I2CM_ADDR (*(RwReg *)0x40003424UL)
96 #define REG_SERCOM1_I2CM_DATA (*(RwReg *)0x40003428UL)
97 #define REG_SERCOM1_I2CM_DBGCTRL (*(RwReg8 *)0x40003430UL)
98 #define REG_SERCOM1_I2CS_CTRLA (*(RwReg *)0x40003400UL)
99 #define REG_SERCOM1_I2CS_CTRLB (*(RwReg *)0x40003404UL)
100 #define REG_SERCOM1_I2CS_CTRLC (*(RwReg *)0x40003408UL)
101 #define REG_SERCOM1_I2CS_INTENCLR (*(RwReg8 *)0x40003414UL)
102 #define REG_SERCOM1_I2CS_INTENSET (*(RwReg8 *)0x40003416UL)
103 #define REG_SERCOM1_I2CS_INTFLAG (*(RwReg8 *)0x40003418UL)
104 #define REG_SERCOM1_I2CS_STATUS (*(RwReg16*)0x4000341AUL)
105 #define REG_SERCOM1_I2CS_SYNCBUSY (*(RoReg *)0x4000341CUL)
106 #define REG_SERCOM1_I2CS_LENGTH (*(RwReg16*)0x40003422UL)
107 #define REG_SERCOM1_I2CS_ADDR (*(RwReg *)0x40003424UL)
108 #define REG_SERCOM1_I2CS_DATA (*(RwReg *)0x40003428UL)
109 #define REG_SERCOM1_SPI_CTRLA (*(RwReg *)0x40003400UL)
110 #define REG_SERCOM1_SPI_CTRLB (*(RwReg *)0x40003404UL)
111 #define REG_SERCOM1_SPI_CTRLC (*(RwReg *)0x40003408UL)
112 #define REG_SERCOM1_SPI_BAUD (*(RwReg8 *)0x4000340CUL)
113 #define REG_SERCOM1_SPI_INTENCLR (*(RwReg8 *)0x40003414UL)
114 #define REG_SERCOM1_SPI_INTENSET (*(RwReg8 *)0x40003416UL)
115 #define REG_SERCOM1_SPI_INTFLAG (*(RwReg8 *)0x40003418UL)
116 #define REG_SERCOM1_SPI_STATUS (*(RwReg16*)0x4000341AUL)
117 #define REG_SERCOM1_SPI_SYNCBUSY (*(RoReg *)0x4000341CUL)
118 #define REG_SERCOM1_SPI_LENGTH (*(RwReg16*)0x40003422UL)
119 #define REG_SERCOM1_SPI_ADDR (*(RwReg *)0x40003424UL)
120 #define REG_SERCOM1_SPI_DATA (*(RwReg *)0x40003428UL)
121 #define REG_SERCOM1_SPI_DBGCTRL (*(RwReg8 *)0x40003430UL)
122 #define REG_SERCOM1_USART_CTRLA (*(RwReg *)0x40003400UL)
123 #define REG_SERCOM1_USART_CTRLB (*(RwReg *)0x40003404UL)
124 #define REG_SERCOM1_USART_CTRLC (*(RwReg *)0x40003408UL)
125 #define REG_SERCOM1_USART_BAUD (*(RwReg16*)0x4000340CUL)
126 #define REG_SERCOM1_USART_RXPL (*(RwReg8 *)0x4000340EUL)
127 #define REG_SERCOM1_USART_INTENCLR (*(RwReg8 *)0x40003414UL)
128 #define REG_SERCOM1_USART_INTENSET (*(RwReg8 *)0x40003416UL)
129 #define REG_SERCOM1_USART_INTFLAG (*(RwReg8 *)0x40003418UL)
130 #define REG_SERCOM1_USART_STATUS (*(RwReg16*)0x4000341AUL)
131 #define REG_SERCOM1_USART_SYNCBUSY (*(RoReg *)0x4000341CUL)
132 #define REG_SERCOM1_USART_RXERRCNT (*(RoReg8 *)0x40003420UL)
133 #define REG_SERCOM1_USART_LENGTH (*(RwReg16*)0x40003422UL)
134 #define REG_SERCOM1_USART_DATA (*(RwReg *)0x40003428UL)
135 #define REG_SERCOM1_USART_DBGCTRL (*(RwReg8 *)0x40003430UL)
136 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
137 
138 /* ========== Instance parameters for SERCOM1 peripheral ========== */
139 #define SERCOM1_CLK_REDUCTION 1 // Reduce clock options to pin 1 for SPI and USART
140 #define SERCOM1_DLY_COMPENSATION 1 // Compensates for a fast DLY50 element. Assuming 20ns
141 #define SERCOM1_DMA 1 // DMA support implemented?
142 #define SERCOM1_DMAC_ID_RX 6 // Index of DMA RX trigger
143 #define SERCOM1_DMAC_ID_TX 7 // Index of DMA TX trigger
144 #define SERCOM1_FIFO_DEPTH_POWER 1 // 2^FIFO_DEPTH_POWER gives rx FIFO depth.
145 #define SERCOM1_GCLK_ID_CORE 8
146 #define SERCOM1_GCLK_ID_SLOW 3
147 #define SERCOM1_INT_MSB 6
148 #define SERCOM1_I2CM 1 // I2C Master mode implemented?
149 #define SERCOM1_I2CS 1 // I2C Slave mode implemented?
150 #define SERCOM1_I2CS_AUTO_ACK 1 // I2C slave automatic acknowledge implemented?
151 #define SERCOM1_I2CS_GROUP_CMD 1 // I2C slave group command implemented?
152 #define SERCOM1_I2CS_SDASETUP_CNT_SIZE 8 // I2CS sda setup count size
153 #define SERCOM1_I2CS_SDASETUP_SIZE 4 // I2CS sda setup size
154 #define SERCOM1_I2CS_SUDAT 1 // I2C slave SDA setup implemented?
155 #define SERCOM1_I2C_FASTMP 1 // I2C fast mode plus implemented?
156 #define SERCOM1_I2C_HSMODE 1 // USART mode implemented?
157 #define SERCOM1_I2C_SCLSM_MODE 1 // I2C SCL clock stretch mode implemented?
158 #define SERCOM1_I2C_SMB_TIMEOUTS 1 // I2C SMBus timeouts implemented?
159 #define SERCOM1_I2C_TENBIT_ADR 1 // I2C ten bit enabled?
160 #define SERCOM1_PMSB 3
161 #define SERCOM1_RETENTION_SUPPORT 0 // Retention supported?
162 #define SERCOM1_SE_CNT 1 // SE counter included?
163 #define SERCOM1_SPI 1 // SPI mode implemented?
164 #define SERCOM1_SPI_HW_SS_CTRL 1 // Master _SS hardware control implemented?
165 #define SERCOM1_SPI_ICSPACE_EXT 1 // SPI inter character space implemented?
166 #define SERCOM1_SPI_OZMO 0 // OZMO features implemented?
167 #define SERCOM1_SPI_WAKE_ON_SSL 1 // _SS low detect implemented?
168 #define SERCOM1_TTBIT_EXTENSION 1 // 32-bit extension implemented?
169 #define SERCOM1_USART 1 // USART mode implemented?
170 #define SERCOM1_USART_AUTOBAUD 1 // USART autobaud implemented?
171 #define SERCOM1_USART_COLDET 1 // USART collision detection implemented?
172 #define SERCOM1_USART_FLOW_CTRL 1 // USART flow control implemented?
173 #define SERCOM1_USART_FRAC_BAUD 1 // USART fractional BAUD implemented?
174 #define SERCOM1_USART_IRDA 1 // USART IrDA implemented?
175 #define SERCOM1_USART_ISO7816 1 // USART ISO7816 mode implemented?
176 #define SERCOM1_USART_LIN_MASTER 1 // USART LIN Master mode implemented?
177 #define SERCOM1_USART_RS485 1 // USART RS485 mode implemented?
178 #define SERCOM1_USART_SAMPA_EXT 1 // USART sample adjust implemented?
179 #define SERCOM1_USART_SAMPR_EXT 1 // USART oversampling adjustment implemented?
180 
181 #endif /* _SAME54_SERCOM1_INSTANCE_ */