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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_92b117bae75cf16a05ca7611db29e9c7.html">instance</a></li> </ul>
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<div class="title">tcc1.h</div> </div>
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<a href="tcc1_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno"> 1</span>  </div>
<div class="line"><a name="l00030"></a><span class="lineno"> 30</span> <span class="preprocessor">#ifndef _SAME54_TCC1_INSTANCE_</span></div>
<div class="line"><a name="l00031"></a><span class="lineno"> 31</span> <span class="preprocessor">#define _SAME54_TCC1_INSTANCE_</span></div>
<div class="line"><a name="l00032"></a><span class="lineno"> 32</span>  </div>
<div class="line"><a name="l00033"></a><span class="lineno"> 33</span> <span class="comment">/* ========== Register definition for TCC1 peripheral ========== */</span></div>
<div class="line"><a name="l00034"></a><span class="lineno"> 34</span> <span class="preprocessor">#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
<div class="line"><a name="l00035"></a><span class="lineno"> 35</span> <span class="preprocessor">#define REG_TCC1_CTRLA (0x41018000) </span></div>
<div class="line"><a name="l00036"></a><span class="lineno"> 36</span> <span class="preprocessor">#define REG_TCC1_CTRLBCLR (0x41018004) </span></div>
<div class="line"><a name="l00037"></a><span class="lineno"> 37</span> <span class="preprocessor">#define REG_TCC1_CTRLBSET (0x41018005) </span></div>
<div class="line"><a name="l00038"></a><span class="lineno"> 38</span> <span class="preprocessor">#define REG_TCC1_SYNCBUSY (0x41018008) </span></div>
<div class="line"><a name="l00039"></a><span class="lineno"> 39</span> <span class="preprocessor">#define REG_TCC1_FCTRLA (0x4101800C) </span></div>
<div class="line"><a name="l00040"></a><span class="lineno"> 40</span> <span class="preprocessor">#define REG_TCC1_FCTRLB (0x41018010) </span></div>
<div class="line"><a name="l00041"></a><span class="lineno"> 41</span> <span class="preprocessor">#define REG_TCC1_WEXCTRL (0x41018014) </span></div>
<div class="line"><a name="l00042"></a><span class="lineno"> 42</span> <span class="preprocessor">#define REG_TCC1_DRVCTRL (0x41018018) </span></div>
<div class="line"><a name="l00043"></a><span class="lineno"> 43</span> <span class="preprocessor">#define REG_TCC1_DBGCTRL (0x4101801E) </span></div>
<div class="line"><a name="l00044"></a><span class="lineno"> 44</span> <span class="preprocessor">#define REG_TCC1_EVCTRL (0x41018020) </span></div>
<div class="line"><a name="l00045"></a><span class="lineno"> 45</span> <span class="preprocessor">#define REG_TCC1_INTENCLR (0x41018024) </span></div>
<div class="line"><a name="l00046"></a><span class="lineno"> 46</span> <span class="preprocessor">#define REG_TCC1_INTENSET (0x41018028) </span></div>
<div class="line"><a name="l00047"></a><span class="lineno"> 47</span> <span class="preprocessor">#define REG_TCC1_INTFLAG (0x4101802C) </span></div>
<div class="line"><a name="l00048"></a><span class="lineno"> 48</span> <span class="preprocessor">#define REG_TCC1_STATUS (0x41018030) </span></div>
<div class="line"><a name="l00049"></a><span class="lineno"> 49</span> <span class="preprocessor">#define REG_TCC1_COUNT (0x41018034) </span></div>
<div class="line"><a name="l00050"></a><span class="lineno"> 50</span> <span class="preprocessor">#define REG_TCC1_PATT (0x41018038) </span></div>
<div class="line"><a name="l00051"></a><span class="lineno"> 51</span> <span class="preprocessor">#define REG_TCC1_WAVE (0x4101803C) </span></div>
<div class="line"><a name="l00052"></a><span class="lineno"> 52</span> <span class="preprocessor">#define REG_TCC1_PER (0x41018040) </span></div>
<div class="line"><a name="l00053"></a><span class="lineno"> 53</span> <span class="preprocessor">#define REG_TCC1_CC0 (0x41018044) </span></div>
<div class="line"><a name="l00054"></a><span class="lineno"> 54</span> <span class="preprocessor">#define REG_TCC1_CC1 (0x41018048) </span></div>
<div class="line"><a name="l00055"></a><span class="lineno"> 55</span> <span class="preprocessor">#define REG_TCC1_CC2 (0x4101804C) </span></div>
<div class="line"><a name="l00056"></a><span class="lineno"> 56</span> <span class="preprocessor">#define REG_TCC1_CC3 (0x41018050) </span></div>
<div class="line"><a name="l00057"></a><span class="lineno"> 57</span> <span class="preprocessor">#define REG_TCC1_PATTBUF (0x41018064) </span></div>
<div class="line"><a name="l00058"></a><span class="lineno"> 58</span> <span class="preprocessor">#define REG_TCC1_PERBUF (0x4101806C) </span></div>
<div class="line"><a name="l00059"></a><span class="lineno"> 59</span> <span class="preprocessor">#define REG_TCC1_CCBUF0 (0x41018070) </span></div>
<div class="line"><a name="l00060"></a><span class="lineno"> 60</span> <span class="preprocessor">#define REG_TCC1_CCBUF1 (0x41018074) </span></div>
<div class="line"><a name="l00061"></a><span class="lineno"> 61</span> <span class="preprocessor">#define REG_TCC1_CCBUF2 (0x41018078) </span></div>
<div class="line"><a name="l00062"></a><span class="lineno"> 62</span> <span class="preprocessor">#define REG_TCC1_CCBUF3 (0x4101807C) </span></div>
<div class="line"><a name="l00063"></a><span class="lineno"> 63</span> <span class="preprocessor">#else</span></div>
<div class="line"><a name="l00064"></a><span class="lineno"><a class="line" href="tcc1_8h.html#ae5cd7851f51bed0c0120fa8eb3f705de"> 64</a></span> <span class="preprocessor">#define REG_TCC1_CTRLA (*(RwReg *)0x41018000UL) </span></div>
<div class="line"><a name="l00065"></a><span class="lineno"><a class="line" href="tcc1_8h.html#a963334a0bf0172f4af2c7ea2be63fd9b"> 65</a></span> <span class="preprocessor">#define REG_TCC1_CTRLBCLR (*(RwReg8 *)0x41018004UL) </span></div>
<div class="line"><a name="l00066"></a><span class="lineno"><a class="line" href="tcc1_8h.html#a2ccc9b17368b82bec29bd91e859b4669"> 66</a></span> <span class="preprocessor">#define REG_TCC1_CTRLBSET (*(RwReg8 *)0x41018005UL) </span></div>
<div class="line"><a name="l00067"></a><span class="lineno"><a class="line" href="tcc1_8h.html#a06e728439e8d707ef68a5837936f00b1"> 67</a></span> <span class="preprocessor">#define REG_TCC1_SYNCBUSY (*(RoReg *)0x41018008UL) </span></div>
<div class="line"><a name="l00068"></a><span class="lineno"><a class="line" href="tcc1_8h.html#a23cb6fe2cfec2c5e6489b62a326d84e5"> 68</a></span> <span class="preprocessor">#define REG_TCC1_FCTRLA (*(RwReg *)0x4101800CUL) </span></div>
<div class="line"><a name="l00069"></a><span class="lineno"><a class="line" href="tcc1_8h.html#a7ee7fd9855dcc2f260a055161ed9b1b6"> 69</a></span> <span class="preprocessor">#define REG_TCC1_FCTRLB (*(RwReg *)0x41018010UL) </span></div>
<div class="line"><a name="l00070"></a><span class="lineno"><a class="line" href="tcc1_8h.html#a6fc2dc89365fb4b0395571be69abb8ba"> 70</a></span> <span class="preprocessor">#define REG_TCC1_WEXCTRL (*(RwReg *)0x41018014UL) </span></div>
<div class="line"><a name="l00071"></a><span class="lineno"><a class="line" href="tcc1_8h.html#ab17fec223c549a0f605db732798a68c5"> 71</a></span> <span class="preprocessor">#define REG_TCC1_DRVCTRL (*(RwReg *)0x41018018UL) </span></div>
<div class="line"><a name="l00072"></a><span class="lineno"><a class="line" href="tcc1_8h.html#a6e6b584653cc910b9c289c1eda03bbe3"> 72</a></span> <span class="preprocessor">#define REG_TCC1_DBGCTRL (*(RwReg8 *)0x4101801EUL) </span></div>
<div class="line"><a name="l00073"></a><span class="lineno"><a class="line" href="tcc1_8h.html#af0b1f8e9ff3efe003808eb2d8408965e"> 73</a></span> <span class="preprocessor">#define REG_TCC1_EVCTRL (*(RwReg *)0x41018020UL) </span></div>
<div class="line"><a name="l00074"></a><span class="lineno"><a class="line" href="tcc1_8h.html#ac0cb1252cf859d4aa67d6004212ac495"> 74</a></span> <span class="preprocessor">#define REG_TCC1_INTENCLR (*(RwReg *)0x41018024UL) </span></div>
<div class="line"><a name="l00075"></a><span class="lineno"><a class="line" href="tcc1_8h.html#af07b2355341e617601807231394b5470"> 75</a></span> <span class="preprocessor">#define REG_TCC1_INTENSET (*(RwReg *)0x41018028UL) </span></div>
<div class="line"><a name="l00076"></a><span class="lineno"><a class="line" href="tcc1_8h.html#ab4cc78645dd2570eba921057e1869467"> 76</a></span> <span class="preprocessor">#define REG_TCC1_INTFLAG (*(RwReg *)0x4101802CUL) </span></div>
<div class="line"><a name="l00077"></a><span class="lineno"><a class="line" href="tcc1_8h.html#a4c77e42df68ed5322240d48e0fb13046"> 77</a></span> <span class="preprocessor">#define REG_TCC1_STATUS (*(RwReg *)0x41018030UL) </span></div>
<div class="line"><a name="l00078"></a><span class="lineno"><a class="line" href="tcc1_8h.html#a4c9fa592136ece3acfbe6a1152bca25f"> 78</a></span> <span class="preprocessor">#define REG_TCC1_COUNT (*(RwReg *)0x41018034UL) </span></div>
<div class="line"><a name="l00079"></a><span class="lineno"><a class="line" href="tcc1_8h.html#a547e919ab428cff5269cf6ceb5820afa"> 79</a></span> <span class="preprocessor">#define REG_TCC1_PATT (*(RwReg16*)0x41018038UL) </span></div>
<div class="line"><a name="l00080"></a><span class="lineno"><a class="line" href="tcc1_8h.html#ab8c27a81ebc3115d0c7de44d0e6a01ab"> 80</a></span> <span class="preprocessor">#define REG_TCC1_WAVE (*(RwReg *)0x4101803CUL) </span></div>
<div class="line"><a name="l00081"></a><span class="lineno"><a class="line" href="tcc1_8h.html#a0e578ce9efac12016f937e00e2b1b94b"> 81</a></span> <span class="preprocessor">#define REG_TCC1_PER (*(RwReg *)0x41018040UL) </span></div>
<div class="line"><a name="l00082"></a><span class="lineno"><a class="line" href="tcc1_8h.html#a21dc13ef126e1b5986e369244fe315d3"> 82</a></span> <span class="preprocessor">#define REG_TCC1_CC0 (*(RwReg *)0x41018044UL) </span></div>
<div class="line"><a name="l00083"></a><span class="lineno"><a class="line" href="tcc1_8h.html#ab4efa5c221d02499fa1b4f9b3115b525"> 83</a></span> <span class="preprocessor">#define REG_TCC1_CC1 (*(RwReg *)0x41018048UL) </span></div>
<div class="line"><a name="l00084"></a><span class="lineno"><a class="line" href="tcc1_8h.html#a9645ceb27a8f55d21687af2c3a623b82"> 84</a></span> <span class="preprocessor">#define REG_TCC1_CC2 (*(RwReg *)0x4101804CUL) </span></div>
<div class="line"><a name="l00085"></a><span class="lineno"><a class="line" href="tcc1_8h.html#aea62880e831defcb53acf897587973f1"> 85</a></span> <span class="preprocessor">#define REG_TCC1_CC3 (*(RwReg *)0x41018050UL) </span></div>
<div class="line"><a name="l00086"></a><span class="lineno"><a class="line" href="tcc1_8h.html#a570b5c372b05f1f31ca27393e4c31484"> 86</a></span> <span class="preprocessor">#define REG_TCC1_PATTBUF (*(RwReg16*)0x41018064UL) </span></div>
<div class="line"><a name="l00087"></a><span class="lineno"><a class="line" href="tcc1_8h.html#ac479a289e38b421bd57c579182ac5048"> 87</a></span> <span class="preprocessor">#define REG_TCC1_PERBUF (*(RwReg *)0x4101806CUL) </span></div>
<div class="line"><a name="l00088"></a><span class="lineno"><a class="line" href="tcc1_8h.html#a6619903bbbb39dafe30896e6e6c5c942"> 88</a></span> <span class="preprocessor">#define REG_TCC1_CCBUF0 (*(RwReg *)0x41018070UL) </span></div>
<div class="line"><a name="l00089"></a><span class="lineno"><a class="line" href="tcc1_8h.html#a2c3998d6d6a70200d0fdced604d9d74b"> 89</a></span> <span class="preprocessor">#define REG_TCC1_CCBUF1 (*(RwReg *)0x41018074UL) </span></div>
<div class="line"><a name="l00090"></a><span class="lineno"><a class="line" href="tcc1_8h.html#aa2d44ea2573632e0793df71911af2030"> 90</a></span> <span class="preprocessor">#define REG_TCC1_CCBUF2 (*(RwReg *)0x41018078UL) </span></div>
<div class="line"><a name="l00091"></a><span class="lineno"><a class="line" href="tcc1_8h.html#a693eff38fc3d27f8e6b8d8096004173f"> 91</a></span> <span class="preprocessor">#define REG_TCC1_CCBUF3 (*(RwReg *)0x4101807CUL) </span></div>
<div class="line"><a name="l00092"></a><span class="lineno"> 92</span> <span class="preprocessor">#endif </span><span class="comment">/* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00093"></a><span class="lineno"> 93</span>  </div>
<div class="line"><a name="l00094"></a><span class="lineno"> 94</span> <span class="comment">/* ========== Instance parameters for TCC1 peripheral ========== */</span></div>
<div class="line"><a name="l00095"></a><span class="lineno"> 95</span> <span class="preprocessor">#define TCC1_CC_NUM 4 // Number of Compare/Capture units</span></div>
<div class="line"><a name="l00096"></a><span class="lineno"> 96</span> <span class="preprocessor">#define TCC1_DITHERING 1 // Dithering feature implemented</span></div>
<div class="line"><a name="l00097"></a><span class="lineno"> 97</span> <span class="preprocessor">#define TCC1_DMAC_ID_MC_0 30</span></div>
<div class="line"><a name="l00098"></a><span class="lineno"> 98</span> <span class="preprocessor">#define TCC1_DMAC_ID_MC_1 31</span></div>
<div class="line"><a name="l00099"></a><span class="lineno"> 99</span> <span class="preprocessor">#define TCC1_DMAC_ID_MC_2 32</span></div>
<div class="line"><a name="l00100"></a><span class="lineno"> 100</span> <span class="preprocessor">#define TCC1_DMAC_ID_MC_3 33</span></div>
<div class="line"><a name="l00101"></a><span class="lineno"> 101</span> <span class="preprocessor">#define TCC1_DMAC_ID_MC_LSB 30</span></div>
<div class="line"><a name="l00102"></a><span class="lineno"> 102</span> <span class="preprocessor">#define TCC1_DMAC_ID_MC_MSB 33</span></div>
<div class="line"><a name="l00103"></a><span class="lineno"> 103</span> <span class="preprocessor">#define TCC1_DMAC_ID_MC_SIZE 4</span></div>
<div class="line"><a name="l00104"></a><span class="lineno"> 104</span> <span class="preprocessor">#define TCC1_DMAC_ID_OVF 29 // DMA overflow/underflow/retrigger trigger</span></div>
<div class="line"><a name="l00105"></a><span class="lineno"> 105</span> <span class="preprocessor">#define TCC1_DTI 1 // Dead-Time-Insertion feature implemented</span></div>
<div class="line"><a name="l00106"></a><span class="lineno"> 106</span> <span class="preprocessor">#define TCC1_EXT 31 // Coding of implemented extended features</span></div>
<div class="line"><a name="l00107"></a><span class="lineno"> 107</span> <span class="preprocessor">#define TCC1_GCLK_ID 25 // Index of Generic Clock</span></div>
<div class="line"><a name="l00108"></a><span class="lineno"> 108</span> <span class="preprocessor">#define TCC1_MASTER_SLAVE_MODE 2 // TCC type 0 : NA, 1 : Master, 2 : Slave</span></div>
<div class="line"><a name="l00109"></a><span class="lineno"> 109</span> <span class="preprocessor">#define TCC1_OTMX 1 // Output Matrix feature implemented</span></div>
<div class="line"><a name="l00110"></a><span class="lineno"> 110</span> <span class="preprocessor">#define TCC1_OW_NUM 8 // Number of Output Waveforms</span></div>
<div class="line"><a name="l00111"></a><span class="lineno"> 111</span> <span class="preprocessor">#define TCC1_PG 1 // Pattern Generation feature implemented</span></div>
<div class="line"><a name="l00112"></a><span class="lineno"> 112</span> <span class="preprocessor">#define TCC1_SIZE 24 </span></div>
<div class="line"><a name="l00113"></a><span class="lineno"> 113</span> <span class="preprocessor">#define TCC1_SWAP 1 // DTI outputs swap feature implemented</span></div>
<div class="line"><a name="l00114"></a><span class="lineno"> 114</span>  </div>
<div class="line"><a name="l00115"></a><span class="lineno"> 115</span> <span class="preprocessor">#endif </span><span class="comment">/* _SAME54_TCC1_INSTANCE_ */</span><span class="preprocessor"></span></div>
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