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30 #ifndef _SAME54_TC0_INSTANCE_
31 #define _SAME54_TC0_INSTANCE_
34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
35 #define REG_TC0_CTRLA (0x40003800)
36 #define REG_TC0_CTRLBCLR (0x40003804)
37 #define REG_TC0_CTRLBSET (0x40003805)
38 #define REG_TC0_EVCTRL (0x40003806)
39 #define REG_TC0_INTENCLR (0x40003808)
40 #define REG_TC0_INTENSET (0x40003809)
41 #define REG_TC0_INTFLAG (0x4000380A)
42 #define REG_TC0_STATUS (0x4000380B)
43 #define REG_TC0_WAVE (0x4000380C)
44 #define REG_TC0_DRVCTRL (0x4000380D)
45 #define REG_TC0_DBGCTRL (0x4000380F)
46 #define REG_TC0_SYNCBUSY (0x40003810)
47 #define REG_TC0_COUNT16_COUNT (0x40003814)
48 #define REG_TC0_COUNT16_CC0 (0x4000381C)
49 #define REG_TC0_COUNT16_CC1 (0x4000381E)
50 #define REG_TC0_COUNT16_CCBUF0 (0x40003830)
51 #define REG_TC0_COUNT16_CCBUF1 (0x40003832)
52 #define REG_TC0_COUNT32_COUNT (0x40003814)
53 #define REG_TC0_COUNT32_CC0 (0x4000381C)
54 #define REG_TC0_COUNT32_CC1 (0x40003820)
55 #define REG_TC0_COUNT32_CCBUF0 (0x40003830)
56 #define REG_TC0_COUNT32_CCBUF1 (0x40003834)
57 #define REG_TC0_COUNT8_COUNT (0x40003814)
58 #define REG_TC0_COUNT8_PER (0x4000381B)
59 #define REG_TC0_COUNT8_CC0 (0x4000381C)
60 #define REG_TC0_COUNT8_CC1 (0x4000381D)
61 #define REG_TC0_COUNT8_PERBUF (0x4000382F)
62 #define REG_TC0_COUNT8_CCBUF0 (0x40003830)
63 #define REG_TC0_COUNT8_CCBUF1 (0x40003831)
65 #define REG_TC0_CTRLA (*(RwReg *)0x40003800UL)
66 #define REG_TC0_CTRLBCLR (*(RwReg8 *)0x40003804UL)
67 #define REG_TC0_CTRLBSET (*(RwReg8 *)0x40003805UL)
68 #define REG_TC0_EVCTRL (*(RwReg16*)0x40003806UL)
69 #define REG_TC0_INTENCLR (*(RwReg8 *)0x40003808UL)
70 #define REG_TC0_INTENSET (*(RwReg8 *)0x40003809UL)
71 #define REG_TC0_INTFLAG (*(RwReg8 *)0x4000380AUL)
72 #define REG_TC0_STATUS (*(RwReg8 *)0x4000380BUL)
73 #define REG_TC0_WAVE (*(RwReg8 *)0x4000380CUL)
74 #define REG_TC0_DRVCTRL (*(RwReg8 *)0x4000380DUL)
75 #define REG_TC0_DBGCTRL (*(RwReg8 *)0x4000380FUL)
76 #define REG_TC0_SYNCBUSY (*(RoReg *)0x40003810UL)
77 #define REG_TC0_COUNT16_COUNT (*(RwReg16*)0x40003814UL)
78 #define REG_TC0_COUNT16_CC0 (*(RwReg16*)0x4000381CUL)
79 #define REG_TC0_COUNT16_CC1 (*(RwReg16*)0x4000381EUL)
80 #define REG_TC0_COUNT16_CCBUF0 (*(RwReg16*)0x40003830UL)
81 #define REG_TC0_COUNT16_CCBUF1 (*(RwReg16*)0x40003832UL)
82 #define REG_TC0_COUNT32_COUNT (*(RwReg *)0x40003814UL)
83 #define REG_TC0_COUNT32_CC0 (*(RwReg *)0x4000381CUL)
84 #define REG_TC0_COUNT32_CC1 (*(RwReg *)0x40003820UL)
85 #define REG_TC0_COUNT32_CCBUF0 (*(RwReg *)0x40003830UL)
86 #define REG_TC0_COUNT32_CCBUF1 (*(RwReg *)0x40003834UL)
87 #define REG_TC0_COUNT8_COUNT (*(RwReg8 *)0x40003814UL)
88 #define REG_TC0_COUNT8_PER (*(RwReg8 *)0x4000381BUL)
89 #define REG_TC0_COUNT8_CC0 (*(RwReg8 *)0x4000381CUL)
90 #define REG_TC0_COUNT8_CC1 (*(RwReg8 *)0x4000381DUL)
91 #define REG_TC0_COUNT8_PERBUF (*(RwReg8 *)0x4000382FUL)
92 #define REG_TC0_COUNT8_CCBUF0 (*(RwReg8 *)0x40003830UL)
93 #define REG_TC0_COUNT8_CCBUF1 (*(RwReg8 *)0x40003831UL)
98 #define TC0_DMAC_ID_MC_0 45
99 #define TC0_DMAC_ID_MC_1 46
100 #define TC0_DMAC_ID_MC_LSB 45
101 #define TC0_DMAC_ID_MC_MSB 46
102 #define TC0_DMAC_ID_MC_SIZE 2
103 #define TC0_DMAC_ID_OVF 44 // Indexes of DMA Overflow trigger
104 #define TC0_EXT 0 // Coding of implemented extended features (keep 0 value)
105 #define TC0_GCLK_ID 9 // Index of Generic Clock
106 #define TC0_MASTER_SLAVE_MODE 1 // TC type 0 : NA, 1 : Master, 2 : Slave
107 #define TC0_OW_NUM 2 // Number of Output Waveforms
