doc/html/adc1_8h_source.html

#ifndef _SAME54_ADC1_INSTANCE_

#define _SAME54_ADC1_INSTANCE_


/* ========== Register definition for ADC1 peripheral ========== */

#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

#define REG_ADC1_CTRLA             (0x43002000)

#define REG_ADC1_EVCTRL            (0x43002002)

#define REG_ADC1_DBGCTRL           (0x43002003)

#define REG_ADC1_INPUTCTRL         (0x43002004)

#define REG_ADC1_CTRLB             (0x43002006)

#define REG_ADC1_REFCTRL           (0x43002008)

#define REG_ADC1_AVGCTRL           (0x4300200A)

#define REG_ADC1_SAMPCTRL          (0x4300200B)

#define REG_ADC1_WINLT             (0x4300200C)

#define REG_ADC1_WINUT             (0x4300200E)

#define REG_ADC1_GAINCORR          (0x43002010)

#define REG_ADC1_OFFSETCORR        (0x43002012)

#define REG_ADC1_SWTRIG            (0x43002014)

#define REG_ADC1_INTENCLR          (0x4300202C)

#define REG_ADC1_INTENSET          (0x4300202D)

#define REG_ADC1_INTFLAG           (0x4300202E)

#define REG_ADC1_STATUS            (0x4300202F)

#define REG_ADC1_SYNCBUSY          (0x43002030)

#define REG_ADC1_DSEQDATA          (0x43002034)

#define REG_ADC1_DSEQCTRL          (0x43002038)

#define REG_ADC1_DSEQSTAT          (0x4300203C)

#define REG_ADC1_RESULT            (0x43002040)

#define REG_ADC1_RESS              (0x43002044)

#define REG_ADC1_CALIB             (0x43002048)

#else

#define REG_ADC1_CTRLA             (*(RwReg16*)0x43002000UL)

#define REG_ADC1_EVCTRL            (*(RwReg8 *)0x43002002UL)

#define REG_ADC1_DBGCTRL           (*(RwReg8 *)0x43002003UL)

#define REG_ADC1_INPUTCTRL         (*(RwReg16*)0x43002004UL)

#define REG_ADC1_CTRLB             (*(RwReg16*)0x43002006UL)

#define REG_ADC1_REFCTRL           (*(RwReg8 *)0x43002008UL)

#define REG_ADC1_AVGCTRL           (*(RwReg8 *)0x4300200AUL)

#define REG_ADC1_SAMPCTRL          (*(RwReg8 *)0x4300200BUL)

#define REG_ADC1_WINLT             (*(RwReg16*)0x4300200CUL)

#define REG_ADC1_WINUT             (*(RwReg16*)0x4300200EUL)

#define REG_ADC1_GAINCORR          (*(RwReg16*)0x43002010UL)

#define REG_ADC1_OFFSETCORR        (*(RwReg16*)0x43002012UL)

#define REG_ADC1_SWTRIG            (*(RwReg8 *)0x43002014UL)

#define REG_ADC1_INTENCLR          (*(RwReg8 *)0x4300202CUL)

#define REG_ADC1_INTENSET          (*(RwReg8 *)0x4300202DUL)

#define REG_ADC1_INTFLAG           (*(RwReg8 *)0x4300202EUL)

#define REG_ADC1_STATUS            (*(RoReg8 *)0x4300202FUL)

#define REG_ADC1_SYNCBUSY          (*(RoReg  *)0x43002030UL)

#define REG_ADC1_DSEQDATA          (*(WoReg  *)0x43002034UL)

#define REG_ADC1_DSEQCTRL          (*(RwReg  *)0x43002038UL)

#define REG_ADC1_DSEQSTAT          (*(RoReg  *)0x4300203CUL)

#define REG_ADC1_RESULT            (*(RoReg16*)0x43002040UL)

#define REG_ADC1_RESS              (*(RoReg16*)0x43002044UL)

#define REG_ADC1_CALIB             (*(RwReg16*)0x43002048UL)

#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


/* ========== Instance parameters for ADC1 peripheral ========== */

#define ADC1_BANDGAP                27       // MUXPOS value to select BANDGAP

#define ADC1_CTAT                   29       // MUXPOS value to select CTAT

#define ADC1_DMAC_ID_RESRDY         70       // Index of DMA RESRDY trigger

#define ADC1_DMAC_ID_SEQ            71       // Index of DMA SEQ trigger

#define ADC1_EXTCHANNEL_MSB         15       // Number of external channels

#define ADC1_GCLK_ID                41       // Index of Generic Clock

#define ADC1_MASTER_SLAVE_MODE      2        // ADC Master/Slave Mode

#define ADC1_OPAMP2                 0        // MUXPOS value to select OPAMP2

#define ADC1_OPAMP01                0        // MUXPOS value to select OPAMP01

#define ADC1_PTAT                   28       // MUXPOS value to select PTAT

#define ADC1_TOUCH_IMPLEMENTED      0        // TOUCH implemented or not

#define ADC1_TOUCH_LINES_NUM        1        // Number of touch lines


#endif /* _SAME54_ADC1_INSTANCE_ */