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#ifndef _SAME54_ADC0_INSTANCE_

#define _SAME54_ADC0_INSTANCE_


/* ========== Register definition for ADC0 peripheral ========== */

#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

#define REG_ADC0_CTRLA             (0x43001C00)

#define REG_ADC0_EVCTRL            (0x43001C02)

#define REG_ADC0_DBGCTRL           (0x43001C03)

#define REG_ADC0_INPUTCTRL         (0x43001C04)

#define REG_ADC0_CTRLB             (0x43001C06)

#define REG_ADC0_REFCTRL           (0x43001C08)

#define REG_ADC0_AVGCTRL           (0x43001C0A)

#define REG_ADC0_SAMPCTRL          (0x43001C0B)

#define REG_ADC0_WINLT             (0x43001C0C)

#define REG_ADC0_WINUT             (0x43001C0E)

#define REG_ADC0_GAINCORR          (0x43001C10)

#define REG_ADC0_OFFSETCORR        (0x43001C12)

#define REG_ADC0_SWTRIG            (0x43001C14)

#define REG_ADC0_INTENCLR          (0x43001C2C)

#define REG_ADC0_INTENSET          (0x43001C2D)

#define REG_ADC0_INTFLAG           (0x43001C2E)

#define REG_ADC0_STATUS            (0x43001C2F)

#define REG_ADC0_SYNCBUSY          (0x43001C30)

#define REG_ADC0_DSEQDATA          (0x43001C34)

#define REG_ADC0_DSEQCTRL          (0x43001C38)

#define REG_ADC0_DSEQSTAT          (0x43001C3C)

#define REG_ADC0_RESULT            (0x43001C40)

#define REG_ADC0_RESS              (0x43001C44)

#define REG_ADC0_CALIB             (0x43001C48)

#else

#define REG_ADC0_CTRLA             (*(RwReg16*)0x43001C00UL)

#define REG_ADC0_EVCTRL            (*(RwReg8 *)0x43001C02UL)

#define REG_ADC0_DBGCTRL           (*(RwReg8 *)0x43001C03UL)

#define REG_ADC0_INPUTCTRL         (*(RwReg16*)0x43001C04UL)

#define REG_ADC0_CTRLB             (*(RwReg16*)0x43001C06UL)

#define REG_ADC0_REFCTRL           (*(RwReg8 *)0x43001C08UL)

#define REG_ADC0_AVGCTRL           (*(RwReg8 *)0x43001C0AUL)

#define REG_ADC0_SAMPCTRL          (*(RwReg8 *)0x43001C0BUL)

#define REG_ADC0_WINLT             (*(RwReg16*)0x43001C0CUL)

#define REG_ADC0_WINUT             (*(RwReg16*)0x43001C0EUL)

#define REG_ADC0_GAINCORR          (*(RwReg16*)0x43001C10UL)

#define REG_ADC0_OFFSETCORR        (*(RwReg16*)0x43001C12UL)

#define REG_ADC0_SWTRIG            (*(RwReg8 *)0x43001C14UL)

#define REG_ADC0_INTENCLR          (*(RwReg8 *)0x43001C2CUL)

#define REG_ADC0_INTENSET          (*(RwReg8 *)0x43001C2DUL)

#define REG_ADC0_INTFLAG           (*(RwReg8 *)0x43001C2EUL)

#define REG_ADC0_STATUS            (*(RoReg8 *)0x43001C2FUL)

#define REG_ADC0_SYNCBUSY          (*(RoReg  *)0x43001C30UL)

#define REG_ADC0_DSEQDATA          (*(WoReg  *)0x43001C34UL)

#define REG_ADC0_DSEQCTRL          (*(RwReg  *)0x43001C38UL)

#define REG_ADC0_DSEQSTAT          (*(RoReg  *)0x43001C3CUL)

#define REG_ADC0_RESULT            (*(RoReg16*)0x43001C40UL)

#define REG_ADC0_RESS              (*(RoReg16*)0x43001C44UL)

#define REG_ADC0_CALIB             (*(RwReg16*)0x43001C48UL)

#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


/* ========== Instance parameters for ADC0 peripheral ========== */

#define ADC0_BANDGAP                27       // MUXPOS value to select BANDGAP

#define ADC0_CTAT                   29       // MUXPOS value to select CTAT

#define ADC0_DMAC_ID_RESRDY         68       // index of DMA RESRDY trigger

#define ADC0_DMAC_ID_SEQ            69       // Index of DMA SEQ trigger

#define ADC0_EXTCHANNEL_MSB         15       // Number of external channels

#define ADC0_GCLK_ID                40       // index of Generic Clock

#define ADC0_MASTER_SLAVE_MODE      1        // ADC Master/Slave Mode

#define ADC0_OPAMP2                 0        // MUXPOS value to select OPAMP2

#define ADC0_OPAMP01                0        // MUXPOS value to select OPAMP01

#define ADC0_PTAT                   28       // MUXPOS value to select PTAT

#define ADC0_TOUCH_IMPLEMENTED      1        // TOUCH implemented or not


#endif /* _SAME54_ADC0_INSTANCE_ */