doc/html/sdhc0_8h_source.html

#ifndef _SAME54_SDHC0_INSTANCE_

#define _SAME54_SDHC0_INSTANCE_


/* ========== Register definition for SDHC0 peripheral ========== */

#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

#define REG_SDHC0_SSAR             (0x45000000)

#define REG_SDHC0_BSR              (0x45000004)

#define REG_SDHC0_BCR              (0x45000006)

#define REG_SDHC0_ARG1R            (0x45000008)

#define REG_SDHC0_TMR              (0x4500000C)

#define REG_SDHC0_CR               (0x4500000E)

#define REG_SDHC0_RR0              (0x45000010)

#define REG_SDHC0_RR1              (0x45000014)

#define REG_SDHC0_RR2              (0x45000018)

#define REG_SDHC0_RR3              (0x4500001C)

#define REG_SDHC0_BDPR             (0x45000020)

#define REG_SDHC0_PSR              (0x45000024)

#define REG_SDHC0_HC1R             (0x45000028)

#define REG_SDHC0_PCR              (0x45000029)

#define REG_SDHC0_BGCR             (0x4500002A)

#define REG_SDHC0_WCR              (0x4500002B)

#define REG_SDHC0_CCR              (0x4500002C)

#define REG_SDHC0_TCR              (0x4500002E)

#define REG_SDHC0_SRR              (0x4500002F)

#define REG_SDHC0_NISTR            (0x45000030)

#define REG_SDHC0_EISTR            (0x45000032)

#define REG_SDHC0_NISTER           (0x45000034)

#define REG_SDHC0_EISTER           (0x45000036)

#define REG_SDHC0_NISIER           (0x45000038)

#define REG_SDHC0_EISIER           (0x4500003A)

#define REG_SDHC0_ACESR            (0x4500003C)

#define REG_SDHC0_HC2R             (0x4500003E)

#define REG_SDHC0_CA0R             (0x45000040)

#define REG_SDHC0_CA1R             (0x45000044)

#define REG_SDHC0_MCCAR            (0x45000048)

#define REG_SDHC0_FERACES          (0x45000050)

#define REG_SDHC0_FEREIS           (0x45000052)

#define REG_SDHC0_AESR             (0x45000054)

#define REG_SDHC0_ASAR0            (0x45000058)

#define REG_SDHC0_PVR0             (0x45000060)

#define REG_SDHC0_PVR1             (0x45000062)

#define REG_SDHC0_PVR2             (0x45000064)

#define REG_SDHC0_PVR3             (0x45000066)

#define REG_SDHC0_PVR4             (0x45000068)

#define REG_SDHC0_PVR5             (0x4500006A)

#define REG_SDHC0_PVR6             (0x4500006C)

#define REG_SDHC0_PVR7             (0x4500006E)

#define REG_SDHC0_SISR             (0x450000FC)

#define REG_SDHC0_HCVR             (0x450000FE)

#define REG_SDHC0_MC1R             (0x45000204)

#define REG_SDHC0_MC2R             (0x45000205)

#define REG_SDHC0_ACR              (0x45000208)

#define REG_SDHC0_CC2R             (0x4500020C)

#define REG_SDHC0_CACR             (0x45000230)

#define REG_SDHC0_DBGR             (0x45000234)

#else

#define REG_SDHC0_SSAR             (*(RwReg  *)0x45000000UL)

#define REG_SDHC0_BSR              (*(RwReg16*)0x45000004UL)

#define REG_SDHC0_BCR              (*(RwReg16*)0x45000006UL)

#define REG_SDHC0_ARG1R            (*(RwReg  *)0x45000008UL)

#define REG_SDHC0_TMR              (*(RwReg16*)0x4500000CUL)

#define REG_SDHC0_CR               (*(RwReg16*)0x4500000EUL)

#define REG_SDHC0_RR0              (*(RoReg  *)0x45000010UL)

#define REG_SDHC0_RR1              (*(RoReg  *)0x45000014UL)

#define REG_SDHC0_RR2              (*(RoReg  *)0x45000018UL)

#define REG_SDHC0_RR3              (*(RoReg  *)0x4500001CUL)

#define REG_SDHC0_BDPR             (*(RwReg  *)0x45000020UL)

#define REG_SDHC0_PSR              (*(RoReg  *)0x45000024UL)

#define REG_SDHC0_HC1R             (*(RwReg8 *)0x45000028UL)

#define REG_SDHC0_PCR              (*(RwReg8 *)0x45000029UL)

#define REG_SDHC0_BGCR             (*(RwReg8 *)0x4500002AUL)

#define REG_SDHC0_WCR              (*(RwReg8 *)0x4500002BUL)

#define REG_SDHC0_CCR              (*(RwReg16*)0x4500002CUL)

#define REG_SDHC0_TCR              (*(RwReg8 *)0x4500002EUL)

#define REG_SDHC0_SRR              (*(RwReg8 *)0x4500002FUL)

#define REG_SDHC0_NISTR            (*(RwReg16*)0x45000030UL)

#define REG_SDHC0_EISTR            (*(RwReg16*)0x45000032UL)

#define REG_SDHC0_NISTER           (*(RwReg16*)0x45000034UL)

#define REG_SDHC0_EISTER           (*(RwReg16*)0x45000036UL)

#define REG_SDHC0_NISIER           (*(RwReg16*)0x45000038UL)

#define REG_SDHC0_EISIER           (*(RwReg16*)0x4500003AUL)

#define REG_SDHC0_ACESR            (*(RoReg16*)0x4500003CUL)

#define REG_SDHC0_HC2R             (*(RwReg16*)0x4500003EUL)

#define REG_SDHC0_CA0R             (*(RoReg  *)0x45000040UL)

#define REG_SDHC0_CA1R             (*(RoReg  *)0x45000044UL)

#define REG_SDHC0_MCCAR            (*(RoReg  *)0x45000048UL)

#define REG_SDHC0_FERACES          (*(WoReg16*)0x45000050UL)

#define REG_SDHC0_FEREIS           (*(WoReg16*)0x45000052UL)

#define REG_SDHC0_AESR             (*(RoReg8 *)0x45000054UL)

#define REG_SDHC0_ASAR0            (*(RwReg  *)0x45000058UL)

#define REG_SDHC0_PVR0             (*(RwReg16*)0x45000060UL)

#define REG_SDHC0_PVR1             (*(RwReg16*)0x45000062UL)

#define REG_SDHC0_PVR2             (*(RwReg16*)0x45000064UL)

#define REG_SDHC0_PVR3             (*(RwReg16*)0x45000066UL)

#define REG_SDHC0_PVR4             (*(RwReg16*)0x45000068UL)

#define REG_SDHC0_PVR5             (*(RwReg16*)0x4500006AUL)

#define REG_SDHC0_PVR6             (*(RwReg16*)0x4500006CUL)

#define REG_SDHC0_PVR7             (*(RwReg16*)0x4500006EUL)

#define REG_SDHC0_SISR             (*(RoReg16*)0x450000FCUL)

#define REG_SDHC0_HCVR             (*(RoReg16*)0x450000FEUL)

#define REG_SDHC0_MC1R             (*(RwReg8 *)0x45000204UL)

#define REG_SDHC0_MC2R             (*(WoReg8 *)0x45000205UL)

#define REG_SDHC0_ACR              (*(RwReg  *)0x45000208UL)

#define REG_SDHC0_CC2R             (*(RwReg  *)0x4500020CUL)

#define REG_SDHC0_CACR             (*(RwReg  *)0x45000230UL)

#define REG_SDHC0_DBGR             (*(RwReg8 *)0x45000234UL)

#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


/* ========== Instance parameters for SDHC0 peripheral ========== */

#define SDHC0_CARD_DATA_SIZE        4

#define SDHC0_CLK_AHB_ID            15

#define SDHC0_GCLK_ID               45

#define SDHC0_GCLK_ID_SLOW          3

#define SDHC0_NB_OF_DEVICES         1

#define SDHC0_NB_REG_PVR            8

#define SDHC0_NB_REG_RR             4


#endif /* _SAME54_SDHC0_INSTANCE_ */