doc/html/instance_2mclk_8h_source.html

#ifndef _SAME54_MCLK_INSTANCE_

#define _SAME54_MCLK_INSTANCE_


/* ========== Register definition for MCLK peripheral ========== */

#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

#define REG_MCLK_INTENCLR          (0x40000801)

#define REG_MCLK_INTENSET          (0x40000802)

#define REG_MCLK_INTFLAG           (0x40000803)

#define REG_MCLK_HSDIV             (0x40000804)

#define REG_MCLK_CPUDIV            (0x40000805)

#define REG_MCLK_AHBMASK           (0x40000810)

#define REG_MCLK_APBAMASK          (0x40000814)

#define REG_MCLK_APBBMASK          (0x40000818)

#define REG_MCLK_APBCMASK          (0x4000081C)

#define REG_MCLK_APBDMASK          (0x40000820)

#else

#define REG_MCLK_INTENCLR          (*(RwReg8 *)0x40000801UL)

#define REG_MCLK_INTENSET          (*(RwReg8 *)0x40000802UL)

#define REG_MCLK_INTFLAG           (*(RwReg8 *)0x40000803UL)

#define REG_MCLK_HSDIV             (*(RoReg8 *)0x40000804UL)

#define REG_MCLK_CPUDIV            (*(RwReg8 *)0x40000805UL)

#define REG_MCLK_AHBMASK           (*(RwReg  *)0x40000810UL)

#define REG_MCLK_APBAMASK          (*(RwReg  *)0x40000814UL)

#define REG_MCLK_APBBMASK          (*(RwReg  *)0x40000818UL)

#define REG_MCLK_APBCMASK          (*(RwReg  *)0x4000081CUL)

#define REG_MCLK_APBDMASK          (*(RwReg  *)0x40000820UL)

#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


/* ========== Instance parameters for MCLK peripheral ========== */

#define MCLK_SYSTEM_CLOCK           48000000 // System Clock Frequency at Reset


#endif /* _SAME54_MCLK_INSTANCE_ */