doc/html/tc2_8h_source.html

#ifndef _SAME54_TC2_INSTANCE_

#define _SAME54_TC2_INSTANCE_


/* ========== Register definition for TC2 peripheral ========== */

#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

#define REG_TC2_CTRLA              (0x4101A000)

#define REG_TC2_CTRLBCLR           (0x4101A004)

#define REG_TC2_CTRLBSET           (0x4101A005)

#define REG_TC2_EVCTRL             (0x4101A006)

#define REG_TC2_INTENCLR           (0x4101A008)

#define REG_TC2_INTENSET           (0x4101A009)

#define REG_TC2_INTFLAG            (0x4101A00A)

#define REG_TC2_STATUS             (0x4101A00B)

#define REG_TC2_WAVE               (0x4101A00C)

#define REG_TC2_DRVCTRL            (0x4101A00D)

#define REG_TC2_DBGCTRL            (0x4101A00F)

#define REG_TC2_SYNCBUSY           (0x4101A010)

#define REG_TC2_COUNT16_COUNT      (0x4101A014)

#define REG_TC2_COUNT16_CC0        (0x4101A01C)

#define REG_TC2_COUNT16_CC1        (0x4101A01E)

#define REG_TC2_COUNT16_CCBUF0     (0x4101A030)

#define REG_TC2_COUNT16_CCBUF1     (0x4101A032)

#define REG_TC2_COUNT32_COUNT      (0x4101A014)

#define REG_TC2_COUNT32_CC0        (0x4101A01C)

#define REG_TC2_COUNT32_CC1        (0x4101A020)

#define REG_TC2_COUNT32_CCBUF0     (0x4101A030)

#define REG_TC2_COUNT32_CCBUF1     (0x4101A034)

#define REG_TC2_COUNT8_COUNT       (0x4101A014)

#define REG_TC2_COUNT8_PER         (0x4101A01B)

#define REG_TC2_COUNT8_CC0         (0x4101A01C)

#define REG_TC2_COUNT8_CC1         (0x4101A01D)

#define REG_TC2_COUNT8_PERBUF      (0x4101A02F)

#define REG_TC2_COUNT8_CCBUF0      (0x4101A030)

#define REG_TC2_COUNT8_CCBUF1      (0x4101A031)

#else

#define REG_TC2_CTRLA              (*(RwReg  *)0x4101A000UL)

#define REG_TC2_CTRLBCLR           (*(RwReg8 *)0x4101A004UL)

#define REG_TC2_CTRLBSET           (*(RwReg8 *)0x4101A005UL)

#define REG_TC2_EVCTRL             (*(RwReg16*)0x4101A006UL)

#define REG_TC2_INTENCLR           (*(RwReg8 *)0x4101A008UL)

#define REG_TC2_INTENSET           (*(RwReg8 *)0x4101A009UL)

#define REG_TC2_INTFLAG            (*(RwReg8 *)0x4101A00AUL)

#define REG_TC2_STATUS             (*(RwReg8 *)0x4101A00BUL)

#define REG_TC2_WAVE               (*(RwReg8 *)0x4101A00CUL)

#define REG_TC2_DRVCTRL            (*(RwReg8 *)0x4101A00DUL)

#define REG_TC2_DBGCTRL            (*(RwReg8 *)0x4101A00FUL)

#define REG_TC2_SYNCBUSY           (*(RoReg  *)0x4101A010UL)

#define REG_TC2_COUNT16_COUNT      (*(RwReg16*)0x4101A014UL)

#define REG_TC2_COUNT16_CC0        (*(RwReg16*)0x4101A01CUL)

#define REG_TC2_COUNT16_CC1        (*(RwReg16*)0x4101A01EUL)

#define REG_TC2_COUNT16_CCBUF0     (*(RwReg16*)0x4101A030UL)

#define REG_TC2_COUNT16_CCBUF1     (*(RwReg16*)0x4101A032UL)

#define REG_TC2_COUNT32_COUNT      (*(RwReg  *)0x4101A014UL)

#define REG_TC2_COUNT32_CC0        (*(RwReg  *)0x4101A01CUL)

#define REG_TC2_COUNT32_CC1        (*(RwReg  *)0x4101A020UL)

#define REG_TC2_COUNT32_CCBUF0     (*(RwReg  *)0x4101A030UL)

#define REG_TC2_COUNT32_CCBUF1     (*(RwReg  *)0x4101A034UL)

#define REG_TC2_COUNT8_COUNT       (*(RwReg8 *)0x4101A014UL)

#define REG_TC2_COUNT8_PER         (*(RwReg8 *)0x4101A01BUL)

#define REG_TC2_COUNT8_CC0         (*(RwReg8 *)0x4101A01CUL)

#define REG_TC2_COUNT8_CC1         (*(RwReg8 *)0x4101A01DUL)

#define REG_TC2_COUNT8_PERBUF      (*(RwReg8 *)0x4101A02FUL)

#define REG_TC2_COUNT8_CCBUF0      (*(RwReg8 *)0x4101A030UL)

#define REG_TC2_COUNT8_CCBUF1      (*(RwReg8 *)0x4101A031UL)

#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


/* ========== Instance parameters for TC2 peripheral ========== */

#define TC2_CC_NUM                  2

#define TC2_DMAC_ID_MC_0            51

#define TC2_DMAC_ID_MC_1            52

#define TC2_DMAC_ID_MC_LSB          51

#define TC2_DMAC_ID_MC_MSB          52

#define TC2_DMAC_ID_MC_SIZE         2

#define TC2_DMAC_ID_OVF             50       // Indexes of DMA Overflow trigger

#define TC2_EXT                     0        // Coding of implemented extended features (keep 0 value)

#define TC2_GCLK_ID                 26       // Index of Generic Clock

#define TC2_MASTER_SLAVE_MODE       1        // TC type 0 : NA, 1 : Master, 2 : Slave

#define TC2_OW_NUM                  2        // Number of Output Waveforms


#endif /* _SAME54_TC2_INSTANCE_ */