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<h4 class="subsection">9.15.10 Intel's MMX and AMD's 3DNow! SIMD Operations</h4>
<p><a name="index-MMX_002c-i386-1135"></a><a name="index-g_t3DNow_0021_002c-i386-1136"></a><a name="index-SIMD_002c-i386-1137"></a><a name="index-MMX_002c-x86_002d64-1138"></a><a name="index-g_t3DNow_0021_002c-x86_002d64-1139"></a><a name="index-SIMD_002c-x86_002d64-1140"></a>
<code>as</code> supports Intel's MMX instruction set (SIMD
instructions for integer data), available on Intel's Pentium MMX
processors and Pentium II processors, AMD's K6 and K6-2 processors,
Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow!
instruction set (SIMD instructions for 32-bit floating point data)
available on AMD's K6-2 processor and possibly others in the future.
<p>Currently, <code>as</code> does not support Intel's floating point
SIMD, Katmai (KNI).
<p>The eight 64-bit MMX operands, also used by 3DNow!, are called ‘<samp><span class="samp">%mm0</span></samp>’,
‘<samp><span class="samp">%mm1</span></samp>’, ... ‘<samp><span class="samp">%mm7</span></samp>’. They contain eight 8-bit integers, four
16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit
floating point values. The MMX registers cannot be used at the same time
as the floating point stack.
<p>See Intel and AMD documentation, keeping in mind that the operand order in
instructions is reversed from the Intel syntax.
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