<html lang="en">
<head>
<title>i386-Memory - Using as</title>
<meta http-equiv="Content-Type" content="text/html">
<meta name="description" content="Using as">
<meta name="generator" content="makeinfo 4.13">
<link title="Top" rel="start" href="index.html#Top">
<link rel="up" href="i386_002dDependent.html#i386_002dDependent" title="i386-Dependent">
<link rel="prev" href="i386_002dPrefixes.html#i386_002dPrefixes" title="i386-Prefixes">
<link rel="next" href="i386_002dJumps.html#i386_002dJumps" title="i386-Jumps">
<link href="http://www.gnu.org/software/texinfo/" rel="generator-home" title="Texinfo Homepage">
<!--
This file documents the GNU Assembler "as".
Copyright (C) 1991-2015 Free Software Foundation, Inc.
Permission is granted to copy, distribute and/or modify this document
under the terms of the GNU Free Documentation License, Version 1.3
or any later version published by the Free Software Foundation;
with no Invariant Sections, with no Front-Cover Texts, and with no
Back-Cover Texts. A copy of the license is included in the
section entitled ``GNU Free Documentation License''.
-->
<meta http-equiv="Content-Style-Type" content="text/css">
<style type="text/css"><!--
pre.display { font-family:inherit }
pre.format { font-family:inherit }
pre.smalldisplay { font-family:inherit; font-size:smaller }
pre.smallformat { font-family:inherit; font-size:smaller }
pre.smallexample { font-size:smaller }
pre.smalllisp { font-size:smaller }
span.sc { font-variant:small-caps }
span.roman { font-family:serif; font-weight:normal; }
span.sansserif { font-family:sans-serif; font-weight:normal; }
--></style>
</head>
<body>
<div class="node">
<a name="i386-Memory"></a>
<a name="i386_002dMemory"></a>
<p>
Next: <a rel="next" accesskey="n" href="i386_002dJumps.html#i386_002dJumps">i386-Jumps</a>,
Previous: <a rel="previous" accesskey="p" href="i386_002dPrefixes.html#i386_002dPrefixes">i386-Prefixes</a>,
Up: <a rel="up" accesskey="u" href="i386_002dDependent.html#i386_002dDependent">i386-Dependent</a>
<hr>
</div>
<h4 class="subsection">9.15.7 Memory References</h4>
<p><a name="index-i386-memory-references-1107"></a><a name="index-memory-references_002c-i386-1108"></a><a name="index-x86_002d64-memory-references-1109"></a><a name="index-memory-references_002c-x86_002d64-1110"></a>An Intel syntax indirect memory reference of the form
<pre class="smallexample"> <var>section</var>:[<var>base</var> + <var>index</var>*<var>scale</var> + <var>disp</var>]
</pre>
<p class="noindent">is translated into the AT&T syntax
<pre class="smallexample"> <var>section</var>:<var>disp</var>(<var>base</var>, <var>index</var>, <var>scale</var>)
</pre>
<p class="noindent">where <var>base</var> and <var>index</var> are the optional 32-bit base and
index registers, <var>disp</var> is the optional displacement, and
<var>scale</var>, taking the values 1, 2, 4, and 8, multiplies <var>index</var>
to calculate the address of the operand. If no <var>scale</var> is
specified, <var>scale</var> is taken to be 1. <var>section</var> specifies the
optional section register for the memory operand, and may override the
default section register (see a 80386 manual for section register
defaults). Note that section overrides in AT&T syntax <em>must</em>
be preceded by a ‘<samp><span class="samp">%</span></samp>’. If you specify a section override which
coincides with the default section register, <code>as</code> does <em>not</em>
output any section register override prefixes to assemble the given
instruction. Thus, section overrides can be specified to emphasize which
section register is used for a given memory operand.
<p>Here are some examples of Intel and AT&T style memory references:
<dl>
<dt>AT&T: ‘<samp><span class="samp">-4(%ebp)</span></samp>’, Intel: ‘<samp><span class="samp">[ebp - 4]</span></samp>’<dd><var>base</var> is ‘<samp><span class="samp">%ebp</span></samp>’; <var>disp</var> is ‘<samp><span class="samp">-4</span></samp>’. <var>section</var> is
missing, and the default section is used (‘<samp><span class="samp">%ss</span></samp>’ for addressing with
‘<samp><span class="samp">%ebp</span></samp>’ as the base register). <var>index</var>, <var>scale</var> are both missing.
<br><dt>AT&T: ‘<samp><span class="samp">foo(,%eax,4)</span></samp>’, Intel: ‘<samp><span class="samp">[foo + eax*4]</span></samp>’<dd><var>index</var> is ‘<samp><span class="samp">%eax</span></samp>’ (scaled by a <var>scale</var> 4); <var>disp</var> is
‘<samp><span class="samp">foo</span></samp>’. All other fields are missing. The section register here
defaults to ‘<samp><span class="samp">%ds</span></samp>’.
<br><dt>AT&T: ‘<samp><span class="samp">foo(,1)</span></samp>’; Intel ‘<samp><span class="samp">[foo]</span></samp>’<dd>This uses the value pointed to by ‘<samp><span class="samp">foo</span></samp>’ as a memory operand.
Note that <var>base</var> and <var>index</var> are both missing, but there is only
<em>one</em> ‘<samp><span class="samp">,</span></samp>’. This is a syntactic exception.
<br><dt>AT&T: ‘<samp><span class="samp">%gs:foo</span></samp>’; Intel ‘<samp><span class="samp">gs:foo</span></samp>’<dd>This selects the contents of the variable ‘<samp><span class="samp">foo</span></samp>’ with section
register <var>section</var> being ‘<samp><span class="samp">%gs</span></samp>’.
</dl>
<p>Absolute (as opposed to PC relative) call and jump operands must be
prefixed with ‘<samp><span class="samp">*</span></samp>’. If no ‘<samp><span class="samp">*</span></samp>’ is specified, <code>as</code>
always chooses PC relative addressing for jump/call labels.
<p>Any instruction that has a memory operand, but no register operand,
<em>must</em> specify its size (byte, word, long, or quadruple) with an
instruction mnemonic suffix (‘<samp><span class="samp">b</span></samp>’, ‘<samp><span class="samp">w</span></samp>’, ‘<samp><span class="samp">l</span></samp>’ or ‘<samp><span class="samp">q</span></samp>’,
respectively).
<p>The x86-64 architecture adds an RIP (instruction pointer relative)
addressing. This addressing mode is specified by using ‘<samp><span class="samp">rip</span></samp>’ as a
base register. Only constant offsets are valid. For example:
<dl>
<dt>AT&T: ‘<samp><span class="samp">1234(%rip)</span></samp>’, Intel: ‘<samp><span class="samp">[rip + 1234]</span></samp>’<dd>Points to the address 1234 bytes past the end of the current
instruction.
<br><dt>AT&T: ‘<samp><span class="samp">symbol(%rip)</span></samp>’, Intel: ‘<samp><span class="samp">[rip + symbol]</span></samp>’<dd>Points to the <code>symbol</code> in RIP relative way, this is shorter than
the default absolute addressing.
</dl>
<p>Other addressing modes remain unchanged in x86-64 architecture, except
registers used are 64-bit instead of 32-bit.
</body></html>