These are the options defined for the Altera Nios II processor.
-G num-mgpopt=option-mgpopt-mno-gpoptsection
attribute.
-mgpopt is equivalent to -mgpopt=local, and -mno-gpopt is equivalent to -mgpopt=none.
The default is -mgpopt except when -fpic or -fPIC is specified to generate position-independent code. Note that the Nios II ABI does not permit GP-relative accesses from shared libraries.
You may need to specify -mno-gpopt explicitly when building
programs that include large amounts of small data, including large
GOT data sections. In this case, the 16-bit offset for GP-relative
addressing may not be large enough to allow access to the entire
small data section.
-mel-meb-mbypass-cache-mno-bypass-cache-mno-cache-volatile-mcache-volatile-mno-fast-sw-div-mfast-sw-div-mno-hw-mul-mhw-mul-mno-hw-mulx-mhw-mulx-mno-hw-div-mhw-divmul, mulx and div family of
instructions by the compiler. The default is to emit mul
and not emit div and mulx.
-mcustom-insn=N-mno-custom-insnThe following values of insn are supported. Except as otherwise noted, floating-point operations are expected to be implemented with normal IEEE 754 semantics and correspond directly to the C operators or the equivalent GCC built-in functions (see Other Builtins).
Single-precision floating point:
Double-precision floating point:
Conversions:
__builtin_lroundf function when
-fno-math-errno is used.
In addition, all of the following transfer instructions for internal registers X and Y must be provided to use any of the double-precision floating-point instructions. Custom instructions taking two double-precision source operands expect the first operand in the 64-bit register X. The other operand (or only operand of a unary operation) is given to the custom arithmetic instruction with the least significant half in source register src1 and the most significant half in src2. A custom instruction that returns a double-precision result returns the most significant 32 bits in the destination register and the other half in 32-bit register Y. GCC automatically generates the necessary code sequences to write register X and/or read register Y when double-precision floating-point instructions are used.
Note that you can gain more local control over generation of Nios II custom
instructions by using the target("custom-insn=N")
and target("no-custom-insn") function attributes
(see Function Attributes)
or pragmas (see Function Specific Option Pragmas).
-mcustom-fpu-cfg=name-mcustom-fpu-cfg=60-1 is equivalent to:
-mcustom-fmuls=252
-mcustom-fadds=253
-mcustom-fsubs=254
-fsingle-precision-constant
-mcustom-fpu-cfg=60-2 is equivalent to:
-mcustom-fmuls=252
-mcustom-fadds=253
-mcustom-fsubs=254
-mcustom-fdivs=255
-fsingle-precision-constant
-mcustom-fpu-cfg=72-3 is equivalent to:
-mcustom-floatus=243
-mcustom-fixsi=244
-mcustom-floatis=245
-mcustom-fcmpgts=246
-mcustom-fcmples=249
-mcustom-fcmpeqs=250
-mcustom-fcmpnes=251
-mcustom-fmuls=252
-mcustom-fadds=253
-mcustom-fsubs=254
-mcustom-fdivs=255
-fsingle-precision-constant
Custom instruction assignments given by individual -mcustom-insn= options override those given by -mcustom-fpu-cfg=, regardless of the order of the options on the command line.
Note that you can gain more local control over selection of a FPU
configuration by using the target("custom-fpu-cfg=name")
function attribute (see Function Attributes)
or pragma (see Function Specific Option Pragmas).
These additional ‘-m’ options are available for the Altera Nios II ELF (bare-metal) target:
-mhal-msmallc-msys-crt0=startfile-msys-lib=systemlibread and write.
This option is typically used to link with a library provided by a HAL BSP.