doc/html/tc5_8h_source.html

#ifndef _SAME54_TC5_INSTANCE_

#define _SAME54_TC5_INSTANCE_


/* ========== Register definition for TC5 peripheral ========== */

#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

#define REG_TC5_CTRLA              (0x42001800)

#define REG_TC5_CTRLBCLR           (0x42001804)

#define REG_TC5_CTRLBSET           (0x42001805)

#define REG_TC5_EVCTRL             (0x42001806)

#define REG_TC5_INTENCLR           (0x42001808)

#define REG_TC5_INTENSET           (0x42001809)

#define REG_TC5_INTFLAG            (0x4200180A)

#define REG_TC5_STATUS             (0x4200180B)

#define REG_TC5_WAVE               (0x4200180C)

#define REG_TC5_DRVCTRL            (0x4200180D)

#define REG_TC5_DBGCTRL            (0x4200180F)

#define REG_TC5_SYNCBUSY           (0x42001810)

#define REG_TC5_COUNT16_COUNT      (0x42001814)

#define REG_TC5_COUNT16_CC0        (0x4200181C)

#define REG_TC5_COUNT16_CC1        (0x4200181E)

#define REG_TC5_COUNT16_CCBUF0     (0x42001830)

#define REG_TC5_COUNT16_CCBUF1     (0x42001832)

#define REG_TC5_COUNT32_COUNT      (0x42001814)

#define REG_TC5_COUNT32_CC0        (0x4200181C)

#define REG_TC5_COUNT32_CC1        (0x42001820)

#define REG_TC5_COUNT32_CCBUF0     (0x42001830)

#define REG_TC5_COUNT32_CCBUF1     (0x42001834)

#define REG_TC5_COUNT8_COUNT       (0x42001814)

#define REG_TC5_COUNT8_PER         (0x4200181B)

#define REG_TC5_COUNT8_CC0         (0x4200181C)

#define REG_TC5_COUNT8_CC1         (0x4200181D)

#define REG_TC5_COUNT8_PERBUF      (0x4200182F)

#define REG_TC5_COUNT8_CCBUF0      (0x42001830)

#define REG_TC5_COUNT8_CCBUF1      (0x42001831)

#else

#define REG_TC5_CTRLA              (*(RwReg  *)0x42001800UL)

#define REG_TC5_CTRLBCLR           (*(RwReg8 *)0x42001804UL)

#define REG_TC5_CTRLBSET           (*(RwReg8 *)0x42001805UL)

#define REG_TC5_EVCTRL             (*(RwReg16*)0x42001806UL)

#define REG_TC5_INTENCLR           (*(RwReg8 *)0x42001808UL)

#define REG_TC5_INTENSET           (*(RwReg8 *)0x42001809UL)

#define REG_TC5_INTFLAG            (*(RwReg8 *)0x4200180AUL)

#define REG_TC5_STATUS             (*(RwReg8 *)0x4200180BUL)

#define REG_TC5_WAVE               (*(RwReg8 *)0x4200180CUL)

#define REG_TC5_DRVCTRL            (*(RwReg8 *)0x4200180DUL)

#define REG_TC5_DBGCTRL            (*(RwReg8 *)0x4200180FUL)

#define REG_TC5_SYNCBUSY           (*(RoReg  *)0x42001810UL)

#define REG_TC5_COUNT16_COUNT      (*(RwReg16*)0x42001814UL)

#define REG_TC5_COUNT16_CC0        (*(RwReg16*)0x4200181CUL)

#define REG_TC5_COUNT16_CC1        (*(RwReg16*)0x4200181EUL)

#define REG_TC5_COUNT16_CCBUF0     (*(RwReg16*)0x42001830UL)

#define REG_TC5_COUNT16_CCBUF1     (*(RwReg16*)0x42001832UL)

#define REG_TC5_COUNT32_COUNT      (*(RwReg  *)0x42001814UL)

#define REG_TC5_COUNT32_CC0        (*(RwReg  *)0x4200181CUL)

#define REG_TC5_COUNT32_CC1        (*(RwReg  *)0x42001820UL)

#define REG_TC5_COUNT32_CCBUF0     (*(RwReg  *)0x42001830UL)

#define REG_TC5_COUNT32_CCBUF1     (*(RwReg  *)0x42001834UL)

#define REG_TC5_COUNT8_COUNT       (*(RwReg8 *)0x42001814UL)

#define REG_TC5_COUNT8_PER         (*(RwReg8 *)0x4200181BUL)

#define REG_TC5_COUNT8_CC0         (*(RwReg8 *)0x4200181CUL)

#define REG_TC5_COUNT8_CC1         (*(RwReg8 *)0x4200181DUL)

#define REG_TC5_COUNT8_PERBUF      (*(RwReg8 *)0x4200182FUL)

#define REG_TC5_COUNT8_CCBUF0      (*(RwReg8 *)0x42001830UL)

#define REG_TC5_COUNT8_CCBUF1      (*(RwReg8 *)0x42001831UL)

#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


/* ========== Instance parameters for TC5 peripheral ========== */

#define TC5_CC_NUM                  2

#define TC5_DMAC_ID_MC_0            60

#define TC5_DMAC_ID_MC_1            61

#define TC5_DMAC_ID_MC_LSB          60

#define TC5_DMAC_ID_MC_MSB          61

#define TC5_DMAC_ID_MC_SIZE         2

#define TC5_DMAC_ID_OVF             59       // Indexes of DMA Overflow trigger

#define TC5_EXT                     0        // Coding of implemented extended features (keep 0 value)

#define TC5_GCLK_ID                 30       // Index of Generic Clock

#define TC5_MASTER_SLAVE_MODE       2        // TC type 0 : NA, 1 : Master, 2 : Slave

#define TC5_OW_NUM                  2        // Number of Output Waveforms


#endif /* _SAME54_TC5_INSTANCE_ */