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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_92b117bae75cf16a05ca7611db29e9c7.html">instance</a></li> </ul>
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<div class="title">tc1.h</div> </div>
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<a href="tc1_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno"> 1</span>  </div>
<div class="line"><a name="l00030"></a><span class="lineno"> 30</span> <span class="preprocessor">#ifndef _SAME54_TC1_INSTANCE_</span></div>
<div class="line"><a name="l00031"></a><span class="lineno"> 31</span> <span class="preprocessor">#define _SAME54_TC1_INSTANCE_</span></div>
<div class="line"><a name="l00032"></a><span class="lineno"> 32</span>  </div>
<div class="line"><a name="l00033"></a><span class="lineno"> 33</span> <span class="comment">/* ========== Register definition for TC1 peripheral ========== */</span></div>
<div class="line"><a name="l00034"></a><span class="lineno"> 34</span> <span class="preprocessor">#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
<div class="line"><a name="l00035"></a><span class="lineno"> 35</span> <span class="preprocessor">#define REG_TC1_CTRLA (0x40003C00) </span></div>
<div class="line"><a name="l00036"></a><span class="lineno"> 36</span> <span class="preprocessor">#define REG_TC1_CTRLBCLR (0x40003C04) </span></div>
<div class="line"><a name="l00037"></a><span class="lineno"> 37</span> <span class="preprocessor">#define REG_TC1_CTRLBSET (0x40003C05) </span></div>
<div class="line"><a name="l00038"></a><span class="lineno"> 38</span> <span class="preprocessor">#define REG_TC1_EVCTRL (0x40003C06) </span></div>
<div class="line"><a name="l00039"></a><span class="lineno"> 39</span> <span class="preprocessor">#define REG_TC1_INTENCLR (0x40003C08) </span></div>
<div class="line"><a name="l00040"></a><span class="lineno"> 40</span> <span class="preprocessor">#define REG_TC1_INTENSET (0x40003C09) </span></div>
<div class="line"><a name="l00041"></a><span class="lineno"> 41</span> <span class="preprocessor">#define REG_TC1_INTFLAG (0x40003C0A) </span></div>
<div class="line"><a name="l00042"></a><span class="lineno"> 42</span> <span class="preprocessor">#define REG_TC1_STATUS (0x40003C0B) </span></div>
<div class="line"><a name="l00043"></a><span class="lineno"> 43</span> <span class="preprocessor">#define REG_TC1_WAVE (0x40003C0C) </span></div>
<div class="line"><a name="l00044"></a><span class="lineno"> 44</span> <span class="preprocessor">#define REG_TC1_DRVCTRL (0x40003C0D) </span></div>
<div class="line"><a name="l00045"></a><span class="lineno"> 45</span> <span class="preprocessor">#define REG_TC1_DBGCTRL (0x40003C0F) </span></div>
<div class="line"><a name="l00046"></a><span class="lineno"> 46</span> <span class="preprocessor">#define REG_TC1_SYNCBUSY (0x40003C10) </span></div>
<div class="line"><a name="l00047"></a><span class="lineno"> 47</span> <span class="preprocessor">#define REG_TC1_COUNT16_COUNT (0x40003C14) </span></div>
<div class="line"><a name="l00048"></a><span class="lineno"> 48</span> <span class="preprocessor">#define REG_TC1_COUNT16_CC0 (0x40003C1C) </span></div>
<div class="line"><a name="l00049"></a><span class="lineno"> 49</span> <span class="preprocessor">#define REG_TC1_COUNT16_CC1 (0x40003C1E) </span></div>
<div class="line"><a name="l00050"></a><span class="lineno"> 50</span> <span class="preprocessor">#define REG_TC1_COUNT16_CCBUF0 (0x40003C30) </span></div>
<div class="line"><a name="l00051"></a><span class="lineno"> 51</span> <span class="preprocessor">#define REG_TC1_COUNT16_CCBUF1 (0x40003C32) </span></div>
<div class="line"><a name="l00052"></a><span class="lineno"> 52</span> <span class="preprocessor">#define REG_TC1_COUNT32_COUNT (0x40003C14) </span></div>
<div class="line"><a name="l00053"></a><span class="lineno"> 53</span> <span class="preprocessor">#define REG_TC1_COUNT32_CC0 (0x40003C1C) </span></div>
<div class="line"><a name="l00054"></a><span class="lineno"> 54</span> <span class="preprocessor">#define REG_TC1_COUNT32_CC1 (0x40003C20) </span></div>
<div class="line"><a name="l00055"></a><span class="lineno"> 55</span> <span class="preprocessor">#define REG_TC1_COUNT32_CCBUF0 (0x40003C30) </span></div>
<div class="line"><a name="l00056"></a><span class="lineno"> 56</span> <span class="preprocessor">#define REG_TC1_COUNT32_CCBUF1 (0x40003C34) </span></div>
<div class="line"><a name="l00057"></a><span class="lineno"> 57</span> <span class="preprocessor">#define REG_TC1_COUNT8_COUNT (0x40003C14) </span></div>
<div class="line"><a name="l00058"></a><span class="lineno"> 58</span> <span class="preprocessor">#define REG_TC1_COUNT8_PER (0x40003C1B) </span></div>
<div class="line"><a name="l00059"></a><span class="lineno"> 59</span> <span class="preprocessor">#define REG_TC1_COUNT8_CC0 (0x40003C1C) </span></div>
<div class="line"><a name="l00060"></a><span class="lineno"> 60</span> <span class="preprocessor">#define REG_TC1_COUNT8_CC1 (0x40003C1D) </span></div>
<div class="line"><a name="l00061"></a><span class="lineno"> 61</span> <span class="preprocessor">#define REG_TC1_COUNT8_PERBUF (0x40003C2F) </span></div>
<div class="line"><a name="l00062"></a><span class="lineno"> 62</span> <span class="preprocessor">#define REG_TC1_COUNT8_CCBUF0 (0x40003C30) </span></div>
<div class="line"><a name="l00063"></a><span class="lineno"> 63</span> <span class="preprocessor">#define REG_TC1_COUNT8_CCBUF1 (0x40003C31) </span></div>
<div class="line"><a name="l00064"></a><span class="lineno"> 64</span> <span class="preprocessor">#else</span></div>
<div class="line"><a name="l00065"></a><span class="lineno"><a class="line" href="tc1_8h.html#a0a9dbca3546f30c58d3477e1b9161e84"> 65</a></span> <span class="preprocessor">#define REG_TC1_CTRLA (*(RwReg *)0x40003C00UL) </span></div>
<div class="line"><a name="l00066"></a><span class="lineno"><a class="line" href="tc1_8h.html#aadcbe3781a33dc7215cde8f635f20667"> 66</a></span> <span class="preprocessor">#define REG_TC1_CTRLBCLR (*(RwReg8 *)0x40003C04UL) </span></div>
<div class="line"><a name="l00067"></a><span class="lineno"><a class="line" href="tc1_8h.html#acc6ab9e9fe44924b2f698ad5cb216be9"> 67</a></span> <span class="preprocessor">#define REG_TC1_CTRLBSET (*(RwReg8 *)0x40003C05UL) </span></div>
<div class="line"><a name="l00068"></a><span class="lineno"><a class="line" href="tc1_8h.html#acd8d2a074cfa058a121bf23a55ecf97b"> 68</a></span> <span class="preprocessor">#define REG_TC1_EVCTRL (*(RwReg16*)0x40003C06UL) </span></div>
<div class="line"><a name="l00069"></a><span class="lineno"><a class="line" href="tc1_8h.html#afbb4d1a4ccc1ad903d89aeccb4be383e"> 69</a></span> <span class="preprocessor">#define REG_TC1_INTENCLR (*(RwReg8 *)0x40003C08UL) </span></div>
<div class="line"><a name="l00070"></a><span class="lineno"><a class="line" href="tc1_8h.html#a3030be985f98283b26a0585d4f27a6c5"> 70</a></span> <span class="preprocessor">#define REG_TC1_INTENSET (*(RwReg8 *)0x40003C09UL) </span></div>
<div class="line"><a name="l00071"></a><span class="lineno"><a class="line" href="tc1_8h.html#a916b0925cfc0d56c0ef525bddc3484c3"> 71</a></span> <span class="preprocessor">#define REG_TC1_INTFLAG (*(RwReg8 *)0x40003C0AUL) </span></div>
<div class="line"><a name="l00072"></a><span class="lineno"><a class="line" href="tc1_8h.html#a96e0b5d907ce70227674f79112b3159d"> 72</a></span> <span class="preprocessor">#define REG_TC1_STATUS (*(RwReg8 *)0x40003C0BUL) </span></div>
<div class="line"><a name="l00073"></a><span class="lineno"><a class="line" href="tc1_8h.html#a0794a522e6da1e9cbf7e0b36047c20a4"> 73</a></span> <span class="preprocessor">#define REG_TC1_WAVE (*(RwReg8 *)0x40003C0CUL) </span></div>
<div class="line"><a name="l00074"></a><span class="lineno"><a class="line" href="tc1_8h.html#afa3c3d2561520ebbbe5e35f44d3f342e"> 74</a></span> <span class="preprocessor">#define REG_TC1_DRVCTRL (*(RwReg8 *)0x40003C0DUL) </span></div>
<div class="line"><a name="l00075"></a><span class="lineno"><a class="line" href="tc1_8h.html#a769bd85182f186d59d852c50a39487b5"> 75</a></span> <span class="preprocessor">#define REG_TC1_DBGCTRL (*(RwReg8 *)0x40003C0FUL) </span></div>
<div class="line"><a name="l00076"></a><span class="lineno"><a class="line" href="tc1_8h.html#a2358d473a1f1b31584f211f03f898483"> 76</a></span> <span class="preprocessor">#define REG_TC1_SYNCBUSY (*(RoReg *)0x40003C10UL) </span></div>
<div class="line"><a name="l00077"></a><span class="lineno"><a class="line" href="tc1_8h.html#a804f4496b30e88e317256bb747f2f4e3"> 77</a></span> <span class="preprocessor">#define REG_TC1_COUNT16_COUNT (*(RwReg16*)0x40003C14UL) </span></div>
<div class="line"><a name="l00078"></a><span class="lineno"><a class="line" href="tc1_8h.html#ae81fce3e1e140410d9201a5a888555df"> 78</a></span> <span class="preprocessor">#define REG_TC1_COUNT16_CC0 (*(RwReg16*)0x40003C1CUL) </span></div>
<div class="line"><a name="l00079"></a><span class="lineno"><a class="line" href="tc1_8h.html#a4950b58e50683fa3460a9aa388a9ca7d"> 79</a></span> <span class="preprocessor">#define REG_TC1_COUNT16_CC1 (*(RwReg16*)0x40003C1EUL) </span></div>
<div class="line"><a name="l00080"></a><span class="lineno"><a class="line" href="tc1_8h.html#a3059e231fbb3d435d421d4b3ec2cf0cd"> 80</a></span> <span class="preprocessor">#define REG_TC1_COUNT16_CCBUF0 (*(RwReg16*)0x40003C30UL) </span></div>
<div class="line"><a name="l00081"></a><span class="lineno"><a class="line" href="tc1_8h.html#ab65a164e8c97de7a93a8a815aa1096d6"> 81</a></span> <span class="preprocessor">#define REG_TC1_COUNT16_CCBUF1 (*(RwReg16*)0x40003C32UL) </span></div>
<div class="line"><a name="l00082"></a><span class="lineno"><a class="line" href="tc1_8h.html#a058b7e2c8a62536d7d366c8aa1290208"> 82</a></span> <span class="preprocessor">#define REG_TC1_COUNT32_COUNT (*(RwReg *)0x40003C14UL) </span></div>
<div class="line"><a name="l00083"></a><span class="lineno"><a class="line" href="tc1_8h.html#a14c57991003eaecac14a17359d0a5c6c"> 83</a></span> <span class="preprocessor">#define REG_TC1_COUNT32_CC0 (*(RwReg *)0x40003C1CUL) </span></div>
<div class="line"><a name="l00084"></a><span class="lineno"><a class="line" href="tc1_8h.html#a67432de67d5e3c52e4dc6fb2ab0d22f3"> 84</a></span> <span class="preprocessor">#define REG_TC1_COUNT32_CC1 (*(RwReg *)0x40003C20UL) </span></div>
<div class="line"><a name="l00085"></a><span class="lineno"><a class="line" href="tc1_8h.html#a0eea55fb6eabe4e24f640e04a1261d09"> 85</a></span> <span class="preprocessor">#define REG_TC1_COUNT32_CCBUF0 (*(RwReg *)0x40003C30UL) </span></div>
<div class="line"><a name="l00086"></a><span class="lineno"><a class="line" href="tc1_8h.html#a468f4b2e5135c280d511ba9ce1b8fccb"> 86</a></span> <span class="preprocessor">#define REG_TC1_COUNT32_CCBUF1 (*(RwReg *)0x40003C34UL) </span></div>
<div class="line"><a name="l00087"></a><span class="lineno"><a class="line" href="tc1_8h.html#a56816963c7df555650aa44d4db2cbd8e"> 87</a></span> <span class="preprocessor">#define REG_TC1_COUNT8_COUNT (*(RwReg8 *)0x40003C14UL) </span></div>
<div class="line"><a name="l00088"></a><span class="lineno"><a class="line" href="tc1_8h.html#a5ae8237a49dcf2e4061bbc9255fbf256"> 88</a></span> <span class="preprocessor">#define REG_TC1_COUNT8_PER (*(RwReg8 *)0x40003C1BUL) </span></div>
<div class="line"><a name="l00089"></a><span class="lineno"><a class="line" href="tc1_8h.html#a742cb8bcf2a98af4cbef1cd639a2eda2"> 89</a></span> <span class="preprocessor">#define REG_TC1_COUNT8_CC0 (*(RwReg8 *)0x40003C1CUL) </span></div>
<div class="line"><a name="l00090"></a><span class="lineno"><a class="line" href="tc1_8h.html#a1e221ba2ad876cc92832a0eed802f645"> 90</a></span> <span class="preprocessor">#define REG_TC1_COUNT8_CC1 (*(RwReg8 *)0x40003C1DUL) </span></div>
<div class="line"><a name="l00091"></a><span class="lineno"><a class="line" href="tc1_8h.html#ac86303282d6364125cf90b00d6057344"> 91</a></span> <span class="preprocessor">#define REG_TC1_COUNT8_PERBUF (*(RwReg8 *)0x40003C2FUL) </span></div>
<div class="line"><a name="l00092"></a><span class="lineno"><a class="line" href="tc1_8h.html#a1161cc5cb7c791e636c3a40f7c3e461d"> 92</a></span> <span class="preprocessor">#define REG_TC1_COUNT8_CCBUF0 (*(RwReg8 *)0x40003C30UL) </span></div>
<div class="line"><a name="l00093"></a><span class="lineno"><a class="line" href="tc1_8h.html#a9e4144a855ba38d4d41ce6b5184e89dd"> 93</a></span> <span class="preprocessor">#define REG_TC1_COUNT8_CCBUF1 (*(RwReg8 *)0x40003C31UL) </span></div>
<div class="line"><a name="l00094"></a><span class="lineno"> 94</span> <span class="preprocessor">#endif </span><span class="comment">/* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00095"></a><span class="lineno"> 95</span>  </div>
<div class="line"><a name="l00096"></a><span class="lineno"> 96</span> <span class="comment">/* ========== Instance parameters for TC1 peripheral ========== */</span></div>
<div class="line"><a name="l00097"></a><span class="lineno"> 97</span> <span class="preprocessor">#define TC1_CC_NUM 2 </span></div>
<div class="line"><a name="l00098"></a><span class="lineno"> 98</span> <span class="preprocessor">#define TC1_DMAC_ID_MC_0 48</span></div>
<div class="line"><a name="l00099"></a><span class="lineno"> 99</span> <span class="preprocessor">#define TC1_DMAC_ID_MC_1 49</span></div>
<div class="line"><a name="l00100"></a><span class="lineno"> 100</span> <span class="preprocessor">#define TC1_DMAC_ID_MC_LSB 48</span></div>
<div class="line"><a name="l00101"></a><span class="lineno"> 101</span> <span class="preprocessor">#define TC1_DMAC_ID_MC_MSB 49</span></div>
<div class="line"><a name="l00102"></a><span class="lineno"> 102</span> <span class="preprocessor">#define TC1_DMAC_ID_MC_SIZE 2</span></div>
<div class="line"><a name="l00103"></a><span class="lineno"> 103</span> <span class="preprocessor">#define TC1_DMAC_ID_OVF 47 // Indexes of DMA Overflow trigger</span></div>
<div class="line"><a name="l00104"></a><span class="lineno"> 104</span> <span class="preprocessor">#define TC1_EXT 0 // Coding of implemented extended features (keep 0 value)</span></div>
<div class="line"><a name="l00105"></a><span class="lineno"> 105</span> <span class="preprocessor">#define TC1_GCLK_ID 9 // Index of Generic Clock</span></div>
<div class="line"><a name="l00106"></a><span class="lineno"> 106</span> <span class="preprocessor">#define TC1_MASTER_SLAVE_MODE 2 // TC type 0 : NA, 1 : Master, 2 : Slave</span></div>
<div class="line"><a name="l00107"></a><span class="lineno"> 107</span> <span class="preprocessor">#define TC1_OW_NUM 2 // Number of Output Waveforms</span></div>
<div class="line"><a name="l00108"></a><span class="lineno"> 108</span>  </div>
<div class="line"><a name="l00109"></a><span class="lineno"> 109</span> <span class="preprocessor">#endif </span><span class="comment">/* _SAME54_TC1_INSTANCE_ */</span><span class="preprocessor"></span></div>
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