SAME54P20A Test Project
clocks.c
1 #include "clocks.h"
2 #include "conf_core.h"
3 
4 #if CONF_CORE_CLK_XOSC0_FREQUENCY > 24000000
5  #define CONF_CORE_CLK_XOSC0_IPTAT (3)
6  #define CONF_CORE_CLK_XOSC0_IMULT (6)
7  #define CONF_CORE_CLK_XOSC0_CFDPRESC (0x0)
8 #elif CONF_CORE_CLK_XOSC0_FREQUENCY > 16000000
9  #define CONF_CORE_CLK_XOSC0_IPTAT (3)
10  #define CONF_CORE_CLK_XOSC0_IMULT (5)
11  #define CONF_CORE_CLK_XOSC0_CFDPRESC (0x1)
12 #elif CONF_CORE_CLK_XOSC0_FREQUENCY > 8000000
13  #define CONF_CORE_CLK_XOSC0_IPTAT (3)
14  #define CONF_CORE_CLK_XOSC0_IMULT (4)
15  #define CONF_CORE_CLK_XOSC0_CFDPRESC (0x2)
16 #else
17  #define CONF_CORE_CLK_XOSC0_IPTAT (2)
18  #define CONF_CORE_CLK_XOSC0_IMULT (3)
19  #define CONF_CORE_CLK_XOSC0_CFDPRESC (0x3)
20 #endif
21 
22 #if CONF_CORE_CLK_XOSC1_FREQUENCY > 24000000
23  #define CONF_CORE_CLK_XOSC1_IPTAT (3)
24  #define CONF_CORE_CLK_XOSC1_IMULT (6)
25  #define CONF_CORE_CLK_XOSC1_CFDPRESC (0x0)
26 #elif CONF_CORE_CLK_XOSC1_FREQUENCY > 16000000
27  #define CONF_CORE_CLK_XOSC1_IPTAT (3)
28  #define CONF_CORE_CLK_XOSC1_IMULT (5)
29  #define CONF_CORE_CLK_XOSC1_CFDPRESC (0x1)
30 #elif CONF_CORE_CLK_XOSC1_FREQUENCY > 8000000
31  #define CONF_CORE_CLK_XOSC1_IPTAT (3)
32  #define CONF_CORE_CLK_XOSC1_IMULT (4)
33  #define CONF_CORE_CLK_XOSC1_CFDPRESC (0x2)
34 #else
35  #define CONF_CORE_CLK_XOSC1_IPTAT (2)
36  #define CONF_CORE_CLK_XOSC1_IMULT (3)
37  #define CONF_CORE_CLK_XOSC1_CFDPRESC (0x3)
38 #endif
39 
40 void clock_osc32k_init(void)
41 {
42 #if CONF_CORE_CLK_XOSC32K_ENABLE == 1
43  OSC32KCTRL->XOSC32K.bit.CGM = CONF_CORE_CLK_XOSC32K_CGM;
44  OSC32KCTRL->XOSC32K.bit.WRTLOCK = CONF_CORE_CLK_XOSC32K_WRTLOCK;
45  OSC32KCTRL->XOSC32K.bit.STARTUP = CONF_CORE_CLK_XOSC32K_STARTUP_TIME;
46  OSC32KCTRL->XOSC32K.bit.RUNSTDBY = CONF_CORE_CLK_XOSC32K_RUNSTDBY;
47  OSC32KCTRL->XOSC32K.bit.ONDEMAND = CONF_CORE_CLK_XOSC32K_ONDEMAND;
48  OSC32KCTRL->XOSC32K.bit.EN1K = CONF_CORE_CLK_XOSC32K_EN1K;
49  OSC32KCTRL->XOSC32K.bit.EN32K = CONF_CORE_CLK_XOSC32K_EN32K;
50  OSC32KCTRL->XOSC32K.bit.XTALEN = CONF_CORE_CLK_XOSC32K_XTALEN;
51  OSC32KCTRL->CFDCTRL.bit.CFDPRESC = CONF_CORE_CLK_XOSC32K_CFDPRESC;
52  OSC32KCTRL->CFDCTRL.bit.SWBACK = CONF_CORE_CLK_XOSC32K_SWBACK;
53  OSC32KCTRL->CFDCTRL.bit.CFDEN = CONF_CORE_CLK_XOSC32K_CFDEN;
54 
55 #if CONF_CORE_CLK_XOSC32K_ENABLE == 1 && CONF_CORE_CLK_XOSC32K_ONDEMAND == 0
56  while(OSC32KCTRL->STATUS.bit.XOSC32KRDY == 0);
57 #endif
58 
59 #endif
60 }
61 void clock_osc_init(void)
62 {
63 #if CONF_CORE_CLK_XOSC0_ENABLE == 1
64  CRITICAL_SECTION_ENTER();
65  OSCCTRL->XOSCCTRL[0].bit.XTALEN = CONF_CORE_CLK_XOSC0_XTALEN;
66  OSCCTRL->XOSCCTRL[0].bit.RUNSTDBY = CONF_CORE_CLK_XOSC0_RUNSTDBY;
67  OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = CONF_CORE_CLK_XOSC0_ONDEMAND;
68  OSCCTRL->XOSCCTRL[0].bit.LOWBUFGAIN = CONF_CORE_CLK_XOSC0_LOWBUFGAIN;
69  OSCCTRL->XOSCCTRL[0].bit.IPTAT = CONF_CORE_CLK_XOSC0_IPTAT;
70  OSCCTRL->XOSCCTRL[0].bit.IMULT = CONF_CORE_CLK_XOSC0_IMULT;
71  OSCCTRL->XOSCCTRL[0].bit.ENALC = CONF_CORE_CLK_XOSC0_ENALC;
72  OSCCTRL->XOSCCTRL[0].bit.CFDEN = CONF_CORE_CLK_XOSC0_CFDEN;
73  OSCCTRL->XOSCCTRL[0].bit.CFDPRESC = CONF_CORE_CLK_XOSC0_CFDPRESC;
74  OSCCTRL->XOSCCTRL[0].bit.SWBEN = CONF_CORE_CLK_XOSC0_SWBEN;
75  OSCCTRL->XOSCCTRL[0].bit.STARTUP = CONF_CORE_CLK_XOSC0_STARTUP_TIME;
76  OSCCTRL->XOSCCTRL[0].bit.ENABLE = CONF_CORE_CLK_XOSC0_ENABLE;
77  CRITICAL_SECTION_LEAVE();
78  while(0 == OSCCTRL->STATUS.bit.XOSCRDY0);
79 #endif
80 
81 #if CONF_CORE_CLK_XOSC1_ENABLE == 1
82  CRITICAL_SECTION_ENTER();
83  OSCCTRL->XOSCCTRL[1].bit.XTALEN = CONF_CORE_CLK_XOSC1_XTALEN;
84  OSCCTRL->XOSCCTRL[1].bit.RUNSTDBY = CONF_CORE_CLK_XOSC1_RUNSTDBY;
85  OSCCTRL->XOSCCTRL[1].bit.LOWBUFGAIN = CONF_CORE_CLK_XOSC1_LOWBUFGAIN;
86  OSCCTRL->XOSCCTRL[1].bit.IPTAT = CONF_CORE_CLK_XOSC1_IPTAT;
87  OSCCTRL->XOSCCTRL[1].bit.IMULT = CONF_CORE_CLK_XOSC1_IMULT;
88  OSCCTRL->XOSCCTRL[1].bit.CFDEN = CONF_CORE_CLK_XOSC1_CFDEN;
89  OSCCTRL->XOSCCTRL[1].bit.CFDPRESC = CONF_CORE_CLK_XOSC1_CFDPRESC;
90  OSCCTRL->XOSCCTRL[1].bit.SWBEN = CONF_CORE_CLK_XOSC1_SWBEN;
91  OSCCTRL->XOSCCTRL[1].bit.STARTUP = CONF_CORE_CLK_XOSC1_STARTUP_TIME;
92  OSCCTRL->XOSCCTRL[1].bit.ENABLE = CONF_CORE_CLK_XOSC1_ENABLE;
93  CRITICAL_SECTION_LEAVE();
94  while(0 == OSCCTRL->STATUS.bit.XOSCRDY1);
95 #endif
96 
97 #if CONF_CORE_CLK_XOSC0_ENABLE == 1
98  CRITICAL_SECTION_ENTER();
99 #if CONF_CORE_CLK_XOSC0_ENALC == 1
100  OSCCTRL->XOSCCTRL[0].bit.ENALC = CONF_CORE_CLK_XOSC0_ENALC;
101 #endif
102 
103 #if CONF_CORE_CLK_XOSC0_ONDEMAND == 1
104  OSCCTRL->XOSCCTRL[0].bit.ONDEMAND = CONF_CORE_CLK_XOSC0_ONDEMAND;
105 #endif
106  CRITICAL_SECTION_LEAVE();
107 #endif
108 
109 #if CONF_CORE_CLK_XOSC1_ENABLE == 1
110  CRITICAL_SECTION_ENTER();
111 #if CONF_CORE_CLK_XOSC1_ENALC == 1
112  OSCCTRL->XOSCCTRL[1].bit.ENALC = CONF_CORE_CLK_XOSC1_ENALC;
113 #endif
114 
115 #if CONF_CORE_CLK_XOSC1_ONDEMAND == 1
116  OSCCTRL->XOSCCTRL[1].bit.ONDEMAND = CONF_CORE_CLK_XOSC1_ONDEMAND;
117 #endif
118  CRITICAL_SECTION_LEAVE();
119 #endif
120 }
121 
122 void clock_mclk_init(void)
123 {
124  CRITICAL_SECTION_ENTER();
125  MCLK->CPUDIV.reg = CONF_CORE_MCLK_CPUDIV;
126  CRITICAL_SECTION_LEAVE();
127 }
128 
129 void clock_gclk_init(void)
130 {
131 #if CONF_CORE_GCLK_0_ENABLE == 1
132  CRITICAL_SECTION_ENTER();
133  GCLK->GENCTRL[0].bit.DIV = CONF_CORE_GCLK_0_DIV_VAL;
134  GCLK->GENCTRL[0].bit.DIVSEL = CONF_CORE_GCLK_0_DIVSEL;
135  GCLK->GENCTRL[0].bit.RUNSTDBY = CONF_CORE_GCLK_0_RUN_IN_STANDBY;
136  GCLK->GENCTRL[0].bit.OE = CONF_CORE_GCLK_0_OUTPUT_ENABLE;
137  GCLK->GENCTRL[0].bit.OOV = CONF_CORE_GCLK_0_DIVSEL;
138  GCLK->GENCTRL[0].bit.IDC = CONF_CORE_GCLK_0_IDC;
139  GCLK->GENCTRL[0].bit.GENEN = CONF_CORE_GCLK_0_ENABLE;
140  GCLK->GENCTRL[0].bit.SRC = CONF_CORE_GCLK_0_CLOCK_SOURCE;
141  CRITICAL_SECTION_LEAVE();
142 #endif
143 #if CONF_CORE_GCLK_1_ENABLE == 1
144  CRITICAL_SECTION_ENTER();
145  GCLK->GENCTRL[1].bit.DIV = CONF_CORE_GCLK_1_DIV_VAL;
146  GCLK->GENCTRL[1].bit.DIVSEL = CONF_CORE_GCLK_1_DIVSEL;
147  GCLK->GENCTRL[1].bit.RUNSTDBY = CONF_CORE_GCLK_1_RUN_IN_STANDBY;
148  GCLK->GENCTRL[1].bit.OE = CONF_CORE_GCLK_1_OUTPUT_ENABLE;
149  GCLK->GENCTRL[1].bit.OOV = CONF_CORE_GCLK_1_DIVSEL;
150  GCLK->GENCTRL[1].bit.IDC = CONF_CORE_GCLK_1_IDC;
151  GCLK->GENCTRL[1].bit.GENEN = CONF_CORE_GCLK_1_ENABLE;
152  GCLK->GENCTRL[1].bit.SRC = CONF_CORE_GCLK_1_CLOCK_SOURCE;
153  CRITICAL_SECTION_LEAVE();
154 #endif
155 #if CONF_CORE_GCLK_2_ENABLE == 1
156  CRITICAL_SECTION_ENTER();
157  GCLK->GENCTRL[2].bit.DIV = CONF_CORE_GCLK_2_DIV_VAL;
158  GCLK->GENCTRL[2].bit.DIVSEL = CONF_CORE_GCLK_2_DIVSEL;
159  GCLK->GENCTRL[2].bit.RUNSTDBY = CONF_CORE_GCLK_2_RUN_IN_STANDBY;
160  GCLK->GENCTRL[2].bit.OE = CONF_CORE_GCLK_2_OUTPUT_ENABLE;
161  GCLK->GENCTRL[2].bit.OOV = CONF_CORE_GCLK_2_DIVSEL;
162  GCLK->GENCTRL[2].bit.IDC = CONF_CORE_GCLK_2_IDC;
163  GCLK->GENCTRL[2].bit.GENEN = CONF_CORE_GCLK_2_ENABLE;
164  GCLK->GENCTRL[2].bit.SRC = CONF_CORE_GCLK_2_CLOCK_SOURCE;
165  CRITICAL_SECTION_LEAVE();
166 #endif
167 #if CONF_CORE_GCLK_3_ENABLE == 1
168  CRITICAL_SECTION_ENTER();
169  GCLK->GENCTRL[3].bit.DIV = CONF_CORE_GCLK_3_DIV_VAL;
170  GCLK->GENCTRL[3].bit.DIVSEL = CONF_CORE_GCLK_3_DIVSEL;
171  GCLK->GENCTRL[3].bit.RUNSTDBY = CONF_CORE_GCLK_3_RUN_IN_STANDBY;
172  GCLK->GENCTRL[3].bit.OE = CONF_CORE_GCLK_3_OUTPUT_ENABLE;
173  GCLK->GENCTRL[3].bit.OOV = CONF_CORE_GCLK_3_DIVSEL;
174  GCLK->GENCTRL[3].bit.IDC = CONF_CORE_GCLK_3_IDC;
175  GCLK->GENCTRL[3].bit.GENEN = CONF_CORE_GCLK_3_ENABLE;
176  GCLK->GENCTRL[3].bit.SRC = CONF_CORE_GCLK_3_CLOCK_SOURCE;
177  CRITICAL_SECTION_LEAVE();
178 #endif
179 #if CONF_CORE_GCLK_4_ENABLE == 1
180  CRITICAL_SECTION_ENTER();
181  GCLK->GENCTRL[4].bit.DIV = CONF_CORE_GCLK_4_DIV_VAL;
182  GCLK->GENCTRL[4].bit.DIVSEL = CONF_CORE_GCLK_4_DIVSEL;
183  GCLK->GENCTRL[4].bit.RUNSTDBY = CONF_CORE_GCLK_4_RUN_IN_STANDBY;
184  GCLK->GENCTRL[4].bit.OE = CONF_CORE_GCLK_4_OUTPUT_ENABLE;
185  GCLK->GENCTRL[4].bit.OOV = CONF_CORE_GCLK_4_DIVSEL;
186  GCLK->GENCTRL[4].bit.IDC = CONF_CORE_GCLK_4_IDC;
187  GCLK->GENCTRL[4].bit.GENEN = CONF_CORE_GCLK_4_ENABLE;
188  GCLK->GENCTRL[4].bit.SRC = CONF_CORE_GCLK_4_CLOCK_SOURCE;
189  CRITICAL_SECTION_LEAVE();
190 #endif
191 #if CONF_CORE_GCLK_5_ENABLE == 1
192  CRITICAL_SECTION_ENTER();
193  GCLK->GENCTRL[5].bit.DIV = CONF_CORE_GCLK_5_DIV_VAL;
194  GCLK->GENCTRL[5].bit.DIVSEL = CONF_CORE_GCLK_5_DIVSEL;
195  GCLK->GENCTRL[5].bit.RUNSTDBY = CONF_CORE_GCLK_5_RUN_IN_STANDBY;
196  GCLK->GENCTRL[5].bit.OE = CONF_CORE_GCLK_5_OUTPUT_ENABLE;
197  GCLK->GENCTRL[5].bit.OOV = CONF_CORE_GCLK_5_DIVSEL;
198  GCLK->GENCTRL[5].bit.IDC = CONF_CORE_GCLK_5_IDC;
199  GCLK->GENCTRL[5].bit.GENEN = CONF_CORE_GCLK_5_ENABLE;
200  GCLK->GENCTRL[5].bit.SRC = CONF_CORE_GCLK_5_CLOCK_SOURCE;
201  CRITICAL_SECTION_LEAVE();
202 #endif
203 #if CONF_CORE_GCLK_6_ENABLE == 1
204  CRITICAL_SECTION_ENTER();
205  GCLK->GENCTRL[6].bit.DIV = CONF_CORE_GCLK_6_DIV_VAL;
206  GCLK->GENCTRL[6].bit.DIVSEL = CONF_CORE_GCLK_6_DIVSEL;
207  GCLK->GENCTRL[6].bit.RUNSTDBY = CONF_CORE_GCLK_6_RUN_IN_STANDBY;
208  GCLK->GENCTRL[6].bit.OE = CONF_CORE_GCLK_6_OUTPUT_ENABLE;
209  GCLK->GENCTRL[6].bit.OOV = CONF_CORE_GCLK_6_DIVSEL;
210  GCLK->GENCTRL[6].bit.IDC = CONF_CORE_GCLK_6_IDC;
211  GCLK->GENCTRL[6].bit.GENEN = CONF_CORE_GCLK_6_ENABLE;
212  GCLK->GENCTRL[6].bit.SRC = CONF_CORE_GCLK_6_CLOCK_SOURCE;
213  CRITICAL_SECTION_LEAVE();
214 #endif
215 #if CONF_CORE_GCLK_7_ENABLE == 1
216  CRITICAL_SECTION_ENTER();
217  GCLK->GENCTRL[7].bit.DIV = CONF_CORE_GCLK_7_DIV_VAL;
218  GCLK->GENCTRL[7].bit.DIVSEL = CONF_CORE_GCLK_7_DIVSEL;
219  GCLK->GENCTRL[7].bit.RUNSTDBY = CONF_CORE_GCLK_7_RUN_IN_STANDBY;
220  GCLK->GENCTRL[7].bit.OE = CONF_CORE_GCLK_7_OUTPUT_ENABLE;
221  GCLK->GENCTRL[7].bit.OOV = CONF_CORE_GCLK_7_DIVSEL;
222  GCLK->GENCTRL[7].bit.IDC = CONF_CORE_GCLK_7_IDC;
223  GCLK->GENCTRL[7].bit.GENEN = CONF_CORE_GCLK_7_ENABLE;
224  GCLK->GENCTRL[7].bit.SRC = CONF_CORE_GCLK_7_CLOCK_SOURCE;
225  CRITICAL_SECTION_LEAVE();
226 #endif
227 #if CONF_CORE_GCLK_8_ENABLE == 1
228  CRITICAL_SECTION_ENTER();
229  GCLK->GENCTRL[8].bit.DIV = CONF_CORE_GCLK_8_DIV_VAL;
230  GCLK->GENCTRL[8].bit.DIVSEL = CONF_CORE_GCLK_8_DIVSEL;
231  GCLK->GENCTRL[8].bit.RUNSTDBY = CONF_CORE_GCLK_8_RUN_IN_STANDBY;
232  GCLK->GENCTRL[8].bit.OE = CONF_CORE_GCLK_8_OUTPUT_ENABLE;
233  GCLK->GENCTRL[8].bit.OOV = CONF_CORE_GCLK_8_DIVSEL;
234  GCLK->GENCTRL[8].bit.IDC = CONF_CORE_GCLK_8_IDC;
235  GCLK->GENCTRL[8].bit.GENEN = CONF_CORE_GCLK_8_ENABLE;
236  GCLK->GENCTRL[8].bit.SRC = CONF_CORE_GCLK_8_CLOCK_SOURCE;
237  CRITICAL_SECTION_LEAVE();
238 #endif
239 #if CONF_CORE_GCLK_9_ENABLE == 1
240  CRITICAL_SECTION_ENTER();
241  GCLK->GENCTRL[9].bit.DIV = CONF_CORE_GCLK_9_DIV_VAL;
242  GCLK->GENCTRL[9].bit.DIVSEL = CONF_CORE_GCLK_9_DIVSEL;
243  GCLK->GENCTRL[9].bit.RUNSTDBY = CONF_CORE_GCLK_9_RUN_IN_STANDBY;
244  GCLK->GENCTRL[9].bit.OE = CONF_CORE_GCLK_9_OUTPUT_ENABLE;
245  GCLK->GENCTRL[9].bit.OOV = CONF_CORE_GCLK_9_DIVSEL;
246  GCLK->GENCTRL[9].bit.IDC = CONF_CORE_GCLK_9_IDC;
247  GCLK->GENCTRL[9].bit.GENEN = CONF_CORE_GCLK_9_ENABLE;
248  GCLK->GENCTRL[9].bit.SRC = CONF_CORE_GCLK_9_CLOCK_SOURCE;
249  CRITICAL_SECTION_LEAVE();
250 #endif
251 #if CONF_CORE_GCLK_10_ENABLE == 1
252  CRITICAL_SECTION_ENTER();
253  GCLK->GENCTRL[10].bit.DIV = CONF_CORE_GCLK_10_DIV_VAL;
254  GCLK->GENCTRL[10].bit.DIVSEL = CONF_CORE_GCLK_10_DIVSEL;
255  GCLK->GENCTRL[10].bit.RUNSTDBY = CONF_CORE_GCLK_10_RUN_IN_STANDBY;
256  GCLK->GENCTRL[10].bit.OE = CONF_CORE_GCLK_10_OUTPUT_ENABLE;
257  GCLK->GENCTRL[10].bit.OOV = CONF_CORE_GCLK_10_DIVSEL;
258  GCLK->GENCTRL[10].bit.IDC = CONF_CORE_GCLK_10_IDC;
259  GCLK->GENCTRL[10].bit.GENEN = CONF_CORE_GCLK_10_ENABLE;
260  GCLK->GENCTRL[10].bit.SRC = CONF_CORE_GCLK_10_CLOCK_SOURCE;
261  CRITICAL_SECTION_LEAVE();
262 #endif
263 #if CONF_CORE_GCLK_11_ENABLE == 1
264  CRITICAL_SECTION_ENTER();
265  GCLK->GENCTRL[11].bit.DIV = CONF_CORE_GCLK_11_DIV_VAL;
266  GCLK->GENCTRL[11].bit.DIVSEL = CONF_CORE_GCLK_11_DIVSEL;
267  GCLK->GENCTRL[11].bit.RUNSTDBY = CONF_CORE_GCLK_11_RUN_IN_STANDBY;
268  GCLK->GENCTRL[11].bit.OE = CONF_CORE_GCLK_11_OUTPUT_ENABLE;
269  GCLK->GENCTRL[11].bit.OOV = CONF_CORE_GCLK_11_DIVSEL;
270  GCLK->GENCTRL[11].bit.IDC = CONF_CORE_GCLK_11_IDC;
271  GCLK->GENCTRL[11].bit.GENEN = CONF_CORE_GCLK_11_ENABLE;
272  GCLK->GENCTRL[11].bit.SRC = CONF_CORE_GCLK_11_CLOCK_SOURCE;
273  CRITICAL_SECTION_LEAVE();
274 #endif
275 }
276 
277 void clock_dpll_init(void)
278 {
279 #if CONF_CORE_CLK_DPLL0_ENABLE == 1
280 #if CONF_CORE_CLK_DPLL0_REFCLK == 0
281  CRITICAL_SECTION_ENTER();
282  GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL0].bit.GEN =
283  GCLK_PCHCTRL_GEN(CONF_CORE_CLK_DPLL0_GCLK_SRC);
284  GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL0].bit.CHEN =
285  CONF_CORE_CLK_DPLL0_ENABLE;
286  CRITICAL_SECTION_LEAVE();
287 #endif
288 
289  CRITICAL_SECTION_ENTER();
290  // write dpll ratio
291  OSCCTRL->Dpll[0].DPLLRATIO.bit.LDRFRAC = CONF_CORE_CLK_DPLL0_LDRFRAC_VAL;
292  OSCCTRL->Dpll[0].DPLLRATIO.bit.LDR = CONF_CORE_CLK_DPLL0_LDR_VAL;
293 
294  // write dpll ctrlb
295  OSCCTRL->Dpll[0].DPLLCTRLB.bit.DIV = CONF_CORE_CLK_DPLL0_DIV_VAL;
296  OSCCTRL->Dpll[0].DPLLCTRLB.bit.DCOEN = CONF_CORE_CLK_DPLL0_DCOEN;
297  OSCCTRL->Dpll[0].DPLLCTRLB.bit.DCOFILTER = CONF_CORE_CLK_DPLL0_DCOFILTER;
298  OSCCTRL->Dpll[0].DPLLCTRLB.bit.LBYPASS = CONF_CORE_CLK_DPLL0_LBYPASS;
299  OSCCTRL->Dpll[0].DPLLCTRLB.bit.LTIME = CONF_CORE_CLK_DPLL0_LTIME;
300  OSCCTRL->Dpll[0].DPLLCTRLB.bit.REFCLK = CONF_CORE_CLK_DPLL0_REFCLK;
301  OSCCTRL->Dpll[0].DPLLCTRLB.bit.WUF = CONF_CORE_CLK_DPLL0_WUF;
302  OSCCTRL->Dpll[0].DPLLCTRLB.bit.FILTER = CONF_CORE_CLK_DPLL0_FILTER;
303  CRITICAL_SECTION_LEAVE();
304 
305  CRITICAL_SECTION_ENTER();
306  OSCCTRL->Dpll[0].DPLLCTRLA.reg = 0;
307  OSCCTRL->Dpll[0].DPLLCTRLA.bit.RUNSTDBY = CONF_CORE_CLK_DPLL0_RUNSTDBY;
308  OSCCTRL->Dpll[0].DPLLCTRLA.bit.ENABLE = CONF_CORE_CLK_DPLL0_ENABLE;
309  CRITICAL_SECTION_LEAVE();
310 #endif
311 
312 #if CONF_CORE_CLK_DPLL1_ENABLE == 1
313 #if CONF_CORE_CLK_DPLL0_REFCLK == 0
314  CRITICAL_SECTION_ENTER();
315  GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL1].bit.GEN =
316  GCLK_PCHCTRL_GEN(CONF_CORE_CLK_DPLL1_GCLK_SRC);
317  GCLK->PCHCTRL[OSCCTRL_GCLK_ID_FDPLL1].bit.CHEN =
318  CONF_CORE_CLK_DPLL1_ENABLE;
319  CRITICAL_SECTION_LEAVE();
320 #endif
321 
322  CRITICAL_SECTION_ENTER();
323  // write dpll ratio
324  OSCCTRL->Dpll[1].DPLLRATIO.bit.LDRFRAC = CONF_CORE_CLK_DPLL1_LDRFRAC_VAL;
325  OSCCTRL->Dpll[1].DPLLRATIO.bit.LDR = CONF_CORE_CLK_DPLL1_LDR_VAL;
326  // write dpll ctrlb
327  OSCCTRL->Dpll[1].DPLLCTRLB.bit.DIV = CONF_CORE_CLK_DPLL1_DIV_VAL;
328  OSCCTRL->Dpll[1].DPLLCTRLB.bit.DCOEN = CONF_CORE_CLK_DPLL1_DCOEN;
329  OSCCTRL->Dpll[1].DPLLCTRLB.bit.DCOFILTER = CONF_CORE_CLK_DPLL1_DCOFILTER;
330  OSCCTRL->Dpll[1].DPLLCTRLB.bit.LBYPASS = CONF_CORE_CLK_DPLL1_LBYPASS;
331  OSCCTRL->Dpll[1].DPLLCTRLB.bit.LTIME = CONF_CORE_CLK_DPLL1_LTIME;
332  OSCCTRL->Dpll[1].DPLLCTRLB.bit.REFCLK = CONF_CORE_CLK_DPLL1_REFCLK;
333  OSCCTRL->Dpll[1].DPLLCTRLB.bit.WUF = CONF_CORE_CLK_DPLL1_WUF;
334  OSCCTRL->Dpll[1].DPLLCTRLB.bit.FILTER = CONF_CORE_CLK_DPLL1_FILTER;
335  CRITICAL_SECTION_LEAVE();
336 
337  CRITICAL_SECTION_ENTER();
338  OSCCTRL->Dpll[1].DPLLCTRLA.reg = 0;
339  OSCCTRL->Dpll[1].DPLLCTRLA.bit.RUNSTDBY = CONF_CORE_CLK_DPLL1_RUNSTDBY;
340  OSCCTRL->Dpll[1].DPLLCTRLA.bit.ENABLE = CONF_CORE_CLK_DPLL1_ENABLE;
341  CRITICAL_SECTION_LEAVE();
342 #endif
343 
344 #if CONF_CORE_CLK_DPLL0_ENABLE == 1
345  while(!(OSCCTRL->Dpll[0].DPLLSTATUS.bit.LOCK || OSCCTRL->Dpll[0].DPLLSTATUS.bit.CLKRDY));
346  CRITICAL_SECTION_ENTER();
347 #if CONF_CORE_CLK_DPLL0_ONDEMAND == 1
348  OSCCTRL->Dpll[0].DPLLCTRLA.bit.ONDEMAND = CONF_CORE_CLK_DPLL0_ONDEMAND;
349 #endif
350  CRITICAL_SECTION_LEAVE();
351 #endif
352 
353 #if CONF_CORE_CLK_DPLL1_ENABLE == 1
354  while(!(OSCCTRL->Dpll[1].DPLLSTATUS.bit.LOCK || OSCCTRL->Dpll[1].DPLLSTATUS.bit.CLKRDY));
355  CRITICAL_SECTION_ENTER();
356 #if CONF_CORE_CLK_DPLL1_ONDEMAND == 1
357  OSCCTRL->Dpll[1].DPLLCTRLA.bit.ONDEMAND = CONF_CORE_CLK_DPLL1_ONDEMAND;
358 #endif
359  CRITICAL_SECTION_LEAVE();
360 #endif
361 }
362 
363 void clock_dfll_init(void)
364 {
365 #if CONF_CORE_CLK_DFLL_ENABLE
366  CRITICAL_SECTION_ENTER();
367  GCLK->GENCTRL[0].bit.SRC = GCLK_GENCTRL_SRC_OSCULP32K;
368  CRITICAL_SECTION_LEAVE();
369  while(GCLK->SYNCBUSY.bit.GENCTRL0);
370 
371  CRITICAL_SECTION_ENTER();
372  // reset stuff
373  OSCCTRL->DFLLCTRLA.reg = 0;
374  CRITICAL_SECTION_LEAVE();
375 #if CONF_CORE_CLK_DFLL_USBCRM != 1 && CONF_CORE_CLK_DFLL_MODE != 0
376  CRITICAL_SECTION_ENTER();
377  // reset stuff
378  GCLK->PCHCTRL[OSCCTRL_GCLK_ID_DFLL48].bit.GEN =
379  GCLK_PCHCTRL_GEN(CONF_CORE_CLK_DFLL_GCLK_SRC);
380  GCLK->PCHCTRL[OSCCTRL_GCLK_ID_DFLL48].bit.EN = CONF_CORE_CLK_DFLL_ENABLE;
381  CRITICAL_SECTION_LEAVE();
382 #endif
383 
384  CRITICAL_SECTION_ENTER();
385  // configure clock multiplier stuff
386  OSCCTRL->DFLLMUL.bit.MUL = CONF_CORE_CLK_DFLL_MUL_VAL;
387  OSCCTRL->DFLLMUL.bit.CSTEP = CONF_CORE_CLK_DFLL_CSTEP_VAL;
388  OSCCTRL->DFLLMUL.bit.FSTEP = CONF_CORE_CLK_DFLL_FSTEP_VAL;
389  CRITICAL_SECTION_LEAVE();
390  while(OSCCTRL->DFLLSYNC.bit.DFLLMUL);
391 
392  CRITICAL_SECTION_ENTER();
393  // reset dfll ctrlb
394  OSCCTRL->DFLLCTRLB.reg = 0;
395  CRITICAL_SECTION_LEAVE();
396  // wait for ctrlb sync
397  while(OSCCTRL->DFLLSYNC.bit.DFLLCTRLB);
398 
399  CRITICAL_SECTION_ENTER();
400  OSCCTRL->DFLLCTRLA.bit.RUNSTDBY = CONF_CORE_CLK_DFLL_RUNSTDBY;
401  OSCCTRL->DFLLCTRLA.bit.ENABLE = CONF_CORE_CLK_DFLL_ENABLE;
402  CRITICAL_SECTION_LEAVE();
403  while(OSCCTRL->DFLLSYNC.bit.ENABLE);
404 #if CONF_CORE_CLK_DFLL_OVERWRITE_CAL == 1
405  CRITICAL_SECTION_ENTER();
406  // set calib for dfll48m
407  OSCCTRL->DFLLVAL.bit.COARSE = CONF_CORE_CLK_DFLL_COARSE_VAL;
408  OSCCTRL->DFLLVAL.bit.FINE = CONF_CORE_CLK_DFLL_FINE_VAL;
409  OSCCTRL->DFLLVAL.bit.DIFF = CONF_CORE_CLK_DFLL_DIFF_VAL;
410  CRITICAL_SECTION_LEAVE();
411 #endif
412 
413  CRITICAL_SECTION_ENTER();
414  // write dfll val
415  // rewriting this for some reason?
416  OSCCTRL->DFLLVAL.reg = OSCCTRL->DFLLVAL.reg;
417  CRITICAL_SECTION_LEAVE();
418  // let dfll val sync
419  while(OSCCTRL->DFLLSYNC.bit.DFLLVAL);
420 
421  CRITICAL_SECTION_ENTER();
422  // write dfll ctrlb
423  OSCCTRL->DFLLCTRLB.bit.WAITLOCK = CONF_CORE_CLK_DFLL_WAITLOCK;
424  OSCCTRL->DFLLCTRLB.bit.BPLCKC = CONF_CORE_CLK_DFLL_BPLKC;
425  OSCCTRL->DFLLCTRLB.bit.QLDIS = CONF_CORE_CLK_DFLL_QLDIS;
426  OSCCTRL->DFLLCTRLB.bit.CCDIS = CONF_CORE_CLK_DFLL_CCDIS;
427  OSCCTRL->DFLLCTRLB.bit.USBCRM = CONF_CORE_CLK_DFLL_USBCRM;
428  OSCCTRL->DFLLCTRLB.bit.LLAW = CONF_CORE_CLK_DFLL_LLAW;
429  OSCCTRL->DFLLCTRLB.bit.STABLE = CONF_CORE_CLK_DFLL_STABLE_FCALIB;
430  OSCCTRL->DFLLCTRLB.bit.MODE = CONF_CORE_CLK_DFLL_MODE;
431  CRITICAL_SECTION_LEAVE();
432  while(OSCCTRL->DFLLSYNC.bit.DFLLCTRLB);
433 
434  if (OSCCTRL->DFLLCTRLB.bit.MODE)
435  {
436  volatile uint32_t status_mask = OSCCTRL_STATUS_DFLLRDY | OSCCTRL_STATUS_DFLLLCKC;
437  while((OSCCTRL->STATUS.reg & status_mask) != status_mask);
438  }
439  else
440  {
441  while(!OSCCTRL->STATUS.bit.DFLLRDY);
442  }
443 
444 #if CONF_CORE_CLK_DFLL_ONDEMAND == 1
445  CRITICAL_SECTION_ENTER();
446  OSCCTRL->DFLLCTRLA.bit.ONDEMAND = CONF_CORE_CLK_DFLL_ONDEMAND;
447  CRITICAL_SECTION_LEAVE();
448 #endif
449 
450  while(GCLK->SYNCBUSY.reg);
451  CRITICAL_SECTION_ENTER();
452  // reset gclk 0
453  GCLK->GENCTRL[0].bit.SRC = CONF_CORE_GCLK_0_CLOCK_SOURCE;
454  CRITICAL_SECTION_LEAVE();
455 #endif
456 }
CONF_CORE_CLK_DFLL_WAITLOCK
#define CONF_CORE_CLK_DFLL_WAITLOCK
This bit controls the DFLL output clock, depending on the lock status:
Definition: conf_core.h:414
CONF_CORE_CLK_XOSC1_ONDEMAND
#define CONF_CORE_CLK_XOSC1_ONDEMAND
The On Demand operation mode allows the oscillator XOSC1 to be enabled or disabled,...
Definition: conf_core.h:207
CONF_CORE_CLK_XOSC0_CFDEN
#define CONF_CORE_CLK_XOSC0_CFDEN
This bit controls the XOSC0 clock failure detector:
Definition: conf_core.h:128
CONF_CORE_CLK_DPLL1_FILTER
#define CONF_CORE_CLK_DPLL1_FILTER
Definition: conf_core.h:535
CONF_CORE_CLK_XOSC1_SWBEN
#define CONF_CORE_CLK_XOSC1_SWBEN
This bit controls the XOSC1 output clock switch back to the external clock or crystal oscillator in c...
Definition: conf_core.h:241
CONF_CORE_CLK_XOSC0_ENALC
#define CONF_CORE_CLK_XOSC0_ENALC
This bit controls the XOSC0 automatic loop control:
Definition: conf_core.h:120
CONF_CORE_CLK_XOSC32K_EN32K
#define CONF_CORE_CLK_XOSC32K_EN32K
Definition: conf_core.h:336
CONF_CORE_CLK_DPLL0_FILTER
#define CONF_CORE_CLK_DPLL0_FILTER
Definition: conf_core.h:490
CONF_CORE_CLK_XOSC32K_CGM
#define CONF_CORE_CLK_XOSC32K_CGM
These bits control the gain of the external crstal oscillator.
Definition: conf_core.h:293
CONF_CORE_MCLK_CPUDIV
#define CONF_CORE_MCLK_CPUDIV
Define the master clock divisor.
Definition: conf_core.h:38
CONF_CORE_CLK_XOSC0_XTALEN
#define CONF_CORE_CLK_XOSC0_XTALEN
This bit controls the connections between the I/O pads and the external clock or crystal oscillator X...
Definition: conf_core.h:84
CONF_CORE_CLK_XOSC1_RUNSTDBY
#define CONF_CORE_CLK_XOSC1_RUNSTDBY
This bit controls how the XOSC1 behaves during standby sleep mode:
Definition: conf_core.h:198
CONF_CORE_CLK_XOSC1_CFDEN
#define CONF_CORE_CLK_XOSC1_CFDEN
This bit controls the XOSC1 clock failure detector:
Definition: conf_core.h:232
CONF_CORE_CLK_XOSC32K_CFDEN
#define CONF_CORE_CLK_XOSC32K_CFDEN
This bit selects the Clock Failulre Detector state.
Definition: conf_core.h:360
MCLK
#define MCLK
(MCLK) APB Base Address
Definition: same54n19a.h:914
CONF_CORE_CLK_XOSC1_ENABLE
#define CONF_CORE_CLK_XOSC1_ENABLE
Enables or Disables the XOSC1 Clock.
Definition: conf_core.h:180
CONF_CORE_CLK_XOSC1_ENALC
#define CONF_CORE_CLK_XOSC1_ENALC
This bit controls the XOSC1 automatic loop control:
Definition: conf_core.h:224
CONF_CORE_CLK_XOSC0_SWBEN
#define CONF_CORE_CLK_XOSC0_SWBEN
This bit controls the XOSC0 output clock switch back to the external clock or crystal oscillator in c...
Definition: conf_core.h:137
CONF_CORE_CLK_XOSC0_ENABLE
#define CONF_CORE_CLK_XOSC0_ENABLE
Enables or Disables the XOSC0 Clock.
Definition: conf_core.h:76
CONF_CORE_CLK_XOSC1_XTALEN
#define CONF_CORE_CLK_XOSC1_XTALEN
This bit controls the connections between the I/O pads and the external clock or crystal oscillator X...
Definition: conf_core.h:188
CONF_CORE_CLK_XOSC32K_XTALEN
#define CONF_CORE_CLK_XOSC32K_XTALEN
This bit controls the connections between the I/O pads and the external clock or crystal oscillator.
Definition: conf_core.h:344
OSC32KCTRL
#define OSC32KCTRL
(OSC32KCTRL) APB Base Address
Definition: same54n19a.h:929
CONF_CORE_CLK_XOSC32K_STARTUP_TIME
#define CONF_CORE_CLK_XOSC32K_STARTUP_TIME
These bits select the startup time for the oscillator.
Definition: conf_core.h:306
CONF_CORE_CLK_DFLL_ONDEMAND
#define CONF_CORE_CLK_DFLL_ONDEMAND
Enables or Disables on-demand operation.
Definition: conf_core.h:398
CONF_CORE_CLK_XOSC32K_RUNSTDBY
#define CONF_CORE_CLK_XOSC32K_RUNSTDBY
This bit controls how XOSC32K behaves during standby sleep mode.
Definition: conf_core.h:322
CONF_CORE_CLK_XOSC0_STARTUP_TIME
#define CONF_CORE_CLK_XOSC0_STARTUP_TIME
These bits select start-up time for XOSC0 according to the table below:
Definition: conf_core.h:159
CONF_CORE_CLK_XOSC32K_ONDEMAND
#define CONF_CORE_CLK_XOSC32K_ONDEMAND
This bit controls how XOSC32K behaves when a peripheral clock request is detected.
Definition: conf_core.h:314
OSCCTRL
#define OSCCTRL
(OSCCTRL) APB Base Address
Definition: same54n19a.h:925
CONF_CORE_CLK_XOSC32K_WRTLOCK
#define CONF_CORE_CLK_XOSC32K_WRTLOCK
This bit locks the XOSC32K register for future writes, effectively freezing the XOSC32K configuration...
Definition: conf_core.h:376
CONF_CORE_CLK_XOSC32K_CFDPRESC
#define CONF_CORE_CLK_XOSC32K_CFDPRESC
This bit selects the prescaler for the CLock Failure Detector:
Definition: conf_core.h:352
CONF_CORE_CLK_XOSC0_RUNSTDBY
#define CONF_CORE_CLK_XOSC0_RUNSTDBY
This bit controls how the XOSC0 behaves during standby sleep mode:
Definition: conf_core.h:94
CONF_CORE_CLK_XOSC1_STARTUP_TIME
#define CONF_CORE_CLK_XOSC1_STARTUP_TIME
These bits select start-up time for XOSC1 according to the table below:
Definition: conf_core.h:263
CONF_CORE_CLK_XOSC32K_EN1K
#define CONF_CORE_CLK_XOSC32K_EN1K
Definition: conf_core.h:329
CONF_CORE_CLK_DFLL_RUNSTDBY
#define CONF_CORE_CLK_DFLL_RUNSTDBY
Enables or Disables run-in-standby operation.
Definition: conf_core.h:406
conf_core.h
CONF_CORE_CLK_XOSC0_ONDEMAND
#define CONF_CORE_CLK_XOSC0_ONDEMAND
The On Demand operation mode allows the oscillator XOSC0 to be enabled or disabled,...
Definition: conf_core.h:103
CONF_CORE_CLK_XOSC32K_SWBACK
#define CONF_CORE_CLK_XOSC32K_SWBACK
This bit controls the XOSC32K output switch back to the external clock or crystal oscillator in case ...
Definition: conf_core.h:368
CONF_CORE_CLK_XOSC0_LOWBUFGAIN
#define CONF_CORE_CLK_XOSC0_LOWBUFGAIN
The default value of LOWBUFGAIN=0 should be used to allow operating with a low amplitude oscillator....
Definition: conf_core.h:112
CONF_CORE_CLK_DFLL_ENABLE
#define CONF_CORE_CLK_DFLL_ENABLE
Enables or Disables the DFLL48M Clock.
Definition: conf_core.h:390
GCLK
#define GCLK
(GCLK) APB Base Address
Definition: same54n19a.h:894
CONF_CORE_CLK_DFLL_GCLK_SRC
#define CONF_CORE_CLK_DFLL_GCLK_SRC
GCLK Source used to generate DFLL48M.
Definition: conf_core.h:444
CONF_CORE_CLK_XOSC1_LOWBUFGAIN
#define CONF_CORE_CLK_XOSC1_LOWBUFGAIN
The default value of LOWBUFGAIN=0 should be used to allow operating with a low amplitude oscillator....
Definition: conf_core.h:216
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