doc/html/can1_8h_source.html

#ifndef _SAME54_CAN1_INSTANCE_

#define _SAME54_CAN1_INSTANCE_


/* ========== Register definition for CAN1 peripheral ========== */

#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

#define REG_CAN1_CREL              (0x42000400)

#define REG_CAN1_ENDN              (0x42000404)

#define REG_CAN1_MRCFG             (0x42000408)

#define REG_CAN1_DBTP              (0x4200040C)

#define REG_CAN1_TEST              (0x42000410)

#define REG_CAN1_RWD               (0x42000414)

#define REG_CAN1_CCCR              (0x42000418)

#define REG_CAN1_NBTP              (0x4200041C)

#define REG_CAN1_TSCC              (0x42000420)

#define REG_CAN1_TSCV              (0x42000424)

#define REG_CAN1_TOCC              (0x42000428)

#define REG_CAN1_TOCV              (0x4200042C)

#define REG_CAN1_ECR               (0x42000440)

#define REG_CAN1_PSR               (0x42000444)

#define REG_CAN1_TDCR              (0x42000448)

#define REG_CAN1_IR                (0x42000450)

#define REG_CAN1_IE                (0x42000454)

#define REG_CAN1_ILS               (0x42000458)

#define REG_CAN1_ILE               (0x4200045C)

#define REG_CAN1_GFC               (0x42000480)

#define REG_CAN1_SIDFC             (0x42000484)

#define REG_CAN1_XIDFC             (0x42000488)

#define REG_CAN1_XIDAM             (0x42000490)

#define REG_CAN1_HPMS              (0x42000494)

#define REG_CAN1_NDAT1             (0x42000498)

#define REG_CAN1_NDAT2             (0x4200049C)

#define REG_CAN1_RXF0C             (0x420004A0)

#define REG_CAN1_RXF0S             (0x420004A4)

#define REG_CAN1_RXF0A             (0x420004A8)

#define REG_CAN1_RXBC              (0x420004AC)

#define REG_CAN1_RXF1C             (0x420004B0)

#define REG_CAN1_RXF1S             (0x420004B4)

#define REG_CAN1_RXF1A             (0x420004B8)

#define REG_CAN1_RXESC             (0x420004BC)

#define REG_CAN1_TXBC              (0x420004C0)

#define REG_CAN1_TXFQS             (0x420004C4)

#define REG_CAN1_TXESC             (0x420004C8)

#define REG_CAN1_TXBRP             (0x420004CC)

#define REG_CAN1_TXBAR             (0x420004D0)

#define REG_CAN1_TXBCR             (0x420004D4)

#define REG_CAN1_TXBTO             (0x420004D8)

#define REG_CAN1_TXBCF             (0x420004DC)

#define REG_CAN1_TXBTIE            (0x420004E0)

#define REG_CAN1_TXBCIE            (0x420004E4)

#define REG_CAN1_TXEFC             (0x420004F0)

#define REG_CAN1_TXEFS             (0x420004F4)

#define REG_CAN1_TXEFA             (0x420004F8)

#else

#define REG_CAN1_CREL              (*(RoReg  *)0x42000400UL)

#define REG_CAN1_ENDN              (*(RoReg  *)0x42000404UL)

#define REG_CAN1_MRCFG             (*(RwReg  *)0x42000408UL)

#define REG_CAN1_DBTP              (*(RwReg  *)0x4200040CUL)

#define REG_CAN1_TEST              (*(RwReg  *)0x42000410UL)

#define REG_CAN1_RWD               (*(RwReg  *)0x42000414UL)

#define REG_CAN1_CCCR              (*(RwReg  *)0x42000418UL)

#define REG_CAN1_NBTP              (*(RwReg  *)0x4200041CUL)

#define REG_CAN1_TSCC              (*(RwReg  *)0x42000420UL)

#define REG_CAN1_TSCV              (*(RoReg  *)0x42000424UL)

#define REG_CAN1_TOCC              (*(RwReg  *)0x42000428UL)

#define REG_CAN1_TOCV              (*(RwReg  *)0x4200042CUL)

#define REG_CAN1_ECR               (*(RoReg  *)0x42000440UL)

#define REG_CAN1_PSR               (*(RoReg  *)0x42000444UL)

#define REG_CAN1_TDCR              (*(RwReg  *)0x42000448UL)

#define REG_CAN1_IR                (*(RwReg  *)0x42000450UL)

#define REG_CAN1_IE                (*(RwReg  *)0x42000454UL)

#define REG_CAN1_ILS               (*(RwReg  *)0x42000458UL)

#define REG_CAN1_ILE               (*(RwReg  *)0x4200045CUL)

#define REG_CAN1_GFC               (*(RwReg  *)0x42000480UL)

#define REG_CAN1_SIDFC             (*(RwReg  *)0x42000484UL)

#define REG_CAN1_XIDFC             (*(RwReg  *)0x42000488UL)

#define REG_CAN1_XIDAM             (*(RwReg  *)0x42000490UL)

#define REG_CAN1_HPMS              (*(RoReg  *)0x42000494UL)

#define REG_CAN1_NDAT1             (*(RwReg  *)0x42000498UL)

#define REG_CAN1_NDAT2             (*(RwReg  *)0x4200049CUL)

#define REG_CAN1_RXF0C             (*(RwReg  *)0x420004A0UL)

#define REG_CAN1_RXF0S             (*(RoReg  *)0x420004A4UL)

#define REG_CAN1_RXF0A             (*(RwReg  *)0x420004A8UL)

#define REG_CAN1_RXBC              (*(RwReg  *)0x420004ACUL)

#define REG_CAN1_RXF1C             (*(RwReg  *)0x420004B0UL)

#define REG_CAN1_RXF1S             (*(RoReg  *)0x420004B4UL)

#define REG_CAN1_RXF1A             (*(RwReg  *)0x420004B8UL)

#define REG_CAN1_RXESC             (*(RwReg  *)0x420004BCUL)

#define REG_CAN1_TXBC              (*(RwReg  *)0x420004C0UL)

#define REG_CAN1_TXFQS             (*(RoReg  *)0x420004C4UL)

#define REG_CAN1_TXESC             (*(RwReg  *)0x420004C8UL)

#define REG_CAN1_TXBRP             (*(RoReg  *)0x420004CCUL)

#define REG_CAN1_TXBAR             (*(RwReg  *)0x420004D0UL)

#define REG_CAN1_TXBCR             (*(RwReg  *)0x420004D4UL)

#define REG_CAN1_TXBTO             (*(RoReg  *)0x420004D8UL)

#define REG_CAN1_TXBCF             (*(RoReg  *)0x420004DCUL)

#define REG_CAN1_TXBTIE            (*(RwReg  *)0x420004E0UL)

#define REG_CAN1_TXBCIE            (*(RwReg  *)0x420004E4UL)

#define REG_CAN1_TXEFC             (*(RwReg  *)0x420004F0UL)

#define REG_CAN1_TXEFS             (*(RoReg  *)0x420004F4UL)

#define REG_CAN1_TXEFA             (*(RwReg  *)0x420004F8UL)

#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


/* ========== Instance parameters for CAN1 peripheral ========== */

#define CAN1_CLK_AHB_ID             18       // Index of AHB clock

#define CAN1_DMAC_ID_DEBUG          21       // DMA CAN Debug Req

#define CAN1_GCLK_ID                28       // Index of Generic Clock

#define CAN1_MSG_RAM_ADDR           0x20000000

#define CAN1_QOS_RESET_VAL          1        // QOS reset value


#endif /* _SAME54_CAN1_INSTANCE_ */