doc/html/can0_8h_source.html

#ifndef _SAME54_CAN0_INSTANCE_

#define _SAME54_CAN0_INSTANCE_


/* ========== Register definition for CAN0 peripheral ========== */

#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

#define REG_CAN0_CREL              (0x42000000)

#define REG_CAN0_ENDN              (0x42000004)

#define REG_CAN0_MRCFG             (0x42000008)

#define REG_CAN0_DBTP              (0x4200000C)

#define REG_CAN0_TEST              (0x42000010)

#define REG_CAN0_RWD               (0x42000014)

#define REG_CAN0_CCCR              (0x42000018)

#define REG_CAN0_NBTP              (0x4200001C)

#define REG_CAN0_TSCC              (0x42000020)

#define REG_CAN0_TSCV              (0x42000024)

#define REG_CAN0_TOCC              (0x42000028)

#define REG_CAN0_TOCV              (0x4200002C)

#define REG_CAN0_ECR               (0x42000040)

#define REG_CAN0_PSR               (0x42000044)

#define REG_CAN0_TDCR              (0x42000048)

#define REG_CAN0_IR                (0x42000050)

#define REG_CAN0_IE                (0x42000054)

#define REG_CAN0_ILS               (0x42000058)

#define REG_CAN0_ILE               (0x4200005C)

#define REG_CAN0_GFC               (0x42000080)

#define REG_CAN0_SIDFC             (0x42000084)

#define REG_CAN0_XIDFC             (0x42000088)

#define REG_CAN0_XIDAM             (0x42000090)

#define REG_CAN0_HPMS              (0x42000094)

#define REG_CAN0_NDAT1             (0x42000098)

#define REG_CAN0_NDAT2             (0x4200009C)

#define REG_CAN0_RXF0C             (0x420000A0)

#define REG_CAN0_RXF0S             (0x420000A4)

#define REG_CAN0_RXF0A             (0x420000A8)

#define REG_CAN0_RXBC              (0x420000AC)

#define REG_CAN0_RXF1C             (0x420000B0)

#define REG_CAN0_RXF1S             (0x420000B4)

#define REG_CAN0_RXF1A             (0x420000B8)

#define REG_CAN0_RXESC             (0x420000BC)

#define REG_CAN0_TXBC              (0x420000C0)

#define REG_CAN0_TXFQS             (0x420000C4)

#define REG_CAN0_TXESC             (0x420000C8)

#define REG_CAN0_TXBRP             (0x420000CC)

#define REG_CAN0_TXBAR             (0x420000D0)

#define REG_CAN0_TXBCR             (0x420000D4)

#define REG_CAN0_TXBTO             (0x420000D8)

#define REG_CAN0_TXBCF             (0x420000DC)

#define REG_CAN0_TXBTIE            (0x420000E0)

#define REG_CAN0_TXBCIE            (0x420000E4)

#define REG_CAN0_TXEFC             (0x420000F0)

#define REG_CAN0_TXEFS             (0x420000F4)

#define REG_CAN0_TXEFA             (0x420000F8)

#else

#define REG_CAN0_CREL              (*(RoReg  *)0x42000000UL)

#define REG_CAN0_ENDN              (*(RoReg  *)0x42000004UL)

#define REG_CAN0_MRCFG             (*(RwReg  *)0x42000008UL)

#define REG_CAN0_DBTP              (*(RwReg  *)0x4200000CUL)

#define REG_CAN0_TEST              (*(RwReg  *)0x42000010UL)

#define REG_CAN0_RWD               (*(RwReg  *)0x42000014UL)

#define REG_CAN0_CCCR              (*(RwReg  *)0x42000018UL)

#define REG_CAN0_NBTP              (*(RwReg  *)0x4200001CUL)

#define REG_CAN0_TSCC              (*(RwReg  *)0x42000020UL)

#define REG_CAN0_TSCV              (*(RoReg  *)0x42000024UL)

#define REG_CAN0_TOCC              (*(RwReg  *)0x42000028UL)

#define REG_CAN0_TOCV              (*(RwReg  *)0x4200002CUL)

#define REG_CAN0_ECR               (*(RoReg  *)0x42000040UL)

#define REG_CAN0_PSR               (*(RoReg  *)0x42000044UL)

#define REG_CAN0_TDCR              (*(RwReg  *)0x42000048UL)

#define REG_CAN0_IR                (*(RwReg  *)0x42000050UL)

#define REG_CAN0_IE                (*(RwReg  *)0x42000054UL)

#define REG_CAN0_ILS               (*(RwReg  *)0x42000058UL)

#define REG_CAN0_ILE               (*(RwReg  *)0x4200005CUL)

#define REG_CAN0_GFC               (*(RwReg  *)0x42000080UL)

#define REG_CAN0_SIDFC             (*(RwReg  *)0x42000084UL)

#define REG_CAN0_XIDFC             (*(RwReg  *)0x42000088UL)

#define REG_CAN0_XIDAM             (*(RwReg  *)0x42000090UL)

#define REG_CAN0_HPMS              (*(RoReg  *)0x42000094UL)

#define REG_CAN0_NDAT1             (*(RwReg  *)0x42000098UL)

#define REG_CAN0_NDAT2             (*(RwReg  *)0x4200009CUL)

#define REG_CAN0_RXF0C             (*(RwReg  *)0x420000A0UL)

#define REG_CAN0_RXF0S             (*(RoReg  *)0x420000A4UL)

#define REG_CAN0_RXF0A             (*(RwReg  *)0x420000A8UL)

#define REG_CAN0_RXBC              (*(RwReg  *)0x420000ACUL)

#define REG_CAN0_RXF1C             (*(RwReg  *)0x420000B0UL)

#define REG_CAN0_RXF1S             (*(RoReg  *)0x420000B4UL)

#define REG_CAN0_RXF1A             (*(RwReg  *)0x420000B8UL)

#define REG_CAN0_RXESC             (*(RwReg  *)0x420000BCUL)

#define REG_CAN0_TXBC              (*(RwReg  *)0x420000C0UL)

#define REG_CAN0_TXFQS             (*(RoReg  *)0x420000C4UL)

#define REG_CAN0_TXESC             (*(RwReg  *)0x420000C8UL)

#define REG_CAN0_TXBRP             (*(RoReg  *)0x420000CCUL)

#define REG_CAN0_TXBAR             (*(RwReg  *)0x420000D0UL)

#define REG_CAN0_TXBCR             (*(RwReg  *)0x420000D4UL)

#define REG_CAN0_TXBTO             (*(RoReg  *)0x420000D8UL)

#define REG_CAN0_TXBCF             (*(RoReg  *)0x420000DCUL)

#define REG_CAN0_TXBTIE            (*(RwReg  *)0x420000E0UL)

#define REG_CAN0_TXBCIE            (*(RwReg  *)0x420000E4UL)

#define REG_CAN0_TXEFC             (*(RwReg  *)0x420000F0UL)

#define REG_CAN0_TXEFS             (*(RoReg  *)0x420000F4UL)

#define REG_CAN0_TXEFA             (*(RwReg  *)0x420000F8UL)

#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


/* ========== Instance parameters for CAN0 peripheral ========== */

#define CAN0_CLK_AHB_ID             17       // Index of AHB clock

#define CAN0_DMAC_ID_DEBUG          20       // DMA CAN Debug Req

#define CAN0_GCLK_ID                27       // Index of Generic Clock

#define CAN0_MSG_RAM_ADDR           0x20000000

#define CAN0_QOS_RESET_VAL          1        // QOS reset value


#endif /* _SAME54_CAN0_INSTANCE_ */