G.5.3 ARM Features

The ‘org.gnu.gdb.arm.core’ feature is required for non-M-profile ARM targets. It should contain registers ‘r0’ through ‘r13’, ‘sp’, ‘lr’, ‘pc’, and ‘cpsr’.

For M-profile targets (e.g. Cortex-M3), the ‘org.gnu.gdb.arm.core’ feature is replaced by ‘org.gnu.gdb.arm.m-profile’. It should contain registers ‘r0’ through ‘r13’, ‘sp’, ‘lr’, ‘pc’, and ‘xpsr’.

The ‘org.gnu.gdb.arm.fpa’ feature is optional. If present, it should contain registers ‘f0’ through ‘f7’ and ‘fps’.

The ‘org.gnu.gdb.xscale.iwmmxt’ feature is optional. If present, it should contain at least registers ‘wR0’ through ‘wR15’ and ‘wCGR0’ through ‘wCGR3’. The ‘wCID’, ‘wCon’, ‘wCSSF’, and ‘wCASF’ registers are optional.

The ‘org.gnu.gdb.arm.vfp’ feature is optional. If present, it should contain at least registers ‘d0’ through ‘d15’. If they are present, ‘d16’ through ‘d31’ should also be included. GDB will synthesize the single-precision registers from halves of the double-precision registers.

The ‘org.gnu.gdb.arm.neon’ feature is optional. It does not need to contain registers; it instructs GDB to display the VFP double-precision registers as vectors and to synthesize the quad-precision registers from pairs of double-precision registers. If this feature is present, ‘org.gnu.gdb.arm.vfp’ must also be present and include 32 double-precision registers.