ARC Directives (Using as)

9.3.3 ARC Machine Directives

The ARC version of as supports the following additional machine directives:

.lcomm symbol, length[, alignment]

Reserve length (an absolute expression) bytes for a local common denoted by symbol. The section and value of symbol are those of the new local common. The addresses are allocated in the bss section, so that at run-time the bytes start off zeroed. Since symbol is not declared global, it is normally not visible to ld. The optional third parameter, alignment, specifies the desired alignment of the symbol in the bss section, specified as a byte boundary (for example, an alignment of 16 means that the least significant 4 bits of the address should be zero). The alignment must be an absolute expression, and it must be a power of two. If no alignment is specified, as will set the alignment to the largest power of two less than or equal to the size of the symbol, up to a maximum of 16.

.lcommon symbol, length[, alignment]

The same as lcomm directive.

.cpu cpu

The .cpu directive must be followed by the desired core version. Permitted values for CPU are:

ARC600: Assemble for the ARC600 instruction set.
arc600_norm: Assemble for ARC 600 with norm instructions.
arc600_mul64: Assemble for ARC 600 with mul64 instructions.
arc600_mul32x16: Assemble for ARC 600 with mul32x16 instructions.
arc601: Assemble for ARC 601 instruction set.
arc601_norm: Assemble for ARC 601 with norm instructions.
arc601_mul64: Assemble for ARC 601 with mul64 instructions.
arc601_mul32x16: Assemble for ARC 601 with mul32x16 instructions.
ARC700: Assemble for the ARC700 instruction set.
NPS400: Assemble for the NPS400 instruction set.
EM: Assemble for the ARC EM instruction set.
arcem: Assemble for ARC EM instruction set
em4: Assemble for ARC EM with code-density instructions.
em4_dmips: Assemble for ARC EM with code-density instructions.
em4_fpus: Assemble for ARC EM with code-density instructions.
em4_fpuda: Assemble for ARC EM with code-density, and double-precision assist instructions.
quarkse_em: Assemble for QuarkSE-EM instruction set.
HS: Assemble for the ARC HS instruction set.
archs: Assemble for ARC HS instruction set.
hs: Assemble for ARC HS instruction set.
hs34: Assemble for ARC HS34 instruction set.
hs38: Assemble for ARC HS38 instruction set.
hs38_linux: Assemble for ARC HS38 with floating point support on.

Note: the .cpu directive overrides the command-line option -mcpu=cpu; a warning is emitted when the version is not consistent between the two.

.extAuxRegister name, addr, mode

Auxiliary registers can be defined in the assembler source code by using this directive. The first parameter, name, is the name of the new auxiliary register. The second parameter, addr, is address the of the auxiliary register. The third parameter, mode, specifies whether the register is readable and/or writable and is one of:

r: Read only;
w: Write only;
r|w: Read and write.

For example:

	.extAuxRegister mulhi, 0x12, w

specifies a write only extension auxiliary register, mulhi at address 0x12.

.extCondCode suffix, val

ARC supports extensible condition codes. This directive defines a new condition code, to be known by the suffix, suffix and will depend on the value, val in the condition code.

For example:

	.extCondCode is_busy,0x14
	add.is_busy  r1,r2,r3

will only execute the add instruction if the condition code value is 0x14.

.extCoreRegister name, regnum, mode, shortcut

Specifies an extension core register named name as a synonym for the register numbered regnum. The register number must be between 32 and 59. The third argument, mode, indicates whether the register is readable and/or writable and is one of:

r: Read only;
w: Write only;
r|w: Read and write.

The final parameter, shortcut indicates whether the register has a short cut in the pipeline. The valid values are:

can_shortcut: The register has a short cut in the pipeline;
cannot_shortcut: The register does not have a short cut in the pipeline.

For example:

	.extCoreRegister mlo, 57, r , can_shortcut

defines a read only extension core register, mlo, which is register 57, and can short cut the pipeline.

.extInstruction name, opcode, subopcode, suffixclass, syntaxclass

ARC allows the user to specify extension instructions. These extension instructions are not macros; the assembler creates encodings for use of these instructions according to the specification by the user.

The first argument, name, gives the name of the instruction.

The second argument, opcode, is the opcode to be used (bits 31:27 in the encoding).

The third argument, subopcode, is the sub-opcode to be used, but the correct value also depends on the fifth argument, syntaxclass

The fourth argument, suffixclass, determines the kinds of suffixes to be allowed. Valid values are:

SUFFIX_NONE: No suffixes are permitted;
SUFFIX_COND: Conditional suffixes are permitted;
SUFFIX_FLAG: Flag setting suffixes are permitted.
SUFFIX_COND|SUFFIX_FLAG: Both conditional and flag setting suffices are permitted.

The fifth and final argument, syntaxclass, determines the syntax class for the instruction. It can have the following values:

SYNTAX_2OP: Two Operand Instruction;
SYNTAX_3OP: Three Operand Instruction.
SYNTAX_1OP: One Operand Instruction.
SYNTAX_NOP: No Operand Instruction.

The syntax class may be followed by ‘|’ and one of the following modifiers.

OP1_MUST_BE_IMM

Modifies syntax class SYNTAX_3OP, specifying that the first operand of a three-operand instruction must be an immediate (i.e., the result is discarded). This is usually used to set the flags using specific instructions and not retain results.

OP1_IMM_IMPLIED

Modifies syntax class SYNTAX_20P, specifying that there is an implied immediate destination operand which does not appear in the syntax.

For example, if the source code contains an instruction like:

inst r1,r2

the first argument is an implied immediate (that is, the result is discarded). This is the same as though the source code were: inst 0,r1,r2.

For example, defining a 64-bit multiplier with immediate operands:

	.extInstruction  mp64, 0x07, 0x2d, SUFFIX_COND|SUFFIX_FLAG,
			 SYNTAX_3OP|OP1_MUST_BE_IMM

which specifies an extension instruction named mp64 with 3 operands. It sets the flags and can be used with a condition code, for which the first operand is an immediate, i.e. equivalent to discarding the result of the operation.

A two operands instruction variant would be:

	.extInstruction mul64, 0x07, 0x2d, SUFFIX_COND,
	SYNTAX_2OP|OP1_IMM_IMPLIED

which describes a two operand instruction with an implicit first immediate operand. The result of this operation would be discarded.

.arc_attribute tag, value

Set the ARC object attribute tag to value.

The tag is either an attribute number, or one of the following: Tag_ARC_PCS_config, Tag_ARC_CPU_base, Tag_ARC_CPU_variation, Tag_ARC_CPU_name, Tag_ARC_ABI_rf16, Tag_ARC_ABI_osver, Tag_ARC_ABI_sda, Tag_ARC_ABI_pic, Tag_ARC_ABI_tls, Tag_ARC_ABI_enumsize, Tag_ARC_ABI_exceptions, Tag_ARC_ABI_double_size, Tag_ARC_ISA_config, Tag_ARC_ISA_apex, Tag_ARC_ISA_mpy_option

The value is either a number, "string", or number, "string" depending on the tag.