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<title>SAME54P20A Test Project: /storage/Shared/Documents/Projects/ePenguin/ePenguin-Software-Framework/arch/arm/SAME54/SAME54A/mcu/inc/instance/tcc4.h Source File</title>
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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_92b117bae75cf16a05ca7611db29e9c7.html">instance</a></li> </ul>
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<div class="title">tcc4.h</div> </div>
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<a href="tcc4_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno"> 1</span>  </div>
<div class="line"><a name="l00030"></a><span class="lineno"> 30</span> <span class="preprocessor">#ifndef _SAME54_TCC4_INSTANCE_</span></div>
<div class="line"><a name="l00031"></a><span class="lineno"> 31</span> <span class="preprocessor">#define _SAME54_TCC4_INSTANCE_</span></div>
<div class="line"><a name="l00032"></a><span class="lineno"> 32</span>  </div>
<div class="line"><a name="l00033"></a><span class="lineno"> 33</span> <span class="comment">/* ========== Register definition for TCC4 peripheral ========== */</span></div>
<div class="line"><a name="l00034"></a><span class="lineno"> 34</span> <span class="preprocessor">#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
<div class="line"><a name="l00035"></a><span class="lineno"> 35</span> <span class="preprocessor">#define REG_TCC4_CTRLA (0x43001000) </span></div>
<div class="line"><a name="l00036"></a><span class="lineno"> 36</span> <span class="preprocessor">#define REG_TCC4_CTRLBCLR (0x43001004) </span></div>
<div class="line"><a name="l00037"></a><span class="lineno"> 37</span> <span class="preprocessor">#define REG_TCC4_CTRLBSET (0x43001005) </span></div>
<div class="line"><a name="l00038"></a><span class="lineno"> 38</span> <span class="preprocessor">#define REG_TCC4_SYNCBUSY (0x43001008) </span></div>
<div class="line"><a name="l00039"></a><span class="lineno"> 39</span> <span class="preprocessor">#define REG_TCC4_FCTRLA (0x4300100C) </span></div>
<div class="line"><a name="l00040"></a><span class="lineno"> 40</span> <span class="preprocessor">#define REG_TCC4_FCTRLB (0x43001010) </span></div>
<div class="line"><a name="l00041"></a><span class="lineno"> 41</span> <span class="preprocessor">#define REG_TCC4_DRVCTRL (0x43001018) </span></div>
<div class="line"><a name="l00042"></a><span class="lineno"> 42</span> <span class="preprocessor">#define REG_TCC4_DBGCTRL (0x4300101E) </span></div>
<div class="line"><a name="l00043"></a><span class="lineno"> 43</span> <span class="preprocessor">#define REG_TCC4_EVCTRL (0x43001020) </span></div>
<div class="line"><a name="l00044"></a><span class="lineno"> 44</span> <span class="preprocessor">#define REG_TCC4_INTENCLR (0x43001024) </span></div>
<div class="line"><a name="l00045"></a><span class="lineno"> 45</span> <span class="preprocessor">#define REG_TCC4_INTENSET (0x43001028) </span></div>
<div class="line"><a name="l00046"></a><span class="lineno"> 46</span> <span class="preprocessor">#define REG_TCC4_INTFLAG (0x4300102C) </span></div>
<div class="line"><a name="l00047"></a><span class="lineno"> 47</span> <span class="preprocessor">#define REG_TCC4_STATUS (0x43001030) </span></div>
<div class="line"><a name="l00048"></a><span class="lineno"> 48</span> <span class="preprocessor">#define REG_TCC4_COUNT (0x43001034) </span></div>
<div class="line"><a name="l00049"></a><span class="lineno"> 49</span> <span class="preprocessor">#define REG_TCC4_WAVE (0x4300103C) </span></div>
<div class="line"><a name="l00050"></a><span class="lineno"> 50</span> <span class="preprocessor">#define REG_TCC4_PER (0x43001040) </span></div>
<div class="line"><a name="l00051"></a><span class="lineno"> 51</span> <span class="preprocessor">#define REG_TCC4_CC0 (0x43001044) </span></div>
<div class="line"><a name="l00052"></a><span class="lineno"> 52</span> <span class="preprocessor">#define REG_TCC4_CC1 (0x43001048) </span></div>
<div class="line"><a name="l00053"></a><span class="lineno"> 53</span> <span class="preprocessor">#define REG_TCC4_PERBUF (0x4300106C) </span></div>
<div class="line"><a name="l00054"></a><span class="lineno"> 54</span> <span class="preprocessor">#define REG_TCC4_CCBUF0 (0x43001070) </span></div>
<div class="line"><a name="l00055"></a><span class="lineno"> 55</span> <span class="preprocessor">#define REG_TCC4_CCBUF1 (0x43001074) </span></div>
<div class="line"><a name="l00056"></a><span class="lineno"> 56</span> <span class="preprocessor">#else</span></div>
<div class="line"><a name="l00057"></a><span class="lineno"><a class="line" href="tcc4_8h.html#a154be97a6091e677620e726d9fcd16f6"> 57</a></span> <span class="preprocessor">#define REG_TCC4_CTRLA (*(RwReg *)0x43001000UL) </span></div>
<div class="line"><a name="l00058"></a><span class="lineno"><a class="line" href="tcc4_8h.html#a92aea089fd44830ed9dbff4286b6e0e5"> 58</a></span> <span class="preprocessor">#define REG_TCC4_CTRLBCLR (*(RwReg8 *)0x43001004UL) </span></div>
<div class="line"><a name="l00059"></a><span class="lineno"><a class="line" href="tcc4_8h.html#ac080190c0fd7f244869e3f899284441a"> 59</a></span> <span class="preprocessor">#define REG_TCC4_CTRLBSET (*(RwReg8 *)0x43001005UL) </span></div>
<div class="line"><a name="l00060"></a><span class="lineno"><a class="line" href="tcc4_8h.html#a5b8d1ec862eac5359180ccf49d1a263d"> 60</a></span> <span class="preprocessor">#define REG_TCC4_SYNCBUSY (*(RoReg *)0x43001008UL) </span></div>
<div class="line"><a name="l00061"></a><span class="lineno"><a class="line" href="tcc4_8h.html#a13d013b320b2d4801841ec8640662442"> 61</a></span> <span class="preprocessor">#define REG_TCC4_FCTRLA (*(RwReg *)0x4300100CUL) </span></div>
<div class="line"><a name="l00062"></a><span class="lineno"><a class="line" href="tcc4_8h.html#a8ec6137be19636d53cd3e094afd6e3f8"> 62</a></span> <span class="preprocessor">#define REG_TCC4_FCTRLB (*(RwReg *)0x43001010UL) </span></div>
<div class="line"><a name="l00063"></a><span class="lineno"><a class="line" href="tcc4_8h.html#a17d56dc3a51610e516aee1a25ac6dc12"> 63</a></span> <span class="preprocessor">#define REG_TCC4_DRVCTRL (*(RwReg *)0x43001018UL) </span></div>
<div class="line"><a name="l00064"></a><span class="lineno"><a class="line" href="tcc4_8h.html#a7e0a53e11d9ae8716d0f731da541f5ea"> 64</a></span> <span class="preprocessor">#define REG_TCC4_DBGCTRL (*(RwReg8 *)0x4300101EUL) </span></div>
<div class="line"><a name="l00065"></a><span class="lineno"><a class="line" href="tcc4_8h.html#a47e4dce19f58b636c6f53c18942d5a49"> 65</a></span> <span class="preprocessor">#define REG_TCC4_EVCTRL (*(RwReg *)0x43001020UL) </span></div>
<div class="line"><a name="l00066"></a><span class="lineno"><a class="line" href="tcc4_8h.html#aefaa183e83258cb99aaeac795c5ae111"> 66</a></span> <span class="preprocessor">#define REG_TCC4_INTENCLR (*(RwReg *)0x43001024UL) </span></div>
<div class="line"><a name="l00067"></a><span class="lineno"><a class="line" href="tcc4_8h.html#a924d257805bcb9e8d543ee89563b55ae"> 67</a></span> <span class="preprocessor">#define REG_TCC4_INTENSET (*(RwReg *)0x43001028UL) </span></div>
<div class="line"><a name="l00068"></a><span class="lineno"><a class="line" href="tcc4_8h.html#a1a91173ccb0b0e7f9fb5ee635c7a26f5"> 68</a></span> <span class="preprocessor">#define REG_TCC4_INTFLAG (*(RwReg *)0x4300102CUL) </span></div>
<div class="line"><a name="l00069"></a><span class="lineno"><a class="line" href="tcc4_8h.html#a006d0e70fd21d35336516ea3eed0d912"> 69</a></span> <span class="preprocessor">#define REG_TCC4_STATUS (*(RwReg *)0x43001030UL) </span></div>
<div class="line"><a name="l00070"></a><span class="lineno"><a class="line" href="tcc4_8h.html#a8a28b152d830800e8bea78ca4fd57cd6"> 70</a></span> <span class="preprocessor">#define REG_TCC4_COUNT (*(RwReg *)0x43001034UL) </span></div>
<div class="line"><a name="l00071"></a><span class="lineno"><a class="line" href="tcc4_8h.html#ab4fb52c94fa88e6db340a480b5275986"> 71</a></span> <span class="preprocessor">#define REG_TCC4_WAVE (*(RwReg *)0x4300103CUL) </span></div>
<div class="line"><a name="l00072"></a><span class="lineno"><a class="line" href="tcc4_8h.html#a931bfcf6b9ec1d20a11375110057ffce"> 72</a></span> <span class="preprocessor">#define REG_TCC4_PER (*(RwReg *)0x43001040UL) </span></div>
<div class="line"><a name="l00073"></a><span class="lineno"><a class="line" href="tcc4_8h.html#af6b669ea857c006f33c247b4174b9db8"> 73</a></span> <span class="preprocessor">#define REG_TCC4_CC0 (*(RwReg *)0x43001044UL) </span></div>
<div class="line"><a name="l00074"></a><span class="lineno"><a class="line" href="tcc4_8h.html#a14c9682586724fff343c90a2f4fe9207"> 74</a></span> <span class="preprocessor">#define REG_TCC4_CC1 (*(RwReg *)0x43001048UL) </span></div>
<div class="line"><a name="l00075"></a><span class="lineno"><a class="line" href="tcc4_8h.html#a4d1045d699c7e27b636dc66408b75f1e"> 75</a></span> <span class="preprocessor">#define REG_TCC4_PERBUF (*(RwReg *)0x4300106CUL) </span></div>
<div class="line"><a name="l00076"></a><span class="lineno"><a class="line" href="tcc4_8h.html#a84e88504780687e77e3c1b2eaba6a72d"> 76</a></span> <span class="preprocessor">#define REG_TCC4_CCBUF0 (*(RwReg *)0x43001070UL) </span></div>
<div class="line"><a name="l00077"></a><span class="lineno"><a class="line" href="tcc4_8h.html#ae43199e68ffea8eea7cf40e890f70594"> 77</a></span> <span class="preprocessor">#define REG_TCC4_CCBUF1 (*(RwReg *)0x43001074UL) </span></div>
<div class="line"><a name="l00078"></a><span class="lineno"> 78</span> <span class="preprocessor">#endif </span><span class="comment">/* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00079"></a><span class="lineno"> 79</span>  </div>
<div class="line"><a name="l00080"></a><span class="lineno"> 80</span> <span class="comment">/* ========== Instance parameters for TCC4 peripheral ========== */</span></div>
<div class="line"><a name="l00081"></a><span class="lineno"> 81</span> <span class="preprocessor">#define TCC4_CC_NUM 2 // Number of Compare/Capture units</span></div>
<div class="line"><a name="l00082"></a><span class="lineno"> 82</span> <span class="preprocessor">#define TCC4_DITHERING 0 // Dithering feature implemented</span></div>
<div class="line"><a name="l00083"></a><span class="lineno"> 83</span> <span class="preprocessor">#define TCC4_DMAC_ID_MC_0 42</span></div>
<div class="line"><a name="l00084"></a><span class="lineno"> 84</span> <span class="preprocessor">#define TCC4_DMAC_ID_MC_1 43</span></div>
<div class="line"><a name="l00085"></a><span class="lineno"> 85</span> <span class="preprocessor">#define TCC4_DMAC_ID_MC_LSB 42</span></div>
<div class="line"><a name="l00086"></a><span class="lineno"> 86</span> <span class="preprocessor">#define TCC4_DMAC_ID_MC_MSB 43</span></div>
<div class="line"><a name="l00087"></a><span class="lineno"> 87</span> <span class="preprocessor">#define TCC4_DMAC_ID_MC_SIZE 2</span></div>
<div class="line"><a name="l00088"></a><span class="lineno"> 88</span> <span class="preprocessor">#define TCC4_DMAC_ID_OVF 41 // DMA overflow/underflow/retrigger trigger</span></div>
<div class="line"><a name="l00089"></a><span class="lineno"> 89</span> <span class="preprocessor">#define TCC4_DTI 0 // Dead-Time-Insertion feature implemented</span></div>
<div class="line"><a name="l00090"></a><span class="lineno"> 90</span> <span class="preprocessor">#define TCC4_EXT 0 // Coding of implemented extended features</span></div>
<div class="line"><a name="l00091"></a><span class="lineno"> 91</span> <span class="preprocessor">#define TCC4_GCLK_ID 38 // Index of Generic Clock</span></div>
<div class="line"><a name="l00092"></a><span class="lineno"> 92</span> <span class="preprocessor">#define TCC4_MASTER_SLAVE_MODE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave</span></div>
<div class="line"><a name="l00093"></a><span class="lineno"> 93</span> <span class="preprocessor">#define TCC4_OTMX 0 // Output Matrix feature implemented</span></div>
<div class="line"><a name="l00094"></a><span class="lineno"> 94</span> <span class="preprocessor">#define TCC4_OW_NUM 2 // Number of Output Waveforms</span></div>
<div class="line"><a name="l00095"></a><span class="lineno"> 95</span> <span class="preprocessor">#define TCC4_PG 0 // Pattern Generation feature implemented</span></div>
<div class="line"><a name="l00096"></a><span class="lineno"> 96</span> <span class="preprocessor">#define TCC4_SIZE 16 </span></div>
<div class="line"><a name="l00097"></a><span class="lineno"> 97</span> <span class="preprocessor">#define TCC4_SWAP 0 // DTI outputs swap feature implemented</span></div>
<div class="line"><a name="l00098"></a><span class="lineno"> 98</span>  </div>
<div class="line"><a name="l00099"></a><span class="lineno"> 99</span> <span class="preprocessor">#endif </span><span class="comment">/* _SAME54_TCC4_INSTANCE_ */</span><span class="preprocessor"></span></div>
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