doc/html/tcc0_8h_source.html

#ifndef _SAME54_TCC0_INSTANCE_

#define _SAME54_TCC0_INSTANCE_


/* ========== Register definition for TCC0 peripheral ========== */

#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

#define REG_TCC0_CTRLA             (0x41016000)

#define REG_TCC0_CTRLBCLR          (0x41016004)

#define REG_TCC0_CTRLBSET          (0x41016005)

#define REG_TCC0_SYNCBUSY          (0x41016008)

#define REG_TCC0_FCTRLA            (0x4101600C)

#define REG_TCC0_FCTRLB            (0x41016010)

#define REG_TCC0_WEXCTRL           (0x41016014)

#define REG_TCC0_DRVCTRL           (0x41016018)

#define REG_TCC0_DBGCTRL           (0x4101601E)

#define REG_TCC0_EVCTRL            (0x41016020)

#define REG_TCC0_INTENCLR          (0x41016024)

#define REG_TCC0_INTENSET          (0x41016028)

#define REG_TCC0_INTFLAG           (0x4101602C)

#define REG_TCC0_STATUS            (0x41016030)

#define REG_TCC0_COUNT             (0x41016034)

#define REG_TCC0_PATT              (0x41016038)

#define REG_TCC0_WAVE              (0x4101603C)

#define REG_TCC0_PER               (0x41016040)

#define REG_TCC0_CC0               (0x41016044)

#define REG_TCC0_CC1               (0x41016048)

#define REG_TCC0_CC2               (0x4101604C)

#define REG_TCC0_CC3               (0x41016050)

#define REG_TCC0_CC4               (0x41016054)

#define REG_TCC0_CC5               (0x41016058)

#define REG_TCC0_PATTBUF           (0x41016064)

#define REG_TCC0_PERBUF            (0x4101606C)

#define REG_TCC0_CCBUF0            (0x41016070)

#define REG_TCC0_CCBUF1            (0x41016074)

#define REG_TCC0_CCBUF2            (0x41016078)

#define REG_TCC0_CCBUF3            (0x4101607C)

#define REG_TCC0_CCBUF4            (0x41016080)

#define REG_TCC0_CCBUF5            (0x41016084)

#else

#define REG_TCC0_CTRLA             (*(RwReg  *)0x41016000UL)

#define REG_TCC0_CTRLBCLR          (*(RwReg8 *)0x41016004UL)

#define REG_TCC0_CTRLBSET          (*(RwReg8 *)0x41016005UL)

#define REG_TCC0_SYNCBUSY          (*(RoReg  *)0x41016008UL)

#define REG_TCC0_FCTRLA            (*(RwReg  *)0x4101600CUL)

#define REG_TCC0_FCTRLB            (*(RwReg  *)0x41016010UL)

#define REG_TCC0_WEXCTRL           (*(RwReg  *)0x41016014UL)

#define REG_TCC0_DRVCTRL           (*(RwReg  *)0x41016018UL)

#define REG_TCC0_DBGCTRL           (*(RwReg8 *)0x4101601EUL)

#define REG_TCC0_EVCTRL            (*(RwReg  *)0x41016020UL)

#define REG_TCC0_INTENCLR          (*(RwReg  *)0x41016024UL)

#define REG_TCC0_INTENSET          (*(RwReg  *)0x41016028UL)

#define REG_TCC0_INTFLAG           (*(RwReg  *)0x4101602CUL)

#define REG_TCC0_STATUS            (*(RwReg  *)0x41016030UL)

#define REG_TCC0_COUNT             (*(RwReg  *)0x41016034UL)

#define REG_TCC0_PATT              (*(RwReg16*)0x41016038UL)

#define REG_TCC0_WAVE              (*(RwReg  *)0x4101603CUL)

#define REG_TCC0_PER               (*(RwReg  *)0x41016040UL)

#define REG_TCC0_CC0               (*(RwReg  *)0x41016044UL)

#define REG_TCC0_CC1               (*(RwReg  *)0x41016048UL)

#define REG_TCC0_CC2               (*(RwReg  *)0x4101604CUL)

#define REG_TCC0_CC3               (*(RwReg  *)0x41016050UL)

#define REG_TCC0_CC4               (*(RwReg  *)0x41016054UL)

#define REG_TCC0_CC5               (*(RwReg  *)0x41016058UL)

#define REG_TCC0_PATTBUF           (*(RwReg16*)0x41016064UL)

#define REG_TCC0_PERBUF            (*(RwReg  *)0x4101606CUL)

#define REG_TCC0_CCBUF0            (*(RwReg  *)0x41016070UL)

#define REG_TCC0_CCBUF1            (*(RwReg  *)0x41016074UL)

#define REG_TCC0_CCBUF2            (*(RwReg  *)0x41016078UL)

#define REG_TCC0_CCBUF3            (*(RwReg  *)0x4101607CUL)

#define REG_TCC0_CCBUF4            (*(RwReg  *)0x41016080UL)

#define REG_TCC0_CCBUF5            (*(RwReg  *)0x41016084UL)

#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


/* ========== Instance parameters for TCC0 peripheral ========== */

#define TCC0_CC_NUM                 6        // Number of Compare/Capture units

#define TCC0_DITHERING              1        // Dithering feature implemented

#define TCC0_DMAC_ID_MC_0           23

#define TCC0_DMAC_ID_MC_1           24

#define TCC0_DMAC_ID_MC_2           25

#define TCC0_DMAC_ID_MC_3           26

#define TCC0_DMAC_ID_MC_4           27

#define TCC0_DMAC_ID_MC_5           28

#define TCC0_DMAC_ID_MC_LSB         23

#define TCC0_DMAC_ID_MC_MSB         28

#define TCC0_DMAC_ID_MC_SIZE        6

#define TCC0_DMAC_ID_OVF            22       // DMA overflow/underflow/retrigger trigger

#define TCC0_DTI                    1        // Dead-Time-Insertion feature implemented

#define TCC0_EXT                    31       // Coding of implemented extended features

#define TCC0_GCLK_ID                25       // Index of Generic Clock

#define TCC0_MASTER_SLAVE_MODE      1        // TCC type 0 : NA, 1 : Master, 2 : Slave

#define TCC0_OTMX                   1        // Output Matrix feature implemented

#define TCC0_OW_NUM                 8        // Number of Output Waveforms

#define TCC0_PG                     1        // Pattern Generation feature implemented

#define TCC0_SIZE                   24

#define TCC0_SWAP                   1        // DTI outputs swap feature implemented


#endif /* _SAME54_TCC0_INSTANCE_ */