SAME54P20A Test Project
tc7.h
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1 
30 #ifndef _SAME54_TC7_INSTANCE_
31 #define _SAME54_TC7_INSTANCE_
32 
33 /* ========== Register definition for TC7 peripheral ========== */
34 #if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
35 #define REG_TC7_CTRLA (0x43001800)
36 #define REG_TC7_CTRLBCLR (0x43001804)
37 #define REG_TC7_CTRLBSET (0x43001805)
38 #define REG_TC7_EVCTRL (0x43001806)
39 #define REG_TC7_INTENCLR (0x43001808)
40 #define REG_TC7_INTENSET (0x43001809)
41 #define REG_TC7_INTFLAG (0x4300180A)
42 #define REG_TC7_STATUS (0x4300180B)
43 #define REG_TC7_WAVE (0x4300180C)
44 #define REG_TC7_DRVCTRL (0x4300180D)
45 #define REG_TC7_DBGCTRL (0x4300180F)
46 #define REG_TC7_SYNCBUSY (0x43001810)
47 #define REG_TC7_COUNT16_COUNT (0x43001814)
48 #define REG_TC7_COUNT16_CC0 (0x4300181C)
49 #define REG_TC7_COUNT16_CC1 (0x4300181E)
50 #define REG_TC7_COUNT16_CCBUF0 (0x43001830)
51 #define REG_TC7_COUNT16_CCBUF1 (0x43001832)
52 #define REG_TC7_COUNT32_COUNT (0x43001814)
53 #define REG_TC7_COUNT32_CC0 (0x4300181C)
54 #define REG_TC7_COUNT32_CC1 (0x43001820)
55 #define REG_TC7_COUNT32_CCBUF0 (0x43001830)
56 #define REG_TC7_COUNT32_CCBUF1 (0x43001834)
57 #define REG_TC7_COUNT8_COUNT (0x43001814)
58 #define REG_TC7_COUNT8_PER (0x4300181B)
59 #define REG_TC7_COUNT8_CC0 (0x4300181C)
60 #define REG_TC7_COUNT8_CC1 (0x4300181D)
61 #define REG_TC7_COUNT8_PERBUF (0x4300182F)
62 #define REG_TC7_COUNT8_CCBUF0 (0x43001830)
63 #define REG_TC7_COUNT8_CCBUF1 (0x43001831)
64 #else
65 #define REG_TC7_CTRLA (*(RwReg *)0x43001800UL)
66 #define REG_TC7_CTRLBCLR (*(RwReg8 *)0x43001804UL)
67 #define REG_TC7_CTRLBSET (*(RwReg8 *)0x43001805UL)
68 #define REG_TC7_EVCTRL (*(RwReg16*)0x43001806UL)
69 #define REG_TC7_INTENCLR (*(RwReg8 *)0x43001808UL)
70 #define REG_TC7_INTENSET (*(RwReg8 *)0x43001809UL)
71 #define REG_TC7_INTFLAG (*(RwReg8 *)0x4300180AUL)
72 #define REG_TC7_STATUS (*(RwReg8 *)0x4300180BUL)
73 #define REG_TC7_WAVE (*(RwReg8 *)0x4300180CUL)
74 #define REG_TC7_DRVCTRL (*(RwReg8 *)0x4300180DUL)
75 #define REG_TC7_DBGCTRL (*(RwReg8 *)0x4300180FUL)
76 #define REG_TC7_SYNCBUSY (*(RoReg *)0x43001810UL)
77 #define REG_TC7_COUNT16_COUNT (*(RwReg16*)0x43001814UL)
78 #define REG_TC7_COUNT16_CC0 (*(RwReg16*)0x4300181CUL)
79 #define REG_TC7_COUNT16_CC1 (*(RwReg16*)0x4300181EUL)
80 #define REG_TC7_COUNT16_CCBUF0 (*(RwReg16*)0x43001830UL)
81 #define REG_TC7_COUNT16_CCBUF1 (*(RwReg16*)0x43001832UL)
82 #define REG_TC7_COUNT32_COUNT (*(RwReg *)0x43001814UL)
83 #define REG_TC7_COUNT32_CC0 (*(RwReg *)0x4300181CUL)
84 #define REG_TC7_COUNT32_CC1 (*(RwReg *)0x43001820UL)
85 #define REG_TC7_COUNT32_CCBUF0 (*(RwReg *)0x43001830UL)
86 #define REG_TC7_COUNT32_CCBUF1 (*(RwReg *)0x43001834UL)
87 #define REG_TC7_COUNT8_COUNT (*(RwReg8 *)0x43001814UL)
88 #define REG_TC7_COUNT8_PER (*(RwReg8 *)0x4300181BUL)
89 #define REG_TC7_COUNT8_CC0 (*(RwReg8 *)0x4300181CUL)
90 #define REG_TC7_COUNT8_CC1 (*(RwReg8 *)0x4300181DUL)
91 #define REG_TC7_COUNT8_PERBUF (*(RwReg8 *)0x4300182FUL)
92 #define REG_TC7_COUNT8_CCBUF0 (*(RwReg8 *)0x43001830UL)
93 #define REG_TC7_COUNT8_CCBUF1 (*(RwReg8 *)0x43001831UL)
94 #endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
95 
96 /* ========== Instance parameters for TC7 peripheral ========== */
97 #define TC7_CC_NUM 2
98 #define TC7_DMAC_ID_MC_0 66
99 #define TC7_DMAC_ID_MC_1 67
100 #define TC7_DMAC_ID_MC_LSB 66
101 #define TC7_DMAC_ID_MC_MSB 67
102 #define TC7_DMAC_ID_MC_SIZE 2
103 #define TC7_DMAC_ID_OVF 65 // Indexes of DMA Overflow trigger
104 #define TC7_EXT 0 // Coding of implemented extended features (keep 0 value)
105 #define TC7_GCLK_ID 39 // Index of Generic Clock
106 #define TC7_MASTER_SLAVE_MODE 2 // TC type 0 : NA, 1 : Master, 2 : Slave
107 #define TC7_OW_NUM 2 // Number of Output Waveforms
108 
109 #endif /* _SAME54_TC7_INSTANCE_ */