SAME54P20A Test Project
clocks.h
1 #ifndef _CLOCKS_H_
2 #define _CLOCKS_H_
3 
4 #include "core.h"
5 
6 // XOSC32K Definitions
7 #define CONF_CORE_CLK_XOSC32KCTRL_CGM_LP_MODE (0x0)
8 #define CONF_CORE_CLK_XOSC32KCTRL_CGM_STD_MODE (0x1)
9 #define CONF_CORE_CLK_XOSC32KCTRL_CGM_HS_MODE (0x2)
10 
11 #define CONF_CORE_CLK_XOSC32KCTRL_STARTUP_62592us (0x0)
12 #define CONF_CORE_CLK_XOSC32KCTRL_STARTUP_125092us (0x1)
13 #define CONF_CORE_CLK_XOSC32KCTRL_STARTUP_500092us (0x2)
14 #define CONF_CORE_CLK_XOSC32KCTRL_STARTUP_1000009200ns (0x3)
15 #define CONF_CORE_CLK_XOSC32KCTRL_STARTUP_2000009200ns (0x4)
16 #define CONF_CORE_CLK_XOSC32KCTRL_STARTUP_4000009200ns (0x5)
17 #define CONF_CORE_CLK_XOSC32KCTRL_STARTUP_8000009200ns (0x6)
18 
19 #define CONF_CORE_CLK_XOSCCTRL_STARTUP_31us 0x0
20 #define CONF_CORE_CLK_XOSCCTRL_STARTUP_61us 0x1
21 #define CONF_CORE_CLK_XOSCCTRL_STARTUP_122us 0x2
22 #define CONF_CORE_CLK_XOSCCTRL_STARTUP_244us 0x3
23 #define CONF_CORE_CLK_XOSCCTRL_STARTUP_488us 0x4
24 #define CONF_CORE_CLK_XOSCCTRL_STARTUP_977us 0x5
25 #define CONF_CORE_CLK_XOSCCTRL_STARTUP_1953us 0x6
26 #define CONF_CORE_CLK_XOSCCTRL_STARTUP_3906us 0x7
27 #define CONF_CORE_CLK_XOSCCTRL_STARTUP_7813us 0x8
28 #define CONF_CORE_CLK_XOSCCTRL_STARTUP_15625us 0x9
29 #define CONF_CORE_CLK_XOSCCTRL_STARTUP_31250us 0xA
30 #define CONF_CORE_CLK_XOSCCTRL_STARTUP_62500us 0xB
31 #define CONF_CORE_CLK_XOSCCTRL_STARTUP_125000us 0xC
32 #define CONF_CORE_CLK_XOSCCTRL_STARTUP_250000us 0xD
33 #define CONF_CORE_CLK_XOSCCTRL_STARTUP_500000us 0xE
34 #define CONF_CORE_CLK_XOSCCTRL_STARTUP_1000000us 0xF
35 
36 // Oscillator Current Multiplier
37 #define CONF_CORE_CLK_XOSCCTRL_IMULT_24MHZ_TO_48MHZ (6)
38 #define CONF_CORE_CLK_XOSCCTRL_IMULT_16MHZ_TO_24MHZ (5)
39 #define CONF_CORE_CLK_XOSCCTRL_IMULT_8MHZ_TO_16MHZ (4)
40 #define CONF_CORE_CLK_XOSCCTRL_IMULT_8MHZ (3)
41 
42 // Oscillator Current Reference
43 #define CONF_CORE_CLK_XOSCCTRL_IPTAT_24MHZ_TO_48MHZ (3)
44 #define CONF_CORE_CLK_XOSCCTRL_IPTAT_16MHZ_TO_24MHZ (3)
45 #define CONF_CORE_CLK_XOSCCTRL_IPTAT_8MHZ_TO_16MHZ (3)
46 #define CONF_CORE_CLK_XOSCCTRL_IPTAT_8MHZ (2)
47 
48 // DFLL Definitions
49 #define CONF_CORE_CLK_DFLLCTRL_STABLE_FCALIB_NOT_FIXED (0)
50 #define CONF_CORE_CLK_DFLLCTRL_STABLE_FCALIB_FIXED (1)
51 
52 // DPLL Definitions
53 #define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_3210KHZ (0x0)
54 #define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_1600KHZ (0x1)
55 #define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_1100KHZ (0x2)
56 #define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_800KHZ (0x3)
57 #define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_640KHZ (0x4)
58 #define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_550KHZ (0x5)
59 #define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_450KHZ (0x6)
60 #define CONF_CORE_CLK_DPLLCTRL_DCOFILTER_400KHZ (0x7)
61 
62 #define CONF_CORE_CLK_DPLLCTRL_LTIME_TIMEOUT_NONE (0x0)
63 #define CONF_CORE_CLK_DPLLCTRL_LTIME_TIMEOUT_800us (0x4)
64 #define CONF_CORE_CLK_DPLLCTRL_LTIME_TIMEOUT_900us (0x5)
65 #define CONF_CORE_CLK_DPLLCTRL_LTIME_TIMEOUT_1000us (0x6)
66 #define CONF_CORE_CLK_DPLLCTRL_LTIME_TIMEOUT_1100us (0x7)
67 
68 #define CONF_CORE_CLK_DPLLCTRL_REFCLK_GCLK (0x0)
69 #define CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC32 (0x1)
70 #define CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC0 (0x2)
71 #define CONF_CORE_CLK_DPLLCTRL_REFCLK_XOSC1 (0x3)
72 
73 void clock_osc32k_init(void);
74 void clock_osc_init(void);
75 void clock_mclk_init(void);
76 void clock_gclk_init(void);
77 void clock_dpll_init(void);
78 void clock_dfll_init(void);
79 #endif