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<h4 class="subsection">9.24.2 Syntax</h4>
<p><a name="index-M68HC11-syntax-1409"></a><a name="index-syntax_002c-M68HC11-1410"></a>
In the M68HC11 syntax, the instruction name comes first and it may
be followed by one or several operands (up to three). Operands are
separated by comma (‘<samp><span class="samp">,</span></samp>’). In the normal mode,
<code>as</code> will complain if too many operands are specified for
a given instruction. In the MRI mode (turned on with ‘<samp><span class="samp">-M</span></samp>’ option),
it will treat them as comments. Example:
<pre class="smallexample"> inx
lda #23
bset 2,x #4
brclr *bot #8 foo
</pre>
<p><a name="index-line-comment-character_002c-M68HC11-1411"></a><a name="index-M68HC11-line-comment-character-1412"></a>The presence of a ‘<samp><span class="samp">;</span></samp>’ character or a ‘<samp><span class="samp">!</span></samp>’ character anywhere
on a line indicates the start of a comment that extends to the end of
that line.
<p>A ‘<samp><span class="samp">*</span></samp>’ or a ‘<samp><span class="samp">#</span></samp>’ character at the start of a line also
introduces a line comment, but these characters do not work elsewhere
on the line. If the first character of the line is a ‘<samp><span class="samp">#</span></samp>’ then as
well as starting a comment, the line could also be logical line number
directive (see <a href="Comments.html#Comments">Comments</a>) or a preprocessor control command
(see <a href="Preprocessing.html#Preprocessing">Preprocessing</a>).
<p><a name="index-line-separator_002c-M68HC11-1413"></a><a name="index-statement-separator_002c-M68HC11-1414"></a><a name="index-M68HC11-line-separator-1415"></a>The M68HC11 assembler does not currently support a line separator
character.
<p><a name="index-M68HC11-addressing-modes-1416"></a><a name="index-addressing-modes_002c-M68HC11-1417"></a>The following addressing modes are understood for 68HC11 and 68HC12:
<dl>
<dt><dfn>Immediate</dfn><dd>‘<samp><span class="samp">#</span><var>number</var></samp>’
<br><dt><dfn>Address Register</dfn><dd>‘<samp><var>number</var><span class="samp">,X</span></samp>’, ‘<samp><var>number</var><span class="samp">,Y</span></samp>’
<p>The <var>number</var> may be omitted in which case 0 is assumed.
<br><dt><dfn>Direct Addressing mode</dfn><dd>‘<samp><span class="samp">*</span><var>symbol</var></samp>’, or ‘<samp><span class="samp">*</span><var>digits</var></samp>’
<br><dt><dfn>Absolute</dfn><dd>‘<samp><var>symbol</var></samp>’, or ‘<samp><var>digits</var></samp>’
</dl>
<p>The M68HC12 has other more complex addressing modes. All of them
are supported and they are represented below:
<dl>
<dt><dfn>Constant Offset Indexed Addressing Mode</dfn><dd>‘<samp><var>number</var><span class="samp">,</span><var>reg</var></samp>’
<p>The <var>number</var> may be omitted in which case 0 is assumed.
The register can be either ‘<samp><span class="samp">X</span></samp>’, ‘<samp><span class="samp">Y</span></samp>’, ‘<samp><span class="samp">SP</span></samp>’ or
‘<samp><span class="samp">PC</span></samp>’. The assembler will use the smaller post-byte definition
according to the constant value (5-bit constant offset, 9-bit constant
offset or 16-bit constant offset). If the constant is not known by
the assembler it will use the 16-bit constant offset post-byte and the value
will be resolved at link time.
<br><dt><dfn>Offset Indexed Indirect</dfn><dd>‘<samp><span class="samp">[</span><var>number</var><span class="samp">,</span><var>reg</var><span class="samp">]</span></samp>’
<p>The register can be either ‘<samp><span class="samp">X</span></samp>’, ‘<samp><span class="samp">Y</span></samp>’, ‘<samp><span class="samp">SP</span></samp>’ or ‘<samp><span class="samp">PC</span></samp>’.
<br><dt><dfn>Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement</dfn><dd>‘<samp><var>number</var><span class="samp">,-</span><var>reg</var></samp>’
‘<samp><var>number</var><span class="samp">,+</span><var>reg</var></samp>’
‘<samp><var>number</var><span class="samp">,</span><var>reg</var><span class="samp">-</span></samp>’
‘<samp><var>number</var><span class="samp">,</span><var>reg</var><span class="samp">+</span></samp>’
<p>The number must be in the range ‘<samp><span class="samp">-8</span></samp>’..‘<samp><span class="samp">+8</span></samp>’ and must not be 0.
The register can be either ‘<samp><span class="samp">X</span></samp>’, ‘<samp><span class="samp">Y</span></samp>’, ‘<samp><span class="samp">SP</span></samp>’ or ‘<samp><span class="samp">PC</span></samp>’.
<br><dt><dfn>Accumulator Offset</dfn><dd>‘<samp><var>acc</var><span class="samp">,</span><var>reg</var></samp>’
<p>The accumulator register can be either ‘<samp><span class="samp">A</span></samp>’, ‘<samp><span class="samp">B</span></samp>’ or ‘<samp><span class="samp">D</span></samp>’.
The register can be either ‘<samp><span class="samp">X</span></samp>’, ‘<samp><span class="samp">Y</span></samp>’, ‘<samp><span class="samp">SP</span></samp>’ or ‘<samp><span class="samp">PC</span></samp>’.
<br><dt><dfn>Accumulator D offset indexed-indirect</dfn><dd>‘<samp><span class="samp">[D,</span><var>reg</var><span class="samp">]</span></samp>’
<p>The register can be either ‘<samp><span class="samp">X</span></samp>’, ‘<samp><span class="samp">Y</span></samp>’, ‘<samp><span class="samp">SP</span></samp>’ or ‘<samp><span class="samp">PC</span></samp>’.
</dl>
<p>For example:
<pre class="smallexample"> ldab 1024,sp
ldd [10,x]
orab 3,+x
stab -2,y-
ldx a,pc
sty [d,sp]
</pre>
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