-mcpu=processor[+extension...]arm1,
arm2,
arm250,
arm3,
arm6,
arm60,
arm600,
arm610,
arm620,
arm7,
arm7m,
arm7d,
arm7dm,
arm7di,
arm7dmi,
arm70,
arm700,
arm700i,
arm710,
arm710t,
arm720,
arm720t,
arm740t,
arm710c,
arm7100,
arm7500,
arm7500fe,
arm7t,
arm7tdmi,
arm7tdmi-s,
arm8,
arm810,
strongarm,
strongarm1,
strongarm110,
strongarm1100,
strongarm1110,
arm9,
arm920,
arm920t,
arm922t,
arm940t,
arm9tdmi,
fa526 (Faraday FA526 processor),
fa626 (Faraday FA626 processor),
arm9e,
arm926e,
arm926ej-s,
arm946e-r0,
arm946e,
arm946e-s,
arm966e-r0,
arm966e,
arm966e-s,
arm968e-s,
arm10t,
arm10tdmi,
arm10e,
arm1020,
arm1020t,
arm1020e,
arm1022e,
arm1026ej-s,
fa606te (Faraday FA606TE processor),
fa616te (Faraday FA616TE processor),
fa626te (Faraday FA626TE processor),
fmp626 (Faraday FMP626 processor),
fa726te (Faraday FA726TE processor),
arm1136j-s,
arm1136jf-s,
arm1156t2-s,
arm1156t2f-s,
arm1176jz-s,
arm1176jzf-s,
mpcore,
mpcorenovfp,
cortex-a5,
cortex-a7,
cortex-a8,
cortex-a9,
cortex-a15,
cortex-a35,
cortex-a53,
cortex-a57,
cortex-a72,
cortex-r4,
cortex-r4f,
cortex-r5,
cortex-r7,
cortex-m7,
cortex-m4,
cortex-m3,
cortex-m1,
cortex-m0,
cortex-m0plus,
exynos-m1,
marvell-pj4,
marvell-whitney,
qdf24xx,
xgene1,
xgene2,
ep9312 (ARM920 with Cirrus Maverick coprocessor),
i80200 (Intel XScale processor)
iwmmxt (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor)
and
xscale.
The special name all may be used to allow the
assembler to accept instructions valid for any ARM processor.
In addition to the basic instruction set, the assembler can be told to
accept various extension mnemonics that extend the processor using the
co-processor instruction space. For example, -mcpu=arm920+maverick
is equivalent to specifying -mcpu=ep9312.
Multiple extensions may be specified, separated by a +. The
extensions should be specified in ascending alphabetical order.
Some extensions may be restricted to particular architectures; this is documented in the list of extensions below.
Extension mnemonics may also be removed from those the assembler accepts.
This is done be prepending no to the option that adds the extension.
Extensions that are removed should be listed after all extensions which have
been added, again in ascending alphabetical order. For example,
-mcpu=ep9312+nomaverick is equivalent to specifying -mcpu=arm920.
The following extensions are currently supported:
crc
crypto (Cryptography Extensions for v8-A architecture, implies fp+simd),
fp (Floating Point Extensions for v8-A architecture),
idiv (Integer Divide Extensions for v7-A and v7-R architectures),
iwmmxt,
iwmmxt2,
xscale,
maverick,
mp (Multiprocessing Extensions for v7-A and v7-R
architectures),
os (Operating System for v6M architecture),
sec (Security Extensions for v6K and v7-A architectures),
simd (Advanced SIMD Extensions for v8-A architecture, implies fp),
virt (Virtualization Extensions for v7-A architecture, implies
idiv),
pan (Priviliged Access Never Extensions for v8-A architecture),
rdma (ARMv8.1 Advanced SIMD extensions for v8-A architecture, implies
simd)
and
xscale.
-march=architecture[+extension...]armv1,
armv2,
armv2a,
armv2s,
armv3,
armv3m,
armv4,
armv4xm,
armv4t,
armv4txm,
armv5,
armv5t,
armv5txm,
armv5te,
armv5texp,
armv6,
armv6j,
armv6k,
armv6z,
armv6kz,
armv6-m,
armv6s-m,
armv7,
armv7-a,
armv7ve,
armv7-r,
armv7-m,
armv7e-m,
armv8-a,
armv8.1-a,
iwmmxt
iwmmxt2
and
xscale.
If both -mcpu and
-march are specified, the assembler will use
the setting for -mcpu.
The architecture option can be extended with the same instruction set
extension options as the -mcpu option.
-mfpu=floating-point-formatsoftfpa,
fpe,
fpe2,
fpe3,
fpa,
fpa10,
fpa11,
arm7500fe,
softvfp,
softvfp+vfp,
vfp,
vfp10,
vfp10-r0,
vfp9,
vfpxd,
vfpv2,
vfpv3,
vfpv3-fp16,
vfpv3-d16,
vfpv3-d16-fp16,
vfpv3xd,
vfpv3xd-d16,
vfpv4,
vfpv4-d16,
fpv4-sp-d16,
fpv5-sp-d16,
fpv5-d16,
fp-armv8,
arm1020t,
arm1020e,
arm1136jf-s,
maverick,
neon,
neon-vfpv4,
neon-fp-armv8,
crypto-neon-fp-armv8,
neon-fp-armv8.1
and
crypto-neon-fp-armv8.1.
In addition to determining which instructions are assembled, this option
also affects the way in which the .double assembler directive behaves
when assembling little-endian code.
The default is dependent on the processor selected. For Architecture 5 or later, the default is to assembler for VFP instructions; for earlier architectures the default is to assemble for FPA instructions.
-mthumb.code 16 directive.
-mthumb-interwork-mimplicit-it=never-mimplicit-it=always-mimplicit-it=arm-mimplicit-it=thumb-mimplicit-it option controls the behavior of the assembler when
conditional instructions are not enclosed in IT blocks.
There are four possible behaviors.
If never is specified, such constructs cause a warning in ARM
code and an error in Thumb-2 code.
If always is specified, such constructs are accepted in both
ARM and Thumb-2 code, where the IT instruction is added implicitly.
If arm is specified, such constructs are accepted in ARM code
and cause an error in Thumb-2 code.
If thumb is specified, such constructs cause a warning in ARM
code and are accepted in Thumb-2 code. If you omit this option, the
behavior is equivalent to -mimplicit-it=arm.
-mapcs-26-mapcs-32-matpcs-mapcs-float-mapcs-reentrant-mfloat-abi=abisoft,
softfp
and
hard.
-meabi=vergnu,
4
and
5.
-EBNote: If a program is being built for a system with big-endian data and little-endian instructions then it should be assembled with the -EB option, (all of it, code and data) and then linked with the --be8 option. This will reverse the endianness of the instructions back to little-endian, but leave the data as big-endian.
-EL-k--fix-v4bxBX instructions in ARMv4 code. This is intended for use with
the linker option of the same name.
-mwarn-deprecated-mno-warn-deprecated-mccs-mwarn-syms-mno-warn-syms