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<li class="navelem"><a class="el" href="dir_ea9599923402ca8ab47fc3e495999dea.html">arch</a></li><li class="navelem"><a class="el" href="dir_9e929c73feaf15d3695ce4c76b483065.html">arm</a></li><li class="navelem"><a class="el" href="dir_58955c0f35a9c3d48181d2be53994c7b.html">SAME54</a></li><li class="navelem"><a class="el" href="dir_09e97e512ca7d4e6cd359f1c5497eeba.html">SAME54A</a></li><li class="navelem"><a class="el" href="dir_4b38d63e5c584a4d6c9001c789e1829f.html">mcu</a></li><li class="navelem"><a class="el" href="dir_d4fc57b996dc082ef023092a5b7d90fc.html">inc</a></li><li class="navelem"><a class="el" href="dir_92b117bae75cf16a05ca7611db29e9c7.html">instance</a></li> </ul>
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<div class="title">tcc0.h</div> </div>
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<a href="tcc0_8h.html">Go to the documentation of this file.</a><div class="fragment"><div class="line"><a name="l00001"></a><span class="lineno"> 1</span>  </div>
<div class="line"><a name="l00030"></a><span class="lineno"> 30</span> <span class="preprocessor">#ifndef _SAME54_TCC0_INSTANCE_</span></div>
<div class="line"><a name="l00031"></a><span class="lineno"> 31</span> <span class="preprocessor">#define _SAME54_TCC0_INSTANCE_</span></div>
<div class="line"><a name="l00032"></a><span class="lineno"> 32</span>  </div>
<div class="line"><a name="l00033"></a><span class="lineno"> 33</span> <span class="comment">/* ========== Register definition for TCC0 peripheral ========== */</span></div>
<div class="line"><a name="l00034"></a><span class="lineno"> 34</span> <span class="preprocessor">#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))</span></div>
<div class="line"><a name="l00035"></a><span class="lineno"> 35</span> <span class="preprocessor">#define REG_TCC0_CTRLA (0x41016000) </span></div>
<div class="line"><a name="l00036"></a><span class="lineno"> 36</span> <span class="preprocessor">#define REG_TCC0_CTRLBCLR (0x41016004) </span></div>
<div class="line"><a name="l00037"></a><span class="lineno"> 37</span> <span class="preprocessor">#define REG_TCC0_CTRLBSET (0x41016005) </span></div>
<div class="line"><a name="l00038"></a><span class="lineno"> 38</span> <span class="preprocessor">#define REG_TCC0_SYNCBUSY (0x41016008) </span></div>
<div class="line"><a name="l00039"></a><span class="lineno"> 39</span> <span class="preprocessor">#define REG_TCC0_FCTRLA (0x4101600C) </span></div>
<div class="line"><a name="l00040"></a><span class="lineno"> 40</span> <span class="preprocessor">#define REG_TCC0_FCTRLB (0x41016010) </span></div>
<div class="line"><a name="l00041"></a><span class="lineno"> 41</span> <span class="preprocessor">#define REG_TCC0_WEXCTRL (0x41016014) </span></div>
<div class="line"><a name="l00042"></a><span class="lineno"> 42</span> <span class="preprocessor">#define REG_TCC0_DRVCTRL (0x41016018) </span></div>
<div class="line"><a name="l00043"></a><span class="lineno"> 43</span> <span class="preprocessor">#define REG_TCC0_DBGCTRL (0x4101601E) </span></div>
<div class="line"><a name="l00044"></a><span class="lineno"> 44</span> <span class="preprocessor">#define REG_TCC0_EVCTRL (0x41016020) </span></div>
<div class="line"><a name="l00045"></a><span class="lineno"> 45</span> <span class="preprocessor">#define REG_TCC0_INTENCLR (0x41016024) </span></div>
<div class="line"><a name="l00046"></a><span class="lineno"> 46</span> <span class="preprocessor">#define REG_TCC0_INTENSET (0x41016028) </span></div>
<div class="line"><a name="l00047"></a><span class="lineno"> 47</span> <span class="preprocessor">#define REG_TCC0_INTFLAG (0x4101602C) </span></div>
<div class="line"><a name="l00048"></a><span class="lineno"> 48</span> <span class="preprocessor">#define REG_TCC0_STATUS (0x41016030) </span></div>
<div class="line"><a name="l00049"></a><span class="lineno"> 49</span> <span class="preprocessor">#define REG_TCC0_COUNT (0x41016034) </span></div>
<div class="line"><a name="l00050"></a><span class="lineno"> 50</span> <span class="preprocessor">#define REG_TCC0_PATT (0x41016038) </span></div>
<div class="line"><a name="l00051"></a><span class="lineno"> 51</span> <span class="preprocessor">#define REG_TCC0_WAVE (0x4101603C) </span></div>
<div class="line"><a name="l00052"></a><span class="lineno"> 52</span> <span class="preprocessor">#define REG_TCC0_PER (0x41016040) </span></div>
<div class="line"><a name="l00053"></a><span class="lineno"> 53</span> <span class="preprocessor">#define REG_TCC0_CC0 (0x41016044) </span></div>
<div class="line"><a name="l00054"></a><span class="lineno"> 54</span> <span class="preprocessor">#define REG_TCC0_CC1 (0x41016048) </span></div>
<div class="line"><a name="l00055"></a><span class="lineno"> 55</span> <span class="preprocessor">#define REG_TCC0_CC2 (0x4101604C) </span></div>
<div class="line"><a name="l00056"></a><span class="lineno"> 56</span> <span class="preprocessor">#define REG_TCC0_CC3 (0x41016050) </span></div>
<div class="line"><a name="l00057"></a><span class="lineno"> 57</span> <span class="preprocessor">#define REG_TCC0_CC4 (0x41016054) </span></div>
<div class="line"><a name="l00058"></a><span class="lineno"> 58</span> <span class="preprocessor">#define REG_TCC0_CC5 (0x41016058) </span></div>
<div class="line"><a name="l00059"></a><span class="lineno"> 59</span> <span class="preprocessor">#define REG_TCC0_PATTBUF (0x41016064) </span></div>
<div class="line"><a name="l00060"></a><span class="lineno"> 60</span> <span class="preprocessor">#define REG_TCC0_PERBUF (0x4101606C) </span></div>
<div class="line"><a name="l00061"></a><span class="lineno"> 61</span> <span class="preprocessor">#define REG_TCC0_CCBUF0 (0x41016070) </span></div>
<div class="line"><a name="l00062"></a><span class="lineno"> 62</span> <span class="preprocessor">#define REG_TCC0_CCBUF1 (0x41016074) </span></div>
<div class="line"><a name="l00063"></a><span class="lineno"> 63</span> <span class="preprocessor">#define REG_TCC0_CCBUF2 (0x41016078) </span></div>
<div class="line"><a name="l00064"></a><span class="lineno"> 64</span> <span class="preprocessor">#define REG_TCC0_CCBUF3 (0x4101607C) </span></div>
<div class="line"><a name="l00065"></a><span class="lineno"> 65</span> <span class="preprocessor">#define REG_TCC0_CCBUF4 (0x41016080) </span></div>
<div class="line"><a name="l00066"></a><span class="lineno"> 66</span> <span class="preprocessor">#define REG_TCC0_CCBUF5 (0x41016084) </span></div>
<div class="line"><a name="l00067"></a><span class="lineno"> 67</span> <span class="preprocessor">#else</span></div>
<div class="line"><a name="l00068"></a><span class="lineno"><a class="line" href="tcc0_8h.html#a1f56c0e830610bfc8c4301f63b813e80"> 68</a></span> <span class="preprocessor">#define REG_TCC0_CTRLA (*(RwReg *)0x41016000UL) </span></div>
<div class="line"><a name="l00069"></a><span class="lineno"><a class="line" href="tcc0_8h.html#a7167c4fcd469e66ad42c0a9265066eba"> 69</a></span> <span class="preprocessor">#define REG_TCC0_CTRLBCLR (*(RwReg8 *)0x41016004UL) </span></div>
<div class="line"><a name="l00070"></a><span class="lineno"><a class="line" href="tcc0_8h.html#a9f91f7fd473ef30569ad9c748864f3c1"> 70</a></span> <span class="preprocessor">#define REG_TCC0_CTRLBSET (*(RwReg8 *)0x41016005UL) </span></div>
<div class="line"><a name="l00071"></a><span class="lineno"><a class="line" href="tcc0_8h.html#ad12e74951448d865aecf208fb76d46c7"> 71</a></span> <span class="preprocessor">#define REG_TCC0_SYNCBUSY (*(RoReg *)0x41016008UL) </span></div>
<div class="line"><a name="l00072"></a><span class="lineno"><a class="line" href="tcc0_8h.html#ab3d8e37144c8544c57de2f9354881af6"> 72</a></span> <span class="preprocessor">#define REG_TCC0_FCTRLA (*(RwReg *)0x4101600CUL) </span></div>
<div class="line"><a name="l00073"></a><span class="lineno"><a class="line" href="tcc0_8h.html#a3e82b63cd5b5717afdb8a5367600ab35"> 73</a></span> <span class="preprocessor">#define REG_TCC0_FCTRLB (*(RwReg *)0x41016010UL) </span></div>
<div class="line"><a name="l00074"></a><span class="lineno"><a class="line" href="tcc0_8h.html#a3b3702b80c2ea5b0b6c96e235ba3fd47"> 74</a></span> <span class="preprocessor">#define REG_TCC0_WEXCTRL (*(RwReg *)0x41016014UL) </span></div>
<div class="line"><a name="l00075"></a><span class="lineno"><a class="line" href="tcc0_8h.html#a7012404b12accd00d325f7d44f47d201"> 75</a></span> <span class="preprocessor">#define REG_TCC0_DRVCTRL (*(RwReg *)0x41016018UL) </span></div>
<div class="line"><a name="l00076"></a><span class="lineno"><a class="line" href="tcc0_8h.html#a12089f69737b0d173085cd9a10a39007"> 76</a></span> <span class="preprocessor">#define REG_TCC0_DBGCTRL (*(RwReg8 *)0x4101601EUL) </span></div>
<div class="line"><a name="l00077"></a><span class="lineno"><a class="line" href="tcc0_8h.html#a291dc420fe89a8f64b5f7595fff350ce"> 77</a></span> <span class="preprocessor">#define REG_TCC0_EVCTRL (*(RwReg *)0x41016020UL) </span></div>
<div class="line"><a name="l00078"></a><span class="lineno"><a class="line" href="tcc0_8h.html#a4a8085ad41af940842d4e6fa315e64b8"> 78</a></span> <span class="preprocessor">#define REG_TCC0_INTENCLR (*(RwReg *)0x41016024UL) </span></div>
<div class="line"><a name="l00079"></a><span class="lineno"><a class="line" href="tcc0_8h.html#a16fcec76af657a3e9bebb6fe67fc691d"> 79</a></span> <span class="preprocessor">#define REG_TCC0_INTENSET (*(RwReg *)0x41016028UL) </span></div>
<div class="line"><a name="l00080"></a><span class="lineno"><a class="line" href="tcc0_8h.html#ad7cfbcbbf271b717b5aad74559a82591"> 80</a></span> <span class="preprocessor">#define REG_TCC0_INTFLAG (*(RwReg *)0x4101602CUL) </span></div>
<div class="line"><a name="l00081"></a><span class="lineno"><a class="line" href="tcc0_8h.html#aed82ff5ae8800131c9024713723432ea"> 81</a></span> <span class="preprocessor">#define REG_TCC0_STATUS (*(RwReg *)0x41016030UL) </span></div>
<div class="line"><a name="l00082"></a><span class="lineno"><a class="line" href="tcc0_8h.html#ad4ec4b4914420f77e12894d137675e56"> 82</a></span> <span class="preprocessor">#define REG_TCC0_COUNT (*(RwReg *)0x41016034UL) </span></div>
<div class="line"><a name="l00083"></a><span class="lineno"><a class="line" href="tcc0_8h.html#a5d6e3f0ebf014ee8f418c4ecb2db0411"> 83</a></span> <span class="preprocessor">#define REG_TCC0_PATT (*(RwReg16*)0x41016038UL) </span></div>
<div class="line"><a name="l00084"></a><span class="lineno"><a class="line" href="tcc0_8h.html#a75eec947876d33c20b90d58491ddbd1d"> 84</a></span> <span class="preprocessor">#define REG_TCC0_WAVE (*(RwReg *)0x4101603CUL) </span></div>
<div class="line"><a name="l00085"></a><span class="lineno"><a class="line" href="tcc0_8h.html#a13d1251e032783cf584cc130fa076293"> 85</a></span> <span class="preprocessor">#define REG_TCC0_PER (*(RwReg *)0x41016040UL) </span></div>
<div class="line"><a name="l00086"></a><span class="lineno"><a class="line" href="tcc0_8h.html#a7c2ef52bf209e4b62b948805d8697625"> 86</a></span> <span class="preprocessor">#define REG_TCC0_CC0 (*(RwReg *)0x41016044UL) </span></div>
<div class="line"><a name="l00087"></a><span class="lineno"><a class="line" href="tcc0_8h.html#a93e21d3c17fde3639b32a4d0afe7533e"> 87</a></span> <span class="preprocessor">#define REG_TCC0_CC1 (*(RwReg *)0x41016048UL) </span></div>
<div class="line"><a name="l00088"></a><span class="lineno"><a class="line" href="tcc0_8h.html#ae6b036c8155abdc365a3a38acb546578"> 88</a></span> <span class="preprocessor">#define REG_TCC0_CC2 (*(RwReg *)0x4101604CUL) </span></div>
<div class="line"><a name="l00089"></a><span class="lineno"><a class="line" href="tcc0_8h.html#abde7ae0589f3b0235df287b0909c49c2"> 89</a></span> <span class="preprocessor">#define REG_TCC0_CC3 (*(RwReg *)0x41016050UL) </span></div>
<div class="line"><a name="l00090"></a><span class="lineno"><a class="line" href="tcc0_8h.html#ae76bb63302e1c7839f49949104f49903"> 90</a></span> <span class="preprocessor">#define REG_TCC0_CC4 (*(RwReg *)0x41016054UL) </span></div>
<div class="line"><a name="l00091"></a><span class="lineno"><a class="line" href="tcc0_8h.html#a6224fc2b6d08d337e0ced80a9a50f5fc"> 91</a></span> <span class="preprocessor">#define REG_TCC0_CC5 (*(RwReg *)0x41016058UL) </span></div>
<div class="line"><a name="l00092"></a><span class="lineno"><a class="line" href="tcc0_8h.html#a32d55e4742123cf33bf5884f83879327"> 92</a></span> <span class="preprocessor">#define REG_TCC0_PATTBUF (*(RwReg16*)0x41016064UL) </span></div>
<div class="line"><a name="l00093"></a><span class="lineno"><a class="line" href="tcc0_8h.html#a6b20471c3267dcd031402672c81f8561"> 93</a></span> <span class="preprocessor">#define REG_TCC0_PERBUF (*(RwReg *)0x4101606CUL) </span></div>
<div class="line"><a name="l00094"></a><span class="lineno"><a class="line" href="tcc0_8h.html#a6865ea9f3c0e33000830919d2a1de6ea"> 94</a></span> <span class="preprocessor">#define REG_TCC0_CCBUF0 (*(RwReg *)0x41016070UL) </span></div>
<div class="line"><a name="l00095"></a><span class="lineno"><a class="line" href="tcc0_8h.html#a7587dcb903166da29fcba9c7102252ce"> 95</a></span> <span class="preprocessor">#define REG_TCC0_CCBUF1 (*(RwReg *)0x41016074UL) </span></div>
<div class="line"><a name="l00096"></a><span class="lineno"><a class="line" href="tcc0_8h.html#aa6c9470a8d907f45fbc5bbf3f20116b7"> 96</a></span> <span class="preprocessor">#define REG_TCC0_CCBUF2 (*(RwReg *)0x41016078UL) </span></div>
<div class="line"><a name="l00097"></a><span class="lineno"><a class="line" href="tcc0_8h.html#a0662625f279bdcbd05796b8b4bc39406"> 97</a></span> <span class="preprocessor">#define REG_TCC0_CCBUF3 (*(RwReg *)0x4101607CUL) </span></div>
<div class="line"><a name="l00098"></a><span class="lineno"><a class="line" href="tcc0_8h.html#aa98a9dc105ee92a7d5a6cdd94c92991b"> 98</a></span> <span class="preprocessor">#define REG_TCC0_CCBUF4 (*(RwReg *)0x41016080UL) </span></div>
<div class="line"><a name="l00099"></a><span class="lineno"><a class="line" href="tcc0_8h.html#acacaefe8c7e65e2c112b4d6c5ba7a9a9"> 99</a></span> <span class="preprocessor">#define REG_TCC0_CCBUF5 (*(RwReg *)0x41016084UL) </span></div>
<div class="line"><a name="l00100"></a><span class="lineno"> 100</span> <span class="preprocessor">#endif </span><span class="comment">/* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */</span><span class="preprocessor"></span></div>
<div class="line"><a name="l00101"></a><span class="lineno"> 101</span>  </div>
<div class="line"><a name="l00102"></a><span class="lineno"> 102</span> <span class="comment">/* ========== Instance parameters for TCC0 peripheral ========== */</span></div>
<div class="line"><a name="l00103"></a><span class="lineno"> 103</span> <span class="preprocessor">#define TCC0_CC_NUM 6 // Number of Compare/Capture units</span></div>
<div class="line"><a name="l00104"></a><span class="lineno"> 104</span> <span class="preprocessor">#define TCC0_DITHERING 1 // Dithering feature implemented</span></div>
<div class="line"><a name="l00105"></a><span class="lineno"> 105</span> <span class="preprocessor">#define TCC0_DMAC_ID_MC_0 23</span></div>
<div class="line"><a name="l00106"></a><span class="lineno"> 106</span> <span class="preprocessor">#define TCC0_DMAC_ID_MC_1 24</span></div>
<div class="line"><a name="l00107"></a><span class="lineno"> 107</span> <span class="preprocessor">#define TCC0_DMAC_ID_MC_2 25</span></div>
<div class="line"><a name="l00108"></a><span class="lineno"> 108</span> <span class="preprocessor">#define TCC0_DMAC_ID_MC_3 26</span></div>
<div class="line"><a name="l00109"></a><span class="lineno"> 109</span> <span class="preprocessor">#define TCC0_DMAC_ID_MC_4 27</span></div>
<div class="line"><a name="l00110"></a><span class="lineno"> 110</span> <span class="preprocessor">#define TCC0_DMAC_ID_MC_5 28</span></div>
<div class="line"><a name="l00111"></a><span class="lineno"> 111</span> <span class="preprocessor">#define TCC0_DMAC_ID_MC_LSB 23</span></div>
<div class="line"><a name="l00112"></a><span class="lineno"> 112</span> <span class="preprocessor">#define TCC0_DMAC_ID_MC_MSB 28</span></div>
<div class="line"><a name="l00113"></a><span class="lineno"> 113</span> <span class="preprocessor">#define TCC0_DMAC_ID_MC_SIZE 6</span></div>
<div class="line"><a name="l00114"></a><span class="lineno"> 114</span> <span class="preprocessor">#define TCC0_DMAC_ID_OVF 22 // DMA overflow/underflow/retrigger trigger</span></div>
<div class="line"><a name="l00115"></a><span class="lineno"> 115</span> <span class="preprocessor">#define TCC0_DTI 1 // Dead-Time-Insertion feature implemented</span></div>
<div class="line"><a name="l00116"></a><span class="lineno"> 116</span> <span class="preprocessor">#define TCC0_EXT 31 // Coding of implemented extended features</span></div>
<div class="line"><a name="l00117"></a><span class="lineno"> 117</span> <span class="preprocessor">#define TCC0_GCLK_ID 25 // Index of Generic Clock</span></div>
<div class="line"><a name="l00118"></a><span class="lineno"> 118</span> <span class="preprocessor">#define TCC0_MASTER_SLAVE_MODE 1 // TCC type 0 : NA, 1 : Master, 2 : Slave</span></div>
<div class="line"><a name="l00119"></a><span class="lineno"> 119</span> <span class="preprocessor">#define TCC0_OTMX 1 // Output Matrix feature implemented</span></div>
<div class="line"><a name="l00120"></a><span class="lineno"> 120</span> <span class="preprocessor">#define TCC0_OW_NUM 8 // Number of Output Waveforms</span></div>
<div class="line"><a name="l00121"></a><span class="lineno"> 121</span> <span class="preprocessor">#define TCC0_PG 1 // Pattern Generation feature implemented</span></div>
<div class="line"><a name="l00122"></a><span class="lineno"> 122</span> <span class="preprocessor">#define TCC0_SIZE 24 </span></div>
<div class="line"><a name="l00123"></a><span class="lineno"> 123</span> <span class="preprocessor">#define TCC0_SWAP 1 // DTI outputs swap feature implemented</span></div>
<div class="line"><a name="l00124"></a><span class="lineno"> 124</span>  </div>
<div class="line"><a name="l00125"></a><span class="lineno"> 125</span> <span class="preprocessor">#endif </span><span class="comment">/* _SAME54_TCC0_INSTANCE_ */</span><span class="preprocessor"></span></div>
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