doc/html/tc1_8h_source.html

#ifndef _SAME54_TC1_INSTANCE_

#define _SAME54_TC1_INSTANCE_


/* ========== Register definition for TC1 peripheral ========== */

#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

#define REG_TC1_CTRLA              (0x40003C00)

#define REG_TC1_CTRLBCLR           (0x40003C04)

#define REG_TC1_CTRLBSET           (0x40003C05)

#define REG_TC1_EVCTRL             (0x40003C06)

#define REG_TC1_INTENCLR           (0x40003C08)

#define REG_TC1_INTENSET           (0x40003C09)

#define REG_TC1_INTFLAG            (0x40003C0A)

#define REG_TC1_STATUS             (0x40003C0B)

#define REG_TC1_WAVE               (0x40003C0C)

#define REG_TC1_DRVCTRL            (0x40003C0D)

#define REG_TC1_DBGCTRL            (0x40003C0F)

#define REG_TC1_SYNCBUSY           (0x40003C10)

#define REG_TC1_COUNT16_COUNT      (0x40003C14)

#define REG_TC1_COUNT16_CC0        (0x40003C1C)

#define REG_TC1_COUNT16_CC1        (0x40003C1E)

#define REG_TC1_COUNT16_CCBUF0     (0x40003C30)

#define REG_TC1_COUNT16_CCBUF1     (0x40003C32)

#define REG_TC1_COUNT32_COUNT      (0x40003C14)

#define REG_TC1_COUNT32_CC0        (0x40003C1C)

#define REG_TC1_COUNT32_CC1        (0x40003C20)

#define REG_TC1_COUNT32_CCBUF0     (0x40003C30)

#define REG_TC1_COUNT32_CCBUF1     (0x40003C34)

#define REG_TC1_COUNT8_COUNT       (0x40003C14)

#define REG_TC1_COUNT8_PER         (0x40003C1B)

#define REG_TC1_COUNT8_CC0         (0x40003C1C)

#define REG_TC1_COUNT8_CC1         (0x40003C1D)

#define REG_TC1_COUNT8_PERBUF      (0x40003C2F)

#define REG_TC1_COUNT8_CCBUF0      (0x40003C30)

#define REG_TC1_COUNT8_CCBUF1      (0x40003C31)

#else

#define REG_TC1_CTRLA              (*(RwReg  *)0x40003C00UL)

#define REG_TC1_CTRLBCLR           (*(RwReg8 *)0x40003C04UL)

#define REG_TC1_CTRLBSET           (*(RwReg8 *)0x40003C05UL)

#define REG_TC1_EVCTRL             (*(RwReg16*)0x40003C06UL)

#define REG_TC1_INTENCLR           (*(RwReg8 *)0x40003C08UL)

#define REG_TC1_INTENSET           (*(RwReg8 *)0x40003C09UL)

#define REG_TC1_INTFLAG            (*(RwReg8 *)0x40003C0AUL)

#define REG_TC1_STATUS             (*(RwReg8 *)0x40003C0BUL)

#define REG_TC1_WAVE               (*(RwReg8 *)0x40003C0CUL)

#define REG_TC1_DRVCTRL            (*(RwReg8 *)0x40003C0DUL)

#define REG_TC1_DBGCTRL            (*(RwReg8 *)0x40003C0FUL)

#define REG_TC1_SYNCBUSY           (*(RoReg  *)0x40003C10UL)

#define REG_TC1_COUNT16_COUNT      (*(RwReg16*)0x40003C14UL)

#define REG_TC1_COUNT16_CC0        (*(RwReg16*)0x40003C1CUL)

#define REG_TC1_COUNT16_CC1        (*(RwReg16*)0x40003C1EUL)

#define REG_TC1_COUNT16_CCBUF0     (*(RwReg16*)0x40003C30UL)

#define REG_TC1_COUNT16_CCBUF1     (*(RwReg16*)0x40003C32UL)

#define REG_TC1_COUNT32_COUNT      (*(RwReg  *)0x40003C14UL)

#define REG_TC1_COUNT32_CC0        (*(RwReg  *)0x40003C1CUL)

#define REG_TC1_COUNT32_CC1        (*(RwReg  *)0x40003C20UL)

#define REG_TC1_COUNT32_CCBUF0     (*(RwReg  *)0x40003C30UL)

#define REG_TC1_COUNT32_CCBUF1     (*(RwReg  *)0x40003C34UL)

#define REG_TC1_COUNT8_COUNT       (*(RwReg8 *)0x40003C14UL)

#define REG_TC1_COUNT8_PER         (*(RwReg8 *)0x40003C1BUL)

#define REG_TC1_COUNT8_CC0         (*(RwReg8 *)0x40003C1CUL)

#define REG_TC1_COUNT8_CC1         (*(RwReg8 *)0x40003C1DUL)

#define REG_TC1_COUNT8_PERBUF      (*(RwReg8 *)0x40003C2FUL)

#define REG_TC1_COUNT8_CCBUF0      (*(RwReg8 *)0x40003C30UL)

#define REG_TC1_COUNT8_CCBUF1      (*(RwReg8 *)0x40003C31UL)

#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */


/* ========== Instance parameters for TC1 peripheral ========== */

#define TC1_CC_NUM                  2

#define TC1_DMAC_ID_MC_0            48

#define TC1_DMAC_ID_MC_1            49

#define TC1_DMAC_ID_MC_LSB          48

#define TC1_DMAC_ID_MC_MSB          49

#define TC1_DMAC_ID_MC_SIZE         2

#define TC1_DMAC_ID_OVF             47       // Indexes of DMA Overflow trigger

#define TC1_EXT                     0        // Coding of implemented extended features (keep 0 value)

#define TC1_GCLK_ID                 9        // Index of Generic Clock

#define TC1_MASTER_SLAVE_MODE       2        // TC type 0 : NA, 1 : Master, 2 : Slave

#define TC1_OW_NUM                  2        // Number of Output Waveforms


#endif /* _SAME54_TC1_INSTANCE_ */