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<h5 class="subsubsection">9.38.3.4 Instruction Formats</h5>
<p><a name="index-instruction-formats_002c-s390-1897"></a><a name="index-s390-instruction-formats-1898"></a>
The Principles of Operation manuals lists 26 instruction formats where
some of the formats have multiple variants. For the ‘<samp><span class="samp">.insn</span></samp>’
pseudo directive the assembler recognizes some of the formats.
Typically, the most general variant of the instruction format is used
by the ‘<samp><span class="samp">.insn</span></samp>’ directive.
<p>The following table lists the abbreviations used in the table of
instruction formats:
<pre class="display">
<p><table summary=""><tr align="left"><td valign="top">OpCode / OpCd </td><td valign="top">Part of the op code.
<br></td></tr><tr align="left"><td valign="top">Bx </td><td valign="top">Base register number for operand x.
<br></td></tr><tr align="left"><td valign="top">Dx </td><td valign="top">Displacement for operand x.
<br></td></tr><tr align="left"><td valign="top">DLx </td><td valign="top">Displacement lower 12 bits for operand x.
<br></td></tr><tr align="left"><td valign="top">DHx </td><td valign="top">Displacement higher 8-bits for operand x.
<br></td></tr><tr align="left"><td valign="top">Rx </td><td valign="top">Register number for operand x.
<br></td></tr><tr align="left"><td valign="top">Xx </td><td valign="top">Index register number for operand x.
<br></td></tr><tr align="left"><td valign="top">Ix </td><td valign="top">Signed immediate for operand x.
<br></td></tr><tr align="left"><td valign="top">Ux </td><td valign="top">Unsigned immediate for operand x.
<br></td></tr></table>
</pre>
<p>An instruction is two, four, or six bytes in length and must be aligned
on a 2 byte boundary. The first two bits of the instruction specify the
length of the instruction, 00 indicates a two byte instruction, 01 and 10
indicates a four byte instruction, and 11 indicates a six byte instruction.
<p>The following table lists the s390 instruction formats that are available
with the ‘<samp><span class="samp">.insn</span></samp>’ pseudo directive:
<dl>
<dt><code>E format</code><dd><pre class="verbatim"> +-------------+
| OpCode |
+-------------+
0 15
</pre>
<br><dt><code>RI format: <insn> R1,I2</code><dd><pre class="verbatim"> +--------+----+----+------------------+
| OpCode | R1 |OpCd| I2 |
+--------+----+----+------------------+
0 8 12 16 31
</pre>
<br><dt><code>RIE format: <insn> R1,R3,I2</code><dd><pre class="verbatim"> +--------+----+----+------------------+--------+--------+
| OpCode | R1 | R3 | I2 |////////| OpCode |
+--------+----+----+------------------+--------+--------+
0 8 12 16 32 40 47
</pre>
<br><dt><code>RIL format: <insn> R1,I2</code><dd><pre class="verbatim"> +--------+----+----+------------------------------------+
| OpCode | R1 |OpCd| I2 |
+--------+----+----+------------------------------------+
0 8 12 16 47
</pre>
<br><dt><code>RILU format: <insn> R1,U2</code><dd><pre class="verbatim"> +--------+----+----+------------------------------------+
| OpCode | R1 |OpCd| U2 |
+--------+----+----+------------------------------------+
0 8 12 16 47
</pre>
<br><dt><code>RIS format: <insn> R1,I2,M3,D4(B4)</code><dd><pre class="verbatim"> +--------+----+----+----+-------------+--------+--------+
| OpCode | R1 | M3 | B4 | D4 | I2 | Opcode |
+--------+----+----+----+-------------+--------+--------+
0 8 12 16 20 32 36 47
</pre>
<br><dt><code>RR format: <insn> R1,R2</code><dd><pre class="verbatim"> +--------+----+----+
| OpCode | R1 | R2 |
+--------+----+----+
0 8 12 15
</pre>
<br><dt><code>RRE format: <insn> R1,R2</code><dd><pre class="verbatim"> +------------------+--------+----+----+
| OpCode |////////| R1 | R2 |
+------------------+--------+----+----+
0 16 24 28 31
</pre>
<br><dt><code>RRF format: <insn> R1,R2,R3,M4</code><dd><pre class="verbatim"> +------------------+----+----+----+----+
| OpCode | R3 | M4 | R1 | R2 |
+------------------+----+----+----+----+
0 16 20 24 28 31
</pre>
<br><dt><code>RRS format: <insn> R1,R2,M3,D4(B4)</code><dd><pre class="verbatim"> +--------+----+----+----+-------------+----+----+--------+
| OpCode | R1 | R3 | B4 | D4 | M3 |////| OpCode |
+--------+----+----+----+-------------+----+----+--------+
0 8 12 16 20 32 36 40 47
</pre>
<br><dt><code>RS format: <insn> R1,R3,D2(B2)</code><dd><pre class="verbatim"> +--------+----+----+----+-------------+
| OpCode | R1 | R3 | B2 | D2 |
+--------+----+----+----+-------------+
0 8 12 16 20 31
</pre>
<br><dt><code>RSE format: <insn> R1,R3,D2(B2)</code><dd><pre class="verbatim"> +--------+----+----+----+-------------+--------+--------+
| OpCode | R1 | R3 | B2 | D2 |////////| OpCode |
+--------+----+----+----+-------------+--------+--------+
0 8 12 16 20 32 40 47
</pre>
<br><dt><code>RSI format: <insn> R1,R3,I2</code><dd><pre class="verbatim"> +--------+----+----+------------------------------------+
| OpCode | R1 | R3 | I2 |
+--------+----+----+------------------------------------+
0 8 12 16 47
</pre>
<br><dt><code>RSY format: <insn> R1,R3,D2(B2)</code><dd><pre class="verbatim"> +--------+----+----+----+-------------+--------+--------+
| OpCode | R1 | R3 | B2 | DL2 | DH2 | OpCode |
+--------+----+----+----+-------------+--------+--------+
0 8 12 16 20 32 40 47
</pre>
<br><dt><code>RX format: <insn> R1,D2(X2,B2)</code><dd><pre class="verbatim"> +--------+----+----+----+-------------+
| OpCode | R1 | X2 | B2 | D2 |
+--------+----+----+----+-------------+
0 8 12 16 20 31
</pre>
<br><dt><code>RXE format: <insn> R1,D2(X2,B2)</code><dd><pre class="verbatim"> +--------+----+----+----+-------------+--------+--------+
| OpCode | R1 | X2 | B2 | D2 |////////| OpCode |
+--------+----+----+----+-------------+--------+--------+
0 8 12 16 20 32 40 47
</pre>
<br><dt><code>RXF format: <insn> R1,R3,D2(X2,B2)</code><dd><pre class="verbatim"> +--------+----+----+----+-------------+----+---+--------+
| OpCode | R3 | X2 | B2 | D2 | R1 |///| OpCode |
+--------+----+----+----+-------------+----+---+--------+
0 8 12 16 20 32 36 40 47
</pre>
<br><dt><code>RXY format: <insn> R1,D2(X2,B2)</code><dd><pre class="verbatim"> +--------+----+----+----+-------------+--------+--------+
| OpCode | R1 | X2 | B2 | DL2 | DH2 | OpCode |
+--------+----+----+----+-------------+--------+--------+
0 8 12 16 20 32 36 40 47
</pre>
<br><dt><code>S format: <insn> D2(B2)</code><dd><pre class="verbatim"> +------------------+----+-------------+
| OpCode | B2 | D2 |
+------------------+----+-------------+
0 16 20 31
</pre>
<br><dt><code>SI format: <insn> D1(B1),I2</code><dd><pre class="verbatim"> +--------+---------+----+-------------+
| OpCode | I2 | B1 | D1 |
+--------+---------+----+-------------+
0 8 16 20 31
</pre>
<br><dt><code>SIY format: <insn> D1(B1),U2</code><dd><pre class="verbatim"> +--------+---------+----+-------------+--------+--------+
| OpCode | I2 | B1 | DL1 | DH1 | OpCode |
+--------+---------+----+-------------+--------+--------+
0 8 16 20 32 36 40 47
</pre>
<br><dt><code>SIL format: <insn> D1(B1),I2</code><dd><pre class="verbatim"> +------------------+----+-------------+-----------------+
| OpCode | B1 | D1 | I2 |
+------------------+----+-------------+-----------------+
0 16 20 32 47
</pre>
<br><dt><code>SS format: <insn> D1(R1,B1),D2(B3),R3</code><dd><pre class="verbatim"> +--------+----+----+----+-------------+----+------------+
| OpCode | R1 | R3 | B1 | D1 | B2 | D2 |
+--------+----+----+----+-------------+----+------------+
0 8 12 16 20 32 36 47
</pre>
<br><dt><code>SSE format: <insn> D1(B1),D2(B2)</code><dd><pre class="verbatim"> +------------------+----+-------------+----+------------+
| OpCode | B1 | D1 | B2 | D2 |
+------------------+----+-------------+----+------------+
0 8 12 16 20 32 36 47
</pre>
<br><dt><code>SSF format: <insn> D1(B1),D2(B2),R3</code><dd><pre class="verbatim"> +--------+----+----+----+-------------+----+------------+
| OpCode | R3 |OpCd| B1 | D1 | B2 | D2 |
+--------+----+----+----+-------------+----+------------+
0 8 12 16 20 32 36 47
</pre>
</dl>
<p>For the complete list of all instruction format variants see the
Principles of Operation manuals.
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