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<h5 class="subsubsection">9.38.3.2 Instruction Mnemonics</h5>
<p><a name="index-instruction-mnemonics_002c-s390-1893"></a><a name="index-s390-instruction-mnemonics-1894"></a>
All instructions documented in the Principles of Operation are supported
with the mnemonic and order of operands as described.
The instruction mnemonic identifies the instruction format
(<a href="s390-Formats.html#s390-Formats">s390 Formats</a>) and the specific operation code for the instruction.
For example, the ‘<samp><span class="samp">lr</span></samp>’ mnemonic denotes the instruction format ‘<samp><span class="samp">RR</span></samp>’
with the operation code ‘<samp><span class="samp">0x18</span></samp>’.
<p>The definition of the various mnemonics follows a scheme, where the first
character usually hint at the type of the instruction:
<pre class="display">
<p><table summary=""><tr align="left"><td valign="top">a </td><td valign="top">add instruction, for example ‘<samp><span class="samp">al</span></samp>’ for add logical 32-bit
<br></td></tr><tr align="left"><td valign="top">b </td><td valign="top">branch instruction, for example ‘<samp><span class="samp">bc</span></samp>’ for branch on condition
<br></td></tr><tr align="left"><td valign="top">c </td><td valign="top">compare or convert instruction, for example ‘<samp><span class="samp">cr</span></samp>’ for compare
register 32-bit
<br></td></tr><tr align="left"><td valign="top">d </td><td valign="top">divide instruction, for example ‘<samp><span class="samp">dlr</span></samp>’ devide logical register
64-bit to 32-bit
<br></td></tr><tr align="left"><td valign="top">i </td><td valign="top">insert instruction, for example ‘<samp><span class="samp">ic</span></samp>’ insert character
<br></td></tr><tr align="left"><td valign="top">l </td><td valign="top">load instruction, for example ‘<samp><span class="samp">ltr</span></samp>’ load and test register
<br></td></tr><tr align="left"><td valign="top">mv </td><td valign="top">move instruction, for example ‘<samp><span class="samp">mvc</span></samp>’ move character
<br></td></tr><tr align="left"><td valign="top">m </td><td valign="top">multiply instruction, for example ‘<samp><span class="samp">mh</span></samp>’ multiply halfword
<br></td></tr><tr align="left"><td valign="top">n </td><td valign="top">and instruction, for example ‘<samp><span class="samp">ni</span></samp>’ and immediate
<br></td></tr><tr align="left"><td valign="top">o </td><td valign="top">or instruction, for example ‘<samp><span class="samp">oc</span></samp>’ or character
<br></td></tr><tr align="left"><td valign="top">sla, sll </td><td valign="top">shift left single instruction
<br></td></tr><tr align="left"><td valign="top">sra, srl </td><td valign="top">shift right single instruction
<br></td></tr><tr align="left"><td valign="top">st </td><td valign="top">store instruction, for example ‘<samp><span class="samp">stm</span></samp>’ store multiple
<br></td></tr><tr align="left"><td valign="top">s </td><td valign="top">subtract instruction, for example ‘<samp><span class="samp">slr</span></samp>’ subtract
logical 32-bit
<br></td></tr><tr align="left"><td valign="top">t </td><td valign="top">test or translate instruction, of example ‘<samp><span class="samp">tm</span></samp>’ test under mask
<br></td></tr><tr align="left"><td valign="top">x </td><td valign="top">exclusive or instruction, for example ‘<samp><span class="samp">xc</span></samp>’ exclusive or
character
<br></td></tr></table>
</pre>
<p>Certain characters at the end of the mnemonic may describe a property
of the instruction:
<pre class="display">
<p><table summary=""><tr align="left"><td valign="top">c </td><td valign="top">the instruction uses a 8-bit character operand
<br></td></tr><tr align="left"><td valign="top">f </td><td valign="top">the instruction extends a 32-bit operand to 64 bit
<br></td></tr><tr align="left"><td valign="top">g </td><td valign="top">the operands are treated as 64-bit values
<br></td></tr><tr align="left"><td valign="top">h </td><td valign="top">the operand uses a 16-bit halfword operand
<br></td></tr><tr align="left"><td valign="top">i </td><td valign="top">the instruction uses an immediate operand
<br></td></tr><tr align="left"><td valign="top">l </td><td valign="top">the instruction uses unsigned, logical operands
<br></td></tr><tr align="left"><td valign="top">m </td><td valign="top">the instruction uses a mask or operates on multiple values
<br></td></tr><tr align="left"><td valign="top">r </td><td valign="top">if r is the last character, the instruction operates on registers
<br></td></tr><tr align="left"><td valign="top">y </td><td valign="top">the instruction uses 20-bit displacements
<br></td></tr></table>
</pre>
<p>There are many exceptions to the scheme outlined in the above lists, in
particular for the priviledged instructions. For non-priviledged
instruction it works quite well, for example the instruction ‘<samp><span class="samp">clgfr</span></samp>’
c: compare instruction, l: unsigned operands, g: 64-bit operands,
f: 32- to 64-bit extension, r: register operands. The instruction compares
an 64-bit value in a register with the zero extended 32-bit value from
a second register.
For a complete list of all mnemonics see appendix B in the Principles
of Operation.
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