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<h4 class="subsection">9.23.3 Motorola Syntax</h4>
<p><a name="index-Motorola-syntax-for-the-680x0-1359"></a><a name="index-alternate-syntax-for-the-680x0-1360"></a>
The standard Motorola syntax for this chip differs from the syntax
already discussed (see <a href="M68K_002dSyntax.html#M68K_002dSyntax">Syntax</a>). <code>as</code> can
accept Motorola syntax for operands, even if <span class="sc">mit</span> syntax is used for
other operands in the same instruction. The two kinds of syntax are
fully compatible.
<p>In the following table <var>apc</var> stands for any of the address registers
(‘<samp><span class="samp">%a0</span></samp>’ through ‘<samp><span class="samp">%a7</span></samp>’), the program counter (‘<samp><span class="samp">%pc</span></samp>’), the
zero-address relative to the program counter (‘<samp><span class="samp">%zpc</span></samp>’), or a
suppressed address register (‘<samp><span class="samp">%za0</span></samp>’ through ‘<samp><span class="samp">%za7</span></samp>’). The use
of <var>size</var> means one of ‘<samp><span class="samp">w</span></samp>’ or ‘<samp><span class="samp">l</span></samp>’, and it may always be
omitted along with the leading dot. The use of <var>scale</var> means one of
‘<samp><span class="samp">1</span></samp>’, ‘<samp><span class="samp">2</span></samp>’, ‘<samp><span class="samp">4</span></samp>’, or ‘<samp><span class="samp">8</span></samp>’, and it may always be omitted
along with the leading asterisk.
<p>The following additional addressing modes are understood:
<dl>
<dt><dfn>Address Register Indirect</dfn><dd>‘<samp><span class="samp">(%a0)</span></samp>’ through ‘<samp><span class="samp">(%a7)</span></samp>’<br>
‘<samp><span class="samp">%a7</span></samp>’ is also known as ‘<samp><span class="samp">%sp</span></samp>’, i.e., the Stack Pointer. <code>%a6</code>
is also known as ‘<samp><span class="samp">%fp</span></samp>’, the Frame Pointer.
<br><dt><dfn>Address Register Postincrement</dfn><dd>‘<samp><span class="samp">(%a0)+</span></samp>’ through ‘<samp><span class="samp">(%a7)+</span></samp>’
<br><dt><dfn>Address Register Predecrement</dfn><dd>‘<samp><span class="samp">-(%a0)</span></samp>’ through ‘<samp><span class="samp">-(%a7)</span></samp>’
<br><dt><dfn>Indirect Plus Offset</dfn><dd>‘<samp><var>number</var><span class="samp">(</span><var>%a0</var><span class="samp">)</span></samp>’ through ‘<samp><var>number</var><span class="samp">(</span><var>%a7</var><span class="samp">)</span></samp>’,
or ‘<samp><var>number</var><span class="samp">(</span><var>%pc</var><span class="samp">)</span></samp>’.
<p>The <var>number</var> may also appear within the parentheses, as in
‘<samp><span class="samp">(</span><var>number</var><span class="samp">,</span><var>%a0</var><span class="samp">)</span></samp>’. When used with the <var>pc</var>, the
<var>number</var> may be omitted (with an address register, omitting the
<var>number</var> produces Address Register Indirect mode).
<br><dt><dfn>Index</dfn><dd>‘<samp><var>number</var><span class="samp">(</span><var>apc</var><span class="samp">,</span><var>register</var><span class="samp">.</span><var>size</var><span class="samp">*</span><var>scale</var><span class="samp">)</span></samp>’
<p>The <var>number</var> may be omitted, or it may appear within the
parentheses. The <var>apc</var> may be omitted. The <var>register</var> and the
<var>apc</var> may appear in either order. If both <var>apc</var> and
<var>register</var> are address registers, and the <var>size</var> and <var>scale</var>
are omitted, then the first register is taken as the base register, and
the second as the index register.
<br><dt><dfn>Postindex</dfn><dd>‘<samp><span class="samp">([</span><var>number</var><span class="samp">,</span><var>apc</var><span class="samp">],</span><var>register</var><span class="samp">.</span><var>size</var><span class="samp">*</span><var>scale</var><span class="samp">,</span><var>onumber</var><span class="samp">)</span></samp>’
<p>The <var>onumber</var>, or the <var>register</var>, or both, may be omitted.
Either the <var>number</var> or the <var>apc</var> may be omitted, but not both.
<br><dt><dfn>Preindex</dfn><dd>‘<samp><span class="samp">([</span><var>number</var><span class="samp">,</span><var>apc</var><span class="samp">,</span><var>register</var><span class="samp">.</span><var>size</var><span class="samp">*</span><var>scale</var><span class="samp">],</span><var>onumber</var><span class="samp">)</span></samp>’
<p>The <var>number</var>, or the <var>apc</var>, or the <var>register</var>, or any two of
them, may be omitted. The <var>onumber</var> may be omitted. The
<var>register</var> and the <var>apc</var> may appear in either order. If both
<var>apc</var> and <var>register</var> are address registers, and the <var>size</var>
and <var>scale</var> are omitted, then the first register is taken as the
base register, and the second as the index register.
</dl>
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