From dec44c16d177c26888ab63fa87d90772d158ed2b Mon Sep 17 00:00:00 2001 From: Penguin Date: Tue, 23 Jun 2020 19:04:54 -0500 Subject: [PATCH] fucking printing on linux --- .#epenguin.hpp | 1 - arch/arm/SAM_D2X/hal/.#hal_sam_d2x.hpp | 1 - arch/arm/SAM_D2X/hal/hal_sam_d2x.hpp | 18 ++++++ arch/arm/SAM_D2X/hdi/hdi_sam_d2x.h | 30 ++-------- epenguin.hpp | 83 +++++++++++++++++++++++++- epenguin_hal.hpp | 10 ++-- 6 files changed, 111 insertions(+), 32 deletions(-) delete mode 120000 .#epenguin.hpp delete mode 120000 arch/arm/SAM_D2X/hal/.#hal_sam_d2x.hpp diff --git a/.#epenguin.hpp b/.#epenguin.hpp deleted file mode 120000 index cb7e426e..00000000 --- a/.#epenguin.hpp +++ /dev/null @@ -1 +0,0 @@ -penguin@penguin-pc.12922:1592934912 \ No newline at end of file diff --git a/arch/arm/SAM_D2X/hal/.#hal_sam_d2x.hpp b/arch/arm/SAM_D2X/hal/.#hal_sam_d2x.hpp deleted file mode 120000 index cb7e426e..00000000 --- a/arch/arm/SAM_D2X/hal/.#hal_sam_d2x.hpp +++ /dev/null @@ -1 +0,0 @@ -penguin@penguin-pc.12922:1592934912 \ No newline at end of file diff --git a/arch/arm/SAM_D2X/hal/hal_sam_d2x.hpp b/arch/arm/SAM_D2X/hal/hal_sam_d2x.hpp index 3da6bd35..9812fbe2 100644 --- a/arch/arm/SAM_D2X/hal/hal_sam_d2x.hpp +++ b/arch/arm/SAM_D2X/hal/hal_sam_d2x.hpp @@ -1,6 +1,24 @@ #ifndef _HAL_SAM_D2X_HPP_ #define _HAL_SAM_D2X_HPP_ +#include "hal_arm.hpp" +namespace hal::arm::sam_d2x +{ + namespace core + { + + }; + + namespace usart + { + + }; + + namespace spi + { + + }; +}; #endif diff --git a/arch/arm/SAM_D2X/hdi/hdi_sam_d2x.h b/arch/arm/SAM_D2X/hdi/hdi_sam_d2x.h index c22d6501..f899fc28 100644 --- a/arch/arm/SAM_D2X/hdi/hdi_sam_d2x.h +++ b/arch/arm/SAM_D2X/hdi/hdi_sam_d2x.h @@ -1,34 +1,14 @@ #ifndef _HDI_SAM_D2X_H_ #define _HDI_SAM_D2X_H_ -#include "hal_arm.h" +#include "hal_arm.hpp" #include #ifdef __cplusplus extern "C" { #endif -#if !(defined(__ASSEMBLY__)) -#ifndef __cplusplus - typedef volatile const uint32_t RoReg; // Read only 32-bit register (volatile const unsigned int) - typedef volatile const uint16_t RoReg16; // Read only 16-bit register (volatile const unsigned int) - typedef volatile const uint8_t RoReg8; // Read only 8-bit register (volatile const unsigned int) -#else - typedef volatile uint32_t RoReg; // Read only 32-bit register (volatile const unsigned int) - typedef volatile uint16_t RoReg16; // Read only 16-bit register (volatile const unsigned int) - typedef volatile uint8_t RoReg8; // Read only 8-bit register (volatile const unsigned int) +#if !(EP_MCU == __SAM_D2X__) + #error Shouldn't have gotten here #endif - typedef volatile uint32_t WoReg; // Write only 32-bit register (volatile unsigned int) - typedef volatile uint16_t WoReg16; // Write only 16-bit register (volatile unsigned int) - typedef volatile uint16_t WoReg8; // Write only 8-bit register (volatile unsigned int) - typedef volatile uint32_t RwReg; // Write only 32-bit register (volatile unsigned int) - typedef volatile uint16_t RwReg16; // Write only 16-bit register (volatile unsigned int) - typedef volatile uint8_t RwReg8; // Write only 8-bit register (volatile unsigned int) -#define CAST(type, value) ((type*)(value)) -#define REG_ACCESS(type, address) (*(type*)(address)) -#else -#define CAST(type, value) (value) -#define REG_ACCESS(type, address) (address) -#endif - typedef enum IRQn { // Cortex-M0+ Processor Exception Numbers @@ -51,8 +31,10 @@ typedef enum IRQn SERCOM1_IRQn = 10, SERCOM2_IRQn = 11, SERCOM3_IRQn = 12, + #if !() SERCOM4_IRQn = 13, - SERCOM5_IRQn = 14 + SERCOM5_IRQn = 14, + }IRQn_Type; #ifdef __cplusplus } diff --git a/epenguin.hpp b/epenguin.hpp index 53d9d5a7..d53ea0dc 100644 --- a/epenguin.hpp +++ b/epenguin.hpp @@ -1,10 +1,89 @@ #ifndef _EPENGUIN_HPP_ #define _EPENGUIN_HPP_ -#include "epenguin_conf.h" -#include "epenguin_hal.hpp" +/* -- ePenguin -- + This master file dictates all supported hardware. It lists supported + architectures, mcu families, and specific mcus. This software framework + targets hardware at the mcu level--not at the board level. Board layers can + be applied, but this framework targets the mcu and the mcu alone. +*/ +#ifndef __UARCHITECTURES__ +#define __UARCHITECTURES__ +#define __UARCH_ARM__ (0) +#define __UARCH_ARM64__ (1) +#define __UARCH_AVR__ (2) +#define __UARCH_AVR32__ (3) +#define __UARCH_X86__ (4) +#define __UARCH_RISCV__ (5) #endif + +#ifndef __UFAMILIES__ +#define __UFAMILIES__ +/* Support ARM MCU Families */ + +/* Microchip */ +#define __SAM_D1X__ (0) +#define __SAM_C1X__ (1) +#define __SAM_D2X__ (2) +#define __SAM_E_D5X__ (3) +#define __SAM_C2X__ (4) +#define __SAM_L2X__ (5) + +/* STMicroelectronics */ + +/* NXP */ + +#endif + +#ifndef __UCONTROLLERS__ +#define __UCONTROLLERS__ + +/* ARM */ +/* Microchip */ +/* SAM_D2X */ +/* D2X Series E */ +#define __ATSAMD21E15A__ (0) +#define __ATSAMD21E15B__ (1) +#define __ATSAMD21E15BU__ (2) +#define __ATSAMD21E15L__ (3) +#define __ATSAMD21E16A__ (4) +#define __ATSAMD21E16B__ (5) +#define __ATSAMD21E16BU__ (6) +#define __ATSAMD21E16L__ (7) +#define __ATSAMD21E17A__ (8) +#define __ATSAMD21E17D__ (9) +#define __ATSAMD21E17DU__ (10) +#define __ATSAMD21E17L__ (11) +#define __ATSAMD21E18A__ (12) +/* D2X Series G */ +#define __ATSAMD21G15A__ (13) +#define __ATSAMD21G15B__ (14) +#define __ATSAMD21G15L__ (15) +#define __ATSAMD21G16A__ (16) +#define __ATSAMD21G16B__ (17) +#define __ATSAMD21G16L__ (18) +#define __ATSAMD21G17A__ (19) +#define __ATSAMD21G17AU__ (20) +#define __ATSAMD21G17D__ (21) +#define __ATSAMD21G17L__ (22) +#define __ATSAMD21G18A__ (23) +#define __ATSAMD21G18AU__ (24) +/* D2X Series J */ +#define __ATSAMD21J15A__ (25) +#define __ATSAMD21J15B__ (26) +#define __ATSAMD21J16A__ (27) +#define __ATSAMD21J16B__ (28) +#define __ATSAMD21J17A__ (29) +#define __ATSAMD21J17D__ (30) +#define __ATSAMD21J18A__ (31) + +#endif +#include "epenguin_conf.hpp" + +#endif + + diff --git a/epenguin_hal.hpp b/epenguin_hal.hpp index 21b49a08..ba3c2d85 100644 --- a/epenguin_hal.hpp +++ b/epenguin_hal.hpp @@ -1,7 +1,9 @@ -#ifndef _EPENGUIN_H_ -#define _EPENGUIN_H_ - -namespace hal{}; +#ifndef _EPENGUIN_HAL_HPP_ +#define _EPENGUIN_HAL_HPP_ +namespace hal +{ + namespace util{}; +}; #endif